1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::R600 {
13
14 enum {
15 PHI = 0, // Target.td:1329
16 INLINEASM = 1, // Target.td:1335
17 INLINEASM_BR = 2, // Target.td:1341
18 CFI_INSTRUCTION = 3, // Target.td:1350
19 EH_LABEL = 4, // Target.td:1359
20 GC_LABEL = 5, // Target.td:1368
21 ANNOTATION_LABEL = 6, // Target.td:1377
22 KILL = 7, // Target.td:1385
23 EXTRACT_SUBREG = 8, // Target.td:1392
24 INSERT_SUBREG = 9, // Target.td:1398
25 IMPLICIT_DEF = 10, // Target.td:1405
26 INIT_UNDEF = 11, // Target.td:1414
27 SUBREG_TO_REG = 12, // Target.td:1421
28 COPY_TO_REGCLASS = 13, // Target.td:1427
29 DBG_VALUE = 14, // Target.td:1434
30 DBG_VALUE_LIST = 15, // Target.td:1441
31 DBG_INSTR_REF = 16, // Target.td:1448
32 DBG_PHI = 17, // Target.td:1455
33 DBG_LABEL = 18, // Target.td:1462
34 REG_SEQUENCE = 19, // Target.td:1469
35 COPY = 20, // Target.td:1476
36 COPY_LANEMASK = 21, // Target.td:1484
37 BUNDLE = 22, // Target.td:1491
38 LIFETIME_START = 23, // Target.td:1497
39 LIFETIME_END = 24, // Target.td:1504
40 PSEUDO_PROBE = 25, // Target.td:1511
41 ARITH_FENCE = 26, // Target.td:1518
42 STACKMAP = 27, // Target.td:1527
43 FENTRY_CALL = 28, // Target.td:1662
44 PATCHPOINT = 29, // Target.td:1535
45 LOAD_STACK_GUARD = 30, // Target.td:1553
46 PREALLOCATED_SETUP = 31, // Target.td:1561
47 PREALLOCATED_ARG = 32, // Target.td:1567
48 STATEPOINT = 33, // Target.td:1544
49 LOCAL_ESCAPE = 34, // Target.td:1573
50 FAULTING_OP = 35, // Target.td:1582
51 PATCHABLE_OP = 36, // Target.td:1602
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1610
53 PATCHABLE_RET = 38, // Target.td:1617
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1626
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1634
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1642
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1652
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1672
59 FAKE_USE = 44, // Target.td:1592
60 MEMBARRIER = 45, // Target.td:1678
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1686
62 RELOC_NONE = 47, // Target.td:1694
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1706
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1702
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1710
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1714
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1937
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1929
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1944
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1522
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1535
96 G_INSERT = 81, // GenericOpcodes.td:1544
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1554
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1574
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1584
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1591
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1951
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1491
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1492
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1493
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1494
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1495
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1496
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1497
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1498
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1481
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1482
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1483
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1484
149 G_FENCE = 134, // GenericOpcodes.td:1500
150 G_PREFETCH = 135, // GenericOpcodes.td:1507
151 G_BRCOND = 136, // GenericOpcodes.td:1647
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1656
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1679
154 G_INTRINSIC = 139, // GenericOpcodes.td:1599
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1606
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1615
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1623
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1637
265 G_BRJT = 250, // GenericOpcodes.td:1667
266 G_VSCALE = 251, // GenericOpcodes.td:1565
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1711
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1719
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1727
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1735
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1746
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1754
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1762
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1769
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1821
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1822
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1823
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1824
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1825
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1826
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1827
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1828
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1829
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1830
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1686
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1696
318 G_MEMCPY = 303, // GenericOpcodes.td:1836
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1844
320 G_MEMMOVE = 305, // GenericOpcodes.td:1852
321 G_MEMSET = 306, // GenericOpcodes.td:1860
322 G_BZERO = 307, // GenericOpcodes.td:1867
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1874
324 G_TRAP = 309, // GenericOpcodes.td:1884
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1891
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1897
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1785
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1791
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1797
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1798
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1800
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1801
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1802
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1803
335 G_VECREDUCE_FMAXIMUMNUM = 320, // GenericOpcodes.td:1804
336 G_VECREDUCE_FMINIMUMNUM = 321, // GenericOpcodes.td:1805
337 G_VECREDUCE_ADD = 322, // GenericOpcodes.td:1807
338 G_VECREDUCE_MUL = 323, // GenericOpcodes.td:1808
339 G_VECREDUCE_AND = 324, // GenericOpcodes.td:1809
340 G_VECREDUCE_OR = 325, // GenericOpcodes.td:1810
341 G_VECREDUCE_XOR = 326, // GenericOpcodes.td:1811
342 G_VECREDUCE_SMAX = 327, // GenericOpcodes.td:1812
343 G_VECREDUCE_SMIN = 328, // GenericOpcodes.td:1813
344 G_VECREDUCE_UMAX = 329, // GenericOpcodes.td:1814
345 G_VECREDUCE_UMIN = 330, // GenericOpcodes.td:1815
346 G_SBFX = 331, // GenericOpcodes.td:1909
347 G_UBFX = 332, // GenericOpcodes.td:1917
348 BRANCH = 333, // R600Instructions.td:1594
349 BRANCH_COND_f32 = 334, // R600Instructions.td:1567
350 BRANCH_COND_i32 = 335, // R600Instructions.td:1563
351 BREAK = 336, // R600Instructions.td:1608
352 BREAKC_f32 = 337, // R600Instructions.td:1584
353 BREAKC_i32 = 338, // R600Instructions.td:1582
354 BREAK_LOGICALNZ_f32 = 339, // R600Instructions.td:1577
355 BREAK_LOGICALNZ_i32 = 340, // R600Instructions.td:1575
356 BREAK_LOGICALZ_f32 = 341, // R600Instructions.td:1577
357 BREAK_LOGICALZ_i32 = 342, // R600Instructions.td:1575
358 CONST_COPY = 343, // R600Instructions.td:1439
359 CONTINUE = 344, // R600Instructions.td:1610
360 CONTINUEC_f32 = 345, // R600Instructions.td:1584
361 CONTINUEC_i32 = 346, // R600Instructions.td:1582
362 CONTINUE_LOGICALNZ_f32 = 347, // R600Instructions.td:1577
363 CONTINUE_LOGICALNZ_i32 = 348, // R600Instructions.td:1575
364 CONTINUE_LOGICALZ_f32 = 349, // R600Instructions.td:1577
365 CONTINUE_LOGICALZ_i32 = 350, // R600Instructions.td:1575
366 CUBE_eg_pseudo = 351, // R600Instructions.td:1074
367 CUBE_r600_pseudo = 352, // R600Instructions.td:1074
368 DEFAULT = 353, // R600Instructions.td:1612
369 DOT_4 = 354, // R600Instructions.td:1061
370 DUMMY_CHAIN = 355, // R600Instructions.td:792
371 ELSE = 356, // R600Instructions.td:1614
372 END = 357, // R600Instructions.td:1620
373 ENDFUNC = 358, // R600Instructions.td:1622
374 ENDIF = 359, // R600Instructions.td:1624
375 ENDLOOP = 360, // R600Instructions.td:1628
376 ENDMAIN = 361, // R600Instructions.td:1618
377 ENDSWITCH = 362, // R600Instructions.td:1616
378 FABS_R600 = 363, // R600Instructions.td:1204
379 FNEG_R600 = 364, // R600Instructions.td:1205
380 FUNC = 365, // R600Instructions.td:1630
381 IFC_f32 = 366, // R600Instructions.td:1584
382 IFC_i32 = 367, // R600Instructions.td:1582
383 IF_LOGICALNZ_f32 = 368, // R600Instructions.td:1577
384 IF_LOGICALNZ_i32 = 369, // R600Instructions.td:1575
385 IF_LOGICALZ_f32 = 370, // R600Instructions.td:1577
386 IF_LOGICALZ_i32 = 371, // R600Instructions.td:1575
387 IF_PREDICATE_SET = 372, // R600Instructions.td:1604
388 JUMP = 373, // R600Instructions.td:1385
389 JUMP_COND = 374, // R600Instructions.td:1378
390 MASK_WRITE = 375, // R600Instructions.td:1402
391 MOV_IMM_F32 = 376, // R600Instructions.td:827
392 MOV_IMM_GLOBAL_ADDR = 377, // R600Instructions.td:820
393 MOV_IMM_I32 = 378, // R600Instructions.td:814
394 PRED_X = 379, // R600Instructions.td:1370
395 R600_EXTRACT_ELT_V2 = 380, // R600Instructions.td:1677
396 R600_EXTRACT_ELT_V4 = 381, // R600Instructions.td:1678
397 R600_INSERT_ELT_V2 = 382, // R600Instructions.td:1680
398 R600_INSERT_ELT_V4 = 383, // R600Instructions.td:1681
399 R600_RegisterLoad = 384, // R600Instructions.td:698
400 R600_RegisterStore = 385, // R600Instructions.td:707
401 RETDYN = 386, // R600Instructions.td:1632
402 RETURN = 387, // R600Instructions.td:88
403 TXD = 388, // R600Instructions.td:1413
404 TXD_SHADOW = 389, // R600Instructions.td:1422
405 WHILELOOP = 390, // R600Instructions.td:1626
406 ADD = 391, // R600Instructions.td:721
407 ADDC_UINT = 392, // EvergreenInstructions.td:523
408 ADD_INT = 393, // R600Instructions.td:848
409 ALU_CLAUSE = 394, // R600Instructions.td:646
410 AND_INT = 395, // R600Instructions.td:844
411 ASHR_eg = 396, // EvergreenInstructions.td:508
412 ASHR_r600 = 397, // R600Instructions.td:1253
413 BCNT_INT = 398, // EvergreenInstructions.td:528
414 BFE_INT_eg = 399, // EvergreenInstructions.td:370
415 BFE_UINT_eg = 400, // EvergreenInstructions.td:365
416 BFI_INT_eg = 401, // EvergreenInstructions.td:411
417 BFM_INT_eg = 402, // EvergreenInstructions.td:492
418 BIT_ALIGN_INT_eg = 403, // EvergreenInstructions.td:500
419 CEIL = 404, // R600Instructions.td:781
420 CF_ALU = 405, // R600Instructions.td:631
421 CF_ALU_BREAK = 406, // R600Instructions.td:635
422 CF_ALU_CONTINUE = 407, // R600Instructions.td:634
423 CF_ALU_ELSE_AFTER = 408, // R600Instructions.td:636
424 CF_ALU_POP_AFTER = 409, // R600Instructions.td:633
425 CF_ALU_PUSH_BEFORE = 410, // R600Instructions.td:632
426 CF_CALL_FS_EG = 411, // EvergreenInstructions.td:850
427 CF_CALL_FS_R600 = 412, // R600Instructions.td:1325
428 CF_CONTINUE_EG = 413, // EvergreenInstructions.td:833
429 CF_CONTINUE_R600 = 414, // R600Instructions.td:1307
430 CF_ELSE_EG = 415, // EvergreenInstructions.td:846
431 CF_ELSE_R600 = 416, // R600Instructions.td:1321
432 CF_END_CM = 417, // CaymanInstructions.td:66
433 CF_END_EG = 418, // EvergreenInstructions.td:859
434 CF_END_R600 = 419, // R600Instructions.td:1334
435 CF_JUMP_EG = 420, // EvergreenInstructions.td:838
436 CF_JUMP_R600 = 421, // R600Instructions.td:1312
437 CF_PUSH_EG = 422, // EvergreenInstructions.td:842
438 CF_PUSH_ELSE_R600 = 423, // R600Instructions.td:1316
439 CF_TC_EG = 424, // EvergreenInstructions.td:811
440 CF_TC_R600 = 425, // R600Instructions.td:1285
441 CF_VC_EG = 426, // EvergreenInstructions.td:815
442 CF_VC_R600 = 427, // R600Instructions.td:1289
443 CNDE_INT = 428, // R600Instructions.td:890
444 CNDE_eg = 429, // EvergreenInstructions.td:511
445 CNDE_r600 = 430, // R600Instructions.td:1235
446 CNDGE_INT = 431, // R600Instructions.td:895
447 CNDGE_eg = 432, // EvergreenInstructions.td:513
448 CNDGE_r600 = 433, // R600Instructions.td:1237
449 CNDGT_INT = 434, // R600Instructions.td:900
450 CNDGT_eg = 435, // EvergreenInstructions.td:512
451 CNDGT_r600 = 436, // R600Instructions.td:1236
452 COS_cm = 437, // CaymanInstructions.td:48
453 COS_eg = 438, // EvergreenInstructions.td:132
454 COS_r600 = 439, // R600Instructions.td:1252
455 COS_r700 = 440, // R700Instructions.td:19
456 CUBE_eg_real = 441, // R600Instructions.td:1085
457 CUBE_r600_real = 442, // R600Instructions.td:1085
458 DOT4_eg = 443, // EvergreenInstructions.td:519
459 DOT4_r600 = 444, // R600Instructions.td:1238
460 EG_ExportBuf = 445, // EvergreenInstructions.td:801
461 EG_ExportSwz = 446, // EvergreenInstructions.td:791
462 END_LOOP_EG = 447, // EvergreenInstructions.td:824
463 END_LOOP_R600 = 448, // R600Instructions.td:1298
464 EXP_IEEE_cm = 449, // CaymanInstructions.td:43
465 EXP_IEEE_eg = 450, // EvergreenInstructions.td:125
466 EXP_IEEE_r600 = 451, // R600Instructions.td:1240
467 FETCH_CLAUSE = 452, // R600Instructions.td:638
468 FFBH_UINT = 453, // EvergreenInstructions.td:529
469 FFBL_INT = 454, // EvergreenInstructions.td:530
470 FLOOR = 455, // R600Instructions.td:783
471 FLT16_TO_FLT32 = 456, // EvergreenInstructions.td:527
472 FLT32_TO_FLT16 = 457, // EvergreenInstructions.td:526
473 FLT_TO_INT_eg = 458, // EvergreenInstructions.td:536
474 FLT_TO_INT_r600 = 459, // R600Instructions.td:1247
475 FLT_TO_UINT_eg = 460, // EvergreenInstructions.td:543
476 FLT_TO_UINT_r600 = 461, // R600Instructions.td:1249
477 FMA_eg = 462, // EvergreenInstructions.td:507
478 FRACT = 463, // R600Instructions.td:779
479 GROUP_BARRIER = 464, // EvergreenInstructions.td:549
480 INTERP_LOAD_P0 = 465, // R600Instructions.td:445
481 INTERP_PAIR_XY = 466, // R600Instructions.td:367
482 INTERP_PAIR_ZW = 467, // R600Instructions.td:373
483 INTERP_VEC_LOAD = 468, // R600Instructions.td:430
484 INTERP_XY = 469, // R600Instructions.td:437
485 INTERP_ZW = 470, // R600Instructions.td:441
486 INT_TO_FLT_eg = 471, // EvergreenInstructions.td:541
487 INT_TO_FLT_r600 = 472, // R600Instructions.td:1248
488 KILLGT = 473, // R600Instructions.td:840
489 LDS_ADD = 474, // EvergreenInstructions.td:687
490 LDS_ADD_RET = 475, // EvergreenInstructions.td:707
491 LDS_AND = 476, // EvergreenInstructions.td:689
492 LDS_AND_RET = 477, // EvergreenInstructions.td:713
493 LDS_BYTE_READ_RET = 478, // EvergreenInstructions.td:743
494 LDS_BYTE_WRITE = 479, // EvergreenInstructions.td:701
495 LDS_CMPST = 480, // EvergreenInstructions.td:693
496 LDS_CMPST_RET = 481, // EvergreenInstructions.td:737
497 LDS_MAX_INT = 482, // EvergreenInstructions.td:695
498 LDS_MAX_INT_RET = 483, // EvergreenInstructions.td:725
499 LDS_MAX_UINT = 484, // EvergreenInstructions.td:697
500 LDS_MAX_UINT_RET = 485, // EvergreenInstructions.td:731
501 LDS_MIN_INT = 486, // EvergreenInstructions.td:694
502 LDS_MIN_INT_RET = 487, // EvergreenInstructions.td:722
503 LDS_MIN_UINT = 488, // EvergreenInstructions.td:696
504 LDS_MIN_UINT_RET = 489, // EvergreenInstructions.td:728
505 LDS_OR = 490, // EvergreenInstructions.td:690
506 LDS_OR_RET = 491, // EvergreenInstructions.td:716
507 LDS_READ_RET = 492, // EvergreenInstructions.td:740
508 LDS_SHORT_READ_RET = 493, // EvergreenInstructions.td:749
509 LDS_SHORT_WRITE = 494, // EvergreenInstructions.td:704
510 LDS_SUB = 495, // EvergreenInstructions.td:688
511 LDS_SUB_RET = 496, // EvergreenInstructions.td:710
512 LDS_UBYTE_READ_RET = 497, // EvergreenInstructions.td:746
513 LDS_USHORT_READ_RET = 498, // EvergreenInstructions.td:752
514 LDS_WRITE = 499, // EvergreenInstructions.td:698
515 LDS_WRXCHG = 500, // EvergreenInstructions.td:692
516 LDS_WRXCHG_RET = 501, // EvergreenInstructions.td:734
517 LDS_XOR = 502, // EvergreenInstructions.td:691
518 LDS_XOR_RET = 503, // EvergreenInstructions.td:719
519 LITERALS = 504, // R600Instructions.td:654
520 LOG_CLAMPED_eg = 505, // EvergreenInstructions.td:515
521 LOG_CLAMPED_r600 = 506, // R600Instructions.td:1241
522 LOG_IEEE_cm = 507, // CaymanInstructions.td:44
523 LOG_IEEE_eg = 508, // EvergreenInstructions.td:126
524 LOG_IEEE_r600 = 509, // R600Instructions.td:1242
525 LOOP_BREAK_EG = 510, // EvergreenInstructions.td:828
526 LOOP_BREAK_R600 = 511, // R600Instructions.td:1302
527 LSHL_eg = 512, // EvergreenInstructions.td:510
528 LSHL_r600 = 513, // R600Instructions.td:1255
529 LSHR_eg = 514, // EvergreenInstructions.td:509
530 LSHR_r600 = 515, // R600Instructions.td:1254
531 MAX = 516, // R600Instructions.td:726
532 MAX_DX10 = 517, // R600Instructions.td:731
533 MAX_INT = 518, // R600Instructions.td:850
534 MAX_UINT = 519, // R600Instructions.td:852
535 MIN = 520, // R600Instructions.td:727
536 MIN_DX10 = 521, // R600Instructions.td:732
537 MIN_INT = 522, // R600Instructions.td:851
538 MIN_UINT = 523, // R600Instructions.td:853
539 MOV = 524, // R600Instructions.td:785
540 MOVA_INT_eg = 525, // EvergreenInstructions.td:533
541 MUL = 526, // R600Instructions.td:723
542 MULADD_IEEE_eg = 527, // EvergreenInstructions.td:506
543 MULADD_IEEE_r600 = 528, // R600Instructions.td:1234
544 MULADD_INT24_cm = 529, // CaymanInstructions.td:22
545 MULADD_UINT24_eg = 530, // EvergreenInstructions.td:494
546 MULADD_eg = 531, // EvergreenInstructions.td:505
547 MULADD_r600 = 532, // R600Instructions.td:1233
548 MULHI_INT_cm = 533, // CaymanInstructions.td:36
549 MULHI_INT_cm24 = 534, // CaymanInstructions.td:39
550 MULHI_INT_eg = 535, // EvergreenInstructions.td:118
551 MULHI_INT_r600 = 536, // R600Instructions.td:1257
552 MULHI_UINT24_eg = 537, // EvergreenInstructions.td:121
553 MULHI_UINT_cm = 538, // CaymanInstructions.td:38
554 MULHI_UINT_cm24 = 539, // CaymanInstructions.td:40
555 MULHI_UINT_eg = 540, // EvergreenInstructions.td:120
556 MULHI_UINT_r600 = 541, // R600Instructions.td:1259
557 MULLO_INT_cm = 542, // CaymanInstructions.td:35
558 MULLO_INT_eg = 543, // EvergreenInstructions.td:117
559 MULLO_INT_r600 = 544, // R600Instructions.td:1256
560 MULLO_UINT_cm = 545, // CaymanInstructions.td:37
561 MULLO_UINT_eg = 546, // EvergreenInstructions.td:119
562 MULLO_UINT_r600 = 547, // R600Instructions.td:1258
563 MUL_IEEE = 548, // R600Instructions.td:724
564 MUL_INT24_cm = 549, // CaymanInstructions.td:25
565 MUL_LIT_eg = 550, // EvergreenInstructions.td:514
566 MUL_LIT_r600 = 551, // R600Instructions.td:1232
567 MUL_UINT24_eg = 552, // EvergreenInstructions.td:516
568 NOT_INT = 553, // R600Instructions.td:847
569 OR_INT = 554, // R600Instructions.td:845
570 PAD = 555, // R600Instructions.td:666
571 POP_EG = 556, // EvergreenInstructions.td:855
572 POP_R600 = 557, // R600Instructions.td:1330
573 PRED_SETE = 558, // R600Instructions.td:833
574 PRED_SETE_INT = 559, // R600Instructions.td:885
575 PRED_SETGE = 560, // R600Instructions.td:835
576 PRED_SETGE_INT = 561, // R600Instructions.td:887
577 PRED_SETGT = 562, // R600Instructions.td:834
578 PRED_SETGT_INT = 563, // R600Instructions.td:886
579 PRED_SETNE = 564, // R600Instructions.td:836
580 PRED_SETNE_INT = 565, // R600Instructions.td:888
581 R600_ExportBuf = 566, // R600Instructions.td:1276
582 R600_ExportSwz = 567, // R600Instructions.td:1267
583 RAT_ATOMIC_ADD_NORET = 568, // EvergreenInstructions.td:82
584 RAT_ATOMIC_ADD_RTN = 569, // EvergreenInstructions.td:78
585 RAT_ATOMIC_AND_NORET = 570, // EvergreenInstructions.td:82
586 RAT_ATOMIC_AND_RTN = 571, // EvergreenInstructions.td:78
587 RAT_ATOMIC_CMPXCHG_INT_NORET = 572, // EvergreenInstructions.td:82
588 RAT_ATOMIC_CMPXCHG_INT_RTN = 573, // EvergreenInstructions.td:78
589 RAT_ATOMIC_DEC_UINT_NORET = 574, // EvergreenInstructions.td:82
590 RAT_ATOMIC_DEC_UINT_RTN = 575, // EvergreenInstructions.td:78
591 RAT_ATOMIC_INC_UINT_NORET = 576, // EvergreenInstructions.td:82
592 RAT_ATOMIC_INC_UINT_RTN = 577, // EvergreenInstructions.td:78
593 RAT_ATOMIC_MAX_INT_NORET = 578, // EvergreenInstructions.td:82
594 RAT_ATOMIC_MAX_INT_RTN = 579, // EvergreenInstructions.td:78
595 RAT_ATOMIC_MAX_UINT_NORET = 580, // EvergreenInstructions.td:82
596 RAT_ATOMIC_MAX_UINT_RTN = 581, // EvergreenInstructions.td:78
597 RAT_ATOMIC_MIN_INT_NORET = 582, // EvergreenInstructions.td:82
598 RAT_ATOMIC_MIN_INT_RTN = 583, // EvergreenInstructions.td:78
599 RAT_ATOMIC_MIN_UINT_NORET = 584, // EvergreenInstructions.td:82
600 RAT_ATOMIC_MIN_UINT_RTN = 585, // EvergreenInstructions.td:78
601 RAT_ATOMIC_OR_NORET = 586, // EvergreenInstructions.td:82
602 RAT_ATOMIC_OR_RTN = 587, // EvergreenInstructions.td:78
603 RAT_ATOMIC_RSUB_NORET = 588, // EvergreenInstructions.td:82
604 RAT_ATOMIC_RSUB_RTN = 589, // EvergreenInstructions.td:78
605 RAT_ATOMIC_SUB_NORET = 590, // EvergreenInstructions.td:82
606 RAT_ATOMIC_SUB_RTN = 591, // EvergreenInstructions.td:78
607 RAT_ATOMIC_XCHG_INT_NORET = 592, // EvergreenInstructions.td:82
608 RAT_ATOMIC_XCHG_INT_RTN = 593, // EvergreenInstructions.td:78
609 RAT_ATOMIC_XOR_NORET = 594, // EvergreenInstructions.td:82
610 RAT_ATOMIC_XOR_RTN = 595, // EvergreenInstructions.td:78
611 RAT_MSKOR = 596, // EvergreenInstructions.td:67
612 RAT_STORE_DWORD128 = 597, // CaymanInstructions.td:84
613 RAT_STORE_DWORD32 = 598, // CaymanInstructions.td:82
614 RAT_STORE_DWORD64 = 599, // CaymanInstructions.td:83
615 RAT_STORE_TYPED_cm = 600, // CaymanInstructions.td:86
616 RAT_STORE_TYPED_eg = 601, // EvergreenInstructions.td:164
617 RAT_WRITE_CACHELESS_128_eg = 602, // EvergreenInstructions.td:158
618 RAT_WRITE_CACHELESS_32_eg = 603, // EvergreenInstructions.td:144
619 RAT_WRITE_CACHELESS_64_eg = 604, // EvergreenInstructions.td:151
620 RECIPSQRT_CLAMPED_cm = 605, // CaymanInstructions.td:42
621 RECIPSQRT_CLAMPED_eg = 606, // EvergreenInstructions.td:124
622 RECIPSQRT_CLAMPED_r600 = 607, // R600Instructions.td:1245
623 RECIPSQRT_IEEE_cm = 608, // CaymanInstructions.td:46
624 RECIPSQRT_IEEE_eg = 609, // EvergreenInstructions.td:128
625 RECIPSQRT_IEEE_r600 = 610, // R600Instructions.td:1246
626 RECIP_CLAMPED_cm = 611, // CaymanInstructions.td:45
627 RECIP_CLAMPED_eg = 612, // EvergreenInstructions.td:127
628 RECIP_CLAMPED_r600 = 613, // R600Instructions.td:1243
629 RECIP_IEEE_cm = 614, // CaymanInstructions.td:33
630 RECIP_IEEE_eg = 615, // EvergreenInstructions.td:114
631 RECIP_IEEE_r600 = 616, // R600Instructions.td:1244
632 RECIP_UINT_eg = 617, // EvergreenInstructions.td:123
633 RECIP_UINT_r600 = 618, // R600Instructions.td:1260
634 RNDNE = 619, // R600Instructions.td:782
635 SETE = 620, // R600Instructions.td:737
636 SETE_DX10 = 621, // R600Instructions.td:757
637 SETE_INT = 622, // R600Instructions.td:855
638 SETGE_DX10 = 623, // R600Instructions.td:767
639 SETGE_INT = 624, // R600Instructions.td:865
640 SETGE_UINT = 625, // R600Instructions.td:880
641 SETGT_DX10 = 626, // R600Instructions.td:762
642 SETGT_INT = 627, // R600Instructions.td:860
643 SETGT_UINT = 628, // R600Instructions.td:875
644 SETNE_DX10 = 629, // R600Instructions.td:773
645 SETNE_INT = 630, // R600Instructions.td:870
646 SGE = 631, // R600Instructions.td:747
647 SGT = 632, // R600Instructions.td:742
648 SIN_cm = 633, // CaymanInstructions.td:47
649 SIN_eg = 634, // EvergreenInstructions.td:131
650 SIN_r600 = 635, // R600Instructions.td:1251
651 SIN_r700 = 636, // R700Instructions.td:18
652 SNE = 637, // R600Instructions.td:752
653 SUBB_UINT = 638, // EvergreenInstructions.td:524
654 SUB_INT = 639, // R600Instructions.td:849
655 TEX_GET_GRADIENTS_H = 640, // R600Instructions.td:959
656 TEX_GET_GRADIENTS_V = 641, // R600Instructions.td:960
657 TEX_GET_TEXTURE_RESINFO = 642, // R600Instructions.td:958
658 TEX_LD = 643, // R600Instructions.td:954
659 TEX_LDPTR = 644, // R600Instructions.td:955
660 TEX_SAMPLE = 645, // R600Instructions.td:948
661 TEX_SAMPLE_C = 646, // R600Instructions.td:949
662 TEX_SAMPLE_C_G = 647, // R600Instructions.td:964
663 TEX_SAMPLE_C_L = 648, // R600Instructions.td:951
664 TEX_SAMPLE_C_LB = 649, // R600Instructions.td:953
665 TEX_SAMPLE_G = 650, // R600Instructions.td:963
666 TEX_SAMPLE_L = 651, // R600Instructions.td:950
667 TEX_SAMPLE_LB = 652, // R600Instructions.td:952
668 TEX_SET_GRADIENTS_H = 653, // R600Instructions.td:961
669 TEX_SET_GRADIENTS_V = 654, // R600Instructions.td:962
670 TEX_VTX_CONSTBUF = 655, // R600Instructions.td:1451
671 TEX_VTX_TEXBUF = 656, // R600Instructions.td:1505
672 TRUNC = 657, // R600Instructions.td:780
673 UINT_TO_FLT_eg = 658, // EvergreenInstructions.td:547
674 UINT_TO_FLT_r600 = 659, // R600Instructions.td:1250
675 VTX_READ_128_cm = 660, // CaymanInstructions.td:162
676 VTX_READ_128_eg = 661, // EvergreenInstructions.td:240
677 VTX_READ_16_cm = 662, // CaymanInstructions.td:120
678 VTX_READ_16_eg = 663, // EvergreenInstructions.td:195
679 VTX_READ_32_cm = 664, // CaymanInstructions.td:131
680 VTX_READ_32_eg = 665, // EvergreenInstructions.td:207
681 VTX_READ_64_cm = 666, // CaymanInstructions.td:151
682 VTX_READ_64_eg = 667, // EvergreenInstructions.td:228
683 VTX_READ_8_cm = 668, // CaymanInstructions.td:109
684 VTX_READ_8_eg = 669, // EvergreenInstructions.td:183
685 WHILE_LOOP_EG = 670, // EvergreenInstructions.td:819
686 WHILE_LOOP_R600 = 671, // R600Instructions.td:1293
687 XOR_INT = 672, // R600Instructions.td:846
688 INSTRUCTION_LIST_END = 673
689 };
690
691} // namespace llvm::R600
692
693#endif // GET_INSTRINFO_ENUM
694
695#ifdef GET_INSTRINFO_SCHED_ENUM
696#undef GET_INSTRINFO_SCHED_ENUM
697
698namespace llvm::R600::Sched {
699
700 enum {
701 NoInstrModel = 0,
702 NullALU = 1,
703 VecALU = 2,
704 AnyALU = 3,
705 TransALU = 4,
706 XALU = 5,
707 SCHED_LIST_END = 6
708 };
709
710} // namespace llvm::R600::Sched
711
712#endif // GET_INSTRINFO_SCHED_ENUM
713
714#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
715
716namespace llvm {
717
718struct R600InstrTable {
719 MCInstrDesc Insts[673];
720 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
721 MCPhysReg ImplicitOps[1];
722 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
723 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
724 MCOperandInfo OperandInfo[461];
725};
726} // namespace llvm
727
728#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
729
730#ifdef GET_INSTRINFO_MC_DESC
731#undef GET_INSTRINFO_MC_DESC
732
733namespace llvm {
734
735static_assert((sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
736static constexpr unsigned R600OpInfoBase = (sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) / sizeof(MCOperandInfo);
737
738extern const R600InstrTable R600Descs = {
739 {
740 { 672, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // XOR_INT
741 { 671, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_R600
742 { 670, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_EG
743 { 669, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_eg
744 { 668, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_cm
745 { 667, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_eg
746 { 666, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_cm
747 { 665, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_eg
748 { 664, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_cm
749 { 663, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_eg
750 { 662, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_cm
751 { 661, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_eg
752 { 660, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_cm
753 { 659, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_r600
754 { 658, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_eg
755 { 657, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // TRUNC
756 { 656, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL }, // TEX_VTX_TEXBUF
757 { 655, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0, 0x1000ULL }, // TEX_VTX_CONSTBUF
758 { 654, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_V
759 { 653, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_H
760 { 652, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_LB
761 { 651, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_L
762 { 650, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_G
763 { 649, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_LB
764 { 648, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_L
765 { 647, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_G
766 { 646, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C
767 { 645, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE
768 { 644, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LDPTR
769 { 643, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LD
770 { 642, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_TEXTURE_RESINFO
771 { 641, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_V
772 { 640, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_H
773 { 639, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUB_INT
774 { 638, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUBB_UINT
775 { 637, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SNE
776 { 636, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r700
777 { 635, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r600
778 { 634, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_eg
779 { 633, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // SIN_cm
780 { 632, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGT
781 { 631, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGE
782 { 630, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_INT
783 { 629, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_DX10
784 { 628, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_UINT
785 { 627, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_INT
786 { 626, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_DX10
787 { 625, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_UINT
788 { 624, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_INT
789 { 623, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_DX10
790 { 622, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_INT
791 { 621, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_DX10
792 { 620, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE
793 { 619, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RNDNE
794 { 618, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_r600
795 { 617, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_eg
796 { 616, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_r600
797 { 615, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_eg
798 { 614, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_IEEE_cm
799 { 613, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_r600
800 { 612, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_eg
801 { 611, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_CLAMPED_cm
802 { 610, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_r600
803 { 609, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_eg
804 { 608, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_IEEE_cm
805 { 607, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_r600
806 { 606, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_eg
807 { 605, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_CLAMPED_cm
808 { 604, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 423, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_64_eg
809 { 603, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 420, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_32_eg
810 { 602, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 417, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_128_eg
811 { 601, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_eg
812 { 600, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_cm
813 { 599, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 411, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD64
814 { 598, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 409, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD32
815 { 597, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD128
816 { 596, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_MSKOR
817 { 595, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_RTN
818 { 594, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_NORET
819 { 593, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_RTN
820 { 592, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_NORET
821 { 591, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_RTN
822 { 590, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_NORET
823 { 589, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_RTN
824 { 588, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_NORET
825 { 587, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_RTN
826 { 586, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_NORET
827 { 585, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_RTN
828 { 584, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_NORET
829 { 583, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_RTN
830 { 582, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_NORET
831 { 581, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_RTN
832 { 580, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_NORET
833 { 579, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_RTN
834 { 578, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_NORET
835 { 577, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_RTN
836 { 576, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_NORET
837 { 575, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_RTN
838 { 574, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_NORET
839 { 573, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_RTN
840 { 572, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_NORET
841 { 571, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_RTN
842 { 570, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_NORET
843 { 569, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_RTN
844 { 568, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_NORET
845 { 567, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportSwz
846 { 566, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportBuf
847 { 565, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE_INT
848 { 564, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE
849 { 563, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT_INT
850 { 562, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT
851 { 561, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE_INT
852 { 560, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE
853 { 559, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE_INT
854 { 558, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE
855 { 557, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_R600
856 { 556, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_EG
857 { 555, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PAD
858 { 554, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // OR_INT
859 { 553, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // NOT_INT
860 { 552, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_UINT24_eg
861 { 551, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_r600
862 { 550, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_eg
863 { 549, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_INT24_cm
864 { 548, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_IEEE
865 { 547, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_r600
866 { 546, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_eg
867 { 545, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_UINT_cm
868 { 544, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_r600
869 { 543, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_eg
870 { 542, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_INT_cm
871 { 541, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_r600
872 { 540, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_eg
873 { 539, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm24
874 { 538, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm
875 { 537, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT24_eg
876 { 536, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_r600
877 { 535, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_eg
878 { 534, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm24
879 { 533, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm
880 { 532, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_r600
881 { 531, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_eg
882 { 530, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_UINT24_eg
883 { 529, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_INT24_cm
884 { 528, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_r600
885 { 527, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_eg
886 { 526, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL
887 { 525, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL }, // MOVA_INT_eg
888 { 524, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // MOV
889 { 523, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_UINT
890 { 522, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_INT
891 { 521, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_DX10
892 { 520, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN
893 { 519, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_UINT
894 { 518, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_INT
895 { 517, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_DX10
896 { 516, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX
897 { 515, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_r600
898 { 514, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_eg
899 { 513, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_r600
900 { 512, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_eg
901 { 511, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_R600
902 { 510, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_EG
903 { 509, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_r600
904 { 508, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_eg
905 { 507, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // LOG_IEEE_cm
906 { 506, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_r600
907 { 505, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_eg
908 { 504, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LITERALS
909 { 503, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_XOR_RET
910 { 502, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_XOR
911 { 501, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_WRXCHG_RET
912 { 500, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_WRXCHG
913 { 499, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_WRITE
914 { 498, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_USHORT_READ_RET
915 { 497, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_UBYTE_READ_RET
916 { 496, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_SUB_RET
917 { 495, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_SUB
918 { 494, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_SHORT_WRITE
919 { 493, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_SHORT_READ_RET
920 { 492, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_READ_RET
921 { 491, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_OR_RET
922 { 490, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_OR
923 { 489, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_UINT_RET
924 { 488, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_UINT
925 { 487, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_INT_RET
926 { 486, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_INT
927 { 485, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_UINT_RET
928 { 484, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_UINT
929 { 483, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_INT_RET
930 { 482, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_INT
931 { 481, 13, 1, 0, 5, 0, 0, R600OpInfoBase + 391, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL }, // LDS_CMPST_RET
932 { 480, 12, 0, 0, 5, 0, 0, R600OpInfoBase + 379, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL }, // LDS_CMPST
933 { 479, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_BYTE_WRITE
934 { 478, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_BYTE_READ_RET
935 { 477, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_AND_RET
936 { 476, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_AND
937 { 475, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_ADD_RET
938 { 474, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_ADD
939 { 473, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL }, // KILLGT
940 { 472, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_r600
941 { 471, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_eg
942 { 470, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_ZW
943 { 469, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_XY
944 { 468, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 351, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_VEC_LOAD
945 { 467, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 346, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_ZW
946 { 466, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 341, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_XY
947 { 465, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INTERP_LOAD_P0
948 { 464, 0, 0, 0, 3, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL }, // GROUP_BARRIER
949 { 463, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FRACT
950 { 462, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // FMA_eg
951 { 461, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_r600
952 { 460, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_eg
953 { 459, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_r600
954 { 458, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_eg
955 { 457, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT32_TO_FLT16
956 { 456, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT16_TO_FLT32
957 { 455, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLOOR
958 { 454, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBL_INT
959 { 453, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBH_UINT
960 { 452, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FETCH_CLAUSE
961 { 451, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_r600
962 { 450, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_eg
963 { 449, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // EXP_IEEE_cm
964 { 448, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_R600
965 { 447, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_EG
966 { 446, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportSwz
967 { 445, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportBuf
968 { 444, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_r600
969 { 443, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_eg
970 { 442, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_r600_real
971 { 441, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_eg_real
972 { 440, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r700
973 { 439, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r600
974 { 438, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_eg
975 { 437, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // COS_cm
976 { 436, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_r600
977 { 435, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_eg
978 { 434, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_INT
979 { 433, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_r600
980 { 432, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_eg
981 { 431, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_INT
982 { 430, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_r600
983 { 429, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_eg
984 { 428, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_INT
985 { 427, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_R600
986 { 426, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_EG
987 { 425, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_R600
988 { 424, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_EG
989 { 423, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_ELSE_R600
990 { 422, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_EG
991 { 421, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_R600
992 { 420, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_EG
993 { 419, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_R600
994 { 418, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_EG
995 { 417, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_CM
996 { 416, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_R600
997 { 415, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_EG
998 { 414, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_R600
999 { 413, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_EG
1000 { 412, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_R600
1001 { 411, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_EG
1002 { 410, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_PUSH_BEFORE
1003 { 409, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_POP_AFTER
1004 { 408, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_ELSE_AFTER
1005 { 407, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_CONTINUE
1006 { 406, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_BREAK
1007 { 405, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU
1008 { 404, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // CEIL
1009 { 403, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BIT_ALIGN_INT_eg
1010 { 402, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // BFM_INT_eg
1011 { 401, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFI_INT_eg
1012 { 400, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_UINT_eg
1013 { 399, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_INT_eg
1014 { 398, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // BCNT_INT
1015 { 397, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_r600
1016 { 396, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_eg
1017 { 395, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // AND_INT
1018 { 394, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALU_CLAUSE
1019 { 393, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD_INT
1020 { 392, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADDC_UINT
1021 { 391, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD
1022 { 390, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // WHILELOOP
1023 { 389, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD_SHADOW
1024 { 388, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD
1025 { 387, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL }, // RETURN
1026 { 386, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // RETDYN
1027 { 385, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL }, // R600_RegisterStore
1028 { 384, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL }, // R600_RegisterLoad
1029 { 383, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 247, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V4
1030 { 382, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V2
1031 { 381, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V4
1032 { 380, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V2
1033 { 379, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 233, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // PRED_X
1034 { 378, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_I32
1035 { 377, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_GLOBAL_ADDR
1036 { 376, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_F32
1037 { 375, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MASK_WRITE
1038 { 374, 2, 0, 0, 3, 0, 0, R600OpInfoBase + 231, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP_COND
1039 { 373, 1, 0, 0, 3, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP
1040 { 372, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // IF_PREDICATE_SET
1041 { 371, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_i32
1042 { 370, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_f32
1043 { 369, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_i32
1044 { 368, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_f32
1045 { 367, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_i32
1046 { 366, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_f32
1047 { 365, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // FUNC
1048 { 364, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FNEG_R600
1049 { 363, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FABS_R600
1050 { 362, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDSWITCH
1051 { 361, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDMAIN
1052 { 360, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDLOOP
1053 { 359, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDIF
1054 { 358, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDFUNC
1055 { 357, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // END
1056 { 356, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ELSE
1057 { 355, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // DUMMY_CHAIN
1058 { 354, 71, 1, 0, 3, 0, 0, R600OpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // DOT_4
1059 { 353, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // DEFAULT
1060 { 352, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_r600_pseudo
1061 { 351, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_eg_pseudo
1062 { 350, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_i32
1063 { 349, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_f32
1064 { 348, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_i32
1065 { 347, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_f32
1066 { 346, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_i32
1067 { 345, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_f32
1068 { 344, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE
1069 { 343, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // CONST_COPY
1070 { 342, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_i32
1071 { 341, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_f32
1072 { 340, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_i32
1073 { 339, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_f32
1074 { 338, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_i32
1075 { 337, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_f32
1076 { 336, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK
1077 { 335, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_i32
1078 { 334, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_f32
1079 { 333, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH
1080 { 332, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX
1081 { 331, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX
1082 { 330, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN
1083 { 329, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX
1084 { 328, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN
1085 { 327, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX
1086 { 326, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR
1087 { 325, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR
1088 { 324, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND
1089 { 323, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL
1090 { 322, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD
1091 { 321, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1092 { 320, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1093 { 319, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1094 { 318, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1095 { 317, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN
1096 { 316, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX
1097 { 315, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL
1098 { 314, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD
1099 { 313, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1100 { 312, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1101 { 311, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP
1102 { 310, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP
1103 { 309, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP
1104 { 308, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET_INLINE
1105 { 307, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO
1106 { 306, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET
1107 { 305, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE
1108 { 304, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE
1109 { 303, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY
1110 { 302, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1111 { 301, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1112 { 300, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMPS
1113 { 299, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMP
1114 { 298, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP
1115 { 297, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT
1116 { 296, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA
1117 { 295, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM
1118 { 294, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV
1119 { 293, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL
1120 { 292, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB
1121 { 291, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD
1122 { 290, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE
1123 { 289, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE
1124 { 288, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC
1125 { 287, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE
1126 { 286, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR
1127 { 285, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST
1128 { 284, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT
1129 { 283, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT
1130 { 282, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR
1131 { 281, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT
1132 { 280, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH
1133 { 279, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH
1134 { 278, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH
1135 { 277, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2
1136 { 276, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN
1137 { 275, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN
1138 { 274, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS
1139 { 273, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN
1140 { 272, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS
1141 { 271, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN
1142 { 270, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS
1143 { 269, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL
1144 { 268, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMUL
1145 { 267, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE
1146 { 266, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP
1147 { 265, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP
1148 { 264, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS
1149 { 263, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_POISON
1150 { 262, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ
1151 { 261, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_POISON
1152 { 260, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ
1153 { 259, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS
1154 { 258, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR
1155 { 257, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR
1156 { 256, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR
1157 { 255, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1158 { 254, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT
1159 { 253, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1160 { 252, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR
1161 { 251, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE
1162 { 250, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT
1163 { 249, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR
1164 { 248, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND
1165 { 247, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND
1166 { 246, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS
1167 { 245, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX
1168 { 244, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN
1169 { 243, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX
1170 { 242, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN
1171 { 241, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK
1172 { 240, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD
1173 { 239, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING
1174 { 238, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING
1175 { 237, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE
1176 { 236, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE
1177 { 235, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE
1178 { 234, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV
1179 { 233, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV
1180 { 232, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV
1181 { 231, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM
1182 { 230, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM
1183 { 229, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM
1184 { 228, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM
1185 { 227, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE
1186 { 226, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE
1187 { 225, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM
1188 { 224, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM
1189 { 223, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE
1190 { 222, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS
1191 { 221, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN
1192 { 220, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS
1193 { 219, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT
1194 { 218, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT
1195 { 217, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP
1196 { 216, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP
1197 { 215, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI
1198 { 214, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI
1199 { 213, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC
1200 { 212, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT
1201 { 211, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG
1202 { 210, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP
1203 { 209, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP
1204 { 208, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10
1205 { 207, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2
1206 { 206, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG
1207 { 205, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10
1208 { 204, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2
1209 { 203, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP
1210 { 202, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI
1211 { 201, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW
1212 { 200, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF
1213 { 199, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM
1214 { 198, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV
1215 { 197, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD
1216 { 196, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA
1217 { 195, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL
1218 { 194, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB
1219 { 193, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD
1220 { 192, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT
1221 { 191, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT
1222 { 190, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX
1223 { 189, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX
1224 { 188, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT
1225 { 187, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT
1226 { 186, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX
1227 { 185, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX
1228 { 184, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT
1229 { 183, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT
1230 { 182, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT
1231 { 181, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT
1232 { 180, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT
1233 { 179, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT
1234 { 178, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH
1235 { 177, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH
1236 { 176, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO
1237 { 175, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO
1238 { 174, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE
1239 { 173, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO
1240 { 172, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE
1241 { 171, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO
1242 { 170, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE
1243 { 169, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO
1244 { 168, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE
1245 { 167, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO
1246 { 166, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT
1247 { 165, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP
1248 { 164, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP
1249 { 163, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP
1250 { 162, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP
1251 { 161, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL
1252 { 160, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR
1253 { 159, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR
1254 { 158, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL
1255 { 157, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR
1256 { 156, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR
1257 { 155, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL
1258 { 154, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT
1259 { 153, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG
1260 { 152, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT
1261 { 151, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG
1262 { 150, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART
1263 { 149, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT
1264 { 148, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT
1265 { 147, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U
1266 { 146, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U
1267 { 145, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S
1268 { 144, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC
1269 { 143, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT
1270 { 142, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1271 { 141, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1272 { 140, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1273 { 139, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC
1274 { 138, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START
1275 { 137, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT
1276 { 136, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND
1277 { 135, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH
1278 { 134, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE
1279 { 133, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1280 { 132, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1281 { 131, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1282 { 130, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1283 { 129, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1284 { 128, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1285 { 127, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1286 { 126, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1287 { 125, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN
1288 { 124, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX
1289 { 123, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB
1290 { 122, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD
1291 { 121, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN
1292 { 120, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX
1293 { 119, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN
1294 { 118, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX
1295 { 117, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR
1296 { 116, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR
1297 { 115, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND
1298 { 114, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND
1299 { 113, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB
1300 { 112, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD
1301 { 111, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG
1302 { 110, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG
1303 { 109, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1304 { 108, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE
1305 { 107, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_FPTRUNCSTORE
1306 { 106, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE
1307 { 105, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1308 { 104, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD
1309 { 103, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD
1310 { 102, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_FPEXTLOAD
1311 { 101, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD
1312 { 100, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD
1313 { 99, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD
1314 { 98, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER
1315 { 97, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER
1316 { 96, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1317 { 95, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT
1318 { 94, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT
1319 { 93, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND
1320 { 92, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC
1321 { 91, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1322 { 90, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1323 { 89, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE
1324 { 88, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST
1325 { 87, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR
1326 { 86, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT
1327 { 85, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS
1328 { 84, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1329 { 83, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR
1330 { 82, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES
1331 { 81, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT
1332 { 80, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES
1333 { 79, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT
1334 { 78, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL
1335 { 77, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1336 { 76, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE
1337 { 75, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX
1338 { 74, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI
1339 { 73, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF
1340 { 72, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL
1341 { 71, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR
1342 { 70, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL
1343 { 69, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR
1344 { 68, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU
1345 { 67, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS
1346 { 66, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR
1347 { 65, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR
1348 { 64, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND
1349 { 63, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM
1350 { 62, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM
1351 { 61, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM
1352 { 60, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM
1353 { 59, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV
1354 { 58, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV
1355 { 57, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL
1356 { 56, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB
1357 { 55, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD
1358 { 54, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN
1359 { 53, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT
1360 { 52, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT
1361 { 51, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1362 { 50, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1363 { 49, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1364 { 48, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1365 { 47, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE
1366 { 46, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1367 { 45, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER
1368 { 44, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE
1369 { 43, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1370 { 42, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14258
1371 { 41, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14257
1372 { 40, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL
1373 { 39, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1374 { 38, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET
1375 { 37, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1376 { 36, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP
1377 { 35, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP
1378 { 34, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE
1379 { 33, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT
1380 { 32, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14256
1381 { 31, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP
1382 { 30, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_13978
1383 { 29, 6, 1, 0, 0, 0, 0, R600OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT
1384 { 28, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL
1385 { 27, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP
1386 { 26, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE
1387 { 25, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE
1388 { 24, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END
1389 { 23, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START
1390 { 22, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE
1391 { 21, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK
1392 { 20, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY
1393 { 19, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE
1394 { 18, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL
1395 { 17, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI
1396 { 16, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF
1397 { 15, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST
1398 { 14, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE
1399 { 13, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS
1400 { 12, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG
1401 { 11, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF
1402 { 10, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF
1403 { 9, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG
1404 { 8, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG
1405 { 7, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL
1406 { 6, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL
1407 { 5, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL
1408 { 4, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL
1409 { 3, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION
1410 { 2, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR
1411 { 1, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM
1412 { 0, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI
1413 }, {
1414 /* 0 */
1415 }, {
1416 0
1417 }, {
1418 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1419 /* 1 */
1420 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1421 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1422 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1423 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1424 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1425 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1426 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1427 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1428 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1429 /* 28 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1430 /* 29 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1431 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1432 /* 34 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1433 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1434 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1435 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1436 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1437 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1438 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1439 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1440 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1441 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1442 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1443 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1444 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1445 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1446 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1447 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1448 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1449 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1450 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1451 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1452 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1453 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1454 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1455 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1456 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1457 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1458 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1459 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1460 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1461 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1462 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1463 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1464 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1465 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1466 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1467 /* 153 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1468 /* 155 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1469 /* 156 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1470 /* 158 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1471 /* 160 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1472 /* 231 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1473 /* 233 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1474 /* 237 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1475 /* 240 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1476 /* 243 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1477 /* 247 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1478 /* 251 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1479 /* 255 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1480 /* 262 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1481 /* 283 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1482 /* 297 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1483 /* 316 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1484 /* 325 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1485 /* 332 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1486 /* 341 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1487 /* 346 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1488 /* 351 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1489 /* 353 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1490 /* 362 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1491 /* 372 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1492 /* 379 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1493 /* 391 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1494 /* 404 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1495 /* 407 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1496 /* 409 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1497 /* 411 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1498 /* 413 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1499 /* 417 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1500 /* 420 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1501 /* 423 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1502 /* 426 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1503 /* 445 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1504 /* 449 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1505 /* 453 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1506 /* 457 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1507 }
1508};
1509
1510
1511#ifdef __GNUC__
1512#pragma GCC diagnostic push
1513#pragma GCC diagnostic ignored "-Woverlength-strings"
1514#endif
1515extern const char R600InstrNameData[] = {
1516 /* 0 */ "CF_TC_R600\000"
1517 /* 11 */ "CF_VC_R600\000"
1518 /* 22 */ "CF_END_R600\000"
1519 /* 34 */ "CF_ELSE_R600\000"
1520 /* 47 */ "CF_PUSH_ELSE_R600\000"
1521 /* 65 */ "CF_CONTINUE_R600\000"
1522 /* 82 */ "FNEG_R600\000"
1523 /* 92 */ "LOOP_BREAK_R600\000"
1524 /* 108 */ "CF_JUMP_R600\000"
1525 /* 121 */ "END_LOOP_R600\000"
1526 /* 135 */ "WHILE_LOOP_R600\000"
1527 /* 151 */ "POP_R600\000"
1528 /* 160 */ "FABS_R600\000"
1529 /* 170 */ "CF_CALL_FS_R600\000"
1530 /* 186 */ "DOT4_r600\000"
1531 /* 196 */ "MULADD_r600\000"
1532 /* 208 */ "LOG_CLAMPED_r600\000"
1533 /* 225 */ "RECIP_CLAMPED_r600\000"
1534 /* 244 */ "RECIPSQRT_CLAMPED_r600\000"
1535 /* 267 */ "CNDE_r600\000"
1536 /* 277 */ "MULADD_IEEE_r600\000"
1537 /* 294 */ "LOG_IEEE_r600\000"
1538 /* 308 */ "RECIP_IEEE_r600\000"
1539 /* 324 */ "EXP_IEEE_r600\000"
1540 /* 338 */ "RECIPSQRT_IEEE_r600\000"
1541 /* 358 */ "CNDGE_r600\000"
1542 /* 369 */ "LSHL_r600\000"
1543 /* 379 */ "SIN_r600\000"
1544 /* 388 */ "ASHR_r600\000"
1545 /* 398 */ "LSHR_r600\000"
1546 /* 408 */ "COS_r600\000"
1547 /* 417 */ "CNDGT_r600\000"
1548 /* 428 */ "MUL_LIT_r600\000"
1549 /* 441 */ "UINT_TO_FLT_r600\000"
1550 /* 458 */ "MULHI_UINT_r600\000"
1551 /* 474 */ "MULLO_UINT_r600\000"
1552 /* 490 */ "FLT_TO_UINT_r600\000"
1553 /* 507 */ "RECIP_UINT_r600\000"
1554 /* 523 */ "MULHI_INT_r600\000"
1555 /* 538 */ "MULLO_INT_r600\000"
1556 /* 553 */ "FLT_TO_INT_r600\000"
1557 /* 569 */ "SIN_r700\000"
1558 /* 578 */ "COS_r700\000"
1559 /* 587 */ "G_FLOG10\000"
1560 /* 596 */ "G_FEXP10\000"
1561 /* 605 */ "SETGE_DX10\000"
1562 /* 616 */ "SETNE_DX10\000"
1563 /* 627 */ "SETE_DX10\000"
1564 /* 637 */ "MIN_DX10\000"
1565 /* 646 */ "SETGT_DX10\000"
1566 /* 657 */ "MAX_DX10\000"
1567 /* 666 */ "INTERP_LOAD_P0\000"
1568 /* 681 */ "RAT_STORE_DWORD32\000"
1569 /* 699 */ "MOV_IMM_F32\000"
1570 /* 711 */ "MOV_IMM_I32\000"
1571 /* 723 */ "FLT16_TO_FLT32\000"
1572 /* 738 */ "CONTINUEC_f32\000"
1573 /* 752 */ "IFC_f32\000"
1574 /* 760 */ "BREAKC_f32\000"
1575 /* 771 */ "BRANCH_COND_f32\000"
1576 /* 787 */ "CONTINUE_LOGICALZ_f32\000"
1577 /* 809 */ "IF_LOGICALZ_f32\000"
1578 /* 825 */ "BREAK_LOGICALZ_f32\000"
1579 /* 844 */ "CONTINUE_LOGICALNZ_f32\000"
1580 /* 867 */ "IF_LOGICALNZ_f32\000"
1581 /* 884 */ "BREAK_LOGICALNZ_f32\000"
1582 /* 904 */ "CONTINUEC_i32\000"
1583 /* 918 */ "IFC_i32\000"
1584 /* 926 */ "BREAKC_i32\000"
1585 /* 937 */ "BRANCH_COND_i32\000"
1586 /* 953 */ "CONTINUE_LOGICALZ_i32\000"
1587 /* 975 */ "IF_LOGICALZ_i32\000"
1588 /* 991 */ "BREAK_LOGICALZ_i32\000"
1589 /* 1010 */ "CONTINUE_LOGICALNZ_i32\000"
1590 /* 1033 */ "IF_LOGICALNZ_i32\000"
1591 /* 1050 */ "BREAK_LOGICALNZ_i32\000"
1592 /* 1070 */ "G_FLOG2\000"
1593 /* 1078 */ "G_FATAN2\000"
1594 /* 1087 */ "G_FEXP2\000"
1595 /* 1095 */ "R600_EXTRACT_ELT_V2\000"
1596 /* 1115 */ "R600_INSERT_ELT_V2\000"
1597 /* 1134 */ "MULHI_UINT_cm24\000"
1598 /* 1150 */ "MULHI_INT_cm24\000"
1599 /* 1165 */ "RAT_STORE_DWORD64\000"
1600 /* 1183 */ "R600_EXTRACT_ELT_V4\000"
1601 /* 1203 */ "R600_INSERT_ELT_V4\000"
1602 /* 1222 */ "DOT_4\000"
1603 /* 1228 */ "FLT32_TO_FLT16\000"
1604 /* 1243 */ "RAT_STORE_DWORD128\000"
1605 /* 1262 */ "G_FMA\000"
1606 /* 1268 */ "G_STRICT_FMA\000"
1607 /* 1281 */ "TEX_SAMPLE_C_LB\000"
1608 /* 1297 */ "TEX_SAMPLE_LB\000"
1609 /* 1311 */ "G_FSUB\000"
1610 /* 1318 */ "G_STRICT_FSUB\000"
1611 /* 1332 */ "G_ATOMICRMW_FSUB\000"
1612 /* 1349 */ "G_SUB\000"
1613 /* 1355 */ "LDS_SUB\000"
1614 /* 1363 */ "G_ATOMICRMW_SUB\000"
1615 /* 1379 */ "G_INTRINSIC\000"
1616 /* 1391 */ "ENDFUNC\000"
1617 /* 1399 */ "G_FPTRUNC\000"
1618 /* 1409 */ "G_INTRINSIC_TRUNC\000"
1619 /* 1427 */ "G_TRUNC\000"
1620 /* 1435 */ "G_BUILD_VECTOR_TRUNC\000"
1621 /* 1456 */ "G_DYN_STACKALLOC\000"
1622 /* 1473 */ "TEX_SAMPLE_C\000"
1623 /* 1486 */ "G_FMAD\000"
1624 /* 1493 */ "G_FPEXTLOAD\000"
1625 /* 1505 */ "G_INDEXED_SEXTLOAD\000"
1626 /* 1524 */ "G_SEXTLOAD\000"
1627 /* 1535 */ "G_INDEXED_ZEXTLOAD\000"
1628 /* 1554 */ "G_ZEXTLOAD\000"
1629 /* 1565 */ "INTERP_VEC_LOAD\000"
1630 /* 1581 */ "G_INDEXED_LOAD\000"
1631 /* 1596 */ "G_LOAD\000"
1632 /* 1603 */ "PAD\000"
1633 /* 1607 */ "G_VECREDUCE_FADD\000"
1634 /* 1624 */ "G_FADD\000"
1635 /* 1631 */ "G_VECREDUCE_SEQ_FADD\000"
1636 /* 1652 */ "G_STRICT_FADD\000"
1637 /* 1666 */ "G_ATOMICRMW_FADD\000"
1638 /* 1683 */ "G_VECREDUCE_ADD\000"
1639 /* 1699 */ "G_ADD\000"
1640 /* 1705 */ "G_PTR_ADD\000"
1641 /* 1715 */ "LDS_ADD\000"
1642 /* 1723 */ "G_ATOMICRMW_ADD\000"
1643 /* 1739 */ "TEX_LD\000"
1644 /* 1746 */ "G_ATOMICRMW_NAND\000"
1645 /* 1763 */ "G_VECREDUCE_AND\000"
1646 /* 1779 */ "G_AND\000"
1647 /* 1785 */ "LDS_AND\000"
1648 /* 1793 */ "G_ATOMICRMW_AND\000"
1649 /* 1809 */ "LIFETIME_END\000"
1650 /* 1822 */ "G_BRCOND\000"
1651 /* 1831 */ "G_ATOMICRMW_USUB_COND\000"
1652 /* 1853 */ "JUMP_COND\000"
1653 /* 1863 */ "G_LLROUND\000"
1654 /* 1873 */ "G_LROUND\000"
1655 /* 1882 */ "G_INTRINSIC_ROUND\000"
1656 /* 1900 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1657 /* 1926 */ "LOAD_STACK_GUARD\000"
1658 /* 1943 */ "TXD\000"
1659 /* 1947 */ "PSEUDO_PROBE\000"
1660 /* 1960 */ "G_SSUBE\000"
1661 /* 1968 */ "G_USUBE\000"
1662 /* 1976 */ "G_FENCE\000"
1663 /* 1984 */ "ARITH_FENCE\000"
1664 /* 1996 */ "REG_SEQUENCE\000"
1665 /* 2009 */ "G_SADDE\000"
1666 /* 2017 */ "G_UADDE\000"
1667 /* 2025 */ "G_GET_FPMODE\000"
1668 /* 2038 */ "G_RESET_FPMODE\000"
1669 /* 2053 */ "G_SET_FPMODE\000"
1670 /* 2066 */ "MUL_IEEE\000"
1671 /* 2075 */ "G_FMINNUM_IEEE\000"
1672 /* 2090 */ "G_FMAXNUM_IEEE\000"
1673 /* 2105 */ "SGE\000"
1674 /* 2109 */ "PRED_SETGE\000"
1675 /* 2120 */ "G_VSCALE\000"
1676 /* 2129 */ "G_JUMP_TABLE\000"
1677 /* 2142 */ "BUNDLE\000"
1678 /* 2149 */ "TEX_SAMPLE\000"
1679 /* 2160 */ "RNDNE\000"
1680 /* 2166 */ "G_MEMSET_INLINE\000"
1681 /* 2182 */ "G_MEMCPY_INLINE\000"
1682 /* 2198 */ "RELOC_NONE\000"
1683 /* 2209 */ "SNE\000"
1684 /* 2213 */ "PRED_SETNE\000"
1685 /* 2224 */ "LOCAL_ESCAPE\000"
1686 /* 2237 */ "CF_ALU_PUSH_BEFORE\000"
1687 /* 2256 */ "G_FPTRUNCSTORE\000"
1688 /* 2271 */ "G_STACKRESTORE\000"
1689 /* 2286 */ "G_INDEXED_STORE\000"
1690 /* 2302 */ "G_STORE\000"
1691 /* 2310 */ "ELSE\000"
1692 /* 2315 */ "G_BITREVERSE\000"
1693 /* 2328 */ "FETCH_CLAUSE\000"
1694 /* 2341 */ "ALU_CLAUSE\000"
1695 /* 2352 */ "FAKE_USE\000"
1696 /* 2361 */ "PRED_SETE\000"
1697 /* 2371 */ "LDS_BYTE_WRITE\000"
1698 /* 2386 */ "MASK_WRITE\000"
1699 /* 2397 */ "LDS_WRITE\000"
1700 /* 2407 */ "LDS_SHORT_WRITE\000"
1701 /* 2423 */ "DBG_VALUE\000"
1702 /* 2433 */ "G_GLOBAL_VALUE\000"
1703 /* 2448 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1704 /* 2471 */ "CONVERGENCECTRL_GLUE\000"
1705 /* 2492 */ "CF_ALU_CONTINUE\000"
1706 /* 2508 */ "G_STACKSAVE\000"
1707 /* 2520 */ "G_MEMMOVE\000"
1708 /* 2530 */ "G_FREEZE\000"
1709 /* 2539 */ "G_FCANONICALIZE\000"
1710 /* 2555 */ "G_FMODF\000"
1711 /* 2563 */ "INIT_UNDEF\000"
1712 /* 2574 */ "G_IMPLICIT_DEF\000"
1713 /* 2589 */ "DBG_INSTR_REF\000"
1714 /* 2603 */ "ENDIF\000"
1715 /* 2609 */ "TEX_VTX_CONSTBUF\000"
1716 /* 2626 */ "TEX_VTX_TEXBUF\000"
1717 /* 2641 */ "G_FNEG\000"
1718 /* 2648 */ "EXTRACT_SUBREG\000"
1719 /* 2663 */ "INSERT_SUBREG\000"
1720 /* 2677 */ "G_SEXT_INREG\000"
1721 /* 2690 */ "SUBREG_TO_REG\000"
1722 /* 2704 */ "CF_TC_EG\000"
1723 /* 2713 */ "CF_VC_EG\000"
1724 /* 2722 */ "CF_END_EG\000"
1725 /* 2732 */ "CF_ELSE_EG\000"
1726 /* 2743 */ "CF_CONTINUE_EG\000"
1727 /* 2758 */ "CF_PUSH_EG\000"
1728 /* 2769 */ "LOOP_BREAK_EG\000"
1729 /* 2783 */ "CF_JUMP_EG\000"
1730 /* 2794 */ "END_LOOP_EG\000"
1731 /* 2806 */ "WHILE_LOOP_EG\000"
1732 /* 2820 */ "POP_EG\000"
1733 /* 2827 */ "CF_CALL_FS_EG\000"
1734 /* 2841 */ "G_ATOMIC_CMPXCHG\000"
1735 /* 2858 */ "LDS_WRXCHG\000"
1736 /* 2869 */ "G_ATOMICRMW_XCHG\000"
1737 /* 2886 */ "G_GET_ROUNDING\000"
1738 /* 2901 */ "G_SET_ROUNDING\000"
1739 /* 2916 */ "G_FLOG\000"
1740 /* 2923 */ "G_VAARG\000"
1741 /* 2931 */ "PREALLOCATED_ARG\000"
1742 /* 2948 */ "TEX_SAMPLE_C_G\000"
1743 /* 2963 */ "TEX_SAMPLE_G\000"
1744 /* 2976 */ "BRANCH\000"
1745 /* 2983 */ "G_PREFETCH\000"
1746 /* 2994 */ "ENDSWITCH\000"
1747 /* 3004 */ "G_SMULH\000"
1748 /* 3012 */ "G_UMULH\000"
1749 /* 3020 */ "G_FTANH\000"
1750 /* 3028 */ "G_FSINH\000"
1751 /* 3036 */ "G_FCOSH\000"
1752 /* 3044 */ "TEX_GET_GRADIENTS_H\000"
1753 /* 3064 */ "TEX_SET_GRADIENTS_H\000"
1754 /* 3084 */ "DBG_PHI\000"
1755 /* 3092 */ "G_FPTOSI\000"
1756 /* 3101 */ "G_FPTOUI\000"
1757 /* 3110 */ "G_FPOWI\000"
1758 /* 3118 */ "CF_ALU_BREAK\000"
1759 /* 3131 */ "COPY_LANEMASK\000"
1760 /* 3145 */ "G_PTRMASK\000"
1761 /* 3155 */ "GC_LABEL\000"
1762 /* 3164 */ "DBG_LABEL\000"
1763 /* 3174 */ "EH_LABEL\000"
1764 /* 3183 */ "ANNOTATION_LABEL\000"
1765 /* 3200 */ "ICALL_BRANCH_FUNNEL\000"
1766 /* 3220 */ "G_FSHL\000"
1767 /* 3227 */ "G_SHL\000"
1768 /* 3233 */ "G_FCEIL\000"
1769 /* 3241 */ "G_SAVGCEIL\000"
1770 /* 3252 */ "G_UAVGCEIL\000"
1771 /* 3263 */ "PATCHABLE_TAIL_CALL\000"
1772 /* 3283 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1773 /* 3310 */ "PATCHABLE_EVENT_CALL\000"
1774 /* 3331 */ "FENTRY_CALL\000"
1775 /* 3343 */ "KILL\000"
1776 /* 3348 */ "G_CONSTANT_POOL\000"
1777 /* 3364 */ "G_ROTL\000"
1778 /* 3371 */ "G_VECREDUCE_FMUL\000"
1779 /* 3388 */ "G_FMUL\000"
1780 /* 3395 */ "G_VECREDUCE_SEQ_FMUL\000"
1781 /* 3416 */ "G_STRICT_FMUL\000"
1782 /* 3430 */ "G_CLMUL\000"
1783 /* 3438 */ "G_VECREDUCE_MUL\000"
1784 /* 3454 */ "G_MUL\000"
1785 /* 3460 */ "TEX_SAMPLE_C_L\000"
1786 /* 3475 */ "TEX_SAMPLE_L\000"
1787 /* 3488 */ "CF_END_CM\000"
1788 /* 3498 */ "G_FREM\000"
1789 /* 3505 */ "G_STRICT_FREM\000"
1790 /* 3519 */ "G_SREM\000"
1791 /* 3526 */ "G_UREM\000"
1792 /* 3533 */ "G_SDIVREM\000"
1793 /* 3543 */ "G_UDIVREM\000"
1794 /* 3553 */ "INLINEASM\000"
1795 /* 3563 */ "G_VECREDUCE_FMINIMUM\000"
1796 /* 3584 */ "G_FMINIMUM\000"
1797 /* 3595 */ "G_ATOMICRMW_FMINIMUM\000"
1798 /* 3616 */ "G_VECREDUCE_FMAXIMUM\000"
1799 /* 3637 */ "G_FMAXIMUM\000"
1800 /* 3648 */ "G_ATOMICRMW_FMAXIMUM\000"
1801 /* 3669 */ "G_VECREDUCE_FMINIMUMNUM\000"
1802 /* 3693 */ "G_FMINIMUMNUM\000"
1803 /* 3707 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1804 /* 3731 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1805 /* 3755 */ "G_FMAXIMUMNUM\000"
1806 /* 3769 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1807 /* 3793 */ "G_FMINNUM\000"
1808 /* 3803 */ "G_FMAXNUM\000"
1809 /* 3813 */ "G_FATAN\000"
1810 /* 3821 */ "G_FTAN\000"
1811 /* 3828 */ "G_INTRINSIC_ROUNDEVEN\000"
1812 /* 3850 */ "G_ASSERT_ALIGN\000"
1813 /* 3865 */ "G_FCOPYSIGN\000"
1814 /* 3877 */ "DUMMY_CHAIN\000"
1815 /* 3889 */ "ENDMAIN\000"
1816 /* 3897 */ "G_VECREDUCE_FMIN\000"
1817 /* 3914 */ "G_ATOMICRMW_FMIN\000"
1818 /* 3931 */ "G_VECREDUCE_SMIN\000"
1819 /* 3948 */ "G_SMIN\000"
1820 /* 3955 */ "G_VECREDUCE_UMIN\000"
1821 /* 3972 */ "G_UMIN\000"
1822 /* 3979 */ "G_ATOMICRMW_UMIN\000"
1823 /* 3996 */ "G_ATOMICRMW_MIN\000"
1824 /* 4012 */ "G_FASIN\000"
1825 /* 4020 */ "G_FSIN\000"
1826 /* 4027 */ "CFI_INSTRUCTION\000"
1827 /* 4043 */ "G_CTLZ_ZERO_POISON\000"
1828 /* 4062 */ "G_CTTZ_ZERO_POISON\000"
1829 /* 4081 */ "RETURN\000"
1830 /* 4088 */ "RAT_ATOMIC_RSUB_RTN\000"
1831 /* 4108 */ "RAT_ATOMIC_SUB_RTN\000"
1832 /* 4127 */ "RAT_ATOMIC_ADD_RTN\000"
1833 /* 4146 */ "RAT_ATOMIC_AND_RTN\000"
1834 /* 4165 */ "RAT_ATOMIC_XOR_RTN\000"
1835 /* 4184 */ "RAT_ATOMIC_OR_RTN\000"
1836 /* 4202 */ "RAT_ATOMIC_DEC_UINT_RTN\000"
1837 /* 4226 */ "RAT_ATOMIC_INC_UINT_RTN\000"
1838 /* 4250 */ "RAT_ATOMIC_MIN_UINT_RTN\000"
1839 /* 4274 */ "RAT_ATOMIC_MAX_UINT_RTN\000"
1840 /* 4298 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\000"
1841 /* 4325 */ "RAT_ATOMIC_XCHG_INT_RTN\000"
1842 /* 4349 */ "RAT_ATOMIC_MIN_INT_RTN\000"
1843 /* 4372 */ "RAT_ATOMIC_MAX_INT_RTN\000"
1844 /* 4395 */ "RETDYN\000"
1845 /* 4402 */ "G_SSUBO\000"
1846 /* 4410 */ "G_USUBO\000"
1847 /* 4418 */ "G_SADDO\000"
1848 /* 4426 */ "G_UADDO\000"
1849 /* 4434 */ "TEX_GET_TEXTURE_RESINFO\000"
1850 /* 4458 */ "JUMP_TABLE_DEBUG_INFO\000"
1851 /* 4480 */ "G_SMULO\000"
1852 /* 4488 */ "G_UMULO\000"
1853 /* 4496 */ "G_BZERO\000"
1854 /* 4504 */ "STACKMAP\000"
1855 /* 4513 */ "G_DEBUGTRAP\000"
1856 /* 4525 */ "G_UBSANTRAP\000"
1857 /* 4537 */ "G_TRAP\000"
1858 /* 4544 */ "G_ATOMICRMW_UDEC_WRAP\000"
1859 /* 4566 */ "G_ATOMICRMW_UINC_WRAP\000"
1860 /* 4588 */ "G_BSWAP\000"
1861 /* 4596 */ "G_SITOFP\000"
1862 /* 4605 */ "G_UITOFP\000"
1863 /* 4614 */ "G_FCMP\000"
1864 /* 4621 */ "G_STRICT_FCMP\000"
1865 /* 4635 */ "G_ICMP\000"
1866 /* 4642 */ "G_SCMP\000"
1867 /* 4649 */ "G_UCMP\000"
1868 /* 4656 */ "JUMP\000"
1869 /* 4661 */ "ENDLOOP\000"
1870 /* 4669 */ "WHILELOOP\000"
1871 /* 4679 */ "CONVERGENCECTRL_LOOP\000"
1872 /* 4700 */ "G_CTPOP\000"
1873 /* 4708 */ "PATCHABLE_OP\000"
1874 /* 4721 */ "FAULTING_OP\000"
1875 /* 4733 */ "PREALLOCATED_SETUP\000"
1876 /* 4752 */ "G_FLDEXP\000"
1877 /* 4761 */ "G_STRICT_FLDEXP\000"
1878 /* 4777 */ "G_FEXP\000"
1879 /* 4784 */ "G_FFREXP\000"
1880 /* 4793 */ "G_BR\000"
1881 /* 4798 */ "INLINEASM_BR\000"
1882 /* 4811 */ "G_BLOCK_ADDR\000"
1883 /* 4824 */ "MOV_IMM_GLOBAL_ADDR\000"
1884 /* 4844 */ "MEMBARRIER\000"
1885 /* 4855 */ "G_CONSTANT_FOLD_BARRIER\000"
1886 /* 4879 */ "GROUP_BARRIER\000"
1887 /* 4893 */ "CF_ALU_ELSE_AFTER\000"
1888 /* 4911 */ "CF_ALU_POP_AFTER\000"
1889 /* 4928 */ "PATCHABLE_FUNCTION_ENTER\000"
1890 /* 4953 */ "G_READCYCLECOUNTER\000"
1891 /* 4972 */ "G_READSTEADYCOUNTER\000"
1892 /* 4992 */ "G_READ_REGISTER\000"
1893 /* 5008 */ "G_WRITE_REGISTER\000"
1894 /* 5025 */ "G_ASHR\000"
1895 /* 5032 */ "G_FSHR\000"
1896 /* 5039 */ "G_LSHR\000"
1897 /* 5046 */ "CONVERGENCECTRL_ANCHOR\000"
1898 /* 5069 */ "RAT_MSKOR\000"
1899 /* 5079 */ "G_FFLOOR\000"
1900 /* 5088 */ "G_SAVGFLOOR\000"
1901 /* 5100 */ "G_UAVGFLOOR\000"
1902 /* 5112 */ "G_EXTRACT_SUBVECTOR\000"
1903 /* 5132 */ "G_INSERT_SUBVECTOR\000"
1904 /* 5151 */ "G_BUILD_VECTOR\000"
1905 /* 5166 */ "G_SHUFFLE_VECTOR\000"
1906 /* 5183 */ "G_STEP_VECTOR\000"
1907 /* 5197 */ "G_SPLAT_VECTOR\000"
1908 /* 5212 */ "G_VECREDUCE_XOR\000"
1909 /* 5228 */ "G_XOR\000"
1910 /* 5234 */ "LDS_XOR\000"
1911 /* 5242 */ "G_ATOMICRMW_XOR\000"
1912 /* 5258 */ "G_VECREDUCE_OR\000"
1913 /* 5273 */ "G_OR\000"
1914 /* 5278 */ "LDS_OR\000"
1915 /* 5285 */ "G_ATOMICRMW_OR\000"
1916 /* 5300 */ "G_ROTR\000"
1917 /* 5307 */ "TEX_LDPTR\000"
1918 /* 5317 */ "G_INTTOPTR\000"
1919 /* 5328 */ "G_FABS\000"
1920 /* 5335 */ "G_ABS\000"
1921 /* 5341 */ "G_ABDS\000"
1922 /* 5348 */ "G_UNMERGE_VALUES\000"
1923 /* 5365 */ "G_MERGE_VALUES\000"
1924 /* 5380 */ "LITERALS\000"
1925 /* 5389 */ "G_CTLS\000"
1926 /* 5396 */ "G_FACOS\000"
1927 /* 5404 */ "G_FCOS\000"
1928 /* 5411 */ "G_FSINCOS\000"
1929 /* 5421 */ "G_STRICT_FCMPS\000"
1930 /* 5436 */ "G_CONCAT_VECTORS\000"
1931 /* 5453 */ "COPY_TO_REGCLASS\000"
1932 /* 5470 */ "G_IS_FPCLASS\000"
1933 /* 5483 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1934 /* 5513 */ "G_VECTOR_COMPRESS\000"
1935 /* 5531 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1936 /* 5558 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1937 /* 5596 */ "G_TRUNC_SSAT_S\000"
1938 /* 5611 */ "G_SSUBSAT\000"
1939 /* 5621 */ "G_USUBSAT\000"
1940 /* 5631 */ "G_SADDSAT\000"
1941 /* 5641 */ "G_UADDSAT\000"
1942 /* 5651 */ "G_SSHLSAT\000"
1943 /* 5661 */ "G_USHLSAT\000"
1944 /* 5671 */ "G_SMULFIXSAT\000"
1945 /* 5684 */ "G_UMULFIXSAT\000"
1946 /* 5697 */ "G_SDIVFIXSAT\000"
1947 /* 5710 */ "G_UDIVFIXSAT\000"
1948 /* 5723 */ "G_ATOMICRMW_USUB_SAT\000"
1949 /* 5744 */ "G_FPTOSI_SAT\000"
1950 /* 5757 */ "G_FPTOUI_SAT\000"
1951 /* 5770 */ "FRACT\000"
1952 /* 5776 */ "G_EXTRACT\000"
1953 /* 5786 */ "G_SELECT\000"
1954 /* 5795 */ "G_BRINDIRECT\000"
1955 /* 5808 */ "RAT_ATOMIC_RSUB_NORET\000"
1956 /* 5830 */ "RAT_ATOMIC_SUB_NORET\000"
1957 /* 5851 */ "RAT_ATOMIC_ADD_NORET\000"
1958 /* 5872 */ "RAT_ATOMIC_AND_NORET\000"
1959 /* 5893 */ "RAT_ATOMIC_XOR_NORET\000"
1960 /* 5914 */ "RAT_ATOMIC_OR_NORET\000"
1961 /* 5934 */ "RAT_ATOMIC_DEC_UINT_NORET\000"
1962 /* 5960 */ "RAT_ATOMIC_INC_UINT_NORET\000"
1963 /* 5986 */ "RAT_ATOMIC_MIN_UINT_NORET\000"
1964 /* 6012 */ "RAT_ATOMIC_MAX_UINT_NORET\000"
1965 /* 6038 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\000"
1966 /* 6067 */ "RAT_ATOMIC_XCHG_INT_NORET\000"
1967 /* 6093 */ "RAT_ATOMIC_MIN_INT_NORET\000"
1968 /* 6118 */ "RAT_ATOMIC_MAX_INT_NORET\000"
1969 /* 6143 */ "LDS_SUB_RET\000"
1970 /* 6155 */ "LDS_UBYTE_READ_RET\000"
1971 /* 6174 */ "LDS_BYTE_READ_RET\000"
1972 /* 6192 */ "LDS_READ_RET\000"
1973 /* 6205 */ "LDS_USHORT_READ_RET\000"
1974 /* 6225 */ "LDS_SHORT_READ_RET\000"
1975 /* 6244 */ "LDS_ADD_RET\000"
1976 /* 6256 */ "LDS_AND_RET\000"
1977 /* 6268 */ "PATCHABLE_RET\000"
1978 /* 6282 */ "LDS_WRXCHG_RET\000"
1979 /* 6297 */ "LDS_XOR_RET\000"
1980 /* 6309 */ "LDS_OR_RET\000"
1981 /* 6320 */ "LDS_MIN_UINT_RET\000"
1982 /* 6337 */ "LDS_MAX_UINT_RET\000"
1983 /* 6354 */ "LDS_MIN_INT_RET\000"
1984 /* 6370 */ "LDS_MAX_INT_RET\000"
1985 /* 6386 */ "LDS_CMPST_RET\000"
1986 /* 6400 */ "G_MEMSET\000"
1987 /* 6409 */ "IF_PREDICATE_SET\000"
1988 /* 6426 */ "KILLGT\000"
1989 /* 6433 */ "SGT\000"
1990 /* 6437 */ "PRED_SETGT\000"
1991 /* 6448 */ "PATCHABLE_FUNCTION_EXIT\000"
1992 /* 6472 */ "G_BRJT\000"
1993 /* 6479 */ "G_EXTRACT_VECTOR_ELT\000"
1994 /* 6500 */ "G_INSERT_VECTOR_ELT\000"
1995 /* 6520 */ "DEFAULT\000"
1996 /* 6528 */ "G_FCONSTANT\000"
1997 /* 6540 */ "G_CONSTANT\000"
1998 /* 6551 */ "G_INTRINSIC_CONVERGENT\000"
1999 /* 6574 */ "STATEPOINT\000"
2000 /* 6585 */ "PATCHPOINT\000"
2001 /* 6596 */ "G_PTRTOINT\000"
2002 /* 6607 */ "G_FRINT\000"
2003 /* 6615 */ "G_INTRINSIC_LLRINT\000"
2004 /* 6634 */ "G_INTRINSIC_LRINT\000"
2005 /* 6652 */ "SUBB_UINT\000"
2006 /* 6662 */ "ADDC_UINT\000"
2007 /* 6672 */ "SETGE_UINT\000"
2008 /* 6683 */ "FFBH_UINT\000"
2009 /* 6693 */ "LDS_MIN_UINT\000"
2010 /* 6706 */ "SETGT_UINT\000"
2011 /* 6717 */ "LDS_MAX_UINT\000"
2012 /* 6730 */ "G_FNEARBYINT\000"
2013 /* 6743 */ "SUB_INT\000"
2014 /* 6751 */ "ADD_INT\000"
2015 /* 6759 */ "AND_INT\000"
2016 /* 6767 */ "CNDE_INT\000"
2017 /* 6776 */ "CNDGE_INT\000"
2018 /* 6786 */ "PRED_SETGE_INT\000"
2019 /* 6801 */ "PRED_SETNE_INT\000"
2020 /* 6816 */ "PRED_SETE_INT\000"
2021 /* 6830 */ "FFBL_INT\000"
2022 /* 6839 */ "LDS_MIN_INT\000"
2023 /* 6851 */ "XOR_INT\000"
2024 /* 6859 */ "CNDGT_INT\000"
2025 /* 6869 */ "PRED_SETGT_INT\000"
2026 /* 6884 */ "BCNT_INT\000"
2027 /* 6893 */ "NOT_INT\000"
2028 /* 6901 */ "LDS_MAX_INT\000"
2029 /* 6913 */ "G_VASTART\000"
2030 /* 6923 */ "LIFETIME_START\000"
2031 /* 6938 */ "G_INVOKE_REGION_START\000"
2032 /* 6960 */ "G_INSERT\000"
2033 /* 6969 */ "G_FSQRT\000"
2034 /* 6977 */ "G_STRICT_FSQRT\000"
2035 /* 6992 */ "G_BITCAST\000"
2036 /* 7002 */ "G_ADDRSPACE_CAST\000"
2037 /* 7019 */ "DBG_VALUE_LIST\000"
2038 /* 7034 */ "LDS_CMPST\000"
2039 /* 7044 */ "G_FPEXT\000"
2040 /* 7052 */ "G_SEXT\000"
2041 /* 7059 */ "G_ASSERT_SEXT\000"
2042 /* 7073 */ "G_ANYEXT\000"
2043 /* 7082 */ "G_ZEXT\000"
2044 /* 7089 */ "G_ASSERT_ZEXT\000"
2045 /* 7103 */ "G_ABDU\000"
2046 /* 7110 */ "CF_ALU\000"
2047 /* 7117 */ "G_TRUNC_SSAT_U\000"
2048 /* 7132 */ "G_TRUNC_USAT_U\000"
2049 /* 7147 */ "G_FDIV\000"
2050 /* 7154 */ "G_STRICT_FDIV\000"
2051 /* 7168 */ "G_SDIV\000"
2052 /* 7175 */ "G_UDIV\000"
2053 /* 7182 */ "G_GET_FPENV\000"
2054 /* 7194 */ "G_RESET_FPENV\000"
2055 /* 7208 */ "G_SET_FPENV\000"
2056 /* 7220 */ "MOV\000"
2057 /* 7224 */ "TEX_GET_GRADIENTS_V\000"
2058 /* 7244 */ "TEX_SET_GRADIENTS_V\000"
2059 /* 7264 */ "TXD_SHADOW\000"
2060 /* 7275 */ "G_FPOW\000"
2061 /* 7282 */ "INTERP_ZW\000"
2062 /* 7292 */ "INTERP_PAIR_ZW\000"
2063 /* 7307 */ "G_VECREDUCE_FMAX\000"
2064 /* 7324 */ "G_ATOMICRMW_FMAX\000"
2065 /* 7341 */ "G_VECREDUCE_SMAX\000"
2066 /* 7358 */ "G_SMAX\000"
2067 /* 7365 */ "G_VECREDUCE_UMAX\000"
2068 /* 7382 */ "G_UMAX\000"
2069 /* 7389 */ "G_ATOMICRMW_UMAX\000"
2070 /* 7406 */ "G_ATOMICRMW_MAX\000"
2071 /* 7422 */ "G_FRAME_INDEX\000"
2072 /* 7436 */ "G_SBFX\000"
2073 /* 7443 */ "G_UBFX\000"
2074 /* 7450 */ "G_SMULFIX\000"
2075 /* 7460 */ "G_UMULFIX\000"
2076 /* 7470 */ "G_SDIVFIX\000"
2077 /* 7480 */ "G_UDIVFIX\000"
2078 /* 7490 */ "PRED_X\000"
2079 /* 7497 */ "G_MEMCPY\000"
2080 /* 7506 */ "CONST_COPY\000"
2081 /* 7517 */ "CONVERGENCECTRL_ENTRY\000"
2082 /* 7539 */ "INTERP_XY\000"
2083 /* 7549 */ "INTERP_PAIR_XY\000"
2084 /* 7564 */ "G_CTLZ\000"
2085 /* 7571 */ "G_CTTZ\000"
2086 /* 7578 */ "R600_RegisterLoad\000"
2087 /* 7596 */ "R600_RegisterStore\000"
2088 /* 7615 */ "R600_ExportBuf\000"
2089 /* 7630 */ "EG_ExportBuf\000"
2090 /* 7643 */ "VTX_READ_32_eg\000"
2091 /* 7658 */ "RAT_WRITE_CACHELESS_32_eg\000"
2092 /* 7684 */ "MULADD_UINT24_eg\000"
2093 /* 7701 */ "MULHI_UINT24_eg\000"
2094 /* 7717 */ "MUL_UINT24_eg\000"
2095 /* 7731 */ "VTX_READ_64_eg\000"
2096 /* 7746 */ "RAT_WRITE_CACHELESS_64_eg\000"
2097 /* 7772 */ "DOT4_eg\000"
2098 /* 7780 */ "VTX_READ_16_eg\000"
2099 /* 7795 */ "VTX_READ_128_eg\000"
2100 /* 7811 */ "RAT_WRITE_CACHELESS_128_eg\000"
2101 /* 7838 */ "VTX_READ_8_eg\000"
2102 /* 7852 */ "FMA_eg\000"
2103 /* 7859 */ "MULADD_eg\000"
2104 /* 7869 */ "LOG_CLAMPED_eg\000"
2105 /* 7884 */ "RECIP_CLAMPED_eg\000"
2106 /* 7901 */ "RECIPSQRT_CLAMPED_eg\000"
2107 /* 7922 */ "RAT_STORE_TYPED_eg\000"
2108 /* 7941 */ "CNDE_eg\000"
2109 /* 7949 */ "MULADD_IEEE_eg\000"
2110 /* 7964 */ "LOG_IEEE_eg\000"
2111 /* 7976 */ "RECIP_IEEE_eg\000"
2112 /* 7990 */ "EXP_IEEE_eg\000"
2113 /* 8002 */ "RECIPSQRT_IEEE_eg\000"
2114 /* 8020 */ "CNDGE_eg\000"
2115 /* 8029 */ "LSHL_eg\000"
2116 /* 8037 */ "SIN_eg\000"
2117 /* 8044 */ "ASHR_eg\000"
2118 /* 8052 */ "LSHR_eg\000"
2119 /* 8060 */ "COS_eg\000"
2120 /* 8067 */ "CNDGT_eg\000"
2121 /* 8076 */ "MUL_LIT_eg\000"
2122 /* 8087 */ "UINT_TO_FLT_eg\000"
2123 /* 8102 */ "BFE_UINT_eg\000"
2124 /* 8114 */ "MULHI_UINT_eg\000"
2125 /* 8128 */ "MULLO_UINT_eg\000"
2126 /* 8142 */ "FLT_TO_UINT_eg\000"
2127 /* 8157 */ "RECIP_UINT_eg\000"
2128 /* 8171 */ "MOVA_INT_eg\000"
2129 /* 8183 */ "BFE_INT_eg\000"
2130 /* 8194 */ "BFI_INT_eg\000"
2131 /* 8205 */ "MULHI_INT_eg\000"
2132 /* 8218 */ "BFM_INT_eg\000"
2133 /* 8229 */ "BIT_ALIGN_INT_eg\000"
2134 /* 8246 */ "MULLO_INT_eg\000"
2135 /* 8259 */ "FLT_TO_INT_eg\000"
2136 /* 8273 */ "CUBE_r600_real\000"
2137 /* 8288 */ "CUBE_eg_real\000"
2138 /* 8301 */ "VTX_READ_32_cm\000"
2139 /* 8316 */ "MULADD_INT24_cm\000"
2140 /* 8332 */ "MUL_INT24_cm\000"
2141 /* 8345 */ "VTX_READ_64_cm\000"
2142 /* 8360 */ "VTX_READ_16_cm\000"
2143 /* 8375 */ "VTX_READ_128_cm\000"
2144 /* 8391 */ "VTX_READ_8_cm\000"
2145 /* 8405 */ "RECIP_CLAMPED_cm\000"
2146 /* 8422 */ "RECIPSQRT_CLAMPED_cm\000"
2147 /* 8443 */ "RAT_STORE_TYPED_cm\000"
2148 /* 8462 */ "LOG_IEEE_cm\000"
2149 /* 8474 */ "RECIP_IEEE_cm\000"
2150 /* 8488 */ "EXP_IEEE_cm\000"
2151 /* 8500 */ "RECIPSQRT_IEEE_cm\000"
2152 /* 8518 */ "SIN_cm\000"
2153 /* 8525 */ "COS_cm\000"
2154 /* 8532 */ "MULHI_UINT_cm\000"
2155 /* 8546 */ "MULLO_UINT_cm\000"
2156 /* 8560 */ "MULHI_INT_cm\000"
2157 /* 8573 */ "MULLO_INT_cm\000"
2158 /* 8586 */ "CUBE_r600_pseudo\000"
2159 /* 8603 */ "CUBE_eg_pseudo\000"
2160 /* 8618 */ "R600_ExportSwz\000"
2161 /* 8633 */ "EG_ExportSwz\000"
2162};
2163#ifdef __GNUC__
2164#pragma GCC diagnostic pop
2165#endif
2166
2167extern const unsigned R600InstrNameIndices[] = {
2168 3088U, 3553U, 4798U, 4027U, 3174U, 3155U, 3183U, 3343U,
2169 2648U, 2663U, 2576U, 2563U, 2690U, 5453U, 2423U, 7019U,
2170 2589U, 3084U, 3164U, 1996U, 7512U, 3131U, 2142U, 6923U,
2171 1809U, 1947U, 1984U, 4504U, 3331U, 6585U, 1926U, 4733U,
2172 2931U, 6574U, 2224U, 4721U, 4708U, 4928U, 6268U, 6448U,
2173 3263U, 3310U, 3283U, 3200U, 2352U, 4844U, 4458U, 2198U,
2174 7517U, 5046U, 4679U, 2471U, 7059U, 7089U, 3850U, 1699U,
2175 1349U, 3454U, 7168U, 7175U, 3519U, 3526U, 3533U, 3543U,
2176 1779U, 5273U, 5228U, 5341U, 7103U, 5100U, 3252U, 5088U,
2177 3241U, 2574U, 3086U, 7422U, 2433U, 2448U, 3348U, 5776U,
2178 5348U, 6960U, 5365U, 5151U, 1435U, 5436U, 6596U, 5317U,
2179 6992U, 2530U, 4855U, 1900U, 1409U, 1882U, 6634U, 6615U,
2180 3828U, 4953U, 4972U, 1596U, 1524U, 1554U, 1493U, 1581U,
2181 1505U, 1535U, 2302U, 2256U, 2286U, 5483U, 2841U, 2869U,
2182 1723U, 1363U, 1793U, 1746U, 5285U, 5242U, 7406U, 3996U,
2183 7389U, 3979U, 1666U, 1332U, 7324U, 3914U, 3648U, 3595U,
2184 3769U, 3707U, 4566U, 4544U, 1831U, 5723U, 1976U, 2983U,
2185 1822U, 5795U, 6938U, 1379U, 5531U, 6551U, 5558U, 7073U,
2186 1427U, 5596U, 7117U, 7132U, 6540U, 6528U, 6913U, 2923U,
2187 7052U, 2677U, 7082U, 3227U, 5039U, 5025U, 3220U, 5032U,
2188 5300U, 3364U, 4635U, 4614U, 4642U, 4649U, 5786U, 4426U,
2189 2017U, 4410U, 1968U, 4418U, 2009U, 4402U, 1960U, 4488U,
2190 4480U, 3012U, 3004U, 5641U, 5631U, 5621U, 5611U, 5661U,
2191 5651U, 7450U, 7460U, 5671U, 5684U, 7470U, 7480U, 5697U,
2192 5710U, 1624U, 1311U, 3388U, 1262U, 1486U, 7147U, 3498U,
2193 2555U, 7275U, 3110U, 4777U, 1087U, 596U, 2916U, 1070U,
2194 587U, 4752U, 4784U, 2641U, 7044U, 1399U, 3092U, 3101U,
2195 4596U, 4605U, 5744U, 5757U, 5328U, 3865U, 5470U, 2539U,
2196 3793U, 3803U, 2075U, 2090U, 3584U, 3637U, 3693U, 3755U,
2197 7182U, 7208U, 7194U, 2025U, 2053U, 2038U, 2886U, 2901U,
2198 1705U, 3145U, 3948U, 7358U, 3972U, 7382U, 5335U, 1873U,
2199 1863U, 4793U, 6472U, 2120U, 5132U, 5112U, 6500U, 6479U,
2200 5166U, 5197U, 5183U, 5513U, 7571U, 4062U, 7564U, 4043U,
2201 5389U, 4700U, 4588U, 2315U, 3430U, 3233U, 5404U, 4020U,
2202 5411U, 3821U, 5396U, 4012U, 3813U, 1078U, 3036U, 3028U,
2203 3020U, 6969U, 5079U, 6607U, 6730U, 7002U, 4811U, 2129U,
2204 1456U, 2508U, 2271U, 1652U, 1318U, 3416U, 7154U, 3505U,
2205 1268U, 6977U, 4761U, 4621U, 5421U, 4992U, 5008U, 7497U,
2206 2182U, 2520U, 6400U, 4496U, 2166U, 4537U, 4513U, 4525U,
2207 1631U, 3395U, 1607U, 3371U, 7307U, 3897U, 3616U, 3563U,
2208 3731U, 3669U, 1683U, 3438U, 1763U, 5258U, 5212U, 7341U,
2209 3931U, 7365U, 3955U, 7436U, 7443U, 2976U, 771U, 937U,
2210 3125U, 760U, 926U, 884U, 1050U, 825U, 991U, 7506U,
2211 2499U, 738U, 904U, 844U, 1010U, 787U, 953U, 8603U,
2212 8586U, 6520U, 1222U, 3877U, 2310U, 1818U, 1391U, 2603U,
2213 4661U, 3889U, 2994U, 160U, 82U, 1394U, 752U, 918U,
2214 867U, 1033U, 809U, 975U, 6409U, 4656U, 1853U, 2386U,
2215 699U, 4824U, 711U, 7490U, 1095U, 1183U, 1115U, 1203U,
2216 7578U, 7596U, 4395U, 4081U, 1943U, 7264U, 4669U, 1620U,
2217 6662U, 6751U, 2341U, 6759U, 8044U, 388U, 6884U, 8183U,
2218 8102U, 8194U, 8218U, 8229U, 3236U, 7110U, 3118U, 2492U,
2219 4893U, 4911U, 2237U, 2827U, 170U, 2743U, 65U, 2732U,
2220 34U, 3488U, 2722U, 22U, 2783U, 108U, 2758U, 47U,
2221 2704U, 0U, 2713U, 11U, 6767U, 7941U, 267U, 6776U,
2222 8020U, 358U, 6859U, 8067U, 417U, 8525U, 8060U, 408U,
2223 578U, 8288U, 8273U, 7772U, 186U, 7630U, 8633U, 2794U,
2224 121U, 8488U, 7990U, 324U, 2328U, 6683U, 6830U, 5082U,
2225 723U, 1228U, 8259U, 553U, 8142U, 490U, 7852U, 5770U,
2226 4879U, 666U, 7549U, 7292U, 1565U, 7539U, 7282U, 8088U,
2227 442U, 6426U, 1715U, 6244U, 1785U, 6256U, 6174U, 2371U,
2228 7034U, 6386U, 6901U, 6370U, 6717U, 6337U, 6839U, 6354U,
2229 6693U, 6320U, 5278U, 6309U, 6192U, 6225U, 2407U, 1355U,
2230 6143U, 6155U, 6205U, 2397U, 2858U, 6282U, 5234U, 6297U,
2231 5380U, 7869U, 208U, 8462U, 7964U, 294U, 2769U, 92U,
2232 8029U, 369U, 8052U, 398U, 7320U, 657U, 6905U, 6721U,
2233 3910U, 637U, 6843U, 6697U, 7220U, 8171U, 3384U, 7949U,
2234 277U, 8316U, 7684U, 7859U, 196U, 8560U, 1150U, 8205U,
2235 523U, 7701U, 8532U, 1134U, 8114U, 458U, 8573U, 8246U,
2236 538U, 8546U, 8128U, 474U, 2066U, 8332U, 8076U, 428U,
2237 7717U, 6893U, 6852U, 1603U, 2820U, 151U, 2361U, 6816U,
2238 2109U, 6786U, 6437U, 6869U, 2213U, 6801U, 7615U, 8618U,
2239 5851U, 4127U, 5872U, 4146U, 6038U, 4298U, 5934U, 4202U,
2240 5960U, 4226U, 6118U, 4372U, 6012U, 4274U, 6093U, 4349U,
2241 5986U, 4250U, 5914U, 4184U, 5808U, 4088U, 5830U, 4108U,
2242 6067U, 4325U, 5893U, 4165U, 5069U, 1243U, 681U, 1165U,
2243 8443U, 7922U, 7811U, 7658U, 7746U, 8422U, 7901U, 244U,
2244 8500U, 8002U, 338U, 8405U, 7884U, 225U, 8474U, 7976U,
2245 308U, 8157U, 507U, 2160U, 2366U, 627U, 6821U, 605U,
2246 6791U, 6672U, 646U, 6874U, 6706U, 616U, 6806U, 2105U,
2247 6433U, 8518U, 8037U, 379U, 569U, 2209U, 6652U, 6743U,
2248 3044U, 7224U, 4434U, 1739U, 5307U, 2149U, 1473U, 2948U,
2249 3460U, 1281U, 2963U, 3475U, 1297U, 3064U, 7244U, 2609U,
2250 2626U, 1403U, 8087U, 441U, 8375U, 7795U, 8360U, 7780U,
2251 8301U, 7643U, 8345U, 7731U, 8391U, 7838U, 2806U, 135U,
2252 6851U,
2253};
2254
2255static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
2256 II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 673, nullptr, 0);
2257}
2258
2259
2260} // namespace llvm
2261
2262#endif // GET_INSTRINFO_MC_DESC
2263
2264#ifdef GET_INSTRINFO_HEADER
2265#undef GET_INSTRINFO_HEADER
2266
2267namespace llvm {
2268
2269struct R600GenInstrInfo : public TargetInstrInfo {
2270 explicit R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2271 ~R600GenInstrInfo() override = default;
2272};
2273
2274} // namespace llvm
2275
2276namespace llvm::R600 {
2277
2278constexpr unsigned SUBOP_FRAMEri_ptr = 0;
2279constexpr unsigned SUBOP_FRAMEri_index = 1;
2280constexpr unsigned SUBOP_MEMrr_ptr = 0;
2281constexpr unsigned SUBOP_MEMrr_index = 1;
2282constexpr unsigned SUBOP_MEMxi_ptr = 0;
2283constexpr unsigned SUBOP_MEMxi_index = 1;
2284
2285} // namespace llvm::R600
2286
2287#endif // GET_INSTRINFO_HEADER
2288
2289#ifdef GET_INSTRINFO_HELPER_DECLS
2290#undef GET_INSTRINFO_HELPER_DECLS
2291
2292
2293#endif // GET_INSTRINFO_HELPER_DECLS
2294
2295#ifdef GET_INSTRINFO_HELPERS
2296#undef GET_INSTRINFO_HELPERS
2297
2298
2299#endif // GET_INSTRINFO_HELPERS
2300
2301#ifdef GET_INSTRINFO_CTOR_DTOR
2302#undef GET_INSTRINFO_CTOR_DTOR
2303
2304namespace llvm {
2305
2306extern const R600InstrTable R600Descs;
2307extern const unsigned R600InstrNameIndices[];
2308extern const char R600InstrNameData[];
2309R600GenInstrInfo::R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2310 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2311 InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 673);
2312}
2313
2314} // namespace llvm
2315
2316#endif // GET_INSTRINFO_CTOR_DTOR
2317
2318#ifdef GET_INSTRINFO_OPERAND_ENUM
2319#undef GET_INSTRINFO_OPERAND_ENUM
2320
2321namespace llvm::R600 {
2322
2323enum class OpName : uint8_t {
2324 dst = 0,
2325 src0 = 1,
2326 update_exec_mask_X = 2,
2327 update_pred_X = 3,
2328 write_X = 4,
2329 omod_X = 5,
2330 dst_rel_X = 6,
2331 clamp_X = 7,
2332 src0_X = 8,
2333 src0_neg_X = 9,
2334 src0_rel_X = 10,
2335 src0_abs_X = 11,
2336 src0_sel_X = 12,
2337 src1_X = 13,
2338 src1_neg_X = 14,
2339 src1_rel_X = 15,
2340 src1_abs_X = 16,
2341 src1_sel_X = 17,
2342 pred_sel_X = 18,
2343 update_exec_mask_Y = 19,
2344 update_pred_Y = 20,
2345 write_Y = 21,
2346 omod_Y = 22,
2347 dst_rel_Y = 23,
2348 clamp_Y = 24,
2349 src0_Y = 25,
2350 src0_neg_Y = 26,
2351 src0_rel_Y = 27,
2352 src0_abs_Y = 28,
2353 src0_sel_Y = 29,
2354 src1_Y = 30,
2355 src1_neg_Y = 31,
2356 src1_rel_Y = 32,
2357 src1_abs_Y = 33,
2358 src1_sel_Y = 34,
2359 pred_sel_Y = 35,
2360 update_exec_mask_Z = 36,
2361 update_pred_Z = 37,
2362 write_Z = 38,
2363 omod_Z = 39,
2364 dst_rel_Z = 40,
2365 clamp_Z = 41,
2366 src0_Z = 42,
2367 src0_neg_Z = 43,
2368 src0_rel_Z = 44,
2369 src0_abs_Z = 45,
2370 src0_sel_Z = 46,
2371 src1_Z = 47,
2372 src1_neg_Z = 48,
2373 src1_rel_Z = 49,
2374 src1_abs_Z = 50,
2375 src1_sel_Z = 51,
2376 pred_sel_Z = 52,
2377 update_exec_mask_W = 53,
2378 update_pred_W = 54,
2379 write_W = 55,
2380 omod_W = 56,
2381 dst_rel_W = 57,
2382 clamp_W = 58,
2383 src0_W = 59,
2384 src0_neg_W = 60,
2385 src0_rel_W = 61,
2386 src0_abs_W = 62,
2387 src0_sel_W = 63,
2388 src1_W = 64,
2389 src1_neg_W = 65,
2390 src1_rel_W = 66,
2391 src1_abs_W = 67,
2392 src1_sel_W = 68,
2393 pred_sel_W = 69,
2394 literal0 = 70,
2395 literal1 = 71,
2396 addr = 72,
2397 chan = 73,
2398 val = 74,
2399 update_exec_mask = 75,
2400 update_pred = 76,
2401 write = 77,
2402 omod = 78,
2403 dst_rel = 79,
2404 clamp = 80,
2405 src0_neg = 81,
2406 src0_rel = 82,
2407 src0_abs = 83,
2408 src0_sel = 84,
2409 src1 = 85,
2410 src1_neg = 86,
2411 src1_rel = 87,
2412 src1_abs = 88,
2413 src1_sel = 89,
2414 last = 90,
2415 pred_sel = 91,
2416 literal = 92,
2417 bank_swizzle = 93,
2418 src2 = 94,
2419 src2_neg = 95,
2420 src2_rel = 96,
2421 src2_sel = 97,
2422 ADDR = 98,
2423 KCACHE_BANK0 = 99,
2424 KCACHE_BANK1 = 100,
2425 KCACHE_MODE0 = 101,
2426 KCACHE_MODE1 = 102,
2427 KCACHE_ADDR0 = 103,
2428 KCACHE_ADDR1 = 104,
2429 COUNT = 105,
2430 Enabled = 106,
2431 NUM_OPERAND_NAMES = 107,
2432}; // enum class OpName
2433
2434LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name);
2435LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx);
2436
2437} // namespace llvm::R600
2438
2439#endif // GET_INSTRINFO_OPERAND_ENUM
2440
2441#ifdef GET_INSTRINFO_NAMED_OPS
2442#undef GET_INSTRINFO_NAMED_OPS
2443
2444namespace llvm::R600 {
2445
2446LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) {
2447 static constexpr uint8_t InstructionIndex[] = {
2448 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2450 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2451 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2455 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2466 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2468 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
2470 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2471 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2472 3, 4, 0, 0, 0, 0, 0, 5, 5, 5, 0, 5, 5, 5, 6, 7,
2473 7, 7, 5, 7, 6, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0,
2474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 7, 7,
2475 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 0, 0, 0,
2476 0, 6, 6, 6, 0, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 6,
2477 0, 6, 0, 0, 0, 5, 5, 6, 6, 5, 9, 10, 9, 10, 11, 9,
2478 12, 13, 9, 10, 9, 10, 9, 10, 9, 10, 9, 10, 11, 11, 9, 9,
2479 10, 11, 11, 9, 9, 10, 9, 10, 0, 6, 6, 6, 6, 6, 0, 0,
2480 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 5, 7,
2481 7, 7, 7, 7, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
2482 5, 5, 5, 5, 5, 5, 7, 7, 5, 6, 5, 0, 0, 0, 5, 5,
2483 5, 5, 5, 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2484 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2485 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6, 6,
2486 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5,
2487 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 5, 5, 5,
2488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2489 0, 6, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2490 5,
2491 };
2492 return InstructionIndex[Opcode];
2493}
2494LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) {
2495 assert(Name != OpName::NUM_OPERAND_NAMES);
2496 static constexpr int8_t OperandMap[][107] = {
2497 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2498 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2499 {0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2500 {0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2501 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2502 {0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2503 {0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2504 {0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2505 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
2506 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2507 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2508 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2509 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2510 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2511 };
2512 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2513 return OperandMap[InstrIdx][(unsigned)Name];
2514}
2515LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) {
2516 assert(Idx >= 0 && Idx < 71);
2517 static constexpr OpName OperandMap[][71] = {
2518 {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2519 {OpName::dst, OpName::src0, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2520 {OpName::dst, OpName::update_exec_mask_X, OpName::update_pred_X, OpName::write_X, OpName::omod_X, OpName::dst_rel_X, OpName::clamp_X, OpName::src0_X, OpName::src0_neg_X, OpName::src0_rel_X, OpName::src0_abs_X, OpName::src0_sel_X, OpName::src1_X, OpName::src1_neg_X, OpName::src1_rel_X, OpName::src1_abs_X, OpName::src1_sel_X, OpName::pred_sel_X, OpName::update_exec_mask_Y, OpName::update_pred_Y, OpName::write_Y, OpName::omod_Y, OpName::dst_rel_Y, OpName::clamp_Y, OpName::src0_Y, OpName::src0_neg_Y, OpName::src0_rel_Y, OpName::src0_abs_Y, OpName::src0_sel_Y, OpName::src1_Y, OpName::src1_neg_Y, OpName::src1_rel_Y, OpName::src1_abs_Y, OpName::src1_sel_Y, OpName::pred_sel_Y, OpName::update_exec_mask_Z, OpName::update_pred_Z, OpName::write_Z, OpName::omod_Z, OpName::dst_rel_Z, OpName::clamp_Z, OpName::src0_Z, OpName::src0_neg_Z, OpName::src0_rel_Z, OpName::src0_abs_Z, OpName::src0_sel_Z, OpName::src1_Z, OpName::src1_neg_Z, OpName::src1_rel_Z, OpName::src1_abs_Z, OpName::src1_sel_Z, OpName::pred_sel_Z, OpName::update_exec_mask_W, OpName::update_pred_W, OpName::write_W, OpName::omod_W, OpName::dst_rel_W, OpName::clamp_W, OpName::src0_W, OpName::src0_neg_W, OpName::src0_rel_W, OpName::src0_abs_W, OpName::src0_sel_W, OpName::src1_W, OpName::src1_neg_W, OpName::src1_rel_W, OpName::src1_abs_W, OpName::src1_sel_W, OpName::pred_sel_W, OpName::literal0, OpName::literal1, },
2521 {OpName::dst, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2522 {OpName::val, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2523 {OpName::dst, OpName::update_exec_mask, OpName::update_pred, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_abs, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2524 {OpName::dst, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2525 {OpName::dst, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_neg, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2526 {OpName::ADDR, OpName::KCACHE_BANK0, OpName::KCACHE_BANK1, OpName::KCACHE_MODE0, OpName::KCACHE_MODE1, OpName::KCACHE_ADDR0, OpName::KCACHE_ADDR1, OpName::COUNT, OpName::Enabled, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2527 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2528 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2529 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2530 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2531 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2532 };
2533 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2534 return OperandMap[InstrIdx][(unsigned)Idx];
2535}
2536
2537} // namespace llvm::R600
2538
2539#endif // GET_INSTRINFO_NAMED_OPS
2540
2541#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2542#undef GET_INSTRINFO_MC_HELPER_DECLS
2543
2544namespace llvm {
2545
2546class MCInst;
2547class FeatureBitset;
2548
2549namespace R600_MC {
2550
2551void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2552
2553} // namespace R600_MC
2554
2555} // namespace llvm
2556
2557#endif // GET_INSTRINFO_MC_HELPER_DECLS
2558
2559#ifdef GET_INSTRINFO_MC_HELPERS
2560#undef GET_INSTRINFO_MC_HELPERS
2561
2562namespace llvm::R600_MC {
2563
2564
2565} // namespace llvm::R600_MC
2566
2567#endif // GET_INSTRINFO_MC_HELPERS
2568
2569#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2570 defined(GET_AVAILABLE_OPCODE_CHECKER)
2571#define GET_COMPUTE_FEATURES
2572#endif
2573#ifdef GET_COMPUTE_FEATURES
2574#undef GET_COMPUTE_FEATURES
2575
2576namespace llvm::R600_MC {
2577
2578// Bits for subtarget features that participate in instruction matching.
2579enum SubtargetFeatureBits : uint8_t {
2580};
2581
2582inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2583 FeatureBitset Features;
2584 return Features;
2585}
2586
2587inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2588 enum : uint8_t {
2589 CEFBS_None,
2590 };
2591
2592 static constexpr FeatureBitset FeatureBitsets[] = {
2593 {}, // CEFBS_None
2594 };
2595 static constexpr uint8_t RequiredFeaturesRefs[] = {
2596 CEFBS_None, // PHI
2597 CEFBS_None, // INLINEASM
2598 CEFBS_None, // INLINEASM_BR
2599 CEFBS_None, // CFI_INSTRUCTION
2600 CEFBS_None, // EH_LABEL
2601 CEFBS_None, // GC_LABEL
2602 CEFBS_None, // ANNOTATION_LABEL
2603 CEFBS_None, // KILL
2604 CEFBS_None, // EXTRACT_SUBREG
2605 CEFBS_None, // INSERT_SUBREG
2606 CEFBS_None, // IMPLICIT_DEF
2607 CEFBS_None, // INIT_UNDEF
2608 CEFBS_None, // SUBREG_TO_REG
2609 CEFBS_None, // COPY_TO_REGCLASS
2610 CEFBS_None, // DBG_VALUE
2611 CEFBS_None, // DBG_VALUE_LIST
2612 CEFBS_None, // DBG_INSTR_REF
2613 CEFBS_None, // DBG_PHI
2614 CEFBS_None, // DBG_LABEL
2615 CEFBS_None, // REG_SEQUENCE
2616 CEFBS_None, // COPY
2617 CEFBS_None, // COPY_LANEMASK
2618 CEFBS_None, // BUNDLE
2619 CEFBS_None, // LIFETIME_START
2620 CEFBS_None, // LIFETIME_END
2621 CEFBS_None, // PSEUDO_PROBE
2622 CEFBS_None, // ARITH_FENCE
2623 CEFBS_None, // STACKMAP
2624 CEFBS_None, // FENTRY_CALL
2625 CEFBS_None, // PATCHPOINT
2626 CEFBS_None, // LOAD_STACK_GUARD
2627 CEFBS_None, // PREALLOCATED_SETUP
2628 CEFBS_None, // PREALLOCATED_ARG
2629 CEFBS_None, // STATEPOINT
2630 CEFBS_None, // LOCAL_ESCAPE
2631 CEFBS_None, // FAULTING_OP
2632 CEFBS_None, // PATCHABLE_OP
2633 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2634 CEFBS_None, // PATCHABLE_RET
2635 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2636 CEFBS_None, // PATCHABLE_TAIL_CALL
2637 CEFBS_None, // PATCHABLE_EVENT_CALL
2638 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2639 CEFBS_None, // ICALL_BRANCH_FUNNEL
2640 CEFBS_None, // FAKE_USE
2641 CEFBS_None, // MEMBARRIER
2642 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2643 CEFBS_None, // RELOC_NONE
2644 CEFBS_None, // CONVERGENCECTRL_ENTRY
2645 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2646 CEFBS_None, // CONVERGENCECTRL_LOOP
2647 CEFBS_None, // CONVERGENCECTRL_GLUE
2648 CEFBS_None, // G_ASSERT_SEXT
2649 CEFBS_None, // G_ASSERT_ZEXT
2650 CEFBS_None, // G_ASSERT_ALIGN
2651 CEFBS_None, // G_ADD
2652 CEFBS_None, // G_SUB
2653 CEFBS_None, // G_MUL
2654 CEFBS_None, // G_SDIV
2655 CEFBS_None, // G_UDIV
2656 CEFBS_None, // G_SREM
2657 CEFBS_None, // G_UREM
2658 CEFBS_None, // G_SDIVREM
2659 CEFBS_None, // G_UDIVREM
2660 CEFBS_None, // G_AND
2661 CEFBS_None, // G_OR
2662 CEFBS_None, // G_XOR
2663 CEFBS_None, // G_ABDS
2664 CEFBS_None, // G_ABDU
2665 CEFBS_None, // G_UAVGFLOOR
2666 CEFBS_None, // G_UAVGCEIL
2667 CEFBS_None, // G_SAVGFLOOR
2668 CEFBS_None, // G_SAVGCEIL
2669 CEFBS_None, // G_IMPLICIT_DEF
2670 CEFBS_None, // G_PHI
2671 CEFBS_None, // G_FRAME_INDEX
2672 CEFBS_None, // G_GLOBAL_VALUE
2673 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2674 CEFBS_None, // G_CONSTANT_POOL
2675 CEFBS_None, // G_EXTRACT
2676 CEFBS_None, // G_UNMERGE_VALUES
2677 CEFBS_None, // G_INSERT
2678 CEFBS_None, // G_MERGE_VALUES
2679 CEFBS_None, // G_BUILD_VECTOR
2680 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2681 CEFBS_None, // G_CONCAT_VECTORS
2682 CEFBS_None, // G_PTRTOINT
2683 CEFBS_None, // G_INTTOPTR
2684 CEFBS_None, // G_BITCAST
2685 CEFBS_None, // G_FREEZE
2686 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2687 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2688 CEFBS_None, // G_INTRINSIC_TRUNC
2689 CEFBS_None, // G_INTRINSIC_ROUND
2690 CEFBS_None, // G_INTRINSIC_LRINT
2691 CEFBS_None, // G_INTRINSIC_LLRINT
2692 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2693 CEFBS_None, // G_READCYCLECOUNTER
2694 CEFBS_None, // G_READSTEADYCOUNTER
2695 CEFBS_None, // G_LOAD
2696 CEFBS_None, // G_SEXTLOAD
2697 CEFBS_None, // G_ZEXTLOAD
2698 CEFBS_None, // G_FPEXTLOAD
2699 CEFBS_None, // G_INDEXED_LOAD
2700 CEFBS_None, // G_INDEXED_SEXTLOAD
2701 CEFBS_None, // G_INDEXED_ZEXTLOAD
2702 CEFBS_None, // G_STORE
2703 CEFBS_None, // G_FPTRUNCSTORE
2704 CEFBS_None, // G_INDEXED_STORE
2705 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2706 CEFBS_None, // G_ATOMIC_CMPXCHG
2707 CEFBS_None, // G_ATOMICRMW_XCHG
2708 CEFBS_None, // G_ATOMICRMW_ADD
2709 CEFBS_None, // G_ATOMICRMW_SUB
2710 CEFBS_None, // G_ATOMICRMW_AND
2711 CEFBS_None, // G_ATOMICRMW_NAND
2712 CEFBS_None, // G_ATOMICRMW_OR
2713 CEFBS_None, // G_ATOMICRMW_XOR
2714 CEFBS_None, // G_ATOMICRMW_MAX
2715 CEFBS_None, // G_ATOMICRMW_MIN
2716 CEFBS_None, // G_ATOMICRMW_UMAX
2717 CEFBS_None, // G_ATOMICRMW_UMIN
2718 CEFBS_None, // G_ATOMICRMW_FADD
2719 CEFBS_None, // G_ATOMICRMW_FSUB
2720 CEFBS_None, // G_ATOMICRMW_FMAX
2721 CEFBS_None, // G_ATOMICRMW_FMIN
2722 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2723 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2724 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2725 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2726 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2727 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2728 CEFBS_None, // G_ATOMICRMW_USUB_COND
2729 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2730 CEFBS_None, // G_FENCE
2731 CEFBS_None, // G_PREFETCH
2732 CEFBS_None, // G_BRCOND
2733 CEFBS_None, // G_BRINDIRECT
2734 CEFBS_None, // G_INVOKE_REGION_START
2735 CEFBS_None, // G_INTRINSIC
2736 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2737 CEFBS_None, // G_INTRINSIC_CONVERGENT
2738 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2739 CEFBS_None, // G_ANYEXT
2740 CEFBS_None, // G_TRUNC
2741 CEFBS_None, // G_TRUNC_SSAT_S
2742 CEFBS_None, // G_TRUNC_SSAT_U
2743 CEFBS_None, // G_TRUNC_USAT_U
2744 CEFBS_None, // G_CONSTANT
2745 CEFBS_None, // G_FCONSTANT
2746 CEFBS_None, // G_VASTART
2747 CEFBS_None, // G_VAARG
2748 CEFBS_None, // G_SEXT
2749 CEFBS_None, // G_SEXT_INREG
2750 CEFBS_None, // G_ZEXT
2751 CEFBS_None, // G_SHL
2752 CEFBS_None, // G_LSHR
2753 CEFBS_None, // G_ASHR
2754 CEFBS_None, // G_FSHL
2755 CEFBS_None, // G_FSHR
2756 CEFBS_None, // G_ROTR
2757 CEFBS_None, // G_ROTL
2758 CEFBS_None, // G_ICMP
2759 CEFBS_None, // G_FCMP
2760 CEFBS_None, // G_SCMP
2761 CEFBS_None, // G_UCMP
2762 CEFBS_None, // G_SELECT
2763 CEFBS_None, // G_UADDO
2764 CEFBS_None, // G_UADDE
2765 CEFBS_None, // G_USUBO
2766 CEFBS_None, // G_USUBE
2767 CEFBS_None, // G_SADDO
2768 CEFBS_None, // G_SADDE
2769 CEFBS_None, // G_SSUBO
2770 CEFBS_None, // G_SSUBE
2771 CEFBS_None, // G_UMULO
2772 CEFBS_None, // G_SMULO
2773 CEFBS_None, // G_UMULH
2774 CEFBS_None, // G_SMULH
2775 CEFBS_None, // G_UADDSAT
2776 CEFBS_None, // G_SADDSAT
2777 CEFBS_None, // G_USUBSAT
2778 CEFBS_None, // G_SSUBSAT
2779 CEFBS_None, // G_USHLSAT
2780 CEFBS_None, // G_SSHLSAT
2781 CEFBS_None, // G_SMULFIX
2782 CEFBS_None, // G_UMULFIX
2783 CEFBS_None, // G_SMULFIXSAT
2784 CEFBS_None, // G_UMULFIXSAT
2785 CEFBS_None, // G_SDIVFIX
2786 CEFBS_None, // G_UDIVFIX
2787 CEFBS_None, // G_SDIVFIXSAT
2788 CEFBS_None, // G_UDIVFIXSAT
2789 CEFBS_None, // G_FADD
2790 CEFBS_None, // G_FSUB
2791 CEFBS_None, // G_FMUL
2792 CEFBS_None, // G_FMA
2793 CEFBS_None, // G_FMAD
2794 CEFBS_None, // G_FDIV
2795 CEFBS_None, // G_FREM
2796 CEFBS_None, // G_FMODF
2797 CEFBS_None, // G_FPOW
2798 CEFBS_None, // G_FPOWI
2799 CEFBS_None, // G_FEXP
2800 CEFBS_None, // G_FEXP2
2801 CEFBS_None, // G_FEXP10
2802 CEFBS_None, // G_FLOG
2803 CEFBS_None, // G_FLOG2
2804 CEFBS_None, // G_FLOG10
2805 CEFBS_None, // G_FLDEXP
2806 CEFBS_None, // G_FFREXP
2807 CEFBS_None, // G_FNEG
2808 CEFBS_None, // G_FPEXT
2809 CEFBS_None, // G_FPTRUNC
2810 CEFBS_None, // G_FPTOSI
2811 CEFBS_None, // G_FPTOUI
2812 CEFBS_None, // G_SITOFP
2813 CEFBS_None, // G_UITOFP
2814 CEFBS_None, // G_FPTOSI_SAT
2815 CEFBS_None, // G_FPTOUI_SAT
2816 CEFBS_None, // G_FABS
2817 CEFBS_None, // G_FCOPYSIGN
2818 CEFBS_None, // G_IS_FPCLASS
2819 CEFBS_None, // G_FCANONICALIZE
2820 CEFBS_None, // G_FMINNUM
2821 CEFBS_None, // G_FMAXNUM
2822 CEFBS_None, // G_FMINNUM_IEEE
2823 CEFBS_None, // G_FMAXNUM_IEEE
2824 CEFBS_None, // G_FMINIMUM
2825 CEFBS_None, // G_FMAXIMUM
2826 CEFBS_None, // G_FMINIMUMNUM
2827 CEFBS_None, // G_FMAXIMUMNUM
2828 CEFBS_None, // G_GET_FPENV
2829 CEFBS_None, // G_SET_FPENV
2830 CEFBS_None, // G_RESET_FPENV
2831 CEFBS_None, // G_GET_FPMODE
2832 CEFBS_None, // G_SET_FPMODE
2833 CEFBS_None, // G_RESET_FPMODE
2834 CEFBS_None, // G_GET_ROUNDING
2835 CEFBS_None, // G_SET_ROUNDING
2836 CEFBS_None, // G_PTR_ADD
2837 CEFBS_None, // G_PTRMASK
2838 CEFBS_None, // G_SMIN
2839 CEFBS_None, // G_SMAX
2840 CEFBS_None, // G_UMIN
2841 CEFBS_None, // G_UMAX
2842 CEFBS_None, // G_ABS
2843 CEFBS_None, // G_LROUND
2844 CEFBS_None, // G_LLROUND
2845 CEFBS_None, // G_BR
2846 CEFBS_None, // G_BRJT
2847 CEFBS_None, // G_VSCALE
2848 CEFBS_None, // G_INSERT_SUBVECTOR
2849 CEFBS_None, // G_EXTRACT_SUBVECTOR
2850 CEFBS_None, // G_INSERT_VECTOR_ELT
2851 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2852 CEFBS_None, // G_SHUFFLE_VECTOR
2853 CEFBS_None, // G_SPLAT_VECTOR
2854 CEFBS_None, // G_STEP_VECTOR
2855 CEFBS_None, // G_VECTOR_COMPRESS
2856 CEFBS_None, // G_CTTZ
2857 CEFBS_None, // G_CTTZ_ZERO_POISON
2858 CEFBS_None, // G_CTLZ
2859 CEFBS_None, // G_CTLZ_ZERO_POISON
2860 CEFBS_None, // G_CTLS
2861 CEFBS_None, // G_CTPOP
2862 CEFBS_None, // G_BSWAP
2863 CEFBS_None, // G_BITREVERSE
2864 CEFBS_None, // G_CLMUL
2865 CEFBS_None, // G_FCEIL
2866 CEFBS_None, // G_FCOS
2867 CEFBS_None, // G_FSIN
2868 CEFBS_None, // G_FSINCOS
2869 CEFBS_None, // G_FTAN
2870 CEFBS_None, // G_FACOS
2871 CEFBS_None, // G_FASIN
2872 CEFBS_None, // G_FATAN
2873 CEFBS_None, // G_FATAN2
2874 CEFBS_None, // G_FCOSH
2875 CEFBS_None, // G_FSINH
2876 CEFBS_None, // G_FTANH
2877 CEFBS_None, // G_FSQRT
2878 CEFBS_None, // G_FFLOOR
2879 CEFBS_None, // G_FRINT
2880 CEFBS_None, // G_FNEARBYINT
2881 CEFBS_None, // G_ADDRSPACE_CAST
2882 CEFBS_None, // G_BLOCK_ADDR
2883 CEFBS_None, // G_JUMP_TABLE
2884 CEFBS_None, // G_DYN_STACKALLOC
2885 CEFBS_None, // G_STACKSAVE
2886 CEFBS_None, // G_STACKRESTORE
2887 CEFBS_None, // G_STRICT_FADD
2888 CEFBS_None, // G_STRICT_FSUB
2889 CEFBS_None, // G_STRICT_FMUL
2890 CEFBS_None, // G_STRICT_FDIV
2891 CEFBS_None, // G_STRICT_FREM
2892 CEFBS_None, // G_STRICT_FMA
2893 CEFBS_None, // G_STRICT_FSQRT
2894 CEFBS_None, // G_STRICT_FLDEXP
2895 CEFBS_None, // G_STRICT_FCMP
2896 CEFBS_None, // G_STRICT_FCMPS
2897 CEFBS_None, // G_READ_REGISTER
2898 CEFBS_None, // G_WRITE_REGISTER
2899 CEFBS_None, // G_MEMCPY
2900 CEFBS_None, // G_MEMCPY_INLINE
2901 CEFBS_None, // G_MEMMOVE
2902 CEFBS_None, // G_MEMSET
2903 CEFBS_None, // G_BZERO
2904 CEFBS_None, // G_MEMSET_INLINE
2905 CEFBS_None, // G_TRAP
2906 CEFBS_None, // G_DEBUGTRAP
2907 CEFBS_None, // G_UBSANTRAP
2908 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2909 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2910 CEFBS_None, // G_VECREDUCE_FADD
2911 CEFBS_None, // G_VECREDUCE_FMUL
2912 CEFBS_None, // G_VECREDUCE_FMAX
2913 CEFBS_None, // G_VECREDUCE_FMIN
2914 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2915 CEFBS_None, // G_VECREDUCE_FMINIMUM
2916 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2917 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2918 CEFBS_None, // G_VECREDUCE_ADD
2919 CEFBS_None, // G_VECREDUCE_MUL
2920 CEFBS_None, // G_VECREDUCE_AND
2921 CEFBS_None, // G_VECREDUCE_OR
2922 CEFBS_None, // G_VECREDUCE_XOR
2923 CEFBS_None, // G_VECREDUCE_SMAX
2924 CEFBS_None, // G_VECREDUCE_SMIN
2925 CEFBS_None, // G_VECREDUCE_UMAX
2926 CEFBS_None, // G_VECREDUCE_UMIN
2927 CEFBS_None, // G_SBFX
2928 CEFBS_None, // G_UBFX
2929 CEFBS_None, // BRANCH
2930 CEFBS_None, // BRANCH_COND_f32
2931 CEFBS_None, // BRANCH_COND_i32
2932 CEFBS_None, // BREAK
2933 CEFBS_None, // BREAKC_f32
2934 CEFBS_None, // BREAKC_i32
2935 CEFBS_None, // BREAK_LOGICALNZ_f32
2936 CEFBS_None, // BREAK_LOGICALNZ_i32
2937 CEFBS_None, // BREAK_LOGICALZ_f32
2938 CEFBS_None, // BREAK_LOGICALZ_i32
2939 CEFBS_None, // CONST_COPY
2940 CEFBS_None, // CONTINUE
2941 CEFBS_None, // CONTINUEC_f32
2942 CEFBS_None, // CONTINUEC_i32
2943 CEFBS_None, // CONTINUE_LOGICALNZ_f32
2944 CEFBS_None, // CONTINUE_LOGICALNZ_i32
2945 CEFBS_None, // CONTINUE_LOGICALZ_f32
2946 CEFBS_None, // CONTINUE_LOGICALZ_i32
2947 CEFBS_None, // CUBE_eg_pseudo
2948 CEFBS_None, // CUBE_r600_pseudo
2949 CEFBS_None, // DEFAULT
2950 CEFBS_None, // DOT_4
2951 CEFBS_None, // DUMMY_CHAIN
2952 CEFBS_None, // ELSE
2953 CEFBS_None, // END
2954 CEFBS_None, // ENDFUNC
2955 CEFBS_None, // ENDIF
2956 CEFBS_None, // ENDLOOP
2957 CEFBS_None, // ENDMAIN
2958 CEFBS_None, // ENDSWITCH
2959 CEFBS_None, // FABS_R600
2960 CEFBS_None, // FNEG_R600
2961 CEFBS_None, // FUNC
2962 CEFBS_None, // IFC_f32
2963 CEFBS_None, // IFC_i32
2964 CEFBS_None, // IF_LOGICALNZ_f32
2965 CEFBS_None, // IF_LOGICALNZ_i32
2966 CEFBS_None, // IF_LOGICALZ_f32
2967 CEFBS_None, // IF_LOGICALZ_i32
2968 CEFBS_None, // IF_PREDICATE_SET
2969 CEFBS_None, // JUMP
2970 CEFBS_None, // JUMP_COND
2971 CEFBS_None, // MASK_WRITE
2972 CEFBS_None, // MOV_IMM_F32
2973 CEFBS_None, // MOV_IMM_GLOBAL_ADDR
2974 CEFBS_None, // MOV_IMM_I32
2975 CEFBS_None, // PRED_X
2976 CEFBS_None, // R600_EXTRACT_ELT_V2
2977 CEFBS_None, // R600_EXTRACT_ELT_V4
2978 CEFBS_None, // R600_INSERT_ELT_V2
2979 CEFBS_None, // R600_INSERT_ELT_V4
2980 CEFBS_None, // R600_RegisterLoad
2981 CEFBS_None, // R600_RegisterStore
2982 CEFBS_None, // RETDYN
2983 CEFBS_None, // RETURN
2984 CEFBS_None, // TXD
2985 CEFBS_None, // TXD_SHADOW
2986 CEFBS_None, // WHILELOOP
2987 CEFBS_None, // ADD
2988 CEFBS_None, // ADDC_UINT
2989 CEFBS_None, // ADD_INT
2990 CEFBS_None, // ALU_CLAUSE
2991 CEFBS_None, // AND_INT
2992 CEFBS_None, // ASHR_eg
2993 CEFBS_None, // ASHR_r600
2994 CEFBS_None, // BCNT_INT
2995 CEFBS_None, // BFE_INT_eg
2996 CEFBS_None, // BFE_UINT_eg
2997 CEFBS_None, // BFI_INT_eg
2998 CEFBS_None, // BFM_INT_eg
2999 CEFBS_None, // BIT_ALIGN_INT_eg
3000 CEFBS_None, // CEIL
3001 CEFBS_None, // CF_ALU
3002 CEFBS_None, // CF_ALU_BREAK
3003 CEFBS_None, // CF_ALU_CONTINUE
3004 CEFBS_None, // CF_ALU_ELSE_AFTER
3005 CEFBS_None, // CF_ALU_POP_AFTER
3006 CEFBS_None, // CF_ALU_PUSH_BEFORE
3007 CEFBS_None, // CF_CALL_FS_EG
3008 CEFBS_None, // CF_CALL_FS_R600
3009 CEFBS_None, // CF_CONTINUE_EG
3010 CEFBS_None, // CF_CONTINUE_R600
3011 CEFBS_None, // CF_ELSE_EG
3012 CEFBS_None, // CF_ELSE_R600
3013 CEFBS_None, // CF_END_CM
3014 CEFBS_None, // CF_END_EG
3015 CEFBS_None, // CF_END_R600
3016 CEFBS_None, // CF_JUMP_EG
3017 CEFBS_None, // CF_JUMP_R600
3018 CEFBS_None, // CF_PUSH_EG
3019 CEFBS_None, // CF_PUSH_ELSE_R600
3020 CEFBS_None, // CF_TC_EG
3021 CEFBS_None, // CF_TC_R600
3022 CEFBS_None, // CF_VC_EG
3023 CEFBS_None, // CF_VC_R600
3024 CEFBS_None, // CNDE_INT
3025 CEFBS_None, // CNDE_eg
3026 CEFBS_None, // CNDE_r600
3027 CEFBS_None, // CNDGE_INT
3028 CEFBS_None, // CNDGE_eg
3029 CEFBS_None, // CNDGE_r600
3030 CEFBS_None, // CNDGT_INT
3031 CEFBS_None, // CNDGT_eg
3032 CEFBS_None, // CNDGT_r600
3033 CEFBS_None, // COS_cm
3034 CEFBS_None, // COS_eg
3035 CEFBS_None, // COS_r600
3036 CEFBS_None, // COS_r700
3037 CEFBS_None, // CUBE_eg_real
3038 CEFBS_None, // CUBE_r600_real
3039 CEFBS_None, // DOT4_eg
3040 CEFBS_None, // DOT4_r600
3041 CEFBS_None, // EG_ExportBuf
3042 CEFBS_None, // EG_ExportSwz
3043 CEFBS_None, // END_LOOP_EG
3044 CEFBS_None, // END_LOOP_R600
3045 CEFBS_None, // EXP_IEEE_cm
3046 CEFBS_None, // EXP_IEEE_eg
3047 CEFBS_None, // EXP_IEEE_r600
3048 CEFBS_None, // FETCH_CLAUSE
3049 CEFBS_None, // FFBH_UINT
3050 CEFBS_None, // FFBL_INT
3051 CEFBS_None, // FLOOR
3052 CEFBS_None, // FLT16_TO_FLT32
3053 CEFBS_None, // FLT32_TO_FLT16
3054 CEFBS_None, // FLT_TO_INT_eg
3055 CEFBS_None, // FLT_TO_INT_r600
3056 CEFBS_None, // FLT_TO_UINT_eg
3057 CEFBS_None, // FLT_TO_UINT_r600
3058 CEFBS_None, // FMA_eg
3059 CEFBS_None, // FRACT
3060 CEFBS_None, // GROUP_BARRIER
3061 CEFBS_None, // INTERP_LOAD_P0
3062 CEFBS_None, // INTERP_PAIR_XY
3063 CEFBS_None, // INTERP_PAIR_ZW
3064 CEFBS_None, // INTERP_VEC_LOAD
3065 CEFBS_None, // INTERP_XY
3066 CEFBS_None, // INTERP_ZW
3067 CEFBS_None, // INT_TO_FLT_eg
3068 CEFBS_None, // INT_TO_FLT_r600
3069 CEFBS_None, // KILLGT
3070 CEFBS_None, // LDS_ADD
3071 CEFBS_None, // LDS_ADD_RET
3072 CEFBS_None, // LDS_AND
3073 CEFBS_None, // LDS_AND_RET
3074 CEFBS_None, // LDS_BYTE_READ_RET
3075 CEFBS_None, // LDS_BYTE_WRITE
3076 CEFBS_None, // LDS_CMPST
3077 CEFBS_None, // LDS_CMPST_RET
3078 CEFBS_None, // LDS_MAX_INT
3079 CEFBS_None, // LDS_MAX_INT_RET
3080 CEFBS_None, // LDS_MAX_UINT
3081 CEFBS_None, // LDS_MAX_UINT_RET
3082 CEFBS_None, // LDS_MIN_INT
3083 CEFBS_None, // LDS_MIN_INT_RET
3084 CEFBS_None, // LDS_MIN_UINT
3085 CEFBS_None, // LDS_MIN_UINT_RET
3086 CEFBS_None, // LDS_OR
3087 CEFBS_None, // LDS_OR_RET
3088 CEFBS_None, // LDS_READ_RET
3089 CEFBS_None, // LDS_SHORT_READ_RET
3090 CEFBS_None, // LDS_SHORT_WRITE
3091 CEFBS_None, // LDS_SUB
3092 CEFBS_None, // LDS_SUB_RET
3093 CEFBS_None, // LDS_UBYTE_READ_RET
3094 CEFBS_None, // LDS_USHORT_READ_RET
3095 CEFBS_None, // LDS_WRITE
3096 CEFBS_None, // LDS_WRXCHG
3097 CEFBS_None, // LDS_WRXCHG_RET
3098 CEFBS_None, // LDS_XOR
3099 CEFBS_None, // LDS_XOR_RET
3100 CEFBS_None, // LITERALS
3101 CEFBS_None, // LOG_CLAMPED_eg
3102 CEFBS_None, // LOG_CLAMPED_r600
3103 CEFBS_None, // LOG_IEEE_cm
3104 CEFBS_None, // LOG_IEEE_eg
3105 CEFBS_None, // LOG_IEEE_r600
3106 CEFBS_None, // LOOP_BREAK_EG
3107 CEFBS_None, // LOOP_BREAK_R600
3108 CEFBS_None, // LSHL_eg
3109 CEFBS_None, // LSHL_r600
3110 CEFBS_None, // LSHR_eg
3111 CEFBS_None, // LSHR_r600
3112 CEFBS_None, // MAX
3113 CEFBS_None, // MAX_DX10
3114 CEFBS_None, // MAX_INT
3115 CEFBS_None, // MAX_UINT
3116 CEFBS_None, // MIN
3117 CEFBS_None, // MIN_DX10
3118 CEFBS_None, // MIN_INT
3119 CEFBS_None, // MIN_UINT
3120 CEFBS_None, // MOV
3121 CEFBS_None, // MOVA_INT_eg
3122 CEFBS_None, // MUL
3123 CEFBS_None, // MULADD_IEEE_eg
3124 CEFBS_None, // MULADD_IEEE_r600
3125 CEFBS_None, // MULADD_INT24_cm
3126 CEFBS_None, // MULADD_UINT24_eg
3127 CEFBS_None, // MULADD_eg
3128 CEFBS_None, // MULADD_r600
3129 CEFBS_None, // MULHI_INT_cm
3130 CEFBS_None, // MULHI_INT_cm24
3131 CEFBS_None, // MULHI_INT_eg
3132 CEFBS_None, // MULHI_INT_r600
3133 CEFBS_None, // MULHI_UINT24_eg
3134 CEFBS_None, // MULHI_UINT_cm
3135 CEFBS_None, // MULHI_UINT_cm24
3136 CEFBS_None, // MULHI_UINT_eg
3137 CEFBS_None, // MULHI_UINT_r600
3138 CEFBS_None, // MULLO_INT_cm
3139 CEFBS_None, // MULLO_INT_eg
3140 CEFBS_None, // MULLO_INT_r600
3141 CEFBS_None, // MULLO_UINT_cm
3142 CEFBS_None, // MULLO_UINT_eg
3143 CEFBS_None, // MULLO_UINT_r600
3144 CEFBS_None, // MUL_IEEE
3145 CEFBS_None, // MUL_INT24_cm
3146 CEFBS_None, // MUL_LIT_eg
3147 CEFBS_None, // MUL_LIT_r600
3148 CEFBS_None, // MUL_UINT24_eg
3149 CEFBS_None, // NOT_INT
3150 CEFBS_None, // OR_INT
3151 CEFBS_None, // PAD
3152 CEFBS_None, // POP_EG
3153 CEFBS_None, // POP_R600
3154 CEFBS_None, // PRED_SETE
3155 CEFBS_None, // PRED_SETE_INT
3156 CEFBS_None, // PRED_SETGE
3157 CEFBS_None, // PRED_SETGE_INT
3158 CEFBS_None, // PRED_SETGT
3159 CEFBS_None, // PRED_SETGT_INT
3160 CEFBS_None, // PRED_SETNE
3161 CEFBS_None, // PRED_SETNE_INT
3162 CEFBS_None, // R600_ExportBuf
3163 CEFBS_None, // R600_ExportSwz
3164 CEFBS_None, // RAT_ATOMIC_ADD_NORET
3165 CEFBS_None, // RAT_ATOMIC_ADD_RTN
3166 CEFBS_None, // RAT_ATOMIC_AND_NORET
3167 CEFBS_None, // RAT_ATOMIC_AND_RTN
3168 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET
3169 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN
3170 CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET
3171 CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN
3172 CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET
3173 CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN
3174 CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET
3175 CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN
3176 CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET
3177 CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN
3178 CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET
3179 CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN
3180 CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET
3181 CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN
3182 CEFBS_None, // RAT_ATOMIC_OR_NORET
3183 CEFBS_None, // RAT_ATOMIC_OR_RTN
3184 CEFBS_None, // RAT_ATOMIC_RSUB_NORET
3185 CEFBS_None, // RAT_ATOMIC_RSUB_RTN
3186 CEFBS_None, // RAT_ATOMIC_SUB_NORET
3187 CEFBS_None, // RAT_ATOMIC_SUB_RTN
3188 CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET
3189 CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN
3190 CEFBS_None, // RAT_ATOMIC_XOR_NORET
3191 CEFBS_None, // RAT_ATOMIC_XOR_RTN
3192 CEFBS_None, // RAT_MSKOR
3193 CEFBS_None, // RAT_STORE_DWORD128
3194 CEFBS_None, // RAT_STORE_DWORD32
3195 CEFBS_None, // RAT_STORE_DWORD64
3196 CEFBS_None, // RAT_STORE_TYPED_cm
3197 CEFBS_None, // RAT_STORE_TYPED_eg
3198 CEFBS_None, // RAT_WRITE_CACHELESS_128_eg
3199 CEFBS_None, // RAT_WRITE_CACHELESS_32_eg
3200 CEFBS_None, // RAT_WRITE_CACHELESS_64_eg
3201 CEFBS_None, // RECIPSQRT_CLAMPED_cm
3202 CEFBS_None, // RECIPSQRT_CLAMPED_eg
3203 CEFBS_None, // RECIPSQRT_CLAMPED_r600
3204 CEFBS_None, // RECIPSQRT_IEEE_cm
3205 CEFBS_None, // RECIPSQRT_IEEE_eg
3206 CEFBS_None, // RECIPSQRT_IEEE_r600
3207 CEFBS_None, // RECIP_CLAMPED_cm
3208 CEFBS_None, // RECIP_CLAMPED_eg
3209 CEFBS_None, // RECIP_CLAMPED_r600
3210 CEFBS_None, // RECIP_IEEE_cm
3211 CEFBS_None, // RECIP_IEEE_eg
3212 CEFBS_None, // RECIP_IEEE_r600
3213 CEFBS_None, // RECIP_UINT_eg
3214 CEFBS_None, // RECIP_UINT_r600
3215 CEFBS_None, // RNDNE
3216 CEFBS_None, // SETE
3217 CEFBS_None, // SETE_DX10
3218 CEFBS_None, // SETE_INT
3219 CEFBS_None, // SETGE_DX10
3220 CEFBS_None, // SETGE_INT
3221 CEFBS_None, // SETGE_UINT
3222 CEFBS_None, // SETGT_DX10
3223 CEFBS_None, // SETGT_INT
3224 CEFBS_None, // SETGT_UINT
3225 CEFBS_None, // SETNE_DX10
3226 CEFBS_None, // SETNE_INT
3227 CEFBS_None, // SGE
3228 CEFBS_None, // SGT
3229 CEFBS_None, // SIN_cm
3230 CEFBS_None, // SIN_eg
3231 CEFBS_None, // SIN_r600
3232 CEFBS_None, // SIN_r700
3233 CEFBS_None, // SNE
3234 CEFBS_None, // SUBB_UINT
3235 CEFBS_None, // SUB_INT
3236 CEFBS_None, // TEX_GET_GRADIENTS_H
3237 CEFBS_None, // TEX_GET_GRADIENTS_V
3238 CEFBS_None, // TEX_GET_TEXTURE_RESINFO
3239 CEFBS_None, // TEX_LD
3240 CEFBS_None, // TEX_LDPTR
3241 CEFBS_None, // TEX_SAMPLE
3242 CEFBS_None, // TEX_SAMPLE_C
3243 CEFBS_None, // TEX_SAMPLE_C_G
3244 CEFBS_None, // TEX_SAMPLE_C_L
3245 CEFBS_None, // TEX_SAMPLE_C_LB
3246 CEFBS_None, // TEX_SAMPLE_G
3247 CEFBS_None, // TEX_SAMPLE_L
3248 CEFBS_None, // TEX_SAMPLE_LB
3249 CEFBS_None, // TEX_SET_GRADIENTS_H
3250 CEFBS_None, // TEX_SET_GRADIENTS_V
3251 CEFBS_None, // TEX_VTX_CONSTBUF
3252 CEFBS_None, // TEX_VTX_TEXBUF
3253 CEFBS_None, // TRUNC
3254 CEFBS_None, // UINT_TO_FLT_eg
3255 CEFBS_None, // UINT_TO_FLT_r600
3256 CEFBS_None, // VTX_READ_128_cm
3257 CEFBS_None, // VTX_READ_128_eg
3258 CEFBS_None, // VTX_READ_16_cm
3259 CEFBS_None, // VTX_READ_16_eg
3260 CEFBS_None, // VTX_READ_32_cm
3261 CEFBS_None, // VTX_READ_32_eg
3262 CEFBS_None, // VTX_READ_64_cm
3263 CEFBS_None, // VTX_READ_64_eg
3264 CEFBS_None, // VTX_READ_8_cm
3265 CEFBS_None, // VTX_READ_8_eg
3266 CEFBS_None, // WHILE_LOOP_EG
3267 CEFBS_None, // WHILE_LOOP_R600
3268 CEFBS_None, // XOR_INT
3269 };
3270
3271 assert(Opcode < 673);
3272 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3273}
3274
3275
3276} // namespace llvm::R600_MC
3277
3278#endif // GET_COMPUTE_FEATURES
3279
3280#ifdef GET_AVAILABLE_OPCODE_CHECKER
3281#undef GET_AVAILABLE_OPCODE_CHECKER
3282
3283namespace llvm::R600_MC {
3284
3285bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3286 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3287 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3288 FeatureBitset MissingFeatures =
3289 (AvailableFeatures & RequiredFeatures) ^
3290 RequiredFeatures;
3291 return !MissingFeatures.any();
3292}
3293
3294} // namespace llvm::R600_MC
3295
3296#endif // GET_AVAILABLE_OPCODE_CHECKER
3297
3298#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3299#undef ENABLE_INSTR_PREDICATE_VERIFIER
3300
3301#include <sstream>
3302
3303namespace llvm::R600_MC {
3304
3305#ifndef NDEBUG
3306static const char *SubtargetFeatureNames[] = {
3307 nullptr
3308};
3309
3310#endif // NDEBUG
3311
3312void verifyInstructionPredicates(
3313 unsigned Opcode, const FeatureBitset &Features) {
3314#ifndef NDEBUG
3315 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3316 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3317 FeatureBitset MissingFeatures =
3318 (AvailableFeatures & RequiredFeatures) ^
3319 RequiredFeatures;
3320 if (MissingFeatures.any()) {
3321 std::ostringstream Msg;
3322 Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
3323 << " instruction but the ";
3324 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3325 if (MissingFeatures.test(i))
3326 Msg << SubtargetFeatureNames[i] << " ";
3327 Msg << "predicate(s) are not met";
3328 report_fatal_error(Msg.str().c_str());
3329 }
3330#endif // NDEBUG
3331}
3332
3333} // namespace llvm::R600_MC
3334
3335#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3336
3337#ifdef GET_INSTRMAP_INFO
3338#undef GET_INSTRMAP_INFO
3339
3340namespace llvm::R600 {
3341
3342enum usesCustomInserter {
3343 usesCustomInserter_0
3344};
3345
3346// getLDSNoRetOp
3347LLVM_READONLY
3348int32_t getLDSNoRetOp(uint32_t Opcode) {
3349 using namespace R600;
3350 static constexpr uint32_t Table[][2] = {
3351 { LDS_ADD_RET, LDS_ADD },
3352 { LDS_AND_RET, LDS_AND },
3353 { LDS_MAX_INT_RET, LDS_MAX_INT },
3354 { LDS_MAX_UINT_RET, LDS_MAX_UINT },
3355 { LDS_MIN_INT_RET, LDS_MIN_INT },
3356 { LDS_MIN_UINT_RET, LDS_MIN_UINT },
3357 { LDS_OR_RET, LDS_OR },
3358 { LDS_SUB_RET, LDS_SUB },
3359 { LDS_WRXCHG_RET, LDS_WRXCHG },
3360 { LDS_XOR_RET, LDS_XOR },
3361 }; // End of Table
3362
3363 unsigned mid;
3364 unsigned start = 0;
3365 unsigned end = 10;
3366 while (start < end) {
3367 mid = start + (end - start) / 2;
3368 if (Opcode == Table[mid][0])
3369 break;
3370 if (Opcode < Table[mid][0])
3371 end = mid;
3372 else
3373 start = mid + 1;
3374 }
3375 if (start == end)
3376 return -1; // Instruction doesn't exist in this table.
3377
3378 return Table[mid][1];
3379}
3380
3381
3382} // namespace llvm::R600
3383
3384#endif // GET_INSTRMAP_INFO
3385
3386