1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::R600 {
13
14 enum {
15 PHI = 0, // Target.td:1200
16 INLINEASM = 1, // Target.td:1206
17 INLINEASM_BR = 2, // Target.td:1212
18 CFI_INSTRUCTION = 3, // Target.td:1221
19 EH_LABEL = 4, // Target.td:1230
20 GC_LABEL = 5, // Target.td:1239
21 ANNOTATION_LABEL = 6, // Target.td:1248
22 KILL = 7, // Target.td:1256
23 EXTRACT_SUBREG = 8, // Target.td:1263
24 INSERT_SUBREG = 9, // Target.td:1269
25 IMPLICIT_DEF = 10, // Target.td:1276
26 INIT_UNDEF = 11, // Target.td:1285
27 SUBREG_TO_REG = 12, // Target.td:1292
28 COPY_TO_REGCLASS = 13, // Target.td:1298
29 DBG_VALUE = 14, // Target.td:1305
30 DBG_VALUE_LIST = 15, // Target.td:1312
31 DBG_INSTR_REF = 16, // Target.td:1319
32 DBG_PHI = 17, // Target.td:1326
33 DBG_LABEL = 18, // Target.td:1333
34 REG_SEQUENCE = 19, // Target.td:1340
35 COPY = 20, // Target.td:1347
36 COPY_LANEMASK = 21, // Target.td:1355
37 BUNDLE = 22, // Target.td:1362
38 LIFETIME_START = 23, // Target.td:1368
39 LIFETIME_END = 24, // Target.td:1375
40 PSEUDO_PROBE = 25, // Target.td:1382
41 ARITH_FENCE = 26, // Target.td:1389
42 STACKMAP = 27, // Target.td:1398
43 FENTRY_CALL = 28, // Target.td:1533
44 PATCHPOINT = 29, // Target.td:1406
45 LOAD_STACK_GUARD = 30, // Target.td:1424
46 PREALLOCATED_SETUP = 31, // Target.td:1432
47 PREALLOCATED_ARG = 32, // Target.td:1438
48 STATEPOINT = 33, // Target.td:1415
49 LOCAL_ESCAPE = 34, // Target.td:1444
50 FAULTING_OP = 35, // Target.td:1453
51 PATCHABLE_OP = 36, // Target.td:1473
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1481
53 PATCHABLE_RET = 38, // Target.td:1488
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1497
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1505
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1513
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1523
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1543
59 FAKE_USE = 44, // Target.td:1463
60 MEMBARRIER = 45, // Target.td:1549
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1557
62 RELOC_NONE = 47, // Target.td:1565
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1576
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1572
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1580
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1584
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1472
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484
96 G_INSERT = 81, // GenericOpcodes.td:1492
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1502
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448
145 G_FENCE = 130, // GenericOpcodes.td:1450
146 G_PREFETCH = 131, // GenericOpcodes.td:1457
147 G_BRCOND = 132, // GenericOpcodes.td:1592
148 G_BRINDIRECT = 133, // GenericOpcodes.td:1601
149 G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624
150 G_INTRINSIC = 135, // GenericOpcodes.td:1544
151 G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551
152 G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560
153 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568
154 G_ANYEXT = 139, // GenericOpcodes.td:44
155 G_TRUNC = 140, // GenericOpcodes.td:83
156 G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90
157 G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97
158 G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104
159 G_CONSTANT = 144, // GenericOpcodes.td:165
160 G_FCONSTANT = 145, // GenericOpcodes.td:172
161 G_VASTART = 146, // GenericOpcodes.td:178
162 G_VAARG = 147, // GenericOpcodes.td:185
163 G_SEXT = 148, // GenericOpcodes.td:52
164 G_SEXT_INREG = 149, // GenericOpcodes.td:66
165 G_ZEXT = 150, // GenericOpcodes.td:74
166 G_SHL = 151, // GenericOpcodes.td:396
167 G_LSHR = 152, // GenericOpcodes.td:403
168 G_ASHR = 153, // GenericOpcodes.td:410
169 G_FSHL = 154, // GenericOpcodes.td:462
170 G_FSHR = 155, // GenericOpcodes.td:470
171 G_ROTR = 156, // GenericOpcodes.td:477
172 G_ROTL = 157, // GenericOpcodes.td:484
173 G_ICMP = 158, // GenericOpcodes.td:491
174 G_FCMP = 159, // GenericOpcodes.td:498
175 G_SCMP = 160, // GenericOpcodes.td:505
176 G_UCMP = 161, // GenericOpcodes.td:512
177 G_SELECT = 162, // GenericOpcodes.td:519
178 G_UADDO = 163, // GenericOpcodes.td:584
179 G_UADDE = 164, // GenericOpcodes.td:592
180 G_USUBO = 165, // GenericOpcodes.td:614
181 G_USUBE = 166, // GenericOpcodes.td:620
182 G_SADDO = 167, // GenericOpcodes.td:599
183 G_SADDE = 168, // GenericOpcodes.td:607
184 G_SSUBO = 169, // GenericOpcodes.td:627
185 G_SSUBE = 170, // GenericOpcodes.td:634
186 G_UMULO = 171, // GenericOpcodes.td:641
187 G_SMULO = 172, // GenericOpcodes.td:649
188 G_UMULH = 173, // GenericOpcodes.td:658
189 G_SMULH = 174, // GenericOpcodes.td:667
190 G_UADDSAT = 175, // GenericOpcodes.td:679
191 G_SADDSAT = 176, // GenericOpcodes.td:687
192 G_USUBSAT = 177, // GenericOpcodes.td:695
193 G_SSUBSAT = 178, // GenericOpcodes.td:703
194 G_USHLSAT = 179, // GenericOpcodes.td:711
195 G_SSHLSAT = 180, // GenericOpcodes.td:719
196 G_SMULFIX = 181, // GenericOpcodes.td:731
197 G_UMULFIX = 182, // GenericOpcodes.td:738
198 G_SMULFIXSAT = 183, // GenericOpcodes.td:748
199 G_UMULFIXSAT = 184, // GenericOpcodes.td:755
200 G_SDIVFIX = 185, // GenericOpcodes.td:766
201 G_UDIVFIX = 186, // GenericOpcodes.td:773
202 G_SDIVFIXSAT = 187, // GenericOpcodes.td:783
203 G_UDIVFIXSAT = 188, // GenericOpcodes.td:790
204 G_FADD = 189, // GenericOpcodes.td:963
205 G_FSUB = 190, // GenericOpcodes.td:971
206 G_FMUL = 191, // GenericOpcodes.td:979
207 G_FMA = 192, // GenericOpcodes.td:988
208 G_FMAD = 193, // GenericOpcodes.td:997
209 G_FDIV = 194, // GenericOpcodes.td:1005
210 G_FREM = 195, // GenericOpcodes.td:1012
211 G_FMODF = 196, // GenericOpcodes.td:1019
212 G_FPOW = 197, // GenericOpcodes.td:1026
213 G_FPOWI = 198, // GenericOpcodes.td:1033
214 G_FEXP = 199, // GenericOpcodes.td:1040
215 G_FEXP2 = 200, // GenericOpcodes.td:1047
216 G_FEXP10 = 201, // GenericOpcodes.td:1054
217 G_FLOG = 202, // GenericOpcodes.td:1061
218 G_FLOG2 = 203, // GenericOpcodes.td:1068
219 G_FLOG10 = 204, // GenericOpcodes.td:1075
220 G_FLDEXP = 205, // GenericOpcodes.td:1082
221 G_FFREXP = 206, // GenericOpcodes.td:1089
222 G_FNEG = 207, // GenericOpcodes.td:801
223 G_FPEXT = 208, // GenericOpcodes.td:807
224 G_FPTRUNC = 209, // GenericOpcodes.td:813
225 G_FPTOSI = 210, // GenericOpcodes.td:819
226 G_FPTOUI = 211, // GenericOpcodes.td:825
227 G_SITOFP = 212, // GenericOpcodes.td:831
228 G_UITOFP = 213, // GenericOpcodes.td:837
229 G_FPTOSI_SAT = 214, // GenericOpcodes.td:843
230 G_FPTOUI_SAT = 215, // GenericOpcodes.td:849
231 G_FABS = 216, // GenericOpcodes.td:855
232 G_FCOPYSIGN = 217, // GenericOpcodes.td:861
233 G_IS_FPCLASS = 218, // GenericOpcodes.td:874
234 G_FCANONICALIZE = 219, // GenericOpcodes.td:867
235 G_FMINNUM = 220, // GenericOpcodes.td:887
236 G_FMAXNUM = 221, // GenericOpcodes.td:894
237 G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912
238 G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919
239 G_FMINIMUM = 224, // GenericOpcodes.td:929
240 G_FMAXIMUM = 225, // GenericOpcodes.td:936
241 G_FMINIMUMNUM = 226, // GenericOpcodes.td:944
242 G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951
243 G_GET_FPENV = 228, // GenericOpcodes.td:1219
244 G_SET_FPENV = 229, // GenericOpcodes.td:1226
245 G_RESET_FPENV = 230, // GenericOpcodes.td:1233
246 G_GET_FPMODE = 231, // GenericOpcodes.td:1240
247 G_SET_FPMODE = 232, // GenericOpcodes.td:1247
248 G_RESET_FPMODE = 233, // GenericOpcodes.td:1254
249 G_GET_ROUNDING = 234, // GenericOpcodes.td:1311
250 G_SET_ROUNDING = 235, // GenericOpcodes.td:1317
251 G_PTR_ADD = 236, // GenericOpcodes.td:526
252 G_PTRMASK = 237, // GenericOpcodes.td:534
253 G_SMIN = 238, // GenericOpcodes.td:541
254 G_SMAX = 239, // GenericOpcodes.td:549
255 G_UMIN = 240, // GenericOpcodes.td:557
256 G_UMAX = 241, // GenericOpcodes.td:565
257 G_ABS = 242, // GenericOpcodes.td:573
258 G_LROUND = 243, // GenericOpcodes.td:283
259 G_LLROUND = 244, // GenericOpcodes.td:289
260 G_BR = 245, // GenericOpcodes.td:1582
261 G_BRJT = 246, // GenericOpcodes.td:1612
262 G_VSCALE = 247, // GenericOpcodes.td:1512
263 G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656
264 G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663
265 G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670
266 G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677
267 G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687
268 G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694
269 G_STEP_VECTOR = 254, // GenericOpcodes.td:1701
270 G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708
271 G_CTTZ = 256, // GenericOpcodes.td:205
272 G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211
273 G_CTLZ = 258, // GenericOpcodes.td:193
274 G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199
275 G_CTLS = 260, // GenericOpcodes.td:217
276 G_CTPOP = 261, // GenericOpcodes.td:223
277 G_BSWAP = 262, // GenericOpcodes.td:229
278 G_BITREVERSE = 263, // GenericOpcodes.td:235
279 G_FCEIL = 264, // GenericOpcodes.td:1096
280 G_FCOS = 265, // GenericOpcodes.td:1103
281 G_FSIN = 266, // GenericOpcodes.td:1110
282 G_FSINCOS = 267, // GenericOpcodes.td:1117
283 G_FTAN = 268, // GenericOpcodes.td:1124
284 G_FACOS = 269, // GenericOpcodes.td:1131
285 G_FASIN = 270, // GenericOpcodes.td:1138
286 G_FATAN = 271, // GenericOpcodes.td:1145
287 G_FATAN2 = 272, // GenericOpcodes.td:1152
288 G_FCOSH = 273, // GenericOpcodes.td:1159
289 G_FSINH = 274, // GenericOpcodes.td:1166
290 G_FTANH = 275, // GenericOpcodes.td:1173
291 G_FSQRT = 276, // GenericOpcodes.td:1183
292 G_FFLOOR = 277, // GenericOpcodes.td:1190
293 G_FRINT = 278, // GenericOpcodes.td:1197
294 G_FNEARBYINT = 279, // GenericOpcodes.td:1204
295 G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241
296 G_BLOCK_ADDR = 281, // GenericOpcodes.td:247
297 G_JUMP_TABLE = 282, // GenericOpcodes.td:253
298 G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259
299 G_STACKSAVE = 284, // GenericOpcodes.td:265
300 G_STACKRESTORE = 285, // GenericOpcodes.td:271
301 G_STRICT_FADD = 286, // GenericOpcodes.td:1758
302 G_STRICT_FSUB = 287, // GenericOpcodes.td:1759
303 G_STRICT_FMUL = 288, // GenericOpcodes.td:1760
304 G_STRICT_FDIV = 289, // GenericOpcodes.td:1761
305 G_STRICT_FREM = 290, // GenericOpcodes.td:1762
306 G_STRICT_FMA = 291, // GenericOpcodes.td:1763
307 G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764
308 G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765
309 G_READ_REGISTER = 294, // GenericOpcodes.td:1631
310 G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641
311 G_MEMCPY = 296, // GenericOpcodes.td:1771
312 G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779
313 G_MEMMOVE = 298, // GenericOpcodes.td:1787
314 G_MEMSET = 299, // GenericOpcodes.td:1795
315 G_BZERO = 300, // GenericOpcodes.td:1802
316 G_TRAP = 301, // GenericOpcodes.td:1812
317 G_DEBUGTRAP = 302, // GenericOpcodes.td:1819
318 G_UBSANTRAP = 303, // GenericOpcodes.td:1825
319 G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724
320 G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730
321 G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736
322 G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737
323 G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739
324 G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740
325 G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744
328 G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745
329 G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752
336 G_SBFX = 321, // GenericOpcodes.td:1837
337 G_UBFX = 322, // GenericOpcodes.td:1845
338 BRANCH = 323, // R600Instructions.td:1594
339 BRANCH_COND_f32 = 324, // R600Instructions.td:1567
340 BRANCH_COND_i32 = 325, // R600Instructions.td:1563
341 BREAK = 326, // R600Instructions.td:1608
342 BREAKC_f32 = 327, // R600Instructions.td:1584
343 BREAKC_i32 = 328, // R600Instructions.td:1582
344 BREAK_LOGICALNZ_f32 = 329, // R600Instructions.td:1577
345 BREAK_LOGICALNZ_i32 = 330, // R600Instructions.td:1575
346 BREAK_LOGICALZ_f32 = 331, // R600Instructions.td:1577
347 BREAK_LOGICALZ_i32 = 332, // R600Instructions.td:1575
348 CONST_COPY = 333, // R600Instructions.td:1439
349 CONTINUE = 334, // R600Instructions.td:1610
350 CONTINUEC_f32 = 335, // R600Instructions.td:1584
351 CONTINUEC_i32 = 336, // R600Instructions.td:1582
352 CONTINUE_LOGICALNZ_f32 = 337, // R600Instructions.td:1577
353 CONTINUE_LOGICALNZ_i32 = 338, // R600Instructions.td:1575
354 CONTINUE_LOGICALZ_f32 = 339, // R600Instructions.td:1577
355 CONTINUE_LOGICALZ_i32 = 340, // R600Instructions.td:1575
356 CUBE_eg_pseudo = 341, // R600Instructions.td:1074
357 CUBE_r600_pseudo = 342, // R600Instructions.td:1074
358 DEFAULT = 343, // R600Instructions.td:1612
359 DOT_4 = 344, // R600Instructions.td:1061
360 DUMMY_CHAIN = 345, // R600Instructions.td:792
361 ELSE = 346, // R600Instructions.td:1614
362 END = 347, // R600Instructions.td:1620
363 ENDFUNC = 348, // R600Instructions.td:1622
364 ENDIF = 349, // R600Instructions.td:1624
365 ENDLOOP = 350, // R600Instructions.td:1628
366 ENDMAIN = 351, // R600Instructions.td:1618
367 ENDSWITCH = 352, // R600Instructions.td:1616
368 FABS_R600 = 353, // R600Instructions.td:1204
369 FNEG_R600 = 354, // R600Instructions.td:1205
370 FUNC = 355, // R600Instructions.td:1630
371 IFC_f32 = 356, // R600Instructions.td:1584
372 IFC_i32 = 357, // R600Instructions.td:1582
373 IF_LOGICALNZ_f32 = 358, // R600Instructions.td:1577
374 IF_LOGICALNZ_i32 = 359, // R600Instructions.td:1575
375 IF_LOGICALZ_f32 = 360, // R600Instructions.td:1577
376 IF_LOGICALZ_i32 = 361, // R600Instructions.td:1575
377 IF_PREDICATE_SET = 362, // R600Instructions.td:1604
378 JUMP = 363, // R600Instructions.td:1385
379 JUMP_COND = 364, // R600Instructions.td:1378
380 MASK_WRITE = 365, // R600Instructions.td:1402
381 MOV_IMM_F32 = 366, // R600Instructions.td:827
382 MOV_IMM_GLOBAL_ADDR = 367, // R600Instructions.td:820
383 MOV_IMM_I32 = 368, // R600Instructions.td:814
384 PRED_X = 369, // R600Instructions.td:1370
385 R600_EXTRACT_ELT_V2 = 370, // R600Instructions.td:1677
386 R600_EXTRACT_ELT_V4 = 371, // R600Instructions.td:1678
387 R600_INSERT_ELT_V2 = 372, // R600Instructions.td:1680
388 R600_INSERT_ELT_V4 = 373, // R600Instructions.td:1681
389 R600_RegisterLoad = 374, // R600Instructions.td:698
390 R600_RegisterStore = 375, // R600Instructions.td:707
391 RETDYN = 376, // R600Instructions.td:1632
392 RETURN = 377, // R600Instructions.td:88
393 TXD = 378, // R600Instructions.td:1413
394 TXD_SHADOW = 379, // R600Instructions.td:1422
395 WHILELOOP = 380, // R600Instructions.td:1626
396 ADD = 381, // R600Instructions.td:721
397 ADDC_UINT = 382, // EvergreenInstructions.td:526
398 ADD_INT = 383, // R600Instructions.td:848
399 ALU_CLAUSE = 384, // R600Instructions.td:646
400 AND_INT = 385, // R600Instructions.td:844
401 ASHR_eg = 386, // EvergreenInstructions.td:511
402 ASHR_r600 = 387, // R600Instructions.td:1253
403 BCNT_INT = 388, // EvergreenInstructions.td:531
404 BFE_INT_eg = 389, // EvergreenInstructions.td:370
405 BFE_UINT_eg = 390, // EvergreenInstructions.td:365
406 BFI_INT_eg = 391, // EvergreenInstructions.td:411
407 BFM_INT_eg = 392, // EvergreenInstructions.td:492
408 BIT_ALIGN_INT_eg = 393, // EvergreenInstructions.td:503
409 CEIL = 394, // R600Instructions.td:781
410 CF_ALU = 395, // R600Instructions.td:631
411 CF_ALU_BREAK = 396, // R600Instructions.td:635
412 CF_ALU_CONTINUE = 397, // R600Instructions.td:634
413 CF_ALU_ELSE_AFTER = 398, // R600Instructions.td:636
414 CF_ALU_POP_AFTER = 399, // R600Instructions.td:633
415 CF_ALU_PUSH_BEFORE = 400, // R600Instructions.td:632
416 CF_CALL_FS_EG = 401, // EvergreenInstructions.td:853
417 CF_CALL_FS_R600 = 402, // R600Instructions.td:1325
418 CF_CONTINUE_EG = 403, // EvergreenInstructions.td:836
419 CF_CONTINUE_R600 = 404, // R600Instructions.td:1307
420 CF_ELSE_EG = 405, // EvergreenInstructions.td:849
421 CF_ELSE_R600 = 406, // R600Instructions.td:1321
422 CF_END_CM = 407, // CaymanInstructions.td:66
423 CF_END_EG = 408, // EvergreenInstructions.td:862
424 CF_END_R600 = 409, // R600Instructions.td:1334
425 CF_JUMP_EG = 410, // EvergreenInstructions.td:841
426 CF_JUMP_R600 = 411, // R600Instructions.td:1312
427 CF_PUSH_EG = 412, // EvergreenInstructions.td:845
428 CF_PUSH_ELSE_R600 = 413, // R600Instructions.td:1316
429 CF_TC_EG = 414, // EvergreenInstructions.td:814
430 CF_TC_R600 = 415, // R600Instructions.td:1285
431 CF_VC_EG = 416, // EvergreenInstructions.td:818
432 CF_VC_R600 = 417, // R600Instructions.td:1289
433 CNDE_INT = 418, // R600Instructions.td:890
434 CNDE_eg = 419, // EvergreenInstructions.td:514
435 CNDE_r600 = 420, // R600Instructions.td:1235
436 CNDGE_INT = 421, // R600Instructions.td:895
437 CNDGE_eg = 422, // EvergreenInstructions.td:516
438 CNDGE_r600 = 423, // R600Instructions.td:1237
439 CNDGT_INT = 424, // R600Instructions.td:900
440 CNDGT_eg = 425, // EvergreenInstructions.td:515
441 CNDGT_r600 = 426, // R600Instructions.td:1236
442 COS_cm = 427, // CaymanInstructions.td:48
443 COS_eg = 428, // EvergreenInstructions.td:132
444 COS_r600 = 429, // R600Instructions.td:1252
445 COS_r700 = 430, // R700Instructions.td:19
446 CUBE_eg_real = 431, // R600Instructions.td:1085
447 CUBE_r600_real = 432, // R600Instructions.td:1085
448 DOT4_eg = 433, // EvergreenInstructions.td:522
449 DOT4_r600 = 434, // R600Instructions.td:1238
450 EG_ExportBuf = 435, // EvergreenInstructions.td:804
451 EG_ExportSwz = 436, // EvergreenInstructions.td:794
452 END_LOOP_EG = 437, // EvergreenInstructions.td:827
453 END_LOOP_R600 = 438, // R600Instructions.td:1298
454 EXP_IEEE_cm = 439, // CaymanInstructions.td:43
455 EXP_IEEE_eg = 440, // EvergreenInstructions.td:125
456 EXP_IEEE_r600 = 441, // R600Instructions.td:1240
457 FETCH_CLAUSE = 442, // R600Instructions.td:638
458 FFBH_UINT = 443, // EvergreenInstructions.td:532
459 FFBL_INT = 444, // EvergreenInstructions.td:533
460 FLOOR = 445, // R600Instructions.td:783
461 FLT16_TO_FLT32 = 446, // EvergreenInstructions.td:530
462 FLT32_TO_FLT16 = 447, // EvergreenInstructions.td:529
463 FLT_TO_INT_eg = 448, // EvergreenInstructions.td:539
464 FLT_TO_INT_r600 = 449, // R600Instructions.td:1247
465 FLT_TO_UINT_eg = 450, // EvergreenInstructions.td:546
466 FLT_TO_UINT_r600 = 451, // R600Instructions.td:1249
467 FMA_eg = 452, // EvergreenInstructions.td:510
468 FRACT = 453, // R600Instructions.td:779
469 GROUP_BARRIER = 454, // EvergreenInstructions.td:552
470 INTERP_LOAD_P0 = 455, // R600Instructions.td:445
471 INTERP_PAIR_XY = 456, // R600Instructions.td:367
472 INTERP_PAIR_ZW = 457, // R600Instructions.td:373
473 INTERP_VEC_LOAD = 458, // R600Instructions.td:430
474 INTERP_XY = 459, // R600Instructions.td:437
475 INTERP_ZW = 460, // R600Instructions.td:441
476 INT_TO_FLT_eg = 461, // EvergreenInstructions.td:544
477 INT_TO_FLT_r600 = 462, // R600Instructions.td:1248
478 KILLGT = 463, // R600Instructions.td:840
479 LDS_ADD = 464, // EvergreenInstructions.td:690
480 LDS_ADD_RET = 465, // EvergreenInstructions.td:710
481 LDS_AND = 466, // EvergreenInstructions.td:692
482 LDS_AND_RET = 467, // EvergreenInstructions.td:716
483 LDS_BYTE_READ_RET = 468, // EvergreenInstructions.td:746
484 LDS_BYTE_WRITE = 469, // EvergreenInstructions.td:704
485 LDS_CMPST = 470, // EvergreenInstructions.td:696
486 LDS_CMPST_RET = 471, // EvergreenInstructions.td:740
487 LDS_MAX_INT = 472, // EvergreenInstructions.td:698
488 LDS_MAX_INT_RET = 473, // EvergreenInstructions.td:728
489 LDS_MAX_UINT = 474, // EvergreenInstructions.td:700
490 LDS_MAX_UINT_RET = 475, // EvergreenInstructions.td:734
491 LDS_MIN_INT = 476, // EvergreenInstructions.td:697
492 LDS_MIN_INT_RET = 477, // EvergreenInstructions.td:725
493 LDS_MIN_UINT = 478, // EvergreenInstructions.td:699
494 LDS_MIN_UINT_RET = 479, // EvergreenInstructions.td:731
495 LDS_OR = 480, // EvergreenInstructions.td:693
496 LDS_OR_RET = 481, // EvergreenInstructions.td:719
497 LDS_READ_RET = 482, // EvergreenInstructions.td:743
498 LDS_SHORT_READ_RET = 483, // EvergreenInstructions.td:752
499 LDS_SHORT_WRITE = 484, // EvergreenInstructions.td:707
500 LDS_SUB = 485, // EvergreenInstructions.td:691
501 LDS_SUB_RET = 486, // EvergreenInstructions.td:713
502 LDS_UBYTE_READ_RET = 487, // EvergreenInstructions.td:749
503 LDS_USHORT_READ_RET = 488, // EvergreenInstructions.td:755
504 LDS_WRITE = 489, // EvergreenInstructions.td:701
505 LDS_WRXCHG = 490, // EvergreenInstructions.td:695
506 LDS_WRXCHG_RET = 491, // EvergreenInstructions.td:737
507 LDS_XOR = 492, // EvergreenInstructions.td:694
508 LDS_XOR_RET = 493, // EvergreenInstructions.td:722
509 LITERALS = 494, // R600Instructions.td:654
510 LOG_CLAMPED_eg = 495, // EvergreenInstructions.td:518
511 LOG_CLAMPED_r600 = 496, // R600Instructions.td:1241
512 LOG_IEEE_cm = 497, // CaymanInstructions.td:44
513 LOG_IEEE_eg = 498, // EvergreenInstructions.td:126
514 LOG_IEEE_r600 = 499, // R600Instructions.td:1242
515 LOOP_BREAK_EG = 500, // EvergreenInstructions.td:831
516 LOOP_BREAK_R600 = 501, // R600Instructions.td:1302
517 LSHL_eg = 502, // EvergreenInstructions.td:513
518 LSHL_r600 = 503, // R600Instructions.td:1255
519 LSHR_eg = 504, // EvergreenInstructions.td:512
520 LSHR_r600 = 505, // R600Instructions.td:1254
521 MAX = 506, // R600Instructions.td:726
522 MAX_DX10 = 507, // R600Instructions.td:731
523 MAX_INT = 508, // R600Instructions.td:850
524 MAX_UINT = 509, // R600Instructions.td:852
525 MIN = 510, // R600Instructions.td:727
526 MIN_DX10 = 511, // R600Instructions.td:732
527 MIN_INT = 512, // R600Instructions.td:851
528 MIN_UINT = 513, // R600Instructions.td:853
529 MOV = 514, // R600Instructions.td:785
530 MOVA_INT_eg = 515, // EvergreenInstructions.td:536
531 MUL = 516, // R600Instructions.td:723
532 MULADD_IEEE_eg = 517, // EvergreenInstructions.td:509
533 MULADD_IEEE_r600 = 518, // R600Instructions.td:1234
534 MULADD_INT24_cm = 519, // CaymanInstructions.td:22
535 MULADD_UINT24_eg = 520, // EvergreenInstructions.td:497
536 MULADD_eg = 521, // EvergreenInstructions.td:508
537 MULADD_r600 = 522, // R600Instructions.td:1233
538 MULHI_INT_cm = 523, // CaymanInstructions.td:36
539 MULHI_INT_cm24 = 524, // CaymanInstructions.td:39
540 MULHI_INT_eg = 525, // EvergreenInstructions.td:118
541 MULHI_INT_r600 = 526, // R600Instructions.td:1257
542 MULHI_UINT24_eg = 527, // EvergreenInstructions.td:121
543 MULHI_UINT_cm = 528, // CaymanInstructions.td:38
544 MULHI_UINT_cm24 = 529, // CaymanInstructions.td:40
545 MULHI_UINT_eg = 530, // EvergreenInstructions.td:120
546 MULHI_UINT_r600 = 531, // R600Instructions.td:1259
547 MULLO_INT_cm = 532, // CaymanInstructions.td:35
548 MULLO_INT_eg = 533, // EvergreenInstructions.td:117
549 MULLO_INT_r600 = 534, // R600Instructions.td:1256
550 MULLO_UINT_cm = 535, // CaymanInstructions.td:37
551 MULLO_UINT_eg = 536, // EvergreenInstructions.td:119
552 MULLO_UINT_r600 = 537, // R600Instructions.td:1258
553 MUL_IEEE = 538, // R600Instructions.td:724
554 MUL_INT24_cm = 539, // CaymanInstructions.td:25
555 MUL_LIT_eg = 540, // EvergreenInstructions.td:517
556 MUL_LIT_r600 = 541, // R600Instructions.td:1232
557 MUL_UINT24_eg = 542, // EvergreenInstructions.td:519
558 NOT_INT = 543, // R600Instructions.td:847
559 OR_INT = 544, // R600Instructions.td:845
560 PAD = 545, // R600Instructions.td:666
561 POP_EG = 546, // EvergreenInstructions.td:858
562 POP_R600 = 547, // R600Instructions.td:1330
563 PRED_SETE = 548, // R600Instructions.td:833
564 PRED_SETE_INT = 549, // R600Instructions.td:885
565 PRED_SETGE = 550, // R600Instructions.td:835
566 PRED_SETGE_INT = 551, // R600Instructions.td:887
567 PRED_SETGT = 552, // R600Instructions.td:834
568 PRED_SETGT_INT = 553, // R600Instructions.td:886
569 PRED_SETNE = 554, // R600Instructions.td:836
570 PRED_SETNE_INT = 555, // R600Instructions.td:888
571 R600_ExportBuf = 556, // R600Instructions.td:1276
572 R600_ExportSwz = 557, // R600Instructions.td:1267
573 RAT_ATOMIC_ADD_NORET = 558, // EvergreenInstructions.td:82
574 RAT_ATOMIC_ADD_RTN = 559, // EvergreenInstructions.td:78
575 RAT_ATOMIC_AND_NORET = 560, // EvergreenInstructions.td:82
576 RAT_ATOMIC_AND_RTN = 561, // EvergreenInstructions.td:78
577 RAT_ATOMIC_CMPXCHG_INT_NORET = 562, // EvergreenInstructions.td:82
578 RAT_ATOMIC_CMPXCHG_INT_RTN = 563, // EvergreenInstructions.td:78
579 RAT_ATOMIC_DEC_UINT_NORET = 564, // EvergreenInstructions.td:82
580 RAT_ATOMIC_DEC_UINT_RTN = 565, // EvergreenInstructions.td:78
581 RAT_ATOMIC_INC_UINT_NORET = 566, // EvergreenInstructions.td:82
582 RAT_ATOMIC_INC_UINT_RTN = 567, // EvergreenInstructions.td:78
583 RAT_ATOMIC_MAX_INT_NORET = 568, // EvergreenInstructions.td:82
584 RAT_ATOMIC_MAX_INT_RTN = 569, // EvergreenInstructions.td:78
585 RAT_ATOMIC_MAX_UINT_NORET = 570, // EvergreenInstructions.td:82
586 RAT_ATOMIC_MAX_UINT_RTN = 571, // EvergreenInstructions.td:78
587 RAT_ATOMIC_MIN_INT_NORET = 572, // EvergreenInstructions.td:82
588 RAT_ATOMIC_MIN_INT_RTN = 573, // EvergreenInstructions.td:78
589 RAT_ATOMIC_MIN_UINT_NORET = 574, // EvergreenInstructions.td:82
590 RAT_ATOMIC_MIN_UINT_RTN = 575, // EvergreenInstructions.td:78
591 RAT_ATOMIC_OR_NORET = 576, // EvergreenInstructions.td:82
592 RAT_ATOMIC_OR_RTN = 577, // EvergreenInstructions.td:78
593 RAT_ATOMIC_RSUB_NORET = 578, // EvergreenInstructions.td:82
594 RAT_ATOMIC_RSUB_RTN = 579, // EvergreenInstructions.td:78
595 RAT_ATOMIC_SUB_NORET = 580, // EvergreenInstructions.td:82
596 RAT_ATOMIC_SUB_RTN = 581, // EvergreenInstructions.td:78
597 RAT_ATOMIC_XCHG_INT_NORET = 582, // EvergreenInstructions.td:82
598 RAT_ATOMIC_XCHG_INT_RTN = 583, // EvergreenInstructions.td:78
599 RAT_ATOMIC_XOR_NORET = 584, // EvergreenInstructions.td:82
600 RAT_ATOMIC_XOR_RTN = 585, // EvergreenInstructions.td:78
601 RAT_MSKOR = 586, // EvergreenInstructions.td:67
602 RAT_STORE_DWORD128 = 587, // CaymanInstructions.td:84
603 RAT_STORE_DWORD32 = 588, // CaymanInstructions.td:82
604 RAT_STORE_DWORD64 = 589, // CaymanInstructions.td:83
605 RAT_STORE_TYPED_cm = 590, // CaymanInstructions.td:86
606 RAT_STORE_TYPED_eg = 591, // EvergreenInstructions.td:164
607 RAT_WRITE_CACHELESS_128_eg = 592, // EvergreenInstructions.td:158
608 RAT_WRITE_CACHELESS_32_eg = 593, // EvergreenInstructions.td:144
609 RAT_WRITE_CACHELESS_64_eg = 594, // EvergreenInstructions.td:151
610 RECIPSQRT_CLAMPED_cm = 595, // CaymanInstructions.td:42
611 RECIPSQRT_CLAMPED_eg = 596, // EvergreenInstructions.td:124
612 RECIPSQRT_CLAMPED_r600 = 597, // R600Instructions.td:1245
613 RECIPSQRT_IEEE_cm = 598, // CaymanInstructions.td:46
614 RECIPSQRT_IEEE_eg = 599, // EvergreenInstructions.td:128
615 RECIPSQRT_IEEE_r600 = 600, // R600Instructions.td:1246
616 RECIP_CLAMPED_cm = 601, // CaymanInstructions.td:45
617 RECIP_CLAMPED_eg = 602, // EvergreenInstructions.td:127
618 RECIP_CLAMPED_r600 = 603, // R600Instructions.td:1243
619 RECIP_IEEE_cm = 604, // CaymanInstructions.td:33
620 RECIP_IEEE_eg = 605, // EvergreenInstructions.td:114
621 RECIP_IEEE_r600 = 606, // R600Instructions.td:1244
622 RECIP_UINT_eg = 607, // EvergreenInstructions.td:123
623 RECIP_UINT_r600 = 608, // R600Instructions.td:1260
624 RNDNE = 609, // R600Instructions.td:782
625 SETE = 610, // R600Instructions.td:737
626 SETE_DX10 = 611, // R600Instructions.td:757
627 SETE_INT = 612, // R600Instructions.td:855
628 SETGE_DX10 = 613, // R600Instructions.td:767
629 SETGE_INT = 614, // R600Instructions.td:865
630 SETGE_UINT = 615, // R600Instructions.td:880
631 SETGT_DX10 = 616, // R600Instructions.td:762
632 SETGT_INT = 617, // R600Instructions.td:860
633 SETGT_UINT = 618, // R600Instructions.td:875
634 SETNE_DX10 = 619, // R600Instructions.td:773
635 SETNE_INT = 620, // R600Instructions.td:870
636 SGE = 621, // R600Instructions.td:747
637 SGT = 622, // R600Instructions.td:742
638 SIN_cm = 623, // CaymanInstructions.td:47
639 SIN_eg = 624, // EvergreenInstructions.td:131
640 SIN_r600 = 625, // R600Instructions.td:1251
641 SIN_r700 = 626, // R700Instructions.td:18
642 SNE = 627, // R600Instructions.td:752
643 SUBB_UINT = 628, // EvergreenInstructions.td:527
644 SUB_INT = 629, // R600Instructions.td:849
645 TEX_GET_GRADIENTS_H = 630, // R600Instructions.td:959
646 TEX_GET_GRADIENTS_V = 631, // R600Instructions.td:960
647 TEX_GET_TEXTURE_RESINFO = 632, // R600Instructions.td:958
648 TEX_LD = 633, // R600Instructions.td:954
649 TEX_LDPTR = 634, // R600Instructions.td:955
650 TEX_SAMPLE = 635, // R600Instructions.td:948
651 TEX_SAMPLE_C = 636, // R600Instructions.td:949
652 TEX_SAMPLE_C_G = 637, // R600Instructions.td:964
653 TEX_SAMPLE_C_L = 638, // R600Instructions.td:951
654 TEX_SAMPLE_C_LB = 639, // R600Instructions.td:953
655 TEX_SAMPLE_G = 640, // R600Instructions.td:963
656 TEX_SAMPLE_L = 641, // R600Instructions.td:950
657 TEX_SAMPLE_LB = 642, // R600Instructions.td:952
658 TEX_SET_GRADIENTS_H = 643, // R600Instructions.td:961
659 TEX_SET_GRADIENTS_V = 644, // R600Instructions.td:962
660 TEX_VTX_CONSTBUF = 645, // R600Instructions.td:1451
661 TEX_VTX_TEXBUF = 646, // R600Instructions.td:1505
662 TRUNC = 647, // R600Instructions.td:780
663 UINT_TO_FLT_eg = 648, // EvergreenInstructions.td:550
664 UINT_TO_FLT_r600 = 649, // R600Instructions.td:1250
665 VTX_READ_128_cm = 650, // CaymanInstructions.td:162
666 VTX_READ_128_eg = 651, // EvergreenInstructions.td:240
667 VTX_READ_16_cm = 652, // CaymanInstructions.td:120
668 VTX_READ_16_eg = 653, // EvergreenInstructions.td:195
669 VTX_READ_32_cm = 654, // CaymanInstructions.td:131
670 VTX_READ_32_eg = 655, // EvergreenInstructions.td:207
671 VTX_READ_64_cm = 656, // CaymanInstructions.td:151
672 VTX_READ_64_eg = 657, // EvergreenInstructions.td:228
673 VTX_READ_8_cm = 658, // CaymanInstructions.td:109
674 VTX_READ_8_eg = 659, // EvergreenInstructions.td:183
675 WHILE_LOOP_EG = 660, // EvergreenInstructions.td:822
676 WHILE_LOOP_R600 = 661, // R600Instructions.td:1293
677 XOR_INT = 662, // R600Instructions.td:846
678 INSTRUCTION_LIST_END = 663
679 };
680
681} // namespace llvm::R600
682
683#endif // GET_INSTRINFO_ENUM
684
685#ifdef GET_INSTRINFO_SCHED_ENUM
686#undef GET_INSTRINFO_SCHED_ENUM
687
688namespace llvm::R600::Sched {
689
690 enum {
691 NoInstrModel = 0,
692 NullALU = 1,
693 VecALU = 2,
694 AnyALU = 3,
695 TransALU = 4,
696 XALU = 5,
697 SCHED_LIST_END = 6
698 };
699
700} // namespace llvm::R600::Sched
701
702#endif // GET_INSTRINFO_SCHED_ENUM
703
704#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
705
706namespace llvm {
707
708struct R600InstrTable {
709 MCInstrDesc Insts[663];
710 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
711 MCPhysReg ImplicitOps[1];
712 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
713 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
714 MCOperandInfo OperandInfo[465];
715};
716} // namespace llvm
717
718#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
719
720#ifdef GET_INSTRINFO_MC_DESC
721#undef GET_INSTRINFO_MC_DESC
722
723namespace llvm {
724
725static_assert((sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
726static constexpr unsigned R600OpInfoBase = (sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) / sizeof(MCOperandInfo);
727
728extern const R600InstrTable R600Descs = {
729 {
730 { 662, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // XOR_INT
731 { 661, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_R600
732 { 660, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_EG
733 { 659, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_eg
734 { 658, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_cm
735 { 657, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 461, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_eg
736 { 656, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 461, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_cm
737 { 655, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_eg
738 { 654, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_cm
739 { 653, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_eg
740 { 652, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_cm
741 { 651, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_eg
742 { 650, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_cm
743 { 649, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_r600
744 { 648, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_eg
745 { 647, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // TRUNC
746 { 646, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL }, // TEX_VTX_TEXBUF
747 { 645, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0, 0x1000ULL }, // TEX_VTX_CONSTBUF
748 { 644, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_V
749 { 643, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_H
750 { 642, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SAMPLE_LB
751 { 641, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SAMPLE_L
752 { 640, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SAMPLE_G
753 { 639, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_LB
754 { 638, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_L
755 { 637, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_G
756 { 636, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C
757 { 635, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_SAMPLE
758 { 634, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_LDPTR
759 { 633, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_LD
760 { 632, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_GET_TEXTURE_RESINFO
761 { 631, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_V
762 { 630, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 430, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_H
763 { 629, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUB_INT
764 { 628, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUBB_UINT
765 { 627, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SNE
766 { 626, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r700
767 { 625, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r600
768 { 624, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_eg
769 { 623, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // SIN_cm
770 { 622, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGT
771 { 621, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGE
772 { 620, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_INT
773 { 619, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_DX10
774 { 618, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_UINT
775 { 617, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_INT
776 { 616, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_DX10
777 { 615, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_UINT
778 { 614, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_INT
779 { 613, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_DX10
780 { 612, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_INT
781 { 611, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_DX10
782 { 610, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE
783 { 609, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RNDNE
784 { 608, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_r600
785 { 607, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_eg
786 { 606, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_r600
787 { 605, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_eg
788 { 604, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_IEEE_cm
789 { 603, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_r600
790 { 602, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_eg
791 { 601, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_CLAMPED_cm
792 { 600, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_r600
793 { 599, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_eg
794 { 598, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_IEEE_cm
795 { 597, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_r600
796 { 596, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_eg
797 { 595, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_CLAMPED_cm
798 { 594, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 427, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_64_eg
799 { 593, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 424, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_32_eg
800 { 592, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 421, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_128_eg
801 { 591, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 417, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_eg
802 { 590, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 417, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_cm
803 { 589, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 415, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD64
804 { 588, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD32
805 { 587, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 411, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD128
806 { 586, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 411, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_MSKOR
807 { 585, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_RTN
808 { 584, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_NORET
809 { 583, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_RTN
810 { 582, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_NORET
811 { 581, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_RTN
812 { 580, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_NORET
813 { 579, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_RTN
814 { 578, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_NORET
815 { 577, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_RTN
816 { 576, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_NORET
817 { 575, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_RTN
818 { 574, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_NORET
819 { 573, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_RTN
820 { 572, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_NORET
821 { 571, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_RTN
822 { 570, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_NORET
823 { 569, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_RTN
824 { 568, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_NORET
825 { 567, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_RTN
826 { 566, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_NORET
827 { 565, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_RTN
828 { 564, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_NORET
829 { 563, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_RTN
830 { 562, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_NORET
831 { 561, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_RTN
832 { 560, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_NORET
833 { 559, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_RTN
834 { 558, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 408, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_NORET
835 { 557, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 336, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportSwz
836 { 556, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 329, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportBuf
837 { 555, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE_INT
838 { 554, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE
839 { 553, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT_INT
840 { 552, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT
841 { 551, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE_INT
842 { 550, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE
843 { 549, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE_INT
844 { 548, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE
845 { 547, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_R600
846 { 546, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_EG
847 { 545, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PAD
848 { 544, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // OR_INT
849 { 543, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // NOT_INT
850 { 542, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_UINT24_eg
851 { 541, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_r600
852 { 540, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_eg
853 { 539, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_INT24_cm
854 { 538, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_IEEE
855 { 537, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_r600
856 { 536, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_eg
857 { 535, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_UINT_cm
858 { 534, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_r600
859 { 533, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_eg
860 { 532, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_INT_cm
861 { 531, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_r600
862 { 530, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_eg
863 { 529, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm24
864 { 528, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm
865 { 527, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT24_eg
866 { 526, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_r600
867 { 525, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_eg
868 { 524, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm24
869 { 523, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm
870 { 522, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_r600
871 { 521, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_eg
872 { 520, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_UINT24_eg
873 { 519, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_INT24_cm
874 { 518, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_r600
875 { 517, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_eg
876 { 516, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL
877 { 515, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL }, // MOVA_INT_eg
878 { 514, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // MOV
879 { 513, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_UINT
880 { 512, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_INT
881 { 511, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_DX10
882 { 510, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN
883 { 509, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_UINT
884 { 508, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_INT
885 { 507, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_DX10
886 { 506, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX
887 { 505, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_r600
888 { 504, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_eg
889 { 503, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_r600
890 { 502, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_eg
891 { 501, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_R600
892 { 500, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_EG
893 { 499, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_r600
894 { 498, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_eg
895 { 497, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // LOG_IEEE_cm
896 { 496, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_r600
897 { 495, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_eg
898 { 494, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 13, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LITERALS
899 { 493, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_XOR_RET
900 { 492, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_XOR
901 { 491, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_WRXCHG_RET
902 { 490, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_WRXCHG
903 { 489, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_WRITE
904 { 488, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 376, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_USHORT_READ_RET
905 { 487, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 376, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_UBYTE_READ_RET
906 { 486, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_SUB_RET
907 { 485, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_SUB
908 { 484, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_SHORT_WRITE
909 { 483, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 376, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_SHORT_READ_RET
910 { 482, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 376, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_READ_RET
911 { 481, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_OR_RET
912 { 480, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_OR
913 { 479, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_UINT_RET
914 { 478, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_UINT
915 { 477, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_INT_RET
916 { 476, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_INT
917 { 475, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_UINT_RET
918 { 474, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_UINT
919 { 473, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_INT_RET
920 { 472, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_INT
921 { 471, 13, 1, 0, 5, 0, 0, R600OpInfoBase + 395, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL }, // LDS_CMPST_RET
922 { 470, 12, 0, 0, 5, 0, 0, R600OpInfoBase + 383, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL }, // LDS_CMPST
923 { 469, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_BYTE_WRITE
924 { 468, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 376, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_BYTE_READ_RET
925 { 467, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_AND_RET
926 { 466, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_AND
927 { 465, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 366, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_ADD_RET
928 { 464, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 357, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_ADD
929 { 463, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL }, // KILLGT
930 { 462, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_r600
931 { 461, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_eg
932 { 460, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_ZW
933 { 459, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_XY
934 { 458, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 355, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_VEC_LOAD
935 { 457, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 350, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_ZW
936 { 456, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 345, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_XY
937 { 455, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INTERP_LOAD_P0
938 { 454, 0, 0, 0, 3, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL }, // GROUP_BARRIER
939 { 453, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FRACT
940 { 452, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // FMA_eg
941 { 451, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_r600
942 { 450, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_eg
943 { 449, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_r600
944 { 448, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_eg
945 { 447, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT32_TO_FLT16
946 { 446, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT16_TO_FLT32
947 { 445, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLOOR
948 { 444, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBL_INT
949 { 443, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBH_UINT
950 { 442, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FETCH_CLAUSE
951 { 441, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_r600
952 { 440, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_eg
953 { 439, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // EXP_IEEE_cm
954 { 438, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_R600
955 { 437, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_EG
956 { 436, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 336, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportSwz
957 { 435, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 329, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportBuf
958 { 434, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_r600
959 { 433, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_eg
960 { 432, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_r600_real
961 { 431, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_eg_real
962 { 430, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r700
963 { 429, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r600
964 { 428, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_eg
965 { 427, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // COS_cm
966 { 426, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_r600
967 { 425, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_eg
968 { 424, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_INT
969 { 423, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_r600
970 { 422, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_eg
971 { 421, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_INT
972 { 420, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_r600
973 { 419, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_eg
974 { 418, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_INT
975 { 417, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_R600
976 { 416, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_EG
977 { 415, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_R600
978 { 414, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_EG
979 { 413, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_ELSE_R600
980 { 412, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_EG
981 { 411, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_R600
982 { 410, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_EG
983 { 409, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_R600
984 { 408, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_EG
985 { 407, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_CM
986 { 406, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_R600
987 { 405, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_EG
988 { 404, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_R600
989 { 403, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_EG
990 { 402, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_R600
991 { 401, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_EG
992 { 400, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_PUSH_BEFORE
993 { 399, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_POP_AFTER
994 { 398, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_ELSE_AFTER
995 { 397, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_CONTINUE
996 { 396, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_BREAK
997 { 395, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 320, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU
998 { 394, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // CEIL
999 { 393, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BIT_ALIGN_INT_eg
1000 { 392, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // BFM_INT_eg
1001 { 391, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFI_INT_eg
1002 { 390, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_UINT_eg
1003 { 389, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 301, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_INT_eg
1004 { 388, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 287, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // BCNT_INT
1005 { 387, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_r600
1006 { 386, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_eg
1007 { 385, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // AND_INT
1008 { 384, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALU_CLAUSE
1009 { 383, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD_INT
1010 { 382, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADDC_UINT
1011 { 381, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 266, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD
1012 { 380, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // WHILELOOP
1013 { 379, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 259, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD_SHADOW
1014 { 378, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 259, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD
1015 { 377, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL }, // RETURN
1016 { 376, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // RETDYN
1017 { 375, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL }, // R600_RegisterStore
1018 { 374, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL }, // R600_RegisterLoad
1019 { 373, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V4
1020 { 372, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 247, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V2
1021 { 371, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V4
1022 { 370, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 241, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V2
1023 { 369, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // PRED_X
1024 { 368, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_I32
1025 { 367, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_GLOBAL_ADDR
1026 { 366, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_F32
1027 { 365, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MASK_WRITE
1028 { 364, 2, 0, 0, 3, 0, 0, R600OpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP_COND
1029 { 363, 1, 0, 0, 3, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP
1030 { 362, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // IF_PREDICATE_SET
1031 { 361, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_i32
1032 { 360, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_f32
1033 { 359, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_i32
1034 { 358, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_f32
1035 { 357, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_i32
1036 { 356, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_f32
1037 { 355, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // FUNC
1038 { 354, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FNEG_R600
1039 { 353, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FABS_R600
1040 { 352, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDSWITCH
1041 { 351, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDMAIN
1042 { 350, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDLOOP
1043 { 349, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDIF
1044 { 348, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDFUNC
1045 { 347, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // END
1046 { 346, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ELSE
1047 { 345, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // DUMMY_CHAIN
1048 { 344, 71, 1, 0, 3, 0, 0, R600OpInfoBase + 164, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // DOT_4
1049 { 343, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // DEFAULT
1050 { 342, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_r600_pseudo
1051 { 341, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_eg_pseudo
1052 { 340, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_i32
1053 { 339, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_f32
1054 { 338, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_i32
1055 { 337, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_f32
1056 { 336, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_i32
1057 { 335, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_f32
1058 { 334, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE
1059 { 333, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // CONST_COPY
1060 { 332, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_i32
1061 { 331, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_f32
1062 { 330, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_i32
1063 { 329, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 159, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_f32
1064 { 328, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_i32
1065 { 327, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 157, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_f32
1066 { 326, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK
1067 { 325, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_i32
1068 { 324, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_f32
1069 { 323, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH
1070 { 322, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX
1071 { 321, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX
1072 { 320, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN
1073 { 319, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX
1074 { 318, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN
1075 { 317, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX
1076 { 316, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR
1077 { 315, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR
1078 { 314, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND
1079 { 313, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL
1080 { 312, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD
1081 { 311, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1082 { 310, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1083 { 309, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN
1084 { 308, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX
1085 { 307, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL
1086 { 306, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD
1087 { 305, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1088 { 304, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1089 { 303, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP
1090 { 302, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP
1091 { 301, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP
1092 { 300, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO
1093 { 299, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET
1094 { 298, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE
1095 { 297, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE
1096 { 296, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY
1097 { 295, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 145, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1098 { 294, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1099 { 293, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP
1100 { 292, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT
1101 { 291, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA
1102 { 290, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM
1103 { 289, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV
1104 { 288, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL
1105 { 287, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB
1106 { 286, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD
1107 { 285, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE
1108 { 284, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE
1109 { 283, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC
1110 { 282, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE
1111 { 281, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR
1112 { 280, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST
1113 { 279, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT
1114 { 278, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT
1115 { 277, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR
1116 { 276, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT
1117 { 275, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH
1118 { 274, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH
1119 { 273, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH
1120 { 272, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2
1121 { 271, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN
1122 { 270, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN
1123 { 269, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS
1124 { 268, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN
1125 { 267, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS
1126 { 266, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN
1127 { 265, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS
1128 { 264, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL
1129 { 263, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE
1130 { 262, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP
1131 { 261, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP
1132 { 260, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS
1133 { 259, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
1134 { 258, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ
1135 { 257, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
1136 { 256, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ
1137 { 255, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS
1138 { 254, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR
1139 { 253, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR
1140 { 252, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR
1141 { 251, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1142 { 250, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT
1143 { 249, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1144 { 248, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR
1145 { 247, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE
1146 { 246, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 127, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT
1147 { 245, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR
1148 { 244, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND
1149 { 243, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND
1150 { 242, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS
1151 { 241, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX
1152 { 240, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN
1153 { 239, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX
1154 { 238, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN
1155 { 237, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK
1156 { 236, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD
1157 { 235, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING
1158 { 234, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING
1159 { 233, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE
1160 { 232, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE
1161 { 231, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE
1162 { 230, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV
1163 { 229, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV
1164 { 228, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV
1165 { 227, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM
1166 { 226, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM
1167 { 225, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM
1168 { 224, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM
1169 { 223, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE
1170 { 222, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE
1171 { 221, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM
1172 { 220, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM
1173 { 219, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE
1174 { 218, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS
1175 { 217, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN
1176 { 216, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS
1177 { 215, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT
1178 { 214, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT
1179 { 213, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP
1180 { 212, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP
1181 { 211, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI
1182 { 210, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI
1183 { 209, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC
1184 { 208, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT
1185 { 207, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG
1186 { 206, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP
1187 { 205, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP
1188 { 204, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10
1189 { 203, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2
1190 { 202, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG
1191 { 201, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10
1192 { 200, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2
1193 { 199, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP
1194 { 198, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI
1195 { 197, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW
1196 { 196, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF
1197 { 195, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM
1198 { 194, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV
1199 { 193, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD
1200 { 192, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA
1201 { 191, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL
1202 { 190, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB
1203 { 189, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD
1204 { 188, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT
1205 { 187, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT
1206 { 186, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX
1207 { 185, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX
1208 { 184, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT
1209 { 183, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT
1210 { 182, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX
1211 { 181, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX
1212 { 180, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT
1213 { 179, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT
1214 { 178, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT
1215 { 177, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT
1216 { 176, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT
1217 { 175, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT
1218 { 174, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH
1219 { 173, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH
1220 { 172, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO
1221 { 171, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO
1222 { 170, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE
1223 { 169, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO
1224 { 168, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE
1225 { 167, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO
1226 { 166, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE
1227 { 165, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO
1228 { 164, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE
1229 { 163, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO
1230 { 162, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT
1231 { 161, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP
1232 { 160, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP
1233 { 159, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP
1234 { 158, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP
1235 { 157, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL
1236 { 156, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR
1237 { 155, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR
1238 { 154, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL
1239 { 153, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR
1240 { 152, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR
1241 { 151, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL
1242 { 150, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT
1243 { 149, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG
1244 { 148, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT
1245 { 147, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG
1246 { 146, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART
1247 { 145, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT
1248 { 144, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT
1249 { 143, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U
1250 { 142, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U
1251 { 141, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S
1252 { 140, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC
1253 { 139, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT
1254 { 138, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1255 { 137, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1256 { 136, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1257 { 135, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC
1258 { 134, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START
1259 { 133, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT
1260 { 132, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND
1261 { 131, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH
1262 { 130, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE
1263 { 129, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1264 { 128, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1265 { 127, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1266 { 126, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1267 { 125, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1268 { 124, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1269 { 123, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN
1270 { 122, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX
1271 { 121, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB
1272 { 120, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD
1273 { 119, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN
1274 { 118, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX
1275 { 117, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN
1276 { 116, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX
1277 { 115, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR
1278 { 114, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR
1279 { 113, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND
1280 { 112, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND
1281 { 111, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB
1282 { 110, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD
1283 { 109, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG
1284 { 108, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG
1285 { 107, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 85, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1286 { 106, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 80, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE
1287 { 105, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE
1288 { 104, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1289 { 103, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD
1290 { 102, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD
1291 { 101, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD
1292 { 100, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD
1293 { 99, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD
1294 { 98, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER
1295 { 97, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER
1296 { 96, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1297 { 95, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT
1298 { 94, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT
1299 { 93, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND
1300 { 92, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC
1301 { 91, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1302 { 90, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1303 { 89, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE
1304 { 88, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST
1305 { 87, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR
1306 { 86, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT
1307 { 85, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS
1308 { 84, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1309 { 83, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR
1310 { 82, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES
1311 { 81, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT
1312 { 80, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES
1313 { 79, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT
1314 { 78, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL
1315 { 77, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 56, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1316 { 76, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE
1317 { 75, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX
1318 { 74, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI
1319 { 73, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF
1320 { 72, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL
1321 { 71, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR
1322 { 70, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL
1323 { 69, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR
1324 { 68, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU
1325 { 67, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS
1326 { 66, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR
1327 { 65, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR
1328 { 64, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND
1329 { 63, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM
1330 { 62, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM
1331 { 61, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM
1332 { 60, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM
1333 { 59, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV
1334 { 58, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV
1335 { 57, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL
1336 { 56, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB
1337 { 55, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD
1338 { 54, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN
1339 { 53, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT
1340 { 52, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT
1341 { 51, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1342 { 50, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1343 { 49, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1344 { 48, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1345 { 47, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE
1346 { 46, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1347 { 45, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER
1348 { 44, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE
1349 { 43, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1350 { 42, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 40, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14576
1351 { 41, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 38, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14575
1352 { 40, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL
1353 { 39, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1354 { 38, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET
1355 { 37, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1356 { 36, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP
1357 { 35, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP
1358 { 34, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE
1359 { 33, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT
1360 { 32, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 33, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14574
1361 { 31, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP
1362 { 30, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_14301
1363 { 29, 6, 1, 0, 0, 0, 0, R600OpInfoBase + 26, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT
1364 { 28, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL
1365 { 27, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP
1366 { 26, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE
1367 { 25, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE
1368 { 24, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END
1369 { 23, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START
1370 { 22, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE
1371 { 21, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK
1372 { 20, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY
1373 { 19, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE
1374 { 18, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL
1375 { 17, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI
1376 { 16, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF
1377 { 15, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST
1378 { 14, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE
1379 { 13, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS
1380 { 12, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG
1381 { 11, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF
1382 { 10, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF
1383 { 9, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG
1384 { 8, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG
1385 { 7, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL
1386 { 6, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL
1387 { 5, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL
1388 { 4, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL
1389 { 3, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION
1390 { 2, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR
1391 { 1, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM
1392 { 0, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI
1393 }, {
1394 /* 0 */
1395 }, {
1396 0
1397 }, {
1398 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1399 /* 1 */
1400 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1401 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1402 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1403 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1404 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1405 /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1406 /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1407 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1408 /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1409 /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1410 /* 32 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1411 /* 33 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1412 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1413 /* 38 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1414 /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1415 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1416 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1417 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1418 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1419 /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1420 /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1421 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1422 /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1423 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1424 /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1425 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1426 /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1427 /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1428 /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1429 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1430 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1431 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1432 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1433 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1434 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1435 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1436 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1437 /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1438 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1439 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1440 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1441 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1442 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1443 /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1444 /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1445 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1446 /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1447 /* 155 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1448 /* 157 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1449 /* 159 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1450 /* 160 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1451 /* 162 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1452 /* 164 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1453 /* 235 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1454 /* 237 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1455 /* 241 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1456 /* 244 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1457 /* 247 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1458 /* 251 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1459 /* 255 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1460 /* 259 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1461 /* 266 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1462 /* 287 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1463 /* 301 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1464 /* 320 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1465 /* 329 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1466 /* 336 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1467 /* 345 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1468 /* 350 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1469 /* 355 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1470 /* 357 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1471 /* 366 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1472 /* 376 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1473 /* 383 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1474 /* 395 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1475 /* 408 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1476 /* 411 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1477 /* 413 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1478 /* 415 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1479 /* 417 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1480 /* 421 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1481 /* 424 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1482 /* 427 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1483 /* 430 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1484 /* 449 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1485 /* 453 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1486 /* 457 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1487 /* 461 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1488 }
1489};
1490
1491
1492#ifdef __GNUC__
1493#pragma GCC diagnostic push
1494#pragma GCC diagnostic ignored "-Woverlength-strings"
1495#endif
1496extern const char R600InstrNameData[] = {
1497 /* 0 */ "CF_TC_R600\000"
1498 /* 11 */ "CF_VC_R600\000"
1499 /* 22 */ "CF_END_R600\000"
1500 /* 34 */ "CF_ELSE_R600\000"
1501 /* 47 */ "CF_PUSH_ELSE_R600\000"
1502 /* 65 */ "CF_CONTINUE_R600\000"
1503 /* 82 */ "FNEG_R600\000"
1504 /* 92 */ "LOOP_BREAK_R600\000"
1505 /* 108 */ "CF_JUMP_R600\000"
1506 /* 121 */ "END_LOOP_R600\000"
1507 /* 135 */ "WHILE_LOOP_R600\000"
1508 /* 151 */ "POP_R600\000"
1509 /* 160 */ "FABS_R600\000"
1510 /* 170 */ "CF_CALL_FS_R600\000"
1511 /* 186 */ "DOT4_r600\000"
1512 /* 196 */ "MULADD_r600\000"
1513 /* 208 */ "LOG_CLAMPED_r600\000"
1514 /* 225 */ "RECIP_CLAMPED_r600\000"
1515 /* 244 */ "RECIPSQRT_CLAMPED_r600\000"
1516 /* 267 */ "CNDE_r600\000"
1517 /* 277 */ "MULADD_IEEE_r600\000"
1518 /* 294 */ "LOG_IEEE_r600\000"
1519 /* 308 */ "RECIP_IEEE_r600\000"
1520 /* 324 */ "EXP_IEEE_r600\000"
1521 /* 338 */ "RECIPSQRT_IEEE_r600\000"
1522 /* 358 */ "CNDGE_r600\000"
1523 /* 369 */ "LSHL_r600\000"
1524 /* 379 */ "SIN_r600\000"
1525 /* 388 */ "ASHR_r600\000"
1526 /* 398 */ "LSHR_r600\000"
1527 /* 408 */ "COS_r600\000"
1528 /* 417 */ "CNDGT_r600\000"
1529 /* 428 */ "MUL_LIT_r600\000"
1530 /* 441 */ "UINT_TO_FLT_r600\000"
1531 /* 458 */ "MULHI_UINT_r600\000"
1532 /* 474 */ "MULLO_UINT_r600\000"
1533 /* 490 */ "FLT_TO_UINT_r600\000"
1534 /* 507 */ "RECIP_UINT_r600\000"
1535 /* 523 */ "MULHI_INT_r600\000"
1536 /* 538 */ "MULLO_INT_r600\000"
1537 /* 553 */ "FLT_TO_INT_r600\000"
1538 /* 569 */ "SIN_r700\000"
1539 /* 578 */ "COS_r700\000"
1540 /* 587 */ "G_FLOG10\000"
1541 /* 596 */ "G_FEXP10\000"
1542 /* 605 */ "SETGE_DX10\000"
1543 /* 616 */ "SETNE_DX10\000"
1544 /* 627 */ "SETE_DX10\000"
1545 /* 637 */ "MIN_DX10\000"
1546 /* 646 */ "SETGT_DX10\000"
1547 /* 657 */ "MAX_DX10\000"
1548 /* 666 */ "INTERP_LOAD_P0\000"
1549 /* 681 */ "RAT_STORE_DWORD32\000"
1550 /* 699 */ "MOV_IMM_F32\000"
1551 /* 711 */ "MOV_IMM_I32\000"
1552 /* 723 */ "FLT16_TO_FLT32\000"
1553 /* 738 */ "CONTINUEC_f32\000"
1554 /* 752 */ "IFC_f32\000"
1555 /* 760 */ "BREAKC_f32\000"
1556 /* 771 */ "BRANCH_COND_f32\000"
1557 /* 787 */ "CONTINUE_LOGICALZ_f32\000"
1558 /* 809 */ "IF_LOGICALZ_f32\000"
1559 /* 825 */ "BREAK_LOGICALZ_f32\000"
1560 /* 844 */ "CONTINUE_LOGICALNZ_f32\000"
1561 /* 867 */ "IF_LOGICALNZ_f32\000"
1562 /* 884 */ "BREAK_LOGICALNZ_f32\000"
1563 /* 904 */ "CONTINUEC_i32\000"
1564 /* 918 */ "IFC_i32\000"
1565 /* 926 */ "BREAKC_i32\000"
1566 /* 937 */ "BRANCH_COND_i32\000"
1567 /* 953 */ "CONTINUE_LOGICALZ_i32\000"
1568 /* 975 */ "IF_LOGICALZ_i32\000"
1569 /* 991 */ "BREAK_LOGICALZ_i32\000"
1570 /* 1010 */ "CONTINUE_LOGICALNZ_i32\000"
1571 /* 1033 */ "IF_LOGICALNZ_i32\000"
1572 /* 1050 */ "BREAK_LOGICALNZ_i32\000"
1573 /* 1070 */ "G_FLOG2\000"
1574 /* 1078 */ "G_FATAN2\000"
1575 /* 1087 */ "G_FEXP2\000"
1576 /* 1095 */ "R600_EXTRACT_ELT_V2\000"
1577 /* 1115 */ "R600_INSERT_ELT_V2\000"
1578 /* 1134 */ "MULHI_UINT_cm24\000"
1579 /* 1150 */ "MULHI_INT_cm24\000"
1580 /* 1165 */ "RAT_STORE_DWORD64\000"
1581 /* 1183 */ "R600_EXTRACT_ELT_V4\000"
1582 /* 1203 */ "R600_INSERT_ELT_V4\000"
1583 /* 1222 */ "DOT_4\000"
1584 /* 1228 */ "FLT32_TO_FLT16\000"
1585 /* 1243 */ "RAT_STORE_DWORD128\000"
1586 /* 1262 */ "G_FMA\000"
1587 /* 1268 */ "G_STRICT_FMA\000"
1588 /* 1281 */ "TEX_SAMPLE_C_LB\000"
1589 /* 1297 */ "TEX_SAMPLE_LB\000"
1590 /* 1311 */ "G_FSUB\000"
1591 /* 1318 */ "G_STRICT_FSUB\000"
1592 /* 1332 */ "G_ATOMICRMW_FSUB\000"
1593 /* 1349 */ "G_SUB\000"
1594 /* 1355 */ "LDS_SUB\000"
1595 /* 1363 */ "G_ATOMICRMW_SUB\000"
1596 /* 1379 */ "G_INTRINSIC\000"
1597 /* 1391 */ "ENDFUNC\000"
1598 /* 1399 */ "G_FPTRUNC\000"
1599 /* 1409 */ "G_INTRINSIC_TRUNC\000"
1600 /* 1427 */ "G_TRUNC\000"
1601 /* 1435 */ "G_BUILD_VECTOR_TRUNC\000"
1602 /* 1456 */ "G_DYN_STACKALLOC\000"
1603 /* 1473 */ "TEX_SAMPLE_C\000"
1604 /* 1486 */ "G_FMAD\000"
1605 /* 1493 */ "G_INDEXED_SEXTLOAD\000"
1606 /* 1512 */ "G_SEXTLOAD\000"
1607 /* 1523 */ "G_INDEXED_ZEXTLOAD\000"
1608 /* 1542 */ "G_ZEXTLOAD\000"
1609 /* 1553 */ "INTERP_VEC_LOAD\000"
1610 /* 1569 */ "G_INDEXED_LOAD\000"
1611 /* 1584 */ "G_LOAD\000"
1612 /* 1591 */ "PAD\000"
1613 /* 1595 */ "G_VECREDUCE_FADD\000"
1614 /* 1612 */ "G_FADD\000"
1615 /* 1619 */ "G_VECREDUCE_SEQ_FADD\000"
1616 /* 1640 */ "G_STRICT_FADD\000"
1617 /* 1654 */ "G_ATOMICRMW_FADD\000"
1618 /* 1671 */ "G_VECREDUCE_ADD\000"
1619 /* 1687 */ "G_ADD\000"
1620 /* 1693 */ "G_PTR_ADD\000"
1621 /* 1703 */ "LDS_ADD\000"
1622 /* 1711 */ "G_ATOMICRMW_ADD\000"
1623 /* 1727 */ "TEX_LD\000"
1624 /* 1734 */ "G_ATOMICRMW_NAND\000"
1625 /* 1751 */ "G_VECREDUCE_AND\000"
1626 /* 1767 */ "G_AND\000"
1627 /* 1773 */ "LDS_AND\000"
1628 /* 1781 */ "G_ATOMICRMW_AND\000"
1629 /* 1797 */ "LIFETIME_END\000"
1630 /* 1810 */ "G_BRCOND\000"
1631 /* 1819 */ "G_ATOMICRMW_USUB_COND\000"
1632 /* 1841 */ "JUMP_COND\000"
1633 /* 1851 */ "G_LLROUND\000"
1634 /* 1861 */ "G_LROUND\000"
1635 /* 1870 */ "G_INTRINSIC_ROUND\000"
1636 /* 1888 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1637 /* 1914 */ "LOAD_STACK_GUARD\000"
1638 /* 1931 */ "TXD\000"
1639 /* 1935 */ "PSEUDO_PROBE\000"
1640 /* 1948 */ "G_SSUBE\000"
1641 /* 1956 */ "G_USUBE\000"
1642 /* 1964 */ "G_FENCE\000"
1643 /* 1972 */ "ARITH_FENCE\000"
1644 /* 1984 */ "REG_SEQUENCE\000"
1645 /* 1997 */ "G_SADDE\000"
1646 /* 2005 */ "G_UADDE\000"
1647 /* 2013 */ "G_GET_FPMODE\000"
1648 /* 2026 */ "G_RESET_FPMODE\000"
1649 /* 2041 */ "G_SET_FPMODE\000"
1650 /* 2054 */ "MUL_IEEE\000"
1651 /* 2063 */ "G_FMINNUM_IEEE\000"
1652 /* 2078 */ "G_FMAXNUM_IEEE\000"
1653 /* 2093 */ "SGE\000"
1654 /* 2097 */ "PRED_SETGE\000"
1655 /* 2108 */ "G_VSCALE\000"
1656 /* 2117 */ "G_JUMP_TABLE\000"
1657 /* 2130 */ "BUNDLE\000"
1658 /* 2137 */ "TEX_SAMPLE\000"
1659 /* 2148 */ "RNDNE\000"
1660 /* 2154 */ "G_MEMCPY_INLINE\000"
1661 /* 2170 */ "RELOC_NONE\000"
1662 /* 2181 */ "SNE\000"
1663 /* 2185 */ "PRED_SETNE\000"
1664 /* 2196 */ "LOCAL_ESCAPE\000"
1665 /* 2209 */ "CF_ALU_PUSH_BEFORE\000"
1666 /* 2228 */ "G_STACKRESTORE\000"
1667 /* 2243 */ "G_INDEXED_STORE\000"
1668 /* 2259 */ "G_STORE\000"
1669 /* 2267 */ "ELSE\000"
1670 /* 2272 */ "G_BITREVERSE\000"
1671 /* 2285 */ "FETCH_CLAUSE\000"
1672 /* 2298 */ "ALU_CLAUSE\000"
1673 /* 2309 */ "FAKE_USE\000"
1674 /* 2318 */ "PRED_SETE\000"
1675 /* 2328 */ "LDS_BYTE_WRITE\000"
1676 /* 2343 */ "MASK_WRITE\000"
1677 /* 2354 */ "LDS_WRITE\000"
1678 /* 2364 */ "LDS_SHORT_WRITE\000"
1679 /* 2380 */ "DBG_VALUE\000"
1680 /* 2390 */ "G_GLOBAL_VALUE\000"
1681 /* 2405 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1682 /* 2428 */ "CONVERGENCECTRL_GLUE\000"
1683 /* 2449 */ "CF_ALU_CONTINUE\000"
1684 /* 2465 */ "G_STACKSAVE\000"
1685 /* 2477 */ "G_MEMMOVE\000"
1686 /* 2487 */ "G_FREEZE\000"
1687 /* 2496 */ "G_FCANONICALIZE\000"
1688 /* 2512 */ "G_FMODF\000"
1689 /* 2520 */ "G_CTLZ_ZERO_UNDEF\000"
1690 /* 2538 */ "G_CTTZ_ZERO_UNDEF\000"
1691 /* 2556 */ "INIT_UNDEF\000"
1692 /* 2567 */ "G_IMPLICIT_DEF\000"
1693 /* 2582 */ "DBG_INSTR_REF\000"
1694 /* 2596 */ "ENDIF\000"
1695 /* 2602 */ "TEX_VTX_CONSTBUF\000"
1696 /* 2619 */ "TEX_VTX_TEXBUF\000"
1697 /* 2634 */ "G_FNEG\000"
1698 /* 2641 */ "EXTRACT_SUBREG\000"
1699 /* 2656 */ "INSERT_SUBREG\000"
1700 /* 2670 */ "G_SEXT_INREG\000"
1701 /* 2683 */ "SUBREG_TO_REG\000"
1702 /* 2697 */ "CF_TC_EG\000"
1703 /* 2706 */ "CF_VC_EG\000"
1704 /* 2715 */ "CF_END_EG\000"
1705 /* 2725 */ "CF_ELSE_EG\000"
1706 /* 2736 */ "CF_CONTINUE_EG\000"
1707 /* 2751 */ "CF_PUSH_EG\000"
1708 /* 2762 */ "LOOP_BREAK_EG\000"
1709 /* 2776 */ "CF_JUMP_EG\000"
1710 /* 2787 */ "END_LOOP_EG\000"
1711 /* 2799 */ "WHILE_LOOP_EG\000"
1712 /* 2813 */ "POP_EG\000"
1713 /* 2820 */ "CF_CALL_FS_EG\000"
1714 /* 2834 */ "G_ATOMIC_CMPXCHG\000"
1715 /* 2851 */ "LDS_WRXCHG\000"
1716 /* 2862 */ "G_ATOMICRMW_XCHG\000"
1717 /* 2879 */ "G_GET_ROUNDING\000"
1718 /* 2894 */ "G_SET_ROUNDING\000"
1719 /* 2909 */ "G_FLOG\000"
1720 /* 2916 */ "G_VAARG\000"
1721 /* 2924 */ "PREALLOCATED_ARG\000"
1722 /* 2941 */ "TEX_SAMPLE_C_G\000"
1723 /* 2956 */ "TEX_SAMPLE_G\000"
1724 /* 2969 */ "BRANCH\000"
1725 /* 2976 */ "G_PREFETCH\000"
1726 /* 2987 */ "ENDSWITCH\000"
1727 /* 2997 */ "G_SMULH\000"
1728 /* 3005 */ "G_UMULH\000"
1729 /* 3013 */ "G_FTANH\000"
1730 /* 3021 */ "G_FSINH\000"
1731 /* 3029 */ "G_FCOSH\000"
1732 /* 3037 */ "TEX_GET_GRADIENTS_H\000"
1733 /* 3057 */ "TEX_SET_GRADIENTS_H\000"
1734 /* 3077 */ "DBG_PHI\000"
1735 /* 3085 */ "G_FPTOSI\000"
1736 /* 3094 */ "G_FPTOUI\000"
1737 /* 3103 */ "G_FPOWI\000"
1738 /* 3111 */ "CF_ALU_BREAK\000"
1739 /* 3124 */ "COPY_LANEMASK\000"
1740 /* 3138 */ "G_PTRMASK\000"
1741 /* 3148 */ "GC_LABEL\000"
1742 /* 3157 */ "DBG_LABEL\000"
1743 /* 3167 */ "EH_LABEL\000"
1744 /* 3176 */ "ANNOTATION_LABEL\000"
1745 /* 3193 */ "ICALL_BRANCH_FUNNEL\000"
1746 /* 3213 */ "G_FSHL\000"
1747 /* 3220 */ "G_SHL\000"
1748 /* 3226 */ "G_FCEIL\000"
1749 /* 3234 */ "G_SAVGCEIL\000"
1750 /* 3245 */ "G_UAVGCEIL\000"
1751 /* 3256 */ "PATCHABLE_TAIL_CALL\000"
1752 /* 3276 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1753 /* 3303 */ "PATCHABLE_EVENT_CALL\000"
1754 /* 3324 */ "FENTRY_CALL\000"
1755 /* 3336 */ "KILL\000"
1756 /* 3341 */ "G_CONSTANT_POOL\000"
1757 /* 3357 */ "G_ROTL\000"
1758 /* 3364 */ "G_VECREDUCE_FMUL\000"
1759 /* 3381 */ "G_FMUL\000"
1760 /* 3388 */ "G_VECREDUCE_SEQ_FMUL\000"
1761 /* 3409 */ "G_STRICT_FMUL\000"
1762 /* 3423 */ "G_VECREDUCE_MUL\000"
1763 /* 3439 */ "G_MUL\000"
1764 /* 3445 */ "TEX_SAMPLE_C_L\000"
1765 /* 3460 */ "TEX_SAMPLE_L\000"
1766 /* 3473 */ "CF_END_CM\000"
1767 /* 3483 */ "G_FREM\000"
1768 /* 3490 */ "G_STRICT_FREM\000"
1769 /* 3504 */ "G_SREM\000"
1770 /* 3511 */ "G_UREM\000"
1771 /* 3518 */ "G_SDIVREM\000"
1772 /* 3528 */ "G_UDIVREM\000"
1773 /* 3538 */ "INLINEASM\000"
1774 /* 3548 */ "G_VECREDUCE_FMINIMUM\000"
1775 /* 3569 */ "G_FMINIMUM\000"
1776 /* 3580 */ "G_ATOMICRMW_FMINIMUM\000"
1777 /* 3601 */ "G_VECREDUCE_FMAXIMUM\000"
1778 /* 3622 */ "G_FMAXIMUM\000"
1779 /* 3633 */ "G_ATOMICRMW_FMAXIMUM\000"
1780 /* 3654 */ "G_FMINIMUMNUM\000"
1781 /* 3668 */ "G_FMAXIMUMNUM\000"
1782 /* 3682 */ "G_FMINNUM\000"
1783 /* 3692 */ "G_FMAXNUM\000"
1784 /* 3702 */ "G_FATAN\000"
1785 /* 3710 */ "G_FTAN\000"
1786 /* 3717 */ "G_INTRINSIC_ROUNDEVEN\000"
1787 /* 3739 */ "G_ASSERT_ALIGN\000"
1788 /* 3754 */ "G_FCOPYSIGN\000"
1789 /* 3766 */ "DUMMY_CHAIN\000"
1790 /* 3778 */ "ENDMAIN\000"
1791 /* 3786 */ "G_VECREDUCE_FMIN\000"
1792 /* 3803 */ "G_ATOMICRMW_FMIN\000"
1793 /* 3820 */ "G_VECREDUCE_SMIN\000"
1794 /* 3837 */ "G_SMIN\000"
1795 /* 3844 */ "G_VECREDUCE_UMIN\000"
1796 /* 3861 */ "G_UMIN\000"
1797 /* 3868 */ "G_ATOMICRMW_UMIN\000"
1798 /* 3885 */ "G_ATOMICRMW_MIN\000"
1799 /* 3901 */ "G_FASIN\000"
1800 /* 3909 */ "G_FSIN\000"
1801 /* 3916 */ "CFI_INSTRUCTION\000"
1802 /* 3932 */ "RETURN\000"
1803 /* 3939 */ "RAT_ATOMIC_RSUB_RTN\000"
1804 /* 3959 */ "RAT_ATOMIC_SUB_RTN\000"
1805 /* 3978 */ "RAT_ATOMIC_ADD_RTN\000"
1806 /* 3997 */ "RAT_ATOMIC_AND_RTN\000"
1807 /* 4016 */ "RAT_ATOMIC_XOR_RTN\000"
1808 /* 4035 */ "RAT_ATOMIC_OR_RTN\000"
1809 /* 4053 */ "RAT_ATOMIC_DEC_UINT_RTN\000"
1810 /* 4077 */ "RAT_ATOMIC_INC_UINT_RTN\000"
1811 /* 4101 */ "RAT_ATOMIC_MIN_UINT_RTN\000"
1812 /* 4125 */ "RAT_ATOMIC_MAX_UINT_RTN\000"
1813 /* 4149 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\000"
1814 /* 4176 */ "RAT_ATOMIC_XCHG_INT_RTN\000"
1815 /* 4200 */ "RAT_ATOMIC_MIN_INT_RTN\000"
1816 /* 4223 */ "RAT_ATOMIC_MAX_INT_RTN\000"
1817 /* 4246 */ "RETDYN\000"
1818 /* 4253 */ "G_SSUBO\000"
1819 /* 4261 */ "G_USUBO\000"
1820 /* 4269 */ "G_SADDO\000"
1821 /* 4277 */ "G_UADDO\000"
1822 /* 4285 */ "TEX_GET_TEXTURE_RESINFO\000"
1823 /* 4309 */ "JUMP_TABLE_DEBUG_INFO\000"
1824 /* 4331 */ "G_SMULO\000"
1825 /* 4339 */ "G_UMULO\000"
1826 /* 4347 */ "G_BZERO\000"
1827 /* 4355 */ "STACKMAP\000"
1828 /* 4364 */ "G_DEBUGTRAP\000"
1829 /* 4376 */ "G_UBSANTRAP\000"
1830 /* 4388 */ "G_TRAP\000"
1831 /* 4395 */ "G_ATOMICRMW_UDEC_WRAP\000"
1832 /* 4417 */ "G_ATOMICRMW_UINC_WRAP\000"
1833 /* 4439 */ "G_BSWAP\000"
1834 /* 4447 */ "G_SITOFP\000"
1835 /* 4456 */ "G_UITOFP\000"
1836 /* 4465 */ "G_FCMP\000"
1837 /* 4472 */ "G_ICMP\000"
1838 /* 4479 */ "G_SCMP\000"
1839 /* 4486 */ "G_UCMP\000"
1840 /* 4493 */ "JUMP\000"
1841 /* 4498 */ "ENDLOOP\000"
1842 /* 4506 */ "WHILELOOP\000"
1843 /* 4516 */ "CONVERGENCECTRL_LOOP\000"
1844 /* 4537 */ "G_CTPOP\000"
1845 /* 4545 */ "PATCHABLE_OP\000"
1846 /* 4558 */ "FAULTING_OP\000"
1847 /* 4570 */ "PREALLOCATED_SETUP\000"
1848 /* 4589 */ "G_FLDEXP\000"
1849 /* 4598 */ "G_STRICT_FLDEXP\000"
1850 /* 4614 */ "G_FEXP\000"
1851 /* 4621 */ "G_FFREXP\000"
1852 /* 4630 */ "G_BR\000"
1853 /* 4635 */ "INLINEASM_BR\000"
1854 /* 4648 */ "G_BLOCK_ADDR\000"
1855 /* 4661 */ "MOV_IMM_GLOBAL_ADDR\000"
1856 /* 4681 */ "MEMBARRIER\000"
1857 /* 4692 */ "G_CONSTANT_FOLD_BARRIER\000"
1858 /* 4716 */ "GROUP_BARRIER\000"
1859 /* 4730 */ "CF_ALU_ELSE_AFTER\000"
1860 /* 4748 */ "CF_ALU_POP_AFTER\000"
1861 /* 4765 */ "PATCHABLE_FUNCTION_ENTER\000"
1862 /* 4790 */ "G_READCYCLECOUNTER\000"
1863 /* 4809 */ "G_READSTEADYCOUNTER\000"
1864 /* 4829 */ "G_READ_REGISTER\000"
1865 /* 4845 */ "G_WRITE_REGISTER\000"
1866 /* 4862 */ "G_ASHR\000"
1867 /* 4869 */ "G_FSHR\000"
1868 /* 4876 */ "G_LSHR\000"
1869 /* 4883 */ "CONVERGENCECTRL_ANCHOR\000"
1870 /* 4906 */ "RAT_MSKOR\000"
1871 /* 4916 */ "G_FFLOOR\000"
1872 /* 4925 */ "G_SAVGFLOOR\000"
1873 /* 4937 */ "G_UAVGFLOOR\000"
1874 /* 4949 */ "G_EXTRACT_SUBVECTOR\000"
1875 /* 4969 */ "G_INSERT_SUBVECTOR\000"
1876 /* 4988 */ "G_BUILD_VECTOR\000"
1877 /* 5003 */ "G_SHUFFLE_VECTOR\000"
1878 /* 5020 */ "G_STEP_VECTOR\000"
1879 /* 5034 */ "G_SPLAT_VECTOR\000"
1880 /* 5049 */ "G_VECREDUCE_XOR\000"
1881 /* 5065 */ "G_XOR\000"
1882 /* 5071 */ "LDS_XOR\000"
1883 /* 5079 */ "G_ATOMICRMW_XOR\000"
1884 /* 5095 */ "G_VECREDUCE_OR\000"
1885 /* 5110 */ "G_OR\000"
1886 /* 5115 */ "LDS_OR\000"
1887 /* 5122 */ "G_ATOMICRMW_OR\000"
1888 /* 5137 */ "G_ROTR\000"
1889 /* 5144 */ "TEX_LDPTR\000"
1890 /* 5154 */ "G_INTTOPTR\000"
1891 /* 5165 */ "G_FABS\000"
1892 /* 5172 */ "G_ABS\000"
1893 /* 5178 */ "G_ABDS\000"
1894 /* 5185 */ "G_UNMERGE_VALUES\000"
1895 /* 5202 */ "G_MERGE_VALUES\000"
1896 /* 5217 */ "LITERALS\000"
1897 /* 5226 */ "G_CTLS\000"
1898 /* 5233 */ "G_FACOS\000"
1899 /* 5241 */ "G_FCOS\000"
1900 /* 5248 */ "G_FSINCOS\000"
1901 /* 5258 */ "G_CONCAT_VECTORS\000"
1902 /* 5275 */ "COPY_TO_REGCLASS\000"
1903 /* 5292 */ "G_IS_FPCLASS\000"
1904 /* 5305 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1905 /* 5335 */ "G_VECTOR_COMPRESS\000"
1906 /* 5353 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1907 /* 5380 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1908 /* 5418 */ "G_TRUNC_SSAT_S\000"
1909 /* 5433 */ "G_SSUBSAT\000"
1910 /* 5443 */ "G_USUBSAT\000"
1911 /* 5453 */ "G_SADDSAT\000"
1912 /* 5463 */ "G_UADDSAT\000"
1913 /* 5473 */ "G_SSHLSAT\000"
1914 /* 5483 */ "G_USHLSAT\000"
1915 /* 5493 */ "G_SMULFIXSAT\000"
1916 /* 5506 */ "G_UMULFIXSAT\000"
1917 /* 5519 */ "G_SDIVFIXSAT\000"
1918 /* 5532 */ "G_UDIVFIXSAT\000"
1919 /* 5545 */ "G_ATOMICRMW_USUB_SAT\000"
1920 /* 5566 */ "G_FPTOSI_SAT\000"
1921 /* 5579 */ "G_FPTOUI_SAT\000"
1922 /* 5592 */ "FRACT\000"
1923 /* 5598 */ "G_EXTRACT\000"
1924 /* 5608 */ "G_SELECT\000"
1925 /* 5617 */ "G_BRINDIRECT\000"
1926 /* 5630 */ "RAT_ATOMIC_RSUB_NORET\000"
1927 /* 5652 */ "RAT_ATOMIC_SUB_NORET\000"
1928 /* 5673 */ "RAT_ATOMIC_ADD_NORET\000"
1929 /* 5694 */ "RAT_ATOMIC_AND_NORET\000"
1930 /* 5715 */ "RAT_ATOMIC_XOR_NORET\000"
1931 /* 5736 */ "RAT_ATOMIC_OR_NORET\000"
1932 /* 5756 */ "RAT_ATOMIC_DEC_UINT_NORET\000"
1933 /* 5782 */ "RAT_ATOMIC_INC_UINT_NORET\000"
1934 /* 5808 */ "RAT_ATOMIC_MIN_UINT_NORET\000"
1935 /* 5834 */ "RAT_ATOMIC_MAX_UINT_NORET\000"
1936 /* 5860 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\000"
1937 /* 5889 */ "RAT_ATOMIC_XCHG_INT_NORET\000"
1938 /* 5915 */ "RAT_ATOMIC_MIN_INT_NORET\000"
1939 /* 5940 */ "RAT_ATOMIC_MAX_INT_NORET\000"
1940 /* 5965 */ "LDS_SUB_RET\000"
1941 /* 5977 */ "LDS_UBYTE_READ_RET\000"
1942 /* 5996 */ "LDS_BYTE_READ_RET\000"
1943 /* 6014 */ "LDS_READ_RET\000"
1944 /* 6027 */ "LDS_USHORT_READ_RET\000"
1945 /* 6047 */ "LDS_SHORT_READ_RET\000"
1946 /* 6066 */ "LDS_ADD_RET\000"
1947 /* 6078 */ "LDS_AND_RET\000"
1948 /* 6090 */ "PATCHABLE_RET\000"
1949 /* 6104 */ "LDS_WRXCHG_RET\000"
1950 /* 6119 */ "LDS_XOR_RET\000"
1951 /* 6131 */ "LDS_OR_RET\000"
1952 /* 6142 */ "LDS_MIN_UINT_RET\000"
1953 /* 6159 */ "LDS_MAX_UINT_RET\000"
1954 /* 6176 */ "LDS_MIN_INT_RET\000"
1955 /* 6192 */ "LDS_MAX_INT_RET\000"
1956 /* 6208 */ "LDS_CMPST_RET\000"
1957 /* 6222 */ "G_MEMSET\000"
1958 /* 6231 */ "IF_PREDICATE_SET\000"
1959 /* 6248 */ "KILLGT\000"
1960 /* 6255 */ "SGT\000"
1961 /* 6259 */ "PRED_SETGT\000"
1962 /* 6270 */ "PATCHABLE_FUNCTION_EXIT\000"
1963 /* 6294 */ "G_BRJT\000"
1964 /* 6301 */ "G_EXTRACT_VECTOR_ELT\000"
1965 /* 6322 */ "G_INSERT_VECTOR_ELT\000"
1966 /* 6342 */ "DEFAULT\000"
1967 /* 6350 */ "G_FCONSTANT\000"
1968 /* 6362 */ "G_CONSTANT\000"
1969 /* 6373 */ "G_INTRINSIC_CONVERGENT\000"
1970 /* 6396 */ "STATEPOINT\000"
1971 /* 6407 */ "PATCHPOINT\000"
1972 /* 6418 */ "G_PTRTOINT\000"
1973 /* 6429 */ "G_FRINT\000"
1974 /* 6437 */ "G_INTRINSIC_LLRINT\000"
1975 /* 6456 */ "G_INTRINSIC_LRINT\000"
1976 /* 6474 */ "SUBB_UINT\000"
1977 /* 6484 */ "ADDC_UINT\000"
1978 /* 6494 */ "SETGE_UINT\000"
1979 /* 6505 */ "FFBH_UINT\000"
1980 /* 6515 */ "LDS_MIN_UINT\000"
1981 /* 6528 */ "SETGT_UINT\000"
1982 /* 6539 */ "LDS_MAX_UINT\000"
1983 /* 6552 */ "G_FNEARBYINT\000"
1984 /* 6565 */ "SUB_INT\000"
1985 /* 6573 */ "ADD_INT\000"
1986 /* 6581 */ "AND_INT\000"
1987 /* 6589 */ "CNDE_INT\000"
1988 /* 6598 */ "CNDGE_INT\000"
1989 /* 6608 */ "PRED_SETGE_INT\000"
1990 /* 6623 */ "PRED_SETNE_INT\000"
1991 /* 6638 */ "PRED_SETE_INT\000"
1992 /* 6652 */ "FFBL_INT\000"
1993 /* 6661 */ "LDS_MIN_INT\000"
1994 /* 6673 */ "XOR_INT\000"
1995 /* 6681 */ "CNDGT_INT\000"
1996 /* 6691 */ "PRED_SETGT_INT\000"
1997 /* 6706 */ "BCNT_INT\000"
1998 /* 6715 */ "NOT_INT\000"
1999 /* 6723 */ "LDS_MAX_INT\000"
2000 /* 6735 */ "G_VASTART\000"
2001 /* 6745 */ "LIFETIME_START\000"
2002 /* 6760 */ "G_INVOKE_REGION_START\000"
2003 /* 6782 */ "G_INSERT\000"
2004 /* 6791 */ "G_FSQRT\000"
2005 /* 6799 */ "G_STRICT_FSQRT\000"
2006 /* 6814 */ "G_BITCAST\000"
2007 /* 6824 */ "G_ADDRSPACE_CAST\000"
2008 /* 6841 */ "DBG_VALUE_LIST\000"
2009 /* 6856 */ "LDS_CMPST\000"
2010 /* 6866 */ "G_FPEXT\000"
2011 /* 6874 */ "G_SEXT\000"
2012 /* 6881 */ "G_ASSERT_SEXT\000"
2013 /* 6895 */ "G_ANYEXT\000"
2014 /* 6904 */ "G_ZEXT\000"
2015 /* 6911 */ "G_ASSERT_ZEXT\000"
2016 /* 6925 */ "G_ABDU\000"
2017 /* 6932 */ "CF_ALU\000"
2018 /* 6939 */ "G_TRUNC_SSAT_U\000"
2019 /* 6954 */ "G_TRUNC_USAT_U\000"
2020 /* 6969 */ "G_FDIV\000"
2021 /* 6976 */ "G_STRICT_FDIV\000"
2022 /* 6990 */ "G_SDIV\000"
2023 /* 6997 */ "G_UDIV\000"
2024 /* 7004 */ "G_GET_FPENV\000"
2025 /* 7016 */ "G_RESET_FPENV\000"
2026 /* 7030 */ "G_SET_FPENV\000"
2027 /* 7042 */ "MOV\000"
2028 /* 7046 */ "TEX_GET_GRADIENTS_V\000"
2029 /* 7066 */ "TEX_SET_GRADIENTS_V\000"
2030 /* 7086 */ "TXD_SHADOW\000"
2031 /* 7097 */ "G_FPOW\000"
2032 /* 7104 */ "INTERP_ZW\000"
2033 /* 7114 */ "INTERP_PAIR_ZW\000"
2034 /* 7129 */ "G_VECREDUCE_FMAX\000"
2035 /* 7146 */ "G_ATOMICRMW_FMAX\000"
2036 /* 7163 */ "G_VECREDUCE_SMAX\000"
2037 /* 7180 */ "G_SMAX\000"
2038 /* 7187 */ "G_VECREDUCE_UMAX\000"
2039 /* 7204 */ "G_UMAX\000"
2040 /* 7211 */ "G_ATOMICRMW_UMAX\000"
2041 /* 7228 */ "G_ATOMICRMW_MAX\000"
2042 /* 7244 */ "G_FRAME_INDEX\000"
2043 /* 7258 */ "G_SBFX\000"
2044 /* 7265 */ "G_UBFX\000"
2045 /* 7272 */ "G_SMULFIX\000"
2046 /* 7282 */ "G_UMULFIX\000"
2047 /* 7292 */ "G_SDIVFIX\000"
2048 /* 7302 */ "G_UDIVFIX\000"
2049 /* 7312 */ "PRED_X\000"
2050 /* 7319 */ "G_MEMCPY\000"
2051 /* 7328 */ "CONST_COPY\000"
2052 /* 7339 */ "CONVERGENCECTRL_ENTRY\000"
2053 /* 7361 */ "INTERP_XY\000"
2054 /* 7371 */ "INTERP_PAIR_XY\000"
2055 /* 7386 */ "G_CTLZ\000"
2056 /* 7393 */ "G_CTTZ\000"
2057 /* 7400 */ "R600_RegisterLoad\000"
2058 /* 7418 */ "R600_RegisterStore\000"
2059 /* 7437 */ "R600_ExportBuf\000"
2060 /* 7452 */ "EG_ExportBuf\000"
2061 /* 7465 */ "VTX_READ_32_eg\000"
2062 /* 7480 */ "RAT_WRITE_CACHELESS_32_eg\000"
2063 /* 7506 */ "MULADD_UINT24_eg\000"
2064 /* 7523 */ "MULHI_UINT24_eg\000"
2065 /* 7539 */ "MUL_UINT24_eg\000"
2066 /* 7553 */ "VTX_READ_64_eg\000"
2067 /* 7568 */ "RAT_WRITE_CACHELESS_64_eg\000"
2068 /* 7594 */ "DOT4_eg\000"
2069 /* 7602 */ "VTX_READ_16_eg\000"
2070 /* 7617 */ "VTX_READ_128_eg\000"
2071 /* 7633 */ "RAT_WRITE_CACHELESS_128_eg\000"
2072 /* 7660 */ "VTX_READ_8_eg\000"
2073 /* 7674 */ "FMA_eg\000"
2074 /* 7681 */ "MULADD_eg\000"
2075 /* 7691 */ "LOG_CLAMPED_eg\000"
2076 /* 7706 */ "RECIP_CLAMPED_eg\000"
2077 /* 7723 */ "RECIPSQRT_CLAMPED_eg\000"
2078 /* 7744 */ "RAT_STORE_TYPED_eg\000"
2079 /* 7763 */ "CNDE_eg\000"
2080 /* 7771 */ "MULADD_IEEE_eg\000"
2081 /* 7786 */ "LOG_IEEE_eg\000"
2082 /* 7798 */ "RECIP_IEEE_eg\000"
2083 /* 7812 */ "EXP_IEEE_eg\000"
2084 /* 7824 */ "RECIPSQRT_IEEE_eg\000"
2085 /* 7842 */ "CNDGE_eg\000"
2086 /* 7851 */ "LSHL_eg\000"
2087 /* 7859 */ "SIN_eg\000"
2088 /* 7866 */ "ASHR_eg\000"
2089 /* 7874 */ "LSHR_eg\000"
2090 /* 7882 */ "COS_eg\000"
2091 /* 7889 */ "CNDGT_eg\000"
2092 /* 7898 */ "MUL_LIT_eg\000"
2093 /* 7909 */ "UINT_TO_FLT_eg\000"
2094 /* 7924 */ "BFE_UINT_eg\000"
2095 /* 7936 */ "MULHI_UINT_eg\000"
2096 /* 7950 */ "MULLO_UINT_eg\000"
2097 /* 7964 */ "FLT_TO_UINT_eg\000"
2098 /* 7979 */ "RECIP_UINT_eg\000"
2099 /* 7993 */ "MOVA_INT_eg\000"
2100 /* 8005 */ "BFE_INT_eg\000"
2101 /* 8016 */ "BFI_INT_eg\000"
2102 /* 8027 */ "MULHI_INT_eg\000"
2103 /* 8040 */ "BFM_INT_eg\000"
2104 /* 8051 */ "BIT_ALIGN_INT_eg\000"
2105 /* 8068 */ "MULLO_INT_eg\000"
2106 /* 8081 */ "FLT_TO_INT_eg\000"
2107 /* 8095 */ "CUBE_r600_real\000"
2108 /* 8110 */ "CUBE_eg_real\000"
2109 /* 8123 */ "VTX_READ_32_cm\000"
2110 /* 8138 */ "MULADD_INT24_cm\000"
2111 /* 8154 */ "MUL_INT24_cm\000"
2112 /* 8167 */ "VTX_READ_64_cm\000"
2113 /* 8182 */ "VTX_READ_16_cm\000"
2114 /* 8197 */ "VTX_READ_128_cm\000"
2115 /* 8213 */ "VTX_READ_8_cm\000"
2116 /* 8227 */ "RECIP_CLAMPED_cm\000"
2117 /* 8244 */ "RECIPSQRT_CLAMPED_cm\000"
2118 /* 8265 */ "RAT_STORE_TYPED_cm\000"
2119 /* 8284 */ "LOG_IEEE_cm\000"
2120 /* 8296 */ "RECIP_IEEE_cm\000"
2121 /* 8310 */ "EXP_IEEE_cm\000"
2122 /* 8322 */ "RECIPSQRT_IEEE_cm\000"
2123 /* 8340 */ "SIN_cm\000"
2124 /* 8347 */ "COS_cm\000"
2125 /* 8354 */ "MULHI_UINT_cm\000"
2126 /* 8368 */ "MULLO_UINT_cm\000"
2127 /* 8382 */ "MULHI_INT_cm\000"
2128 /* 8395 */ "MULLO_INT_cm\000"
2129 /* 8408 */ "CUBE_r600_pseudo\000"
2130 /* 8425 */ "CUBE_eg_pseudo\000"
2131 /* 8440 */ "R600_ExportSwz\000"
2132 /* 8455 */ "EG_ExportSwz\000"
2133};
2134#ifdef __GNUC__
2135#pragma GCC diagnostic pop
2136#endif
2137
2138extern const unsigned R600InstrNameIndices[] = {
2139 3081U, 3538U, 4635U, 3916U, 3167U, 3148U, 3176U, 3336U,
2140 2641U, 2656U, 2569U, 2556U, 2683U, 5275U, 2380U, 6841U,
2141 2582U, 3077U, 3157U, 1984U, 7334U, 3124U, 2130U, 6745U,
2142 1797U, 1935U, 1972U, 4355U, 3324U, 6407U, 1914U, 4570U,
2143 2924U, 6396U, 2196U, 4558U, 4545U, 4765U, 6090U, 6270U,
2144 3256U, 3303U, 3276U, 3193U, 2309U, 4681U, 4309U, 2170U,
2145 7339U, 4883U, 4516U, 2428U, 6881U, 6911U, 3739U, 1687U,
2146 1349U, 3439U, 6990U, 6997U, 3504U, 3511U, 3518U, 3528U,
2147 1767U, 5110U, 5065U, 5178U, 6925U, 4937U, 3245U, 4925U,
2148 3234U, 2567U, 3079U, 7244U, 2390U, 2405U, 3341U, 5598U,
2149 5185U, 6782U, 5202U, 4988U, 1435U, 5258U, 6418U, 5154U,
2150 6814U, 2487U, 4692U, 1888U, 1409U, 1870U, 6456U, 6437U,
2151 3717U, 4790U, 4809U, 1584U, 1512U, 1542U, 1569U, 1493U,
2152 1523U, 2259U, 2243U, 5305U, 2834U, 2862U, 1711U, 1363U,
2153 1781U, 1734U, 5122U, 5079U, 7228U, 3885U, 7211U, 3868U,
2154 1654U, 1332U, 7146U, 3803U, 3633U, 3580U, 4417U, 4395U,
2155 1819U, 5545U, 1964U, 2976U, 1810U, 5617U, 6760U, 1379U,
2156 5353U, 6373U, 5380U, 6895U, 1427U, 5418U, 6939U, 6954U,
2157 6362U, 6350U, 6735U, 2916U, 6874U, 2670U, 6904U, 3220U,
2158 4876U, 4862U, 3213U, 4869U, 5137U, 3357U, 4472U, 4465U,
2159 4479U, 4486U, 5608U, 4277U, 2005U, 4261U, 1956U, 4269U,
2160 1997U, 4253U, 1948U, 4339U, 4331U, 3005U, 2997U, 5463U,
2161 5453U, 5443U, 5433U, 5483U, 5473U, 7272U, 7282U, 5493U,
2162 5506U, 7292U, 7302U, 5519U, 5532U, 1612U, 1311U, 3381U,
2163 1262U, 1486U, 6969U, 3483U, 2512U, 7097U, 3103U, 4614U,
2164 1087U, 596U, 2909U, 1070U, 587U, 4589U, 4621U, 2634U,
2165 6866U, 1399U, 3085U, 3094U, 4447U, 4456U, 5566U, 5579U,
2166 5165U, 3754U, 5292U, 2496U, 3682U, 3692U, 2063U, 2078U,
2167 3569U, 3622U, 3654U, 3668U, 7004U, 7030U, 7016U, 2013U,
2168 2041U, 2026U, 2879U, 2894U, 1693U, 3138U, 3837U, 7180U,
2169 3861U, 7204U, 5172U, 1861U, 1851U, 4630U, 6294U, 2108U,
2170 4969U, 4949U, 6322U, 6301U, 5003U, 5034U, 5020U, 5335U,
2171 7393U, 2538U, 7386U, 2520U, 5226U, 4537U, 4439U, 2272U,
2172 3226U, 5241U, 3909U, 5248U, 3710U, 5233U, 3901U, 3702U,
2173 1078U, 3029U, 3021U, 3013U, 6791U, 4916U, 6429U, 6552U,
2174 6824U, 4648U, 2117U, 1456U, 2465U, 2228U, 1640U, 1318U,
2175 3409U, 6976U, 3490U, 1268U, 6799U, 4598U, 4829U, 4845U,
2176 7319U, 2154U, 2477U, 6222U, 4347U, 4388U, 4364U, 4376U,
2177 1619U, 3388U, 1595U, 3364U, 7129U, 3786U, 3601U, 3548U,
2178 1671U, 3423U, 1751U, 5095U, 5049U, 7163U, 3820U, 7187U,
2179 3844U, 7258U, 7265U, 2969U, 771U, 937U, 3118U, 760U,
2180 926U, 884U, 1050U, 825U, 991U, 7328U, 2456U, 738U,
2181 904U, 844U, 1010U, 787U, 953U, 8425U, 8408U, 6342U,
2182 1222U, 3766U, 2267U, 1806U, 1391U, 2596U, 4498U, 3778U,
2183 2987U, 160U, 82U, 1394U, 752U, 918U, 867U, 1033U,
2184 809U, 975U, 6231U, 4493U, 1841U, 2343U, 699U, 4661U,
2185 711U, 7312U, 1095U, 1183U, 1115U, 1203U, 7400U, 7418U,
2186 4246U, 3932U, 1931U, 7086U, 4506U, 1608U, 6484U, 6573U,
2187 2298U, 6581U, 7866U, 388U, 6706U, 8005U, 7924U, 8016U,
2188 8040U, 8051U, 3229U, 6932U, 3111U, 2449U, 4730U, 4748U,
2189 2209U, 2820U, 170U, 2736U, 65U, 2725U, 34U, 3473U,
2190 2715U, 22U, 2776U, 108U, 2751U, 47U, 2697U, 0U,
2191 2706U, 11U, 6589U, 7763U, 267U, 6598U, 7842U, 358U,
2192 6681U, 7889U, 417U, 8347U, 7882U, 408U, 578U, 8110U,
2193 8095U, 7594U, 186U, 7452U, 8455U, 2787U, 121U, 8310U,
2194 7812U, 324U, 2285U, 6505U, 6652U, 4919U, 723U, 1228U,
2195 8081U, 553U, 7964U, 490U, 7674U, 5592U, 4716U, 666U,
2196 7371U, 7114U, 1553U, 7361U, 7104U, 7910U, 442U, 6248U,
2197 1703U, 6066U, 1773U, 6078U, 5996U, 2328U, 6856U, 6208U,
2198 6723U, 6192U, 6539U, 6159U, 6661U, 6176U, 6515U, 6142U,
2199 5115U, 6131U, 6014U, 6047U, 2364U, 1355U, 5965U, 5977U,
2200 6027U, 2354U, 2851U, 6104U, 5071U, 6119U, 5217U, 7691U,
2201 208U, 8284U, 7786U, 294U, 2762U, 92U, 7851U, 369U,
2202 7874U, 398U, 7142U, 657U, 6727U, 6543U, 3799U, 637U,
2203 6665U, 6519U, 7042U, 7993U, 3377U, 7771U, 277U, 8138U,
2204 7506U, 7681U, 196U, 8382U, 1150U, 8027U, 523U, 7523U,
2205 8354U, 1134U, 7936U, 458U, 8395U, 8068U, 538U, 8368U,
2206 7950U, 474U, 2054U, 8154U, 7898U, 428U, 7539U, 6715U,
2207 6674U, 1591U, 2813U, 151U, 2318U, 6638U, 2097U, 6608U,
2208 6259U, 6691U, 2185U, 6623U, 7437U, 8440U, 5673U, 3978U,
2209 5694U, 3997U, 5860U, 4149U, 5756U, 4053U, 5782U, 4077U,
2210 5940U, 4223U, 5834U, 4125U, 5915U, 4200U, 5808U, 4101U,
2211 5736U, 4035U, 5630U, 3939U, 5652U, 3959U, 5889U, 4176U,
2212 5715U, 4016U, 4906U, 1243U, 681U, 1165U, 8265U, 7744U,
2213 7633U, 7480U, 7568U, 8244U, 7723U, 244U, 8322U, 7824U,
2214 338U, 8227U, 7706U, 225U, 8296U, 7798U, 308U, 7979U,
2215 507U, 2148U, 2323U, 627U, 6643U, 605U, 6613U, 6494U,
2216 646U, 6696U, 6528U, 616U, 6628U, 2093U, 6255U, 8340U,
2217 7859U, 379U, 569U, 2181U, 6474U, 6565U, 3037U, 7046U,
2218 4285U, 1727U, 5144U, 2137U, 1473U, 2941U, 3445U, 1281U,
2219 2956U, 3460U, 1297U, 3057U, 7066U, 2602U, 2619U, 1403U,
2220 7909U, 441U, 8197U, 7617U, 8182U, 7602U, 8123U, 7465U,
2221 8167U, 7553U, 8213U, 7660U, 2799U, 135U, 6673U,
2222};
2223
2224static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
2225 II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 663, nullptr, 0);
2226}
2227
2228
2229} // namespace llvm
2230
2231#endif // GET_INSTRINFO_MC_DESC
2232
2233#ifdef GET_INSTRINFO_HEADER
2234#undef GET_INSTRINFO_HEADER
2235
2236namespace llvm {
2237
2238struct R600GenInstrInfo : public TargetInstrInfo {
2239 explicit R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2240 ~R600GenInstrInfo() override = default;
2241};
2242
2243} // namespace llvm
2244
2245namespace llvm::R600 {
2246
2247constexpr unsigned SUBOP_FRAMEri_ptr = 0;
2248constexpr unsigned SUBOP_FRAMEri_index = 1;
2249constexpr unsigned SUBOP_MEMrr_ptr = 0;
2250constexpr unsigned SUBOP_MEMrr_index = 1;
2251constexpr unsigned SUBOP_MEMxi_ptr = 0;
2252constexpr unsigned SUBOP_MEMxi_index = 1;
2253
2254} // namespace llvm::R600
2255
2256#endif // GET_INSTRINFO_HEADER
2257
2258#ifdef GET_INSTRINFO_HELPER_DECLS
2259#undef GET_INSTRINFO_HELPER_DECLS
2260
2261
2262#endif // GET_INSTRINFO_HELPER_DECLS
2263
2264#ifdef GET_INSTRINFO_HELPERS
2265#undef GET_INSTRINFO_HELPERS
2266
2267
2268#endif // GET_INSTRINFO_HELPERS
2269
2270#ifdef GET_INSTRINFO_CTOR_DTOR
2271#undef GET_INSTRINFO_CTOR_DTOR
2272
2273namespace llvm {
2274
2275extern const R600InstrTable R600Descs;
2276extern const unsigned R600InstrNameIndices[];
2277extern const char R600InstrNameData[];
2278R600GenInstrInfo::R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2279 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2280 InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 663);
2281}
2282
2283} // namespace llvm
2284
2285#endif // GET_INSTRINFO_CTOR_DTOR
2286
2287#ifdef GET_INSTRINFO_OPERAND_ENUM
2288#undef GET_INSTRINFO_OPERAND_ENUM
2289
2290namespace llvm::R600 {
2291
2292enum class OpName : uint8_t {
2293 dst = 0,
2294 src0 = 1,
2295 update_exec_mask_X = 2,
2296 update_pred_X = 3,
2297 write_X = 4,
2298 omod_X = 5,
2299 dst_rel_X = 6,
2300 clamp_X = 7,
2301 src0_X = 8,
2302 src0_neg_X = 9,
2303 src0_rel_X = 10,
2304 src0_abs_X = 11,
2305 src0_sel_X = 12,
2306 src1_X = 13,
2307 src1_neg_X = 14,
2308 src1_rel_X = 15,
2309 src1_abs_X = 16,
2310 src1_sel_X = 17,
2311 pred_sel_X = 18,
2312 update_exec_mask_Y = 19,
2313 update_pred_Y = 20,
2314 write_Y = 21,
2315 omod_Y = 22,
2316 dst_rel_Y = 23,
2317 clamp_Y = 24,
2318 src0_Y = 25,
2319 src0_neg_Y = 26,
2320 src0_rel_Y = 27,
2321 src0_abs_Y = 28,
2322 src0_sel_Y = 29,
2323 src1_Y = 30,
2324 src1_neg_Y = 31,
2325 src1_rel_Y = 32,
2326 src1_abs_Y = 33,
2327 src1_sel_Y = 34,
2328 pred_sel_Y = 35,
2329 update_exec_mask_Z = 36,
2330 update_pred_Z = 37,
2331 write_Z = 38,
2332 omod_Z = 39,
2333 dst_rel_Z = 40,
2334 clamp_Z = 41,
2335 src0_Z = 42,
2336 src0_neg_Z = 43,
2337 src0_rel_Z = 44,
2338 src0_abs_Z = 45,
2339 src0_sel_Z = 46,
2340 src1_Z = 47,
2341 src1_neg_Z = 48,
2342 src1_rel_Z = 49,
2343 src1_abs_Z = 50,
2344 src1_sel_Z = 51,
2345 pred_sel_Z = 52,
2346 update_exec_mask_W = 53,
2347 update_pred_W = 54,
2348 write_W = 55,
2349 omod_W = 56,
2350 dst_rel_W = 57,
2351 clamp_W = 58,
2352 src0_W = 59,
2353 src0_neg_W = 60,
2354 src0_rel_W = 61,
2355 src0_abs_W = 62,
2356 src0_sel_W = 63,
2357 src1_W = 64,
2358 src1_neg_W = 65,
2359 src1_rel_W = 66,
2360 src1_abs_W = 67,
2361 src1_sel_W = 68,
2362 pred_sel_W = 69,
2363 literal0 = 70,
2364 literal1 = 71,
2365 addr = 72,
2366 chan = 73,
2367 val = 74,
2368 update_exec_mask = 75,
2369 update_pred = 76,
2370 write = 77,
2371 omod = 78,
2372 dst_rel = 79,
2373 clamp = 80,
2374 src0_neg = 81,
2375 src0_rel = 82,
2376 src0_abs = 83,
2377 src0_sel = 84,
2378 src1 = 85,
2379 src1_neg = 86,
2380 src1_rel = 87,
2381 src1_abs = 88,
2382 src1_sel = 89,
2383 last = 90,
2384 pred_sel = 91,
2385 literal = 92,
2386 bank_swizzle = 93,
2387 src2 = 94,
2388 src2_neg = 95,
2389 src2_rel = 96,
2390 src2_sel = 97,
2391 ADDR = 98,
2392 KCACHE_BANK0 = 99,
2393 KCACHE_BANK1 = 100,
2394 KCACHE_MODE0 = 101,
2395 KCACHE_MODE1 = 102,
2396 KCACHE_ADDR0 = 103,
2397 KCACHE_ADDR1 = 104,
2398 COUNT = 105,
2399 Enabled = 106,
2400 NUM_OPERAND_NAMES = 107,
2401}; // enum class OpName
2402
2403LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name);
2404LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx);
2405
2406} // namespace llvm::R600
2407
2408#endif // GET_INSTRINFO_OPERAND_ENUM
2409
2410#ifdef GET_INSTRINFO_NAMED_OPS
2411#undef GET_INSTRINFO_NAMED_OPS
2412
2413namespace llvm::R600 {
2414
2415LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint16_t Opcode) {
2416 static constexpr uint8_t InstructionIndex[] = {
2417 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2418 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2419 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2420 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2421 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2422 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2423 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2424 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2425 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2426 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2427 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2428 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2429 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2430 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2431 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2432 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2433 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2434 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2436 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2437 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2438 0, 0, 0, 0, 0, 1, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0,
2439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2440 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 5, 5,
2441 0, 5, 5, 5, 6, 7, 7, 7, 5, 7, 6, 8, 8, 8, 8, 8,
2442 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2443 0, 0, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5,
2444 5, 5, 5, 0, 0, 0, 0, 6, 6, 6, 0, 6, 6, 6, 6, 6,
2445 6, 6, 6, 6, 7, 6, 0, 6, 0, 0, 0, 5, 5, 6, 6, 5,
2446 9, 10, 9, 10, 11, 9, 12, 13, 9, 10, 9, 10, 9, 10, 9, 10,
2447 9, 10, 11, 11, 9, 9, 10, 11, 11, 9, 9, 10, 9, 10, 0, 6,
2448 6, 6, 6, 6, 0, 0, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
2449 5, 5, 6, 6, 5, 7, 7, 7, 7, 7, 7, 5, 5, 5, 5, 5,
2450 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 7, 7, 5, 6,
2451 5, 0, 0, 0, 5, 5, 5, 5, 5, 5, 5, 5, 0, 0, 0, 0,
2452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2454 0, 0, 0, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
2455 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6,
2456 6, 6, 6, 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2457 0, 0, 0, 0, 0, 0, 0, 6, 6, 6, 0, 0, 0, 0, 0, 0,
2458 0, 0, 0, 0, 0, 0, 5,
2459 };
2460 return InstructionIndex[Opcode];
2461}
2462LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name) {
2463 assert(Name != OpName::NUM_OPERAND_NAMES);
2464 static constexpr int8_t OperandMap[][107] = {
2465 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2466 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2467 {0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2468 {0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2469 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2470 {0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2471 {0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2472 {0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2473 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
2474 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2475 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2476 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2477 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2478 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2479 };
2480 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2481 return OperandMap[InstrIdx][(unsigned)Name];
2482}
2483LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx) {
2484 assert(Idx >= 0 && Idx < 71);
2485 static constexpr OpName OperandMap[][71] = {
2486 {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2487 {OpName::dst, OpName::src0, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2488 {OpName::dst, OpName::update_exec_mask_X, OpName::update_pred_X, OpName::write_X, OpName::omod_X, OpName::dst_rel_X, OpName::clamp_X, OpName::src0_X, OpName::src0_neg_X, OpName::src0_rel_X, OpName::src0_abs_X, OpName::src0_sel_X, OpName::src1_X, OpName::src1_neg_X, OpName::src1_rel_X, OpName::src1_abs_X, OpName::src1_sel_X, OpName::pred_sel_X, OpName::update_exec_mask_Y, OpName::update_pred_Y, OpName::write_Y, OpName::omod_Y, OpName::dst_rel_Y, OpName::clamp_Y, OpName::src0_Y, OpName::src0_neg_Y, OpName::src0_rel_Y, OpName::src0_abs_Y, OpName::src0_sel_Y, OpName::src1_Y, OpName::src1_neg_Y, OpName::src1_rel_Y, OpName::src1_abs_Y, OpName::src1_sel_Y, OpName::pred_sel_Y, OpName::update_exec_mask_Z, OpName::update_pred_Z, OpName::write_Z, OpName::omod_Z, OpName::dst_rel_Z, OpName::clamp_Z, OpName::src0_Z, OpName::src0_neg_Z, OpName::src0_rel_Z, OpName::src0_abs_Z, OpName::src0_sel_Z, OpName::src1_Z, OpName::src1_neg_Z, OpName::src1_rel_Z, OpName::src1_abs_Z, OpName::src1_sel_Z, OpName::pred_sel_Z, OpName::update_exec_mask_W, OpName::update_pred_W, OpName::write_W, OpName::omod_W, OpName::dst_rel_W, OpName::clamp_W, OpName::src0_W, OpName::src0_neg_W, OpName::src0_rel_W, OpName::src0_abs_W, OpName::src0_sel_W, OpName::src1_W, OpName::src1_neg_W, OpName::src1_rel_W, OpName::src1_abs_W, OpName::src1_sel_W, OpName::pred_sel_W, OpName::literal0, OpName::literal1, },
2489 {OpName::dst, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2490 {OpName::val, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2491 {OpName::dst, OpName::update_exec_mask, OpName::update_pred, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_abs, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2492 {OpName::dst, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2493 {OpName::dst, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_neg, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2494 {OpName::ADDR, OpName::KCACHE_BANK0, OpName::KCACHE_BANK1, OpName::KCACHE_MODE0, OpName::KCACHE_MODE1, OpName::KCACHE_ADDR0, OpName::KCACHE_ADDR1, OpName::COUNT, OpName::Enabled, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2495 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2496 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2497 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2498 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2499 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2500 };
2501 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2502 return OperandMap[InstrIdx][(unsigned)Idx];
2503}
2504
2505} // namespace llvm::R600
2506
2507#endif // GET_INSTRINFO_NAMED_OPS
2508
2509#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2510#undef GET_INSTRINFO_MC_HELPER_DECLS
2511
2512namespace llvm {
2513
2514class MCInst;
2515class FeatureBitset;
2516
2517namespace R600_MC {
2518
2519void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2520
2521} // namespace R600_MC
2522
2523} // namespace llvm
2524
2525#endif // GET_INSTRINFO_MC_HELPER_DECLS
2526
2527#ifdef GET_INSTRINFO_MC_HELPERS
2528#undef GET_INSTRINFO_MC_HELPERS
2529
2530namespace llvm::R600_MC {
2531
2532
2533} // namespace llvm::R600_MC
2534
2535#endif // GET_INSTRINFO_MC_HELPERS
2536
2537#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2538 defined(GET_AVAILABLE_OPCODE_CHECKER)
2539#define GET_COMPUTE_FEATURES
2540#endif
2541#ifdef GET_COMPUTE_FEATURES
2542#undef GET_COMPUTE_FEATURES
2543
2544namespace llvm::R600_MC {
2545
2546// Bits for subtarget features that participate in instruction matching.
2547enum SubtargetFeatureBits : uint8_t {
2548};
2549
2550inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2551 FeatureBitset Features;
2552 return Features;
2553}
2554
2555inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2556 enum : uint8_t {
2557 CEFBS_None,
2558 };
2559
2560 static constexpr FeatureBitset FeatureBitsets[] = {
2561 {}, // CEFBS_None
2562 };
2563 static constexpr uint8_t RequiredFeaturesRefs[] = {
2564 CEFBS_None, // PHI
2565 CEFBS_None, // INLINEASM
2566 CEFBS_None, // INLINEASM_BR
2567 CEFBS_None, // CFI_INSTRUCTION
2568 CEFBS_None, // EH_LABEL
2569 CEFBS_None, // GC_LABEL
2570 CEFBS_None, // ANNOTATION_LABEL
2571 CEFBS_None, // KILL
2572 CEFBS_None, // EXTRACT_SUBREG
2573 CEFBS_None, // INSERT_SUBREG
2574 CEFBS_None, // IMPLICIT_DEF
2575 CEFBS_None, // INIT_UNDEF
2576 CEFBS_None, // SUBREG_TO_REG
2577 CEFBS_None, // COPY_TO_REGCLASS
2578 CEFBS_None, // DBG_VALUE
2579 CEFBS_None, // DBG_VALUE_LIST
2580 CEFBS_None, // DBG_INSTR_REF
2581 CEFBS_None, // DBG_PHI
2582 CEFBS_None, // DBG_LABEL
2583 CEFBS_None, // REG_SEQUENCE
2584 CEFBS_None, // COPY
2585 CEFBS_None, // COPY_LANEMASK
2586 CEFBS_None, // BUNDLE
2587 CEFBS_None, // LIFETIME_START
2588 CEFBS_None, // LIFETIME_END
2589 CEFBS_None, // PSEUDO_PROBE
2590 CEFBS_None, // ARITH_FENCE
2591 CEFBS_None, // STACKMAP
2592 CEFBS_None, // FENTRY_CALL
2593 CEFBS_None, // PATCHPOINT
2594 CEFBS_None, // LOAD_STACK_GUARD
2595 CEFBS_None, // PREALLOCATED_SETUP
2596 CEFBS_None, // PREALLOCATED_ARG
2597 CEFBS_None, // STATEPOINT
2598 CEFBS_None, // LOCAL_ESCAPE
2599 CEFBS_None, // FAULTING_OP
2600 CEFBS_None, // PATCHABLE_OP
2601 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2602 CEFBS_None, // PATCHABLE_RET
2603 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2604 CEFBS_None, // PATCHABLE_TAIL_CALL
2605 CEFBS_None, // PATCHABLE_EVENT_CALL
2606 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2607 CEFBS_None, // ICALL_BRANCH_FUNNEL
2608 CEFBS_None, // FAKE_USE
2609 CEFBS_None, // MEMBARRIER
2610 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2611 CEFBS_None, // RELOC_NONE
2612 CEFBS_None, // CONVERGENCECTRL_ENTRY
2613 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2614 CEFBS_None, // CONVERGENCECTRL_LOOP
2615 CEFBS_None, // CONVERGENCECTRL_GLUE
2616 CEFBS_None, // G_ASSERT_SEXT
2617 CEFBS_None, // G_ASSERT_ZEXT
2618 CEFBS_None, // G_ASSERT_ALIGN
2619 CEFBS_None, // G_ADD
2620 CEFBS_None, // G_SUB
2621 CEFBS_None, // G_MUL
2622 CEFBS_None, // G_SDIV
2623 CEFBS_None, // G_UDIV
2624 CEFBS_None, // G_SREM
2625 CEFBS_None, // G_UREM
2626 CEFBS_None, // G_SDIVREM
2627 CEFBS_None, // G_UDIVREM
2628 CEFBS_None, // G_AND
2629 CEFBS_None, // G_OR
2630 CEFBS_None, // G_XOR
2631 CEFBS_None, // G_ABDS
2632 CEFBS_None, // G_ABDU
2633 CEFBS_None, // G_UAVGFLOOR
2634 CEFBS_None, // G_UAVGCEIL
2635 CEFBS_None, // G_SAVGFLOOR
2636 CEFBS_None, // G_SAVGCEIL
2637 CEFBS_None, // G_IMPLICIT_DEF
2638 CEFBS_None, // G_PHI
2639 CEFBS_None, // G_FRAME_INDEX
2640 CEFBS_None, // G_GLOBAL_VALUE
2641 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2642 CEFBS_None, // G_CONSTANT_POOL
2643 CEFBS_None, // G_EXTRACT
2644 CEFBS_None, // G_UNMERGE_VALUES
2645 CEFBS_None, // G_INSERT
2646 CEFBS_None, // G_MERGE_VALUES
2647 CEFBS_None, // G_BUILD_VECTOR
2648 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2649 CEFBS_None, // G_CONCAT_VECTORS
2650 CEFBS_None, // G_PTRTOINT
2651 CEFBS_None, // G_INTTOPTR
2652 CEFBS_None, // G_BITCAST
2653 CEFBS_None, // G_FREEZE
2654 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2655 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2656 CEFBS_None, // G_INTRINSIC_TRUNC
2657 CEFBS_None, // G_INTRINSIC_ROUND
2658 CEFBS_None, // G_INTRINSIC_LRINT
2659 CEFBS_None, // G_INTRINSIC_LLRINT
2660 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2661 CEFBS_None, // G_READCYCLECOUNTER
2662 CEFBS_None, // G_READSTEADYCOUNTER
2663 CEFBS_None, // G_LOAD
2664 CEFBS_None, // G_SEXTLOAD
2665 CEFBS_None, // G_ZEXTLOAD
2666 CEFBS_None, // G_INDEXED_LOAD
2667 CEFBS_None, // G_INDEXED_SEXTLOAD
2668 CEFBS_None, // G_INDEXED_ZEXTLOAD
2669 CEFBS_None, // G_STORE
2670 CEFBS_None, // G_INDEXED_STORE
2671 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2672 CEFBS_None, // G_ATOMIC_CMPXCHG
2673 CEFBS_None, // G_ATOMICRMW_XCHG
2674 CEFBS_None, // G_ATOMICRMW_ADD
2675 CEFBS_None, // G_ATOMICRMW_SUB
2676 CEFBS_None, // G_ATOMICRMW_AND
2677 CEFBS_None, // G_ATOMICRMW_NAND
2678 CEFBS_None, // G_ATOMICRMW_OR
2679 CEFBS_None, // G_ATOMICRMW_XOR
2680 CEFBS_None, // G_ATOMICRMW_MAX
2681 CEFBS_None, // G_ATOMICRMW_MIN
2682 CEFBS_None, // G_ATOMICRMW_UMAX
2683 CEFBS_None, // G_ATOMICRMW_UMIN
2684 CEFBS_None, // G_ATOMICRMW_FADD
2685 CEFBS_None, // G_ATOMICRMW_FSUB
2686 CEFBS_None, // G_ATOMICRMW_FMAX
2687 CEFBS_None, // G_ATOMICRMW_FMIN
2688 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2689 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2690 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2691 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2692 CEFBS_None, // G_ATOMICRMW_USUB_COND
2693 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2694 CEFBS_None, // G_FENCE
2695 CEFBS_None, // G_PREFETCH
2696 CEFBS_None, // G_BRCOND
2697 CEFBS_None, // G_BRINDIRECT
2698 CEFBS_None, // G_INVOKE_REGION_START
2699 CEFBS_None, // G_INTRINSIC
2700 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2701 CEFBS_None, // G_INTRINSIC_CONVERGENT
2702 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2703 CEFBS_None, // G_ANYEXT
2704 CEFBS_None, // G_TRUNC
2705 CEFBS_None, // G_TRUNC_SSAT_S
2706 CEFBS_None, // G_TRUNC_SSAT_U
2707 CEFBS_None, // G_TRUNC_USAT_U
2708 CEFBS_None, // G_CONSTANT
2709 CEFBS_None, // G_FCONSTANT
2710 CEFBS_None, // G_VASTART
2711 CEFBS_None, // G_VAARG
2712 CEFBS_None, // G_SEXT
2713 CEFBS_None, // G_SEXT_INREG
2714 CEFBS_None, // G_ZEXT
2715 CEFBS_None, // G_SHL
2716 CEFBS_None, // G_LSHR
2717 CEFBS_None, // G_ASHR
2718 CEFBS_None, // G_FSHL
2719 CEFBS_None, // G_FSHR
2720 CEFBS_None, // G_ROTR
2721 CEFBS_None, // G_ROTL
2722 CEFBS_None, // G_ICMP
2723 CEFBS_None, // G_FCMP
2724 CEFBS_None, // G_SCMP
2725 CEFBS_None, // G_UCMP
2726 CEFBS_None, // G_SELECT
2727 CEFBS_None, // G_UADDO
2728 CEFBS_None, // G_UADDE
2729 CEFBS_None, // G_USUBO
2730 CEFBS_None, // G_USUBE
2731 CEFBS_None, // G_SADDO
2732 CEFBS_None, // G_SADDE
2733 CEFBS_None, // G_SSUBO
2734 CEFBS_None, // G_SSUBE
2735 CEFBS_None, // G_UMULO
2736 CEFBS_None, // G_SMULO
2737 CEFBS_None, // G_UMULH
2738 CEFBS_None, // G_SMULH
2739 CEFBS_None, // G_UADDSAT
2740 CEFBS_None, // G_SADDSAT
2741 CEFBS_None, // G_USUBSAT
2742 CEFBS_None, // G_SSUBSAT
2743 CEFBS_None, // G_USHLSAT
2744 CEFBS_None, // G_SSHLSAT
2745 CEFBS_None, // G_SMULFIX
2746 CEFBS_None, // G_UMULFIX
2747 CEFBS_None, // G_SMULFIXSAT
2748 CEFBS_None, // G_UMULFIXSAT
2749 CEFBS_None, // G_SDIVFIX
2750 CEFBS_None, // G_UDIVFIX
2751 CEFBS_None, // G_SDIVFIXSAT
2752 CEFBS_None, // G_UDIVFIXSAT
2753 CEFBS_None, // G_FADD
2754 CEFBS_None, // G_FSUB
2755 CEFBS_None, // G_FMUL
2756 CEFBS_None, // G_FMA
2757 CEFBS_None, // G_FMAD
2758 CEFBS_None, // G_FDIV
2759 CEFBS_None, // G_FREM
2760 CEFBS_None, // G_FMODF
2761 CEFBS_None, // G_FPOW
2762 CEFBS_None, // G_FPOWI
2763 CEFBS_None, // G_FEXP
2764 CEFBS_None, // G_FEXP2
2765 CEFBS_None, // G_FEXP10
2766 CEFBS_None, // G_FLOG
2767 CEFBS_None, // G_FLOG2
2768 CEFBS_None, // G_FLOG10
2769 CEFBS_None, // G_FLDEXP
2770 CEFBS_None, // G_FFREXP
2771 CEFBS_None, // G_FNEG
2772 CEFBS_None, // G_FPEXT
2773 CEFBS_None, // G_FPTRUNC
2774 CEFBS_None, // G_FPTOSI
2775 CEFBS_None, // G_FPTOUI
2776 CEFBS_None, // G_SITOFP
2777 CEFBS_None, // G_UITOFP
2778 CEFBS_None, // G_FPTOSI_SAT
2779 CEFBS_None, // G_FPTOUI_SAT
2780 CEFBS_None, // G_FABS
2781 CEFBS_None, // G_FCOPYSIGN
2782 CEFBS_None, // G_IS_FPCLASS
2783 CEFBS_None, // G_FCANONICALIZE
2784 CEFBS_None, // G_FMINNUM
2785 CEFBS_None, // G_FMAXNUM
2786 CEFBS_None, // G_FMINNUM_IEEE
2787 CEFBS_None, // G_FMAXNUM_IEEE
2788 CEFBS_None, // G_FMINIMUM
2789 CEFBS_None, // G_FMAXIMUM
2790 CEFBS_None, // G_FMINIMUMNUM
2791 CEFBS_None, // G_FMAXIMUMNUM
2792 CEFBS_None, // G_GET_FPENV
2793 CEFBS_None, // G_SET_FPENV
2794 CEFBS_None, // G_RESET_FPENV
2795 CEFBS_None, // G_GET_FPMODE
2796 CEFBS_None, // G_SET_FPMODE
2797 CEFBS_None, // G_RESET_FPMODE
2798 CEFBS_None, // G_GET_ROUNDING
2799 CEFBS_None, // G_SET_ROUNDING
2800 CEFBS_None, // G_PTR_ADD
2801 CEFBS_None, // G_PTRMASK
2802 CEFBS_None, // G_SMIN
2803 CEFBS_None, // G_SMAX
2804 CEFBS_None, // G_UMIN
2805 CEFBS_None, // G_UMAX
2806 CEFBS_None, // G_ABS
2807 CEFBS_None, // G_LROUND
2808 CEFBS_None, // G_LLROUND
2809 CEFBS_None, // G_BR
2810 CEFBS_None, // G_BRJT
2811 CEFBS_None, // G_VSCALE
2812 CEFBS_None, // G_INSERT_SUBVECTOR
2813 CEFBS_None, // G_EXTRACT_SUBVECTOR
2814 CEFBS_None, // G_INSERT_VECTOR_ELT
2815 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2816 CEFBS_None, // G_SHUFFLE_VECTOR
2817 CEFBS_None, // G_SPLAT_VECTOR
2818 CEFBS_None, // G_STEP_VECTOR
2819 CEFBS_None, // G_VECTOR_COMPRESS
2820 CEFBS_None, // G_CTTZ
2821 CEFBS_None, // G_CTTZ_ZERO_UNDEF
2822 CEFBS_None, // G_CTLZ
2823 CEFBS_None, // G_CTLZ_ZERO_UNDEF
2824 CEFBS_None, // G_CTLS
2825 CEFBS_None, // G_CTPOP
2826 CEFBS_None, // G_BSWAP
2827 CEFBS_None, // G_BITREVERSE
2828 CEFBS_None, // G_FCEIL
2829 CEFBS_None, // G_FCOS
2830 CEFBS_None, // G_FSIN
2831 CEFBS_None, // G_FSINCOS
2832 CEFBS_None, // G_FTAN
2833 CEFBS_None, // G_FACOS
2834 CEFBS_None, // G_FASIN
2835 CEFBS_None, // G_FATAN
2836 CEFBS_None, // G_FATAN2
2837 CEFBS_None, // G_FCOSH
2838 CEFBS_None, // G_FSINH
2839 CEFBS_None, // G_FTANH
2840 CEFBS_None, // G_FSQRT
2841 CEFBS_None, // G_FFLOOR
2842 CEFBS_None, // G_FRINT
2843 CEFBS_None, // G_FNEARBYINT
2844 CEFBS_None, // G_ADDRSPACE_CAST
2845 CEFBS_None, // G_BLOCK_ADDR
2846 CEFBS_None, // G_JUMP_TABLE
2847 CEFBS_None, // G_DYN_STACKALLOC
2848 CEFBS_None, // G_STACKSAVE
2849 CEFBS_None, // G_STACKRESTORE
2850 CEFBS_None, // G_STRICT_FADD
2851 CEFBS_None, // G_STRICT_FSUB
2852 CEFBS_None, // G_STRICT_FMUL
2853 CEFBS_None, // G_STRICT_FDIV
2854 CEFBS_None, // G_STRICT_FREM
2855 CEFBS_None, // G_STRICT_FMA
2856 CEFBS_None, // G_STRICT_FSQRT
2857 CEFBS_None, // G_STRICT_FLDEXP
2858 CEFBS_None, // G_READ_REGISTER
2859 CEFBS_None, // G_WRITE_REGISTER
2860 CEFBS_None, // G_MEMCPY
2861 CEFBS_None, // G_MEMCPY_INLINE
2862 CEFBS_None, // G_MEMMOVE
2863 CEFBS_None, // G_MEMSET
2864 CEFBS_None, // G_BZERO
2865 CEFBS_None, // G_TRAP
2866 CEFBS_None, // G_DEBUGTRAP
2867 CEFBS_None, // G_UBSANTRAP
2868 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2869 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2870 CEFBS_None, // G_VECREDUCE_FADD
2871 CEFBS_None, // G_VECREDUCE_FMUL
2872 CEFBS_None, // G_VECREDUCE_FMAX
2873 CEFBS_None, // G_VECREDUCE_FMIN
2874 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2875 CEFBS_None, // G_VECREDUCE_FMINIMUM
2876 CEFBS_None, // G_VECREDUCE_ADD
2877 CEFBS_None, // G_VECREDUCE_MUL
2878 CEFBS_None, // G_VECREDUCE_AND
2879 CEFBS_None, // G_VECREDUCE_OR
2880 CEFBS_None, // G_VECREDUCE_XOR
2881 CEFBS_None, // G_VECREDUCE_SMAX
2882 CEFBS_None, // G_VECREDUCE_SMIN
2883 CEFBS_None, // G_VECREDUCE_UMAX
2884 CEFBS_None, // G_VECREDUCE_UMIN
2885 CEFBS_None, // G_SBFX
2886 CEFBS_None, // G_UBFX
2887 CEFBS_None, // BRANCH
2888 CEFBS_None, // BRANCH_COND_f32
2889 CEFBS_None, // BRANCH_COND_i32
2890 CEFBS_None, // BREAK
2891 CEFBS_None, // BREAKC_f32
2892 CEFBS_None, // BREAKC_i32
2893 CEFBS_None, // BREAK_LOGICALNZ_f32
2894 CEFBS_None, // BREAK_LOGICALNZ_i32
2895 CEFBS_None, // BREAK_LOGICALZ_f32
2896 CEFBS_None, // BREAK_LOGICALZ_i32
2897 CEFBS_None, // CONST_COPY
2898 CEFBS_None, // CONTINUE
2899 CEFBS_None, // CONTINUEC_f32
2900 CEFBS_None, // CONTINUEC_i32
2901 CEFBS_None, // CONTINUE_LOGICALNZ_f32
2902 CEFBS_None, // CONTINUE_LOGICALNZ_i32
2903 CEFBS_None, // CONTINUE_LOGICALZ_f32
2904 CEFBS_None, // CONTINUE_LOGICALZ_i32
2905 CEFBS_None, // CUBE_eg_pseudo
2906 CEFBS_None, // CUBE_r600_pseudo
2907 CEFBS_None, // DEFAULT
2908 CEFBS_None, // DOT_4
2909 CEFBS_None, // DUMMY_CHAIN
2910 CEFBS_None, // ELSE
2911 CEFBS_None, // END
2912 CEFBS_None, // ENDFUNC
2913 CEFBS_None, // ENDIF
2914 CEFBS_None, // ENDLOOP
2915 CEFBS_None, // ENDMAIN
2916 CEFBS_None, // ENDSWITCH
2917 CEFBS_None, // FABS_R600
2918 CEFBS_None, // FNEG_R600
2919 CEFBS_None, // FUNC
2920 CEFBS_None, // IFC_f32
2921 CEFBS_None, // IFC_i32
2922 CEFBS_None, // IF_LOGICALNZ_f32
2923 CEFBS_None, // IF_LOGICALNZ_i32
2924 CEFBS_None, // IF_LOGICALZ_f32
2925 CEFBS_None, // IF_LOGICALZ_i32
2926 CEFBS_None, // IF_PREDICATE_SET
2927 CEFBS_None, // JUMP
2928 CEFBS_None, // JUMP_COND
2929 CEFBS_None, // MASK_WRITE
2930 CEFBS_None, // MOV_IMM_F32
2931 CEFBS_None, // MOV_IMM_GLOBAL_ADDR
2932 CEFBS_None, // MOV_IMM_I32
2933 CEFBS_None, // PRED_X
2934 CEFBS_None, // R600_EXTRACT_ELT_V2
2935 CEFBS_None, // R600_EXTRACT_ELT_V4
2936 CEFBS_None, // R600_INSERT_ELT_V2
2937 CEFBS_None, // R600_INSERT_ELT_V4
2938 CEFBS_None, // R600_RegisterLoad
2939 CEFBS_None, // R600_RegisterStore
2940 CEFBS_None, // RETDYN
2941 CEFBS_None, // RETURN
2942 CEFBS_None, // TXD
2943 CEFBS_None, // TXD_SHADOW
2944 CEFBS_None, // WHILELOOP
2945 CEFBS_None, // ADD
2946 CEFBS_None, // ADDC_UINT
2947 CEFBS_None, // ADD_INT
2948 CEFBS_None, // ALU_CLAUSE
2949 CEFBS_None, // AND_INT
2950 CEFBS_None, // ASHR_eg
2951 CEFBS_None, // ASHR_r600
2952 CEFBS_None, // BCNT_INT
2953 CEFBS_None, // BFE_INT_eg
2954 CEFBS_None, // BFE_UINT_eg
2955 CEFBS_None, // BFI_INT_eg
2956 CEFBS_None, // BFM_INT_eg
2957 CEFBS_None, // BIT_ALIGN_INT_eg
2958 CEFBS_None, // CEIL
2959 CEFBS_None, // CF_ALU
2960 CEFBS_None, // CF_ALU_BREAK
2961 CEFBS_None, // CF_ALU_CONTINUE
2962 CEFBS_None, // CF_ALU_ELSE_AFTER
2963 CEFBS_None, // CF_ALU_POP_AFTER
2964 CEFBS_None, // CF_ALU_PUSH_BEFORE
2965 CEFBS_None, // CF_CALL_FS_EG
2966 CEFBS_None, // CF_CALL_FS_R600
2967 CEFBS_None, // CF_CONTINUE_EG
2968 CEFBS_None, // CF_CONTINUE_R600
2969 CEFBS_None, // CF_ELSE_EG
2970 CEFBS_None, // CF_ELSE_R600
2971 CEFBS_None, // CF_END_CM
2972 CEFBS_None, // CF_END_EG
2973 CEFBS_None, // CF_END_R600
2974 CEFBS_None, // CF_JUMP_EG
2975 CEFBS_None, // CF_JUMP_R600
2976 CEFBS_None, // CF_PUSH_EG
2977 CEFBS_None, // CF_PUSH_ELSE_R600
2978 CEFBS_None, // CF_TC_EG
2979 CEFBS_None, // CF_TC_R600
2980 CEFBS_None, // CF_VC_EG
2981 CEFBS_None, // CF_VC_R600
2982 CEFBS_None, // CNDE_INT
2983 CEFBS_None, // CNDE_eg
2984 CEFBS_None, // CNDE_r600
2985 CEFBS_None, // CNDGE_INT
2986 CEFBS_None, // CNDGE_eg
2987 CEFBS_None, // CNDGE_r600
2988 CEFBS_None, // CNDGT_INT
2989 CEFBS_None, // CNDGT_eg
2990 CEFBS_None, // CNDGT_r600
2991 CEFBS_None, // COS_cm
2992 CEFBS_None, // COS_eg
2993 CEFBS_None, // COS_r600
2994 CEFBS_None, // COS_r700
2995 CEFBS_None, // CUBE_eg_real
2996 CEFBS_None, // CUBE_r600_real
2997 CEFBS_None, // DOT4_eg
2998 CEFBS_None, // DOT4_r600
2999 CEFBS_None, // EG_ExportBuf
3000 CEFBS_None, // EG_ExportSwz
3001 CEFBS_None, // END_LOOP_EG
3002 CEFBS_None, // END_LOOP_R600
3003 CEFBS_None, // EXP_IEEE_cm
3004 CEFBS_None, // EXP_IEEE_eg
3005 CEFBS_None, // EXP_IEEE_r600
3006 CEFBS_None, // FETCH_CLAUSE
3007 CEFBS_None, // FFBH_UINT
3008 CEFBS_None, // FFBL_INT
3009 CEFBS_None, // FLOOR
3010 CEFBS_None, // FLT16_TO_FLT32
3011 CEFBS_None, // FLT32_TO_FLT16
3012 CEFBS_None, // FLT_TO_INT_eg
3013 CEFBS_None, // FLT_TO_INT_r600
3014 CEFBS_None, // FLT_TO_UINT_eg
3015 CEFBS_None, // FLT_TO_UINT_r600
3016 CEFBS_None, // FMA_eg
3017 CEFBS_None, // FRACT
3018 CEFBS_None, // GROUP_BARRIER
3019 CEFBS_None, // INTERP_LOAD_P0
3020 CEFBS_None, // INTERP_PAIR_XY
3021 CEFBS_None, // INTERP_PAIR_ZW
3022 CEFBS_None, // INTERP_VEC_LOAD
3023 CEFBS_None, // INTERP_XY
3024 CEFBS_None, // INTERP_ZW
3025 CEFBS_None, // INT_TO_FLT_eg
3026 CEFBS_None, // INT_TO_FLT_r600
3027 CEFBS_None, // KILLGT
3028 CEFBS_None, // LDS_ADD
3029 CEFBS_None, // LDS_ADD_RET
3030 CEFBS_None, // LDS_AND
3031 CEFBS_None, // LDS_AND_RET
3032 CEFBS_None, // LDS_BYTE_READ_RET
3033 CEFBS_None, // LDS_BYTE_WRITE
3034 CEFBS_None, // LDS_CMPST
3035 CEFBS_None, // LDS_CMPST_RET
3036 CEFBS_None, // LDS_MAX_INT
3037 CEFBS_None, // LDS_MAX_INT_RET
3038 CEFBS_None, // LDS_MAX_UINT
3039 CEFBS_None, // LDS_MAX_UINT_RET
3040 CEFBS_None, // LDS_MIN_INT
3041 CEFBS_None, // LDS_MIN_INT_RET
3042 CEFBS_None, // LDS_MIN_UINT
3043 CEFBS_None, // LDS_MIN_UINT_RET
3044 CEFBS_None, // LDS_OR
3045 CEFBS_None, // LDS_OR_RET
3046 CEFBS_None, // LDS_READ_RET
3047 CEFBS_None, // LDS_SHORT_READ_RET
3048 CEFBS_None, // LDS_SHORT_WRITE
3049 CEFBS_None, // LDS_SUB
3050 CEFBS_None, // LDS_SUB_RET
3051 CEFBS_None, // LDS_UBYTE_READ_RET
3052 CEFBS_None, // LDS_USHORT_READ_RET
3053 CEFBS_None, // LDS_WRITE
3054 CEFBS_None, // LDS_WRXCHG
3055 CEFBS_None, // LDS_WRXCHG_RET
3056 CEFBS_None, // LDS_XOR
3057 CEFBS_None, // LDS_XOR_RET
3058 CEFBS_None, // LITERALS
3059 CEFBS_None, // LOG_CLAMPED_eg
3060 CEFBS_None, // LOG_CLAMPED_r600
3061 CEFBS_None, // LOG_IEEE_cm
3062 CEFBS_None, // LOG_IEEE_eg
3063 CEFBS_None, // LOG_IEEE_r600
3064 CEFBS_None, // LOOP_BREAK_EG
3065 CEFBS_None, // LOOP_BREAK_R600
3066 CEFBS_None, // LSHL_eg
3067 CEFBS_None, // LSHL_r600
3068 CEFBS_None, // LSHR_eg
3069 CEFBS_None, // LSHR_r600
3070 CEFBS_None, // MAX
3071 CEFBS_None, // MAX_DX10
3072 CEFBS_None, // MAX_INT
3073 CEFBS_None, // MAX_UINT
3074 CEFBS_None, // MIN
3075 CEFBS_None, // MIN_DX10
3076 CEFBS_None, // MIN_INT
3077 CEFBS_None, // MIN_UINT
3078 CEFBS_None, // MOV
3079 CEFBS_None, // MOVA_INT_eg
3080 CEFBS_None, // MUL
3081 CEFBS_None, // MULADD_IEEE_eg
3082 CEFBS_None, // MULADD_IEEE_r600
3083 CEFBS_None, // MULADD_INT24_cm
3084 CEFBS_None, // MULADD_UINT24_eg
3085 CEFBS_None, // MULADD_eg
3086 CEFBS_None, // MULADD_r600
3087 CEFBS_None, // MULHI_INT_cm
3088 CEFBS_None, // MULHI_INT_cm24
3089 CEFBS_None, // MULHI_INT_eg
3090 CEFBS_None, // MULHI_INT_r600
3091 CEFBS_None, // MULHI_UINT24_eg
3092 CEFBS_None, // MULHI_UINT_cm
3093 CEFBS_None, // MULHI_UINT_cm24
3094 CEFBS_None, // MULHI_UINT_eg
3095 CEFBS_None, // MULHI_UINT_r600
3096 CEFBS_None, // MULLO_INT_cm
3097 CEFBS_None, // MULLO_INT_eg
3098 CEFBS_None, // MULLO_INT_r600
3099 CEFBS_None, // MULLO_UINT_cm
3100 CEFBS_None, // MULLO_UINT_eg
3101 CEFBS_None, // MULLO_UINT_r600
3102 CEFBS_None, // MUL_IEEE
3103 CEFBS_None, // MUL_INT24_cm
3104 CEFBS_None, // MUL_LIT_eg
3105 CEFBS_None, // MUL_LIT_r600
3106 CEFBS_None, // MUL_UINT24_eg
3107 CEFBS_None, // NOT_INT
3108 CEFBS_None, // OR_INT
3109 CEFBS_None, // PAD
3110 CEFBS_None, // POP_EG
3111 CEFBS_None, // POP_R600
3112 CEFBS_None, // PRED_SETE
3113 CEFBS_None, // PRED_SETE_INT
3114 CEFBS_None, // PRED_SETGE
3115 CEFBS_None, // PRED_SETGE_INT
3116 CEFBS_None, // PRED_SETGT
3117 CEFBS_None, // PRED_SETGT_INT
3118 CEFBS_None, // PRED_SETNE
3119 CEFBS_None, // PRED_SETNE_INT
3120 CEFBS_None, // R600_ExportBuf
3121 CEFBS_None, // R600_ExportSwz
3122 CEFBS_None, // RAT_ATOMIC_ADD_NORET
3123 CEFBS_None, // RAT_ATOMIC_ADD_RTN
3124 CEFBS_None, // RAT_ATOMIC_AND_NORET
3125 CEFBS_None, // RAT_ATOMIC_AND_RTN
3126 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET
3127 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN
3128 CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET
3129 CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN
3130 CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET
3131 CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN
3132 CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET
3133 CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN
3134 CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET
3135 CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN
3136 CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET
3137 CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN
3138 CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET
3139 CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN
3140 CEFBS_None, // RAT_ATOMIC_OR_NORET
3141 CEFBS_None, // RAT_ATOMIC_OR_RTN
3142 CEFBS_None, // RAT_ATOMIC_RSUB_NORET
3143 CEFBS_None, // RAT_ATOMIC_RSUB_RTN
3144 CEFBS_None, // RAT_ATOMIC_SUB_NORET
3145 CEFBS_None, // RAT_ATOMIC_SUB_RTN
3146 CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET
3147 CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN
3148 CEFBS_None, // RAT_ATOMIC_XOR_NORET
3149 CEFBS_None, // RAT_ATOMIC_XOR_RTN
3150 CEFBS_None, // RAT_MSKOR
3151 CEFBS_None, // RAT_STORE_DWORD128
3152 CEFBS_None, // RAT_STORE_DWORD32
3153 CEFBS_None, // RAT_STORE_DWORD64
3154 CEFBS_None, // RAT_STORE_TYPED_cm
3155 CEFBS_None, // RAT_STORE_TYPED_eg
3156 CEFBS_None, // RAT_WRITE_CACHELESS_128_eg
3157 CEFBS_None, // RAT_WRITE_CACHELESS_32_eg
3158 CEFBS_None, // RAT_WRITE_CACHELESS_64_eg
3159 CEFBS_None, // RECIPSQRT_CLAMPED_cm
3160 CEFBS_None, // RECIPSQRT_CLAMPED_eg
3161 CEFBS_None, // RECIPSQRT_CLAMPED_r600
3162 CEFBS_None, // RECIPSQRT_IEEE_cm
3163 CEFBS_None, // RECIPSQRT_IEEE_eg
3164 CEFBS_None, // RECIPSQRT_IEEE_r600
3165 CEFBS_None, // RECIP_CLAMPED_cm
3166 CEFBS_None, // RECIP_CLAMPED_eg
3167 CEFBS_None, // RECIP_CLAMPED_r600
3168 CEFBS_None, // RECIP_IEEE_cm
3169 CEFBS_None, // RECIP_IEEE_eg
3170 CEFBS_None, // RECIP_IEEE_r600
3171 CEFBS_None, // RECIP_UINT_eg
3172 CEFBS_None, // RECIP_UINT_r600
3173 CEFBS_None, // RNDNE
3174 CEFBS_None, // SETE
3175 CEFBS_None, // SETE_DX10
3176 CEFBS_None, // SETE_INT
3177 CEFBS_None, // SETGE_DX10
3178 CEFBS_None, // SETGE_INT
3179 CEFBS_None, // SETGE_UINT
3180 CEFBS_None, // SETGT_DX10
3181 CEFBS_None, // SETGT_INT
3182 CEFBS_None, // SETGT_UINT
3183 CEFBS_None, // SETNE_DX10
3184 CEFBS_None, // SETNE_INT
3185 CEFBS_None, // SGE
3186 CEFBS_None, // SGT
3187 CEFBS_None, // SIN_cm
3188 CEFBS_None, // SIN_eg
3189 CEFBS_None, // SIN_r600
3190 CEFBS_None, // SIN_r700
3191 CEFBS_None, // SNE
3192 CEFBS_None, // SUBB_UINT
3193 CEFBS_None, // SUB_INT
3194 CEFBS_None, // TEX_GET_GRADIENTS_H
3195 CEFBS_None, // TEX_GET_GRADIENTS_V
3196 CEFBS_None, // TEX_GET_TEXTURE_RESINFO
3197 CEFBS_None, // TEX_LD
3198 CEFBS_None, // TEX_LDPTR
3199 CEFBS_None, // TEX_SAMPLE
3200 CEFBS_None, // TEX_SAMPLE_C
3201 CEFBS_None, // TEX_SAMPLE_C_G
3202 CEFBS_None, // TEX_SAMPLE_C_L
3203 CEFBS_None, // TEX_SAMPLE_C_LB
3204 CEFBS_None, // TEX_SAMPLE_G
3205 CEFBS_None, // TEX_SAMPLE_L
3206 CEFBS_None, // TEX_SAMPLE_LB
3207 CEFBS_None, // TEX_SET_GRADIENTS_H
3208 CEFBS_None, // TEX_SET_GRADIENTS_V
3209 CEFBS_None, // TEX_VTX_CONSTBUF
3210 CEFBS_None, // TEX_VTX_TEXBUF
3211 CEFBS_None, // TRUNC
3212 CEFBS_None, // UINT_TO_FLT_eg
3213 CEFBS_None, // UINT_TO_FLT_r600
3214 CEFBS_None, // VTX_READ_128_cm
3215 CEFBS_None, // VTX_READ_128_eg
3216 CEFBS_None, // VTX_READ_16_cm
3217 CEFBS_None, // VTX_READ_16_eg
3218 CEFBS_None, // VTX_READ_32_cm
3219 CEFBS_None, // VTX_READ_32_eg
3220 CEFBS_None, // VTX_READ_64_cm
3221 CEFBS_None, // VTX_READ_64_eg
3222 CEFBS_None, // VTX_READ_8_cm
3223 CEFBS_None, // VTX_READ_8_eg
3224 CEFBS_None, // WHILE_LOOP_EG
3225 CEFBS_None, // WHILE_LOOP_R600
3226 CEFBS_None, // XOR_INT
3227 };
3228
3229 assert(Opcode < 663);
3230 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3231}
3232
3233
3234} // namespace llvm::R600_MC
3235
3236#endif // GET_COMPUTE_FEATURES
3237
3238#ifdef GET_AVAILABLE_OPCODE_CHECKER
3239#undef GET_AVAILABLE_OPCODE_CHECKER
3240
3241namespace llvm::R600_MC {
3242
3243bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3244 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3245 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3246 FeatureBitset MissingFeatures =
3247 (AvailableFeatures & RequiredFeatures) ^
3248 RequiredFeatures;
3249 return !MissingFeatures.any();
3250}
3251
3252} // namespace llvm::R600_MC
3253
3254#endif // GET_AVAILABLE_OPCODE_CHECKER
3255
3256#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3257#undef ENABLE_INSTR_PREDICATE_VERIFIER
3258
3259#include <sstream>
3260
3261namespace llvm::R600_MC {
3262
3263#ifndef NDEBUG
3264static const char *SubtargetFeatureNames[] = {
3265 nullptr
3266};
3267
3268#endif // NDEBUG
3269
3270void verifyInstructionPredicates(
3271 unsigned Opcode, const FeatureBitset &Features) {
3272#ifndef NDEBUG
3273 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3274 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3275 FeatureBitset MissingFeatures =
3276 (AvailableFeatures & RequiredFeatures) ^
3277 RequiredFeatures;
3278 if (MissingFeatures.any()) {
3279 std::ostringstream Msg;
3280 Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
3281 << " instruction but the ";
3282 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3283 if (MissingFeatures.test(i))
3284 Msg << SubtargetFeatureNames[i] << " ";
3285 Msg << "predicate(s) are not met";
3286 report_fatal_error(Msg.str().c_str());
3287 }
3288#endif // NDEBUG
3289}
3290
3291} // namespace llvm::R600_MC
3292
3293#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3294
3295#ifdef GET_INSTRMAP_INFO
3296#undef GET_INSTRMAP_INFO
3297
3298namespace llvm::R600 {
3299
3300enum usesCustomInserter {
3301 usesCustomInserter_0
3302};
3303
3304// getLDSNoRetOp
3305LLVM_READONLY
3306int getLDSNoRetOp(uint16_t Opcode) {
3307 using namespace R600;
3308 static constexpr uint16_t Table[][2] = {
3309 { LDS_ADD_RET, LDS_ADD },
3310 { LDS_AND_RET, LDS_AND },
3311 { LDS_MAX_INT_RET, LDS_MAX_INT },
3312 { LDS_MAX_UINT_RET, LDS_MAX_UINT },
3313 { LDS_MIN_INT_RET, LDS_MIN_INT },
3314 { LDS_MIN_UINT_RET, LDS_MIN_UINT },
3315 { LDS_OR_RET, LDS_OR },
3316 { LDS_SUB_RET, LDS_SUB },
3317 { LDS_WRXCHG_RET, LDS_WRXCHG },
3318 { LDS_XOR_RET, LDS_XOR },
3319 }; // End of Table
3320
3321 unsigned mid;
3322 unsigned start = 0;
3323 unsigned end = 10;
3324 while (start < end) {
3325 mid = start + (end - start) / 2;
3326 if (Opcode == Table[mid][0])
3327 break;
3328 if (Opcode < Table[mid][0])
3329 end = mid;
3330 else
3331 start = mid + 1;
3332 }
3333 if (start == end)
3334 return -1; // Instruction doesn't exist in this table.
3335
3336 return Table[mid][1];
3337}
3338
3339
3340} // namespace llvm::R600
3341
3342#endif // GET_INSTRMAP_INFO
3343
3344