1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::R600 {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1530
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543
96 G_INSERT = 81, // GenericOpcodes.td:1552
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1562
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330
114 G_LOAD = 99, // GenericOpcodes.td:1357
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1366
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1374
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1383
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410
121 G_STORE = 106, // GenericOpcodes.td:1418
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1436
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1508
150 G_PREFETCH = 135, // GenericOpcodes.td:1515
151 G_BRCOND = 136, // GenericOpcodes.td:1655
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1664
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687
154 G_INTRINSIC = 139, // GenericOpcodes.td:1607
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:609
183 G_UADDE = 168, // GenericOpcodes.td:617
184 G_USUBO = 169, // GenericOpcodes.td:639
185 G_USUBE = 170, // GenericOpcodes.td:645
186 G_SADDO = 171, // GenericOpcodes.td:624
187 G_SADDE = 172, // GenericOpcodes.td:632
188 G_SSUBO = 173, // GenericOpcodes.td:652
189 G_SSUBE = 174, // GenericOpcodes.td:659
190 G_UMULO = 175, // GenericOpcodes.td:666
191 G_SMULO = 176, // GenericOpcodes.td:674
192 G_UMULH = 177, // GenericOpcodes.td:683
193 G_SMULH = 178, // GenericOpcodes.td:692
194 G_UADDSAT = 179, // GenericOpcodes.td:704
195 G_SADDSAT = 180, // GenericOpcodes.td:712
196 G_USUBSAT = 181, // GenericOpcodes.td:720
197 G_SSUBSAT = 182, // GenericOpcodes.td:728
198 G_USHLSAT = 183, // GenericOpcodes.td:736
199 G_SSHLSAT = 184, // GenericOpcodes.td:744
200 G_SMULFIX = 185, // GenericOpcodes.td:756
201 G_UMULFIX = 186, // GenericOpcodes.td:763
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:773
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:780
204 G_SDIVFIX = 189, // GenericOpcodes.td:791
205 G_UDIVFIX = 190, // GenericOpcodes.td:798
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:808
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:815
208 G_FADD = 193, // GenericOpcodes.td:988
209 G_FSUB = 194, // GenericOpcodes.td:996
210 G_FMUL = 195, // GenericOpcodes.td:1004
211 G_FMA = 196, // GenericOpcodes.td:1013
212 G_FMAD = 197, // GenericOpcodes.td:1022
213 G_FDIV = 198, // GenericOpcodes.td:1030
214 G_FREM = 199, // GenericOpcodes.td:1037
215 G_FMODF = 200, // GenericOpcodes.td:1044
216 G_FPOW = 201, // GenericOpcodes.td:1051
217 G_FPOWI = 202, // GenericOpcodes.td:1058
218 G_FEXP = 203, // GenericOpcodes.td:1065
219 G_FEXP2 = 204, // GenericOpcodes.td:1072
220 G_FEXP10 = 205, // GenericOpcodes.td:1079
221 G_FLOG = 206, // GenericOpcodes.td:1086
222 G_FLOG2 = 207, // GenericOpcodes.td:1093
223 G_FLOG10 = 208, // GenericOpcodes.td:1100
224 G_FLDEXP = 209, // GenericOpcodes.td:1107
225 G_FFREXP = 210, // GenericOpcodes.td:1114
226 G_FNEG = 211, // GenericOpcodes.td:826
227 G_FPEXT = 212, // GenericOpcodes.td:832
228 G_FPTRUNC = 213, // GenericOpcodes.td:838
229 G_FPTOSI = 214, // GenericOpcodes.td:844
230 G_FPTOUI = 215, // GenericOpcodes.td:850
231 G_SITOFP = 216, // GenericOpcodes.td:856
232 G_UITOFP = 217, // GenericOpcodes.td:862
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:868
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:874
235 G_FABS = 220, // GenericOpcodes.td:880
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:886
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:899
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:892
239 G_FMINNUM = 224, // GenericOpcodes.td:912
240 G_FMAXNUM = 225, // GenericOpcodes.td:919
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944
243 G_FMINIMUM = 228, // GenericOpcodes.td:954
244 G_FMAXIMUM = 229, // GenericOpcodes.td:961
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:969
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976
247 G_GET_FPENV = 232, // GenericOpcodes.td:1244
248 G_SET_FPENV = 233, // GenericOpcodes.td:1251
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1258
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1265
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1272
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1279
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1336
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1342
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1645
265 G_BRJT = 250, // GenericOpcodes.td:1675
266 G_VSCALE = 251, // GenericOpcodes.td:1573
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1770
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_FCEIL = 270, // GenericOpcodes.td:1121
286 G_FCOS = 271, // GenericOpcodes.td:1128
287 G_FSIN = 272, // GenericOpcodes.td:1135
288 G_FSINCOS = 273, // GenericOpcodes.td:1142
289 G_FTAN = 274, // GenericOpcodes.td:1149
290 G_FACOS = 275, // GenericOpcodes.td:1156
291 G_FASIN = 276, // GenericOpcodes.td:1163
292 G_FATAN = 277, // GenericOpcodes.td:1170
293 G_FATAN2 = 278, // GenericOpcodes.td:1177
294 G_FCOSH = 279, // GenericOpcodes.td:1184
295 G_FSINH = 280, // GenericOpcodes.td:1191
296 G_FTANH = 281, // GenericOpcodes.td:1198
297 G_FSQRT = 282, // GenericOpcodes.td:1208
298 G_FFLOOR = 283, // GenericOpcodes.td:1215
299 G_FRINT = 284, // GenericOpcodes.td:1222
300 G_FNEARBYINT = 285, // GenericOpcodes.td:1229
301 G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248
302 G_BLOCK_ADDR = 287, // GenericOpcodes.td:254
303 G_JUMP_TABLE = 288, // GenericOpcodes.td:260
304 G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266
305 G_STACKSAVE = 290, // GenericOpcodes.td:272
306 G_STACKRESTORE = 291, // GenericOpcodes.td:278
307 G_STRICT_FADD = 292, // GenericOpcodes.td:1829
308 G_STRICT_FSUB = 293, // GenericOpcodes.td:1830
309 G_STRICT_FMUL = 294, // GenericOpcodes.td:1831
310 G_STRICT_FDIV = 295, // GenericOpcodes.td:1832
311 G_STRICT_FREM = 296, // GenericOpcodes.td:1833
312 G_STRICT_FMA = 297, // GenericOpcodes.td:1834
313 G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835
314 G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836
315 G_STRICT_FCMP = 300, // GenericOpcodes.td:1837
316 G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838
317 G_READ_REGISTER = 302, // GenericOpcodes.td:1694
318 G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704
319 G_MEMCPY = 304, // GenericOpcodes.td:1844
320 G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852
321 G_MEMMOVE = 306, // GenericOpcodes.td:1860
322 G_MEMSET = 307, // GenericOpcodes.td:1868
323 G_BZERO = 308, // GenericOpcodes.td:1875
324 G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882
325 G_TRAP = 310, // GenericOpcodes.td:1892
326 G_DEBUGTRAP = 311, // GenericOpcodes.td:1899
327 G_UBSANTRAP = 312, // GenericOpcodes.td:1905
328 G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793
329 G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799
330 G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805
331 G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806
332 G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808
333 G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809
334 G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810
335 G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811
336 G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812
337 G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813
338 G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815
339 G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816
340 G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817
341 G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818
342 G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819
343 G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820
344 G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821
345 G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822
346 G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823
347 G_SBFX = 332, // GenericOpcodes.td:1917
348 G_UBFX = 333, // GenericOpcodes.td:1925
349 BRANCH = 334, // R600Instructions.td:1594
350 BRANCH_COND_f32 = 335, // R600Instructions.td:1567
351 BRANCH_COND_i32 = 336, // R600Instructions.td:1563
352 BREAK = 337, // R600Instructions.td:1608
353 BREAKC_f32 = 338, // R600Instructions.td:1584
354 BREAKC_i32 = 339, // R600Instructions.td:1582
355 BREAK_LOGICALNZ_f32 = 340, // R600Instructions.td:1577
356 BREAK_LOGICALNZ_i32 = 341, // R600Instructions.td:1575
357 BREAK_LOGICALZ_f32 = 342, // R600Instructions.td:1577
358 BREAK_LOGICALZ_i32 = 343, // R600Instructions.td:1575
359 CONST_COPY = 344, // R600Instructions.td:1439
360 CONTINUE = 345, // R600Instructions.td:1610
361 CONTINUEC_f32 = 346, // R600Instructions.td:1584
362 CONTINUEC_i32 = 347, // R600Instructions.td:1582
363 CONTINUE_LOGICALNZ_f32 = 348, // R600Instructions.td:1577
364 CONTINUE_LOGICALNZ_i32 = 349, // R600Instructions.td:1575
365 CONTINUE_LOGICALZ_f32 = 350, // R600Instructions.td:1577
366 CONTINUE_LOGICALZ_i32 = 351, // R600Instructions.td:1575
367 CUBE_eg_pseudo = 352, // R600Instructions.td:1074
368 CUBE_r600_pseudo = 353, // R600Instructions.td:1074
369 DEFAULT = 354, // R600Instructions.td:1612
370 DOT_4 = 355, // R600Instructions.td:1061
371 DUMMY_CHAIN = 356, // R600Instructions.td:792
372 ELSE = 357, // R600Instructions.td:1614
373 END = 358, // R600Instructions.td:1620
374 ENDFUNC = 359, // R600Instructions.td:1622
375 ENDIF = 360, // R600Instructions.td:1624
376 ENDLOOP = 361, // R600Instructions.td:1628
377 ENDMAIN = 362, // R600Instructions.td:1618
378 ENDSWITCH = 363, // R600Instructions.td:1616
379 FABS_R600 = 364, // R600Instructions.td:1204
380 FNEG_R600 = 365, // R600Instructions.td:1205
381 FUNC = 366, // R600Instructions.td:1630
382 IFC_f32 = 367, // R600Instructions.td:1584
383 IFC_i32 = 368, // R600Instructions.td:1582
384 IF_LOGICALNZ_f32 = 369, // R600Instructions.td:1577
385 IF_LOGICALNZ_i32 = 370, // R600Instructions.td:1575
386 IF_LOGICALZ_f32 = 371, // R600Instructions.td:1577
387 IF_LOGICALZ_i32 = 372, // R600Instructions.td:1575
388 IF_PREDICATE_SET = 373, // R600Instructions.td:1604
389 JUMP = 374, // R600Instructions.td:1385
390 JUMP_COND = 375, // R600Instructions.td:1378
391 MASK_WRITE = 376, // R600Instructions.td:1402
392 MOV_IMM_F32 = 377, // R600Instructions.td:827
393 MOV_IMM_GLOBAL_ADDR = 378, // R600Instructions.td:820
394 MOV_IMM_I32 = 379, // R600Instructions.td:814
395 PRED_X = 380, // R600Instructions.td:1370
396 R600_EXTRACT_ELT_V2 = 381, // R600Instructions.td:1677
397 R600_EXTRACT_ELT_V4 = 382, // R600Instructions.td:1678
398 R600_INSERT_ELT_V2 = 383, // R600Instructions.td:1680
399 R600_INSERT_ELT_V4 = 384, // R600Instructions.td:1681
400 R600_RegisterLoad = 385, // R600Instructions.td:698
401 R600_RegisterStore = 386, // R600Instructions.td:707
402 RETDYN = 387, // R600Instructions.td:1632
403 RETURN = 388, // R600Instructions.td:88
404 TXD = 389, // R600Instructions.td:1413
405 TXD_SHADOW = 390, // R600Instructions.td:1422
406 WHILELOOP = 391, // R600Instructions.td:1626
407 ADD = 392, // R600Instructions.td:721
408 ADDC_UINT = 393, // EvergreenInstructions.td:523
409 ADD_INT = 394, // R600Instructions.td:848
410 ALU_CLAUSE = 395, // R600Instructions.td:646
411 AND_INT = 396, // R600Instructions.td:844
412 ASHR_eg = 397, // EvergreenInstructions.td:508
413 ASHR_r600 = 398, // R600Instructions.td:1253
414 BCNT_INT = 399, // EvergreenInstructions.td:528
415 BFE_INT_eg = 400, // EvergreenInstructions.td:370
416 BFE_UINT_eg = 401, // EvergreenInstructions.td:365
417 BFI_INT_eg = 402, // EvergreenInstructions.td:411
418 BFM_INT_eg = 403, // EvergreenInstructions.td:492
419 BIT_ALIGN_INT_eg = 404, // EvergreenInstructions.td:500
420 CEIL = 405, // R600Instructions.td:781
421 CF_ALU = 406, // R600Instructions.td:631
422 CF_ALU_BREAK = 407, // R600Instructions.td:635
423 CF_ALU_CONTINUE = 408, // R600Instructions.td:634
424 CF_ALU_ELSE_AFTER = 409, // R600Instructions.td:636
425 CF_ALU_POP_AFTER = 410, // R600Instructions.td:633
426 CF_ALU_PUSH_BEFORE = 411, // R600Instructions.td:632
427 CF_CALL_FS_EG = 412, // EvergreenInstructions.td:850
428 CF_CALL_FS_R600 = 413, // R600Instructions.td:1325
429 CF_CONTINUE_EG = 414, // EvergreenInstructions.td:833
430 CF_CONTINUE_R600 = 415, // R600Instructions.td:1307
431 CF_ELSE_EG = 416, // EvergreenInstructions.td:846
432 CF_ELSE_R600 = 417, // R600Instructions.td:1321
433 CF_END_CM = 418, // CaymanInstructions.td:66
434 CF_END_EG = 419, // EvergreenInstructions.td:859
435 CF_END_R600 = 420, // R600Instructions.td:1334
436 CF_JUMP_EG = 421, // EvergreenInstructions.td:838
437 CF_JUMP_R600 = 422, // R600Instructions.td:1312
438 CF_PUSH_EG = 423, // EvergreenInstructions.td:842
439 CF_PUSH_ELSE_R600 = 424, // R600Instructions.td:1316
440 CF_TC_EG = 425, // EvergreenInstructions.td:811
441 CF_TC_R600 = 426, // R600Instructions.td:1285
442 CF_VC_EG = 427, // EvergreenInstructions.td:815
443 CF_VC_R600 = 428, // R600Instructions.td:1289
444 CNDE_INT = 429, // R600Instructions.td:890
445 CNDE_eg = 430, // EvergreenInstructions.td:511
446 CNDE_r600 = 431, // R600Instructions.td:1235
447 CNDGE_INT = 432, // R600Instructions.td:895
448 CNDGE_eg = 433, // EvergreenInstructions.td:513
449 CNDGE_r600 = 434, // R600Instructions.td:1237
450 CNDGT_INT = 435, // R600Instructions.td:900
451 CNDGT_eg = 436, // EvergreenInstructions.td:512
452 CNDGT_r600 = 437, // R600Instructions.td:1236
453 COS_cm = 438, // CaymanInstructions.td:48
454 COS_eg = 439, // EvergreenInstructions.td:132
455 COS_r600 = 440, // R600Instructions.td:1252
456 COS_r700 = 441, // R700Instructions.td:19
457 CUBE_eg_real = 442, // R600Instructions.td:1085
458 CUBE_r600_real = 443, // R600Instructions.td:1085
459 DOT4_eg = 444, // EvergreenInstructions.td:519
460 DOT4_r600 = 445, // R600Instructions.td:1238
461 EG_ExportBuf = 446, // EvergreenInstructions.td:801
462 EG_ExportSwz = 447, // EvergreenInstructions.td:791
463 END_LOOP_EG = 448, // EvergreenInstructions.td:824
464 END_LOOP_R600 = 449, // R600Instructions.td:1298
465 EXP_IEEE_cm = 450, // CaymanInstructions.td:43
466 EXP_IEEE_eg = 451, // EvergreenInstructions.td:125
467 EXP_IEEE_r600 = 452, // R600Instructions.td:1240
468 FETCH_CLAUSE = 453, // R600Instructions.td:638
469 FFBH_UINT = 454, // EvergreenInstructions.td:529
470 FFBL_INT = 455, // EvergreenInstructions.td:530
471 FLOOR = 456, // R600Instructions.td:783
472 FLT16_TO_FLT32 = 457, // EvergreenInstructions.td:527
473 FLT32_TO_FLT16 = 458, // EvergreenInstructions.td:526
474 FLT_TO_INT_eg = 459, // EvergreenInstructions.td:536
475 FLT_TO_INT_r600 = 460, // R600Instructions.td:1247
476 FLT_TO_UINT_eg = 461, // EvergreenInstructions.td:543
477 FLT_TO_UINT_r600 = 462, // R600Instructions.td:1249
478 FMA_eg = 463, // EvergreenInstructions.td:507
479 FRACT = 464, // R600Instructions.td:779
480 GROUP_BARRIER = 465, // EvergreenInstructions.td:549
481 INTERP_LOAD_P0 = 466, // R600Instructions.td:445
482 INTERP_PAIR_XY = 467, // R600Instructions.td:367
483 INTERP_PAIR_ZW = 468, // R600Instructions.td:373
484 INTERP_VEC_LOAD = 469, // R600Instructions.td:430
485 INTERP_XY = 470, // R600Instructions.td:437
486 INTERP_ZW = 471, // R600Instructions.td:441
487 INT_TO_FLT_eg = 472, // EvergreenInstructions.td:541
488 INT_TO_FLT_r600 = 473, // R600Instructions.td:1248
489 KILLGT = 474, // R600Instructions.td:840
490 LDS_ADD = 475, // EvergreenInstructions.td:687
491 LDS_ADD_RET = 476, // EvergreenInstructions.td:707
492 LDS_AND = 477, // EvergreenInstructions.td:689
493 LDS_AND_RET = 478, // EvergreenInstructions.td:713
494 LDS_BYTE_READ_RET = 479, // EvergreenInstructions.td:743
495 LDS_BYTE_WRITE = 480, // EvergreenInstructions.td:701
496 LDS_CMPST = 481, // EvergreenInstructions.td:693
497 LDS_CMPST_RET = 482, // EvergreenInstructions.td:737
498 LDS_MAX_INT = 483, // EvergreenInstructions.td:695
499 LDS_MAX_INT_RET = 484, // EvergreenInstructions.td:725
500 LDS_MAX_UINT = 485, // EvergreenInstructions.td:697
501 LDS_MAX_UINT_RET = 486, // EvergreenInstructions.td:731
502 LDS_MIN_INT = 487, // EvergreenInstructions.td:694
503 LDS_MIN_INT_RET = 488, // EvergreenInstructions.td:722
504 LDS_MIN_UINT = 489, // EvergreenInstructions.td:696
505 LDS_MIN_UINT_RET = 490, // EvergreenInstructions.td:728
506 LDS_OR = 491, // EvergreenInstructions.td:690
507 LDS_OR_RET = 492, // EvergreenInstructions.td:716
508 LDS_READ_RET = 493, // EvergreenInstructions.td:740
509 LDS_SHORT_READ_RET = 494, // EvergreenInstructions.td:749
510 LDS_SHORT_WRITE = 495, // EvergreenInstructions.td:704
511 LDS_SUB = 496, // EvergreenInstructions.td:688
512 LDS_SUB_RET = 497, // EvergreenInstructions.td:710
513 LDS_UBYTE_READ_RET = 498, // EvergreenInstructions.td:746
514 LDS_USHORT_READ_RET = 499, // EvergreenInstructions.td:752
515 LDS_WRITE = 500, // EvergreenInstructions.td:698
516 LDS_WRXCHG = 501, // EvergreenInstructions.td:692
517 LDS_WRXCHG_RET = 502, // EvergreenInstructions.td:734
518 LDS_XOR = 503, // EvergreenInstructions.td:691
519 LDS_XOR_RET = 504, // EvergreenInstructions.td:719
520 LITERALS = 505, // R600Instructions.td:654
521 LOG_CLAMPED_eg = 506, // EvergreenInstructions.td:515
522 LOG_CLAMPED_r600 = 507, // R600Instructions.td:1241
523 LOG_IEEE_cm = 508, // CaymanInstructions.td:44
524 LOG_IEEE_eg = 509, // EvergreenInstructions.td:126
525 LOG_IEEE_r600 = 510, // R600Instructions.td:1242
526 LOOP_BREAK_EG = 511, // EvergreenInstructions.td:828
527 LOOP_BREAK_R600 = 512, // R600Instructions.td:1302
528 LSHL_eg = 513, // EvergreenInstructions.td:510
529 LSHL_r600 = 514, // R600Instructions.td:1255
530 LSHR_eg = 515, // EvergreenInstructions.td:509
531 LSHR_r600 = 516, // R600Instructions.td:1254
532 MAX = 517, // R600Instructions.td:726
533 MAX_DX10 = 518, // R600Instructions.td:731
534 MAX_INT = 519, // R600Instructions.td:850
535 MAX_UINT = 520, // R600Instructions.td:852
536 MIN = 521, // R600Instructions.td:727
537 MIN_DX10 = 522, // R600Instructions.td:732
538 MIN_INT = 523, // R600Instructions.td:851
539 MIN_UINT = 524, // R600Instructions.td:853
540 MOV = 525, // R600Instructions.td:785
541 MOVA_INT_eg = 526, // EvergreenInstructions.td:533
542 MUL = 527, // R600Instructions.td:723
543 MULADD_IEEE_eg = 528, // EvergreenInstructions.td:506
544 MULADD_IEEE_r600 = 529, // R600Instructions.td:1234
545 MULADD_INT24_cm = 530, // CaymanInstructions.td:22
546 MULADD_UINT24_eg = 531, // EvergreenInstructions.td:494
547 MULADD_eg = 532, // EvergreenInstructions.td:505
548 MULADD_r600 = 533, // R600Instructions.td:1233
549 MULHI_INT_cm = 534, // CaymanInstructions.td:36
550 MULHI_INT_cm24 = 535, // CaymanInstructions.td:39
551 MULHI_INT_eg = 536, // EvergreenInstructions.td:118
552 MULHI_INT_r600 = 537, // R600Instructions.td:1257
553 MULHI_UINT24_eg = 538, // EvergreenInstructions.td:121
554 MULHI_UINT_cm = 539, // CaymanInstructions.td:38
555 MULHI_UINT_cm24 = 540, // CaymanInstructions.td:40
556 MULHI_UINT_eg = 541, // EvergreenInstructions.td:120
557 MULHI_UINT_r600 = 542, // R600Instructions.td:1259
558 MULLO_INT_cm = 543, // CaymanInstructions.td:35
559 MULLO_INT_eg = 544, // EvergreenInstructions.td:117
560 MULLO_INT_r600 = 545, // R600Instructions.td:1256
561 MULLO_UINT_cm = 546, // CaymanInstructions.td:37
562 MULLO_UINT_eg = 547, // EvergreenInstructions.td:119
563 MULLO_UINT_r600 = 548, // R600Instructions.td:1258
564 MUL_IEEE = 549, // R600Instructions.td:724
565 MUL_INT24_cm = 550, // CaymanInstructions.td:25
566 MUL_LIT_eg = 551, // EvergreenInstructions.td:514
567 MUL_LIT_r600 = 552, // R600Instructions.td:1232
568 MUL_UINT24_eg = 553, // EvergreenInstructions.td:516
569 NOT_INT = 554, // R600Instructions.td:847
570 OR_INT = 555, // R600Instructions.td:845
571 PAD = 556, // R600Instructions.td:666
572 POP_EG = 557, // EvergreenInstructions.td:855
573 POP_R600 = 558, // R600Instructions.td:1330
574 PRED_SETE = 559, // R600Instructions.td:833
575 PRED_SETE_INT = 560, // R600Instructions.td:885
576 PRED_SETGE = 561, // R600Instructions.td:835
577 PRED_SETGE_INT = 562, // R600Instructions.td:887
578 PRED_SETGT = 563, // R600Instructions.td:834
579 PRED_SETGT_INT = 564, // R600Instructions.td:886
580 PRED_SETNE = 565, // R600Instructions.td:836
581 PRED_SETNE_INT = 566, // R600Instructions.td:888
582 R600_ExportBuf = 567, // R600Instructions.td:1276
583 R600_ExportSwz = 568, // R600Instructions.td:1267
584 RAT_ATOMIC_ADD_NORET = 569, // EvergreenInstructions.td:82
585 RAT_ATOMIC_ADD_RTN = 570, // EvergreenInstructions.td:78
586 RAT_ATOMIC_AND_NORET = 571, // EvergreenInstructions.td:82
587 RAT_ATOMIC_AND_RTN = 572, // EvergreenInstructions.td:78
588 RAT_ATOMIC_CMPXCHG_INT_NORET = 573, // EvergreenInstructions.td:82
589 RAT_ATOMIC_CMPXCHG_INT_RTN = 574, // EvergreenInstructions.td:78
590 RAT_ATOMIC_DEC_UINT_NORET = 575, // EvergreenInstructions.td:82
591 RAT_ATOMIC_DEC_UINT_RTN = 576, // EvergreenInstructions.td:78
592 RAT_ATOMIC_INC_UINT_NORET = 577, // EvergreenInstructions.td:82
593 RAT_ATOMIC_INC_UINT_RTN = 578, // EvergreenInstructions.td:78
594 RAT_ATOMIC_MAX_INT_NORET = 579, // EvergreenInstructions.td:82
595 RAT_ATOMIC_MAX_INT_RTN = 580, // EvergreenInstructions.td:78
596 RAT_ATOMIC_MAX_UINT_NORET = 581, // EvergreenInstructions.td:82
597 RAT_ATOMIC_MAX_UINT_RTN = 582, // EvergreenInstructions.td:78
598 RAT_ATOMIC_MIN_INT_NORET = 583, // EvergreenInstructions.td:82
599 RAT_ATOMIC_MIN_INT_RTN = 584, // EvergreenInstructions.td:78
600 RAT_ATOMIC_MIN_UINT_NORET = 585, // EvergreenInstructions.td:82
601 RAT_ATOMIC_MIN_UINT_RTN = 586, // EvergreenInstructions.td:78
602 RAT_ATOMIC_OR_NORET = 587, // EvergreenInstructions.td:82
603 RAT_ATOMIC_OR_RTN = 588, // EvergreenInstructions.td:78
604 RAT_ATOMIC_RSUB_NORET = 589, // EvergreenInstructions.td:82
605 RAT_ATOMIC_RSUB_RTN = 590, // EvergreenInstructions.td:78
606 RAT_ATOMIC_SUB_NORET = 591, // EvergreenInstructions.td:82
607 RAT_ATOMIC_SUB_RTN = 592, // EvergreenInstructions.td:78
608 RAT_ATOMIC_XCHG_INT_NORET = 593, // EvergreenInstructions.td:82
609 RAT_ATOMIC_XCHG_INT_RTN = 594, // EvergreenInstructions.td:78
610 RAT_ATOMIC_XOR_NORET = 595, // EvergreenInstructions.td:82
611 RAT_ATOMIC_XOR_RTN = 596, // EvergreenInstructions.td:78
612 RAT_MSKOR = 597, // EvergreenInstructions.td:67
613 RAT_STORE_DWORD128 = 598, // CaymanInstructions.td:84
614 RAT_STORE_DWORD32 = 599, // CaymanInstructions.td:82
615 RAT_STORE_DWORD64 = 600, // CaymanInstructions.td:83
616 RAT_STORE_TYPED_cm = 601, // CaymanInstructions.td:86
617 RAT_STORE_TYPED_eg = 602, // EvergreenInstructions.td:164
618 RAT_WRITE_CACHELESS_128_eg = 603, // EvergreenInstructions.td:158
619 RAT_WRITE_CACHELESS_32_eg = 604, // EvergreenInstructions.td:144
620 RAT_WRITE_CACHELESS_64_eg = 605, // EvergreenInstructions.td:151
621 RECIPSQRT_CLAMPED_cm = 606, // CaymanInstructions.td:42
622 RECIPSQRT_CLAMPED_eg = 607, // EvergreenInstructions.td:124
623 RECIPSQRT_CLAMPED_r600 = 608, // R600Instructions.td:1245
624 RECIPSQRT_IEEE_cm = 609, // CaymanInstructions.td:46
625 RECIPSQRT_IEEE_eg = 610, // EvergreenInstructions.td:128
626 RECIPSQRT_IEEE_r600 = 611, // R600Instructions.td:1246
627 RECIP_CLAMPED_cm = 612, // CaymanInstructions.td:45
628 RECIP_CLAMPED_eg = 613, // EvergreenInstructions.td:127
629 RECIP_CLAMPED_r600 = 614, // R600Instructions.td:1243
630 RECIP_IEEE_cm = 615, // CaymanInstructions.td:33
631 RECIP_IEEE_eg = 616, // EvergreenInstructions.td:114
632 RECIP_IEEE_r600 = 617, // R600Instructions.td:1244
633 RECIP_UINT_eg = 618, // EvergreenInstructions.td:123
634 RECIP_UINT_r600 = 619, // R600Instructions.td:1260
635 RNDNE = 620, // R600Instructions.td:782
636 SETE = 621, // R600Instructions.td:737
637 SETE_DX10 = 622, // R600Instructions.td:757
638 SETE_INT = 623, // R600Instructions.td:855
639 SETGE_DX10 = 624, // R600Instructions.td:767
640 SETGE_INT = 625, // R600Instructions.td:865
641 SETGE_UINT = 626, // R600Instructions.td:880
642 SETGT_DX10 = 627, // R600Instructions.td:762
643 SETGT_INT = 628, // R600Instructions.td:860
644 SETGT_UINT = 629, // R600Instructions.td:875
645 SETNE_DX10 = 630, // R600Instructions.td:773
646 SETNE_INT = 631, // R600Instructions.td:870
647 SGE = 632, // R600Instructions.td:747
648 SGT = 633, // R600Instructions.td:742
649 SIN_cm = 634, // CaymanInstructions.td:47
650 SIN_eg = 635, // EvergreenInstructions.td:131
651 SIN_r600 = 636, // R600Instructions.td:1251
652 SIN_r700 = 637, // R700Instructions.td:18
653 SNE = 638, // R600Instructions.td:752
654 SUBB_UINT = 639, // EvergreenInstructions.td:524
655 SUB_INT = 640, // R600Instructions.td:849
656 TEX_GET_GRADIENTS_H = 641, // R600Instructions.td:959
657 TEX_GET_GRADIENTS_V = 642, // R600Instructions.td:960
658 TEX_GET_TEXTURE_RESINFO = 643, // R600Instructions.td:958
659 TEX_LD = 644, // R600Instructions.td:954
660 TEX_LDPTR = 645, // R600Instructions.td:955
661 TEX_SAMPLE = 646, // R600Instructions.td:948
662 TEX_SAMPLE_C = 647, // R600Instructions.td:949
663 TEX_SAMPLE_C_G = 648, // R600Instructions.td:964
664 TEX_SAMPLE_C_L = 649, // R600Instructions.td:951
665 TEX_SAMPLE_C_LB = 650, // R600Instructions.td:953
666 TEX_SAMPLE_G = 651, // R600Instructions.td:963
667 TEX_SAMPLE_L = 652, // R600Instructions.td:950
668 TEX_SAMPLE_LB = 653, // R600Instructions.td:952
669 TEX_SET_GRADIENTS_H = 654, // R600Instructions.td:961
670 TEX_SET_GRADIENTS_V = 655, // R600Instructions.td:962
671 TEX_VTX_CONSTBUF = 656, // R600Instructions.td:1451
672 TEX_VTX_TEXBUF = 657, // R600Instructions.td:1505
673 TRUNC = 658, // R600Instructions.td:780
674 UINT_TO_FLT_eg = 659, // EvergreenInstructions.td:547
675 UINT_TO_FLT_r600 = 660, // R600Instructions.td:1250
676 VTX_READ_128_cm = 661, // CaymanInstructions.td:162
677 VTX_READ_128_eg = 662, // EvergreenInstructions.td:240
678 VTX_READ_16_cm = 663, // CaymanInstructions.td:120
679 VTX_READ_16_eg = 664, // EvergreenInstructions.td:195
680 VTX_READ_32_cm = 665, // CaymanInstructions.td:131
681 VTX_READ_32_eg = 666, // EvergreenInstructions.td:207
682 VTX_READ_64_cm = 667, // CaymanInstructions.td:151
683 VTX_READ_64_eg = 668, // EvergreenInstructions.td:228
684 VTX_READ_8_cm = 669, // CaymanInstructions.td:109
685 VTX_READ_8_eg = 670, // EvergreenInstructions.td:183
686 WHILE_LOOP_EG = 671, // EvergreenInstructions.td:819
687 WHILE_LOOP_R600 = 672, // R600Instructions.td:1293
688 XOR_INT = 673, // R600Instructions.td:846
689 INSTRUCTION_LIST_END = 674
690 };
691
692} // namespace llvm::R600
693
694#endif // GET_INSTRINFO_ENUM
695
696#ifdef GET_INSTRINFO_SCHED_ENUM
697#undef GET_INSTRINFO_SCHED_ENUM
698
699namespace llvm::R600::Sched {
700
701 enum {
702 NoInstrModel = 0,
703 NullALU = 1,
704 VecALU = 2,
705 AnyALU = 3,
706 TransALU = 4,
707 XALU = 5,
708 SCHED_LIST_END = 6
709 };
710
711} // namespace llvm::R600::Sched
712
713#endif // GET_INSTRINFO_SCHED_ENUM
714
715#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
716
717namespace llvm {
718
719struct R600InstrTable {
720 MCInstrDesc Insts[674];
721 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
722 MCPhysReg ImplicitOps[1];
723 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
724 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
725 MCOperandInfo OperandInfo[461];
726};
727} // namespace llvm
728
729#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
730
731#ifdef GET_INSTRINFO_MC_DESC
732#undef GET_INSTRINFO_MC_DESC
733
734namespace llvm {
735
736static_assert((sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
737static constexpr unsigned R600OpInfoBase = (sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) / sizeof(MCOperandInfo);
738
739extern const R600InstrTable R600Descs = {
740 {
741 { 673, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // XOR_INT
742 { 672, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_R600
743 { 671, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_EG
744 { 670, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_eg
745 { 669, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_cm
746 { 668, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_eg
747 { 667, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_cm
748 { 666, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_eg
749 { 665, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_cm
750 { 664, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_eg
751 { 663, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_cm
752 { 662, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_eg
753 { 661, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_cm
754 { 660, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_r600
755 { 659, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_eg
756 { 658, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // TRUNC
757 { 657, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL }, // TEX_VTX_TEXBUF
758 { 656, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0, 0x1000ULL }, // TEX_VTX_CONSTBUF
759 { 655, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_V
760 { 654, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_H
761 { 653, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_LB
762 { 652, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_L
763 { 651, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_G
764 { 650, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_LB
765 { 649, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_L
766 { 648, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_G
767 { 647, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C
768 { 646, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE
769 { 645, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LDPTR
770 { 644, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LD
771 { 643, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_TEXTURE_RESINFO
772 { 642, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_V
773 { 641, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_H
774 { 640, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUB_INT
775 { 639, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUBB_UINT
776 { 638, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SNE
777 { 637, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r700
778 { 636, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r600
779 { 635, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_eg
780 { 634, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // SIN_cm
781 { 633, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGT
782 { 632, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGE
783 { 631, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_INT
784 { 630, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_DX10
785 { 629, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_UINT
786 { 628, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_INT
787 { 627, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_DX10
788 { 626, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_UINT
789 { 625, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_INT
790 { 624, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_DX10
791 { 623, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_INT
792 { 622, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_DX10
793 { 621, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE
794 { 620, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RNDNE
795 { 619, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_r600
796 { 618, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_eg
797 { 617, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_r600
798 { 616, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_eg
799 { 615, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_IEEE_cm
800 { 614, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_r600
801 { 613, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_eg
802 { 612, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_CLAMPED_cm
803 { 611, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_r600
804 { 610, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_eg
805 { 609, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_IEEE_cm
806 { 608, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_r600
807 { 607, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_eg
808 { 606, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_CLAMPED_cm
809 { 605, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 423, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_64_eg
810 { 604, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 420, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_32_eg
811 { 603, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 417, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_128_eg
812 { 602, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_eg
813 { 601, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_cm
814 { 600, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 411, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD64
815 { 599, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 409, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD32
816 { 598, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD128
817 { 597, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_MSKOR
818 { 596, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_RTN
819 { 595, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_NORET
820 { 594, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_RTN
821 { 593, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_NORET
822 { 592, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_RTN
823 { 591, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_NORET
824 { 590, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_RTN
825 { 589, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_NORET
826 { 588, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_RTN
827 { 587, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_NORET
828 { 586, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_RTN
829 { 585, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_NORET
830 { 584, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_RTN
831 { 583, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_NORET
832 { 582, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_RTN
833 { 581, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_NORET
834 { 580, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_RTN
835 { 579, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_NORET
836 { 578, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_RTN
837 { 577, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_NORET
838 { 576, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_RTN
839 { 575, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_NORET
840 { 574, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_RTN
841 { 573, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_NORET
842 { 572, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_RTN
843 { 571, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_NORET
844 { 570, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_RTN
845 { 569, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_NORET
846 { 568, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportSwz
847 { 567, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportBuf
848 { 566, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE_INT
849 { 565, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE
850 { 564, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT_INT
851 { 563, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT
852 { 562, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE_INT
853 { 561, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE
854 { 560, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE_INT
855 { 559, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE
856 { 558, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_R600
857 { 557, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_EG
858 { 556, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PAD
859 { 555, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // OR_INT
860 { 554, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // NOT_INT
861 { 553, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_UINT24_eg
862 { 552, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_r600
863 { 551, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_eg
864 { 550, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_INT24_cm
865 { 549, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_IEEE
866 { 548, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_r600
867 { 547, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_eg
868 { 546, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_UINT_cm
869 { 545, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_r600
870 { 544, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_eg
871 { 543, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_INT_cm
872 { 542, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_r600
873 { 541, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_eg
874 { 540, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm24
875 { 539, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm
876 { 538, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT24_eg
877 { 537, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_r600
878 { 536, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_eg
879 { 535, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm24
880 { 534, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm
881 { 533, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_r600
882 { 532, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_eg
883 { 531, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_UINT24_eg
884 { 530, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_INT24_cm
885 { 529, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_r600
886 { 528, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_eg
887 { 527, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL
888 { 526, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL }, // MOVA_INT_eg
889 { 525, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // MOV
890 { 524, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_UINT
891 { 523, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_INT
892 { 522, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_DX10
893 { 521, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN
894 { 520, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_UINT
895 { 519, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_INT
896 { 518, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_DX10
897 { 517, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX
898 { 516, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_r600
899 { 515, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_eg
900 { 514, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_r600
901 { 513, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_eg
902 { 512, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_R600
903 { 511, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_EG
904 { 510, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_r600
905 { 509, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_eg
906 { 508, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // LOG_IEEE_cm
907 { 507, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_r600
908 { 506, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_eg
909 { 505, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LITERALS
910 { 504, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_XOR_RET
911 { 503, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_XOR
912 { 502, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_WRXCHG_RET
913 { 501, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_WRXCHG
914 { 500, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_WRITE
915 { 499, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_USHORT_READ_RET
916 { 498, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_UBYTE_READ_RET
917 { 497, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_SUB_RET
918 { 496, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_SUB
919 { 495, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_SHORT_WRITE
920 { 494, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_SHORT_READ_RET
921 { 493, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_READ_RET
922 { 492, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_OR_RET
923 { 491, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_OR
924 { 490, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_UINT_RET
925 { 489, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_UINT
926 { 488, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_INT_RET
927 { 487, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_INT
928 { 486, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_UINT_RET
929 { 485, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_UINT
930 { 484, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_INT_RET
931 { 483, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_INT
932 { 482, 13, 1, 0, 5, 0, 0, R600OpInfoBase + 391, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL }, // LDS_CMPST_RET
933 { 481, 12, 0, 0, 5, 0, 0, R600OpInfoBase + 379, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL }, // LDS_CMPST
934 { 480, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_BYTE_WRITE
935 { 479, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_BYTE_READ_RET
936 { 478, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_AND_RET
937 { 477, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_AND
938 { 476, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_ADD_RET
939 { 475, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_ADD
940 { 474, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL }, // KILLGT
941 { 473, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_r600
942 { 472, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_eg
943 { 471, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_ZW
944 { 470, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_XY
945 { 469, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 351, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_VEC_LOAD
946 { 468, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 346, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_ZW
947 { 467, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 341, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_XY
948 { 466, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INTERP_LOAD_P0
949 { 465, 0, 0, 0, 3, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL }, // GROUP_BARRIER
950 { 464, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FRACT
951 { 463, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // FMA_eg
952 { 462, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_r600
953 { 461, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_eg
954 { 460, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_r600
955 { 459, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_eg
956 { 458, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT32_TO_FLT16
957 { 457, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT16_TO_FLT32
958 { 456, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLOOR
959 { 455, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBL_INT
960 { 454, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBH_UINT
961 { 453, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FETCH_CLAUSE
962 { 452, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_r600
963 { 451, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_eg
964 { 450, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // EXP_IEEE_cm
965 { 449, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_R600
966 { 448, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_EG
967 { 447, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportSwz
968 { 446, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportBuf
969 { 445, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_r600
970 { 444, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_eg
971 { 443, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_r600_real
972 { 442, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_eg_real
973 { 441, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r700
974 { 440, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r600
975 { 439, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_eg
976 { 438, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // COS_cm
977 { 437, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_r600
978 { 436, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_eg
979 { 435, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_INT
980 { 434, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_r600
981 { 433, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_eg
982 { 432, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_INT
983 { 431, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_r600
984 { 430, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_eg
985 { 429, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_INT
986 { 428, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_R600
987 { 427, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_EG
988 { 426, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_R600
989 { 425, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_EG
990 { 424, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_ELSE_R600
991 { 423, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_EG
992 { 422, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_R600
993 { 421, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_EG
994 { 420, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_R600
995 { 419, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_EG
996 { 418, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_CM
997 { 417, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_R600
998 { 416, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_EG
999 { 415, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_R600
1000 { 414, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_EG
1001 { 413, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_R600
1002 { 412, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_EG
1003 { 411, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_PUSH_BEFORE
1004 { 410, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_POP_AFTER
1005 { 409, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_ELSE_AFTER
1006 { 408, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_CONTINUE
1007 { 407, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_BREAK
1008 { 406, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU
1009 { 405, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // CEIL
1010 { 404, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BIT_ALIGN_INT_eg
1011 { 403, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // BFM_INT_eg
1012 { 402, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFI_INT_eg
1013 { 401, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_UINT_eg
1014 { 400, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_INT_eg
1015 { 399, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // BCNT_INT
1016 { 398, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_r600
1017 { 397, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_eg
1018 { 396, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // AND_INT
1019 { 395, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALU_CLAUSE
1020 { 394, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD_INT
1021 { 393, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADDC_UINT
1022 { 392, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD
1023 { 391, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // WHILELOOP
1024 { 390, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD_SHADOW
1025 { 389, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD
1026 { 388, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL }, // RETURN
1027 { 387, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // RETDYN
1028 { 386, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL }, // R600_RegisterStore
1029 { 385, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL }, // R600_RegisterLoad
1030 { 384, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 247, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V4
1031 { 383, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V2
1032 { 382, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V4
1033 { 381, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V2
1034 { 380, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 233, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // PRED_X
1035 { 379, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_I32
1036 { 378, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_GLOBAL_ADDR
1037 { 377, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_F32
1038 { 376, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MASK_WRITE
1039 { 375, 2, 0, 0, 3, 0, 0, R600OpInfoBase + 231, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP_COND
1040 { 374, 1, 0, 0, 3, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP
1041 { 373, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // IF_PREDICATE_SET
1042 { 372, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_i32
1043 { 371, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_f32
1044 { 370, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_i32
1045 { 369, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_f32
1046 { 368, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_i32
1047 { 367, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_f32
1048 { 366, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // FUNC
1049 { 365, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FNEG_R600
1050 { 364, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FABS_R600
1051 { 363, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDSWITCH
1052 { 362, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDMAIN
1053 { 361, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDLOOP
1054 { 360, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDIF
1055 { 359, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDFUNC
1056 { 358, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // END
1057 { 357, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ELSE
1058 { 356, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // DUMMY_CHAIN
1059 { 355, 71, 1, 0, 3, 0, 0, R600OpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // DOT_4
1060 { 354, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // DEFAULT
1061 { 353, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_r600_pseudo
1062 { 352, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_eg_pseudo
1063 { 351, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_i32
1064 { 350, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_f32
1065 { 349, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_i32
1066 { 348, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_f32
1067 { 347, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_i32
1068 { 346, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_f32
1069 { 345, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE
1070 { 344, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // CONST_COPY
1071 { 343, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_i32
1072 { 342, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_f32
1073 { 341, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_i32
1074 { 340, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_f32
1075 { 339, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_i32
1076 { 338, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_f32
1077 { 337, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK
1078 { 336, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_i32
1079 { 335, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_f32
1080 { 334, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH
1081 { 333, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX
1082 { 332, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX
1083 { 331, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN
1084 { 330, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX
1085 { 329, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN
1086 { 328, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX
1087 { 327, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR
1088 { 326, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR
1089 { 325, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND
1090 { 324, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL
1091 { 323, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD
1092 { 322, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1093 { 321, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1094 { 320, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1095 { 319, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1096 { 318, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN
1097 { 317, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX
1098 { 316, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL
1099 { 315, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD
1100 { 314, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1101 { 313, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1102 { 312, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP
1103 { 311, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP
1104 { 310, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP
1105 { 309, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET_INLINE
1106 { 308, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO
1107 { 307, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET
1108 { 306, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE
1109 { 305, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE
1110 { 304, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY
1111 { 303, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1112 { 302, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1113 { 301, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMPS
1114 { 300, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMP
1115 { 299, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP
1116 { 298, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT
1117 { 297, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA
1118 { 296, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM
1119 { 295, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV
1120 { 294, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL
1121 { 293, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB
1122 { 292, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD
1123 { 291, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE
1124 { 290, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE
1125 { 289, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC
1126 { 288, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE
1127 { 287, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR
1128 { 286, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST
1129 { 285, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT
1130 { 284, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT
1131 { 283, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR
1132 { 282, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT
1133 { 281, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH
1134 { 280, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH
1135 { 279, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH
1136 { 278, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2
1137 { 277, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN
1138 { 276, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN
1139 { 275, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS
1140 { 274, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN
1141 { 273, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS
1142 { 272, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN
1143 { 271, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS
1144 { 270, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL
1145 { 269, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMULH
1146 { 268, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMUL
1147 { 267, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE
1148 { 266, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP
1149 { 265, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP
1150 { 264, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS
1151 { 263, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_POISON
1152 { 262, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ
1153 { 261, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_POISON
1154 { 260, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ
1155 { 259, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS
1156 { 258, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR
1157 { 257, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR
1158 { 256, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR
1159 { 255, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1160 { 254, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT
1161 { 253, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1162 { 252, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR
1163 { 251, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE
1164 { 250, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT
1165 { 249, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR
1166 { 248, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND
1167 { 247, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND
1168 { 246, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS
1169 { 245, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX
1170 { 244, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN
1171 { 243, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX
1172 { 242, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN
1173 { 241, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK
1174 { 240, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD
1175 { 239, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING
1176 { 238, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING
1177 { 237, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE
1178 { 236, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE
1179 { 235, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE
1180 { 234, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV
1181 { 233, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV
1182 { 232, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV
1183 { 231, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM
1184 { 230, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM
1185 { 229, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM
1186 { 228, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM
1187 { 227, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE
1188 { 226, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE
1189 { 225, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM
1190 { 224, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM
1191 { 223, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE
1192 { 222, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS
1193 { 221, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN
1194 { 220, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS
1195 { 219, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT
1196 { 218, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT
1197 { 217, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP
1198 { 216, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP
1199 { 215, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI
1200 { 214, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI
1201 { 213, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC
1202 { 212, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT
1203 { 211, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG
1204 { 210, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP
1205 { 209, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP
1206 { 208, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10
1207 { 207, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2
1208 { 206, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG
1209 { 205, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10
1210 { 204, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2
1211 { 203, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP
1212 { 202, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI
1213 { 201, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW
1214 { 200, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF
1215 { 199, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM
1216 { 198, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV
1217 { 197, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD
1218 { 196, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA
1219 { 195, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL
1220 { 194, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB
1221 { 193, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD
1222 { 192, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT
1223 { 191, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT
1224 { 190, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX
1225 { 189, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX
1226 { 188, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT
1227 { 187, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT
1228 { 186, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX
1229 { 185, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX
1230 { 184, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT
1231 { 183, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT
1232 { 182, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT
1233 { 181, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT
1234 { 180, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT
1235 { 179, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT
1236 { 178, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH
1237 { 177, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH
1238 { 176, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO
1239 { 175, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO
1240 { 174, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE
1241 { 173, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO
1242 { 172, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE
1243 { 171, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO
1244 { 170, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE
1245 { 169, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO
1246 { 168, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE
1247 { 167, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO
1248 { 166, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT
1249 { 165, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP
1250 { 164, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP
1251 { 163, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP
1252 { 162, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP
1253 { 161, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL
1254 { 160, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR
1255 { 159, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR
1256 { 158, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL
1257 { 157, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR
1258 { 156, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR
1259 { 155, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL
1260 { 154, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT
1261 { 153, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG
1262 { 152, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT
1263 { 151, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG
1264 { 150, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART
1265 { 149, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT
1266 { 148, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT
1267 { 147, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U
1268 { 146, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U
1269 { 145, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S
1270 { 144, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC
1271 { 143, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT
1272 { 142, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1273 { 141, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1274 { 140, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1275 { 139, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC
1276 { 138, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START
1277 { 137, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT
1278 { 136, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND
1279 { 135, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH
1280 { 134, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE
1281 { 133, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1282 { 132, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1283 { 131, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1284 { 130, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1285 { 129, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1286 { 128, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1287 { 127, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1288 { 126, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1289 { 125, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN
1290 { 124, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX
1291 { 123, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB
1292 { 122, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD
1293 { 121, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN
1294 { 120, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX
1295 { 119, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN
1296 { 118, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX
1297 { 117, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR
1298 { 116, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR
1299 { 115, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND
1300 { 114, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND
1301 { 113, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB
1302 { 112, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD
1303 { 111, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG
1304 { 110, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG
1305 { 109, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1306 { 108, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE
1307 { 107, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_FPTRUNCSTORE
1308 { 106, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE
1309 { 105, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1310 { 104, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD
1311 { 103, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD
1312 { 102, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_FPEXTLOAD
1313 { 101, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD
1314 { 100, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD
1315 { 99, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD
1316 { 98, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER
1317 { 97, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER
1318 { 96, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1319 { 95, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT
1320 { 94, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT
1321 { 93, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND
1322 { 92, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC
1323 { 91, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1324 { 90, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1325 { 89, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE
1326 { 88, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST
1327 { 87, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR
1328 { 86, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT
1329 { 85, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS
1330 { 84, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1331 { 83, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR
1332 { 82, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES
1333 { 81, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT
1334 { 80, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES
1335 { 79, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT
1336 { 78, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL
1337 { 77, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1338 { 76, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE
1339 { 75, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX
1340 { 74, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI
1341 { 73, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF
1342 { 72, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL
1343 { 71, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR
1344 { 70, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL
1345 { 69, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR
1346 { 68, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU
1347 { 67, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS
1348 { 66, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR
1349 { 65, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR
1350 { 64, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND
1351 { 63, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM
1352 { 62, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM
1353 { 61, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM
1354 { 60, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM
1355 { 59, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV
1356 { 58, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV
1357 { 57, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL
1358 { 56, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB
1359 { 55, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD
1360 { 54, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN
1361 { 53, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT
1362 { 52, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT
1363 { 51, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1364 { 50, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1365 { 49, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1366 { 48, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1367 { 47, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE
1368 { 46, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1369 { 45, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER
1370 { 44, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE
1371 { 43, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1372 { 42, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14629
1373 { 41, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14628
1374 { 40, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL
1375 { 39, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1376 { 38, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET
1377 { 37, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1378 { 36, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP
1379 { 35, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP
1380 { 34, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE
1381 { 33, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT
1382 { 32, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14627
1383 { 31, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP
1384 { 30, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_14348
1385 { 29, 6, 1, 0, 0, 0, 0, R600OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT
1386 { 28, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL
1387 { 27, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP
1388 { 26, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE
1389 { 25, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE
1390 { 24, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END
1391 { 23, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START
1392 { 22, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE
1393 { 21, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK
1394 { 20, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY
1395 { 19, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE
1396 { 18, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL
1397 { 17, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI
1398 { 16, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF
1399 { 15, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST
1400 { 14, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE
1401 { 13, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS
1402 { 12, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG
1403 { 11, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF
1404 { 10, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF
1405 { 9, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG
1406 { 8, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG
1407 { 7, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL
1408 { 6, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL
1409 { 5, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL
1410 { 4, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL
1411 { 3, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION
1412 { 2, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR
1413 { 1, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM
1414 { 0, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI
1415 }, {
1416 /* 0 */
1417 }, {
1418 0
1419 }, {
1420 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1421 /* 1 */
1422 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1423 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1424 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1425 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1426 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1427 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1428 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1429 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1430 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1431 /* 28 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1432 /* 29 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1433 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1434 /* 34 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1435 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1436 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1437 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1438 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1439 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1440 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1441 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1442 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1443 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1444 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1445 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1446 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1447 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1448 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1449 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1450 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1451 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1452 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1453 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1454 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1455 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1456 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1457 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1458 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1459 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1460 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1461 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1462 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1463 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1464 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1465 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1466 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1467 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1468 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1469 /* 153 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1470 /* 155 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1471 /* 156 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1472 /* 158 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1473 /* 160 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1474 /* 231 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1475 /* 233 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1476 /* 237 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1477 /* 240 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1478 /* 243 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1479 /* 247 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1480 /* 251 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1481 /* 255 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1482 /* 262 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1483 /* 283 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1484 /* 297 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1485 /* 316 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1486 /* 325 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1487 /* 332 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1488 /* 341 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1489 /* 346 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1490 /* 351 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1491 /* 353 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1492 /* 362 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1493 /* 372 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1494 /* 379 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1495 /* 391 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1496 /* 404 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1497 /* 407 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1498 /* 409 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1499 /* 411 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1500 /* 413 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1501 /* 417 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1502 /* 420 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1503 /* 423 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1504 /* 426 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1505 /* 445 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1506 /* 449 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1507 /* 453 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1508 /* 457 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1509 }
1510};
1511
1512
1513#ifdef __GNUC__
1514#pragma GCC diagnostic push
1515#pragma GCC diagnostic ignored "-Woverlength-strings"
1516#endif
1517extern const char R600InstrNameData[] = {
1518 /* 0 */ "CF_TC_R600\000"
1519 /* 11 */ "CF_VC_R600\000"
1520 /* 22 */ "CF_END_R600\000"
1521 /* 34 */ "CF_ELSE_R600\000"
1522 /* 47 */ "CF_PUSH_ELSE_R600\000"
1523 /* 65 */ "CF_CONTINUE_R600\000"
1524 /* 82 */ "FNEG_R600\000"
1525 /* 92 */ "LOOP_BREAK_R600\000"
1526 /* 108 */ "CF_JUMP_R600\000"
1527 /* 121 */ "END_LOOP_R600\000"
1528 /* 135 */ "WHILE_LOOP_R600\000"
1529 /* 151 */ "POP_R600\000"
1530 /* 160 */ "FABS_R600\000"
1531 /* 170 */ "CF_CALL_FS_R600\000"
1532 /* 186 */ "DOT4_r600\000"
1533 /* 196 */ "MULADD_r600\000"
1534 /* 208 */ "LOG_CLAMPED_r600\000"
1535 /* 225 */ "RECIP_CLAMPED_r600\000"
1536 /* 244 */ "RECIPSQRT_CLAMPED_r600\000"
1537 /* 267 */ "CNDE_r600\000"
1538 /* 277 */ "MULADD_IEEE_r600\000"
1539 /* 294 */ "LOG_IEEE_r600\000"
1540 /* 308 */ "RECIP_IEEE_r600\000"
1541 /* 324 */ "EXP_IEEE_r600\000"
1542 /* 338 */ "RECIPSQRT_IEEE_r600\000"
1543 /* 358 */ "CNDGE_r600\000"
1544 /* 369 */ "LSHL_r600\000"
1545 /* 379 */ "SIN_r600\000"
1546 /* 388 */ "ASHR_r600\000"
1547 /* 398 */ "LSHR_r600\000"
1548 /* 408 */ "COS_r600\000"
1549 /* 417 */ "CNDGT_r600\000"
1550 /* 428 */ "MUL_LIT_r600\000"
1551 /* 441 */ "UINT_TO_FLT_r600\000"
1552 /* 458 */ "MULHI_UINT_r600\000"
1553 /* 474 */ "MULLO_UINT_r600\000"
1554 /* 490 */ "FLT_TO_UINT_r600\000"
1555 /* 507 */ "RECIP_UINT_r600\000"
1556 /* 523 */ "MULHI_INT_r600\000"
1557 /* 538 */ "MULLO_INT_r600\000"
1558 /* 553 */ "FLT_TO_INT_r600\000"
1559 /* 569 */ "SIN_r700\000"
1560 /* 578 */ "COS_r700\000"
1561 /* 587 */ "G_FLOG10\000"
1562 /* 596 */ "G_FEXP10\000"
1563 /* 605 */ "SETGE_DX10\000"
1564 /* 616 */ "SETNE_DX10\000"
1565 /* 627 */ "SETE_DX10\000"
1566 /* 637 */ "MIN_DX10\000"
1567 /* 646 */ "SETGT_DX10\000"
1568 /* 657 */ "MAX_DX10\000"
1569 /* 666 */ "INTERP_LOAD_P0\000"
1570 /* 681 */ "RAT_STORE_DWORD32\000"
1571 /* 699 */ "MOV_IMM_F32\000"
1572 /* 711 */ "MOV_IMM_I32\000"
1573 /* 723 */ "FLT16_TO_FLT32\000"
1574 /* 738 */ "CONTINUEC_f32\000"
1575 /* 752 */ "IFC_f32\000"
1576 /* 760 */ "BREAKC_f32\000"
1577 /* 771 */ "BRANCH_COND_f32\000"
1578 /* 787 */ "CONTINUE_LOGICALZ_f32\000"
1579 /* 809 */ "IF_LOGICALZ_f32\000"
1580 /* 825 */ "BREAK_LOGICALZ_f32\000"
1581 /* 844 */ "CONTINUE_LOGICALNZ_f32\000"
1582 /* 867 */ "IF_LOGICALNZ_f32\000"
1583 /* 884 */ "BREAK_LOGICALNZ_f32\000"
1584 /* 904 */ "CONTINUEC_i32\000"
1585 /* 918 */ "IFC_i32\000"
1586 /* 926 */ "BREAKC_i32\000"
1587 /* 937 */ "BRANCH_COND_i32\000"
1588 /* 953 */ "CONTINUE_LOGICALZ_i32\000"
1589 /* 975 */ "IF_LOGICALZ_i32\000"
1590 /* 991 */ "BREAK_LOGICALZ_i32\000"
1591 /* 1010 */ "CONTINUE_LOGICALNZ_i32\000"
1592 /* 1033 */ "IF_LOGICALNZ_i32\000"
1593 /* 1050 */ "BREAK_LOGICALNZ_i32\000"
1594 /* 1070 */ "G_FLOG2\000"
1595 /* 1078 */ "G_FATAN2\000"
1596 /* 1087 */ "G_FEXP2\000"
1597 /* 1095 */ "R600_EXTRACT_ELT_V2\000"
1598 /* 1115 */ "R600_INSERT_ELT_V2\000"
1599 /* 1134 */ "MULHI_UINT_cm24\000"
1600 /* 1150 */ "MULHI_INT_cm24\000"
1601 /* 1165 */ "RAT_STORE_DWORD64\000"
1602 /* 1183 */ "R600_EXTRACT_ELT_V4\000"
1603 /* 1203 */ "R600_INSERT_ELT_V4\000"
1604 /* 1222 */ "DOT_4\000"
1605 /* 1228 */ "FLT32_TO_FLT16\000"
1606 /* 1243 */ "RAT_STORE_DWORD128\000"
1607 /* 1262 */ "G_FMA\000"
1608 /* 1268 */ "G_STRICT_FMA\000"
1609 /* 1281 */ "TEX_SAMPLE_C_LB\000"
1610 /* 1297 */ "TEX_SAMPLE_LB\000"
1611 /* 1311 */ "G_FSUB\000"
1612 /* 1318 */ "G_STRICT_FSUB\000"
1613 /* 1332 */ "G_ATOMICRMW_FSUB\000"
1614 /* 1349 */ "G_SUB\000"
1615 /* 1355 */ "LDS_SUB\000"
1616 /* 1363 */ "G_ATOMICRMW_SUB\000"
1617 /* 1379 */ "G_INTRINSIC\000"
1618 /* 1391 */ "ENDFUNC\000"
1619 /* 1399 */ "G_FPTRUNC\000"
1620 /* 1409 */ "G_INTRINSIC_TRUNC\000"
1621 /* 1427 */ "G_TRUNC\000"
1622 /* 1435 */ "G_BUILD_VECTOR_TRUNC\000"
1623 /* 1456 */ "G_DYN_STACKALLOC\000"
1624 /* 1473 */ "TEX_SAMPLE_C\000"
1625 /* 1486 */ "G_FMAD\000"
1626 /* 1493 */ "G_FPEXTLOAD\000"
1627 /* 1505 */ "G_INDEXED_SEXTLOAD\000"
1628 /* 1524 */ "G_SEXTLOAD\000"
1629 /* 1535 */ "G_INDEXED_ZEXTLOAD\000"
1630 /* 1554 */ "G_ZEXTLOAD\000"
1631 /* 1565 */ "INTERP_VEC_LOAD\000"
1632 /* 1581 */ "G_INDEXED_LOAD\000"
1633 /* 1596 */ "G_LOAD\000"
1634 /* 1603 */ "PAD\000"
1635 /* 1607 */ "G_VECREDUCE_FADD\000"
1636 /* 1624 */ "G_FADD\000"
1637 /* 1631 */ "G_VECREDUCE_SEQ_FADD\000"
1638 /* 1652 */ "G_STRICT_FADD\000"
1639 /* 1666 */ "G_ATOMICRMW_FADD\000"
1640 /* 1683 */ "G_VECREDUCE_ADD\000"
1641 /* 1699 */ "G_ADD\000"
1642 /* 1705 */ "G_PTR_ADD\000"
1643 /* 1715 */ "LDS_ADD\000"
1644 /* 1723 */ "G_ATOMICRMW_ADD\000"
1645 /* 1739 */ "TEX_LD\000"
1646 /* 1746 */ "G_ATOMICRMW_NAND\000"
1647 /* 1763 */ "G_VECREDUCE_AND\000"
1648 /* 1779 */ "G_AND\000"
1649 /* 1785 */ "LDS_AND\000"
1650 /* 1793 */ "G_ATOMICRMW_AND\000"
1651 /* 1809 */ "LIFETIME_END\000"
1652 /* 1822 */ "G_BRCOND\000"
1653 /* 1831 */ "G_ATOMICRMW_USUB_COND\000"
1654 /* 1853 */ "JUMP_COND\000"
1655 /* 1863 */ "G_LLROUND\000"
1656 /* 1873 */ "G_LROUND\000"
1657 /* 1882 */ "G_INTRINSIC_ROUND\000"
1658 /* 1900 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1659 /* 1926 */ "LOAD_STACK_GUARD\000"
1660 /* 1943 */ "TXD\000"
1661 /* 1947 */ "PSEUDO_PROBE\000"
1662 /* 1960 */ "G_SSUBE\000"
1663 /* 1968 */ "G_USUBE\000"
1664 /* 1976 */ "G_FENCE\000"
1665 /* 1984 */ "ARITH_FENCE\000"
1666 /* 1996 */ "REG_SEQUENCE\000"
1667 /* 2009 */ "G_SADDE\000"
1668 /* 2017 */ "G_UADDE\000"
1669 /* 2025 */ "G_GET_FPMODE\000"
1670 /* 2038 */ "G_RESET_FPMODE\000"
1671 /* 2053 */ "G_SET_FPMODE\000"
1672 /* 2066 */ "MUL_IEEE\000"
1673 /* 2075 */ "G_FMINNUM_IEEE\000"
1674 /* 2090 */ "G_FMAXNUM_IEEE\000"
1675 /* 2105 */ "SGE\000"
1676 /* 2109 */ "PRED_SETGE\000"
1677 /* 2120 */ "G_VSCALE\000"
1678 /* 2129 */ "G_JUMP_TABLE\000"
1679 /* 2142 */ "BUNDLE\000"
1680 /* 2149 */ "TEX_SAMPLE\000"
1681 /* 2160 */ "RNDNE\000"
1682 /* 2166 */ "G_MEMSET_INLINE\000"
1683 /* 2182 */ "G_MEMCPY_INLINE\000"
1684 /* 2198 */ "RELOC_NONE\000"
1685 /* 2209 */ "SNE\000"
1686 /* 2213 */ "PRED_SETNE\000"
1687 /* 2224 */ "LOCAL_ESCAPE\000"
1688 /* 2237 */ "CF_ALU_PUSH_BEFORE\000"
1689 /* 2256 */ "G_FPTRUNCSTORE\000"
1690 /* 2271 */ "G_STACKRESTORE\000"
1691 /* 2286 */ "G_INDEXED_STORE\000"
1692 /* 2302 */ "G_STORE\000"
1693 /* 2310 */ "ELSE\000"
1694 /* 2315 */ "G_BITREVERSE\000"
1695 /* 2328 */ "FETCH_CLAUSE\000"
1696 /* 2341 */ "ALU_CLAUSE\000"
1697 /* 2352 */ "FAKE_USE\000"
1698 /* 2361 */ "PRED_SETE\000"
1699 /* 2371 */ "LDS_BYTE_WRITE\000"
1700 /* 2386 */ "MASK_WRITE\000"
1701 /* 2397 */ "LDS_WRITE\000"
1702 /* 2407 */ "LDS_SHORT_WRITE\000"
1703 /* 2423 */ "DBG_VALUE\000"
1704 /* 2433 */ "G_GLOBAL_VALUE\000"
1705 /* 2448 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1706 /* 2471 */ "CONVERGENCECTRL_GLUE\000"
1707 /* 2492 */ "CF_ALU_CONTINUE\000"
1708 /* 2508 */ "G_STACKSAVE\000"
1709 /* 2520 */ "G_MEMMOVE\000"
1710 /* 2530 */ "G_FREEZE\000"
1711 /* 2539 */ "G_FCANONICALIZE\000"
1712 /* 2555 */ "G_FMODF\000"
1713 /* 2563 */ "INIT_UNDEF\000"
1714 /* 2574 */ "G_IMPLICIT_DEF\000"
1715 /* 2589 */ "DBG_INSTR_REF\000"
1716 /* 2603 */ "ENDIF\000"
1717 /* 2609 */ "TEX_VTX_CONSTBUF\000"
1718 /* 2626 */ "TEX_VTX_TEXBUF\000"
1719 /* 2641 */ "G_FNEG\000"
1720 /* 2648 */ "EXTRACT_SUBREG\000"
1721 /* 2663 */ "INSERT_SUBREG\000"
1722 /* 2677 */ "G_SEXT_INREG\000"
1723 /* 2690 */ "SUBREG_TO_REG\000"
1724 /* 2704 */ "CF_TC_EG\000"
1725 /* 2713 */ "CF_VC_EG\000"
1726 /* 2722 */ "CF_END_EG\000"
1727 /* 2732 */ "CF_ELSE_EG\000"
1728 /* 2743 */ "CF_CONTINUE_EG\000"
1729 /* 2758 */ "CF_PUSH_EG\000"
1730 /* 2769 */ "LOOP_BREAK_EG\000"
1731 /* 2783 */ "CF_JUMP_EG\000"
1732 /* 2794 */ "END_LOOP_EG\000"
1733 /* 2806 */ "WHILE_LOOP_EG\000"
1734 /* 2820 */ "POP_EG\000"
1735 /* 2827 */ "CF_CALL_FS_EG\000"
1736 /* 2841 */ "G_ATOMIC_CMPXCHG\000"
1737 /* 2858 */ "LDS_WRXCHG\000"
1738 /* 2869 */ "G_ATOMICRMW_XCHG\000"
1739 /* 2886 */ "G_GET_ROUNDING\000"
1740 /* 2901 */ "G_SET_ROUNDING\000"
1741 /* 2916 */ "G_FLOG\000"
1742 /* 2923 */ "G_VAARG\000"
1743 /* 2931 */ "PREALLOCATED_ARG\000"
1744 /* 2948 */ "TEX_SAMPLE_C_G\000"
1745 /* 2963 */ "TEX_SAMPLE_G\000"
1746 /* 2976 */ "BRANCH\000"
1747 /* 2983 */ "G_PREFETCH\000"
1748 /* 2994 */ "ENDSWITCH\000"
1749 /* 3004 */ "G_CLMULH\000"
1750 /* 3013 */ "G_SMULH\000"
1751 /* 3021 */ "G_UMULH\000"
1752 /* 3029 */ "G_FTANH\000"
1753 /* 3037 */ "G_FSINH\000"
1754 /* 3045 */ "G_FCOSH\000"
1755 /* 3053 */ "TEX_GET_GRADIENTS_H\000"
1756 /* 3073 */ "TEX_SET_GRADIENTS_H\000"
1757 /* 3093 */ "DBG_PHI\000"
1758 /* 3101 */ "G_FPTOSI\000"
1759 /* 3110 */ "G_FPTOUI\000"
1760 /* 3119 */ "G_FPOWI\000"
1761 /* 3127 */ "CF_ALU_BREAK\000"
1762 /* 3140 */ "COPY_LANEMASK\000"
1763 /* 3154 */ "G_PTRMASK\000"
1764 /* 3164 */ "GC_LABEL\000"
1765 /* 3173 */ "DBG_LABEL\000"
1766 /* 3183 */ "EH_LABEL\000"
1767 /* 3192 */ "ANNOTATION_LABEL\000"
1768 /* 3209 */ "ICALL_BRANCH_FUNNEL\000"
1769 /* 3229 */ "G_FSHL\000"
1770 /* 3236 */ "G_SHL\000"
1771 /* 3242 */ "G_FCEIL\000"
1772 /* 3250 */ "G_SAVGCEIL\000"
1773 /* 3261 */ "G_UAVGCEIL\000"
1774 /* 3272 */ "PATCHABLE_TAIL_CALL\000"
1775 /* 3292 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1776 /* 3319 */ "PATCHABLE_EVENT_CALL\000"
1777 /* 3340 */ "FENTRY_CALL\000"
1778 /* 3352 */ "KILL\000"
1779 /* 3357 */ "G_CONSTANT_POOL\000"
1780 /* 3373 */ "G_ROTL\000"
1781 /* 3380 */ "G_VECREDUCE_FMUL\000"
1782 /* 3397 */ "G_FMUL\000"
1783 /* 3404 */ "G_VECREDUCE_SEQ_FMUL\000"
1784 /* 3425 */ "G_STRICT_FMUL\000"
1785 /* 3439 */ "G_CLMUL\000"
1786 /* 3447 */ "G_VECREDUCE_MUL\000"
1787 /* 3463 */ "G_MUL\000"
1788 /* 3469 */ "TEX_SAMPLE_C_L\000"
1789 /* 3484 */ "TEX_SAMPLE_L\000"
1790 /* 3497 */ "CF_END_CM\000"
1791 /* 3507 */ "G_FREM\000"
1792 /* 3514 */ "G_STRICT_FREM\000"
1793 /* 3528 */ "G_SREM\000"
1794 /* 3535 */ "G_UREM\000"
1795 /* 3542 */ "G_SDIVREM\000"
1796 /* 3552 */ "G_UDIVREM\000"
1797 /* 3562 */ "INLINEASM\000"
1798 /* 3572 */ "G_VECREDUCE_FMINIMUM\000"
1799 /* 3593 */ "G_FMINIMUM\000"
1800 /* 3604 */ "G_ATOMICRMW_FMINIMUM\000"
1801 /* 3625 */ "G_VECREDUCE_FMAXIMUM\000"
1802 /* 3646 */ "G_FMAXIMUM\000"
1803 /* 3657 */ "G_ATOMICRMW_FMAXIMUM\000"
1804 /* 3678 */ "G_VECREDUCE_FMINIMUMNUM\000"
1805 /* 3702 */ "G_FMINIMUMNUM\000"
1806 /* 3716 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1807 /* 3740 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1808 /* 3764 */ "G_FMAXIMUMNUM\000"
1809 /* 3778 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1810 /* 3802 */ "G_FMINNUM\000"
1811 /* 3812 */ "G_FMAXNUM\000"
1812 /* 3822 */ "G_FATAN\000"
1813 /* 3830 */ "G_FTAN\000"
1814 /* 3837 */ "G_INTRINSIC_ROUNDEVEN\000"
1815 /* 3859 */ "G_ASSERT_ALIGN\000"
1816 /* 3874 */ "G_FCOPYSIGN\000"
1817 /* 3886 */ "DUMMY_CHAIN\000"
1818 /* 3898 */ "ENDMAIN\000"
1819 /* 3906 */ "G_VECREDUCE_FMIN\000"
1820 /* 3923 */ "G_ATOMICRMW_FMIN\000"
1821 /* 3940 */ "G_VECREDUCE_SMIN\000"
1822 /* 3957 */ "G_SMIN\000"
1823 /* 3964 */ "G_VECREDUCE_UMIN\000"
1824 /* 3981 */ "G_UMIN\000"
1825 /* 3988 */ "G_ATOMICRMW_UMIN\000"
1826 /* 4005 */ "G_ATOMICRMW_MIN\000"
1827 /* 4021 */ "G_FASIN\000"
1828 /* 4029 */ "G_FSIN\000"
1829 /* 4036 */ "CFI_INSTRUCTION\000"
1830 /* 4052 */ "G_CTLZ_ZERO_POISON\000"
1831 /* 4071 */ "G_CTTZ_ZERO_POISON\000"
1832 /* 4090 */ "RETURN\000"
1833 /* 4097 */ "RAT_ATOMIC_RSUB_RTN\000"
1834 /* 4117 */ "RAT_ATOMIC_SUB_RTN\000"
1835 /* 4136 */ "RAT_ATOMIC_ADD_RTN\000"
1836 /* 4155 */ "RAT_ATOMIC_AND_RTN\000"
1837 /* 4174 */ "RAT_ATOMIC_XOR_RTN\000"
1838 /* 4193 */ "RAT_ATOMIC_OR_RTN\000"
1839 /* 4211 */ "RAT_ATOMIC_DEC_UINT_RTN\000"
1840 /* 4235 */ "RAT_ATOMIC_INC_UINT_RTN\000"
1841 /* 4259 */ "RAT_ATOMIC_MIN_UINT_RTN\000"
1842 /* 4283 */ "RAT_ATOMIC_MAX_UINT_RTN\000"
1843 /* 4307 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\000"
1844 /* 4334 */ "RAT_ATOMIC_XCHG_INT_RTN\000"
1845 /* 4358 */ "RAT_ATOMIC_MIN_INT_RTN\000"
1846 /* 4381 */ "RAT_ATOMIC_MAX_INT_RTN\000"
1847 /* 4404 */ "RETDYN\000"
1848 /* 4411 */ "G_SSUBO\000"
1849 /* 4419 */ "G_USUBO\000"
1850 /* 4427 */ "G_SADDO\000"
1851 /* 4435 */ "G_UADDO\000"
1852 /* 4443 */ "TEX_GET_TEXTURE_RESINFO\000"
1853 /* 4467 */ "JUMP_TABLE_DEBUG_INFO\000"
1854 /* 4489 */ "G_SMULO\000"
1855 /* 4497 */ "G_UMULO\000"
1856 /* 4505 */ "G_BZERO\000"
1857 /* 4513 */ "STACKMAP\000"
1858 /* 4522 */ "G_DEBUGTRAP\000"
1859 /* 4534 */ "G_UBSANTRAP\000"
1860 /* 4546 */ "G_TRAP\000"
1861 /* 4553 */ "G_ATOMICRMW_UDEC_WRAP\000"
1862 /* 4575 */ "G_ATOMICRMW_UINC_WRAP\000"
1863 /* 4597 */ "G_BSWAP\000"
1864 /* 4605 */ "G_SITOFP\000"
1865 /* 4614 */ "G_UITOFP\000"
1866 /* 4623 */ "G_FCMP\000"
1867 /* 4630 */ "G_STRICT_FCMP\000"
1868 /* 4644 */ "G_ICMP\000"
1869 /* 4651 */ "G_SCMP\000"
1870 /* 4658 */ "G_UCMP\000"
1871 /* 4665 */ "JUMP\000"
1872 /* 4670 */ "ENDLOOP\000"
1873 /* 4678 */ "WHILELOOP\000"
1874 /* 4688 */ "CONVERGENCECTRL_LOOP\000"
1875 /* 4709 */ "G_CTPOP\000"
1876 /* 4717 */ "PATCHABLE_OP\000"
1877 /* 4730 */ "FAULTING_OP\000"
1878 /* 4742 */ "PREALLOCATED_SETUP\000"
1879 /* 4761 */ "G_FLDEXP\000"
1880 /* 4770 */ "G_STRICT_FLDEXP\000"
1881 /* 4786 */ "G_FEXP\000"
1882 /* 4793 */ "G_FFREXP\000"
1883 /* 4802 */ "G_BR\000"
1884 /* 4807 */ "INLINEASM_BR\000"
1885 /* 4820 */ "G_BLOCK_ADDR\000"
1886 /* 4833 */ "MOV_IMM_GLOBAL_ADDR\000"
1887 /* 4853 */ "MEMBARRIER\000"
1888 /* 4864 */ "G_CONSTANT_FOLD_BARRIER\000"
1889 /* 4888 */ "GROUP_BARRIER\000"
1890 /* 4902 */ "CF_ALU_ELSE_AFTER\000"
1891 /* 4920 */ "CF_ALU_POP_AFTER\000"
1892 /* 4937 */ "PATCHABLE_FUNCTION_ENTER\000"
1893 /* 4962 */ "G_READCYCLECOUNTER\000"
1894 /* 4981 */ "G_READSTEADYCOUNTER\000"
1895 /* 5001 */ "G_READ_REGISTER\000"
1896 /* 5017 */ "G_WRITE_REGISTER\000"
1897 /* 5034 */ "G_ASHR\000"
1898 /* 5041 */ "G_FSHR\000"
1899 /* 5048 */ "G_LSHR\000"
1900 /* 5055 */ "CONVERGENCECTRL_ANCHOR\000"
1901 /* 5078 */ "RAT_MSKOR\000"
1902 /* 5088 */ "G_FFLOOR\000"
1903 /* 5097 */ "G_SAVGFLOOR\000"
1904 /* 5109 */ "G_UAVGFLOOR\000"
1905 /* 5121 */ "G_EXTRACT_SUBVECTOR\000"
1906 /* 5141 */ "G_INSERT_SUBVECTOR\000"
1907 /* 5160 */ "G_BUILD_VECTOR\000"
1908 /* 5175 */ "G_SHUFFLE_VECTOR\000"
1909 /* 5192 */ "G_STEP_VECTOR\000"
1910 /* 5206 */ "G_SPLAT_VECTOR\000"
1911 /* 5221 */ "G_VECREDUCE_XOR\000"
1912 /* 5237 */ "G_XOR\000"
1913 /* 5243 */ "LDS_XOR\000"
1914 /* 5251 */ "G_ATOMICRMW_XOR\000"
1915 /* 5267 */ "G_VECREDUCE_OR\000"
1916 /* 5282 */ "G_OR\000"
1917 /* 5287 */ "LDS_OR\000"
1918 /* 5294 */ "G_ATOMICRMW_OR\000"
1919 /* 5309 */ "G_ROTR\000"
1920 /* 5316 */ "TEX_LDPTR\000"
1921 /* 5326 */ "G_INTTOPTR\000"
1922 /* 5337 */ "G_FABS\000"
1923 /* 5344 */ "G_ABS\000"
1924 /* 5350 */ "G_ABDS\000"
1925 /* 5357 */ "G_UNMERGE_VALUES\000"
1926 /* 5374 */ "G_MERGE_VALUES\000"
1927 /* 5389 */ "LITERALS\000"
1928 /* 5398 */ "G_CTLS\000"
1929 /* 5405 */ "G_FACOS\000"
1930 /* 5413 */ "G_FCOS\000"
1931 /* 5420 */ "G_FSINCOS\000"
1932 /* 5430 */ "G_STRICT_FCMPS\000"
1933 /* 5445 */ "G_CONCAT_VECTORS\000"
1934 /* 5462 */ "COPY_TO_REGCLASS\000"
1935 /* 5479 */ "G_IS_FPCLASS\000"
1936 /* 5492 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1937 /* 5522 */ "G_VECTOR_COMPRESS\000"
1938 /* 5540 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1939 /* 5567 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1940 /* 5605 */ "G_TRUNC_SSAT_S\000"
1941 /* 5620 */ "G_SSUBSAT\000"
1942 /* 5630 */ "G_USUBSAT\000"
1943 /* 5640 */ "G_SADDSAT\000"
1944 /* 5650 */ "G_UADDSAT\000"
1945 /* 5660 */ "G_SSHLSAT\000"
1946 /* 5670 */ "G_USHLSAT\000"
1947 /* 5680 */ "G_SMULFIXSAT\000"
1948 /* 5693 */ "G_UMULFIXSAT\000"
1949 /* 5706 */ "G_SDIVFIXSAT\000"
1950 /* 5719 */ "G_UDIVFIXSAT\000"
1951 /* 5732 */ "G_ATOMICRMW_USUB_SAT\000"
1952 /* 5753 */ "G_FPTOSI_SAT\000"
1953 /* 5766 */ "G_FPTOUI_SAT\000"
1954 /* 5779 */ "FRACT\000"
1955 /* 5785 */ "G_EXTRACT\000"
1956 /* 5795 */ "G_SELECT\000"
1957 /* 5804 */ "G_BRINDIRECT\000"
1958 /* 5817 */ "RAT_ATOMIC_RSUB_NORET\000"
1959 /* 5839 */ "RAT_ATOMIC_SUB_NORET\000"
1960 /* 5860 */ "RAT_ATOMIC_ADD_NORET\000"
1961 /* 5881 */ "RAT_ATOMIC_AND_NORET\000"
1962 /* 5902 */ "RAT_ATOMIC_XOR_NORET\000"
1963 /* 5923 */ "RAT_ATOMIC_OR_NORET\000"
1964 /* 5943 */ "RAT_ATOMIC_DEC_UINT_NORET\000"
1965 /* 5969 */ "RAT_ATOMIC_INC_UINT_NORET\000"
1966 /* 5995 */ "RAT_ATOMIC_MIN_UINT_NORET\000"
1967 /* 6021 */ "RAT_ATOMIC_MAX_UINT_NORET\000"
1968 /* 6047 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\000"
1969 /* 6076 */ "RAT_ATOMIC_XCHG_INT_NORET\000"
1970 /* 6102 */ "RAT_ATOMIC_MIN_INT_NORET\000"
1971 /* 6127 */ "RAT_ATOMIC_MAX_INT_NORET\000"
1972 /* 6152 */ "LDS_SUB_RET\000"
1973 /* 6164 */ "LDS_UBYTE_READ_RET\000"
1974 /* 6183 */ "LDS_BYTE_READ_RET\000"
1975 /* 6201 */ "LDS_READ_RET\000"
1976 /* 6214 */ "LDS_USHORT_READ_RET\000"
1977 /* 6234 */ "LDS_SHORT_READ_RET\000"
1978 /* 6253 */ "LDS_ADD_RET\000"
1979 /* 6265 */ "LDS_AND_RET\000"
1980 /* 6277 */ "PATCHABLE_RET\000"
1981 /* 6291 */ "LDS_WRXCHG_RET\000"
1982 /* 6306 */ "LDS_XOR_RET\000"
1983 /* 6318 */ "LDS_OR_RET\000"
1984 /* 6329 */ "LDS_MIN_UINT_RET\000"
1985 /* 6346 */ "LDS_MAX_UINT_RET\000"
1986 /* 6363 */ "LDS_MIN_INT_RET\000"
1987 /* 6379 */ "LDS_MAX_INT_RET\000"
1988 /* 6395 */ "LDS_CMPST_RET\000"
1989 /* 6409 */ "G_MEMSET\000"
1990 /* 6418 */ "IF_PREDICATE_SET\000"
1991 /* 6435 */ "KILLGT\000"
1992 /* 6442 */ "SGT\000"
1993 /* 6446 */ "PRED_SETGT\000"
1994 /* 6457 */ "PATCHABLE_FUNCTION_EXIT\000"
1995 /* 6481 */ "G_BRJT\000"
1996 /* 6488 */ "G_EXTRACT_VECTOR_ELT\000"
1997 /* 6509 */ "G_INSERT_VECTOR_ELT\000"
1998 /* 6529 */ "DEFAULT\000"
1999 /* 6537 */ "G_FCONSTANT\000"
2000 /* 6549 */ "G_CONSTANT\000"
2001 /* 6560 */ "G_INTRINSIC_CONVERGENT\000"
2002 /* 6583 */ "STATEPOINT\000"
2003 /* 6594 */ "PATCHPOINT\000"
2004 /* 6605 */ "G_PTRTOINT\000"
2005 /* 6616 */ "G_FRINT\000"
2006 /* 6624 */ "G_INTRINSIC_LLRINT\000"
2007 /* 6643 */ "G_INTRINSIC_LRINT\000"
2008 /* 6661 */ "SUBB_UINT\000"
2009 /* 6671 */ "ADDC_UINT\000"
2010 /* 6681 */ "SETGE_UINT\000"
2011 /* 6692 */ "FFBH_UINT\000"
2012 /* 6702 */ "LDS_MIN_UINT\000"
2013 /* 6715 */ "SETGT_UINT\000"
2014 /* 6726 */ "LDS_MAX_UINT\000"
2015 /* 6739 */ "G_FNEARBYINT\000"
2016 /* 6752 */ "SUB_INT\000"
2017 /* 6760 */ "ADD_INT\000"
2018 /* 6768 */ "AND_INT\000"
2019 /* 6776 */ "CNDE_INT\000"
2020 /* 6785 */ "CNDGE_INT\000"
2021 /* 6795 */ "PRED_SETGE_INT\000"
2022 /* 6810 */ "PRED_SETNE_INT\000"
2023 /* 6825 */ "PRED_SETE_INT\000"
2024 /* 6839 */ "FFBL_INT\000"
2025 /* 6848 */ "LDS_MIN_INT\000"
2026 /* 6860 */ "XOR_INT\000"
2027 /* 6868 */ "CNDGT_INT\000"
2028 /* 6878 */ "PRED_SETGT_INT\000"
2029 /* 6893 */ "BCNT_INT\000"
2030 /* 6902 */ "NOT_INT\000"
2031 /* 6910 */ "LDS_MAX_INT\000"
2032 /* 6922 */ "G_VASTART\000"
2033 /* 6932 */ "LIFETIME_START\000"
2034 /* 6947 */ "G_INVOKE_REGION_START\000"
2035 /* 6969 */ "G_INSERT\000"
2036 /* 6978 */ "G_FSQRT\000"
2037 /* 6986 */ "G_STRICT_FSQRT\000"
2038 /* 7001 */ "G_BITCAST\000"
2039 /* 7011 */ "G_ADDRSPACE_CAST\000"
2040 /* 7028 */ "DBG_VALUE_LIST\000"
2041 /* 7043 */ "LDS_CMPST\000"
2042 /* 7053 */ "G_FPEXT\000"
2043 /* 7061 */ "G_SEXT\000"
2044 /* 7068 */ "G_ASSERT_SEXT\000"
2045 /* 7082 */ "G_ANYEXT\000"
2046 /* 7091 */ "G_ZEXT\000"
2047 /* 7098 */ "G_ASSERT_ZEXT\000"
2048 /* 7112 */ "G_ABDU\000"
2049 /* 7119 */ "CF_ALU\000"
2050 /* 7126 */ "G_TRUNC_SSAT_U\000"
2051 /* 7141 */ "G_TRUNC_USAT_U\000"
2052 /* 7156 */ "G_FDIV\000"
2053 /* 7163 */ "G_STRICT_FDIV\000"
2054 /* 7177 */ "G_SDIV\000"
2055 /* 7184 */ "G_UDIV\000"
2056 /* 7191 */ "G_GET_FPENV\000"
2057 /* 7203 */ "G_RESET_FPENV\000"
2058 /* 7217 */ "G_SET_FPENV\000"
2059 /* 7229 */ "MOV\000"
2060 /* 7233 */ "TEX_GET_GRADIENTS_V\000"
2061 /* 7253 */ "TEX_SET_GRADIENTS_V\000"
2062 /* 7273 */ "TXD_SHADOW\000"
2063 /* 7284 */ "G_FPOW\000"
2064 /* 7291 */ "INTERP_ZW\000"
2065 /* 7301 */ "INTERP_PAIR_ZW\000"
2066 /* 7316 */ "G_VECREDUCE_FMAX\000"
2067 /* 7333 */ "G_ATOMICRMW_FMAX\000"
2068 /* 7350 */ "G_VECREDUCE_SMAX\000"
2069 /* 7367 */ "G_SMAX\000"
2070 /* 7374 */ "G_VECREDUCE_UMAX\000"
2071 /* 7391 */ "G_UMAX\000"
2072 /* 7398 */ "G_ATOMICRMW_UMAX\000"
2073 /* 7415 */ "G_ATOMICRMW_MAX\000"
2074 /* 7431 */ "G_FRAME_INDEX\000"
2075 /* 7445 */ "G_SBFX\000"
2076 /* 7452 */ "G_UBFX\000"
2077 /* 7459 */ "G_SMULFIX\000"
2078 /* 7469 */ "G_UMULFIX\000"
2079 /* 7479 */ "G_SDIVFIX\000"
2080 /* 7489 */ "G_UDIVFIX\000"
2081 /* 7499 */ "PRED_X\000"
2082 /* 7506 */ "G_MEMCPY\000"
2083 /* 7515 */ "CONST_COPY\000"
2084 /* 7526 */ "CONVERGENCECTRL_ENTRY\000"
2085 /* 7548 */ "INTERP_XY\000"
2086 /* 7558 */ "INTERP_PAIR_XY\000"
2087 /* 7573 */ "G_CTLZ\000"
2088 /* 7580 */ "G_CTTZ\000"
2089 /* 7587 */ "R600_RegisterLoad\000"
2090 /* 7605 */ "R600_RegisterStore\000"
2091 /* 7624 */ "R600_ExportBuf\000"
2092 /* 7639 */ "EG_ExportBuf\000"
2093 /* 7652 */ "VTX_READ_32_eg\000"
2094 /* 7667 */ "RAT_WRITE_CACHELESS_32_eg\000"
2095 /* 7693 */ "MULADD_UINT24_eg\000"
2096 /* 7710 */ "MULHI_UINT24_eg\000"
2097 /* 7726 */ "MUL_UINT24_eg\000"
2098 /* 7740 */ "VTX_READ_64_eg\000"
2099 /* 7755 */ "RAT_WRITE_CACHELESS_64_eg\000"
2100 /* 7781 */ "DOT4_eg\000"
2101 /* 7789 */ "VTX_READ_16_eg\000"
2102 /* 7804 */ "VTX_READ_128_eg\000"
2103 /* 7820 */ "RAT_WRITE_CACHELESS_128_eg\000"
2104 /* 7847 */ "VTX_READ_8_eg\000"
2105 /* 7861 */ "FMA_eg\000"
2106 /* 7868 */ "MULADD_eg\000"
2107 /* 7878 */ "LOG_CLAMPED_eg\000"
2108 /* 7893 */ "RECIP_CLAMPED_eg\000"
2109 /* 7910 */ "RECIPSQRT_CLAMPED_eg\000"
2110 /* 7931 */ "RAT_STORE_TYPED_eg\000"
2111 /* 7950 */ "CNDE_eg\000"
2112 /* 7958 */ "MULADD_IEEE_eg\000"
2113 /* 7973 */ "LOG_IEEE_eg\000"
2114 /* 7985 */ "RECIP_IEEE_eg\000"
2115 /* 7999 */ "EXP_IEEE_eg\000"
2116 /* 8011 */ "RECIPSQRT_IEEE_eg\000"
2117 /* 8029 */ "CNDGE_eg\000"
2118 /* 8038 */ "LSHL_eg\000"
2119 /* 8046 */ "SIN_eg\000"
2120 /* 8053 */ "ASHR_eg\000"
2121 /* 8061 */ "LSHR_eg\000"
2122 /* 8069 */ "COS_eg\000"
2123 /* 8076 */ "CNDGT_eg\000"
2124 /* 8085 */ "MUL_LIT_eg\000"
2125 /* 8096 */ "UINT_TO_FLT_eg\000"
2126 /* 8111 */ "BFE_UINT_eg\000"
2127 /* 8123 */ "MULHI_UINT_eg\000"
2128 /* 8137 */ "MULLO_UINT_eg\000"
2129 /* 8151 */ "FLT_TO_UINT_eg\000"
2130 /* 8166 */ "RECIP_UINT_eg\000"
2131 /* 8180 */ "MOVA_INT_eg\000"
2132 /* 8192 */ "BFE_INT_eg\000"
2133 /* 8203 */ "BFI_INT_eg\000"
2134 /* 8214 */ "MULHI_INT_eg\000"
2135 /* 8227 */ "BFM_INT_eg\000"
2136 /* 8238 */ "BIT_ALIGN_INT_eg\000"
2137 /* 8255 */ "MULLO_INT_eg\000"
2138 /* 8268 */ "FLT_TO_INT_eg\000"
2139 /* 8282 */ "CUBE_r600_real\000"
2140 /* 8297 */ "CUBE_eg_real\000"
2141 /* 8310 */ "VTX_READ_32_cm\000"
2142 /* 8325 */ "MULADD_INT24_cm\000"
2143 /* 8341 */ "MUL_INT24_cm\000"
2144 /* 8354 */ "VTX_READ_64_cm\000"
2145 /* 8369 */ "VTX_READ_16_cm\000"
2146 /* 8384 */ "VTX_READ_128_cm\000"
2147 /* 8400 */ "VTX_READ_8_cm\000"
2148 /* 8414 */ "RECIP_CLAMPED_cm\000"
2149 /* 8431 */ "RECIPSQRT_CLAMPED_cm\000"
2150 /* 8452 */ "RAT_STORE_TYPED_cm\000"
2151 /* 8471 */ "LOG_IEEE_cm\000"
2152 /* 8483 */ "RECIP_IEEE_cm\000"
2153 /* 8497 */ "EXP_IEEE_cm\000"
2154 /* 8509 */ "RECIPSQRT_IEEE_cm\000"
2155 /* 8527 */ "SIN_cm\000"
2156 /* 8534 */ "COS_cm\000"
2157 /* 8541 */ "MULHI_UINT_cm\000"
2158 /* 8555 */ "MULLO_UINT_cm\000"
2159 /* 8569 */ "MULHI_INT_cm\000"
2160 /* 8582 */ "MULLO_INT_cm\000"
2161 /* 8595 */ "CUBE_r600_pseudo\000"
2162 /* 8612 */ "CUBE_eg_pseudo\000"
2163 /* 8627 */ "R600_ExportSwz\000"
2164 /* 8642 */ "EG_ExportSwz\000"
2165};
2166#ifdef __GNUC__
2167#pragma GCC diagnostic pop
2168#endif
2169
2170extern const unsigned R600InstrNameIndices[] = {
2171 3097U, 3562U, 4807U, 4036U, 3183U, 3164U, 3192U, 3352U,
2172 2648U, 2663U, 2576U, 2563U, 2690U, 5462U, 2423U, 7028U,
2173 2589U, 3093U, 3173U, 1996U, 7521U, 3140U, 2142U, 6932U,
2174 1809U, 1947U, 1984U, 4513U, 3340U, 6594U, 1926U, 4742U,
2175 2931U, 6583U, 2224U, 4730U, 4717U, 4937U, 6277U, 6457U,
2176 3272U, 3319U, 3292U, 3209U, 2352U, 4853U, 4467U, 2198U,
2177 7526U, 5055U, 4688U, 2471U, 7068U, 7098U, 3859U, 1699U,
2178 1349U, 3463U, 7177U, 7184U, 3528U, 3535U, 3542U, 3552U,
2179 1779U, 5282U, 5237U, 5350U, 7112U, 5109U, 3261U, 5097U,
2180 3250U, 2574U, 3095U, 7431U, 2433U, 2448U, 3357U, 5785U,
2181 5357U, 6969U, 5374U, 5160U, 1435U, 5445U, 6605U, 5326U,
2182 7001U, 2530U, 4864U, 1900U, 1409U, 1882U, 6643U, 6624U,
2183 3837U, 4962U, 4981U, 1596U, 1524U, 1554U, 1493U, 1581U,
2184 1505U, 1535U, 2302U, 2256U, 2286U, 5492U, 2841U, 2869U,
2185 1723U, 1363U, 1793U, 1746U, 5294U, 5251U, 7415U, 4005U,
2186 7398U, 3988U, 1666U, 1332U, 7333U, 3923U, 3657U, 3604U,
2187 3778U, 3716U, 4575U, 4553U, 1831U, 5732U, 1976U, 2983U,
2188 1822U, 5804U, 6947U, 1379U, 5540U, 6560U, 5567U, 7082U,
2189 1427U, 5605U, 7126U, 7141U, 6549U, 6537U, 6922U, 2923U,
2190 7061U, 2677U, 7091U, 3236U, 5048U, 5034U, 3229U, 5041U,
2191 5309U, 3373U, 4644U, 4623U, 4651U, 4658U, 5795U, 4435U,
2192 2017U, 4419U, 1968U, 4427U, 2009U, 4411U, 1960U, 4497U,
2193 4489U, 3021U, 3013U, 5650U, 5640U, 5630U, 5620U, 5670U,
2194 5660U, 7459U, 7469U, 5680U, 5693U, 7479U, 7489U, 5706U,
2195 5719U, 1624U, 1311U, 3397U, 1262U, 1486U, 7156U, 3507U,
2196 2555U, 7284U, 3119U, 4786U, 1087U, 596U, 2916U, 1070U,
2197 587U, 4761U, 4793U, 2641U, 7053U, 1399U, 3101U, 3110U,
2198 4605U, 4614U, 5753U, 5766U, 5337U, 3874U, 5479U, 2539U,
2199 3802U, 3812U, 2075U, 2090U, 3593U, 3646U, 3702U, 3764U,
2200 7191U, 7217U, 7203U, 2025U, 2053U, 2038U, 2886U, 2901U,
2201 1705U, 3154U, 3957U, 7367U, 3981U, 7391U, 5344U, 1873U,
2202 1863U, 4802U, 6481U, 2120U, 5141U, 5121U, 6509U, 6488U,
2203 5175U, 5206U, 5192U, 5522U, 7580U, 4071U, 7573U, 4052U,
2204 5398U, 4709U, 4597U, 2315U, 3439U, 3004U, 3242U, 5413U,
2205 4029U, 5420U, 3830U, 5405U, 4021U, 3822U, 1078U, 3045U,
2206 3037U, 3029U, 6978U, 5088U, 6616U, 6739U, 7011U, 4820U,
2207 2129U, 1456U, 2508U, 2271U, 1652U, 1318U, 3425U, 7163U,
2208 3514U, 1268U, 6986U, 4770U, 4630U, 5430U, 5001U, 5017U,
2209 7506U, 2182U, 2520U, 6409U, 4505U, 2166U, 4546U, 4522U,
2210 4534U, 1631U, 3404U, 1607U, 3380U, 7316U, 3906U, 3625U,
2211 3572U, 3740U, 3678U, 1683U, 3447U, 1763U, 5267U, 5221U,
2212 7350U, 3940U, 7374U, 3964U, 7445U, 7452U, 2976U, 771U,
2213 937U, 3134U, 760U, 926U, 884U, 1050U, 825U, 991U,
2214 7515U, 2499U, 738U, 904U, 844U, 1010U, 787U, 953U,
2215 8612U, 8595U, 6529U, 1222U, 3886U, 2310U, 1818U, 1391U,
2216 2603U, 4670U, 3898U, 2994U, 160U, 82U, 1394U, 752U,
2217 918U, 867U, 1033U, 809U, 975U, 6418U, 4665U, 1853U,
2218 2386U, 699U, 4833U, 711U, 7499U, 1095U, 1183U, 1115U,
2219 1203U, 7587U, 7605U, 4404U, 4090U, 1943U, 7273U, 4678U,
2220 1620U, 6671U, 6760U, 2341U, 6768U, 8053U, 388U, 6893U,
2221 8192U, 8111U, 8203U, 8227U, 8238U, 3245U, 7119U, 3127U,
2222 2492U, 4902U, 4920U, 2237U, 2827U, 170U, 2743U, 65U,
2223 2732U, 34U, 3497U, 2722U, 22U, 2783U, 108U, 2758U,
2224 47U, 2704U, 0U, 2713U, 11U, 6776U, 7950U, 267U,
2225 6785U, 8029U, 358U, 6868U, 8076U, 417U, 8534U, 8069U,
2226 408U, 578U, 8297U, 8282U, 7781U, 186U, 7639U, 8642U,
2227 2794U, 121U, 8497U, 7999U, 324U, 2328U, 6692U, 6839U,
2228 5091U, 723U, 1228U, 8268U, 553U, 8151U, 490U, 7861U,
2229 5779U, 4888U, 666U, 7558U, 7301U, 1565U, 7548U, 7291U,
2230 8097U, 442U, 6435U, 1715U, 6253U, 1785U, 6265U, 6183U,
2231 2371U, 7043U, 6395U, 6910U, 6379U, 6726U, 6346U, 6848U,
2232 6363U, 6702U, 6329U, 5287U, 6318U, 6201U, 6234U, 2407U,
2233 1355U, 6152U, 6164U, 6214U, 2397U, 2858U, 6291U, 5243U,
2234 6306U, 5389U, 7878U, 208U, 8471U, 7973U, 294U, 2769U,
2235 92U, 8038U, 369U, 8061U, 398U, 7329U, 657U, 6914U,
2236 6730U, 3919U, 637U, 6852U, 6706U, 7229U, 8180U, 3393U,
2237 7958U, 277U, 8325U, 7693U, 7868U, 196U, 8569U, 1150U,
2238 8214U, 523U, 7710U, 8541U, 1134U, 8123U, 458U, 8582U,
2239 8255U, 538U, 8555U, 8137U, 474U, 2066U, 8341U, 8085U,
2240 428U, 7726U, 6902U, 6861U, 1603U, 2820U, 151U, 2361U,
2241 6825U, 2109U, 6795U, 6446U, 6878U, 2213U, 6810U, 7624U,
2242 8627U, 5860U, 4136U, 5881U, 4155U, 6047U, 4307U, 5943U,
2243 4211U, 5969U, 4235U, 6127U, 4381U, 6021U, 4283U, 6102U,
2244 4358U, 5995U, 4259U, 5923U, 4193U, 5817U, 4097U, 5839U,
2245 4117U, 6076U, 4334U, 5902U, 4174U, 5078U, 1243U, 681U,
2246 1165U, 8452U, 7931U, 7820U, 7667U, 7755U, 8431U, 7910U,
2247 244U, 8509U, 8011U, 338U, 8414U, 7893U, 225U, 8483U,
2248 7985U, 308U, 8166U, 507U, 2160U, 2366U, 627U, 6830U,
2249 605U, 6800U, 6681U, 646U, 6883U, 6715U, 616U, 6815U,
2250 2105U, 6442U, 8527U, 8046U, 379U, 569U, 2209U, 6661U,
2251 6752U, 3053U, 7233U, 4443U, 1739U, 5316U, 2149U, 1473U,
2252 2948U, 3469U, 1281U, 2963U, 3484U, 1297U, 3073U, 7253U,
2253 2609U, 2626U, 1403U, 8096U, 441U, 8384U, 7804U, 8369U,
2254 7789U, 8310U, 7652U, 8354U, 7740U, 8400U, 7847U, 2806U,
2255 135U, 6860U,
2256};
2257
2258static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
2259 II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 674, nullptr, 0);
2260}
2261
2262
2263} // namespace llvm
2264
2265#endif // GET_INSTRINFO_MC_DESC
2266
2267#ifdef GET_INSTRINFO_HEADER
2268#undef GET_INSTRINFO_HEADER
2269
2270namespace llvm {
2271
2272struct R600GenInstrInfo : public TargetInstrInfo {
2273 explicit R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2274 ~R600GenInstrInfo() override = default;
2275};
2276
2277} // namespace llvm
2278
2279namespace llvm::R600 {
2280
2281constexpr unsigned SUBOP_FRAMEri_ptr = 0;
2282constexpr unsigned SUBOP_FRAMEri_index = 1;
2283constexpr unsigned SUBOP_MEMrr_ptr = 0;
2284constexpr unsigned SUBOP_MEMrr_index = 1;
2285constexpr unsigned SUBOP_MEMxi_ptr = 0;
2286constexpr unsigned SUBOP_MEMxi_index = 1;
2287
2288} // namespace llvm::R600
2289
2290#endif // GET_INSTRINFO_HEADER
2291
2292#ifdef GET_INSTRINFO_HELPER_DECLS
2293#undef GET_INSTRINFO_HELPER_DECLS
2294
2295
2296#endif // GET_INSTRINFO_HELPER_DECLS
2297
2298#ifdef GET_INSTRINFO_HELPERS
2299#undef GET_INSTRINFO_HELPERS
2300
2301
2302#endif // GET_INSTRINFO_HELPERS
2303
2304#ifdef GET_INSTRINFO_CTOR_DTOR
2305#undef GET_INSTRINFO_CTOR_DTOR
2306
2307namespace llvm {
2308
2309extern const R600InstrTable R600Descs;
2310extern const unsigned R600InstrNameIndices[];
2311extern const char R600InstrNameData[];
2312R600GenInstrInfo::R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2313 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2314 InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 674);
2315}
2316
2317} // namespace llvm
2318
2319#endif // GET_INSTRINFO_CTOR_DTOR
2320
2321#ifdef GET_INSTRINFO_OPERAND_ENUM
2322#undef GET_INSTRINFO_OPERAND_ENUM
2323
2324namespace llvm::R600 {
2325
2326enum class OpName : uint8_t {
2327 dst = 0,
2328 src0 = 1,
2329 update_exec_mask_X = 2,
2330 update_pred_X = 3,
2331 write_X = 4,
2332 omod_X = 5,
2333 dst_rel_X = 6,
2334 clamp_X = 7,
2335 src0_X = 8,
2336 src0_neg_X = 9,
2337 src0_rel_X = 10,
2338 src0_abs_X = 11,
2339 src0_sel_X = 12,
2340 src1_X = 13,
2341 src1_neg_X = 14,
2342 src1_rel_X = 15,
2343 src1_abs_X = 16,
2344 src1_sel_X = 17,
2345 pred_sel_X = 18,
2346 update_exec_mask_Y = 19,
2347 update_pred_Y = 20,
2348 write_Y = 21,
2349 omod_Y = 22,
2350 dst_rel_Y = 23,
2351 clamp_Y = 24,
2352 src0_Y = 25,
2353 src0_neg_Y = 26,
2354 src0_rel_Y = 27,
2355 src0_abs_Y = 28,
2356 src0_sel_Y = 29,
2357 src1_Y = 30,
2358 src1_neg_Y = 31,
2359 src1_rel_Y = 32,
2360 src1_abs_Y = 33,
2361 src1_sel_Y = 34,
2362 pred_sel_Y = 35,
2363 update_exec_mask_Z = 36,
2364 update_pred_Z = 37,
2365 write_Z = 38,
2366 omod_Z = 39,
2367 dst_rel_Z = 40,
2368 clamp_Z = 41,
2369 src0_Z = 42,
2370 src0_neg_Z = 43,
2371 src0_rel_Z = 44,
2372 src0_abs_Z = 45,
2373 src0_sel_Z = 46,
2374 src1_Z = 47,
2375 src1_neg_Z = 48,
2376 src1_rel_Z = 49,
2377 src1_abs_Z = 50,
2378 src1_sel_Z = 51,
2379 pred_sel_Z = 52,
2380 update_exec_mask_W = 53,
2381 update_pred_W = 54,
2382 write_W = 55,
2383 omod_W = 56,
2384 dst_rel_W = 57,
2385 clamp_W = 58,
2386 src0_W = 59,
2387 src0_neg_W = 60,
2388 src0_rel_W = 61,
2389 src0_abs_W = 62,
2390 src0_sel_W = 63,
2391 src1_W = 64,
2392 src1_neg_W = 65,
2393 src1_rel_W = 66,
2394 src1_abs_W = 67,
2395 src1_sel_W = 68,
2396 pred_sel_W = 69,
2397 literal0 = 70,
2398 literal1 = 71,
2399 addr = 72,
2400 chan = 73,
2401 val = 74,
2402 update_exec_mask = 75,
2403 update_pred = 76,
2404 write = 77,
2405 omod = 78,
2406 dst_rel = 79,
2407 clamp = 80,
2408 src0_neg = 81,
2409 src0_rel = 82,
2410 src0_abs = 83,
2411 src0_sel = 84,
2412 src1 = 85,
2413 src1_neg = 86,
2414 src1_rel = 87,
2415 src1_abs = 88,
2416 src1_sel = 89,
2417 last = 90,
2418 pred_sel = 91,
2419 literal = 92,
2420 bank_swizzle = 93,
2421 src2 = 94,
2422 src2_neg = 95,
2423 src2_rel = 96,
2424 src2_sel = 97,
2425 ADDR = 98,
2426 KCACHE_BANK0 = 99,
2427 KCACHE_BANK1 = 100,
2428 KCACHE_MODE0 = 101,
2429 KCACHE_MODE1 = 102,
2430 KCACHE_ADDR0 = 103,
2431 KCACHE_ADDR1 = 104,
2432 COUNT = 105,
2433 Enabled = 106,
2434 NUM_OPERAND_NAMES = 107,
2435}; // enum class OpName
2436
2437LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name);
2438LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx);
2439
2440} // namespace llvm::R600
2441
2442#endif // GET_INSTRINFO_OPERAND_ENUM
2443
2444#ifdef GET_INSTRINFO_NAMED_OPS
2445#undef GET_INSTRINFO_NAMED_OPS
2446
2447namespace llvm::R600 {
2448
2449LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) {
2450 static constexpr uint8_t InstructionIndex[] = {
2451 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2455 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2466 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2468 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2471 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2473 1, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2475 0, 3, 4, 0, 0, 0, 0, 0, 5, 5, 5, 0, 5, 5, 5, 6,
2476 7, 7, 7, 5, 7, 6, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0,
2477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 7,
2478 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 0, 0,
2479 0, 0, 6, 6, 6, 0, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7,
2480 6, 0, 6, 0, 0, 0, 5, 5, 6, 6, 5, 9, 10, 9, 10, 11,
2481 9, 12, 13, 9, 10, 9, 10, 9, 10, 9, 10, 9, 10, 11, 11, 9,
2482 9, 10, 11, 11, 9, 9, 10, 9, 10, 0, 6, 6, 6, 6, 6, 0,
2483 0, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 5,
2484 7, 7, 7, 7, 7, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
2485 5, 5, 5, 5, 5, 5, 5, 7, 7, 5, 6, 5, 0, 0, 0, 5,
2486 5, 5, 5, 5, 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6,
2489 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5,
2490 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 5, 5,
2491 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2492 0, 0, 6, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2493 0, 5,
2494 };
2495 return InstructionIndex[Opcode];
2496}
2497LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) {
2498 assert(Name != OpName::NUM_OPERAND_NAMES);
2499 static constexpr int8_t OperandMap[][107] = {
2500 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2501 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2502 {0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2503 {0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2504 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2505 {0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2506 {0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2507 {0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2508 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
2509 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2510 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2511 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2512 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2513 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2514 };
2515 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2516 return OperandMap[InstrIdx][(unsigned)Name];
2517}
2518LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) {
2519 assert(Idx >= 0 && Idx < 71);
2520 static constexpr OpName OperandMap[][71] = {
2521 {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2522 {OpName::dst, OpName::src0, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2523 {OpName::dst, OpName::update_exec_mask_X, OpName::update_pred_X, OpName::write_X, OpName::omod_X, OpName::dst_rel_X, OpName::clamp_X, OpName::src0_X, OpName::src0_neg_X, OpName::src0_rel_X, OpName::src0_abs_X, OpName::src0_sel_X, OpName::src1_X, OpName::src1_neg_X, OpName::src1_rel_X, OpName::src1_abs_X, OpName::src1_sel_X, OpName::pred_sel_X, OpName::update_exec_mask_Y, OpName::update_pred_Y, OpName::write_Y, OpName::omod_Y, OpName::dst_rel_Y, OpName::clamp_Y, OpName::src0_Y, OpName::src0_neg_Y, OpName::src0_rel_Y, OpName::src0_abs_Y, OpName::src0_sel_Y, OpName::src1_Y, OpName::src1_neg_Y, OpName::src1_rel_Y, OpName::src1_abs_Y, OpName::src1_sel_Y, OpName::pred_sel_Y, OpName::update_exec_mask_Z, OpName::update_pred_Z, OpName::write_Z, OpName::omod_Z, OpName::dst_rel_Z, OpName::clamp_Z, OpName::src0_Z, OpName::src0_neg_Z, OpName::src0_rel_Z, OpName::src0_abs_Z, OpName::src0_sel_Z, OpName::src1_Z, OpName::src1_neg_Z, OpName::src1_rel_Z, OpName::src1_abs_Z, OpName::src1_sel_Z, OpName::pred_sel_Z, OpName::update_exec_mask_W, OpName::update_pred_W, OpName::write_W, OpName::omod_W, OpName::dst_rel_W, OpName::clamp_W, OpName::src0_W, OpName::src0_neg_W, OpName::src0_rel_W, OpName::src0_abs_W, OpName::src0_sel_W, OpName::src1_W, OpName::src1_neg_W, OpName::src1_rel_W, OpName::src1_abs_W, OpName::src1_sel_W, OpName::pred_sel_W, OpName::literal0, OpName::literal1, },
2524 {OpName::dst, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2525 {OpName::val, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2526 {OpName::dst, OpName::update_exec_mask, OpName::update_pred, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_abs, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2527 {OpName::dst, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2528 {OpName::dst, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_neg, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2529 {OpName::ADDR, OpName::KCACHE_BANK0, OpName::KCACHE_BANK1, OpName::KCACHE_MODE0, OpName::KCACHE_MODE1, OpName::KCACHE_ADDR0, OpName::KCACHE_ADDR1, OpName::COUNT, OpName::Enabled, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2530 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2531 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2532 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2533 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2534 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2535 };
2536 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2537 return OperandMap[InstrIdx][(unsigned)Idx];
2538}
2539
2540} // namespace llvm::R600
2541
2542#endif // GET_INSTRINFO_NAMED_OPS
2543
2544#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2545#undef GET_INSTRINFO_MC_HELPER_DECLS
2546
2547namespace llvm {
2548
2549class MCInst;
2550class FeatureBitset;
2551
2552namespace R600_MC {
2553
2554void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2555
2556} // namespace R600_MC
2557
2558} // namespace llvm
2559
2560#endif // GET_INSTRINFO_MC_HELPER_DECLS
2561
2562#ifdef GET_INSTRINFO_MC_HELPERS
2563#undef GET_INSTRINFO_MC_HELPERS
2564
2565namespace llvm::R600_MC {
2566
2567
2568} // namespace llvm::R600_MC
2569
2570#endif // GET_INSTRINFO_MC_HELPERS
2571
2572#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2573 defined(GET_AVAILABLE_OPCODE_CHECKER)
2574#define GET_COMPUTE_FEATURES
2575#endif
2576#ifdef GET_COMPUTE_FEATURES
2577#undef GET_COMPUTE_FEATURES
2578
2579namespace llvm::R600_MC {
2580
2581// Bits for subtarget features that participate in instruction matching.
2582enum SubtargetFeatureBits : uint8_t {
2583};
2584
2585inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2586 FeatureBitset Features;
2587 return Features;
2588}
2589
2590inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2591 enum : uint8_t {
2592 CEFBS_None,
2593 };
2594
2595 static constexpr FeatureBitset FeatureBitsets[] = {
2596 {}, // CEFBS_None
2597 };
2598 static constexpr uint8_t RequiredFeaturesRefs[] = {
2599 CEFBS_None, // PHI
2600 CEFBS_None, // INLINEASM
2601 CEFBS_None, // INLINEASM_BR
2602 CEFBS_None, // CFI_INSTRUCTION
2603 CEFBS_None, // EH_LABEL
2604 CEFBS_None, // GC_LABEL
2605 CEFBS_None, // ANNOTATION_LABEL
2606 CEFBS_None, // KILL
2607 CEFBS_None, // EXTRACT_SUBREG
2608 CEFBS_None, // INSERT_SUBREG
2609 CEFBS_None, // IMPLICIT_DEF
2610 CEFBS_None, // INIT_UNDEF
2611 CEFBS_None, // SUBREG_TO_REG
2612 CEFBS_None, // COPY_TO_REGCLASS
2613 CEFBS_None, // DBG_VALUE
2614 CEFBS_None, // DBG_VALUE_LIST
2615 CEFBS_None, // DBG_INSTR_REF
2616 CEFBS_None, // DBG_PHI
2617 CEFBS_None, // DBG_LABEL
2618 CEFBS_None, // REG_SEQUENCE
2619 CEFBS_None, // COPY
2620 CEFBS_None, // COPY_LANEMASK
2621 CEFBS_None, // BUNDLE
2622 CEFBS_None, // LIFETIME_START
2623 CEFBS_None, // LIFETIME_END
2624 CEFBS_None, // PSEUDO_PROBE
2625 CEFBS_None, // ARITH_FENCE
2626 CEFBS_None, // STACKMAP
2627 CEFBS_None, // FENTRY_CALL
2628 CEFBS_None, // PATCHPOINT
2629 CEFBS_None, // LOAD_STACK_GUARD
2630 CEFBS_None, // PREALLOCATED_SETUP
2631 CEFBS_None, // PREALLOCATED_ARG
2632 CEFBS_None, // STATEPOINT
2633 CEFBS_None, // LOCAL_ESCAPE
2634 CEFBS_None, // FAULTING_OP
2635 CEFBS_None, // PATCHABLE_OP
2636 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2637 CEFBS_None, // PATCHABLE_RET
2638 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2639 CEFBS_None, // PATCHABLE_TAIL_CALL
2640 CEFBS_None, // PATCHABLE_EVENT_CALL
2641 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2642 CEFBS_None, // ICALL_BRANCH_FUNNEL
2643 CEFBS_None, // FAKE_USE
2644 CEFBS_None, // MEMBARRIER
2645 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2646 CEFBS_None, // RELOC_NONE
2647 CEFBS_None, // CONVERGENCECTRL_ENTRY
2648 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2649 CEFBS_None, // CONVERGENCECTRL_LOOP
2650 CEFBS_None, // CONVERGENCECTRL_GLUE
2651 CEFBS_None, // G_ASSERT_SEXT
2652 CEFBS_None, // G_ASSERT_ZEXT
2653 CEFBS_None, // G_ASSERT_ALIGN
2654 CEFBS_None, // G_ADD
2655 CEFBS_None, // G_SUB
2656 CEFBS_None, // G_MUL
2657 CEFBS_None, // G_SDIV
2658 CEFBS_None, // G_UDIV
2659 CEFBS_None, // G_SREM
2660 CEFBS_None, // G_UREM
2661 CEFBS_None, // G_SDIVREM
2662 CEFBS_None, // G_UDIVREM
2663 CEFBS_None, // G_AND
2664 CEFBS_None, // G_OR
2665 CEFBS_None, // G_XOR
2666 CEFBS_None, // G_ABDS
2667 CEFBS_None, // G_ABDU
2668 CEFBS_None, // G_UAVGFLOOR
2669 CEFBS_None, // G_UAVGCEIL
2670 CEFBS_None, // G_SAVGFLOOR
2671 CEFBS_None, // G_SAVGCEIL
2672 CEFBS_None, // G_IMPLICIT_DEF
2673 CEFBS_None, // G_PHI
2674 CEFBS_None, // G_FRAME_INDEX
2675 CEFBS_None, // G_GLOBAL_VALUE
2676 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2677 CEFBS_None, // G_CONSTANT_POOL
2678 CEFBS_None, // G_EXTRACT
2679 CEFBS_None, // G_UNMERGE_VALUES
2680 CEFBS_None, // G_INSERT
2681 CEFBS_None, // G_MERGE_VALUES
2682 CEFBS_None, // G_BUILD_VECTOR
2683 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2684 CEFBS_None, // G_CONCAT_VECTORS
2685 CEFBS_None, // G_PTRTOINT
2686 CEFBS_None, // G_INTTOPTR
2687 CEFBS_None, // G_BITCAST
2688 CEFBS_None, // G_FREEZE
2689 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2690 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2691 CEFBS_None, // G_INTRINSIC_TRUNC
2692 CEFBS_None, // G_INTRINSIC_ROUND
2693 CEFBS_None, // G_INTRINSIC_LRINT
2694 CEFBS_None, // G_INTRINSIC_LLRINT
2695 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2696 CEFBS_None, // G_READCYCLECOUNTER
2697 CEFBS_None, // G_READSTEADYCOUNTER
2698 CEFBS_None, // G_LOAD
2699 CEFBS_None, // G_SEXTLOAD
2700 CEFBS_None, // G_ZEXTLOAD
2701 CEFBS_None, // G_FPEXTLOAD
2702 CEFBS_None, // G_INDEXED_LOAD
2703 CEFBS_None, // G_INDEXED_SEXTLOAD
2704 CEFBS_None, // G_INDEXED_ZEXTLOAD
2705 CEFBS_None, // G_STORE
2706 CEFBS_None, // G_FPTRUNCSTORE
2707 CEFBS_None, // G_INDEXED_STORE
2708 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2709 CEFBS_None, // G_ATOMIC_CMPXCHG
2710 CEFBS_None, // G_ATOMICRMW_XCHG
2711 CEFBS_None, // G_ATOMICRMW_ADD
2712 CEFBS_None, // G_ATOMICRMW_SUB
2713 CEFBS_None, // G_ATOMICRMW_AND
2714 CEFBS_None, // G_ATOMICRMW_NAND
2715 CEFBS_None, // G_ATOMICRMW_OR
2716 CEFBS_None, // G_ATOMICRMW_XOR
2717 CEFBS_None, // G_ATOMICRMW_MAX
2718 CEFBS_None, // G_ATOMICRMW_MIN
2719 CEFBS_None, // G_ATOMICRMW_UMAX
2720 CEFBS_None, // G_ATOMICRMW_UMIN
2721 CEFBS_None, // G_ATOMICRMW_FADD
2722 CEFBS_None, // G_ATOMICRMW_FSUB
2723 CEFBS_None, // G_ATOMICRMW_FMAX
2724 CEFBS_None, // G_ATOMICRMW_FMIN
2725 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2726 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2727 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2728 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2729 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2730 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2731 CEFBS_None, // G_ATOMICRMW_USUB_COND
2732 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2733 CEFBS_None, // G_FENCE
2734 CEFBS_None, // G_PREFETCH
2735 CEFBS_None, // G_BRCOND
2736 CEFBS_None, // G_BRINDIRECT
2737 CEFBS_None, // G_INVOKE_REGION_START
2738 CEFBS_None, // G_INTRINSIC
2739 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2740 CEFBS_None, // G_INTRINSIC_CONVERGENT
2741 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2742 CEFBS_None, // G_ANYEXT
2743 CEFBS_None, // G_TRUNC
2744 CEFBS_None, // G_TRUNC_SSAT_S
2745 CEFBS_None, // G_TRUNC_SSAT_U
2746 CEFBS_None, // G_TRUNC_USAT_U
2747 CEFBS_None, // G_CONSTANT
2748 CEFBS_None, // G_FCONSTANT
2749 CEFBS_None, // G_VASTART
2750 CEFBS_None, // G_VAARG
2751 CEFBS_None, // G_SEXT
2752 CEFBS_None, // G_SEXT_INREG
2753 CEFBS_None, // G_ZEXT
2754 CEFBS_None, // G_SHL
2755 CEFBS_None, // G_LSHR
2756 CEFBS_None, // G_ASHR
2757 CEFBS_None, // G_FSHL
2758 CEFBS_None, // G_FSHR
2759 CEFBS_None, // G_ROTR
2760 CEFBS_None, // G_ROTL
2761 CEFBS_None, // G_ICMP
2762 CEFBS_None, // G_FCMP
2763 CEFBS_None, // G_SCMP
2764 CEFBS_None, // G_UCMP
2765 CEFBS_None, // G_SELECT
2766 CEFBS_None, // G_UADDO
2767 CEFBS_None, // G_UADDE
2768 CEFBS_None, // G_USUBO
2769 CEFBS_None, // G_USUBE
2770 CEFBS_None, // G_SADDO
2771 CEFBS_None, // G_SADDE
2772 CEFBS_None, // G_SSUBO
2773 CEFBS_None, // G_SSUBE
2774 CEFBS_None, // G_UMULO
2775 CEFBS_None, // G_SMULO
2776 CEFBS_None, // G_UMULH
2777 CEFBS_None, // G_SMULH
2778 CEFBS_None, // G_UADDSAT
2779 CEFBS_None, // G_SADDSAT
2780 CEFBS_None, // G_USUBSAT
2781 CEFBS_None, // G_SSUBSAT
2782 CEFBS_None, // G_USHLSAT
2783 CEFBS_None, // G_SSHLSAT
2784 CEFBS_None, // G_SMULFIX
2785 CEFBS_None, // G_UMULFIX
2786 CEFBS_None, // G_SMULFIXSAT
2787 CEFBS_None, // G_UMULFIXSAT
2788 CEFBS_None, // G_SDIVFIX
2789 CEFBS_None, // G_UDIVFIX
2790 CEFBS_None, // G_SDIVFIXSAT
2791 CEFBS_None, // G_UDIVFIXSAT
2792 CEFBS_None, // G_FADD
2793 CEFBS_None, // G_FSUB
2794 CEFBS_None, // G_FMUL
2795 CEFBS_None, // G_FMA
2796 CEFBS_None, // G_FMAD
2797 CEFBS_None, // G_FDIV
2798 CEFBS_None, // G_FREM
2799 CEFBS_None, // G_FMODF
2800 CEFBS_None, // G_FPOW
2801 CEFBS_None, // G_FPOWI
2802 CEFBS_None, // G_FEXP
2803 CEFBS_None, // G_FEXP2
2804 CEFBS_None, // G_FEXP10
2805 CEFBS_None, // G_FLOG
2806 CEFBS_None, // G_FLOG2
2807 CEFBS_None, // G_FLOG10
2808 CEFBS_None, // G_FLDEXP
2809 CEFBS_None, // G_FFREXP
2810 CEFBS_None, // G_FNEG
2811 CEFBS_None, // G_FPEXT
2812 CEFBS_None, // G_FPTRUNC
2813 CEFBS_None, // G_FPTOSI
2814 CEFBS_None, // G_FPTOUI
2815 CEFBS_None, // G_SITOFP
2816 CEFBS_None, // G_UITOFP
2817 CEFBS_None, // G_FPTOSI_SAT
2818 CEFBS_None, // G_FPTOUI_SAT
2819 CEFBS_None, // G_FABS
2820 CEFBS_None, // G_FCOPYSIGN
2821 CEFBS_None, // G_IS_FPCLASS
2822 CEFBS_None, // G_FCANONICALIZE
2823 CEFBS_None, // G_FMINNUM
2824 CEFBS_None, // G_FMAXNUM
2825 CEFBS_None, // G_FMINNUM_IEEE
2826 CEFBS_None, // G_FMAXNUM_IEEE
2827 CEFBS_None, // G_FMINIMUM
2828 CEFBS_None, // G_FMAXIMUM
2829 CEFBS_None, // G_FMINIMUMNUM
2830 CEFBS_None, // G_FMAXIMUMNUM
2831 CEFBS_None, // G_GET_FPENV
2832 CEFBS_None, // G_SET_FPENV
2833 CEFBS_None, // G_RESET_FPENV
2834 CEFBS_None, // G_GET_FPMODE
2835 CEFBS_None, // G_SET_FPMODE
2836 CEFBS_None, // G_RESET_FPMODE
2837 CEFBS_None, // G_GET_ROUNDING
2838 CEFBS_None, // G_SET_ROUNDING
2839 CEFBS_None, // G_PTR_ADD
2840 CEFBS_None, // G_PTRMASK
2841 CEFBS_None, // G_SMIN
2842 CEFBS_None, // G_SMAX
2843 CEFBS_None, // G_UMIN
2844 CEFBS_None, // G_UMAX
2845 CEFBS_None, // G_ABS
2846 CEFBS_None, // G_LROUND
2847 CEFBS_None, // G_LLROUND
2848 CEFBS_None, // G_BR
2849 CEFBS_None, // G_BRJT
2850 CEFBS_None, // G_VSCALE
2851 CEFBS_None, // G_INSERT_SUBVECTOR
2852 CEFBS_None, // G_EXTRACT_SUBVECTOR
2853 CEFBS_None, // G_INSERT_VECTOR_ELT
2854 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2855 CEFBS_None, // G_SHUFFLE_VECTOR
2856 CEFBS_None, // G_SPLAT_VECTOR
2857 CEFBS_None, // G_STEP_VECTOR
2858 CEFBS_None, // G_VECTOR_COMPRESS
2859 CEFBS_None, // G_CTTZ
2860 CEFBS_None, // G_CTTZ_ZERO_POISON
2861 CEFBS_None, // G_CTLZ
2862 CEFBS_None, // G_CTLZ_ZERO_POISON
2863 CEFBS_None, // G_CTLS
2864 CEFBS_None, // G_CTPOP
2865 CEFBS_None, // G_BSWAP
2866 CEFBS_None, // G_BITREVERSE
2867 CEFBS_None, // G_CLMUL
2868 CEFBS_None, // G_CLMULH
2869 CEFBS_None, // G_FCEIL
2870 CEFBS_None, // G_FCOS
2871 CEFBS_None, // G_FSIN
2872 CEFBS_None, // G_FSINCOS
2873 CEFBS_None, // G_FTAN
2874 CEFBS_None, // G_FACOS
2875 CEFBS_None, // G_FASIN
2876 CEFBS_None, // G_FATAN
2877 CEFBS_None, // G_FATAN2
2878 CEFBS_None, // G_FCOSH
2879 CEFBS_None, // G_FSINH
2880 CEFBS_None, // G_FTANH
2881 CEFBS_None, // G_FSQRT
2882 CEFBS_None, // G_FFLOOR
2883 CEFBS_None, // G_FRINT
2884 CEFBS_None, // G_FNEARBYINT
2885 CEFBS_None, // G_ADDRSPACE_CAST
2886 CEFBS_None, // G_BLOCK_ADDR
2887 CEFBS_None, // G_JUMP_TABLE
2888 CEFBS_None, // G_DYN_STACKALLOC
2889 CEFBS_None, // G_STACKSAVE
2890 CEFBS_None, // G_STACKRESTORE
2891 CEFBS_None, // G_STRICT_FADD
2892 CEFBS_None, // G_STRICT_FSUB
2893 CEFBS_None, // G_STRICT_FMUL
2894 CEFBS_None, // G_STRICT_FDIV
2895 CEFBS_None, // G_STRICT_FREM
2896 CEFBS_None, // G_STRICT_FMA
2897 CEFBS_None, // G_STRICT_FSQRT
2898 CEFBS_None, // G_STRICT_FLDEXP
2899 CEFBS_None, // G_STRICT_FCMP
2900 CEFBS_None, // G_STRICT_FCMPS
2901 CEFBS_None, // G_READ_REGISTER
2902 CEFBS_None, // G_WRITE_REGISTER
2903 CEFBS_None, // G_MEMCPY
2904 CEFBS_None, // G_MEMCPY_INLINE
2905 CEFBS_None, // G_MEMMOVE
2906 CEFBS_None, // G_MEMSET
2907 CEFBS_None, // G_BZERO
2908 CEFBS_None, // G_MEMSET_INLINE
2909 CEFBS_None, // G_TRAP
2910 CEFBS_None, // G_DEBUGTRAP
2911 CEFBS_None, // G_UBSANTRAP
2912 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2913 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2914 CEFBS_None, // G_VECREDUCE_FADD
2915 CEFBS_None, // G_VECREDUCE_FMUL
2916 CEFBS_None, // G_VECREDUCE_FMAX
2917 CEFBS_None, // G_VECREDUCE_FMIN
2918 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2919 CEFBS_None, // G_VECREDUCE_FMINIMUM
2920 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2921 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2922 CEFBS_None, // G_VECREDUCE_ADD
2923 CEFBS_None, // G_VECREDUCE_MUL
2924 CEFBS_None, // G_VECREDUCE_AND
2925 CEFBS_None, // G_VECREDUCE_OR
2926 CEFBS_None, // G_VECREDUCE_XOR
2927 CEFBS_None, // G_VECREDUCE_SMAX
2928 CEFBS_None, // G_VECREDUCE_SMIN
2929 CEFBS_None, // G_VECREDUCE_UMAX
2930 CEFBS_None, // G_VECREDUCE_UMIN
2931 CEFBS_None, // G_SBFX
2932 CEFBS_None, // G_UBFX
2933 CEFBS_None, // BRANCH
2934 CEFBS_None, // BRANCH_COND_f32
2935 CEFBS_None, // BRANCH_COND_i32
2936 CEFBS_None, // BREAK
2937 CEFBS_None, // BREAKC_f32
2938 CEFBS_None, // BREAKC_i32
2939 CEFBS_None, // BREAK_LOGICALNZ_f32
2940 CEFBS_None, // BREAK_LOGICALNZ_i32
2941 CEFBS_None, // BREAK_LOGICALZ_f32
2942 CEFBS_None, // BREAK_LOGICALZ_i32
2943 CEFBS_None, // CONST_COPY
2944 CEFBS_None, // CONTINUE
2945 CEFBS_None, // CONTINUEC_f32
2946 CEFBS_None, // CONTINUEC_i32
2947 CEFBS_None, // CONTINUE_LOGICALNZ_f32
2948 CEFBS_None, // CONTINUE_LOGICALNZ_i32
2949 CEFBS_None, // CONTINUE_LOGICALZ_f32
2950 CEFBS_None, // CONTINUE_LOGICALZ_i32
2951 CEFBS_None, // CUBE_eg_pseudo
2952 CEFBS_None, // CUBE_r600_pseudo
2953 CEFBS_None, // DEFAULT
2954 CEFBS_None, // DOT_4
2955 CEFBS_None, // DUMMY_CHAIN
2956 CEFBS_None, // ELSE
2957 CEFBS_None, // END
2958 CEFBS_None, // ENDFUNC
2959 CEFBS_None, // ENDIF
2960 CEFBS_None, // ENDLOOP
2961 CEFBS_None, // ENDMAIN
2962 CEFBS_None, // ENDSWITCH
2963 CEFBS_None, // FABS_R600
2964 CEFBS_None, // FNEG_R600
2965 CEFBS_None, // FUNC
2966 CEFBS_None, // IFC_f32
2967 CEFBS_None, // IFC_i32
2968 CEFBS_None, // IF_LOGICALNZ_f32
2969 CEFBS_None, // IF_LOGICALNZ_i32
2970 CEFBS_None, // IF_LOGICALZ_f32
2971 CEFBS_None, // IF_LOGICALZ_i32
2972 CEFBS_None, // IF_PREDICATE_SET
2973 CEFBS_None, // JUMP
2974 CEFBS_None, // JUMP_COND
2975 CEFBS_None, // MASK_WRITE
2976 CEFBS_None, // MOV_IMM_F32
2977 CEFBS_None, // MOV_IMM_GLOBAL_ADDR
2978 CEFBS_None, // MOV_IMM_I32
2979 CEFBS_None, // PRED_X
2980 CEFBS_None, // R600_EXTRACT_ELT_V2
2981 CEFBS_None, // R600_EXTRACT_ELT_V4
2982 CEFBS_None, // R600_INSERT_ELT_V2
2983 CEFBS_None, // R600_INSERT_ELT_V4
2984 CEFBS_None, // R600_RegisterLoad
2985 CEFBS_None, // R600_RegisterStore
2986 CEFBS_None, // RETDYN
2987 CEFBS_None, // RETURN
2988 CEFBS_None, // TXD
2989 CEFBS_None, // TXD_SHADOW
2990 CEFBS_None, // WHILELOOP
2991 CEFBS_None, // ADD
2992 CEFBS_None, // ADDC_UINT
2993 CEFBS_None, // ADD_INT
2994 CEFBS_None, // ALU_CLAUSE
2995 CEFBS_None, // AND_INT
2996 CEFBS_None, // ASHR_eg
2997 CEFBS_None, // ASHR_r600
2998 CEFBS_None, // BCNT_INT
2999 CEFBS_None, // BFE_INT_eg
3000 CEFBS_None, // BFE_UINT_eg
3001 CEFBS_None, // BFI_INT_eg
3002 CEFBS_None, // BFM_INT_eg
3003 CEFBS_None, // BIT_ALIGN_INT_eg
3004 CEFBS_None, // CEIL
3005 CEFBS_None, // CF_ALU
3006 CEFBS_None, // CF_ALU_BREAK
3007 CEFBS_None, // CF_ALU_CONTINUE
3008 CEFBS_None, // CF_ALU_ELSE_AFTER
3009 CEFBS_None, // CF_ALU_POP_AFTER
3010 CEFBS_None, // CF_ALU_PUSH_BEFORE
3011 CEFBS_None, // CF_CALL_FS_EG
3012 CEFBS_None, // CF_CALL_FS_R600
3013 CEFBS_None, // CF_CONTINUE_EG
3014 CEFBS_None, // CF_CONTINUE_R600
3015 CEFBS_None, // CF_ELSE_EG
3016 CEFBS_None, // CF_ELSE_R600
3017 CEFBS_None, // CF_END_CM
3018 CEFBS_None, // CF_END_EG
3019 CEFBS_None, // CF_END_R600
3020 CEFBS_None, // CF_JUMP_EG
3021 CEFBS_None, // CF_JUMP_R600
3022 CEFBS_None, // CF_PUSH_EG
3023 CEFBS_None, // CF_PUSH_ELSE_R600
3024 CEFBS_None, // CF_TC_EG
3025 CEFBS_None, // CF_TC_R600
3026 CEFBS_None, // CF_VC_EG
3027 CEFBS_None, // CF_VC_R600
3028 CEFBS_None, // CNDE_INT
3029 CEFBS_None, // CNDE_eg
3030 CEFBS_None, // CNDE_r600
3031 CEFBS_None, // CNDGE_INT
3032 CEFBS_None, // CNDGE_eg
3033 CEFBS_None, // CNDGE_r600
3034 CEFBS_None, // CNDGT_INT
3035 CEFBS_None, // CNDGT_eg
3036 CEFBS_None, // CNDGT_r600
3037 CEFBS_None, // COS_cm
3038 CEFBS_None, // COS_eg
3039 CEFBS_None, // COS_r600
3040 CEFBS_None, // COS_r700
3041 CEFBS_None, // CUBE_eg_real
3042 CEFBS_None, // CUBE_r600_real
3043 CEFBS_None, // DOT4_eg
3044 CEFBS_None, // DOT4_r600
3045 CEFBS_None, // EG_ExportBuf
3046 CEFBS_None, // EG_ExportSwz
3047 CEFBS_None, // END_LOOP_EG
3048 CEFBS_None, // END_LOOP_R600
3049 CEFBS_None, // EXP_IEEE_cm
3050 CEFBS_None, // EXP_IEEE_eg
3051 CEFBS_None, // EXP_IEEE_r600
3052 CEFBS_None, // FETCH_CLAUSE
3053 CEFBS_None, // FFBH_UINT
3054 CEFBS_None, // FFBL_INT
3055 CEFBS_None, // FLOOR
3056 CEFBS_None, // FLT16_TO_FLT32
3057 CEFBS_None, // FLT32_TO_FLT16
3058 CEFBS_None, // FLT_TO_INT_eg
3059 CEFBS_None, // FLT_TO_INT_r600
3060 CEFBS_None, // FLT_TO_UINT_eg
3061 CEFBS_None, // FLT_TO_UINT_r600
3062 CEFBS_None, // FMA_eg
3063 CEFBS_None, // FRACT
3064 CEFBS_None, // GROUP_BARRIER
3065 CEFBS_None, // INTERP_LOAD_P0
3066 CEFBS_None, // INTERP_PAIR_XY
3067 CEFBS_None, // INTERP_PAIR_ZW
3068 CEFBS_None, // INTERP_VEC_LOAD
3069 CEFBS_None, // INTERP_XY
3070 CEFBS_None, // INTERP_ZW
3071 CEFBS_None, // INT_TO_FLT_eg
3072 CEFBS_None, // INT_TO_FLT_r600
3073 CEFBS_None, // KILLGT
3074 CEFBS_None, // LDS_ADD
3075 CEFBS_None, // LDS_ADD_RET
3076 CEFBS_None, // LDS_AND
3077 CEFBS_None, // LDS_AND_RET
3078 CEFBS_None, // LDS_BYTE_READ_RET
3079 CEFBS_None, // LDS_BYTE_WRITE
3080 CEFBS_None, // LDS_CMPST
3081 CEFBS_None, // LDS_CMPST_RET
3082 CEFBS_None, // LDS_MAX_INT
3083 CEFBS_None, // LDS_MAX_INT_RET
3084 CEFBS_None, // LDS_MAX_UINT
3085 CEFBS_None, // LDS_MAX_UINT_RET
3086 CEFBS_None, // LDS_MIN_INT
3087 CEFBS_None, // LDS_MIN_INT_RET
3088 CEFBS_None, // LDS_MIN_UINT
3089 CEFBS_None, // LDS_MIN_UINT_RET
3090 CEFBS_None, // LDS_OR
3091 CEFBS_None, // LDS_OR_RET
3092 CEFBS_None, // LDS_READ_RET
3093 CEFBS_None, // LDS_SHORT_READ_RET
3094 CEFBS_None, // LDS_SHORT_WRITE
3095 CEFBS_None, // LDS_SUB
3096 CEFBS_None, // LDS_SUB_RET
3097 CEFBS_None, // LDS_UBYTE_READ_RET
3098 CEFBS_None, // LDS_USHORT_READ_RET
3099 CEFBS_None, // LDS_WRITE
3100 CEFBS_None, // LDS_WRXCHG
3101 CEFBS_None, // LDS_WRXCHG_RET
3102 CEFBS_None, // LDS_XOR
3103 CEFBS_None, // LDS_XOR_RET
3104 CEFBS_None, // LITERALS
3105 CEFBS_None, // LOG_CLAMPED_eg
3106 CEFBS_None, // LOG_CLAMPED_r600
3107 CEFBS_None, // LOG_IEEE_cm
3108 CEFBS_None, // LOG_IEEE_eg
3109 CEFBS_None, // LOG_IEEE_r600
3110 CEFBS_None, // LOOP_BREAK_EG
3111 CEFBS_None, // LOOP_BREAK_R600
3112 CEFBS_None, // LSHL_eg
3113 CEFBS_None, // LSHL_r600
3114 CEFBS_None, // LSHR_eg
3115 CEFBS_None, // LSHR_r600
3116 CEFBS_None, // MAX
3117 CEFBS_None, // MAX_DX10
3118 CEFBS_None, // MAX_INT
3119 CEFBS_None, // MAX_UINT
3120 CEFBS_None, // MIN
3121 CEFBS_None, // MIN_DX10
3122 CEFBS_None, // MIN_INT
3123 CEFBS_None, // MIN_UINT
3124 CEFBS_None, // MOV
3125 CEFBS_None, // MOVA_INT_eg
3126 CEFBS_None, // MUL
3127 CEFBS_None, // MULADD_IEEE_eg
3128 CEFBS_None, // MULADD_IEEE_r600
3129 CEFBS_None, // MULADD_INT24_cm
3130 CEFBS_None, // MULADD_UINT24_eg
3131 CEFBS_None, // MULADD_eg
3132 CEFBS_None, // MULADD_r600
3133 CEFBS_None, // MULHI_INT_cm
3134 CEFBS_None, // MULHI_INT_cm24
3135 CEFBS_None, // MULHI_INT_eg
3136 CEFBS_None, // MULHI_INT_r600
3137 CEFBS_None, // MULHI_UINT24_eg
3138 CEFBS_None, // MULHI_UINT_cm
3139 CEFBS_None, // MULHI_UINT_cm24
3140 CEFBS_None, // MULHI_UINT_eg
3141 CEFBS_None, // MULHI_UINT_r600
3142 CEFBS_None, // MULLO_INT_cm
3143 CEFBS_None, // MULLO_INT_eg
3144 CEFBS_None, // MULLO_INT_r600
3145 CEFBS_None, // MULLO_UINT_cm
3146 CEFBS_None, // MULLO_UINT_eg
3147 CEFBS_None, // MULLO_UINT_r600
3148 CEFBS_None, // MUL_IEEE
3149 CEFBS_None, // MUL_INT24_cm
3150 CEFBS_None, // MUL_LIT_eg
3151 CEFBS_None, // MUL_LIT_r600
3152 CEFBS_None, // MUL_UINT24_eg
3153 CEFBS_None, // NOT_INT
3154 CEFBS_None, // OR_INT
3155 CEFBS_None, // PAD
3156 CEFBS_None, // POP_EG
3157 CEFBS_None, // POP_R600
3158 CEFBS_None, // PRED_SETE
3159 CEFBS_None, // PRED_SETE_INT
3160 CEFBS_None, // PRED_SETGE
3161 CEFBS_None, // PRED_SETGE_INT
3162 CEFBS_None, // PRED_SETGT
3163 CEFBS_None, // PRED_SETGT_INT
3164 CEFBS_None, // PRED_SETNE
3165 CEFBS_None, // PRED_SETNE_INT
3166 CEFBS_None, // R600_ExportBuf
3167 CEFBS_None, // R600_ExportSwz
3168 CEFBS_None, // RAT_ATOMIC_ADD_NORET
3169 CEFBS_None, // RAT_ATOMIC_ADD_RTN
3170 CEFBS_None, // RAT_ATOMIC_AND_NORET
3171 CEFBS_None, // RAT_ATOMIC_AND_RTN
3172 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET
3173 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN
3174 CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET
3175 CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN
3176 CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET
3177 CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN
3178 CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET
3179 CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN
3180 CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET
3181 CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN
3182 CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET
3183 CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN
3184 CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET
3185 CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN
3186 CEFBS_None, // RAT_ATOMIC_OR_NORET
3187 CEFBS_None, // RAT_ATOMIC_OR_RTN
3188 CEFBS_None, // RAT_ATOMIC_RSUB_NORET
3189 CEFBS_None, // RAT_ATOMIC_RSUB_RTN
3190 CEFBS_None, // RAT_ATOMIC_SUB_NORET
3191 CEFBS_None, // RAT_ATOMIC_SUB_RTN
3192 CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET
3193 CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN
3194 CEFBS_None, // RAT_ATOMIC_XOR_NORET
3195 CEFBS_None, // RAT_ATOMIC_XOR_RTN
3196 CEFBS_None, // RAT_MSKOR
3197 CEFBS_None, // RAT_STORE_DWORD128
3198 CEFBS_None, // RAT_STORE_DWORD32
3199 CEFBS_None, // RAT_STORE_DWORD64
3200 CEFBS_None, // RAT_STORE_TYPED_cm
3201 CEFBS_None, // RAT_STORE_TYPED_eg
3202 CEFBS_None, // RAT_WRITE_CACHELESS_128_eg
3203 CEFBS_None, // RAT_WRITE_CACHELESS_32_eg
3204 CEFBS_None, // RAT_WRITE_CACHELESS_64_eg
3205 CEFBS_None, // RECIPSQRT_CLAMPED_cm
3206 CEFBS_None, // RECIPSQRT_CLAMPED_eg
3207 CEFBS_None, // RECIPSQRT_CLAMPED_r600
3208 CEFBS_None, // RECIPSQRT_IEEE_cm
3209 CEFBS_None, // RECIPSQRT_IEEE_eg
3210 CEFBS_None, // RECIPSQRT_IEEE_r600
3211 CEFBS_None, // RECIP_CLAMPED_cm
3212 CEFBS_None, // RECIP_CLAMPED_eg
3213 CEFBS_None, // RECIP_CLAMPED_r600
3214 CEFBS_None, // RECIP_IEEE_cm
3215 CEFBS_None, // RECIP_IEEE_eg
3216 CEFBS_None, // RECIP_IEEE_r600
3217 CEFBS_None, // RECIP_UINT_eg
3218 CEFBS_None, // RECIP_UINT_r600
3219 CEFBS_None, // RNDNE
3220 CEFBS_None, // SETE
3221 CEFBS_None, // SETE_DX10
3222 CEFBS_None, // SETE_INT
3223 CEFBS_None, // SETGE_DX10
3224 CEFBS_None, // SETGE_INT
3225 CEFBS_None, // SETGE_UINT
3226 CEFBS_None, // SETGT_DX10
3227 CEFBS_None, // SETGT_INT
3228 CEFBS_None, // SETGT_UINT
3229 CEFBS_None, // SETNE_DX10
3230 CEFBS_None, // SETNE_INT
3231 CEFBS_None, // SGE
3232 CEFBS_None, // SGT
3233 CEFBS_None, // SIN_cm
3234 CEFBS_None, // SIN_eg
3235 CEFBS_None, // SIN_r600
3236 CEFBS_None, // SIN_r700
3237 CEFBS_None, // SNE
3238 CEFBS_None, // SUBB_UINT
3239 CEFBS_None, // SUB_INT
3240 CEFBS_None, // TEX_GET_GRADIENTS_H
3241 CEFBS_None, // TEX_GET_GRADIENTS_V
3242 CEFBS_None, // TEX_GET_TEXTURE_RESINFO
3243 CEFBS_None, // TEX_LD
3244 CEFBS_None, // TEX_LDPTR
3245 CEFBS_None, // TEX_SAMPLE
3246 CEFBS_None, // TEX_SAMPLE_C
3247 CEFBS_None, // TEX_SAMPLE_C_G
3248 CEFBS_None, // TEX_SAMPLE_C_L
3249 CEFBS_None, // TEX_SAMPLE_C_LB
3250 CEFBS_None, // TEX_SAMPLE_G
3251 CEFBS_None, // TEX_SAMPLE_L
3252 CEFBS_None, // TEX_SAMPLE_LB
3253 CEFBS_None, // TEX_SET_GRADIENTS_H
3254 CEFBS_None, // TEX_SET_GRADIENTS_V
3255 CEFBS_None, // TEX_VTX_CONSTBUF
3256 CEFBS_None, // TEX_VTX_TEXBUF
3257 CEFBS_None, // TRUNC
3258 CEFBS_None, // UINT_TO_FLT_eg
3259 CEFBS_None, // UINT_TO_FLT_r600
3260 CEFBS_None, // VTX_READ_128_cm
3261 CEFBS_None, // VTX_READ_128_eg
3262 CEFBS_None, // VTX_READ_16_cm
3263 CEFBS_None, // VTX_READ_16_eg
3264 CEFBS_None, // VTX_READ_32_cm
3265 CEFBS_None, // VTX_READ_32_eg
3266 CEFBS_None, // VTX_READ_64_cm
3267 CEFBS_None, // VTX_READ_64_eg
3268 CEFBS_None, // VTX_READ_8_cm
3269 CEFBS_None, // VTX_READ_8_eg
3270 CEFBS_None, // WHILE_LOOP_EG
3271 CEFBS_None, // WHILE_LOOP_R600
3272 CEFBS_None, // XOR_INT
3273 };
3274
3275 assert(Opcode < 674);
3276 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3277}
3278
3279
3280} // namespace llvm::R600_MC
3281
3282#endif // GET_COMPUTE_FEATURES
3283
3284#ifdef GET_AVAILABLE_OPCODE_CHECKER
3285#undef GET_AVAILABLE_OPCODE_CHECKER
3286
3287namespace llvm::R600_MC {
3288
3289bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3290 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3291 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3292 FeatureBitset MissingFeatures =
3293 (AvailableFeatures & RequiredFeatures) ^
3294 RequiredFeatures;
3295 return !MissingFeatures.any();
3296}
3297
3298} // namespace llvm::R600_MC
3299
3300#endif // GET_AVAILABLE_OPCODE_CHECKER
3301
3302#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3303#undef ENABLE_INSTR_PREDICATE_VERIFIER
3304
3305#include <sstream>
3306
3307namespace llvm::R600_MC {
3308
3309#ifndef NDEBUG
3310static const char *SubtargetFeatureNames[] = {
3311 nullptr
3312};
3313
3314#endif // NDEBUG
3315
3316void verifyInstructionPredicates(
3317 unsigned Opcode, const FeatureBitset &Features) {
3318#ifndef NDEBUG
3319 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3320 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3321 FeatureBitset MissingFeatures =
3322 (AvailableFeatures & RequiredFeatures) ^
3323 RequiredFeatures;
3324 if (MissingFeatures.any()) {
3325 std::ostringstream Msg;
3326 Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
3327 << " instruction but the ";
3328 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3329 if (MissingFeatures.test(i))
3330 Msg << SubtargetFeatureNames[i] << " ";
3331 Msg << "predicate(s) are not met";
3332 report_fatal_error(Msg.str().c_str());
3333 }
3334#endif // NDEBUG
3335}
3336
3337} // namespace llvm::R600_MC
3338
3339#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3340
3341#ifdef GET_INSTRMAP_INFO
3342#undef GET_INSTRMAP_INFO
3343
3344namespace llvm::R600 {
3345
3346enum usesCustomInserter {
3347 usesCustomInserter_0
3348};
3349
3350// getLDSNoRetOp
3351LLVM_READONLY
3352int32_t getLDSNoRetOp(uint32_t Opcode) {
3353 using namespace R600;
3354 static constexpr uint32_t Table[][2] = {
3355 { LDS_ADD_RET, LDS_ADD },
3356 { LDS_AND_RET, LDS_AND },
3357 { LDS_MAX_INT_RET, LDS_MAX_INT },
3358 { LDS_MAX_UINT_RET, LDS_MAX_UINT },
3359 { LDS_MIN_INT_RET, LDS_MIN_INT },
3360 { LDS_MIN_UINT_RET, LDS_MIN_UINT },
3361 { LDS_OR_RET, LDS_OR },
3362 { LDS_SUB_RET, LDS_SUB },
3363 { LDS_WRXCHG_RET, LDS_WRXCHG },
3364 { LDS_XOR_RET, LDS_XOR },
3365 }; // End of Table
3366
3367 unsigned mid;
3368 unsigned start = 0;
3369 unsigned end = 10;
3370 while (start < end) {
3371 mid = start + (end - start) / 2;
3372 if (Opcode == Table[mid][0])
3373 break;
3374 if (Opcode < Table[mid][0])
3375 end = mid;
3376 else
3377 start = mid + 1;
3378 }
3379 if (start == end)
3380 return -1; // Instruction doesn't exist in this table.
3381
3382 return Table[mid][1];
3383}
3384
3385
3386} // namespace llvm::R600
3387
3388#endif // GET_INSTRMAP_INFO
3389
3390