1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::R600 {
13
14 enum {
15 PHI = 0, // Target.td:1324
16 INLINEASM = 1, // Target.td:1330
17 INLINEASM_BR = 2, // Target.td:1336
18 CFI_INSTRUCTION = 3, // Target.td:1345
19 EH_LABEL = 4, // Target.td:1354
20 GC_LABEL = 5, // Target.td:1363
21 ANNOTATION_LABEL = 6, // Target.td:1372
22 KILL = 7, // Target.td:1380
23 EXTRACT_SUBREG = 8, // Target.td:1387
24 INSERT_SUBREG = 9, // Target.td:1393
25 IMPLICIT_DEF = 10, // Target.td:1400
26 INIT_UNDEF = 11, // Target.td:1409
27 SUBREG_TO_REG = 12, // Target.td:1416
28 COPY_TO_REGCLASS = 13, // Target.td:1422
29 DBG_VALUE = 14, // Target.td:1429
30 DBG_VALUE_LIST = 15, // Target.td:1436
31 DBG_INSTR_REF = 16, // Target.td:1443
32 DBG_PHI = 17, // Target.td:1450
33 DBG_LABEL = 18, // Target.td:1457
34 REG_SEQUENCE = 19, // Target.td:1464
35 COPY = 20, // Target.td:1471
36 COPY_LANEMASK = 21, // Target.td:1479
37 BUNDLE = 22, // Target.td:1486
38 LIFETIME_START = 23, // Target.td:1492
39 LIFETIME_END = 24, // Target.td:1499
40 PSEUDO_PROBE = 25, // Target.td:1506
41 ARITH_FENCE = 26, // Target.td:1513
42 STACKMAP = 27, // Target.td:1522
43 FENTRY_CALL = 28, // Target.td:1657
44 PATCHPOINT = 29, // Target.td:1530
45 LOAD_STACK_GUARD = 30, // Target.td:1548
46 PREALLOCATED_SETUP = 31, // Target.td:1556
47 PREALLOCATED_ARG = 32, // Target.td:1562
48 STATEPOINT = 33, // Target.td:1539
49 LOCAL_ESCAPE = 34, // Target.td:1568
50 FAULTING_OP = 35, // Target.td:1577
51 PATCHABLE_OP = 36, // Target.td:1597
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1605
53 PATCHABLE_RET = 38, // Target.td:1612
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1621
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1629
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1637
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1647
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1667
59 FAKE_USE = 44, // Target.td:1587
60 MEMBARRIER = 45, // Target.td:1673
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1681
62 RELOC_NONE = 47, // Target.td:1689
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1701
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1697
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1705
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1709
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1929
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1921
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1936
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1516
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1529
96 G_INSERT = 81, // GenericOpcodes.td:1538
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1548
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1568
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1578
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1585
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1943
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1481
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1482
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1483
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1484
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1485
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1486
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1487
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1488
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1494
150 G_PREFETCH = 135, // GenericOpcodes.td:1501
151 G_BRCOND = 136, // GenericOpcodes.td:1641
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1650
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1673
154 G_INTRINSIC = 139, // GenericOpcodes.td:1593
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1600
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1609
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1617
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1631
265 G_BRJT = 250, // GenericOpcodes.td:1661
266 G_VSCALE = 251, // GenericOpcodes.td:1559
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1705
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1713
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1721
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1729
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1740
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1748
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1756
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1763
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1813
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1814
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1815
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1816
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1817
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1818
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1819
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1820
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1821
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1822
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1680
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1690
318 G_MEMCPY = 303, // GenericOpcodes.td:1828
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1836
320 G_MEMMOVE = 305, // GenericOpcodes.td:1844
321 G_MEMSET = 306, // GenericOpcodes.td:1852
322 G_BZERO = 307, // GenericOpcodes.td:1859
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1866
324 G_TRAP = 309, // GenericOpcodes.td:1876
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1883
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1889
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1779
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1785
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1791
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1792
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1794
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1795
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1796
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1797
335 G_VECREDUCE_ADD = 320, // GenericOpcodes.td:1799
336 G_VECREDUCE_MUL = 321, // GenericOpcodes.td:1800
337 G_VECREDUCE_AND = 322, // GenericOpcodes.td:1801
338 G_VECREDUCE_OR = 323, // GenericOpcodes.td:1802
339 G_VECREDUCE_XOR = 324, // GenericOpcodes.td:1803
340 G_VECREDUCE_SMAX = 325, // GenericOpcodes.td:1804
341 G_VECREDUCE_SMIN = 326, // GenericOpcodes.td:1805
342 G_VECREDUCE_UMAX = 327, // GenericOpcodes.td:1806
343 G_VECREDUCE_UMIN = 328, // GenericOpcodes.td:1807
344 G_SBFX = 329, // GenericOpcodes.td:1901
345 G_UBFX = 330, // GenericOpcodes.td:1909
346 BRANCH = 331, // R600Instructions.td:1594
347 BRANCH_COND_f32 = 332, // R600Instructions.td:1567
348 BRANCH_COND_i32 = 333, // R600Instructions.td:1563
349 BREAK = 334, // R600Instructions.td:1608
350 BREAKC_f32 = 335, // R600Instructions.td:1584
351 BREAKC_i32 = 336, // R600Instructions.td:1582
352 BREAK_LOGICALNZ_f32 = 337, // R600Instructions.td:1577
353 BREAK_LOGICALNZ_i32 = 338, // R600Instructions.td:1575
354 BREAK_LOGICALZ_f32 = 339, // R600Instructions.td:1577
355 BREAK_LOGICALZ_i32 = 340, // R600Instructions.td:1575
356 CONST_COPY = 341, // R600Instructions.td:1439
357 CONTINUE = 342, // R600Instructions.td:1610
358 CONTINUEC_f32 = 343, // R600Instructions.td:1584
359 CONTINUEC_i32 = 344, // R600Instructions.td:1582
360 CONTINUE_LOGICALNZ_f32 = 345, // R600Instructions.td:1577
361 CONTINUE_LOGICALNZ_i32 = 346, // R600Instructions.td:1575
362 CONTINUE_LOGICALZ_f32 = 347, // R600Instructions.td:1577
363 CONTINUE_LOGICALZ_i32 = 348, // R600Instructions.td:1575
364 CUBE_eg_pseudo = 349, // R600Instructions.td:1074
365 CUBE_r600_pseudo = 350, // R600Instructions.td:1074
366 DEFAULT = 351, // R600Instructions.td:1612
367 DOT_4 = 352, // R600Instructions.td:1061
368 DUMMY_CHAIN = 353, // R600Instructions.td:792
369 ELSE = 354, // R600Instructions.td:1614
370 END = 355, // R600Instructions.td:1620
371 ENDFUNC = 356, // R600Instructions.td:1622
372 ENDIF = 357, // R600Instructions.td:1624
373 ENDLOOP = 358, // R600Instructions.td:1628
374 ENDMAIN = 359, // R600Instructions.td:1618
375 ENDSWITCH = 360, // R600Instructions.td:1616
376 FABS_R600 = 361, // R600Instructions.td:1204
377 FNEG_R600 = 362, // R600Instructions.td:1205
378 FUNC = 363, // R600Instructions.td:1630
379 IFC_f32 = 364, // R600Instructions.td:1584
380 IFC_i32 = 365, // R600Instructions.td:1582
381 IF_LOGICALNZ_f32 = 366, // R600Instructions.td:1577
382 IF_LOGICALNZ_i32 = 367, // R600Instructions.td:1575
383 IF_LOGICALZ_f32 = 368, // R600Instructions.td:1577
384 IF_LOGICALZ_i32 = 369, // R600Instructions.td:1575
385 IF_PREDICATE_SET = 370, // R600Instructions.td:1604
386 JUMP = 371, // R600Instructions.td:1385
387 JUMP_COND = 372, // R600Instructions.td:1378
388 MASK_WRITE = 373, // R600Instructions.td:1402
389 MOV_IMM_F32 = 374, // R600Instructions.td:827
390 MOV_IMM_GLOBAL_ADDR = 375, // R600Instructions.td:820
391 MOV_IMM_I32 = 376, // R600Instructions.td:814
392 PRED_X = 377, // R600Instructions.td:1370
393 R600_EXTRACT_ELT_V2 = 378, // R600Instructions.td:1677
394 R600_EXTRACT_ELT_V4 = 379, // R600Instructions.td:1678
395 R600_INSERT_ELT_V2 = 380, // R600Instructions.td:1680
396 R600_INSERT_ELT_V4 = 381, // R600Instructions.td:1681
397 R600_RegisterLoad = 382, // R600Instructions.td:698
398 R600_RegisterStore = 383, // R600Instructions.td:707
399 RETDYN = 384, // R600Instructions.td:1632
400 RETURN = 385, // R600Instructions.td:88
401 TXD = 386, // R600Instructions.td:1413
402 TXD_SHADOW = 387, // R600Instructions.td:1422
403 WHILELOOP = 388, // R600Instructions.td:1626
404 ADD = 389, // R600Instructions.td:721
405 ADDC_UINT = 390, // EvergreenInstructions.td:523
406 ADD_INT = 391, // R600Instructions.td:848
407 ALU_CLAUSE = 392, // R600Instructions.td:646
408 AND_INT = 393, // R600Instructions.td:844
409 ASHR_eg = 394, // EvergreenInstructions.td:508
410 ASHR_r600 = 395, // R600Instructions.td:1253
411 BCNT_INT = 396, // EvergreenInstructions.td:528
412 BFE_INT_eg = 397, // EvergreenInstructions.td:370
413 BFE_UINT_eg = 398, // EvergreenInstructions.td:365
414 BFI_INT_eg = 399, // EvergreenInstructions.td:411
415 BFM_INT_eg = 400, // EvergreenInstructions.td:492
416 BIT_ALIGN_INT_eg = 401, // EvergreenInstructions.td:500
417 CEIL = 402, // R600Instructions.td:781
418 CF_ALU = 403, // R600Instructions.td:631
419 CF_ALU_BREAK = 404, // R600Instructions.td:635
420 CF_ALU_CONTINUE = 405, // R600Instructions.td:634
421 CF_ALU_ELSE_AFTER = 406, // R600Instructions.td:636
422 CF_ALU_POP_AFTER = 407, // R600Instructions.td:633
423 CF_ALU_PUSH_BEFORE = 408, // R600Instructions.td:632
424 CF_CALL_FS_EG = 409, // EvergreenInstructions.td:850
425 CF_CALL_FS_R600 = 410, // R600Instructions.td:1325
426 CF_CONTINUE_EG = 411, // EvergreenInstructions.td:833
427 CF_CONTINUE_R600 = 412, // R600Instructions.td:1307
428 CF_ELSE_EG = 413, // EvergreenInstructions.td:846
429 CF_ELSE_R600 = 414, // R600Instructions.td:1321
430 CF_END_CM = 415, // CaymanInstructions.td:66
431 CF_END_EG = 416, // EvergreenInstructions.td:859
432 CF_END_R600 = 417, // R600Instructions.td:1334
433 CF_JUMP_EG = 418, // EvergreenInstructions.td:838
434 CF_JUMP_R600 = 419, // R600Instructions.td:1312
435 CF_PUSH_EG = 420, // EvergreenInstructions.td:842
436 CF_PUSH_ELSE_R600 = 421, // R600Instructions.td:1316
437 CF_TC_EG = 422, // EvergreenInstructions.td:811
438 CF_TC_R600 = 423, // R600Instructions.td:1285
439 CF_VC_EG = 424, // EvergreenInstructions.td:815
440 CF_VC_R600 = 425, // R600Instructions.td:1289
441 CNDE_INT = 426, // R600Instructions.td:890
442 CNDE_eg = 427, // EvergreenInstructions.td:511
443 CNDE_r600 = 428, // R600Instructions.td:1235
444 CNDGE_INT = 429, // R600Instructions.td:895
445 CNDGE_eg = 430, // EvergreenInstructions.td:513
446 CNDGE_r600 = 431, // R600Instructions.td:1237
447 CNDGT_INT = 432, // R600Instructions.td:900
448 CNDGT_eg = 433, // EvergreenInstructions.td:512
449 CNDGT_r600 = 434, // R600Instructions.td:1236
450 COS_cm = 435, // CaymanInstructions.td:48
451 COS_eg = 436, // EvergreenInstructions.td:132
452 COS_r600 = 437, // R600Instructions.td:1252
453 COS_r700 = 438, // R700Instructions.td:19
454 CUBE_eg_real = 439, // R600Instructions.td:1085
455 CUBE_r600_real = 440, // R600Instructions.td:1085
456 DOT4_eg = 441, // EvergreenInstructions.td:519
457 DOT4_r600 = 442, // R600Instructions.td:1238
458 EG_ExportBuf = 443, // EvergreenInstructions.td:801
459 EG_ExportSwz = 444, // EvergreenInstructions.td:791
460 END_LOOP_EG = 445, // EvergreenInstructions.td:824
461 END_LOOP_R600 = 446, // R600Instructions.td:1298
462 EXP_IEEE_cm = 447, // CaymanInstructions.td:43
463 EXP_IEEE_eg = 448, // EvergreenInstructions.td:125
464 EXP_IEEE_r600 = 449, // R600Instructions.td:1240
465 FETCH_CLAUSE = 450, // R600Instructions.td:638
466 FFBH_UINT = 451, // EvergreenInstructions.td:529
467 FFBL_INT = 452, // EvergreenInstructions.td:530
468 FLOOR = 453, // R600Instructions.td:783
469 FLT16_TO_FLT32 = 454, // EvergreenInstructions.td:527
470 FLT32_TO_FLT16 = 455, // EvergreenInstructions.td:526
471 FLT_TO_INT_eg = 456, // EvergreenInstructions.td:536
472 FLT_TO_INT_r600 = 457, // R600Instructions.td:1247
473 FLT_TO_UINT_eg = 458, // EvergreenInstructions.td:543
474 FLT_TO_UINT_r600 = 459, // R600Instructions.td:1249
475 FMA_eg = 460, // EvergreenInstructions.td:507
476 FRACT = 461, // R600Instructions.td:779
477 GROUP_BARRIER = 462, // EvergreenInstructions.td:549
478 INTERP_LOAD_P0 = 463, // R600Instructions.td:445
479 INTERP_PAIR_XY = 464, // R600Instructions.td:367
480 INTERP_PAIR_ZW = 465, // R600Instructions.td:373
481 INTERP_VEC_LOAD = 466, // R600Instructions.td:430
482 INTERP_XY = 467, // R600Instructions.td:437
483 INTERP_ZW = 468, // R600Instructions.td:441
484 INT_TO_FLT_eg = 469, // EvergreenInstructions.td:541
485 INT_TO_FLT_r600 = 470, // R600Instructions.td:1248
486 KILLGT = 471, // R600Instructions.td:840
487 LDS_ADD = 472, // EvergreenInstructions.td:687
488 LDS_ADD_RET = 473, // EvergreenInstructions.td:707
489 LDS_AND = 474, // EvergreenInstructions.td:689
490 LDS_AND_RET = 475, // EvergreenInstructions.td:713
491 LDS_BYTE_READ_RET = 476, // EvergreenInstructions.td:743
492 LDS_BYTE_WRITE = 477, // EvergreenInstructions.td:701
493 LDS_CMPST = 478, // EvergreenInstructions.td:693
494 LDS_CMPST_RET = 479, // EvergreenInstructions.td:737
495 LDS_MAX_INT = 480, // EvergreenInstructions.td:695
496 LDS_MAX_INT_RET = 481, // EvergreenInstructions.td:725
497 LDS_MAX_UINT = 482, // EvergreenInstructions.td:697
498 LDS_MAX_UINT_RET = 483, // EvergreenInstructions.td:731
499 LDS_MIN_INT = 484, // EvergreenInstructions.td:694
500 LDS_MIN_INT_RET = 485, // EvergreenInstructions.td:722
501 LDS_MIN_UINT = 486, // EvergreenInstructions.td:696
502 LDS_MIN_UINT_RET = 487, // EvergreenInstructions.td:728
503 LDS_OR = 488, // EvergreenInstructions.td:690
504 LDS_OR_RET = 489, // EvergreenInstructions.td:716
505 LDS_READ_RET = 490, // EvergreenInstructions.td:740
506 LDS_SHORT_READ_RET = 491, // EvergreenInstructions.td:749
507 LDS_SHORT_WRITE = 492, // EvergreenInstructions.td:704
508 LDS_SUB = 493, // EvergreenInstructions.td:688
509 LDS_SUB_RET = 494, // EvergreenInstructions.td:710
510 LDS_UBYTE_READ_RET = 495, // EvergreenInstructions.td:746
511 LDS_USHORT_READ_RET = 496, // EvergreenInstructions.td:752
512 LDS_WRITE = 497, // EvergreenInstructions.td:698
513 LDS_WRXCHG = 498, // EvergreenInstructions.td:692
514 LDS_WRXCHG_RET = 499, // EvergreenInstructions.td:734
515 LDS_XOR = 500, // EvergreenInstructions.td:691
516 LDS_XOR_RET = 501, // EvergreenInstructions.td:719
517 LITERALS = 502, // R600Instructions.td:654
518 LOG_CLAMPED_eg = 503, // EvergreenInstructions.td:515
519 LOG_CLAMPED_r600 = 504, // R600Instructions.td:1241
520 LOG_IEEE_cm = 505, // CaymanInstructions.td:44
521 LOG_IEEE_eg = 506, // EvergreenInstructions.td:126
522 LOG_IEEE_r600 = 507, // R600Instructions.td:1242
523 LOOP_BREAK_EG = 508, // EvergreenInstructions.td:828
524 LOOP_BREAK_R600 = 509, // R600Instructions.td:1302
525 LSHL_eg = 510, // EvergreenInstructions.td:510
526 LSHL_r600 = 511, // R600Instructions.td:1255
527 LSHR_eg = 512, // EvergreenInstructions.td:509
528 LSHR_r600 = 513, // R600Instructions.td:1254
529 MAX = 514, // R600Instructions.td:726
530 MAX_DX10 = 515, // R600Instructions.td:731
531 MAX_INT = 516, // R600Instructions.td:850
532 MAX_UINT = 517, // R600Instructions.td:852
533 MIN = 518, // R600Instructions.td:727
534 MIN_DX10 = 519, // R600Instructions.td:732
535 MIN_INT = 520, // R600Instructions.td:851
536 MIN_UINT = 521, // R600Instructions.td:853
537 MOV = 522, // R600Instructions.td:785
538 MOVA_INT_eg = 523, // EvergreenInstructions.td:533
539 MUL = 524, // R600Instructions.td:723
540 MULADD_IEEE_eg = 525, // EvergreenInstructions.td:506
541 MULADD_IEEE_r600 = 526, // R600Instructions.td:1234
542 MULADD_INT24_cm = 527, // CaymanInstructions.td:22
543 MULADD_UINT24_eg = 528, // EvergreenInstructions.td:494
544 MULADD_eg = 529, // EvergreenInstructions.td:505
545 MULADD_r600 = 530, // R600Instructions.td:1233
546 MULHI_INT_cm = 531, // CaymanInstructions.td:36
547 MULHI_INT_cm24 = 532, // CaymanInstructions.td:39
548 MULHI_INT_eg = 533, // EvergreenInstructions.td:118
549 MULHI_INT_r600 = 534, // R600Instructions.td:1257
550 MULHI_UINT24_eg = 535, // EvergreenInstructions.td:121
551 MULHI_UINT_cm = 536, // CaymanInstructions.td:38
552 MULHI_UINT_cm24 = 537, // CaymanInstructions.td:40
553 MULHI_UINT_eg = 538, // EvergreenInstructions.td:120
554 MULHI_UINT_r600 = 539, // R600Instructions.td:1259
555 MULLO_INT_cm = 540, // CaymanInstructions.td:35
556 MULLO_INT_eg = 541, // EvergreenInstructions.td:117
557 MULLO_INT_r600 = 542, // R600Instructions.td:1256
558 MULLO_UINT_cm = 543, // CaymanInstructions.td:37
559 MULLO_UINT_eg = 544, // EvergreenInstructions.td:119
560 MULLO_UINT_r600 = 545, // R600Instructions.td:1258
561 MUL_IEEE = 546, // R600Instructions.td:724
562 MUL_INT24_cm = 547, // CaymanInstructions.td:25
563 MUL_LIT_eg = 548, // EvergreenInstructions.td:514
564 MUL_LIT_r600 = 549, // R600Instructions.td:1232
565 MUL_UINT24_eg = 550, // EvergreenInstructions.td:516
566 NOT_INT = 551, // R600Instructions.td:847
567 OR_INT = 552, // R600Instructions.td:845
568 PAD = 553, // R600Instructions.td:666
569 POP_EG = 554, // EvergreenInstructions.td:855
570 POP_R600 = 555, // R600Instructions.td:1330
571 PRED_SETE = 556, // R600Instructions.td:833
572 PRED_SETE_INT = 557, // R600Instructions.td:885
573 PRED_SETGE = 558, // R600Instructions.td:835
574 PRED_SETGE_INT = 559, // R600Instructions.td:887
575 PRED_SETGT = 560, // R600Instructions.td:834
576 PRED_SETGT_INT = 561, // R600Instructions.td:886
577 PRED_SETNE = 562, // R600Instructions.td:836
578 PRED_SETNE_INT = 563, // R600Instructions.td:888
579 R600_ExportBuf = 564, // R600Instructions.td:1276
580 R600_ExportSwz = 565, // R600Instructions.td:1267
581 RAT_ATOMIC_ADD_NORET = 566, // EvergreenInstructions.td:82
582 RAT_ATOMIC_ADD_RTN = 567, // EvergreenInstructions.td:78
583 RAT_ATOMIC_AND_NORET = 568, // EvergreenInstructions.td:82
584 RAT_ATOMIC_AND_RTN = 569, // EvergreenInstructions.td:78
585 RAT_ATOMIC_CMPXCHG_INT_NORET = 570, // EvergreenInstructions.td:82
586 RAT_ATOMIC_CMPXCHG_INT_RTN = 571, // EvergreenInstructions.td:78
587 RAT_ATOMIC_DEC_UINT_NORET = 572, // EvergreenInstructions.td:82
588 RAT_ATOMIC_DEC_UINT_RTN = 573, // EvergreenInstructions.td:78
589 RAT_ATOMIC_INC_UINT_NORET = 574, // EvergreenInstructions.td:82
590 RAT_ATOMIC_INC_UINT_RTN = 575, // EvergreenInstructions.td:78
591 RAT_ATOMIC_MAX_INT_NORET = 576, // EvergreenInstructions.td:82
592 RAT_ATOMIC_MAX_INT_RTN = 577, // EvergreenInstructions.td:78
593 RAT_ATOMIC_MAX_UINT_NORET = 578, // EvergreenInstructions.td:82
594 RAT_ATOMIC_MAX_UINT_RTN = 579, // EvergreenInstructions.td:78
595 RAT_ATOMIC_MIN_INT_NORET = 580, // EvergreenInstructions.td:82
596 RAT_ATOMIC_MIN_INT_RTN = 581, // EvergreenInstructions.td:78
597 RAT_ATOMIC_MIN_UINT_NORET = 582, // EvergreenInstructions.td:82
598 RAT_ATOMIC_MIN_UINT_RTN = 583, // EvergreenInstructions.td:78
599 RAT_ATOMIC_OR_NORET = 584, // EvergreenInstructions.td:82
600 RAT_ATOMIC_OR_RTN = 585, // EvergreenInstructions.td:78
601 RAT_ATOMIC_RSUB_NORET = 586, // EvergreenInstructions.td:82
602 RAT_ATOMIC_RSUB_RTN = 587, // EvergreenInstructions.td:78
603 RAT_ATOMIC_SUB_NORET = 588, // EvergreenInstructions.td:82
604 RAT_ATOMIC_SUB_RTN = 589, // EvergreenInstructions.td:78
605 RAT_ATOMIC_XCHG_INT_NORET = 590, // EvergreenInstructions.td:82
606 RAT_ATOMIC_XCHG_INT_RTN = 591, // EvergreenInstructions.td:78
607 RAT_ATOMIC_XOR_NORET = 592, // EvergreenInstructions.td:82
608 RAT_ATOMIC_XOR_RTN = 593, // EvergreenInstructions.td:78
609 RAT_MSKOR = 594, // EvergreenInstructions.td:67
610 RAT_STORE_DWORD128 = 595, // CaymanInstructions.td:84
611 RAT_STORE_DWORD32 = 596, // CaymanInstructions.td:82
612 RAT_STORE_DWORD64 = 597, // CaymanInstructions.td:83
613 RAT_STORE_TYPED_cm = 598, // CaymanInstructions.td:86
614 RAT_STORE_TYPED_eg = 599, // EvergreenInstructions.td:164
615 RAT_WRITE_CACHELESS_128_eg = 600, // EvergreenInstructions.td:158
616 RAT_WRITE_CACHELESS_32_eg = 601, // EvergreenInstructions.td:144
617 RAT_WRITE_CACHELESS_64_eg = 602, // EvergreenInstructions.td:151
618 RECIPSQRT_CLAMPED_cm = 603, // CaymanInstructions.td:42
619 RECIPSQRT_CLAMPED_eg = 604, // EvergreenInstructions.td:124
620 RECIPSQRT_CLAMPED_r600 = 605, // R600Instructions.td:1245
621 RECIPSQRT_IEEE_cm = 606, // CaymanInstructions.td:46
622 RECIPSQRT_IEEE_eg = 607, // EvergreenInstructions.td:128
623 RECIPSQRT_IEEE_r600 = 608, // R600Instructions.td:1246
624 RECIP_CLAMPED_cm = 609, // CaymanInstructions.td:45
625 RECIP_CLAMPED_eg = 610, // EvergreenInstructions.td:127
626 RECIP_CLAMPED_r600 = 611, // R600Instructions.td:1243
627 RECIP_IEEE_cm = 612, // CaymanInstructions.td:33
628 RECIP_IEEE_eg = 613, // EvergreenInstructions.td:114
629 RECIP_IEEE_r600 = 614, // R600Instructions.td:1244
630 RECIP_UINT_eg = 615, // EvergreenInstructions.td:123
631 RECIP_UINT_r600 = 616, // R600Instructions.td:1260
632 RNDNE = 617, // R600Instructions.td:782
633 SETE = 618, // R600Instructions.td:737
634 SETE_DX10 = 619, // R600Instructions.td:757
635 SETE_INT = 620, // R600Instructions.td:855
636 SETGE_DX10 = 621, // R600Instructions.td:767
637 SETGE_INT = 622, // R600Instructions.td:865
638 SETGE_UINT = 623, // R600Instructions.td:880
639 SETGT_DX10 = 624, // R600Instructions.td:762
640 SETGT_INT = 625, // R600Instructions.td:860
641 SETGT_UINT = 626, // R600Instructions.td:875
642 SETNE_DX10 = 627, // R600Instructions.td:773
643 SETNE_INT = 628, // R600Instructions.td:870
644 SGE = 629, // R600Instructions.td:747
645 SGT = 630, // R600Instructions.td:742
646 SIN_cm = 631, // CaymanInstructions.td:47
647 SIN_eg = 632, // EvergreenInstructions.td:131
648 SIN_r600 = 633, // R600Instructions.td:1251
649 SIN_r700 = 634, // R700Instructions.td:18
650 SNE = 635, // R600Instructions.td:752
651 SUBB_UINT = 636, // EvergreenInstructions.td:524
652 SUB_INT = 637, // R600Instructions.td:849
653 TEX_GET_GRADIENTS_H = 638, // R600Instructions.td:959
654 TEX_GET_GRADIENTS_V = 639, // R600Instructions.td:960
655 TEX_GET_TEXTURE_RESINFO = 640, // R600Instructions.td:958
656 TEX_LD = 641, // R600Instructions.td:954
657 TEX_LDPTR = 642, // R600Instructions.td:955
658 TEX_SAMPLE = 643, // R600Instructions.td:948
659 TEX_SAMPLE_C = 644, // R600Instructions.td:949
660 TEX_SAMPLE_C_G = 645, // R600Instructions.td:964
661 TEX_SAMPLE_C_L = 646, // R600Instructions.td:951
662 TEX_SAMPLE_C_LB = 647, // R600Instructions.td:953
663 TEX_SAMPLE_G = 648, // R600Instructions.td:963
664 TEX_SAMPLE_L = 649, // R600Instructions.td:950
665 TEX_SAMPLE_LB = 650, // R600Instructions.td:952
666 TEX_SET_GRADIENTS_H = 651, // R600Instructions.td:961
667 TEX_SET_GRADIENTS_V = 652, // R600Instructions.td:962
668 TEX_VTX_CONSTBUF = 653, // R600Instructions.td:1451
669 TEX_VTX_TEXBUF = 654, // R600Instructions.td:1505
670 TRUNC = 655, // R600Instructions.td:780
671 UINT_TO_FLT_eg = 656, // EvergreenInstructions.td:547
672 UINT_TO_FLT_r600 = 657, // R600Instructions.td:1250
673 VTX_READ_128_cm = 658, // CaymanInstructions.td:162
674 VTX_READ_128_eg = 659, // EvergreenInstructions.td:240
675 VTX_READ_16_cm = 660, // CaymanInstructions.td:120
676 VTX_READ_16_eg = 661, // EvergreenInstructions.td:195
677 VTX_READ_32_cm = 662, // CaymanInstructions.td:131
678 VTX_READ_32_eg = 663, // EvergreenInstructions.td:207
679 VTX_READ_64_cm = 664, // CaymanInstructions.td:151
680 VTX_READ_64_eg = 665, // EvergreenInstructions.td:228
681 VTX_READ_8_cm = 666, // CaymanInstructions.td:109
682 VTX_READ_8_eg = 667, // EvergreenInstructions.td:183
683 WHILE_LOOP_EG = 668, // EvergreenInstructions.td:819
684 WHILE_LOOP_R600 = 669, // R600Instructions.td:1293
685 XOR_INT = 670, // R600Instructions.td:846
686 INSTRUCTION_LIST_END = 671
687 };
688
689} // namespace llvm::R600
690
691#endif // GET_INSTRINFO_ENUM
692
693#ifdef GET_INSTRINFO_SCHED_ENUM
694#undef GET_INSTRINFO_SCHED_ENUM
695
696namespace llvm::R600::Sched {
697
698 enum {
699 NoInstrModel = 0,
700 NullALU = 1,
701 VecALU = 2,
702 AnyALU = 3,
703 TransALU = 4,
704 XALU = 5,
705 SCHED_LIST_END = 6
706 };
707
708} // namespace llvm::R600::Sched
709
710#endif // GET_INSTRINFO_SCHED_ENUM
711
712#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
713
714namespace llvm {
715
716struct R600InstrTable {
717 MCInstrDesc Insts[671];
718 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
719 MCPhysReg ImplicitOps[1];
720 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
721 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
722 MCOperandInfo OperandInfo[461];
723};
724} // namespace llvm
725
726#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
727
728#ifdef GET_INSTRINFO_MC_DESC
729#undef GET_INSTRINFO_MC_DESC
730
731namespace llvm {
732
733static_assert((sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
734static constexpr unsigned R600OpInfoBase = (sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) / sizeof(MCOperandInfo);
735
736extern const R600InstrTable R600Descs = {
737 {
738 { 670, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // XOR_INT
739 { 669, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_R600
740 { 668, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_EG
741 { 667, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_eg
742 { 666, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_cm
743 { 665, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_eg
744 { 664, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_cm
745 { 663, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_eg
746 { 662, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_cm
747 { 661, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_eg
748 { 660, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_cm
749 { 659, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_eg
750 { 658, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_cm
751 { 657, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_r600
752 { 656, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_eg
753 { 655, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // TRUNC
754 { 654, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL }, // TEX_VTX_TEXBUF
755 { 653, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0, 0x1000ULL }, // TEX_VTX_CONSTBUF
756 { 652, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_V
757 { 651, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_H
758 { 650, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_LB
759 { 649, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_L
760 { 648, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_G
761 { 647, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_LB
762 { 646, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_L
763 { 645, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_G
764 { 644, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C
765 { 643, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE
766 { 642, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LDPTR
767 { 641, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LD
768 { 640, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_TEXTURE_RESINFO
769 { 639, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_V
770 { 638, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_H
771 { 637, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUB_INT
772 { 636, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUBB_UINT
773 { 635, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SNE
774 { 634, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r700
775 { 633, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r600
776 { 632, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_eg
777 { 631, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // SIN_cm
778 { 630, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGT
779 { 629, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGE
780 { 628, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_INT
781 { 627, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_DX10
782 { 626, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_UINT
783 { 625, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_INT
784 { 624, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_DX10
785 { 623, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_UINT
786 { 622, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_INT
787 { 621, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_DX10
788 { 620, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_INT
789 { 619, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_DX10
790 { 618, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE
791 { 617, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RNDNE
792 { 616, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_r600
793 { 615, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_eg
794 { 614, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_r600
795 { 613, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_eg
796 { 612, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_IEEE_cm
797 { 611, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_r600
798 { 610, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_eg
799 { 609, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_CLAMPED_cm
800 { 608, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_r600
801 { 607, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_eg
802 { 606, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_IEEE_cm
803 { 605, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_r600
804 { 604, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_eg
805 { 603, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_CLAMPED_cm
806 { 602, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 423, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_64_eg
807 { 601, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 420, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_32_eg
808 { 600, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 417, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_128_eg
809 { 599, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_eg
810 { 598, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_cm
811 { 597, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 411, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD64
812 { 596, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 409, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD32
813 { 595, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD128
814 { 594, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_MSKOR
815 { 593, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_RTN
816 { 592, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_NORET
817 { 591, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_RTN
818 { 590, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_NORET
819 { 589, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_RTN
820 { 588, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_NORET
821 { 587, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_RTN
822 { 586, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_NORET
823 { 585, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_RTN
824 { 584, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_NORET
825 { 583, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_RTN
826 { 582, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_NORET
827 { 581, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_RTN
828 { 580, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_NORET
829 { 579, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_RTN
830 { 578, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_NORET
831 { 577, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_RTN
832 { 576, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_NORET
833 { 575, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_RTN
834 { 574, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_NORET
835 { 573, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_RTN
836 { 572, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_NORET
837 { 571, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_RTN
838 { 570, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_NORET
839 { 569, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_RTN
840 { 568, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_NORET
841 { 567, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_RTN
842 { 566, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_NORET
843 { 565, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportSwz
844 { 564, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportBuf
845 { 563, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE_INT
846 { 562, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE
847 { 561, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT_INT
848 { 560, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT
849 { 559, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE_INT
850 { 558, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE
851 { 557, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE_INT
852 { 556, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE
853 { 555, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_R600
854 { 554, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_EG
855 { 553, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PAD
856 { 552, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // OR_INT
857 { 551, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // NOT_INT
858 { 550, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_UINT24_eg
859 { 549, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_r600
860 { 548, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_eg
861 { 547, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_INT24_cm
862 { 546, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_IEEE
863 { 545, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_r600
864 { 544, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_eg
865 { 543, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_UINT_cm
866 { 542, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_r600
867 { 541, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_eg
868 { 540, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_INT_cm
869 { 539, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_r600
870 { 538, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_eg
871 { 537, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm24
872 { 536, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm
873 { 535, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT24_eg
874 { 534, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_r600
875 { 533, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_eg
876 { 532, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm24
877 { 531, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm
878 { 530, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_r600
879 { 529, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_eg
880 { 528, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_UINT24_eg
881 { 527, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_INT24_cm
882 { 526, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_r600
883 { 525, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_eg
884 { 524, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL
885 { 523, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL }, // MOVA_INT_eg
886 { 522, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // MOV
887 { 521, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_UINT
888 { 520, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_INT
889 { 519, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_DX10
890 { 518, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN
891 { 517, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_UINT
892 { 516, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_INT
893 { 515, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_DX10
894 { 514, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX
895 { 513, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_r600
896 { 512, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_eg
897 { 511, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_r600
898 { 510, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_eg
899 { 509, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_R600
900 { 508, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_EG
901 { 507, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_r600
902 { 506, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_eg
903 { 505, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // LOG_IEEE_cm
904 { 504, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_r600
905 { 503, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_eg
906 { 502, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LITERALS
907 { 501, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_XOR_RET
908 { 500, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_XOR
909 { 499, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_WRXCHG_RET
910 { 498, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_WRXCHG
911 { 497, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_WRITE
912 { 496, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_USHORT_READ_RET
913 { 495, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_UBYTE_READ_RET
914 { 494, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_SUB_RET
915 { 493, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_SUB
916 { 492, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_SHORT_WRITE
917 { 491, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_SHORT_READ_RET
918 { 490, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_READ_RET
919 { 489, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_OR_RET
920 { 488, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_OR
921 { 487, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_UINT_RET
922 { 486, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_UINT
923 { 485, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_INT_RET
924 { 484, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_INT
925 { 483, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_UINT_RET
926 { 482, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_UINT
927 { 481, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_INT_RET
928 { 480, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_INT
929 { 479, 13, 1, 0, 5, 0, 0, R600OpInfoBase + 391, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL }, // LDS_CMPST_RET
930 { 478, 12, 0, 0, 5, 0, 0, R600OpInfoBase + 379, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL }, // LDS_CMPST
931 { 477, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_BYTE_WRITE
932 { 476, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_BYTE_READ_RET
933 { 475, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_AND_RET
934 { 474, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_AND
935 { 473, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_ADD_RET
936 { 472, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_ADD
937 { 471, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL }, // KILLGT
938 { 470, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_r600
939 { 469, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_eg
940 { 468, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_ZW
941 { 467, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_XY
942 { 466, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 351, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_VEC_LOAD
943 { 465, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 346, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_ZW
944 { 464, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 341, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_XY
945 { 463, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INTERP_LOAD_P0
946 { 462, 0, 0, 0, 3, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL }, // GROUP_BARRIER
947 { 461, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FRACT
948 { 460, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // FMA_eg
949 { 459, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_r600
950 { 458, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_eg
951 { 457, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_r600
952 { 456, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_eg
953 { 455, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT32_TO_FLT16
954 { 454, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT16_TO_FLT32
955 { 453, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLOOR
956 { 452, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBL_INT
957 { 451, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBH_UINT
958 { 450, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FETCH_CLAUSE
959 { 449, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_r600
960 { 448, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_eg
961 { 447, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // EXP_IEEE_cm
962 { 446, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_R600
963 { 445, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_EG
964 { 444, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportSwz
965 { 443, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportBuf
966 { 442, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_r600
967 { 441, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_eg
968 { 440, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_r600_real
969 { 439, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_eg_real
970 { 438, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r700
971 { 437, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r600
972 { 436, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_eg
973 { 435, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // COS_cm
974 { 434, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_r600
975 { 433, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_eg
976 { 432, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_INT
977 { 431, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_r600
978 { 430, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_eg
979 { 429, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_INT
980 { 428, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_r600
981 { 427, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_eg
982 { 426, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_INT
983 { 425, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_R600
984 { 424, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_EG
985 { 423, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_R600
986 { 422, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_EG
987 { 421, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_ELSE_R600
988 { 420, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_EG
989 { 419, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_R600
990 { 418, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_EG
991 { 417, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_R600
992 { 416, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_EG
993 { 415, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_CM
994 { 414, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_R600
995 { 413, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_EG
996 { 412, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_R600
997 { 411, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_EG
998 { 410, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_R600
999 { 409, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_EG
1000 { 408, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_PUSH_BEFORE
1001 { 407, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_POP_AFTER
1002 { 406, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_ELSE_AFTER
1003 { 405, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_CONTINUE
1004 { 404, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_BREAK
1005 { 403, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU
1006 { 402, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // CEIL
1007 { 401, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BIT_ALIGN_INT_eg
1008 { 400, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // BFM_INT_eg
1009 { 399, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFI_INT_eg
1010 { 398, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_UINT_eg
1011 { 397, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_INT_eg
1012 { 396, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // BCNT_INT
1013 { 395, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_r600
1014 { 394, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_eg
1015 { 393, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // AND_INT
1016 { 392, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALU_CLAUSE
1017 { 391, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD_INT
1018 { 390, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADDC_UINT
1019 { 389, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD
1020 { 388, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // WHILELOOP
1021 { 387, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD_SHADOW
1022 { 386, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD
1023 { 385, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL }, // RETURN
1024 { 384, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // RETDYN
1025 { 383, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL }, // R600_RegisterStore
1026 { 382, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL }, // R600_RegisterLoad
1027 { 381, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 247, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V4
1028 { 380, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V2
1029 { 379, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V4
1030 { 378, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V2
1031 { 377, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 233, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // PRED_X
1032 { 376, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_I32
1033 { 375, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_GLOBAL_ADDR
1034 { 374, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_F32
1035 { 373, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MASK_WRITE
1036 { 372, 2, 0, 0, 3, 0, 0, R600OpInfoBase + 231, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP_COND
1037 { 371, 1, 0, 0, 3, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP
1038 { 370, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // IF_PREDICATE_SET
1039 { 369, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_i32
1040 { 368, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_f32
1041 { 367, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_i32
1042 { 366, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_f32
1043 { 365, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_i32
1044 { 364, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_f32
1045 { 363, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // FUNC
1046 { 362, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FNEG_R600
1047 { 361, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FABS_R600
1048 { 360, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDSWITCH
1049 { 359, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDMAIN
1050 { 358, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDLOOP
1051 { 357, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDIF
1052 { 356, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDFUNC
1053 { 355, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // END
1054 { 354, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ELSE
1055 { 353, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // DUMMY_CHAIN
1056 { 352, 71, 1, 0, 3, 0, 0, R600OpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // DOT_4
1057 { 351, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // DEFAULT
1058 { 350, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_r600_pseudo
1059 { 349, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_eg_pseudo
1060 { 348, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_i32
1061 { 347, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_f32
1062 { 346, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_i32
1063 { 345, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_f32
1064 { 344, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_i32
1065 { 343, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_f32
1066 { 342, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE
1067 { 341, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // CONST_COPY
1068 { 340, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_i32
1069 { 339, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_f32
1070 { 338, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_i32
1071 { 337, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_f32
1072 { 336, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_i32
1073 { 335, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_f32
1074 { 334, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK
1075 { 333, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_i32
1076 { 332, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_f32
1077 { 331, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH
1078 { 330, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX
1079 { 329, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX
1080 { 328, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN
1081 { 327, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX
1082 { 326, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN
1083 { 325, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX
1084 { 324, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR
1085 { 323, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR
1086 { 322, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND
1087 { 321, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL
1088 { 320, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD
1089 { 319, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1090 { 318, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1091 { 317, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN
1092 { 316, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX
1093 { 315, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL
1094 { 314, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD
1095 { 313, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1096 { 312, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1097 { 311, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP
1098 { 310, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP
1099 { 309, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP
1100 { 308, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET_INLINE
1101 { 307, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO
1102 { 306, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET
1103 { 305, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE
1104 { 304, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE
1105 { 303, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY
1106 { 302, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1107 { 301, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1108 { 300, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMPS
1109 { 299, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMP
1110 { 298, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP
1111 { 297, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT
1112 { 296, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA
1113 { 295, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM
1114 { 294, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV
1115 { 293, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL
1116 { 292, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB
1117 { 291, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD
1118 { 290, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE
1119 { 289, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE
1120 { 288, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC
1121 { 287, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE
1122 { 286, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR
1123 { 285, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST
1124 { 284, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT
1125 { 283, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT
1126 { 282, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR
1127 { 281, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT
1128 { 280, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH
1129 { 279, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH
1130 { 278, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH
1131 { 277, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2
1132 { 276, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN
1133 { 275, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN
1134 { 274, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS
1135 { 273, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN
1136 { 272, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS
1137 { 271, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN
1138 { 270, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS
1139 { 269, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL
1140 { 268, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMUL
1141 { 267, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE
1142 { 266, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP
1143 { 265, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP
1144 { 264, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS
1145 { 263, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_POISON
1146 { 262, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ
1147 { 261, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_POISON
1148 { 260, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ
1149 { 259, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS
1150 { 258, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR
1151 { 257, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR
1152 { 256, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR
1153 { 255, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1154 { 254, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT
1155 { 253, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1156 { 252, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR
1157 { 251, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE
1158 { 250, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT
1159 { 249, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR
1160 { 248, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND
1161 { 247, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND
1162 { 246, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS
1163 { 245, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX
1164 { 244, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN
1165 { 243, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX
1166 { 242, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN
1167 { 241, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK
1168 { 240, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD
1169 { 239, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING
1170 { 238, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING
1171 { 237, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE
1172 { 236, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE
1173 { 235, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE
1174 { 234, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV
1175 { 233, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV
1176 { 232, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV
1177 { 231, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM
1178 { 230, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM
1179 { 229, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM
1180 { 228, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM
1181 { 227, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE
1182 { 226, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE
1183 { 225, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM
1184 { 224, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM
1185 { 223, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE
1186 { 222, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS
1187 { 221, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN
1188 { 220, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS
1189 { 219, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT
1190 { 218, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT
1191 { 217, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP
1192 { 216, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP
1193 { 215, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI
1194 { 214, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI
1195 { 213, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC
1196 { 212, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT
1197 { 211, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG
1198 { 210, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP
1199 { 209, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP
1200 { 208, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10
1201 { 207, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2
1202 { 206, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG
1203 { 205, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10
1204 { 204, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2
1205 { 203, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP
1206 { 202, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI
1207 { 201, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW
1208 { 200, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF
1209 { 199, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM
1210 { 198, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV
1211 { 197, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD
1212 { 196, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA
1213 { 195, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL
1214 { 194, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB
1215 { 193, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD
1216 { 192, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT
1217 { 191, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT
1218 { 190, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX
1219 { 189, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX
1220 { 188, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT
1221 { 187, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT
1222 { 186, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX
1223 { 185, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX
1224 { 184, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT
1225 { 183, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT
1226 { 182, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT
1227 { 181, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT
1228 { 180, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT
1229 { 179, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT
1230 { 178, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH
1231 { 177, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH
1232 { 176, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO
1233 { 175, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO
1234 { 174, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE
1235 { 173, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO
1236 { 172, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE
1237 { 171, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO
1238 { 170, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE
1239 { 169, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO
1240 { 168, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE
1241 { 167, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO
1242 { 166, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT
1243 { 165, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP
1244 { 164, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP
1245 { 163, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP
1246 { 162, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP
1247 { 161, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL
1248 { 160, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR
1249 { 159, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR
1250 { 158, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL
1251 { 157, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR
1252 { 156, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR
1253 { 155, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL
1254 { 154, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT
1255 { 153, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG
1256 { 152, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT
1257 { 151, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG
1258 { 150, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART
1259 { 149, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT
1260 { 148, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT
1261 { 147, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U
1262 { 146, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U
1263 { 145, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S
1264 { 144, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC
1265 { 143, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT
1266 { 142, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1267 { 141, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1268 { 140, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1269 { 139, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC
1270 { 138, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START
1271 { 137, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT
1272 { 136, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND
1273 { 135, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH
1274 { 134, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE
1275 { 133, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1276 { 132, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1277 { 131, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1278 { 130, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1279 { 129, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1280 { 128, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1281 { 127, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1282 { 126, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1283 { 125, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN
1284 { 124, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX
1285 { 123, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB
1286 { 122, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD
1287 { 121, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN
1288 { 120, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX
1289 { 119, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN
1290 { 118, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX
1291 { 117, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR
1292 { 116, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR
1293 { 115, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND
1294 { 114, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND
1295 { 113, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB
1296 { 112, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD
1297 { 111, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG
1298 { 110, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG
1299 { 109, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1300 { 108, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE
1301 { 107, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_FPTRUNCSTORE
1302 { 106, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE
1303 { 105, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1304 { 104, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD
1305 { 103, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD
1306 { 102, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_FPEXTLOAD
1307 { 101, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD
1308 { 100, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD
1309 { 99, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD
1310 { 98, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER
1311 { 97, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER
1312 { 96, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1313 { 95, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT
1314 { 94, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT
1315 { 93, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND
1316 { 92, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC
1317 { 91, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1318 { 90, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1319 { 89, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE
1320 { 88, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST
1321 { 87, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR
1322 { 86, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT
1323 { 85, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS
1324 { 84, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1325 { 83, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR
1326 { 82, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES
1327 { 81, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT
1328 { 80, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES
1329 { 79, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT
1330 { 78, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL
1331 { 77, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1332 { 76, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE
1333 { 75, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX
1334 { 74, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI
1335 { 73, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF
1336 { 72, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL
1337 { 71, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR
1338 { 70, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL
1339 { 69, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR
1340 { 68, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU
1341 { 67, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS
1342 { 66, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR
1343 { 65, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR
1344 { 64, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND
1345 { 63, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM
1346 { 62, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM
1347 { 61, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM
1348 { 60, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM
1349 { 59, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV
1350 { 58, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV
1351 { 57, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL
1352 { 56, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB
1353 { 55, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD
1354 { 54, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN
1355 { 53, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT
1356 { 52, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT
1357 { 51, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1358 { 50, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1359 { 49, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1360 { 48, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1361 { 47, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE
1362 { 46, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1363 { 45, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER
1364 { 44, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE
1365 { 43, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1366 { 42, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_13831
1367 { 41, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_13830
1368 { 40, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL
1369 { 39, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1370 { 38, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET
1371 { 37, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1372 { 36, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP
1373 { 35, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP
1374 { 34, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE
1375 { 33, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT
1376 { 32, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_13829
1377 { 31, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP
1378 { 30, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_13555
1379 { 29, 6, 1, 0, 0, 0, 0, R600OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT
1380 { 28, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL
1381 { 27, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP
1382 { 26, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE
1383 { 25, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE
1384 { 24, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END
1385 { 23, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START
1386 { 22, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE
1387 { 21, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK
1388 { 20, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY
1389 { 19, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE
1390 { 18, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL
1391 { 17, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI
1392 { 16, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF
1393 { 15, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST
1394 { 14, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE
1395 { 13, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS
1396 { 12, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG
1397 { 11, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF
1398 { 10, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF
1399 { 9, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG
1400 { 8, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG
1401 { 7, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL
1402 { 6, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL
1403 { 5, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL
1404 { 4, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL
1405 { 3, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION
1406 { 2, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR
1407 { 1, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM
1408 { 0, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI
1409 }, {
1410 /* 0 */
1411 }, {
1412 0
1413 }, {
1414 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1415 /* 1 */
1416 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1417 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1418 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1419 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1420 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1421 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1422 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1423 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1424 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1425 /* 28 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1426 /* 29 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1427 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1428 /* 34 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1429 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1430 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1431 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1432 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1433 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1434 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1435 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1436 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1437 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1438 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1439 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1440 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1441 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1442 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1443 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1444 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1445 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1446 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1447 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1448 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1449 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1450 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1451 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1452 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1453 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1454 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1455 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1456 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1457 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1458 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1459 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1460 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1461 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1462 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1463 /* 153 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1464 /* 155 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1465 /* 156 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1466 /* 158 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1467 /* 160 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1468 /* 231 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1469 /* 233 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1470 /* 237 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1471 /* 240 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1472 /* 243 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1473 /* 247 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1474 /* 251 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1475 /* 255 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1476 /* 262 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1477 /* 283 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1478 /* 297 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1479 /* 316 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1480 /* 325 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1481 /* 332 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1482 /* 341 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1483 /* 346 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1484 /* 351 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1485 /* 353 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1486 /* 362 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1487 /* 372 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1488 /* 379 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1489 /* 391 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1490 /* 404 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1491 /* 407 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1492 /* 409 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1493 /* 411 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1494 /* 413 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1495 /* 417 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1496 /* 420 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1497 /* 423 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1498 /* 426 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1499 /* 445 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1500 /* 449 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1501 /* 453 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1502 /* 457 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1503 }
1504};
1505
1506
1507#ifdef __GNUC__
1508#pragma GCC diagnostic push
1509#pragma GCC diagnostic ignored "-Woverlength-strings"
1510#endif
1511extern const char R600InstrNameData[] = {
1512 /* 0 */ "CF_TC_R600\000"
1513 /* 11 */ "CF_VC_R600\000"
1514 /* 22 */ "CF_END_R600\000"
1515 /* 34 */ "CF_ELSE_R600\000"
1516 /* 47 */ "CF_PUSH_ELSE_R600\000"
1517 /* 65 */ "CF_CONTINUE_R600\000"
1518 /* 82 */ "FNEG_R600\000"
1519 /* 92 */ "LOOP_BREAK_R600\000"
1520 /* 108 */ "CF_JUMP_R600\000"
1521 /* 121 */ "END_LOOP_R600\000"
1522 /* 135 */ "WHILE_LOOP_R600\000"
1523 /* 151 */ "POP_R600\000"
1524 /* 160 */ "FABS_R600\000"
1525 /* 170 */ "CF_CALL_FS_R600\000"
1526 /* 186 */ "DOT4_r600\000"
1527 /* 196 */ "MULADD_r600\000"
1528 /* 208 */ "LOG_CLAMPED_r600\000"
1529 /* 225 */ "RECIP_CLAMPED_r600\000"
1530 /* 244 */ "RECIPSQRT_CLAMPED_r600\000"
1531 /* 267 */ "CNDE_r600\000"
1532 /* 277 */ "MULADD_IEEE_r600\000"
1533 /* 294 */ "LOG_IEEE_r600\000"
1534 /* 308 */ "RECIP_IEEE_r600\000"
1535 /* 324 */ "EXP_IEEE_r600\000"
1536 /* 338 */ "RECIPSQRT_IEEE_r600\000"
1537 /* 358 */ "CNDGE_r600\000"
1538 /* 369 */ "LSHL_r600\000"
1539 /* 379 */ "SIN_r600\000"
1540 /* 388 */ "ASHR_r600\000"
1541 /* 398 */ "LSHR_r600\000"
1542 /* 408 */ "COS_r600\000"
1543 /* 417 */ "CNDGT_r600\000"
1544 /* 428 */ "MUL_LIT_r600\000"
1545 /* 441 */ "UINT_TO_FLT_r600\000"
1546 /* 458 */ "MULHI_UINT_r600\000"
1547 /* 474 */ "MULLO_UINT_r600\000"
1548 /* 490 */ "FLT_TO_UINT_r600\000"
1549 /* 507 */ "RECIP_UINT_r600\000"
1550 /* 523 */ "MULHI_INT_r600\000"
1551 /* 538 */ "MULLO_INT_r600\000"
1552 /* 553 */ "FLT_TO_INT_r600\000"
1553 /* 569 */ "SIN_r700\000"
1554 /* 578 */ "COS_r700\000"
1555 /* 587 */ "G_FLOG10\000"
1556 /* 596 */ "G_FEXP10\000"
1557 /* 605 */ "SETGE_DX10\000"
1558 /* 616 */ "SETNE_DX10\000"
1559 /* 627 */ "SETE_DX10\000"
1560 /* 637 */ "MIN_DX10\000"
1561 /* 646 */ "SETGT_DX10\000"
1562 /* 657 */ "MAX_DX10\000"
1563 /* 666 */ "INTERP_LOAD_P0\000"
1564 /* 681 */ "RAT_STORE_DWORD32\000"
1565 /* 699 */ "MOV_IMM_F32\000"
1566 /* 711 */ "MOV_IMM_I32\000"
1567 /* 723 */ "FLT16_TO_FLT32\000"
1568 /* 738 */ "CONTINUEC_f32\000"
1569 /* 752 */ "IFC_f32\000"
1570 /* 760 */ "BREAKC_f32\000"
1571 /* 771 */ "BRANCH_COND_f32\000"
1572 /* 787 */ "CONTINUE_LOGICALZ_f32\000"
1573 /* 809 */ "IF_LOGICALZ_f32\000"
1574 /* 825 */ "BREAK_LOGICALZ_f32\000"
1575 /* 844 */ "CONTINUE_LOGICALNZ_f32\000"
1576 /* 867 */ "IF_LOGICALNZ_f32\000"
1577 /* 884 */ "BREAK_LOGICALNZ_f32\000"
1578 /* 904 */ "CONTINUEC_i32\000"
1579 /* 918 */ "IFC_i32\000"
1580 /* 926 */ "BREAKC_i32\000"
1581 /* 937 */ "BRANCH_COND_i32\000"
1582 /* 953 */ "CONTINUE_LOGICALZ_i32\000"
1583 /* 975 */ "IF_LOGICALZ_i32\000"
1584 /* 991 */ "BREAK_LOGICALZ_i32\000"
1585 /* 1010 */ "CONTINUE_LOGICALNZ_i32\000"
1586 /* 1033 */ "IF_LOGICALNZ_i32\000"
1587 /* 1050 */ "BREAK_LOGICALNZ_i32\000"
1588 /* 1070 */ "G_FLOG2\000"
1589 /* 1078 */ "G_FATAN2\000"
1590 /* 1087 */ "G_FEXP2\000"
1591 /* 1095 */ "R600_EXTRACT_ELT_V2\000"
1592 /* 1115 */ "R600_INSERT_ELT_V2\000"
1593 /* 1134 */ "MULHI_UINT_cm24\000"
1594 /* 1150 */ "MULHI_INT_cm24\000"
1595 /* 1165 */ "RAT_STORE_DWORD64\000"
1596 /* 1183 */ "R600_EXTRACT_ELT_V4\000"
1597 /* 1203 */ "R600_INSERT_ELT_V4\000"
1598 /* 1222 */ "DOT_4\000"
1599 /* 1228 */ "FLT32_TO_FLT16\000"
1600 /* 1243 */ "RAT_STORE_DWORD128\000"
1601 /* 1262 */ "G_FMA\000"
1602 /* 1268 */ "G_STRICT_FMA\000"
1603 /* 1281 */ "TEX_SAMPLE_C_LB\000"
1604 /* 1297 */ "TEX_SAMPLE_LB\000"
1605 /* 1311 */ "G_FSUB\000"
1606 /* 1318 */ "G_STRICT_FSUB\000"
1607 /* 1332 */ "G_ATOMICRMW_FSUB\000"
1608 /* 1349 */ "G_SUB\000"
1609 /* 1355 */ "LDS_SUB\000"
1610 /* 1363 */ "G_ATOMICRMW_SUB\000"
1611 /* 1379 */ "G_INTRINSIC\000"
1612 /* 1391 */ "ENDFUNC\000"
1613 /* 1399 */ "G_FPTRUNC\000"
1614 /* 1409 */ "G_INTRINSIC_TRUNC\000"
1615 /* 1427 */ "G_TRUNC\000"
1616 /* 1435 */ "G_BUILD_VECTOR_TRUNC\000"
1617 /* 1456 */ "G_DYN_STACKALLOC\000"
1618 /* 1473 */ "TEX_SAMPLE_C\000"
1619 /* 1486 */ "G_FMAD\000"
1620 /* 1493 */ "G_FPEXTLOAD\000"
1621 /* 1505 */ "G_INDEXED_SEXTLOAD\000"
1622 /* 1524 */ "G_SEXTLOAD\000"
1623 /* 1535 */ "G_INDEXED_ZEXTLOAD\000"
1624 /* 1554 */ "G_ZEXTLOAD\000"
1625 /* 1565 */ "INTERP_VEC_LOAD\000"
1626 /* 1581 */ "G_INDEXED_LOAD\000"
1627 /* 1596 */ "G_LOAD\000"
1628 /* 1603 */ "PAD\000"
1629 /* 1607 */ "G_VECREDUCE_FADD\000"
1630 /* 1624 */ "G_FADD\000"
1631 /* 1631 */ "G_VECREDUCE_SEQ_FADD\000"
1632 /* 1652 */ "G_STRICT_FADD\000"
1633 /* 1666 */ "G_ATOMICRMW_FADD\000"
1634 /* 1683 */ "G_VECREDUCE_ADD\000"
1635 /* 1699 */ "G_ADD\000"
1636 /* 1705 */ "G_PTR_ADD\000"
1637 /* 1715 */ "LDS_ADD\000"
1638 /* 1723 */ "G_ATOMICRMW_ADD\000"
1639 /* 1739 */ "TEX_LD\000"
1640 /* 1746 */ "G_ATOMICRMW_NAND\000"
1641 /* 1763 */ "G_VECREDUCE_AND\000"
1642 /* 1779 */ "G_AND\000"
1643 /* 1785 */ "LDS_AND\000"
1644 /* 1793 */ "G_ATOMICRMW_AND\000"
1645 /* 1809 */ "LIFETIME_END\000"
1646 /* 1822 */ "G_BRCOND\000"
1647 /* 1831 */ "G_ATOMICRMW_USUB_COND\000"
1648 /* 1853 */ "JUMP_COND\000"
1649 /* 1863 */ "G_LLROUND\000"
1650 /* 1873 */ "G_LROUND\000"
1651 /* 1882 */ "G_INTRINSIC_ROUND\000"
1652 /* 1900 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1653 /* 1926 */ "LOAD_STACK_GUARD\000"
1654 /* 1943 */ "TXD\000"
1655 /* 1947 */ "PSEUDO_PROBE\000"
1656 /* 1960 */ "G_SSUBE\000"
1657 /* 1968 */ "G_USUBE\000"
1658 /* 1976 */ "G_FENCE\000"
1659 /* 1984 */ "ARITH_FENCE\000"
1660 /* 1996 */ "REG_SEQUENCE\000"
1661 /* 2009 */ "G_SADDE\000"
1662 /* 2017 */ "G_UADDE\000"
1663 /* 2025 */ "G_GET_FPMODE\000"
1664 /* 2038 */ "G_RESET_FPMODE\000"
1665 /* 2053 */ "G_SET_FPMODE\000"
1666 /* 2066 */ "MUL_IEEE\000"
1667 /* 2075 */ "G_FMINNUM_IEEE\000"
1668 /* 2090 */ "G_FMAXNUM_IEEE\000"
1669 /* 2105 */ "SGE\000"
1670 /* 2109 */ "PRED_SETGE\000"
1671 /* 2120 */ "G_VSCALE\000"
1672 /* 2129 */ "G_JUMP_TABLE\000"
1673 /* 2142 */ "BUNDLE\000"
1674 /* 2149 */ "TEX_SAMPLE\000"
1675 /* 2160 */ "RNDNE\000"
1676 /* 2166 */ "G_MEMSET_INLINE\000"
1677 /* 2182 */ "G_MEMCPY_INLINE\000"
1678 /* 2198 */ "RELOC_NONE\000"
1679 /* 2209 */ "SNE\000"
1680 /* 2213 */ "PRED_SETNE\000"
1681 /* 2224 */ "LOCAL_ESCAPE\000"
1682 /* 2237 */ "CF_ALU_PUSH_BEFORE\000"
1683 /* 2256 */ "G_FPTRUNCSTORE\000"
1684 /* 2271 */ "G_STACKRESTORE\000"
1685 /* 2286 */ "G_INDEXED_STORE\000"
1686 /* 2302 */ "G_STORE\000"
1687 /* 2310 */ "ELSE\000"
1688 /* 2315 */ "G_BITREVERSE\000"
1689 /* 2328 */ "FETCH_CLAUSE\000"
1690 /* 2341 */ "ALU_CLAUSE\000"
1691 /* 2352 */ "FAKE_USE\000"
1692 /* 2361 */ "PRED_SETE\000"
1693 /* 2371 */ "LDS_BYTE_WRITE\000"
1694 /* 2386 */ "MASK_WRITE\000"
1695 /* 2397 */ "LDS_WRITE\000"
1696 /* 2407 */ "LDS_SHORT_WRITE\000"
1697 /* 2423 */ "DBG_VALUE\000"
1698 /* 2433 */ "G_GLOBAL_VALUE\000"
1699 /* 2448 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1700 /* 2471 */ "CONVERGENCECTRL_GLUE\000"
1701 /* 2492 */ "CF_ALU_CONTINUE\000"
1702 /* 2508 */ "G_STACKSAVE\000"
1703 /* 2520 */ "G_MEMMOVE\000"
1704 /* 2530 */ "G_FREEZE\000"
1705 /* 2539 */ "G_FCANONICALIZE\000"
1706 /* 2555 */ "G_FMODF\000"
1707 /* 2563 */ "INIT_UNDEF\000"
1708 /* 2574 */ "G_IMPLICIT_DEF\000"
1709 /* 2589 */ "DBG_INSTR_REF\000"
1710 /* 2603 */ "ENDIF\000"
1711 /* 2609 */ "TEX_VTX_CONSTBUF\000"
1712 /* 2626 */ "TEX_VTX_TEXBUF\000"
1713 /* 2641 */ "G_FNEG\000"
1714 /* 2648 */ "EXTRACT_SUBREG\000"
1715 /* 2663 */ "INSERT_SUBREG\000"
1716 /* 2677 */ "G_SEXT_INREG\000"
1717 /* 2690 */ "SUBREG_TO_REG\000"
1718 /* 2704 */ "CF_TC_EG\000"
1719 /* 2713 */ "CF_VC_EG\000"
1720 /* 2722 */ "CF_END_EG\000"
1721 /* 2732 */ "CF_ELSE_EG\000"
1722 /* 2743 */ "CF_CONTINUE_EG\000"
1723 /* 2758 */ "CF_PUSH_EG\000"
1724 /* 2769 */ "LOOP_BREAK_EG\000"
1725 /* 2783 */ "CF_JUMP_EG\000"
1726 /* 2794 */ "END_LOOP_EG\000"
1727 /* 2806 */ "WHILE_LOOP_EG\000"
1728 /* 2820 */ "POP_EG\000"
1729 /* 2827 */ "CF_CALL_FS_EG\000"
1730 /* 2841 */ "G_ATOMIC_CMPXCHG\000"
1731 /* 2858 */ "LDS_WRXCHG\000"
1732 /* 2869 */ "G_ATOMICRMW_XCHG\000"
1733 /* 2886 */ "G_GET_ROUNDING\000"
1734 /* 2901 */ "G_SET_ROUNDING\000"
1735 /* 2916 */ "G_FLOG\000"
1736 /* 2923 */ "G_VAARG\000"
1737 /* 2931 */ "PREALLOCATED_ARG\000"
1738 /* 2948 */ "TEX_SAMPLE_C_G\000"
1739 /* 2963 */ "TEX_SAMPLE_G\000"
1740 /* 2976 */ "BRANCH\000"
1741 /* 2983 */ "G_PREFETCH\000"
1742 /* 2994 */ "ENDSWITCH\000"
1743 /* 3004 */ "G_SMULH\000"
1744 /* 3012 */ "G_UMULH\000"
1745 /* 3020 */ "G_FTANH\000"
1746 /* 3028 */ "G_FSINH\000"
1747 /* 3036 */ "G_FCOSH\000"
1748 /* 3044 */ "TEX_GET_GRADIENTS_H\000"
1749 /* 3064 */ "TEX_SET_GRADIENTS_H\000"
1750 /* 3084 */ "DBG_PHI\000"
1751 /* 3092 */ "G_FPTOSI\000"
1752 /* 3101 */ "G_FPTOUI\000"
1753 /* 3110 */ "G_FPOWI\000"
1754 /* 3118 */ "CF_ALU_BREAK\000"
1755 /* 3131 */ "COPY_LANEMASK\000"
1756 /* 3145 */ "G_PTRMASK\000"
1757 /* 3155 */ "GC_LABEL\000"
1758 /* 3164 */ "DBG_LABEL\000"
1759 /* 3174 */ "EH_LABEL\000"
1760 /* 3183 */ "ANNOTATION_LABEL\000"
1761 /* 3200 */ "ICALL_BRANCH_FUNNEL\000"
1762 /* 3220 */ "G_FSHL\000"
1763 /* 3227 */ "G_SHL\000"
1764 /* 3233 */ "G_FCEIL\000"
1765 /* 3241 */ "G_SAVGCEIL\000"
1766 /* 3252 */ "G_UAVGCEIL\000"
1767 /* 3263 */ "PATCHABLE_TAIL_CALL\000"
1768 /* 3283 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1769 /* 3310 */ "PATCHABLE_EVENT_CALL\000"
1770 /* 3331 */ "FENTRY_CALL\000"
1771 /* 3343 */ "KILL\000"
1772 /* 3348 */ "G_CONSTANT_POOL\000"
1773 /* 3364 */ "G_ROTL\000"
1774 /* 3371 */ "G_VECREDUCE_FMUL\000"
1775 /* 3388 */ "G_FMUL\000"
1776 /* 3395 */ "G_VECREDUCE_SEQ_FMUL\000"
1777 /* 3416 */ "G_STRICT_FMUL\000"
1778 /* 3430 */ "G_CLMUL\000"
1779 /* 3438 */ "G_VECREDUCE_MUL\000"
1780 /* 3454 */ "G_MUL\000"
1781 /* 3460 */ "TEX_SAMPLE_C_L\000"
1782 /* 3475 */ "TEX_SAMPLE_L\000"
1783 /* 3488 */ "CF_END_CM\000"
1784 /* 3498 */ "G_FREM\000"
1785 /* 3505 */ "G_STRICT_FREM\000"
1786 /* 3519 */ "G_SREM\000"
1787 /* 3526 */ "G_UREM\000"
1788 /* 3533 */ "G_SDIVREM\000"
1789 /* 3543 */ "G_UDIVREM\000"
1790 /* 3553 */ "INLINEASM\000"
1791 /* 3563 */ "G_VECREDUCE_FMINIMUM\000"
1792 /* 3584 */ "G_FMINIMUM\000"
1793 /* 3595 */ "G_ATOMICRMW_FMINIMUM\000"
1794 /* 3616 */ "G_VECREDUCE_FMAXIMUM\000"
1795 /* 3637 */ "G_FMAXIMUM\000"
1796 /* 3648 */ "G_ATOMICRMW_FMAXIMUM\000"
1797 /* 3669 */ "G_FMINIMUMNUM\000"
1798 /* 3683 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1799 /* 3707 */ "G_FMAXIMUMNUM\000"
1800 /* 3721 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1801 /* 3745 */ "G_FMINNUM\000"
1802 /* 3755 */ "G_FMAXNUM\000"
1803 /* 3765 */ "G_FATAN\000"
1804 /* 3773 */ "G_FTAN\000"
1805 /* 3780 */ "G_INTRINSIC_ROUNDEVEN\000"
1806 /* 3802 */ "G_ASSERT_ALIGN\000"
1807 /* 3817 */ "G_FCOPYSIGN\000"
1808 /* 3829 */ "DUMMY_CHAIN\000"
1809 /* 3841 */ "ENDMAIN\000"
1810 /* 3849 */ "G_VECREDUCE_FMIN\000"
1811 /* 3866 */ "G_ATOMICRMW_FMIN\000"
1812 /* 3883 */ "G_VECREDUCE_SMIN\000"
1813 /* 3900 */ "G_SMIN\000"
1814 /* 3907 */ "G_VECREDUCE_UMIN\000"
1815 /* 3924 */ "G_UMIN\000"
1816 /* 3931 */ "G_ATOMICRMW_UMIN\000"
1817 /* 3948 */ "G_ATOMICRMW_MIN\000"
1818 /* 3964 */ "G_FASIN\000"
1819 /* 3972 */ "G_FSIN\000"
1820 /* 3979 */ "CFI_INSTRUCTION\000"
1821 /* 3995 */ "G_CTLZ_ZERO_POISON\000"
1822 /* 4014 */ "G_CTTZ_ZERO_POISON\000"
1823 /* 4033 */ "RETURN\000"
1824 /* 4040 */ "RAT_ATOMIC_RSUB_RTN\000"
1825 /* 4060 */ "RAT_ATOMIC_SUB_RTN\000"
1826 /* 4079 */ "RAT_ATOMIC_ADD_RTN\000"
1827 /* 4098 */ "RAT_ATOMIC_AND_RTN\000"
1828 /* 4117 */ "RAT_ATOMIC_XOR_RTN\000"
1829 /* 4136 */ "RAT_ATOMIC_OR_RTN\000"
1830 /* 4154 */ "RAT_ATOMIC_DEC_UINT_RTN\000"
1831 /* 4178 */ "RAT_ATOMIC_INC_UINT_RTN\000"
1832 /* 4202 */ "RAT_ATOMIC_MIN_UINT_RTN\000"
1833 /* 4226 */ "RAT_ATOMIC_MAX_UINT_RTN\000"
1834 /* 4250 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\000"
1835 /* 4277 */ "RAT_ATOMIC_XCHG_INT_RTN\000"
1836 /* 4301 */ "RAT_ATOMIC_MIN_INT_RTN\000"
1837 /* 4324 */ "RAT_ATOMIC_MAX_INT_RTN\000"
1838 /* 4347 */ "RETDYN\000"
1839 /* 4354 */ "G_SSUBO\000"
1840 /* 4362 */ "G_USUBO\000"
1841 /* 4370 */ "G_SADDO\000"
1842 /* 4378 */ "G_UADDO\000"
1843 /* 4386 */ "TEX_GET_TEXTURE_RESINFO\000"
1844 /* 4410 */ "JUMP_TABLE_DEBUG_INFO\000"
1845 /* 4432 */ "G_SMULO\000"
1846 /* 4440 */ "G_UMULO\000"
1847 /* 4448 */ "G_BZERO\000"
1848 /* 4456 */ "STACKMAP\000"
1849 /* 4465 */ "G_DEBUGTRAP\000"
1850 /* 4477 */ "G_UBSANTRAP\000"
1851 /* 4489 */ "G_TRAP\000"
1852 /* 4496 */ "G_ATOMICRMW_UDEC_WRAP\000"
1853 /* 4518 */ "G_ATOMICRMW_UINC_WRAP\000"
1854 /* 4540 */ "G_BSWAP\000"
1855 /* 4548 */ "G_SITOFP\000"
1856 /* 4557 */ "G_UITOFP\000"
1857 /* 4566 */ "G_FCMP\000"
1858 /* 4573 */ "G_STRICT_FCMP\000"
1859 /* 4587 */ "G_ICMP\000"
1860 /* 4594 */ "G_SCMP\000"
1861 /* 4601 */ "G_UCMP\000"
1862 /* 4608 */ "JUMP\000"
1863 /* 4613 */ "ENDLOOP\000"
1864 /* 4621 */ "WHILELOOP\000"
1865 /* 4631 */ "CONVERGENCECTRL_LOOP\000"
1866 /* 4652 */ "G_CTPOP\000"
1867 /* 4660 */ "PATCHABLE_OP\000"
1868 /* 4673 */ "FAULTING_OP\000"
1869 /* 4685 */ "PREALLOCATED_SETUP\000"
1870 /* 4704 */ "G_FLDEXP\000"
1871 /* 4713 */ "G_STRICT_FLDEXP\000"
1872 /* 4729 */ "G_FEXP\000"
1873 /* 4736 */ "G_FFREXP\000"
1874 /* 4745 */ "G_BR\000"
1875 /* 4750 */ "INLINEASM_BR\000"
1876 /* 4763 */ "G_BLOCK_ADDR\000"
1877 /* 4776 */ "MOV_IMM_GLOBAL_ADDR\000"
1878 /* 4796 */ "MEMBARRIER\000"
1879 /* 4807 */ "G_CONSTANT_FOLD_BARRIER\000"
1880 /* 4831 */ "GROUP_BARRIER\000"
1881 /* 4845 */ "CF_ALU_ELSE_AFTER\000"
1882 /* 4863 */ "CF_ALU_POP_AFTER\000"
1883 /* 4880 */ "PATCHABLE_FUNCTION_ENTER\000"
1884 /* 4905 */ "G_READCYCLECOUNTER\000"
1885 /* 4924 */ "G_READSTEADYCOUNTER\000"
1886 /* 4944 */ "G_READ_REGISTER\000"
1887 /* 4960 */ "G_WRITE_REGISTER\000"
1888 /* 4977 */ "G_ASHR\000"
1889 /* 4984 */ "G_FSHR\000"
1890 /* 4991 */ "G_LSHR\000"
1891 /* 4998 */ "CONVERGENCECTRL_ANCHOR\000"
1892 /* 5021 */ "RAT_MSKOR\000"
1893 /* 5031 */ "G_FFLOOR\000"
1894 /* 5040 */ "G_SAVGFLOOR\000"
1895 /* 5052 */ "G_UAVGFLOOR\000"
1896 /* 5064 */ "G_EXTRACT_SUBVECTOR\000"
1897 /* 5084 */ "G_INSERT_SUBVECTOR\000"
1898 /* 5103 */ "G_BUILD_VECTOR\000"
1899 /* 5118 */ "G_SHUFFLE_VECTOR\000"
1900 /* 5135 */ "G_STEP_VECTOR\000"
1901 /* 5149 */ "G_SPLAT_VECTOR\000"
1902 /* 5164 */ "G_VECREDUCE_XOR\000"
1903 /* 5180 */ "G_XOR\000"
1904 /* 5186 */ "LDS_XOR\000"
1905 /* 5194 */ "G_ATOMICRMW_XOR\000"
1906 /* 5210 */ "G_VECREDUCE_OR\000"
1907 /* 5225 */ "G_OR\000"
1908 /* 5230 */ "LDS_OR\000"
1909 /* 5237 */ "G_ATOMICRMW_OR\000"
1910 /* 5252 */ "G_ROTR\000"
1911 /* 5259 */ "TEX_LDPTR\000"
1912 /* 5269 */ "G_INTTOPTR\000"
1913 /* 5280 */ "G_FABS\000"
1914 /* 5287 */ "G_ABS\000"
1915 /* 5293 */ "G_ABDS\000"
1916 /* 5300 */ "G_UNMERGE_VALUES\000"
1917 /* 5317 */ "G_MERGE_VALUES\000"
1918 /* 5332 */ "LITERALS\000"
1919 /* 5341 */ "G_CTLS\000"
1920 /* 5348 */ "G_FACOS\000"
1921 /* 5356 */ "G_FCOS\000"
1922 /* 5363 */ "G_FSINCOS\000"
1923 /* 5373 */ "G_STRICT_FCMPS\000"
1924 /* 5388 */ "G_CONCAT_VECTORS\000"
1925 /* 5405 */ "COPY_TO_REGCLASS\000"
1926 /* 5422 */ "G_IS_FPCLASS\000"
1927 /* 5435 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1928 /* 5465 */ "G_VECTOR_COMPRESS\000"
1929 /* 5483 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1930 /* 5510 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1931 /* 5548 */ "G_TRUNC_SSAT_S\000"
1932 /* 5563 */ "G_SSUBSAT\000"
1933 /* 5573 */ "G_USUBSAT\000"
1934 /* 5583 */ "G_SADDSAT\000"
1935 /* 5593 */ "G_UADDSAT\000"
1936 /* 5603 */ "G_SSHLSAT\000"
1937 /* 5613 */ "G_USHLSAT\000"
1938 /* 5623 */ "G_SMULFIXSAT\000"
1939 /* 5636 */ "G_UMULFIXSAT\000"
1940 /* 5649 */ "G_SDIVFIXSAT\000"
1941 /* 5662 */ "G_UDIVFIXSAT\000"
1942 /* 5675 */ "G_ATOMICRMW_USUB_SAT\000"
1943 /* 5696 */ "G_FPTOSI_SAT\000"
1944 /* 5709 */ "G_FPTOUI_SAT\000"
1945 /* 5722 */ "FRACT\000"
1946 /* 5728 */ "G_EXTRACT\000"
1947 /* 5738 */ "G_SELECT\000"
1948 /* 5747 */ "G_BRINDIRECT\000"
1949 /* 5760 */ "RAT_ATOMIC_RSUB_NORET\000"
1950 /* 5782 */ "RAT_ATOMIC_SUB_NORET\000"
1951 /* 5803 */ "RAT_ATOMIC_ADD_NORET\000"
1952 /* 5824 */ "RAT_ATOMIC_AND_NORET\000"
1953 /* 5845 */ "RAT_ATOMIC_XOR_NORET\000"
1954 /* 5866 */ "RAT_ATOMIC_OR_NORET\000"
1955 /* 5886 */ "RAT_ATOMIC_DEC_UINT_NORET\000"
1956 /* 5912 */ "RAT_ATOMIC_INC_UINT_NORET\000"
1957 /* 5938 */ "RAT_ATOMIC_MIN_UINT_NORET\000"
1958 /* 5964 */ "RAT_ATOMIC_MAX_UINT_NORET\000"
1959 /* 5990 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\000"
1960 /* 6019 */ "RAT_ATOMIC_XCHG_INT_NORET\000"
1961 /* 6045 */ "RAT_ATOMIC_MIN_INT_NORET\000"
1962 /* 6070 */ "RAT_ATOMIC_MAX_INT_NORET\000"
1963 /* 6095 */ "LDS_SUB_RET\000"
1964 /* 6107 */ "LDS_UBYTE_READ_RET\000"
1965 /* 6126 */ "LDS_BYTE_READ_RET\000"
1966 /* 6144 */ "LDS_READ_RET\000"
1967 /* 6157 */ "LDS_USHORT_READ_RET\000"
1968 /* 6177 */ "LDS_SHORT_READ_RET\000"
1969 /* 6196 */ "LDS_ADD_RET\000"
1970 /* 6208 */ "LDS_AND_RET\000"
1971 /* 6220 */ "PATCHABLE_RET\000"
1972 /* 6234 */ "LDS_WRXCHG_RET\000"
1973 /* 6249 */ "LDS_XOR_RET\000"
1974 /* 6261 */ "LDS_OR_RET\000"
1975 /* 6272 */ "LDS_MIN_UINT_RET\000"
1976 /* 6289 */ "LDS_MAX_UINT_RET\000"
1977 /* 6306 */ "LDS_MIN_INT_RET\000"
1978 /* 6322 */ "LDS_MAX_INT_RET\000"
1979 /* 6338 */ "LDS_CMPST_RET\000"
1980 /* 6352 */ "G_MEMSET\000"
1981 /* 6361 */ "IF_PREDICATE_SET\000"
1982 /* 6378 */ "KILLGT\000"
1983 /* 6385 */ "SGT\000"
1984 /* 6389 */ "PRED_SETGT\000"
1985 /* 6400 */ "PATCHABLE_FUNCTION_EXIT\000"
1986 /* 6424 */ "G_BRJT\000"
1987 /* 6431 */ "G_EXTRACT_VECTOR_ELT\000"
1988 /* 6452 */ "G_INSERT_VECTOR_ELT\000"
1989 /* 6472 */ "DEFAULT\000"
1990 /* 6480 */ "G_FCONSTANT\000"
1991 /* 6492 */ "G_CONSTANT\000"
1992 /* 6503 */ "G_INTRINSIC_CONVERGENT\000"
1993 /* 6526 */ "STATEPOINT\000"
1994 /* 6537 */ "PATCHPOINT\000"
1995 /* 6548 */ "G_PTRTOINT\000"
1996 /* 6559 */ "G_FRINT\000"
1997 /* 6567 */ "G_INTRINSIC_LLRINT\000"
1998 /* 6586 */ "G_INTRINSIC_LRINT\000"
1999 /* 6604 */ "SUBB_UINT\000"
2000 /* 6614 */ "ADDC_UINT\000"
2001 /* 6624 */ "SETGE_UINT\000"
2002 /* 6635 */ "FFBH_UINT\000"
2003 /* 6645 */ "LDS_MIN_UINT\000"
2004 /* 6658 */ "SETGT_UINT\000"
2005 /* 6669 */ "LDS_MAX_UINT\000"
2006 /* 6682 */ "G_FNEARBYINT\000"
2007 /* 6695 */ "SUB_INT\000"
2008 /* 6703 */ "ADD_INT\000"
2009 /* 6711 */ "AND_INT\000"
2010 /* 6719 */ "CNDE_INT\000"
2011 /* 6728 */ "CNDGE_INT\000"
2012 /* 6738 */ "PRED_SETGE_INT\000"
2013 /* 6753 */ "PRED_SETNE_INT\000"
2014 /* 6768 */ "PRED_SETE_INT\000"
2015 /* 6782 */ "FFBL_INT\000"
2016 /* 6791 */ "LDS_MIN_INT\000"
2017 /* 6803 */ "XOR_INT\000"
2018 /* 6811 */ "CNDGT_INT\000"
2019 /* 6821 */ "PRED_SETGT_INT\000"
2020 /* 6836 */ "BCNT_INT\000"
2021 /* 6845 */ "NOT_INT\000"
2022 /* 6853 */ "LDS_MAX_INT\000"
2023 /* 6865 */ "G_VASTART\000"
2024 /* 6875 */ "LIFETIME_START\000"
2025 /* 6890 */ "G_INVOKE_REGION_START\000"
2026 /* 6912 */ "G_INSERT\000"
2027 /* 6921 */ "G_FSQRT\000"
2028 /* 6929 */ "G_STRICT_FSQRT\000"
2029 /* 6944 */ "G_BITCAST\000"
2030 /* 6954 */ "G_ADDRSPACE_CAST\000"
2031 /* 6971 */ "DBG_VALUE_LIST\000"
2032 /* 6986 */ "LDS_CMPST\000"
2033 /* 6996 */ "G_FPEXT\000"
2034 /* 7004 */ "G_SEXT\000"
2035 /* 7011 */ "G_ASSERT_SEXT\000"
2036 /* 7025 */ "G_ANYEXT\000"
2037 /* 7034 */ "G_ZEXT\000"
2038 /* 7041 */ "G_ASSERT_ZEXT\000"
2039 /* 7055 */ "G_ABDU\000"
2040 /* 7062 */ "CF_ALU\000"
2041 /* 7069 */ "G_TRUNC_SSAT_U\000"
2042 /* 7084 */ "G_TRUNC_USAT_U\000"
2043 /* 7099 */ "G_FDIV\000"
2044 /* 7106 */ "G_STRICT_FDIV\000"
2045 /* 7120 */ "G_SDIV\000"
2046 /* 7127 */ "G_UDIV\000"
2047 /* 7134 */ "G_GET_FPENV\000"
2048 /* 7146 */ "G_RESET_FPENV\000"
2049 /* 7160 */ "G_SET_FPENV\000"
2050 /* 7172 */ "MOV\000"
2051 /* 7176 */ "TEX_GET_GRADIENTS_V\000"
2052 /* 7196 */ "TEX_SET_GRADIENTS_V\000"
2053 /* 7216 */ "TXD_SHADOW\000"
2054 /* 7227 */ "G_FPOW\000"
2055 /* 7234 */ "INTERP_ZW\000"
2056 /* 7244 */ "INTERP_PAIR_ZW\000"
2057 /* 7259 */ "G_VECREDUCE_FMAX\000"
2058 /* 7276 */ "G_ATOMICRMW_FMAX\000"
2059 /* 7293 */ "G_VECREDUCE_SMAX\000"
2060 /* 7310 */ "G_SMAX\000"
2061 /* 7317 */ "G_VECREDUCE_UMAX\000"
2062 /* 7334 */ "G_UMAX\000"
2063 /* 7341 */ "G_ATOMICRMW_UMAX\000"
2064 /* 7358 */ "G_ATOMICRMW_MAX\000"
2065 /* 7374 */ "G_FRAME_INDEX\000"
2066 /* 7388 */ "G_SBFX\000"
2067 /* 7395 */ "G_UBFX\000"
2068 /* 7402 */ "G_SMULFIX\000"
2069 /* 7412 */ "G_UMULFIX\000"
2070 /* 7422 */ "G_SDIVFIX\000"
2071 /* 7432 */ "G_UDIVFIX\000"
2072 /* 7442 */ "PRED_X\000"
2073 /* 7449 */ "G_MEMCPY\000"
2074 /* 7458 */ "CONST_COPY\000"
2075 /* 7469 */ "CONVERGENCECTRL_ENTRY\000"
2076 /* 7491 */ "INTERP_XY\000"
2077 /* 7501 */ "INTERP_PAIR_XY\000"
2078 /* 7516 */ "G_CTLZ\000"
2079 /* 7523 */ "G_CTTZ\000"
2080 /* 7530 */ "R600_RegisterLoad\000"
2081 /* 7548 */ "R600_RegisterStore\000"
2082 /* 7567 */ "R600_ExportBuf\000"
2083 /* 7582 */ "EG_ExportBuf\000"
2084 /* 7595 */ "VTX_READ_32_eg\000"
2085 /* 7610 */ "RAT_WRITE_CACHELESS_32_eg\000"
2086 /* 7636 */ "MULADD_UINT24_eg\000"
2087 /* 7653 */ "MULHI_UINT24_eg\000"
2088 /* 7669 */ "MUL_UINT24_eg\000"
2089 /* 7683 */ "VTX_READ_64_eg\000"
2090 /* 7698 */ "RAT_WRITE_CACHELESS_64_eg\000"
2091 /* 7724 */ "DOT4_eg\000"
2092 /* 7732 */ "VTX_READ_16_eg\000"
2093 /* 7747 */ "VTX_READ_128_eg\000"
2094 /* 7763 */ "RAT_WRITE_CACHELESS_128_eg\000"
2095 /* 7790 */ "VTX_READ_8_eg\000"
2096 /* 7804 */ "FMA_eg\000"
2097 /* 7811 */ "MULADD_eg\000"
2098 /* 7821 */ "LOG_CLAMPED_eg\000"
2099 /* 7836 */ "RECIP_CLAMPED_eg\000"
2100 /* 7853 */ "RECIPSQRT_CLAMPED_eg\000"
2101 /* 7874 */ "RAT_STORE_TYPED_eg\000"
2102 /* 7893 */ "CNDE_eg\000"
2103 /* 7901 */ "MULADD_IEEE_eg\000"
2104 /* 7916 */ "LOG_IEEE_eg\000"
2105 /* 7928 */ "RECIP_IEEE_eg\000"
2106 /* 7942 */ "EXP_IEEE_eg\000"
2107 /* 7954 */ "RECIPSQRT_IEEE_eg\000"
2108 /* 7972 */ "CNDGE_eg\000"
2109 /* 7981 */ "LSHL_eg\000"
2110 /* 7989 */ "SIN_eg\000"
2111 /* 7996 */ "ASHR_eg\000"
2112 /* 8004 */ "LSHR_eg\000"
2113 /* 8012 */ "COS_eg\000"
2114 /* 8019 */ "CNDGT_eg\000"
2115 /* 8028 */ "MUL_LIT_eg\000"
2116 /* 8039 */ "UINT_TO_FLT_eg\000"
2117 /* 8054 */ "BFE_UINT_eg\000"
2118 /* 8066 */ "MULHI_UINT_eg\000"
2119 /* 8080 */ "MULLO_UINT_eg\000"
2120 /* 8094 */ "FLT_TO_UINT_eg\000"
2121 /* 8109 */ "RECIP_UINT_eg\000"
2122 /* 8123 */ "MOVA_INT_eg\000"
2123 /* 8135 */ "BFE_INT_eg\000"
2124 /* 8146 */ "BFI_INT_eg\000"
2125 /* 8157 */ "MULHI_INT_eg\000"
2126 /* 8170 */ "BFM_INT_eg\000"
2127 /* 8181 */ "BIT_ALIGN_INT_eg\000"
2128 /* 8198 */ "MULLO_INT_eg\000"
2129 /* 8211 */ "FLT_TO_INT_eg\000"
2130 /* 8225 */ "CUBE_r600_real\000"
2131 /* 8240 */ "CUBE_eg_real\000"
2132 /* 8253 */ "VTX_READ_32_cm\000"
2133 /* 8268 */ "MULADD_INT24_cm\000"
2134 /* 8284 */ "MUL_INT24_cm\000"
2135 /* 8297 */ "VTX_READ_64_cm\000"
2136 /* 8312 */ "VTX_READ_16_cm\000"
2137 /* 8327 */ "VTX_READ_128_cm\000"
2138 /* 8343 */ "VTX_READ_8_cm\000"
2139 /* 8357 */ "RECIP_CLAMPED_cm\000"
2140 /* 8374 */ "RECIPSQRT_CLAMPED_cm\000"
2141 /* 8395 */ "RAT_STORE_TYPED_cm\000"
2142 /* 8414 */ "LOG_IEEE_cm\000"
2143 /* 8426 */ "RECIP_IEEE_cm\000"
2144 /* 8440 */ "EXP_IEEE_cm\000"
2145 /* 8452 */ "RECIPSQRT_IEEE_cm\000"
2146 /* 8470 */ "SIN_cm\000"
2147 /* 8477 */ "COS_cm\000"
2148 /* 8484 */ "MULHI_UINT_cm\000"
2149 /* 8498 */ "MULLO_UINT_cm\000"
2150 /* 8512 */ "MULHI_INT_cm\000"
2151 /* 8525 */ "MULLO_INT_cm\000"
2152 /* 8538 */ "CUBE_r600_pseudo\000"
2153 /* 8555 */ "CUBE_eg_pseudo\000"
2154 /* 8570 */ "R600_ExportSwz\000"
2155 /* 8585 */ "EG_ExportSwz\000"
2156};
2157#ifdef __GNUC__
2158#pragma GCC diagnostic pop
2159#endif
2160
2161extern const unsigned R600InstrNameIndices[] = {
2162 3088U, 3553U, 4750U, 3979U, 3174U, 3155U, 3183U, 3343U,
2163 2648U, 2663U, 2576U, 2563U, 2690U, 5405U, 2423U, 6971U,
2164 2589U, 3084U, 3164U, 1996U, 7464U, 3131U, 2142U, 6875U,
2165 1809U, 1947U, 1984U, 4456U, 3331U, 6537U, 1926U, 4685U,
2166 2931U, 6526U, 2224U, 4673U, 4660U, 4880U, 6220U, 6400U,
2167 3263U, 3310U, 3283U, 3200U, 2352U, 4796U, 4410U, 2198U,
2168 7469U, 4998U, 4631U, 2471U, 7011U, 7041U, 3802U, 1699U,
2169 1349U, 3454U, 7120U, 7127U, 3519U, 3526U, 3533U, 3543U,
2170 1779U, 5225U, 5180U, 5293U, 7055U, 5052U, 3252U, 5040U,
2171 3241U, 2574U, 3086U, 7374U, 2433U, 2448U, 3348U, 5728U,
2172 5300U, 6912U, 5317U, 5103U, 1435U, 5388U, 6548U, 5269U,
2173 6944U, 2530U, 4807U, 1900U, 1409U, 1882U, 6586U, 6567U,
2174 3780U, 4905U, 4924U, 1596U, 1524U, 1554U, 1493U, 1581U,
2175 1505U, 1535U, 2302U, 2256U, 2286U, 5435U, 2841U, 2869U,
2176 1723U, 1363U, 1793U, 1746U, 5237U, 5194U, 7358U, 3948U,
2177 7341U, 3931U, 1666U, 1332U, 7276U, 3866U, 3648U, 3595U,
2178 3721U, 3683U, 4518U, 4496U, 1831U, 5675U, 1976U, 2983U,
2179 1822U, 5747U, 6890U, 1379U, 5483U, 6503U, 5510U, 7025U,
2180 1427U, 5548U, 7069U, 7084U, 6492U, 6480U, 6865U, 2923U,
2181 7004U, 2677U, 7034U, 3227U, 4991U, 4977U, 3220U, 4984U,
2182 5252U, 3364U, 4587U, 4566U, 4594U, 4601U, 5738U, 4378U,
2183 2017U, 4362U, 1968U, 4370U, 2009U, 4354U, 1960U, 4440U,
2184 4432U, 3012U, 3004U, 5593U, 5583U, 5573U, 5563U, 5613U,
2185 5603U, 7402U, 7412U, 5623U, 5636U, 7422U, 7432U, 5649U,
2186 5662U, 1624U, 1311U, 3388U, 1262U, 1486U, 7099U, 3498U,
2187 2555U, 7227U, 3110U, 4729U, 1087U, 596U, 2916U, 1070U,
2188 587U, 4704U, 4736U, 2641U, 6996U, 1399U, 3092U, 3101U,
2189 4548U, 4557U, 5696U, 5709U, 5280U, 3817U, 5422U, 2539U,
2190 3745U, 3755U, 2075U, 2090U, 3584U, 3637U, 3669U, 3707U,
2191 7134U, 7160U, 7146U, 2025U, 2053U, 2038U, 2886U, 2901U,
2192 1705U, 3145U, 3900U, 7310U, 3924U, 7334U, 5287U, 1873U,
2193 1863U, 4745U, 6424U, 2120U, 5084U, 5064U, 6452U, 6431U,
2194 5118U, 5149U, 5135U, 5465U, 7523U, 4014U, 7516U, 3995U,
2195 5341U, 4652U, 4540U, 2315U, 3430U, 3233U, 5356U, 3972U,
2196 5363U, 3773U, 5348U, 3964U, 3765U, 1078U, 3036U, 3028U,
2197 3020U, 6921U, 5031U, 6559U, 6682U, 6954U, 4763U, 2129U,
2198 1456U, 2508U, 2271U, 1652U, 1318U, 3416U, 7106U, 3505U,
2199 1268U, 6929U, 4713U, 4573U, 5373U, 4944U, 4960U, 7449U,
2200 2182U, 2520U, 6352U, 4448U, 2166U, 4489U, 4465U, 4477U,
2201 1631U, 3395U, 1607U, 3371U, 7259U, 3849U, 3616U, 3563U,
2202 1683U, 3438U, 1763U, 5210U, 5164U, 7293U, 3883U, 7317U,
2203 3907U, 7388U, 7395U, 2976U, 771U, 937U, 3125U, 760U,
2204 926U, 884U, 1050U, 825U, 991U, 7458U, 2499U, 738U,
2205 904U, 844U, 1010U, 787U, 953U, 8555U, 8538U, 6472U,
2206 1222U, 3829U, 2310U, 1818U, 1391U, 2603U, 4613U, 3841U,
2207 2994U, 160U, 82U, 1394U, 752U, 918U, 867U, 1033U,
2208 809U, 975U, 6361U, 4608U, 1853U, 2386U, 699U, 4776U,
2209 711U, 7442U, 1095U, 1183U, 1115U, 1203U, 7530U, 7548U,
2210 4347U, 4033U, 1943U, 7216U, 4621U, 1620U, 6614U, 6703U,
2211 2341U, 6711U, 7996U, 388U, 6836U, 8135U, 8054U, 8146U,
2212 8170U, 8181U, 3236U, 7062U, 3118U, 2492U, 4845U, 4863U,
2213 2237U, 2827U, 170U, 2743U, 65U, 2732U, 34U, 3488U,
2214 2722U, 22U, 2783U, 108U, 2758U, 47U, 2704U, 0U,
2215 2713U, 11U, 6719U, 7893U, 267U, 6728U, 7972U, 358U,
2216 6811U, 8019U, 417U, 8477U, 8012U, 408U, 578U, 8240U,
2217 8225U, 7724U, 186U, 7582U, 8585U, 2794U, 121U, 8440U,
2218 7942U, 324U, 2328U, 6635U, 6782U, 5034U, 723U, 1228U,
2219 8211U, 553U, 8094U, 490U, 7804U, 5722U, 4831U, 666U,
2220 7501U, 7244U, 1565U, 7491U, 7234U, 8040U, 442U, 6378U,
2221 1715U, 6196U, 1785U, 6208U, 6126U, 2371U, 6986U, 6338U,
2222 6853U, 6322U, 6669U, 6289U, 6791U, 6306U, 6645U, 6272U,
2223 5230U, 6261U, 6144U, 6177U, 2407U, 1355U, 6095U, 6107U,
2224 6157U, 2397U, 2858U, 6234U, 5186U, 6249U, 5332U, 7821U,
2225 208U, 8414U, 7916U, 294U, 2769U, 92U, 7981U, 369U,
2226 8004U, 398U, 7272U, 657U, 6857U, 6673U, 3862U, 637U,
2227 6795U, 6649U, 7172U, 8123U, 3384U, 7901U, 277U, 8268U,
2228 7636U, 7811U, 196U, 8512U, 1150U, 8157U, 523U, 7653U,
2229 8484U, 1134U, 8066U, 458U, 8525U, 8198U, 538U, 8498U,
2230 8080U, 474U, 2066U, 8284U, 8028U, 428U, 7669U, 6845U,
2231 6804U, 1603U, 2820U, 151U, 2361U, 6768U, 2109U, 6738U,
2232 6389U, 6821U, 2213U, 6753U, 7567U, 8570U, 5803U, 4079U,
2233 5824U, 4098U, 5990U, 4250U, 5886U, 4154U, 5912U, 4178U,
2234 6070U, 4324U, 5964U, 4226U, 6045U, 4301U, 5938U, 4202U,
2235 5866U, 4136U, 5760U, 4040U, 5782U, 4060U, 6019U, 4277U,
2236 5845U, 4117U, 5021U, 1243U, 681U, 1165U, 8395U, 7874U,
2237 7763U, 7610U, 7698U, 8374U, 7853U, 244U, 8452U, 7954U,
2238 338U, 8357U, 7836U, 225U, 8426U, 7928U, 308U, 8109U,
2239 507U, 2160U, 2366U, 627U, 6773U, 605U, 6743U, 6624U,
2240 646U, 6826U, 6658U, 616U, 6758U, 2105U, 6385U, 8470U,
2241 7989U, 379U, 569U, 2209U, 6604U, 6695U, 3044U, 7176U,
2242 4386U, 1739U, 5259U, 2149U, 1473U, 2948U, 3460U, 1281U,
2243 2963U, 3475U, 1297U, 3064U, 7196U, 2609U, 2626U, 1403U,
2244 8039U, 441U, 8327U, 7747U, 8312U, 7732U, 8253U, 7595U,
2245 8297U, 7683U, 8343U, 7790U, 2806U, 135U, 6803U,
2246};
2247
2248static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
2249 II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 671, nullptr, 0);
2250}
2251
2252
2253} // namespace llvm
2254
2255#endif // GET_INSTRINFO_MC_DESC
2256
2257#ifdef GET_INSTRINFO_HEADER
2258#undef GET_INSTRINFO_HEADER
2259
2260namespace llvm {
2261
2262struct R600GenInstrInfo : public TargetInstrInfo {
2263 explicit R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2264 ~R600GenInstrInfo() override = default;
2265};
2266
2267} // namespace llvm
2268
2269namespace llvm::R600 {
2270
2271constexpr unsigned SUBOP_FRAMEri_ptr = 0;
2272constexpr unsigned SUBOP_FRAMEri_index = 1;
2273constexpr unsigned SUBOP_MEMrr_ptr = 0;
2274constexpr unsigned SUBOP_MEMrr_index = 1;
2275constexpr unsigned SUBOP_MEMxi_ptr = 0;
2276constexpr unsigned SUBOP_MEMxi_index = 1;
2277
2278} // namespace llvm::R600
2279
2280#endif // GET_INSTRINFO_HEADER
2281
2282#ifdef GET_INSTRINFO_HELPER_DECLS
2283#undef GET_INSTRINFO_HELPER_DECLS
2284
2285
2286#endif // GET_INSTRINFO_HELPER_DECLS
2287
2288#ifdef GET_INSTRINFO_HELPERS
2289#undef GET_INSTRINFO_HELPERS
2290
2291
2292#endif // GET_INSTRINFO_HELPERS
2293
2294#ifdef GET_INSTRINFO_CTOR_DTOR
2295#undef GET_INSTRINFO_CTOR_DTOR
2296
2297namespace llvm {
2298
2299extern const R600InstrTable R600Descs;
2300extern const unsigned R600InstrNameIndices[];
2301extern const char R600InstrNameData[];
2302R600GenInstrInfo::R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2303 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2304 InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 671);
2305}
2306
2307} // namespace llvm
2308
2309#endif // GET_INSTRINFO_CTOR_DTOR
2310
2311#ifdef GET_INSTRINFO_OPERAND_ENUM
2312#undef GET_INSTRINFO_OPERAND_ENUM
2313
2314namespace llvm::R600 {
2315
2316enum class OpName : uint8_t {
2317 dst = 0,
2318 src0 = 1,
2319 update_exec_mask_X = 2,
2320 update_pred_X = 3,
2321 write_X = 4,
2322 omod_X = 5,
2323 dst_rel_X = 6,
2324 clamp_X = 7,
2325 src0_X = 8,
2326 src0_neg_X = 9,
2327 src0_rel_X = 10,
2328 src0_abs_X = 11,
2329 src0_sel_X = 12,
2330 src1_X = 13,
2331 src1_neg_X = 14,
2332 src1_rel_X = 15,
2333 src1_abs_X = 16,
2334 src1_sel_X = 17,
2335 pred_sel_X = 18,
2336 update_exec_mask_Y = 19,
2337 update_pred_Y = 20,
2338 write_Y = 21,
2339 omod_Y = 22,
2340 dst_rel_Y = 23,
2341 clamp_Y = 24,
2342 src0_Y = 25,
2343 src0_neg_Y = 26,
2344 src0_rel_Y = 27,
2345 src0_abs_Y = 28,
2346 src0_sel_Y = 29,
2347 src1_Y = 30,
2348 src1_neg_Y = 31,
2349 src1_rel_Y = 32,
2350 src1_abs_Y = 33,
2351 src1_sel_Y = 34,
2352 pred_sel_Y = 35,
2353 update_exec_mask_Z = 36,
2354 update_pred_Z = 37,
2355 write_Z = 38,
2356 omod_Z = 39,
2357 dst_rel_Z = 40,
2358 clamp_Z = 41,
2359 src0_Z = 42,
2360 src0_neg_Z = 43,
2361 src0_rel_Z = 44,
2362 src0_abs_Z = 45,
2363 src0_sel_Z = 46,
2364 src1_Z = 47,
2365 src1_neg_Z = 48,
2366 src1_rel_Z = 49,
2367 src1_abs_Z = 50,
2368 src1_sel_Z = 51,
2369 pred_sel_Z = 52,
2370 update_exec_mask_W = 53,
2371 update_pred_W = 54,
2372 write_W = 55,
2373 omod_W = 56,
2374 dst_rel_W = 57,
2375 clamp_W = 58,
2376 src0_W = 59,
2377 src0_neg_W = 60,
2378 src0_rel_W = 61,
2379 src0_abs_W = 62,
2380 src0_sel_W = 63,
2381 src1_W = 64,
2382 src1_neg_W = 65,
2383 src1_rel_W = 66,
2384 src1_abs_W = 67,
2385 src1_sel_W = 68,
2386 pred_sel_W = 69,
2387 literal0 = 70,
2388 literal1 = 71,
2389 addr = 72,
2390 chan = 73,
2391 val = 74,
2392 update_exec_mask = 75,
2393 update_pred = 76,
2394 write = 77,
2395 omod = 78,
2396 dst_rel = 79,
2397 clamp = 80,
2398 src0_neg = 81,
2399 src0_rel = 82,
2400 src0_abs = 83,
2401 src0_sel = 84,
2402 src1 = 85,
2403 src1_neg = 86,
2404 src1_rel = 87,
2405 src1_abs = 88,
2406 src1_sel = 89,
2407 last = 90,
2408 pred_sel = 91,
2409 literal = 92,
2410 bank_swizzle = 93,
2411 src2 = 94,
2412 src2_neg = 95,
2413 src2_rel = 96,
2414 src2_sel = 97,
2415 ADDR = 98,
2416 KCACHE_BANK0 = 99,
2417 KCACHE_BANK1 = 100,
2418 KCACHE_MODE0 = 101,
2419 KCACHE_MODE1 = 102,
2420 KCACHE_ADDR0 = 103,
2421 KCACHE_ADDR1 = 104,
2422 COUNT = 105,
2423 Enabled = 106,
2424 NUM_OPERAND_NAMES = 107,
2425}; // enum class OpName
2426
2427LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name);
2428LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx);
2429
2430} // namespace llvm::R600
2431
2432#endif // GET_INSTRINFO_OPERAND_ENUM
2433
2434#ifdef GET_INSTRINFO_NAMED_OPS
2435#undef GET_INSTRINFO_NAMED_OPS
2436
2437namespace llvm::R600 {
2438
2439LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) {
2440 static constexpr uint8_t InstructionIndex[] = {
2441 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2442 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2443 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2444 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2446 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2447 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2448 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2450 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2451 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2455 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
2463 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 4,
2465 0, 0, 0, 0, 0, 5, 5, 5, 0, 5, 5, 5, 6, 7, 7, 7,
2466 5, 7, 6, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0,
2467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 7, 7, 7, 7,
2468 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 0, 0, 0, 0, 6,
2469 6, 6, 0, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 6, 0, 6,
2470 0, 0, 0, 5, 5, 6, 6, 5, 9, 10, 9, 10, 11, 9, 12, 13,
2471 9, 10, 9, 10, 9, 10, 9, 10, 9, 10, 11, 11, 9, 9, 10, 11,
2472 11, 9, 9, 10, 9, 10, 0, 6, 6, 6, 6, 6, 0, 0, 5, 5,
2473 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 5, 7, 7, 7,
2474 7, 7, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
2475 5, 5, 5, 5, 7, 7, 5, 6, 5, 0, 0, 0, 5, 5, 5, 5,
2476 5, 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2478 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6, 6, 6, 6,
2479 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5,
2480 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 5, 5, 5, 0, 0,
2481 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6,
2482 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5,
2483 };
2484 return InstructionIndex[Opcode];
2485}
2486LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) {
2487 assert(Name != OpName::NUM_OPERAND_NAMES);
2488 static constexpr int8_t OperandMap[][107] = {
2489 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2490 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2491 {0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2492 {0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2493 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2494 {0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2495 {0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2496 {0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2497 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
2498 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2499 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2500 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2501 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2502 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2503 };
2504 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2505 return OperandMap[InstrIdx][(unsigned)Name];
2506}
2507LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) {
2508 assert(Idx >= 0 && Idx < 71);
2509 static constexpr OpName OperandMap[][71] = {
2510 {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2511 {OpName::dst, OpName::src0, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2512 {OpName::dst, OpName::update_exec_mask_X, OpName::update_pred_X, OpName::write_X, OpName::omod_X, OpName::dst_rel_X, OpName::clamp_X, OpName::src0_X, OpName::src0_neg_X, OpName::src0_rel_X, OpName::src0_abs_X, OpName::src0_sel_X, OpName::src1_X, OpName::src1_neg_X, OpName::src1_rel_X, OpName::src1_abs_X, OpName::src1_sel_X, OpName::pred_sel_X, OpName::update_exec_mask_Y, OpName::update_pred_Y, OpName::write_Y, OpName::omod_Y, OpName::dst_rel_Y, OpName::clamp_Y, OpName::src0_Y, OpName::src0_neg_Y, OpName::src0_rel_Y, OpName::src0_abs_Y, OpName::src0_sel_Y, OpName::src1_Y, OpName::src1_neg_Y, OpName::src1_rel_Y, OpName::src1_abs_Y, OpName::src1_sel_Y, OpName::pred_sel_Y, OpName::update_exec_mask_Z, OpName::update_pred_Z, OpName::write_Z, OpName::omod_Z, OpName::dst_rel_Z, OpName::clamp_Z, OpName::src0_Z, OpName::src0_neg_Z, OpName::src0_rel_Z, OpName::src0_abs_Z, OpName::src0_sel_Z, OpName::src1_Z, OpName::src1_neg_Z, OpName::src1_rel_Z, OpName::src1_abs_Z, OpName::src1_sel_Z, OpName::pred_sel_Z, OpName::update_exec_mask_W, OpName::update_pred_W, OpName::write_W, OpName::omod_W, OpName::dst_rel_W, OpName::clamp_W, OpName::src0_W, OpName::src0_neg_W, OpName::src0_rel_W, OpName::src0_abs_W, OpName::src0_sel_W, OpName::src1_W, OpName::src1_neg_W, OpName::src1_rel_W, OpName::src1_abs_W, OpName::src1_sel_W, OpName::pred_sel_W, OpName::literal0, OpName::literal1, },
2513 {OpName::dst, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2514 {OpName::val, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2515 {OpName::dst, OpName::update_exec_mask, OpName::update_pred, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_abs, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2516 {OpName::dst, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2517 {OpName::dst, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_neg, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2518 {OpName::ADDR, OpName::KCACHE_BANK0, OpName::KCACHE_BANK1, OpName::KCACHE_MODE0, OpName::KCACHE_MODE1, OpName::KCACHE_ADDR0, OpName::KCACHE_ADDR1, OpName::COUNT, OpName::Enabled, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2519 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2520 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2521 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2522 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2523 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2524 };
2525 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2526 return OperandMap[InstrIdx][(unsigned)Idx];
2527}
2528
2529} // namespace llvm::R600
2530
2531#endif // GET_INSTRINFO_NAMED_OPS
2532
2533#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2534#undef GET_INSTRINFO_MC_HELPER_DECLS
2535
2536namespace llvm {
2537
2538class MCInst;
2539class FeatureBitset;
2540
2541namespace R600_MC {
2542
2543void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2544
2545} // namespace R600_MC
2546
2547} // namespace llvm
2548
2549#endif // GET_INSTRINFO_MC_HELPER_DECLS
2550
2551#ifdef GET_INSTRINFO_MC_HELPERS
2552#undef GET_INSTRINFO_MC_HELPERS
2553
2554namespace llvm::R600_MC {
2555
2556
2557} // namespace llvm::R600_MC
2558
2559#endif // GET_INSTRINFO_MC_HELPERS
2560
2561#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2562 defined(GET_AVAILABLE_OPCODE_CHECKER)
2563#define GET_COMPUTE_FEATURES
2564#endif
2565#ifdef GET_COMPUTE_FEATURES
2566#undef GET_COMPUTE_FEATURES
2567
2568namespace llvm::R600_MC {
2569
2570// Bits for subtarget features that participate in instruction matching.
2571enum SubtargetFeatureBits : uint8_t {
2572};
2573
2574inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2575 FeatureBitset Features;
2576 return Features;
2577}
2578
2579inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2580 enum : uint8_t {
2581 CEFBS_None,
2582 };
2583
2584 static constexpr FeatureBitset FeatureBitsets[] = {
2585 {}, // CEFBS_None
2586 };
2587 static constexpr uint8_t RequiredFeaturesRefs[] = {
2588 CEFBS_None, // PHI
2589 CEFBS_None, // INLINEASM
2590 CEFBS_None, // INLINEASM_BR
2591 CEFBS_None, // CFI_INSTRUCTION
2592 CEFBS_None, // EH_LABEL
2593 CEFBS_None, // GC_LABEL
2594 CEFBS_None, // ANNOTATION_LABEL
2595 CEFBS_None, // KILL
2596 CEFBS_None, // EXTRACT_SUBREG
2597 CEFBS_None, // INSERT_SUBREG
2598 CEFBS_None, // IMPLICIT_DEF
2599 CEFBS_None, // INIT_UNDEF
2600 CEFBS_None, // SUBREG_TO_REG
2601 CEFBS_None, // COPY_TO_REGCLASS
2602 CEFBS_None, // DBG_VALUE
2603 CEFBS_None, // DBG_VALUE_LIST
2604 CEFBS_None, // DBG_INSTR_REF
2605 CEFBS_None, // DBG_PHI
2606 CEFBS_None, // DBG_LABEL
2607 CEFBS_None, // REG_SEQUENCE
2608 CEFBS_None, // COPY
2609 CEFBS_None, // COPY_LANEMASK
2610 CEFBS_None, // BUNDLE
2611 CEFBS_None, // LIFETIME_START
2612 CEFBS_None, // LIFETIME_END
2613 CEFBS_None, // PSEUDO_PROBE
2614 CEFBS_None, // ARITH_FENCE
2615 CEFBS_None, // STACKMAP
2616 CEFBS_None, // FENTRY_CALL
2617 CEFBS_None, // PATCHPOINT
2618 CEFBS_None, // LOAD_STACK_GUARD
2619 CEFBS_None, // PREALLOCATED_SETUP
2620 CEFBS_None, // PREALLOCATED_ARG
2621 CEFBS_None, // STATEPOINT
2622 CEFBS_None, // LOCAL_ESCAPE
2623 CEFBS_None, // FAULTING_OP
2624 CEFBS_None, // PATCHABLE_OP
2625 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2626 CEFBS_None, // PATCHABLE_RET
2627 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2628 CEFBS_None, // PATCHABLE_TAIL_CALL
2629 CEFBS_None, // PATCHABLE_EVENT_CALL
2630 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2631 CEFBS_None, // ICALL_BRANCH_FUNNEL
2632 CEFBS_None, // FAKE_USE
2633 CEFBS_None, // MEMBARRIER
2634 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2635 CEFBS_None, // RELOC_NONE
2636 CEFBS_None, // CONVERGENCECTRL_ENTRY
2637 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2638 CEFBS_None, // CONVERGENCECTRL_LOOP
2639 CEFBS_None, // CONVERGENCECTRL_GLUE
2640 CEFBS_None, // G_ASSERT_SEXT
2641 CEFBS_None, // G_ASSERT_ZEXT
2642 CEFBS_None, // G_ASSERT_ALIGN
2643 CEFBS_None, // G_ADD
2644 CEFBS_None, // G_SUB
2645 CEFBS_None, // G_MUL
2646 CEFBS_None, // G_SDIV
2647 CEFBS_None, // G_UDIV
2648 CEFBS_None, // G_SREM
2649 CEFBS_None, // G_UREM
2650 CEFBS_None, // G_SDIVREM
2651 CEFBS_None, // G_UDIVREM
2652 CEFBS_None, // G_AND
2653 CEFBS_None, // G_OR
2654 CEFBS_None, // G_XOR
2655 CEFBS_None, // G_ABDS
2656 CEFBS_None, // G_ABDU
2657 CEFBS_None, // G_UAVGFLOOR
2658 CEFBS_None, // G_UAVGCEIL
2659 CEFBS_None, // G_SAVGFLOOR
2660 CEFBS_None, // G_SAVGCEIL
2661 CEFBS_None, // G_IMPLICIT_DEF
2662 CEFBS_None, // G_PHI
2663 CEFBS_None, // G_FRAME_INDEX
2664 CEFBS_None, // G_GLOBAL_VALUE
2665 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2666 CEFBS_None, // G_CONSTANT_POOL
2667 CEFBS_None, // G_EXTRACT
2668 CEFBS_None, // G_UNMERGE_VALUES
2669 CEFBS_None, // G_INSERT
2670 CEFBS_None, // G_MERGE_VALUES
2671 CEFBS_None, // G_BUILD_VECTOR
2672 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2673 CEFBS_None, // G_CONCAT_VECTORS
2674 CEFBS_None, // G_PTRTOINT
2675 CEFBS_None, // G_INTTOPTR
2676 CEFBS_None, // G_BITCAST
2677 CEFBS_None, // G_FREEZE
2678 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2679 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2680 CEFBS_None, // G_INTRINSIC_TRUNC
2681 CEFBS_None, // G_INTRINSIC_ROUND
2682 CEFBS_None, // G_INTRINSIC_LRINT
2683 CEFBS_None, // G_INTRINSIC_LLRINT
2684 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2685 CEFBS_None, // G_READCYCLECOUNTER
2686 CEFBS_None, // G_READSTEADYCOUNTER
2687 CEFBS_None, // G_LOAD
2688 CEFBS_None, // G_SEXTLOAD
2689 CEFBS_None, // G_ZEXTLOAD
2690 CEFBS_None, // G_FPEXTLOAD
2691 CEFBS_None, // G_INDEXED_LOAD
2692 CEFBS_None, // G_INDEXED_SEXTLOAD
2693 CEFBS_None, // G_INDEXED_ZEXTLOAD
2694 CEFBS_None, // G_STORE
2695 CEFBS_None, // G_FPTRUNCSTORE
2696 CEFBS_None, // G_INDEXED_STORE
2697 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2698 CEFBS_None, // G_ATOMIC_CMPXCHG
2699 CEFBS_None, // G_ATOMICRMW_XCHG
2700 CEFBS_None, // G_ATOMICRMW_ADD
2701 CEFBS_None, // G_ATOMICRMW_SUB
2702 CEFBS_None, // G_ATOMICRMW_AND
2703 CEFBS_None, // G_ATOMICRMW_NAND
2704 CEFBS_None, // G_ATOMICRMW_OR
2705 CEFBS_None, // G_ATOMICRMW_XOR
2706 CEFBS_None, // G_ATOMICRMW_MAX
2707 CEFBS_None, // G_ATOMICRMW_MIN
2708 CEFBS_None, // G_ATOMICRMW_UMAX
2709 CEFBS_None, // G_ATOMICRMW_UMIN
2710 CEFBS_None, // G_ATOMICRMW_FADD
2711 CEFBS_None, // G_ATOMICRMW_FSUB
2712 CEFBS_None, // G_ATOMICRMW_FMAX
2713 CEFBS_None, // G_ATOMICRMW_FMIN
2714 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2715 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2716 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2717 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2718 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2719 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2720 CEFBS_None, // G_ATOMICRMW_USUB_COND
2721 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2722 CEFBS_None, // G_FENCE
2723 CEFBS_None, // G_PREFETCH
2724 CEFBS_None, // G_BRCOND
2725 CEFBS_None, // G_BRINDIRECT
2726 CEFBS_None, // G_INVOKE_REGION_START
2727 CEFBS_None, // G_INTRINSIC
2728 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2729 CEFBS_None, // G_INTRINSIC_CONVERGENT
2730 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2731 CEFBS_None, // G_ANYEXT
2732 CEFBS_None, // G_TRUNC
2733 CEFBS_None, // G_TRUNC_SSAT_S
2734 CEFBS_None, // G_TRUNC_SSAT_U
2735 CEFBS_None, // G_TRUNC_USAT_U
2736 CEFBS_None, // G_CONSTANT
2737 CEFBS_None, // G_FCONSTANT
2738 CEFBS_None, // G_VASTART
2739 CEFBS_None, // G_VAARG
2740 CEFBS_None, // G_SEXT
2741 CEFBS_None, // G_SEXT_INREG
2742 CEFBS_None, // G_ZEXT
2743 CEFBS_None, // G_SHL
2744 CEFBS_None, // G_LSHR
2745 CEFBS_None, // G_ASHR
2746 CEFBS_None, // G_FSHL
2747 CEFBS_None, // G_FSHR
2748 CEFBS_None, // G_ROTR
2749 CEFBS_None, // G_ROTL
2750 CEFBS_None, // G_ICMP
2751 CEFBS_None, // G_FCMP
2752 CEFBS_None, // G_SCMP
2753 CEFBS_None, // G_UCMP
2754 CEFBS_None, // G_SELECT
2755 CEFBS_None, // G_UADDO
2756 CEFBS_None, // G_UADDE
2757 CEFBS_None, // G_USUBO
2758 CEFBS_None, // G_USUBE
2759 CEFBS_None, // G_SADDO
2760 CEFBS_None, // G_SADDE
2761 CEFBS_None, // G_SSUBO
2762 CEFBS_None, // G_SSUBE
2763 CEFBS_None, // G_UMULO
2764 CEFBS_None, // G_SMULO
2765 CEFBS_None, // G_UMULH
2766 CEFBS_None, // G_SMULH
2767 CEFBS_None, // G_UADDSAT
2768 CEFBS_None, // G_SADDSAT
2769 CEFBS_None, // G_USUBSAT
2770 CEFBS_None, // G_SSUBSAT
2771 CEFBS_None, // G_USHLSAT
2772 CEFBS_None, // G_SSHLSAT
2773 CEFBS_None, // G_SMULFIX
2774 CEFBS_None, // G_UMULFIX
2775 CEFBS_None, // G_SMULFIXSAT
2776 CEFBS_None, // G_UMULFIXSAT
2777 CEFBS_None, // G_SDIVFIX
2778 CEFBS_None, // G_UDIVFIX
2779 CEFBS_None, // G_SDIVFIXSAT
2780 CEFBS_None, // G_UDIVFIXSAT
2781 CEFBS_None, // G_FADD
2782 CEFBS_None, // G_FSUB
2783 CEFBS_None, // G_FMUL
2784 CEFBS_None, // G_FMA
2785 CEFBS_None, // G_FMAD
2786 CEFBS_None, // G_FDIV
2787 CEFBS_None, // G_FREM
2788 CEFBS_None, // G_FMODF
2789 CEFBS_None, // G_FPOW
2790 CEFBS_None, // G_FPOWI
2791 CEFBS_None, // G_FEXP
2792 CEFBS_None, // G_FEXP2
2793 CEFBS_None, // G_FEXP10
2794 CEFBS_None, // G_FLOG
2795 CEFBS_None, // G_FLOG2
2796 CEFBS_None, // G_FLOG10
2797 CEFBS_None, // G_FLDEXP
2798 CEFBS_None, // G_FFREXP
2799 CEFBS_None, // G_FNEG
2800 CEFBS_None, // G_FPEXT
2801 CEFBS_None, // G_FPTRUNC
2802 CEFBS_None, // G_FPTOSI
2803 CEFBS_None, // G_FPTOUI
2804 CEFBS_None, // G_SITOFP
2805 CEFBS_None, // G_UITOFP
2806 CEFBS_None, // G_FPTOSI_SAT
2807 CEFBS_None, // G_FPTOUI_SAT
2808 CEFBS_None, // G_FABS
2809 CEFBS_None, // G_FCOPYSIGN
2810 CEFBS_None, // G_IS_FPCLASS
2811 CEFBS_None, // G_FCANONICALIZE
2812 CEFBS_None, // G_FMINNUM
2813 CEFBS_None, // G_FMAXNUM
2814 CEFBS_None, // G_FMINNUM_IEEE
2815 CEFBS_None, // G_FMAXNUM_IEEE
2816 CEFBS_None, // G_FMINIMUM
2817 CEFBS_None, // G_FMAXIMUM
2818 CEFBS_None, // G_FMINIMUMNUM
2819 CEFBS_None, // G_FMAXIMUMNUM
2820 CEFBS_None, // G_GET_FPENV
2821 CEFBS_None, // G_SET_FPENV
2822 CEFBS_None, // G_RESET_FPENV
2823 CEFBS_None, // G_GET_FPMODE
2824 CEFBS_None, // G_SET_FPMODE
2825 CEFBS_None, // G_RESET_FPMODE
2826 CEFBS_None, // G_GET_ROUNDING
2827 CEFBS_None, // G_SET_ROUNDING
2828 CEFBS_None, // G_PTR_ADD
2829 CEFBS_None, // G_PTRMASK
2830 CEFBS_None, // G_SMIN
2831 CEFBS_None, // G_SMAX
2832 CEFBS_None, // G_UMIN
2833 CEFBS_None, // G_UMAX
2834 CEFBS_None, // G_ABS
2835 CEFBS_None, // G_LROUND
2836 CEFBS_None, // G_LLROUND
2837 CEFBS_None, // G_BR
2838 CEFBS_None, // G_BRJT
2839 CEFBS_None, // G_VSCALE
2840 CEFBS_None, // G_INSERT_SUBVECTOR
2841 CEFBS_None, // G_EXTRACT_SUBVECTOR
2842 CEFBS_None, // G_INSERT_VECTOR_ELT
2843 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2844 CEFBS_None, // G_SHUFFLE_VECTOR
2845 CEFBS_None, // G_SPLAT_VECTOR
2846 CEFBS_None, // G_STEP_VECTOR
2847 CEFBS_None, // G_VECTOR_COMPRESS
2848 CEFBS_None, // G_CTTZ
2849 CEFBS_None, // G_CTTZ_ZERO_POISON
2850 CEFBS_None, // G_CTLZ
2851 CEFBS_None, // G_CTLZ_ZERO_POISON
2852 CEFBS_None, // G_CTLS
2853 CEFBS_None, // G_CTPOP
2854 CEFBS_None, // G_BSWAP
2855 CEFBS_None, // G_BITREVERSE
2856 CEFBS_None, // G_CLMUL
2857 CEFBS_None, // G_FCEIL
2858 CEFBS_None, // G_FCOS
2859 CEFBS_None, // G_FSIN
2860 CEFBS_None, // G_FSINCOS
2861 CEFBS_None, // G_FTAN
2862 CEFBS_None, // G_FACOS
2863 CEFBS_None, // G_FASIN
2864 CEFBS_None, // G_FATAN
2865 CEFBS_None, // G_FATAN2
2866 CEFBS_None, // G_FCOSH
2867 CEFBS_None, // G_FSINH
2868 CEFBS_None, // G_FTANH
2869 CEFBS_None, // G_FSQRT
2870 CEFBS_None, // G_FFLOOR
2871 CEFBS_None, // G_FRINT
2872 CEFBS_None, // G_FNEARBYINT
2873 CEFBS_None, // G_ADDRSPACE_CAST
2874 CEFBS_None, // G_BLOCK_ADDR
2875 CEFBS_None, // G_JUMP_TABLE
2876 CEFBS_None, // G_DYN_STACKALLOC
2877 CEFBS_None, // G_STACKSAVE
2878 CEFBS_None, // G_STACKRESTORE
2879 CEFBS_None, // G_STRICT_FADD
2880 CEFBS_None, // G_STRICT_FSUB
2881 CEFBS_None, // G_STRICT_FMUL
2882 CEFBS_None, // G_STRICT_FDIV
2883 CEFBS_None, // G_STRICT_FREM
2884 CEFBS_None, // G_STRICT_FMA
2885 CEFBS_None, // G_STRICT_FSQRT
2886 CEFBS_None, // G_STRICT_FLDEXP
2887 CEFBS_None, // G_STRICT_FCMP
2888 CEFBS_None, // G_STRICT_FCMPS
2889 CEFBS_None, // G_READ_REGISTER
2890 CEFBS_None, // G_WRITE_REGISTER
2891 CEFBS_None, // G_MEMCPY
2892 CEFBS_None, // G_MEMCPY_INLINE
2893 CEFBS_None, // G_MEMMOVE
2894 CEFBS_None, // G_MEMSET
2895 CEFBS_None, // G_BZERO
2896 CEFBS_None, // G_MEMSET_INLINE
2897 CEFBS_None, // G_TRAP
2898 CEFBS_None, // G_DEBUGTRAP
2899 CEFBS_None, // G_UBSANTRAP
2900 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2901 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2902 CEFBS_None, // G_VECREDUCE_FADD
2903 CEFBS_None, // G_VECREDUCE_FMUL
2904 CEFBS_None, // G_VECREDUCE_FMAX
2905 CEFBS_None, // G_VECREDUCE_FMIN
2906 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2907 CEFBS_None, // G_VECREDUCE_FMINIMUM
2908 CEFBS_None, // G_VECREDUCE_ADD
2909 CEFBS_None, // G_VECREDUCE_MUL
2910 CEFBS_None, // G_VECREDUCE_AND
2911 CEFBS_None, // G_VECREDUCE_OR
2912 CEFBS_None, // G_VECREDUCE_XOR
2913 CEFBS_None, // G_VECREDUCE_SMAX
2914 CEFBS_None, // G_VECREDUCE_SMIN
2915 CEFBS_None, // G_VECREDUCE_UMAX
2916 CEFBS_None, // G_VECREDUCE_UMIN
2917 CEFBS_None, // G_SBFX
2918 CEFBS_None, // G_UBFX
2919 CEFBS_None, // BRANCH
2920 CEFBS_None, // BRANCH_COND_f32
2921 CEFBS_None, // BRANCH_COND_i32
2922 CEFBS_None, // BREAK
2923 CEFBS_None, // BREAKC_f32
2924 CEFBS_None, // BREAKC_i32
2925 CEFBS_None, // BREAK_LOGICALNZ_f32
2926 CEFBS_None, // BREAK_LOGICALNZ_i32
2927 CEFBS_None, // BREAK_LOGICALZ_f32
2928 CEFBS_None, // BREAK_LOGICALZ_i32
2929 CEFBS_None, // CONST_COPY
2930 CEFBS_None, // CONTINUE
2931 CEFBS_None, // CONTINUEC_f32
2932 CEFBS_None, // CONTINUEC_i32
2933 CEFBS_None, // CONTINUE_LOGICALNZ_f32
2934 CEFBS_None, // CONTINUE_LOGICALNZ_i32
2935 CEFBS_None, // CONTINUE_LOGICALZ_f32
2936 CEFBS_None, // CONTINUE_LOGICALZ_i32
2937 CEFBS_None, // CUBE_eg_pseudo
2938 CEFBS_None, // CUBE_r600_pseudo
2939 CEFBS_None, // DEFAULT
2940 CEFBS_None, // DOT_4
2941 CEFBS_None, // DUMMY_CHAIN
2942 CEFBS_None, // ELSE
2943 CEFBS_None, // END
2944 CEFBS_None, // ENDFUNC
2945 CEFBS_None, // ENDIF
2946 CEFBS_None, // ENDLOOP
2947 CEFBS_None, // ENDMAIN
2948 CEFBS_None, // ENDSWITCH
2949 CEFBS_None, // FABS_R600
2950 CEFBS_None, // FNEG_R600
2951 CEFBS_None, // FUNC
2952 CEFBS_None, // IFC_f32
2953 CEFBS_None, // IFC_i32
2954 CEFBS_None, // IF_LOGICALNZ_f32
2955 CEFBS_None, // IF_LOGICALNZ_i32
2956 CEFBS_None, // IF_LOGICALZ_f32
2957 CEFBS_None, // IF_LOGICALZ_i32
2958 CEFBS_None, // IF_PREDICATE_SET
2959 CEFBS_None, // JUMP
2960 CEFBS_None, // JUMP_COND
2961 CEFBS_None, // MASK_WRITE
2962 CEFBS_None, // MOV_IMM_F32
2963 CEFBS_None, // MOV_IMM_GLOBAL_ADDR
2964 CEFBS_None, // MOV_IMM_I32
2965 CEFBS_None, // PRED_X
2966 CEFBS_None, // R600_EXTRACT_ELT_V2
2967 CEFBS_None, // R600_EXTRACT_ELT_V4
2968 CEFBS_None, // R600_INSERT_ELT_V2
2969 CEFBS_None, // R600_INSERT_ELT_V4
2970 CEFBS_None, // R600_RegisterLoad
2971 CEFBS_None, // R600_RegisterStore
2972 CEFBS_None, // RETDYN
2973 CEFBS_None, // RETURN
2974 CEFBS_None, // TXD
2975 CEFBS_None, // TXD_SHADOW
2976 CEFBS_None, // WHILELOOP
2977 CEFBS_None, // ADD
2978 CEFBS_None, // ADDC_UINT
2979 CEFBS_None, // ADD_INT
2980 CEFBS_None, // ALU_CLAUSE
2981 CEFBS_None, // AND_INT
2982 CEFBS_None, // ASHR_eg
2983 CEFBS_None, // ASHR_r600
2984 CEFBS_None, // BCNT_INT
2985 CEFBS_None, // BFE_INT_eg
2986 CEFBS_None, // BFE_UINT_eg
2987 CEFBS_None, // BFI_INT_eg
2988 CEFBS_None, // BFM_INT_eg
2989 CEFBS_None, // BIT_ALIGN_INT_eg
2990 CEFBS_None, // CEIL
2991 CEFBS_None, // CF_ALU
2992 CEFBS_None, // CF_ALU_BREAK
2993 CEFBS_None, // CF_ALU_CONTINUE
2994 CEFBS_None, // CF_ALU_ELSE_AFTER
2995 CEFBS_None, // CF_ALU_POP_AFTER
2996 CEFBS_None, // CF_ALU_PUSH_BEFORE
2997 CEFBS_None, // CF_CALL_FS_EG
2998 CEFBS_None, // CF_CALL_FS_R600
2999 CEFBS_None, // CF_CONTINUE_EG
3000 CEFBS_None, // CF_CONTINUE_R600
3001 CEFBS_None, // CF_ELSE_EG
3002 CEFBS_None, // CF_ELSE_R600
3003 CEFBS_None, // CF_END_CM
3004 CEFBS_None, // CF_END_EG
3005 CEFBS_None, // CF_END_R600
3006 CEFBS_None, // CF_JUMP_EG
3007 CEFBS_None, // CF_JUMP_R600
3008 CEFBS_None, // CF_PUSH_EG
3009 CEFBS_None, // CF_PUSH_ELSE_R600
3010 CEFBS_None, // CF_TC_EG
3011 CEFBS_None, // CF_TC_R600
3012 CEFBS_None, // CF_VC_EG
3013 CEFBS_None, // CF_VC_R600
3014 CEFBS_None, // CNDE_INT
3015 CEFBS_None, // CNDE_eg
3016 CEFBS_None, // CNDE_r600
3017 CEFBS_None, // CNDGE_INT
3018 CEFBS_None, // CNDGE_eg
3019 CEFBS_None, // CNDGE_r600
3020 CEFBS_None, // CNDGT_INT
3021 CEFBS_None, // CNDGT_eg
3022 CEFBS_None, // CNDGT_r600
3023 CEFBS_None, // COS_cm
3024 CEFBS_None, // COS_eg
3025 CEFBS_None, // COS_r600
3026 CEFBS_None, // COS_r700
3027 CEFBS_None, // CUBE_eg_real
3028 CEFBS_None, // CUBE_r600_real
3029 CEFBS_None, // DOT4_eg
3030 CEFBS_None, // DOT4_r600
3031 CEFBS_None, // EG_ExportBuf
3032 CEFBS_None, // EG_ExportSwz
3033 CEFBS_None, // END_LOOP_EG
3034 CEFBS_None, // END_LOOP_R600
3035 CEFBS_None, // EXP_IEEE_cm
3036 CEFBS_None, // EXP_IEEE_eg
3037 CEFBS_None, // EXP_IEEE_r600
3038 CEFBS_None, // FETCH_CLAUSE
3039 CEFBS_None, // FFBH_UINT
3040 CEFBS_None, // FFBL_INT
3041 CEFBS_None, // FLOOR
3042 CEFBS_None, // FLT16_TO_FLT32
3043 CEFBS_None, // FLT32_TO_FLT16
3044 CEFBS_None, // FLT_TO_INT_eg
3045 CEFBS_None, // FLT_TO_INT_r600
3046 CEFBS_None, // FLT_TO_UINT_eg
3047 CEFBS_None, // FLT_TO_UINT_r600
3048 CEFBS_None, // FMA_eg
3049 CEFBS_None, // FRACT
3050 CEFBS_None, // GROUP_BARRIER
3051 CEFBS_None, // INTERP_LOAD_P0
3052 CEFBS_None, // INTERP_PAIR_XY
3053 CEFBS_None, // INTERP_PAIR_ZW
3054 CEFBS_None, // INTERP_VEC_LOAD
3055 CEFBS_None, // INTERP_XY
3056 CEFBS_None, // INTERP_ZW
3057 CEFBS_None, // INT_TO_FLT_eg
3058 CEFBS_None, // INT_TO_FLT_r600
3059 CEFBS_None, // KILLGT
3060 CEFBS_None, // LDS_ADD
3061 CEFBS_None, // LDS_ADD_RET
3062 CEFBS_None, // LDS_AND
3063 CEFBS_None, // LDS_AND_RET
3064 CEFBS_None, // LDS_BYTE_READ_RET
3065 CEFBS_None, // LDS_BYTE_WRITE
3066 CEFBS_None, // LDS_CMPST
3067 CEFBS_None, // LDS_CMPST_RET
3068 CEFBS_None, // LDS_MAX_INT
3069 CEFBS_None, // LDS_MAX_INT_RET
3070 CEFBS_None, // LDS_MAX_UINT
3071 CEFBS_None, // LDS_MAX_UINT_RET
3072 CEFBS_None, // LDS_MIN_INT
3073 CEFBS_None, // LDS_MIN_INT_RET
3074 CEFBS_None, // LDS_MIN_UINT
3075 CEFBS_None, // LDS_MIN_UINT_RET
3076 CEFBS_None, // LDS_OR
3077 CEFBS_None, // LDS_OR_RET
3078 CEFBS_None, // LDS_READ_RET
3079 CEFBS_None, // LDS_SHORT_READ_RET
3080 CEFBS_None, // LDS_SHORT_WRITE
3081 CEFBS_None, // LDS_SUB
3082 CEFBS_None, // LDS_SUB_RET
3083 CEFBS_None, // LDS_UBYTE_READ_RET
3084 CEFBS_None, // LDS_USHORT_READ_RET
3085 CEFBS_None, // LDS_WRITE
3086 CEFBS_None, // LDS_WRXCHG
3087 CEFBS_None, // LDS_WRXCHG_RET
3088 CEFBS_None, // LDS_XOR
3089 CEFBS_None, // LDS_XOR_RET
3090 CEFBS_None, // LITERALS
3091 CEFBS_None, // LOG_CLAMPED_eg
3092 CEFBS_None, // LOG_CLAMPED_r600
3093 CEFBS_None, // LOG_IEEE_cm
3094 CEFBS_None, // LOG_IEEE_eg
3095 CEFBS_None, // LOG_IEEE_r600
3096 CEFBS_None, // LOOP_BREAK_EG
3097 CEFBS_None, // LOOP_BREAK_R600
3098 CEFBS_None, // LSHL_eg
3099 CEFBS_None, // LSHL_r600
3100 CEFBS_None, // LSHR_eg
3101 CEFBS_None, // LSHR_r600
3102 CEFBS_None, // MAX
3103 CEFBS_None, // MAX_DX10
3104 CEFBS_None, // MAX_INT
3105 CEFBS_None, // MAX_UINT
3106 CEFBS_None, // MIN
3107 CEFBS_None, // MIN_DX10
3108 CEFBS_None, // MIN_INT
3109 CEFBS_None, // MIN_UINT
3110 CEFBS_None, // MOV
3111 CEFBS_None, // MOVA_INT_eg
3112 CEFBS_None, // MUL
3113 CEFBS_None, // MULADD_IEEE_eg
3114 CEFBS_None, // MULADD_IEEE_r600
3115 CEFBS_None, // MULADD_INT24_cm
3116 CEFBS_None, // MULADD_UINT24_eg
3117 CEFBS_None, // MULADD_eg
3118 CEFBS_None, // MULADD_r600
3119 CEFBS_None, // MULHI_INT_cm
3120 CEFBS_None, // MULHI_INT_cm24
3121 CEFBS_None, // MULHI_INT_eg
3122 CEFBS_None, // MULHI_INT_r600
3123 CEFBS_None, // MULHI_UINT24_eg
3124 CEFBS_None, // MULHI_UINT_cm
3125 CEFBS_None, // MULHI_UINT_cm24
3126 CEFBS_None, // MULHI_UINT_eg
3127 CEFBS_None, // MULHI_UINT_r600
3128 CEFBS_None, // MULLO_INT_cm
3129 CEFBS_None, // MULLO_INT_eg
3130 CEFBS_None, // MULLO_INT_r600
3131 CEFBS_None, // MULLO_UINT_cm
3132 CEFBS_None, // MULLO_UINT_eg
3133 CEFBS_None, // MULLO_UINT_r600
3134 CEFBS_None, // MUL_IEEE
3135 CEFBS_None, // MUL_INT24_cm
3136 CEFBS_None, // MUL_LIT_eg
3137 CEFBS_None, // MUL_LIT_r600
3138 CEFBS_None, // MUL_UINT24_eg
3139 CEFBS_None, // NOT_INT
3140 CEFBS_None, // OR_INT
3141 CEFBS_None, // PAD
3142 CEFBS_None, // POP_EG
3143 CEFBS_None, // POP_R600
3144 CEFBS_None, // PRED_SETE
3145 CEFBS_None, // PRED_SETE_INT
3146 CEFBS_None, // PRED_SETGE
3147 CEFBS_None, // PRED_SETGE_INT
3148 CEFBS_None, // PRED_SETGT
3149 CEFBS_None, // PRED_SETGT_INT
3150 CEFBS_None, // PRED_SETNE
3151 CEFBS_None, // PRED_SETNE_INT
3152 CEFBS_None, // R600_ExportBuf
3153 CEFBS_None, // R600_ExportSwz
3154 CEFBS_None, // RAT_ATOMIC_ADD_NORET
3155 CEFBS_None, // RAT_ATOMIC_ADD_RTN
3156 CEFBS_None, // RAT_ATOMIC_AND_NORET
3157 CEFBS_None, // RAT_ATOMIC_AND_RTN
3158 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET
3159 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN
3160 CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET
3161 CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN
3162 CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET
3163 CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN
3164 CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET
3165 CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN
3166 CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET
3167 CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN
3168 CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET
3169 CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN
3170 CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET
3171 CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN
3172 CEFBS_None, // RAT_ATOMIC_OR_NORET
3173 CEFBS_None, // RAT_ATOMIC_OR_RTN
3174 CEFBS_None, // RAT_ATOMIC_RSUB_NORET
3175 CEFBS_None, // RAT_ATOMIC_RSUB_RTN
3176 CEFBS_None, // RAT_ATOMIC_SUB_NORET
3177 CEFBS_None, // RAT_ATOMIC_SUB_RTN
3178 CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET
3179 CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN
3180 CEFBS_None, // RAT_ATOMIC_XOR_NORET
3181 CEFBS_None, // RAT_ATOMIC_XOR_RTN
3182 CEFBS_None, // RAT_MSKOR
3183 CEFBS_None, // RAT_STORE_DWORD128
3184 CEFBS_None, // RAT_STORE_DWORD32
3185 CEFBS_None, // RAT_STORE_DWORD64
3186 CEFBS_None, // RAT_STORE_TYPED_cm
3187 CEFBS_None, // RAT_STORE_TYPED_eg
3188 CEFBS_None, // RAT_WRITE_CACHELESS_128_eg
3189 CEFBS_None, // RAT_WRITE_CACHELESS_32_eg
3190 CEFBS_None, // RAT_WRITE_CACHELESS_64_eg
3191 CEFBS_None, // RECIPSQRT_CLAMPED_cm
3192 CEFBS_None, // RECIPSQRT_CLAMPED_eg
3193 CEFBS_None, // RECIPSQRT_CLAMPED_r600
3194 CEFBS_None, // RECIPSQRT_IEEE_cm
3195 CEFBS_None, // RECIPSQRT_IEEE_eg
3196 CEFBS_None, // RECIPSQRT_IEEE_r600
3197 CEFBS_None, // RECIP_CLAMPED_cm
3198 CEFBS_None, // RECIP_CLAMPED_eg
3199 CEFBS_None, // RECIP_CLAMPED_r600
3200 CEFBS_None, // RECIP_IEEE_cm
3201 CEFBS_None, // RECIP_IEEE_eg
3202 CEFBS_None, // RECIP_IEEE_r600
3203 CEFBS_None, // RECIP_UINT_eg
3204 CEFBS_None, // RECIP_UINT_r600
3205 CEFBS_None, // RNDNE
3206 CEFBS_None, // SETE
3207 CEFBS_None, // SETE_DX10
3208 CEFBS_None, // SETE_INT
3209 CEFBS_None, // SETGE_DX10
3210 CEFBS_None, // SETGE_INT
3211 CEFBS_None, // SETGE_UINT
3212 CEFBS_None, // SETGT_DX10
3213 CEFBS_None, // SETGT_INT
3214 CEFBS_None, // SETGT_UINT
3215 CEFBS_None, // SETNE_DX10
3216 CEFBS_None, // SETNE_INT
3217 CEFBS_None, // SGE
3218 CEFBS_None, // SGT
3219 CEFBS_None, // SIN_cm
3220 CEFBS_None, // SIN_eg
3221 CEFBS_None, // SIN_r600
3222 CEFBS_None, // SIN_r700
3223 CEFBS_None, // SNE
3224 CEFBS_None, // SUBB_UINT
3225 CEFBS_None, // SUB_INT
3226 CEFBS_None, // TEX_GET_GRADIENTS_H
3227 CEFBS_None, // TEX_GET_GRADIENTS_V
3228 CEFBS_None, // TEX_GET_TEXTURE_RESINFO
3229 CEFBS_None, // TEX_LD
3230 CEFBS_None, // TEX_LDPTR
3231 CEFBS_None, // TEX_SAMPLE
3232 CEFBS_None, // TEX_SAMPLE_C
3233 CEFBS_None, // TEX_SAMPLE_C_G
3234 CEFBS_None, // TEX_SAMPLE_C_L
3235 CEFBS_None, // TEX_SAMPLE_C_LB
3236 CEFBS_None, // TEX_SAMPLE_G
3237 CEFBS_None, // TEX_SAMPLE_L
3238 CEFBS_None, // TEX_SAMPLE_LB
3239 CEFBS_None, // TEX_SET_GRADIENTS_H
3240 CEFBS_None, // TEX_SET_GRADIENTS_V
3241 CEFBS_None, // TEX_VTX_CONSTBUF
3242 CEFBS_None, // TEX_VTX_TEXBUF
3243 CEFBS_None, // TRUNC
3244 CEFBS_None, // UINT_TO_FLT_eg
3245 CEFBS_None, // UINT_TO_FLT_r600
3246 CEFBS_None, // VTX_READ_128_cm
3247 CEFBS_None, // VTX_READ_128_eg
3248 CEFBS_None, // VTX_READ_16_cm
3249 CEFBS_None, // VTX_READ_16_eg
3250 CEFBS_None, // VTX_READ_32_cm
3251 CEFBS_None, // VTX_READ_32_eg
3252 CEFBS_None, // VTX_READ_64_cm
3253 CEFBS_None, // VTX_READ_64_eg
3254 CEFBS_None, // VTX_READ_8_cm
3255 CEFBS_None, // VTX_READ_8_eg
3256 CEFBS_None, // WHILE_LOOP_EG
3257 CEFBS_None, // WHILE_LOOP_R600
3258 CEFBS_None, // XOR_INT
3259 };
3260
3261 assert(Opcode < 671);
3262 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3263}
3264
3265
3266} // namespace llvm::R600_MC
3267
3268#endif // GET_COMPUTE_FEATURES
3269
3270#ifdef GET_AVAILABLE_OPCODE_CHECKER
3271#undef GET_AVAILABLE_OPCODE_CHECKER
3272
3273namespace llvm::R600_MC {
3274
3275bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3276 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3277 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3278 FeatureBitset MissingFeatures =
3279 (AvailableFeatures & RequiredFeatures) ^
3280 RequiredFeatures;
3281 return !MissingFeatures.any();
3282}
3283
3284} // namespace llvm::R600_MC
3285
3286#endif // GET_AVAILABLE_OPCODE_CHECKER
3287
3288#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3289#undef ENABLE_INSTR_PREDICATE_VERIFIER
3290
3291#include <sstream>
3292
3293namespace llvm::R600_MC {
3294
3295#ifndef NDEBUG
3296static const char *SubtargetFeatureNames[] = {
3297 nullptr
3298};
3299
3300#endif // NDEBUG
3301
3302void verifyInstructionPredicates(
3303 unsigned Opcode, const FeatureBitset &Features) {
3304#ifndef NDEBUG
3305 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3306 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3307 FeatureBitset MissingFeatures =
3308 (AvailableFeatures & RequiredFeatures) ^
3309 RequiredFeatures;
3310 if (MissingFeatures.any()) {
3311 std::ostringstream Msg;
3312 Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
3313 << " instruction but the ";
3314 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3315 if (MissingFeatures.test(i))
3316 Msg << SubtargetFeatureNames[i] << " ";
3317 Msg << "predicate(s) are not met";
3318 report_fatal_error(Msg.str().c_str());
3319 }
3320#endif // NDEBUG
3321}
3322
3323} // namespace llvm::R600_MC
3324
3325#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3326
3327#ifdef GET_INSTRMAP_INFO
3328#undef GET_INSTRMAP_INFO
3329
3330namespace llvm::R600 {
3331
3332enum usesCustomInserter {
3333 usesCustomInserter_0
3334};
3335
3336// getLDSNoRetOp
3337LLVM_READONLY
3338int32_t getLDSNoRetOp(uint32_t Opcode) {
3339 using namespace R600;
3340 static constexpr uint32_t Table[][2] = {
3341 { LDS_ADD_RET, LDS_ADD },
3342 { LDS_AND_RET, LDS_AND },
3343 { LDS_MAX_INT_RET, LDS_MAX_INT },
3344 { LDS_MAX_UINT_RET, LDS_MAX_UINT },
3345 { LDS_MIN_INT_RET, LDS_MIN_INT },
3346 { LDS_MIN_UINT_RET, LDS_MIN_UINT },
3347 { LDS_OR_RET, LDS_OR },
3348 { LDS_SUB_RET, LDS_SUB },
3349 { LDS_WRXCHG_RET, LDS_WRXCHG },
3350 { LDS_XOR_RET, LDS_XOR },
3351 }; // End of Table
3352
3353 unsigned mid;
3354 unsigned start = 0;
3355 unsigned end = 10;
3356 while (start < end) {
3357 mid = start + (end - start) / 2;
3358 if (Opcode == Table[mid][0])
3359 break;
3360 if (Opcode < Table[mid][0])
3361 end = mid;
3362 else
3363 start = mid + 1;
3364 }
3365 if (start == end)
3366 return -1; // Instruction doesn't exist in this table.
3367
3368 return Table[mid][1];
3369}
3370
3371
3372} // namespace llvm::R600
3373
3374#endif // GET_INSTRMAP_INFO
3375
3376