1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::R600 {
13
14 enum {
15 PHI = 0, // Target.td:1301
16 INLINEASM = 1, // Target.td:1307
17 INLINEASM_BR = 2, // Target.td:1313
18 CFI_INSTRUCTION = 3, // Target.td:1322
19 EH_LABEL = 4, // Target.td:1331
20 GC_LABEL = 5, // Target.td:1340
21 ANNOTATION_LABEL = 6, // Target.td:1349
22 KILL = 7, // Target.td:1357
23 EXTRACT_SUBREG = 8, // Target.td:1364
24 INSERT_SUBREG = 9, // Target.td:1370
25 IMPLICIT_DEF = 10, // Target.td:1377
26 INIT_UNDEF = 11, // Target.td:1386
27 SUBREG_TO_REG = 12, // Target.td:1393
28 COPY_TO_REGCLASS = 13, // Target.td:1399
29 DBG_VALUE = 14, // Target.td:1406
30 DBG_VALUE_LIST = 15, // Target.td:1413
31 DBG_INSTR_REF = 16, // Target.td:1420
32 DBG_PHI = 17, // Target.td:1427
33 DBG_LABEL = 18, // Target.td:1434
34 REG_SEQUENCE = 19, // Target.td:1441
35 COPY = 20, // Target.td:1448
36 COPY_LANEMASK = 21, // Target.td:1456
37 BUNDLE = 22, // Target.td:1463
38 LIFETIME_START = 23, // Target.td:1469
39 LIFETIME_END = 24, // Target.td:1476
40 PSEUDO_PROBE = 25, // Target.td:1483
41 ARITH_FENCE = 26, // Target.td:1490
42 STACKMAP = 27, // Target.td:1499
43 FENTRY_CALL = 28, // Target.td:1634
44 PATCHPOINT = 29, // Target.td:1507
45 LOAD_STACK_GUARD = 30, // Target.td:1525
46 PREALLOCATED_SETUP = 31, // Target.td:1533
47 PREALLOCATED_ARG = 32, // Target.td:1539
48 STATEPOINT = 33, // Target.td:1516
49 LOCAL_ESCAPE = 34, // Target.td:1545
50 FAULTING_OP = 35, // Target.td:1554
51 PATCHABLE_OP = 36, // Target.td:1574
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1582
53 PATCHABLE_RET = 38, // Target.td:1589
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1598
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1606
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1614
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1624
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1644
59 FAKE_USE = 44, // Target.td:1564
60 MEMBARRIER = 45, // Target.td:1650
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1658
62 RELOC_NONE = 47, // Target.td:1666
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1678
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1674
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1682
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1686
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1867
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1859
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1874
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1474
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1486
96 G_INSERT = 81, // GenericOpcodes.td:1494
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1504
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1523
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1532
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1539
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1881
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_FMAXIMUMNUM = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_FMINIMUMNUM = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_UINC_WRAP = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_UDEC_WRAP = 129, // GenericOpcodes.td:1448
145 G_ATOMICRMW_USUB_COND = 130, // GenericOpcodes.td:1449
146 G_ATOMICRMW_USUB_SAT = 131, // GenericOpcodes.td:1450
147 G_FENCE = 132, // GenericOpcodes.td:1452
148 G_PREFETCH = 133, // GenericOpcodes.td:1459
149 G_BRCOND = 134, // GenericOpcodes.td:1594
150 G_BRINDIRECT = 135, // GenericOpcodes.td:1603
151 G_INVOKE_REGION_START = 136, // GenericOpcodes.td:1626
152 G_INTRINSIC = 137, // GenericOpcodes.td:1546
153 G_INTRINSIC_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1553
154 G_INTRINSIC_CONVERGENT = 139, // GenericOpcodes.td:1562
155 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1570
156 G_ANYEXT = 141, // GenericOpcodes.td:44
157 G_TRUNC = 142, // GenericOpcodes.td:83
158 G_TRUNC_SSAT_S = 143, // GenericOpcodes.td:90
159 G_TRUNC_SSAT_U = 144, // GenericOpcodes.td:97
160 G_TRUNC_USAT_U = 145, // GenericOpcodes.td:104
161 G_CONSTANT = 146, // GenericOpcodes.td:165
162 G_FCONSTANT = 147, // GenericOpcodes.td:172
163 G_VASTART = 148, // GenericOpcodes.td:178
164 G_VAARG = 149, // GenericOpcodes.td:185
165 G_SEXT = 150, // GenericOpcodes.td:52
166 G_SEXT_INREG = 151, // GenericOpcodes.td:66
167 G_ZEXT = 152, // GenericOpcodes.td:74
168 G_SHL = 153, // GenericOpcodes.td:396
169 G_LSHR = 154, // GenericOpcodes.td:403
170 G_ASHR = 155, // GenericOpcodes.td:410
171 G_FSHL = 156, // GenericOpcodes.td:462
172 G_FSHR = 157, // GenericOpcodes.td:470
173 G_ROTR = 158, // GenericOpcodes.td:477
174 G_ROTL = 159, // GenericOpcodes.td:484
175 G_ICMP = 160, // GenericOpcodes.td:491
176 G_FCMP = 161, // GenericOpcodes.td:498
177 G_SCMP = 162, // GenericOpcodes.td:505
178 G_UCMP = 163, // GenericOpcodes.td:512
179 G_SELECT = 164, // GenericOpcodes.td:519
180 G_UADDO = 165, // GenericOpcodes.td:584
181 G_UADDE = 166, // GenericOpcodes.td:592
182 G_USUBO = 167, // GenericOpcodes.td:614
183 G_USUBE = 168, // GenericOpcodes.td:620
184 G_SADDO = 169, // GenericOpcodes.td:599
185 G_SADDE = 170, // GenericOpcodes.td:607
186 G_SSUBO = 171, // GenericOpcodes.td:627
187 G_SSUBE = 172, // GenericOpcodes.td:634
188 G_UMULO = 173, // GenericOpcodes.td:641
189 G_SMULO = 174, // GenericOpcodes.td:649
190 G_UMULH = 175, // GenericOpcodes.td:658
191 G_SMULH = 176, // GenericOpcodes.td:667
192 G_UADDSAT = 177, // GenericOpcodes.td:679
193 G_SADDSAT = 178, // GenericOpcodes.td:687
194 G_USUBSAT = 179, // GenericOpcodes.td:695
195 G_SSUBSAT = 180, // GenericOpcodes.td:703
196 G_USHLSAT = 181, // GenericOpcodes.td:711
197 G_SSHLSAT = 182, // GenericOpcodes.td:719
198 G_SMULFIX = 183, // GenericOpcodes.td:731
199 G_UMULFIX = 184, // GenericOpcodes.td:738
200 G_SMULFIXSAT = 185, // GenericOpcodes.td:748
201 G_UMULFIXSAT = 186, // GenericOpcodes.td:755
202 G_SDIVFIX = 187, // GenericOpcodes.td:766
203 G_UDIVFIX = 188, // GenericOpcodes.td:773
204 G_SDIVFIXSAT = 189, // GenericOpcodes.td:783
205 G_UDIVFIXSAT = 190, // GenericOpcodes.td:790
206 G_FADD = 191, // GenericOpcodes.td:963
207 G_FSUB = 192, // GenericOpcodes.td:971
208 G_FMUL = 193, // GenericOpcodes.td:979
209 G_FMA = 194, // GenericOpcodes.td:988
210 G_FMAD = 195, // GenericOpcodes.td:997
211 G_FDIV = 196, // GenericOpcodes.td:1005
212 G_FREM = 197, // GenericOpcodes.td:1012
213 G_FMODF = 198, // GenericOpcodes.td:1019
214 G_FPOW = 199, // GenericOpcodes.td:1026
215 G_FPOWI = 200, // GenericOpcodes.td:1033
216 G_FEXP = 201, // GenericOpcodes.td:1040
217 G_FEXP2 = 202, // GenericOpcodes.td:1047
218 G_FEXP10 = 203, // GenericOpcodes.td:1054
219 G_FLOG = 204, // GenericOpcodes.td:1061
220 G_FLOG2 = 205, // GenericOpcodes.td:1068
221 G_FLOG10 = 206, // GenericOpcodes.td:1075
222 G_FLDEXP = 207, // GenericOpcodes.td:1082
223 G_FFREXP = 208, // GenericOpcodes.td:1089
224 G_FNEG = 209, // GenericOpcodes.td:801
225 G_FPEXT = 210, // GenericOpcodes.td:807
226 G_FPTRUNC = 211, // GenericOpcodes.td:813
227 G_FPTOSI = 212, // GenericOpcodes.td:819
228 G_FPTOUI = 213, // GenericOpcodes.td:825
229 G_SITOFP = 214, // GenericOpcodes.td:831
230 G_UITOFP = 215, // GenericOpcodes.td:837
231 G_FPTOSI_SAT = 216, // GenericOpcodes.td:843
232 G_FPTOUI_SAT = 217, // GenericOpcodes.td:849
233 G_FABS = 218, // GenericOpcodes.td:855
234 G_FCOPYSIGN = 219, // GenericOpcodes.td:861
235 G_IS_FPCLASS = 220, // GenericOpcodes.td:874
236 G_FCANONICALIZE = 221, // GenericOpcodes.td:867
237 G_FMINNUM = 222, // GenericOpcodes.td:887
238 G_FMAXNUM = 223, // GenericOpcodes.td:894
239 G_FMINNUM_IEEE = 224, // GenericOpcodes.td:912
240 G_FMAXNUM_IEEE = 225, // GenericOpcodes.td:919
241 G_FMINIMUM = 226, // GenericOpcodes.td:929
242 G_FMAXIMUM = 227, // GenericOpcodes.td:936
243 G_FMINIMUMNUM = 228, // GenericOpcodes.td:944
244 G_FMAXIMUMNUM = 229, // GenericOpcodes.td:951
245 G_GET_FPENV = 230, // GenericOpcodes.td:1219
246 G_SET_FPENV = 231, // GenericOpcodes.td:1226
247 G_RESET_FPENV = 232, // GenericOpcodes.td:1233
248 G_GET_FPMODE = 233, // GenericOpcodes.td:1240
249 G_SET_FPMODE = 234, // GenericOpcodes.td:1247
250 G_RESET_FPMODE = 235, // GenericOpcodes.td:1254
251 G_GET_ROUNDING = 236, // GenericOpcodes.td:1311
252 G_SET_ROUNDING = 237, // GenericOpcodes.td:1317
253 G_PTR_ADD = 238, // GenericOpcodes.td:526
254 G_PTRMASK = 239, // GenericOpcodes.td:534
255 G_SMIN = 240, // GenericOpcodes.td:541
256 G_SMAX = 241, // GenericOpcodes.td:549
257 G_UMIN = 242, // GenericOpcodes.td:557
258 G_UMAX = 243, // GenericOpcodes.td:565
259 G_ABS = 244, // GenericOpcodes.td:573
260 G_LROUND = 245, // GenericOpcodes.td:283
261 G_LLROUND = 246, // GenericOpcodes.td:289
262 G_BR = 247, // GenericOpcodes.td:1584
263 G_BRJT = 248, // GenericOpcodes.td:1614
264 G_VSCALE = 249, // GenericOpcodes.td:1514
265 G_INSERT_SUBVECTOR = 250, // GenericOpcodes.td:1658
266 G_EXTRACT_SUBVECTOR = 251, // GenericOpcodes.td:1665
267 G_INSERT_VECTOR_ELT = 252, // GenericOpcodes.td:1672
268 G_EXTRACT_VECTOR_ELT = 253, // GenericOpcodes.td:1679
269 G_SHUFFLE_VECTOR = 254, // GenericOpcodes.td:1689
270 G_SPLAT_VECTOR = 255, // GenericOpcodes.td:1696
271 G_STEP_VECTOR = 256, // GenericOpcodes.td:1703
272 G_VECTOR_COMPRESS = 257, // GenericOpcodes.td:1710
273 G_CTTZ = 258, // GenericOpcodes.td:205
274 G_CTTZ_ZERO_UNDEF = 259, // GenericOpcodes.td:211
275 G_CTLZ = 260, // GenericOpcodes.td:193
276 G_CTLZ_ZERO_UNDEF = 261, // GenericOpcodes.td:199
277 G_CTLS = 262, // GenericOpcodes.td:217
278 G_CTPOP = 263, // GenericOpcodes.td:223
279 G_BSWAP = 264, // GenericOpcodes.td:229
280 G_BITREVERSE = 265, // GenericOpcodes.td:235
281 G_FCEIL = 266, // GenericOpcodes.td:1096
282 G_FCOS = 267, // GenericOpcodes.td:1103
283 G_FSIN = 268, // GenericOpcodes.td:1110
284 G_FSINCOS = 269, // GenericOpcodes.td:1117
285 G_FTAN = 270, // GenericOpcodes.td:1124
286 G_FACOS = 271, // GenericOpcodes.td:1131
287 G_FASIN = 272, // GenericOpcodes.td:1138
288 G_FATAN = 273, // GenericOpcodes.td:1145
289 G_FATAN2 = 274, // GenericOpcodes.td:1152
290 G_FCOSH = 275, // GenericOpcodes.td:1159
291 G_FSINH = 276, // GenericOpcodes.td:1166
292 G_FTANH = 277, // GenericOpcodes.td:1173
293 G_FSQRT = 278, // GenericOpcodes.td:1183
294 G_FFLOOR = 279, // GenericOpcodes.td:1190
295 G_FRINT = 280, // GenericOpcodes.td:1197
296 G_FNEARBYINT = 281, // GenericOpcodes.td:1204
297 G_ADDRSPACE_CAST = 282, // GenericOpcodes.td:241
298 G_BLOCK_ADDR = 283, // GenericOpcodes.td:247
299 G_JUMP_TABLE = 284, // GenericOpcodes.td:253
300 G_DYN_STACKALLOC = 285, // GenericOpcodes.td:259
301 G_STACKSAVE = 286, // GenericOpcodes.td:265
302 G_STACKRESTORE = 287, // GenericOpcodes.td:271
303 G_STRICT_FADD = 288, // GenericOpcodes.td:1760
304 G_STRICT_FSUB = 289, // GenericOpcodes.td:1761
305 G_STRICT_FMUL = 290, // GenericOpcodes.td:1762
306 G_STRICT_FDIV = 291, // GenericOpcodes.td:1763
307 G_STRICT_FREM = 292, // GenericOpcodes.td:1764
308 G_STRICT_FMA = 293, // GenericOpcodes.td:1765
309 G_STRICT_FSQRT = 294, // GenericOpcodes.td:1766
310 G_STRICT_FLDEXP = 295, // GenericOpcodes.td:1767
311 G_READ_REGISTER = 296, // GenericOpcodes.td:1633
312 G_WRITE_REGISTER = 297, // GenericOpcodes.td:1643
313 G_MEMCPY = 298, // GenericOpcodes.td:1773
314 G_MEMCPY_INLINE = 299, // GenericOpcodes.td:1781
315 G_MEMMOVE = 300, // GenericOpcodes.td:1789
316 G_MEMSET = 301, // GenericOpcodes.td:1797
317 G_BZERO = 302, // GenericOpcodes.td:1804
318 G_TRAP = 303, // GenericOpcodes.td:1814
319 G_DEBUGTRAP = 304, // GenericOpcodes.td:1821
320 G_UBSANTRAP = 305, // GenericOpcodes.td:1827
321 G_VECREDUCE_SEQ_FADD = 306, // GenericOpcodes.td:1726
322 G_VECREDUCE_SEQ_FMUL = 307, // GenericOpcodes.td:1732
323 G_VECREDUCE_FADD = 308, // GenericOpcodes.td:1738
324 G_VECREDUCE_FMUL = 309, // GenericOpcodes.td:1739
325 G_VECREDUCE_FMAX = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMIN = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_FMAXIMUM = 312, // GenericOpcodes.td:1743
328 G_VECREDUCE_FMINIMUM = 313, // GenericOpcodes.td:1744
329 G_VECREDUCE_ADD = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_MUL = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_AND = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_OR = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_XOR = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_SMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_SMIN = 320, // GenericOpcodes.td:1752
336 G_VECREDUCE_UMAX = 321, // GenericOpcodes.td:1753
337 G_VECREDUCE_UMIN = 322, // GenericOpcodes.td:1754
338 G_SBFX = 323, // GenericOpcodes.td:1839
339 G_UBFX = 324, // GenericOpcodes.td:1847
340 BRANCH = 325, // R600Instructions.td:1594
341 BRANCH_COND_f32 = 326, // R600Instructions.td:1567
342 BRANCH_COND_i32 = 327, // R600Instructions.td:1563
343 BREAK = 328, // R600Instructions.td:1608
344 BREAKC_f32 = 329, // R600Instructions.td:1584
345 BREAKC_i32 = 330, // R600Instructions.td:1582
346 BREAK_LOGICALNZ_f32 = 331, // R600Instructions.td:1577
347 BREAK_LOGICALNZ_i32 = 332, // R600Instructions.td:1575
348 BREAK_LOGICALZ_f32 = 333, // R600Instructions.td:1577
349 BREAK_LOGICALZ_i32 = 334, // R600Instructions.td:1575
350 CONST_COPY = 335, // R600Instructions.td:1439
351 CONTINUE = 336, // R600Instructions.td:1610
352 CONTINUEC_f32 = 337, // R600Instructions.td:1584
353 CONTINUEC_i32 = 338, // R600Instructions.td:1582
354 CONTINUE_LOGICALNZ_f32 = 339, // R600Instructions.td:1577
355 CONTINUE_LOGICALNZ_i32 = 340, // R600Instructions.td:1575
356 CONTINUE_LOGICALZ_f32 = 341, // R600Instructions.td:1577
357 CONTINUE_LOGICALZ_i32 = 342, // R600Instructions.td:1575
358 CUBE_eg_pseudo = 343, // R600Instructions.td:1074
359 CUBE_r600_pseudo = 344, // R600Instructions.td:1074
360 DEFAULT = 345, // R600Instructions.td:1612
361 DOT_4 = 346, // R600Instructions.td:1061
362 DUMMY_CHAIN = 347, // R600Instructions.td:792
363 ELSE = 348, // R600Instructions.td:1614
364 END = 349, // R600Instructions.td:1620
365 ENDFUNC = 350, // R600Instructions.td:1622
366 ENDIF = 351, // R600Instructions.td:1624
367 ENDLOOP = 352, // R600Instructions.td:1628
368 ENDMAIN = 353, // R600Instructions.td:1618
369 ENDSWITCH = 354, // R600Instructions.td:1616
370 FABS_R600 = 355, // R600Instructions.td:1204
371 FNEG_R600 = 356, // R600Instructions.td:1205
372 FUNC = 357, // R600Instructions.td:1630
373 IFC_f32 = 358, // R600Instructions.td:1584
374 IFC_i32 = 359, // R600Instructions.td:1582
375 IF_LOGICALNZ_f32 = 360, // R600Instructions.td:1577
376 IF_LOGICALNZ_i32 = 361, // R600Instructions.td:1575
377 IF_LOGICALZ_f32 = 362, // R600Instructions.td:1577
378 IF_LOGICALZ_i32 = 363, // R600Instructions.td:1575
379 IF_PREDICATE_SET = 364, // R600Instructions.td:1604
380 JUMP = 365, // R600Instructions.td:1385
381 JUMP_COND = 366, // R600Instructions.td:1378
382 MASK_WRITE = 367, // R600Instructions.td:1402
383 MOV_IMM_F32 = 368, // R600Instructions.td:827
384 MOV_IMM_GLOBAL_ADDR = 369, // R600Instructions.td:820
385 MOV_IMM_I32 = 370, // R600Instructions.td:814
386 PRED_X = 371, // R600Instructions.td:1370
387 R600_EXTRACT_ELT_V2 = 372, // R600Instructions.td:1677
388 R600_EXTRACT_ELT_V4 = 373, // R600Instructions.td:1678
389 R600_INSERT_ELT_V2 = 374, // R600Instructions.td:1680
390 R600_INSERT_ELT_V4 = 375, // R600Instructions.td:1681
391 R600_RegisterLoad = 376, // R600Instructions.td:698
392 R600_RegisterStore = 377, // R600Instructions.td:707
393 RETDYN = 378, // R600Instructions.td:1632
394 RETURN = 379, // R600Instructions.td:88
395 TXD = 380, // R600Instructions.td:1413
396 TXD_SHADOW = 381, // R600Instructions.td:1422
397 WHILELOOP = 382, // R600Instructions.td:1626
398 ADD = 383, // R600Instructions.td:721
399 ADDC_UINT = 384, // EvergreenInstructions.td:526
400 ADD_INT = 385, // R600Instructions.td:848
401 ALU_CLAUSE = 386, // R600Instructions.td:646
402 AND_INT = 387, // R600Instructions.td:844
403 ASHR_eg = 388, // EvergreenInstructions.td:511
404 ASHR_r600 = 389, // R600Instructions.td:1253
405 BCNT_INT = 390, // EvergreenInstructions.td:531
406 BFE_INT_eg = 391, // EvergreenInstructions.td:370
407 BFE_UINT_eg = 392, // EvergreenInstructions.td:365
408 BFI_INT_eg = 393, // EvergreenInstructions.td:411
409 BFM_INT_eg = 394, // EvergreenInstructions.td:492
410 BIT_ALIGN_INT_eg = 395, // EvergreenInstructions.td:503
411 CEIL = 396, // R600Instructions.td:781
412 CF_ALU = 397, // R600Instructions.td:631
413 CF_ALU_BREAK = 398, // R600Instructions.td:635
414 CF_ALU_CONTINUE = 399, // R600Instructions.td:634
415 CF_ALU_ELSE_AFTER = 400, // R600Instructions.td:636
416 CF_ALU_POP_AFTER = 401, // R600Instructions.td:633
417 CF_ALU_PUSH_BEFORE = 402, // R600Instructions.td:632
418 CF_CALL_FS_EG = 403, // EvergreenInstructions.td:853
419 CF_CALL_FS_R600 = 404, // R600Instructions.td:1325
420 CF_CONTINUE_EG = 405, // EvergreenInstructions.td:836
421 CF_CONTINUE_R600 = 406, // R600Instructions.td:1307
422 CF_ELSE_EG = 407, // EvergreenInstructions.td:849
423 CF_ELSE_R600 = 408, // R600Instructions.td:1321
424 CF_END_CM = 409, // CaymanInstructions.td:66
425 CF_END_EG = 410, // EvergreenInstructions.td:862
426 CF_END_R600 = 411, // R600Instructions.td:1334
427 CF_JUMP_EG = 412, // EvergreenInstructions.td:841
428 CF_JUMP_R600 = 413, // R600Instructions.td:1312
429 CF_PUSH_EG = 414, // EvergreenInstructions.td:845
430 CF_PUSH_ELSE_R600 = 415, // R600Instructions.td:1316
431 CF_TC_EG = 416, // EvergreenInstructions.td:814
432 CF_TC_R600 = 417, // R600Instructions.td:1285
433 CF_VC_EG = 418, // EvergreenInstructions.td:818
434 CF_VC_R600 = 419, // R600Instructions.td:1289
435 CNDE_INT = 420, // R600Instructions.td:890
436 CNDE_eg = 421, // EvergreenInstructions.td:514
437 CNDE_r600 = 422, // R600Instructions.td:1235
438 CNDGE_INT = 423, // R600Instructions.td:895
439 CNDGE_eg = 424, // EvergreenInstructions.td:516
440 CNDGE_r600 = 425, // R600Instructions.td:1237
441 CNDGT_INT = 426, // R600Instructions.td:900
442 CNDGT_eg = 427, // EvergreenInstructions.td:515
443 CNDGT_r600 = 428, // R600Instructions.td:1236
444 COS_cm = 429, // CaymanInstructions.td:48
445 COS_eg = 430, // EvergreenInstructions.td:132
446 COS_r600 = 431, // R600Instructions.td:1252
447 COS_r700 = 432, // R700Instructions.td:19
448 CUBE_eg_real = 433, // R600Instructions.td:1085
449 CUBE_r600_real = 434, // R600Instructions.td:1085
450 DOT4_eg = 435, // EvergreenInstructions.td:522
451 DOT4_r600 = 436, // R600Instructions.td:1238
452 EG_ExportBuf = 437, // EvergreenInstructions.td:804
453 EG_ExportSwz = 438, // EvergreenInstructions.td:794
454 END_LOOP_EG = 439, // EvergreenInstructions.td:827
455 END_LOOP_R600 = 440, // R600Instructions.td:1298
456 EXP_IEEE_cm = 441, // CaymanInstructions.td:43
457 EXP_IEEE_eg = 442, // EvergreenInstructions.td:125
458 EXP_IEEE_r600 = 443, // R600Instructions.td:1240
459 FETCH_CLAUSE = 444, // R600Instructions.td:638
460 FFBH_UINT = 445, // EvergreenInstructions.td:532
461 FFBL_INT = 446, // EvergreenInstructions.td:533
462 FLOOR = 447, // R600Instructions.td:783
463 FLT16_TO_FLT32 = 448, // EvergreenInstructions.td:530
464 FLT32_TO_FLT16 = 449, // EvergreenInstructions.td:529
465 FLT_TO_INT_eg = 450, // EvergreenInstructions.td:539
466 FLT_TO_INT_r600 = 451, // R600Instructions.td:1247
467 FLT_TO_UINT_eg = 452, // EvergreenInstructions.td:546
468 FLT_TO_UINT_r600 = 453, // R600Instructions.td:1249
469 FMA_eg = 454, // EvergreenInstructions.td:510
470 FRACT = 455, // R600Instructions.td:779
471 GROUP_BARRIER = 456, // EvergreenInstructions.td:552
472 INTERP_LOAD_P0 = 457, // R600Instructions.td:445
473 INTERP_PAIR_XY = 458, // R600Instructions.td:367
474 INTERP_PAIR_ZW = 459, // R600Instructions.td:373
475 INTERP_VEC_LOAD = 460, // R600Instructions.td:430
476 INTERP_XY = 461, // R600Instructions.td:437
477 INTERP_ZW = 462, // R600Instructions.td:441
478 INT_TO_FLT_eg = 463, // EvergreenInstructions.td:544
479 INT_TO_FLT_r600 = 464, // R600Instructions.td:1248
480 KILLGT = 465, // R600Instructions.td:840
481 LDS_ADD = 466, // EvergreenInstructions.td:690
482 LDS_ADD_RET = 467, // EvergreenInstructions.td:710
483 LDS_AND = 468, // EvergreenInstructions.td:692
484 LDS_AND_RET = 469, // EvergreenInstructions.td:716
485 LDS_BYTE_READ_RET = 470, // EvergreenInstructions.td:746
486 LDS_BYTE_WRITE = 471, // EvergreenInstructions.td:704
487 LDS_CMPST = 472, // EvergreenInstructions.td:696
488 LDS_CMPST_RET = 473, // EvergreenInstructions.td:740
489 LDS_MAX_INT = 474, // EvergreenInstructions.td:698
490 LDS_MAX_INT_RET = 475, // EvergreenInstructions.td:728
491 LDS_MAX_UINT = 476, // EvergreenInstructions.td:700
492 LDS_MAX_UINT_RET = 477, // EvergreenInstructions.td:734
493 LDS_MIN_INT = 478, // EvergreenInstructions.td:697
494 LDS_MIN_INT_RET = 479, // EvergreenInstructions.td:725
495 LDS_MIN_UINT = 480, // EvergreenInstructions.td:699
496 LDS_MIN_UINT_RET = 481, // EvergreenInstructions.td:731
497 LDS_OR = 482, // EvergreenInstructions.td:693
498 LDS_OR_RET = 483, // EvergreenInstructions.td:719
499 LDS_READ_RET = 484, // EvergreenInstructions.td:743
500 LDS_SHORT_READ_RET = 485, // EvergreenInstructions.td:752
501 LDS_SHORT_WRITE = 486, // EvergreenInstructions.td:707
502 LDS_SUB = 487, // EvergreenInstructions.td:691
503 LDS_SUB_RET = 488, // EvergreenInstructions.td:713
504 LDS_UBYTE_READ_RET = 489, // EvergreenInstructions.td:749
505 LDS_USHORT_READ_RET = 490, // EvergreenInstructions.td:755
506 LDS_WRITE = 491, // EvergreenInstructions.td:701
507 LDS_WRXCHG = 492, // EvergreenInstructions.td:695
508 LDS_WRXCHG_RET = 493, // EvergreenInstructions.td:737
509 LDS_XOR = 494, // EvergreenInstructions.td:694
510 LDS_XOR_RET = 495, // EvergreenInstructions.td:722
511 LITERALS = 496, // R600Instructions.td:654
512 LOG_CLAMPED_eg = 497, // EvergreenInstructions.td:518
513 LOG_CLAMPED_r600 = 498, // R600Instructions.td:1241
514 LOG_IEEE_cm = 499, // CaymanInstructions.td:44
515 LOG_IEEE_eg = 500, // EvergreenInstructions.td:126
516 LOG_IEEE_r600 = 501, // R600Instructions.td:1242
517 LOOP_BREAK_EG = 502, // EvergreenInstructions.td:831
518 LOOP_BREAK_R600 = 503, // R600Instructions.td:1302
519 LSHL_eg = 504, // EvergreenInstructions.td:513
520 LSHL_r600 = 505, // R600Instructions.td:1255
521 LSHR_eg = 506, // EvergreenInstructions.td:512
522 LSHR_r600 = 507, // R600Instructions.td:1254
523 MAX = 508, // R600Instructions.td:726
524 MAX_DX10 = 509, // R600Instructions.td:731
525 MAX_INT = 510, // R600Instructions.td:850
526 MAX_UINT = 511, // R600Instructions.td:852
527 MIN = 512, // R600Instructions.td:727
528 MIN_DX10 = 513, // R600Instructions.td:732
529 MIN_INT = 514, // R600Instructions.td:851
530 MIN_UINT = 515, // R600Instructions.td:853
531 MOV = 516, // R600Instructions.td:785
532 MOVA_INT_eg = 517, // EvergreenInstructions.td:536
533 MUL = 518, // R600Instructions.td:723
534 MULADD_IEEE_eg = 519, // EvergreenInstructions.td:509
535 MULADD_IEEE_r600 = 520, // R600Instructions.td:1234
536 MULADD_INT24_cm = 521, // CaymanInstructions.td:22
537 MULADD_UINT24_eg = 522, // EvergreenInstructions.td:497
538 MULADD_eg = 523, // EvergreenInstructions.td:508
539 MULADD_r600 = 524, // R600Instructions.td:1233
540 MULHI_INT_cm = 525, // CaymanInstructions.td:36
541 MULHI_INT_cm24 = 526, // CaymanInstructions.td:39
542 MULHI_INT_eg = 527, // EvergreenInstructions.td:118
543 MULHI_INT_r600 = 528, // R600Instructions.td:1257
544 MULHI_UINT24_eg = 529, // EvergreenInstructions.td:121
545 MULHI_UINT_cm = 530, // CaymanInstructions.td:38
546 MULHI_UINT_cm24 = 531, // CaymanInstructions.td:40
547 MULHI_UINT_eg = 532, // EvergreenInstructions.td:120
548 MULHI_UINT_r600 = 533, // R600Instructions.td:1259
549 MULLO_INT_cm = 534, // CaymanInstructions.td:35
550 MULLO_INT_eg = 535, // EvergreenInstructions.td:117
551 MULLO_INT_r600 = 536, // R600Instructions.td:1256
552 MULLO_UINT_cm = 537, // CaymanInstructions.td:37
553 MULLO_UINT_eg = 538, // EvergreenInstructions.td:119
554 MULLO_UINT_r600 = 539, // R600Instructions.td:1258
555 MUL_IEEE = 540, // R600Instructions.td:724
556 MUL_INT24_cm = 541, // CaymanInstructions.td:25
557 MUL_LIT_eg = 542, // EvergreenInstructions.td:517
558 MUL_LIT_r600 = 543, // R600Instructions.td:1232
559 MUL_UINT24_eg = 544, // EvergreenInstructions.td:519
560 NOT_INT = 545, // R600Instructions.td:847
561 OR_INT = 546, // R600Instructions.td:845
562 PAD = 547, // R600Instructions.td:666
563 POP_EG = 548, // EvergreenInstructions.td:858
564 POP_R600 = 549, // R600Instructions.td:1330
565 PRED_SETE = 550, // R600Instructions.td:833
566 PRED_SETE_INT = 551, // R600Instructions.td:885
567 PRED_SETGE = 552, // R600Instructions.td:835
568 PRED_SETGE_INT = 553, // R600Instructions.td:887
569 PRED_SETGT = 554, // R600Instructions.td:834
570 PRED_SETGT_INT = 555, // R600Instructions.td:886
571 PRED_SETNE = 556, // R600Instructions.td:836
572 PRED_SETNE_INT = 557, // R600Instructions.td:888
573 R600_ExportBuf = 558, // R600Instructions.td:1276
574 R600_ExportSwz = 559, // R600Instructions.td:1267
575 RAT_ATOMIC_ADD_NORET = 560, // EvergreenInstructions.td:82
576 RAT_ATOMIC_ADD_RTN = 561, // EvergreenInstructions.td:78
577 RAT_ATOMIC_AND_NORET = 562, // EvergreenInstructions.td:82
578 RAT_ATOMIC_AND_RTN = 563, // EvergreenInstructions.td:78
579 RAT_ATOMIC_CMPXCHG_INT_NORET = 564, // EvergreenInstructions.td:82
580 RAT_ATOMIC_CMPXCHG_INT_RTN = 565, // EvergreenInstructions.td:78
581 RAT_ATOMIC_DEC_UINT_NORET = 566, // EvergreenInstructions.td:82
582 RAT_ATOMIC_DEC_UINT_RTN = 567, // EvergreenInstructions.td:78
583 RAT_ATOMIC_INC_UINT_NORET = 568, // EvergreenInstructions.td:82
584 RAT_ATOMIC_INC_UINT_RTN = 569, // EvergreenInstructions.td:78
585 RAT_ATOMIC_MAX_INT_NORET = 570, // EvergreenInstructions.td:82
586 RAT_ATOMIC_MAX_INT_RTN = 571, // EvergreenInstructions.td:78
587 RAT_ATOMIC_MAX_UINT_NORET = 572, // EvergreenInstructions.td:82
588 RAT_ATOMIC_MAX_UINT_RTN = 573, // EvergreenInstructions.td:78
589 RAT_ATOMIC_MIN_INT_NORET = 574, // EvergreenInstructions.td:82
590 RAT_ATOMIC_MIN_INT_RTN = 575, // EvergreenInstructions.td:78
591 RAT_ATOMIC_MIN_UINT_NORET = 576, // EvergreenInstructions.td:82
592 RAT_ATOMIC_MIN_UINT_RTN = 577, // EvergreenInstructions.td:78
593 RAT_ATOMIC_OR_NORET = 578, // EvergreenInstructions.td:82
594 RAT_ATOMIC_OR_RTN = 579, // EvergreenInstructions.td:78
595 RAT_ATOMIC_RSUB_NORET = 580, // EvergreenInstructions.td:82
596 RAT_ATOMIC_RSUB_RTN = 581, // EvergreenInstructions.td:78
597 RAT_ATOMIC_SUB_NORET = 582, // EvergreenInstructions.td:82
598 RAT_ATOMIC_SUB_RTN = 583, // EvergreenInstructions.td:78
599 RAT_ATOMIC_XCHG_INT_NORET = 584, // EvergreenInstructions.td:82
600 RAT_ATOMIC_XCHG_INT_RTN = 585, // EvergreenInstructions.td:78
601 RAT_ATOMIC_XOR_NORET = 586, // EvergreenInstructions.td:82
602 RAT_ATOMIC_XOR_RTN = 587, // EvergreenInstructions.td:78
603 RAT_MSKOR = 588, // EvergreenInstructions.td:67
604 RAT_STORE_DWORD128 = 589, // CaymanInstructions.td:84
605 RAT_STORE_DWORD32 = 590, // CaymanInstructions.td:82
606 RAT_STORE_DWORD64 = 591, // CaymanInstructions.td:83
607 RAT_STORE_TYPED_cm = 592, // CaymanInstructions.td:86
608 RAT_STORE_TYPED_eg = 593, // EvergreenInstructions.td:164
609 RAT_WRITE_CACHELESS_128_eg = 594, // EvergreenInstructions.td:158
610 RAT_WRITE_CACHELESS_32_eg = 595, // EvergreenInstructions.td:144
611 RAT_WRITE_CACHELESS_64_eg = 596, // EvergreenInstructions.td:151
612 RECIPSQRT_CLAMPED_cm = 597, // CaymanInstructions.td:42
613 RECIPSQRT_CLAMPED_eg = 598, // EvergreenInstructions.td:124
614 RECIPSQRT_CLAMPED_r600 = 599, // R600Instructions.td:1245
615 RECIPSQRT_IEEE_cm = 600, // CaymanInstructions.td:46
616 RECIPSQRT_IEEE_eg = 601, // EvergreenInstructions.td:128
617 RECIPSQRT_IEEE_r600 = 602, // R600Instructions.td:1246
618 RECIP_CLAMPED_cm = 603, // CaymanInstructions.td:45
619 RECIP_CLAMPED_eg = 604, // EvergreenInstructions.td:127
620 RECIP_CLAMPED_r600 = 605, // R600Instructions.td:1243
621 RECIP_IEEE_cm = 606, // CaymanInstructions.td:33
622 RECIP_IEEE_eg = 607, // EvergreenInstructions.td:114
623 RECIP_IEEE_r600 = 608, // R600Instructions.td:1244
624 RECIP_UINT_eg = 609, // EvergreenInstructions.td:123
625 RECIP_UINT_r600 = 610, // R600Instructions.td:1260
626 RNDNE = 611, // R600Instructions.td:782
627 SETE = 612, // R600Instructions.td:737
628 SETE_DX10 = 613, // R600Instructions.td:757
629 SETE_INT = 614, // R600Instructions.td:855
630 SETGE_DX10 = 615, // R600Instructions.td:767
631 SETGE_INT = 616, // R600Instructions.td:865
632 SETGE_UINT = 617, // R600Instructions.td:880
633 SETGT_DX10 = 618, // R600Instructions.td:762
634 SETGT_INT = 619, // R600Instructions.td:860
635 SETGT_UINT = 620, // R600Instructions.td:875
636 SETNE_DX10 = 621, // R600Instructions.td:773
637 SETNE_INT = 622, // R600Instructions.td:870
638 SGE = 623, // R600Instructions.td:747
639 SGT = 624, // R600Instructions.td:742
640 SIN_cm = 625, // CaymanInstructions.td:47
641 SIN_eg = 626, // EvergreenInstructions.td:131
642 SIN_r600 = 627, // R600Instructions.td:1251
643 SIN_r700 = 628, // R700Instructions.td:18
644 SNE = 629, // R600Instructions.td:752
645 SUBB_UINT = 630, // EvergreenInstructions.td:527
646 SUB_INT = 631, // R600Instructions.td:849
647 TEX_GET_GRADIENTS_H = 632, // R600Instructions.td:959
648 TEX_GET_GRADIENTS_V = 633, // R600Instructions.td:960
649 TEX_GET_TEXTURE_RESINFO = 634, // R600Instructions.td:958
650 TEX_LD = 635, // R600Instructions.td:954
651 TEX_LDPTR = 636, // R600Instructions.td:955
652 TEX_SAMPLE = 637, // R600Instructions.td:948
653 TEX_SAMPLE_C = 638, // R600Instructions.td:949
654 TEX_SAMPLE_C_G = 639, // R600Instructions.td:964
655 TEX_SAMPLE_C_L = 640, // R600Instructions.td:951
656 TEX_SAMPLE_C_LB = 641, // R600Instructions.td:953
657 TEX_SAMPLE_G = 642, // R600Instructions.td:963
658 TEX_SAMPLE_L = 643, // R600Instructions.td:950
659 TEX_SAMPLE_LB = 644, // R600Instructions.td:952
660 TEX_SET_GRADIENTS_H = 645, // R600Instructions.td:961
661 TEX_SET_GRADIENTS_V = 646, // R600Instructions.td:962
662 TEX_VTX_CONSTBUF = 647, // R600Instructions.td:1451
663 TEX_VTX_TEXBUF = 648, // R600Instructions.td:1505
664 TRUNC = 649, // R600Instructions.td:780
665 UINT_TO_FLT_eg = 650, // EvergreenInstructions.td:550
666 UINT_TO_FLT_r600 = 651, // R600Instructions.td:1250
667 VTX_READ_128_cm = 652, // CaymanInstructions.td:162
668 VTX_READ_128_eg = 653, // EvergreenInstructions.td:240
669 VTX_READ_16_cm = 654, // CaymanInstructions.td:120
670 VTX_READ_16_eg = 655, // EvergreenInstructions.td:195
671 VTX_READ_32_cm = 656, // CaymanInstructions.td:131
672 VTX_READ_32_eg = 657, // EvergreenInstructions.td:207
673 VTX_READ_64_cm = 658, // CaymanInstructions.td:151
674 VTX_READ_64_eg = 659, // EvergreenInstructions.td:228
675 VTX_READ_8_cm = 660, // CaymanInstructions.td:109
676 VTX_READ_8_eg = 661, // EvergreenInstructions.td:183
677 WHILE_LOOP_EG = 662, // EvergreenInstructions.td:822
678 WHILE_LOOP_R600 = 663, // R600Instructions.td:1293
679 XOR_INT = 664, // R600Instructions.td:846
680 INSTRUCTION_LIST_END = 665
681 };
682
683} // namespace llvm::R600
684
685#endif // GET_INSTRINFO_ENUM
686
687#ifdef GET_INSTRINFO_SCHED_ENUM
688#undef GET_INSTRINFO_SCHED_ENUM
689
690namespace llvm::R600::Sched {
691
692 enum {
693 NoInstrModel = 0,
694 NullALU = 1,
695 VecALU = 2,
696 AnyALU = 3,
697 TransALU = 4,
698 XALU = 5,
699 SCHED_LIST_END = 6
700 };
701
702} // namespace llvm::R600::Sched
703
704#endif // GET_INSTRINFO_SCHED_ENUM
705
706#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
707
708namespace llvm {
709
710struct R600InstrTable {
711 MCInstrDesc Insts[665];
712 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
713 MCPhysReg ImplicitOps[1];
714 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
715 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
716 MCOperandInfo OperandInfo[461];
717};
718} // namespace llvm
719
720#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
721
722#ifdef GET_INSTRINFO_MC_DESC
723#undef GET_INSTRINFO_MC_DESC
724
725namespace llvm {
726
727static_assert((sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
728static constexpr unsigned R600OpInfoBase = (sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) / sizeof(MCOperandInfo);
729
730extern const R600InstrTable R600Descs = {
731 {
732 { 664, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // XOR_INT
733 { 663, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_R600
734 { 662, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_EG
735 { 661, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_eg
736 { 660, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_cm
737 { 659, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_eg
738 { 658, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_cm
739 { 657, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_eg
740 { 656, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_cm
741 { 655, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_eg
742 { 654, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_cm
743 { 653, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_eg
744 { 652, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_cm
745 { 651, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_r600
746 { 650, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_eg
747 { 649, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // TRUNC
748 { 648, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL }, // TEX_VTX_TEXBUF
749 { 647, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0, 0x1000ULL }, // TEX_VTX_CONSTBUF
750 { 646, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_V
751 { 645, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_H
752 { 644, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_LB
753 { 643, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_L
754 { 642, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_G
755 { 641, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_LB
756 { 640, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_L
757 { 639, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_G
758 { 638, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C
759 { 637, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE
760 { 636, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LDPTR
761 { 635, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LD
762 { 634, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_TEXTURE_RESINFO
763 { 633, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_V
764 { 632, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_H
765 { 631, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUB_INT
766 { 630, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUBB_UINT
767 { 629, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SNE
768 { 628, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r700
769 { 627, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r600
770 { 626, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_eg
771 { 625, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // SIN_cm
772 { 624, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGT
773 { 623, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGE
774 { 622, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_INT
775 { 621, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_DX10
776 { 620, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_UINT
777 { 619, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_INT
778 { 618, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_DX10
779 { 617, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_UINT
780 { 616, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_INT
781 { 615, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_DX10
782 { 614, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_INT
783 { 613, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_DX10
784 { 612, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE
785 { 611, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RNDNE
786 { 610, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_r600
787 { 609, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_eg
788 { 608, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_r600
789 { 607, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_eg
790 { 606, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_IEEE_cm
791 { 605, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_r600
792 { 604, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_eg
793 { 603, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_CLAMPED_cm
794 { 602, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_r600
795 { 601, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_eg
796 { 600, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_IEEE_cm
797 { 599, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_r600
798 { 598, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_eg
799 { 597, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_CLAMPED_cm
800 { 596, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 423, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_64_eg
801 { 595, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 420, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_32_eg
802 { 594, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 417, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_128_eg
803 { 593, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_eg
804 { 592, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_cm
805 { 591, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 411, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD64
806 { 590, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 409, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD32
807 { 589, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD128
808 { 588, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_MSKOR
809 { 587, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_RTN
810 { 586, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_NORET
811 { 585, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_RTN
812 { 584, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_NORET
813 { 583, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_RTN
814 { 582, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_NORET
815 { 581, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_RTN
816 { 580, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_NORET
817 { 579, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_RTN
818 { 578, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_NORET
819 { 577, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_RTN
820 { 576, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_NORET
821 { 575, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_RTN
822 { 574, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_NORET
823 { 573, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_RTN
824 { 572, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_NORET
825 { 571, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_RTN
826 { 570, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_NORET
827 { 569, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_RTN
828 { 568, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_NORET
829 { 567, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_RTN
830 { 566, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_NORET
831 { 565, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_RTN
832 { 564, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_NORET
833 { 563, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_RTN
834 { 562, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_NORET
835 { 561, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_RTN
836 { 560, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_NORET
837 { 559, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportSwz
838 { 558, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportBuf
839 { 557, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE_INT
840 { 556, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE
841 { 555, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT_INT
842 { 554, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT
843 { 553, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE_INT
844 { 552, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE
845 { 551, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE_INT
846 { 550, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE
847 { 549, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_R600
848 { 548, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_EG
849 { 547, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PAD
850 { 546, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // OR_INT
851 { 545, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // NOT_INT
852 { 544, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_UINT24_eg
853 { 543, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_r600
854 { 542, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_eg
855 { 541, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_INT24_cm
856 { 540, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_IEEE
857 { 539, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_r600
858 { 538, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_eg
859 { 537, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_UINT_cm
860 { 536, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_r600
861 { 535, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_eg
862 { 534, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_INT_cm
863 { 533, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_r600
864 { 532, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_eg
865 { 531, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm24
866 { 530, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm
867 { 529, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT24_eg
868 { 528, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_r600
869 { 527, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_eg
870 { 526, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm24
871 { 525, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm
872 { 524, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_r600
873 { 523, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_eg
874 { 522, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_UINT24_eg
875 { 521, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_INT24_cm
876 { 520, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_r600
877 { 519, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_eg
878 { 518, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL
879 { 517, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL }, // MOVA_INT_eg
880 { 516, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // MOV
881 { 515, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_UINT
882 { 514, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_INT
883 { 513, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_DX10
884 { 512, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN
885 { 511, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_UINT
886 { 510, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_INT
887 { 509, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_DX10
888 { 508, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX
889 { 507, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_r600
890 { 506, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_eg
891 { 505, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_r600
892 { 504, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_eg
893 { 503, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_R600
894 { 502, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_EG
895 { 501, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_r600
896 { 500, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_eg
897 { 499, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // LOG_IEEE_cm
898 { 498, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_r600
899 { 497, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_eg
900 { 496, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LITERALS
901 { 495, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_XOR_RET
902 { 494, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_XOR
903 { 493, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_WRXCHG_RET
904 { 492, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_WRXCHG
905 { 491, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_WRITE
906 { 490, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_USHORT_READ_RET
907 { 489, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_UBYTE_READ_RET
908 { 488, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_SUB_RET
909 { 487, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_SUB
910 { 486, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_SHORT_WRITE
911 { 485, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_SHORT_READ_RET
912 { 484, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_READ_RET
913 { 483, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_OR_RET
914 { 482, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_OR
915 { 481, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_UINT_RET
916 { 480, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_UINT
917 { 479, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_INT_RET
918 { 478, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_INT
919 { 477, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_UINT_RET
920 { 476, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_UINT
921 { 475, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_INT_RET
922 { 474, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_INT
923 { 473, 13, 1, 0, 5, 0, 0, R600OpInfoBase + 391, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL }, // LDS_CMPST_RET
924 { 472, 12, 0, 0, 5, 0, 0, R600OpInfoBase + 379, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL }, // LDS_CMPST
925 { 471, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_BYTE_WRITE
926 { 470, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_BYTE_READ_RET
927 { 469, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_AND_RET
928 { 468, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_AND
929 { 467, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_ADD_RET
930 { 466, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_ADD
931 { 465, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL }, // KILLGT
932 { 464, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_r600
933 { 463, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_eg
934 { 462, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_ZW
935 { 461, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_XY
936 { 460, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 351, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_VEC_LOAD
937 { 459, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 346, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_ZW
938 { 458, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 341, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_XY
939 { 457, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INTERP_LOAD_P0
940 { 456, 0, 0, 0, 3, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL }, // GROUP_BARRIER
941 { 455, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FRACT
942 { 454, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // FMA_eg
943 { 453, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_r600
944 { 452, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_eg
945 { 451, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_r600
946 { 450, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_eg
947 { 449, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT32_TO_FLT16
948 { 448, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT16_TO_FLT32
949 { 447, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLOOR
950 { 446, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBL_INT
951 { 445, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBH_UINT
952 { 444, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FETCH_CLAUSE
953 { 443, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_r600
954 { 442, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_eg
955 { 441, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // EXP_IEEE_cm
956 { 440, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_R600
957 { 439, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_EG
958 { 438, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportSwz
959 { 437, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportBuf
960 { 436, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_r600
961 { 435, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_eg
962 { 434, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_r600_real
963 { 433, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_eg_real
964 { 432, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r700
965 { 431, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r600
966 { 430, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_eg
967 { 429, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // COS_cm
968 { 428, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_r600
969 { 427, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_eg
970 { 426, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_INT
971 { 425, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_r600
972 { 424, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_eg
973 { 423, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_INT
974 { 422, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_r600
975 { 421, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_eg
976 { 420, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_INT
977 { 419, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_R600
978 { 418, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_EG
979 { 417, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_R600
980 { 416, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_EG
981 { 415, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_ELSE_R600
982 { 414, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_EG
983 { 413, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_R600
984 { 412, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_EG
985 { 411, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_R600
986 { 410, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_EG
987 { 409, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_CM
988 { 408, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_R600
989 { 407, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_EG
990 { 406, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_R600
991 { 405, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_EG
992 { 404, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_R600
993 { 403, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_EG
994 { 402, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_PUSH_BEFORE
995 { 401, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_POP_AFTER
996 { 400, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_ELSE_AFTER
997 { 399, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_CONTINUE
998 { 398, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_BREAK
999 { 397, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU
1000 { 396, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // CEIL
1001 { 395, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BIT_ALIGN_INT_eg
1002 { 394, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // BFM_INT_eg
1003 { 393, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFI_INT_eg
1004 { 392, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_UINT_eg
1005 { 391, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_INT_eg
1006 { 390, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // BCNT_INT
1007 { 389, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_r600
1008 { 388, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_eg
1009 { 387, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // AND_INT
1010 { 386, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALU_CLAUSE
1011 { 385, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD_INT
1012 { 384, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADDC_UINT
1013 { 383, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD
1014 { 382, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // WHILELOOP
1015 { 381, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD_SHADOW
1016 { 380, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD
1017 { 379, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL }, // RETURN
1018 { 378, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // RETDYN
1019 { 377, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL }, // R600_RegisterStore
1020 { 376, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL }, // R600_RegisterLoad
1021 { 375, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 247, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V4
1022 { 374, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V2
1023 { 373, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V4
1024 { 372, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V2
1025 { 371, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 233, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // PRED_X
1026 { 370, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_I32
1027 { 369, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_GLOBAL_ADDR
1028 { 368, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_F32
1029 { 367, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MASK_WRITE
1030 { 366, 2, 0, 0, 3, 0, 0, R600OpInfoBase + 231, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP_COND
1031 { 365, 1, 0, 0, 3, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP
1032 { 364, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // IF_PREDICATE_SET
1033 { 363, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_i32
1034 { 362, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_f32
1035 { 361, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_i32
1036 { 360, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_f32
1037 { 359, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_i32
1038 { 358, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_f32
1039 { 357, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // FUNC
1040 { 356, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FNEG_R600
1041 { 355, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FABS_R600
1042 { 354, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDSWITCH
1043 { 353, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDMAIN
1044 { 352, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDLOOP
1045 { 351, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDIF
1046 { 350, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDFUNC
1047 { 349, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // END
1048 { 348, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ELSE
1049 { 347, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // DUMMY_CHAIN
1050 { 346, 71, 1, 0, 3, 0, 0, R600OpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // DOT_4
1051 { 345, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // DEFAULT
1052 { 344, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_r600_pseudo
1053 { 343, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_eg_pseudo
1054 { 342, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_i32
1055 { 341, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_f32
1056 { 340, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_i32
1057 { 339, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_f32
1058 { 338, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_i32
1059 { 337, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_f32
1060 { 336, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE
1061 { 335, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // CONST_COPY
1062 { 334, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_i32
1063 { 333, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_f32
1064 { 332, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_i32
1065 { 331, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_f32
1066 { 330, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_i32
1067 { 329, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_f32
1068 { 328, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK
1069 { 327, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_i32
1070 { 326, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_f32
1071 { 325, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH
1072 { 324, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX
1073 { 323, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX
1074 { 322, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN
1075 { 321, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX
1076 { 320, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN
1077 { 319, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX
1078 { 318, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR
1079 { 317, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR
1080 { 316, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND
1081 { 315, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL
1082 { 314, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD
1083 { 313, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1084 { 312, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1085 { 311, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN
1086 { 310, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX
1087 { 309, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL
1088 { 308, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD
1089 { 307, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1090 { 306, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1091 { 305, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP
1092 { 304, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP
1093 { 303, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP
1094 { 302, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO
1095 { 301, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET
1096 { 300, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE
1097 { 299, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE
1098 { 298, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY
1099 { 297, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1100 { 296, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1101 { 295, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP
1102 { 294, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT
1103 { 293, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA
1104 { 292, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM
1105 { 291, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV
1106 { 290, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL
1107 { 289, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB
1108 { 288, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD
1109 { 287, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE
1110 { 286, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE
1111 { 285, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC
1112 { 284, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE
1113 { 283, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR
1114 { 282, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST
1115 { 281, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT
1116 { 280, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT
1117 { 279, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR
1118 { 278, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT
1119 { 277, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH
1120 { 276, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH
1121 { 275, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH
1122 { 274, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2
1123 { 273, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN
1124 { 272, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN
1125 { 271, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS
1126 { 270, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN
1127 { 269, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS
1128 { 268, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN
1129 { 267, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS
1130 { 266, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL
1131 { 265, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE
1132 { 264, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP
1133 { 263, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP
1134 { 262, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS
1135 { 261, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
1136 { 260, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ
1137 { 259, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
1138 { 258, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ
1139 { 257, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS
1140 { 256, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR
1141 { 255, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR
1142 { 254, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR
1143 { 253, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1144 { 252, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT
1145 { 251, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1146 { 250, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR
1147 { 249, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE
1148 { 248, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT
1149 { 247, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR
1150 { 246, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND
1151 { 245, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND
1152 { 244, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS
1153 { 243, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX
1154 { 242, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN
1155 { 241, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX
1156 { 240, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN
1157 { 239, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK
1158 { 238, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD
1159 { 237, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING
1160 { 236, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING
1161 { 235, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE
1162 { 234, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE
1163 { 233, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE
1164 { 232, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV
1165 { 231, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV
1166 { 230, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV
1167 { 229, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM
1168 { 228, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM
1169 { 227, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM
1170 { 226, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM
1171 { 225, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE
1172 { 224, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE
1173 { 223, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM
1174 { 222, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM
1175 { 221, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE
1176 { 220, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS
1177 { 219, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN
1178 { 218, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS
1179 { 217, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT
1180 { 216, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT
1181 { 215, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP
1182 { 214, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP
1183 { 213, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI
1184 { 212, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI
1185 { 211, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC
1186 { 210, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT
1187 { 209, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG
1188 { 208, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP
1189 { 207, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP
1190 { 206, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10
1191 { 205, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2
1192 { 204, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG
1193 { 203, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10
1194 { 202, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2
1195 { 201, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP
1196 { 200, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI
1197 { 199, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW
1198 { 198, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF
1199 { 197, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM
1200 { 196, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV
1201 { 195, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD
1202 { 194, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA
1203 { 193, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL
1204 { 192, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB
1205 { 191, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD
1206 { 190, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT
1207 { 189, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT
1208 { 188, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX
1209 { 187, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX
1210 { 186, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT
1211 { 185, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT
1212 { 184, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX
1213 { 183, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX
1214 { 182, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT
1215 { 181, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT
1216 { 180, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT
1217 { 179, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT
1218 { 178, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT
1219 { 177, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT
1220 { 176, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH
1221 { 175, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH
1222 { 174, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO
1223 { 173, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO
1224 { 172, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE
1225 { 171, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO
1226 { 170, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE
1227 { 169, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO
1228 { 168, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE
1229 { 167, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO
1230 { 166, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE
1231 { 165, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO
1232 { 164, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT
1233 { 163, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP
1234 { 162, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP
1235 { 161, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP
1236 { 160, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP
1237 { 159, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL
1238 { 158, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR
1239 { 157, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR
1240 { 156, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL
1241 { 155, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR
1242 { 154, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR
1243 { 153, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL
1244 { 152, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT
1245 { 151, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG
1246 { 150, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT
1247 { 149, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG
1248 { 148, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART
1249 { 147, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT
1250 { 146, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT
1251 { 145, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U
1252 { 144, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U
1253 { 143, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S
1254 { 142, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC
1255 { 141, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT
1256 { 140, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1257 { 139, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1258 { 138, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1259 { 137, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC
1260 { 136, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START
1261 { 135, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT
1262 { 134, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND
1263 { 133, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH
1264 { 132, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE
1265 { 131, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1266 { 130, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1267 { 129, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1268 { 128, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1269 { 127, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1270 { 126, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1271 { 125, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1272 { 124, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1273 { 123, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN
1274 { 122, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX
1275 { 121, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB
1276 { 120, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD
1277 { 119, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN
1278 { 118, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX
1279 { 117, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN
1280 { 116, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX
1281 { 115, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR
1282 { 114, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR
1283 { 113, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND
1284 { 112, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND
1285 { 111, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB
1286 { 110, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD
1287 { 109, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG
1288 { 108, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG
1289 { 107, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1290 { 106, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE
1291 { 105, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE
1292 { 104, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1293 { 103, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD
1294 { 102, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD
1295 { 101, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD
1296 { 100, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD
1297 { 99, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD
1298 { 98, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER
1299 { 97, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER
1300 { 96, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1301 { 95, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT
1302 { 94, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT
1303 { 93, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND
1304 { 92, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC
1305 { 91, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1306 { 90, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1307 { 89, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE
1308 { 88, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST
1309 { 87, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR
1310 { 86, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT
1311 { 85, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS
1312 { 84, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1313 { 83, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR
1314 { 82, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES
1315 { 81, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT
1316 { 80, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES
1317 { 79, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT
1318 { 78, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL
1319 { 77, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1320 { 76, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE
1321 { 75, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX
1322 { 74, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI
1323 { 73, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF
1324 { 72, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL
1325 { 71, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR
1326 { 70, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL
1327 { 69, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR
1328 { 68, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU
1329 { 67, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS
1330 { 66, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR
1331 { 65, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR
1332 { 64, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND
1333 { 63, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM
1334 { 62, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM
1335 { 61, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM
1336 { 60, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM
1337 { 59, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV
1338 { 58, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV
1339 { 57, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL
1340 { 56, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB
1341 { 55, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD
1342 { 54, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN
1343 { 53, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT
1344 { 52, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT
1345 { 51, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1346 { 50, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1347 { 49, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1348 { 48, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1349 { 47, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE
1350 { 46, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1351 { 45, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER
1352 { 44, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE
1353 { 43, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1354 { 42, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_13817
1355 { 41, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_13816
1356 { 40, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL
1357 { 39, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1358 { 38, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET
1359 { 37, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1360 { 36, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP
1361 { 35, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP
1362 { 34, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE
1363 { 33, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT
1364 { 32, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_13815
1365 { 31, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP
1366 { 30, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_13542
1367 { 29, 6, 1, 0, 0, 0, 0, R600OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT
1368 { 28, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL
1369 { 27, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP
1370 { 26, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE
1371 { 25, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE
1372 { 24, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END
1373 { 23, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START
1374 { 22, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE
1375 { 21, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK
1376 { 20, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY
1377 { 19, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE
1378 { 18, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL
1379 { 17, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI
1380 { 16, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF
1381 { 15, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST
1382 { 14, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE
1383 { 13, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS
1384 { 12, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG
1385 { 11, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF
1386 { 10, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF
1387 { 9, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG
1388 { 8, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG
1389 { 7, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL
1390 { 6, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL
1391 { 5, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL
1392 { 4, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL
1393 { 3, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION
1394 { 2, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR
1395 { 1, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM
1396 { 0, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI
1397 }, {
1398 /* 0 */
1399 }, {
1400 0
1401 }, {
1402 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1403 /* 1 */
1404 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1405 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1406 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1407 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1408 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1409 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1410 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1411 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1412 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1413 /* 28 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1414 /* 29 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1415 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1416 /* 34 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1417 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1418 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1419 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1420 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1421 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1422 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1423 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1424 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1425 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1426 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1427 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1428 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1429 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1430 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1431 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1432 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1433 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1434 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1435 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1436 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1437 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1438 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1439 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1440 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1441 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1442 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1443 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1444 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1445 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1446 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1447 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1448 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1449 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1450 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1451 /* 153 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1452 /* 155 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1453 /* 156 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1454 /* 158 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1455 /* 160 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1456 /* 231 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1457 /* 233 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1458 /* 237 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1459 /* 240 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1460 /* 243 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1461 /* 247 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1462 /* 251 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1463 /* 255 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1464 /* 262 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1465 /* 283 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1466 /* 297 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1467 /* 316 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1468 /* 325 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1469 /* 332 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1470 /* 341 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1471 /* 346 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1472 /* 351 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1473 /* 353 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1474 /* 362 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1475 /* 372 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1476 /* 379 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1477 /* 391 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1478 /* 404 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1479 /* 407 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1480 /* 409 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1481 /* 411 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1482 /* 413 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1483 /* 417 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1484 /* 420 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1485 /* 423 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1486 /* 426 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1487 /* 445 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1488 /* 449 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1489 /* 453 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1490 /* 457 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1491 }
1492};
1493
1494
1495#ifdef __GNUC__
1496#pragma GCC diagnostic push
1497#pragma GCC diagnostic ignored "-Woverlength-strings"
1498#endif
1499extern const char R600InstrNameData[] = {
1500 /* 0 */ "CF_TC_R600\000"
1501 /* 11 */ "CF_VC_R600\000"
1502 /* 22 */ "CF_END_R600\000"
1503 /* 34 */ "CF_ELSE_R600\000"
1504 /* 47 */ "CF_PUSH_ELSE_R600\000"
1505 /* 65 */ "CF_CONTINUE_R600\000"
1506 /* 82 */ "FNEG_R600\000"
1507 /* 92 */ "LOOP_BREAK_R600\000"
1508 /* 108 */ "CF_JUMP_R600\000"
1509 /* 121 */ "END_LOOP_R600\000"
1510 /* 135 */ "WHILE_LOOP_R600\000"
1511 /* 151 */ "POP_R600\000"
1512 /* 160 */ "FABS_R600\000"
1513 /* 170 */ "CF_CALL_FS_R600\000"
1514 /* 186 */ "DOT4_r600\000"
1515 /* 196 */ "MULADD_r600\000"
1516 /* 208 */ "LOG_CLAMPED_r600\000"
1517 /* 225 */ "RECIP_CLAMPED_r600\000"
1518 /* 244 */ "RECIPSQRT_CLAMPED_r600\000"
1519 /* 267 */ "CNDE_r600\000"
1520 /* 277 */ "MULADD_IEEE_r600\000"
1521 /* 294 */ "LOG_IEEE_r600\000"
1522 /* 308 */ "RECIP_IEEE_r600\000"
1523 /* 324 */ "EXP_IEEE_r600\000"
1524 /* 338 */ "RECIPSQRT_IEEE_r600\000"
1525 /* 358 */ "CNDGE_r600\000"
1526 /* 369 */ "LSHL_r600\000"
1527 /* 379 */ "SIN_r600\000"
1528 /* 388 */ "ASHR_r600\000"
1529 /* 398 */ "LSHR_r600\000"
1530 /* 408 */ "COS_r600\000"
1531 /* 417 */ "CNDGT_r600\000"
1532 /* 428 */ "MUL_LIT_r600\000"
1533 /* 441 */ "UINT_TO_FLT_r600\000"
1534 /* 458 */ "MULHI_UINT_r600\000"
1535 /* 474 */ "MULLO_UINT_r600\000"
1536 /* 490 */ "FLT_TO_UINT_r600\000"
1537 /* 507 */ "RECIP_UINT_r600\000"
1538 /* 523 */ "MULHI_INT_r600\000"
1539 /* 538 */ "MULLO_INT_r600\000"
1540 /* 553 */ "FLT_TO_INT_r600\000"
1541 /* 569 */ "SIN_r700\000"
1542 /* 578 */ "COS_r700\000"
1543 /* 587 */ "G_FLOG10\000"
1544 /* 596 */ "G_FEXP10\000"
1545 /* 605 */ "SETGE_DX10\000"
1546 /* 616 */ "SETNE_DX10\000"
1547 /* 627 */ "SETE_DX10\000"
1548 /* 637 */ "MIN_DX10\000"
1549 /* 646 */ "SETGT_DX10\000"
1550 /* 657 */ "MAX_DX10\000"
1551 /* 666 */ "INTERP_LOAD_P0\000"
1552 /* 681 */ "RAT_STORE_DWORD32\000"
1553 /* 699 */ "MOV_IMM_F32\000"
1554 /* 711 */ "MOV_IMM_I32\000"
1555 /* 723 */ "FLT16_TO_FLT32\000"
1556 /* 738 */ "CONTINUEC_f32\000"
1557 /* 752 */ "IFC_f32\000"
1558 /* 760 */ "BREAKC_f32\000"
1559 /* 771 */ "BRANCH_COND_f32\000"
1560 /* 787 */ "CONTINUE_LOGICALZ_f32\000"
1561 /* 809 */ "IF_LOGICALZ_f32\000"
1562 /* 825 */ "BREAK_LOGICALZ_f32\000"
1563 /* 844 */ "CONTINUE_LOGICALNZ_f32\000"
1564 /* 867 */ "IF_LOGICALNZ_f32\000"
1565 /* 884 */ "BREAK_LOGICALNZ_f32\000"
1566 /* 904 */ "CONTINUEC_i32\000"
1567 /* 918 */ "IFC_i32\000"
1568 /* 926 */ "BREAKC_i32\000"
1569 /* 937 */ "BRANCH_COND_i32\000"
1570 /* 953 */ "CONTINUE_LOGICALZ_i32\000"
1571 /* 975 */ "IF_LOGICALZ_i32\000"
1572 /* 991 */ "BREAK_LOGICALZ_i32\000"
1573 /* 1010 */ "CONTINUE_LOGICALNZ_i32\000"
1574 /* 1033 */ "IF_LOGICALNZ_i32\000"
1575 /* 1050 */ "BREAK_LOGICALNZ_i32\000"
1576 /* 1070 */ "G_FLOG2\000"
1577 /* 1078 */ "G_FATAN2\000"
1578 /* 1087 */ "G_FEXP2\000"
1579 /* 1095 */ "R600_EXTRACT_ELT_V2\000"
1580 /* 1115 */ "R600_INSERT_ELT_V2\000"
1581 /* 1134 */ "MULHI_UINT_cm24\000"
1582 /* 1150 */ "MULHI_INT_cm24\000"
1583 /* 1165 */ "RAT_STORE_DWORD64\000"
1584 /* 1183 */ "R600_EXTRACT_ELT_V4\000"
1585 /* 1203 */ "R600_INSERT_ELT_V4\000"
1586 /* 1222 */ "DOT_4\000"
1587 /* 1228 */ "FLT32_TO_FLT16\000"
1588 /* 1243 */ "RAT_STORE_DWORD128\000"
1589 /* 1262 */ "G_FMA\000"
1590 /* 1268 */ "G_STRICT_FMA\000"
1591 /* 1281 */ "TEX_SAMPLE_C_LB\000"
1592 /* 1297 */ "TEX_SAMPLE_LB\000"
1593 /* 1311 */ "G_FSUB\000"
1594 /* 1318 */ "G_STRICT_FSUB\000"
1595 /* 1332 */ "G_ATOMICRMW_FSUB\000"
1596 /* 1349 */ "G_SUB\000"
1597 /* 1355 */ "LDS_SUB\000"
1598 /* 1363 */ "G_ATOMICRMW_SUB\000"
1599 /* 1379 */ "G_INTRINSIC\000"
1600 /* 1391 */ "ENDFUNC\000"
1601 /* 1399 */ "G_FPTRUNC\000"
1602 /* 1409 */ "G_INTRINSIC_TRUNC\000"
1603 /* 1427 */ "G_TRUNC\000"
1604 /* 1435 */ "G_BUILD_VECTOR_TRUNC\000"
1605 /* 1456 */ "G_DYN_STACKALLOC\000"
1606 /* 1473 */ "TEX_SAMPLE_C\000"
1607 /* 1486 */ "G_FMAD\000"
1608 /* 1493 */ "G_INDEXED_SEXTLOAD\000"
1609 /* 1512 */ "G_SEXTLOAD\000"
1610 /* 1523 */ "G_INDEXED_ZEXTLOAD\000"
1611 /* 1542 */ "G_ZEXTLOAD\000"
1612 /* 1553 */ "INTERP_VEC_LOAD\000"
1613 /* 1569 */ "G_INDEXED_LOAD\000"
1614 /* 1584 */ "G_LOAD\000"
1615 /* 1591 */ "PAD\000"
1616 /* 1595 */ "G_VECREDUCE_FADD\000"
1617 /* 1612 */ "G_FADD\000"
1618 /* 1619 */ "G_VECREDUCE_SEQ_FADD\000"
1619 /* 1640 */ "G_STRICT_FADD\000"
1620 /* 1654 */ "G_ATOMICRMW_FADD\000"
1621 /* 1671 */ "G_VECREDUCE_ADD\000"
1622 /* 1687 */ "G_ADD\000"
1623 /* 1693 */ "G_PTR_ADD\000"
1624 /* 1703 */ "LDS_ADD\000"
1625 /* 1711 */ "G_ATOMICRMW_ADD\000"
1626 /* 1727 */ "TEX_LD\000"
1627 /* 1734 */ "G_ATOMICRMW_NAND\000"
1628 /* 1751 */ "G_VECREDUCE_AND\000"
1629 /* 1767 */ "G_AND\000"
1630 /* 1773 */ "LDS_AND\000"
1631 /* 1781 */ "G_ATOMICRMW_AND\000"
1632 /* 1797 */ "LIFETIME_END\000"
1633 /* 1810 */ "G_BRCOND\000"
1634 /* 1819 */ "G_ATOMICRMW_USUB_COND\000"
1635 /* 1841 */ "JUMP_COND\000"
1636 /* 1851 */ "G_LLROUND\000"
1637 /* 1861 */ "G_LROUND\000"
1638 /* 1870 */ "G_INTRINSIC_ROUND\000"
1639 /* 1888 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1640 /* 1914 */ "LOAD_STACK_GUARD\000"
1641 /* 1931 */ "TXD\000"
1642 /* 1935 */ "PSEUDO_PROBE\000"
1643 /* 1948 */ "G_SSUBE\000"
1644 /* 1956 */ "G_USUBE\000"
1645 /* 1964 */ "G_FENCE\000"
1646 /* 1972 */ "ARITH_FENCE\000"
1647 /* 1984 */ "REG_SEQUENCE\000"
1648 /* 1997 */ "G_SADDE\000"
1649 /* 2005 */ "G_UADDE\000"
1650 /* 2013 */ "G_GET_FPMODE\000"
1651 /* 2026 */ "G_RESET_FPMODE\000"
1652 /* 2041 */ "G_SET_FPMODE\000"
1653 /* 2054 */ "MUL_IEEE\000"
1654 /* 2063 */ "G_FMINNUM_IEEE\000"
1655 /* 2078 */ "G_FMAXNUM_IEEE\000"
1656 /* 2093 */ "SGE\000"
1657 /* 2097 */ "PRED_SETGE\000"
1658 /* 2108 */ "G_VSCALE\000"
1659 /* 2117 */ "G_JUMP_TABLE\000"
1660 /* 2130 */ "BUNDLE\000"
1661 /* 2137 */ "TEX_SAMPLE\000"
1662 /* 2148 */ "RNDNE\000"
1663 /* 2154 */ "G_MEMCPY_INLINE\000"
1664 /* 2170 */ "RELOC_NONE\000"
1665 /* 2181 */ "SNE\000"
1666 /* 2185 */ "PRED_SETNE\000"
1667 /* 2196 */ "LOCAL_ESCAPE\000"
1668 /* 2209 */ "CF_ALU_PUSH_BEFORE\000"
1669 /* 2228 */ "G_STACKRESTORE\000"
1670 /* 2243 */ "G_INDEXED_STORE\000"
1671 /* 2259 */ "G_STORE\000"
1672 /* 2267 */ "ELSE\000"
1673 /* 2272 */ "G_BITREVERSE\000"
1674 /* 2285 */ "FETCH_CLAUSE\000"
1675 /* 2298 */ "ALU_CLAUSE\000"
1676 /* 2309 */ "FAKE_USE\000"
1677 /* 2318 */ "PRED_SETE\000"
1678 /* 2328 */ "LDS_BYTE_WRITE\000"
1679 /* 2343 */ "MASK_WRITE\000"
1680 /* 2354 */ "LDS_WRITE\000"
1681 /* 2364 */ "LDS_SHORT_WRITE\000"
1682 /* 2380 */ "DBG_VALUE\000"
1683 /* 2390 */ "G_GLOBAL_VALUE\000"
1684 /* 2405 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1685 /* 2428 */ "CONVERGENCECTRL_GLUE\000"
1686 /* 2449 */ "CF_ALU_CONTINUE\000"
1687 /* 2465 */ "G_STACKSAVE\000"
1688 /* 2477 */ "G_MEMMOVE\000"
1689 /* 2487 */ "G_FREEZE\000"
1690 /* 2496 */ "G_FCANONICALIZE\000"
1691 /* 2512 */ "G_FMODF\000"
1692 /* 2520 */ "G_CTLZ_ZERO_UNDEF\000"
1693 /* 2538 */ "G_CTTZ_ZERO_UNDEF\000"
1694 /* 2556 */ "INIT_UNDEF\000"
1695 /* 2567 */ "G_IMPLICIT_DEF\000"
1696 /* 2582 */ "DBG_INSTR_REF\000"
1697 /* 2596 */ "ENDIF\000"
1698 /* 2602 */ "TEX_VTX_CONSTBUF\000"
1699 /* 2619 */ "TEX_VTX_TEXBUF\000"
1700 /* 2634 */ "G_FNEG\000"
1701 /* 2641 */ "EXTRACT_SUBREG\000"
1702 /* 2656 */ "INSERT_SUBREG\000"
1703 /* 2670 */ "G_SEXT_INREG\000"
1704 /* 2683 */ "SUBREG_TO_REG\000"
1705 /* 2697 */ "CF_TC_EG\000"
1706 /* 2706 */ "CF_VC_EG\000"
1707 /* 2715 */ "CF_END_EG\000"
1708 /* 2725 */ "CF_ELSE_EG\000"
1709 /* 2736 */ "CF_CONTINUE_EG\000"
1710 /* 2751 */ "CF_PUSH_EG\000"
1711 /* 2762 */ "LOOP_BREAK_EG\000"
1712 /* 2776 */ "CF_JUMP_EG\000"
1713 /* 2787 */ "END_LOOP_EG\000"
1714 /* 2799 */ "WHILE_LOOP_EG\000"
1715 /* 2813 */ "POP_EG\000"
1716 /* 2820 */ "CF_CALL_FS_EG\000"
1717 /* 2834 */ "G_ATOMIC_CMPXCHG\000"
1718 /* 2851 */ "LDS_WRXCHG\000"
1719 /* 2862 */ "G_ATOMICRMW_XCHG\000"
1720 /* 2879 */ "G_GET_ROUNDING\000"
1721 /* 2894 */ "G_SET_ROUNDING\000"
1722 /* 2909 */ "G_FLOG\000"
1723 /* 2916 */ "G_VAARG\000"
1724 /* 2924 */ "PREALLOCATED_ARG\000"
1725 /* 2941 */ "TEX_SAMPLE_C_G\000"
1726 /* 2956 */ "TEX_SAMPLE_G\000"
1727 /* 2969 */ "BRANCH\000"
1728 /* 2976 */ "G_PREFETCH\000"
1729 /* 2987 */ "ENDSWITCH\000"
1730 /* 2997 */ "G_SMULH\000"
1731 /* 3005 */ "G_UMULH\000"
1732 /* 3013 */ "G_FTANH\000"
1733 /* 3021 */ "G_FSINH\000"
1734 /* 3029 */ "G_FCOSH\000"
1735 /* 3037 */ "TEX_GET_GRADIENTS_H\000"
1736 /* 3057 */ "TEX_SET_GRADIENTS_H\000"
1737 /* 3077 */ "DBG_PHI\000"
1738 /* 3085 */ "G_FPTOSI\000"
1739 /* 3094 */ "G_FPTOUI\000"
1740 /* 3103 */ "G_FPOWI\000"
1741 /* 3111 */ "CF_ALU_BREAK\000"
1742 /* 3124 */ "COPY_LANEMASK\000"
1743 /* 3138 */ "G_PTRMASK\000"
1744 /* 3148 */ "GC_LABEL\000"
1745 /* 3157 */ "DBG_LABEL\000"
1746 /* 3167 */ "EH_LABEL\000"
1747 /* 3176 */ "ANNOTATION_LABEL\000"
1748 /* 3193 */ "ICALL_BRANCH_FUNNEL\000"
1749 /* 3213 */ "G_FSHL\000"
1750 /* 3220 */ "G_SHL\000"
1751 /* 3226 */ "G_FCEIL\000"
1752 /* 3234 */ "G_SAVGCEIL\000"
1753 /* 3245 */ "G_UAVGCEIL\000"
1754 /* 3256 */ "PATCHABLE_TAIL_CALL\000"
1755 /* 3276 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1756 /* 3303 */ "PATCHABLE_EVENT_CALL\000"
1757 /* 3324 */ "FENTRY_CALL\000"
1758 /* 3336 */ "KILL\000"
1759 /* 3341 */ "G_CONSTANT_POOL\000"
1760 /* 3357 */ "G_ROTL\000"
1761 /* 3364 */ "G_VECREDUCE_FMUL\000"
1762 /* 3381 */ "G_FMUL\000"
1763 /* 3388 */ "G_VECREDUCE_SEQ_FMUL\000"
1764 /* 3409 */ "G_STRICT_FMUL\000"
1765 /* 3423 */ "G_VECREDUCE_MUL\000"
1766 /* 3439 */ "G_MUL\000"
1767 /* 3445 */ "TEX_SAMPLE_C_L\000"
1768 /* 3460 */ "TEX_SAMPLE_L\000"
1769 /* 3473 */ "CF_END_CM\000"
1770 /* 3483 */ "G_FREM\000"
1771 /* 3490 */ "G_STRICT_FREM\000"
1772 /* 3504 */ "G_SREM\000"
1773 /* 3511 */ "G_UREM\000"
1774 /* 3518 */ "G_SDIVREM\000"
1775 /* 3528 */ "G_UDIVREM\000"
1776 /* 3538 */ "INLINEASM\000"
1777 /* 3548 */ "G_VECREDUCE_FMINIMUM\000"
1778 /* 3569 */ "G_FMINIMUM\000"
1779 /* 3580 */ "G_ATOMICRMW_FMINIMUM\000"
1780 /* 3601 */ "G_VECREDUCE_FMAXIMUM\000"
1781 /* 3622 */ "G_FMAXIMUM\000"
1782 /* 3633 */ "G_ATOMICRMW_FMAXIMUM\000"
1783 /* 3654 */ "G_FMINIMUMNUM\000"
1784 /* 3668 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1785 /* 3692 */ "G_FMAXIMUMNUM\000"
1786 /* 3706 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1787 /* 3730 */ "G_FMINNUM\000"
1788 /* 3740 */ "G_FMAXNUM\000"
1789 /* 3750 */ "G_FATAN\000"
1790 /* 3758 */ "G_FTAN\000"
1791 /* 3765 */ "G_INTRINSIC_ROUNDEVEN\000"
1792 /* 3787 */ "G_ASSERT_ALIGN\000"
1793 /* 3802 */ "G_FCOPYSIGN\000"
1794 /* 3814 */ "DUMMY_CHAIN\000"
1795 /* 3826 */ "ENDMAIN\000"
1796 /* 3834 */ "G_VECREDUCE_FMIN\000"
1797 /* 3851 */ "G_ATOMICRMW_FMIN\000"
1798 /* 3868 */ "G_VECREDUCE_SMIN\000"
1799 /* 3885 */ "G_SMIN\000"
1800 /* 3892 */ "G_VECREDUCE_UMIN\000"
1801 /* 3909 */ "G_UMIN\000"
1802 /* 3916 */ "G_ATOMICRMW_UMIN\000"
1803 /* 3933 */ "G_ATOMICRMW_MIN\000"
1804 /* 3949 */ "G_FASIN\000"
1805 /* 3957 */ "G_FSIN\000"
1806 /* 3964 */ "CFI_INSTRUCTION\000"
1807 /* 3980 */ "RETURN\000"
1808 /* 3987 */ "RAT_ATOMIC_RSUB_RTN\000"
1809 /* 4007 */ "RAT_ATOMIC_SUB_RTN\000"
1810 /* 4026 */ "RAT_ATOMIC_ADD_RTN\000"
1811 /* 4045 */ "RAT_ATOMIC_AND_RTN\000"
1812 /* 4064 */ "RAT_ATOMIC_XOR_RTN\000"
1813 /* 4083 */ "RAT_ATOMIC_OR_RTN\000"
1814 /* 4101 */ "RAT_ATOMIC_DEC_UINT_RTN\000"
1815 /* 4125 */ "RAT_ATOMIC_INC_UINT_RTN\000"
1816 /* 4149 */ "RAT_ATOMIC_MIN_UINT_RTN\000"
1817 /* 4173 */ "RAT_ATOMIC_MAX_UINT_RTN\000"
1818 /* 4197 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\000"
1819 /* 4224 */ "RAT_ATOMIC_XCHG_INT_RTN\000"
1820 /* 4248 */ "RAT_ATOMIC_MIN_INT_RTN\000"
1821 /* 4271 */ "RAT_ATOMIC_MAX_INT_RTN\000"
1822 /* 4294 */ "RETDYN\000"
1823 /* 4301 */ "G_SSUBO\000"
1824 /* 4309 */ "G_USUBO\000"
1825 /* 4317 */ "G_SADDO\000"
1826 /* 4325 */ "G_UADDO\000"
1827 /* 4333 */ "TEX_GET_TEXTURE_RESINFO\000"
1828 /* 4357 */ "JUMP_TABLE_DEBUG_INFO\000"
1829 /* 4379 */ "G_SMULO\000"
1830 /* 4387 */ "G_UMULO\000"
1831 /* 4395 */ "G_BZERO\000"
1832 /* 4403 */ "STACKMAP\000"
1833 /* 4412 */ "G_DEBUGTRAP\000"
1834 /* 4424 */ "G_UBSANTRAP\000"
1835 /* 4436 */ "G_TRAP\000"
1836 /* 4443 */ "G_ATOMICRMW_UDEC_WRAP\000"
1837 /* 4465 */ "G_ATOMICRMW_UINC_WRAP\000"
1838 /* 4487 */ "G_BSWAP\000"
1839 /* 4495 */ "G_SITOFP\000"
1840 /* 4504 */ "G_UITOFP\000"
1841 /* 4513 */ "G_FCMP\000"
1842 /* 4520 */ "G_ICMP\000"
1843 /* 4527 */ "G_SCMP\000"
1844 /* 4534 */ "G_UCMP\000"
1845 /* 4541 */ "JUMP\000"
1846 /* 4546 */ "ENDLOOP\000"
1847 /* 4554 */ "WHILELOOP\000"
1848 /* 4564 */ "CONVERGENCECTRL_LOOP\000"
1849 /* 4585 */ "G_CTPOP\000"
1850 /* 4593 */ "PATCHABLE_OP\000"
1851 /* 4606 */ "FAULTING_OP\000"
1852 /* 4618 */ "PREALLOCATED_SETUP\000"
1853 /* 4637 */ "G_FLDEXP\000"
1854 /* 4646 */ "G_STRICT_FLDEXP\000"
1855 /* 4662 */ "G_FEXP\000"
1856 /* 4669 */ "G_FFREXP\000"
1857 /* 4678 */ "G_BR\000"
1858 /* 4683 */ "INLINEASM_BR\000"
1859 /* 4696 */ "G_BLOCK_ADDR\000"
1860 /* 4709 */ "MOV_IMM_GLOBAL_ADDR\000"
1861 /* 4729 */ "MEMBARRIER\000"
1862 /* 4740 */ "G_CONSTANT_FOLD_BARRIER\000"
1863 /* 4764 */ "GROUP_BARRIER\000"
1864 /* 4778 */ "CF_ALU_ELSE_AFTER\000"
1865 /* 4796 */ "CF_ALU_POP_AFTER\000"
1866 /* 4813 */ "PATCHABLE_FUNCTION_ENTER\000"
1867 /* 4838 */ "G_READCYCLECOUNTER\000"
1868 /* 4857 */ "G_READSTEADYCOUNTER\000"
1869 /* 4877 */ "G_READ_REGISTER\000"
1870 /* 4893 */ "G_WRITE_REGISTER\000"
1871 /* 4910 */ "G_ASHR\000"
1872 /* 4917 */ "G_FSHR\000"
1873 /* 4924 */ "G_LSHR\000"
1874 /* 4931 */ "CONVERGENCECTRL_ANCHOR\000"
1875 /* 4954 */ "RAT_MSKOR\000"
1876 /* 4964 */ "G_FFLOOR\000"
1877 /* 4973 */ "G_SAVGFLOOR\000"
1878 /* 4985 */ "G_UAVGFLOOR\000"
1879 /* 4997 */ "G_EXTRACT_SUBVECTOR\000"
1880 /* 5017 */ "G_INSERT_SUBVECTOR\000"
1881 /* 5036 */ "G_BUILD_VECTOR\000"
1882 /* 5051 */ "G_SHUFFLE_VECTOR\000"
1883 /* 5068 */ "G_STEP_VECTOR\000"
1884 /* 5082 */ "G_SPLAT_VECTOR\000"
1885 /* 5097 */ "G_VECREDUCE_XOR\000"
1886 /* 5113 */ "G_XOR\000"
1887 /* 5119 */ "LDS_XOR\000"
1888 /* 5127 */ "G_ATOMICRMW_XOR\000"
1889 /* 5143 */ "G_VECREDUCE_OR\000"
1890 /* 5158 */ "G_OR\000"
1891 /* 5163 */ "LDS_OR\000"
1892 /* 5170 */ "G_ATOMICRMW_OR\000"
1893 /* 5185 */ "G_ROTR\000"
1894 /* 5192 */ "TEX_LDPTR\000"
1895 /* 5202 */ "G_INTTOPTR\000"
1896 /* 5213 */ "G_FABS\000"
1897 /* 5220 */ "G_ABS\000"
1898 /* 5226 */ "G_ABDS\000"
1899 /* 5233 */ "G_UNMERGE_VALUES\000"
1900 /* 5250 */ "G_MERGE_VALUES\000"
1901 /* 5265 */ "LITERALS\000"
1902 /* 5274 */ "G_CTLS\000"
1903 /* 5281 */ "G_FACOS\000"
1904 /* 5289 */ "G_FCOS\000"
1905 /* 5296 */ "G_FSINCOS\000"
1906 /* 5306 */ "G_CONCAT_VECTORS\000"
1907 /* 5323 */ "COPY_TO_REGCLASS\000"
1908 /* 5340 */ "G_IS_FPCLASS\000"
1909 /* 5353 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1910 /* 5383 */ "G_VECTOR_COMPRESS\000"
1911 /* 5401 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1912 /* 5428 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1913 /* 5466 */ "G_TRUNC_SSAT_S\000"
1914 /* 5481 */ "G_SSUBSAT\000"
1915 /* 5491 */ "G_USUBSAT\000"
1916 /* 5501 */ "G_SADDSAT\000"
1917 /* 5511 */ "G_UADDSAT\000"
1918 /* 5521 */ "G_SSHLSAT\000"
1919 /* 5531 */ "G_USHLSAT\000"
1920 /* 5541 */ "G_SMULFIXSAT\000"
1921 /* 5554 */ "G_UMULFIXSAT\000"
1922 /* 5567 */ "G_SDIVFIXSAT\000"
1923 /* 5580 */ "G_UDIVFIXSAT\000"
1924 /* 5593 */ "G_ATOMICRMW_USUB_SAT\000"
1925 /* 5614 */ "G_FPTOSI_SAT\000"
1926 /* 5627 */ "G_FPTOUI_SAT\000"
1927 /* 5640 */ "FRACT\000"
1928 /* 5646 */ "G_EXTRACT\000"
1929 /* 5656 */ "G_SELECT\000"
1930 /* 5665 */ "G_BRINDIRECT\000"
1931 /* 5678 */ "RAT_ATOMIC_RSUB_NORET\000"
1932 /* 5700 */ "RAT_ATOMIC_SUB_NORET\000"
1933 /* 5721 */ "RAT_ATOMIC_ADD_NORET\000"
1934 /* 5742 */ "RAT_ATOMIC_AND_NORET\000"
1935 /* 5763 */ "RAT_ATOMIC_XOR_NORET\000"
1936 /* 5784 */ "RAT_ATOMIC_OR_NORET\000"
1937 /* 5804 */ "RAT_ATOMIC_DEC_UINT_NORET\000"
1938 /* 5830 */ "RAT_ATOMIC_INC_UINT_NORET\000"
1939 /* 5856 */ "RAT_ATOMIC_MIN_UINT_NORET\000"
1940 /* 5882 */ "RAT_ATOMIC_MAX_UINT_NORET\000"
1941 /* 5908 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\000"
1942 /* 5937 */ "RAT_ATOMIC_XCHG_INT_NORET\000"
1943 /* 5963 */ "RAT_ATOMIC_MIN_INT_NORET\000"
1944 /* 5988 */ "RAT_ATOMIC_MAX_INT_NORET\000"
1945 /* 6013 */ "LDS_SUB_RET\000"
1946 /* 6025 */ "LDS_UBYTE_READ_RET\000"
1947 /* 6044 */ "LDS_BYTE_READ_RET\000"
1948 /* 6062 */ "LDS_READ_RET\000"
1949 /* 6075 */ "LDS_USHORT_READ_RET\000"
1950 /* 6095 */ "LDS_SHORT_READ_RET\000"
1951 /* 6114 */ "LDS_ADD_RET\000"
1952 /* 6126 */ "LDS_AND_RET\000"
1953 /* 6138 */ "PATCHABLE_RET\000"
1954 /* 6152 */ "LDS_WRXCHG_RET\000"
1955 /* 6167 */ "LDS_XOR_RET\000"
1956 /* 6179 */ "LDS_OR_RET\000"
1957 /* 6190 */ "LDS_MIN_UINT_RET\000"
1958 /* 6207 */ "LDS_MAX_UINT_RET\000"
1959 /* 6224 */ "LDS_MIN_INT_RET\000"
1960 /* 6240 */ "LDS_MAX_INT_RET\000"
1961 /* 6256 */ "LDS_CMPST_RET\000"
1962 /* 6270 */ "G_MEMSET\000"
1963 /* 6279 */ "IF_PREDICATE_SET\000"
1964 /* 6296 */ "KILLGT\000"
1965 /* 6303 */ "SGT\000"
1966 /* 6307 */ "PRED_SETGT\000"
1967 /* 6318 */ "PATCHABLE_FUNCTION_EXIT\000"
1968 /* 6342 */ "G_BRJT\000"
1969 /* 6349 */ "G_EXTRACT_VECTOR_ELT\000"
1970 /* 6370 */ "G_INSERT_VECTOR_ELT\000"
1971 /* 6390 */ "DEFAULT\000"
1972 /* 6398 */ "G_FCONSTANT\000"
1973 /* 6410 */ "G_CONSTANT\000"
1974 /* 6421 */ "G_INTRINSIC_CONVERGENT\000"
1975 /* 6444 */ "STATEPOINT\000"
1976 /* 6455 */ "PATCHPOINT\000"
1977 /* 6466 */ "G_PTRTOINT\000"
1978 /* 6477 */ "G_FRINT\000"
1979 /* 6485 */ "G_INTRINSIC_LLRINT\000"
1980 /* 6504 */ "G_INTRINSIC_LRINT\000"
1981 /* 6522 */ "SUBB_UINT\000"
1982 /* 6532 */ "ADDC_UINT\000"
1983 /* 6542 */ "SETGE_UINT\000"
1984 /* 6553 */ "FFBH_UINT\000"
1985 /* 6563 */ "LDS_MIN_UINT\000"
1986 /* 6576 */ "SETGT_UINT\000"
1987 /* 6587 */ "LDS_MAX_UINT\000"
1988 /* 6600 */ "G_FNEARBYINT\000"
1989 /* 6613 */ "SUB_INT\000"
1990 /* 6621 */ "ADD_INT\000"
1991 /* 6629 */ "AND_INT\000"
1992 /* 6637 */ "CNDE_INT\000"
1993 /* 6646 */ "CNDGE_INT\000"
1994 /* 6656 */ "PRED_SETGE_INT\000"
1995 /* 6671 */ "PRED_SETNE_INT\000"
1996 /* 6686 */ "PRED_SETE_INT\000"
1997 /* 6700 */ "FFBL_INT\000"
1998 /* 6709 */ "LDS_MIN_INT\000"
1999 /* 6721 */ "XOR_INT\000"
2000 /* 6729 */ "CNDGT_INT\000"
2001 /* 6739 */ "PRED_SETGT_INT\000"
2002 /* 6754 */ "BCNT_INT\000"
2003 /* 6763 */ "NOT_INT\000"
2004 /* 6771 */ "LDS_MAX_INT\000"
2005 /* 6783 */ "G_VASTART\000"
2006 /* 6793 */ "LIFETIME_START\000"
2007 /* 6808 */ "G_INVOKE_REGION_START\000"
2008 /* 6830 */ "G_INSERT\000"
2009 /* 6839 */ "G_FSQRT\000"
2010 /* 6847 */ "G_STRICT_FSQRT\000"
2011 /* 6862 */ "G_BITCAST\000"
2012 /* 6872 */ "G_ADDRSPACE_CAST\000"
2013 /* 6889 */ "DBG_VALUE_LIST\000"
2014 /* 6904 */ "LDS_CMPST\000"
2015 /* 6914 */ "G_FPEXT\000"
2016 /* 6922 */ "G_SEXT\000"
2017 /* 6929 */ "G_ASSERT_SEXT\000"
2018 /* 6943 */ "G_ANYEXT\000"
2019 /* 6952 */ "G_ZEXT\000"
2020 /* 6959 */ "G_ASSERT_ZEXT\000"
2021 /* 6973 */ "G_ABDU\000"
2022 /* 6980 */ "CF_ALU\000"
2023 /* 6987 */ "G_TRUNC_SSAT_U\000"
2024 /* 7002 */ "G_TRUNC_USAT_U\000"
2025 /* 7017 */ "G_FDIV\000"
2026 /* 7024 */ "G_STRICT_FDIV\000"
2027 /* 7038 */ "G_SDIV\000"
2028 /* 7045 */ "G_UDIV\000"
2029 /* 7052 */ "G_GET_FPENV\000"
2030 /* 7064 */ "G_RESET_FPENV\000"
2031 /* 7078 */ "G_SET_FPENV\000"
2032 /* 7090 */ "MOV\000"
2033 /* 7094 */ "TEX_GET_GRADIENTS_V\000"
2034 /* 7114 */ "TEX_SET_GRADIENTS_V\000"
2035 /* 7134 */ "TXD_SHADOW\000"
2036 /* 7145 */ "G_FPOW\000"
2037 /* 7152 */ "INTERP_ZW\000"
2038 /* 7162 */ "INTERP_PAIR_ZW\000"
2039 /* 7177 */ "G_VECREDUCE_FMAX\000"
2040 /* 7194 */ "G_ATOMICRMW_FMAX\000"
2041 /* 7211 */ "G_VECREDUCE_SMAX\000"
2042 /* 7228 */ "G_SMAX\000"
2043 /* 7235 */ "G_VECREDUCE_UMAX\000"
2044 /* 7252 */ "G_UMAX\000"
2045 /* 7259 */ "G_ATOMICRMW_UMAX\000"
2046 /* 7276 */ "G_ATOMICRMW_MAX\000"
2047 /* 7292 */ "G_FRAME_INDEX\000"
2048 /* 7306 */ "G_SBFX\000"
2049 /* 7313 */ "G_UBFX\000"
2050 /* 7320 */ "G_SMULFIX\000"
2051 /* 7330 */ "G_UMULFIX\000"
2052 /* 7340 */ "G_SDIVFIX\000"
2053 /* 7350 */ "G_UDIVFIX\000"
2054 /* 7360 */ "PRED_X\000"
2055 /* 7367 */ "G_MEMCPY\000"
2056 /* 7376 */ "CONST_COPY\000"
2057 /* 7387 */ "CONVERGENCECTRL_ENTRY\000"
2058 /* 7409 */ "INTERP_XY\000"
2059 /* 7419 */ "INTERP_PAIR_XY\000"
2060 /* 7434 */ "G_CTLZ\000"
2061 /* 7441 */ "G_CTTZ\000"
2062 /* 7448 */ "R600_RegisterLoad\000"
2063 /* 7466 */ "R600_RegisterStore\000"
2064 /* 7485 */ "R600_ExportBuf\000"
2065 /* 7500 */ "EG_ExportBuf\000"
2066 /* 7513 */ "VTX_READ_32_eg\000"
2067 /* 7528 */ "RAT_WRITE_CACHELESS_32_eg\000"
2068 /* 7554 */ "MULADD_UINT24_eg\000"
2069 /* 7571 */ "MULHI_UINT24_eg\000"
2070 /* 7587 */ "MUL_UINT24_eg\000"
2071 /* 7601 */ "VTX_READ_64_eg\000"
2072 /* 7616 */ "RAT_WRITE_CACHELESS_64_eg\000"
2073 /* 7642 */ "DOT4_eg\000"
2074 /* 7650 */ "VTX_READ_16_eg\000"
2075 /* 7665 */ "VTX_READ_128_eg\000"
2076 /* 7681 */ "RAT_WRITE_CACHELESS_128_eg\000"
2077 /* 7708 */ "VTX_READ_8_eg\000"
2078 /* 7722 */ "FMA_eg\000"
2079 /* 7729 */ "MULADD_eg\000"
2080 /* 7739 */ "LOG_CLAMPED_eg\000"
2081 /* 7754 */ "RECIP_CLAMPED_eg\000"
2082 /* 7771 */ "RECIPSQRT_CLAMPED_eg\000"
2083 /* 7792 */ "RAT_STORE_TYPED_eg\000"
2084 /* 7811 */ "CNDE_eg\000"
2085 /* 7819 */ "MULADD_IEEE_eg\000"
2086 /* 7834 */ "LOG_IEEE_eg\000"
2087 /* 7846 */ "RECIP_IEEE_eg\000"
2088 /* 7860 */ "EXP_IEEE_eg\000"
2089 /* 7872 */ "RECIPSQRT_IEEE_eg\000"
2090 /* 7890 */ "CNDGE_eg\000"
2091 /* 7899 */ "LSHL_eg\000"
2092 /* 7907 */ "SIN_eg\000"
2093 /* 7914 */ "ASHR_eg\000"
2094 /* 7922 */ "LSHR_eg\000"
2095 /* 7930 */ "COS_eg\000"
2096 /* 7937 */ "CNDGT_eg\000"
2097 /* 7946 */ "MUL_LIT_eg\000"
2098 /* 7957 */ "UINT_TO_FLT_eg\000"
2099 /* 7972 */ "BFE_UINT_eg\000"
2100 /* 7984 */ "MULHI_UINT_eg\000"
2101 /* 7998 */ "MULLO_UINT_eg\000"
2102 /* 8012 */ "FLT_TO_UINT_eg\000"
2103 /* 8027 */ "RECIP_UINT_eg\000"
2104 /* 8041 */ "MOVA_INT_eg\000"
2105 /* 8053 */ "BFE_INT_eg\000"
2106 /* 8064 */ "BFI_INT_eg\000"
2107 /* 8075 */ "MULHI_INT_eg\000"
2108 /* 8088 */ "BFM_INT_eg\000"
2109 /* 8099 */ "BIT_ALIGN_INT_eg\000"
2110 /* 8116 */ "MULLO_INT_eg\000"
2111 /* 8129 */ "FLT_TO_INT_eg\000"
2112 /* 8143 */ "CUBE_r600_real\000"
2113 /* 8158 */ "CUBE_eg_real\000"
2114 /* 8171 */ "VTX_READ_32_cm\000"
2115 /* 8186 */ "MULADD_INT24_cm\000"
2116 /* 8202 */ "MUL_INT24_cm\000"
2117 /* 8215 */ "VTX_READ_64_cm\000"
2118 /* 8230 */ "VTX_READ_16_cm\000"
2119 /* 8245 */ "VTX_READ_128_cm\000"
2120 /* 8261 */ "VTX_READ_8_cm\000"
2121 /* 8275 */ "RECIP_CLAMPED_cm\000"
2122 /* 8292 */ "RECIPSQRT_CLAMPED_cm\000"
2123 /* 8313 */ "RAT_STORE_TYPED_cm\000"
2124 /* 8332 */ "LOG_IEEE_cm\000"
2125 /* 8344 */ "RECIP_IEEE_cm\000"
2126 /* 8358 */ "EXP_IEEE_cm\000"
2127 /* 8370 */ "RECIPSQRT_IEEE_cm\000"
2128 /* 8388 */ "SIN_cm\000"
2129 /* 8395 */ "COS_cm\000"
2130 /* 8402 */ "MULHI_UINT_cm\000"
2131 /* 8416 */ "MULLO_UINT_cm\000"
2132 /* 8430 */ "MULHI_INT_cm\000"
2133 /* 8443 */ "MULLO_INT_cm\000"
2134 /* 8456 */ "CUBE_r600_pseudo\000"
2135 /* 8473 */ "CUBE_eg_pseudo\000"
2136 /* 8488 */ "R600_ExportSwz\000"
2137 /* 8503 */ "EG_ExportSwz\000"
2138};
2139#ifdef __GNUC__
2140#pragma GCC diagnostic pop
2141#endif
2142
2143extern const unsigned R600InstrNameIndices[] = {
2144 3081U, 3538U, 4683U, 3964U, 3167U, 3148U, 3176U, 3336U,
2145 2641U, 2656U, 2569U, 2556U, 2683U, 5323U, 2380U, 6889U,
2146 2582U, 3077U, 3157U, 1984U, 7382U, 3124U, 2130U, 6793U,
2147 1797U, 1935U, 1972U, 4403U, 3324U, 6455U, 1914U, 4618U,
2148 2924U, 6444U, 2196U, 4606U, 4593U, 4813U, 6138U, 6318U,
2149 3256U, 3303U, 3276U, 3193U, 2309U, 4729U, 4357U, 2170U,
2150 7387U, 4931U, 4564U, 2428U, 6929U, 6959U, 3787U, 1687U,
2151 1349U, 3439U, 7038U, 7045U, 3504U, 3511U, 3518U, 3528U,
2152 1767U, 5158U, 5113U, 5226U, 6973U, 4985U, 3245U, 4973U,
2153 3234U, 2567U, 3079U, 7292U, 2390U, 2405U, 3341U, 5646U,
2154 5233U, 6830U, 5250U, 5036U, 1435U, 5306U, 6466U, 5202U,
2155 6862U, 2487U, 4740U, 1888U, 1409U, 1870U, 6504U, 6485U,
2156 3765U, 4838U, 4857U, 1584U, 1512U, 1542U, 1569U, 1493U,
2157 1523U, 2259U, 2243U, 5353U, 2834U, 2862U, 1711U, 1363U,
2158 1781U, 1734U, 5170U, 5127U, 7276U, 3933U, 7259U, 3916U,
2159 1654U, 1332U, 7194U, 3851U, 3633U, 3580U, 3706U, 3668U,
2160 4465U, 4443U, 1819U, 5593U, 1964U, 2976U, 1810U, 5665U,
2161 6808U, 1379U, 5401U, 6421U, 5428U, 6943U, 1427U, 5466U,
2162 6987U, 7002U, 6410U, 6398U, 6783U, 2916U, 6922U, 2670U,
2163 6952U, 3220U, 4924U, 4910U, 3213U, 4917U, 5185U, 3357U,
2164 4520U, 4513U, 4527U, 4534U, 5656U, 4325U, 2005U, 4309U,
2165 1956U, 4317U, 1997U, 4301U, 1948U, 4387U, 4379U, 3005U,
2166 2997U, 5511U, 5501U, 5491U, 5481U, 5531U, 5521U, 7320U,
2167 7330U, 5541U, 5554U, 7340U, 7350U, 5567U, 5580U, 1612U,
2168 1311U, 3381U, 1262U, 1486U, 7017U, 3483U, 2512U, 7145U,
2169 3103U, 4662U, 1087U, 596U, 2909U, 1070U, 587U, 4637U,
2170 4669U, 2634U, 6914U, 1399U, 3085U, 3094U, 4495U, 4504U,
2171 5614U, 5627U, 5213U, 3802U, 5340U, 2496U, 3730U, 3740U,
2172 2063U, 2078U, 3569U, 3622U, 3654U, 3692U, 7052U, 7078U,
2173 7064U, 2013U, 2041U, 2026U, 2879U, 2894U, 1693U, 3138U,
2174 3885U, 7228U, 3909U, 7252U, 5220U, 1861U, 1851U, 4678U,
2175 6342U, 2108U, 5017U, 4997U, 6370U, 6349U, 5051U, 5082U,
2176 5068U, 5383U, 7441U, 2538U, 7434U, 2520U, 5274U, 4585U,
2177 4487U, 2272U, 3226U, 5289U, 3957U, 5296U, 3758U, 5281U,
2178 3949U, 3750U, 1078U, 3029U, 3021U, 3013U, 6839U, 4964U,
2179 6477U, 6600U, 6872U, 4696U, 2117U, 1456U, 2465U, 2228U,
2180 1640U, 1318U, 3409U, 7024U, 3490U, 1268U, 6847U, 4646U,
2181 4877U, 4893U, 7367U, 2154U, 2477U, 6270U, 4395U, 4436U,
2182 4412U, 4424U, 1619U, 3388U, 1595U, 3364U, 7177U, 3834U,
2183 3601U, 3548U, 1671U, 3423U, 1751U, 5143U, 5097U, 7211U,
2184 3868U, 7235U, 3892U, 7306U, 7313U, 2969U, 771U, 937U,
2185 3118U, 760U, 926U, 884U, 1050U, 825U, 991U, 7376U,
2186 2456U, 738U, 904U, 844U, 1010U, 787U, 953U, 8473U,
2187 8456U, 6390U, 1222U, 3814U, 2267U, 1806U, 1391U, 2596U,
2188 4546U, 3826U, 2987U, 160U, 82U, 1394U, 752U, 918U,
2189 867U, 1033U, 809U, 975U, 6279U, 4541U, 1841U, 2343U,
2190 699U, 4709U, 711U, 7360U, 1095U, 1183U, 1115U, 1203U,
2191 7448U, 7466U, 4294U, 3980U, 1931U, 7134U, 4554U, 1608U,
2192 6532U, 6621U, 2298U, 6629U, 7914U, 388U, 6754U, 8053U,
2193 7972U, 8064U, 8088U, 8099U, 3229U, 6980U, 3111U, 2449U,
2194 4778U, 4796U, 2209U, 2820U, 170U, 2736U, 65U, 2725U,
2195 34U, 3473U, 2715U, 22U, 2776U, 108U, 2751U, 47U,
2196 2697U, 0U, 2706U, 11U, 6637U, 7811U, 267U, 6646U,
2197 7890U, 358U, 6729U, 7937U, 417U, 8395U, 7930U, 408U,
2198 578U, 8158U, 8143U, 7642U, 186U, 7500U, 8503U, 2787U,
2199 121U, 8358U, 7860U, 324U, 2285U, 6553U, 6700U, 4967U,
2200 723U, 1228U, 8129U, 553U, 8012U, 490U, 7722U, 5640U,
2201 4764U, 666U, 7419U, 7162U, 1553U, 7409U, 7152U, 7958U,
2202 442U, 6296U, 1703U, 6114U, 1773U, 6126U, 6044U, 2328U,
2203 6904U, 6256U, 6771U, 6240U, 6587U, 6207U, 6709U, 6224U,
2204 6563U, 6190U, 5163U, 6179U, 6062U, 6095U, 2364U, 1355U,
2205 6013U, 6025U, 6075U, 2354U, 2851U, 6152U, 5119U, 6167U,
2206 5265U, 7739U, 208U, 8332U, 7834U, 294U, 2762U, 92U,
2207 7899U, 369U, 7922U, 398U, 7190U, 657U, 6775U, 6591U,
2208 3847U, 637U, 6713U, 6567U, 7090U, 8041U, 3377U, 7819U,
2209 277U, 8186U, 7554U, 7729U, 196U, 8430U, 1150U, 8075U,
2210 523U, 7571U, 8402U, 1134U, 7984U, 458U, 8443U, 8116U,
2211 538U, 8416U, 7998U, 474U, 2054U, 8202U, 7946U, 428U,
2212 7587U, 6763U, 6722U, 1591U, 2813U, 151U, 2318U, 6686U,
2213 2097U, 6656U, 6307U, 6739U, 2185U, 6671U, 7485U, 8488U,
2214 5721U, 4026U, 5742U, 4045U, 5908U, 4197U, 5804U, 4101U,
2215 5830U, 4125U, 5988U, 4271U, 5882U, 4173U, 5963U, 4248U,
2216 5856U, 4149U, 5784U, 4083U, 5678U, 3987U, 5700U, 4007U,
2217 5937U, 4224U, 5763U, 4064U, 4954U, 1243U, 681U, 1165U,
2218 8313U, 7792U, 7681U, 7528U, 7616U, 8292U, 7771U, 244U,
2219 8370U, 7872U, 338U, 8275U, 7754U, 225U, 8344U, 7846U,
2220 308U, 8027U, 507U, 2148U, 2323U, 627U, 6691U, 605U,
2221 6661U, 6542U, 646U, 6744U, 6576U, 616U, 6676U, 2093U,
2222 6303U, 8388U, 7907U, 379U, 569U, 2181U, 6522U, 6613U,
2223 3037U, 7094U, 4333U, 1727U, 5192U, 2137U, 1473U, 2941U,
2224 3445U, 1281U, 2956U, 3460U, 1297U, 3057U, 7114U, 2602U,
2225 2619U, 1403U, 7957U, 441U, 8245U, 7665U, 8230U, 7650U,
2226 8171U, 7513U, 8215U, 7601U, 8261U, 7708U, 2799U, 135U,
2227 6721U,
2228};
2229
2230static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
2231 II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 665, nullptr, 0);
2232}
2233
2234
2235} // namespace llvm
2236
2237#endif // GET_INSTRINFO_MC_DESC
2238
2239#ifdef GET_INSTRINFO_HEADER
2240#undef GET_INSTRINFO_HEADER
2241
2242namespace llvm {
2243
2244struct R600GenInstrInfo : public TargetInstrInfo {
2245 explicit R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2246 ~R600GenInstrInfo() override = default;
2247};
2248
2249} // namespace llvm
2250
2251namespace llvm::R600 {
2252
2253constexpr unsigned SUBOP_FRAMEri_ptr = 0;
2254constexpr unsigned SUBOP_FRAMEri_index = 1;
2255constexpr unsigned SUBOP_MEMrr_ptr = 0;
2256constexpr unsigned SUBOP_MEMrr_index = 1;
2257constexpr unsigned SUBOP_MEMxi_ptr = 0;
2258constexpr unsigned SUBOP_MEMxi_index = 1;
2259
2260} // namespace llvm::R600
2261
2262#endif // GET_INSTRINFO_HEADER
2263
2264#ifdef GET_INSTRINFO_HELPER_DECLS
2265#undef GET_INSTRINFO_HELPER_DECLS
2266
2267
2268#endif // GET_INSTRINFO_HELPER_DECLS
2269
2270#ifdef GET_INSTRINFO_HELPERS
2271#undef GET_INSTRINFO_HELPERS
2272
2273
2274#endif // GET_INSTRINFO_HELPERS
2275
2276#ifdef GET_INSTRINFO_CTOR_DTOR
2277#undef GET_INSTRINFO_CTOR_DTOR
2278
2279namespace llvm {
2280
2281extern const R600InstrTable R600Descs;
2282extern const unsigned R600InstrNameIndices[];
2283extern const char R600InstrNameData[];
2284R600GenInstrInfo::R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2285 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2286 InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 665);
2287}
2288
2289} // namespace llvm
2290
2291#endif // GET_INSTRINFO_CTOR_DTOR
2292
2293#ifdef GET_INSTRINFO_OPERAND_ENUM
2294#undef GET_INSTRINFO_OPERAND_ENUM
2295
2296namespace llvm::R600 {
2297
2298enum class OpName : uint8_t {
2299 dst = 0,
2300 src0 = 1,
2301 update_exec_mask_X = 2,
2302 update_pred_X = 3,
2303 write_X = 4,
2304 omod_X = 5,
2305 dst_rel_X = 6,
2306 clamp_X = 7,
2307 src0_X = 8,
2308 src0_neg_X = 9,
2309 src0_rel_X = 10,
2310 src0_abs_X = 11,
2311 src0_sel_X = 12,
2312 src1_X = 13,
2313 src1_neg_X = 14,
2314 src1_rel_X = 15,
2315 src1_abs_X = 16,
2316 src1_sel_X = 17,
2317 pred_sel_X = 18,
2318 update_exec_mask_Y = 19,
2319 update_pred_Y = 20,
2320 write_Y = 21,
2321 omod_Y = 22,
2322 dst_rel_Y = 23,
2323 clamp_Y = 24,
2324 src0_Y = 25,
2325 src0_neg_Y = 26,
2326 src0_rel_Y = 27,
2327 src0_abs_Y = 28,
2328 src0_sel_Y = 29,
2329 src1_Y = 30,
2330 src1_neg_Y = 31,
2331 src1_rel_Y = 32,
2332 src1_abs_Y = 33,
2333 src1_sel_Y = 34,
2334 pred_sel_Y = 35,
2335 update_exec_mask_Z = 36,
2336 update_pred_Z = 37,
2337 write_Z = 38,
2338 omod_Z = 39,
2339 dst_rel_Z = 40,
2340 clamp_Z = 41,
2341 src0_Z = 42,
2342 src0_neg_Z = 43,
2343 src0_rel_Z = 44,
2344 src0_abs_Z = 45,
2345 src0_sel_Z = 46,
2346 src1_Z = 47,
2347 src1_neg_Z = 48,
2348 src1_rel_Z = 49,
2349 src1_abs_Z = 50,
2350 src1_sel_Z = 51,
2351 pred_sel_Z = 52,
2352 update_exec_mask_W = 53,
2353 update_pred_W = 54,
2354 write_W = 55,
2355 omod_W = 56,
2356 dst_rel_W = 57,
2357 clamp_W = 58,
2358 src0_W = 59,
2359 src0_neg_W = 60,
2360 src0_rel_W = 61,
2361 src0_abs_W = 62,
2362 src0_sel_W = 63,
2363 src1_W = 64,
2364 src1_neg_W = 65,
2365 src1_rel_W = 66,
2366 src1_abs_W = 67,
2367 src1_sel_W = 68,
2368 pred_sel_W = 69,
2369 literal0 = 70,
2370 literal1 = 71,
2371 addr = 72,
2372 chan = 73,
2373 val = 74,
2374 update_exec_mask = 75,
2375 update_pred = 76,
2376 write = 77,
2377 omod = 78,
2378 dst_rel = 79,
2379 clamp = 80,
2380 src0_neg = 81,
2381 src0_rel = 82,
2382 src0_abs = 83,
2383 src0_sel = 84,
2384 src1 = 85,
2385 src1_neg = 86,
2386 src1_rel = 87,
2387 src1_abs = 88,
2388 src1_sel = 89,
2389 last = 90,
2390 pred_sel = 91,
2391 literal = 92,
2392 bank_swizzle = 93,
2393 src2 = 94,
2394 src2_neg = 95,
2395 src2_rel = 96,
2396 src2_sel = 97,
2397 ADDR = 98,
2398 KCACHE_BANK0 = 99,
2399 KCACHE_BANK1 = 100,
2400 KCACHE_MODE0 = 101,
2401 KCACHE_MODE1 = 102,
2402 KCACHE_ADDR0 = 103,
2403 KCACHE_ADDR1 = 104,
2404 COUNT = 105,
2405 Enabled = 106,
2406 NUM_OPERAND_NAMES = 107,
2407}; // enum class OpName
2408
2409LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name);
2410LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx);
2411
2412} // namespace llvm::R600
2413
2414#endif // GET_INSTRINFO_OPERAND_ENUM
2415
2416#ifdef GET_INSTRINFO_NAMED_OPS
2417#undef GET_INSTRINFO_NAMED_OPS
2418
2419namespace llvm::R600 {
2420
2421LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) {
2422 static constexpr uint8_t InstructionIndex[] = {
2423 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2424 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2425 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2426 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2427 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2428 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2429 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2430 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2431 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2432 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2433 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2434 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2436 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2437 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2438 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2440 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2441 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2442 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2443 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2444 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 2, 0, 0, 0, 0, 0,
2445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2446 0, 0, 0, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 0, 5,
2447 5, 5, 0, 5, 5, 5, 6, 7, 7, 7, 5, 7, 6, 8, 8, 8,
2448 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2449 0, 0, 0, 0, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6,
2450 6, 5, 5, 5, 5, 0, 0, 0, 0, 6, 6, 6, 0, 6, 6, 6,
2451 6, 6, 6, 6, 6, 6, 7, 6, 0, 6, 0, 0, 0, 5, 5, 6,
2452 6, 5, 9, 10, 9, 10, 11, 9, 12, 13, 9, 10, 9, 10, 9, 10,
2453 9, 10, 9, 10, 11, 11, 9, 9, 10, 11, 11, 9, 9, 10, 9, 10,
2454 0, 6, 6, 6, 6, 6, 0, 0, 5, 5, 5, 5, 5, 5, 5, 5,
2455 5, 5, 5, 5, 6, 6, 5, 7, 7, 7, 7, 7, 7, 5, 5, 5,
2456 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 7, 7,
2457 5, 6, 5, 0, 0, 0, 5, 5, 5, 5, 5, 5, 5, 5, 0, 0,
2458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2460 0, 0, 0, 0, 0, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
2461 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
2462 5, 6, 6, 6, 6, 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0,
2463 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6, 6, 0, 0, 0, 0,
2464 0, 0, 0, 0, 0, 0, 0, 0, 5,
2465 };
2466 return InstructionIndex[Opcode];
2467}
2468LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) {
2469 assert(Name != OpName::NUM_OPERAND_NAMES);
2470 static constexpr int8_t OperandMap[][107] = {
2471 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2472 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2473 {0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2474 {0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2475 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2476 {0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2477 {0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2478 {0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2479 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
2480 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2481 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2482 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2483 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2484 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2485 };
2486 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2487 return OperandMap[InstrIdx][(unsigned)Name];
2488}
2489LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) {
2490 assert(Idx >= 0 && Idx < 71);
2491 static constexpr OpName OperandMap[][71] = {
2492 {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2493 {OpName::dst, OpName::src0, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2494 {OpName::dst, OpName::update_exec_mask_X, OpName::update_pred_X, OpName::write_X, OpName::omod_X, OpName::dst_rel_X, OpName::clamp_X, OpName::src0_X, OpName::src0_neg_X, OpName::src0_rel_X, OpName::src0_abs_X, OpName::src0_sel_X, OpName::src1_X, OpName::src1_neg_X, OpName::src1_rel_X, OpName::src1_abs_X, OpName::src1_sel_X, OpName::pred_sel_X, OpName::update_exec_mask_Y, OpName::update_pred_Y, OpName::write_Y, OpName::omod_Y, OpName::dst_rel_Y, OpName::clamp_Y, OpName::src0_Y, OpName::src0_neg_Y, OpName::src0_rel_Y, OpName::src0_abs_Y, OpName::src0_sel_Y, OpName::src1_Y, OpName::src1_neg_Y, OpName::src1_rel_Y, OpName::src1_abs_Y, OpName::src1_sel_Y, OpName::pred_sel_Y, OpName::update_exec_mask_Z, OpName::update_pred_Z, OpName::write_Z, OpName::omod_Z, OpName::dst_rel_Z, OpName::clamp_Z, OpName::src0_Z, OpName::src0_neg_Z, OpName::src0_rel_Z, OpName::src0_abs_Z, OpName::src0_sel_Z, OpName::src1_Z, OpName::src1_neg_Z, OpName::src1_rel_Z, OpName::src1_abs_Z, OpName::src1_sel_Z, OpName::pred_sel_Z, OpName::update_exec_mask_W, OpName::update_pred_W, OpName::write_W, OpName::omod_W, OpName::dst_rel_W, OpName::clamp_W, OpName::src0_W, OpName::src0_neg_W, OpName::src0_rel_W, OpName::src0_abs_W, OpName::src0_sel_W, OpName::src1_W, OpName::src1_neg_W, OpName::src1_rel_W, OpName::src1_abs_W, OpName::src1_sel_W, OpName::pred_sel_W, OpName::literal0, OpName::literal1, },
2495 {OpName::dst, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2496 {OpName::val, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2497 {OpName::dst, OpName::update_exec_mask, OpName::update_pred, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_abs, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2498 {OpName::dst, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2499 {OpName::dst, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_neg, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2500 {OpName::ADDR, OpName::KCACHE_BANK0, OpName::KCACHE_BANK1, OpName::KCACHE_MODE0, OpName::KCACHE_MODE1, OpName::KCACHE_ADDR0, OpName::KCACHE_ADDR1, OpName::COUNT, OpName::Enabled, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2501 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2502 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2503 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2504 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2505 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2506 };
2507 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2508 return OperandMap[InstrIdx][(unsigned)Idx];
2509}
2510
2511} // namespace llvm::R600
2512
2513#endif // GET_INSTRINFO_NAMED_OPS
2514
2515#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2516#undef GET_INSTRINFO_MC_HELPER_DECLS
2517
2518namespace llvm {
2519
2520class MCInst;
2521class FeatureBitset;
2522
2523namespace R600_MC {
2524
2525void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2526
2527} // namespace R600_MC
2528
2529} // namespace llvm
2530
2531#endif // GET_INSTRINFO_MC_HELPER_DECLS
2532
2533#ifdef GET_INSTRINFO_MC_HELPERS
2534#undef GET_INSTRINFO_MC_HELPERS
2535
2536namespace llvm::R600_MC {
2537
2538
2539} // namespace llvm::R600_MC
2540
2541#endif // GET_INSTRINFO_MC_HELPERS
2542
2543#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2544 defined(GET_AVAILABLE_OPCODE_CHECKER)
2545#define GET_COMPUTE_FEATURES
2546#endif
2547#ifdef GET_COMPUTE_FEATURES
2548#undef GET_COMPUTE_FEATURES
2549
2550namespace llvm::R600_MC {
2551
2552// Bits for subtarget features that participate in instruction matching.
2553enum SubtargetFeatureBits : uint8_t {
2554};
2555
2556inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2557 FeatureBitset Features;
2558 return Features;
2559}
2560
2561inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2562 enum : uint8_t {
2563 CEFBS_None,
2564 };
2565
2566 static constexpr FeatureBitset FeatureBitsets[] = {
2567 {}, // CEFBS_None
2568 };
2569 static constexpr uint8_t RequiredFeaturesRefs[] = {
2570 CEFBS_None, // PHI
2571 CEFBS_None, // INLINEASM
2572 CEFBS_None, // INLINEASM_BR
2573 CEFBS_None, // CFI_INSTRUCTION
2574 CEFBS_None, // EH_LABEL
2575 CEFBS_None, // GC_LABEL
2576 CEFBS_None, // ANNOTATION_LABEL
2577 CEFBS_None, // KILL
2578 CEFBS_None, // EXTRACT_SUBREG
2579 CEFBS_None, // INSERT_SUBREG
2580 CEFBS_None, // IMPLICIT_DEF
2581 CEFBS_None, // INIT_UNDEF
2582 CEFBS_None, // SUBREG_TO_REG
2583 CEFBS_None, // COPY_TO_REGCLASS
2584 CEFBS_None, // DBG_VALUE
2585 CEFBS_None, // DBG_VALUE_LIST
2586 CEFBS_None, // DBG_INSTR_REF
2587 CEFBS_None, // DBG_PHI
2588 CEFBS_None, // DBG_LABEL
2589 CEFBS_None, // REG_SEQUENCE
2590 CEFBS_None, // COPY
2591 CEFBS_None, // COPY_LANEMASK
2592 CEFBS_None, // BUNDLE
2593 CEFBS_None, // LIFETIME_START
2594 CEFBS_None, // LIFETIME_END
2595 CEFBS_None, // PSEUDO_PROBE
2596 CEFBS_None, // ARITH_FENCE
2597 CEFBS_None, // STACKMAP
2598 CEFBS_None, // FENTRY_CALL
2599 CEFBS_None, // PATCHPOINT
2600 CEFBS_None, // LOAD_STACK_GUARD
2601 CEFBS_None, // PREALLOCATED_SETUP
2602 CEFBS_None, // PREALLOCATED_ARG
2603 CEFBS_None, // STATEPOINT
2604 CEFBS_None, // LOCAL_ESCAPE
2605 CEFBS_None, // FAULTING_OP
2606 CEFBS_None, // PATCHABLE_OP
2607 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2608 CEFBS_None, // PATCHABLE_RET
2609 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2610 CEFBS_None, // PATCHABLE_TAIL_CALL
2611 CEFBS_None, // PATCHABLE_EVENT_CALL
2612 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2613 CEFBS_None, // ICALL_BRANCH_FUNNEL
2614 CEFBS_None, // FAKE_USE
2615 CEFBS_None, // MEMBARRIER
2616 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2617 CEFBS_None, // RELOC_NONE
2618 CEFBS_None, // CONVERGENCECTRL_ENTRY
2619 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2620 CEFBS_None, // CONVERGENCECTRL_LOOP
2621 CEFBS_None, // CONVERGENCECTRL_GLUE
2622 CEFBS_None, // G_ASSERT_SEXT
2623 CEFBS_None, // G_ASSERT_ZEXT
2624 CEFBS_None, // G_ASSERT_ALIGN
2625 CEFBS_None, // G_ADD
2626 CEFBS_None, // G_SUB
2627 CEFBS_None, // G_MUL
2628 CEFBS_None, // G_SDIV
2629 CEFBS_None, // G_UDIV
2630 CEFBS_None, // G_SREM
2631 CEFBS_None, // G_UREM
2632 CEFBS_None, // G_SDIVREM
2633 CEFBS_None, // G_UDIVREM
2634 CEFBS_None, // G_AND
2635 CEFBS_None, // G_OR
2636 CEFBS_None, // G_XOR
2637 CEFBS_None, // G_ABDS
2638 CEFBS_None, // G_ABDU
2639 CEFBS_None, // G_UAVGFLOOR
2640 CEFBS_None, // G_UAVGCEIL
2641 CEFBS_None, // G_SAVGFLOOR
2642 CEFBS_None, // G_SAVGCEIL
2643 CEFBS_None, // G_IMPLICIT_DEF
2644 CEFBS_None, // G_PHI
2645 CEFBS_None, // G_FRAME_INDEX
2646 CEFBS_None, // G_GLOBAL_VALUE
2647 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2648 CEFBS_None, // G_CONSTANT_POOL
2649 CEFBS_None, // G_EXTRACT
2650 CEFBS_None, // G_UNMERGE_VALUES
2651 CEFBS_None, // G_INSERT
2652 CEFBS_None, // G_MERGE_VALUES
2653 CEFBS_None, // G_BUILD_VECTOR
2654 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2655 CEFBS_None, // G_CONCAT_VECTORS
2656 CEFBS_None, // G_PTRTOINT
2657 CEFBS_None, // G_INTTOPTR
2658 CEFBS_None, // G_BITCAST
2659 CEFBS_None, // G_FREEZE
2660 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2661 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2662 CEFBS_None, // G_INTRINSIC_TRUNC
2663 CEFBS_None, // G_INTRINSIC_ROUND
2664 CEFBS_None, // G_INTRINSIC_LRINT
2665 CEFBS_None, // G_INTRINSIC_LLRINT
2666 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2667 CEFBS_None, // G_READCYCLECOUNTER
2668 CEFBS_None, // G_READSTEADYCOUNTER
2669 CEFBS_None, // G_LOAD
2670 CEFBS_None, // G_SEXTLOAD
2671 CEFBS_None, // G_ZEXTLOAD
2672 CEFBS_None, // G_INDEXED_LOAD
2673 CEFBS_None, // G_INDEXED_SEXTLOAD
2674 CEFBS_None, // G_INDEXED_ZEXTLOAD
2675 CEFBS_None, // G_STORE
2676 CEFBS_None, // G_INDEXED_STORE
2677 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2678 CEFBS_None, // G_ATOMIC_CMPXCHG
2679 CEFBS_None, // G_ATOMICRMW_XCHG
2680 CEFBS_None, // G_ATOMICRMW_ADD
2681 CEFBS_None, // G_ATOMICRMW_SUB
2682 CEFBS_None, // G_ATOMICRMW_AND
2683 CEFBS_None, // G_ATOMICRMW_NAND
2684 CEFBS_None, // G_ATOMICRMW_OR
2685 CEFBS_None, // G_ATOMICRMW_XOR
2686 CEFBS_None, // G_ATOMICRMW_MAX
2687 CEFBS_None, // G_ATOMICRMW_MIN
2688 CEFBS_None, // G_ATOMICRMW_UMAX
2689 CEFBS_None, // G_ATOMICRMW_UMIN
2690 CEFBS_None, // G_ATOMICRMW_FADD
2691 CEFBS_None, // G_ATOMICRMW_FSUB
2692 CEFBS_None, // G_ATOMICRMW_FMAX
2693 CEFBS_None, // G_ATOMICRMW_FMIN
2694 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2695 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2696 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2697 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2698 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2699 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2700 CEFBS_None, // G_ATOMICRMW_USUB_COND
2701 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2702 CEFBS_None, // G_FENCE
2703 CEFBS_None, // G_PREFETCH
2704 CEFBS_None, // G_BRCOND
2705 CEFBS_None, // G_BRINDIRECT
2706 CEFBS_None, // G_INVOKE_REGION_START
2707 CEFBS_None, // G_INTRINSIC
2708 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2709 CEFBS_None, // G_INTRINSIC_CONVERGENT
2710 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2711 CEFBS_None, // G_ANYEXT
2712 CEFBS_None, // G_TRUNC
2713 CEFBS_None, // G_TRUNC_SSAT_S
2714 CEFBS_None, // G_TRUNC_SSAT_U
2715 CEFBS_None, // G_TRUNC_USAT_U
2716 CEFBS_None, // G_CONSTANT
2717 CEFBS_None, // G_FCONSTANT
2718 CEFBS_None, // G_VASTART
2719 CEFBS_None, // G_VAARG
2720 CEFBS_None, // G_SEXT
2721 CEFBS_None, // G_SEXT_INREG
2722 CEFBS_None, // G_ZEXT
2723 CEFBS_None, // G_SHL
2724 CEFBS_None, // G_LSHR
2725 CEFBS_None, // G_ASHR
2726 CEFBS_None, // G_FSHL
2727 CEFBS_None, // G_FSHR
2728 CEFBS_None, // G_ROTR
2729 CEFBS_None, // G_ROTL
2730 CEFBS_None, // G_ICMP
2731 CEFBS_None, // G_FCMP
2732 CEFBS_None, // G_SCMP
2733 CEFBS_None, // G_UCMP
2734 CEFBS_None, // G_SELECT
2735 CEFBS_None, // G_UADDO
2736 CEFBS_None, // G_UADDE
2737 CEFBS_None, // G_USUBO
2738 CEFBS_None, // G_USUBE
2739 CEFBS_None, // G_SADDO
2740 CEFBS_None, // G_SADDE
2741 CEFBS_None, // G_SSUBO
2742 CEFBS_None, // G_SSUBE
2743 CEFBS_None, // G_UMULO
2744 CEFBS_None, // G_SMULO
2745 CEFBS_None, // G_UMULH
2746 CEFBS_None, // G_SMULH
2747 CEFBS_None, // G_UADDSAT
2748 CEFBS_None, // G_SADDSAT
2749 CEFBS_None, // G_USUBSAT
2750 CEFBS_None, // G_SSUBSAT
2751 CEFBS_None, // G_USHLSAT
2752 CEFBS_None, // G_SSHLSAT
2753 CEFBS_None, // G_SMULFIX
2754 CEFBS_None, // G_UMULFIX
2755 CEFBS_None, // G_SMULFIXSAT
2756 CEFBS_None, // G_UMULFIXSAT
2757 CEFBS_None, // G_SDIVFIX
2758 CEFBS_None, // G_UDIVFIX
2759 CEFBS_None, // G_SDIVFIXSAT
2760 CEFBS_None, // G_UDIVFIXSAT
2761 CEFBS_None, // G_FADD
2762 CEFBS_None, // G_FSUB
2763 CEFBS_None, // G_FMUL
2764 CEFBS_None, // G_FMA
2765 CEFBS_None, // G_FMAD
2766 CEFBS_None, // G_FDIV
2767 CEFBS_None, // G_FREM
2768 CEFBS_None, // G_FMODF
2769 CEFBS_None, // G_FPOW
2770 CEFBS_None, // G_FPOWI
2771 CEFBS_None, // G_FEXP
2772 CEFBS_None, // G_FEXP2
2773 CEFBS_None, // G_FEXP10
2774 CEFBS_None, // G_FLOG
2775 CEFBS_None, // G_FLOG2
2776 CEFBS_None, // G_FLOG10
2777 CEFBS_None, // G_FLDEXP
2778 CEFBS_None, // G_FFREXP
2779 CEFBS_None, // G_FNEG
2780 CEFBS_None, // G_FPEXT
2781 CEFBS_None, // G_FPTRUNC
2782 CEFBS_None, // G_FPTOSI
2783 CEFBS_None, // G_FPTOUI
2784 CEFBS_None, // G_SITOFP
2785 CEFBS_None, // G_UITOFP
2786 CEFBS_None, // G_FPTOSI_SAT
2787 CEFBS_None, // G_FPTOUI_SAT
2788 CEFBS_None, // G_FABS
2789 CEFBS_None, // G_FCOPYSIGN
2790 CEFBS_None, // G_IS_FPCLASS
2791 CEFBS_None, // G_FCANONICALIZE
2792 CEFBS_None, // G_FMINNUM
2793 CEFBS_None, // G_FMAXNUM
2794 CEFBS_None, // G_FMINNUM_IEEE
2795 CEFBS_None, // G_FMAXNUM_IEEE
2796 CEFBS_None, // G_FMINIMUM
2797 CEFBS_None, // G_FMAXIMUM
2798 CEFBS_None, // G_FMINIMUMNUM
2799 CEFBS_None, // G_FMAXIMUMNUM
2800 CEFBS_None, // G_GET_FPENV
2801 CEFBS_None, // G_SET_FPENV
2802 CEFBS_None, // G_RESET_FPENV
2803 CEFBS_None, // G_GET_FPMODE
2804 CEFBS_None, // G_SET_FPMODE
2805 CEFBS_None, // G_RESET_FPMODE
2806 CEFBS_None, // G_GET_ROUNDING
2807 CEFBS_None, // G_SET_ROUNDING
2808 CEFBS_None, // G_PTR_ADD
2809 CEFBS_None, // G_PTRMASK
2810 CEFBS_None, // G_SMIN
2811 CEFBS_None, // G_SMAX
2812 CEFBS_None, // G_UMIN
2813 CEFBS_None, // G_UMAX
2814 CEFBS_None, // G_ABS
2815 CEFBS_None, // G_LROUND
2816 CEFBS_None, // G_LLROUND
2817 CEFBS_None, // G_BR
2818 CEFBS_None, // G_BRJT
2819 CEFBS_None, // G_VSCALE
2820 CEFBS_None, // G_INSERT_SUBVECTOR
2821 CEFBS_None, // G_EXTRACT_SUBVECTOR
2822 CEFBS_None, // G_INSERT_VECTOR_ELT
2823 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2824 CEFBS_None, // G_SHUFFLE_VECTOR
2825 CEFBS_None, // G_SPLAT_VECTOR
2826 CEFBS_None, // G_STEP_VECTOR
2827 CEFBS_None, // G_VECTOR_COMPRESS
2828 CEFBS_None, // G_CTTZ
2829 CEFBS_None, // G_CTTZ_ZERO_UNDEF
2830 CEFBS_None, // G_CTLZ
2831 CEFBS_None, // G_CTLZ_ZERO_UNDEF
2832 CEFBS_None, // G_CTLS
2833 CEFBS_None, // G_CTPOP
2834 CEFBS_None, // G_BSWAP
2835 CEFBS_None, // G_BITREVERSE
2836 CEFBS_None, // G_FCEIL
2837 CEFBS_None, // G_FCOS
2838 CEFBS_None, // G_FSIN
2839 CEFBS_None, // G_FSINCOS
2840 CEFBS_None, // G_FTAN
2841 CEFBS_None, // G_FACOS
2842 CEFBS_None, // G_FASIN
2843 CEFBS_None, // G_FATAN
2844 CEFBS_None, // G_FATAN2
2845 CEFBS_None, // G_FCOSH
2846 CEFBS_None, // G_FSINH
2847 CEFBS_None, // G_FTANH
2848 CEFBS_None, // G_FSQRT
2849 CEFBS_None, // G_FFLOOR
2850 CEFBS_None, // G_FRINT
2851 CEFBS_None, // G_FNEARBYINT
2852 CEFBS_None, // G_ADDRSPACE_CAST
2853 CEFBS_None, // G_BLOCK_ADDR
2854 CEFBS_None, // G_JUMP_TABLE
2855 CEFBS_None, // G_DYN_STACKALLOC
2856 CEFBS_None, // G_STACKSAVE
2857 CEFBS_None, // G_STACKRESTORE
2858 CEFBS_None, // G_STRICT_FADD
2859 CEFBS_None, // G_STRICT_FSUB
2860 CEFBS_None, // G_STRICT_FMUL
2861 CEFBS_None, // G_STRICT_FDIV
2862 CEFBS_None, // G_STRICT_FREM
2863 CEFBS_None, // G_STRICT_FMA
2864 CEFBS_None, // G_STRICT_FSQRT
2865 CEFBS_None, // G_STRICT_FLDEXP
2866 CEFBS_None, // G_READ_REGISTER
2867 CEFBS_None, // G_WRITE_REGISTER
2868 CEFBS_None, // G_MEMCPY
2869 CEFBS_None, // G_MEMCPY_INLINE
2870 CEFBS_None, // G_MEMMOVE
2871 CEFBS_None, // G_MEMSET
2872 CEFBS_None, // G_BZERO
2873 CEFBS_None, // G_TRAP
2874 CEFBS_None, // G_DEBUGTRAP
2875 CEFBS_None, // G_UBSANTRAP
2876 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2877 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2878 CEFBS_None, // G_VECREDUCE_FADD
2879 CEFBS_None, // G_VECREDUCE_FMUL
2880 CEFBS_None, // G_VECREDUCE_FMAX
2881 CEFBS_None, // G_VECREDUCE_FMIN
2882 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2883 CEFBS_None, // G_VECREDUCE_FMINIMUM
2884 CEFBS_None, // G_VECREDUCE_ADD
2885 CEFBS_None, // G_VECREDUCE_MUL
2886 CEFBS_None, // G_VECREDUCE_AND
2887 CEFBS_None, // G_VECREDUCE_OR
2888 CEFBS_None, // G_VECREDUCE_XOR
2889 CEFBS_None, // G_VECREDUCE_SMAX
2890 CEFBS_None, // G_VECREDUCE_SMIN
2891 CEFBS_None, // G_VECREDUCE_UMAX
2892 CEFBS_None, // G_VECREDUCE_UMIN
2893 CEFBS_None, // G_SBFX
2894 CEFBS_None, // G_UBFX
2895 CEFBS_None, // BRANCH
2896 CEFBS_None, // BRANCH_COND_f32
2897 CEFBS_None, // BRANCH_COND_i32
2898 CEFBS_None, // BREAK
2899 CEFBS_None, // BREAKC_f32
2900 CEFBS_None, // BREAKC_i32
2901 CEFBS_None, // BREAK_LOGICALNZ_f32
2902 CEFBS_None, // BREAK_LOGICALNZ_i32
2903 CEFBS_None, // BREAK_LOGICALZ_f32
2904 CEFBS_None, // BREAK_LOGICALZ_i32
2905 CEFBS_None, // CONST_COPY
2906 CEFBS_None, // CONTINUE
2907 CEFBS_None, // CONTINUEC_f32
2908 CEFBS_None, // CONTINUEC_i32
2909 CEFBS_None, // CONTINUE_LOGICALNZ_f32
2910 CEFBS_None, // CONTINUE_LOGICALNZ_i32
2911 CEFBS_None, // CONTINUE_LOGICALZ_f32
2912 CEFBS_None, // CONTINUE_LOGICALZ_i32
2913 CEFBS_None, // CUBE_eg_pseudo
2914 CEFBS_None, // CUBE_r600_pseudo
2915 CEFBS_None, // DEFAULT
2916 CEFBS_None, // DOT_4
2917 CEFBS_None, // DUMMY_CHAIN
2918 CEFBS_None, // ELSE
2919 CEFBS_None, // END
2920 CEFBS_None, // ENDFUNC
2921 CEFBS_None, // ENDIF
2922 CEFBS_None, // ENDLOOP
2923 CEFBS_None, // ENDMAIN
2924 CEFBS_None, // ENDSWITCH
2925 CEFBS_None, // FABS_R600
2926 CEFBS_None, // FNEG_R600
2927 CEFBS_None, // FUNC
2928 CEFBS_None, // IFC_f32
2929 CEFBS_None, // IFC_i32
2930 CEFBS_None, // IF_LOGICALNZ_f32
2931 CEFBS_None, // IF_LOGICALNZ_i32
2932 CEFBS_None, // IF_LOGICALZ_f32
2933 CEFBS_None, // IF_LOGICALZ_i32
2934 CEFBS_None, // IF_PREDICATE_SET
2935 CEFBS_None, // JUMP
2936 CEFBS_None, // JUMP_COND
2937 CEFBS_None, // MASK_WRITE
2938 CEFBS_None, // MOV_IMM_F32
2939 CEFBS_None, // MOV_IMM_GLOBAL_ADDR
2940 CEFBS_None, // MOV_IMM_I32
2941 CEFBS_None, // PRED_X
2942 CEFBS_None, // R600_EXTRACT_ELT_V2
2943 CEFBS_None, // R600_EXTRACT_ELT_V4
2944 CEFBS_None, // R600_INSERT_ELT_V2
2945 CEFBS_None, // R600_INSERT_ELT_V4
2946 CEFBS_None, // R600_RegisterLoad
2947 CEFBS_None, // R600_RegisterStore
2948 CEFBS_None, // RETDYN
2949 CEFBS_None, // RETURN
2950 CEFBS_None, // TXD
2951 CEFBS_None, // TXD_SHADOW
2952 CEFBS_None, // WHILELOOP
2953 CEFBS_None, // ADD
2954 CEFBS_None, // ADDC_UINT
2955 CEFBS_None, // ADD_INT
2956 CEFBS_None, // ALU_CLAUSE
2957 CEFBS_None, // AND_INT
2958 CEFBS_None, // ASHR_eg
2959 CEFBS_None, // ASHR_r600
2960 CEFBS_None, // BCNT_INT
2961 CEFBS_None, // BFE_INT_eg
2962 CEFBS_None, // BFE_UINT_eg
2963 CEFBS_None, // BFI_INT_eg
2964 CEFBS_None, // BFM_INT_eg
2965 CEFBS_None, // BIT_ALIGN_INT_eg
2966 CEFBS_None, // CEIL
2967 CEFBS_None, // CF_ALU
2968 CEFBS_None, // CF_ALU_BREAK
2969 CEFBS_None, // CF_ALU_CONTINUE
2970 CEFBS_None, // CF_ALU_ELSE_AFTER
2971 CEFBS_None, // CF_ALU_POP_AFTER
2972 CEFBS_None, // CF_ALU_PUSH_BEFORE
2973 CEFBS_None, // CF_CALL_FS_EG
2974 CEFBS_None, // CF_CALL_FS_R600
2975 CEFBS_None, // CF_CONTINUE_EG
2976 CEFBS_None, // CF_CONTINUE_R600
2977 CEFBS_None, // CF_ELSE_EG
2978 CEFBS_None, // CF_ELSE_R600
2979 CEFBS_None, // CF_END_CM
2980 CEFBS_None, // CF_END_EG
2981 CEFBS_None, // CF_END_R600
2982 CEFBS_None, // CF_JUMP_EG
2983 CEFBS_None, // CF_JUMP_R600
2984 CEFBS_None, // CF_PUSH_EG
2985 CEFBS_None, // CF_PUSH_ELSE_R600
2986 CEFBS_None, // CF_TC_EG
2987 CEFBS_None, // CF_TC_R600
2988 CEFBS_None, // CF_VC_EG
2989 CEFBS_None, // CF_VC_R600
2990 CEFBS_None, // CNDE_INT
2991 CEFBS_None, // CNDE_eg
2992 CEFBS_None, // CNDE_r600
2993 CEFBS_None, // CNDGE_INT
2994 CEFBS_None, // CNDGE_eg
2995 CEFBS_None, // CNDGE_r600
2996 CEFBS_None, // CNDGT_INT
2997 CEFBS_None, // CNDGT_eg
2998 CEFBS_None, // CNDGT_r600
2999 CEFBS_None, // COS_cm
3000 CEFBS_None, // COS_eg
3001 CEFBS_None, // COS_r600
3002 CEFBS_None, // COS_r700
3003 CEFBS_None, // CUBE_eg_real
3004 CEFBS_None, // CUBE_r600_real
3005 CEFBS_None, // DOT4_eg
3006 CEFBS_None, // DOT4_r600
3007 CEFBS_None, // EG_ExportBuf
3008 CEFBS_None, // EG_ExportSwz
3009 CEFBS_None, // END_LOOP_EG
3010 CEFBS_None, // END_LOOP_R600
3011 CEFBS_None, // EXP_IEEE_cm
3012 CEFBS_None, // EXP_IEEE_eg
3013 CEFBS_None, // EXP_IEEE_r600
3014 CEFBS_None, // FETCH_CLAUSE
3015 CEFBS_None, // FFBH_UINT
3016 CEFBS_None, // FFBL_INT
3017 CEFBS_None, // FLOOR
3018 CEFBS_None, // FLT16_TO_FLT32
3019 CEFBS_None, // FLT32_TO_FLT16
3020 CEFBS_None, // FLT_TO_INT_eg
3021 CEFBS_None, // FLT_TO_INT_r600
3022 CEFBS_None, // FLT_TO_UINT_eg
3023 CEFBS_None, // FLT_TO_UINT_r600
3024 CEFBS_None, // FMA_eg
3025 CEFBS_None, // FRACT
3026 CEFBS_None, // GROUP_BARRIER
3027 CEFBS_None, // INTERP_LOAD_P0
3028 CEFBS_None, // INTERP_PAIR_XY
3029 CEFBS_None, // INTERP_PAIR_ZW
3030 CEFBS_None, // INTERP_VEC_LOAD
3031 CEFBS_None, // INTERP_XY
3032 CEFBS_None, // INTERP_ZW
3033 CEFBS_None, // INT_TO_FLT_eg
3034 CEFBS_None, // INT_TO_FLT_r600
3035 CEFBS_None, // KILLGT
3036 CEFBS_None, // LDS_ADD
3037 CEFBS_None, // LDS_ADD_RET
3038 CEFBS_None, // LDS_AND
3039 CEFBS_None, // LDS_AND_RET
3040 CEFBS_None, // LDS_BYTE_READ_RET
3041 CEFBS_None, // LDS_BYTE_WRITE
3042 CEFBS_None, // LDS_CMPST
3043 CEFBS_None, // LDS_CMPST_RET
3044 CEFBS_None, // LDS_MAX_INT
3045 CEFBS_None, // LDS_MAX_INT_RET
3046 CEFBS_None, // LDS_MAX_UINT
3047 CEFBS_None, // LDS_MAX_UINT_RET
3048 CEFBS_None, // LDS_MIN_INT
3049 CEFBS_None, // LDS_MIN_INT_RET
3050 CEFBS_None, // LDS_MIN_UINT
3051 CEFBS_None, // LDS_MIN_UINT_RET
3052 CEFBS_None, // LDS_OR
3053 CEFBS_None, // LDS_OR_RET
3054 CEFBS_None, // LDS_READ_RET
3055 CEFBS_None, // LDS_SHORT_READ_RET
3056 CEFBS_None, // LDS_SHORT_WRITE
3057 CEFBS_None, // LDS_SUB
3058 CEFBS_None, // LDS_SUB_RET
3059 CEFBS_None, // LDS_UBYTE_READ_RET
3060 CEFBS_None, // LDS_USHORT_READ_RET
3061 CEFBS_None, // LDS_WRITE
3062 CEFBS_None, // LDS_WRXCHG
3063 CEFBS_None, // LDS_WRXCHG_RET
3064 CEFBS_None, // LDS_XOR
3065 CEFBS_None, // LDS_XOR_RET
3066 CEFBS_None, // LITERALS
3067 CEFBS_None, // LOG_CLAMPED_eg
3068 CEFBS_None, // LOG_CLAMPED_r600
3069 CEFBS_None, // LOG_IEEE_cm
3070 CEFBS_None, // LOG_IEEE_eg
3071 CEFBS_None, // LOG_IEEE_r600
3072 CEFBS_None, // LOOP_BREAK_EG
3073 CEFBS_None, // LOOP_BREAK_R600
3074 CEFBS_None, // LSHL_eg
3075 CEFBS_None, // LSHL_r600
3076 CEFBS_None, // LSHR_eg
3077 CEFBS_None, // LSHR_r600
3078 CEFBS_None, // MAX
3079 CEFBS_None, // MAX_DX10
3080 CEFBS_None, // MAX_INT
3081 CEFBS_None, // MAX_UINT
3082 CEFBS_None, // MIN
3083 CEFBS_None, // MIN_DX10
3084 CEFBS_None, // MIN_INT
3085 CEFBS_None, // MIN_UINT
3086 CEFBS_None, // MOV
3087 CEFBS_None, // MOVA_INT_eg
3088 CEFBS_None, // MUL
3089 CEFBS_None, // MULADD_IEEE_eg
3090 CEFBS_None, // MULADD_IEEE_r600
3091 CEFBS_None, // MULADD_INT24_cm
3092 CEFBS_None, // MULADD_UINT24_eg
3093 CEFBS_None, // MULADD_eg
3094 CEFBS_None, // MULADD_r600
3095 CEFBS_None, // MULHI_INT_cm
3096 CEFBS_None, // MULHI_INT_cm24
3097 CEFBS_None, // MULHI_INT_eg
3098 CEFBS_None, // MULHI_INT_r600
3099 CEFBS_None, // MULHI_UINT24_eg
3100 CEFBS_None, // MULHI_UINT_cm
3101 CEFBS_None, // MULHI_UINT_cm24
3102 CEFBS_None, // MULHI_UINT_eg
3103 CEFBS_None, // MULHI_UINT_r600
3104 CEFBS_None, // MULLO_INT_cm
3105 CEFBS_None, // MULLO_INT_eg
3106 CEFBS_None, // MULLO_INT_r600
3107 CEFBS_None, // MULLO_UINT_cm
3108 CEFBS_None, // MULLO_UINT_eg
3109 CEFBS_None, // MULLO_UINT_r600
3110 CEFBS_None, // MUL_IEEE
3111 CEFBS_None, // MUL_INT24_cm
3112 CEFBS_None, // MUL_LIT_eg
3113 CEFBS_None, // MUL_LIT_r600
3114 CEFBS_None, // MUL_UINT24_eg
3115 CEFBS_None, // NOT_INT
3116 CEFBS_None, // OR_INT
3117 CEFBS_None, // PAD
3118 CEFBS_None, // POP_EG
3119 CEFBS_None, // POP_R600
3120 CEFBS_None, // PRED_SETE
3121 CEFBS_None, // PRED_SETE_INT
3122 CEFBS_None, // PRED_SETGE
3123 CEFBS_None, // PRED_SETGE_INT
3124 CEFBS_None, // PRED_SETGT
3125 CEFBS_None, // PRED_SETGT_INT
3126 CEFBS_None, // PRED_SETNE
3127 CEFBS_None, // PRED_SETNE_INT
3128 CEFBS_None, // R600_ExportBuf
3129 CEFBS_None, // R600_ExportSwz
3130 CEFBS_None, // RAT_ATOMIC_ADD_NORET
3131 CEFBS_None, // RAT_ATOMIC_ADD_RTN
3132 CEFBS_None, // RAT_ATOMIC_AND_NORET
3133 CEFBS_None, // RAT_ATOMIC_AND_RTN
3134 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET
3135 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN
3136 CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET
3137 CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN
3138 CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET
3139 CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN
3140 CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET
3141 CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN
3142 CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET
3143 CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN
3144 CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET
3145 CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN
3146 CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET
3147 CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN
3148 CEFBS_None, // RAT_ATOMIC_OR_NORET
3149 CEFBS_None, // RAT_ATOMIC_OR_RTN
3150 CEFBS_None, // RAT_ATOMIC_RSUB_NORET
3151 CEFBS_None, // RAT_ATOMIC_RSUB_RTN
3152 CEFBS_None, // RAT_ATOMIC_SUB_NORET
3153 CEFBS_None, // RAT_ATOMIC_SUB_RTN
3154 CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET
3155 CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN
3156 CEFBS_None, // RAT_ATOMIC_XOR_NORET
3157 CEFBS_None, // RAT_ATOMIC_XOR_RTN
3158 CEFBS_None, // RAT_MSKOR
3159 CEFBS_None, // RAT_STORE_DWORD128
3160 CEFBS_None, // RAT_STORE_DWORD32
3161 CEFBS_None, // RAT_STORE_DWORD64
3162 CEFBS_None, // RAT_STORE_TYPED_cm
3163 CEFBS_None, // RAT_STORE_TYPED_eg
3164 CEFBS_None, // RAT_WRITE_CACHELESS_128_eg
3165 CEFBS_None, // RAT_WRITE_CACHELESS_32_eg
3166 CEFBS_None, // RAT_WRITE_CACHELESS_64_eg
3167 CEFBS_None, // RECIPSQRT_CLAMPED_cm
3168 CEFBS_None, // RECIPSQRT_CLAMPED_eg
3169 CEFBS_None, // RECIPSQRT_CLAMPED_r600
3170 CEFBS_None, // RECIPSQRT_IEEE_cm
3171 CEFBS_None, // RECIPSQRT_IEEE_eg
3172 CEFBS_None, // RECIPSQRT_IEEE_r600
3173 CEFBS_None, // RECIP_CLAMPED_cm
3174 CEFBS_None, // RECIP_CLAMPED_eg
3175 CEFBS_None, // RECIP_CLAMPED_r600
3176 CEFBS_None, // RECIP_IEEE_cm
3177 CEFBS_None, // RECIP_IEEE_eg
3178 CEFBS_None, // RECIP_IEEE_r600
3179 CEFBS_None, // RECIP_UINT_eg
3180 CEFBS_None, // RECIP_UINT_r600
3181 CEFBS_None, // RNDNE
3182 CEFBS_None, // SETE
3183 CEFBS_None, // SETE_DX10
3184 CEFBS_None, // SETE_INT
3185 CEFBS_None, // SETGE_DX10
3186 CEFBS_None, // SETGE_INT
3187 CEFBS_None, // SETGE_UINT
3188 CEFBS_None, // SETGT_DX10
3189 CEFBS_None, // SETGT_INT
3190 CEFBS_None, // SETGT_UINT
3191 CEFBS_None, // SETNE_DX10
3192 CEFBS_None, // SETNE_INT
3193 CEFBS_None, // SGE
3194 CEFBS_None, // SGT
3195 CEFBS_None, // SIN_cm
3196 CEFBS_None, // SIN_eg
3197 CEFBS_None, // SIN_r600
3198 CEFBS_None, // SIN_r700
3199 CEFBS_None, // SNE
3200 CEFBS_None, // SUBB_UINT
3201 CEFBS_None, // SUB_INT
3202 CEFBS_None, // TEX_GET_GRADIENTS_H
3203 CEFBS_None, // TEX_GET_GRADIENTS_V
3204 CEFBS_None, // TEX_GET_TEXTURE_RESINFO
3205 CEFBS_None, // TEX_LD
3206 CEFBS_None, // TEX_LDPTR
3207 CEFBS_None, // TEX_SAMPLE
3208 CEFBS_None, // TEX_SAMPLE_C
3209 CEFBS_None, // TEX_SAMPLE_C_G
3210 CEFBS_None, // TEX_SAMPLE_C_L
3211 CEFBS_None, // TEX_SAMPLE_C_LB
3212 CEFBS_None, // TEX_SAMPLE_G
3213 CEFBS_None, // TEX_SAMPLE_L
3214 CEFBS_None, // TEX_SAMPLE_LB
3215 CEFBS_None, // TEX_SET_GRADIENTS_H
3216 CEFBS_None, // TEX_SET_GRADIENTS_V
3217 CEFBS_None, // TEX_VTX_CONSTBUF
3218 CEFBS_None, // TEX_VTX_TEXBUF
3219 CEFBS_None, // TRUNC
3220 CEFBS_None, // UINT_TO_FLT_eg
3221 CEFBS_None, // UINT_TO_FLT_r600
3222 CEFBS_None, // VTX_READ_128_cm
3223 CEFBS_None, // VTX_READ_128_eg
3224 CEFBS_None, // VTX_READ_16_cm
3225 CEFBS_None, // VTX_READ_16_eg
3226 CEFBS_None, // VTX_READ_32_cm
3227 CEFBS_None, // VTX_READ_32_eg
3228 CEFBS_None, // VTX_READ_64_cm
3229 CEFBS_None, // VTX_READ_64_eg
3230 CEFBS_None, // VTX_READ_8_cm
3231 CEFBS_None, // VTX_READ_8_eg
3232 CEFBS_None, // WHILE_LOOP_EG
3233 CEFBS_None, // WHILE_LOOP_R600
3234 CEFBS_None, // XOR_INT
3235 };
3236
3237 assert(Opcode < 665);
3238 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3239}
3240
3241
3242} // namespace llvm::R600_MC
3243
3244#endif // GET_COMPUTE_FEATURES
3245
3246#ifdef GET_AVAILABLE_OPCODE_CHECKER
3247#undef GET_AVAILABLE_OPCODE_CHECKER
3248
3249namespace llvm::R600_MC {
3250
3251bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3252 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3253 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3254 FeatureBitset MissingFeatures =
3255 (AvailableFeatures & RequiredFeatures) ^
3256 RequiredFeatures;
3257 return !MissingFeatures.any();
3258}
3259
3260} // namespace llvm::R600_MC
3261
3262#endif // GET_AVAILABLE_OPCODE_CHECKER
3263
3264#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3265#undef ENABLE_INSTR_PREDICATE_VERIFIER
3266
3267#include <sstream>
3268
3269namespace llvm::R600_MC {
3270
3271#ifndef NDEBUG
3272static const char *SubtargetFeatureNames[] = {
3273 nullptr
3274};
3275
3276#endif // NDEBUG
3277
3278void verifyInstructionPredicates(
3279 unsigned Opcode, const FeatureBitset &Features) {
3280#ifndef NDEBUG
3281 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3282 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3283 FeatureBitset MissingFeatures =
3284 (AvailableFeatures & RequiredFeatures) ^
3285 RequiredFeatures;
3286 if (MissingFeatures.any()) {
3287 std::ostringstream Msg;
3288 Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
3289 << " instruction but the ";
3290 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3291 if (MissingFeatures.test(i))
3292 Msg << SubtargetFeatureNames[i] << " ";
3293 Msg << "predicate(s) are not met";
3294 report_fatal_error(Msg.str().c_str());
3295 }
3296#endif // NDEBUG
3297}
3298
3299} // namespace llvm::R600_MC
3300
3301#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3302
3303#ifdef GET_INSTRMAP_INFO
3304#undef GET_INSTRMAP_INFO
3305
3306namespace llvm::R600 {
3307
3308enum usesCustomInserter {
3309 usesCustomInserter_0
3310};
3311
3312// getLDSNoRetOp
3313LLVM_READONLY
3314int32_t getLDSNoRetOp(uint32_t Opcode) {
3315 using namespace R600;
3316 static constexpr uint32_t Table[][2] = {
3317 { LDS_ADD_RET, LDS_ADD },
3318 { LDS_AND_RET, LDS_AND },
3319 { LDS_MAX_INT_RET, LDS_MAX_INT },
3320 { LDS_MAX_UINT_RET, LDS_MAX_UINT },
3321 { LDS_MIN_INT_RET, LDS_MIN_INT },
3322 { LDS_MIN_UINT_RET, LDS_MIN_UINT },
3323 { LDS_OR_RET, LDS_OR },
3324 { LDS_SUB_RET, LDS_SUB },
3325 { LDS_WRXCHG_RET, LDS_WRXCHG },
3326 { LDS_XOR_RET, LDS_XOR },
3327 }; // End of Table
3328
3329 unsigned mid;
3330 unsigned start = 0;
3331 unsigned end = 10;
3332 while (start < end) {
3333 mid = start + (end - start) / 2;
3334 if (Opcode == Table[mid][0])
3335 break;
3336 if (Opcode < Table[mid][0])
3337 end = mid;
3338 else
3339 start = mid + 1;
3340 }
3341 if (start == end)
3342 return -1; // Instruction doesn't exist in this table.
3343
3344 return Table[mid][1];
3345}
3346
3347
3348} // namespace llvm::R600
3349
3350#endif // GET_INSTRMAP_INFO
3351
3352