1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::R600 {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1540
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553
96 G_INSERT = 81, // GenericOpcodes.td:1562
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1572
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340
114 G_LOAD = 99, // GenericOpcodes.td:1367
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1376
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1384
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1393
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420
121 G_STORE = 106, // GenericOpcodes.td:1428
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1446
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502
149 G_FENCE = 134, // GenericOpcodes.td:1518
150 G_PREFETCH = 135, // GenericOpcodes.td:1525
151 G_BRCOND = 136, // GenericOpcodes.td:1665
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1674
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697
154 G_INTRINSIC = 139, // GenericOpcodes.td:1617
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:619
183 G_UADDE = 168, // GenericOpcodes.td:627
184 G_USUBO = 169, // GenericOpcodes.td:649
185 G_USUBE = 170, // GenericOpcodes.td:655
186 G_SADDO = 171, // GenericOpcodes.td:634
187 G_SADDE = 172, // GenericOpcodes.td:642
188 G_SSUBO = 173, // GenericOpcodes.td:662
189 G_SSUBE = 174, // GenericOpcodes.td:669
190 G_UMULO = 175, // GenericOpcodes.td:676
191 G_SMULO = 176, // GenericOpcodes.td:684
192 G_UMULH = 177, // GenericOpcodes.td:693
193 G_SMULH = 178, // GenericOpcodes.td:702
194 G_UADDSAT = 179, // GenericOpcodes.td:714
195 G_SADDSAT = 180, // GenericOpcodes.td:722
196 G_USUBSAT = 181, // GenericOpcodes.td:730
197 G_SSUBSAT = 182, // GenericOpcodes.td:738
198 G_USHLSAT = 183, // GenericOpcodes.td:746
199 G_SSHLSAT = 184, // GenericOpcodes.td:754
200 G_SMULFIX = 185, // GenericOpcodes.td:766
201 G_UMULFIX = 186, // GenericOpcodes.td:773
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:783
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:790
204 G_SDIVFIX = 189, // GenericOpcodes.td:801
205 G_UDIVFIX = 190, // GenericOpcodes.td:808
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:818
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:825
208 G_FADD = 193, // GenericOpcodes.td:998
209 G_FSUB = 194, // GenericOpcodes.td:1006
210 G_FMUL = 195, // GenericOpcodes.td:1014
211 G_FMA = 196, // GenericOpcodes.td:1023
212 G_FMAD = 197, // GenericOpcodes.td:1032
213 G_FDIV = 198, // GenericOpcodes.td:1040
214 G_FREM = 199, // GenericOpcodes.td:1047
215 G_FMODF = 200, // GenericOpcodes.td:1054
216 G_FPOW = 201, // GenericOpcodes.td:1061
217 G_FPOWI = 202, // GenericOpcodes.td:1068
218 G_FEXP = 203, // GenericOpcodes.td:1075
219 G_FEXP2 = 204, // GenericOpcodes.td:1082
220 G_FEXP10 = 205, // GenericOpcodes.td:1089
221 G_FLOG = 206, // GenericOpcodes.td:1096
222 G_FLOG2 = 207, // GenericOpcodes.td:1103
223 G_FLOG10 = 208, // GenericOpcodes.td:1110
224 G_FLDEXP = 209, // GenericOpcodes.td:1117
225 G_FFREXP = 210, // GenericOpcodes.td:1124
226 G_FNEG = 211, // GenericOpcodes.td:836
227 G_FPEXT = 212, // GenericOpcodes.td:842
228 G_FPTRUNC = 213, // GenericOpcodes.td:848
229 G_FPTOSI = 214, // GenericOpcodes.td:854
230 G_FPTOUI = 215, // GenericOpcodes.td:860
231 G_SITOFP = 216, // GenericOpcodes.td:866
232 G_UITOFP = 217, // GenericOpcodes.td:872
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:878
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:884
235 G_FABS = 220, // GenericOpcodes.td:890
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:896
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:909
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:902
239 G_FMINNUM = 224, // GenericOpcodes.td:922
240 G_FMAXNUM = 225, // GenericOpcodes.td:929
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954
243 G_FMINIMUM = 228, // GenericOpcodes.td:964
244 G_FMAXIMUM = 229, // GenericOpcodes.td:971
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:979
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986
247 G_GET_FPENV = 232, // GenericOpcodes.td:1254
248 G_SET_FPENV = 233, // GenericOpcodes.td:1261
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1268
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1275
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1282
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1289
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1346
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1352
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1655
265 G_BRJT = 250, // GenericOpcodes.td:1685
266 G_VSCALE = 251, // GenericOpcodes.td:1583
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1780
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_CLMULR = 270, // GenericOpcodes.td:606
286 G_FCEIL = 271, // GenericOpcodes.td:1131
287 G_FCOS = 272, // GenericOpcodes.td:1138
288 G_FSIN = 273, // GenericOpcodes.td:1145
289 G_FSINCOS = 274, // GenericOpcodes.td:1152
290 G_FTAN = 275, // GenericOpcodes.td:1159
291 G_FACOS = 276, // GenericOpcodes.td:1166
292 G_FASIN = 277, // GenericOpcodes.td:1173
293 G_FATAN = 278, // GenericOpcodes.td:1180
294 G_FATAN2 = 279, // GenericOpcodes.td:1187
295 G_FCOSH = 280, // GenericOpcodes.td:1194
296 G_FSINH = 281, // GenericOpcodes.td:1201
297 G_FTANH = 282, // GenericOpcodes.td:1208
298 G_FSQRT = 283, // GenericOpcodes.td:1218
299 G_FFLOOR = 284, // GenericOpcodes.td:1225
300 G_FRINT = 285, // GenericOpcodes.td:1232
301 G_FNEARBYINT = 286, // GenericOpcodes.td:1239
302 G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248
303 G_BLOCK_ADDR = 288, // GenericOpcodes.td:254
304 G_JUMP_TABLE = 289, // GenericOpcodes.td:260
305 G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266
306 G_STACKSAVE = 291, // GenericOpcodes.td:272
307 G_STACKRESTORE = 292, // GenericOpcodes.td:278
308 G_STRICT_FADD = 293, // GenericOpcodes.td:1839
309 G_STRICT_FSUB = 294, // GenericOpcodes.td:1840
310 G_STRICT_FMUL = 295, // GenericOpcodes.td:1841
311 G_STRICT_FDIV = 296, // GenericOpcodes.td:1842
312 G_STRICT_FREM = 297, // GenericOpcodes.td:1843
313 G_STRICT_FMA = 298, // GenericOpcodes.td:1844
314 G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845
315 G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846
316 G_STRICT_FCMP = 301, // GenericOpcodes.td:1847
317 G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848
318 G_READ_REGISTER = 303, // GenericOpcodes.td:1704
319 G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714
320 G_MEMCPY = 305, // GenericOpcodes.td:1854
321 G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862
322 G_MEMMOVE = 307, // GenericOpcodes.td:1870
323 G_MEMSET = 308, // GenericOpcodes.td:1878
324 G_BZERO = 309, // GenericOpcodes.td:1885
325 G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892
326 G_TRAP = 311, // GenericOpcodes.td:1902
327 G_DEBUGTRAP = 312, // GenericOpcodes.td:1909
328 G_UBSANTRAP = 313, // GenericOpcodes.td:1915
329 G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803
330 G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809
331 G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815
332 G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816
333 G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818
334 G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819
335 G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820
336 G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821
337 G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822
338 G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823
339 G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825
340 G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826
341 G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827
342 G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828
343 G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829
344 G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830
345 G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831
346 G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832
347 G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833
348 G_SBFX = 333, // GenericOpcodes.td:1927
349 G_UBFX = 334, // GenericOpcodes.td:1935
350 BRANCH = 335, // R600Instructions.td:1594
351 BRANCH_COND_f32 = 336, // R600Instructions.td:1567
352 BRANCH_COND_i32 = 337, // R600Instructions.td:1563
353 BREAK = 338, // R600Instructions.td:1608
354 BREAKC_f32 = 339, // R600Instructions.td:1584
355 BREAKC_i32 = 340, // R600Instructions.td:1582
356 BREAK_LOGICALNZ_f32 = 341, // R600Instructions.td:1577
357 BREAK_LOGICALNZ_i32 = 342, // R600Instructions.td:1575
358 BREAK_LOGICALZ_f32 = 343, // R600Instructions.td:1577
359 BREAK_LOGICALZ_i32 = 344, // R600Instructions.td:1575
360 CONST_COPY = 345, // R600Instructions.td:1439
361 CONTINUE = 346, // R600Instructions.td:1610
362 CONTINUEC_f32 = 347, // R600Instructions.td:1584
363 CONTINUEC_i32 = 348, // R600Instructions.td:1582
364 CONTINUE_LOGICALNZ_f32 = 349, // R600Instructions.td:1577
365 CONTINUE_LOGICALNZ_i32 = 350, // R600Instructions.td:1575
366 CONTINUE_LOGICALZ_f32 = 351, // R600Instructions.td:1577
367 CONTINUE_LOGICALZ_i32 = 352, // R600Instructions.td:1575
368 CUBE_eg_pseudo = 353, // R600Instructions.td:1074
369 CUBE_r600_pseudo = 354, // R600Instructions.td:1074
370 DEFAULT = 355, // R600Instructions.td:1612
371 DOT_4 = 356, // R600Instructions.td:1061
372 DUMMY_CHAIN = 357, // R600Instructions.td:792
373 ELSE = 358, // R600Instructions.td:1614
374 END = 359, // R600Instructions.td:1620
375 ENDFUNC = 360, // R600Instructions.td:1622
376 ENDIF = 361, // R600Instructions.td:1624
377 ENDLOOP = 362, // R600Instructions.td:1628
378 ENDMAIN = 363, // R600Instructions.td:1618
379 ENDSWITCH = 364, // R600Instructions.td:1616
380 FABS_R600 = 365, // R600Instructions.td:1204
381 FNEG_R600 = 366, // R600Instructions.td:1205
382 FUNC = 367, // R600Instructions.td:1630
383 IFC_f32 = 368, // R600Instructions.td:1584
384 IFC_i32 = 369, // R600Instructions.td:1582
385 IF_LOGICALNZ_f32 = 370, // R600Instructions.td:1577
386 IF_LOGICALNZ_i32 = 371, // R600Instructions.td:1575
387 IF_LOGICALZ_f32 = 372, // R600Instructions.td:1577
388 IF_LOGICALZ_i32 = 373, // R600Instructions.td:1575
389 IF_PREDICATE_SET = 374, // R600Instructions.td:1604
390 JUMP = 375, // R600Instructions.td:1385
391 JUMP_COND = 376, // R600Instructions.td:1378
392 MASK_WRITE = 377, // R600Instructions.td:1402
393 MOV_IMM_F32 = 378, // R600Instructions.td:827
394 MOV_IMM_GLOBAL_ADDR = 379, // R600Instructions.td:820
395 MOV_IMM_I32 = 380, // R600Instructions.td:814
396 PRED_X = 381, // R600Instructions.td:1370
397 R600_EXTRACT_ELT_V2 = 382, // R600Instructions.td:1677
398 R600_EXTRACT_ELT_V4 = 383, // R600Instructions.td:1678
399 R600_INSERT_ELT_V2 = 384, // R600Instructions.td:1680
400 R600_INSERT_ELT_V4 = 385, // R600Instructions.td:1681
401 R600_RegisterLoad = 386, // R600Instructions.td:698
402 R600_RegisterStore = 387, // R600Instructions.td:707
403 RETDYN = 388, // R600Instructions.td:1632
404 RETURN = 389, // R600Instructions.td:88
405 TXD = 390, // R600Instructions.td:1413
406 TXD_SHADOW = 391, // R600Instructions.td:1422
407 WHILELOOP = 392, // R600Instructions.td:1626
408 ADD = 393, // R600Instructions.td:721
409 ADDC_UINT = 394, // EvergreenInstructions.td:523
410 ADD_INT = 395, // R600Instructions.td:848
411 ALU_CLAUSE = 396, // R600Instructions.td:646
412 AND_INT = 397, // R600Instructions.td:844
413 ASHR_eg = 398, // EvergreenInstructions.td:508
414 ASHR_r600 = 399, // R600Instructions.td:1253
415 BCNT_INT = 400, // EvergreenInstructions.td:528
416 BFE_INT_eg = 401, // EvergreenInstructions.td:370
417 BFE_UINT_eg = 402, // EvergreenInstructions.td:365
418 BFI_INT_eg = 403, // EvergreenInstructions.td:411
419 BFM_INT_eg = 404, // EvergreenInstructions.td:492
420 BIT_ALIGN_INT_eg = 405, // EvergreenInstructions.td:500
421 CEIL = 406, // R600Instructions.td:781
422 CF_ALU = 407, // R600Instructions.td:631
423 CF_ALU_BREAK = 408, // R600Instructions.td:635
424 CF_ALU_CONTINUE = 409, // R600Instructions.td:634
425 CF_ALU_ELSE_AFTER = 410, // R600Instructions.td:636
426 CF_ALU_POP_AFTER = 411, // R600Instructions.td:633
427 CF_ALU_PUSH_BEFORE = 412, // R600Instructions.td:632
428 CF_CALL_FS_EG = 413, // EvergreenInstructions.td:850
429 CF_CALL_FS_R600 = 414, // R600Instructions.td:1325
430 CF_CONTINUE_EG = 415, // EvergreenInstructions.td:833
431 CF_CONTINUE_R600 = 416, // R600Instructions.td:1307
432 CF_ELSE_EG = 417, // EvergreenInstructions.td:846
433 CF_ELSE_R600 = 418, // R600Instructions.td:1321
434 CF_END_CM = 419, // CaymanInstructions.td:66
435 CF_END_EG = 420, // EvergreenInstructions.td:859
436 CF_END_R600 = 421, // R600Instructions.td:1334
437 CF_JUMP_EG = 422, // EvergreenInstructions.td:838
438 CF_JUMP_R600 = 423, // R600Instructions.td:1312
439 CF_PUSH_EG = 424, // EvergreenInstructions.td:842
440 CF_PUSH_ELSE_R600 = 425, // R600Instructions.td:1316
441 CF_TC_EG = 426, // EvergreenInstructions.td:811
442 CF_TC_R600 = 427, // R600Instructions.td:1285
443 CF_VC_EG = 428, // EvergreenInstructions.td:815
444 CF_VC_R600 = 429, // R600Instructions.td:1289
445 CNDE_INT = 430, // R600Instructions.td:890
446 CNDE_eg = 431, // EvergreenInstructions.td:511
447 CNDE_r600 = 432, // R600Instructions.td:1235
448 CNDGE_INT = 433, // R600Instructions.td:895
449 CNDGE_eg = 434, // EvergreenInstructions.td:513
450 CNDGE_r600 = 435, // R600Instructions.td:1237
451 CNDGT_INT = 436, // R600Instructions.td:900
452 CNDGT_eg = 437, // EvergreenInstructions.td:512
453 CNDGT_r600 = 438, // R600Instructions.td:1236
454 COS_cm = 439, // CaymanInstructions.td:48
455 COS_eg = 440, // EvergreenInstructions.td:132
456 COS_r600 = 441, // R600Instructions.td:1252
457 COS_r700 = 442, // R700Instructions.td:19
458 CUBE_eg_real = 443, // R600Instructions.td:1085
459 CUBE_r600_real = 444, // R600Instructions.td:1085
460 DOT4_eg = 445, // EvergreenInstructions.td:519
461 DOT4_r600 = 446, // R600Instructions.td:1238
462 EG_ExportBuf = 447, // EvergreenInstructions.td:801
463 EG_ExportSwz = 448, // EvergreenInstructions.td:791
464 END_LOOP_EG = 449, // EvergreenInstructions.td:824
465 END_LOOP_R600 = 450, // R600Instructions.td:1298
466 EXP_IEEE_cm = 451, // CaymanInstructions.td:43
467 EXP_IEEE_eg = 452, // EvergreenInstructions.td:125
468 EXP_IEEE_r600 = 453, // R600Instructions.td:1240
469 FETCH_CLAUSE = 454, // R600Instructions.td:638
470 FFBH_UINT = 455, // EvergreenInstructions.td:529
471 FFBL_INT = 456, // EvergreenInstructions.td:530
472 FLOOR = 457, // R600Instructions.td:783
473 FLT16_TO_FLT32 = 458, // EvergreenInstructions.td:527
474 FLT32_TO_FLT16 = 459, // EvergreenInstructions.td:526
475 FLT_TO_INT_eg = 460, // EvergreenInstructions.td:536
476 FLT_TO_INT_r600 = 461, // R600Instructions.td:1247
477 FLT_TO_UINT_eg = 462, // EvergreenInstructions.td:543
478 FLT_TO_UINT_r600 = 463, // R600Instructions.td:1249
479 FMA_eg = 464, // EvergreenInstructions.td:507
480 FRACT = 465, // R600Instructions.td:779
481 GROUP_BARRIER = 466, // EvergreenInstructions.td:549
482 INTERP_LOAD_P0 = 467, // R600Instructions.td:445
483 INTERP_PAIR_XY = 468, // R600Instructions.td:367
484 INTERP_PAIR_ZW = 469, // R600Instructions.td:373
485 INTERP_VEC_LOAD = 470, // R600Instructions.td:430
486 INTERP_XY = 471, // R600Instructions.td:437
487 INTERP_ZW = 472, // R600Instructions.td:441
488 INT_TO_FLT_eg = 473, // EvergreenInstructions.td:541
489 INT_TO_FLT_r600 = 474, // R600Instructions.td:1248
490 KILLGT = 475, // R600Instructions.td:840
491 LDS_ADD = 476, // EvergreenInstructions.td:687
492 LDS_ADD_RET = 477, // EvergreenInstructions.td:707
493 LDS_AND = 478, // EvergreenInstructions.td:689
494 LDS_AND_RET = 479, // EvergreenInstructions.td:713
495 LDS_BYTE_READ_RET = 480, // EvergreenInstructions.td:743
496 LDS_BYTE_WRITE = 481, // EvergreenInstructions.td:701
497 LDS_CMPST = 482, // EvergreenInstructions.td:693
498 LDS_CMPST_RET = 483, // EvergreenInstructions.td:737
499 LDS_MAX_INT = 484, // EvergreenInstructions.td:695
500 LDS_MAX_INT_RET = 485, // EvergreenInstructions.td:725
501 LDS_MAX_UINT = 486, // EvergreenInstructions.td:697
502 LDS_MAX_UINT_RET = 487, // EvergreenInstructions.td:731
503 LDS_MIN_INT = 488, // EvergreenInstructions.td:694
504 LDS_MIN_INT_RET = 489, // EvergreenInstructions.td:722
505 LDS_MIN_UINT = 490, // EvergreenInstructions.td:696
506 LDS_MIN_UINT_RET = 491, // EvergreenInstructions.td:728
507 LDS_OR = 492, // EvergreenInstructions.td:690
508 LDS_OR_RET = 493, // EvergreenInstructions.td:716
509 LDS_READ_RET = 494, // EvergreenInstructions.td:740
510 LDS_SHORT_READ_RET = 495, // EvergreenInstructions.td:749
511 LDS_SHORT_WRITE = 496, // EvergreenInstructions.td:704
512 LDS_SUB = 497, // EvergreenInstructions.td:688
513 LDS_SUB_RET = 498, // EvergreenInstructions.td:710
514 LDS_UBYTE_READ_RET = 499, // EvergreenInstructions.td:746
515 LDS_USHORT_READ_RET = 500, // EvergreenInstructions.td:752
516 LDS_WRITE = 501, // EvergreenInstructions.td:698
517 LDS_WRXCHG = 502, // EvergreenInstructions.td:692
518 LDS_WRXCHG_RET = 503, // EvergreenInstructions.td:734
519 LDS_XOR = 504, // EvergreenInstructions.td:691
520 LDS_XOR_RET = 505, // EvergreenInstructions.td:719
521 LITERALS = 506, // R600Instructions.td:654
522 LOG_CLAMPED_eg = 507, // EvergreenInstructions.td:515
523 LOG_CLAMPED_r600 = 508, // R600Instructions.td:1241
524 LOG_IEEE_cm = 509, // CaymanInstructions.td:44
525 LOG_IEEE_eg = 510, // EvergreenInstructions.td:126
526 LOG_IEEE_r600 = 511, // R600Instructions.td:1242
527 LOOP_BREAK_EG = 512, // EvergreenInstructions.td:828
528 LOOP_BREAK_R600 = 513, // R600Instructions.td:1302
529 LSHL_eg = 514, // EvergreenInstructions.td:510
530 LSHL_r600 = 515, // R600Instructions.td:1255
531 LSHR_eg = 516, // EvergreenInstructions.td:509
532 LSHR_r600 = 517, // R600Instructions.td:1254
533 MAX = 518, // R600Instructions.td:726
534 MAX_DX10 = 519, // R600Instructions.td:731
535 MAX_INT = 520, // R600Instructions.td:850
536 MAX_UINT = 521, // R600Instructions.td:852
537 MIN = 522, // R600Instructions.td:727
538 MIN_DX10 = 523, // R600Instructions.td:732
539 MIN_INT = 524, // R600Instructions.td:851
540 MIN_UINT = 525, // R600Instructions.td:853
541 MOV = 526, // R600Instructions.td:785
542 MOVA_INT_eg = 527, // EvergreenInstructions.td:533
543 MUL = 528, // R600Instructions.td:723
544 MULADD_IEEE_eg = 529, // EvergreenInstructions.td:506
545 MULADD_IEEE_r600 = 530, // R600Instructions.td:1234
546 MULADD_INT24_cm = 531, // CaymanInstructions.td:22
547 MULADD_UINT24_eg = 532, // EvergreenInstructions.td:494
548 MULADD_eg = 533, // EvergreenInstructions.td:505
549 MULADD_r600 = 534, // R600Instructions.td:1233
550 MULHI_INT_cm = 535, // CaymanInstructions.td:36
551 MULHI_INT_cm24 = 536, // CaymanInstructions.td:39
552 MULHI_INT_eg = 537, // EvergreenInstructions.td:118
553 MULHI_INT_r600 = 538, // R600Instructions.td:1257
554 MULHI_UINT24_eg = 539, // EvergreenInstructions.td:121
555 MULHI_UINT_cm = 540, // CaymanInstructions.td:38
556 MULHI_UINT_cm24 = 541, // CaymanInstructions.td:40
557 MULHI_UINT_eg = 542, // EvergreenInstructions.td:120
558 MULHI_UINT_r600 = 543, // R600Instructions.td:1259
559 MULLO_INT_cm = 544, // CaymanInstructions.td:35
560 MULLO_INT_eg = 545, // EvergreenInstructions.td:117
561 MULLO_INT_r600 = 546, // R600Instructions.td:1256
562 MULLO_UINT_cm = 547, // CaymanInstructions.td:37
563 MULLO_UINT_eg = 548, // EvergreenInstructions.td:119
564 MULLO_UINT_r600 = 549, // R600Instructions.td:1258
565 MUL_IEEE = 550, // R600Instructions.td:724
566 MUL_INT24_cm = 551, // CaymanInstructions.td:25
567 MUL_LIT_eg = 552, // EvergreenInstructions.td:514
568 MUL_LIT_r600 = 553, // R600Instructions.td:1232
569 MUL_UINT24_eg = 554, // EvergreenInstructions.td:516
570 NOT_INT = 555, // R600Instructions.td:847
571 OR_INT = 556, // R600Instructions.td:845
572 PAD = 557, // R600Instructions.td:666
573 POP_EG = 558, // EvergreenInstructions.td:855
574 POP_R600 = 559, // R600Instructions.td:1330
575 PRED_SETE = 560, // R600Instructions.td:833
576 PRED_SETE_INT = 561, // R600Instructions.td:885
577 PRED_SETGE = 562, // R600Instructions.td:835
578 PRED_SETGE_INT = 563, // R600Instructions.td:887
579 PRED_SETGT = 564, // R600Instructions.td:834
580 PRED_SETGT_INT = 565, // R600Instructions.td:886
581 PRED_SETNE = 566, // R600Instructions.td:836
582 PRED_SETNE_INT = 567, // R600Instructions.td:888
583 R600_ExportBuf = 568, // R600Instructions.td:1276
584 R600_ExportSwz = 569, // R600Instructions.td:1267
585 RAT_ATOMIC_ADD_NORET = 570, // EvergreenInstructions.td:82
586 RAT_ATOMIC_ADD_RTN = 571, // EvergreenInstructions.td:78
587 RAT_ATOMIC_AND_NORET = 572, // EvergreenInstructions.td:82
588 RAT_ATOMIC_AND_RTN = 573, // EvergreenInstructions.td:78
589 RAT_ATOMIC_CMPXCHG_INT_NORET = 574, // EvergreenInstructions.td:82
590 RAT_ATOMIC_CMPXCHG_INT_RTN = 575, // EvergreenInstructions.td:78
591 RAT_ATOMIC_DEC_UINT_NORET = 576, // EvergreenInstructions.td:82
592 RAT_ATOMIC_DEC_UINT_RTN = 577, // EvergreenInstructions.td:78
593 RAT_ATOMIC_INC_UINT_NORET = 578, // EvergreenInstructions.td:82
594 RAT_ATOMIC_INC_UINT_RTN = 579, // EvergreenInstructions.td:78
595 RAT_ATOMIC_MAX_INT_NORET = 580, // EvergreenInstructions.td:82
596 RAT_ATOMIC_MAX_INT_RTN = 581, // EvergreenInstructions.td:78
597 RAT_ATOMIC_MAX_UINT_NORET = 582, // EvergreenInstructions.td:82
598 RAT_ATOMIC_MAX_UINT_RTN = 583, // EvergreenInstructions.td:78
599 RAT_ATOMIC_MIN_INT_NORET = 584, // EvergreenInstructions.td:82
600 RAT_ATOMIC_MIN_INT_RTN = 585, // EvergreenInstructions.td:78
601 RAT_ATOMIC_MIN_UINT_NORET = 586, // EvergreenInstructions.td:82
602 RAT_ATOMIC_MIN_UINT_RTN = 587, // EvergreenInstructions.td:78
603 RAT_ATOMIC_OR_NORET = 588, // EvergreenInstructions.td:82
604 RAT_ATOMIC_OR_RTN = 589, // EvergreenInstructions.td:78
605 RAT_ATOMIC_RSUB_NORET = 590, // EvergreenInstructions.td:82
606 RAT_ATOMIC_RSUB_RTN = 591, // EvergreenInstructions.td:78
607 RAT_ATOMIC_SUB_NORET = 592, // EvergreenInstructions.td:82
608 RAT_ATOMIC_SUB_RTN = 593, // EvergreenInstructions.td:78
609 RAT_ATOMIC_XCHG_INT_NORET = 594, // EvergreenInstructions.td:82
610 RAT_ATOMIC_XCHG_INT_RTN = 595, // EvergreenInstructions.td:78
611 RAT_ATOMIC_XOR_NORET = 596, // EvergreenInstructions.td:82
612 RAT_ATOMIC_XOR_RTN = 597, // EvergreenInstructions.td:78
613 RAT_MSKOR = 598, // EvergreenInstructions.td:67
614 RAT_STORE_DWORD128 = 599, // CaymanInstructions.td:84
615 RAT_STORE_DWORD32 = 600, // CaymanInstructions.td:82
616 RAT_STORE_DWORD64 = 601, // CaymanInstructions.td:83
617 RAT_STORE_TYPED_cm = 602, // CaymanInstructions.td:86
618 RAT_STORE_TYPED_eg = 603, // EvergreenInstructions.td:164
619 RAT_WRITE_CACHELESS_128_eg = 604, // EvergreenInstructions.td:158
620 RAT_WRITE_CACHELESS_32_eg = 605, // EvergreenInstructions.td:144
621 RAT_WRITE_CACHELESS_64_eg = 606, // EvergreenInstructions.td:151
622 RECIPSQRT_CLAMPED_cm = 607, // CaymanInstructions.td:42
623 RECIPSQRT_CLAMPED_eg = 608, // EvergreenInstructions.td:124
624 RECIPSQRT_CLAMPED_r600 = 609, // R600Instructions.td:1245
625 RECIPSQRT_IEEE_cm = 610, // CaymanInstructions.td:46
626 RECIPSQRT_IEEE_eg = 611, // EvergreenInstructions.td:128
627 RECIPSQRT_IEEE_r600 = 612, // R600Instructions.td:1246
628 RECIP_CLAMPED_cm = 613, // CaymanInstructions.td:45
629 RECIP_CLAMPED_eg = 614, // EvergreenInstructions.td:127
630 RECIP_CLAMPED_r600 = 615, // R600Instructions.td:1243
631 RECIP_IEEE_cm = 616, // CaymanInstructions.td:33
632 RECIP_IEEE_eg = 617, // EvergreenInstructions.td:114
633 RECIP_IEEE_r600 = 618, // R600Instructions.td:1244
634 RECIP_UINT_eg = 619, // EvergreenInstructions.td:123
635 RECIP_UINT_r600 = 620, // R600Instructions.td:1260
636 RNDNE = 621, // R600Instructions.td:782
637 SETE = 622, // R600Instructions.td:737
638 SETE_DX10 = 623, // R600Instructions.td:757
639 SETE_INT = 624, // R600Instructions.td:855
640 SETGE_DX10 = 625, // R600Instructions.td:767
641 SETGE_INT = 626, // R600Instructions.td:865
642 SETGE_UINT = 627, // R600Instructions.td:880
643 SETGT_DX10 = 628, // R600Instructions.td:762
644 SETGT_INT = 629, // R600Instructions.td:860
645 SETGT_UINT = 630, // R600Instructions.td:875
646 SETNE_DX10 = 631, // R600Instructions.td:773
647 SETNE_INT = 632, // R600Instructions.td:870
648 SGE = 633, // R600Instructions.td:747
649 SGT = 634, // R600Instructions.td:742
650 SIN_cm = 635, // CaymanInstructions.td:47
651 SIN_eg = 636, // EvergreenInstructions.td:131
652 SIN_r600 = 637, // R600Instructions.td:1251
653 SIN_r700 = 638, // R700Instructions.td:18
654 SNE = 639, // R600Instructions.td:752
655 SUBB_UINT = 640, // EvergreenInstructions.td:524
656 SUB_INT = 641, // R600Instructions.td:849
657 TEX_GET_GRADIENTS_H = 642, // R600Instructions.td:959
658 TEX_GET_GRADIENTS_V = 643, // R600Instructions.td:960
659 TEX_GET_TEXTURE_RESINFO = 644, // R600Instructions.td:958
660 TEX_LD = 645, // R600Instructions.td:954
661 TEX_LDPTR = 646, // R600Instructions.td:955
662 TEX_SAMPLE = 647, // R600Instructions.td:948
663 TEX_SAMPLE_C = 648, // R600Instructions.td:949
664 TEX_SAMPLE_C_G = 649, // R600Instructions.td:964
665 TEX_SAMPLE_C_L = 650, // R600Instructions.td:951
666 TEX_SAMPLE_C_LB = 651, // R600Instructions.td:953
667 TEX_SAMPLE_G = 652, // R600Instructions.td:963
668 TEX_SAMPLE_L = 653, // R600Instructions.td:950
669 TEX_SAMPLE_LB = 654, // R600Instructions.td:952
670 TEX_SET_GRADIENTS_H = 655, // R600Instructions.td:961
671 TEX_SET_GRADIENTS_V = 656, // R600Instructions.td:962
672 TEX_VTX_CONSTBUF = 657, // R600Instructions.td:1451
673 TEX_VTX_TEXBUF = 658, // R600Instructions.td:1505
674 TRUNC = 659, // R600Instructions.td:780
675 UINT_TO_FLT_eg = 660, // EvergreenInstructions.td:547
676 UINT_TO_FLT_r600 = 661, // R600Instructions.td:1250
677 VTX_READ_128_cm = 662, // CaymanInstructions.td:162
678 VTX_READ_128_eg = 663, // EvergreenInstructions.td:240
679 VTX_READ_16_cm = 664, // CaymanInstructions.td:120
680 VTX_READ_16_eg = 665, // EvergreenInstructions.td:195
681 VTX_READ_32_cm = 666, // CaymanInstructions.td:131
682 VTX_READ_32_eg = 667, // EvergreenInstructions.td:207
683 VTX_READ_64_cm = 668, // CaymanInstructions.td:151
684 VTX_READ_64_eg = 669, // EvergreenInstructions.td:228
685 VTX_READ_8_cm = 670, // CaymanInstructions.td:109
686 VTX_READ_8_eg = 671, // EvergreenInstructions.td:183
687 WHILE_LOOP_EG = 672, // EvergreenInstructions.td:819
688 WHILE_LOOP_R600 = 673, // R600Instructions.td:1293
689 XOR_INT = 674, // R600Instructions.td:846
690 INSTRUCTION_LIST_END = 675
691 };
692
693} // namespace llvm::R600
694
695#endif // GET_INSTRINFO_ENUM
696
697#ifdef GET_INSTRINFO_SCHED_ENUM
698#undef GET_INSTRINFO_SCHED_ENUM
699
700namespace llvm::R600::Sched {
701
702 enum {
703 NoInstrModel = 0,
704 NullALU = 1,
705 VecALU = 2,
706 AnyALU = 3,
707 TransALU = 4,
708 XALU = 5,
709 SCHED_LIST_END = 6
710 };
711
712} // namespace llvm::R600::Sched
713
714#endif // GET_INSTRINFO_SCHED_ENUM
715
716#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
717
718namespace llvm {
719
720struct R600InstrTable {
721 MCInstrDesc Insts[675];
722 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
723 MCPhysReg ImplicitOps[1];
724 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
725 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
726 MCOperandInfo OperandInfo[461];
727};
728} // namespace llvm
729
730#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
731
732#ifdef GET_INSTRINFO_MC_DESC
733#undef GET_INSTRINFO_MC_DESC
734
735namespace llvm {
736
737static_assert((sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) % sizeof(MCOperandInfo) == 0);
738static constexpr unsigned R600OpInfoBase = (sizeof R600InstrTable::ImplicitOps + sizeof R600InstrTable::Padding) / sizeof(MCOperandInfo);
739
740extern const R600InstrTable R600Descs = {
741 {
742 { 674, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // XOR_INT
743 { 673, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_R600
744 { 672, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WHILE_LOOP_EG
745 { 671, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_eg
746 { 670, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_8_cm
747 { 669, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_eg
748 { 668, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 457, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_64_cm
749 { 667, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_eg
750 { 666, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 453, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_32_cm
751 { 665, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_eg
752 { 664, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 449, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_16_cm
753 { 663, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_eg
754 { 662, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::MayLoad), 0x1000ULL }, // VTX_READ_128_cm
755 { 661, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_r600
756 { 660, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // UINT_TO_FLT_eg
757 { 659, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // TRUNC
758 { 658, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1000ULL }, // TEX_VTX_TEXBUF
759 { 657, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 445, 0, 0, 0x1000ULL }, // TEX_VTX_CONSTBUF
760 { 656, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_V
761 { 655, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SET_GRADIENTS_H
762 { 654, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_LB
763 { 653, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_L
764 { 652, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_G
765 { 651, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_LB
766 { 650, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_L
767 { 649, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C_G
768 { 648, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE_C
769 { 647, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_SAMPLE
770 { 646, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LDPTR
771 { 645, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_LD
772 { 644, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_TEXTURE_RESINFO
773 { 643, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_V
774 { 642, 19, 1, 0, 1, 0, 0, R600OpInfoBase + 426, 0, 0, 0x2000ULL }, // TEX_GET_GRADIENTS_H
775 { 641, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUB_INT
776 { 640, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SUBB_UINT
777 { 639, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SNE
778 { 638, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r700
779 { 637, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_r600
780 { 636, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // SIN_eg
781 { 635, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // SIN_cm
782 { 634, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGT
783 { 633, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SGE
784 { 632, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_INT
785 { 631, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETNE_DX10
786 { 630, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_UINT
787 { 629, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_INT
788 { 628, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGT_DX10
789 { 627, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_UINT
790 { 626, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_INT
791 { 625, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETGE_DX10
792 { 624, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_INT
793 { 623, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE_DX10
794 { 622, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // SETE
795 { 621, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RNDNE
796 { 620, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_r600
797 { 619, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_UINT_eg
798 { 618, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_r600
799 { 617, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_IEEE_eg
800 { 616, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_IEEE_cm
801 { 615, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_r600
802 { 614, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIP_CLAMPED_eg
803 { 613, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIP_CLAMPED_cm
804 { 612, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_r600
805 { 611, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_IEEE_eg
806 { 610, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_IEEE_cm
807 { 609, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_r600
808 { 608, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // RECIPSQRT_CLAMPED_eg
809 { 607, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // RECIPSQRT_CLAMPED_cm
810 { 606, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 423, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_64_eg
811 { 605, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 420, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_32_eg
812 { 604, 3, 0, 0, 1, 0, 0, R600OpInfoBase + 417, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x20000ULL }, // RAT_WRITE_CACHELESS_128_eg
813 { 603, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_eg
814 { 602, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 413, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_STORE_TYPED_cm
815 { 601, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 411, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD64
816 { 600, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 409, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD32
817 { 599, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_STORE_DWORD128
818 { 598, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 407, 0, 0|(1ULL<<MCID::MayStore), 0x20000ULL }, // RAT_MSKOR
819 { 597, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_RTN
820 { 596, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XOR_NORET
821 { 595, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_RTN
822 { 594, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_XCHG_INT_NORET
823 { 593, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_RTN
824 { 592, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_SUB_NORET
825 { 591, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_RTN
826 { 590, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_RSUB_NORET
827 { 589, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_RTN
828 { 588, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_OR_NORET
829 { 587, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_RTN
830 { 586, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_UINT_NORET
831 { 585, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_RTN
832 { 584, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MIN_INT_NORET
833 { 583, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_RTN
834 { 582, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_UINT_NORET
835 { 581, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_RTN
836 { 580, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_MAX_INT_NORET
837 { 579, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_RTN
838 { 578, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_INC_UINT_NORET
839 { 577, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_RTN
840 { 576, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_DEC_UINT_NORET
841 { 575, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_RTN
842 { 574, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_CMPXCHG_INT_NORET
843 { 573, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_RTN
844 { 572, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_AND_NORET
845 { 571, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_RTN
846 { 570, 3, 1, 0, 1, 0, 0, R600OpInfoBase + 404, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // RAT_ATOMIC_ADD_NORET
847 { 569, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportSwz
848 { 568, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // R600_ExportBuf
849 { 567, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE_INT
850 { 566, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETNE
851 { 565, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT_INT
852 { 564, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGT
853 { 563, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE_INT
854 { 562, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETGE
855 { 561, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE_INT
856 { 560, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // PRED_SETE
857 { 559, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_R600
858 { 558, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // POP_EG
859 { 557, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PAD
860 { 556, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // OR_INT
861 { 555, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // NOT_INT
862 { 554, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_UINT24_eg
863 { 553, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_r600
864 { 552, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MUL_LIT_eg
865 { 551, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_INT24_cm
866 { 550, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL_IEEE
867 { 549, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_r600
868 { 548, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_UINT_eg
869 { 547, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_UINT_cm
870 { 546, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_r600
871 { 545, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULLO_INT_eg
872 { 544, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULLO_INT_cm
873 { 543, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_r600
874 { 542, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT_eg
875 { 541, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm24
876 { 540, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_UINT_cm
877 { 539, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_UINT24_eg
878 { 538, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_r600
879 { 537, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MULHI_INT_eg
880 { 536, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm24
881 { 535, 21, 1, 0, 4, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a40ULL }, // MULHI_INT_cm
882 { 534, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_r600
883 { 533, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_eg
884 { 532, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_UINT24_eg
885 { 531, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_INT24_cm
886 { 530, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_r600
887 { 529, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // MULADD_IEEE_eg
888 { 528, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MUL
889 { 527, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4600ULL }, // MOVA_INT_eg
890 { 526, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // MOV
891 { 525, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_UINT
892 { 524, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_INT
893 { 523, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN_DX10
894 { 522, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MIN
895 { 521, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_UINT
896 { 520, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_INT
897 { 519, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX_DX10
898 { 518, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // MAX
899 { 517, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_r600
900 { 516, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHR_eg
901 { 515, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_r600
902 { 514, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // LSHL_eg
903 { 513, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_R600
904 { 512, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LOOP_BREAK_EG
905 { 511, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_r600
906 { 510, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_IEEE_eg
907 { 509, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // LOG_IEEE_cm
908 { 508, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_r600
909 { 507, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // LOG_CLAMPED_eg
910 { 506, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LITERALS
911 { 505, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_XOR_RET
912 { 504, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_XOR
913 { 503, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_WRXCHG_RET
914 { 502, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_WRXCHG
915 { 501, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_WRITE
916 { 500, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_USHORT_READ_RET
917 { 499, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_UBYTE_READ_RET
918 { 498, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_SUB_RET
919 { 497, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_SUB
920 { 496, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_SHORT_WRITE
921 { 495, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_SHORT_READ_RET
922 { 494, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_READ_RET
923 { 493, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_OR_RET
924 { 492, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_OR
925 { 491, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_UINT_RET
926 { 490, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_UINT
927 { 489, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MIN_INT_RET
928 { 488, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MIN_INT
929 { 487, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_UINT_RET
930 { 486, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_UINT
931 { 485, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_MAX_INT_RET
932 { 484, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_MAX_INT
933 { 483, 13, 1, 0, 5, 0, 0, R600OpInfoBase + 391, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x44200ULL }, // LDS_CMPST_RET
934 { 482, 12, 0, 0, 5, 0, 0, R600OpInfoBase + 379, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44200ULL }, // LDS_CMPST
935 { 481, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x14200ULL }, // LDS_BYTE_WRITE
936 { 480, 7, 1, 0, 5, 0, 0, R600OpInfoBase + 372, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0xc200ULL }, // LDS_BYTE_READ_RET
937 { 479, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_AND_RET
938 { 478, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_AND
939 { 477, 10, 1, 0, 5, 0, 0, R600OpInfoBase + 362, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x14200ULL }, // LDS_ADD_RET
940 { 476, 9, 0, 0, 5, 0, 0, R600OpInfoBase + 353, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x14200ULL }, // LDS_ADD
941 { 475, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a00ULL }, // KILLGT
942 { 474, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_r600
943 { 473, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INT_TO_FLT_eg
944 { 472, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_ZW
945 { 471, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // INTERP_XY
946 { 470, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 351, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_VEC_LOAD
947 { 469, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 346, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_ZW
948 { 468, 5, 2, 0, 1, 0, 0, R600OpInfoBase + 341, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INTERP_PAIR_XY
949 { 467, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // INTERP_LOAD_P0
950 { 466, 0, 0, 0, 3, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000ULL }, // GROUP_BARRIER
951 { 465, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FRACT
952 { 464, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // FMA_eg
953 { 463, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_r600
954 { 462, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_UINT_eg
955 { 461, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_r600
956 { 460, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT_TO_INT_eg
957 { 459, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT32_TO_FLT16
958 { 458, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLT16_TO_FLT32
959 { 457, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FLOOR
960 { 456, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBL_INT
961 { 455, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // FFBH_UINT
962 { 454, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FETCH_CLAUSE
963 { 453, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_r600
964 { 452, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // EXP_IEEE_eg
965 { 451, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4640ULL }, // EXP_IEEE_cm
966 { 450, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_R600
967 { 449, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // END_LOOP_EG
968 { 448, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 332, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportSwz
969 { 447, 7, 0, 0, 1, 0, 0, R600OpInfoBase + 325, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x20000ULL }, // EG_ExportBuf
970 { 446, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_r600
971 { 445, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // DOT4_eg
972 { 444, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_r600_real
973 { 443, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // CUBE_eg_real
974 { 442, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r700
975 { 441, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_r600
976 { 440, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4610ULL }, // COS_eg
977 { 439, 14, 1, 0, 4, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4650ULL }, // COS_cm
978 { 438, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_r600
979 { 437, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_eg
980 { 436, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGT_INT
981 { 435, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_r600
982 { 434, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_eg
983 { 433, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDGE_INT
984 { 432, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_r600
985 { 431, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_eg
986 { 430, 19, 1, 0, 3, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // CNDE_INT
987 { 429, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_R600
988 { 428, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_VC_EG
989 { 427, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_R600
990 { 426, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_TC_EG
991 { 425, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_ELSE_R600
992 { 424, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_PUSH_EG
993 { 423, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_R600
994 { 422, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_JUMP_EG
995 { 421, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_R600
996 { 420, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_EG
997 { 419, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_END_CM
998 { 418, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_R600
999 { 417, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ELSE_EG
1000 { 416, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_R600
1001 { 415, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CONTINUE_EG
1002 { 414, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_R600
1003 { 413, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_CALL_FS_EG
1004 { 412, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_PUSH_BEFORE
1005 { 411, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_POP_AFTER
1006 { 410, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_ELSE_AFTER
1007 { 409, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_CONTINUE
1008 { 408, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU_BREAK
1009 { 407, 9, 0, 0, 1, 0, 0, R600OpInfoBase + 316, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CF_ALU
1010 { 406, 14, 1, 0, 3, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // CEIL
1011 { 405, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BIT_ALIGN_INT_eg
1012 { 404, 21, 1, 0, 2, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // BFM_INT_eg
1013 { 403, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFI_INT_eg
1014 { 402, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_UINT_eg
1015 { 401, 19, 1, 0, 2, 0, 0, R600OpInfoBase + 297, 0, 0|(1ULL<<MCID::Predicable), 0x4220ULL }, // BFE_INT_eg
1016 { 400, 14, 1, 0, 2, 0, 0, R600OpInfoBase + 283, 0, 0|(1ULL<<MCID::Predicable), 0x4600ULL }, // BCNT_INT
1017 { 399, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_r600
1018 { 398, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ASHR_eg
1019 { 397, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // AND_INT
1020 { 396, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ALU_CLAUSE
1021 { 395, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD_INT
1022 { 394, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADDC_UINT
1023 { 393, 21, 1, 0, 3, 0, 0, R600OpInfoBase + 262, 0, 0|(1ULL<<MCID::Predicable), 0x4a00ULL }, // ADD
1024 { 392, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // WHILELOOP
1025 { 391, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD_SHADOW
1026 { 390, 7, 1, 0, 1, 0, 0, R600OpInfoBase + 255, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2000ULL }, // TXD
1027 { 389, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL }, // RETURN
1028 { 388, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // RETDYN
1029 { 387, 4, 0, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4000000000000000ULL }, // R600_RegisterStore
1030 { 386, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 251, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x8000000000000000ULL }, // R600_RegisterLoad
1031 { 385, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 247, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V4
1032 { 384, 4, 1, 0, 3, 0, 0, R600OpInfoBase + 243, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_INSERT_ELT_V2
1033 { 383, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V4
1034 { 382, 3, 1, 0, 3, 0, 0, R600OpInfoBase + 237, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // R600_EXTRACT_ELT_V2
1035 { 381, 4, 1, 0, 1, 0, 0, R600OpInfoBase + 233, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // PRED_X
1036 { 380, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_I32
1037 { 379, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_GLOBAL_ADDR
1038 { 378, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MOV_IMM_F32
1039 { 377, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MASK_WRITE
1040 { 376, 2, 0, 0, 3, 0, 0, R600OpInfoBase + 231, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP_COND
1041 { 375, 1, 0, 0, 3, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMP
1042 { 374, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // IF_PREDICATE_SET
1043 { 373, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_i32
1044 { 372, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALZ_f32
1045 { 371, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_i32
1046 { 370, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IF_LOGICALNZ_f32
1047 { 369, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_i32
1048 { 368, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // IFC_f32
1049 { 367, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // FUNC
1050 { 366, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FNEG_R600
1051 { 365, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // FABS_R600
1052 { 364, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDSWITCH
1053 { 363, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDMAIN
1054 { 362, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDLOOP
1055 { 361, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDIF
1056 { 360, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ENDFUNC
1057 { 359, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // END
1058 { 358, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // ELSE
1059 { 357, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // DUMMY_CHAIN
1060 { 356, 71, 1, 0, 3, 0, 0, R600OpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // DOT_4
1061 { 355, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // DEFAULT
1062 { 354, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_r600_pseudo
1063 { 353, 2, 1, 0, 2, 0, 0, R600OpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // CUBE_eg_pseudo
1064 { 352, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_i32
1065 { 351, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALZ_f32
1066 { 350, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_i32
1067 { 349, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE_LOGICALNZ_f32
1068 { 348, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_i32
1069 { 347, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUEC_f32
1070 { 346, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // CONTINUE
1071 { 345, 2, 1, 0, 1, 0, 0, R600OpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // CONST_COPY
1072 { 344, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_i32
1073 { 343, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALZ_f32
1074 { 342, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_i32
1075 { 341, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK_LOGICALNZ_f32
1076 { 340, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_i32
1077 { 339, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 153, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAKC_f32
1078 { 338, 0, 0, 0, 1, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // BREAK
1079 { 337, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_i32
1080 { 336, 2, 0, 0, 1, 0, 0, R600OpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH_COND_f32
1081 { 335, 1, 0, 0, 1, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BRANCH
1082 { 334, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX
1083 { 333, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX
1084 { 332, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN
1085 { 331, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX
1086 { 330, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN
1087 { 329, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX
1088 { 328, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR
1089 { 327, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR
1090 { 326, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND
1091 { 325, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL
1092 { 324, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD
1093 { 323, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
1094 { 322, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
1095 { 321, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM
1096 { 320, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
1097 { 319, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN
1098 { 318, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX
1099 { 317, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL
1100 { 316, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD
1101 { 315, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
1102 { 314, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
1103 { 313, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP
1104 { 312, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP
1105 { 311, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP
1106 { 310, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET_INLINE
1107 { 309, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO
1108 { 308, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET
1109 { 307, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE
1110 { 306, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE
1111 { 305, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY
1112 { 304, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
1113 { 303, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
1114 { 302, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMPS
1115 { 301, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMP
1116 { 300, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP
1117 { 299, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT
1118 { 298, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA
1119 { 297, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM
1120 { 296, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV
1121 { 295, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL
1122 { 294, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB
1123 { 293, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD
1124 { 292, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE
1125 { 291, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE
1126 { 290, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC
1127 { 289, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE
1128 { 288, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR
1129 { 287, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST
1130 { 286, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT
1131 { 285, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT
1132 { 284, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR
1133 { 283, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT
1134 { 282, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH
1135 { 281, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH
1136 { 280, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH
1137 { 279, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2
1138 { 278, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN
1139 { 277, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN
1140 { 276, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS
1141 { 275, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN
1142 { 274, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS
1143 { 273, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN
1144 { 272, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS
1145 { 271, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL
1146 { 270, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMULR
1147 { 269, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMULH
1148 { 268, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMUL
1149 { 267, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE
1150 { 266, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP
1151 { 265, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP
1152 { 264, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS
1153 { 263, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_POISON
1154 { 262, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ
1155 { 261, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_POISON
1156 { 260, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ
1157 { 259, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS
1158 { 258, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR
1159 { 257, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR
1160 { 256, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR
1161 { 255, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
1162 { 254, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT
1163 { 253, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR
1164 { 252, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR
1165 { 251, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE
1166 { 250, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT
1167 { 249, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR
1168 { 248, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND
1169 { 247, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND
1170 { 246, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS
1171 { 245, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX
1172 { 244, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN
1173 { 243, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX
1174 { 242, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN
1175 { 241, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK
1176 { 240, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD
1177 { 239, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING
1178 { 238, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING
1179 { 237, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE
1180 { 236, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE
1181 { 235, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE
1182 { 234, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV
1183 { 233, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV
1184 { 232, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV
1185 { 231, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM
1186 { 230, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM
1187 { 229, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM
1188 { 228, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM
1189 { 227, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE
1190 { 226, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE
1191 { 225, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM
1192 { 224, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM
1193 { 223, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE
1194 { 222, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS
1195 { 221, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN
1196 { 220, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS
1197 { 219, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT
1198 { 218, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT
1199 { 217, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP
1200 { 216, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP
1201 { 215, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI
1202 { 214, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI
1203 { 213, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC
1204 { 212, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT
1205 { 211, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG
1206 { 210, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP
1207 { 209, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP
1208 { 208, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10
1209 { 207, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2
1210 { 206, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG
1211 { 205, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10
1212 { 204, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2
1213 { 203, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP
1214 { 202, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI
1215 { 201, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW
1216 { 200, 3, 2, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF
1217 { 199, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM
1218 { 198, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV
1219 { 197, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD
1220 { 196, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA
1221 { 195, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL
1222 { 194, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB
1223 { 193, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD
1224 { 192, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT
1225 { 191, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT
1226 { 190, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX
1227 { 189, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX
1228 { 188, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT
1229 { 187, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT
1230 { 186, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX
1231 { 185, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX
1232 { 184, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT
1233 { 183, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT
1234 { 182, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT
1235 { 181, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT
1236 { 180, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT
1237 { 179, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT
1238 { 178, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH
1239 { 177, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH
1240 { 176, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO
1241 { 175, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO
1242 { 174, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE
1243 { 173, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO
1244 { 172, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE
1245 { 171, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO
1246 { 170, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE
1247 { 169, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO
1248 { 168, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE
1249 { 167, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO
1250 { 166, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT
1251 { 165, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP
1252 { 164, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP
1253 { 163, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP
1254 { 162, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP
1255 { 161, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL
1256 { 160, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR
1257 { 159, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR
1258 { 158, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL
1259 { 157, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR
1260 { 156, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR
1261 { 155, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL
1262 { 154, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT
1263 { 153, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG
1264 { 152, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT
1265 { 151, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG
1266 { 150, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART
1267 { 149, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT
1268 { 148, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT
1269 { 147, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U
1270 { 146, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U
1271 { 145, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S
1272 { 144, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC
1273 { 143, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT
1274 { 142, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1275 { 141, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
1276 { 140, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1277 { 139, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC
1278 { 138, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START
1279 { 137, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT
1280 { 136, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND
1281 { 135, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH
1282 { 134, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE
1283 { 133, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1284 { 132, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1285 { 131, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1286 { 130, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1287 { 129, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1288 { 128, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1289 { 127, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1290 { 126, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1291 { 125, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN
1292 { 124, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX
1293 { 123, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB
1294 { 122, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD
1295 { 121, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN
1296 { 120, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX
1297 { 119, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN
1298 { 118, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX
1299 { 117, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR
1300 { 116, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR
1301 { 115, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND
1302 { 114, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND
1303 { 113, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB
1304 { 112, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD
1305 { 111, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG
1306 { 110, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG
1307 { 109, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1308 { 108, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE
1309 { 107, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_FPTRUNCSTORE
1310 { 106, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE
1311 { 105, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1312 { 104, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD
1313 { 103, 5, 2, 0, 0, 0, 0, R600OpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD
1314 { 102, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_FPEXTLOAD
1315 { 101, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD
1316 { 100, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD
1317 { 99, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD
1318 { 98, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER
1319 { 97, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER
1320 { 96, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1321 { 95, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT
1322 { 94, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT
1323 { 93, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND
1324 { 92, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC
1325 { 91, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1326 { 90, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1327 { 89, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE
1328 { 88, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST
1329 { 87, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR
1330 { 86, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT
1331 { 85, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS
1332 { 84, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1333 { 83, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR
1334 { 82, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES
1335 { 81, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT
1336 { 80, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES
1337 { 79, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT
1338 { 78, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL
1339 { 77, 5, 1, 0, 0, 0, 0, R600OpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1340 { 76, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE
1341 { 75, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX
1342 { 74, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI
1343 { 73, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF
1344 { 72, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL
1345 { 71, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR
1346 { 70, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL
1347 { 69, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR
1348 { 68, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU
1349 { 67, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS
1350 { 66, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR
1351 { 65, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR
1352 { 64, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND
1353 { 63, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM
1354 { 62, 4, 2, 0, 0, 0, 0, R600OpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM
1355 { 61, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM
1356 { 60, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM
1357 { 59, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV
1358 { 58, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV
1359 { 57, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL
1360 { 56, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB
1361 { 55, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD
1362 { 54, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN
1363 { 53, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT
1364 { 52, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT
1365 { 51, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1366 { 50, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1367 { 49, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1368 { 48, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1369 { 47, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE
1370 { 46, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1371 { 45, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER
1372 { 44, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE
1373 { 43, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1374 { 42, 3, 0, 0, 0, 0, 0, R600OpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14701
1375 { 41, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14700
1376 { 40, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL
1377 { 39, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1378 { 38, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET
1379 { 37, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1380 { 36, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP
1381 { 35, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP
1382 { 34, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE
1383 { 33, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT
1384 { 32, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_14699
1385 { 31, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP
1386 { 30, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_14418
1387 { 29, 6, 1, 0, 0, 0, 0, R600OpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT
1388 { 28, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL
1389 { 27, 2, 0, 0, 0, 0, 0, R600OpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP
1390 { 26, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE
1391 { 25, 4, 0, 0, 0, 0, 0, R600OpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE
1392 { 24, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END
1393 { 23, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START
1394 { 22, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE
1395 { 21, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK
1396 { 20, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY
1397 { 19, 2, 1, 0, 0, 0, 0, R600OpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE
1398 { 18, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL
1399 { 17, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI
1400 { 16, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF
1401 { 15, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST
1402 { 14, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE
1403 { 13, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS
1404 { 12, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG
1405 { 11, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF
1406 { 10, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF
1407 { 9, 4, 1, 0, 0, 0, 0, R600OpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG
1408 { 8, 3, 1, 0, 0, 0, 0, R600OpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG
1409 { 7, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL
1410 { 6, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL
1411 { 5, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL
1412 { 4, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL
1413 { 3, 1, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION
1414 { 2, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR
1415 { 1, 0, 0, 0, 0, 0, 0, R600OpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM
1416 { 0, 1, 1, 0, 0, 0, 0, R600OpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI
1417 }, {
1418 /* 0 */
1419 }, {
1420 0
1421 }, {
1422 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1423 /* 1 */
1424 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1425 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1426 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1427 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1428 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1429 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1430 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1431 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1432 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1433 /* 28 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1434 /* 29 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1435 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1436 /* 34 */ { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1437 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_AddrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1438 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1439 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1440 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1441 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1442 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1443 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1444 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1445 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1446 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1447 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1448 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1449 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1450 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1451 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1452 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1453 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1454 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1455 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1456 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1457 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1458 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1459 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1460 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1461 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1462 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1463 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1464 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1465 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1466 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1467 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1468 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1469 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1470 /* 151 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1471 /* 153 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1472 /* 155 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1473 /* 156 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1474 /* 158 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1475 /* 160 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1476 /* 231 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1477 /* 233 */ { R600::R600_Predicate_BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1478 /* 237 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1479 /* 240 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1480 /* 243 */ { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg64VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1481 /* 247 */ { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128VerticalRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1482 /* 251 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1483 /* 255 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1484 /* 262 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1485 /* 283 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1486 /* 297 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1487 /* 316 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1488 /* 325 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1489 /* 332 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1490 /* 341 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1491 /* 346 */ { R600::R600_TReg32_ZRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { R600::R600_TReg32_YRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1492 /* 351 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1493 /* 353 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1494 /* 362 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1495 /* 372 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1496 /* 379 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1497 /* 391 */ { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_Reg32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { R600::R600_PredicateRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1498 /* 404 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1499 /* 407 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1500 /* 409 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1501 /* 411 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1502 /* 413 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1503 /* 417 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1504 /* 420 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1505 /* 423 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1506 /* 426 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1507 /* 445 */ { R600::R600_Reg128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1508 /* 449 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1509 /* 453 */ { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1510 /* 457 */ { R600::R600_Reg64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { R600::R600_TReg32_XRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1511 }
1512};
1513
1514
1515#ifdef __GNUC__
1516#pragma GCC diagnostic push
1517#pragma GCC diagnostic ignored "-Woverlength-strings"
1518#endif
1519extern const char R600InstrNameData[] = {
1520 /* 0 */ "CF_TC_R600\000"
1521 /* 11 */ "CF_VC_R600\000"
1522 /* 22 */ "CF_END_R600\000"
1523 /* 34 */ "CF_ELSE_R600\000"
1524 /* 47 */ "CF_PUSH_ELSE_R600\000"
1525 /* 65 */ "CF_CONTINUE_R600\000"
1526 /* 82 */ "FNEG_R600\000"
1527 /* 92 */ "LOOP_BREAK_R600\000"
1528 /* 108 */ "CF_JUMP_R600\000"
1529 /* 121 */ "END_LOOP_R600\000"
1530 /* 135 */ "WHILE_LOOP_R600\000"
1531 /* 151 */ "POP_R600\000"
1532 /* 160 */ "FABS_R600\000"
1533 /* 170 */ "CF_CALL_FS_R600\000"
1534 /* 186 */ "DOT4_r600\000"
1535 /* 196 */ "MULADD_r600\000"
1536 /* 208 */ "LOG_CLAMPED_r600\000"
1537 /* 225 */ "RECIP_CLAMPED_r600\000"
1538 /* 244 */ "RECIPSQRT_CLAMPED_r600\000"
1539 /* 267 */ "CNDE_r600\000"
1540 /* 277 */ "MULADD_IEEE_r600\000"
1541 /* 294 */ "LOG_IEEE_r600\000"
1542 /* 308 */ "RECIP_IEEE_r600\000"
1543 /* 324 */ "EXP_IEEE_r600\000"
1544 /* 338 */ "RECIPSQRT_IEEE_r600\000"
1545 /* 358 */ "CNDGE_r600\000"
1546 /* 369 */ "LSHL_r600\000"
1547 /* 379 */ "SIN_r600\000"
1548 /* 388 */ "ASHR_r600\000"
1549 /* 398 */ "LSHR_r600\000"
1550 /* 408 */ "COS_r600\000"
1551 /* 417 */ "CNDGT_r600\000"
1552 /* 428 */ "MUL_LIT_r600\000"
1553 /* 441 */ "UINT_TO_FLT_r600\000"
1554 /* 458 */ "MULHI_UINT_r600\000"
1555 /* 474 */ "MULLO_UINT_r600\000"
1556 /* 490 */ "FLT_TO_UINT_r600\000"
1557 /* 507 */ "RECIP_UINT_r600\000"
1558 /* 523 */ "MULHI_INT_r600\000"
1559 /* 538 */ "MULLO_INT_r600\000"
1560 /* 553 */ "FLT_TO_INT_r600\000"
1561 /* 569 */ "SIN_r700\000"
1562 /* 578 */ "COS_r700\000"
1563 /* 587 */ "G_FLOG10\000"
1564 /* 596 */ "G_FEXP10\000"
1565 /* 605 */ "SETGE_DX10\000"
1566 /* 616 */ "SETNE_DX10\000"
1567 /* 627 */ "SETE_DX10\000"
1568 /* 637 */ "MIN_DX10\000"
1569 /* 646 */ "SETGT_DX10\000"
1570 /* 657 */ "MAX_DX10\000"
1571 /* 666 */ "INTERP_LOAD_P0\000"
1572 /* 681 */ "RAT_STORE_DWORD32\000"
1573 /* 699 */ "MOV_IMM_F32\000"
1574 /* 711 */ "MOV_IMM_I32\000"
1575 /* 723 */ "FLT16_TO_FLT32\000"
1576 /* 738 */ "CONTINUEC_f32\000"
1577 /* 752 */ "IFC_f32\000"
1578 /* 760 */ "BREAKC_f32\000"
1579 /* 771 */ "BRANCH_COND_f32\000"
1580 /* 787 */ "CONTINUE_LOGICALZ_f32\000"
1581 /* 809 */ "IF_LOGICALZ_f32\000"
1582 /* 825 */ "BREAK_LOGICALZ_f32\000"
1583 /* 844 */ "CONTINUE_LOGICALNZ_f32\000"
1584 /* 867 */ "IF_LOGICALNZ_f32\000"
1585 /* 884 */ "BREAK_LOGICALNZ_f32\000"
1586 /* 904 */ "CONTINUEC_i32\000"
1587 /* 918 */ "IFC_i32\000"
1588 /* 926 */ "BREAKC_i32\000"
1589 /* 937 */ "BRANCH_COND_i32\000"
1590 /* 953 */ "CONTINUE_LOGICALZ_i32\000"
1591 /* 975 */ "IF_LOGICALZ_i32\000"
1592 /* 991 */ "BREAK_LOGICALZ_i32\000"
1593 /* 1010 */ "CONTINUE_LOGICALNZ_i32\000"
1594 /* 1033 */ "IF_LOGICALNZ_i32\000"
1595 /* 1050 */ "BREAK_LOGICALNZ_i32\000"
1596 /* 1070 */ "G_FLOG2\000"
1597 /* 1078 */ "G_FATAN2\000"
1598 /* 1087 */ "G_FEXP2\000"
1599 /* 1095 */ "R600_EXTRACT_ELT_V2\000"
1600 /* 1115 */ "R600_INSERT_ELT_V2\000"
1601 /* 1134 */ "MULHI_UINT_cm24\000"
1602 /* 1150 */ "MULHI_INT_cm24\000"
1603 /* 1165 */ "RAT_STORE_DWORD64\000"
1604 /* 1183 */ "R600_EXTRACT_ELT_V4\000"
1605 /* 1203 */ "R600_INSERT_ELT_V4\000"
1606 /* 1222 */ "DOT_4\000"
1607 /* 1228 */ "FLT32_TO_FLT16\000"
1608 /* 1243 */ "RAT_STORE_DWORD128\000"
1609 /* 1262 */ "G_FMA\000"
1610 /* 1268 */ "G_STRICT_FMA\000"
1611 /* 1281 */ "TEX_SAMPLE_C_LB\000"
1612 /* 1297 */ "TEX_SAMPLE_LB\000"
1613 /* 1311 */ "G_FSUB\000"
1614 /* 1318 */ "G_STRICT_FSUB\000"
1615 /* 1332 */ "G_ATOMICRMW_FSUB\000"
1616 /* 1349 */ "G_SUB\000"
1617 /* 1355 */ "LDS_SUB\000"
1618 /* 1363 */ "G_ATOMICRMW_SUB\000"
1619 /* 1379 */ "G_INTRINSIC\000"
1620 /* 1391 */ "ENDFUNC\000"
1621 /* 1399 */ "G_FPTRUNC\000"
1622 /* 1409 */ "G_INTRINSIC_TRUNC\000"
1623 /* 1427 */ "G_TRUNC\000"
1624 /* 1435 */ "G_BUILD_VECTOR_TRUNC\000"
1625 /* 1456 */ "G_DYN_STACKALLOC\000"
1626 /* 1473 */ "TEX_SAMPLE_C\000"
1627 /* 1486 */ "G_FMAD\000"
1628 /* 1493 */ "G_FPEXTLOAD\000"
1629 /* 1505 */ "G_INDEXED_SEXTLOAD\000"
1630 /* 1524 */ "G_SEXTLOAD\000"
1631 /* 1535 */ "G_INDEXED_ZEXTLOAD\000"
1632 /* 1554 */ "G_ZEXTLOAD\000"
1633 /* 1565 */ "INTERP_VEC_LOAD\000"
1634 /* 1581 */ "G_INDEXED_LOAD\000"
1635 /* 1596 */ "G_LOAD\000"
1636 /* 1603 */ "PAD\000"
1637 /* 1607 */ "G_VECREDUCE_FADD\000"
1638 /* 1624 */ "G_FADD\000"
1639 /* 1631 */ "G_VECREDUCE_SEQ_FADD\000"
1640 /* 1652 */ "G_STRICT_FADD\000"
1641 /* 1666 */ "G_ATOMICRMW_FADD\000"
1642 /* 1683 */ "G_VECREDUCE_ADD\000"
1643 /* 1699 */ "G_ADD\000"
1644 /* 1705 */ "G_PTR_ADD\000"
1645 /* 1715 */ "LDS_ADD\000"
1646 /* 1723 */ "G_ATOMICRMW_ADD\000"
1647 /* 1739 */ "TEX_LD\000"
1648 /* 1746 */ "G_ATOMICRMW_NAND\000"
1649 /* 1763 */ "G_VECREDUCE_AND\000"
1650 /* 1779 */ "G_AND\000"
1651 /* 1785 */ "LDS_AND\000"
1652 /* 1793 */ "G_ATOMICRMW_AND\000"
1653 /* 1809 */ "LIFETIME_END\000"
1654 /* 1822 */ "G_BRCOND\000"
1655 /* 1831 */ "G_ATOMICRMW_USUB_COND\000"
1656 /* 1853 */ "JUMP_COND\000"
1657 /* 1863 */ "G_LLROUND\000"
1658 /* 1873 */ "G_LROUND\000"
1659 /* 1882 */ "G_INTRINSIC_ROUND\000"
1660 /* 1900 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1661 /* 1926 */ "LOAD_STACK_GUARD\000"
1662 /* 1943 */ "TXD\000"
1663 /* 1947 */ "PSEUDO_PROBE\000"
1664 /* 1960 */ "G_SSUBE\000"
1665 /* 1968 */ "G_USUBE\000"
1666 /* 1976 */ "G_FENCE\000"
1667 /* 1984 */ "ARITH_FENCE\000"
1668 /* 1996 */ "REG_SEQUENCE\000"
1669 /* 2009 */ "G_SADDE\000"
1670 /* 2017 */ "G_UADDE\000"
1671 /* 2025 */ "G_GET_FPMODE\000"
1672 /* 2038 */ "G_RESET_FPMODE\000"
1673 /* 2053 */ "G_SET_FPMODE\000"
1674 /* 2066 */ "MUL_IEEE\000"
1675 /* 2075 */ "G_FMINNUM_IEEE\000"
1676 /* 2090 */ "G_FMAXNUM_IEEE\000"
1677 /* 2105 */ "SGE\000"
1678 /* 2109 */ "PRED_SETGE\000"
1679 /* 2120 */ "G_VSCALE\000"
1680 /* 2129 */ "G_JUMP_TABLE\000"
1681 /* 2142 */ "BUNDLE\000"
1682 /* 2149 */ "TEX_SAMPLE\000"
1683 /* 2160 */ "RNDNE\000"
1684 /* 2166 */ "G_MEMSET_INLINE\000"
1685 /* 2182 */ "G_MEMCPY_INLINE\000"
1686 /* 2198 */ "RELOC_NONE\000"
1687 /* 2209 */ "SNE\000"
1688 /* 2213 */ "PRED_SETNE\000"
1689 /* 2224 */ "LOCAL_ESCAPE\000"
1690 /* 2237 */ "CF_ALU_PUSH_BEFORE\000"
1691 /* 2256 */ "G_FPTRUNCSTORE\000"
1692 /* 2271 */ "G_STACKRESTORE\000"
1693 /* 2286 */ "G_INDEXED_STORE\000"
1694 /* 2302 */ "G_STORE\000"
1695 /* 2310 */ "ELSE\000"
1696 /* 2315 */ "G_BITREVERSE\000"
1697 /* 2328 */ "FETCH_CLAUSE\000"
1698 /* 2341 */ "ALU_CLAUSE\000"
1699 /* 2352 */ "FAKE_USE\000"
1700 /* 2361 */ "PRED_SETE\000"
1701 /* 2371 */ "LDS_BYTE_WRITE\000"
1702 /* 2386 */ "MASK_WRITE\000"
1703 /* 2397 */ "LDS_WRITE\000"
1704 /* 2407 */ "LDS_SHORT_WRITE\000"
1705 /* 2423 */ "DBG_VALUE\000"
1706 /* 2433 */ "G_GLOBAL_VALUE\000"
1707 /* 2448 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1708 /* 2471 */ "CONVERGENCECTRL_GLUE\000"
1709 /* 2492 */ "CF_ALU_CONTINUE\000"
1710 /* 2508 */ "G_STACKSAVE\000"
1711 /* 2520 */ "G_MEMMOVE\000"
1712 /* 2530 */ "G_FREEZE\000"
1713 /* 2539 */ "G_FCANONICALIZE\000"
1714 /* 2555 */ "G_FMODF\000"
1715 /* 2563 */ "INIT_UNDEF\000"
1716 /* 2574 */ "G_IMPLICIT_DEF\000"
1717 /* 2589 */ "DBG_INSTR_REF\000"
1718 /* 2603 */ "ENDIF\000"
1719 /* 2609 */ "TEX_VTX_CONSTBUF\000"
1720 /* 2626 */ "TEX_VTX_TEXBUF\000"
1721 /* 2641 */ "G_FNEG\000"
1722 /* 2648 */ "EXTRACT_SUBREG\000"
1723 /* 2663 */ "INSERT_SUBREG\000"
1724 /* 2677 */ "G_SEXT_INREG\000"
1725 /* 2690 */ "SUBREG_TO_REG\000"
1726 /* 2704 */ "CF_TC_EG\000"
1727 /* 2713 */ "CF_VC_EG\000"
1728 /* 2722 */ "CF_END_EG\000"
1729 /* 2732 */ "CF_ELSE_EG\000"
1730 /* 2743 */ "CF_CONTINUE_EG\000"
1731 /* 2758 */ "CF_PUSH_EG\000"
1732 /* 2769 */ "LOOP_BREAK_EG\000"
1733 /* 2783 */ "CF_JUMP_EG\000"
1734 /* 2794 */ "END_LOOP_EG\000"
1735 /* 2806 */ "WHILE_LOOP_EG\000"
1736 /* 2820 */ "POP_EG\000"
1737 /* 2827 */ "CF_CALL_FS_EG\000"
1738 /* 2841 */ "G_ATOMIC_CMPXCHG\000"
1739 /* 2858 */ "LDS_WRXCHG\000"
1740 /* 2869 */ "G_ATOMICRMW_XCHG\000"
1741 /* 2886 */ "G_GET_ROUNDING\000"
1742 /* 2901 */ "G_SET_ROUNDING\000"
1743 /* 2916 */ "G_FLOG\000"
1744 /* 2923 */ "G_VAARG\000"
1745 /* 2931 */ "PREALLOCATED_ARG\000"
1746 /* 2948 */ "TEX_SAMPLE_C_G\000"
1747 /* 2963 */ "TEX_SAMPLE_G\000"
1748 /* 2976 */ "BRANCH\000"
1749 /* 2983 */ "G_PREFETCH\000"
1750 /* 2994 */ "ENDSWITCH\000"
1751 /* 3004 */ "G_CLMULH\000"
1752 /* 3013 */ "G_SMULH\000"
1753 /* 3021 */ "G_UMULH\000"
1754 /* 3029 */ "G_FTANH\000"
1755 /* 3037 */ "G_FSINH\000"
1756 /* 3045 */ "G_FCOSH\000"
1757 /* 3053 */ "TEX_GET_GRADIENTS_H\000"
1758 /* 3073 */ "TEX_SET_GRADIENTS_H\000"
1759 /* 3093 */ "DBG_PHI\000"
1760 /* 3101 */ "G_FPTOSI\000"
1761 /* 3110 */ "G_FPTOUI\000"
1762 /* 3119 */ "G_FPOWI\000"
1763 /* 3127 */ "CF_ALU_BREAK\000"
1764 /* 3140 */ "COPY_LANEMASK\000"
1765 /* 3154 */ "G_PTRMASK\000"
1766 /* 3164 */ "GC_LABEL\000"
1767 /* 3173 */ "DBG_LABEL\000"
1768 /* 3183 */ "EH_LABEL\000"
1769 /* 3192 */ "ANNOTATION_LABEL\000"
1770 /* 3209 */ "ICALL_BRANCH_FUNNEL\000"
1771 /* 3229 */ "G_FSHL\000"
1772 /* 3236 */ "G_SHL\000"
1773 /* 3242 */ "G_FCEIL\000"
1774 /* 3250 */ "G_SAVGCEIL\000"
1775 /* 3261 */ "G_UAVGCEIL\000"
1776 /* 3272 */ "PATCHABLE_TAIL_CALL\000"
1777 /* 3292 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1778 /* 3319 */ "PATCHABLE_EVENT_CALL\000"
1779 /* 3340 */ "FENTRY_CALL\000"
1780 /* 3352 */ "KILL\000"
1781 /* 3357 */ "G_CONSTANT_POOL\000"
1782 /* 3373 */ "G_ROTL\000"
1783 /* 3380 */ "G_VECREDUCE_FMUL\000"
1784 /* 3397 */ "G_FMUL\000"
1785 /* 3404 */ "G_VECREDUCE_SEQ_FMUL\000"
1786 /* 3425 */ "G_STRICT_FMUL\000"
1787 /* 3439 */ "G_CLMUL\000"
1788 /* 3447 */ "G_VECREDUCE_MUL\000"
1789 /* 3463 */ "G_MUL\000"
1790 /* 3469 */ "TEX_SAMPLE_C_L\000"
1791 /* 3484 */ "TEX_SAMPLE_L\000"
1792 /* 3497 */ "CF_END_CM\000"
1793 /* 3507 */ "G_FREM\000"
1794 /* 3514 */ "G_STRICT_FREM\000"
1795 /* 3528 */ "G_SREM\000"
1796 /* 3535 */ "G_UREM\000"
1797 /* 3542 */ "G_SDIVREM\000"
1798 /* 3552 */ "G_UDIVREM\000"
1799 /* 3562 */ "INLINEASM\000"
1800 /* 3572 */ "G_VECREDUCE_FMINIMUM\000"
1801 /* 3593 */ "G_FMINIMUM\000"
1802 /* 3604 */ "G_ATOMICRMW_FMINIMUM\000"
1803 /* 3625 */ "G_VECREDUCE_FMAXIMUM\000"
1804 /* 3646 */ "G_FMAXIMUM\000"
1805 /* 3657 */ "G_ATOMICRMW_FMAXIMUM\000"
1806 /* 3678 */ "G_VECREDUCE_FMINIMUMNUM\000"
1807 /* 3702 */ "G_FMINIMUMNUM\000"
1808 /* 3716 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1809 /* 3740 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1810 /* 3764 */ "G_FMAXIMUMNUM\000"
1811 /* 3778 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1812 /* 3802 */ "G_FMINNUM\000"
1813 /* 3812 */ "G_FMAXNUM\000"
1814 /* 3822 */ "G_FATAN\000"
1815 /* 3830 */ "G_FTAN\000"
1816 /* 3837 */ "G_INTRINSIC_ROUNDEVEN\000"
1817 /* 3859 */ "G_ASSERT_ALIGN\000"
1818 /* 3874 */ "G_FCOPYSIGN\000"
1819 /* 3886 */ "DUMMY_CHAIN\000"
1820 /* 3898 */ "ENDMAIN\000"
1821 /* 3906 */ "G_VECREDUCE_FMIN\000"
1822 /* 3923 */ "G_ATOMICRMW_FMIN\000"
1823 /* 3940 */ "G_VECREDUCE_SMIN\000"
1824 /* 3957 */ "G_SMIN\000"
1825 /* 3964 */ "G_VECREDUCE_UMIN\000"
1826 /* 3981 */ "G_UMIN\000"
1827 /* 3988 */ "G_ATOMICRMW_UMIN\000"
1828 /* 4005 */ "G_ATOMICRMW_MIN\000"
1829 /* 4021 */ "G_FASIN\000"
1830 /* 4029 */ "G_FSIN\000"
1831 /* 4036 */ "CFI_INSTRUCTION\000"
1832 /* 4052 */ "G_CTLZ_ZERO_POISON\000"
1833 /* 4071 */ "G_CTTZ_ZERO_POISON\000"
1834 /* 4090 */ "RETURN\000"
1835 /* 4097 */ "RAT_ATOMIC_RSUB_RTN\000"
1836 /* 4117 */ "RAT_ATOMIC_SUB_RTN\000"
1837 /* 4136 */ "RAT_ATOMIC_ADD_RTN\000"
1838 /* 4155 */ "RAT_ATOMIC_AND_RTN\000"
1839 /* 4174 */ "RAT_ATOMIC_XOR_RTN\000"
1840 /* 4193 */ "RAT_ATOMIC_OR_RTN\000"
1841 /* 4211 */ "RAT_ATOMIC_DEC_UINT_RTN\000"
1842 /* 4235 */ "RAT_ATOMIC_INC_UINT_RTN\000"
1843 /* 4259 */ "RAT_ATOMIC_MIN_UINT_RTN\000"
1844 /* 4283 */ "RAT_ATOMIC_MAX_UINT_RTN\000"
1845 /* 4307 */ "RAT_ATOMIC_CMPXCHG_INT_RTN\000"
1846 /* 4334 */ "RAT_ATOMIC_XCHG_INT_RTN\000"
1847 /* 4358 */ "RAT_ATOMIC_MIN_INT_RTN\000"
1848 /* 4381 */ "RAT_ATOMIC_MAX_INT_RTN\000"
1849 /* 4404 */ "RETDYN\000"
1850 /* 4411 */ "G_SSUBO\000"
1851 /* 4419 */ "G_USUBO\000"
1852 /* 4427 */ "G_SADDO\000"
1853 /* 4435 */ "G_UADDO\000"
1854 /* 4443 */ "TEX_GET_TEXTURE_RESINFO\000"
1855 /* 4467 */ "JUMP_TABLE_DEBUG_INFO\000"
1856 /* 4489 */ "G_SMULO\000"
1857 /* 4497 */ "G_UMULO\000"
1858 /* 4505 */ "G_BZERO\000"
1859 /* 4513 */ "STACKMAP\000"
1860 /* 4522 */ "G_DEBUGTRAP\000"
1861 /* 4534 */ "G_UBSANTRAP\000"
1862 /* 4546 */ "G_TRAP\000"
1863 /* 4553 */ "G_ATOMICRMW_UDEC_WRAP\000"
1864 /* 4575 */ "G_ATOMICRMW_UINC_WRAP\000"
1865 /* 4597 */ "G_BSWAP\000"
1866 /* 4605 */ "G_SITOFP\000"
1867 /* 4614 */ "G_UITOFP\000"
1868 /* 4623 */ "G_FCMP\000"
1869 /* 4630 */ "G_STRICT_FCMP\000"
1870 /* 4644 */ "G_ICMP\000"
1871 /* 4651 */ "G_SCMP\000"
1872 /* 4658 */ "G_UCMP\000"
1873 /* 4665 */ "JUMP\000"
1874 /* 4670 */ "ENDLOOP\000"
1875 /* 4678 */ "WHILELOOP\000"
1876 /* 4688 */ "CONVERGENCECTRL_LOOP\000"
1877 /* 4709 */ "G_CTPOP\000"
1878 /* 4717 */ "PATCHABLE_OP\000"
1879 /* 4730 */ "FAULTING_OP\000"
1880 /* 4742 */ "PREALLOCATED_SETUP\000"
1881 /* 4761 */ "G_FLDEXP\000"
1882 /* 4770 */ "G_STRICT_FLDEXP\000"
1883 /* 4786 */ "G_FEXP\000"
1884 /* 4793 */ "G_FFREXP\000"
1885 /* 4802 */ "G_BR\000"
1886 /* 4807 */ "INLINEASM_BR\000"
1887 /* 4820 */ "G_BLOCK_ADDR\000"
1888 /* 4833 */ "MOV_IMM_GLOBAL_ADDR\000"
1889 /* 4853 */ "MEMBARRIER\000"
1890 /* 4864 */ "G_CONSTANT_FOLD_BARRIER\000"
1891 /* 4888 */ "GROUP_BARRIER\000"
1892 /* 4902 */ "CF_ALU_ELSE_AFTER\000"
1893 /* 4920 */ "CF_ALU_POP_AFTER\000"
1894 /* 4937 */ "PATCHABLE_FUNCTION_ENTER\000"
1895 /* 4962 */ "G_READCYCLECOUNTER\000"
1896 /* 4981 */ "G_READSTEADYCOUNTER\000"
1897 /* 5001 */ "G_READ_REGISTER\000"
1898 /* 5017 */ "G_WRITE_REGISTER\000"
1899 /* 5034 */ "G_ASHR\000"
1900 /* 5041 */ "G_FSHR\000"
1901 /* 5048 */ "G_LSHR\000"
1902 /* 5055 */ "G_CLMULR\000"
1903 /* 5064 */ "CONVERGENCECTRL_ANCHOR\000"
1904 /* 5087 */ "RAT_MSKOR\000"
1905 /* 5097 */ "G_FFLOOR\000"
1906 /* 5106 */ "G_SAVGFLOOR\000"
1907 /* 5118 */ "G_UAVGFLOOR\000"
1908 /* 5130 */ "G_EXTRACT_SUBVECTOR\000"
1909 /* 5150 */ "G_INSERT_SUBVECTOR\000"
1910 /* 5169 */ "G_BUILD_VECTOR\000"
1911 /* 5184 */ "G_SHUFFLE_VECTOR\000"
1912 /* 5201 */ "G_STEP_VECTOR\000"
1913 /* 5215 */ "G_SPLAT_VECTOR\000"
1914 /* 5230 */ "G_VECREDUCE_XOR\000"
1915 /* 5246 */ "G_XOR\000"
1916 /* 5252 */ "LDS_XOR\000"
1917 /* 5260 */ "G_ATOMICRMW_XOR\000"
1918 /* 5276 */ "G_VECREDUCE_OR\000"
1919 /* 5291 */ "G_OR\000"
1920 /* 5296 */ "LDS_OR\000"
1921 /* 5303 */ "G_ATOMICRMW_OR\000"
1922 /* 5318 */ "G_ROTR\000"
1923 /* 5325 */ "TEX_LDPTR\000"
1924 /* 5335 */ "G_INTTOPTR\000"
1925 /* 5346 */ "G_FABS\000"
1926 /* 5353 */ "G_ABS\000"
1927 /* 5359 */ "G_ABDS\000"
1928 /* 5366 */ "G_UNMERGE_VALUES\000"
1929 /* 5383 */ "G_MERGE_VALUES\000"
1930 /* 5398 */ "LITERALS\000"
1931 /* 5407 */ "G_CTLS\000"
1932 /* 5414 */ "G_FACOS\000"
1933 /* 5422 */ "G_FCOS\000"
1934 /* 5429 */ "G_FSINCOS\000"
1935 /* 5439 */ "G_STRICT_FCMPS\000"
1936 /* 5454 */ "G_CONCAT_VECTORS\000"
1937 /* 5471 */ "COPY_TO_REGCLASS\000"
1938 /* 5488 */ "G_IS_FPCLASS\000"
1939 /* 5501 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1940 /* 5531 */ "G_VECTOR_COMPRESS\000"
1941 /* 5549 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1942 /* 5576 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1943 /* 5614 */ "G_TRUNC_SSAT_S\000"
1944 /* 5629 */ "G_SSUBSAT\000"
1945 /* 5639 */ "G_USUBSAT\000"
1946 /* 5649 */ "G_SADDSAT\000"
1947 /* 5659 */ "G_UADDSAT\000"
1948 /* 5669 */ "G_SSHLSAT\000"
1949 /* 5679 */ "G_USHLSAT\000"
1950 /* 5689 */ "G_SMULFIXSAT\000"
1951 /* 5702 */ "G_UMULFIXSAT\000"
1952 /* 5715 */ "G_SDIVFIXSAT\000"
1953 /* 5728 */ "G_UDIVFIXSAT\000"
1954 /* 5741 */ "G_ATOMICRMW_USUB_SAT\000"
1955 /* 5762 */ "G_FPTOSI_SAT\000"
1956 /* 5775 */ "G_FPTOUI_SAT\000"
1957 /* 5788 */ "FRACT\000"
1958 /* 5794 */ "G_EXTRACT\000"
1959 /* 5804 */ "G_SELECT\000"
1960 /* 5813 */ "G_BRINDIRECT\000"
1961 /* 5826 */ "RAT_ATOMIC_RSUB_NORET\000"
1962 /* 5848 */ "RAT_ATOMIC_SUB_NORET\000"
1963 /* 5869 */ "RAT_ATOMIC_ADD_NORET\000"
1964 /* 5890 */ "RAT_ATOMIC_AND_NORET\000"
1965 /* 5911 */ "RAT_ATOMIC_XOR_NORET\000"
1966 /* 5932 */ "RAT_ATOMIC_OR_NORET\000"
1967 /* 5952 */ "RAT_ATOMIC_DEC_UINT_NORET\000"
1968 /* 5978 */ "RAT_ATOMIC_INC_UINT_NORET\000"
1969 /* 6004 */ "RAT_ATOMIC_MIN_UINT_NORET\000"
1970 /* 6030 */ "RAT_ATOMIC_MAX_UINT_NORET\000"
1971 /* 6056 */ "RAT_ATOMIC_CMPXCHG_INT_NORET\000"
1972 /* 6085 */ "RAT_ATOMIC_XCHG_INT_NORET\000"
1973 /* 6111 */ "RAT_ATOMIC_MIN_INT_NORET\000"
1974 /* 6136 */ "RAT_ATOMIC_MAX_INT_NORET\000"
1975 /* 6161 */ "LDS_SUB_RET\000"
1976 /* 6173 */ "LDS_UBYTE_READ_RET\000"
1977 /* 6192 */ "LDS_BYTE_READ_RET\000"
1978 /* 6210 */ "LDS_READ_RET\000"
1979 /* 6223 */ "LDS_USHORT_READ_RET\000"
1980 /* 6243 */ "LDS_SHORT_READ_RET\000"
1981 /* 6262 */ "LDS_ADD_RET\000"
1982 /* 6274 */ "LDS_AND_RET\000"
1983 /* 6286 */ "PATCHABLE_RET\000"
1984 /* 6300 */ "LDS_WRXCHG_RET\000"
1985 /* 6315 */ "LDS_XOR_RET\000"
1986 /* 6327 */ "LDS_OR_RET\000"
1987 /* 6338 */ "LDS_MIN_UINT_RET\000"
1988 /* 6355 */ "LDS_MAX_UINT_RET\000"
1989 /* 6372 */ "LDS_MIN_INT_RET\000"
1990 /* 6388 */ "LDS_MAX_INT_RET\000"
1991 /* 6404 */ "LDS_CMPST_RET\000"
1992 /* 6418 */ "G_MEMSET\000"
1993 /* 6427 */ "IF_PREDICATE_SET\000"
1994 /* 6444 */ "KILLGT\000"
1995 /* 6451 */ "SGT\000"
1996 /* 6455 */ "PRED_SETGT\000"
1997 /* 6466 */ "PATCHABLE_FUNCTION_EXIT\000"
1998 /* 6490 */ "G_BRJT\000"
1999 /* 6497 */ "G_EXTRACT_VECTOR_ELT\000"
2000 /* 6518 */ "G_INSERT_VECTOR_ELT\000"
2001 /* 6538 */ "DEFAULT\000"
2002 /* 6546 */ "G_FCONSTANT\000"
2003 /* 6558 */ "G_CONSTANT\000"
2004 /* 6569 */ "G_INTRINSIC_CONVERGENT\000"
2005 /* 6592 */ "STATEPOINT\000"
2006 /* 6603 */ "PATCHPOINT\000"
2007 /* 6614 */ "G_PTRTOINT\000"
2008 /* 6625 */ "G_FRINT\000"
2009 /* 6633 */ "G_INTRINSIC_LLRINT\000"
2010 /* 6652 */ "G_INTRINSIC_LRINT\000"
2011 /* 6670 */ "SUBB_UINT\000"
2012 /* 6680 */ "ADDC_UINT\000"
2013 /* 6690 */ "SETGE_UINT\000"
2014 /* 6701 */ "FFBH_UINT\000"
2015 /* 6711 */ "LDS_MIN_UINT\000"
2016 /* 6724 */ "SETGT_UINT\000"
2017 /* 6735 */ "LDS_MAX_UINT\000"
2018 /* 6748 */ "G_FNEARBYINT\000"
2019 /* 6761 */ "SUB_INT\000"
2020 /* 6769 */ "ADD_INT\000"
2021 /* 6777 */ "AND_INT\000"
2022 /* 6785 */ "CNDE_INT\000"
2023 /* 6794 */ "CNDGE_INT\000"
2024 /* 6804 */ "PRED_SETGE_INT\000"
2025 /* 6819 */ "PRED_SETNE_INT\000"
2026 /* 6834 */ "PRED_SETE_INT\000"
2027 /* 6848 */ "FFBL_INT\000"
2028 /* 6857 */ "LDS_MIN_INT\000"
2029 /* 6869 */ "XOR_INT\000"
2030 /* 6877 */ "CNDGT_INT\000"
2031 /* 6887 */ "PRED_SETGT_INT\000"
2032 /* 6902 */ "BCNT_INT\000"
2033 /* 6911 */ "NOT_INT\000"
2034 /* 6919 */ "LDS_MAX_INT\000"
2035 /* 6931 */ "G_VASTART\000"
2036 /* 6941 */ "LIFETIME_START\000"
2037 /* 6956 */ "G_INVOKE_REGION_START\000"
2038 /* 6978 */ "G_INSERT\000"
2039 /* 6987 */ "G_FSQRT\000"
2040 /* 6995 */ "G_STRICT_FSQRT\000"
2041 /* 7010 */ "G_BITCAST\000"
2042 /* 7020 */ "G_ADDRSPACE_CAST\000"
2043 /* 7037 */ "DBG_VALUE_LIST\000"
2044 /* 7052 */ "LDS_CMPST\000"
2045 /* 7062 */ "G_FPEXT\000"
2046 /* 7070 */ "G_SEXT\000"
2047 /* 7077 */ "G_ASSERT_SEXT\000"
2048 /* 7091 */ "G_ANYEXT\000"
2049 /* 7100 */ "G_ZEXT\000"
2050 /* 7107 */ "G_ASSERT_ZEXT\000"
2051 /* 7121 */ "G_ABDU\000"
2052 /* 7128 */ "CF_ALU\000"
2053 /* 7135 */ "G_TRUNC_SSAT_U\000"
2054 /* 7150 */ "G_TRUNC_USAT_U\000"
2055 /* 7165 */ "G_FDIV\000"
2056 /* 7172 */ "G_STRICT_FDIV\000"
2057 /* 7186 */ "G_SDIV\000"
2058 /* 7193 */ "G_UDIV\000"
2059 /* 7200 */ "G_GET_FPENV\000"
2060 /* 7212 */ "G_RESET_FPENV\000"
2061 /* 7226 */ "G_SET_FPENV\000"
2062 /* 7238 */ "MOV\000"
2063 /* 7242 */ "TEX_GET_GRADIENTS_V\000"
2064 /* 7262 */ "TEX_SET_GRADIENTS_V\000"
2065 /* 7282 */ "TXD_SHADOW\000"
2066 /* 7293 */ "G_FPOW\000"
2067 /* 7300 */ "INTERP_ZW\000"
2068 /* 7310 */ "INTERP_PAIR_ZW\000"
2069 /* 7325 */ "G_VECREDUCE_FMAX\000"
2070 /* 7342 */ "G_ATOMICRMW_FMAX\000"
2071 /* 7359 */ "G_VECREDUCE_SMAX\000"
2072 /* 7376 */ "G_SMAX\000"
2073 /* 7383 */ "G_VECREDUCE_UMAX\000"
2074 /* 7400 */ "G_UMAX\000"
2075 /* 7407 */ "G_ATOMICRMW_UMAX\000"
2076 /* 7424 */ "G_ATOMICRMW_MAX\000"
2077 /* 7440 */ "G_FRAME_INDEX\000"
2078 /* 7454 */ "G_SBFX\000"
2079 /* 7461 */ "G_UBFX\000"
2080 /* 7468 */ "G_SMULFIX\000"
2081 /* 7478 */ "G_UMULFIX\000"
2082 /* 7488 */ "G_SDIVFIX\000"
2083 /* 7498 */ "G_UDIVFIX\000"
2084 /* 7508 */ "PRED_X\000"
2085 /* 7515 */ "G_MEMCPY\000"
2086 /* 7524 */ "CONST_COPY\000"
2087 /* 7535 */ "CONVERGENCECTRL_ENTRY\000"
2088 /* 7557 */ "INTERP_XY\000"
2089 /* 7567 */ "INTERP_PAIR_XY\000"
2090 /* 7582 */ "G_CTLZ\000"
2091 /* 7589 */ "G_CTTZ\000"
2092 /* 7596 */ "R600_RegisterLoad\000"
2093 /* 7614 */ "R600_RegisterStore\000"
2094 /* 7633 */ "R600_ExportBuf\000"
2095 /* 7648 */ "EG_ExportBuf\000"
2096 /* 7661 */ "VTX_READ_32_eg\000"
2097 /* 7676 */ "RAT_WRITE_CACHELESS_32_eg\000"
2098 /* 7702 */ "MULADD_UINT24_eg\000"
2099 /* 7719 */ "MULHI_UINT24_eg\000"
2100 /* 7735 */ "MUL_UINT24_eg\000"
2101 /* 7749 */ "VTX_READ_64_eg\000"
2102 /* 7764 */ "RAT_WRITE_CACHELESS_64_eg\000"
2103 /* 7790 */ "DOT4_eg\000"
2104 /* 7798 */ "VTX_READ_16_eg\000"
2105 /* 7813 */ "VTX_READ_128_eg\000"
2106 /* 7829 */ "RAT_WRITE_CACHELESS_128_eg\000"
2107 /* 7856 */ "VTX_READ_8_eg\000"
2108 /* 7870 */ "FMA_eg\000"
2109 /* 7877 */ "MULADD_eg\000"
2110 /* 7887 */ "LOG_CLAMPED_eg\000"
2111 /* 7902 */ "RECIP_CLAMPED_eg\000"
2112 /* 7919 */ "RECIPSQRT_CLAMPED_eg\000"
2113 /* 7940 */ "RAT_STORE_TYPED_eg\000"
2114 /* 7959 */ "CNDE_eg\000"
2115 /* 7967 */ "MULADD_IEEE_eg\000"
2116 /* 7982 */ "LOG_IEEE_eg\000"
2117 /* 7994 */ "RECIP_IEEE_eg\000"
2118 /* 8008 */ "EXP_IEEE_eg\000"
2119 /* 8020 */ "RECIPSQRT_IEEE_eg\000"
2120 /* 8038 */ "CNDGE_eg\000"
2121 /* 8047 */ "LSHL_eg\000"
2122 /* 8055 */ "SIN_eg\000"
2123 /* 8062 */ "ASHR_eg\000"
2124 /* 8070 */ "LSHR_eg\000"
2125 /* 8078 */ "COS_eg\000"
2126 /* 8085 */ "CNDGT_eg\000"
2127 /* 8094 */ "MUL_LIT_eg\000"
2128 /* 8105 */ "UINT_TO_FLT_eg\000"
2129 /* 8120 */ "BFE_UINT_eg\000"
2130 /* 8132 */ "MULHI_UINT_eg\000"
2131 /* 8146 */ "MULLO_UINT_eg\000"
2132 /* 8160 */ "FLT_TO_UINT_eg\000"
2133 /* 8175 */ "RECIP_UINT_eg\000"
2134 /* 8189 */ "MOVA_INT_eg\000"
2135 /* 8201 */ "BFE_INT_eg\000"
2136 /* 8212 */ "BFI_INT_eg\000"
2137 /* 8223 */ "MULHI_INT_eg\000"
2138 /* 8236 */ "BFM_INT_eg\000"
2139 /* 8247 */ "BIT_ALIGN_INT_eg\000"
2140 /* 8264 */ "MULLO_INT_eg\000"
2141 /* 8277 */ "FLT_TO_INT_eg\000"
2142 /* 8291 */ "CUBE_r600_real\000"
2143 /* 8306 */ "CUBE_eg_real\000"
2144 /* 8319 */ "VTX_READ_32_cm\000"
2145 /* 8334 */ "MULADD_INT24_cm\000"
2146 /* 8350 */ "MUL_INT24_cm\000"
2147 /* 8363 */ "VTX_READ_64_cm\000"
2148 /* 8378 */ "VTX_READ_16_cm\000"
2149 /* 8393 */ "VTX_READ_128_cm\000"
2150 /* 8409 */ "VTX_READ_8_cm\000"
2151 /* 8423 */ "RECIP_CLAMPED_cm\000"
2152 /* 8440 */ "RECIPSQRT_CLAMPED_cm\000"
2153 /* 8461 */ "RAT_STORE_TYPED_cm\000"
2154 /* 8480 */ "LOG_IEEE_cm\000"
2155 /* 8492 */ "RECIP_IEEE_cm\000"
2156 /* 8506 */ "EXP_IEEE_cm\000"
2157 /* 8518 */ "RECIPSQRT_IEEE_cm\000"
2158 /* 8536 */ "SIN_cm\000"
2159 /* 8543 */ "COS_cm\000"
2160 /* 8550 */ "MULHI_UINT_cm\000"
2161 /* 8564 */ "MULLO_UINT_cm\000"
2162 /* 8578 */ "MULHI_INT_cm\000"
2163 /* 8591 */ "MULLO_INT_cm\000"
2164 /* 8604 */ "CUBE_r600_pseudo\000"
2165 /* 8621 */ "CUBE_eg_pseudo\000"
2166 /* 8636 */ "R600_ExportSwz\000"
2167 /* 8651 */ "EG_ExportSwz\000"
2168};
2169#ifdef __GNUC__
2170#pragma GCC diagnostic pop
2171#endif
2172
2173extern const unsigned R600InstrNameIndices[] = {
2174 3097U, 3562U, 4807U, 4036U, 3183U, 3164U, 3192U, 3352U,
2175 2648U, 2663U, 2576U, 2563U, 2690U, 5471U, 2423U, 7037U,
2176 2589U, 3093U, 3173U, 1996U, 7530U, 3140U, 2142U, 6941U,
2177 1809U, 1947U, 1984U, 4513U, 3340U, 6603U, 1926U, 4742U,
2178 2931U, 6592U, 2224U, 4730U, 4717U, 4937U, 6286U, 6466U,
2179 3272U, 3319U, 3292U, 3209U, 2352U, 4853U, 4467U, 2198U,
2180 7535U, 5064U, 4688U, 2471U, 7077U, 7107U, 3859U, 1699U,
2181 1349U, 3463U, 7186U, 7193U, 3528U, 3535U, 3542U, 3552U,
2182 1779U, 5291U, 5246U, 5359U, 7121U, 5118U, 3261U, 5106U,
2183 3250U, 2574U, 3095U, 7440U, 2433U, 2448U, 3357U, 5794U,
2184 5366U, 6978U, 5383U, 5169U, 1435U, 5454U, 6614U, 5335U,
2185 7010U, 2530U, 4864U, 1900U, 1409U, 1882U, 6652U, 6633U,
2186 3837U, 4962U, 4981U, 1596U, 1524U, 1554U, 1493U, 1581U,
2187 1505U, 1535U, 2302U, 2256U, 2286U, 5501U, 2841U, 2869U,
2188 1723U, 1363U, 1793U, 1746U, 5303U, 5260U, 7424U, 4005U,
2189 7407U, 3988U, 1666U, 1332U, 7342U, 3923U, 3657U, 3604U,
2190 3778U, 3716U, 4575U, 4553U, 1831U, 5741U, 1976U, 2983U,
2191 1822U, 5813U, 6956U, 1379U, 5549U, 6569U, 5576U, 7091U,
2192 1427U, 5614U, 7135U, 7150U, 6558U, 6546U, 6931U, 2923U,
2193 7070U, 2677U, 7100U, 3236U, 5048U, 5034U, 3229U, 5041U,
2194 5318U, 3373U, 4644U, 4623U, 4651U, 4658U, 5804U, 4435U,
2195 2017U, 4419U, 1968U, 4427U, 2009U, 4411U, 1960U, 4497U,
2196 4489U, 3021U, 3013U, 5659U, 5649U, 5639U, 5629U, 5679U,
2197 5669U, 7468U, 7478U, 5689U, 5702U, 7488U, 7498U, 5715U,
2198 5728U, 1624U, 1311U, 3397U, 1262U, 1486U, 7165U, 3507U,
2199 2555U, 7293U, 3119U, 4786U, 1087U, 596U, 2916U, 1070U,
2200 587U, 4761U, 4793U, 2641U, 7062U, 1399U, 3101U, 3110U,
2201 4605U, 4614U, 5762U, 5775U, 5346U, 3874U, 5488U, 2539U,
2202 3802U, 3812U, 2075U, 2090U, 3593U, 3646U, 3702U, 3764U,
2203 7200U, 7226U, 7212U, 2025U, 2053U, 2038U, 2886U, 2901U,
2204 1705U, 3154U, 3957U, 7376U, 3981U, 7400U, 5353U, 1873U,
2205 1863U, 4802U, 6490U, 2120U, 5150U, 5130U, 6518U, 6497U,
2206 5184U, 5215U, 5201U, 5531U, 7589U, 4071U, 7582U, 4052U,
2207 5407U, 4709U, 4597U, 2315U, 3439U, 3004U, 5055U, 3242U,
2208 5422U, 4029U, 5429U, 3830U, 5414U, 4021U, 3822U, 1078U,
2209 3045U, 3037U, 3029U, 6987U, 5097U, 6625U, 6748U, 7020U,
2210 4820U, 2129U, 1456U, 2508U, 2271U, 1652U, 1318U, 3425U,
2211 7172U, 3514U, 1268U, 6995U, 4770U, 4630U, 5439U, 5001U,
2212 5017U, 7515U, 2182U, 2520U, 6418U, 4505U, 2166U, 4546U,
2213 4522U, 4534U, 1631U, 3404U, 1607U, 3380U, 7325U, 3906U,
2214 3625U, 3572U, 3740U, 3678U, 1683U, 3447U, 1763U, 5276U,
2215 5230U, 7359U, 3940U, 7383U, 3964U, 7454U, 7461U, 2976U,
2216 771U, 937U, 3134U, 760U, 926U, 884U, 1050U, 825U,
2217 991U, 7524U, 2499U, 738U, 904U, 844U, 1010U, 787U,
2218 953U, 8621U, 8604U, 6538U, 1222U, 3886U, 2310U, 1818U,
2219 1391U, 2603U, 4670U, 3898U, 2994U, 160U, 82U, 1394U,
2220 752U, 918U, 867U, 1033U, 809U, 975U, 6427U, 4665U,
2221 1853U, 2386U, 699U, 4833U, 711U, 7508U, 1095U, 1183U,
2222 1115U, 1203U, 7596U, 7614U, 4404U, 4090U, 1943U, 7282U,
2223 4678U, 1620U, 6680U, 6769U, 2341U, 6777U, 8062U, 388U,
2224 6902U, 8201U, 8120U, 8212U, 8236U, 8247U, 3245U, 7128U,
2225 3127U, 2492U, 4902U, 4920U, 2237U, 2827U, 170U, 2743U,
2226 65U, 2732U, 34U, 3497U, 2722U, 22U, 2783U, 108U,
2227 2758U, 47U, 2704U, 0U, 2713U, 11U, 6785U, 7959U,
2228 267U, 6794U, 8038U, 358U, 6877U, 8085U, 417U, 8543U,
2229 8078U, 408U, 578U, 8306U, 8291U, 7790U, 186U, 7648U,
2230 8651U, 2794U, 121U, 8506U, 8008U, 324U, 2328U, 6701U,
2231 6848U, 5100U, 723U, 1228U, 8277U, 553U, 8160U, 490U,
2232 7870U, 5788U, 4888U, 666U, 7567U, 7310U, 1565U, 7557U,
2233 7300U, 8106U, 442U, 6444U, 1715U, 6262U, 1785U, 6274U,
2234 6192U, 2371U, 7052U, 6404U, 6919U, 6388U, 6735U, 6355U,
2235 6857U, 6372U, 6711U, 6338U, 5296U, 6327U, 6210U, 6243U,
2236 2407U, 1355U, 6161U, 6173U, 6223U, 2397U, 2858U, 6300U,
2237 5252U, 6315U, 5398U, 7887U, 208U, 8480U, 7982U, 294U,
2238 2769U, 92U, 8047U, 369U, 8070U, 398U, 7338U, 657U,
2239 6923U, 6739U, 3919U, 637U, 6861U, 6715U, 7238U, 8189U,
2240 3393U, 7967U, 277U, 8334U, 7702U, 7877U, 196U, 8578U,
2241 1150U, 8223U, 523U, 7719U, 8550U, 1134U, 8132U, 458U,
2242 8591U, 8264U, 538U, 8564U, 8146U, 474U, 2066U, 8350U,
2243 8094U, 428U, 7735U, 6911U, 6870U, 1603U, 2820U, 151U,
2244 2361U, 6834U, 2109U, 6804U, 6455U, 6887U, 2213U, 6819U,
2245 7633U, 8636U, 5869U, 4136U, 5890U, 4155U, 6056U, 4307U,
2246 5952U, 4211U, 5978U, 4235U, 6136U, 4381U, 6030U, 4283U,
2247 6111U, 4358U, 6004U, 4259U, 5932U, 4193U, 5826U, 4097U,
2248 5848U, 4117U, 6085U, 4334U, 5911U, 4174U, 5087U, 1243U,
2249 681U, 1165U, 8461U, 7940U, 7829U, 7676U, 7764U, 8440U,
2250 7919U, 244U, 8518U, 8020U, 338U, 8423U, 7902U, 225U,
2251 8492U, 7994U, 308U, 8175U, 507U, 2160U, 2366U, 627U,
2252 6839U, 605U, 6809U, 6690U, 646U, 6892U, 6724U, 616U,
2253 6824U, 2105U, 6451U, 8536U, 8055U, 379U, 569U, 2209U,
2254 6670U, 6761U, 3053U, 7242U, 4443U, 1739U, 5325U, 2149U,
2255 1473U, 2948U, 3469U, 1281U, 2963U, 3484U, 1297U, 3073U,
2256 7262U, 2609U, 2626U, 1403U, 8105U, 441U, 8393U, 7813U,
2257 8378U, 7798U, 8319U, 7661U, 8363U, 7749U, 8409U, 7856U,
2258 2806U, 135U, 6869U,
2259};
2260
2261static inline void InitR600MCInstrInfo(MCInstrInfo *II) {
2262 II->InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 675, nullptr, 0);
2263}
2264
2265
2266} // namespace llvm
2267
2268#endif // GET_INSTRINFO_MC_DESC
2269
2270#ifdef GET_INSTRINFO_HEADER
2271#undef GET_INSTRINFO_HEADER
2272
2273namespace llvm {
2274
2275struct R600GenInstrInfo : public TargetInstrInfo {
2276 explicit R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2277 ~R600GenInstrInfo() override = default;
2278};
2279
2280} // namespace llvm
2281
2282namespace llvm::R600 {
2283
2284constexpr unsigned SUBOP_FRAMEri_ptr = 0;
2285constexpr unsigned SUBOP_FRAMEri_index = 1;
2286constexpr unsigned SUBOP_MEMrr_ptr = 0;
2287constexpr unsigned SUBOP_MEMrr_index = 1;
2288constexpr unsigned SUBOP_MEMxi_ptr = 0;
2289constexpr unsigned SUBOP_MEMxi_index = 1;
2290
2291} // namespace llvm::R600
2292
2293#endif // GET_INSTRINFO_HEADER
2294
2295#ifdef GET_INSTRINFO_HELPER_DECLS
2296#undef GET_INSTRINFO_HELPER_DECLS
2297
2298
2299#endif // GET_INSTRINFO_HELPER_DECLS
2300
2301#ifdef GET_INSTRINFO_HELPERS
2302#undef GET_INSTRINFO_HELPERS
2303
2304
2305#endif // GET_INSTRINFO_HELPERS
2306
2307#ifdef GET_INSTRINFO_CTOR_DTOR
2308#undef GET_INSTRINFO_CTOR_DTOR
2309
2310namespace llvm {
2311
2312extern const R600InstrTable R600Descs;
2313extern const unsigned R600InstrNameIndices[];
2314extern const char R600InstrNameData[];
2315R600GenInstrInfo::R600GenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2316 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2317 InitMCInstrInfo(R600Descs.Insts, R600InstrNameIndices, R600InstrNameData, nullptr, nullptr, 675);
2318}
2319
2320} // namespace llvm
2321
2322#endif // GET_INSTRINFO_CTOR_DTOR
2323
2324#ifdef GET_INSTRINFO_OPERAND_ENUM
2325#undef GET_INSTRINFO_OPERAND_ENUM
2326
2327namespace llvm::R600 {
2328
2329enum class OpName : uint8_t {
2330 dst = 0,
2331 src0 = 1,
2332 update_exec_mask_X = 2,
2333 update_pred_X = 3,
2334 write_X = 4,
2335 omod_X = 5,
2336 dst_rel_X = 6,
2337 clamp_X = 7,
2338 src0_X = 8,
2339 src0_neg_X = 9,
2340 src0_rel_X = 10,
2341 src0_abs_X = 11,
2342 src0_sel_X = 12,
2343 src1_X = 13,
2344 src1_neg_X = 14,
2345 src1_rel_X = 15,
2346 src1_abs_X = 16,
2347 src1_sel_X = 17,
2348 pred_sel_X = 18,
2349 update_exec_mask_Y = 19,
2350 update_pred_Y = 20,
2351 write_Y = 21,
2352 omod_Y = 22,
2353 dst_rel_Y = 23,
2354 clamp_Y = 24,
2355 src0_Y = 25,
2356 src0_neg_Y = 26,
2357 src0_rel_Y = 27,
2358 src0_abs_Y = 28,
2359 src0_sel_Y = 29,
2360 src1_Y = 30,
2361 src1_neg_Y = 31,
2362 src1_rel_Y = 32,
2363 src1_abs_Y = 33,
2364 src1_sel_Y = 34,
2365 pred_sel_Y = 35,
2366 update_exec_mask_Z = 36,
2367 update_pred_Z = 37,
2368 write_Z = 38,
2369 omod_Z = 39,
2370 dst_rel_Z = 40,
2371 clamp_Z = 41,
2372 src0_Z = 42,
2373 src0_neg_Z = 43,
2374 src0_rel_Z = 44,
2375 src0_abs_Z = 45,
2376 src0_sel_Z = 46,
2377 src1_Z = 47,
2378 src1_neg_Z = 48,
2379 src1_rel_Z = 49,
2380 src1_abs_Z = 50,
2381 src1_sel_Z = 51,
2382 pred_sel_Z = 52,
2383 update_exec_mask_W = 53,
2384 update_pred_W = 54,
2385 write_W = 55,
2386 omod_W = 56,
2387 dst_rel_W = 57,
2388 clamp_W = 58,
2389 src0_W = 59,
2390 src0_neg_W = 60,
2391 src0_rel_W = 61,
2392 src0_abs_W = 62,
2393 src0_sel_W = 63,
2394 src1_W = 64,
2395 src1_neg_W = 65,
2396 src1_rel_W = 66,
2397 src1_abs_W = 67,
2398 src1_sel_W = 68,
2399 pred_sel_W = 69,
2400 literal0 = 70,
2401 literal1 = 71,
2402 addr = 72,
2403 chan = 73,
2404 val = 74,
2405 update_exec_mask = 75,
2406 update_pred = 76,
2407 write = 77,
2408 omod = 78,
2409 dst_rel = 79,
2410 clamp = 80,
2411 src0_neg = 81,
2412 src0_rel = 82,
2413 src0_abs = 83,
2414 src0_sel = 84,
2415 src1 = 85,
2416 src1_neg = 86,
2417 src1_rel = 87,
2418 src1_abs = 88,
2419 src1_sel = 89,
2420 last = 90,
2421 pred_sel = 91,
2422 literal = 92,
2423 bank_swizzle = 93,
2424 src2 = 94,
2425 src2_neg = 95,
2426 src2_rel = 96,
2427 src2_sel = 97,
2428 ADDR = 98,
2429 KCACHE_BANK0 = 99,
2430 KCACHE_BANK1 = 100,
2431 KCACHE_MODE0 = 101,
2432 KCACHE_MODE1 = 102,
2433 KCACHE_ADDR0 = 103,
2434 KCACHE_ADDR1 = 104,
2435 COUNT = 105,
2436 Enabled = 106,
2437 NUM_OPERAND_NAMES = 107,
2438}; // enum class OpName
2439
2440LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name);
2441LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx);
2442
2443} // namespace llvm::R600
2444
2445#endif // GET_INSTRINFO_OPERAND_ENUM
2446
2447#ifdef GET_INSTRINFO_NAMED_OPS
2448#undef GET_INSTRINFO_NAMED_OPS
2449
2450namespace llvm::R600 {
2451
2452LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) {
2453 static constexpr uint8_t InstructionIndex[] = {
2454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2455 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2466 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2468 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2471 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2475 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2476 0, 1, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2478 0, 0, 3, 4, 0, 0, 0, 0, 0, 5, 5, 5, 0, 5, 5, 5,
2479 6, 7, 7, 7, 5, 7, 6, 8, 8, 8, 8, 8, 8, 0, 0, 0,
2480 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 7,
2481 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 0,
2482 0, 0, 0, 6, 6, 6, 0, 6, 6, 6, 6, 6, 6, 6, 6, 6,
2483 7, 6, 0, 6, 0, 0, 0, 5, 5, 6, 6, 5, 9, 10, 9, 10,
2484 11, 9, 12, 13, 9, 10, 9, 10, 9, 10, 9, 10, 9, 10, 11, 11,
2485 9, 9, 10, 11, 11, 9, 9, 10, 9, 10, 0, 6, 6, 6, 6, 6,
2486 0, 0, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6,
2487 5, 7, 7, 7, 7, 7, 7, 5, 5, 5, 5, 5, 5, 5, 5, 5,
2488 5, 5, 5, 5, 5, 5, 5, 5, 7, 7, 5, 6, 5, 0, 0, 0,
2489 5, 5, 5, 5, 5, 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0,
2490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6,
2492 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5,
2493 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 5,
2494 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2495 0, 0, 0, 6, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2496 0, 0, 5,
2497 };
2498 return InstructionIndex[Opcode];
2499}
2500LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) {
2501 assert(Name != OpName::NUM_OPERAND_NAMES);
2502 static constexpr int8_t OperandMap[][107] = {
2503 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2504 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2505 {0, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2506 {0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2507 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 3, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2508 {0, 7, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2509 {0, 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 6, 7, 8, 9, -1, -1, -1, -1, -1, 10, 11, 12, 13, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2510 {0, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 4, 5, -1, 6, 7, 8, 9, -1, 10, 15, 16, 17, 18, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2511 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, },
2512 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 6, 7, -1, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2513 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 7, 8, -1, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2514 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, -1, -1, -1, -1, -1, 4, 5, -1, 6, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2515 {-1, 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, 2, 3, -1, 4, -1, 5, 9, 10, -1, 11, 6, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2516 {0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 3, 4, -1, 5, -1, 6, 10, 11, -1, 12, 7, -1, 8, 9, -1, -1, -1, -1, -1, -1, -1, -1, -1, },
2517 };
2518 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2519 return OperandMap[InstrIdx][(unsigned)Name];
2520}
2521LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) {
2522 assert(Idx >= 0 && Idx < 71);
2523 static constexpr OpName OperandMap[][71] = {
2524 {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2525 {OpName::dst, OpName::src0, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2526 {OpName::dst, OpName::update_exec_mask_X, OpName::update_pred_X, OpName::write_X, OpName::omod_X, OpName::dst_rel_X, OpName::clamp_X, OpName::src0_X, OpName::src0_neg_X, OpName::src0_rel_X, OpName::src0_abs_X, OpName::src0_sel_X, OpName::src1_X, OpName::src1_neg_X, OpName::src1_rel_X, OpName::src1_abs_X, OpName::src1_sel_X, OpName::pred_sel_X, OpName::update_exec_mask_Y, OpName::update_pred_Y, OpName::write_Y, OpName::omod_Y, OpName::dst_rel_Y, OpName::clamp_Y, OpName::src0_Y, OpName::src0_neg_Y, OpName::src0_rel_Y, OpName::src0_abs_Y, OpName::src0_sel_Y, OpName::src1_Y, OpName::src1_neg_Y, OpName::src1_rel_Y, OpName::src1_abs_Y, OpName::src1_sel_Y, OpName::pred_sel_Y, OpName::update_exec_mask_Z, OpName::update_pred_Z, OpName::write_Z, OpName::omod_Z, OpName::dst_rel_Z, OpName::clamp_Z, OpName::src0_Z, OpName::src0_neg_Z, OpName::src0_rel_Z, OpName::src0_abs_Z, OpName::src0_sel_Z, OpName::src1_Z, OpName::src1_neg_Z, OpName::src1_rel_Z, OpName::src1_abs_Z, OpName::src1_sel_Z, OpName::pred_sel_Z, OpName::update_exec_mask_W, OpName::update_pred_W, OpName::write_W, OpName::omod_W, OpName::dst_rel_W, OpName::clamp_W, OpName::src0_W, OpName::src0_neg_W, OpName::src0_rel_W, OpName::src0_abs_W, OpName::src0_sel_W, OpName::src1_W, OpName::src1_neg_W, OpName::src1_rel_W, OpName::src1_abs_W, OpName::src1_sel_W, OpName::pred_sel_W, OpName::literal0, OpName::literal1, },
2527 {OpName::dst, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2528 {OpName::val, OpName::addr, OpName::NUM_OPERAND_NAMES, OpName::chan, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2529 {OpName::dst, OpName::update_exec_mask, OpName::update_pred, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_abs, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2530 {OpName::dst, OpName::write, OpName::omod, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_abs, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2531 {OpName::dst, OpName::dst_rel, OpName::clamp, OpName::src0, OpName::src0_neg, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_neg, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_neg, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::literal, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2532 {OpName::ADDR, OpName::KCACHE_BANK0, OpName::KCACHE_BANK1, OpName::KCACHE_MODE0, OpName::KCACHE_MODE1, OpName::KCACHE_ADDR0, OpName::KCACHE_ADDR1, OpName::COUNT, OpName::Enabled, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2533 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2534 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2535 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2536 {OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2537 {OpName::dst, OpName::src0, OpName::src0_rel, OpName::src0_sel, OpName::src1, OpName::src1_rel, OpName::src1_sel, OpName::src2, OpName::src2_rel, OpName::src2_sel, OpName::last, OpName::pred_sel, OpName::bank_swizzle, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
2538 };
2539 unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
2540 return OperandMap[InstrIdx][(unsigned)Idx];
2541}
2542
2543} // namespace llvm::R600
2544
2545#endif // GET_INSTRINFO_NAMED_OPS
2546
2547#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2548#undef GET_INSTRINFO_MC_HELPER_DECLS
2549
2550namespace llvm {
2551
2552class MCInst;
2553class FeatureBitset;
2554
2555namespace R600_MC {
2556
2557void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2558
2559} // namespace R600_MC
2560
2561} // namespace llvm
2562
2563#endif // GET_INSTRINFO_MC_HELPER_DECLS
2564
2565#ifdef GET_INSTRINFO_MC_HELPERS
2566#undef GET_INSTRINFO_MC_HELPERS
2567
2568namespace llvm::R600_MC {
2569
2570
2571} // namespace llvm::R600_MC
2572
2573#endif // GET_INSTRINFO_MC_HELPERS
2574
2575#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2576 defined(GET_AVAILABLE_OPCODE_CHECKER)
2577#define GET_COMPUTE_FEATURES
2578#endif
2579#ifdef GET_COMPUTE_FEATURES
2580#undef GET_COMPUTE_FEATURES
2581
2582namespace llvm::R600_MC {
2583
2584// Bits for subtarget features that participate in instruction matching.
2585enum SubtargetFeatureBits : uint8_t {
2586};
2587
2588inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2589 FeatureBitset Features;
2590 return Features;
2591}
2592
2593inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2594 enum : uint8_t {
2595 CEFBS_None,
2596 };
2597
2598 static constexpr FeatureBitset FeatureBitsets[] = {
2599 {}, // CEFBS_None
2600 };
2601 static constexpr uint8_t RequiredFeaturesRefs[] = {
2602 CEFBS_None, // PHI
2603 CEFBS_None, // INLINEASM
2604 CEFBS_None, // INLINEASM_BR
2605 CEFBS_None, // CFI_INSTRUCTION
2606 CEFBS_None, // EH_LABEL
2607 CEFBS_None, // GC_LABEL
2608 CEFBS_None, // ANNOTATION_LABEL
2609 CEFBS_None, // KILL
2610 CEFBS_None, // EXTRACT_SUBREG
2611 CEFBS_None, // INSERT_SUBREG
2612 CEFBS_None, // IMPLICIT_DEF
2613 CEFBS_None, // INIT_UNDEF
2614 CEFBS_None, // SUBREG_TO_REG
2615 CEFBS_None, // COPY_TO_REGCLASS
2616 CEFBS_None, // DBG_VALUE
2617 CEFBS_None, // DBG_VALUE_LIST
2618 CEFBS_None, // DBG_INSTR_REF
2619 CEFBS_None, // DBG_PHI
2620 CEFBS_None, // DBG_LABEL
2621 CEFBS_None, // REG_SEQUENCE
2622 CEFBS_None, // COPY
2623 CEFBS_None, // COPY_LANEMASK
2624 CEFBS_None, // BUNDLE
2625 CEFBS_None, // LIFETIME_START
2626 CEFBS_None, // LIFETIME_END
2627 CEFBS_None, // PSEUDO_PROBE
2628 CEFBS_None, // ARITH_FENCE
2629 CEFBS_None, // STACKMAP
2630 CEFBS_None, // FENTRY_CALL
2631 CEFBS_None, // PATCHPOINT
2632 CEFBS_None, // LOAD_STACK_GUARD
2633 CEFBS_None, // PREALLOCATED_SETUP
2634 CEFBS_None, // PREALLOCATED_ARG
2635 CEFBS_None, // STATEPOINT
2636 CEFBS_None, // LOCAL_ESCAPE
2637 CEFBS_None, // FAULTING_OP
2638 CEFBS_None, // PATCHABLE_OP
2639 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
2640 CEFBS_None, // PATCHABLE_RET
2641 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
2642 CEFBS_None, // PATCHABLE_TAIL_CALL
2643 CEFBS_None, // PATCHABLE_EVENT_CALL
2644 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
2645 CEFBS_None, // ICALL_BRANCH_FUNNEL
2646 CEFBS_None, // FAKE_USE
2647 CEFBS_None, // MEMBARRIER
2648 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
2649 CEFBS_None, // RELOC_NONE
2650 CEFBS_None, // CONVERGENCECTRL_ENTRY
2651 CEFBS_None, // CONVERGENCECTRL_ANCHOR
2652 CEFBS_None, // CONVERGENCECTRL_LOOP
2653 CEFBS_None, // CONVERGENCECTRL_GLUE
2654 CEFBS_None, // G_ASSERT_SEXT
2655 CEFBS_None, // G_ASSERT_ZEXT
2656 CEFBS_None, // G_ASSERT_ALIGN
2657 CEFBS_None, // G_ADD
2658 CEFBS_None, // G_SUB
2659 CEFBS_None, // G_MUL
2660 CEFBS_None, // G_SDIV
2661 CEFBS_None, // G_UDIV
2662 CEFBS_None, // G_SREM
2663 CEFBS_None, // G_UREM
2664 CEFBS_None, // G_SDIVREM
2665 CEFBS_None, // G_UDIVREM
2666 CEFBS_None, // G_AND
2667 CEFBS_None, // G_OR
2668 CEFBS_None, // G_XOR
2669 CEFBS_None, // G_ABDS
2670 CEFBS_None, // G_ABDU
2671 CEFBS_None, // G_UAVGFLOOR
2672 CEFBS_None, // G_UAVGCEIL
2673 CEFBS_None, // G_SAVGFLOOR
2674 CEFBS_None, // G_SAVGCEIL
2675 CEFBS_None, // G_IMPLICIT_DEF
2676 CEFBS_None, // G_PHI
2677 CEFBS_None, // G_FRAME_INDEX
2678 CEFBS_None, // G_GLOBAL_VALUE
2679 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2680 CEFBS_None, // G_CONSTANT_POOL
2681 CEFBS_None, // G_EXTRACT
2682 CEFBS_None, // G_UNMERGE_VALUES
2683 CEFBS_None, // G_INSERT
2684 CEFBS_None, // G_MERGE_VALUES
2685 CEFBS_None, // G_BUILD_VECTOR
2686 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2687 CEFBS_None, // G_CONCAT_VECTORS
2688 CEFBS_None, // G_PTRTOINT
2689 CEFBS_None, // G_INTTOPTR
2690 CEFBS_None, // G_BITCAST
2691 CEFBS_None, // G_FREEZE
2692 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2693 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2694 CEFBS_None, // G_INTRINSIC_TRUNC
2695 CEFBS_None, // G_INTRINSIC_ROUND
2696 CEFBS_None, // G_INTRINSIC_LRINT
2697 CEFBS_None, // G_INTRINSIC_LLRINT
2698 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2699 CEFBS_None, // G_READCYCLECOUNTER
2700 CEFBS_None, // G_READSTEADYCOUNTER
2701 CEFBS_None, // G_LOAD
2702 CEFBS_None, // G_SEXTLOAD
2703 CEFBS_None, // G_ZEXTLOAD
2704 CEFBS_None, // G_FPEXTLOAD
2705 CEFBS_None, // G_INDEXED_LOAD
2706 CEFBS_None, // G_INDEXED_SEXTLOAD
2707 CEFBS_None, // G_INDEXED_ZEXTLOAD
2708 CEFBS_None, // G_STORE
2709 CEFBS_None, // G_FPTRUNCSTORE
2710 CEFBS_None, // G_INDEXED_STORE
2711 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2712 CEFBS_None, // G_ATOMIC_CMPXCHG
2713 CEFBS_None, // G_ATOMICRMW_XCHG
2714 CEFBS_None, // G_ATOMICRMW_ADD
2715 CEFBS_None, // G_ATOMICRMW_SUB
2716 CEFBS_None, // G_ATOMICRMW_AND
2717 CEFBS_None, // G_ATOMICRMW_NAND
2718 CEFBS_None, // G_ATOMICRMW_OR
2719 CEFBS_None, // G_ATOMICRMW_XOR
2720 CEFBS_None, // G_ATOMICRMW_MAX
2721 CEFBS_None, // G_ATOMICRMW_MIN
2722 CEFBS_None, // G_ATOMICRMW_UMAX
2723 CEFBS_None, // G_ATOMICRMW_UMIN
2724 CEFBS_None, // G_ATOMICRMW_FADD
2725 CEFBS_None, // G_ATOMICRMW_FSUB
2726 CEFBS_None, // G_ATOMICRMW_FMAX
2727 CEFBS_None, // G_ATOMICRMW_FMIN
2728 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2729 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2730 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2731 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2732 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2733 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2734 CEFBS_None, // G_ATOMICRMW_USUB_COND
2735 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2736 CEFBS_None, // G_FENCE
2737 CEFBS_None, // G_PREFETCH
2738 CEFBS_None, // G_BRCOND
2739 CEFBS_None, // G_BRINDIRECT
2740 CEFBS_None, // G_INVOKE_REGION_START
2741 CEFBS_None, // G_INTRINSIC
2742 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2743 CEFBS_None, // G_INTRINSIC_CONVERGENT
2744 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2745 CEFBS_None, // G_ANYEXT
2746 CEFBS_None, // G_TRUNC
2747 CEFBS_None, // G_TRUNC_SSAT_S
2748 CEFBS_None, // G_TRUNC_SSAT_U
2749 CEFBS_None, // G_TRUNC_USAT_U
2750 CEFBS_None, // G_CONSTANT
2751 CEFBS_None, // G_FCONSTANT
2752 CEFBS_None, // G_VASTART
2753 CEFBS_None, // G_VAARG
2754 CEFBS_None, // G_SEXT
2755 CEFBS_None, // G_SEXT_INREG
2756 CEFBS_None, // G_ZEXT
2757 CEFBS_None, // G_SHL
2758 CEFBS_None, // G_LSHR
2759 CEFBS_None, // G_ASHR
2760 CEFBS_None, // G_FSHL
2761 CEFBS_None, // G_FSHR
2762 CEFBS_None, // G_ROTR
2763 CEFBS_None, // G_ROTL
2764 CEFBS_None, // G_ICMP
2765 CEFBS_None, // G_FCMP
2766 CEFBS_None, // G_SCMP
2767 CEFBS_None, // G_UCMP
2768 CEFBS_None, // G_SELECT
2769 CEFBS_None, // G_UADDO
2770 CEFBS_None, // G_UADDE
2771 CEFBS_None, // G_USUBO
2772 CEFBS_None, // G_USUBE
2773 CEFBS_None, // G_SADDO
2774 CEFBS_None, // G_SADDE
2775 CEFBS_None, // G_SSUBO
2776 CEFBS_None, // G_SSUBE
2777 CEFBS_None, // G_UMULO
2778 CEFBS_None, // G_SMULO
2779 CEFBS_None, // G_UMULH
2780 CEFBS_None, // G_SMULH
2781 CEFBS_None, // G_UADDSAT
2782 CEFBS_None, // G_SADDSAT
2783 CEFBS_None, // G_USUBSAT
2784 CEFBS_None, // G_SSUBSAT
2785 CEFBS_None, // G_USHLSAT
2786 CEFBS_None, // G_SSHLSAT
2787 CEFBS_None, // G_SMULFIX
2788 CEFBS_None, // G_UMULFIX
2789 CEFBS_None, // G_SMULFIXSAT
2790 CEFBS_None, // G_UMULFIXSAT
2791 CEFBS_None, // G_SDIVFIX
2792 CEFBS_None, // G_UDIVFIX
2793 CEFBS_None, // G_SDIVFIXSAT
2794 CEFBS_None, // G_UDIVFIXSAT
2795 CEFBS_None, // G_FADD
2796 CEFBS_None, // G_FSUB
2797 CEFBS_None, // G_FMUL
2798 CEFBS_None, // G_FMA
2799 CEFBS_None, // G_FMAD
2800 CEFBS_None, // G_FDIV
2801 CEFBS_None, // G_FREM
2802 CEFBS_None, // G_FMODF
2803 CEFBS_None, // G_FPOW
2804 CEFBS_None, // G_FPOWI
2805 CEFBS_None, // G_FEXP
2806 CEFBS_None, // G_FEXP2
2807 CEFBS_None, // G_FEXP10
2808 CEFBS_None, // G_FLOG
2809 CEFBS_None, // G_FLOG2
2810 CEFBS_None, // G_FLOG10
2811 CEFBS_None, // G_FLDEXP
2812 CEFBS_None, // G_FFREXP
2813 CEFBS_None, // G_FNEG
2814 CEFBS_None, // G_FPEXT
2815 CEFBS_None, // G_FPTRUNC
2816 CEFBS_None, // G_FPTOSI
2817 CEFBS_None, // G_FPTOUI
2818 CEFBS_None, // G_SITOFP
2819 CEFBS_None, // G_UITOFP
2820 CEFBS_None, // G_FPTOSI_SAT
2821 CEFBS_None, // G_FPTOUI_SAT
2822 CEFBS_None, // G_FABS
2823 CEFBS_None, // G_FCOPYSIGN
2824 CEFBS_None, // G_IS_FPCLASS
2825 CEFBS_None, // G_FCANONICALIZE
2826 CEFBS_None, // G_FMINNUM
2827 CEFBS_None, // G_FMAXNUM
2828 CEFBS_None, // G_FMINNUM_IEEE
2829 CEFBS_None, // G_FMAXNUM_IEEE
2830 CEFBS_None, // G_FMINIMUM
2831 CEFBS_None, // G_FMAXIMUM
2832 CEFBS_None, // G_FMINIMUMNUM
2833 CEFBS_None, // G_FMAXIMUMNUM
2834 CEFBS_None, // G_GET_FPENV
2835 CEFBS_None, // G_SET_FPENV
2836 CEFBS_None, // G_RESET_FPENV
2837 CEFBS_None, // G_GET_FPMODE
2838 CEFBS_None, // G_SET_FPMODE
2839 CEFBS_None, // G_RESET_FPMODE
2840 CEFBS_None, // G_GET_ROUNDING
2841 CEFBS_None, // G_SET_ROUNDING
2842 CEFBS_None, // G_PTR_ADD
2843 CEFBS_None, // G_PTRMASK
2844 CEFBS_None, // G_SMIN
2845 CEFBS_None, // G_SMAX
2846 CEFBS_None, // G_UMIN
2847 CEFBS_None, // G_UMAX
2848 CEFBS_None, // G_ABS
2849 CEFBS_None, // G_LROUND
2850 CEFBS_None, // G_LLROUND
2851 CEFBS_None, // G_BR
2852 CEFBS_None, // G_BRJT
2853 CEFBS_None, // G_VSCALE
2854 CEFBS_None, // G_INSERT_SUBVECTOR
2855 CEFBS_None, // G_EXTRACT_SUBVECTOR
2856 CEFBS_None, // G_INSERT_VECTOR_ELT
2857 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2858 CEFBS_None, // G_SHUFFLE_VECTOR
2859 CEFBS_None, // G_SPLAT_VECTOR
2860 CEFBS_None, // G_STEP_VECTOR
2861 CEFBS_None, // G_VECTOR_COMPRESS
2862 CEFBS_None, // G_CTTZ
2863 CEFBS_None, // G_CTTZ_ZERO_POISON
2864 CEFBS_None, // G_CTLZ
2865 CEFBS_None, // G_CTLZ_ZERO_POISON
2866 CEFBS_None, // G_CTLS
2867 CEFBS_None, // G_CTPOP
2868 CEFBS_None, // G_BSWAP
2869 CEFBS_None, // G_BITREVERSE
2870 CEFBS_None, // G_CLMUL
2871 CEFBS_None, // G_CLMULH
2872 CEFBS_None, // G_CLMULR
2873 CEFBS_None, // G_FCEIL
2874 CEFBS_None, // G_FCOS
2875 CEFBS_None, // G_FSIN
2876 CEFBS_None, // G_FSINCOS
2877 CEFBS_None, // G_FTAN
2878 CEFBS_None, // G_FACOS
2879 CEFBS_None, // G_FASIN
2880 CEFBS_None, // G_FATAN
2881 CEFBS_None, // G_FATAN2
2882 CEFBS_None, // G_FCOSH
2883 CEFBS_None, // G_FSINH
2884 CEFBS_None, // G_FTANH
2885 CEFBS_None, // G_FSQRT
2886 CEFBS_None, // G_FFLOOR
2887 CEFBS_None, // G_FRINT
2888 CEFBS_None, // G_FNEARBYINT
2889 CEFBS_None, // G_ADDRSPACE_CAST
2890 CEFBS_None, // G_BLOCK_ADDR
2891 CEFBS_None, // G_JUMP_TABLE
2892 CEFBS_None, // G_DYN_STACKALLOC
2893 CEFBS_None, // G_STACKSAVE
2894 CEFBS_None, // G_STACKRESTORE
2895 CEFBS_None, // G_STRICT_FADD
2896 CEFBS_None, // G_STRICT_FSUB
2897 CEFBS_None, // G_STRICT_FMUL
2898 CEFBS_None, // G_STRICT_FDIV
2899 CEFBS_None, // G_STRICT_FREM
2900 CEFBS_None, // G_STRICT_FMA
2901 CEFBS_None, // G_STRICT_FSQRT
2902 CEFBS_None, // G_STRICT_FLDEXP
2903 CEFBS_None, // G_STRICT_FCMP
2904 CEFBS_None, // G_STRICT_FCMPS
2905 CEFBS_None, // G_READ_REGISTER
2906 CEFBS_None, // G_WRITE_REGISTER
2907 CEFBS_None, // G_MEMCPY
2908 CEFBS_None, // G_MEMCPY_INLINE
2909 CEFBS_None, // G_MEMMOVE
2910 CEFBS_None, // G_MEMSET
2911 CEFBS_None, // G_BZERO
2912 CEFBS_None, // G_MEMSET_INLINE
2913 CEFBS_None, // G_TRAP
2914 CEFBS_None, // G_DEBUGTRAP
2915 CEFBS_None, // G_UBSANTRAP
2916 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2917 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2918 CEFBS_None, // G_VECREDUCE_FADD
2919 CEFBS_None, // G_VECREDUCE_FMUL
2920 CEFBS_None, // G_VECREDUCE_FMAX
2921 CEFBS_None, // G_VECREDUCE_FMIN
2922 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2923 CEFBS_None, // G_VECREDUCE_FMINIMUM
2924 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2925 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2926 CEFBS_None, // G_VECREDUCE_ADD
2927 CEFBS_None, // G_VECREDUCE_MUL
2928 CEFBS_None, // G_VECREDUCE_AND
2929 CEFBS_None, // G_VECREDUCE_OR
2930 CEFBS_None, // G_VECREDUCE_XOR
2931 CEFBS_None, // G_VECREDUCE_SMAX
2932 CEFBS_None, // G_VECREDUCE_SMIN
2933 CEFBS_None, // G_VECREDUCE_UMAX
2934 CEFBS_None, // G_VECREDUCE_UMIN
2935 CEFBS_None, // G_SBFX
2936 CEFBS_None, // G_UBFX
2937 CEFBS_None, // BRANCH
2938 CEFBS_None, // BRANCH_COND_f32
2939 CEFBS_None, // BRANCH_COND_i32
2940 CEFBS_None, // BREAK
2941 CEFBS_None, // BREAKC_f32
2942 CEFBS_None, // BREAKC_i32
2943 CEFBS_None, // BREAK_LOGICALNZ_f32
2944 CEFBS_None, // BREAK_LOGICALNZ_i32
2945 CEFBS_None, // BREAK_LOGICALZ_f32
2946 CEFBS_None, // BREAK_LOGICALZ_i32
2947 CEFBS_None, // CONST_COPY
2948 CEFBS_None, // CONTINUE
2949 CEFBS_None, // CONTINUEC_f32
2950 CEFBS_None, // CONTINUEC_i32
2951 CEFBS_None, // CONTINUE_LOGICALNZ_f32
2952 CEFBS_None, // CONTINUE_LOGICALNZ_i32
2953 CEFBS_None, // CONTINUE_LOGICALZ_f32
2954 CEFBS_None, // CONTINUE_LOGICALZ_i32
2955 CEFBS_None, // CUBE_eg_pseudo
2956 CEFBS_None, // CUBE_r600_pseudo
2957 CEFBS_None, // DEFAULT
2958 CEFBS_None, // DOT_4
2959 CEFBS_None, // DUMMY_CHAIN
2960 CEFBS_None, // ELSE
2961 CEFBS_None, // END
2962 CEFBS_None, // ENDFUNC
2963 CEFBS_None, // ENDIF
2964 CEFBS_None, // ENDLOOP
2965 CEFBS_None, // ENDMAIN
2966 CEFBS_None, // ENDSWITCH
2967 CEFBS_None, // FABS_R600
2968 CEFBS_None, // FNEG_R600
2969 CEFBS_None, // FUNC
2970 CEFBS_None, // IFC_f32
2971 CEFBS_None, // IFC_i32
2972 CEFBS_None, // IF_LOGICALNZ_f32
2973 CEFBS_None, // IF_LOGICALNZ_i32
2974 CEFBS_None, // IF_LOGICALZ_f32
2975 CEFBS_None, // IF_LOGICALZ_i32
2976 CEFBS_None, // IF_PREDICATE_SET
2977 CEFBS_None, // JUMP
2978 CEFBS_None, // JUMP_COND
2979 CEFBS_None, // MASK_WRITE
2980 CEFBS_None, // MOV_IMM_F32
2981 CEFBS_None, // MOV_IMM_GLOBAL_ADDR
2982 CEFBS_None, // MOV_IMM_I32
2983 CEFBS_None, // PRED_X
2984 CEFBS_None, // R600_EXTRACT_ELT_V2
2985 CEFBS_None, // R600_EXTRACT_ELT_V4
2986 CEFBS_None, // R600_INSERT_ELT_V2
2987 CEFBS_None, // R600_INSERT_ELT_V4
2988 CEFBS_None, // R600_RegisterLoad
2989 CEFBS_None, // R600_RegisterStore
2990 CEFBS_None, // RETDYN
2991 CEFBS_None, // RETURN
2992 CEFBS_None, // TXD
2993 CEFBS_None, // TXD_SHADOW
2994 CEFBS_None, // WHILELOOP
2995 CEFBS_None, // ADD
2996 CEFBS_None, // ADDC_UINT
2997 CEFBS_None, // ADD_INT
2998 CEFBS_None, // ALU_CLAUSE
2999 CEFBS_None, // AND_INT
3000 CEFBS_None, // ASHR_eg
3001 CEFBS_None, // ASHR_r600
3002 CEFBS_None, // BCNT_INT
3003 CEFBS_None, // BFE_INT_eg
3004 CEFBS_None, // BFE_UINT_eg
3005 CEFBS_None, // BFI_INT_eg
3006 CEFBS_None, // BFM_INT_eg
3007 CEFBS_None, // BIT_ALIGN_INT_eg
3008 CEFBS_None, // CEIL
3009 CEFBS_None, // CF_ALU
3010 CEFBS_None, // CF_ALU_BREAK
3011 CEFBS_None, // CF_ALU_CONTINUE
3012 CEFBS_None, // CF_ALU_ELSE_AFTER
3013 CEFBS_None, // CF_ALU_POP_AFTER
3014 CEFBS_None, // CF_ALU_PUSH_BEFORE
3015 CEFBS_None, // CF_CALL_FS_EG
3016 CEFBS_None, // CF_CALL_FS_R600
3017 CEFBS_None, // CF_CONTINUE_EG
3018 CEFBS_None, // CF_CONTINUE_R600
3019 CEFBS_None, // CF_ELSE_EG
3020 CEFBS_None, // CF_ELSE_R600
3021 CEFBS_None, // CF_END_CM
3022 CEFBS_None, // CF_END_EG
3023 CEFBS_None, // CF_END_R600
3024 CEFBS_None, // CF_JUMP_EG
3025 CEFBS_None, // CF_JUMP_R600
3026 CEFBS_None, // CF_PUSH_EG
3027 CEFBS_None, // CF_PUSH_ELSE_R600
3028 CEFBS_None, // CF_TC_EG
3029 CEFBS_None, // CF_TC_R600
3030 CEFBS_None, // CF_VC_EG
3031 CEFBS_None, // CF_VC_R600
3032 CEFBS_None, // CNDE_INT
3033 CEFBS_None, // CNDE_eg
3034 CEFBS_None, // CNDE_r600
3035 CEFBS_None, // CNDGE_INT
3036 CEFBS_None, // CNDGE_eg
3037 CEFBS_None, // CNDGE_r600
3038 CEFBS_None, // CNDGT_INT
3039 CEFBS_None, // CNDGT_eg
3040 CEFBS_None, // CNDGT_r600
3041 CEFBS_None, // COS_cm
3042 CEFBS_None, // COS_eg
3043 CEFBS_None, // COS_r600
3044 CEFBS_None, // COS_r700
3045 CEFBS_None, // CUBE_eg_real
3046 CEFBS_None, // CUBE_r600_real
3047 CEFBS_None, // DOT4_eg
3048 CEFBS_None, // DOT4_r600
3049 CEFBS_None, // EG_ExportBuf
3050 CEFBS_None, // EG_ExportSwz
3051 CEFBS_None, // END_LOOP_EG
3052 CEFBS_None, // END_LOOP_R600
3053 CEFBS_None, // EXP_IEEE_cm
3054 CEFBS_None, // EXP_IEEE_eg
3055 CEFBS_None, // EXP_IEEE_r600
3056 CEFBS_None, // FETCH_CLAUSE
3057 CEFBS_None, // FFBH_UINT
3058 CEFBS_None, // FFBL_INT
3059 CEFBS_None, // FLOOR
3060 CEFBS_None, // FLT16_TO_FLT32
3061 CEFBS_None, // FLT32_TO_FLT16
3062 CEFBS_None, // FLT_TO_INT_eg
3063 CEFBS_None, // FLT_TO_INT_r600
3064 CEFBS_None, // FLT_TO_UINT_eg
3065 CEFBS_None, // FLT_TO_UINT_r600
3066 CEFBS_None, // FMA_eg
3067 CEFBS_None, // FRACT
3068 CEFBS_None, // GROUP_BARRIER
3069 CEFBS_None, // INTERP_LOAD_P0
3070 CEFBS_None, // INTERP_PAIR_XY
3071 CEFBS_None, // INTERP_PAIR_ZW
3072 CEFBS_None, // INTERP_VEC_LOAD
3073 CEFBS_None, // INTERP_XY
3074 CEFBS_None, // INTERP_ZW
3075 CEFBS_None, // INT_TO_FLT_eg
3076 CEFBS_None, // INT_TO_FLT_r600
3077 CEFBS_None, // KILLGT
3078 CEFBS_None, // LDS_ADD
3079 CEFBS_None, // LDS_ADD_RET
3080 CEFBS_None, // LDS_AND
3081 CEFBS_None, // LDS_AND_RET
3082 CEFBS_None, // LDS_BYTE_READ_RET
3083 CEFBS_None, // LDS_BYTE_WRITE
3084 CEFBS_None, // LDS_CMPST
3085 CEFBS_None, // LDS_CMPST_RET
3086 CEFBS_None, // LDS_MAX_INT
3087 CEFBS_None, // LDS_MAX_INT_RET
3088 CEFBS_None, // LDS_MAX_UINT
3089 CEFBS_None, // LDS_MAX_UINT_RET
3090 CEFBS_None, // LDS_MIN_INT
3091 CEFBS_None, // LDS_MIN_INT_RET
3092 CEFBS_None, // LDS_MIN_UINT
3093 CEFBS_None, // LDS_MIN_UINT_RET
3094 CEFBS_None, // LDS_OR
3095 CEFBS_None, // LDS_OR_RET
3096 CEFBS_None, // LDS_READ_RET
3097 CEFBS_None, // LDS_SHORT_READ_RET
3098 CEFBS_None, // LDS_SHORT_WRITE
3099 CEFBS_None, // LDS_SUB
3100 CEFBS_None, // LDS_SUB_RET
3101 CEFBS_None, // LDS_UBYTE_READ_RET
3102 CEFBS_None, // LDS_USHORT_READ_RET
3103 CEFBS_None, // LDS_WRITE
3104 CEFBS_None, // LDS_WRXCHG
3105 CEFBS_None, // LDS_WRXCHG_RET
3106 CEFBS_None, // LDS_XOR
3107 CEFBS_None, // LDS_XOR_RET
3108 CEFBS_None, // LITERALS
3109 CEFBS_None, // LOG_CLAMPED_eg
3110 CEFBS_None, // LOG_CLAMPED_r600
3111 CEFBS_None, // LOG_IEEE_cm
3112 CEFBS_None, // LOG_IEEE_eg
3113 CEFBS_None, // LOG_IEEE_r600
3114 CEFBS_None, // LOOP_BREAK_EG
3115 CEFBS_None, // LOOP_BREAK_R600
3116 CEFBS_None, // LSHL_eg
3117 CEFBS_None, // LSHL_r600
3118 CEFBS_None, // LSHR_eg
3119 CEFBS_None, // LSHR_r600
3120 CEFBS_None, // MAX
3121 CEFBS_None, // MAX_DX10
3122 CEFBS_None, // MAX_INT
3123 CEFBS_None, // MAX_UINT
3124 CEFBS_None, // MIN
3125 CEFBS_None, // MIN_DX10
3126 CEFBS_None, // MIN_INT
3127 CEFBS_None, // MIN_UINT
3128 CEFBS_None, // MOV
3129 CEFBS_None, // MOVA_INT_eg
3130 CEFBS_None, // MUL
3131 CEFBS_None, // MULADD_IEEE_eg
3132 CEFBS_None, // MULADD_IEEE_r600
3133 CEFBS_None, // MULADD_INT24_cm
3134 CEFBS_None, // MULADD_UINT24_eg
3135 CEFBS_None, // MULADD_eg
3136 CEFBS_None, // MULADD_r600
3137 CEFBS_None, // MULHI_INT_cm
3138 CEFBS_None, // MULHI_INT_cm24
3139 CEFBS_None, // MULHI_INT_eg
3140 CEFBS_None, // MULHI_INT_r600
3141 CEFBS_None, // MULHI_UINT24_eg
3142 CEFBS_None, // MULHI_UINT_cm
3143 CEFBS_None, // MULHI_UINT_cm24
3144 CEFBS_None, // MULHI_UINT_eg
3145 CEFBS_None, // MULHI_UINT_r600
3146 CEFBS_None, // MULLO_INT_cm
3147 CEFBS_None, // MULLO_INT_eg
3148 CEFBS_None, // MULLO_INT_r600
3149 CEFBS_None, // MULLO_UINT_cm
3150 CEFBS_None, // MULLO_UINT_eg
3151 CEFBS_None, // MULLO_UINT_r600
3152 CEFBS_None, // MUL_IEEE
3153 CEFBS_None, // MUL_INT24_cm
3154 CEFBS_None, // MUL_LIT_eg
3155 CEFBS_None, // MUL_LIT_r600
3156 CEFBS_None, // MUL_UINT24_eg
3157 CEFBS_None, // NOT_INT
3158 CEFBS_None, // OR_INT
3159 CEFBS_None, // PAD
3160 CEFBS_None, // POP_EG
3161 CEFBS_None, // POP_R600
3162 CEFBS_None, // PRED_SETE
3163 CEFBS_None, // PRED_SETE_INT
3164 CEFBS_None, // PRED_SETGE
3165 CEFBS_None, // PRED_SETGE_INT
3166 CEFBS_None, // PRED_SETGT
3167 CEFBS_None, // PRED_SETGT_INT
3168 CEFBS_None, // PRED_SETNE
3169 CEFBS_None, // PRED_SETNE_INT
3170 CEFBS_None, // R600_ExportBuf
3171 CEFBS_None, // R600_ExportSwz
3172 CEFBS_None, // RAT_ATOMIC_ADD_NORET
3173 CEFBS_None, // RAT_ATOMIC_ADD_RTN
3174 CEFBS_None, // RAT_ATOMIC_AND_NORET
3175 CEFBS_None, // RAT_ATOMIC_AND_RTN
3176 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_NORET
3177 CEFBS_None, // RAT_ATOMIC_CMPXCHG_INT_RTN
3178 CEFBS_None, // RAT_ATOMIC_DEC_UINT_NORET
3179 CEFBS_None, // RAT_ATOMIC_DEC_UINT_RTN
3180 CEFBS_None, // RAT_ATOMIC_INC_UINT_NORET
3181 CEFBS_None, // RAT_ATOMIC_INC_UINT_RTN
3182 CEFBS_None, // RAT_ATOMIC_MAX_INT_NORET
3183 CEFBS_None, // RAT_ATOMIC_MAX_INT_RTN
3184 CEFBS_None, // RAT_ATOMIC_MAX_UINT_NORET
3185 CEFBS_None, // RAT_ATOMIC_MAX_UINT_RTN
3186 CEFBS_None, // RAT_ATOMIC_MIN_INT_NORET
3187 CEFBS_None, // RAT_ATOMIC_MIN_INT_RTN
3188 CEFBS_None, // RAT_ATOMIC_MIN_UINT_NORET
3189 CEFBS_None, // RAT_ATOMIC_MIN_UINT_RTN
3190 CEFBS_None, // RAT_ATOMIC_OR_NORET
3191 CEFBS_None, // RAT_ATOMIC_OR_RTN
3192 CEFBS_None, // RAT_ATOMIC_RSUB_NORET
3193 CEFBS_None, // RAT_ATOMIC_RSUB_RTN
3194 CEFBS_None, // RAT_ATOMIC_SUB_NORET
3195 CEFBS_None, // RAT_ATOMIC_SUB_RTN
3196 CEFBS_None, // RAT_ATOMIC_XCHG_INT_NORET
3197 CEFBS_None, // RAT_ATOMIC_XCHG_INT_RTN
3198 CEFBS_None, // RAT_ATOMIC_XOR_NORET
3199 CEFBS_None, // RAT_ATOMIC_XOR_RTN
3200 CEFBS_None, // RAT_MSKOR
3201 CEFBS_None, // RAT_STORE_DWORD128
3202 CEFBS_None, // RAT_STORE_DWORD32
3203 CEFBS_None, // RAT_STORE_DWORD64
3204 CEFBS_None, // RAT_STORE_TYPED_cm
3205 CEFBS_None, // RAT_STORE_TYPED_eg
3206 CEFBS_None, // RAT_WRITE_CACHELESS_128_eg
3207 CEFBS_None, // RAT_WRITE_CACHELESS_32_eg
3208 CEFBS_None, // RAT_WRITE_CACHELESS_64_eg
3209 CEFBS_None, // RECIPSQRT_CLAMPED_cm
3210 CEFBS_None, // RECIPSQRT_CLAMPED_eg
3211 CEFBS_None, // RECIPSQRT_CLAMPED_r600
3212 CEFBS_None, // RECIPSQRT_IEEE_cm
3213 CEFBS_None, // RECIPSQRT_IEEE_eg
3214 CEFBS_None, // RECIPSQRT_IEEE_r600
3215 CEFBS_None, // RECIP_CLAMPED_cm
3216 CEFBS_None, // RECIP_CLAMPED_eg
3217 CEFBS_None, // RECIP_CLAMPED_r600
3218 CEFBS_None, // RECIP_IEEE_cm
3219 CEFBS_None, // RECIP_IEEE_eg
3220 CEFBS_None, // RECIP_IEEE_r600
3221 CEFBS_None, // RECIP_UINT_eg
3222 CEFBS_None, // RECIP_UINT_r600
3223 CEFBS_None, // RNDNE
3224 CEFBS_None, // SETE
3225 CEFBS_None, // SETE_DX10
3226 CEFBS_None, // SETE_INT
3227 CEFBS_None, // SETGE_DX10
3228 CEFBS_None, // SETGE_INT
3229 CEFBS_None, // SETGE_UINT
3230 CEFBS_None, // SETGT_DX10
3231 CEFBS_None, // SETGT_INT
3232 CEFBS_None, // SETGT_UINT
3233 CEFBS_None, // SETNE_DX10
3234 CEFBS_None, // SETNE_INT
3235 CEFBS_None, // SGE
3236 CEFBS_None, // SGT
3237 CEFBS_None, // SIN_cm
3238 CEFBS_None, // SIN_eg
3239 CEFBS_None, // SIN_r600
3240 CEFBS_None, // SIN_r700
3241 CEFBS_None, // SNE
3242 CEFBS_None, // SUBB_UINT
3243 CEFBS_None, // SUB_INT
3244 CEFBS_None, // TEX_GET_GRADIENTS_H
3245 CEFBS_None, // TEX_GET_GRADIENTS_V
3246 CEFBS_None, // TEX_GET_TEXTURE_RESINFO
3247 CEFBS_None, // TEX_LD
3248 CEFBS_None, // TEX_LDPTR
3249 CEFBS_None, // TEX_SAMPLE
3250 CEFBS_None, // TEX_SAMPLE_C
3251 CEFBS_None, // TEX_SAMPLE_C_G
3252 CEFBS_None, // TEX_SAMPLE_C_L
3253 CEFBS_None, // TEX_SAMPLE_C_LB
3254 CEFBS_None, // TEX_SAMPLE_G
3255 CEFBS_None, // TEX_SAMPLE_L
3256 CEFBS_None, // TEX_SAMPLE_LB
3257 CEFBS_None, // TEX_SET_GRADIENTS_H
3258 CEFBS_None, // TEX_SET_GRADIENTS_V
3259 CEFBS_None, // TEX_VTX_CONSTBUF
3260 CEFBS_None, // TEX_VTX_TEXBUF
3261 CEFBS_None, // TRUNC
3262 CEFBS_None, // UINT_TO_FLT_eg
3263 CEFBS_None, // UINT_TO_FLT_r600
3264 CEFBS_None, // VTX_READ_128_cm
3265 CEFBS_None, // VTX_READ_128_eg
3266 CEFBS_None, // VTX_READ_16_cm
3267 CEFBS_None, // VTX_READ_16_eg
3268 CEFBS_None, // VTX_READ_32_cm
3269 CEFBS_None, // VTX_READ_32_eg
3270 CEFBS_None, // VTX_READ_64_cm
3271 CEFBS_None, // VTX_READ_64_eg
3272 CEFBS_None, // VTX_READ_8_cm
3273 CEFBS_None, // VTX_READ_8_eg
3274 CEFBS_None, // WHILE_LOOP_EG
3275 CEFBS_None, // WHILE_LOOP_R600
3276 CEFBS_None, // XOR_INT
3277 };
3278
3279 assert(Opcode < 675);
3280 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3281}
3282
3283
3284} // namespace llvm::R600_MC
3285
3286#endif // GET_COMPUTE_FEATURES
3287
3288#ifdef GET_AVAILABLE_OPCODE_CHECKER
3289#undef GET_AVAILABLE_OPCODE_CHECKER
3290
3291namespace llvm::R600_MC {
3292
3293bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3294 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3295 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3296 FeatureBitset MissingFeatures =
3297 (AvailableFeatures & RequiredFeatures) ^
3298 RequiredFeatures;
3299 return !MissingFeatures.any();
3300}
3301
3302} // namespace llvm::R600_MC
3303
3304#endif // GET_AVAILABLE_OPCODE_CHECKER
3305
3306#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3307#undef ENABLE_INSTR_PREDICATE_VERIFIER
3308
3309#include <sstream>
3310
3311namespace llvm::R600_MC {
3312
3313#ifndef NDEBUG
3314static const char *SubtargetFeatureNames[] = {
3315 nullptr
3316};
3317
3318#endif // NDEBUG
3319
3320void verifyInstructionPredicates(
3321 unsigned Opcode, const FeatureBitset &Features) {
3322#ifndef NDEBUG
3323 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3324 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3325 FeatureBitset MissingFeatures =
3326 (AvailableFeatures & RequiredFeatures) ^
3327 RequiredFeatures;
3328 if (MissingFeatures.any()) {
3329 std::ostringstream Msg;
3330 Msg << "Attempting to emit " << &R600InstrNameData[R600InstrNameIndices[Opcode]]
3331 << " instruction but the ";
3332 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3333 if (MissingFeatures.test(i))
3334 Msg << SubtargetFeatureNames[i] << " ";
3335 Msg << "predicate(s) are not met";
3336 report_fatal_error(Msg.str().c_str());
3337 }
3338#endif // NDEBUG
3339}
3340
3341} // namespace llvm::R600_MC
3342
3343#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3344
3345#ifdef GET_INSTRMAP_INFO
3346#undef GET_INSTRMAP_INFO
3347
3348namespace llvm::R600 {
3349
3350enum usesCustomInserter {
3351 usesCustomInserter_0
3352};
3353
3354// getLDSNoRetOp
3355LLVM_READONLY
3356int32_t getLDSNoRetOp(uint32_t Opcode) {
3357 using namespace R600;
3358 static constexpr uint32_t Table[][2] = {
3359 { LDS_ADD_RET, LDS_ADD },
3360 { LDS_AND_RET, LDS_AND },
3361 { LDS_MAX_INT_RET, LDS_MAX_INT },
3362 { LDS_MAX_UINT_RET, LDS_MAX_UINT },
3363 { LDS_MIN_INT_RET, LDS_MIN_INT },
3364 { LDS_MIN_UINT_RET, LDS_MIN_UINT },
3365 { LDS_OR_RET, LDS_OR },
3366 { LDS_SUB_RET, LDS_SUB },
3367 { LDS_WRXCHG_RET, LDS_WRXCHG },
3368 { LDS_XOR_RET, LDS_XOR },
3369 }; // End of Table
3370
3371 unsigned mid;
3372 unsigned start = 0;
3373 unsigned end = 10;
3374 while (start < end) {
3375 mid = start + (end - start) / 2;
3376 if (Opcode == Table[mid][0])
3377 break;
3378 if (Opcode < Table[mid][0])
3379 end = mid;
3380 else
3381 start = mid + 1;
3382 }
3383 if (start == end)
3384 return -1; // Instruction doesn't exist in this table.
3385
3386 return Table[mid][1];
3387}
3388
3389
3390} // namespace llvm::R600
3391
3392#endif // GET_INSTRMAP_INFO
3393
3394