1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass R600MCRegisterClasses[];
12
13static const MVT::SimpleValueType R600VTLists[] = {
14 /* 0 */ MVT::f32, MVT::i32, MVT::Other,
15 /* 3 */ MVT::v2f32, MVT::v2i32, MVT::i64, MVT::f64, MVT::Other,
16 /* 8 */ MVT::v2f32, MVT::v2i32, MVT::Other,
17 /* 11 */ MVT::v4f32, MVT::v4i32, MVT::Other,
18};
19
20#ifdef __GNUC__
21#pragma GCC diagnostic push
22#pragma GCC diagnostic ignored "-Woverlength-strings"
23#endif
24static constexpr char R600SubRegIndexStrings[] = {
25 /* 0 */ "sub10\000"
26 /* 6 */ "sub0\000"
27 /* 11 */ "sub11\000"
28 /* 17 */ "sub1\000"
29 /* 22 */ "sub12\000"
30 /* 28 */ "sub2\000"
31 /* 33 */ "sub13\000"
32 /* 39 */ "sub3\000"
33 /* 44 */ "sub14\000"
34 /* 50 */ "sub4\000"
35 /* 55 */ "sub15\000"
36 /* 61 */ "sub5\000"
37 /* 66 */ "sub6\000"
38 /* 71 */ "sub7\000"
39 /* 76 */ "sub8\000"
40 /* 81 */ "sub9\000"
41};
42#ifdef __GNUC__
43#pragma GCC diagnostic pop
44#endif
45
46
47static constexpr uint32_t R600SubRegIndexNameOffsets[] = {
48 6,
49 17,
50 28,
51 39,
52 50,
53 61,
54 66,
55 71,
56 76,
57 81,
58 0,
59 11,
60 22,
61 33,
62 44,
63 55,
64};
65
66static const TargetRegisterInfo::SubRegCoveredBits R600SubRegIdxRangeTable[] = {
67 { .Offset: 65535, .Size: 65535 },
68 { .Offset: 0, .Size: 32 }, // sub0
69 { .Offset: 32, .Size: 32 }, // sub1
70 { .Offset: 64, .Size: 32 }, // sub2
71 { .Offset: 96, .Size: 32 }, // sub3
72 { .Offset: 128, .Size: 32 }, // sub4
73 { .Offset: 160, .Size: 32 }, // sub5
74 { .Offset: 192, .Size: 32 }, // sub6
75 { .Offset: 224, .Size: 32 }, // sub7
76 { .Offset: 256, .Size: 32 }, // sub8
77 { .Offset: 288, .Size: 32 }, // sub9
78 { .Offset: 320, .Size: 32 }, // sub10
79 { .Offset: 352, .Size: 32 }, // sub11
80 { .Offset: 384, .Size: 32 }, // sub12
81 { .Offset: 416, .Size: 32 }, // sub13
82 { .Offset: 448, .Size: 32 }, // sub14
83 { .Offset: 480, .Size: 32 }, // sub15
84};
85
86
87static const LaneBitmask R600SubRegIndexLaneMaskTable[] = {
88 LaneBitmask::getAll(),
89 LaneBitmask(0x0000000000000001), // sub0
90 LaneBitmask(0x0000000000000002), // sub1
91 LaneBitmask(0x0000000000000004), // sub2
92 LaneBitmask(0x0000000000000008), // sub3
93 LaneBitmask(0x0000000000000010), // sub4
94 LaneBitmask(0x0000000000000020), // sub5
95 LaneBitmask(0x0000000000000040), // sub6
96 LaneBitmask(0x0000000000000080), // sub7
97 LaneBitmask(0x0000000000000100), // sub8
98 LaneBitmask(0x0000000000000200), // sub9
99 LaneBitmask(0x0000000000000400), // sub10
100 LaneBitmask(0x0000000000000800), // sub11
101 LaneBitmask(0x0000000000001000), // sub12
102 LaneBitmask(0x0000000000002000), // sub13
103 LaneBitmask(0x0000000000004000), // sub14
104 LaneBitmask(0x0000000000008000), // sub15
105 };
106
107
108
109static const TargetRegisterInfo::RegClassInfo R600RegClassInfos[] = {
110 // Mode = 0 (DefaultMode)
111 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_Reg32
112 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_TReg32
113 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_TReg32_X
114 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 1 }, // R600_Addr
115 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC0
116 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC1
117 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_TReg32_W
118 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_TReg32_Y
119 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_TReg32_Z
120 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_ArrayBase
121 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC0_W
122 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC0_X
123 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC0_Y
124 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC0_Z
125 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC1_W
126 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC1_X
127 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC1_Y
128 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_KC1_Z
129 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 1 }, // R600_LDS_SRC_REG
130 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 1 }, // R600_Predicate
131 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 1 }, // R600_Addr_W
132 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 1 }, // R600_Addr_Y
133 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 1 }, // R600_Addr_Z
134 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 0 }, // R600_LDS_SRC_REG_and_R600_Reg32
135 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*R600VTLists+*/.VTListOffset: 1 }, // R600_Predicate_Bit
136 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*R600VTLists+*/.VTListOffset: 3 }, // R600_Reg64
137 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*R600VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical
138 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*R600VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
139 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*R600VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
140 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*R600VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
141 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*R600VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
142 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*R600VTLists+*/.VTListOffset: 11 }, // R600_Reg128
143 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*R600VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical
144 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*R600VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
145 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*R600VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
146 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*R600VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
147 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*R600VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
148};
149static const uint32_t R600_Reg32SubClassMask[] = {
150 0x0083ffff, 0x00000000,
151 0xfe000000, 0x0000001f, // sub0
152 0xfe000000, 0x0000001f, // sub1
153 0x80000000, 0x0000001f, // sub2
154 0x80000000, 0x0000001f, // sub3
155};
156
157static const uint32_t R600_TReg32SubClassMask[] = {
158 0x000001c6, 0x00000000,
159 0xfe000000, 0x0000001f, // sub0
160 0xfe000000, 0x0000001f, // sub1
161 0x80000000, 0x0000001f, // sub2
162 0x80000000, 0x0000001f, // sub3
163};
164
165static const uint32_t R600_TReg32_XSubClassMask[] = {
166 0x00000004, 0x00000000,
167 0x92000000, 0x00000004, // sub0
168 0x10000000, 0x00000004, // sub1
169 0x00000000, 0x00000004, // sub2
170 0x00000000, 0x00000004, // sub3
171};
172
173static const uint32_t R600_AddrSubClassMask[] = {
174 0x00000008, 0x00000000,
175};
176
177static const uint32_t R600_KC0SubClassMask[] = {
178 0x00003c10, 0x00000000,
179};
180
181static const uint32_t R600_KC1SubClassMask[] = {
182 0x0003c020, 0x00000000,
183};
184
185static const uint32_t R600_TReg32_WSubClassMask[] = {
186 0x00000040, 0x00000000,
187 0x08000000, 0x00000002, // sub0
188 0x08000000, 0x00000002, // sub1
189 0x00000000, 0x00000002, // sub2
190 0x80000000, 0x00000002, // sub3
191};
192
193static const uint32_t R600_TReg32_YSubClassMask[] = {
194 0x00000080, 0x00000000,
195 0x20000000, 0x00000008, // sub0
196 0xa2000000, 0x00000008, // sub1
197 0x00000000, 0x00000008, // sub2
198 0x00000000, 0x00000008, // sub3
199};
200
201static const uint32_t R600_TReg32_ZSubClassMask[] = {
202 0x00000100, 0x00000000,
203 0x40000000, 0x00000010, // sub0
204 0x40000000, 0x00000010, // sub1
205 0x80000000, 0x00000010, // sub2
206 0x00000000, 0x00000010, // sub3
207};
208
209static const uint32_t R600_ArrayBaseSubClassMask[] = {
210 0x00000200, 0x00000000,
211};
212
213static const uint32_t R600_KC0_WSubClassMask[] = {
214 0x00000400, 0x00000000,
215};
216
217static const uint32_t R600_KC0_XSubClassMask[] = {
218 0x00000800, 0x00000000,
219};
220
221static const uint32_t R600_KC0_YSubClassMask[] = {
222 0x00001000, 0x00000000,
223};
224
225static const uint32_t R600_KC0_ZSubClassMask[] = {
226 0x00002000, 0x00000000,
227};
228
229static const uint32_t R600_KC1_WSubClassMask[] = {
230 0x00004000, 0x00000000,
231};
232
233static const uint32_t R600_KC1_XSubClassMask[] = {
234 0x00008000, 0x00000000,
235};
236
237static const uint32_t R600_KC1_YSubClassMask[] = {
238 0x00010000, 0x00000000,
239};
240
241static const uint32_t R600_KC1_ZSubClassMask[] = {
242 0x00020000, 0x00000000,
243};
244
245static const uint32_t R600_LDS_SRC_REGSubClassMask[] = {
246 0x00840000, 0x00000000,
247};
248
249static const uint32_t R600_PredicateSubClassMask[] = {
250 0x00080000, 0x00000000,
251};
252
253static const uint32_t R600_Addr_WSubClassMask[] = {
254 0x00100000, 0x00000000,
255};
256
257static const uint32_t R600_Addr_YSubClassMask[] = {
258 0x00200000, 0x00000000,
259};
260
261static const uint32_t R600_Addr_ZSubClassMask[] = {
262 0x00400000, 0x00000000,
263};
264
265static const uint32_t R600_LDS_SRC_REG_and_R600_Reg32SubClassMask[] = {
266 0x00800000, 0x00000000,
267};
268
269static const uint32_t R600_Predicate_BitSubClassMask[] = {
270 0x01000000, 0x00000000,
271};
272
273static const uint32_t R600_Reg64SubClassMask[] = {
274 0x02000000, 0x00000000,
275};
276
277static const uint32_t R600_Reg64VerticalSubClassMask[] = {
278 0x7c000000, 0x00000000,
279};
280
281static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSubClassMask[] = {
282 0x08000000, 0x00000000,
283};
284
285static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSubClassMask[] = {
286 0x10000000, 0x00000000,
287};
288
289static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSubClassMask[] = {
290 0x20000000, 0x00000000,
291};
292
293static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSubClassMask[] = {
294 0x40000000, 0x00000000,
295};
296
297static const uint32_t R600_Reg128SubClassMask[] = {
298 0x80000000, 0x00000000,
299};
300
301static const uint32_t R600_Reg128VerticalSubClassMask[] = {
302 0x00000000, 0x0000001f,
303};
304
305static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSubClassMask[] = {
306 0x00000000, 0x00000002,
307};
308
309static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSubClassMask[] = {
310 0x00000000, 0x00000004,
311};
312
313static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSubClassMask[] = {
314 0x00000000, 0x00000008,
315};
316
317static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSubClassMask[] = {
318 0x00000000, 0x00000010,
319};
320
321static const uint16_t SuperRegIdxSeqs[] = {
322 /* 0 */ 1, 2, 3, 4, 0,
323};
324
325static unsigned const R600_TReg32Superclasses[] = {
326 R600::R600_Reg32RegClassID,
327};
328
329static unsigned const R600_TReg32_XSuperclasses[] = {
330 R600::R600_Reg32RegClassID,
331 R600::R600_TReg32RegClassID,
332};
333
334static unsigned const R600_AddrSuperclasses[] = {
335 R600::R600_Reg32RegClassID,
336};
337
338static unsigned const R600_KC0Superclasses[] = {
339 R600::R600_Reg32RegClassID,
340};
341
342static unsigned const R600_KC1Superclasses[] = {
343 R600::R600_Reg32RegClassID,
344};
345
346static unsigned const R600_TReg32_WSuperclasses[] = {
347 R600::R600_Reg32RegClassID,
348 R600::R600_TReg32RegClassID,
349};
350
351static unsigned const R600_TReg32_YSuperclasses[] = {
352 R600::R600_Reg32RegClassID,
353 R600::R600_TReg32RegClassID,
354};
355
356static unsigned const R600_TReg32_ZSuperclasses[] = {
357 R600::R600_Reg32RegClassID,
358 R600::R600_TReg32RegClassID,
359};
360
361static unsigned const R600_ArrayBaseSuperclasses[] = {
362 R600::R600_Reg32RegClassID,
363};
364
365static unsigned const R600_KC0_WSuperclasses[] = {
366 R600::R600_Reg32RegClassID,
367 R600::R600_KC0RegClassID,
368};
369
370static unsigned const R600_KC0_XSuperclasses[] = {
371 R600::R600_Reg32RegClassID,
372 R600::R600_KC0RegClassID,
373};
374
375static unsigned const R600_KC0_YSuperclasses[] = {
376 R600::R600_Reg32RegClassID,
377 R600::R600_KC0RegClassID,
378};
379
380static unsigned const R600_KC0_ZSuperclasses[] = {
381 R600::R600_Reg32RegClassID,
382 R600::R600_KC0RegClassID,
383};
384
385static unsigned const R600_KC1_WSuperclasses[] = {
386 R600::R600_Reg32RegClassID,
387 R600::R600_KC1RegClassID,
388};
389
390static unsigned const R600_KC1_XSuperclasses[] = {
391 R600::R600_Reg32RegClassID,
392 R600::R600_KC1RegClassID,
393};
394
395static unsigned const R600_KC1_YSuperclasses[] = {
396 R600::R600_Reg32RegClassID,
397 R600::R600_KC1RegClassID,
398};
399
400static unsigned const R600_KC1_ZSuperclasses[] = {
401 R600::R600_Reg32RegClassID,
402 R600::R600_KC1RegClassID,
403};
404
405static unsigned const R600_LDS_SRC_REG_and_R600_Reg32Superclasses[] = {
406 R600::R600_Reg32RegClassID,
407 R600::R600_LDS_SRC_REGRegClassID,
408};
409
410static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = {
411 R600::R600_Reg64VerticalRegClassID,
412};
413
414static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = {
415 R600::R600_Reg64VerticalRegClassID,
416};
417
418static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = {
419 R600::R600_Reg64VerticalRegClassID,
420};
421
422static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = {
423 R600::R600_Reg64VerticalRegClassID,
424};
425
426static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = {
427 R600::R600_Reg128VerticalRegClassID,
428};
429
430static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = {
431 R600::R600_Reg128VerticalRegClassID,
432};
433
434static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = {
435 R600::R600_Reg128VerticalRegClassID,
436};
437
438static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = {
439 R600::R600_Reg128VerticalRegClassID,
440};
441
442namespace R600 {
443
444// Register class instances.
445 extern const TargetRegisterClass R600_Reg32RegClass = {
446 .MC: &R600MCRegisterClasses[R600_Reg32RegClassID],
447 .SubClassMask: R600_Reg32SubClassMask,
448 .SuperRegIndices: SuperRegIdxSeqs + 0,
449 .LaneMask: LaneBitmask(0x0000000000000001),
450 .AllocationPriority: 0,
451 .GlobalPriority: false,
452 .TSFlags: 0x00, /* TSFlags */
453 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
454 .CoveredBySubRegs: false, /* CoveredBySubRegs */
455 .SuperClasses: nullptr, .SuperClassesSize: 0,
456 .OrderFunc: nullptr
457 };
458
459 extern const TargetRegisterClass R600_TReg32RegClass = {
460 .MC: &R600MCRegisterClasses[R600_TReg32RegClassID],
461 .SubClassMask: R600_TReg32SubClassMask,
462 .SuperRegIndices: SuperRegIdxSeqs + 0,
463 .LaneMask: LaneBitmask(0x0000000000000001),
464 .AllocationPriority: 0,
465 .GlobalPriority: false,
466 .TSFlags: 0x00, /* TSFlags */
467 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
468 .CoveredBySubRegs: false, /* CoveredBySubRegs */
469 .SuperClasses: R600_TReg32Superclasses, .SuperClassesSize: 1,
470 .OrderFunc: nullptr
471 };
472
473 extern const TargetRegisterClass R600_TReg32_XRegClass = {
474 .MC: &R600MCRegisterClasses[R600_TReg32_XRegClassID],
475 .SubClassMask: R600_TReg32_XSubClassMask,
476 .SuperRegIndices: SuperRegIdxSeqs + 0,
477 .LaneMask: LaneBitmask(0x0000000000000001),
478 .AllocationPriority: 0,
479 .GlobalPriority: false,
480 .TSFlags: 0x00, /* TSFlags */
481 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
482 .CoveredBySubRegs: false, /* CoveredBySubRegs */
483 .SuperClasses: R600_TReg32_XSuperclasses, .SuperClassesSize: 2,
484 .OrderFunc: nullptr
485 };
486
487 extern const TargetRegisterClass R600_AddrRegClass = {
488 .MC: &R600MCRegisterClasses[R600_AddrRegClassID],
489 .SubClassMask: R600_AddrSubClassMask,
490 .SuperRegIndices: SuperRegIdxSeqs + 4,
491 .LaneMask: LaneBitmask(0x0000000000000001),
492 .AllocationPriority: 0,
493 .GlobalPriority: false,
494 .TSFlags: 0x00, /* TSFlags */
495 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
496 .CoveredBySubRegs: false, /* CoveredBySubRegs */
497 .SuperClasses: R600_AddrSuperclasses, .SuperClassesSize: 1,
498 .OrderFunc: nullptr
499 };
500
501 extern const TargetRegisterClass R600_KC0RegClass = {
502 .MC: &R600MCRegisterClasses[R600_KC0RegClassID],
503 .SubClassMask: R600_KC0SubClassMask,
504 .SuperRegIndices: SuperRegIdxSeqs + 4,
505 .LaneMask: LaneBitmask(0x0000000000000001),
506 .AllocationPriority: 0,
507 .GlobalPriority: false,
508 .TSFlags: 0x00, /* TSFlags */
509 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
510 .CoveredBySubRegs: false, /* CoveredBySubRegs */
511 .SuperClasses: R600_KC0Superclasses, .SuperClassesSize: 1,
512 .OrderFunc: nullptr
513 };
514
515 extern const TargetRegisterClass R600_KC1RegClass = {
516 .MC: &R600MCRegisterClasses[R600_KC1RegClassID],
517 .SubClassMask: R600_KC1SubClassMask,
518 .SuperRegIndices: SuperRegIdxSeqs + 4,
519 .LaneMask: LaneBitmask(0x0000000000000001),
520 .AllocationPriority: 0,
521 .GlobalPriority: false,
522 .TSFlags: 0x00, /* TSFlags */
523 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
524 .CoveredBySubRegs: false, /* CoveredBySubRegs */
525 .SuperClasses: R600_KC1Superclasses, .SuperClassesSize: 1,
526 .OrderFunc: nullptr
527 };
528
529 extern const TargetRegisterClass R600_TReg32_WRegClass = {
530 .MC: &R600MCRegisterClasses[R600_TReg32_WRegClassID],
531 .SubClassMask: R600_TReg32_WSubClassMask,
532 .SuperRegIndices: SuperRegIdxSeqs + 0,
533 .LaneMask: LaneBitmask(0x0000000000000001),
534 .AllocationPriority: 0,
535 .GlobalPriority: false,
536 .TSFlags: 0x00, /* TSFlags */
537 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
538 .CoveredBySubRegs: false, /* CoveredBySubRegs */
539 .SuperClasses: R600_TReg32_WSuperclasses, .SuperClassesSize: 2,
540 .OrderFunc: nullptr
541 };
542
543 extern const TargetRegisterClass R600_TReg32_YRegClass = {
544 .MC: &R600MCRegisterClasses[R600_TReg32_YRegClassID],
545 .SubClassMask: R600_TReg32_YSubClassMask,
546 .SuperRegIndices: SuperRegIdxSeqs + 0,
547 .LaneMask: LaneBitmask(0x0000000000000001),
548 .AllocationPriority: 0,
549 .GlobalPriority: false,
550 .TSFlags: 0x00, /* TSFlags */
551 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
552 .CoveredBySubRegs: false, /* CoveredBySubRegs */
553 .SuperClasses: R600_TReg32_YSuperclasses, .SuperClassesSize: 2,
554 .OrderFunc: nullptr
555 };
556
557 extern const TargetRegisterClass R600_TReg32_ZRegClass = {
558 .MC: &R600MCRegisterClasses[R600_TReg32_ZRegClassID],
559 .SubClassMask: R600_TReg32_ZSubClassMask,
560 .SuperRegIndices: SuperRegIdxSeqs + 0,
561 .LaneMask: LaneBitmask(0x0000000000000001),
562 .AllocationPriority: 0,
563 .GlobalPriority: false,
564 .TSFlags: 0x00, /* TSFlags */
565 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
566 .CoveredBySubRegs: false, /* CoveredBySubRegs */
567 .SuperClasses: R600_TReg32_ZSuperclasses, .SuperClassesSize: 2,
568 .OrderFunc: nullptr
569 };
570
571 extern const TargetRegisterClass R600_ArrayBaseRegClass = {
572 .MC: &R600MCRegisterClasses[R600_ArrayBaseRegClassID],
573 .SubClassMask: R600_ArrayBaseSubClassMask,
574 .SuperRegIndices: SuperRegIdxSeqs + 4,
575 .LaneMask: LaneBitmask(0x0000000000000001),
576 .AllocationPriority: 0,
577 .GlobalPriority: false,
578 .TSFlags: 0x00, /* TSFlags */
579 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
580 .CoveredBySubRegs: false, /* CoveredBySubRegs */
581 .SuperClasses: R600_ArrayBaseSuperclasses, .SuperClassesSize: 1,
582 .OrderFunc: nullptr
583 };
584
585 extern const TargetRegisterClass R600_KC0_WRegClass = {
586 .MC: &R600MCRegisterClasses[R600_KC0_WRegClassID],
587 .SubClassMask: R600_KC0_WSubClassMask,
588 .SuperRegIndices: SuperRegIdxSeqs + 4,
589 .LaneMask: LaneBitmask(0x0000000000000001),
590 .AllocationPriority: 0,
591 .GlobalPriority: false,
592 .TSFlags: 0x00, /* TSFlags */
593 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
594 .CoveredBySubRegs: false, /* CoveredBySubRegs */
595 .SuperClasses: R600_KC0_WSuperclasses, .SuperClassesSize: 2,
596 .OrderFunc: nullptr
597 };
598
599 extern const TargetRegisterClass R600_KC0_XRegClass = {
600 .MC: &R600MCRegisterClasses[R600_KC0_XRegClassID],
601 .SubClassMask: R600_KC0_XSubClassMask,
602 .SuperRegIndices: SuperRegIdxSeqs + 4,
603 .LaneMask: LaneBitmask(0x0000000000000001),
604 .AllocationPriority: 0,
605 .GlobalPriority: false,
606 .TSFlags: 0x00, /* TSFlags */
607 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
608 .CoveredBySubRegs: false, /* CoveredBySubRegs */
609 .SuperClasses: R600_KC0_XSuperclasses, .SuperClassesSize: 2,
610 .OrderFunc: nullptr
611 };
612
613 extern const TargetRegisterClass R600_KC0_YRegClass = {
614 .MC: &R600MCRegisterClasses[R600_KC0_YRegClassID],
615 .SubClassMask: R600_KC0_YSubClassMask,
616 .SuperRegIndices: SuperRegIdxSeqs + 4,
617 .LaneMask: LaneBitmask(0x0000000000000001),
618 .AllocationPriority: 0,
619 .GlobalPriority: false,
620 .TSFlags: 0x00, /* TSFlags */
621 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
622 .CoveredBySubRegs: false, /* CoveredBySubRegs */
623 .SuperClasses: R600_KC0_YSuperclasses, .SuperClassesSize: 2,
624 .OrderFunc: nullptr
625 };
626
627 extern const TargetRegisterClass R600_KC0_ZRegClass = {
628 .MC: &R600MCRegisterClasses[R600_KC0_ZRegClassID],
629 .SubClassMask: R600_KC0_ZSubClassMask,
630 .SuperRegIndices: SuperRegIdxSeqs + 4,
631 .LaneMask: LaneBitmask(0x0000000000000001),
632 .AllocationPriority: 0,
633 .GlobalPriority: false,
634 .TSFlags: 0x00, /* TSFlags */
635 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
636 .CoveredBySubRegs: false, /* CoveredBySubRegs */
637 .SuperClasses: R600_KC0_ZSuperclasses, .SuperClassesSize: 2,
638 .OrderFunc: nullptr
639 };
640
641 extern const TargetRegisterClass R600_KC1_WRegClass = {
642 .MC: &R600MCRegisterClasses[R600_KC1_WRegClassID],
643 .SubClassMask: R600_KC1_WSubClassMask,
644 .SuperRegIndices: SuperRegIdxSeqs + 4,
645 .LaneMask: LaneBitmask(0x0000000000000001),
646 .AllocationPriority: 0,
647 .GlobalPriority: false,
648 .TSFlags: 0x00, /* TSFlags */
649 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
650 .CoveredBySubRegs: false, /* CoveredBySubRegs */
651 .SuperClasses: R600_KC1_WSuperclasses, .SuperClassesSize: 2,
652 .OrderFunc: nullptr
653 };
654
655 extern const TargetRegisterClass R600_KC1_XRegClass = {
656 .MC: &R600MCRegisterClasses[R600_KC1_XRegClassID],
657 .SubClassMask: R600_KC1_XSubClassMask,
658 .SuperRegIndices: SuperRegIdxSeqs + 4,
659 .LaneMask: LaneBitmask(0x0000000000000001),
660 .AllocationPriority: 0,
661 .GlobalPriority: false,
662 .TSFlags: 0x00, /* TSFlags */
663 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
664 .CoveredBySubRegs: false, /* CoveredBySubRegs */
665 .SuperClasses: R600_KC1_XSuperclasses, .SuperClassesSize: 2,
666 .OrderFunc: nullptr
667 };
668
669 extern const TargetRegisterClass R600_KC1_YRegClass = {
670 .MC: &R600MCRegisterClasses[R600_KC1_YRegClassID],
671 .SubClassMask: R600_KC1_YSubClassMask,
672 .SuperRegIndices: SuperRegIdxSeqs + 4,
673 .LaneMask: LaneBitmask(0x0000000000000001),
674 .AllocationPriority: 0,
675 .GlobalPriority: false,
676 .TSFlags: 0x00, /* TSFlags */
677 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
678 .CoveredBySubRegs: false, /* CoveredBySubRegs */
679 .SuperClasses: R600_KC1_YSuperclasses, .SuperClassesSize: 2,
680 .OrderFunc: nullptr
681 };
682
683 extern const TargetRegisterClass R600_KC1_ZRegClass = {
684 .MC: &R600MCRegisterClasses[R600_KC1_ZRegClassID],
685 .SubClassMask: R600_KC1_ZSubClassMask,
686 .SuperRegIndices: SuperRegIdxSeqs + 4,
687 .LaneMask: LaneBitmask(0x0000000000000001),
688 .AllocationPriority: 0,
689 .GlobalPriority: false,
690 .TSFlags: 0x00, /* TSFlags */
691 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
692 .CoveredBySubRegs: false, /* CoveredBySubRegs */
693 .SuperClasses: R600_KC1_ZSuperclasses, .SuperClassesSize: 2,
694 .OrderFunc: nullptr
695 };
696
697 extern const TargetRegisterClass R600_LDS_SRC_REGRegClass = {
698 .MC: &R600MCRegisterClasses[R600_LDS_SRC_REGRegClassID],
699 .SubClassMask: R600_LDS_SRC_REGSubClassMask,
700 .SuperRegIndices: SuperRegIdxSeqs + 4,
701 .LaneMask: LaneBitmask(0x0000000000000001),
702 .AllocationPriority: 0,
703 .GlobalPriority: false,
704 .TSFlags: 0x00, /* TSFlags */
705 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
706 .CoveredBySubRegs: false, /* CoveredBySubRegs */
707 .SuperClasses: nullptr, .SuperClassesSize: 0,
708 .OrderFunc: nullptr
709 };
710
711 extern const TargetRegisterClass R600_PredicateRegClass = {
712 .MC: &R600MCRegisterClasses[R600_PredicateRegClassID],
713 .SubClassMask: R600_PredicateSubClassMask,
714 .SuperRegIndices: SuperRegIdxSeqs + 4,
715 .LaneMask: LaneBitmask(0x0000000000000001),
716 .AllocationPriority: 0,
717 .GlobalPriority: false,
718 .TSFlags: 0x00, /* TSFlags */
719 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
720 .CoveredBySubRegs: false, /* CoveredBySubRegs */
721 .SuperClasses: nullptr, .SuperClassesSize: 0,
722 .OrderFunc: nullptr
723 };
724
725 extern const TargetRegisterClass R600_Addr_WRegClass = {
726 .MC: &R600MCRegisterClasses[R600_Addr_WRegClassID],
727 .SubClassMask: R600_Addr_WSubClassMask,
728 .SuperRegIndices: SuperRegIdxSeqs + 4,
729 .LaneMask: LaneBitmask(0x0000000000000001),
730 .AllocationPriority: 0,
731 .GlobalPriority: false,
732 .TSFlags: 0x00, /* TSFlags */
733 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
734 .CoveredBySubRegs: false, /* CoveredBySubRegs */
735 .SuperClasses: nullptr, .SuperClassesSize: 0,
736 .OrderFunc: nullptr
737 };
738
739 extern const TargetRegisterClass R600_Addr_YRegClass = {
740 .MC: &R600MCRegisterClasses[R600_Addr_YRegClassID],
741 .SubClassMask: R600_Addr_YSubClassMask,
742 .SuperRegIndices: SuperRegIdxSeqs + 4,
743 .LaneMask: LaneBitmask(0x0000000000000001),
744 .AllocationPriority: 0,
745 .GlobalPriority: false,
746 .TSFlags: 0x00, /* TSFlags */
747 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
748 .CoveredBySubRegs: false, /* CoveredBySubRegs */
749 .SuperClasses: nullptr, .SuperClassesSize: 0,
750 .OrderFunc: nullptr
751 };
752
753 extern const TargetRegisterClass R600_Addr_ZRegClass = {
754 .MC: &R600MCRegisterClasses[R600_Addr_ZRegClassID],
755 .SubClassMask: R600_Addr_ZSubClassMask,
756 .SuperRegIndices: SuperRegIdxSeqs + 4,
757 .LaneMask: LaneBitmask(0x0000000000000001),
758 .AllocationPriority: 0,
759 .GlobalPriority: false,
760 .TSFlags: 0x00, /* TSFlags */
761 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
762 .CoveredBySubRegs: false, /* CoveredBySubRegs */
763 .SuperClasses: nullptr, .SuperClassesSize: 0,
764 .OrderFunc: nullptr
765 };
766
767 extern const TargetRegisterClass R600_LDS_SRC_REG_and_R600_Reg32RegClass = {
768 .MC: &R600MCRegisterClasses[R600_LDS_SRC_REG_and_R600_Reg32RegClassID],
769 .SubClassMask: R600_LDS_SRC_REG_and_R600_Reg32SubClassMask,
770 .SuperRegIndices: SuperRegIdxSeqs + 4,
771 .LaneMask: LaneBitmask(0x0000000000000001),
772 .AllocationPriority: 0,
773 .GlobalPriority: false,
774 .TSFlags: 0x00, /* TSFlags */
775 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
776 .CoveredBySubRegs: false, /* CoveredBySubRegs */
777 .SuperClasses: R600_LDS_SRC_REG_and_R600_Reg32Superclasses, .SuperClassesSize: 2,
778 .OrderFunc: nullptr
779 };
780
781 extern const TargetRegisterClass R600_Predicate_BitRegClass = {
782 .MC: &R600MCRegisterClasses[R600_Predicate_BitRegClassID],
783 .SubClassMask: R600_Predicate_BitSubClassMask,
784 .SuperRegIndices: SuperRegIdxSeqs + 4,
785 .LaneMask: LaneBitmask(0x0000000000000001),
786 .AllocationPriority: 0,
787 .GlobalPriority: false,
788 .TSFlags: 0x00, /* TSFlags */
789 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
790 .CoveredBySubRegs: false, /* CoveredBySubRegs */
791 .SuperClasses: nullptr, .SuperClassesSize: 0,
792 .OrderFunc: nullptr
793 };
794
795 extern const TargetRegisterClass R600_Reg64RegClass = {
796 .MC: &R600MCRegisterClasses[R600_Reg64RegClassID],
797 .SubClassMask: R600_Reg64SubClassMask,
798 .SuperRegIndices: SuperRegIdxSeqs + 4,
799 .LaneMask: LaneBitmask(0x0000000000000003),
800 .AllocationPriority: 0,
801 .GlobalPriority: false,
802 .TSFlags: 0x00, /* TSFlags */
803 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
804 .CoveredBySubRegs: false, /* CoveredBySubRegs */
805 .SuperClasses: nullptr, .SuperClassesSize: 0,
806 .OrderFunc: nullptr
807 };
808
809 extern const TargetRegisterClass R600_Reg64VerticalRegClass = {
810 .MC: &R600MCRegisterClasses[R600_Reg64VerticalRegClassID],
811 .SubClassMask: R600_Reg64VerticalSubClassMask,
812 .SuperRegIndices: SuperRegIdxSeqs + 4,
813 .LaneMask: LaneBitmask(0x0000000000000003),
814 .AllocationPriority: 0,
815 .GlobalPriority: false,
816 .TSFlags: 0x00, /* TSFlags */
817 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
818 .CoveredBySubRegs: false, /* CoveredBySubRegs */
819 .SuperClasses: nullptr, .SuperClassesSize: 0,
820 .OrderFunc: nullptr
821 };
822
823 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass = {
824 .MC: &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClassID],
825 .SubClassMask: R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSubClassMask,
826 .SuperRegIndices: SuperRegIdxSeqs + 4,
827 .LaneMask: LaneBitmask(0x0000000000000003),
828 .AllocationPriority: 0,
829 .GlobalPriority: false,
830 .TSFlags: 0x00, /* TSFlags */
831 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
832 .CoveredBySubRegs: false, /* CoveredBySubRegs */
833 .SuperClasses: R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSuperclasses, .SuperClassesSize: 1,
834 .OrderFunc: nullptr
835 };
836
837 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass = {
838 .MC: &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClassID],
839 .SubClassMask: R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSubClassMask,
840 .SuperRegIndices: SuperRegIdxSeqs + 4,
841 .LaneMask: LaneBitmask(0x0000000000000003),
842 .AllocationPriority: 0,
843 .GlobalPriority: false,
844 .TSFlags: 0x00, /* TSFlags */
845 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
846 .CoveredBySubRegs: false, /* CoveredBySubRegs */
847 .SuperClasses: R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSuperclasses, .SuperClassesSize: 1,
848 .OrderFunc: nullptr
849 };
850
851 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass = {
852 .MC: &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClassID],
853 .SubClassMask: R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSubClassMask,
854 .SuperRegIndices: SuperRegIdxSeqs + 4,
855 .LaneMask: LaneBitmask(0x0000000000000003),
856 .AllocationPriority: 0,
857 .GlobalPriority: false,
858 .TSFlags: 0x00, /* TSFlags */
859 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
860 .CoveredBySubRegs: false, /* CoveredBySubRegs */
861 .SuperClasses: R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSuperclasses, .SuperClassesSize: 1,
862 .OrderFunc: nullptr
863 };
864
865 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass = {
866 .MC: &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClassID],
867 .SubClassMask: R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSubClassMask,
868 .SuperRegIndices: SuperRegIdxSeqs + 4,
869 .LaneMask: LaneBitmask(0x0000000000000003),
870 .AllocationPriority: 0,
871 .GlobalPriority: false,
872 .TSFlags: 0x00, /* TSFlags */
873 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
874 .CoveredBySubRegs: false, /* CoveredBySubRegs */
875 .SuperClasses: R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSuperclasses, .SuperClassesSize: 1,
876 .OrderFunc: nullptr
877 };
878
879 extern const TargetRegisterClass R600_Reg128RegClass = {
880 .MC: &R600MCRegisterClasses[R600_Reg128RegClassID],
881 .SubClassMask: R600_Reg128SubClassMask,
882 .SuperRegIndices: SuperRegIdxSeqs + 4,
883 .LaneMask: LaneBitmask(0x000000000000000F),
884 .AllocationPriority: 0,
885 .GlobalPriority: false,
886 .TSFlags: 0x00, /* TSFlags */
887 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
888 .CoveredBySubRegs: false, /* CoveredBySubRegs */
889 .SuperClasses: nullptr, .SuperClassesSize: 0,
890 .OrderFunc: nullptr
891 };
892
893 extern const TargetRegisterClass R600_Reg128VerticalRegClass = {
894 .MC: &R600MCRegisterClasses[R600_Reg128VerticalRegClassID],
895 .SubClassMask: R600_Reg128VerticalSubClassMask,
896 .SuperRegIndices: SuperRegIdxSeqs + 4,
897 .LaneMask: LaneBitmask(0x000000000000000F),
898 .AllocationPriority: 0,
899 .GlobalPriority: false,
900 .TSFlags: 0x00, /* TSFlags */
901 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
902 .CoveredBySubRegs: false, /* CoveredBySubRegs */
903 .SuperClasses: nullptr, .SuperClassesSize: 0,
904 .OrderFunc: nullptr
905 };
906
907 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass = {
908 .MC: &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClassID],
909 .SubClassMask: R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSubClassMask,
910 .SuperRegIndices: SuperRegIdxSeqs + 4,
911 .LaneMask: LaneBitmask(0x000000000000000F),
912 .AllocationPriority: 0,
913 .GlobalPriority: false,
914 .TSFlags: 0x00, /* TSFlags */
915 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
916 .CoveredBySubRegs: false, /* CoveredBySubRegs */
917 .SuperClasses: R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSuperclasses, .SuperClassesSize: 1,
918 .OrderFunc: nullptr
919 };
920
921 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass = {
922 .MC: &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClassID],
923 .SubClassMask: R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSubClassMask,
924 .SuperRegIndices: SuperRegIdxSeqs + 4,
925 .LaneMask: LaneBitmask(0x000000000000000F),
926 .AllocationPriority: 0,
927 .GlobalPriority: false,
928 .TSFlags: 0x00, /* TSFlags */
929 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
930 .CoveredBySubRegs: false, /* CoveredBySubRegs */
931 .SuperClasses: R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSuperclasses, .SuperClassesSize: 1,
932 .OrderFunc: nullptr
933 };
934
935 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass = {
936 .MC: &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClassID],
937 .SubClassMask: R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSubClassMask,
938 .SuperRegIndices: SuperRegIdxSeqs + 4,
939 .LaneMask: LaneBitmask(0x000000000000000F),
940 .AllocationPriority: 0,
941 .GlobalPriority: false,
942 .TSFlags: 0x00, /* TSFlags */
943 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
944 .CoveredBySubRegs: false, /* CoveredBySubRegs */
945 .SuperClasses: R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSuperclasses, .SuperClassesSize: 1,
946 .OrderFunc: nullptr
947 };
948
949 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass = {
950 .MC: &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClassID],
951 .SubClassMask: R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSubClassMask,
952 .SuperRegIndices: SuperRegIdxSeqs + 4,
953 .LaneMask: LaneBitmask(0x000000000000000F),
954 .AllocationPriority: 0,
955 .GlobalPriority: false,
956 .TSFlags: 0x00, /* TSFlags */
957 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
958 .CoveredBySubRegs: false, /* CoveredBySubRegs */
959 .SuperClasses: R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSuperclasses, .SuperClassesSize: 1,
960 .OrderFunc: nullptr
961 };
962
963
964} // namespace R600
965static const TargetRegisterClass *const R600RegisterClasses[] = {
966 &R600::R600_Reg32RegClass,
967 &R600::R600_TReg32RegClass,
968 &R600::R600_TReg32_XRegClass,
969 &R600::R600_AddrRegClass,
970 &R600::R600_KC0RegClass,
971 &R600::R600_KC1RegClass,
972 &R600::R600_TReg32_WRegClass,
973 &R600::R600_TReg32_YRegClass,
974 &R600::R600_TReg32_ZRegClass,
975 &R600::R600_ArrayBaseRegClass,
976 &R600::R600_KC0_WRegClass,
977 &R600::R600_KC0_XRegClass,
978 &R600::R600_KC0_YRegClass,
979 &R600::R600_KC0_ZRegClass,
980 &R600::R600_KC1_WRegClass,
981 &R600::R600_KC1_XRegClass,
982 &R600::R600_KC1_YRegClass,
983 &R600::R600_KC1_ZRegClass,
984 &R600::R600_LDS_SRC_REGRegClass,
985 &R600::R600_PredicateRegClass,
986 &R600::R600_Addr_WRegClass,
987 &R600::R600_Addr_YRegClass,
988 &R600::R600_Addr_ZRegClass,
989 &R600::R600_LDS_SRC_REG_and_R600_Reg32RegClass,
990 &R600::R600_Predicate_BitRegClass,
991 &R600::R600_Reg64RegClass,
992 &R600::R600_Reg64VerticalRegClass,
993 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass,
994 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass,
995 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass,
996 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass,
997 &R600::R600_Reg128RegClass,
998 &R600::R600_Reg128VerticalRegClass,
999 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass,
1000 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass,
1001 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass,
1002 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass,
1003 };
1004
1005static const uint8_t R600CostPerUseTable[] = {
10060, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1007
1008
1009static const bool R600InAllocatableClassTable[] = {
1010false, true, false, true, false, false, true, true, true, true, false, false, true, true, true, true, false, true, false, false, true, true, true, true, false, false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1011
1012
1013static const TargetRegisterInfoDesc R600RegInfoDesc = { // Extra Descriptors
1014.CostPerUse: R600CostPerUseTable, .NumCosts: 1, .InAllocatableClass: R600InAllocatableClassTable};
1015
1016unsigned R600GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1017 static const uint8_t Rows[1][16] = {
1018 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1019 };
1020
1021 --IdxA; assert(IdxA < 16); (void) IdxA;
1022 --IdxB; assert(IdxB < 16);
1023 return Rows[0][IdxB];
1024}
1025
1026unsigned R600GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1027 static const uint8_t Table[16][16] = {
1028 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1029 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1030 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1031 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1032 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1033 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1034 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1035 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1036 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1037 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1038 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1042 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1043 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1044 };
1045
1046 --IdxA; assert(IdxA < 16);
1047 --IdxB; assert(IdxB < 16);
1048 return Table[IdxA][IdxB];
1049 }
1050
1051 struct MaskRolOp {
1052 LaneBitmask Mask;
1053 uint8_t RotateLeft;
1054 };
1055 static const MaskRolOp LaneMaskComposeSequences[] = {
1056 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
1057 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
1058 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
1059 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
1060 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
1061 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
1062 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 12
1063 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 7 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 14
1064 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 8 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 16
1065 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 9 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 18
1066 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 10 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 20
1067 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 11 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 22
1068 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 12 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 24
1069 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 13 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 26
1070 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 14 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 28
1071 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 15 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 30
1072 };
1073 static const uint8_t CompositeSequences[] = {
1074 0, // to sub0
1075 2, // to sub1
1076 4, // to sub2
1077 6, // to sub3
1078 8, // to sub4
1079 10, // to sub5
1080 12, // to sub6
1081 14, // to sub7
1082 16, // to sub8
1083 18, // to sub9
1084 20, // to sub10
1085 22, // to sub11
1086 24, // to sub12
1087 26, // to sub13
1088 28, // to sub14
1089 30 // to sub15
1090 };
1091
1092LaneBitmask R600GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1093 --IdxA; assert(IdxA < 16 && "Subregister index out of bounds");
1094 LaneBitmask Result;
1095 for (const MaskRolOp *Ops =
1096 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1097 Ops->Mask.any(); ++Ops) {
1098 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1099 if (unsigned S = Ops->RotateLeft)
1100 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1101 else
1102 Result |= LaneBitmask(M);
1103 }
1104 return Result;
1105}
1106
1107LaneBitmask R600GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1108 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
1109 --IdxA; assert(IdxA < 16 && "Subregister index out of bounds");
1110 LaneBitmask Result;
1111 for (const MaskRolOp *Ops =
1112 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1113 Ops->Mask.any(); ++Ops) {
1114 LaneBitmask::Type M = LaneMask.getAsInteger();
1115 if (unsigned S = Ops->RotateLeft)
1116 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1117 else
1118 Result |= LaneBitmask(M);
1119 }
1120 return Result;
1121}
1122
1123const TargetRegisterClass *R600GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1124 static constexpr uint8_t Table[37][16] = {
1125 { // R600_Reg32
1126 0, // sub0
1127 0, // sub1
1128 0, // sub2
1129 0, // sub3
1130 0, // sub4
1131 0, // sub5
1132 0, // sub6
1133 0, // sub7
1134 0, // sub8
1135 0, // sub9
1136 0, // sub10
1137 0, // sub11
1138 0, // sub12
1139 0, // sub13
1140 0, // sub14
1141 0, // sub15
1142 },
1143 { // R600_TReg32
1144 0, // sub0
1145 0, // sub1
1146 0, // sub2
1147 0, // sub3
1148 0, // sub4
1149 0, // sub5
1150 0, // sub6
1151 0, // sub7
1152 0, // sub8
1153 0, // sub9
1154 0, // sub10
1155 0, // sub11
1156 0, // sub12
1157 0, // sub13
1158 0, // sub14
1159 0, // sub15
1160 },
1161 { // R600_TReg32_X
1162 0, // sub0
1163 0, // sub1
1164 0, // sub2
1165 0, // sub3
1166 0, // sub4
1167 0, // sub5
1168 0, // sub6
1169 0, // sub7
1170 0, // sub8
1171 0, // sub9
1172 0, // sub10
1173 0, // sub11
1174 0, // sub12
1175 0, // sub13
1176 0, // sub14
1177 0, // sub15
1178 },
1179 { // R600_Addr
1180 0, // sub0
1181 0, // sub1
1182 0, // sub2
1183 0, // sub3
1184 0, // sub4
1185 0, // sub5
1186 0, // sub6
1187 0, // sub7
1188 0, // sub8
1189 0, // sub9
1190 0, // sub10
1191 0, // sub11
1192 0, // sub12
1193 0, // sub13
1194 0, // sub14
1195 0, // sub15
1196 },
1197 { // R600_KC0
1198 0, // sub0
1199 0, // sub1
1200 0, // sub2
1201 0, // sub3
1202 0, // sub4
1203 0, // sub5
1204 0, // sub6
1205 0, // sub7
1206 0, // sub8
1207 0, // sub9
1208 0, // sub10
1209 0, // sub11
1210 0, // sub12
1211 0, // sub13
1212 0, // sub14
1213 0, // sub15
1214 },
1215 { // R600_KC1
1216 0, // sub0
1217 0, // sub1
1218 0, // sub2
1219 0, // sub3
1220 0, // sub4
1221 0, // sub5
1222 0, // sub6
1223 0, // sub7
1224 0, // sub8
1225 0, // sub9
1226 0, // sub10
1227 0, // sub11
1228 0, // sub12
1229 0, // sub13
1230 0, // sub14
1231 0, // sub15
1232 },
1233 { // R600_TReg32_W
1234 0, // sub0
1235 0, // sub1
1236 0, // sub2
1237 0, // sub3
1238 0, // sub4
1239 0, // sub5
1240 0, // sub6
1241 0, // sub7
1242 0, // sub8
1243 0, // sub9
1244 0, // sub10
1245 0, // sub11
1246 0, // sub12
1247 0, // sub13
1248 0, // sub14
1249 0, // sub15
1250 },
1251 { // R600_TReg32_Y
1252 0, // sub0
1253 0, // sub1
1254 0, // sub2
1255 0, // sub3
1256 0, // sub4
1257 0, // sub5
1258 0, // sub6
1259 0, // sub7
1260 0, // sub8
1261 0, // sub9
1262 0, // sub10
1263 0, // sub11
1264 0, // sub12
1265 0, // sub13
1266 0, // sub14
1267 0, // sub15
1268 },
1269 { // R600_TReg32_Z
1270 0, // sub0
1271 0, // sub1
1272 0, // sub2
1273 0, // sub3
1274 0, // sub4
1275 0, // sub5
1276 0, // sub6
1277 0, // sub7
1278 0, // sub8
1279 0, // sub9
1280 0, // sub10
1281 0, // sub11
1282 0, // sub12
1283 0, // sub13
1284 0, // sub14
1285 0, // sub15
1286 },
1287 { // R600_ArrayBase
1288 0, // sub0
1289 0, // sub1
1290 0, // sub2
1291 0, // sub3
1292 0, // sub4
1293 0, // sub5
1294 0, // sub6
1295 0, // sub7
1296 0, // sub8
1297 0, // sub9
1298 0, // sub10
1299 0, // sub11
1300 0, // sub12
1301 0, // sub13
1302 0, // sub14
1303 0, // sub15
1304 },
1305 { // R600_KC0_W
1306 0, // sub0
1307 0, // sub1
1308 0, // sub2
1309 0, // sub3
1310 0, // sub4
1311 0, // sub5
1312 0, // sub6
1313 0, // sub7
1314 0, // sub8
1315 0, // sub9
1316 0, // sub10
1317 0, // sub11
1318 0, // sub12
1319 0, // sub13
1320 0, // sub14
1321 0, // sub15
1322 },
1323 { // R600_KC0_X
1324 0, // sub0
1325 0, // sub1
1326 0, // sub2
1327 0, // sub3
1328 0, // sub4
1329 0, // sub5
1330 0, // sub6
1331 0, // sub7
1332 0, // sub8
1333 0, // sub9
1334 0, // sub10
1335 0, // sub11
1336 0, // sub12
1337 0, // sub13
1338 0, // sub14
1339 0, // sub15
1340 },
1341 { // R600_KC0_Y
1342 0, // sub0
1343 0, // sub1
1344 0, // sub2
1345 0, // sub3
1346 0, // sub4
1347 0, // sub5
1348 0, // sub6
1349 0, // sub7
1350 0, // sub8
1351 0, // sub9
1352 0, // sub10
1353 0, // sub11
1354 0, // sub12
1355 0, // sub13
1356 0, // sub14
1357 0, // sub15
1358 },
1359 { // R600_KC0_Z
1360 0, // sub0
1361 0, // sub1
1362 0, // sub2
1363 0, // sub3
1364 0, // sub4
1365 0, // sub5
1366 0, // sub6
1367 0, // sub7
1368 0, // sub8
1369 0, // sub9
1370 0, // sub10
1371 0, // sub11
1372 0, // sub12
1373 0, // sub13
1374 0, // sub14
1375 0, // sub15
1376 },
1377 { // R600_KC1_W
1378 0, // sub0
1379 0, // sub1
1380 0, // sub2
1381 0, // sub3
1382 0, // sub4
1383 0, // sub5
1384 0, // sub6
1385 0, // sub7
1386 0, // sub8
1387 0, // sub9
1388 0, // sub10
1389 0, // sub11
1390 0, // sub12
1391 0, // sub13
1392 0, // sub14
1393 0, // sub15
1394 },
1395 { // R600_KC1_X
1396 0, // sub0
1397 0, // sub1
1398 0, // sub2
1399 0, // sub3
1400 0, // sub4
1401 0, // sub5
1402 0, // sub6
1403 0, // sub7
1404 0, // sub8
1405 0, // sub9
1406 0, // sub10
1407 0, // sub11
1408 0, // sub12
1409 0, // sub13
1410 0, // sub14
1411 0, // sub15
1412 },
1413 { // R600_KC1_Y
1414 0, // sub0
1415 0, // sub1
1416 0, // sub2
1417 0, // sub3
1418 0, // sub4
1419 0, // sub5
1420 0, // sub6
1421 0, // sub7
1422 0, // sub8
1423 0, // sub9
1424 0, // sub10
1425 0, // sub11
1426 0, // sub12
1427 0, // sub13
1428 0, // sub14
1429 0, // sub15
1430 },
1431 { // R600_KC1_Z
1432 0, // sub0
1433 0, // sub1
1434 0, // sub2
1435 0, // sub3
1436 0, // sub4
1437 0, // sub5
1438 0, // sub6
1439 0, // sub7
1440 0, // sub8
1441 0, // sub9
1442 0, // sub10
1443 0, // sub11
1444 0, // sub12
1445 0, // sub13
1446 0, // sub14
1447 0, // sub15
1448 },
1449 { // R600_LDS_SRC_REG
1450 0, // sub0
1451 0, // sub1
1452 0, // sub2
1453 0, // sub3
1454 0, // sub4
1455 0, // sub5
1456 0, // sub6
1457 0, // sub7
1458 0, // sub8
1459 0, // sub9
1460 0, // sub10
1461 0, // sub11
1462 0, // sub12
1463 0, // sub13
1464 0, // sub14
1465 0, // sub15
1466 },
1467 { // R600_Predicate
1468 0, // sub0
1469 0, // sub1
1470 0, // sub2
1471 0, // sub3
1472 0, // sub4
1473 0, // sub5
1474 0, // sub6
1475 0, // sub7
1476 0, // sub8
1477 0, // sub9
1478 0, // sub10
1479 0, // sub11
1480 0, // sub12
1481 0, // sub13
1482 0, // sub14
1483 0, // sub15
1484 },
1485 { // R600_Addr_W
1486 0, // sub0
1487 0, // sub1
1488 0, // sub2
1489 0, // sub3
1490 0, // sub4
1491 0, // sub5
1492 0, // sub6
1493 0, // sub7
1494 0, // sub8
1495 0, // sub9
1496 0, // sub10
1497 0, // sub11
1498 0, // sub12
1499 0, // sub13
1500 0, // sub14
1501 0, // sub15
1502 },
1503 { // R600_Addr_Y
1504 0, // sub0
1505 0, // sub1
1506 0, // sub2
1507 0, // sub3
1508 0, // sub4
1509 0, // sub5
1510 0, // sub6
1511 0, // sub7
1512 0, // sub8
1513 0, // sub9
1514 0, // sub10
1515 0, // sub11
1516 0, // sub12
1517 0, // sub13
1518 0, // sub14
1519 0, // sub15
1520 },
1521 { // R600_Addr_Z
1522 0, // sub0
1523 0, // sub1
1524 0, // sub2
1525 0, // sub3
1526 0, // sub4
1527 0, // sub5
1528 0, // sub6
1529 0, // sub7
1530 0, // sub8
1531 0, // sub9
1532 0, // sub10
1533 0, // sub11
1534 0, // sub12
1535 0, // sub13
1536 0, // sub14
1537 0, // sub15
1538 },
1539 { // R600_LDS_SRC_REG_and_R600_Reg32
1540 0, // sub0
1541 0, // sub1
1542 0, // sub2
1543 0, // sub3
1544 0, // sub4
1545 0, // sub5
1546 0, // sub6
1547 0, // sub7
1548 0, // sub8
1549 0, // sub9
1550 0, // sub10
1551 0, // sub11
1552 0, // sub12
1553 0, // sub13
1554 0, // sub14
1555 0, // sub15
1556 },
1557 { // R600_Predicate_Bit
1558 0, // sub0
1559 0, // sub1
1560 0, // sub2
1561 0, // sub3
1562 0, // sub4
1563 0, // sub5
1564 0, // sub6
1565 0, // sub7
1566 0, // sub8
1567 0, // sub9
1568 0, // sub10
1569 0, // sub11
1570 0, // sub12
1571 0, // sub13
1572 0, // sub14
1573 0, // sub15
1574 },
1575 { // R600_Reg64
1576 26, // sub0 -> R600_Reg64
1577 26, // sub1 -> R600_Reg64
1578 0, // sub2
1579 0, // sub3
1580 0, // sub4
1581 0, // sub5
1582 0, // sub6
1583 0, // sub7
1584 0, // sub8
1585 0, // sub9
1586 0, // sub10
1587 0, // sub11
1588 0, // sub12
1589 0, // sub13
1590 0, // sub14
1591 0, // sub15
1592 },
1593 { // R600_Reg64Vertical
1594 27, // sub0 -> R600_Reg64Vertical
1595 27, // sub1 -> R600_Reg64Vertical
1596 0, // sub2
1597 0, // sub3
1598 0, // sub4
1599 0, // sub5
1600 0, // sub6
1601 0, // sub7
1602 0, // sub8
1603 0, // sub9
1604 0, // sub10
1605 0, // sub11
1606 0, // sub12
1607 0, // sub13
1608 0, // sub14
1609 0, // sub15
1610 },
1611 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
1612 28, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
1613 28, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
1614 0, // sub2
1615 0, // sub3
1616 0, // sub4
1617 0, // sub5
1618 0, // sub6
1619 0, // sub7
1620 0, // sub8
1621 0, // sub9
1622 0, // sub10
1623 0, // sub11
1624 0, // sub12
1625 0, // sub13
1626 0, // sub14
1627 0, // sub15
1628 },
1629 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
1630 29, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
1631 29, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
1632 0, // sub2
1633 0, // sub3
1634 0, // sub4
1635 0, // sub5
1636 0, // sub6
1637 0, // sub7
1638 0, // sub8
1639 0, // sub9
1640 0, // sub10
1641 0, // sub11
1642 0, // sub12
1643 0, // sub13
1644 0, // sub14
1645 0, // sub15
1646 },
1647 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
1648 30, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
1649 30, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
1650 0, // sub2
1651 0, // sub3
1652 0, // sub4
1653 0, // sub5
1654 0, // sub6
1655 0, // sub7
1656 0, // sub8
1657 0, // sub9
1658 0, // sub10
1659 0, // sub11
1660 0, // sub12
1661 0, // sub13
1662 0, // sub14
1663 0, // sub15
1664 },
1665 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
1666 31, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
1667 31, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
1668 0, // sub2
1669 0, // sub3
1670 0, // sub4
1671 0, // sub5
1672 0, // sub6
1673 0, // sub7
1674 0, // sub8
1675 0, // sub9
1676 0, // sub10
1677 0, // sub11
1678 0, // sub12
1679 0, // sub13
1680 0, // sub14
1681 0, // sub15
1682 },
1683 { // R600_Reg128
1684 32, // sub0 -> R600_Reg128
1685 32, // sub1 -> R600_Reg128
1686 32, // sub2 -> R600_Reg128
1687 32, // sub3 -> R600_Reg128
1688 0, // sub4
1689 0, // sub5
1690 0, // sub6
1691 0, // sub7
1692 0, // sub8
1693 0, // sub9
1694 0, // sub10
1695 0, // sub11
1696 0, // sub12
1697 0, // sub13
1698 0, // sub14
1699 0, // sub15
1700 },
1701 { // R600_Reg128Vertical
1702 33, // sub0 -> R600_Reg128Vertical
1703 33, // sub1 -> R600_Reg128Vertical
1704 33, // sub2 -> R600_Reg128Vertical
1705 33, // sub3 -> R600_Reg128Vertical
1706 0, // sub4
1707 0, // sub5
1708 0, // sub6
1709 0, // sub7
1710 0, // sub8
1711 0, // sub9
1712 0, // sub10
1713 0, // sub11
1714 0, // sub12
1715 0, // sub13
1716 0, // sub14
1717 0, // sub15
1718 },
1719 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1720 34, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1721 34, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1722 34, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1723 34, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1724 0, // sub4
1725 0, // sub5
1726 0, // sub6
1727 0, // sub7
1728 0, // sub8
1729 0, // sub9
1730 0, // sub10
1731 0, // sub11
1732 0, // sub12
1733 0, // sub13
1734 0, // sub14
1735 0, // sub15
1736 },
1737 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1738 35, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1739 35, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1740 35, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1741 35, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1742 0, // sub4
1743 0, // sub5
1744 0, // sub6
1745 0, // sub7
1746 0, // sub8
1747 0, // sub9
1748 0, // sub10
1749 0, // sub11
1750 0, // sub12
1751 0, // sub13
1752 0, // sub14
1753 0, // sub15
1754 },
1755 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1756 36, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1757 36, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1758 36, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1759 36, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1760 0, // sub4
1761 0, // sub5
1762 0, // sub6
1763 0, // sub7
1764 0, // sub8
1765 0, // sub9
1766 0, // sub10
1767 0, // sub11
1768 0, // sub12
1769 0, // sub13
1770 0, // sub14
1771 0, // sub15
1772 },
1773 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1774 37, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1775 37, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1776 37, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1777 37, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1778 0, // sub4
1779 0, // sub5
1780 0, // sub6
1781 0, // sub7
1782 0, // sub8
1783 0, // sub9
1784 0, // sub10
1785 0, // sub11
1786 0, // sub12
1787 0, // sub13
1788 0, // sub14
1789 0, // sub15
1790 },
1791
1792 };
1793 assert(RC && "Missing regclass");
1794 if (!Idx) return RC;
1795 --Idx;
1796 assert(Idx < 16 && "Bad subreg");
1797 unsigned TV = Table[RC->getID()][Idx];
1798 return TV ? getRegClass(i: TV - 1) : nullptr;
1799}const TargetRegisterClass *R600GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1800 static constexpr uint8_t Table[37][16] = {
1801 { // R600_Reg32
1802 0, // R600_Reg32:sub0
1803 0, // R600_Reg32:sub1
1804 0, // R600_Reg32:sub2
1805 0, // R600_Reg32:sub3
1806 0, // R600_Reg32:sub4
1807 0, // R600_Reg32:sub5
1808 0, // R600_Reg32:sub6
1809 0, // R600_Reg32:sub7
1810 0, // R600_Reg32:sub8
1811 0, // R600_Reg32:sub9
1812 0, // R600_Reg32:sub10
1813 0, // R600_Reg32:sub11
1814 0, // R600_Reg32:sub12
1815 0, // R600_Reg32:sub13
1816 0, // R600_Reg32:sub14
1817 0, // R600_Reg32:sub15
1818 },
1819 { // R600_TReg32
1820 0, // R600_TReg32:sub0
1821 0, // R600_TReg32:sub1
1822 0, // R600_TReg32:sub2
1823 0, // R600_TReg32:sub3
1824 0, // R600_TReg32:sub4
1825 0, // R600_TReg32:sub5
1826 0, // R600_TReg32:sub6
1827 0, // R600_TReg32:sub7
1828 0, // R600_TReg32:sub8
1829 0, // R600_TReg32:sub9
1830 0, // R600_TReg32:sub10
1831 0, // R600_TReg32:sub11
1832 0, // R600_TReg32:sub12
1833 0, // R600_TReg32:sub13
1834 0, // R600_TReg32:sub14
1835 0, // R600_TReg32:sub15
1836 },
1837 { // R600_TReg32_X
1838 0, // R600_TReg32_X:sub0
1839 0, // R600_TReg32_X:sub1
1840 0, // R600_TReg32_X:sub2
1841 0, // R600_TReg32_X:sub3
1842 0, // R600_TReg32_X:sub4
1843 0, // R600_TReg32_X:sub5
1844 0, // R600_TReg32_X:sub6
1845 0, // R600_TReg32_X:sub7
1846 0, // R600_TReg32_X:sub8
1847 0, // R600_TReg32_X:sub9
1848 0, // R600_TReg32_X:sub10
1849 0, // R600_TReg32_X:sub11
1850 0, // R600_TReg32_X:sub12
1851 0, // R600_TReg32_X:sub13
1852 0, // R600_TReg32_X:sub14
1853 0, // R600_TReg32_X:sub15
1854 },
1855 { // R600_Addr
1856 0, // R600_Addr:sub0
1857 0, // R600_Addr:sub1
1858 0, // R600_Addr:sub2
1859 0, // R600_Addr:sub3
1860 0, // R600_Addr:sub4
1861 0, // R600_Addr:sub5
1862 0, // R600_Addr:sub6
1863 0, // R600_Addr:sub7
1864 0, // R600_Addr:sub8
1865 0, // R600_Addr:sub9
1866 0, // R600_Addr:sub10
1867 0, // R600_Addr:sub11
1868 0, // R600_Addr:sub12
1869 0, // R600_Addr:sub13
1870 0, // R600_Addr:sub14
1871 0, // R600_Addr:sub15
1872 },
1873 { // R600_KC0
1874 0, // R600_KC0:sub0
1875 0, // R600_KC0:sub1
1876 0, // R600_KC0:sub2
1877 0, // R600_KC0:sub3
1878 0, // R600_KC0:sub4
1879 0, // R600_KC0:sub5
1880 0, // R600_KC0:sub6
1881 0, // R600_KC0:sub7
1882 0, // R600_KC0:sub8
1883 0, // R600_KC0:sub9
1884 0, // R600_KC0:sub10
1885 0, // R600_KC0:sub11
1886 0, // R600_KC0:sub12
1887 0, // R600_KC0:sub13
1888 0, // R600_KC0:sub14
1889 0, // R600_KC0:sub15
1890 },
1891 { // R600_KC1
1892 0, // R600_KC1:sub0
1893 0, // R600_KC1:sub1
1894 0, // R600_KC1:sub2
1895 0, // R600_KC1:sub3
1896 0, // R600_KC1:sub4
1897 0, // R600_KC1:sub5
1898 0, // R600_KC1:sub6
1899 0, // R600_KC1:sub7
1900 0, // R600_KC1:sub8
1901 0, // R600_KC1:sub9
1902 0, // R600_KC1:sub10
1903 0, // R600_KC1:sub11
1904 0, // R600_KC1:sub12
1905 0, // R600_KC1:sub13
1906 0, // R600_KC1:sub14
1907 0, // R600_KC1:sub15
1908 },
1909 { // R600_TReg32_W
1910 0, // R600_TReg32_W:sub0
1911 0, // R600_TReg32_W:sub1
1912 0, // R600_TReg32_W:sub2
1913 0, // R600_TReg32_W:sub3
1914 0, // R600_TReg32_W:sub4
1915 0, // R600_TReg32_W:sub5
1916 0, // R600_TReg32_W:sub6
1917 0, // R600_TReg32_W:sub7
1918 0, // R600_TReg32_W:sub8
1919 0, // R600_TReg32_W:sub9
1920 0, // R600_TReg32_W:sub10
1921 0, // R600_TReg32_W:sub11
1922 0, // R600_TReg32_W:sub12
1923 0, // R600_TReg32_W:sub13
1924 0, // R600_TReg32_W:sub14
1925 0, // R600_TReg32_W:sub15
1926 },
1927 { // R600_TReg32_Y
1928 0, // R600_TReg32_Y:sub0
1929 0, // R600_TReg32_Y:sub1
1930 0, // R600_TReg32_Y:sub2
1931 0, // R600_TReg32_Y:sub3
1932 0, // R600_TReg32_Y:sub4
1933 0, // R600_TReg32_Y:sub5
1934 0, // R600_TReg32_Y:sub6
1935 0, // R600_TReg32_Y:sub7
1936 0, // R600_TReg32_Y:sub8
1937 0, // R600_TReg32_Y:sub9
1938 0, // R600_TReg32_Y:sub10
1939 0, // R600_TReg32_Y:sub11
1940 0, // R600_TReg32_Y:sub12
1941 0, // R600_TReg32_Y:sub13
1942 0, // R600_TReg32_Y:sub14
1943 0, // R600_TReg32_Y:sub15
1944 },
1945 { // R600_TReg32_Z
1946 0, // R600_TReg32_Z:sub0
1947 0, // R600_TReg32_Z:sub1
1948 0, // R600_TReg32_Z:sub2
1949 0, // R600_TReg32_Z:sub3
1950 0, // R600_TReg32_Z:sub4
1951 0, // R600_TReg32_Z:sub5
1952 0, // R600_TReg32_Z:sub6
1953 0, // R600_TReg32_Z:sub7
1954 0, // R600_TReg32_Z:sub8
1955 0, // R600_TReg32_Z:sub9
1956 0, // R600_TReg32_Z:sub10
1957 0, // R600_TReg32_Z:sub11
1958 0, // R600_TReg32_Z:sub12
1959 0, // R600_TReg32_Z:sub13
1960 0, // R600_TReg32_Z:sub14
1961 0, // R600_TReg32_Z:sub15
1962 },
1963 { // R600_ArrayBase
1964 0, // R600_ArrayBase:sub0
1965 0, // R600_ArrayBase:sub1
1966 0, // R600_ArrayBase:sub2
1967 0, // R600_ArrayBase:sub3
1968 0, // R600_ArrayBase:sub4
1969 0, // R600_ArrayBase:sub5
1970 0, // R600_ArrayBase:sub6
1971 0, // R600_ArrayBase:sub7
1972 0, // R600_ArrayBase:sub8
1973 0, // R600_ArrayBase:sub9
1974 0, // R600_ArrayBase:sub10
1975 0, // R600_ArrayBase:sub11
1976 0, // R600_ArrayBase:sub12
1977 0, // R600_ArrayBase:sub13
1978 0, // R600_ArrayBase:sub14
1979 0, // R600_ArrayBase:sub15
1980 },
1981 { // R600_KC0_W
1982 0, // R600_KC0_W:sub0
1983 0, // R600_KC0_W:sub1
1984 0, // R600_KC0_W:sub2
1985 0, // R600_KC0_W:sub3
1986 0, // R600_KC0_W:sub4
1987 0, // R600_KC0_W:sub5
1988 0, // R600_KC0_W:sub6
1989 0, // R600_KC0_W:sub7
1990 0, // R600_KC0_W:sub8
1991 0, // R600_KC0_W:sub9
1992 0, // R600_KC0_W:sub10
1993 0, // R600_KC0_W:sub11
1994 0, // R600_KC0_W:sub12
1995 0, // R600_KC0_W:sub13
1996 0, // R600_KC0_W:sub14
1997 0, // R600_KC0_W:sub15
1998 },
1999 { // R600_KC0_X
2000 0, // R600_KC0_X:sub0
2001 0, // R600_KC0_X:sub1
2002 0, // R600_KC0_X:sub2
2003 0, // R600_KC0_X:sub3
2004 0, // R600_KC0_X:sub4
2005 0, // R600_KC0_X:sub5
2006 0, // R600_KC0_X:sub6
2007 0, // R600_KC0_X:sub7
2008 0, // R600_KC0_X:sub8
2009 0, // R600_KC0_X:sub9
2010 0, // R600_KC0_X:sub10
2011 0, // R600_KC0_X:sub11
2012 0, // R600_KC0_X:sub12
2013 0, // R600_KC0_X:sub13
2014 0, // R600_KC0_X:sub14
2015 0, // R600_KC0_X:sub15
2016 },
2017 { // R600_KC0_Y
2018 0, // R600_KC0_Y:sub0
2019 0, // R600_KC0_Y:sub1
2020 0, // R600_KC0_Y:sub2
2021 0, // R600_KC0_Y:sub3
2022 0, // R600_KC0_Y:sub4
2023 0, // R600_KC0_Y:sub5
2024 0, // R600_KC0_Y:sub6
2025 0, // R600_KC0_Y:sub7
2026 0, // R600_KC0_Y:sub8
2027 0, // R600_KC0_Y:sub9
2028 0, // R600_KC0_Y:sub10
2029 0, // R600_KC0_Y:sub11
2030 0, // R600_KC0_Y:sub12
2031 0, // R600_KC0_Y:sub13
2032 0, // R600_KC0_Y:sub14
2033 0, // R600_KC0_Y:sub15
2034 },
2035 { // R600_KC0_Z
2036 0, // R600_KC0_Z:sub0
2037 0, // R600_KC0_Z:sub1
2038 0, // R600_KC0_Z:sub2
2039 0, // R600_KC0_Z:sub3
2040 0, // R600_KC0_Z:sub4
2041 0, // R600_KC0_Z:sub5
2042 0, // R600_KC0_Z:sub6
2043 0, // R600_KC0_Z:sub7
2044 0, // R600_KC0_Z:sub8
2045 0, // R600_KC0_Z:sub9
2046 0, // R600_KC0_Z:sub10
2047 0, // R600_KC0_Z:sub11
2048 0, // R600_KC0_Z:sub12
2049 0, // R600_KC0_Z:sub13
2050 0, // R600_KC0_Z:sub14
2051 0, // R600_KC0_Z:sub15
2052 },
2053 { // R600_KC1_W
2054 0, // R600_KC1_W:sub0
2055 0, // R600_KC1_W:sub1
2056 0, // R600_KC1_W:sub2
2057 0, // R600_KC1_W:sub3
2058 0, // R600_KC1_W:sub4
2059 0, // R600_KC1_W:sub5
2060 0, // R600_KC1_W:sub6
2061 0, // R600_KC1_W:sub7
2062 0, // R600_KC1_W:sub8
2063 0, // R600_KC1_W:sub9
2064 0, // R600_KC1_W:sub10
2065 0, // R600_KC1_W:sub11
2066 0, // R600_KC1_W:sub12
2067 0, // R600_KC1_W:sub13
2068 0, // R600_KC1_W:sub14
2069 0, // R600_KC1_W:sub15
2070 },
2071 { // R600_KC1_X
2072 0, // R600_KC1_X:sub0
2073 0, // R600_KC1_X:sub1
2074 0, // R600_KC1_X:sub2
2075 0, // R600_KC1_X:sub3
2076 0, // R600_KC1_X:sub4
2077 0, // R600_KC1_X:sub5
2078 0, // R600_KC1_X:sub6
2079 0, // R600_KC1_X:sub7
2080 0, // R600_KC1_X:sub8
2081 0, // R600_KC1_X:sub9
2082 0, // R600_KC1_X:sub10
2083 0, // R600_KC1_X:sub11
2084 0, // R600_KC1_X:sub12
2085 0, // R600_KC1_X:sub13
2086 0, // R600_KC1_X:sub14
2087 0, // R600_KC1_X:sub15
2088 },
2089 { // R600_KC1_Y
2090 0, // R600_KC1_Y:sub0
2091 0, // R600_KC1_Y:sub1
2092 0, // R600_KC1_Y:sub2
2093 0, // R600_KC1_Y:sub3
2094 0, // R600_KC1_Y:sub4
2095 0, // R600_KC1_Y:sub5
2096 0, // R600_KC1_Y:sub6
2097 0, // R600_KC1_Y:sub7
2098 0, // R600_KC1_Y:sub8
2099 0, // R600_KC1_Y:sub9
2100 0, // R600_KC1_Y:sub10
2101 0, // R600_KC1_Y:sub11
2102 0, // R600_KC1_Y:sub12
2103 0, // R600_KC1_Y:sub13
2104 0, // R600_KC1_Y:sub14
2105 0, // R600_KC1_Y:sub15
2106 },
2107 { // R600_KC1_Z
2108 0, // R600_KC1_Z:sub0
2109 0, // R600_KC1_Z:sub1
2110 0, // R600_KC1_Z:sub2
2111 0, // R600_KC1_Z:sub3
2112 0, // R600_KC1_Z:sub4
2113 0, // R600_KC1_Z:sub5
2114 0, // R600_KC1_Z:sub6
2115 0, // R600_KC1_Z:sub7
2116 0, // R600_KC1_Z:sub8
2117 0, // R600_KC1_Z:sub9
2118 0, // R600_KC1_Z:sub10
2119 0, // R600_KC1_Z:sub11
2120 0, // R600_KC1_Z:sub12
2121 0, // R600_KC1_Z:sub13
2122 0, // R600_KC1_Z:sub14
2123 0, // R600_KC1_Z:sub15
2124 },
2125 { // R600_LDS_SRC_REG
2126 0, // R600_LDS_SRC_REG:sub0
2127 0, // R600_LDS_SRC_REG:sub1
2128 0, // R600_LDS_SRC_REG:sub2
2129 0, // R600_LDS_SRC_REG:sub3
2130 0, // R600_LDS_SRC_REG:sub4
2131 0, // R600_LDS_SRC_REG:sub5
2132 0, // R600_LDS_SRC_REG:sub6
2133 0, // R600_LDS_SRC_REG:sub7
2134 0, // R600_LDS_SRC_REG:sub8
2135 0, // R600_LDS_SRC_REG:sub9
2136 0, // R600_LDS_SRC_REG:sub10
2137 0, // R600_LDS_SRC_REG:sub11
2138 0, // R600_LDS_SRC_REG:sub12
2139 0, // R600_LDS_SRC_REG:sub13
2140 0, // R600_LDS_SRC_REG:sub14
2141 0, // R600_LDS_SRC_REG:sub15
2142 },
2143 { // R600_Predicate
2144 0, // R600_Predicate:sub0
2145 0, // R600_Predicate:sub1
2146 0, // R600_Predicate:sub2
2147 0, // R600_Predicate:sub3
2148 0, // R600_Predicate:sub4
2149 0, // R600_Predicate:sub5
2150 0, // R600_Predicate:sub6
2151 0, // R600_Predicate:sub7
2152 0, // R600_Predicate:sub8
2153 0, // R600_Predicate:sub9
2154 0, // R600_Predicate:sub10
2155 0, // R600_Predicate:sub11
2156 0, // R600_Predicate:sub12
2157 0, // R600_Predicate:sub13
2158 0, // R600_Predicate:sub14
2159 0, // R600_Predicate:sub15
2160 },
2161 { // R600_Addr_W
2162 0, // R600_Addr_W:sub0
2163 0, // R600_Addr_W:sub1
2164 0, // R600_Addr_W:sub2
2165 0, // R600_Addr_W:sub3
2166 0, // R600_Addr_W:sub4
2167 0, // R600_Addr_W:sub5
2168 0, // R600_Addr_W:sub6
2169 0, // R600_Addr_W:sub7
2170 0, // R600_Addr_W:sub8
2171 0, // R600_Addr_W:sub9
2172 0, // R600_Addr_W:sub10
2173 0, // R600_Addr_W:sub11
2174 0, // R600_Addr_W:sub12
2175 0, // R600_Addr_W:sub13
2176 0, // R600_Addr_W:sub14
2177 0, // R600_Addr_W:sub15
2178 },
2179 { // R600_Addr_Y
2180 0, // R600_Addr_Y:sub0
2181 0, // R600_Addr_Y:sub1
2182 0, // R600_Addr_Y:sub2
2183 0, // R600_Addr_Y:sub3
2184 0, // R600_Addr_Y:sub4
2185 0, // R600_Addr_Y:sub5
2186 0, // R600_Addr_Y:sub6
2187 0, // R600_Addr_Y:sub7
2188 0, // R600_Addr_Y:sub8
2189 0, // R600_Addr_Y:sub9
2190 0, // R600_Addr_Y:sub10
2191 0, // R600_Addr_Y:sub11
2192 0, // R600_Addr_Y:sub12
2193 0, // R600_Addr_Y:sub13
2194 0, // R600_Addr_Y:sub14
2195 0, // R600_Addr_Y:sub15
2196 },
2197 { // R600_Addr_Z
2198 0, // R600_Addr_Z:sub0
2199 0, // R600_Addr_Z:sub1
2200 0, // R600_Addr_Z:sub2
2201 0, // R600_Addr_Z:sub3
2202 0, // R600_Addr_Z:sub4
2203 0, // R600_Addr_Z:sub5
2204 0, // R600_Addr_Z:sub6
2205 0, // R600_Addr_Z:sub7
2206 0, // R600_Addr_Z:sub8
2207 0, // R600_Addr_Z:sub9
2208 0, // R600_Addr_Z:sub10
2209 0, // R600_Addr_Z:sub11
2210 0, // R600_Addr_Z:sub12
2211 0, // R600_Addr_Z:sub13
2212 0, // R600_Addr_Z:sub14
2213 0, // R600_Addr_Z:sub15
2214 },
2215 { // R600_LDS_SRC_REG_and_R600_Reg32
2216 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub0
2217 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub1
2218 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub2
2219 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub3
2220 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub4
2221 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub5
2222 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub6
2223 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub7
2224 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub8
2225 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub9
2226 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub10
2227 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub11
2228 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub12
2229 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub13
2230 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub14
2231 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub15
2232 },
2233 { // R600_Predicate_Bit
2234 0, // R600_Predicate_Bit:sub0
2235 0, // R600_Predicate_Bit:sub1
2236 0, // R600_Predicate_Bit:sub2
2237 0, // R600_Predicate_Bit:sub3
2238 0, // R600_Predicate_Bit:sub4
2239 0, // R600_Predicate_Bit:sub5
2240 0, // R600_Predicate_Bit:sub6
2241 0, // R600_Predicate_Bit:sub7
2242 0, // R600_Predicate_Bit:sub8
2243 0, // R600_Predicate_Bit:sub9
2244 0, // R600_Predicate_Bit:sub10
2245 0, // R600_Predicate_Bit:sub11
2246 0, // R600_Predicate_Bit:sub12
2247 0, // R600_Predicate_Bit:sub13
2248 0, // R600_Predicate_Bit:sub14
2249 0, // R600_Predicate_Bit:sub15
2250 },
2251 { // R600_Reg64
2252 3, // R600_Reg64:sub0 -> R600_TReg32_X
2253 8, // R600_Reg64:sub1 -> R600_TReg32_Y
2254 0, // R600_Reg64:sub2
2255 0, // R600_Reg64:sub3
2256 0, // R600_Reg64:sub4
2257 0, // R600_Reg64:sub5
2258 0, // R600_Reg64:sub6
2259 0, // R600_Reg64:sub7
2260 0, // R600_Reg64:sub8
2261 0, // R600_Reg64:sub9
2262 0, // R600_Reg64:sub10
2263 0, // R600_Reg64:sub11
2264 0, // R600_Reg64:sub12
2265 0, // R600_Reg64:sub13
2266 0, // R600_Reg64:sub14
2267 0, // R600_Reg64:sub15
2268 },
2269 { // R600_Reg64Vertical
2270 2, // R600_Reg64Vertical:sub0 -> R600_TReg32
2271 2, // R600_Reg64Vertical:sub1 -> R600_TReg32
2272 0, // R600_Reg64Vertical:sub2
2273 0, // R600_Reg64Vertical:sub3
2274 0, // R600_Reg64Vertical:sub4
2275 0, // R600_Reg64Vertical:sub5
2276 0, // R600_Reg64Vertical:sub6
2277 0, // R600_Reg64Vertical:sub7
2278 0, // R600_Reg64Vertical:sub8
2279 0, // R600_Reg64Vertical:sub9
2280 0, // R600_Reg64Vertical:sub10
2281 0, // R600_Reg64Vertical:sub11
2282 0, // R600_Reg64Vertical:sub12
2283 0, // R600_Reg64Vertical:sub13
2284 0, // R600_Reg64Vertical:sub14
2285 0, // R600_Reg64Vertical:sub15
2286 },
2287 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
2288 7, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub0 -> R600_TReg32_W
2289 7, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub1 -> R600_TReg32_W
2290 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub2
2291 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub3
2292 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub4
2293 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub5
2294 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub6
2295 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub7
2296 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub8
2297 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub9
2298 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub10
2299 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub11
2300 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub12
2301 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub13
2302 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub14
2303 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub15
2304 },
2305 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
2306 3, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub0 -> R600_TReg32_X
2307 3, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub1 -> R600_TReg32_X
2308 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub2
2309 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub3
2310 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub4
2311 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub5
2312 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub6
2313 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub7
2314 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub8
2315 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub9
2316 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub10
2317 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub11
2318 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub12
2319 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub13
2320 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub14
2321 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub15
2322 },
2323 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
2324 8, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub0 -> R600_TReg32_Y
2325 8, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub1 -> R600_TReg32_Y
2326 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub2
2327 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub3
2328 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub4
2329 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub5
2330 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub6
2331 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub7
2332 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub8
2333 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub9
2334 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub10
2335 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub11
2336 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub12
2337 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub13
2338 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub14
2339 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub15
2340 },
2341 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
2342 9, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub0 -> R600_TReg32_Z
2343 9, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub1 -> R600_TReg32_Z
2344 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub2
2345 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub3
2346 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub4
2347 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub5
2348 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub6
2349 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub7
2350 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub8
2351 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub9
2352 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub10
2353 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub11
2354 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub12
2355 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub13
2356 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub14
2357 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub15
2358 },
2359 { // R600_Reg128
2360 3, // R600_Reg128:sub0 -> R600_TReg32_X
2361 8, // R600_Reg128:sub1 -> R600_TReg32_Y
2362 9, // R600_Reg128:sub2 -> R600_TReg32_Z
2363 7, // R600_Reg128:sub3 -> R600_TReg32_W
2364 0, // R600_Reg128:sub4
2365 0, // R600_Reg128:sub5
2366 0, // R600_Reg128:sub6
2367 0, // R600_Reg128:sub7
2368 0, // R600_Reg128:sub8
2369 0, // R600_Reg128:sub9
2370 0, // R600_Reg128:sub10
2371 0, // R600_Reg128:sub11
2372 0, // R600_Reg128:sub12
2373 0, // R600_Reg128:sub13
2374 0, // R600_Reg128:sub14
2375 0, // R600_Reg128:sub15
2376 },
2377 { // R600_Reg128Vertical
2378 2, // R600_Reg128Vertical:sub0 -> R600_TReg32
2379 2, // R600_Reg128Vertical:sub1 -> R600_TReg32
2380 2, // R600_Reg128Vertical:sub2 -> R600_TReg32
2381 2, // R600_Reg128Vertical:sub3 -> R600_TReg32
2382 0, // R600_Reg128Vertical:sub4
2383 0, // R600_Reg128Vertical:sub5
2384 0, // R600_Reg128Vertical:sub6
2385 0, // R600_Reg128Vertical:sub7
2386 0, // R600_Reg128Vertical:sub8
2387 0, // R600_Reg128Vertical:sub9
2388 0, // R600_Reg128Vertical:sub10
2389 0, // R600_Reg128Vertical:sub11
2390 0, // R600_Reg128Vertical:sub12
2391 0, // R600_Reg128Vertical:sub13
2392 0, // R600_Reg128Vertical:sub14
2393 0, // R600_Reg128Vertical:sub15
2394 },
2395 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
2396 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub0 -> R600_TReg32_W
2397 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub1 -> R600_TReg32_W
2398 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub2 -> R600_TReg32_W
2399 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub3 -> R600_TReg32_W
2400 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub4
2401 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub5
2402 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub6
2403 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub7
2404 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub8
2405 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub9
2406 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub10
2407 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub11
2408 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub12
2409 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub13
2410 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub14
2411 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub15
2412 },
2413 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
2414 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub0 -> R600_TReg32_X
2415 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub1 -> R600_TReg32_X
2416 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub2 -> R600_TReg32_X
2417 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub3 -> R600_TReg32_X
2418 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub4
2419 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub5
2420 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub6
2421 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub7
2422 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub8
2423 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub9
2424 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub10
2425 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub11
2426 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub12
2427 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub13
2428 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub14
2429 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub15
2430 },
2431 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
2432 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub0 -> R600_TReg32_Y
2433 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub1 -> R600_TReg32_Y
2434 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub2 -> R600_TReg32_Y
2435 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub3 -> R600_TReg32_Y
2436 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub4
2437 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub5
2438 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub6
2439 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub7
2440 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub8
2441 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub9
2442 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub10
2443 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub11
2444 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub12
2445 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub13
2446 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub14
2447 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub15
2448 },
2449 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
2450 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub0 -> R600_TReg32_Z
2451 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub1 -> R600_TReg32_Z
2452 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub2 -> R600_TReg32_Z
2453 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub3 -> R600_TReg32_Z
2454 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub4
2455 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub5
2456 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub6
2457 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub7
2458 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub8
2459 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub9
2460 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub10
2461 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub11
2462 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub12
2463 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub13
2464 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub14
2465 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub15
2466 },
2467
2468 };
2469 assert(RC && "Missing regclass");
2470 if (!Idx) return RC;
2471 --Idx;
2472 assert(Idx < 16 && "Bad subreg");
2473 unsigned TV = Table[RC->getID()][Idx];
2474 return TV ? getRegClass(i: TV - 1) : nullptr;
2475}/// Get the weight in units of pressure for this register class.
2476const RegClassWeight &R600GenRegisterInfo::
2477getRegClassWeight(const TargetRegisterClass *RC) const {
2478 static const RegClassWeight RCWeightTable[] = {
2479 {.RegWeight: 0, .WeightLimit: 942}, // R600_Reg32
2480 {.RegWeight: 0, .WeightLimit: 513}, // R600_TReg32
2481 {.RegWeight: 0, .WeightLimit: 129}, // R600_TReg32_X
2482 {.RegWeight: 0, .WeightLimit: 128}, // R600_Addr
2483 {.RegWeight: 0, .WeightLimit: 128}, // R600_KC0
2484 {.RegWeight: 0, .WeightLimit: 128}, // R600_KC1
2485 {.RegWeight: 0, .WeightLimit: 128}, // R600_TReg32_W
2486 {.RegWeight: 0, .WeightLimit: 128}, // R600_TReg32_Y
2487 {.RegWeight: 0, .WeightLimit: 128}, // R600_TReg32_Z
2488 {.RegWeight: 0, .WeightLimit: 33}, // R600_ArrayBase
2489 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC0_W
2490 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC0_X
2491 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC0_Y
2492 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC0_Z
2493 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC1_W
2494 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC1_X
2495 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC1_Y
2496 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC1_Z
2497 {.RegWeight: 0, .WeightLimit: 1}, // R600_LDS_SRC_REG
2498 {.RegWeight: 0, .WeightLimit: 3}, // R600_Predicate
2499 {.RegWeight: 0, .WeightLimit: 0}, // R600_Addr_W
2500 {.RegWeight: 0, .WeightLimit: 0}, // R600_Addr_Y
2501 {.RegWeight: 0, .WeightLimit: 0}, // R600_Addr_Z
2502 {.RegWeight: 1, .WeightLimit: 1}, // R600_LDS_SRC_REG_and_R600_Reg32
2503 {.RegWeight: 0, .WeightLimit: 1}, // R600_Predicate_Bit
2504 {.RegWeight: 0, .WeightLimit: 128}, // R600_Reg64
2505 {.RegWeight: 0, .WeightLimit: 16}, // R600_Reg64Vertical
2506 {.RegWeight: 2, .WeightLimit: 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
2507 {.RegWeight: 2, .WeightLimit: 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
2508 {.RegWeight: 2, .WeightLimit: 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
2509 {.RegWeight: 2, .WeightLimit: 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
2510 {.RegWeight: 0, .WeightLimit: 512}, // R600_Reg128
2511 {.RegWeight: 0, .WeightLimit: 16}, // R600_Reg128Vertical
2512 {.RegWeight: 4, .WeightLimit: 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
2513 {.RegWeight: 4, .WeightLimit: 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
2514 {.RegWeight: 4, .WeightLimit: 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
2515 {.RegWeight: 4, .WeightLimit: 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
2516 };
2517 return RCWeightTable[RC->getID()];
2518}
2519
2520/// Get the weight in units of pressure for this register unit.
2521unsigned R600GenRegisterInfo::
2522getRegUnitWeight(MCRegUnit RegUnit) const {
2523 assert(static_cast<unsigned>(RegUnit) < 1342 && "invalid register unit");
2524 // All register units have unit weight.
2525 return 1;
2526}
2527
2528
2529// Get the number of dimensions of register pressure.
2530unsigned R600GenRegisterInfo::getNumRegPressureSets() const {
2531 return 23;
2532}
2533
2534// Get the name of this register unit pressure set.
2535const char *R600GenRegisterInfo::
2536getRegPressureSetName(unsigned Idx) const {
2537 static const char *PressureNameTable[] = {
2538 "R600_LDS_SRC_REG_and_R600_Reg32",
2539 "R600_Predicate_Bit",
2540 "R600_Predicate",
2541 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_W",
2542 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_X",
2543 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y",
2544 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z",
2545 "R600_Reg64Vertical",
2546 "R600_ArrayBase",
2547 "R600_TReg32_W",
2548 "R600_TReg32_Y",
2549 "R600_TReg32_Z",
2550 "R600_Reg64",
2551 "R600_TReg32_X",
2552 "R600_Reg64_with_R600_Reg64Vertical",
2553 "R600_TReg32_W_with_R600_Reg64Vertical",
2554 "R600_TReg32_Y_with_R600_Reg64Vertical",
2555 "R600_TReg32_Z_with_R600_Reg64Vertical",
2556 "R600_TReg32_X_with_R600_Reg64Vertical",
2557 "R600_TReg32_Y_with_R600_Reg64",
2558 "R600_TReg32_X_with_R600_Reg64",
2559 "R600_TReg32",
2560 "R600_Reg32",
2561 };
2562 return PressureNameTable[Idx];
2563}
2564
2565// Get the register unit pressure limit for this dimension.
2566// This limit must be adjusted dynamically for reserved registers.
2567unsigned R600GenRegisterInfo::
2568getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2569 static const uint16_t PressureLimitTable[] = {
2570 1, // 0: R600_LDS_SRC_REG_and_R600_Reg32
2571 1, // 1: R600_Predicate_Bit
2572 3, // 2: R600_Predicate
2573 4, // 3: R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
2574 4, // 4: R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
2575 4, // 5: R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
2576 4, // 6: R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
2577 16, // 7: R600_Reg64Vertical
2578 33, // 8: R600_ArrayBase
2579 128, // 9: R600_TReg32_W
2580 128, // 10: R600_TReg32_Y
2581 128, // 11: R600_TReg32_Z
2582 128, // 12: R600_Reg64
2583 129, // 13: R600_TReg32_X
2584 136, // 14: R600_Reg64_with_R600_Reg64Vertical
2585 140, // 15: R600_TReg32_W_with_R600_Reg64Vertical
2586 140, // 16: R600_TReg32_Y_with_R600_Reg64Vertical
2587 140, // 17: R600_TReg32_Z_with_R600_Reg64Vertical
2588 141, // 18: R600_TReg32_X_with_R600_Reg64Vertical
2589 192, // 19: R600_TReg32_Y_with_R600_Reg64
2590 193, // 20: R600_TReg32_X_with_R600_Reg64
2591 513, // 21: R600_TReg32
2592 942, // 22: R600_Reg32
2593 };
2594 return PressureLimitTable[Idx];
2595}
2596
2597/// Table of pressure sets per register class or unit.
2598static const int RCSetsTable[] = {
2599 /* 0 */ 1, -1,
2600 /* 2 */ 2, -1,
2601 /* 4 */ 0, 22, -1,
2602 /* 7 */ 8, 22, -1,
2603 /* 10 */ 9, 15, 21, 22, -1,
2604 /* 15 */ 11, 17, 21, 22, -1,
2605 /* 20 */ 7, 14, 15, 16, 17, 18, 21, 22, -1,
2606 /* 29 */ 3, 7, 9, 14, 15, 16, 17, 18, 21, 22, -1,
2607 /* 40 */ 6, 7, 11, 14, 15, 16, 17, 18, 21, 22, -1,
2608 /* 51 */ 10, 16, 19, 21, 22, -1,
2609 /* 57 */ 13, 18, 20, 21, 22, -1,
2610 /* 63 */ 12, 14, 19, 20, 21, 22, -1,
2611 /* 70 */ 10, 12, 14, 16, 19, 20, 21, 22, -1,
2612 /* 79 */ 12, 13, 14, 18, 19, 20, 21, 22, -1,
2613 /* 88 */ 5, 7, 10, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1,
2614 /* 102 */ 4, 7, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1,
2615};
2616
2617/// Get the dimensions of register pressure impacted by this register class.
2618/// Returns a -1 terminated array of pressure set IDs
2619const int *R600GenRegisterInfo::
2620getRegClassPressureSets(const TargetRegisterClass *RC) const {
2621 static const uint8_t RCSetStartTable[] = {
2622 5,12,57,1,1,1,10,51,15,7,1,1,1,1,1,1,1,1,1,2,1,1,1,4,0,63,20,29,102,88,40,12,20,29,102,88,40,};
2623 return &RCSetsTable[RCSetStartTable[RC->getID()]];
2624}
2625
2626/// Get the dimensions of register pressure impacted by this register unit.
2627/// Returns a -1 terminated array of pressure set IDs
2628const int *R600GenRegisterInfo::
2629getRegUnitPressureSets(MCRegUnit RegUnit) const {
2630 assert(static_cast<unsigned>(RegUnit) < 1342 && "invalid register unit");
2631 static const uint8_t RUSetStartTable[] = {
2632 5,1,5,1,1,5,57,5,5,1,1,5,5,5,5,1,4,1,1,0,2,2,2,1,1,5,1,1,5,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,29,29,29,29,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,102,102,102,102,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,88,88,88,88,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,40,40,40,40,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,};
2633 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
2634}
2635
2636extern const MCRegisterDesc R600RegDesc[];
2637extern const int16_t R600RegDiffLists[];
2638extern const LaneBitmask R600LaneMaskLists[];
2639extern const char R600RegStrings[];
2640extern const char R600RegClassStrings[];
2641extern const MCPhysReg R600RegUnitRoots[][2];
2642extern const uint16_t R600SubRegIdxLists[];
2643extern const uint16_t R600RegEncodingTable[];
2644
2645R600GenRegisterInfo::
2646R600GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2647 unsigned PC, unsigned HwMode)
2648 : TargetRegisterInfo(&R600RegInfoDesc, R600RegisterClasses,
2649 R600SubRegIndexStrings, R600SubRegIndexNameOffsets,
2650 R600SubRegIdxRangeTable, R600SubRegIndexLaneMaskTable,
2651
2652 LaneBitmask(0xFFFFFFFFFFFFFFF0), R600RegClassInfos, R600VTLists, HwMode) {
2653 InitMCRegisterInfo(D: R600RegDesc, NR: 1675, RA, PC,
2654 C: R600MCRegisterClasses, NC: 37, RURoots: R600RegUnitRoots, NRU: 1342, DL: R600RegDiffLists,
2655 RUMS: R600LaneMaskLists, Strings: R600RegStrings, ClassStrings: R600RegClassStrings, SubIndices: R600SubRegIdxLists, NumIndices: 17,
2656 RET: R600RegEncodingTable, RUI: nullptr);
2657
2658}
2659
2660
2661
2662ArrayRef<const uint32_t *> R600GenRegisterInfo::getRegMasks() const {
2663 return {};
2664}
2665
2666bool R600GenRegisterInfo::
2667isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2668 return
2669 false;
2670}
2671
2672bool R600GenRegisterInfo::
2673isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
2674 return
2675 false;
2676}
2677
2678bool R600GenRegisterInfo::
2679isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2680 return
2681 false;
2682}
2683
2684bool R600GenRegisterInfo::
2685isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2686 return
2687 false;
2688}
2689
2690bool R600GenRegisterInfo::
2691isConstantPhysReg(MCRegister PhysReg) const {
2692 return
2693 false;
2694}
2695
2696ArrayRef<const char *> R600GenRegisterInfo::getRegMaskNames() const {
2697 return {};
2698}
2699
2700const R600FrameLowering *
2701R600GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2702 return static_cast<const R600FrameLowering *>(
2703 MF.getSubtarget().getFrameLowering());
2704}
2705
2706
2707} // namespace llvm
2708