1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass R600MCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::f32, MVT::i32, MVT::Other,
15 /* 3 */ MVT::v2f32, MVT::v2i32, MVT::i64, MVT::f64, MVT::Other,
16 /* 8 */ MVT::v2f32, MVT::v2i32, MVT::Other,
17 /* 11 */ MVT::v4f32, MVT::v4i32, MVT::Other,
18};
19
20static const char *SubRegIndexNameTable[] = { "sub0", "sub1", "sub2", "sub3", "sub4", "sub5", "sub6", "sub7", "sub8", "sub9", "sub10", "sub11", "sub12", "sub13", "sub14", "sub15", "" };
21
22static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
23 { .Offset: 65535, .Size: 65535 },
24 { .Offset: 0, .Size: 32 }, // sub0
25 { .Offset: 32, .Size: 32 }, // sub1
26 { .Offset: 64, .Size: 32 }, // sub2
27 { .Offset: 96, .Size: 32 }, // sub3
28 { .Offset: 128, .Size: 32 }, // sub4
29 { .Offset: 160, .Size: 32 }, // sub5
30 { .Offset: 192, .Size: 32 }, // sub6
31 { .Offset: 224, .Size: 32 }, // sub7
32 { .Offset: 256, .Size: 32 }, // sub8
33 { .Offset: 288, .Size: 32 }, // sub9
34 { .Offset: 320, .Size: 32 }, // sub10
35 { .Offset: 352, .Size: 32 }, // sub11
36 { .Offset: 384, .Size: 32 }, // sub12
37 { .Offset: 416, .Size: 32 }, // sub13
38 { .Offset: 448, .Size: 32 }, // sub14
39 { .Offset: 480, .Size: 32 }, // sub15
40};
41
42
43static const LaneBitmask SubRegIndexLaneMaskTable[] = {
44 LaneBitmask::getAll(),
45 LaneBitmask(0x0000000000000001), // sub0
46 LaneBitmask(0x0000000000000002), // sub1
47 LaneBitmask(0x0000000000000004), // sub2
48 LaneBitmask(0x0000000000000008), // sub3
49 LaneBitmask(0x0000000000000010), // sub4
50 LaneBitmask(0x0000000000000020), // sub5
51 LaneBitmask(0x0000000000000040), // sub6
52 LaneBitmask(0x0000000000000080), // sub7
53 LaneBitmask(0x0000000000000100), // sub8
54 LaneBitmask(0x0000000000000200), // sub9
55 LaneBitmask(0x0000000000000400), // sub10
56 LaneBitmask(0x0000000000000800), // sub11
57 LaneBitmask(0x0000000000001000), // sub12
58 LaneBitmask(0x0000000000002000), // sub13
59 LaneBitmask(0x0000000000004000), // sub14
60 LaneBitmask(0x0000000000008000), // sub15
61 };
62
63
64
65static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
66 // Mode = 0 (Default)
67 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_Reg32
68 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_TReg32
69 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_TReg32_X
70 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 1 }, // R600_Addr
71 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC0
72 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC1
73 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_TReg32_W
74 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_TReg32_Y
75 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_TReg32_Z
76 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_ArrayBase
77 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC0_W
78 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC0_X
79 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC0_Y
80 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC0_Z
81 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC1_W
82 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC1_X
83 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC1_Y
84 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_KC1_Z
85 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 1 }, // R600_LDS_SRC_REG
86 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 1 }, // R600_Predicate
87 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 1 }, // R600_Addr_W
88 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 1 }, // R600_Addr_Y
89 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 1 }, // R600_Addr_Z
90 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 0 }, // R600_LDS_SRC_REG_and_R600_Reg32
91 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 32, /*VTLists+*/.VTListOffset: 1 }, // R600_Predicate_Bit
92 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 3 }, // R600_Reg64
93 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical
94 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
95 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
96 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
97 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 8 }, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
98 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // R600_Reg128
99 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical
100 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
101 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
102 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
103 { .RegSize: 128, .SpillSize: 128, .SpillAlignment: 128, /*VTLists+*/.VTListOffset: 11 }, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
104};
105static const uint32_t R600_Reg32SubClassMask[] = {
106 0x0083ffff, 0x00000000,
107 0xfe000000, 0x0000001f, // sub0
108 0xfe000000, 0x0000001f, // sub1
109 0x80000000, 0x0000001f, // sub2
110 0x80000000, 0x0000001f, // sub3
111};
112
113static const uint32_t R600_TReg32SubClassMask[] = {
114 0x000001c6, 0x00000000,
115 0xfe000000, 0x0000001f, // sub0
116 0xfe000000, 0x0000001f, // sub1
117 0x80000000, 0x0000001f, // sub2
118 0x80000000, 0x0000001f, // sub3
119};
120
121static const uint32_t R600_TReg32_XSubClassMask[] = {
122 0x00000004, 0x00000000,
123 0x92000000, 0x00000004, // sub0
124 0x10000000, 0x00000004, // sub1
125 0x00000000, 0x00000004, // sub2
126 0x00000000, 0x00000004, // sub3
127};
128
129static const uint32_t R600_AddrSubClassMask[] = {
130 0x00000008, 0x00000000,
131};
132
133static const uint32_t R600_KC0SubClassMask[] = {
134 0x00003c10, 0x00000000,
135};
136
137static const uint32_t R600_KC1SubClassMask[] = {
138 0x0003c020, 0x00000000,
139};
140
141static const uint32_t R600_TReg32_WSubClassMask[] = {
142 0x00000040, 0x00000000,
143 0x08000000, 0x00000002, // sub0
144 0x08000000, 0x00000002, // sub1
145 0x00000000, 0x00000002, // sub2
146 0x80000000, 0x00000002, // sub3
147};
148
149static const uint32_t R600_TReg32_YSubClassMask[] = {
150 0x00000080, 0x00000000,
151 0x20000000, 0x00000008, // sub0
152 0xa2000000, 0x00000008, // sub1
153 0x00000000, 0x00000008, // sub2
154 0x00000000, 0x00000008, // sub3
155};
156
157static const uint32_t R600_TReg32_ZSubClassMask[] = {
158 0x00000100, 0x00000000,
159 0x40000000, 0x00000010, // sub0
160 0x40000000, 0x00000010, // sub1
161 0x80000000, 0x00000010, // sub2
162 0x00000000, 0x00000010, // sub3
163};
164
165static const uint32_t R600_ArrayBaseSubClassMask[] = {
166 0x00000200, 0x00000000,
167};
168
169static const uint32_t R600_KC0_WSubClassMask[] = {
170 0x00000400, 0x00000000,
171};
172
173static const uint32_t R600_KC0_XSubClassMask[] = {
174 0x00000800, 0x00000000,
175};
176
177static const uint32_t R600_KC0_YSubClassMask[] = {
178 0x00001000, 0x00000000,
179};
180
181static const uint32_t R600_KC0_ZSubClassMask[] = {
182 0x00002000, 0x00000000,
183};
184
185static const uint32_t R600_KC1_WSubClassMask[] = {
186 0x00004000, 0x00000000,
187};
188
189static const uint32_t R600_KC1_XSubClassMask[] = {
190 0x00008000, 0x00000000,
191};
192
193static const uint32_t R600_KC1_YSubClassMask[] = {
194 0x00010000, 0x00000000,
195};
196
197static const uint32_t R600_KC1_ZSubClassMask[] = {
198 0x00020000, 0x00000000,
199};
200
201static const uint32_t R600_LDS_SRC_REGSubClassMask[] = {
202 0x00840000, 0x00000000,
203};
204
205static const uint32_t R600_PredicateSubClassMask[] = {
206 0x00080000, 0x00000000,
207};
208
209static const uint32_t R600_Addr_WSubClassMask[] = {
210 0x00100000, 0x00000000,
211};
212
213static const uint32_t R600_Addr_YSubClassMask[] = {
214 0x00200000, 0x00000000,
215};
216
217static const uint32_t R600_Addr_ZSubClassMask[] = {
218 0x00400000, 0x00000000,
219};
220
221static const uint32_t R600_LDS_SRC_REG_and_R600_Reg32SubClassMask[] = {
222 0x00800000, 0x00000000,
223};
224
225static const uint32_t R600_Predicate_BitSubClassMask[] = {
226 0x01000000, 0x00000000,
227};
228
229static const uint32_t R600_Reg64SubClassMask[] = {
230 0x02000000, 0x00000000,
231};
232
233static const uint32_t R600_Reg64VerticalSubClassMask[] = {
234 0x7c000000, 0x00000000,
235};
236
237static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSubClassMask[] = {
238 0x08000000, 0x00000000,
239};
240
241static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSubClassMask[] = {
242 0x10000000, 0x00000000,
243};
244
245static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSubClassMask[] = {
246 0x20000000, 0x00000000,
247};
248
249static const uint32_t R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSubClassMask[] = {
250 0x40000000, 0x00000000,
251};
252
253static const uint32_t R600_Reg128SubClassMask[] = {
254 0x80000000, 0x00000000,
255};
256
257static const uint32_t R600_Reg128VerticalSubClassMask[] = {
258 0x00000000, 0x0000001f,
259};
260
261static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSubClassMask[] = {
262 0x00000000, 0x00000002,
263};
264
265static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSubClassMask[] = {
266 0x00000000, 0x00000004,
267};
268
269static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSubClassMask[] = {
270 0x00000000, 0x00000008,
271};
272
273static const uint32_t R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSubClassMask[] = {
274 0x00000000, 0x00000010,
275};
276
277static const uint16_t SuperRegIdxSeqs[] = {
278 /* 0 */ 1, 2, 3, 4, 0,
279};
280
281static unsigned const R600_TReg32Superclasses[] = {
282 R600::R600_Reg32RegClassID,
283};
284
285static unsigned const R600_TReg32_XSuperclasses[] = {
286 R600::R600_Reg32RegClassID,
287 R600::R600_TReg32RegClassID,
288};
289
290static unsigned const R600_AddrSuperclasses[] = {
291 R600::R600_Reg32RegClassID,
292};
293
294static unsigned const R600_KC0Superclasses[] = {
295 R600::R600_Reg32RegClassID,
296};
297
298static unsigned const R600_KC1Superclasses[] = {
299 R600::R600_Reg32RegClassID,
300};
301
302static unsigned const R600_TReg32_WSuperclasses[] = {
303 R600::R600_Reg32RegClassID,
304 R600::R600_TReg32RegClassID,
305};
306
307static unsigned const R600_TReg32_YSuperclasses[] = {
308 R600::R600_Reg32RegClassID,
309 R600::R600_TReg32RegClassID,
310};
311
312static unsigned const R600_TReg32_ZSuperclasses[] = {
313 R600::R600_Reg32RegClassID,
314 R600::R600_TReg32RegClassID,
315};
316
317static unsigned const R600_ArrayBaseSuperclasses[] = {
318 R600::R600_Reg32RegClassID,
319};
320
321static unsigned const R600_KC0_WSuperclasses[] = {
322 R600::R600_Reg32RegClassID,
323 R600::R600_KC0RegClassID,
324};
325
326static unsigned const R600_KC0_XSuperclasses[] = {
327 R600::R600_Reg32RegClassID,
328 R600::R600_KC0RegClassID,
329};
330
331static unsigned const R600_KC0_YSuperclasses[] = {
332 R600::R600_Reg32RegClassID,
333 R600::R600_KC0RegClassID,
334};
335
336static unsigned const R600_KC0_ZSuperclasses[] = {
337 R600::R600_Reg32RegClassID,
338 R600::R600_KC0RegClassID,
339};
340
341static unsigned const R600_KC1_WSuperclasses[] = {
342 R600::R600_Reg32RegClassID,
343 R600::R600_KC1RegClassID,
344};
345
346static unsigned const R600_KC1_XSuperclasses[] = {
347 R600::R600_Reg32RegClassID,
348 R600::R600_KC1RegClassID,
349};
350
351static unsigned const R600_KC1_YSuperclasses[] = {
352 R600::R600_Reg32RegClassID,
353 R600::R600_KC1RegClassID,
354};
355
356static unsigned const R600_KC1_ZSuperclasses[] = {
357 R600::R600_Reg32RegClassID,
358 R600::R600_KC1RegClassID,
359};
360
361static unsigned const R600_LDS_SRC_REG_and_R600_Reg32Superclasses[] = {
362 R600::R600_Reg32RegClassID,
363 R600::R600_LDS_SRC_REGRegClassID,
364};
365
366static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = {
367 R600::R600_Reg64VerticalRegClassID,
368};
369
370static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = {
371 R600::R600_Reg64VerticalRegClassID,
372};
373
374static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = {
375 R600::R600_Reg64VerticalRegClassID,
376};
377
378static unsigned const R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = {
379 R600::R600_Reg64VerticalRegClassID,
380};
381
382static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = {
383 R600::R600_Reg128VerticalRegClassID,
384};
385
386static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = {
387 R600::R600_Reg128VerticalRegClassID,
388};
389
390static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = {
391 R600::R600_Reg128VerticalRegClassID,
392};
393
394static unsigned const R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = {
395 R600::R600_Reg128VerticalRegClassID,
396};
397
398
399namespace R600 { // Register class instances
400 extern const TargetRegisterClass R600_Reg32RegClass = {
401 .MC: &R600MCRegisterClasses[R600_Reg32RegClassID],
402 .SubClassMask: R600_Reg32SubClassMask,
403 .SuperRegIndices: SuperRegIdxSeqs + 0,
404 .LaneMask: LaneBitmask(0x0000000000000001),
405 .AllocationPriority: 0,
406 .GlobalPriority: false,
407 .TSFlags: 0x00, /* TSFlags */
408 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
409 .CoveredBySubRegs: false, /* CoveredBySubRegs */
410 .SuperClasses: nullptr, .SuperClassesSize: 0,
411 .OrderFunc: nullptr
412 };
413
414 extern const TargetRegisterClass R600_TReg32RegClass = {
415 .MC: &R600MCRegisterClasses[R600_TReg32RegClassID],
416 .SubClassMask: R600_TReg32SubClassMask,
417 .SuperRegIndices: SuperRegIdxSeqs + 0,
418 .LaneMask: LaneBitmask(0x0000000000000001),
419 .AllocationPriority: 0,
420 .GlobalPriority: false,
421 .TSFlags: 0x00, /* TSFlags */
422 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
423 .CoveredBySubRegs: false, /* CoveredBySubRegs */
424 .SuperClasses: R600_TReg32Superclasses, .SuperClassesSize: 1,
425 .OrderFunc: nullptr
426 };
427
428 extern const TargetRegisterClass R600_TReg32_XRegClass = {
429 .MC: &R600MCRegisterClasses[R600_TReg32_XRegClassID],
430 .SubClassMask: R600_TReg32_XSubClassMask,
431 .SuperRegIndices: SuperRegIdxSeqs + 0,
432 .LaneMask: LaneBitmask(0x0000000000000001),
433 .AllocationPriority: 0,
434 .GlobalPriority: false,
435 .TSFlags: 0x00, /* TSFlags */
436 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
437 .CoveredBySubRegs: false, /* CoveredBySubRegs */
438 .SuperClasses: R600_TReg32_XSuperclasses, .SuperClassesSize: 2,
439 .OrderFunc: nullptr
440 };
441
442 extern const TargetRegisterClass R600_AddrRegClass = {
443 .MC: &R600MCRegisterClasses[R600_AddrRegClassID],
444 .SubClassMask: R600_AddrSubClassMask,
445 .SuperRegIndices: SuperRegIdxSeqs + 4,
446 .LaneMask: LaneBitmask(0x0000000000000001),
447 .AllocationPriority: 0,
448 .GlobalPriority: false,
449 .TSFlags: 0x00, /* TSFlags */
450 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
451 .CoveredBySubRegs: false, /* CoveredBySubRegs */
452 .SuperClasses: R600_AddrSuperclasses, .SuperClassesSize: 1,
453 .OrderFunc: nullptr
454 };
455
456 extern const TargetRegisterClass R600_KC0RegClass = {
457 .MC: &R600MCRegisterClasses[R600_KC0RegClassID],
458 .SubClassMask: R600_KC0SubClassMask,
459 .SuperRegIndices: SuperRegIdxSeqs + 4,
460 .LaneMask: LaneBitmask(0x0000000000000001),
461 .AllocationPriority: 0,
462 .GlobalPriority: false,
463 .TSFlags: 0x00, /* TSFlags */
464 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
465 .CoveredBySubRegs: false, /* CoveredBySubRegs */
466 .SuperClasses: R600_KC0Superclasses, .SuperClassesSize: 1,
467 .OrderFunc: nullptr
468 };
469
470 extern const TargetRegisterClass R600_KC1RegClass = {
471 .MC: &R600MCRegisterClasses[R600_KC1RegClassID],
472 .SubClassMask: R600_KC1SubClassMask,
473 .SuperRegIndices: SuperRegIdxSeqs + 4,
474 .LaneMask: LaneBitmask(0x0000000000000001),
475 .AllocationPriority: 0,
476 .GlobalPriority: false,
477 .TSFlags: 0x00, /* TSFlags */
478 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
479 .CoveredBySubRegs: false, /* CoveredBySubRegs */
480 .SuperClasses: R600_KC1Superclasses, .SuperClassesSize: 1,
481 .OrderFunc: nullptr
482 };
483
484 extern const TargetRegisterClass R600_TReg32_WRegClass = {
485 .MC: &R600MCRegisterClasses[R600_TReg32_WRegClassID],
486 .SubClassMask: R600_TReg32_WSubClassMask,
487 .SuperRegIndices: SuperRegIdxSeqs + 0,
488 .LaneMask: LaneBitmask(0x0000000000000001),
489 .AllocationPriority: 0,
490 .GlobalPriority: false,
491 .TSFlags: 0x00, /* TSFlags */
492 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
493 .CoveredBySubRegs: false, /* CoveredBySubRegs */
494 .SuperClasses: R600_TReg32_WSuperclasses, .SuperClassesSize: 2,
495 .OrderFunc: nullptr
496 };
497
498 extern const TargetRegisterClass R600_TReg32_YRegClass = {
499 .MC: &R600MCRegisterClasses[R600_TReg32_YRegClassID],
500 .SubClassMask: R600_TReg32_YSubClassMask,
501 .SuperRegIndices: SuperRegIdxSeqs + 0,
502 .LaneMask: LaneBitmask(0x0000000000000001),
503 .AllocationPriority: 0,
504 .GlobalPriority: false,
505 .TSFlags: 0x00, /* TSFlags */
506 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
507 .CoveredBySubRegs: false, /* CoveredBySubRegs */
508 .SuperClasses: R600_TReg32_YSuperclasses, .SuperClassesSize: 2,
509 .OrderFunc: nullptr
510 };
511
512 extern const TargetRegisterClass R600_TReg32_ZRegClass = {
513 .MC: &R600MCRegisterClasses[R600_TReg32_ZRegClassID],
514 .SubClassMask: R600_TReg32_ZSubClassMask,
515 .SuperRegIndices: SuperRegIdxSeqs + 0,
516 .LaneMask: LaneBitmask(0x0000000000000001),
517 .AllocationPriority: 0,
518 .GlobalPriority: false,
519 .TSFlags: 0x00, /* TSFlags */
520 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
521 .CoveredBySubRegs: false, /* CoveredBySubRegs */
522 .SuperClasses: R600_TReg32_ZSuperclasses, .SuperClassesSize: 2,
523 .OrderFunc: nullptr
524 };
525
526 extern const TargetRegisterClass R600_ArrayBaseRegClass = {
527 .MC: &R600MCRegisterClasses[R600_ArrayBaseRegClassID],
528 .SubClassMask: R600_ArrayBaseSubClassMask,
529 .SuperRegIndices: SuperRegIdxSeqs + 4,
530 .LaneMask: LaneBitmask(0x0000000000000001),
531 .AllocationPriority: 0,
532 .GlobalPriority: false,
533 .TSFlags: 0x00, /* TSFlags */
534 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
535 .CoveredBySubRegs: false, /* CoveredBySubRegs */
536 .SuperClasses: R600_ArrayBaseSuperclasses, .SuperClassesSize: 1,
537 .OrderFunc: nullptr
538 };
539
540 extern const TargetRegisterClass R600_KC0_WRegClass = {
541 .MC: &R600MCRegisterClasses[R600_KC0_WRegClassID],
542 .SubClassMask: R600_KC0_WSubClassMask,
543 .SuperRegIndices: SuperRegIdxSeqs + 4,
544 .LaneMask: LaneBitmask(0x0000000000000001),
545 .AllocationPriority: 0,
546 .GlobalPriority: false,
547 .TSFlags: 0x00, /* TSFlags */
548 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
549 .CoveredBySubRegs: false, /* CoveredBySubRegs */
550 .SuperClasses: R600_KC0_WSuperclasses, .SuperClassesSize: 2,
551 .OrderFunc: nullptr
552 };
553
554 extern const TargetRegisterClass R600_KC0_XRegClass = {
555 .MC: &R600MCRegisterClasses[R600_KC0_XRegClassID],
556 .SubClassMask: R600_KC0_XSubClassMask,
557 .SuperRegIndices: SuperRegIdxSeqs + 4,
558 .LaneMask: LaneBitmask(0x0000000000000001),
559 .AllocationPriority: 0,
560 .GlobalPriority: false,
561 .TSFlags: 0x00, /* TSFlags */
562 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
563 .CoveredBySubRegs: false, /* CoveredBySubRegs */
564 .SuperClasses: R600_KC0_XSuperclasses, .SuperClassesSize: 2,
565 .OrderFunc: nullptr
566 };
567
568 extern const TargetRegisterClass R600_KC0_YRegClass = {
569 .MC: &R600MCRegisterClasses[R600_KC0_YRegClassID],
570 .SubClassMask: R600_KC0_YSubClassMask,
571 .SuperRegIndices: SuperRegIdxSeqs + 4,
572 .LaneMask: LaneBitmask(0x0000000000000001),
573 .AllocationPriority: 0,
574 .GlobalPriority: false,
575 .TSFlags: 0x00, /* TSFlags */
576 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
577 .CoveredBySubRegs: false, /* CoveredBySubRegs */
578 .SuperClasses: R600_KC0_YSuperclasses, .SuperClassesSize: 2,
579 .OrderFunc: nullptr
580 };
581
582 extern const TargetRegisterClass R600_KC0_ZRegClass = {
583 .MC: &R600MCRegisterClasses[R600_KC0_ZRegClassID],
584 .SubClassMask: R600_KC0_ZSubClassMask,
585 .SuperRegIndices: SuperRegIdxSeqs + 4,
586 .LaneMask: LaneBitmask(0x0000000000000001),
587 .AllocationPriority: 0,
588 .GlobalPriority: false,
589 .TSFlags: 0x00, /* TSFlags */
590 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
591 .CoveredBySubRegs: false, /* CoveredBySubRegs */
592 .SuperClasses: R600_KC0_ZSuperclasses, .SuperClassesSize: 2,
593 .OrderFunc: nullptr
594 };
595
596 extern const TargetRegisterClass R600_KC1_WRegClass = {
597 .MC: &R600MCRegisterClasses[R600_KC1_WRegClassID],
598 .SubClassMask: R600_KC1_WSubClassMask,
599 .SuperRegIndices: SuperRegIdxSeqs + 4,
600 .LaneMask: LaneBitmask(0x0000000000000001),
601 .AllocationPriority: 0,
602 .GlobalPriority: false,
603 .TSFlags: 0x00, /* TSFlags */
604 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
605 .CoveredBySubRegs: false, /* CoveredBySubRegs */
606 .SuperClasses: R600_KC1_WSuperclasses, .SuperClassesSize: 2,
607 .OrderFunc: nullptr
608 };
609
610 extern const TargetRegisterClass R600_KC1_XRegClass = {
611 .MC: &R600MCRegisterClasses[R600_KC1_XRegClassID],
612 .SubClassMask: R600_KC1_XSubClassMask,
613 .SuperRegIndices: SuperRegIdxSeqs + 4,
614 .LaneMask: LaneBitmask(0x0000000000000001),
615 .AllocationPriority: 0,
616 .GlobalPriority: false,
617 .TSFlags: 0x00, /* TSFlags */
618 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
619 .CoveredBySubRegs: false, /* CoveredBySubRegs */
620 .SuperClasses: R600_KC1_XSuperclasses, .SuperClassesSize: 2,
621 .OrderFunc: nullptr
622 };
623
624 extern const TargetRegisterClass R600_KC1_YRegClass = {
625 .MC: &R600MCRegisterClasses[R600_KC1_YRegClassID],
626 .SubClassMask: R600_KC1_YSubClassMask,
627 .SuperRegIndices: SuperRegIdxSeqs + 4,
628 .LaneMask: LaneBitmask(0x0000000000000001),
629 .AllocationPriority: 0,
630 .GlobalPriority: false,
631 .TSFlags: 0x00, /* TSFlags */
632 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
633 .CoveredBySubRegs: false, /* CoveredBySubRegs */
634 .SuperClasses: R600_KC1_YSuperclasses, .SuperClassesSize: 2,
635 .OrderFunc: nullptr
636 };
637
638 extern const TargetRegisterClass R600_KC1_ZRegClass = {
639 .MC: &R600MCRegisterClasses[R600_KC1_ZRegClassID],
640 .SubClassMask: R600_KC1_ZSubClassMask,
641 .SuperRegIndices: SuperRegIdxSeqs + 4,
642 .LaneMask: LaneBitmask(0x0000000000000001),
643 .AllocationPriority: 0,
644 .GlobalPriority: false,
645 .TSFlags: 0x00, /* TSFlags */
646 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
647 .CoveredBySubRegs: false, /* CoveredBySubRegs */
648 .SuperClasses: R600_KC1_ZSuperclasses, .SuperClassesSize: 2,
649 .OrderFunc: nullptr
650 };
651
652 extern const TargetRegisterClass R600_LDS_SRC_REGRegClass = {
653 .MC: &R600MCRegisterClasses[R600_LDS_SRC_REGRegClassID],
654 .SubClassMask: R600_LDS_SRC_REGSubClassMask,
655 .SuperRegIndices: SuperRegIdxSeqs + 4,
656 .LaneMask: LaneBitmask(0x0000000000000001),
657 .AllocationPriority: 0,
658 .GlobalPriority: false,
659 .TSFlags: 0x00, /* TSFlags */
660 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
661 .CoveredBySubRegs: false, /* CoveredBySubRegs */
662 .SuperClasses: nullptr, .SuperClassesSize: 0,
663 .OrderFunc: nullptr
664 };
665
666 extern const TargetRegisterClass R600_PredicateRegClass = {
667 .MC: &R600MCRegisterClasses[R600_PredicateRegClassID],
668 .SubClassMask: R600_PredicateSubClassMask,
669 .SuperRegIndices: SuperRegIdxSeqs + 4,
670 .LaneMask: LaneBitmask(0x0000000000000001),
671 .AllocationPriority: 0,
672 .GlobalPriority: false,
673 .TSFlags: 0x00, /* TSFlags */
674 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
675 .CoveredBySubRegs: false, /* CoveredBySubRegs */
676 .SuperClasses: nullptr, .SuperClassesSize: 0,
677 .OrderFunc: nullptr
678 };
679
680 extern const TargetRegisterClass R600_Addr_WRegClass = {
681 .MC: &R600MCRegisterClasses[R600_Addr_WRegClassID],
682 .SubClassMask: R600_Addr_WSubClassMask,
683 .SuperRegIndices: SuperRegIdxSeqs + 4,
684 .LaneMask: LaneBitmask(0x0000000000000001),
685 .AllocationPriority: 0,
686 .GlobalPriority: false,
687 .TSFlags: 0x00, /* TSFlags */
688 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
689 .CoveredBySubRegs: false, /* CoveredBySubRegs */
690 .SuperClasses: nullptr, .SuperClassesSize: 0,
691 .OrderFunc: nullptr
692 };
693
694 extern const TargetRegisterClass R600_Addr_YRegClass = {
695 .MC: &R600MCRegisterClasses[R600_Addr_YRegClassID],
696 .SubClassMask: R600_Addr_YSubClassMask,
697 .SuperRegIndices: SuperRegIdxSeqs + 4,
698 .LaneMask: LaneBitmask(0x0000000000000001),
699 .AllocationPriority: 0,
700 .GlobalPriority: false,
701 .TSFlags: 0x00, /* TSFlags */
702 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
703 .CoveredBySubRegs: false, /* CoveredBySubRegs */
704 .SuperClasses: nullptr, .SuperClassesSize: 0,
705 .OrderFunc: nullptr
706 };
707
708 extern const TargetRegisterClass R600_Addr_ZRegClass = {
709 .MC: &R600MCRegisterClasses[R600_Addr_ZRegClassID],
710 .SubClassMask: R600_Addr_ZSubClassMask,
711 .SuperRegIndices: SuperRegIdxSeqs + 4,
712 .LaneMask: LaneBitmask(0x0000000000000001),
713 .AllocationPriority: 0,
714 .GlobalPriority: false,
715 .TSFlags: 0x00, /* TSFlags */
716 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
717 .CoveredBySubRegs: false, /* CoveredBySubRegs */
718 .SuperClasses: nullptr, .SuperClassesSize: 0,
719 .OrderFunc: nullptr
720 };
721
722 extern const TargetRegisterClass R600_LDS_SRC_REG_and_R600_Reg32RegClass = {
723 .MC: &R600MCRegisterClasses[R600_LDS_SRC_REG_and_R600_Reg32RegClassID],
724 .SubClassMask: R600_LDS_SRC_REG_and_R600_Reg32SubClassMask,
725 .SuperRegIndices: SuperRegIdxSeqs + 4,
726 .LaneMask: LaneBitmask(0x0000000000000001),
727 .AllocationPriority: 0,
728 .GlobalPriority: false,
729 .TSFlags: 0x00, /* TSFlags */
730 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
731 .CoveredBySubRegs: false, /* CoveredBySubRegs */
732 .SuperClasses: R600_LDS_SRC_REG_and_R600_Reg32Superclasses, .SuperClassesSize: 2,
733 .OrderFunc: nullptr
734 };
735
736 extern const TargetRegisterClass R600_Predicate_BitRegClass = {
737 .MC: &R600MCRegisterClasses[R600_Predicate_BitRegClassID],
738 .SubClassMask: R600_Predicate_BitSubClassMask,
739 .SuperRegIndices: SuperRegIdxSeqs + 4,
740 .LaneMask: LaneBitmask(0x0000000000000001),
741 .AllocationPriority: 0,
742 .GlobalPriority: false,
743 .TSFlags: 0x00, /* TSFlags */
744 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
745 .CoveredBySubRegs: false, /* CoveredBySubRegs */
746 .SuperClasses: nullptr, .SuperClassesSize: 0,
747 .OrderFunc: nullptr
748 };
749
750 extern const TargetRegisterClass R600_Reg64RegClass = {
751 .MC: &R600MCRegisterClasses[R600_Reg64RegClassID],
752 .SubClassMask: R600_Reg64SubClassMask,
753 .SuperRegIndices: SuperRegIdxSeqs + 4,
754 .LaneMask: LaneBitmask(0x0000000000000003),
755 .AllocationPriority: 0,
756 .GlobalPriority: false,
757 .TSFlags: 0x00, /* TSFlags */
758 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
759 .CoveredBySubRegs: false, /* CoveredBySubRegs */
760 .SuperClasses: nullptr, .SuperClassesSize: 0,
761 .OrderFunc: nullptr
762 };
763
764 extern const TargetRegisterClass R600_Reg64VerticalRegClass = {
765 .MC: &R600MCRegisterClasses[R600_Reg64VerticalRegClassID],
766 .SubClassMask: R600_Reg64VerticalSubClassMask,
767 .SuperRegIndices: SuperRegIdxSeqs + 4,
768 .LaneMask: LaneBitmask(0x0000000000000003),
769 .AllocationPriority: 0,
770 .GlobalPriority: false,
771 .TSFlags: 0x00, /* TSFlags */
772 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
773 .CoveredBySubRegs: false, /* CoveredBySubRegs */
774 .SuperClasses: nullptr, .SuperClassesSize: 0,
775 .OrderFunc: nullptr
776 };
777
778 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass = {
779 .MC: &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClassID],
780 .SubClassMask: R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSubClassMask,
781 .SuperRegIndices: SuperRegIdxSeqs + 4,
782 .LaneMask: LaneBitmask(0x0000000000000003),
783 .AllocationPriority: 0,
784 .GlobalPriority: false,
785 .TSFlags: 0x00, /* TSFlags */
786 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
787 .CoveredBySubRegs: false, /* CoveredBySubRegs */
788 .SuperClasses: R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSuperclasses, .SuperClassesSize: 1,
789 .OrderFunc: nullptr
790 };
791
792 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass = {
793 .MC: &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClassID],
794 .SubClassMask: R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSubClassMask,
795 .SuperRegIndices: SuperRegIdxSeqs + 4,
796 .LaneMask: LaneBitmask(0x0000000000000003),
797 .AllocationPriority: 0,
798 .GlobalPriority: false,
799 .TSFlags: 0x00, /* TSFlags */
800 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
801 .CoveredBySubRegs: false, /* CoveredBySubRegs */
802 .SuperClasses: R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSuperclasses, .SuperClassesSize: 1,
803 .OrderFunc: nullptr
804 };
805
806 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass = {
807 .MC: &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClassID],
808 .SubClassMask: R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSubClassMask,
809 .SuperRegIndices: SuperRegIdxSeqs + 4,
810 .LaneMask: LaneBitmask(0x0000000000000003),
811 .AllocationPriority: 0,
812 .GlobalPriority: false,
813 .TSFlags: 0x00, /* TSFlags */
814 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
815 .CoveredBySubRegs: false, /* CoveredBySubRegs */
816 .SuperClasses: R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSuperclasses, .SuperClassesSize: 1,
817 .OrderFunc: nullptr
818 };
819
820 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass = {
821 .MC: &R600MCRegisterClasses[R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClassID],
822 .SubClassMask: R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSubClassMask,
823 .SuperRegIndices: SuperRegIdxSeqs + 4,
824 .LaneMask: LaneBitmask(0x0000000000000003),
825 .AllocationPriority: 0,
826 .GlobalPriority: false,
827 .TSFlags: 0x00, /* TSFlags */
828 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
829 .CoveredBySubRegs: false, /* CoveredBySubRegs */
830 .SuperClasses: R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSuperclasses, .SuperClassesSize: 1,
831 .OrderFunc: nullptr
832 };
833
834 extern const TargetRegisterClass R600_Reg128RegClass = {
835 .MC: &R600MCRegisterClasses[R600_Reg128RegClassID],
836 .SubClassMask: R600_Reg128SubClassMask,
837 .SuperRegIndices: SuperRegIdxSeqs + 4,
838 .LaneMask: LaneBitmask(0x000000000000000F),
839 .AllocationPriority: 0,
840 .GlobalPriority: false,
841 .TSFlags: 0x00, /* TSFlags */
842 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
843 .CoveredBySubRegs: false, /* CoveredBySubRegs */
844 .SuperClasses: nullptr, .SuperClassesSize: 0,
845 .OrderFunc: nullptr
846 };
847
848 extern const TargetRegisterClass R600_Reg128VerticalRegClass = {
849 .MC: &R600MCRegisterClasses[R600_Reg128VerticalRegClassID],
850 .SubClassMask: R600_Reg128VerticalSubClassMask,
851 .SuperRegIndices: SuperRegIdxSeqs + 4,
852 .LaneMask: LaneBitmask(0x000000000000000F),
853 .AllocationPriority: 0,
854 .GlobalPriority: false,
855 .TSFlags: 0x00, /* TSFlags */
856 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
857 .CoveredBySubRegs: false, /* CoveredBySubRegs */
858 .SuperClasses: nullptr, .SuperClassesSize: 0,
859 .OrderFunc: nullptr
860 };
861
862 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass = {
863 .MC: &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClassID],
864 .SubClassMask: R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSubClassMask,
865 .SuperRegIndices: SuperRegIdxSeqs + 4,
866 .LaneMask: LaneBitmask(0x000000000000000F),
867 .AllocationPriority: 0,
868 .GlobalPriority: false,
869 .TSFlags: 0x00, /* TSFlags */
870 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
871 .CoveredBySubRegs: false, /* CoveredBySubRegs */
872 .SuperClasses: R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSuperclasses, .SuperClassesSize: 1,
873 .OrderFunc: nullptr
874 };
875
876 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass = {
877 .MC: &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClassID],
878 .SubClassMask: R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSubClassMask,
879 .SuperRegIndices: SuperRegIdxSeqs + 4,
880 .LaneMask: LaneBitmask(0x000000000000000F),
881 .AllocationPriority: 0,
882 .GlobalPriority: false,
883 .TSFlags: 0x00, /* TSFlags */
884 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
885 .CoveredBySubRegs: false, /* CoveredBySubRegs */
886 .SuperClasses: R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSuperclasses, .SuperClassesSize: 1,
887 .OrderFunc: nullptr
888 };
889
890 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass = {
891 .MC: &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClassID],
892 .SubClassMask: R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSubClassMask,
893 .SuperRegIndices: SuperRegIdxSeqs + 4,
894 .LaneMask: LaneBitmask(0x000000000000000F),
895 .AllocationPriority: 0,
896 .GlobalPriority: false,
897 .TSFlags: 0x00, /* TSFlags */
898 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
899 .CoveredBySubRegs: false, /* CoveredBySubRegs */
900 .SuperClasses: R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSuperclasses, .SuperClassesSize: 1,
901 .OrderFunc: nullptr
902 };
903
904 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass = {
905 .MC: &R600MCRegisterClasses[R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClassID],
906 .SubClassMask: R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSubClassMask,
907 .SuperRegIndices: SuperRegIdxSeqs + 4,
908 .LaneMask: LaneBitmask(0x000000000000000F),
909 .AllocationPriority: 0,
910 .GlobalPriority: false,
911 .TSFlags: 0x00, /* TSFlags */
912 .HasDisjunctSubRegs: true, /* HasDisjunctSubRegs */
913 .CoveredBySubRegs: false, /* CoveredBySubRegs */
914 .SuperClasses: R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSuperclasses, .SuperClassesSize: 1,
915 .OrderFunc: nullptr
916 };
917
918} // end namespace R600
919
920namespace {
921 const TargetRegisterClass *const RegisterClasses[] = {
922 &R600::R600_Reg32RegClass,
923 &R600::R600_TReg32RegClass,
924 &R600::R600_TReg32_XRegClass,
925 &R600::R600_AddrRegClass,
926 &R600::R600_KC0RegClass,
927 &R600::R600_KC1RegClass,
928 &R600::R600_TReg32_WRegClass,
929 &R600::R600_TReg32_YRegClass,
930 &R600::R600_TReg32_ZRegClass,
931 &R600::R600_ArrayBaseRegClass,
932 &R600::R600_KC0_WRegClass,
933 &R600::R600_KC0_XRegClass,
934 &R600::R600_KC0_YRegClass,
935 &R600::R600_KC0_ZRegClass,
936 &R600::R600_KC1_WRegClass,
937 &R600::R600_KC1_XRegClass,
938 &R600::R600_KC1_YRegClass,
939 &R600::R600_KC1_ZRegClass,
940 &R600::R600_LDS_SRC_REGRegClass,
941 &R600::R600_PredicateRegClass,
942 &R600::R600_Addr_WRegClass,
943 &R600::R600_Addr_YRegClass,
944 &R600::R600_Addr_ZRegClass,
945 &R600::R600_LDS_SRC_REG_and_R600_Reg32RegClass,
946 &R600::R600_Predicate_BitRegClass,
947 &R600::R600_Reg64RegClass,
948 &R600::R600_Reg64VerticalRegClass,
949 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass,
950 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass,
951 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass,
952 &R600::R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass,
953 &R600::R600_Reg128RegClass,
954 &R600::R600_Reg128VerticalRegClass,
955 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass,
956 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass,
957 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass,
958 &R600::R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass,
959 };
960} // end anonymous namespace
961
962static const uint8_t CostPerUseTable[] = {
9630, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
964
965
966static const bool InAllocatableClassTable[] = {
967false, true, false, true, false, false, true, true, true, true, false, false, true, true, true, true, false, true, false, false, true, true, true, true, false, false, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
968
969
970static const TargetRegisterInfoDesc R600RegInfoDesc = { // Extra Descriptors
971.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
972
973unsigned R600GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
974 static const uint8_t Rows[1][16] = {
975 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
976 };
977
978 --IdxA; assert(IdxA < 16); (void) IdxA;
979 --IdxB; assert(IdxB < 16);
980 return Rows[0][IdxB];
981}
982
983unsigned R600GenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
984 static const uint8_t Table[16][16] = {
985 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
986 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
987 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
988 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
989 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
990 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
991 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
992 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
993 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
994 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
995 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
996 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
997 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
998 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
999 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1000 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1001 };
1002
1003 --IdxA; assert(IdxA < 16);
1004 --IdxB; assert(IdxB < 16);
1005 return Table[IdxA][IdxB];
1006 }
1007
1008 struct MaskRolOp {
1009 LaneBitmask Mask;
1010 uint8_t RotateLeft;
1011 };
1012 static const MaskRolOp LaneMaskComposeSequences[] = {
1013 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 0
1014 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 1 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 2
1015 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 2 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 4
1016 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 3 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 6
1017 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 4 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 8
1018 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 5 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 10
1019 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 6 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 12
1020 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 7 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 14
1021 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 8 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 16
1022 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 9 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 18
1023 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 10 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 20
1024 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 11 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 22
1025 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 12 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 24
1026 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 13 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 26
1027 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 14 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 }, // Sequence 28
1028 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 15 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 30
1029 };
1030 static const uint8_t CompositeSequences[] = {
1031 0, // to sub0
1032 2, // to sub1
1033 4, // to sub2
1034 6, // to sub3
1035 8, // to sub4
1036 10, // to sub5
1037 12, // to sub6
1038 14, // to sub7
1039 16, // to sub8
1040 18, // to sub9
1041 20, // to sub10
1042 22, // to sub11
1043 24, // to sub12
1044 26, // to sub13
1045 28, // to sub14
1046 30 // to sub15
1047 };
1048
1049LaneBitmask R600GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1050 --IdxA; assert(IdxA < 16 && "Subregister index out of bounds");
1051 LaneBitmask Result;
1052 for (const MaskRolOp *Ops =
1053 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1054 Ops->Mask.any(); ++Ops) {
1055 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1056 if (unsigned S = Ops->RotateLeft)
1057 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1058 else
1059 Result |= LaneBitmask(M);
1060 }
1061 return Result;
1062}
1063
1064LaneBitmask R600GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1065 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
1066 --IdxA; assert(IdxA < 16 && "Subregister index out of bounds");
1067 LaneBitmask Result;
1068 for (const MaskRolOp *Ops =
1069 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1070 Ops->Mask.any(); ++Ops) {
1071 LaneBitmask::Type M = LaneMask.getAsInteger();
1072 if (unsigned S = Ops->RotateLeft)
1073 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1074 else
1075 Result |= LaneBitmask(M);
1076 }
1077 return Result;
1078}
1079
1080const TargetRegisterClass *R600GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1081 static const uint8_t Table[37][16] = {
1082 { // R600_Reg32
1083 0, // sub0
1084 0, // sub1
1085 0, // sub2
1086 0, // sub3
1087 0, // sub4
1088 0, // sub5
1089 0, // sub6
1090 0, // sub7
1091 0, // sub8
1092 0, // sub9
1093 0, // sub10
1094 0, // sub11
1095 0, // sub12
1096 0, // sub13
1097 0, // sub14
1098 0, // sub15
1099 },
1100 { // R600_TReg32
1101 0, // sub0
1102 0, // sub1
1103 0, // sub2
1104 0, // sub3
1105 0, // sub4
1106 0, // sub5
1107 0, // sub6
1108 0, // sub7
1109 0, // sub8
1110 0, // sub9
1111 0, // sub10
1112 0, // sub11
1113 0, // sub12
1114 0, // sub13
1115 0, // sub14
1116 0, // sub15
1117 },
1118 { // R600_TReg32_X
1119 0, // sub0
1120 0, // sub1
1121 0, // sub2
1122 0, // sub3
1123 0, // sub4
1124 0, // sub5
1125 0, // sub6
1126 0, // sub7
1127 0, // sub8
1128 0, // sub9
1129 0, // sub10
1130 0, // sub11
1131 0, // sub12
1132 0, // sub13
1133 0, // sub14
1134 0, // sub15
1135 },
1136 { // R600_Addr
1137 0, // sub0
1138 0, // sub1
1139 0, // sub2
1140 0, // sub3
1141 0, // sub4
1142 0, // sub5
1143 0, // sub6
1144 0, // sub7
1145 0, // sub8
1146 0, // sub9
1147 0, // sub10
1148 0, // sub11
1149 0, // sub12
1150 0, // sub13
1151 0, // sub14
1152 0, // sub15
1153 },
1154 { // R600_KC0
1155 0, // sub0
1156 0, // sub1
1157 0, // sub2
1158 0, // sub3
1159 0, // sub4
1160 0, // sub5
1161 0, // sub6
1162 0, // sub7
1163 0, // sub8
1164 0, // sub9
1165 0, // sub10
1166 0, // sub11
1167 0, // sub12
1168 0, // sub13
1169 0, // sub14
1170 0, // sub15
1171 },
1172 { // R600_KC1
1173 0, // sub0
1174 0, // sub1
1175 0, // sub2
1176 0, // sub3
1177 0, // sub4
1178 0, // sub5
1179 0, // sub6
1180 0, // sub7
1181 0, // sub8
1182 0, // sub9
1183 0, // sub10
1184 0, // sub11
1185 0, // sub12
1186 0, // sub13
1187 0, // sub14
1188 0, // sub15
1189 },
1190 { // R600_TReg32_W
1191 0, // sub0
1192 0, // sub1
1193 0, // sub2
1194 0, // sub3
1195 0, // sub4
1196 0, // sub5
1197 0, // sub6
1198 0, // sub7
1199 0, // sub8
1200 0, // sub9
1201 0, // sub10
1202 0, // sub11
1203 0, // sub12
1204 0, // sub13
1205 0, // sub14
1206 0, // sub15
1207 },
1208 { // R600_TReg32_Y
1209 0, // sub0
1210 0, // sub1
1211 0, // sub2
1212 0, // sub3
1213 0, // sub4
1214 0, // sub5
1215 0, // sub6
1216 0, // sub7
1217 0, // sub8
1218 0, // sub9
1219 0, // sub10
1220 0, // sub11
1221 0, // sub12
1222 0, // sub13
1223 0, // sub14
1224 0, // sub15
1225 },
1226 { // R600_TReg32_Z
1227 0, // sub0
1228 0, // sub1
1229 0, // sub2
1230 0, // sub3
1231 0, // sub4
1232 0, // sub5
1233 0, // sub6
1234 0, // sub7
1235 0, // sub8
1236 0, // sub9
1237 0, // sub10
1238 0, // sub11
1239 0, // sub12
1240 0, // sub13
1241 0, // sub14
1242 0, // sub15
1243 },
1244 { // R600_ArrayBase
1245 0, // sub0
1246 0, // sub1
1247 0, // sub2
1248 0, // sub3
1249 0, // sub4
1250 0, // sub5
1251 0, // sub6
1252 0, // sub7
1253 0, // sub8
1254 0, // sub9
1255 0, // sub10
1256 0, // sub11
1257 0, // sub12
1258 0, // sub13
1259 0, // sub14
1260 0, // sub15
1261 },
1262 { // R600_KC0_W
1263 0, // sub0
1264 0, // sub1
1265 0, // sub2
1266 0, // sub3
1267 0, // sub4
1268 0, // sub5
1269 0, // sub6
1270 0, // sub7
1271 0, // sub8
1272 0, // sub9
1273 0, // sub10
1274 0, // sub11
1275 0, // sub12
1276 0, // sub13
1277 0, // sub14
1278 0, // sub15
1279 },
1280 { // R600_KC0_X
1281 0, // sub0
1282 0, // sub1
1283 0, // sub2
1284 0, // sub3
1285 0, // sub4
1286 0, // sub5
1287 0, // sub6
1288 0, // sub7
1289 0, // sub8
1290 0, // sub9
1291 0, // sub10
1292 0, // sub11
1293 0, // sub12
1294 0, // sub13
1295 0, // sub14
1296 0, // sub15
1297 },
1298 { // R600_KC0_Y
1299 0, // sub0
1300 0, // sub1
1301 0, // sub2
1302 0, // sub3
1303 0, // sub4
1304 0, // sub5
1305 0, // sub6
1306 0, // sub7
1307 0, // sub8
1308 0, // sub9
1309 0, // sub10
1310 0, // sub11
1311 0, // sub12
1312 0, // sub13
1313 0, // sub14
1314 0, // sub15
1315 },
1316 { // R600_KC0_Z
1317 0, // sub0
1318 0, // sub1
1319 0, // sub2
1320 0, // sub3
1321 0, // sub4
1322 0, // sub5
1323 0, // sub6
1324 0, // sub7
1325 0, // sub8
1326 0, // sub9
1327 0, // sub10
1328 0, // sub11
1329 0, // sub12
1330 0, // sub13
1331 0, // sub14
1332 0, // sub15
1333 },
1334 { // R600_KC1_W
1335 0, // sub0
1336 0, // sub1
1337 0, // sub2
1338 0, // sub3
1339 0, // sub4
1340 0, // sub5
1341 0, // sub6
1342 0, // sub7
1343 0, // sub8
1344 0, // sub9
1345 0, // sub10
1346 0, // sub11
1347 0, // sub12
1348 0, // sub13
1349 0, // sub14
1350 0, // sub15
1351 },
1352 { // R600_KC1_X
1353 0, // sub0
1354 0, // sub1
1355 0, // sub2
1356 0, // sub3
1357 0, // sub4
1358 0, // sub5
1359 0, // sub6
1360 0, // sub7
1361 0, // sub8
1362 0, // sub9
1363 0, // sub10
1364 0, // sub11
1365 0, // sub12
1366 0, // sub13
1367 0, // sub14
1368 0, // sub15
1369 },
1370 { // R600_KC1_Y
1371 0, // sub0
1372 0, // sub1
1373 0, // sub2
1374 0, // sub3
1375 0, // sub4
1376 0, // sub5
1377 0, // sub6
1378 0, // sub7
1379 0, // sub8
1380 0, // sub9
1381 0, // sub10
1382 0, // sub11
1383 0, // sub12
1384 0, // sub13
1385 0, // sub14
1386 0, // sub15
1387 },
1388 { // R600_KC1_Z
1389 0, // sub0
1390 0, // sub1
1391 0, // sub2
1392 0, // sub3
1393 0, // sub4
1394 0, // sub5
1395 0, // sub6
1396 0, // sub7
1397 0, // sub8
1398 0, // sub9
1399 0, // sub10
1400 0, // sub11
1401 0, // sub12
1402 0, // sub13
1403 0, // sub14
1404 0, // sub15
1405 },
1406 { // R600_LDS_SRC_REG
1407 0, // sub0
1408 0, // sub1
1409 0, // sub2
1410 0, // sub3
1411 0, // sub4
1412 0, // sub5
1413 0, // sub6
1414 0, // sub7
1415 0, // sub8
1416 0, // sub9
1417 0, // sub10
1418 0, // sub11
1419 0, // sub12
1420 0, // sub13
1421 0, // sub14
1422 0, // sub15
1423 },
1424 { // R600_Predicate
1425 0, // sub0
1426 0, // sub1
1427 0, // sub2
1428 0, // sub3
1429 0, // sub4
1430 0, // sub5
1431 0, // sub6
1432 0, // sub7
1433 0, // sub8
1434 0, // sub9
1435 0, // sub10
1436 0, // sub11
1437 0, // sub12
1438 0, // sub13
1439 0, // sub14
1440 0, // sub15
1441 },
1442 { // R600_Addr_W
1443 0, // sub0
1444 0, // sub1
1445 0, // sub2
1446 0, // sub3
1447 0, // sub4
1448 0, // sub5
1449 0, // sub6
1450 0, // sub7
1451 0, // sub8
1452 0, // sub9
1453 0, // sub10
1454 0, // sub11
1455 0, // sub12
1456 0, // sub13
1457 0, // sub14
1458 0, // sub15
1459 },
1460 { // R600_Addr_Y
1461 0, // sub0
1462 0, // sub1
1463 0, // sub2
1464 0, // sub3
1465 0, // sub4
1466 0, // sub5
1467 0, // sub6
1468 0, // sub7
1469 0, // sub8
1470 0, // sub9
1471 0, // sub10
1472 0, // sub11
1473 0, // sub12
1474 0, // sub13
1475 0, // sub14
1476 0, // sub15
1477 },
1478 { // R600_Addr_Z
1479 0, // sub0
1480 0, // sub1
1481 0, // sub2
1482 0, // sub3
1483 0, // sub4
1484 0, // sub5
1485 0, // sub6
1486 0, // sub7
1487 0, // sub8
1488 0, // sub9
1489 0, // sub10
1490 0, // sub11
1491 0, // sub12
1492 0, // sub13
1493 0, // sub14
1494 0, // sub15
1495 },
1496 { // R600_LDS_SRC_REG_and_R600_Reg32
1497 0, // sub0
1498 0, // sub1
1499 0, // sub2
1500 0, // sub3
1501 0, // sub4
1502 0, // sub5
1503 0, // sub6
1504 0, // sub7
1505 0, // sub8
1506 0, // sub9
1507 0, // sub10
1508 0, // sub11
1509 0, // sub12
1510 0, // sub13
1511 0, // sub14
1512 0, // sub15
1513 },
1514 { // R600_Predicate_Bit
1515 0, // sub0
1516 0, // sub1
1517 0, // sub2
1518 0, // sub3
1519 0, // sub4
1520 0, // sub5
1521 0, // sub6
1522 0, // sub7
1523 0, // sub8
1524 0, // sub9
1525 0, // sub10
1526 0, // sub11
1527 0, // sub12
1528 0, // sub13
1529 0, // sub14
1530 0, // sub15
1531 },
1532 { // R600_Reg64
1533 26, // sub0 -> R600_Reg64
1534 26, // sub1 -> R600_Reg64
1535 0, // sub2
1536 0, // sub3
1537 0, // sub4
1538 0, // sub5
1539 0, // sub6
1540 0, // sub7
1541 0, // sub8
1542 0, // sub9
1543 0, // sub10
1544 0, // sub11
1545 0, // sub12
1546 0, // sub13
1547 0, // sub14
1548 0, // sub15
1549 },
1550 { // R600_Reg64Vertical
1551 27, // sub0 -> R600_Reg64Vertical
1552 27, // sub1 -> R600_Reg64Vertical
1553 0, // sub2
1554 0, // sub3
1555 0, // sub4
1556 0, // sub5
1557 0, // sub6
1558 0, // sub7
1559 0, // sub8
1560 0, // sub9
1561 0, // sub10
1562 0, // sub11
1563 0, // sub12
1564 0, // sub13
1565 0, // sub14
1566 0, // sub15
1567 },
1568 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
1569 28, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
1570 28, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
1571 0, // sub2
1572 0, // sub3
1573 0, // sub4
1574 0, // sub5
1575 0, // sub6
1576 0, // sub7
1577 0, // sub8
1578 0, // sub9
1579 0, // sub10
1580 0, // sub11
1581 0, // sub12
1582 0, // sub13
1583 0, // sub14
1584 0, // sub15
1585 },
1586 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
1587 29, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
1588 29, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
1589 0, // sub2
1590 0, // sub3
1591 0, // sub4
1592 0, // sub5
1593 0, // sub6
1594 0, // sub7
1595 0, // sub8
1596 0, // sub9
1597 0, // sub10
1598 0, // sub11
1599 0, // sub12
1600 0, // sub13
1601 0, // sub14
1602 0, // sub15
1603 },
1604 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
1605 30, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
1606 30, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
1607 0, // sub2
1608 0, // sub3
1609 0, // sub4
1610 0, // sub5
1611 0, // sub6
1612 0, // sub7
1613 0, // sub8
1614 0, // sub9
1615 0, // sub10
1616 0, // sub11
1617 0, // sub12
1618 0, // sub13
1619 0, // sub14
1620 0, // sub15
1621 },
1622 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
1623 31, // sub0 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
1624 31, // sub1 -> R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
1625 0, // sub2
1626 0, // sub3
1627 0, // sub4
1628 0, // sub5
1629 0, // sub6
1630 0, // sub7
1631 0, // sub8
1632 0, // sub9
1633 0, // sub10
1634 0, // sub11
1635 0, // sub12
1636 0, // sub13
1637 0, // sub14
1638 0, // sub15
1639 },
1640 { // R600_Reg128
1641 32, // sub0 -> R600_Reg128
1642 32, // sub1 -> R600_Reg128
1643 32, // sub2 -> R600_Reg128
1644 32, // sub3 -> R600_Reg128
1645 0, // sub4
1646 0, // sub5
1647 0, // sub6
1648 0, // sub7
1649 0, // sub8
1650 0, // sub9
1651 0, // sub10
1652 0, // sub11
1653 0, // sub12
1654 0, // sub13
1655 0, // sub14
1656 0, // sub15
1657 },
1658 { // R600_Reg128Vertical
1659 33, // sub0 -> R600_Reg128Vertical
1660 33, // sub1 -> R600_Reg128Vertical
1661 33, // sub2 -> R600_Reg128Vertical
1662 33, // sub3 -> R600_Reg128Vertical
1663 0, // sub4
1664 0, // sub5
1665 0, // sub6
1666 0, // sub7
1667 0, // sub8
1668 0, // sub9
1669 0, // sub10
1670 0, // sub11
1671 0, // sub12
1672 0, // sub13
1673 0, // sub14
1674 0, // sub15
1675 },
1676 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1677 34, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1678 34, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1679 34, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1680 34, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
1681 0, // sub4
1682 0, // sub5
1683 0, // sub6
1684 0, // sub7
1685 0, // sub8
1686 0, // sub9
1687 0, // sub10
1688 0, // sub11
1689 0, // sub12
1690 0, // sub13
1691 0, // sub14
1692 0, // sub15
1693 },
1694 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1695 35, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1696 35, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1697 35, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1698 35, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
1699 0, // sub4
1700 0, // sub5
1701 0, // sub6
1702 0, // sub7
1703 0, // sub8
1704 0, // sub9
1705 0, // sub10
1706 0, // sub11
1707 0, // sub12
1708 0, // sub13
1709 0, // sub14
1710 0, // sub15
1711 },
1712 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1713 36, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1714 36, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1715 36, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1716 36, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
1717 0, // sub4
1718 0, // sub5
1719 0, // sub6
1720 0, // sub7
1721 0, // sub8
1722 0, // sub9
1723 0, // sub10
1724 0, // sub11
1725 0, // sub12
1726 0, // sub13
1727 0, // sub14
1728 0, // sub15
1729 },
1730 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1731 37, // sub0 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1732 37, // sub1 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1733 37, // sub2 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1734 37, // sub3 -> R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
1735 0, // sub4
1736 0, // sub5
1737 0, // sub6
1738 0, // sub7
1739 0, // sub8
1740 0, // sub9
1741 0, // sub10
1742 0, // sub11
1743 0, // sub12
1744 0, // sub13
1745 0, // sub14
1746 0, // sub15
1747 },
1748 };
1749 assert(RC && "Missing regclass");
1750 if (!Idx) return RC;
1751 --Idx;
1752 assert(Idx < 16 && "Bad subreg");
1753 unsigned TV = Table[RC->getID()][Idx];
1754 return TV ? getRegClass(i: TV - 1) : nullptr;
1755}
1756
1757const TargetRegisterClass *R600GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1758 static const uint8_t Table[37][16] = {
1759 { // R600_Reg32
1760 0, // R600_Reg32:sub0
1761 0, // R600_Reg32:sub1
1762 0, // R600_Reg32:sub2
1763 0, // R600_Reg32:sub3
1764 0, // R600_Reg32:sub4
1765 0, // R600_Reg32:sub5
1766 0, // R600_Reg32:sub6
1767 0, // R600_Reg32:sub7
1768 0, // R600_Reg32:sub8
1769 0, // R600_Reg32:sub9
1770 0, // R600_Reg32:sub10
1771 0, // R600_Reg32:sub11
1772 0, // R600_Reg32:sub12
1773 0, // R600_Reg32:sub13
1774 0, // R600_Reg32:sub14
1775 0, // R600_Reg32:sub15
1776 },
1777 { // R600_TReg32
1778 0, // R600_TReg32:sub0
1779 0, // R600_TReg32:sub1
1780 0, // R600_TReg32:sub2
1781 0, // R600_TReg32:sub3
1782 0, // R600_TReg32:sub4
1783 0, // R600_TReg32:sub5
1784 0, // R600_TReg32:sub6
1785 0, // R600_TReg32:sub7
1786 0, // R600_TReg32:sub8
1787 0, // R600_TReg32:sub9
1788 0, // R600_TReg32:sub10
1789 0, // R600_TReg32:sub11
1790 0, // R600_TReg32:sub12
1791 0, // R600_TReg32:sub13
1792 0, // R600_TReg32:sub14
1793 0, // R600_TReg32:sub15
1794 },
1795 { // R600_TReg32_X
1796 0, // R600_TReg32_X:sub0
1797 0, // R600_TReg32_X:sub1
1798 0, // R600_TReg32_X:sub2
1799 0, // R600_TReg32_X:sub3
1800 0, // R600_TReg32_X:sub4
1801 0, // R600_TReg32_X:sub5
1802 0, // R600_TReg32_X:sub6
1803 0, // R600_TReg32_X:sub7
1804 0, // R600_TReg32_X:sub8
1805 0, // R600_TReg32_X:sub9
1806 0, // R600_TReg32_X:sub10
1807 0, // R600_TReg32_X:sub11
1808 0, // R600_TReg32_X:sub12
1809 0, // R600_TReg32_X:sub13
1810 0, // R600_TReg32_X:sub14
1811 0, // R600_TReg32_X:sub15
1812 },
1813 { // R600_Addr
1814 0, // R600_Addr:sub0
1815 0, // R600_Addr:sub1
1816 0, // R600_Addr:sub2
1817 0, // R600_Addr:sub3
1818 0, // R600_Addr:sub4
1819 0, // R600_Addr:sub5
1820 0, // R600_Addr:sub6
1821 0, // R600_Addr:sub7
1822 0, // R600_Addr:sub8
1823 0, // R600_Addr:sub9
1824 0, // R600_Addr:sub10
1825 0, // R600_Addr:sub11
1826 0, // R600_Addr:sub12
1827 0, // R600_Addr:sub13
1828 0, // R600_Addr:sub14
1829 0, // R600_Addr:sub15
1830 },
1831 { // R600_KC0
1832 0, // R600_KC0:sub0
1833 0, // R600_KC0:sub1
1834 0, // R600_KC0:sub2
1835 0, // R600_KC0:sub3
1836 0, // R600_KC0:sub4
1837 0, // R600_KC0:sub5
1838 0, // R600_KC0:sub6
1839 0, // R600_KC0:sub7
1840 0, // R600_KC0:sub8
1841 0, // R600_KC0:sub9
1842 0, // R600_KC0:sub10
1843 0, // R600_KC0:sub11
1844 0, // R600_KC0:sub12
1845 0, // R600_KC0:sub13
1846 0, // R600_KC0:sub14
1847 0, // R600_KC0:sub15
1848 },
1849 { // R600_KC1
1850 0, // R600_KC1:sub0
1851 0, // R600_KC1:sub1
1852 0, // R600_KC1:sub2
1853 0, // R600_KC1:sub3
1854 0, // R600_KC1:sub4
1855 0, // R600_KC1:sub5
1856 0, // R600_KC1:sub6
1857 0, // R600_KC1:sub7
1858 0, // R600_KC1:sub8
1859 0, // R600_KC1:sub9
1860 0, // R600_KC1:sub10
1861 0, // R600_KC1:sub11
1862 0, // R600_KC1:sub12
1863 0, // R600_KC1:sub13
1864 0, // R600_KC1:sub14
1865 0, // R600_KC1:sub15
1866 },
1867 { // R600_TReg32_W
1868 0, // R600_TReg32_W:sub0
1869 0, // R600_TReg32_W:sub1
1870 0, // R600_TReg32_W:sub2
1871 0, // R600_TReg32_W:sub3
1872 0, // R600_TReg32_W:sub4
1873 0, // R600_TReg32_W:sub5
1874 0, // R600_TReg32_W:sub6
1875 0, // R600_TReg32_W:sub7
1876 0, // R600_TReg32_W:sub8
1877 0, // R600_TReg32_W:sub9
1878 0, // R600_TReg32_W:sub10
1879 0, // R600_TReg32_W:sub11
1880 0, // R600_TReg32_W:sub12
1881 0, // R600_TReg32_W:sub13
1882 0, // R600_TReg32_W:sub14
1883 0, // R600_TReg32_W:sub15
1884 },
1885 { // R600_TReg32_Y
1886 0, // R600_TReg32_Y:sub0
1887 0, // R600_TReg32_Y:sub1
1888 0, // R600_TReg32_Y:sub2
1889 0, // R600_TReg32_Y:sub3
1890 0, // R600_TReg32_Y:sub4
1891 0, // R600_TReg32_Y:sub5
1892 0, // R600_TReg32_Y:sub6
1893 0, // R600_TReg32_Y:sub7
1894 0, // R600_TReg32_Y:sub8
1895 0, // R600_TReg32_Y:sub9
1896 0, // R600_TReg32_Y:sub10
1897 0, // R600_TReg32_Y:sub11
1898 0, // R600_TReg32_Y:sub12
1899 0, // R600_TReg32_Y:sub13
1900 0, // R600_TReg32_Y:sub14
1901 0, // R600_TReg32_Y:sub15
1902 },
1903 { // R600_TReg32_Z
1904 0, // R600_TReg32_Z:sub0
1905 0, // R600_TReg32_Z:sub1
1906 0, // R600_TReg32_Z:sub2
1907 0, // R600_TReg32_Z:sub3
1908 0, // R600_TReg32_Z:sub4
1909 0, // R600_TReg32_Z:sub5
1910 0, // R600_TReg32_Z:sub6
1911 0, // R600_TReg32_Z:sub7
1912 0, // R600_TReg32_Z:sub8
1913 0, // R600_TReg32_Z:sub9
1914 0, // R600_TReg32_Z:sub10
1915 0, // R600_TReg32_Z:sub11
1916 0, // R600_TReg32_Z:sub12
1917 0, // R600_TReg32_Z:sub13
1918 0, // R600_TReg32_Z:sub14
1919 0, // R600_TReg32_Z:sub15
1920 },
1921 { // R600_ArrayBase
1922 0, // R600_ArrayBase:sub0
1923 0, // R600_ArrayBase:sub1
1924 0, // R600_ArrayBase:sub2
1925 0, // R600_ArrayBase:sub3
1926 0, // R600_ArrayBase:sub4
1927 0, // R600_ArrayBase:sub5
1928 0, // R600_ArrayBase:sub6
1929 0, // R600_ArrayBase:sub7
1930 0, // R600_ArrayBase:sub8
1931 0, // R600_ArrayBase:sub9
1932 0, // R600_ArrayBase:sub10
1933 0, // R600_ArrayBase:sub11
1934 0, // R600_ArrayBase:sub12
1935 0, // R600_ArrayBase:sub13
1936 0, // R600_ArrayBase:sub14
1937 0, // R600_ArrayBase:sub15
1938 },
1939 { // R600_KC0_W
1940 0, // R600_KC0_W:sub0
1941 0, // R600_KC0_W:sub1
1942 0, // R600_KC0_W:sub2
1943 0, // R600_KC0_W:sub3
1944 0, // R600_KC0_W:sub4
1945 0, // R600_KC0_W:sub5
1946 0, // R600_KC0_W:sub6
1947 0, // R600_KC0_W:sub7
1948 0, // R600_KC0_W:sub8
1949 0, // R600_KC0_W:sub9
1950 0, // R600_KC0_W:sub10
1951 0, // R600_KC0_W:sub11
1952 0, // R600_KC0_W:sub12
1953 0, // R600_KC0_W:sub13
1954 0, // R600_KC0_W:sub14
1955 0, // R600_KC0_W:sub15
1956 },
1957 { // R600_KC0_X
1958 0, // R600_KC0_X:sub0
1959 0, // R600_KC0_X:sub1
1960 0, // R600_KC0_X:sub2
1961 0, // R600_KC0_X:sub3
1962 0, // R600_KC0_X:sub4
1963 0, // R600_KC0_X:sub5
1964 0, // R600_KC0_X:sub6
1965 0, // R600_KC0_X:sub7
1966 0, // R600_KC0_X:sub8
1967 0, // R600_KC0_X:sub9
1968 0, // R600_KC0_X:sub10
1969 0, // R600_KC0_X:sub11
1970 0, // R600_KC0_X:sub12
1971 0, // R600_KC0_X:sub13
1972 0, // R600_KC0_X:sub14
1973 0, // R600_KC0_X:sub15
1974 },
1975 { // R600_KC0_Y
1976 0, // R600_KC0_Y:sub0
1977 0, // R600_KC0_Y:sub1
1978 0, // R600_KC0_Y:sub2
1979 0, // R600_KC0_Y:sub3
1980 0, // R600_KC0_Y:sub4
1981 0, // R600_KC0_Y:sub5
1982 0, // R600_KC0_Y:sub6
1983 0, // R600_KC0_Y:sub7
1984 0, // R600_KC0_Y:sub8
1985 0, // R600_KC0_Y:sub9
1986 0, // R600_KC0_Y:sub10
1987 0, // R600_KC0_Y:sub11
1988 0, // R600_KC0_Y:sub12
1989 0, // R600_KC0_Y:sub13
1990 0, // R600_KC0_Y:sub14
1991 0, // R600_KC0_Y:sub15
1992 },
1993 { // R600_KC0_Z
1994 0, // R600_KC0_Z:sub0
1995 0, // R600_KC0_Z:sub1
1996 0, // R600_KC0_Z:sub2
1997 0, // R600_KC0_Z:sub3
1998 0, // R600_KC0_Z:sub4
1999 0, // R600_KC0_Z:sub5
2000 0, // R600_KC0_Z:sub6
2001 0, // R600_KC0_Z:sub7
2002 0, // R600_KC0_Z:sub8
2003 0, // R600_KC0_Z:sub9
2004 0, // R600_KC0_Z:sub10
2005 0, // R600_KC0_Z:sub11
2006 0, // R600_KC0_Z:sub12
2007 0, // R600_KC0_Z:sub13
2008 0, // R600_KC0_Z:sub14
2009 0, // R600_KC0_Z:sub15
2010 },
2011 { // R600_KC1_W
2012 0, // R600_KC1_W:sub0
2013 0, // R600_KC1_W:sub1
2014 0, // R600_KC1_W:sub2
2015 0, // R600_KC1_W:sub3
2016 0, // R600_KC1_W:sub4
2017 0, // R600_KC1_W:sub5
2018 0, // R600_KC1_W:sub6
2019 0, // R600_KC1_W:sub7
2020 0, // R600_KC1_W:sub8
2021 0, // R600_KC1_W:sub9
2022 0, // R600_KC1_W:sub10
2023 0, // R600_KC1_W:sub11
2024 0, // R600_KC1_W:sub12
2025 0, // R600_KC1_W:sub13
2026 0, // R600_KC1_W:sub14
2027 0, // R600_KC1_W:sub15
2028 },
2029 { // R600_KC1_X
2030 0, // R600_KC1_X:sub0
2031 0, // R600_KC1_X:sub1
2032 0, // R600_KC1_X:sub2
2033 0, // R600_KC1_X:sub3
2034 0, // R600_KC1_X:sub4
2035 0, // R600_KC1_X:sub5
2036 0, // R600_KC1_X:sub6
2037 0, // R600_KC1_X:sub7
2038 0, // R600_KC1_X:sub8
2039 0, // R600_KC1_X:sub9
2040 0, // R600_KC1_X:sub10
2041 0, // R600_KC1_X:sub11
2042 0, // R600_KC1_X:sub12
2043 0, // R600_KC1_X:sub13
2044 0, // R600_KC1_X:sub14
2045 0, // R600_KC1_X:sub15
2046 },
2047 { // R600_KC1_Y
2048 0, // R600_KC1_Y:sub0
2049 0, // R600_KC1_Y:sub1
2050 0, // R600_KC1_Y:sub2
2051 0, // R600_KC1_Y:sub3
2052 0, // R600_KC1_Y:sub4
2053 0, // R600_KC1_Y:sub5
2054 0, // R600_KC1_Y:sub6
2055 0, // R600_KC1_Y:sub7
2056 0, // R600_KC1_Y:sub8
2057 0, // R600_KC1_Y:sub9
2058 0, // R600_KC1_Y:sub10
2059 0, // R600_KC1_Y:sub11
2060 0, // R600_KC1_Y:sub12
2061 0, // R600_KC1_Y:sub13
2062 0, // R600_KC1_Y:sub14
2063 0, // R600_KC1_Y:sub15
2064 },
2065 { // R600_KC1_Z
2066 0, // R600_KC1_Z:sub0
2067 0, // R600_KC1_Z:sub1
2068 0, // R600_KC1_Z:sub2
2069 0, // R600_KC1_Z:sub3
2070 0, // R600_KC1_Z:sub4
2071 0, // R600_KC1_Z:sub5
2072 0, // R600_KC1_Z:sub6
2073 0, // R600_KC1_Z:sub7
2074 0, // R600_KC1_Z:sub8
2075 0, // R600_KC1_Z:sub9
2076 0, // R600_KC1_Z:sub10
2077 0, // R600_KC1_Z:sub11
2078 0, // R600_KC1_Z:sub12
2079 0, // R600_KC1_Z:sub13
2080 0, // R600_KC1_Z:sub14
2081 0, // R600_KC1_Z:sub15
2082 },
2083 { // R600_LDS_SRC_REG
2084 0, // R600_LDS_SRC_REG:sub0
2085 0, // R600_LDS_SRC_REG:sub1
2086 0, // R600_LDS_SRC_REG:sub2
2087 0, // R600_LDS_SRC_REG:sub3
2088 0, // R600_LDS_SRC_REG:sub4
2089 0, // R600_LDS_SRC_REG:sub5
2090 0, // R600_LDS_SRC_REG:sub6
2091 0, // R600_LDS_SRC_REG:sub7
2092 0, // R600_LDS_SRC_REG:sub8
2093 0, // R600_LDS_SRC_REG:sub9
2094 0, // R600_LDS_SRC_REG:sub10
2095 0, // R600_LDS_SRC_REG:sub11
2096 0, // R600_LDS_SRC_REG:sub12
2097 0, // R600_LDS_SRC_REG:sub13
2098 0, // R600_LDS_SRC_REG:sub14
2099 0, // R600_LDS_SRC_REG:sub15
2100 },
2101 { // R600_Predicate
2102 0, // R600_Predicate:sub0
2103 0, // R600_Predicate:sub1
2104 0, // R600_Predicate:sub2
2105 0, // R600_Predicate:sub3
2106 0, // R600_Predicate:sub4
2107 0, // R600_Predicate:sub5
2108 0, // R600_Predicate:sub6
2109 0, // R600_Predicate:sub7
2110 0, // R600_Predicate:sub8
2111 0, // R600_Predicate:sub9
2112 0, // R600_Predicate:sub10
2113 0, // R600_Predicate:sub11
2114 0, // R600_Predicate:sub12
2115 0, // R600_Predicate:sub13
2116 0, // R600_Predicate:sub14
2117 0, // R600_Predicate:sub15
2118 },
2119 { // R600_Addr_W
2120 0, // R600_Addr_W:sub0
2121 0, // R600_Addr_W:sub1
2122 0, // R600_Addr_W:sub2
2123 0, // R600_Addr_W:sub3
2124 0, // R600_Addr_W:sub4
2125 0, // R600_Addr_W:sub5
2126 0, // R600_Addr_W:sub6
2127 0, // R600_Addr_W:sub7
2128 0, // R600_Addr_W:sub8
2129 0, // R600_Addr_W:sub9
2130 0, // R600_Addr_W:sub10
2131 0, // R600_Addr_W:sub11
2132 0, // R600_Addr_W:sub12
2133 0, // R600_Addr_W:sub13
2134 0, // R600_Addr_W:sub14
2135 0, // R600_Addr_W:sub15
2136 },
2137 { // R600_Addr_Y
2138 0, // R600_Addr_Y:sub0
2139 0, // R600_Addr_Y:sub1
2140 0, // R600_Addr_Y:sub2
2141 0, // R600_Addr_Y:sub3
2142 0, // R600_Addr_Y:sub4
2143 0, // R600_Addr_Y:sub5
2144 0, // R600_Addr_Y:sub6
2145 0, // R600_Addr_Y:sub7
2146 0, // R600_Addr_Y:sub8
2147 0, // R600_Addr_Y:sub9
2148 0, // R600_Addr_Y:sub10
2149 0, // R600_Addr_Y:sub11
2150 0, // R600_Addr_Y:sub12
2151 0, // R600_Addr_Y:sub13
2152 0, // R600_Addr_Y:sub14
2153 0, // R600_Addr_Y:sub15
2154 },
2155 { // R600_Addr_Z
2156 0, // R600_Addr_Z:sub0
2157 0, // R600_Addr_Z:sub1
2158 0, // R600_Addr_Z:sub2
2159 0, // R600_Addr_Z:sub3
2160 0, // R600_Addr_Z:sub4
2161 0, // R600_Addr_Z:sub5
2162 0, // R600_Addr_Z:sub6
2163 0, // R600_Addr_Z:sub7
2164 0, // R600_Addr_Z:sub8
2165 0, // R600_Addr_Z:sub9
2166 0, // R600_Addr_Z:sub10
2167 0, // R600_Addr_Z:sub11
2168 0, // R600_Addr_Z:sub12
2169 0, // R600_Addr_Z:sub13
2170 0, // R600_Addr_Z:sub14
2171 0, // R600_Addr_Z:sub15
2172 },
2173 { // R600_LDS_SRC_REG_and_R600_Reg32
2174 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub0
2175 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub1
2176 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub2
2177 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub3
2178 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub4
2179 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub5
2180 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub6
2181 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub7
2182 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub8
2183 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub9
2184 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub10
2185 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub11
2186 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub12
2187 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub13
2188 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub14
2189 0, // R600_LDS_SRC_REG_and_R600_Reg32:sub15
2190 },
2191 { // R600_Predicate_Bit
2192 0, // R600_Predicate_Bit:sub0
2193 0, // R600_Predicate_Bit:sub1
2194 0, // R600_Predicate_Bit:sub2
2195 0, // R600_Predicate_Bit:sub3
2196 0, // R600_Predicate_Bit:sub4
2197 0, // R600_Predicate_Bit:sub5
2198 0, // R600_Predicate_Bit:sub6
2199 0, // R600_Predicate_Bit:sub7
2200 0, // R600_Predicate_Bit:sub8
2201 0, // R600_Predicate_Bit:sub9
2202 0, // R600_Predicate_Bit:sub10
2203 0, // R600_Predicate_Bit:sub11
2204 0, // R600_Predicate_Bit:sub12
2205 0, // R600_Predicate_Bit:sub13
2206 0, // R600_Predicate_Bit:sub14
2207 0, // R600_Predicate_Bit:sub15
2208 },
2209 { // R600_Reg64
2210 3, // R600_Reg64:sub0 -> R600_TReg32_X
2211 8, // R600_Reg64:sub1 -> R600_TReg32_Y
2212 0, // R600_Reg64:sub2
2213 0, // R600_Reg64:sub3
2214 0, // R600_Reg64:sub4
2215 0, // R600_Reg64:sub5
2216 0, // R600_Reg64:sub6
2217 0, // R600_Reg64:sub7
2218 0, // R600_Reg64:sub8
2219 0, // R600_Reg64:sub9
2220 0, // R600_Reg64:sub10
2221 0, // R600_Reg64:sub11
2222 0, // R600_Reg64:sub12
2223 0, // R600_Reg64:sub13
2224 0, // R600_Reg64:sub14
2225 0, // R600_Reg64:sub15
2226 },
2227 { // R600_Reg64Vertical
2228 2, // R600_Reg64Vertical:sub0 -> R600_TReg32
2229 2, // R600_Reg64Vertical:sub1 -> R600_TReg32
2230 0, // R600_Reg64Vertical:sub2
2231 0, // R600_Reg64Vertical:sub3
2232 0, // R600_Reg64Vertical:sub4
2233 0, // R600_Reg64Vertical:sub5
2234 0, // R600_Reg64Vertical:sub6
2235 0, // R600_Reg64Vertical:sub7
2236 0, // R600_Reg64Vertical:sub8
2237 0, // R600_Reg64Vertical:sub9
2238 0, // R600_Reg64Vertical:sub10
2239 0, // R600_Reg64Vertical:sub11
2240 0, // R600_Reg64Vertical:sub12
2241 0, // R600_Reg64Vertical:sub13
2242 0, // R600_Reg64Vertical:sub14
2243 0, // R600_Reg64Vertical:sub15
2244 },
2245 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
2246 7, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub0 -> R600_TReg32_W
2247 7, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub1 -> R600_TReg32_W
2248 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub2
2249 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub3
2250 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub4
2251 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub5
2252 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub6
2253 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub7
2254 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub8
2255 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub9
2256 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub10
2257 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub11
2258 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub12
2259 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub13
2260 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub14
2261 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W:sub15
2262 },
2263 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
2264 3, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub0 -> R600_TReg32_X
2265 3, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub1 -> R600_TReg32_X
2266 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub2
2267 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub3
2268 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub4
2269 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub5
2270 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub6
2271 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub7
2272 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub8
2273 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub9
2274 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub10
2275 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub11
2276 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub12
2277 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub13
2278 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub14
2279 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X:sub15
2280 },
2281 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
2282 8, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub0 -> R600_TReg32_Y
2283 8, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub1 -> R600_TReg32_Y
2284 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub2
2285 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub3
2286 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub4
2287 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub5
2288 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub6
2289 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub7
2290 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub8
2291 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub9
2292 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub10
2293 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub11
2294 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub12
2295 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub13
2296 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub14
2297 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y:sub15
2298 },
2299 { // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
2300 9, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub0 -> R600_TReg32_Z
2301 9, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub1 -> R600_TReg32_Z
2302 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub2
2303 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub3
2304 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub4
2305 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub5
2306 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub6
2307 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub7
2308 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub8
2309 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub9
2310 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub10
2311 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub11
2312 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub12
2313 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub13
2314 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub14
2315 0, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z:sub15
2316 },
2317 { // R600_Reg128
2318 3, // R600_Reg128:sub0 -> R600_TReg32_X
2319 8, // R600_Reg128:sub1 -> R600_TReg32_Y
2320 9, // R600_Reg128:sub2 -> R600_TReg32_Z
2321 7, // R600_Reg128:sub3 -> R600_TReg32_W
2322 0, // R600_Reg128:sub4
2323 0, // R600_Reg128:sub5
2324 0, // R600_Reg128:sub6
2325 0, // R600_Reg128:sub7
2326 0, // R600_Reg128:sub8
2327 0, // R600_Reg128:sub9
2328 0, // R600_Reg128:sub10
2329 0, // R600_Reg128:sub11
2330 0, // R600_Reg128:sub12
2331 0, // R600_Reg128:sub13
2332 0, // R600_Reg128:sub14
2333 0, // R600_Reg128:sub15
2334 },
2335 { // R600_Reg128Vertical
2336 2, // R600_Reg128Vertical:sub0 -> R600_TReg32
2337 2, // R600_Reg128Vertical:sub1 -> R600_TReg32
2338 2, // R600_Reg128Vertical:sub2 -> R600_TReg32
2339 2, // R600_Reg128Vertical:sub3 -> R600_TReg32
2340 0, // R600_Reg128Vertical:sub4
2341 0, // R600_Reg128Vertical:sub5
2342 0, // R600_Reg128Vertical:sub6
2343 0, // R600_Reg128Vertical:sub7
2344 0, // R600_Reg128Vertical:sub8
2345 0, // R600_Reg128Vertical:sub9
2346 0, // R600_Reg128Vertical:sub10
2347 0, // R600_Reg128Vertical:sub11
2348 0, // R600_Reg128Vertical:sub12
2349 0, // R600_Reg128Vertical:sub13
2350 0, // R600_Reg128Vertical:sub14
2351 0, // R600_Reg128Vertical:sub15
2352 },
2353 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
2354 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub0 -> R600_TReg32_W
2355 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub1 -> R600_TReg32_W
2356 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub2 -> R600_TReg32_W
2357 7, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub3 -> R600_TReg32_W
2358 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub4
2359 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub5
2360 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub6
2361 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub7
2362 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub8
2363 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub9
2364 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub10
2365 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub11
2366 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub12
2367 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub13
2368 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub14
2369 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W:sub15
2370 },
2371 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
2372 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub0 -> R600_TReg32_X
2373 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub1 -> R600_TReg32_X
2374 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub2 -> R600_TReg32_X
2375 3, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub3 -> R600_TReg32_X
2376 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub4
2377 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub5
2378 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub6
2379 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub7
2380 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub8
2381 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub9
2382 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub10
2383 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub11
2384 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub12
2385 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub13
2386 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub14
2387 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X:sub15
2388 },
2389 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
2390 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub0 -> R600_TReg32_Y
2391 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub1 -> R600_TReg32_Y
2392 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub2 -> R600_TReg32_Y
2393 8, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub3 -> R600_TReg32_Y
2394 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub4
2395 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub5
2396 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub6
2397 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub7
2398 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub8
2399 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub9
2400 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub10
2401 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub11
2402 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub12
2403 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub13
2404 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub14
2405 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y:sub15
2406 },
2407 { // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
2408 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub0 -> R600_TReg32_Z
2409 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub1 -> R600_TReg32_Z
2410 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub2 -> R600_TReg32_Z
2411 9, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub3 -> R600_TReg32_Z
2412 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub4
2413 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub5
2414 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub6
2415 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub7
2416 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub8
2417 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub9
2418 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub10
2419 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub11
2420 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub12
2421 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub13
2422 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub14
2423 0, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z:sub15
2424 },
2425 };
2426 assert(RC && "Missing regclass");
2427 if (!Idx) return RC;
2428 --Idx;
2429 assert(Idx < 16 && "Bad subreg");
2430 unsigned TV = Table[RC->getID()][Idx];
2431 return TV ? getRegClass(i: TV - 1) : nullptr;
2432}
2433
2434/// Get the weight in units of pressure for this register class.
2435const RegClassWeight &R600GenRegisterInfo::
2436getRegClassWeight(const TargetRegisterClass *RC) const {
2437 static const RegClassWeight RCWeightTable[] = {
2438 {.RegWeight: 0, .WeightLimit: 942}, // R600_Reg32
2439 {.RegWeight: 0, .WeightLimit: 513}, // R600_TReg32
2440 {.RegWeight: 0, .WeightLimit: 129}, // R600_TReg32_X
2441 {.RegWeight: 0, .WeightLimit: 128}, // R600_Addr
2442 {.RegWeight: 0, .WeightLimit: 128}, // R600_KC0
2443 {.RegWeight: 0, .WeightLimit: 128}, // R600_KC1
2444 {.RegWeight: 0, .WeightLimit: 128}, // R600_TReg32_W
2445 {.RegWeight: 0, .WeightLimit: 128}, // R600_TReg32_Y
2446 {.RegWeight: 0, .WeightLimit: 128}, // R600_TReg32_Z
2447 {.RegWeight: 0, .WeightLimit: 33}, // R600_ArrayBase
2448 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC0_W
2449 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC0_X
2450 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC0_Y
2451 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC0_Z
2452 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC1_W
2453 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC1_X
2454 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC1_Y
2455 {.RegWeight: 0, .WeightLimit: 32}, // R600_KC1_Z
2456 {.RegWeight: 0, .WeightLimit: 1}, // R600_LDS_SRC_REG
2457 {.RegWeight: 0, .WeightLimit: 3}, // R600_Predicate
2458 {.RegWeight: 0, .WeightLimit: 0}, // R600_Addr_W
2459 {.RegWeight: 0, .WeightLimit: 0}, // R600_Addr_Y
2460 {.RegWeight: 0, .WeightLimit: 0}, // R600_Addr_Z
2461 {.RegWeight: 1, .WeightLimit: 1}, // R600_LDS_SRC_REG_and_R600_Reg32
2462 {.RegWeight: 0, .WeightLimit: 1}, // R600_Predicate_Bit
2463 {.RegWeight: 0, .WeightLimit: 128}, // R600_Reg64
2464 {.RegWeight: 0, .WeightLimit: 16}, // R600_Reg64Vertical
2465 {.RegWeight: 2, .WeightLimit: 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
2466 {.RegWeight: 2, .WeightLimit: 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
2467 {.RegWeight: 2, .WeightLimit: 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
2468 {.RegWeight: 2, .WeightLimit: 4}, // R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
2469 {.RegWeight: 0, .WeightLimit: 512}, // R600_Reg128
2470 {.RegWeight: 0, .WeightLimit: 16}, // R600_Reg128Vertical
2471 {.RegWeight: 4, .WeightLimit: 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_W
2472 {.RegWeight: 4, .WeightLimit: 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_X
2473 {.RegWeight: 4, .WeightLimit: 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Y
2474 {.RegWeight: 4, .WeightLimit: 4}, // R600_Reg128Vertical_with_sub0_in_R600_TReg32_Z
2475 };
2476 return RCWeightTable[RC->getID()];
2477}
2478
2479/// Get the weight in units of pressure for this register unit.
2480unsigned R600GenRegisterInfo::
2481getRegUnitWeight(MCRegUnit RegUnit) const {
2482 assert(static_cast<unsigned>(RegUnit) < 1342 && "invalid register unit");
2483 // All register units have unit weight.
2484 return 1;
2485}
2486
2487
2488// Get the number of dimensions of register pressure.
2489unsigned R600GenRegisterInfo::getNumRegPressureSets() const {
2490 return 23;
2491}
2492
2493// Get the name of this register unit pressure set.
2494const char *R600GenRegisterInfo::
2495getRegPressureSetName(unsigned Idx) const {
2496 static const char *PressureNameTable[] = {
2497 "R600_LDS_SRC_REG_and_R600_Reg32",
2498 "R600_Predicate_Bit",
2499 "R600_Predicate",
2500 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_W",
2501 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_X",
2502 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y",
2503 "R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z",
2504 "R600_Reg64Vertical",
2505 "R600_ArrayBase",
2506 "R600_TReg32_W",
2507 "R600_TReg32_Y",
2508 "R600_TReg32_Z",
2509 "R600_Reg64",
2510 "R600_TReg32_X",
2511 "R600_Reg64_with_R600_Reg64Vertical",
2512 "R600_TReg32_W_with_R600_Reg64Vertical",
2513 "R600_TReg32_Y_with_R600_Reg64Vertical",
2514 "R600_TReg32_Z_with_R600_Reg64Vertical",
2515 "R600_TReg32_X_with_R600_Reg64Vertical",
2516 "R600_TReg32_Y_with_R600_Reg64",
2517 "R600_TReg32_X_with_R600_Reg64",
2518 "R600_TReg32",
2519 "R600_Reg32",
2520 };
2521 return PressureNameTable[Idx];
2522}
2523
2524// Get the register unit pressure limit for this dimension.
2525// This limit must be adjusted dynamically for reserved registers.
2526unsigned R600GenRegisterInfo::
2527getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2528 static const uint16_t PressureLimitTable[] = {
2529 1, // 0: R600_LDS_SRC_REG_and_R600_Reg32
2530 1, // 1: R600_Predicate_Bit
2531 3, // 2: R600_Predicate
2532 4, // 3: R600_Reg64Vertical_with_sub0_in_R600_TReg32_W
2533 4, // 4: R600_Reg64Vertical_with_sub0_in_R600_TReg32_X
2534 4, // 5: R600_Reg64Vertical_with_sub0_in_R600_TReg32_Y
2535 4, // 6: R600_Reg64Vertical_with_sub0_in_R600_TReg32_Z
2536 16, // 7: R600_Reg64Vertical
2537 33, // 8: R600_ArrayBase
2538 128, // 9: R600_TReg32_W
2539 128, // 10: R600_TReg32_Y
2540 128, // 11: R600_TReg32_Z
2541 128, // 12: R600_Reg64
2542 129, // 13: R600_TReg32_X
2543 136, // 14: R600_Reg64_with_R600_Reg64Vertical
2544 140, // 15: R600_TReg32_W_with_R600_Reg64Vertical
2545 140, // 16: R600_TReg32_Y_with_R600_Reg64Vertical
2546 140, // 17: R600_TReg32_Z_with_R600_Reg64Vertical
2547 141, // 18: R600_TReg32_X_with_R600_Reg64Vertical
2548 192, // 19: R600_TReg32_Y_with_R600_Reg64
2549 193, // 20: R600_TReg32_X_with_R600_Reg64
2550 513, // 21: R600_TReg32
2551 942, // 22: R600_Reg32
2552 };
2553 return PressureLimitTable[Idx];
2554}
2555
2556/// Table of pressure sets per register class or unit.
2557static const int RCSetsTable[] = {
2558 /* 0 */ 1, -1,
2559 /* 2 */ 2, -1,
2560 /* 4 */ 0, 22, -1,
2561 /* 7 */ 8, 22, -1,
2562 /* 10 */ 9, 15, 21, 22, -1,
2563 /* 15 */ 11, 17, 21, 22, -1,
2564 /* 20 */ 7, 14, 15, 16, 17, 18, 21, 22, -1,
2565 /* 29 */ 3, 7, 9, 14, 15, 16, 17, 18, 21, 22, -1,
2566 /* 40 */ 6, 7, 11, 14, 15, 16, 17, 18, 21, 22, -1,
2567 /* 51 */ 10, 16, 19, 21, 22, -1,
2568 /* 57 */ 13, 18, 20, 21, 22, -1,
2569 /* 63 */ 12, 14, 19, 20, 21, 22, -1,
2570 /* 70 */ 10, 12, 14, 16, 19, 20, 21, 22, -1,
2571 /* 79 */ 12, 13, 14, 18, 19, 20, 21, 22, -1,
2572 /* 88 */ 5, 7, 10, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1,
2573 /* 102 */ 4, 7, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, -1,
2574};
2575
2576/// Get the dimensions of register pressure impacted by this register class.
2577/// Returns a -1 terminated array of pressure set IDs
2578const int *R600GenRegisterInfo::
2579getRegClassPressureSets(const TargetRegisterClass *RC) const {
2580 static const uint8_t RCSetStartTable[] = {
2581 5,12,57,1,1,1,10,51,15,7,1,1,1,1,1,1,1,1,1,2,1,1,1,4,0,63,20,29,102,88,40,12,20,29,102,88,40,};
2582 return &RCSetsTable[RCSetStartTable[RC->getID()]];
2583}
2584
2585/// Get the dimensions of register pressure impacted by this register unit.
2586/// Returns a -1 terminated array of pressure set IDs
2587const int *R600GenRegisterInfo::
2588getRegUnitPressureSets(MCRegUnit RegUnit) const {
2589 assert(static_cast<unsigned>(RegUnit) < 1342 && "invalid register unit");
2590 static const uint8_t RUSetStartTable[] = {
2591 5,1,5,1,1,5,57,5,5,1,1,5,5,5,5,1,4,1,1,0,2,2,2,1,1,5,1,1,5,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,29,29,29,29,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,102,102,102,102,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,79,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,57,88,88,88,88,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,70,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,40,40,40,40,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,};
2592 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
2593}
2594
2595extern const MCRegisterDesc R600RegDesc[];
2596extern const int16_t R600RegDiffLists[];
2597extern const LaneBitmask R600LaneMaskLists[];
2598extern const char R600RegStrings[];
2599extern const char R600RegClassStrings[];
2600extern const MCPhysReg R600RegUnitRoots[][2];
2601extern const uint16_t R600SubRegIdxLists[];
2602extern const uint16_t R600RegEncodingTable[];
2603R600GenRegisterInfo::
2604R600GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2605 unsigned PC, unsigned HwMode)
2606 : TargetRegisterInfo(&R600RegInfoDesc, RegisterClasses, RegisterClasses+37,
2607 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
2608 LaneBitmask(0xFFFFFFFFFFFFFFF0), RegClassInfos, VTLists, HwMode) {
2609 InitMCRegisterInfo(D: R600RegDesc, NR: 1675, RA, PC,
2610 C: R600MCRegisterClasses, NC: 37,
2611 RURoots: R600RegUnitRoots,
2612 NRU: 1342,
2613 DL: R600RegDiffLists,
2614 RUMS: R600LaneMaskLists,
2615 Strings: R600RegStrings,
2616 ClassStrings: R600RegClassStrings,
2617 SubIndices: R600SubRegIdxLists,
2618 NumIndices: 17,
2619 RET: R600RegEncodingTable);
2620
2621}
2622
2623
2624
2625ArrayRef<const uint32_t *> R600GenRegisterInfo::getRegMasks() const {
2626 return {};
2627}
2628
2629bool R600GenRegisterInfo::
2630isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2631 return
2632 false;
2633}
2634
2635bool R600GenRegisterInfo::
2636isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
2637 return
2638 false;
2639}
2640
2641bool R600GenRegisterInfo::
2642isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2643 return
2644 false;
2645}
2646
2647bool R600GenRegisterInfo::
2648isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2649 return
2650 false;
2651}
2652
2653bool R600GenRegisterInfo::
2654isConstantPhysReg(MCRegister PhysReg) const {
2655 return
2656 false;
2657}
2658
2659ArrayRef<const char *> R600GenRegisterInfo::getRegMaskNames() const {
2660 return {};
2661}
2662
2663const R600FrameLowering *
2664R600GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2665 return static_cast<const R600FrameLowering *>(
2666 MF.getSubtarget().getFrameLowering());
2667}
2668
2669} // end namespace llvm
2670
2671