1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace R600 {
15
16enum {
17 FeatureAddressableLocalMemorySize32768 = 0,
18 FeatureAddressableLocalMemorySize65536 = 1,
19 FeatureAddressableLocalMemorySize163840 = 2,
20 FeatureAddressableLocalMemorySize327680 = 3,
21 FeatureCFALUBug = 4,
22 FeatureCaymanISA = 5,
23 FeatureEvergreen = 6,
24 FeatureFMA = 7,
25 FeatureFP64 = 8,
26 FeatureFetchLimit8 = 9,
27 FeatureFetchLimit16 = 10,
28 FeatureMadMacF32Insts = 11,
29 FeatureNorthernIslands = 12,
30 FeatureR600 = 13,
31 FeatureR600ALUInst = 14,
32 FeatureR700 = 15,
33 FeatureVertexCache = 16,
34 FeatureWavefrontSize16 = 17,
35 FeatureWavefrontSize32 = 18,
36 FeatureWavefrontSize64 = 19,
37 NumSubtargetFeatures = 20
38};
39
40} // namespace R600
41
42} // namespace llvm
43
44#endif // GET_SUBTARGETINFO_ENUM
45
46#ifdef GET_SUBTARGETINFO_MACRO
47
48GET_SUBTARGETINFO_MACRO(HasCFALUBug, false, hasCFALUBug)
49GET_SUBTARGETINFO_MACRO(HasCaymanISA, false, hasCaymanISA)
50GET_SUBTARGETINFO_MACRO(HasFMA, false, hasFMA)
51GET_SUBTARGETINFO_MACRO(HasFP64, false, hasFP64)
52GET_SUBTARGETINFO_MACRO(HasMadMacF32Insts, false, hasMadMacF32Insts)
53GET_SUBTARGETINFO_MACRO(HasR600ALUInst, true, hasR600ALUInst)
54GET_SUBTARGETINFO_MACRO(HasVertexCache, false, hasVertexCache)
55
56#undef GET_SUBTARGETINFO_MACRO
57#endif // GET_SUBTARGETINFO_MACRO
58
59#ifdef GET_SUBTARGETINFO_MC_DESC
60#undef GET_SUBTARGETINFO_MC_DESC
61
62namespace llvm {
63
64// Sorted (by key) array of values for CPU features.
65extern const llvm::SubtargetFeatureKV R600FeatureKV[] = {
66 { "HasVertexCache", "Specify use of dedicated vertex cache", R600::FeatureVertexCache, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
67 { "R600ALUInst", "Older version of ALU instructions encoding", R600::FeatureR600ALUInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
68 { "addressablelocalmemorysize163840", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize163840, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
69 { "addressablelocalmemorysize32768", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
70 { "addressablelocalmemorysize327680", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize327680, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
71 { "addressablelocalmemorysize65536", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
72 { "caymanISA", "Use Cayman ISA", R600::FeatureCaymanISA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
73 { "cfalubug", "GPU has CF_ALU bug", R600::FeatureCFALUBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { "evergreen", "EVERGREEN GPU generation", R600::FeatureEvergreen, { { { 0xc01ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { "fetch16", "Limit the maximum number of fetches in a clause to 16", R600::FeatureFetchLimit16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { "fetch8", "Limit the maximum number of fetches in a clause to 8", R600::FeatureFetchLimit8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", R600::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { "fp64", "Enable double precision operations", R600::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { "mad-mac-f32-insts", "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions", R600::FeatureMadMacF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { "northern-islands", "NORTHERN_ISLANDS GPU generation", R600::FeatureNorthernIslands, { { { 0x80c01ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { "r600", "R600 GPU generation", R600::FeatureR600, { { { 0x4a00ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { "r700", "R700 GPU generation", R600::FeatureR700, { { { 0xc00ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { "wavefrontsize16", "The number of threads per wavefront", R600::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { "wavefrontsize32", "The number of threads per wavefront", R600::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { "wavefrontsize64", "The number of threads per wavefront", R600::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86};
87
88#ifdef DBGFIELD
89#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
90#endif
91#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
92#define DBGFIELD(x) x,
93#define DBGVAL_OR_NULLPTR(x) x
94#else
95#define DBGFIELD(x)
96#define DBGVAL_OR_NULLPTR(x) nullptr
97#endif
98
99// Functional units for "R600_VLIW5_Itin"
100namespace R600_VLIW5_ItinFU {
101
102 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
103 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
104 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
105 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
106 const InstrStage::FuncUnits TRANS = 1ULL << 4;
107 const InstrStage::FuncUnits ALU_NULL = 1ULL << 5;
108
109} // namespace R600_VLIW5_ItinFU
110
111// Functional units for "R600_VLIW4_Itin"
112namespace R600_VLIW4_ItinFU {
113
114 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
115 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
116 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
117 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
118 const InstrStage::FuncUnits ALU_NULL = 1ULL << 4;
119
120} // namespace R600_VLIW4_ItinFU
121
122extern const llvm::InstrStage R600Stages[] = {
123 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
124 { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
125 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
126 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
127 { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
128 { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
129 { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
130 { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
131 { 0, 0, 0, llvm::InstrStage::Required } // End stages
132};
133extern const unsigned R600OperandCycles[] = {
134 0, // No itinerary
135 0 // End operand cycles
136};
137extern const unsigned R600ForwardingPaths[] = {
138 0, // No itinerary
139 0 // End bypass tables
140};
141
142static constexpr llvm::InstrItinerary R600_VLIW5_Itin[] = {
143 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
144 { 1, 1, 2, 0, 0 }, // 1 NullALU
145 { 1, 2, 3, 0, 0 }, // 2 VecALU
146 { 1, 3, 4, 0, 0 }, // 3 AnyALU
147 { 1, 4, 5, 0, 0 }, // 4 TransALU
148 { 1, 5, 6, 0, 0 }, // 5 XALU
149 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
150};
151
152static constexpr llvm::InstrItinerary R600_VLIW4_Itin[] = {
153 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
154 { 1, 6, 7, 0, 0 }, // 1 NullALU
155 { 1, 7, 8, 0, 0 }, // 2 VecALU
156 { 1, 7, 8, 0, 0 }, // 3 AnyALU
157 { 1, 6, 7, 0, 0 }, // 4 TransALU
158 { 0, 0, 0, 0, 0 }, // 5 XALU
159 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
160};
161
162// ===============================================================
163// Data tables for the new per-operand machine model.
164
165// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
166extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
167 { 0, 0, 0 }, // Invalid
168}; // R600WriteProcResTable
169
170// {Cycles, WriteResourceID}
171extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
172 { 0, 0}, // Invalid
173}; // R600WriteLatencyTable
174
175// {UseIdx, WriteResourceID, Cycles}
176extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
177 {0, 0, 0}, // Invalid
178}; // R600ReadAdvanceTable
179
180#ifdef __GNUC__
181#pragma GCC diagnostic push
182#pragma GCC diagnostic ignored "-Woverlength-strings"
183#endif
184static constexpr char R600SchedClassNamesStorage[] =
185 "\0"
186 "InvalidSchedClass\0"
187 ;
188#ifdef __GNUC__
189#pragma GCC diagnostic pop
190#endif
191
192static constexpr llvm::StringTable
193R600SchedClassNames = R600SchedClassNamesStorage;
194
195static const llvm::MCSchedModel NoSchedModel = {
196 MCSchedModel::DefaultIssueWidth,
197 MCSchedModel::DefaultMicroOpBufferSize,
198 MCSchedModel::DefaultLoopMicroOpBufferSize,
199 MCSchedModel::DefaultLoadLatency,
200 MCSchedModel::DefaultHighLatency,
201 MCSchedModel::DefaultMispredictPenalty,
202 false, // PostRAScheduler
203 false, // CompleteModel
204 false, // EnableIntervals
205 0, // Processor ID
206 nullptr, nullptr, 0, 0, // No instruction-level machine model.
207 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
208 nullptr, // No Itinerary
209 nullptr // No extra processor descriptor
210};
211
212static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
213 MCSchedModel::DefaultIssueWidth,
214 MCSchedModel::DefaultMicroOpBufferSize,
215 MCSchedModel::DefaultLoopMicroOpBufferSize,
216 MCSchedModel::DefaultLoadLatency,
217 MCSchedModel::DefaultHighLatency,
218 MCSchedModel::DefaultMispredictPenalty,
219 false, // PostRAScheduler
220 false, // CompleteModel
221 false, // EnableIntervals
222 1, // Processor ID
223 nullptr, nullptr, 0, 0, // No instruction-level machine model.
224 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
225 R600_VLIW5_Itin,
226 nullptr // No extra processor descriptor
227};
228
229static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
230 MCSchedModel::DefaultIssueWidth,
231 MCSchedModel::DefaultMicroOpBufferSize,
232 MCSchedModel::DefaultLoopMicroOpBufferSize,
233 MCSchedModel::DefaultLoadLatency,
234 MCSchedModel::DefaultHighLatency,
235 MCSchedModel::DefaultMispredictPenalty,
236 false, // PostRAScheduler
237 false, // CompleteModel
238 false, // EnableIntervals
239 2, // Processor ID
240 nullptr, nullptr, 0, 0, // No instruction-level machine model.
241 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
242 R600_VLIW4_Itin,
243 nullptr // No extra processor descriptor
244};
245
246#undef DBGFIELD
247
248#undef DBGVAL_OR_NULLPTR
249
250// Sorted (by key) array of values for CPU subtype.
251extern const llvm::SubtargetSubTypeKV R600SubTypeKV[] = {
252 { "barts", { { { 0x11010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
253 { "caicos", { { { 0x1010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
254 { "cayman", { { { 0x10a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW4_ItinModel },
255 { "cedar", { { { 0x50050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
256 { "cypress", { { { 0x900c0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
257 { "juniper", { { { 0x90040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
258 { "r600", { { { 0x92000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
259 { "r630", { { { 0x52000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
260 { "redwood", { { { 0x90050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
261 { "rs880", { { { 0x22000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
262 { "rv670", { { { 0x92000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
263 { "rv710", { { { 0x58000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
264 { "rv730", { { { 0x58000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
265 { "rv770", { { { 0x98000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
266 { "sumo", { { { 0x80050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
267 { "turks", { { { 0x11010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
268};
269
270// Sorted array of names of CPU subtypes, including aliases.
271extern const llvm::StringRef R600Names[] = {
272"barts",
273"caicos",
274"cayman",
275"cedar",
276"cypress",
277"juniper",
278"r600",
279"r630",
280"redwood",
281"rs880",
282"rv670",
283"rv710",
284"rv730",
285"rv770",
286"sumo",
287"turks"};
288
289namespace R600_MC {
290
291unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
292 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
293 // Don't know how to resolve this scheduling class.
294 return 0;
295}
296
297} // namespace R600_MC
298struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
299 R600GenMCSubtargetInfo(const Triple &TT,
300 StringRef CPU, StringRef TuneCPU, StringRef FS,
301 ArrayRef<StringRef> PN,
302 ArrayRef<SubtargetFeatureKV> PF,
303 ArrayRef<SubtargetSubTypeKV> PD,
304 const MCWriteProcResEntry *WPR,
305 const MCWriteLatencyEntry *WL,
306 const MCReadAdvanceEntry *RA, const InstrStage *IS,
307 const unsigned *OC, const unsigned *FP) :
308 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
309 WPR, WL, RA, IS, OC, FP) { }
310
311 unsigned resolveVariantSchedClass(unsigned SchedClass,
312 const MCInst *MI, const MCInstrInfo *MCII,
313 unsigned CPUID) const final {
314 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
315 }
316};
317
318static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
319 return new R600GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, R600Names, R600FeatureKV, R600SubTypeKV,
320 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
321 R600Stages, R600OperandCycles, R600ForwardingPaths);
322}
323
324
325} // namespace llvm
326
327#endif // GET_SUBTARGETINFO_MC_DESC
328
329#ifdef GET_SUBTARGETINFO_TARGET_DESC
330#undef GET_SUBTARGETINFO_TARGET_DESC
331
332#include "llvm/ADT/BitmaskEnum.h"
333#include "llvm/Support/Debug.h"
334#include "llvm/Support/raw_ostream.h"
335
336// ParseSubtargetFeatures - Parses features string setting specified
337// subtarget options.
338void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
339 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
340 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
341 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
342 InitMCProcessorInfo(CPU, TuneCPU, FS);
343 const FeatureBitset &Bits = getFeatureBits();
344 if (Bits[R600::FeatureAddressableLocalMemorySize32768] && AddressableLocalMemorySize < 32768) AddressableLocalMemorySize = 32768;
345 if (Bits[R600::FeatureAddressableLocalMemorySize65536] && AddressableLocalMemorySize < 65536) AddressableLocalMemorySize = 65536;
346 if (Bits[R600::FeatureAddressableLocalMemorySize163840] && AddressableLocalMemorySize < 163840) AddressableLocalMemorySize = 163840;
347 if (Bits[R600::FeatureAddressableLocalMemorySize327680] && AddressableLocalMemorySize < 327680) AddressableLocalMemorySize = 327680;
348 if (Bits[R600::FeatureCFALUBug]) HasCFALUBug = true;
349 if (Bits[R600::FeatureCaymanISA]) HasCaymanISA = true;
350 if (Bits[R600::FeatureEvergreen] && Gen < R600Subtarget::EVERGREEN) Gen = R600Subtarget::EVERGREEN;
351 if (Bits[R600::FeatureFMA]) HasFMA = true;
352 if (Bits[R600::FeatureFP64]) HasFP64 = true;
353 if (Bits[R600::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
354 if (Bits[R600::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
355 if (Bits[R600::FeatureMadMacF32Insts]) HasMadMacF32Insts = true;
356 if (Bits[R600::FeatureNorthernIslands] && Gen < R600Subtarget::NORTHERN_ISLANDS) Gen = R600Subtarget::NORTHERN_ISLANDS;
357 if (Bits[R600::FeatureR600] && Gen < R600Subtarget::R600) Gen = R600Subtarget::R600;
358 if (Bits[R600::FeatureR600ALUInst]) HasR600ALUInst = false;
359 if (Bits[R600::FeatureR700] && Gen < R600Subtarget::R700) Gen = R600Subtarget::R700;
360 if (Bits[R600::FeatureVertexCache]) HasVertexCache = true;
361 if (Bits[R600::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4;
362 if (Bits[R600::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5;
363 if (Bits[R600::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6;
364}
365
366#endif // GET_SUBTARGETINFO_TARGET_DESC
367
368#ifdef GET_SUBTARGETINFO_HEADER
369#undef GET_SUBTARGETINFO_HEADER
370
371namespace llvm {
372
373class DFAPacketizer;
374namespace R600_MC {
375
376unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
377
378} // namespace R600_MC
379struct R600GenSubtargetInfo : public TargetSubtargetInfo {
380 explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
381public:
382 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
383 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
384 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
385};
386
387} // namespace llvm
388
389#endif // GET_SUBTARGETINFO_HEADER
390
391#ifdef GET_SUBTARGETINFO_CTOR
392#undef GET_SUBTARGETINFO_CTOR
393
394#include "llvm/CodeGen/TargetSchedule.h"
395
396namespace llvm {
397
398extern const llvm::StringRef R600Names[];
399extern const llvm::SubtargetFeatureKV R600FeatureKV[];
400extern const llvm::SubtargetSubTypeKV R600SubTypeKV[];
401extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
402extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
403extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
404extern const llvm::InstrStage R600Stages[];
405extern const unsigned R600OperandCycles[];
406extern const unsigned R600ForwardingPaths[];
407R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
408 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(R600Names, 16), ArrayRef(R600FeatureKV, 20), ArrayRef(R600SubTypeKV, 16),
409 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
410 R600Stages, R600OperandCycles, R600ForwardingPaths) {}
411
412unsigned R600GenSubtargetInfo
413::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
414 report_fatal_error("Expected a variant SchedClass");
415} // R600GenSubtargetInfo::resolveSchedClass
416
417unsigned R600GenSubtargetInfo
418::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
419 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
420} // R600GenSubtargetInfo::resolveVariantSchedClass
421
422
423} // namespace llvm
424
425#endif // GET_SUBTARGETINFO_CTOR
426
427#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
428#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
429
430
431#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
432
433#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
434#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
435
436
437#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
438
439