1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace R600 {
15
16enum {
17 FeatureAddressableLocalMemorySize32768 = 0,
18 FeatureAddressableLocalMemorySize65536 = 1,
19 FeatureAddressableLocalMemorySize163840 = 2,
20 FeatureAddressableLocalMemorySize196608 = 3,
21 FeatureAddressableLocalMemorySize327680 = 4,
22 FeatureCFALUBug = 5,
23 FeatureCaymanISA = 6,
24 FeatureEvergreen = 7,
25 FeatureFMA = 8,
26 FeatureFP64 = 9,
27 FeatureFetchLimit8 = 10,
28 FeatureFetchLimit16 = 11,
29 FeatureFlatOffsetBits12 = 12,
30 FeatureFlatOffsetBits24 = 13,
31 FeatureLDSAllocGranularity256 = 14,
32 FeatureLDSAllocGranularity512 = 15,
33 FeatureLDSAllocGranularity1024 = 16,
34 FeatureLDSAllocGranularity1280 = 17,
35 FeatureLDSAllocGranularity2048 = 18,
36 FeatureLDSEncodingGranularity256 = 19,
37 FeatureLDSEncodingGranularity512 = 20,
38 FeatureLDSEncodingGranularity1024 = 21,
39 FeatureLDSEncodingGranularity1280 = 22,
40 FeatureLDSEncodingGranularity2048 = 23,
41 FeatureMadMacF32Insts = 24,
42 FeatureNorthernIslands = 25,
43 FeatureR600 = 26,
44 FeatureR600ALUInst = 27,
45 FeatureR700 = 28,
46 FeatureSupportsWave32 = 29,
47 FeatureSupportsWave64 = 30,
48 FeatureVertexCache = 31,
49 FeatureWavefrontSize16 = 32,
50 FeatureWavefrontSize32 = 33,
51 FeatureWavefrontSize64 = 34,
52 NumSubtargetFeatures = 35
53};
54
55} // namespace R600
56
57} // namespace llvm
58
59#endif // GET_SUBTARGETINFO_ENUM
60
61#ifdef GET_SUBTARGETINFO_MACRO
62
63GET_SUBTARGETINFO_MACRO(HasCFALUBug, false, hasCFALUBug)
64GET_SUBTARGETINFO_MACRO(HasCaymanISA, false, hasCaymanISA)
65GET_SUBTARGETINFO_MACRO(HasFMA, false, hasFMA)
66GET_SUBTARGETINFO_MACRO(HasFP64, false, hasFP64)
67GET_SUBTARGETINFO_MACRO(HasMadMacF32Insts, false, hasMadMacF32Insts)
68GET_SUBTARGETINFO_MACRO(HasR600ALUInst, true, hasR600ALUInst)
69GET_SUBTARGETINFO_MACRO(HasVertexCache, false, hasVertexCache)
70GET_SUBTARGETINFO_MACRO(SupportsWave32, false, supportsWave32)
71GET_SUBTARGETINFO_MACRO(SupportsWave64, false, supportsWave64)
72
73#undef GET_SUBTARGETINFO_MACRO
74#endif // GET_SUBTARGETINFO_MACRO
75
76#ifdef GET_SUBTARGETINFO_MC_DESC
77#undef GET_SUBTARGETINFO_MC_DESC
78
79namespace llvm {
80
81// Sorted (by key) array of values for CPU features.
82extern const llvm::SubtargetFeatureKVStorage< 35, 1413> R600FeatureKVStorage = {
83 {
84 { sizeof(SubtargetFeatureKV) * 35 + 1, sizeof(SubtargetFeatureKV) * 35 + 16, R600::FeatureVertexCache, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { sizeof(SubtargetFeatureKV) * 34 + 54, sizeof(SubtargetFeatureKV) * 34 + 66, R600::FeatureR600ALUInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { sizeof(SubtargetFeatureKV) * 33 + 109, sizeof(SubtargetFeatureKV) * 33 + 142, R600::FeatureAddressableLocalMemorySize163840, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { sizeof(SubtargetFeatureKV) * 32 + 176, sizeof(SubtargetFeatureKV) * 32 + 142, R600::FeatureAddressableLocalMemorySize196608, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { sizeof(SubtargetFeatureKV) * 31 + 209, sizeof(SubtargetFeatureKV) * 31 + 142, R600::FeatureAddressableLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { sizeof(SubtargetFeatureKV) * 30 + 241, sizeof(SubtargetFeatureKV) * 30 + 142, R600::FeatureAddressableLocalMemorySize327680, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { sizeof(SubtargetFeatureKV) * 29 + 274, sizeof(SubtargetFeatureKV) * 29 + 142, R600::FeatureAddressableLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 { sizeof(SubtargetFeatureKV) * 28 + 306, sizeof(SubtargetFeatureKV) * 28 + 316, R600::FeatureCaymanISA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
92 { sizeof(SubtargetFeatureKV) * 27 + 331, sizeof(SubtargetFeatureKV) * 27 + 340, R600::FeatureCFALUBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
93 { sizeof(SubtargetFeatureKV) * 26 + 359, sizeof(SubtargetFeatureKV) * 26 + 369, R600::FeatureEvergreen, { { { 0x1084801ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
94 { sizeof(SubtargetFeatureKV) * 25 + 394, sizeof(SubtargetFeatureKV) * 25 + 402, R600::FeatureFetchLimit16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
95 { sizeof(SubtargetFeatureKV) * 24 + 456, sizeof(SubtargetFeatureKV) * 24 + 463, R600::FeatureFetchLimit8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
96 { sizeof(SubtargetFeatureKV) * 23 + 516, sizeof(SubtargetFeatureKV) * 23 + 536, R600::FeatureFlatOffsetBits12, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
97 { sizeof(SubtargetFeatureKV) * 22 + 576, sizeof(SubtargetFeatureKV) * 22 + 536, R600::FeatureFlatOffsetBits24, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
98 { sizeof(SubtargetFeatureKV) * 21 + 596, sizeof(SubtargetFeatureKV) * 21 + 601, R600::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
99 { sizeof(SubtargetFeatureKV) * 20 + 665, sizeof(SubtargetFeatureKV) * 20 + 670, R600::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
100 { sizeof(SubtargetFeatureKV) * 19 + 705, sizeof(SubtargetFeatureKV) * 19 + 732, R600::FeatureLDSAllocGranularity1024, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
101 { sizeof(SubtargetFeatureKV) * 18 + 769, sizeof(SubtargetFeatureKV) * 18 + 732, R600::FeatureLDSAllocGranularity1280, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
102 { sizeof(SubtargetFeatureKV) * 17 + 796, sizeof(SubtargetFeatureKV) * 17 + 732, R600::FeatureLDSAllocGranularity2048, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
103 { sizeof(SubtargetFeatureKV) * 16 + 823, sizeof(SubtargetFeatureKV) * 16 + 732, R600::FeatureLDSAllocGranularity256, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
104 { sizeof(SubtargetFeatureKV) * 15 + 849, sizeof(SubtargetFeatureKV) * 15 + 732, R600::FeatureLDSAllocGranularity512, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
105 { sizeof(SubtargetFeatureKV) * 14 + 875, sizeof(SubtargetFeatureKV) * 14 + 905, R600::FeatureLDSEncodingGranularity1024, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
106 { sizeof(SubtargetFeatureKV) * 13 + 940, sizeof(SubtargetFeatureKV) * 13 + 905, R600::FeatureLDSEncodingGranularity1280, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
107 { sizeof(SubtargetFeatureKV) * 12 + 970, sizeof(SubtargetFeatureKV) * 12 + 905, R600::FeatureLDSEncodingGranularity2048, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
108 { sizeof(SubtargetFeatureKV) * 11 + 1000, sizeof(SubtargetFeatureKV) * 11 + 905, R600::FeatureLDSEncodingGranularity256, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
109 { sizeof(SubtargetFeatureKV) * 10 + 1029, sizeof(SubtargetFeatureKV) * 10 + 905, R600::FeatureLDSEncodingGranularity512, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
110 { sizeof(SubtargetFeatureKV) * 9 + 1058, sizeof(SubtargetFeatureKV) * 9 + 1076, R600::FeatureMadMacF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
111 { sizeof(SubtargetFeatureKV) * 8 + 1137, sizeof(SubtargetFeatureKV) * 8 + 1154, R600::FeatureNorthernIslands, { { { 0x401084801ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
112 { sizeof(SubtargetFeatureKV) * 7 + 1186, sizeof(SubtargetFeatureKV) * 7 + 1191, R600::FeatureR600, { { { 0x9000400ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
113 { sizeof(SubtargetFeatureKV) * 6 + 1211, sizeof(SubtargetFeatureKV) * 6 + 1216, R600::FeatureR700, { { { 0x1000800ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
114 { sizeof(SubtargetFeatureKV) * 5 + 1236, sizeof(SubtargetFeatureKV) * 5 + 1252, R600::FeatureSupportsWave32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
115 { sizeof(SubtargetFeatureKV) * 4 + 1282, sizeof(SubtargetFeatureKV) * 4 + 1298, R600::FeatureSupportsWave64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
116 { sizeof(SubtargetFeatureKV) * 3 + 1328, sizeof(SubtargetFeatureKV) * 3 + 1344, R600::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
117 { sizeof(SubtargetFeatureKV) * 2 + 1380, sizeof(SubtargetFeatureKV) * 2 + 1344, R600::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
118 { sizeof(SubtargetFeatureKV) * 1 + 1396, sizeof(SubtargetFeatureKV) * 1 + 1344, R600::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
119 },
120 "\000HasVertexCache\000Specify use of dedicated vertex cache\000R600ALUI"
121 "nst\000Older version of ALU instructions encoding\000addressablelocalme"
122 "morysize163840\000The size of local memory in bytes\000addressablelocal"
123 "memorysize196608\000addressablelocalmemorysize32768\000addressablelocal"
124 "memorysize327680\000addressablelocalmemorysize65536\000caymanISA\000Use"
125 " Cayman ISA\000cfalubug\000GPU has CF_ALU bug\000evergreen\000EVERGREEN"
126 " GPU generation\000fetch16\000Limit the maximum number of fetches in a "
127 "clause to 16\000fetch8\000Limit the maximum number of fetches in a clau"
128 "se to 8\000flat-offset-bits-12\000Number of bits for flat offset encodi"
129 "ng\000flat-offset-bits-24\000fmaf\000Enable single precision FMA (not a"
130 "s fast as mul+add, but fused)\000fp64\000Enable double precision operat"
131 "ions\000lds-alloc-granularity-1024\000LDS allocation granularity in byt"
132 "es.\000lds-alloc-granularity-1280\000lds-alloc-granularity-2048\000lds-"
133 "alloc-granularity-256\000lds-alloc-granularity-512\000lds-encoding-gran"
134 "ularity-1024\000LDS encoding granularity in bytes.\000lds-encoding-gran"
135 "ularity-1280\000lds-encoding-granularity-2048\000lds-encoding-granulari"
136 "ty-256\000lds-encoding-granularity-512\000mad-mac-f32-insts\000Has v_ma"
137 "d_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions\000northern-island"
138 "s\000NORTHERN_ISLANDS GPU generation\000r600\000R600 GPU generation\000"
139 "r700\000R700 GPU generation\000supports-wave32\000Hardware supports wav"
140 "e32 mode\000supports-wave64\000Hardware supports wave64 mode\000wavefro"
141 "ntsize16\000The number of threads per wavefront\000wavefrontsize32\000w"
142 "avefrontsize64\000"};
143
144#ifdef DBGFIELD
145#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
146#endif
147#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
148#define DBGFIELD(x) x,
149#define DBGVAL_OR_NULLPTR(x) x
150#else
151#define DBGFIELD(x)
152#define DBGVAL_OR_NULLPTR(x) nullptr
153#endif
154
155// Functional units for "R600_VLIW5_Itin"
156namespace R600_VLIW5_ItinFU {
157
158 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
159 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
160 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
161 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
162 const InstrStage::FuncUnits TRANS = 1ULL << 4;
163 const InstrStage::FuncUnits ALU_NULL = 1ULL << 5;
164
165} // namespace R600_VLIW5_ItinFU
166
167// Functional units for "R600_VLIW4_Itin"
168namespace R600_VLIW4_ItinFU {
169
170 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
171 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
172 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
173 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
174 const InstrStage::FuncUnits ALU_NULL = 1ULL << 4;
175
176} // namespace R600_VLIW4_ItinFU
177
178extern const llvm::InstrStage R600Stages[] = {
179 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
180 { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
181 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
182 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
183 { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
184 { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
185 { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
186 { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
187 { 0, 0, 0, llvm::InstrStage::Required } // End stages
188};
189extern const unsigned R600OperandCycles[] = {
190 0, // No itinerary
191 0 // End operand cycles
192};
193extern const unsigned R600ForwardingPaths[] = {
194 0, // No itinerary
195 0 // End bypass tables
196};
197
198static constexpr llvm::InstrItinerary R600_VLIW5_Itin[] = {
199 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
200 { 1, 1, 2, 0, 0 }, // 1 NullALU
201 { 1, 2, 3, 0, 0 }, // 2 VecALU
202 { 1, 3, 4, 0, 0 }, // 3 AnyALU
203 { 1, 4, 5, 0, 0 }, // 4 TransALU
204 { 1, 5, 6, 0, 0 }, // 5 XALU
205 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
206};
207
208static constexpr llvm::InstrItinerary R600_VLIW4_Itin[] = {
209 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
210 { 1, 6, 7, 0, 0 }, // 1 NullALU
211 { 1, 7, 8, 0, 0 }, // 2 VecALU
212 { 1, 7, 8, 0, 0 }, // 3 AnyALU
213 { 1, 6, 7, 0, 0 }, // 4 TransALU
214 { 0, 0, 0, 0, 0 }, // 5 XALU
215 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
216};
217
218// ===============================================================
219// Data tables for the new per-operand machine model.
220
221static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
222static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
223
224// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
225extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
226 { 0, 0, 0 }, // Invalid
227}; // R600WriteProcResTable
228
229// {Cycles, WriteResourceID}
230extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
231 { 0, 0}, // Invalid
232}; // R600WriteLatencyTable
233
234// {UseIdx, WriteResourceID, Cycles}
235extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
236 {0, 0, 0}, // Invalid
237}; // R600ReadAdvanceTable
238
239#ifdef __GNUC__
240#pragma GCC diagnostic push
241#pragma GCC diagnostic ignored "-Woverlength-strings"
242#endif
243static constexpr char R600SchedClassNamesStorage[] =
244 "\0"
245 "InvalidSchedClass\0"
246 ;
247#ifdef __GNUC__
248#pragma GCC diagnostic pop
249#endif
250
251static constexpr llvm::StringTable
252R600SchedClassNames = R600SchedClassNamesStorage;
253
254extern const llvm::MCSchedModel R600SchedModels[] = {
255{ // NoSchedModel
256 MCSchedModel::DefaultIssueWidth,
257 MCSchedModel::DefaultMicroOpBufferSize,
258 MCSchedModel::DefaultLoopMicroOpBufferSize,
259 MCSchedModel::DefaultLoadLatency,
260 MCSchedModel::DefaultHighLatency,
261 MCSchedModel::DefaultMispredictPenalty,
262 false, // PostRAScheduler
263 false, // CompleteModel
264 false, // EnableIntervals
265 0, // Processor ID
266 nullptr, nullptr, 0, 0, // No instruction-level machine model.
267 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
268 nullptr, // No Itinerary
269 nullptr // No extra processor descriptor
270 },
271{ // R600_VLIW5_ItinModel
272 MCSchedModel::DefaultIssueWidth,
273 MCSchedModel::DefaultMicroOpBufferSize,
274 MCSchedModel::DefaultLoopMicroOpBufferSize,
275 MCSchedModel::DefaultLoadLatency,
276 MCSchedModel::DefaultHighLatency,
277 MCSchedModel::DefaultMispredictPenalty,
278 false, // PostRAScheduler
279 false, // CompleteModel
280 false, // EnableIntervals
281 1, // Processor ID
282 nullptr, nullptr, 0, 0, // No instruction-level machine model.
283 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
284 R600_VLIW5_Itin,
285 nullptr // No extra processor descriptor
286 },
287{ // R600_VLIW4_ItinModel
288 MCSchedModel::DefaultIssueWidth,
289 MCSchedModel::DefaultMicroOpBufferSize,
290 MCSchedModel::DefaultLoopMicroOpBufferSize,
291 MCSchedModel::DefaultLoadLatency,
292 MCSchedModel::DefaultHighLatency,
293 MCSchedModel::DefaultMispredictPenalty,
294 false, // PostRAScheduler
295 false, // CompleteModel
296 false, // EnableIntervals
297 2, // Processor ID
298 nullptr, nullptr, 0, 0, // No instruction-level machine model.
299 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
300 R600_VLIW4_Itin,
301 nullptr // No extra processor descriptor
302 },
303};
304
305#undef DBGFIELD
306
307#undef DBGVAL_OR_NULLPTR
308
309static constexpr size_t R600CPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 10>);
310// Sorted (by key) array of values for CPU subtype.
311extern const llvm::SubtargetSubTypeKVStorage< 16, 10, 164> R600SubTypeKVStorage = {
312 {
313 { sizeof(SubtargetSubTypeKV) * 16 + R600CPUAliasArraySize + 7, { { { 0x82000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
314 { sizeof(SubtargetSubTypeKV) * 15 + R600CPUAliasArraySize + 13, { { { 0x2000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
315 { sizeof(SubtargetSubTypeKV) * 14 + R600CPUAliasArraySize + 20, { { { 0x2000140ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 },
316 { sizeof(SubtargetSubTypeKV) * 13 + R600CPUAliasArraySize + 27, { { { 0x2800000a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
317 { sizeof(SubtargetSubTypeKV) * 12 + R600CPUAliasArraySize + 33, { { { 0x480000180ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
318 { sizeof(SubtargetSubTypeKV) * 11 + R600CPUAliasArraySize + 49, { { { 0x480000080ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
319 { sizeof(SubtargetSubTypeKV) * 10 + R600CPUAliasArraySize + 62, { { { 0x484000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
320 { sizeof(SubtargetSubTypeKV) * 9 + R600CPUAliasArraySize + 67, { { { 0x284000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
321 { sizeof(SubtargetSubTypeKV) * 8 + R600CPUAliasArraySize + 72, { { { 0x4800000a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
322 { sizeof(SubtargetSubTypeKV) * 7 + R600CPUAliasArraySize + 86, { { { 0x104000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
323 { sizeof(SubtargetSubTypeKV) * 6 + R600CPUAliasArraySize + 116, { { { 0x484000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
324 { sizeof(SubtargetSubTypeKV) * 5 + R600CPUAliasArraySize + 122, { { { 0x290000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
325 { sizeof(SubtargetSubTypeKV) * 4 + R600CPUAliasArraySize + 128, { { { 0x290000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
326 { sizeof(SubtargetSubTypeKV) * 3 + R600CPUAliasArraySize + 140, { { { 0x490000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
327 { sizeof(SubtargetSubTypeKV) * 2 + R600CPUAliasArraySize + 146, { { { 0x4000000a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
328 { sizeof(SubtargetSubTypeKV) * 1 + R600CPUAliasArraySize + 157, { { { 0x82000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
329 },
330 { {
331 { sizeof(SubtargetSubTypeAliasKV) * 10 + 1, 2 },
332 { sizeof(SubtargetSubTypeAliasKV) * 9 + 41, 4 },
333 { sizeof(SubtargetSubTypeAliasKV) * 8 + 57, 3 },
334 { sizeof(SubtargetSubTypeAliasKV) * 7 + 80, 9 },
335 { sizeof(SubtargetSubTypeAliasKV) * 6 + 92, 9 },
336 { sizeof(SubtargetSubTypeAliasKV) * 5 + 98, 9 },
337 { sizeof(SubtargetSubTypeAliasKV) * 4 + 104, 6 },
338 { sizeof(SubtargetSubTypeAliasKV) * 3 + 110, 6 },
339 { sizeof(SubtargetSubTypeAliasKV) * 2 + 134, 13 },
340 { sizeof(SubtargetSubTypeAliasKV) * 1 + 151, 14 },
341 } },
342 "\000aruba\000barts\000caicos\000cayman\000cedar\000cypress\000hemlock\000"
343 "juniper\000palm\000r600\000r630\000redwood\000rs780\000rs880\000rv610\000"
344 "rv620\000rv630\000rv635\000rv670\000rv710\000rv730\000rv740\000rv770\000"
345 "sumo\000sumo2\000turks\000"};
346
347namespace R600_MC {
348
349unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
350 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
351 // Don't know how to resolve this scheduling class.
352 return 0;
353}
354
355} // namespace R600_MC
356struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
357 R600GenMCSubtargetInfo(const Triple &TT,
358 StringRef CPU, StringRef TuneCPU, StringRef FS,
359 StringTable PN,
360 ArrayRef<SubtargetFeatureKV> PF,
361 ArrayRef<SubtargetSubTypeKV> PD,
362 ArrayRef<SubtargetSubTypeAliasKV> PA,
363 const MCSchedModel *PSM,
364 const MCWriteProcResEntry *WPR,
365 const MCWriteLatencyEntry *WL,
366 const MCReadAdvanceEntry *RA, const InstrStage *IS,
367 const unsigned *OC, const unsigned *FP) :
368 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
369 WPR, WL, RA, IS, OC, FP) { }
370
371 unsigned resolveVariantSchedClass(unsigned SchedClass,
372 const MCInst *MI, const MCInstrInfo *MCII,
373 unsigned CPUID) const final {
374 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
375 }
376};
377
378static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
379 return new R600GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(R600SubTypeKVStorage.Strings), R600FeatureKVStorage.Features, R600SubTypeKVStorage.SubTypes, ArrayRef(R600SubTypeKVStorage.Aliases).take_front(10), R600SchedModels,
380 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
381 R600Stages, R600OperandCycles, R600ForwardingPaths);
382}
383
384
385} // namespace llvm
386
387#endif // GET_SUBTARGETINFO_MC_DESC
388
389#ifdef GET_SUBTARGETINFO_TARGET_DESC
390#undef GET_SUBTARGETINFO_TARGET_DESC
391
392#include "llvm/ADT/BitmaskEnum.h"
393#include "llvm/Support/Debug.h"
394#include "llvm/Support/raw_ostream.h"
395
396// ParseSubtargetFeatures - Parses features string setting specified
397// subtarget options.
398void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
399 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
400 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
401 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
402 InitMCProcessorInfo(CPU, TuneCPU, FS);
403 const FeatureBitset &Bits = getFeatureBits();
404 if (Bits[R600::FeatureAddressableLocalMemorySize32768] && AddressableLocalMemorySize < 32768) AddressableLocalMemorySize = 32768;
405 if (Bits[R600::FeatureAddressableLocalMemorySize65536] && AddressableLocalMemorySize < 65536) AddressableLocalMemorySize = 65536;
406 if (Bits[R600::FeatureAddressableLocalMemorySize163840] && AddressableLocalMemorySize < 163840) AddressableLocalMemorySize = 163840;
407 if (Bits[R600::FeatureAddressableLocalMemorySize196608] && AddressableLocalMemorySize < 196608) AddressableLocalMemorySize = 196608;
408 if (Bits[R600::FeatureAddressableLocalMemorySize327680] && AddressableLocalMemorySize < 327680) AddressableLocalMemorySize = 327680;
409 if (Bits[R600::FeatureCFALUBug]) HasCFALUBug = true;
410 if (Bits[R600::FeatureCaymanISA]) HasCaymanISA = true;
411 if (Bits[R600::FeatureEvergreen] && Gen < R600Subtarget::EVERGREEN) Gen = R600Subtarget::EVERGREEN;
412 if (Bits[R600::FeatureFMA]) HasFMA = true;
413 if (Bits[R600::FeatureFP64]) HasFP64 = true;
414 if (Bits[R600::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
415 if (Bits[R600::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
416 if (Bits[R600::FeatureFlatOffsetBits12] && FlatOffsetBitWidth < 12) FlatOffsetBitWidth = 12;
417 if (Bits[R600::FeatureFlatOffsetBits24] && FlatOffsetBitWidth < 24) FlatOffsetBitWidth = 24;
418 if (Bits[R600::FeatureLDSAllocGranularity256] && LDSAllocationGranularity < 256) LDSAllocationGranularity = 256;
419 if (Bits[R600::FeatureLDSAllocGranularity512] && LDSAllocationGranularity < 512) LDSAllocationGranularity = 512;
420 if (Bits[R600::FeatureLDSAllocGranularity1024] && LDSAllocationGranularity < 1024) LDSAllocationGranularity = 1024;
421 if (Bits[R600::FeatureLDSAllocGranularity1280] && LDSAllocationGranularity < 1280) LDSAllocationGranularity = 1280;
422 if (Bits[R600::FeatureLDSAllocGranularity2048] && LDSAllocationGranularity < 2048) LDSAllocationGranularity = 2048;
423 if (Bits[R600::FeatureLDSEncodingGranularity256] && LDSEncodingGranularity < 256) LDSEncodingGranularity = 256;
424 if (Bits[R600::FeatureLDSEncodingGranularity512] && LDSEncodingGranularity < 512) LDSEncodingGranularity = 512;
425 if (Bits[R600::FeatureLDSEncodingGranularity1024] && LDSEncodingGranularity < 1024) LDSEncodingGranularity = 1024;
426 if (Bits[R600::FeatureLDSEncodingGranularity1280] && LDSEncodingGranularity < 1280) LDSEncodingGranularity = 1280;
427 if (Bits[R600::FeatureLDSEncodingGranularity2048] && LDSEncodingGranularity < 2048) LDSEncodingGranularity = 2048;
428 if (Bits[R600::FeatureMadMacF32Insts]) HasMadMacF32Insts = true;
429 if (Bits[R600::FeatureNorthernIslands] && Gen < R600Subtarget::NORTHERN_ISLANDS) Gen = R600Subtarget::NORTHERN_ISLANDS;
430 if (Bits[R600::FeatureR600] && Gen < R600Subtarget::R600) Gen = R600Subtarget::R600;
431 if (Bits[R600::FeatureR600ALUInst]) HasR600ALUInst = false;
432 if (Bits[R600::FeatureR700] && Gen < R600Subtarget::R700) Gen = R600Subtarget::R700;
433 if (Bits[R600::FeatureSupportsWave32]) SupportsWave32 = true;
434 if (Bits[R600::FeatureSupportsWave64]) SupportsWave64 = true;
435 if (Bits[R600::FeatureVertexCache]) HasVertexCache = true;
436 if (Bits[R600::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4;
437 if (Bits[R600::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5;
438 if (Bits[R600::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6;
439}
440
441#endif // GET_SUBTARGETINFO_TARGET_DESC
442
443#ifdef GET_SUBTARGETINFO_HEADER
444#undef GET_SUBTARGETINFO_HEADER
445
446namespace llvm {
447
448class DFAPacketizer;
449namespace R600_MC {
450
451unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
452
453} // namespace R600_MC
454struct R600GenSubtargetInfo : public TargetSubtargetInfo {
455 explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
456public:
457 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
458 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
459 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
460 const FeatureBitset &getInlineIgnoreFeatures() const override;
461 const FeatureBitset &getInlineInverseFeatures() const override;
462 const FeatureBitset &getInlineMustMatchFeatures() const override;
463};
464
465} // namespace llvm
466
467#endif // GET_SUBTARGETINFO_HEADER
468
469#ifdef GET_SUBTARGETINFO_CTOR
470#undef GET_SUBTARGETINFO_CTOR
471
472#include "llvm/CodeGen/TargetSchedule.h"
473
474namespace llvm {
475
476extern const llvm::StringRef R600Names[];
477extern const llvm::SubtargetFeatureKVStorage<35, 1413> R600FeatureKVStorage;
478extern const llvm::SubtargetSubTypeKVStorage<16, 10, 164> R600SubTypeKVStorage;
479extern const llvm::MCSchedModel R600SchedModels[];
480extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
481extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
482extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
483extern const llvm::InstrStage R600Stages[];
484extern const unsigned R600OperandCycles[];
485extern const unsigned R600ForwardingPaths[];
486R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
487 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(R600SubTypeKVStorage.Strings), ArrayRef(R600FeatureKVStorage.Features), ArrayRef(R600SubTypeKVStorage.SubTypes), ArrayRef(R600SubTypeKVStorage.Aliases).take_front(10), R600SchedModels,
488 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
489 R600Stages, R600OperandCycles, R600ForwardingPaths) {}
490
491unsigned R600GenSubtargetInfo
492::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
493 report_fatal_error("Expected a variant SchedClass");
494} // R600GenSubtargetInfo::resolveSchedClass
495
496unsigned R600GenSubtargetInfo
497::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
498 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
499} // R600GenSubtargetInfo::resolveVariantSchedClass
500
501const FeatureBitset &R600GenSubtargetInfo::getInlineIgnoreFeatures() const {
502 static constexpr FeatureBitset Features = {
503R600::FeatureSupportsWave32,
504R600::FeatureSupportsWave64,
505 };
506 return Features;
507}
508
509const FeatureBitset &R600GenSubtargetInfo::getInlineInverseFeatures() const {
510 static constexpr FeatureBitset Features = {
511 };
512 return Features;
513}
514
515const FeatureBitset &R600GenSubtargetInfo::getInlineMustMatchFeatures() const {
516 static constexpr FeatureBitset Features = {
517 };
518 return Features;
519}
520
521
522} // namespace llvm
523
524#endif // GET_SUBTARGETINFO_CTOR
525
526#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
527#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
528
529
530#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
531
532#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
533#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
534
535
536#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
537
538