1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace R600 {
15
16enum {
17 FeatureAddressableLocalMemorySize32768 = 0,
18 FeatureAddressableLocalMemorySize65536 = 1,
19 FeatureAddressableLocalMemorySize163840 = 2,
20 FeatureAddressableLocalMemorySize196608 = 3,
21 FeatureAddressableLocalMemorySize327680 = 4,
22 FeatureCFALUBug = 5,
23 FeatureCaymanISA = 6,
24 FeatureEvergreen = 7,
25 FeatureFMA = 8,
26 FeatureFP64 = 9,
27 FeatureFetchLimit8 = 10,
28 FeatureFetchLimit16 = 11,
29 FeatureFlatOffsetBits12 = 12,
30 FeatureFlatOffsetBits24 = 13,
31 FeatureMadMacF32Insts = 14,
32 FeatureNorthernIslands = 15,
33 FeatureR600 = 16,
34 FeatureR600ALUInst = 17,
35 FeatureR700 = 18,
36 FeatureSupportsWave32 = 19,
37 FeatureSupportsWave64 = 20,
38 FeatureVertexCache = 21,
39 FeatureWavefrontSize16 = 22,
40 FeatureWavefrontSize32 = 23,
41 FeatureWavefrontSize64 = 24,
42 NumSubtargetFeatures = 25
43};
44
45} // namespace R600
46
47} // namespace llvm
48
49#endif // GET_SUBTARGETINFO_ENUM
50
51#ifdef GET_SUBTARGETINFO_MACRO
52
53GET_SUBTARGETINFO_MACRO(HasCFALUBug, false, hasCFALUBug)
54GET_SUBTARGETINFO_MACRO(HasCaymanISA, false, hasCaymanISA)
55GET_SUBTARGETINFO_MACRO(HasFMA, false, hasFMA)
56GET_SUBTARGETINFO_MACRO(HasFP64, false, hasFP64)
57GET_SUBTARGETINFO_MACRO(HasMadMacF32Insts, false, hasMadMacF32Insts)
58GET_SUBTARGETINFO_MACRO(HasR600ALUInst, true, hasR600ALUInst)
59GET_SUBTARGETINFO_MACRO(HasVertexCache, false, hasVertexCache)
60GET_SUBTARGETINFO_MACRO(SupportsWave32, false, supportsWave32)
61GET_SUBTARGETINFO_MACRO(SupportsWave64, false, supportsWave64)
62
63#undef GET_SUBTARGETINFO_MACRO
64#endif // GET_SUBTARGETINFO_MACRO
65
66#ifdef GET_SUBTARGETINFO_MC_DESC
67#undef GET_SUBTARGETINFO_MC_DESC
68
69namespace llvm {
70
71// Sorted (by key) array of values for CPU features.
72extern const llvm::SubtargetFeatureKVStorage< 25, 1060> R600FeatureKVStorage = {
73 {
74 { sizeof(SubtargetFeatureKV) * 25 + 1, sizeof(SubtargetFeatureKV) * 25 + 16, R600::FeatureVertexCache, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { sizeof(SubtargetFeatureKV) * 24 + 54, sizeof(SubtargetFeatureKV) * 24 + 66, R600::FeatureR600ALUInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { sizeof(SubtargetFeatureKV) * 23 + 109, sizeof(SubtargetFeatureKV) * 23 + 142, R600::FeatureAddressableLocalMemorySize163840, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { sizeof(SubtargetFeatureKV) * 22 + 176, sizeof(SubtargetFeatureKV) * 22 + 142, R600::FeatureAddressableLocalMemorySize196608, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { sizeof(SubtargetFeatureKV) * 21 + 209, sizeof(SubtargetFeatureKV) * 21 + 142, R600::FeatureAddressableLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { sizeof(SubtargetFeatureKV) * 20 + 241, sizeof(SubtargetFeatureKV) * 20 + 142, R600::FeatureAddressableLocalMemorySize327680, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { sizeof(SubtargetFeatureKV) * 19 + 274, sizeof(SubtargetFeatureKV) * 19 + 142, R600::FeatureAddressableLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { sizeof(SubtargetFeatureKV) * 18 + 306, sizeof(SubtargetFeatureKV) * 18 + 316, R600::FeatureCaymanISA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { sizeof(SubtargetFeatureKV) * 17 + 331, sizeof(SubtargetFeatureKV) * 17 + 340, R600::FeatureCFALUBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { sizeof(SubtargetFeatureKV) * 16 + 359, sizeof(SubtargetFeatureKV) * 16 + 369, R600::FeatureEvergreen, { { { 0x4801ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { sizeof(SubtargetFeatureKV) * 15 + 394, sizeof(SubtargetFeatureKV) * 15 + 402, R600::FeatureFetchLimit16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { sizeof(SubtargetFeatureKV) * 14 + 456, sizeof(SubtargetFeatureKV) * 14 + 463, R600::FeatureFetchLimit8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { sizeof(SubtargetFeatureKV) * 13 + 516, sizeof(SubtargetFeatureKV) * 13 + 536, R600::FeatureFlatOffsetBits12, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { sizeof(SubtargetFeatureKV) * 12 + 576, sizeof(SubtargetFeatureKV) * 12 + 536, R600::FeatureFlatOffsetBits24, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { sizeof(SubtargetFeatureKV) * 11 + 596, sizeof(SubtargetFeatureKV) * 11 + 601, R600::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { sizeof(SubtargetFeatureKV) * 10 + 665, sizeof(SubtargetFeatureKV) * 10 + 670, R600::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { sizeof(SubtargetFeatureKV) * 9 + 705, sizeof(SubtargetFeatureKV) * 9 + 723, R600::FeatureMadMacF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 { sizeof(SubtargetFeatureKV) * 8 + 784, sizeof(SubtargetFeatureKV) * 8 + 801, R600::FeatureNorthernIslands, { { { 0x1004801ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
92 { sizeof(SubtargetFeatureKV) * 7 + 833, sizeof(SubtargetFeatureKV) * 7 + 838, R600::FeatureR600, { { { 0x24400ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
93 { sizeof(SubtargetFeatureKV) * 6 + 858, sizeof(SubtargetFeatureKV) * 6 + 863, R600::FeatureR700, { { { 0x4800ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
94 { sizeof(SubtargetFeatureKV) * 5 + 883, sizeof(SubtargetFeatureKV) * 5 + 899, R600::FeatureSupportsWave32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
95 { sizeof(SubtargetFeatureKV) * 4 + 929, sizeof(SubtargetFeatureKV) * 4 + 945, R600::FeatureSupportsWave64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
96 { sizeof(SubtargetFeatureKV) * 3 + 975, sizeof(SubtargetFeatureKV) * 3 + 991, R600::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
97 { sizeof(SubtargetFeatureKV) * 2 + 1027, sizeof(SubtargetFeatureKV) * 2 + 991, R600::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
98 { sizeof(SubtargetFeatureKV) * 1 + 1043, sizeof(SubtargetFeatureKV) * 1 + 991, R600::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
99 },
100 "\000HasVertexCache\000Specify use of dedicated vertex cache\000R600ALUI"
101 "nst\000Older version of ALU instructions encoding\000addressablelocalme"
102 "morysize163840\000The size of local memory in bytes\000addressablelocal"
103 "memorysize196608\000addressablelocalmemorysize32768\000addressablelocal"
104 "memorysize327680\000addressablelocalmemorysize65536\000caymanISA\000Use"
105 " Cayman ISA\000cfalubug\000GPU has CF_ALU bug\000evergreen\000EVERGREEN"
106 " GPU generation\000fetch16\000Limit the maximum number of fetches in a "
107 "clause to 16\000fetch8\000Limit the maximum number of fetches in a clau"
108 "se to 8\000flat-offset-bits-12\000Number of bits for flat offset encodi"
109 "ng\000flat-offset-bits-24\000fmaf\000Enable single precision FMA (not a"
110 "s fast as mul+add, but fused)\000fp64\000Enable double precision operat"
111 "ions\000mad-mac-f32-insts\000Has v_mad_f32/v_mac_f32/v_madak_f32/v_madm"
112 "k_f32 instructions\000northern-islands\000NORTHERN_ISLANDS GPU generati"
113 "on\000r600\000R600 GPU generation\000r700\000R700 GPU generation\000sup"
114 "ports-wave32\000Hardware supports wave32 mode\000supports-wave64\000Har"
115 "dware supports wave64 mode\000wavefrontsize16\000The number of threads "
116 "per wavefront\000wavefrontsize32\000wavefrontsize64\000"};
117
118#ifdef DBGFIELD
119#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
120#endif
121#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
122#define DBGFIELD(x) x,
123#define DBGVAL_OR_NULLPTR(x) x
124#else
125#define DBGFIELD(x)
126#define DBGVAL_OR_NULLPTR(x) nullptr
127#endif
128
129// Functional units for "R600_VLIW5_Itin"
130namespace R600_VLIW5_ItinFU {
131
132 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
133 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
134 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
135 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
136 const InstrStage::FuncUnits TRANS = 1ULL << 4;
137 const InstrStage::FuncUnits ALU_NULL = 1ULL << 5;
138
139} // namespace R600_VLIW5_ItinFU
140
141// Functional units for "R600_VLIW4_Itin"
142namespace R600_VLIW4_ItinFU {
143
144 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
145 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
146 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
147 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
148 const InstrStage::FuncUnits ALU_NULL = 1ULL << 4;
149
150} // namespace R600_VLIW4_ItinFU
151
152extern const llvm::InstrStage R600Stages[] = {
153 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
154 { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
155 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
156 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
157 { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
158 { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
159 { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
160 { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
161 { 0, 0, 0, llvm::InstrStage::Required } // End stages
162};
163extern const unsigned R600OperandCycles[] = {
164 0, // No itinerary
165 0 // End operand cycles
166};
167extern const unsigned R600ForwardingPaths[] = {
168 0, // No itinerary
169 0 // End bypass tables
170};
171
172static constexpr llvm::InstrItinerary R600_VLIW5_Itin[] = {
173 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
174 { 1, 1, 2, 0, 0 }, // 1 NullALU
175 { 1, 2, 3, 0, 0 }, // 2 VecALU
176 { 1, 3, 4, 0, 0 }, // 3 AnyALU
177 { 1, 4, 5, 0, 0 }, // 4 TransALU
178 { 1, 5, 6, 0, 0 }, // 5 XALU
179 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
180};
181
182static constexpr llvm::InstrItinerary R600_VLIW4_Itin[] = {
183 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
184 { 1, 6, 7, 0, 0 }, // 1 NullALU
185 { 1, 7, 8, 0, 0 }, // 2 VecALU
186 { 1, 7, 8, 0, 0 }, // 3 AnyALU
187 { 1, 6, 7, 0, 0 }, // 4 TransALU
188 { 0, 0, 0, 0, 0 }, // 5 XALU
189 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
190};
191
192// ===============================================================
193// Data tables for the new per-operand machine model.
194
195static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
196static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
197
198// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
199extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
200 { 0, 0, 0 }, // Invalid
201}; // R600WriteProcResTable
202
203// {Cycles, WriteResourceID}
204extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
205 { 0, 0}, // Invalid
206}; // R600WriteLatencyTable
207
208// {UseIdx, WriteResourceID, Cycles}
209extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
210 {0, 0, 0}, // Invalid
211}; // R600ReadAdvanceTable
212
213#ifdef __GNUC__
214#pragma GCC diagnostic push
215#pragma GCC diagnostic ignored "-Woverlength-strings"
216#endif
217static constexpr char R600SchedClassNamesStorage[] =
218 "\0"
219 "InvalidSchedClass\0"
220 ;
221#ifdef __GNUC__
222#pragma GCC diagnostic pop
223#endif
224
225static constexpr llvm::StringTable
226R600SchedClassNames = R600SchedClassNamesStorage;
227
228extern const llvm::MCSchedModel R600SchedModels[] = {
229{ // NoSchedModel
230 MCSchedModel::DefaultIssueWidth,
231 MCSchedModel::DefaultMicroOpBufferSize,
232 MCSchedModel::DefaultLoopMicroOpBufferSize,
233 MCSchedModel::DefaultLoadLatency,
234 MCSchedModel::DefaultHighLatency,
235 MCSchedModel::DefaultMispredictPenalty,
236 false, // PostRAScheduler
237 false, // CompleteModel
238 false, // EnableIntervals
239 0, // Processor ID
240 nullptr, nullptr, 0, 0, // No instruction-level machine model.
241 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
242 nullptr, // No Itinerary
243 nullptr // No extra processor descriptor
244 },
245{ // R600_VLIW5_ItinModel
246 MCSchedModel::DefaultIssueWidth,
247 MCSchedModel::DefaultMicroOpBufferSize,
248 MCSchedModel::DefaultLoopMicroOpBufferSize,
249 MCSchedModel::DefaultLoadLatency,
250 MCSchedModel::DefaultHighLatency,
251 MCSchedModel::DefaultMispredictPenalty,
252 false, // PostRAScheduler
253 false, // CompleteModel
254 false, // EnableIntervals
255 1, // Processor ID
256 nullptr, nullptr, 0, 0, // No instruction-level machine model.
257 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
258 R600_VLIW5_Itin,
259 nullptr // No extra processor descriptor
260 },
261{ // R600_VLIW4_ItinModel
262 MCSchedModel::DefaultIssueWidth,
263 MCSchedModel::DefaultMicroOpBufferSize,
264 MCSchedModel::DefaultLoopMicroOpBufferSize,
265 MCSchedModel::DefaultLoadLatency,
266 MCSchedModel::DefaultHighLatency,
267 MCSchedModel::DefaultMispredictPenalty,
268 false, // PostRAScheduler
269 false, // CompleteModel
270 false, // EnableIntervals
271 2, // Processor ID
272 nullptr, nullptr, 0, 0, // No instruction-level machine model.
273 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
274 R600_VLIW4_Itin,
275 nullptr // No extra processor descriptor
276 },
277};
278
279#undef DBGFIELD
280
281#undef DBGVAL_OR_NULLPTR
282
283static constexpr size_t R600CPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 10>);
284// Sorted (by key) array of values for CPU subtype.
285extern const llvm::SubtargetSubTypeKVStorage< 16, 10, 164> R600SubTypeKVStorage = {
286 {
287 { sizeof(SubtargetSubTypeKV) * 16 + R600CPUAliasArraySize + 7, { { { 0x208020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
288 { sizeof(SubtargetSubTypeKV) * 15 + R600CPUAliasArraySize + 13, { { { 0x8020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
289 { sizeof(SubtargetSubTypeKV) * 14 + R600CPUAliasArraySize + 20, { { { 0x8140ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 },
290 { sizeof(SubtargetSubTypeKV) * 13 + R600CPUAliasArraySize + 27, { { { 0xa000a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
291 { sizeof(SubtargetSubTypeKV) * 12 + R600CPUAliasArraySize + 33, { { { 0x1200180ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
292 { sizeof(SubtargetSubTypeKV) * 11 + R600CPUAliasArraySize + 49, { { { 0x1200080ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
293 { sizeof(SubtargetSubTypeKV) * 10 + R600CPUAliasArraySize + 62, { { { 0x1210000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
294 { sizeof(SubtargetSubTypeKV) * 9 + R600CPUAliasArraySize + 67, { { { 0xa10000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
295 { sizeof(SubtargetSubTypeKV) * 8 + R600CPUAliasArraySize + 72, { { { 0x12000a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
296 { sizeof(SubtargetSubTypeKV) * 7 + R600CPUAliasArraySize + 86, { { { 0x410000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
297 { sizeof(SubtargetSubTypeKV) * 6 + R600CPUAliasArraySize + 116, { { { 0x1210000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
298 { sizeof(SubtargetSubTypeKV) * 5 + R600CPUAliasArraySize + 122, { { { 0xa40000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
299 { sizeof(SubtargetSubTypeKV) * 4 + R600CPUAliasArraySize + 128, { { { 0xa40000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
300 { sizeof(SubtargetSubTypeKV) * 3 + R600CPUAliasArraySize + 140, { { { 0x1240000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
301 { sizeof(SubtargetSubTypeKV) * 2 + R600CPUAliasArraySize + 146, { { { 0x10000a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
302 { sizeof(SubtargetSubTypeKV) * 1 + R600CPUAliasArraySize + 157, { { { 0x208020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
303 },
304 { {
305 { sizeof(SubtargetSubTypeAliasKV) * 10 + 1, 2 },
306 { sizeof(SubtargetSubTypeAliasKV) * 9 + 41, 4 },
307 { sizeof(SubtargetSubTypeAliasKV) * 8 + 57, 3 },
308 { sizeof(SubtargetSubTypeAliasKV) * 7 + 80, 9 },
309 { sizeof(SubtargetSubTypeAliasKV) * 6 + 92, 9 },
310 { sizeof(SubtargetSubTypeAliasKV) * 5 + 98, 9 },
311 { sizeof(SubtargetSubTypeAliasKV) * 4 + 104, 6 },
312 { sizeof(SubtargetSubTypeAliasKV) * 3 + 110, 6 },
313 { sizeof(SubtargetSubTypeAliasKV) * 2 + 134, 13 },
314 { sizeof(SubtargetSubTypeAliasKV) * 1 + 151, 14 },
315 } },
316 "\000aruba\000barts\000caicos\000cayman\000cedar\000cypress\000hemlock\000"
317 "juniper\000palm\000r600\000r630\000redwood\000rs780\000rs880\000rv610\000"
318 "rv620\000rv630\000rv635\000rv670\000rv710\000rv730\000rv740\000rv770\000"
319 "sumo\000sumo2\000turks\000"};
320
321namespace R600_MC {
322
323unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
324 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
325 // Don't know how to resolve this scheduling class.
326 return 0;
327}
328
329} // namespace R600_MC
330struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
331 R600GenMCSubtargetInfo(const Triple &TT,
332 StringRef CPU, StringRef TuneCPU, StringRef FS,
333 StringTable PN,
334 ArrayRef<SubtargetFeatureKV> PF,
335 ArrayRef<SubtargetSubTypeKV> PD,
336 ArrayRef<SubtargetSubTypeAliasKV> PA,
337 const MCSchedModel *PSM,
338 const MCWriteProcResEntry *WPR,
339 const MCWriteLatencyEntry *WL,
340 const MCReadAdvanceEntry *RA, const InstrStage *IS,
341 const unsigned *OC, const unsigned *FP) :
342 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM,
343 WPR, WL, RA, IS, OC, FP) { }
344
345 unsigned resolveVariantSchedClass(unsigned SchedClass,
346 const MCInst *MI, const MCInstrInfo *MCII,
347 unsigned CPUID) const final {
348 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
349 }
350};
351
352static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
353 return new R600GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(R600SubTypeKVStorage.Strings), R600FeatureKVStorage.Features, R600SubTypeKVStorage.SubTypes, ArrayRef(R600SubTypeKVStorage.Aliases).take_front(10), R600SchedModels,
354 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
355 R600Stages, R600OperandCycles, R600ForwardingPaths);
356}
357
358
359} // namespace llvm
360
361#endif // GET_SUBTARGETINFO_MC_DESC
362
363#ifdef GET_SUBTARGETINFO_TARGET_DESC
364#undef GET_SUBTARGETINFO_TARGET_DESC
365
366#include "llvm/ADT/BitmaskEnum.h"
367#include "llvm/Support/Debug.h"
368#include "llvm/Support/raw_ostream.h"
369
370// ParseSubtargetFeatures - Parses features string setting specified
371// subtarget options.
372void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
373 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
374 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
375 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
376 InitMCProcessorInfo(CPU, TuneCPU, FS);
377 const FeatureBitset &Bits = getFeatureBits();
378 if (Bits[R600::FeatureAddressableLocalMemorySize32768] && AddressableLocalMemorySize < 32768) AddressableLocalMemorySize = 32768;
379 if (Bits[R600::FeatureAddressableLocalMemorySize65536] && AddressableLocalMemorySize < 65536) AddressableLocalMemorySize = 65536;
380 if (Bits[R600::FeatureAddressableLocalMemorySize163840] && AddressableLocalMemorySize < 163840) AddressableLocalMemorySize = 163840;
381 if (Bits[R600::FeatureAddressableLocalMemorySize196608] && AddressableLocalMemorySize < 196608) AddressableLocalMemorySize = 196608;
382 if (Bits[R600::FeatureAddressableLocalMemorySize327680] && AddressableLocalMemorySize < 327680) AddressableLocalMemorySize = 327680;
383 if (Bits[R600::FeatureCFALUBug]) HasCFALUBug = true;
384 if (Bits[R600::FeatureCaymanISA]) HasCaymanISA = true;
385 if (Bits[R600::FeatureEvergreen] && Gen < R600Subtarget::EVERGREEN) Gen = R600Subtarget::EVERGREEN;
386 if (Bits[R600::FeatureFMA]) HasFMA = true;
387 if (Bits[R600::FeatureFP64]) HasFP64 = true;
388 if (Bits[R600::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
389 if (Bits[R600::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
390 if (Bits[R600::FeatureFlatOffsetBits12] && FlatOffsetBitWidth < 12) FlatOffsetBitWidth = 12;
391 if (Bits[R600::FeatureFlatOffsetBits24] && FlatOffsetBitWidth < 24) FlatOffsetBitWidth = 24;
392 if (Bits[R600::FeatureMadMacF32Insts]) HasMadMacF32Insts = true;
393 if (Bits[R600::FeatureNorthernIslands] && Gen < R600Subtarget::NORTHERN_ISLANDS) Gen = R600Subtarget::NORTHERN_ISLANDS;
394 if (Bits[R600::FeatureR600] && Gen < R600Subtarget::R600) Gen = R600Subtarget::R600;
395 if (Bits[R600::FeatureR600ALUInst]) HasR600ALUInst = false;
396 if (Bits[R600::FeatureR700] && Gen < R600Subtarget::R700) Gen = R600Subtarget::R700;
397 if (Bits[R600::FeatureSupportsWave32]) SupportsWave32 = true;
398 if (Bits[R600::FeatureSupportsWave64]) SupportsWave64 = true;
399 if (Bits[R600::FeatureVertexCache]) HasVertexCache = true;
400 if (Bits[R600::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4;
401 if (Bits[R600::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5;
402 if (Bits[R600::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6;
403}
404
405#endif // GET_SUBTARGETINFO_TARGET_DESC
406
407#ifdef GET_SUBTARGETINFO_HEADER
408#undef GET_SUBTARGETINFO_HEADER
409
410namespace llvm {
411
412class DFAPacketizer;
413namespace R600_MC {
414
415unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
416
417} // namespace R600_MC
418struct R600GenSubtargetInfo : public TargetSubtargetInfo {
419 explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
420public:
421 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
422 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
423 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
424 const FeatureBitset &getInlineIgnoreFeatures() const override;
425 const FeatureBitset &getInlineInverseFeatures() const override;
426 const FeatureBitset &getInlineMustMatchFeatures() const override;
427};
428
429} // namespace llvm
430
431#endif // GET_SUBTARGETINFO_HEADER
432
433#ifdef GET_SUBTARGETINFO_CTOR
434#undef GET_SUBTARGETINFO_CTOR
435
436#include "llvm/CodeGen/TargetSchedule.h"
437
438namespace llvm {
439
440extern const llvm::StringRef R600Names[];
441extern const llvm::SubtargetFeatureKVStorage<25, 1060> R600FeatureKVStorage;
442extern const llvm::SubtargetSubTypeKVStorage<16, 10, 164> R600SubTypeKVStorage;
443extern const llvm::MCSchedModel R600SchedModels[];
444extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
445extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
446extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
447extern const llvm::InstrStage R600Stages[];
448extern const unsigned R600OperandCycles[];
449extern const unsigned R600ForwardingPaths[];
450R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
451 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(R600SubTypeKVStorage.Strings), ArrayRef(R600FeatureKVStorage.Features), ArrayRef(R600SubTypeKVStorage.SubTypes), ArrayRef(R600SubTypeKVStorage.Aliases).take_front(10), R600SchedModels,
452 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
453 R600Stages, R600OperandCycles, R600ForwardingPaths) {}
454
455unsigned R600GenSubtargetInfo
456::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
457 report_fatal_error("Expected a variant SchedClass");
458} // R600GenSubtargetInfo::resolveSchedClass
459
460unsigned R600GenSubtargetInfo
461::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
462 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
463} // R600GenSubtargetInfo::resolveVariantSchedClass
464
465const FeatureBitset &R600GenSubtargetInfo::getInlineIgnoreFeatures() const {
466 static constexpr FeatureBitset Features = {
467R600::FeatureSupportsWave32,
468R600::FeatureSupportsWave64,
469 };
470 return Features;
471}
472
473const FeatureBitset &R600GenSubtargetInfo::getInlineInverseFeatures() const {
474 static constexpr FeatureBitset Features = {
475 };
476 return Features;
477}
478
479const FeatureBitset &R600GenSubtargetInfo::getInlineMustMatchFeatures() const {
480 static constexpr FeatureBitset Features = {
481 };
482 return Features;
483}
484
485
486} // namespace llvm
487
488#endif // GET_SUBTARGETINFO_CTOR
489
490#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
491#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
492
493
494#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
495
496#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
497#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
498
499
500#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
501
502