1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace R600 {
15
16enum {
17 FeatureAddressableLocalMemorySize32768 = 0,
18 FeatureAddressableLocalMemorySize65536 = 1,
19 FeatureAddressableLocalMemorySize163840 = 2,
20 FeatureAddressableLocalMemorySize327680 = 3,
21 FeatureCFALUBug = 4,
22 FeatureCaymanISA = 5,
23 FeatureEvergreen = 6,
24 FeatureFMA = 7,
25 FeatureFP64 = 8,
26 FeatureFetchLimit8 = 9,
27 FeatureFetchLimit16 = 10,
28 FeatureFlatOffsetBits12 = 11,
29 FeatureFlatOffsetBits24 = 12,
30 FeatureMadMacF32Insts = 13,
31 FeatureNorthernIslands = 14,
32 FeatureR600 = 15,
33 FeatureR600ALUInst = 16,
34 FeatureR700 = 17,
35 FeatureVertexCache = 18,
36 FeatureWavefrontSize16 = 19,
37 FeatureWavefrontSize32 = 20,
38 FeatureWavefrontSize64 = 21,
39 NumSubtargetFeatures = 22
40};
41
42} // namespace R600
43
44} // namespace llvm
45
46#endif // GET_SUBTARGETINFO_ENUM
47
48#ifdef GET_SUBTARGETINFO_MACRO
49
50GET_SUBTARGETINFO_MACRO(HasCFALUBug, false, hasCFALUBug)
51GET_SUBTARGETINFO_MACRO(HasCaymanISA, false, hasCaymanISA)
52GET_SUBTARGETINFO_MACRO(HasFMA, false, hasFMA)
53GET_SUBTARGETINFO_MACRO(HasFP64, false, hasFP64)
54GET_SUBTARGETINFO_MACRO(HasMadMacF32Insts, false, hasMadMacF32Insts)
55GET_SUBTARGETINFO_MACRO(HasR600ALUInst, true, hasR600ALUInst)
56GET_SUBTARGETINFO_MACRO(HasVertexCache, false, hasVertexCache)
57
58#undef GET_SUBTARGETINFO_MACRO
59#endif // GET_SUBTARGETINFO_MACRO
60
61#ifdef GET_SUBTARGETINFO_MC_DESC
62#undef GET_SUBTARGETINFO_MC_DESC
63
64namespace llvm {
65
66// Sorted (by key) array of values for CPU features.
67extern const llvm::SubtargetFeatureKV R600FeatureKV[] = {
68 { "HasVertexCache", "Specify use of dedicated vertex cache", R600::FeatureVertexCache, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
69 { "R600ALUInst", "Older version of ALU instructions encoding", R600::FeatureR600ALUInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
70 { "addressablelocalmemorysize163840", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize163840, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
71 { "addressablelocalmemorysize32768", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
72 { "addressablelocalmemorysize327680", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize327680, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
73 { "addressablelocalmemorysize65536", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { "caymanISA", "Use Cayman ISA", R600::FeatureCaymanISA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { "cfalubug", "GPU has CF_ALU bug", R600::FeatureCFALUBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { "evergreen", "EVERGREEN GPU generation", R600::FeatureEvergreen, { { { 0x2401ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { "fetch16", "Limit the maximum number of fetches in a clause to 16", R600::FeatureFetchLimit16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { "fetch8", "Limit the maximum number of fetches in a clause to 8", R600::FeatureFetchLimit8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { "flat-offset-bits-12", "Number of bits for flat offset encoding", R600::FeatureFlatOffsetBits12, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { "flat-offset-bits-24", "Number of bits for flat offset encoding", R600::FeatureFlatOffsetBits24, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", R600::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { "fp64", "Enable double precision operations", R600::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { "mad-mac-f32-insts", "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions", R600::FeatureMadMacF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { "northern-islands", "NORTHERN_ISLANDS GPU generation", R600::FeatureNorthernIslands, { { { 0x202401ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { "r600", "R600 GPU generation", R600::FeatureR600, { { { 0x12200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { "r700", "R700 GPU generation", R600::FeatureR700, { { { 0x2400ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { "wavefrontsize16", "The number of threads per wavefront", R600::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { "wavefrontsize32", "The number of threads per wavefront", R600::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { "wavefrontsize64", "The number of threads per wavefront", R600::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90};
91
92#ifdef DBGFIELD
93#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
94#endif
95#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
96#define DBGFIELD(x) x,
97#define DBGVAL_OR_NULLPTR(x) x
98#else
99#define DBGFIELD(x)
100#define DBGVAL_OR_NULLPTR(x) nullptr
101#endif
102
103// Functional units for "R600_VLIW5_Itin"
104namespace R600_VLIW5_ItinFU {
105
106 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
107 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
108 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
109 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
110 const InstrStage::FuncUnits TRANS = 1ULL << 4;
111 const InstrStage::FuncUnits ALU_NULL = 1ULL << 5;
112
113} // namespace R600_VLIW5_ItinFU
114
115// Functional units for "R600_VLIW4_Itin"
116namespace R600_VLIW4_ItinFU {
117
118 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
119 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
120 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
121 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
122 const InstrStage::FuncUnits ALU_NULL = 1ULL << 4;
123
124} // namespace R600_VLIW4_ItinFU
125
126extern const llvm::InstrStage R600Stages[] = {
127 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
128 { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
129 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
130 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
131 { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
132 { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
133 { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
134 { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
135 { 0, 0, 0, llvm::InstrStage::Required } // End stages
136};
137extern const unsigned R600OperandCycles[] = {
138 0, // No itinerary
139 0 // End operand cycles
140};
141extern const unsigned R600ForwardingPaths[] = {
142 0, // No itinerary
143 0 // End bypass tables
144};
145
146static constexpr llvm::InstrItinerary R600_VLIW5_Itin[] = {
147 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
148 { 1, 1, 2, 0, 0 }, // 1 NullALU
149 { 1, 2, 3, 0, 0 }, // 2 VecALU
150 { 1, 3, 4, 0, 0 }, // 3 AnyALU
151 { 1, 4, 5, 0, 0 }, // 4 TransALU
152 { 1, 5, 6, 0, 0 }, // 5 XALU
153 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
154};
155
156static constexpr llvm::InstrItinerary R600_VLIW4_Itin[] = {
157 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
158 { 1, 6, 7, 0, 0 }, // 1 NullALU
159 { 1, 7, 8, 0, 0 }, // 2 VecALU
160 { 1, 7, 8, 0, 0 }, // 3 AnyALU
161 { 1, 6, 7, 0, 0 }, // 4 TransALU
162 { 0, 0, 0, 0, 0 }, // 5 XALU
163 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
164};
165
166// ===============================================================
167// Data tables for the new per-operand machine model.
168
169// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
170extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
171 { 0, 0, 0 }, // Invalid
172}; // R600WriteProcResTable
173
174// {Cycles, WriteResourceID}
175extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
176 { 0, 0}, // Invalid
177}; // R600WriteLatencyTable
178
179// {UseIdx, WriteResourceID, Cycles}
180extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
181 {0, 0, 0}, // Invalid
182}; // R600ReadAdvanceTable
183
184#ifdef __GNUC__
185#pragma GCC diagnostic push
186#pragma GCC diagnostic ignored "-Woverlength-strings"
187#endif
188static constexpr char R600SchedClassNamesStorage[] =
189 "\0"
190 "InvalidSchedClass\0"
191 ;
192#ifdef __GNUC__
193#pragma GCC diagnostic pop
194#endif
195
196static constexpr llvm::StringTable
197R600SchedClassNames = R600SchedClassNamesStorage;
198
199static const llvm::MCSchedModel NoSchedModel = {
200 MCSchedModel::DefaultIssueWidth,
201 MCSchedModel::DefaultMicroOpBufferSize,
202 MCSchedModel::DefaultLoopMicroOpBufferSize,
203 MCSchedModel::DefaultLoadLatency,
204 MCSchedModel::DefaultHighLatency,
205 MCSchedModel::DefaultMispredictPenalty,
206 false, // PostRAScheduler
207 false, // CompleteModel
208 false, // EnableIntervals
209 0, // Processor ID
210 nullptr, nullptr, 0, 0, // No instruction-level machine model.
211 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
212 nullptr, // No Itinerary
213 nullptr // No extra processor descriptor
214};
215
216static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
217 MCSchedModel::DefaultIssueWidth,
218 MCSchedModel::DefaultMicroOpBufferSize,
219 MCSchedModel::DefaultLoopMicroOpBufferSize,
220 MCSchedModel::DefaultLoadLatency,
221 MCSchedModel::DefaultHighLatency,
222 MCSchedModel::DefaultMispredictPenalty,
223 false, // PostRAScheduler
224 false, // CompleteModel
225 false, // EnableIntervals
226 1, // Processor ID
227 nullptr, nullptr, 0, 0, // No instruction-level machine model.
228 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
229 R600_VLIW5_Itin,
230 nullptr // No extra processor descriptor
231};
232
233static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
234 MCSchedModel::DefaultIssueWidth,
235 MCSchedModel::DefaultMicroOpBufferSize,
236 MCSchedModel::DefaultLoopMicroOpBufferSize,
237 MCSchedModel::DefaultLoadLatency,
238 MCSchedModel::DefaultHighLatency,
239 MCSchedModel::DefaultMispredictPenalty,
240 false, // PostRAScheduler
241 false, // CompleteModel
242 false, // EnableIntervals
243 2, // Processor ID
244 nullptr, nullptr, 0, 0, // No instruction-level machine model.
245 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
246 R600_VLIW4_Itin,
247 nullptr // No extra processor descriptor
248};
249
250#undef DBGFIELD
251
252#undef DBGVAL_OR_NULLPTR
253
254// Sorted (by key) array of values for CPU subtype.
255extern const llvm::SubtargetSubTypeKV R600SubTypeKV[] = {
256 { "barts", { { { 0x44010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
257 { "caicos", { { { 0x4010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
258 { "cayman", { { { 0x40a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW4_ItinModel },
259 { "cedar", { { { 0x140050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
260 { "cypress", { { { 0x2400c0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
261 { "juniper", { { { 0x240040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
262 { "r600", { { { 0x248000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
263 { "r630", { { { 0x148000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
264 { "redwood", { { { 0x240050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
265 { "rs880", { { { 0x88000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
266 { "rv670", { { { 0x248000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
267 { "rv710", { { { 0x160000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
268 { "rv730", { { { 0x160000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
269 { "rv770", { { { 0x260000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
270 { "sumo", { { { 0x200050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
271 { "turks", { { { 0x44010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
272};
273
274// Sorted array of names of CPU subtypes, including aliases.
275extern const llvm::StringRef R600Names[] = {
276"barts",
277"caicos",
278"cayman",
279"cedar",
280"cypress",
281"juniper",
282"r600",
283"r630",
284"redwood",
285"rs880",
286"rv670",
287"rv710",
288"rv730",
289"rv770",
290"sumo",
291"turks"};
292
293namespace R600_MC {
294
295unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
296 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
297 // Don't know how to resolve this scheduling class.
298 return 0;
299}
300
301} // namespace R600_MC
302struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
303 R600GenMCSubtargetInfo(const Triple &TT,
304 StringRef CPU, StringRef TuneCPU, StringRef FS,
305 ArrayRef<StringRef> PN,
306 ArrayRef<SubtargetFeatureKV> PF,
307 ArrayRef<SubtargetSubTypeKV> PD,
308 const MCWriteProcResEntry *WPR,
309 const MCWriteLatencyEntry *WL,
310 const MCReadAdvanceEntry *RA, const InstrStage *IS,
311 const unsigned *OC, const unsigned *FP) :
312 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
313 WPR, WL, RA, IS, OC, FP) { }
314
315 unsigned resolveVariantSchedClass(unsigned SchedClass,
316 const MCInst *MI, const MCInstrInfo *MCII,
317 unsigned CPUID) const final {
318 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
319 }
320};
321
322static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
323 return new R600GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, R600Names, R600FeatureKV, R600SubTypeKV,
324 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
325 R600Stages, R600OperandCycles, R600ForwardingPaths);
326}
327
328
329} // namespace llvm
330
331#endif // GET_SUBTARGETINFO_MC_DESC
332
333#ifdef GET_SUBTARGETINFO_TARGET_DESC
334#undef GET_SUBTARGETINFO_TARGET_DESC
335
336#include "llvm/ADT/BitmaskEnum.h"
337#include "llvm/Support/Debug.h"
338#include "llvm/Support/raw_ostream.h"
339
340// ParseSubtargetFeatures - Parses features string setting specified
341// subtarget options.
342void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
343 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
344 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
345 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
346 InitMCProcessorInfo(CPU, TuneCPU, FS);
347 const FeatureBitset &Bits = getFeatureBits();
348 if (Bits[R600::FeatureAddressableLocalMemorySize32768] && AddressableLocalMemorySize < 32768) AddressableLocalMemorySize = 32768;
349 if (Bits[R600::FeatureAddressableLocalMemorySize65536] && AddressableLocalMemorySize < 65536) AddressableLocalMemorySize = 65536;
350 if (Bits[R600::FeatureAddressableLocalMemorySize163840] && AddressableLocalMemorySize < 163840) AddressableLocalMemorySize = 163840;
351 if (Bits[R600::FeatureAddressableLocalMemorySize327680] && AddressableLocalMemorySize < 327680) AddressableLocalMemorySize = 327680;
352 if (Bits[R600::FeatureCFALUBug]) HasCFALUBug = true;
353 if (Bits[R600::FeatureCaymanISA]) HasCaymanISA = true;
354 if (Bits[R600::FeatureEvergreen] && Gen < R600Subtarget::EVERGREEN) Gen = R600Subtarget::EVERGREEN;
355 if (Bits[R600::FeatureFMA]) HasFMA = true;
356 if (Bits[R600::FeatureFP64]) HasFP64 = true;
357 if (Bits[R600::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
358 if (Bits[R600::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
359 if (Bits[R600::FeatureFlatOffsetBits12] && FlatOffsetBitWidth < 12) FlatOffsetBitWidth = 12;
360 if (Bits[R600::FeatureFlatOffsetBits24] && FlatOffsetBitWidth < 24) FlatOffsetBitWidth = 24;
361 if (Bits[R600::FeatureMadMacF32Insts]) HasMadMacF32Insts = true;
362 if (Bits[R600::FeatureNorthernIslands] && Gen < R600Subtarget::NORTHERN_ISLANDS) Gen = R600Subtarget::NORTHERN_ISLANDS;
363 if (Bits[R600::FeatureR600] && Gen < R600Subtarget::R600) Gen = R600Subtarget::R600;
364 if (Bits[R600::FeatureR600ALUInst]) HasR600ALUInst = false;
365 if (Bits[R600::FeatureR700] && Gen < R600Subtarget::R700) Gen = R600Subtarget::R700;
366 if (Bits[R600::FeatureVertexCache]) HasVertexCache = true;
367 if (Bits[R600::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4;
368 if (Bits[R600::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5;
369 if (Bits[R600::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6;
370}
371
372#endif // GET_SUBTARGETINFO_TARGET_DESC
373
374#ifdef GET_SUBTARGETINFO_HEADER
375#undef GET_SUBTARGETINFO_HEADER
376
377namespace llvm {
378
379class DFAPacketizer;
380namespace R600_MC {
381
382unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
383
384} // namespace R600_MC
385struct R600GenSubtargetInfo : public TargetSubtargetInfo {
386 explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
387public:
388 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
389 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
390 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
391};
392
393} // namespace llvm
394
395#endif // GET_SUBTARGETINFO_HEADER
396
397#ifdef GET_SUBTARGETINFO_CTOR
398#undef GET_SUBTARGETINFO_CTOR
399
400#include "llvm/CodeGen/TargetSchedule.h"
401
402namespace llvm {
403
404extern const llvm::StringRef R600Names[];
405extern const llvm::SubtargetFeatureKV R600FeatureKV[];
406extern const llvm::SubtargetSubTypeKV R600SubTypeKV[];
407extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
408extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
409extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
410extern const llvm::InstrStage R600Stages[];
411extern const unsigned R600OperandCycles[];
412extern const unsigned R600ForwardingPaths[];
413R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
414 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(R600Names, 16), ArrayRef(R600FeatureKV, 22), ArrayRef(R600SubTypeKV, 16),
415 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
416 R600Stages, R600OperandCycles, R600ForwardingPaths) {}
417
418unsigned R600GenSubtargetInfo
419::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
420 report_fatal_error("Expected a variant SchedClass");
421} // R600GenSubtargetInfo::resolveSchedClass
422
423unsigned R600GenSubtargetInfo
424::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
425 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
426} // R600GenSubtargetInfo::resolveVariantSchedClass
427
428
429} // namespace llvm
430
431#endif // GET_SUBTARGETINFO_CTOR
432
433#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
434#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
435
436
437#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
438
439#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
440#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
441
442
443#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
444
445