1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace R600 {
15
16enum {
17 FeatureAddressableLocalMemorySize32768 = 0,
18 FeatureAddressableLocalMemorySize65536 = 1,
19 FeatureAddressableLocalMemorySize163840 = 2,
20 FeatureAddressableLocalMemorySize327680 = 3,
21 FeatureCFALUBug = 4,
22 FeatureCaymanISA = 5,
23 FeatureEvergreen = 6,
24 FeatureFMA = 7,
25 FeatureFP64 = 8,
26 FeatureFetchLimit8 = 9,
27 FeatureFetchLimit16 = 10,
28 FeatureMadMacF32Insts = 11,
29 FeatureNorthernIslands = 12,
30 FeaturePromoteAlloca = 13,
31 FeatureR600 = 14,
32 FeatureR600ALUInst = 15,
33 FeatureR700 = 16,
34 FeatureVertexCache = 17,
35 FeatureWavefrontSize16 = 18,
36 FeatureWavefrontSize32 = 19,
37 FeatureWavefrontSize64 = 20,
38 NumSubtargetFeatures = 21
39};
40
41} // namespace R600
42
43} // namespace llvm
44
45#endif // GET_SUBTARGETINFO_ENUM
46
47#ifdef GET_SUBTARGETINFO_MACRO
48
49GET_SUBTARGETINFO_MACRO(EnablePromoteAlloca, false, enablePromoteAlloca)
50GET_SUBTARGETINFO_MACRO(HasCFALUBug, false, hasCFALUBug)
51GET_SUBTARGETINFO_MACRO(HasCaymanISA, false, hasCaymanISA)
52GET_SUBTARGETINFO_MACRO(HasFMA, false, hasFMA)
53GET_SUBTARGETINFO_MACRO(HasFP64, false, hasFP64)
54GET_SUBTARGETINFO_MACRO(HasMadMacF32Insts, false, hasMadMacF32Insts)
55GET_SUBTARGETINFO_MACRO(HasR600ALUInst, true, hasR600ALUInst)
56GET_SUBTARGETINFO_MACRO(HasVertexCache, false, hasVertexCache)
57
58#undef GET_SUBTARGETINFO_MACRO
59#endif // GET_SUBTARGETINFO_MACRO
60
61#ifdef GET_SUBTARGETINFO_MC_DESC
62#undef GET_SUBTARGETINFO_MC_DESC
63
64namespace llvm {
65
66// Sorted (by key) array of values for CPU features.
67extern const llvm::SubtargetFeatureKV R600FeatureKV[] = {
68 { "HasVertexCache", "Specify use of dedicated vertex cache", R600::FeatureVertexCache, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
69 { "R600ALUInst", "Older version of ALU instructions encoding", R600::FeatureR600ALUInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
70 { "addressablelocalmemorysize163840", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize163840, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
71 { "addressablelocalmemorysize32768", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
72 { "addressablelocalmemorysize327680", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize327680, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
73 { "addressablelocalmemorysize65536", "The size of local memory in bytes", R600::FeatureAddressableLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { "caymanISA", "Use Cayman ISA", R600::FeatureCaymanISA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { "cfalubug", "GPU has CF_ALU bug", R600::FeatureCFALUBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { "evergreen", "EVERGREEN GPU generation", R600::FeatureEvergreen, { { { 0xc01ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { "fetch16", "Limit the maximum number of fetches in a clause to 16", R600::FeatureFetchLimit16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { "fetch8", "Limit the maximum number of fetches in a clause to 8", R600::FeatureFetchLimit8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", R600::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { "fp64", "Enable double precision operations", R600::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { "mad-mac-f32-insts", "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions", R600::FeatureMadMacF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { "northern-islands", "NORTHERN_ISLANDS GPU generation", R600::FeatureNorthernIslands, { { { 0x100c01ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { "promote-alloca", "Enable promote alloca pass", R600::FeaturePromoteAlloca, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { "r600", "R600 GPU generation", R600::FeatureR600, { { { 0x8a00ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { "r700", "R700 GPU generation", R600::FeatureR700, { { { 0xc00ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { "wavefrontsize16", "The number of threads per wavefront", R600::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { "wavefrontsize32", "The number of threads per wavefront", R600::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { "wavefrontsize64", "The number of threads per wavefront", R600::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89};
90
91#ifdef DBGFIELD
92#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
93#endif
94#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
95#define DBGFIELD(x) x,
96#define DBGVAL_OR_NULLPTR(x) x
97#else
98#define DBGFIELD(x)
99#define DBGVAL_OR_NULLPTR(x) nullptr
100#endif
101
102// Functional units for "R600_VLIW5_Itin"
103namespace R600_VLIW5_ItinFU {
104
105 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
106 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
107 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
108 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
109 const InstrStage::FuncUnits TRANS = 1ULL << 4;
110 const InstrStage::FuncUnits ALU_NULL = 1ULL << 5;
111
112} // namespace R600_VLIW5_ItinFU
113
114// Functional units for "R600_VLIW4_Itin"
115namespace R600_VLIW4_ItinFU {
116
117 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
118 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
119 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
120 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
121 const InstrStage::FuncUnits ALU_NULL = 1ULL << 4;
122
123} // namespace R600_VLIW4_ItinFU
124
125extern const llvm::InstrStage R600Stages[] = {
126 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
127 { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
128 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
129 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
130 { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
131 { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
132 { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
133 { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
134 { 0, 0, 0, llvm::InstrStage::Required } // End stages
135};
136extern const unsigned R600OperandCycles[] = {
137 0, // No itinerary
138 0 // End operand cycles
139};
140extern const unsigned R600ForwardingPaths[] = {
141 0, // No itinerary
142 0 // End bypass tables
143};
144
145static constexpr llvm::InstrItinerary R600_VLIW5_Itin[] = {
146 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
147 { 1, 1, 2, 0, 0 }, // 1 NullALU
148 { 1, 2, 3, 0, 0 }, // 2 VecALU
149 { 1, 3, 4, 0, 0 }, // 3 AnyALU
150 { 1, 4, 5, 0, 0 }, // 4 TransALU
151 { 1, 5, 6, 0, 0 }, // 5 XALU
152 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
153};
154
155static constexpr llvm::InstrItinerary R600_VLIW4_Itin[] = {
156 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
157 { 1, 6, 7, 0, 0 }, // 1 NullALU
158 { 1, 7, 8, 0, 0 }, // 2 VecALU
159 { 1, 7, 8, 0, 0 }, // 3 AnyALU
160 { 1, 6, 7, 0, 0 }, // 4 TransALU
161 { 0, 0, 0, 0, 0 }, // 5 XALU
162 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
163};
164
165// ===============================================================
166// Data tables for the new per-operand machine model.
167
168// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
169extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
170 { 0, 0, 0 }, // Invalid
171}; // R600WriteProcResTable
172
173// {Cycles, WriteResourceID}
174extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
175 { 0, 0}, // Invalid
176}; // R600WriteLatencyTable
177
178// {UseIdx, WriteResourceID, Cycles}
179extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
180 {0, 0, 0}, // Invalid
181}; // R600ReadAdvanceTable
182
183#ifdef __GNUC__
184#pragma GCC diagnostic push
185#pragma GCC diagnostic ignored "-Woverlength-strings"
186#endif
187static constexpr char R600SchedClassNamesStorage[] =
188 "\0"
189 "InvalidSchedClass\0"
190 ;
191#ifdef __GNUC__
192#pragma GCC diagnostic pop
193#endif
194
195static constexpr llvm::StringTable
196R600SchedClassNames = R600SchedClassNamesStorage;
197
198static const llvm::MCSchedModel NoSchedModel = {
199 MCSchedModel::DefaultIssueWidth,
200 MCSchedModel::DefaultMicroOpBufferSize,
201 MCSchedModel::DefaultLoopMicroOpBufferSize,
202 MCSchedModel::DefaultLoadLatency,
203 MCSchedModel::DefaultHighLatency,
204 MCSchedModel::DefaultMispredictPenalty,
205 false, // PostRAScheduler
206 false, // CompleteModel
207 false, // EnableIntervals
208 0, // Processor ID
209 nullptr, nullptr, 0, 0, // No instruction-level machine model.
210 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
211 nullptr, // No Itinerary
212 nullptr // No extra processor descriptor
213};
214
215static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
216 MCSchedModel::DefaultIssueWidth,
217 MCSchedModel::DefaultMicroOpBufferSize,
218 MCSchedModel::DefaultLoopMicroOpBufferSize,
219 MCSchedModel::DefaultLoadLatency,
220 MCSchedModel::DefaultHighLatency,
221 MCSchedModel::DefaultMispredictPenalty,
222 false, // PostRAScheduler
223 false, // CompleteModel
224 false, // EnableIntervals
225 1, // Processor ID
226 nullptr, nullptr, 0, 0, // No instruction-level machine model.
227 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
228 R600_VLIW5_Itin,
229 nullptr // No extra processor descriptor
230};
231
232static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
233 MCSchedModel::DefaultIssueWidth,
234 MCSchedModel::DefaultMicroOpBufferSize,
235 MCSchedModel::DefaultLoopMicroOpBufferSize,
236 MCSchedModel::DefaultLoadLatency,
237 MCSchedModel::DefaultHighLatency,
238 MCSchedModel::DefaultMispredictPenalty,
239 false, // PostRAScheduler
240 false, // CompleteModel
241 false, // EnableIntervals
242 2, // Processor ID
243 nullptr, nullptr, 0, 0, // No instruction-level machine model.
244 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
245 R600_VLIW4_Itin,
246 nullptr // No extra processor descriptor
247};
248
249#undef DBGFIELD
250
251#undef DBGVAL_OR_NULLPTR
252
253// Sorted (by key) array of values for CPU subtype.
254extern const llvm::SubtargetSubTypeKV R600SubTypeKV[] = {
255 { "barts", { { { 0x21010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
256 { "caicos", { { { 0x1010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
257 { "cayman", { { { 0x10a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW4_ItinModel },
258 { "cedar", { { { 0xa0050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
259 { "cypress", { { { 0x1200c0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
260 { "juniper", { { { 0x120040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
261 { "r600", { { { 0x124000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
262 { "r630", { { { 0xa4000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
263 { "redwood", { { { 0x120050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
264 { "rs880", { { { 0x44000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
265 { "rv670", { { { 0x124000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
266 { "rv710", { { { 0xb0000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
267 { "rv730", { { { 0xb0000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
268 { "rv770", { { { 0x130000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
269 { "sumo", { { { 0x100050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
270 { "turks", { { { 0x21010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &R600_VLIW5_ItinModel },
271};
272
273// Sorted array of names of CPU subtypes, including aliases.
274extern const llvm::StringRef R600Names[] = {
275"barts",
276"caicos",
277"cayman",
278"cedar",
279"cypress",
280"juniper",
281"r600",
282"r630",
283"redwood",
284"rs880",
285"rv670",
286"rv710",
287"rv730",
288"rv770",
289"sumo",
290"turks"};
291
292namespace R600_MC {
293
294unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
295 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
296 // Don't know how to resolve this scheduling class.
297 return 0;
298}
299
300} // namespace R600_MC
301struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
302 R600GenMCSubtargetInfo(const Triple &TT,
303 StringRef CPU, StringRef TuneCPU, StringRef FS,
304 ArrayRef<StringRef> PN,
305 ArrayRef<SubtargetFeatureKV> PF,
306 ArrayRef<SubtargetSubTypeKV> PD,
307 const MCWriteProcResEntry *WPR,
308 const MCWriteLatencyEntry *WL,
309 const MCReadAdvanceEntry *RA, const InstrStage *IS,
310 const unsigned *OC, const unsigned *FP) :
311 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
312 WPR, WL, RA, IS, OC, FP) { }
313
314 unsigned resolveVariantSchedClass(unsigned SchedClass,
315 const MCInst *MI, const MCInstrInfo *MCII,
316 unsigned CPUID) const final {
317 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
318 }
319};
320
321static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
322 return new R600GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, R600Names, R600FeatureKV, R600SubTypeKV,
323 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
324 R600Stages, R600OperandCycles, R600ForwardingPaths);
325}
326
327
328} // namespace llvm
329
330#endif // GET_SUBTARGETINFO_MC_DESC
331
332#ifdef GET_SUBTARGETINFO_TARGET_DESC
333#undef GET_SUBTARGETINFO_TARGET_DESC
334
335#include "llvm/ADT/BitmaskEnum.h"
336#include "llvm/Support/Debug.h"
337#include "llvm/Support/raw_ostream.h"
338
339// ParseSubtargetFeatures - Parses features string setting specified
340// subtarget options.
341void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
342 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
343 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
344 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
345 InitMCProcessorInfo(CPU, TuneCPU, FS);
346 const FeatureBitset &Bits = getFeatureBits();
347 if (Bits[R600::FeatureAddressableLocalMemorySize32768] && AddressableLocalMemorySize < 32768) AddressableLocalMemorySize = 32768;
348 if (Bits[R600::FeatureAddressableLocalMemorySize65536] && AddressableLocalMemorySize < 65536) AddressableLocalMemorySize = 65536;
349 if (Bits[R600::FeatureAddressableLocalMemorySize163840] && AddressableLocalMemorySize < 163840) AddressableLocalMemorySize = 163840;
350 if (Bits[R600::FeatureAddressableLocalMemorySize327680] && AddressableLocalMemorySize < 327680) AddressableLocalMemorySize = 327680;
351 if (Bits[R600::FeatureCFALUBug]) HasCFALUBug = true;
352 if (Bits[R600::FeatureCaymanISA]) HasCaymanISA = true;
353 if (Bits[R600::FeatureEvergreen] && Gen < R600Subtarget::EVERGREEN) Gen = R600Subtarget::EVERGREEN;
354 if (Bits[R600::FeatureFMA]) HasFMA = true;
355 if (Bits[R600::FeatureFP64]) HasFP64 = true;
356 if (Bits[R600::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
357 if (Bits[R600::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
358 if (Bits[R600::FeatureMadMacF32Insts]) HasMadMacF32Insts = true;
359 if (Bits[R600::FeatureNorthernIslands] && Gen < R600Subtarget::NORTHERN_ISLANDS) Gen = R600Subtarget::NORTHERN_ISLANDS;
360 if (Bits[R600::FeaturePromoteAlloca]) EnablePromoteAlloca = true;
361 if (Bits[R600::FeatureR600] && Gen < R600Subtarget::R600) Gen = R600Subtarget::R600;
362 if (Bits[R600::FeatureR600ALUInst]) HasR600ALUInst = false;
363 if (Bits[R600::FeatureR700] && Gen < R600Subtarget::R700) Gen = R600Subtarget::R700;
364 if (Bits[R600::FeatureVertexCache]) HasVertexCache = true;
365 if (Bits[R600::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4;
366 if (Bits[R600::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5;
367 if (Bits[R600::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6;
368}
369
370#endif // GET_SUBTARGETINFO_TARGET_DESC
371
372#ifdef GET_SUBTARGETINFO_HEADER
373#undef GET_SUBTARGETINFO_HEADER
374
375namespace llvm {
376
377class DFAPacketizer;
378namespace R600_MC {
379
380unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
381
382} // namespace R600_MC
383struct R600GenSubtargetInfo : public TargetSubtargetInfo {
384 explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
385public:
386 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
387 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
388 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
389};
390
391} // namespace llvm
392
393#endif // GET_SUBTARGETINFO_HEADER
394
395#ifdef GET_SUBTARGETINFO_CTOR
396#undef GET_SUBTARGETINFO_CTOR
397
398#include "llvm/CodeGen/TargetSchedule.h"
399
400namespace llvm {
401
402extern const llvm::StringRef R600Names[];
403extern const llvm::SubtargetFeatureKV R600FeatureKV[];
404extern const llvm::SubtargetSubTypeKV R600SubTypeKV[];
405extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
406extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
407extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
408extern const llvm::InstrStage R600Stages[];
409extern const unsigned R600OperandCycles[];
410extern const unsigned R600ForwardingPaths[];
411R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
412 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(R600Names, 16), ArrayRef(R600FeatureKV, 21), ArrayRef(R600SubTypeKV, 16),
413 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
414 R600Stages, R600OperandCycles, R600ForwardingPaths) {}
415
416unsigned R600GenSubtargetInfo
417::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
418 report_fatal_error("Expected a variant SchedClass");
419} // R600GenSubtargetInfo::resolveSchedClass
420
421unsigned R600GenSubtargetInfo
422::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
423 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
424} // R600GenSubtargetInfo::resolveVariantSchedClass
425
426
427} // namespace llvm
428
429#endif // GET_SUBTARGETINFO_CTOR
430
431#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
432#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
433
434
435#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
436
437#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
438#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
439
440
441#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
442
443