1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace R600 {
15
16enum {
17 FeatureAddressableLocalMemorySize32768 = 0,
18 FeatureAddressableLocalMemorySize65536 = 1,
19 FeatureAddressableLocalMemorySize163840 = 2,
20 FeatureAddressableLocalMemorySize327680 = 3,
21 FeatureCFALUBug = 4,
22 FeatureCaymanISA = 5,
23 FeatureEvergreen = 6,
24 FeatureFMA = 7,
25 FeatureFP64 = 8,
26 FeatureFetchLimit8 = 9,
27 FeatureFetchLimit16 = 10,
28 FeatureFlatOffsetBits12 = 11,
29 FeatureFlatOffsetBits24 = 12,
30 FeatureMadMacF32Insts = 13,
31 FeatureNorthernIslands = 14,
32 FeatureR600 = 15,
33 FeatureR600ALUInst = 16,
34 FeatureR700 = 17,
35 FeatureVertexCache = 18,
36 FeatureWavefrontSize16 = 19,
37 FeatureWavefrontSize32 = 20,
38 FeatureWavefrontSize64 = 21,
39 NumSubtargetFeatures = 22
40};
41
42} // namespace R600
43
44} // namespace llvm
45
46#endif // GET_SUBTARGETINFO_ENUM
47
48#ifdef GET_SUBTARGETINFO_MACRO
49
50GET_SUBTARGETINFO_MACRO(HasCFALUBug, false, hasCFALUBug)
51GET_SUBTARGETINFO_MACRO(HasCaymanISA, false, hasCaymanISA)
52GET_SUBTARGETINFO_MACRO(HasFMA, false, hasFMA)
53GET_SUBTARGETINFO_MACRO(HasFP64, false, hasFP64)
54GET_SUBTARGETINFO_MACRO(HasMadMacF32Insts, false, hasMadMacF32Insts)
55GET_SUBTARGETINFO_MACRO(HasR600ALUInst, true, hasR600ALUInst)
56GET_SUBTARGETINFO_MACRO(HasVertexCache, false, hasVertexCache)
57
58#undef GET_SUBTARGETINFO_MACRO
59#endif // GET_SUBTARGETINFO_MACRO
60
61#ifdef GET_SUBTARGETINFO_MC_DESC
62#undef GET_SUBTARGETINFO_MC_DESC
63
64namespace llvm {
65
66// Sorted (by key) array of values for CPU features.
67extern const llvm::SubtargetFeatureKVStorage< 22, 935> R600FeatureKVStorage = {
68 {
69 { sizeof(SubtargetFeatureKV) * 22 + 1, sizeof(SubtargetFeatureKV) * 22 + 16, R600::FeatureVertexCache, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
70 { sizeof(SubtargetFeatureKV) * 21 + 54, sizeof(SubtargetFeatureKV) * 21 + 66, R600::FeatureR600ALUInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
71 { sizeof(SubtargetFeatureKV) * 20 + 109, sizeof(SubtargetFeatureKV) * 20 + 142, R600::FeatureAddressableLocalMemorySize163840, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
72 { sizeof(SubtargetFeatureKV) * 19 + 176, sizeof(SubtargetFeatureKV) * 19 + 142, R600::FeatureAddressableLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
73 { sizeof(SubtargetFeatureKV) * 18 + 208, sizeof(SubtargetFeatureKV) * 18 + 142, R600::FeatureAddressableLocalMemorySize327680, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { sizeof(SubtargetFeatureKV) * 17 + 241, sizeof(SubtargetFeatureKV) * 17 + 142, R600::FeatureAddressableLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { sizeof(SubtargetFeatureKV) * 16 + 273, sizeof(SubtargetFeatureKV) * 16 + 283, R600::FeatureCaymanISA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { sizeof(SubtargetFeatureKV) * 15 + 298, sizeof(SubtargetFeatureKV) * 15 + 307, R600::FeatureCFALUBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { sizeof(SubtargetFeatureKV) * 14 + 326, sizeof(SubtargetFeatureKV) * 14 + 336, R600::FeatureEvergreen, { { { 0x2401ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { sizeof(SubtargetFeatureKV) * 13 + 361, sizeof(SubtargetFeatureKV) * 13 + 369, R600::FeatureFetchLimit16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { sizeof(SubtargetFeatureKV) * 12 + 423, sizeof(SubtargetFeatureKV) * 12 + 430, R600::FeatureFetchLimit8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80 { sizeof(SubtargetFeatureKV) * 11 + 483, sizeof(SubtargetFeatureKV) * 11 + 503, R600::FeatureFlatOffsetBits12, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
81 { sizeof(SubtargetFeatureKV) * 10 + 543, sizeof(SubtargetFeatureKV) * 10 + 503, R600::FeatureFlatOffsetBits24, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
82 { sizeof(SubtargetFeatureKV) * 9 + 563, sizeof(SubtargetFeatureKV) * 9 + 568, R600::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
83 { sizeof(SubtargetFeatureKV) * 8 + 632, sizeof(SubtargetFeatureKV) * 8 + 637, R600::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { sizeof(SubtargetFeatureKV) * 7 + 672, sizeof(SubtargetFeatureKV) * 7 + 690, R600::FeatureMadMacF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { sizeof(SubtargetFeatureKV) * 6 + 751, sizeof(SubtargetFeatureKV) * 6 + 768, R600::FeatureNorthernIslands, { { { 0x202401ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { sizeof(SubtargetFeatureKV) * 5 + 800, sizeof(SubtargetFeatureKV) * 5 + 805, R600::FeatureR600, { { { 0x12200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { sizeof(SubtargetFeatureKV) * 4 + 825, sizeof(SubtargetFeatureKV) * 4 + 830, R600::FeatureR700, { { { 0x2400ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { sizeof(SubtargetFeatureKV) * 3 + 850, sizeof(SubtargetFeatureKV) * 3 + 866, R600::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { sizeof(SubtargetFeatureKV) * 2 + 902, sizeof(SubtargetFeatureKV) * 2 + 866, R600::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { sizeof(SubtargetFeatureKV) * 1 + 918, sizeof(SubtargetFeatureKV) * 1 + 866, R600::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 },
92 "\000HasVertexCache\000Specify use of dedicated vertex cache\000R600ALUI"
93 "nst\000Older version of ALU instructions encoding\000addressablelocalme"
94 "morysize163840\000The size of local memory in bytes\000addressablelocal"
95 "memorysize32768\000addressablelocalmemorysize327680\000addressablelocal"
96 "memorysize65536\000caymanISA\000Use Cayman ISA\000cfalubug\000GPU has C"
97 "F_ALU bug\000evergreen\000EVERGREEN GPU generation\000fetch16\000Limit "
98 "the maximum number of fetches in a clause to 16\000fetch8\000Limit the "
99 "maximum number of fetches in a clause to 8\000flat-offset-bits-12\000Nu"
100 "mber of bits for flat offset encoding\000flat-offset-bits-24\000fmaf\000"
101 "Enable single precision FMA (not as fast as mul+add, but fused)\000fp64"
102 "\000Enable double precision operations\000mad-mac-f32-insts\000Has v_ma"
103 "d_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions\000northern-island"
104 "s\000NORTHERN_ISLANDS GPU generation\000r600\000R600 GPU generation\000"
105 "r700\000R700 GPU generation\000wavefrontsize16\000The number of threads"
106 " per wavefront\000wavefrontsize32\000wavefrontsize64\000"};
107
108#ifdef DBGFIELD
109#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
110#endif
111#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
112#define DBGFIELD(x) x,
113#define DBGVAL_OR_NULLPTR(x) x
114#else
115#define DBGFIELD(x)
116#define DBGVAL_OR_NULLPTR(x) nullptr
117#endif
118
119// Functional units for "R600_VLIW5_Itin"
120namespace R600_VLIW5_ItinFU {
121
122 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
123 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
124 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
125 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
126 const InstrStage::FuncUnits TRANS = 1ULL << 4;
127 const InstrStage::FuncUnits ALU_NULL = 1ULL << 5;
128
129} // namespace R600_VLIW5_ItinFU
130
131// Functional units for "R600_VLIW4_Itin"
132namespace R600_VLIW4_ItinFU {
133
134 const InstrStage::FuncUnits ALU_X = 1ULL << 0;
135 const InstrStage::FuncUnits ALU_Y = 1ULL << 1;
136 const InstrStage::FuncUnits ALU_Z = 1ULL << 2;
137 const InstrStage::FuncUnits ALU_W = 1ULL << 3;
138 const InstrStage::FuncUnits ALU_NULL = 1ULL << 4;
139
140} // namespace R600_VLIW4_ItinFU
141
142extern const llvm::InstrStage R600Stages[] = {
143 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
144 { 1, R600_VLIW5_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
145 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
146 { 1, R600_VLIW5_ItinFU::ALU_X | R600_VLIW5_ItinFU::ALU_Y | R600_VLIW5_ItinFU::ALU_Z | R600_VLIW5_ItinFU::ALU_W | R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
147 { 1, R600_VLIW5_ItinFU::TRANS, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
148 { 1, R600_VLIW5_ItinFU::ALU_X, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
149 { 1, R600_VLIW4_ItinFU::ALU_NULL, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
150 { 1, R600_VLIW4_ItinFU::ALU_X | R600_VLIW4_ItinFU::ALU_Y | R600_VLIW4_ItinFU::ALU_Z | R600_VLIW4_ItinFU::ALU_W, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
151 { 0, 0, 0, llvm::InstrStage::Required } // End stages
152};
153extern const unsigned R600OperandCycles[] = {
154 0, // No itinerary
155 0 // End operand cycles
156};
157extern const unsigned R600ForwardingPaths[] = {
158 0, // No itinerary
159 0 // End bypass tables
160};
161
162static constexpr llvm::InstrItinerary R600_VLIW5_Itin[] = {
163 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
164 { 1, 1, 2, 0, 0 }, // 1 NullALU
165 { 1, 2, 3, 0, 0 }, // 2 VecALU
166 { 1, 3, 4, 0, 0 }, // 3 AnyALU
167 { 1, 4, 5, 0, 0 }, // 4 TransALU
168 { 1, 5, 6, 0, 0 }, // 5 XALU
169 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
170};
171
172static constexpr llvm::InstrItinerary R600_VLIW4_Itin[] = {
173 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
174 { 1, 6, 7, 0, 0 }, // 1 NullALU
175 { 1, 7, 8, 0, 0 }, // 2 VecALU
176 { 1, 7, 8, 0, 0 }, // 3 AnyALU
177 { 1, 6, 7, 0, 0 }, // 4 TransALU
178 { 0, 0, 0, 0, 0 }, // 5 XALU
179 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
180};
181
182// ===============================================================
183// Data tables for the new per-operand machine model.
184
185static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
186static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
187
188// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
189extern const llvm::MCWriteProcResEntry R600WriteProcResTable[] = {
190 { 0, 0, 0 }, // Invalid
191}; // R600WriteProcResTable
192
193// {Cycles, WriteResourceID}
194extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[] = {
195 { 0, 0}, // Invalid
196}; // R600WriteLatencyTable
197
198// {UseIdx, WriteResourceID, Cycles}
199extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[] = {
200 {0, 0, 0}, // Invalid
201}; // R600ReadAdvanceTable
202
203#ifdef __GNUC__
204#pragma GCC diagnostic push
205#pragma GCC diagnostic ignored "-Woverlength-strings"
206#endif
207static constexpr char R600SchedClassNamesStorage[] =
208 "\0"
209 "InvalidSchedClass\0"
210 ;
211#ifdef __GNUC__
212#pragma GCC diagnostic pop
213#endif
214
215static constexpr llvm::StringTable
216R600SchedClassNames = R600SchedClassNamesStorage;
217
218extern const llvm::MCSchedModel R600SchedModels[] = {
219{ // NoSchedModel
220 MCSchedModel::DefaultIssueWidth,
221 MCSchedModel::DefaultMicroOpBufferSize,
222 MCSchedModel::DefaultLoopMicroOpBufferSize,
223 MCSchedModel::DefaultLoadLatency,
224 MCSchedModel::DefaultHighLatency,
225 MCSchedModel::DefaultMispredictPenalty,
226 false, // PostRAScheduler
227 false, // CompleteModel
228 false, // EnableIntervals
229 0, // Processor ID
230 nullptr, nullptr, 0, 0, // No instruction-level machine model.
231 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
232 nullptr, // No Itinerary
233 nullptr // No extra processor descriptor
234 },
235{ // R600_VLIW5_ItinModel
236 MCSchedModel::DefaultIssueWidth,
237 MCSchedModel::DefaultMicroOpBufferSize,
238 MCSchedModel::DefaultLoopMicroOpBufferSize,
239 MCSchedModel::DefaultLoadLatency,
240 MCSchedModel::DefaultHighLatency,
241 MCSchedModel::DefaultMispredictPenalty,
242 false, // PostRAScheduler
243 false, // CompleteModel
244 false, // EnableIntervals
245 1, // Processor ID
246 nullptr, nullptr, 0, 0, // No instruction-level machine model.
247 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
248 R600_VLIW5_Itin,
249 nullptr // No extra processor descriptor
250 },
251{ // R600_VLIW4_ItinModel
252 MCSchedModel::DefaultIssueWidth,
253 MCSchedModel::DefaultMicroOpBufferSize,
254 MCSchedModel::DefaultLoopMicroOpBufferSize,
255 MCSchedModel::DefaultLoadLatency,
256 MCSchedModel::DefaultHighLatency,
257 MCSchedModel::DefaultMispredictPenalty,
258 false, // PostRAScheduler
259 false, // CompleteModel
260 false, // EnableIntervals
261 2, // Processor ID
262 nullptr, nullptr, 0, 0, // No instruction-level machine model.
263 DBGVAL_OR_NULLPTR(&R600SchedClassNames), // SchedClassNames
264 R600_VLIW4_Itin,
265 nullptr // No extra processor descriptor
266 },
267};
268
269#undef DBGFIELD
270
271#undef DBGVAL_OR_NULLPTR
272
273// Sorted (by key) array of values for CPU subtype.
274extern const llvm::SubtargetSubTypeKVStorage< 16, 103> R600SubTypeKVStorage = {
275 {
276 { sizeof(SubtargetSubTypeKV) * 16 + 1, { { { 0x44010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
277 { sizeof(SubtargetSubTypeKV) * 15 + 7, { { { 0x4010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
278 { sizeof(SubtargetSubTypeKV) * 14 + 14, { { { 0x40a0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 },
279 { sizeof(SubtargetSubTypeKV) * 13 + 21, { { { 0x140050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
280 { sizeof(SubtargetSubTypeKV) * 12 + 27, { { { 0x2400c0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
281 { sizeof(SubtargetSubTypeKV) * 11 + 35, { { { 0x240040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
282 { sizeof(SubtargetSubTypeKV) * 10 + 43, { { { 0x248000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
283 { sizeof(SubtargetSubTypeKV) * 9 + 48, { { { 0x148000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
284 { sizeof(SubtargetSubTypeKV) * 8 + 53, { { { 0x240050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
285 { sizeof(SubtargetSubTypeKV) * 7 + 61, { { { 0x88000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
286 { sizeof(SubtargetSubTypeKV) * 6 + 67, { { { 0x248000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
287 { sizeof(SubtargetSubTypeKV) * 5 + 73, { { { 0x160000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
288 { sizeof(SubtargetSubTypeKV) * 4 + 79, { { { 0x160000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
289 { sizeof(SubtargetSubTypeKV) * 3 + 85, { { { 0x260000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
290 { sizeof(SubtargetSubTypeKV) * 2 + 91, { { { 0x200050ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
291 { sizeof(SubtargetSubTypeKV) * 1 + 96, { { { 0x44010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 },
292 },
293 "\000barts\000caicos\000cayman\000cedar\000cypress\000juniper\000r600\000"
294 "r630\000redwood\000rs880\000rv670\000rv710\000rv730\000rv770\000sumo\000"
295 "turks\000"};
296
297namespace R600_MC {
298
299unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
300 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
301 // Don't know how to resolve this scheduling class.
302 return 0;
303}
304
305} // namespace R600_MC
306struct R600GenMCSubtargetInfo : public MCSubtargetInfo {
307 R600GenMCSubtargetInfo(const Triple &TT,
308 StringRef CPU, StringRef TuneCPU, StringRef FS,
309 StringTable PN,
310 ArrayRef<SubtargetFeatureKV> PF,
311 ArrayRef<SubtargetSubTypeKV> PD,
312 const MCSchedModel *PSM,
313 const MCWriteProcResEntry *WPR,
314 const MCWriteLatencyEntry *WL,
315 const MCReadAdvanceEntry *RA, const InstrStage *IS,
316 const unsigned *OC, const unsigned *FP) :
317 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
318 WPR, WL, RA, IS, OC, FP) { }
319
320 unsigned resolveVariantSchedClass(unsigned SchedClass,
321 const MCInst *MI, const MCInstrInfo *MCII,
322 unsigned CPUID) const final {
323 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
324 }
325};
326
327static inline MCSubtargetInfo *createR600MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
328 return new R600GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(R600SubTypeKVStorage.Strings), R600FeatureKVStorage.Features, R600SubTypeKVStorage.SubTypes, R600SchedModels,
329 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
330 R600Stages, R600OperandCycles, R600ForwardingPaths);
331}
332
333
334} // namespace llvm
335
336#endif // GET_SUBTARGETINFO_MC_DESC
337
338#ifdef GET_SUBTARGETINFO_TARGET_DESC
339#undef GET_SUBTARGETINFO_TARGET_DESC
340
341#include "llvm/ADT/BitmaskEnum.h"
342#include "llvm/Support/Debug.h"
343#include "llvm/Support/raw_ostream.h"
344
345// ParseSubtargetFeatures - Parses features string setting specified
346// subtarget options.
347void llvm::R600Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
348 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
349 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
350 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
351 InitMCProcessorInfo(CPU, TuneCPU, FS);
352 const FeatureBitset &Bits = getFeatureBits();
353 if (Bits[R600::FeatureAddressableLocalMemorySize32768] && AddressableLocalMemorySize < 32768) AddressableLocalMemorySize = 32768;
354 if (Bits[R600::FeatureAddressableLocalMemorySize65536] && AddressableLocalMemorySize < 65536) AddressableLocalMemorySize = 65536;
355 if (Bits[R600::FeatureAddressableLocalMemorySize163840] && AddressableLocalMemorySize < 163840) AddressableLocalMemorySize = 163840;
356 if (Bits[R600::FeatureAddressableLocalMemorySize327680] && AddressableLocalMemorySize < 327680) AddressableLocalMemorySize = 327680;
357 if (Bits[R600::FeatureCFALUBug]) HasCFALUBug = true;
358 if (Bits[R600::FeatureCaymanISA]) HasCaymanISA = true;
359 if (Bits[R600::FeatureEvergreen] && Gen < R600Subtarget::EVERGREEN) Gen = R600Subtarget::EVERGREEN;
360 if (Bits[R600::FeatureFMA]) HasFMA = true;
361 if (Bits[R600::FeatureFP64]) HasFP64 = true;
362 if (Bits[R600::FeatureFetchLimit8] && TexVTXClauseSize < 8) TexVTXClauseSize = 8;
363 if (Bits[R600::FeatureFetchLimit16] && TexVTXClauseSize < 16) TexVTXClauseSize = 16;
364 if (Bits[R600::FeatureFlatOffsetBits12] && FlatOffsetBitWidth < 12) FlatOffsetBitWidth = 12;
365 if (Bits[R600::FeatureFlatOffsetBits24] && FlatOffsetBitWidth < 24) FlatOffsetBitWidth = 24;
366 if (Bits[R600::FeatureMadMacF32Insts]) HasMadMacF32Insts = true;
367 if (Bits[R600::FeatureNorthernIslands] && Gen < R600Subtarget::NORTHERN_ISLANDS) Gen = R600Subtarget::NORTHERN_ISLANDS;
368 if (Bits[R600::FeatureR600] && Gen < R600Subtarget::R600) Gen = R600Subtarget::R600;
369 if (Bits[R600::FeatureR600ALUInst]) HasR600ALUInst = false;
370 if (Bits[R600::FeatureR700] && Gen < R600Subtarget::R700) Gen = R600Subtarget::R700;
371 if (Bits[R600::FeatureVertexCache]) HasVertexCache = true;
372 if (Bits[R600::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4;
373 if (Bits[R600::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5;
374 if (Bits[R600::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6;
375}
376
377#endif // GET_SUBTARGETINFO_TARGET_DESC
378
379#ifdef GET_SUBTARGETINFO_HEADER
380#undef GET_SUBTARGETINFO_HEADER
381
382namespace llvm {
383
384class DFAPacketizer;
385namespace R600_MC {
386
387unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
388
389} // namespace R600_MC
390struct R600GenSubtargetInfo : public TargetSubtargetInfo {
391 explicit R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
392public:
393 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
394 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
395 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
396 const FeatureBitset &getInlineIgnoreFeatures() const override;
397 const FeatureBitset &getInlineInverseFeatures() const override;
398 const FeatureBitset &getInlineMustMatchFeatures() const override;
399};
400
401} // namespace llvm
402
403#endif // GET_SUBTARGETINFO_HEADER
404
405#ifdef GET_SUBTARGETINFO_CTOR
406#undef GET_SUBTARGETINFO_CTOR
407
408#include "llvm/CodeGen/TargetSchedule.h"
409
410namespace llvm {
411
412extern const llvm::StringRef R600Names[];
413extern const llvm::SubtargetFeatureKVStorage<22, 935> R600FeatureKVStorage;
414extern const llvm::SubtargetSubTypeKVStorage<16, 103> R600SubTypeKVStorage;
415extern const llvm::MCSchedModel R600SchedModels[];
416extern const llvm::MCWriteProcResEntry R600WriteProcResTable[];
417extern const llvm::MCWriteLatencyEntry R600WriteLatencyTable[];
418extern const llvm::MCReadAdvanceEntry R600ReadAdvanceTable[];
419extern const llvm::InstrStage R600Stages[];
420extern const unsigned R600OperandCycles[];
421extern const unsigned R600ForwardingPaths[];
422R600GenSubtargetInfo::R600GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
423 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(R600SubTypeKVStorage.Strings), ArrayRef(R600FeatureKVStorage.Features), ArrayRef(R600SubTypeKVStorage.SubTypes), R600SchedModels,
424 R600WriteProcResTable, R600WriteLatencyTable, R600ReadAdvanceTable,
425 R600Stages, R600OperandCycles, R600ForwardingPaths) {}
426
427unsigned R600GenSubtargetInfo
428::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
429 report_fatal_error("Expected a variant SchedClass");
430} // R600GenSubtargetInfo::resolveSchedClass
431
432unsigned R600GenSubtargetInfo
433::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
434 return R600_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
435} // R600GenSubtargetInfo::resolveVariantSchedClass
436
437const FeatureBitset &R600GenSubtargetInfo::getInlineIgnoreFeatures() const {
438 static constexpr FeatureBitset Features = {
439 };
440 return Features;
441}
442
443const FeatureBitset &R600GenSubtargetInfo::getInlineInverseFeatures() const {
444 static constexpr FeatureBitset Features = {
445 };
446 return Features;
447}
448
449const FeatureBitset &R600GenSubtargetInfo::getInlineMustMatchFeatures() const {
450 static constexpr FeatureBitset Features = {
451 };
452 return Features;
453}
454
455
456} // namespace llvm
457
458#endif // GET_SUBTARGETINFO_CTOR
459
460#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
461#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
462
463
464#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
465
466#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
467#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
468
469
470#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
471
472