1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: ARM.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands,
18 const SmallBitVector &OptionalOperandsMask,
19 ArrayRef<unsigned> DefaultsOffset);
20 void convertToMapAndConstraints(unsigned Kind,
21 const OperandVector &Operands) override;
22 unsigned MatchInstructionImpl(const OperandVector &Operands,
23 MCInst &Inst,
24 SmallVectorImpl<NearMissInfo> *NearMisses,
25 bool matchingInlineAsm,
26 unsigned VariantID = 0);
27 ParseStatus MatchOperandParserImpl(
28 OperandVector &Operands,
29 StringRef Mnemonic,
30 bool ParseForAllFeatures = false);
31 ParseStatus tryCustomParseOperand(
32 OperandVector &Operands,
33 unsigned MCK);
34
35#endif // GET_ASSEMBLER_HEADER
36
37
38#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
39#undef GET_OPERAND_DIAGNOSTIC_TYPES
40
41 Match_AlignedMemory16,
42 Match_AlignedMemory32,
43 Match_AlignedMemory64,
44 Match_AlignedMemory64or128,
45 Match_AlignedMemory64or128or256,
46 Match_AlignedMemoryNone,
47 Match_ComplexRotationEven,
48 Match_ComplexRotationOdd,
49 Match_CondCodeRestrictedFP,
50 Match_CondCodeRestrictedI,
51 Match_CondCodeRestrictedS,
52 Match_CondCodeRestrictedU,
53 Match_DPR,
54 Match_DPR_8,
55 Match_DPR_RegList,
56 Match_DPR_VFP2,
57 Match_DupAlignedMemory16,
58 Match_DupAlignedMemory32,
59 Match_DupAlignedMemory64,
60 Match_DupAlignedMemory64or128,
61 Match_DupAlignedMemoryNone,
62 Match_GPR,
63 Match_GPRnoip,
64 Match_GPRnopc,
65 Match_GPRnosp,
66 Match_GPRsp,
67 Match_GPRwithAPSR,
68 Match_GPRwithAPSR_NZCVnosp,
69 Match_GPRwithZR,
70 Match_GPRwithZRnosp,
71 Match_Imm0_1,
72 Match_Imm0_15,
73 Match_Imm0_239,
74 Match_Imm0_255,
75 Match_Imm0_255Expr,
76 Match_Imm0_3,
77 Match_Imm0_31,
78 Match_Imm0_32,
79 Match_Imm0_4095,
80 Match_Imm0_63,
81 Match_Imm0_65535,
82 Match_Imm0_65535Expr,
83 Match_Imm0_7,
84 Match_Imm11b,
85 Match_Imm12b,
86 Match_Imm13b,
87 Match_Imm16,
88 Match_Imm1_15,
89 Match_Imm1_31,
90 Match_Imm1_7,
91 Match_Imm24bit,
92 Match_Imm256_65535Expr,
93 Match_Imm32,
94 Match_Imm3b,
95 Match_Imm4b,
96 Match_Imm6b,
97 Match_Imm7b,
98 Match_Imm8,
99 Match_Imm8_255,
100 Match_Imm9b,
101 Match_ImmRange1_16,
102 Match_ImmRange1_32,
103 Match_ImmThumbSR,
104 Match_LELabel,
105 Match_MVELongShift,
106 Match_MVEShiftImm1_15,
107 Match_MVEShiftImm1_7,
108 Match_MVEVcvtImm16,
109 Match_MVEVcvtImm32,
110 Match_MveSaturate,
111 Match_PKHLSLImm,
112 Match_QPR,
113 Match_QPR_8,
114 Match_QPR_VFP2,
115 Match_SPR,
116 Match_SPRRegList,
117 Match_SPR_8,
118 Match_SetEndImm,
119 Match_ShrImm16,
120 Match_ShrImm32,
121 Match_ShrImm64,
122 Match_ShrImm8,
123 Match_VIDUP_imm,
124 Match_VecListFourMQ,
125 Match_VecListTwoMQ,
126 Match_WLSLabel,
127 Match_hGPR,
128 Match_rGPR,
129 Match_tGPR,
130 Match_tGPREven,
131 Match_tGPROdd,
132 END_OPERAND_DIAGNOSTIC_TYPES
133#endif // GET_OPERAND_DIAGNOSTIC_TYPES
134
135
136#ifdef GET_REGISTER_MATCHER
137#undef GET_REGISTER_MATCHER
138
139// Bits for subtarget features that participate in instruction matching.
140enum SubtargetFeatureBits : uint8_t {
141 Feature_HasV4TBit = 35,
142 Feature_HasV5TBit = 36,
143 Feature_HasV5TEBit = 37,
144 Feature_HasV6Bit = 38,
145 Feature_HasV6MBit = 40,
146 Feature_HasV8MBaselineBit = 45,
147 Feature_HasV8MMainlineBit = 46,
148 Feature_HasV8_1MMainlineBit = 47,
149 Feature_HasMVEIntBit = 26,
150 Feature_HasMVEFloatBit = 25,
151 Feature_HasCDEBit = 4,
152 Feature_HasFPRegsBit = 18,
153 Feature_HasFPRegs16Bit = 19,
154 Feature_HasNoFPRegs16Bit = 29,
155 Feature_HasFPRegs64Bit = 20,
156 Feature_HasFPRegsV8_1MBit = 21,
157 Feature_HasV6T2Bit = 41,
158 Feature_HasV6KBit = 39,
159 Feature_HasV7Bit = 42,
160 Feature_HasV8Bit = 44,
161 Feature_PreV8Bit = 64,
162 Feature_HasV8_1aBit = 48,
163 Feature_HasV8_2aBit = 49,
164 Feature_HasV8_3aBit = 50,
165 Feature_HasV8_4aBit = 51,
166 Feature_HasV8_5aBit = 52,
167 Feature_HasV8_6aBit = 53,
168 Feature_HasV8_7aBit = 54,
169 Feature_HasVFP2Bit = 55,
170 Feature_HasVFP3Bit = 56,
171 Feature_HasVFP4Bit = 57,
172 Feature_HasDPVFPBit = 10,
173 Feature_HasFPARMv8Bit = 17,
174 Feature_HasNEONBit = 28,
175 Feature_HasSHA2Bit = 33,
176 Feature_HasAESBit = 1,
177 Feature_HasCryptoBit = 7,
178 Feature_HasDotProdBit = 14,
179 Feature_HasCRCBit = 6,
180 Feature_HasRASBit = 31,
181 Feature_HasLOBBit = 23,
182 Feature_HasPACBTIBit = 30,
183 Feature_HasFP16Bit = 15,
184 Feature_HasFullFP16Bit = 22,
185 Feature_HasFP16FMLBit = 16,
186 Feature_HasBF16Bit = 3,
187 Feature_HasMatMulInt8Bit = 27,
188 Feature_HasDivideInThumbBit = 13,
189 Feature_HasDivideInARMBit = 12,
190 Feature_HasDSPBit = 11,
191 Feature_HasDBBit = 8,
192 Feature_HasDFBBit = 9,
193 Feature_HasV7ClrexBit = 43,
194 Feature_HasAcquireReleaseBit = 2,
195 Feature_HasMPBit = 24,
196 Feature_HasVirtualizationBit = 58,
197 Feature_HasTrustZoneBit = 34,
198 Feature_Has8MSecExtBit = 0,
199 Feature_IsThumbBit = 62,
200 Feature_IsThumb2Bit = 63,
201 Feature_IsMClassBit = 60,
202 Feature_IsNotMClassBit = 61,
203 Feature_IsARMBit = 59,
204 Feature_UseNegativeImmediatesBit = 65,
205 Feature_HasSBBit = 32,
206 Feature_HasCLRBHBBit = 5,
207};
208
209static MCRegister MatchRegisterName(StringRef Name) {
210 switch (Name.size()) {
211 default: break;
212 case 2: // 45 strings to match.
213 switch (Name[0]) {
214 default: break;
215 case 'd': // 10 strings to match.
216 switch (Name[1]) {
217 default: break;
218 case '0': // 1 string to match.
219 return ARM::D0; // "d0"
220 case '1': // 1 string to match.
221 return ARM::D1; // "d1"
222 case '2': // 1 string to match.
223 return ARM::D2; // "d2"
224 case '3': // 1 string to match.
225 return ARM::D3; // "d3"
226 case '4': // 1 string to match.
227 return ARM::D4; // "d4"
228 case '5': // 1 string to match.
229 return ARM::D5; // "d5"
230 case '6': // 1 string to match.
231 return ARM::D6; // "d6"
232 case '7': // 1 string to match.
233 return ARM::D7; // "d7"
234 case '8': // 1 string to match.
235 return ARM::D8; // "d8"
236 case '9': // 1 string to match.
237 return ARM::D9; // "d9"
238 }
239 break;
240 case 'l': // 1 string to match.
241 if (Name[1] != 'r')
242 break;
243 return ARM::LR; // "lr"
244 case 'p': // 2 strings to match.
245 switch (Name[1]) {
246 default: break;
247 case '0': // 1 string to match.
248 return ARM::P0; // "p0"
249 case 'c': // 1 string to match.
250 return ARM::PC; // "pc"
251 }
252 break;
253 case 'q': // 10 strings to match.
254 switch (Name[1]) {
255 default: break;
256 case '0': // 1 string to match.
257 return ARM::Q0; // "q0"
258 case '1': // 1 string to match.
259 return ARM::Q1; // "q1"
260 case '2': // 1 string to match.
261 return ARM::Q2; // "q2"
262 case '3': // 1 string to match.
263 return ARM::Q3; // "q3"
264 case '4': // 1 string to match.
265 return ARM::Q4; // "q4"
266 case '5': // 1 string to match.
267 return ARM::Q5; // "q5"
268 case '6': // 1 string to match.
269 return ARM::Q6; // "q6"
270 case '7': // 1 string to match.
271 return ARM::Q7; // "q7"
272 case '8': // 1 string to match.
273 return ARM::Q8; // "q8"
274 case '9': // 1 string to match.
275 return ARM::Q9; // "q9"
276 }
277 break;
278 case 'r': // 10 strings to match.
279 switch (Name[1]) {
280 default: break;
281 case '0': // 1 string to match.
282 return ARM::R0; // "r0"
283 case '1': // 1 string to match.
284 return ARM::R1; // "r1"
285 case '2': // 1 string to match.
286 return ARM::R2; // "r2"
287 case '3': // 1 string to match.
288 return ARM::R3; // "r3"
289 case '4': // 1 string to match.
290 return ARM::R4; // "r4"
291 case '5': // 1 string to match.
292 return ARM::R5; // "r5"
293 case '6': // 1 string to match.
294 return ARM::R6; // "r6"
295 case '7': // 1 string to match.
296 return ARM::R7; // "r7"
297 case '8': // 1 string to match.
298 return ARM::R8; // "r8"
299 case '9': // 1 string to match.
300 return ARM::R9; // "r9"
301 }
302 break;
303 case 's': // 11 strings to match.
304 switch (Name[1]) {
305 default: break;
306 case '0': // 1 string to match.
307 return ARM::S0; // "s0"
308 case '1': // 1 string to match.
309 return ARM::S1; // "s1"
310 case '2': // 1 string to match.
311 return ARM::S2; // "s2"
312 case '3': // 1 string to match.
313 return ARM::S3; // "s3"
314 case '4': // 1 string to match.
315 return ARM::S4; // "s4"
316 case '5': // 1 string to match.
317 return ARM::S5; // "s5"
318 case '6': // 1 string to match.
319 return ARM::S6; // "s6"
320 case '7': // 1 string to match.
321 return ARM::S7; // "s7"
322 case '8': // 1 string to match.
323 return ARM::S8; // "s8"
324 case '9': // 1 string to match.
325 return ARM::S9; // "s9"
326 case 'p': // 1 string to match.
327 return ARM::SP; // "sp"
328 }
329 break;
330 case 'z': // 1 string to match.
331 if (Name[1] != 'r')
332 break;
333 return ARM::ZR; // "zr"
334 }
335 break;
336 case 3: // 54 strings to match.
337 switch (Name[0]) {
338 default: break;
339 case 'd': // 22 strings to match.
340 switch (Name[1]) {
341 default: break;
342 case '1': // 10 strings to match.
343 switch (Name[2]) {
344 default: break;
345 case '0': // 1 string to match.
346 return ARM::D10; // "d10"
347 case '1': // 1 string to match.
348 return ARM::D11; // "d11"
349 case '2': // 1 string to match.
350 return ARM::D12; // "d12"
351 case '3': // 1 string to match.
352 return ARM::D13; // "d13"
353 case '4': // 1 string to match.
354 return ARM::D14; // "d14"
355 case '5': // 1 string to match.
356 return ARM::D15; // "d15"
357 case '6': // 1 string to match.
358 return ARM::D16; // "d16"
359 case '7': // 1 string to match.
360 return ARM::D17; // "d17"
361 case '8': // 1 string to match.
362 return ARM::D18; // "d18"
363 case '9': // 1 string to match.
364 return ARM::D19; // "d19"
365 }
366 break;
367 case '2': // 10 strings to match.
368 switch (Name[2]) {
369 default: break;
370 case '0': // 1 string to match.
371 return ARM::D20; // "d20"
372 case '1': // 1 string to match.
373 return ARM::D21; // "d21"
374 case '2': // 1 string to match.
375 return ARM::D22; // "d22"
376 case '3': // 1 string to match.
377 return ARM::D23; // "d23"
378 case '4': // 1 string to match.
379 return ARM::D24; // "d24"
380 case '5': // 1 string to match.
381 return ARM::D25; // "d25"
382 case '6': // 1 string to match.
383 return ARM::D26; // "d26"
384 case '7': // 1 string to match.
385 return ARM::D27; // "d27"
386 case '8': // 1 string to match.
387 return ARM::D28; // "d28"
388 case '9': // 1 string to match.
389 return ARM::D29; // "d29"
390 }
391 break;
392 case '3': // 2 strings to match.
393 switch (Name[2]) {
394 default: break;
395 case '0': // 1 string to match.
396 return ARM::D30; // "d30"
397 case '1': // 1 string to match.
398 return ARM::D31; // "d31"
399 }
400 break;
401 }
402 break;
403 case 'q': // 6 strings to match.
404 if (Name[1] != '1')
405 break;
406 switch (Name[2]) {
407 default: break;
408 case '0': // 1 string to match.
409 return ARM::Q10; // "q10"
410 case '1': // 1 string to match.
411 return ARM::Q11; // "q11"
412 case '2': // 1 string to match.
413 return ARM::Q12; // "q12"
414 case '3': // 1 string to match.
415 return ARM::Q13; // "q13"
416 case '4': // 1 string to match.
417 return ARM::Q14; // "q14"
418 case '5': // 1 string to match.
419 return ARM::Q15; // "q15"
420 }
421 break;
422 case 'r': // 3 strings to match.
423 if (Name[1] != '1')
424 break;
425 switch (Name[2]) {
426 default: break;
427 case '0': // 1 string to match.
428 return ARM::R10; // "r10"
429 case '1': // 1 string to match.
430 return ARM::R11; // "r11"
431 case '2': // 1 string to match.
432 return ARM::R12; // "r12"
433 }
434 break;
435 case 's': // 22 strings to match.
436 switch (Name[1]) {
437 default: break;
438 case '1': // 10 strings to match.
439 switch (Name[2]) {
440 default: break;
441 case '0': // 1 string to match.
442 return ARM::S10; // "s10"
443 case '1': // 1 string to match.
444 return ARM::S11; // "s11"
445 case '2': // 1 string to match.
446 return ARM::S12; // "s12"
447 case '3': // 1 string to match.
448 return ARM::S13; // "s13"
449 case '4': // 1 string to match.
450 return ARM::S14; // "s14"
451 case '5': // 1 string to match.
452 return ARM::S15; // "s15"
453 case '6': // 1 string to match.
454 return ARM::S16; // "s16"
455 case '7': // 1 string to match.
456 return ARM::S17; // "s17"
457 case '8': // 1 string to match.
458 return ARM::S18; // "s18"
459 case '9': // 1 string to match.
460 return ARM::S19; // "s19"
461 }
462 break;
463 case '2': // 10 strings to match.
464 switch (Name[2]) {
465 default: break;
466 case '0': // 1 string to match.
467 return ARM::S20; // "s20"
468 case '1': // 1 string to match.
469 return ARM::S21; // "s21"
470 case '2': // 1 string to match.
471 return ARM::S22; // "s22"
472 case '3': // 1 string to match.
473 return ARM::S23; // "s23"
474 case '4': // 1 string to match.
475 return ARM::S24; // "s24"
476 case '5': // 1 string to match.
477 return ARM::S25; // "s25"
478 case '6': // 1 string to match.
479 return ARM::S26; // "s26"
480 case '7': // 1 string to match.
481 return ARM::S27; // "s27"
482 case '8': // 1 string to match.
483 return ARM::S28; // "s28"
484 case '9': // 1 string to match.
485 return ARM::S29; // "s29"
486 }
487 break;
488 case '3': // 2 strings to match.
489 switch (Name[2]) {
490 default: break;
491 case '0': // 1 string to match.
492 return ARM::S30; // "s30"
493 case '1': // 1 string to match.
494 return ARM::S31; // "s31"
495 }
496 break;
497 }
498 break;
499 case 'v': // 1 string to match.
500 if (memcmp(Name.data()+1, "pr", 2) != 0)
501 break;
502 return ARM::VPR; // "vpr"
503 }
504 break;
505 case 4: // 3 strings to match.
506 switch (Name[0]) {
507 default: break;
508 case 'a': // 1 string to match.
509 if (memcmp(Name.data()+1, "psr", 3) != 0)
510 break;
511 return ARM::APSR; // "apsr"
512 case 'c': // 1 string to match.
513 if (memcmp(Name.data()+1, "psr", 3) != 0)
514 break;
515 return ARM::CPSR; // "cpsr"
516 case 's': // 1 string to match.
517 if (memcmp(Name.data()+1, "psr", 3) != 0)
518 break;
519 return ARM::SPSR; // "spsr"
520 }
521 break;
522 case 5: // 6 strings to match.
523 switch (Name[0]) {
524 default: break;
525 case 'f': // 3 strings to match.
526 if (Name[1] != 'p')
527 break;
528 switch (Name[2]) {
529 default: break;
530 case 'e': // 1 string to match.
531 if (memcmp(Name.data()+3, "xc", 2) != 0)
532 break;
533 return ARM::FPEXC; // "fpexc"
534 case 's': // 2 strings to match.
535 switch (Name[3]) {
536 default: break;
537 case 'c': // 1 string to match.
538 if (Name[4] != 'r')
539 break;
540 return ARM::FPSCR; // "fpscr"
541 case 'i': // 1 string to match.
542 if (Name[4] != 'd')
543 break;
544 return ARM::FPSID; // "fpsid"
545 }
546 break;
547 }
548 break;
549 case 'm': // 3 strings to match.
550 if (memcmp(Name.data()+1, "vfr", 3) != 0)
551 break;
552 switch (Name[4]) {
553 default: break;
554 case '0': // 1 string to match.
555 return ARM::MVFR0; // "mvfr0"
556 case '1': // 1 string to match.
557 return ARM::MVFR1; // "mvfr1"
558 case '2': // 1 string to match.
559 return ARM::MVFR2; // "mvfr2"
560 }
561 break;
562 }
563 break;
564 case 6: // 2 strings to match.
565 if (memcmp(Name.data()+0, "fp", 2) != 0)
566 break;
567 switch (Name[2]) {
568 default: break;
569 case 'c': // 1 string to match.
570 if (memcmp(Name.data()+3, "xts", 3) != 0)
571 break;
572 return ARM::FPCXTS; // "fpcxts"
573 case 'i': // 1 string to match.
574 if (memcmp(Name.data()+3, "nst", 3) != 0)
575 break;
576 return ARM::FPINST; // "fpinst"
577 }
578 break;
579 case 7: // 3 strings to match.
580 switch (Name[0]) {
581 default: break;
582 case 'f': // 2 strings to match.
583 if (Name[1] != 'p')
584 break;
585 switch (Name[2]) {
586 default: break;
587 case 'c': // 1 string to match.
588 if (memcmp(Name.data()+3, "xtns", 4) != 0)
589 break;
590 return ARM::FPCXTNS; // "fpcxtns"
591 case 'i': // 1 string to match.
592 if (memcmp(Name.data()+3, "nst2", 4) != 0)
593 break;
594 return ARM::FPINST2; // "fpinst2"
595 }
596 break;
597 case 'i': // 1 string to match.
598 if (memcmp(Name.data()+1, "tstate", 6) != 0)
599 break;
600 return ARM::ITSTATE; // "itstate"
601 }
602 break;
603 case 8: // 1 string to match.
604 if (memcmp(Name.data()+0, "fpscr_rm", 8) != 0)
605 break;
606 return ARM::FPSCR_RM; // "fpscr_rm"
607 case 9: // 1 string to match.
608 if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0)
609 break;
610 return ARM::APSR_NZCV; // "apsr_nzcv"
611 case 10: // 1 string to match.
612 if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0)
613 break;
614 return ARM::FPSCR_NZCV; // "fpscr_nzcv"
615 case 12: // 2 strings to match.
616 switch (Name[0]) {
617 default: break;
618 case 'f': // 1 string to match.
619 if (memcmp(Name.data()+1, "pscr_nzcvqc", 11) != 0)
620 break;
621 return ARM::FPSCR_NZCVQC; // "fpscr_nzcvqc"
622 case 'r': // 1 string to match.
623 if (memcmp(Name.data()+1, "a_auth_code", 11) != 0)
624 break;
625 return ARM::RA_AUTH_CODE; // "ra_auth_code"
626 }
627 break;
628 }
629 return ARM::NoRegister;
630}
631
632#endif // GET_REGISTER_MATCHER
633
634
635#ifdef GET_SUBTARGET_FEATURE_NAME
636#undef GET_SUBTARGET_FEATURE_NAME
637
638// User-level names for subtarget features that participate in
639// instruction matching.
640static const char *getSubtargetFeatureName(uint64_t Val) {
641 switch(Val) {
642 case Feature_HasV4TBit: return "armv4t";
643 case Feature_HasV5TBit: return "armv5t";
644 case Feature_HasV5TEBit: return "armv5te";
645 case Feature_HasV6Bit: return "armv6";
646 case Feature_HasV6MBit: return "armv6m or armv6t2";
647 case Feature_HasV8MBaselineBit: return "armv8m.base";
648 case Feature_HasV8MMainlineBit: return "armv8m.main";
649 case Feature_HasV8_1MMainlineBit: return "armv8.1m.main";
650 case Feature_HasMVEIntBit: return "mve";
651 case Feature_HasMVEFloatBit: return "mve.fp";
652 case Feature_HasCDEBit: return "cde";
653 case Feature_HasFPRegsBit: return "fp registers";
654 case Feature_HasFPRegs16Bit: return "16-bit fp registers";
655 case Feature_HasNoFPRegs16Bit: return "16-bit fp registers";
656 case Feature_HasFPRegs64Bit: return "64-bit fp registers";
657 case Feature_HasFPRegsV8_1MBit: return "armv8.1m.main with FP or MVE";
658 case Feature_HasV6T2Bit: return "armv6t2";
659 case Feature_HasV6KBit: return "armv6k";
660 case Feature_HasV7Bit: return "armv7";
661 case Feature_HasV8Bit: return "armv8";
662 case Feature_PreV8Bit: return "armv7 or earlier";
663 case Feature_HasV8_1aBit: return "armv8.1a";
664 case Feature_HasV8_2aBit: return "armv8.2a";
665 case Feature_HasV8_3aBit: return "armv8.3a";
666 case Feature_HasV8_4aBit: return "armv8.4a";
667 case Feature_HasV8_5aBit: return "armv8.5a";
668 case Feature_HasV8_6aBit: return "armv8.6a";
669 case Feature_HasV8_7aBit: return "armv8.7a";
670 case Feature_HasVFP2Bit: return "VFP2";
671 case Feature_HasVFP3Bit: return "VFP3";
672 case Feature_HasVFP4Bit: return "VFP4";
673 case Feature_HasDPVFPBit: return "double precision VFP";
674 case Feature_HasFPARMv8Bit: return "FPARMv8";
675 case Feature_HasNEONBit: return "NEON";
676 case Feature_HasSHA2Bit: return "sha2";
677 case Feature_HasAESBit: return "aes";
678 case Feature_HasCryptoBit: return "crypto";
679 case Feature_HasDotProdBit: return "dotprod";
680 case Feature_HasCRCBit: return "crc";
681 case Feature_HasRASBit: return "ras";
682 case Feature_HasLOBBit: return "lob";
683 case Feature_HasPACBTIBit: return "pacbti";
684 case Feature_HasFP16Bit: return "half-float conversions";
685 case Feature_HasFullFP16Bit: return "full half-float";
686 case Feature_HasFP16FMLBit: return "full half-float fml";
687 case Feature_HasBF16Bit: return "BFloat16 floating point extension";
688 case Feature_HasMatMulInt8Bit: return "8-bit integer matrix multiply";
689 case Feature_HasDivideInThumbBit: return "divide in THUMB";
690 case Feature_HasDivideInARMBit: return "divide in ARM";
691 case Feature_HasDSPBit: return "dsp";
692 case Feature_HasDBBit: return "data-barriers";
693 case Feature_HasDFBBit: return "full-data-barrier";
694 case Feature_HasV7ClrexBit: return "v7 clrex";
695 case Feature_HasAcquireReleaseBit: return "acquire/release";
696 case Feature_HasMPBit: return "mp-extensions";
697 case Feature_HasVirtualizationBit: return "virtualization-extensions";
698 case Feature_HasTrustZoneBit: return "TrustZone";
699 case Feature_Has8MSecExtBit: return "ARMv8-M Security Extensions";
700 case Feature_IsThumbBit: return "thumb";
701 case Feature_IsThumb2Bit: return "thumb2";
702 case Feature_IsMClassBit: return "armv*m";
703 case Feature_IsNotMClassBit: return "!armv*m";
704 case Feature_IsARMBit: return "arm-mode";
705 case Feature_UseNegativeImmediatesBit: return "NegativeImmediates";
706 case Feature_HasSBBit: return "sb";
707 case Feature_HasCLRBHBBit: return "clrbhb";
708 default: return "(unknown)";
709 }
710}
711
712#endif // GET_SUBTARGET_FEATURE_NAME
713
714
715#ifdef GET_MATCHER_IMPLEMENTATION
716#undef GET_MATCHER_IMPLEMENTATION
717
718static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
719 switch (VariantID) {
720 case 0:
721 break;
722 }
723 switch (Mnemonic.size()) {
724 default: break;
725 case 3: // 4 strings to match.
726 switch (Mnemonic[0]) {
727 default: break;
728 case 'r': // 1 string to match.
729 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
730 break;
731 Mnemonic = "rfeia"; // "rfe"
732 return;
733 case 's': // 3 strings to match.
734 switch (Mnemonic[1]) {
735 default: break;
736 case 'm': // 1 string to match.
737 if (Mnemonic[2] != 'i')
738 break;
739 Mnemonic = "smc"; // "smi"
740 return;
741 case 'r': // 1 string to match.
742 if (Mnemonic[2] != 's')
743 break;
744 Mnemonic = "srsia"; // "srs"
745 return;
746 case 'w': // 1 string to match.
747 if (Mnemonic[2] != 'i')
748 break;
749 Mnemonic = "svc"; // "swi"
750 return;
751 }
752 break;
753 }
754 break;
755 case 4: // 10 strings to match.
756 switch (Mnemonic[0]) {
757 default: break;
758 case 'f': // 8 strings to match.
759 switch (Mnemonic[1]) {
760 default: break;
761 case 'l': // 2 strings to match.
762 if (Mnemonic[2] != 'd')
763 break;
764 switch (Mnemonic[3]) {
765 default: break;
766 case 'd': // 1 string to match.
767 if (Features.test(Feature_HasVFP2Bit)) // "fldd"
768 Mnemonic = "vldr";
769 return;
770 case 's': // 1 string to match.
771 if (Features.test(Feature_HasVFP2Bit)) // "flds"
772 Mnemonic = "vldr";
773 return;
774 }
775 break;
776 case 'm': // 4 strings to match.
777 switch (Mnemonic[2]) {
778 default: break;
779 case 'r': // 2 strings to match.
780 switch (Mnemonic[3]) {
781 default: break;
782 case 's': // 1 string to match.
783 if (Features.test(Feature_HasVFP2Bit)) // "fmrs"
784 Mnemonic = "vmov";
785 return;
786 case 'x': // 1 string to match.
787 if (Features.test(Feature_HasVFP2Bit)) // "fmrx"
788 Mnemonic = "vmrs";
789 return;
790 }
791 break;
792 case 's': // 1 string to match.
793 if (Mnemonic[3] != 'r')
794 break;
795 if (Features.test(Feature_HasVFP2Bit)) // "fmsr"
796 Mnemonic = "vmov";
797 return;
798 case 'x': // 1 string to match.
799 if (Mnemonic[3] != 'r')
800 break;
801 if (Features.test(Feature_HasVFP2Bit)) // "fmxr"
802 Mnemonic = "vmsr";
803 return;
804 }
805 break;
806 case 's': // 2 strings to match.
807 if (Mnemonic[2] != 't')
808 break;
809 switch (Mnemonic[3]) {
810 default: break;
811 case 'd': // 1 string to match.
812 if (Features.test(Feature_HasVFP2Bit)) // "fstd"
813 Mnemonic = "vstr";
814 return;
815 case 's': // 1 string to match.
816 if (Features.test(Feature_HasVFP2Bit)) // "fsts"
817 Mnemonic = "vstr";
818 return;
819 }
820 break;
821 }
822 break;
823 case 'v': // 2 strings to match.
824 switch (Mnemonic[1]) {
825 default: break;
826 case 'l': // 1 string to match.
827 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
828 break;
829 Mnemonic = "vldmia"; // "vldm"
830 return;
831 case 's': // 1 string to match.
832 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
833 break;
834 Mnemonic = "vstmia"; // "vstm"
835 return;
836 }
837 break;
838 }
839 break;
840 case 5: // 51 strings to match.
841 switch (Mnemonic[0]) {
842 default: break;
843 case 'f': // 18 strings to match.
844 switch (Mnemonic[1]) {
845 default: break;
846 case 'a': // 2 strings to match.
847 if (memcmp(Mnemonic.data()+2, "dd", 2) != 0)
848 break;
849 switch (Mnemonic[4]) {
850 default: break;
851 case 'd': // 1 string to match.
852 if (Features.test(Feature_HasVFP2Bit)) // "faddd"
853 Mnemonic = "vadd.f64";
854 return;
855 case 's': // 1 string to match.
856 if (Features.test(Feature_HasVFP2Bit)) // "fadds"
857 Mnemonic = "vadd.f32";
858 return;
859 }
860 break;
861 case 'c': // 4 strings to match.
862 switch (Mnemonic[2]) {
863 default: break;
864 case 'm': // 2 strings to match.
865 if (Mnemonic[3] != 'p')
866 break;
867 switch (Mnemonic[4]) {
868 default: break;
869 case 'd': // 1 string to match.
870 if (Features.test(Feature_HasVFP2Bit)) // "fcmpd"
871 Mnemonic = "vcmp.f64";
872 return;
873 case 's': // 1 string to match.
874 if (Features.test(Feature_HasVFP2Bit)) // "fcmps"
875 Mnemonic = "vcmp.f32";
876 return;
877 }
878 break;
879 case 'p': // 2 strings to match.
880 if (Mnemonic[3] != 'y')
881 break;
882 switch (Mnemonic[4]) {
883 default: break;
884 case 'd': // 1 string to match.
885 if (Features.test(Feature_HasVFP2Bit)) // "fcpyd"
886 Mnemonic = "vmov.f64";
887 return;
888 case 's': // 1 string to match.
889 if (Features.test(Feature_HasVFP2Bit)) // "fcpys"
890 Mnemonic = "vmov.f32";
891 return;
892 }
893 break;
894 }
895 break;
896 case 'd': // 2 strings to match.
897 if (memcmp(Mnemonic.data()+2, "iv", 2) != 0)
898 break;
899 switch (Mnemonic[4]) {
900 default: break;
901 case 'd': // 1 string to match.
902 if (Features.test(Feature_HasVFP2Bit)) // "fdivd"
903 Mnemonic = "vdiv.f64";
904 return;
905 case 's': // 1 string to match.
906 if (Features.test(Feature_HasVFP2Bit)) // "fdivs"
907 Mnemonic = "vdiv.f32";
908 return;
909 }
910 break;
911 case 'm': // 8 strings to match.
912 switch (Mnemonic[2]) {
913 default: break;
914 case 'a': // 2 strings to match.
915 if (Mnemonic[3] != 'c')
916 break;
917 switch (Mnemonic[4]) {
918 default: break;
919 case 'd': // 1 string to match.
920 if (Features.test(Feature_HasVFP2Bit)) // "fmacd"
921 Mnemonic = "vmla.f64";
922 return;
923 case 's': // 1 string to match.
924 if (Features.test(Feature_HasVFP2Bit)) // "fmacs"
925 Mnemonic = "vmla.f32";
926 return;
927 }
928 break;
929 case 'd': // 1 string to match.
930 if (memcmp(Mnemonic.data()+3, "rr", 2) != 0)
931 break;
932 if (Features.test(Feature_HasVFP2Bit)) // "fmdrr"
933 Mnemonic = "vmov";
934 return;
935 case 'r': // 3 strings to match.
936 switch (Mnemonic[3]) {
937 default: break;
938 case 'd': // 2 strings to match.
939 switch (Mnemonic[4]) {
940 default: break;
941 case 'd': // 1 string to match.
942 if (Features.test(Feature_HasVFP2Bit)) // "fmrdd"
943 Mnemonic = "vmov";
944 return;
945 case 's': // 1 string to match.
946 if (Features.test(Feature_HasVFP2Bit)) // "fmrds"
947 Mnemonic = "vmov";
948 return;
949 }
950 break;
951 case 'r': // 1 string to match.
952 if (Mnemonic[4] != 'd')
953 break;
954 if (Features.test(Feature_HasVFP2Bit)) // "fmrrd"
955 Mnemonic = "vmov";
956 return;
957 }
958 break;
959 case 'u': // 2 strings to match.
960 if (Mnemonic[3] != 'l')
961 break;
962 switch (Mnemonic[4]) {
963 default: break;
964 case 'd': // 1 string to match.
965 if (Features.test(Feature_HasVFP2Bit)) // "fmuld"
966 Mnemonic = "vmul.f64";
967 return;
968 case 's': // 1 string to match.
969 if (Features.test(Feature_HasVFP2Bit)) // "fmuls"
970 Mnemonic = "vmul.f32";
971 return;
972 }
973 break;
974 }
975 break;
976 case 'n': // 2 strings to match.
977 if (memcmp(Mnemonic.data()+2, "eg", 2) != 0)
978 break;
979 switch (Mnemonic[4]) {
980 default: break;
981 case 'd': // 1 string to match.
982 if (Features.test(Feature_HasVFP2Bit)) // "fnegd"
983 Mnemonic = "vneg.f64";
984 return;
985 case 's': // 1 string to match.
986 if (Features.test(Feature_HasVFP2Bit)) // "fnegs"
987 Mnemonic = "vneg.f32";
988 return;
989 }
990 break;
991 }
992 break;
993 case 'l': // 3 strings to match.
994 if (memcmp(Mnemonic.data()+1, "dm", 2) != 0)
995 break;
996 switch (Mnemonic[3]) {
997 default: break;
998 case 'e': // 1 string to match.
999 if (Mnemonic[4] != 'a')
1000 break;
1001 Mnemonic = "ldmdb"; // "ldmea"
1002 return;
1003 case 'f': // 1 string to match.
1004 if (Mnemonic[4] != 'd')
1005 break;
1006 Mnemonic = "ldm"; // "ldmfd"
1007 return;
1008 case 'i': // 1 string to match.
1009 if (Mnemonic[4] != 'a')
1010 break;
1011 Mnemonic = "ldm"; // "ldmia"
1012 return;
1013 }
1014 break;
1015 case 'r': // 4 strings to match.
1016 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0)
1017 break;
1018 switch (Mnemonic[3]) {
1019 default: break;
1020 case 'e': // 2 strings to match.
1021 switch (Mnemonic[4]) {
1022 default: break;
1023 case 'a': // 1 string to match.
1024 Mnemonic = "rfedb"; // "rfeea"
1025 return;
1026 case 'd': // 1 string to match.
1027 Mnemonic = "rfeib"; // "rfeed"
1028 return;
1029 }
1030 break;
1031 case 'f': // 2 strings to match.
1032 switch (Mnemonic[4]) {
1033 default: break;
1034 case 'a': // 1 string to match.
1035 Mnemonic = "rfeda"; // "rfefa"
1036 return;
1037 case 'd': // 1 string to match.
1038 Mnemonic = "rfeia"; // "rfefd"
1039 return;
1040 }
1041 break;
1042 }
1043 break;
1044 case 's': // 7 strings to match.
1045 switch (Mnemonic[1]) {
1046 default: break;
1047 case 'r': // 4 strings to match.
1048 if (Mnemonic[2] != 's')
1049 break;
1050 switch (Mnemonic[3]) {
1051 default: break;
1052 case 'e': // 2 strings to match.
1053 switch (Mnemonic[4]) {
1054 default: break;
1055 case 'a': // 1 string to match.
1056 Mnemonic = "srsia"; // "srsea"
1057 return;
1058 case 'd': // 1 string to match.
1059 Mnemonic = "srsda"; // "srsed"
1060 return;
1061 }
1062 break;
1063 case 'f': // 2 strings to match.
1064 switch (Mnemonic[4]) {
1065 default: break;
1066 case 'a': // 1 string to match.
1067 Mnemonic = "srsib"; // "srsfa"
1068 return;
1069 case 'd': // 1 string to match.
1070 Mnemonic = "srsdb"; // "srsfd"
1071 return;
1072 }
1073 break;
1074 }
1075 break;
1076 case 't': // 3 strings to match.
1077 if (Mnemonic[2] != 'm')
1078 break;
1079 switch (Mnemonic[3]) {
1080 default: break;
1081 case 'e': // 1 string to match.
1082 if (Mnemonic[4] != 'a')
1083 break;
1084 Mnemonic = "stm"; // "stmea"
1085 return;
1086 case 'f': // 1 string to match.
1087 if (Mnemonic[4] != 'd')
1088 break;
1089 Mnemonic = "stmdb"; // "stmfd"
1090 return;
1091 case 'i': // 1 string to match.
1092 if (Mnemonic[4] != 'a')
1093 break;
1094 Mnemonic = "stm"; // "stmia"
1095 return;
1096 }
1097 break;
1098 }
1099 break;
1100 case 'v': // 19 strings to match.
1101 switch (Mnemonic[1]) {
1102 default: break;
1103 case 'a': // 3 strings to match.
1104 switch (Mnemonic[2]) {
1105 default: break;
1106 case 'b': // 1 string to match.
1107 if (memcmp(Mnemonic.data()+3, "sq", 2) != 0)
1108 break;
1109 if (Features.test(Feature_HasNEONBit)) // "vabsq"
1110 Mnemonic = "vabs";
1111 return;
1112 case 'd': // 1 string to match.
1113 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
1114 break;
1115 if (Features.test(Feature_HasNEONBit)) // "vaddq"
1116 Mnemonic = "vadd";
1117 return;
1118 case 'n': // 1 string to match.
1119 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0)
1120 break;
1121 if (Features.test(Feature_HasNEONBit)) // "vandq"
1122 Mnemonic = "vand";
1123 return;
1124 }
1125 break;
1126 case 'b': // 1 string to match.
1127 if (memcmp(Mnemonic.data()+2, "icq", 3) != 0)
1128 break;
1129 if (Features.test(Feature_HasNEONBit)) // "vbicq"
1130 Mnemonic = "vbic";
1131 return;
1132 case 'c': // 3 strings to match.
1133 switch (Mnemonic[2]) {
1134 default: break;
1135 case 'e': // 1 string to match.
1136 if (memcmp(Mnemonic.data()+3, "qq", 2) != 0)
1137 break;
1138 if (Features.test(Feature_HasNEONBit)) // "vceqq"
1139 Mnemonic = "vceq";
1140 return;
1141 case 'l': // 1 string to match.
1142 if (memcmp(Mnemonic.data()+3, "eq", 2) != 0)
1143 break;
1144 if (Features.test(Feature_HasNEONBit)) // "vcleq"
1145 Mnemonic = "vcle";
1146 return;
1147 case 'v': // 1 string to match.
1148 if (memcmp(Mnemonic.data()+3, "tq", 2) != 0)
1149 break;
1150 if (Features.test(Feature_HasNEONBit)) // "vcvtq"
1151 Mnemonic = "vcvt";
1152 return;
1153 }
1154 break;
1155 case 'e': // 1 string to match.
1156 if (memcmp(Mnemonic.data()+2, "orq", 3) != 0)
1157 break;
1158 if (Features.test(Feature_HasNEONBit)) // "veorq"
1159 Mnemonic = "veor";
1160 return;
1161 case 'm': // 5 strings to match.
1162 switch (Mnemonic[2]) {
1163 default: break;
1164 case 'a': // 1 string to match.
1165 if (memcmp(Mnemonic.data()+3, "xq", 2) != 0)
1166 break;
1167 if (Features.test(Feature_HasNEONBit)) // "vmaxq"
1168 Mnemonic = "vmax";
1169 return;
1170 case 'i': // 1 string to match.
1171 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1172 break;
1173 if (Features.test(Feature_HasNEONBit)) // "vminq"
1174 Mnemonic = "vmin";
1175 return;
1176 case 'o': // 1 string to match.
1177 if (memcmp(Mnemonic.data()+3, "vq", 2) != 0)
1178 break;
1179 if (Features.test(Feature_HasNEONBit)) // "vmovq"
1180 Mnemonic = "vmov";
1181 return;
1182 case 'u': // 1 string to match.
1183 if (memcmp(Mnemonic.data()+3, "lq", 2) != 0)
1184 break;
1185 if (Features.test(Feature_HasNEONBit)) // "vmulq"
1186 Mnemonic = "vmul";
1187 return;
1188 case 'v': // 1 string to match.
1189 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0)
1190 break;
1191 if (Features.test(Feature_HasNEONBit)) // "vmvnq"
1192 Mnemonic = "vmvn";
1193 return;
1194 }
1195 break;
1196 case 'o': // 1 string to match.
1197 if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0)
1198 break;
1199 if (Features.test(Feature_HasNEONBit)) // "vorrq"
1200 Mnemonic = "vorr";
1201 return;
1202 case 's': // 4 strings to match.
1203 switch (Mnemonic[2]) {
1204 default: break;
1205 case 'h': // 2 strings to match.
1206 switch (Mnemonic[3]) {
1207 default: break;
1208 case 'l': // 1 string to match.
1209 if (Mnemonic[4] != 'q')
1210 break;
1211 if (Features.test(Feature_HasNEONBit)) // "vshlq"
1212 Mnemonic = "vshl";
1213 return;
1214 case 'r': // 1 string to match.
1215 if (Mnemonic[4] != 'q')
1216 break;
1217 if (Features.test(Feature_HasNEONBit)) // "vshrq"
1218 Mnemonic = "vshr";
1219 return;
1220 }
1221 break;
1222 case 'u': // 1 string to match.
1223 if (memcmp(Mnemonic.data()+3, "bq", 2) != 0)
1224 break;
1225 if (Features.test(Feature_HasNEONBit)) // "vsubq"
1226 Mnemonic = "vsub";
1227 return;
1228 case 'w': // 1 string to match.
1229 if (memcmp(Mnemonic.data()+3, "pq", 2) != 0)
1230 break;
1231 if (Features.test(Feature_HasNEONBit)) // "vswpq"
1232 Mnemonic = "vswp";
1233 return;
1234 }
1235 break;
1236 case 'z': // 1 string to match.
1237 if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0)
1238 break;
1239 if (Features.test(Feature_HasNEONBit)) // "vzipq"
1240 Mnemonic = "vzip";
1241 return;
1242 }
1243 break;
1244 }
1245 break;
1246 case 6: // 10 strings to match.
1247 if (Mnemonic[0] != 'f')
1248 break;
1249 switch (Mnemonic[1]) {
1250 default: break;
1251 case 's': // 4 strings to match.
1252 switch (Mnemonic[2]) {
1253 default: break;
1254 case 'i': // 2 strings to match.
1255 if (memcmp(Mnemonic.data()+3, "to", 2) != 0)
1256 break;
1257 switch (Mnemonic[5]) {
1258 default: break;
1259 case 'd': // 1 string to match.
1260 if (Features.test(Feature_HasVFP2Bit)) // "fsitod"
1261 Mnemonic = "vcvt.f64.s32";
1262 return;
1263 case 's': // 1 string to match.
1264 if (Features.test(Feature_HasVFP2Bit)) // "fsitos"
1265 Mnemonic = "vcvt.f32.s32";
1266 return;
1267 }
1268 break;
1269 case 'q': // 2 strings to match.
1270 if (memcmp(Mnemonic.data()+3, "rt", 2) != 0)
1271 break;
1272 switch (Mnemonic[5]) {
1273 default: break;
1274 case 'd': // 1 string to match.
1275 if (Features.test(Feature_HasVFP2Bit)) // "fsqrtd"
1276 Mnemonic = "vsqrt";
1277 return;
1278 case 's': // 1 string to match.
1279 if (Features.test(Feature_HasVFP2Bit)) // "fsqrts"
1280 Mnemonic = "vsqrt";
1281 return;
1282 }
1283 break;
1284 }
1285 break;
1286 case 't': // 4 strings to match.
1287 if (Mnemonic[2] != 'o')
1288 break;
1289 switch (Mnemonic[3]) {
1290 default: break;
1291 case 's': // 2 strings to match.
1292 if (Mnemonic[4] != 'i')
1293 break;
1294 switch (Mnemonic[5]) {
1295 default: break;
1296 case 'd': // 1 string to match.
1297 if (Features.test(Feature_HasVFP2Bit)) // "ftosid"
1298 Mnemonic = "vcvtr.s32.f64";
1299 return;
1300 case 's': // 1 string to match.
1301 if (Features.test(Feature_HasVFP2Bit)) // "ftosis"
1302 Mnemonic = "vcvtr.s32.f32";
1303 return;
1304 }
1305 break;
1306 case 'u': // 2 strings to match.
1307 if (Mnemonic[4] != 'i')
1308 break;
1309 switch (Mnemonic[5]) {
1310 default: break;
1311 case 'd': // 1 string to match.
1312 if (Features.test(Feature_HasVFP2Bit)) // "ftouid"
1313 Mnemonic = "vcvtr.u32.f64";
1314 return;
1315 case 's': // 1 string to match.
1316 if (Features.test(Feature_HasVFP2Bit)) // "ftouis"
1317 Mnemonic = "vcvtr.u32.f32";
1318 return;
1319 }
1320 break;
1321 }
1322 break;
1323 case 'u': // 2 strings to match.
1324 if (memcmp(Mnemonic.data()+2, "ito", 3) != 0)
1325 break;
1326 switch (Mnemonic[5]) {
1327 default: break;
1328 case 'd': // 1 string to match.
1329 if (Features.test(Feature_HasVFP2Bit)) // "fuitod"
1330 Mnemonic = "vcvt.f64.u32";
1331 return;
1332 case 's': // 1 string to match.
1333 if (Features.test(Feature_HasVFP2Bit)) // "fuitos"
1334 Mnemonic = "vcvt.f32.u32";
1335 return;
1336 }
1337 break;
1338 }
1339 break;
1340 case 7: // 9 strings to match.
1341 switch (Mnemonic[0]) {
1342 default: break;
1343 case 'f': // 8 strings to match.
1344 switch (Mnemonic[1]) {
1345 default: break;
1346 case 'l': // 2 strings to match.
1347 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0)
1348 break;
1349 switch (Mnemonic[4]) {
1350 default: break;
1351 case 'e': // 1 string to match.
1352 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1353 break;
1354 if (Features.test(Feature_HasVFP2Bit)) // "fldmeax"
1355 Mnemonic = "fldmdbx";
1356 return;
1357 case 'f': // 1 string to match.
1358 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1359 break;
1360 if (Features.test(Feature_HasVFP2Bit)) // "fldmfdx"
1361 Mnemonic = "fldmiax";
1362 return;
1363 }
1364 break;
1365 case 's': // 2 strings to match.
1366 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0)
1367 break;
1368 switch (Mnemonic[4]) {
1369 default: break;
1370 case 'e': // 1 string to match.
1371 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0)
1372 break;
1373 if (Features.test(Feature_HasVFP2Bit)) // "fstmeax"
1374 Mnemonic = "fstmiax";
1375 return;
1376 case 'f': // 1 string to match.
1377 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0)
1378 break;
1379 if (Features.test(Feature_HasVFP2Bit)) // "fstmfdx"
1380 Mnemonic = "fstmdbx";
1381 return;
1382 }
1383 break;
1384 case 't': // 4 strings to match.
1385 if (Mnemonic[2] != 'o')
1386 break;
1387 switch (Mnemonic[3]) {
1388 default: break;
1389 case 's': // 2 strings to match.
1390 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1391 break;
1392 switch (Mnemonic[6]) {
1393 default: break;
1394 case 'd': // 1 string to match.
1395 if (Features.test(Feature_HasVFP2Bit)) // "ftosizd"
1396 Mnemonic = "vcvt.s32.f64";
1397 return;
1398 case 's': // 1 string to match.
1399 if (Features.test(Feature_HasVFP2Bit)) // "ftosizs"
1400 Mnemonic = "vcvt.s32.f32";
1401 return;
1402 }
1403 break;
1404 case 'u': // 2 strings to match.
1405 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0)
1406 break;
1407 switch (Mnemonic[6]) {
1408 default: break;
1409 case 'd': // 1 string to match.
1410 if (Features.test(Feature_HasVFP2Bit)) // "ftouizd"
1411 Mnemonic = "vcvt.u32.f64";
1412 return;
1413 case 's': // 1 string to match.
1414 if (Features.test(Feature_HasVFP2Bit)) // "ftouizs"
1415 Mnemonic = "vcvt.u32.f32";
1416 return;
1417 }
1418 break;
1419 }
1420 break;
1421 }
1422 break;
1423 case 'v': // 1 string to match.
1424 if (memcmp(Mnemonic.data()+1, "ldrb.8", 6) != 0)
1425 break;
1426 Mnemonic = "vldrb.u8"; // "vldrb.8"
1427 return;
1428 }
1429 break;
1430 case 8: // 13 strings to match.
1431 switch (Mnemonic[0]) {
1432 default: break;
1433 case 'q': // 1 string to match.
1434 if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0)
1435 break;
1436 Mnemonic = "qsax"; // "qsubaddx"
1437 return;
1438 case 's': // 2 strings to match.
1439 switch (Mnemonic[1]) {
1440 default: break;
1441 case 'a': // 1 string to match.
1442 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1443 break;
1444 Mnemonic = "sasx"; // "saddsubx"
1445 return;
1446 case 's': // 1 string to match.
1447 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1448 break;
1449 Mnemonic = "ssax"; // "ssubaddx"
1450 return;
1451 }
1452 break;
1453 case 'u': // 2 strings to match.
1454 switch (Mnemonic[1]) {
1455 default: break;
1456 case 'a': // 1 string to match.
1457 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0)
1458 break;
1459 Mnemonic = "uasx"; // "uaddsubx"
1460 return;
1461 case 's': // 1 string to match.
1462 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0)
1463 break;
1464 Mnemonic = "usax"; // "usubaddx"
1465 return;
1466 }
1467 break;
1468 case 'v': // 8 strings to match.
1469 switch (Mnemonic[1]) {
1470 default: break;
1471 case 'l': // 6 strings to match.
1472 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0)
1473 break;
1474 switch (Mnemonic[4]) {
1475 default: break;
1476 case 'b': // 3 strings to match.
1477 switch (Mnemonic[5]) {
1478 default: break;
1479 case '.': // 1 string to match.
1480 if (memcmp(Mnemonic.data()+6, "s8", 2) != 0)
1481 break;
1482 Mnemonic = "vldrb.u8"; // "vldrb.s8"
1483 return;
1484 case 'e': // 1 string to match.
1485 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0)
1486 break;
1487 Mnemonic = "vldrbe.u8"; // "vldrbe.8"
1488 return;
1489 case 't': // 1 string to match.
1490 if (memcmp(Mnemonic.data()+6, ".8", 2) != 0)
1491 break;
1492 Mnemonic = "vldrbt.u8"; // "vldrbt.8"
1493 return;
1494 }
1495 break;
1496 case 'd': // 1 string to match.
1497 if (memcmp(Mnemonic.data()+5, ".64", 3) != 0)
1498 break;
1499 Mnemonic = "vldrd.u64"; // "vldrd.64"
1500 return;
1501 case 'h': // 1 string to match.
1502 if (memcmp(Mnemonic.data()+5, ".16", 3) != 0)
1503 break;
1504 Mnemonic = "vldrh.u16"; // "vldrh.16"
1505 return;
1506 case 'w': // 1 string to match.
1507 if (memcmp(Mnemonic.data()+5, ".32", 3) != 0)
1508 break;
1509 Mnemonic = "vldrw.u32"; // "vldrw.32"
1510 return;
1511 }
1512 break;
1513 case 's': // 2 strings to match.
1514 if (memcmp(Mnemonic.data()+2, "trb.", 4) != 0)
1515 break;
1516 switch (Mnemonic[6]) {
1517 default: break;
1518 case 's': // 1 string to match.
1519 if (Mnemonic[7] != '8')
1520 break;
1521 Mnemonic = "vstrb.8"; // "vstrb.s8"
1522 return;
1523 case 'u': // 1 string to match.
1524 if (Mnemonic[7] != '8')
1525 break;
1526 Mnemonic = "vstrb.8"; // "vstrb.u8"
1527 return;
1528 }
1529 break;
1530 }
1531 break;
1532 }
1533 break;
1534 case 9: // 35 strings to match.
1535 switch (Mnemonic[0]) {
1536 default: break;
1537 case 's': // 2 strings to match.
1538 if (Mnemonic[1] != 'h')
1539 break;
1540 switch (Mnemonic[2]) {
1541 default: break;
1542 case 'a': // 1 string to match.
1543 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1544 break;
1545 Mnemonic = "shasx"; // "shaddsubx"
1546 return;
1547 case 's': // 1 string to match.
1548 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1549 break;
1550 Mnemonic = "shsax"; // "shsubaddx"
1551 return;
1552 }
1553 break;
1554 case 'u': // 4 strings to match.
1555 switch (Mnemonic[1]) {
1556 default: break;
1557 case 'h': // 2 strings to match.
1558 switch (Mnemonic[2]) {
1559 default: break;
1560 case 'a': // 1 string to match.
1561 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1562 break;
1563 Mnemonic = "uhasx"; // "uhaddsubx"
1564 return;
1565 case 's': // 1 string to match.
1566 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1567 break;
1568 Mnemonic = "uhsax"; // "uhsubaddx"
1569 return;
1570 }
1571 break;
1572 case 'q': // 2 strings to match.
1573 switch (Mnemonic[2]) {
1574 default: break;
1575 case 'a': // 1 string to match.
1576 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0)
1577 break;
1578 Mnemonic = "uqasx"; // "uqaddsubx"
1579 return;
1580 case 's': // 1 string to match.
1581 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0)
1582 break;
1583 Mnemonic = "uqsax"; // "uqsubaddx"
1584 return;
1585 }
1586 break;
1587 }
1588 break;
1589 case 'v': // 29 strings to match.
1590 switch (Mnemonic[1]) {
1591 default: break;
1592 case 'l': // 14 strings to match.
1593 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0)
1594 break;
1595 switch (Mnemonic[4]) {
1596 default: break;
1597 case 'b': // 2 strings to match.
1598 switch (Mnemonic[5]) {
1599 default: break;
1600 case 'e': // 1 string to match.
1601 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0)
1602 break;
1603 Mnemonic = "vldrbe.u8"; // "vldrbe.s8"
1604 return;
1605 case 't': // 1 string to match.
1606 if (memcmp(Mnemonic.data()+6, ".s8", 3) != 0)
1607 break;
1608 Mnemonic = "vldrbt.u8"; // "vldrbt.s8"
1609 return;
1610 }
1611 break;
1612 case 'd': // 4 strings to match.
1613 switch (Mnemonic[5]) {
1614 default: break;
1615 case '.': // 2 strings to match.
1616 switch (Mnemonic[6]) {
1617 default: break;
1618 case 'f': // 1 string to match.
1619 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1620 break;
1621 Mnemonic = "vldrd.u64"; // "vldrd.f64"
1622 return;
1623 case 's': // 1 string to match.
1624 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1625 break;
1626 Mnemonic = "vldrd.u64"; // "vldrd.s64"
1627 return;
1628 }
1629 break;
1630 case 'e': // 1 string to match.
1631 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0)
1632 break;
1633 Mnemonic = "vldrde.u64"; // "vldrde.64"
1634 return;
1635 case 't': // 1 string to match.
1636 if (memcmp(Mnemonic.data()+6, ".64", 3) != 0)
1637 break;
1638 Mnemonic = "vldrdt.u64"; // "vldrdt.64"
1639 return;
1640 }
1641 break;
1642 case 'h': // 4 strings to match.
1643 switch (Mnemonic[5]) {
1644 default: break;
1645 case '.': // 2 strings to match.
1646 switch (Mnemonic[6]) {
1647 default: break;
1648 case 'f': // 1 string to match.
1649 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1650 break;
1651 Mnemonic = "vldrh.u16"; // "vldrh.f16"
1652 return;
1653 case 's': // 1 string to match.
1654 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1655 break;
1656 Mnemonic = "vldrh.u16"; // "vldrh.s16"
1657 return;
1658 }
1659 break;
1660 case 'e': // 1 string to match.
1661 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0)
1662 break;
1663 Mnemonic = "vldrhe.u16"; // "vldrhe.16"
1664 return;
1665 case 't': // 1 string to match.
1666 if (memcmp(Mnemonic.data()+6, ".16", 3) != 0)
1667 break;
1668 Mnemonic = "vldrht.u16"; // "vldrht.16"
1669 return;
1670 }
1671 break;
1672 case 'w': // 4 strings to match.
1673 switch (Mnemonic[5]) {
1674 default: break;
1675 case '.': // 2 strings to match.
1676 switch (Mnemonic[6]) {
1677 default: break;
1678 case 'f': // 1 string to match.
1679 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1680 break;
1681 Mnemonic = "vldrw.u32"; // "vldrw.f32"
1682 return;
1683 case 's': // 1 string to match.
1684 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1685 break;
1686 Mnemonic = "vldrw.u32"; // "vldrw.s32"
1687 return;
1688 }
1689 break;
1690 case 'e': // 1 string to match.
1691 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0)
1692 break;
1693 Mnemonic = "vldrwe.u32"; // "vldrwe.32"
1694 return;
1695 case 't': // 1 string to match.
1696 if (memcmp(Mnemonic.data()+6, ".32", 3) != 0)
1697 break;
1698 Mnemonic = "vldrwt.u32"; // "vldrwt.32"
1699 return;
1700 }
1701 break;
1702 }
1703 break;
1704 case 'm': // 2 strings to match.
1705 if (memcmp(Mnemonic.data()+2, "ovq.f", 5) != 0)
1706 break;
1707 switch (Mnemonic[7]) {
1708 default: break;
1709 case '3': // 1 string to match.
1710 if (Mnemonic[8] != '2')
1711 break;
1712 if (Features.test(Feature_HasNEONBit)) // "vmovq.f32"
1713 Mnemonic = "vmov.f32";
1714 return;
1715 case '6': // 1 string to match.
1716 if (Mnemonic[8] != '4')
1717 break;
1718 if (Features.test(Feature_HasNEONBit)) // "vmovq.f64"
1719 Mnemonic = "vmov.f64";
1720 return;
1721 }
1722 break;
1723 case 's': // 13 strings to match.
1724 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0)
1725 break;
1726 switch (Mnemonic[4]) {
1727 default: break;
1728 case 'b': // 4 strings to match.
1729 switch (Mnemonic[5]) {
1730 default: break;
1731 case 'e': // 2 strings to match.
1732 if (Mnemonic[6] != '.')
1733 break;
1734 switch (Mnemonic[7]) {
1735 default: break;
1736 case 's': // 1 string to match.
1737 if (Mnemonic[8] != '8')
1738 break;
1739 Mnemonic = "vstrbe.8"; // "vstrbe.s8"
1740 return;
1741 case 'u': // 1 string to match.
1742 if (Mnemonic[8] != '8')
1743 break;
1744 Mnemonic = "vstrbe.8"; // "vstrbe.u8"
1745 return;
1746 }
1747 break;
1748 case 't': // 2 strings to match.
1749 if (Mnemonic[6] != '.')
1750 break;
1751 switch (Mnemonic[7]) {
1752 default: break;
1753 case 's': // 1 string to match.
1754 if (Mnemonic[8] != '8')
1755 break;
1756 Mnemonic = "vstrbt.8"; // "vstrbt.s8"
1757 return;
1758 case 'u': // 1 string to match.
1759 if (Mnemonic[8] != '8')
1760 break;
1761 Mnemonic = "vstrbt.8"; // "vstrbt.u8"
1762 return;
1763 }
1764 break;
1765 }
1766 break;
1767 case 'd': // 3 strings to match.
1768 if (Mnemonic[5] != '.')
1769 break;
1770 switch (Mnemonic[6]) {
1771 default: break;
1772 case 'f': // 1 string to match.
1773 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1774 break;
1775 Mnemonic = "vstrd.64"; // "vstrd.f64"
1776 return;
1777 case 's': // 1 string to match.
1778 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1779 break;
1780 Mnemonic = "vstrd.64"; // "vstrd.s64"
1781 return;
1782 case 'u': // 1 string to match.
1783 if (memcmp(Mnemonic.data()+7, "64", 2) != 0)
1784 break;
1785 Mnemonic = "vstrd.64"; // "vstrd.u64"
1786 return;
1787 }
1788 break;
1789 case 'h': // 3 strings to match.
1790 if (Mnemonic[5] != '.')
1791 break;
1792 switch (Mnemonic[6]) {
1793 default: break;
1794 case 'f': // 1 string to match.
1795 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1796 break;
1797 Mnemonic = "vstrh.16"; // "vstrh.f16"
1798 return;
1799 case 's': // 1 string to match.
1800 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1801 break;
1802 Mnemonic = "vstrh.16"; // "vstrh.s16"
1803 return;
1804 case 'u': // 1 string to match.
1805 if (memcmp(Mnemonic.data()+7, "16", 2) != 0)
1806 break;
1807 Mnemonic = "vstrh.16"; // "vstrh.u16"
1808 return;
1809 }
1810 break;
1811 case 'w': // 3 strings to match.
1812 if (Mnemonic[5] != '.')
1813 break;
1814 switch (Mnemonic[6]) {
1815 default: break;
1816 case 'f': // 1 string to match.
1817 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1818 break;
1819 Mnemonic = "vstrw.32"; // "vstrw.f32"
1820 return;
1821 case 's': // 1 string to match.
1822 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1823 break;
1824 Mnemonic = "vstrw.32"; // "vstrw.s32"
1825 return;
1826 case 'u': // 1 string to match.
1827 if (memcmp(Mnemonic.data()+7, "32", 2) != 0)
1828 break;
1829 Mnemonic = "vstrw.32"; // "vstrw.u32"
1830 return;
1831 }
1832 break;
1833 }
1834 break;
1835 }
1836 break;
1837 }
1838 break;
1839 case 10: // 30 strings to match.
1840 if (Mnemonic[0] != 'v')
1841 break;
1842 switch (Mnemonic[1]) {
1843 default: break;
1844 case 'l': // 12 strings to match.
1845 if (memcmp(Mnemonic.data()+2, "dr", 2) != 0)
1846 break;
1847 switch (Mnemonic[4]) {
1848 default: break;
1849 case 'd': // 4 strings to match.
1850 switch (Mnemonic[5]) {
1851 default: break;
1852 case 'e': // 2 strings to match.
1853 if (Mnemonic[6] != '.')
1854 break;
1855 switch (Mnemonic[7]) {
1856 default: break;
1857 case 'f': // 1 string to match.
1858 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1859 break;
1860 Mnemonic = "vldrde.u64"; // "vldrde.f64"
1861 return;
1862 case 's': // 1 string to match.
1863 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1864 break;
1865 Mnemonic = "vldrde.u64"; // "vldrde.s64"
1866 return;
1867 }
1868 break;
1869 case 't': // 2 strings to match.
1870 if (Mnemonic[6] != '.')
1871 break;
1872 switch (Mnemonic[7]) {
1873 default: break;
1874 case 'f': // 1 string to match.
1875 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1876 break;
1877 Mnemonic = "vldrdt.u64"; // "vldrdt.f64"
1878 return;
1879 case 's': // 1 string to match.
1880 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1881 break;
1882 Mnemonic = "vldrdt.u64"; // "vldrdt.s64"
1883 return;
1884 }
1885 break;
1886 }
1887 break;
1888 case 'h': // 4 strings to match.
1889 switch (Mnemonic[5]) {
1890 default: break;
1891 case 'e': // 2 strings to match.
1892 if (Mnemonic[6] != '.')
1893 break;
1894 switch (Mnemonic[7]) {
1895 default: break;
1896 case 'f': // 1 string to match.
1897 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1898 break;
1899 Mnemonic = "vldrhe.u16"; // "vldrhe.f16"
1900 return;
1901 case 's': // 1 string to match.
1902 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1903 break;
1904 Mnemonic = "vldrhe.u16"; // "vldrhe.s16"
1905 return;
1906 }
1907 break;
1908 case 't': // 2 strings to match.
1909 if (Mnemonic[6] != '.')
1910 break;
1911 switch (Mnemonic[7]) {
1912 default: break;
1913 case 'f': // 1 string to match.
1914 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1915 break;
1916 Mnemonic = "vldrht.u16"; // "vldrht.f16"
1917 return;
1918 case 's': // 1 string to match.
1919 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
1920 break;
1921 Mnemonic = "vldrht.u16"; // "vldrht.s16"
1922 return;
1923 }
1924 break;
1925 }
1926 break;
1927 case 'w': // 4 strings to match.
1928 switch (Mnemonic[5]) {
1929 default: break;
1930 case 'e': // 2 strings to match.
1931 if (Mnemonic[6] != '.')
1932 break;
1933 switch (Mnemonic[7]) {
1934 default: break;
1935 case 'f': // 1 string to match.
1936 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1937 break;
1938 Mnemonic = "vldrwe.u32"; // "vldrwe.f32"
1939 return;
1940 case 's': // 1 string to match.
1941 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1942 break;
1943 Mnemonic = "vldrwe.u32"; // "vldrwe.s32"
1944 return;
1945 }
1946 break;
1947 case 't': // 2 strings to match.
1948 if (Mnemonic[6] != '.')
1949 break;
1950 switch (Mnemonic[7]) {
1951 default: break;
1952 case 'f': // 1 string to match.
1953 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1954 break;
1955 Mnemonic = "vldrwt.u32"; // "vldrwt.f32"
1956 return;
1957 case 's': // 1 string to match.
1958 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
1959 break;
1960 Mnemonic = "vldrwt.u32"; // "vldrwt.s32"
1961 return;
1962 }
1963 break;
1964 }
1965 break;
1966 }
1967 break;
1968 case 's': // 18 strings to match.
1969 if (memcmp(Mnemonic.data()+2, "tr", 2) != 0)
1970 break;
1971 switch (Mnemonic[4]) {
1972 default: break;
1973 case 'd': // 6 strings to match.
1974 switch (Mnemonic[5]) {
1975 default: break;
1976 case 'e': // 3 strings to match.
1977 if (Mnemonic[6] != '.')
1978 break;
1979 switch (Mnemonic[7]) {
1980 default: break;
1981 case 'f': // 1 string to match.
1982 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1983 break;
1984 Mnemonic = "vstrde.64"; // "vstrde.f64"
1985 return;
1986 case 's': // 1 string to match.
1987 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1988 break;
1989 Mnemonic = "vstrde.64"; // "vstrde.s64"
1990 return;
1991 case 'u': // 1 string to match.
1992 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
1993 break;
1994 Mnemonic = "vstrde.64"; // "vstrde.u64"
1995 return;
1996 }
1997 break;
1998 case 't': // 3 strings to match.
1999 if (Mnemonic[6] != '.')
2000 break;
2001 switch (Mnemonic[7]) {
2002 default: break;
2003 case 'f': // 1 string to match.
2004 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
2005 break;
2006 Mnemonic = "vstrdt.64"; // "vstrdt.f64"
2007 return;
2008 case 's': // 1 string to match.
2009 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
2010 break;
2011 Mnemonic = "vstrdt.64"; // "vstrdt.s64"
2012 return;
2013 case 'u': // 1 string to match.
2014 if (memcmp(Mnemonic.data()+8, "64", 2) != 0)
2015 break;
2016 Mnemonic = "vstrdt.64"; // "vstrdt.u64"
2017 return;
2018 }
2019 break;
2020 }
2021 break;
2022 case 'h': // 6 strings to match.
2023 switch (Mnemonic[5]) {
2024 default: break;
2025 case 'e': // 3 strings to match.
2026 if (Mnemonic[6] != '.')
2027 break;
2028 switch (Mnemonic[7]) {
2029 default: break;
2030 case 'f': // 1 string to match.
2031 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2032 break;
2033 Mnemonic = "vstrhe.16"; // "vstrhe.f16"
2034 return;
2035 case 's': // 1 string to match.
2036 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2037 break;
2038 Mnemonic = "vstrhe.16"; // "vstrhe.s16"
2039 return;
2040 case 'u': // 1 string to match.
2041 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2042 break;
2043 Mnemonic = "vstrhe.16"; // "vstrhe.u16"
2044 return;
2045 }
2046 break;
2047 case 't': // 3 strings to match.
2048 if (Mnemonic[6] != '.')
2049 break;
2050 switch (Mnemonic[7]) {
2051 default: break;
2052 case 'f': // 1 string to match.
2053 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2054 break;
2055 Mnemonic = "vstrht.16"; // "vstrht.f16"
2056 return;
2057 case 's': // 1 string to match.
2058 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2059 break;
2060 Mnemonic = "vstrht.16"; // "vstrht.s16"
2061 return;
2062 case 'u': // 1 string to match.
2063 if (memcmp(Mnemonic.data()+8, "16", 2) != 0)
2064 break;
2065 Mnemonic = "vstrht.16"; // "vstrht.u16"
2066 return;
2067 }
2068 break;
2069 }
2070 break;
2071 case 'w': // 6 strings to match.
2072 switch (Mnemonic[5]) {
2073 default: break;
2074 case 'e': // 3 strings to match.
2075 if (Mnemonic[6] != '.')
2076 break;
2077 switch (Mnemonic[7]) {
2078 default: break;
2079 case 'f': // 1 string to match.
2080 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2081 break;
2082 Mnemonic = "vstrwe.32"; // "vstrwe.f32"
2083 return;
2084 case 's': // 1 string to match.
2085 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2086 break;
2087 Mnemonic = "vstrwe.32"; // "vstrwe.s32"
2088 return;
2089 case 'u': // 1 string to match.
2090 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2091 break;
2092 Mnemonic = "vstrwe.32"; // "vstrwe.u32"
2093 return;
2094 }
2095 break;
2096 case 't': // 3 strings to match.
2097 if (Mnemonic[6] != '.')
2098 break;
2099 switch (Mnemonic[7]) {
2100 default: break;
2101 case 'f': // 1 string to match.
2102 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2103 break;
2104 Mnemonic = "vstrwt.32"; // "vstrwt.f32"
2105 return;
2106 case 's': // 1 string to match.
2107 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2108 break;
2109 Mnemonic = "vstrwt.32"; // "vstrwt.s32"
2110 return;
2111 case 'u': // 1 string to match.
2112 if (memcmp(Mnemonic.data()+8, "32", 2) != 0)
2113 break;
2114 Mnemonic = "vstrwt.32"; // "vstrwt.u32"
2115 return;
2116 }
2117 break;
2118 }
2119 break;
2120 }
2121 break;
2122 }
2123 break;
2124 case 11: // 2 strings to match.
2125 if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0)
2126 break;
2127 switch (Mnemonic[8]) {
2128 default: break;
2129 case 'f': // 1 string to match.
2130 if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
2131 break;
2132 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.f32"
2133 Mnemonic = "vrecpe.f32";
2134 return;
2135 case 'u': // 1 string to match.
2136 if (memcmp(Mnemonic.data()+9, "32", 2) != 0)
2137 break;
2138 if (Features.test(Feature_HasNEONBit)) // "vrecpeq.u32"
2139 Mnemonic = "vrecpe.u32";
2140 return;
2141 }
2142 break;
2143 }
2144}
2145
2146enum {
2147 Tie0_1_1,
2148 Tie0_2_2,
2149 Tie0_2_4,
2150 Tie0_3_3,
2151 Tie0_4_4,
2152 Tie0_4_5,
2153 Tie1_1_1,
2154 Tie1_2_2,
2155 Tie1_3_3,
2156 Tie1_4_4,
2157 Tie2_4_4,
2158};
2159
2160static const uint8_t TiedAsmOperandTable[][3] = {
2161 /* Tie0_1_1 */ { 0, 1, 1 },
2162 /* Tie0_2_2 */ { 0, 2, 2 },
2163 /* Tie0_2_4 */ { 0, 2, 4 },
2164 /* Tie0_3_3 */ { 0, 3, 3 },
2165 /* Tie0_4_4 */ { 0, 4, 4 },
2166 /* Tie0_4_5 */ { 0, 4, 5 },
2167 /* Tie1_1_1 */ { 1, 1, 1 },
2168 /* Tie1_2_2 */ { 1, 2, 2 },
2169 /* Tie1_3_3 */ { 1, 3, 3 },
2170 /* Tie1_4_4 */ { 1, 4, 4 },
2171 /* Tie2_4_4 */ { 2, 4, 4 },
2172};
2173
2174namespace {
2175enum OperatorConversionKind {
2176 CVT_Done,
2177 CVT_Reg,
2178 CVT_Tied,
2179 CVT_95_Reg,
2180 CVT_95_addCCOutOperands_95_defaultCCOutOp,
2181 CVT_95_addCondCodeOperands_95_defaultCondCodeOp,
2182 CVT_95_addRegShiftedImmOperands,
2183 CVT_95_addImmOperands,
2184 CVT_95_addT2SOImmNotOperands,
2185 CVT_95_addRegShiftedRegOperands,
2186 CVT_95_addModImmOperands,
2187 CVT_95_addModImmNotOperands,
2188 CVT_95_addImm0_95_508s4Operands,
2189 CVT_regSP,
2190 CVT_95_addImm0_95_508s4NegOperands,
2191 CVT_95_addThumbModImmNeg8_95_255Operands,
2192 CVT_95_addImm0_95_1020s4Operands,
2193 CVT_95_addThumbModImmNeg1_95_7Operands,
2194 CVT_95_addImm0_95_4095NegOperands,
2195 CVT_95_addT2SOImmNegOperands,
2196 CVT_95_addModImmNegOperands,
2197 CVT_95_addUnsignedOffset_95_b8s2Operands,
2198 CVT_95_addAdrLabelOperands,
2199 CVT_imm_95_45,
2200 CVT_cvtThumbBranches,
2201 CVT_95_addARMBranchTargetOperands,
2202 CVT_95_addBitfieldOperands,
2203 CVT_95_addITCondCodeOperands,
2204 CVT_imm_95_0,
2205 CVT_95_addThumbBranchTargetOperands,
2206 CVT_imm_95_15,
2207 CVT_95_addCoprocNumOperands,
2208 CVT_95_addCoprocRegOperands,
2209 CVT_95_addITCondCodeInvOperands,
2210 CVT_imm_95_22,
2211 CVT_95_addRegListWithAPSROperands,
2212 CVT_95_addProcIFlagsOperands,
2213 CVT_imm_95_20,
2214 CVT_regZR,
2215 CVT_imm_95_12,
2216 CVT_95_addMemBarrierOptOperands,
2217 CVT_imm_95_16,
2218 CVT_95_addFPImmOperands,
2219 CVT_95_addDPRRegListOperands,
2220 CVT_imm_95_1,
2221 CVT_95_addInstSyncBarrierOptOperands,
2222 CVT_95_addITMaskOperands,
2223 CVT_95_addMemNoOffsetOperands,
2224 CVT_95_addAddrMode5Operands,
2225 CVT_95_addCoprocOptionOperands,
2226 CVT_95_addPostIdxImm8s4Operands,
2227 CVT_95_addRegListOperands,
2228 CVT_95_addThumbMemPCOperands,
2229 CVT_95_addMemThumbRIs4Operands,
2230 CVT_95_addMemThumbRROperands,
2231 CVT_95_addMemThumbSPIOperands,
2232 CVT_95_addConstPoolAsmImmOperands,
2233 CVT_95_addMemImm12OffsetOperands,
2234 CVT_95_addMemImmOffsetOperands,
2235 CVT_95_addMemRegOffsetOperands,
2236 CVT_95_addMemUImm12OffsetOperands,
2237 CVT_95_addT2MemRegOffsetOperands,
2238 CVT_95_addMemPCRelImm12Operands,
2239 CVT_95_addAM2OffsetImmOperands,
2240 CVT_95_addPostIdxRegShiftedOperands,
2241 CVT_95_addMemThumbRIs1Operands,
2242 CVT_95_addMemImm8s4OffsetOperands,
2243 CVT_95_addAddrMode3Operands,
2244 CVT_95_addImm8s4Operands,
2245 CVT_95_addAM3OffsetOperands,
2246 CVT_95_addMemImm0_95_1020s4OffsetOperands,
2247 CVT_95_addMemThumbRIs2Operands,
2248 CVT_95_addPostIdxRegOperands,
2249 CVT_95_addPostIdxImm8Operands,
2250 CVT_reg0,
2251 CVT_regCPSR,
2252 CVT_imm_95_14,
2253 CVT_95_addBankedRegOperands,
2254 CVT_95_addMSRMaskOperands,
2255 CVT_cvtThumbMultiply,
2256 CVT_regR8,
2257 CVT_regR0,
2258 CVT_imm_95_29,
2259 CVT_imm_95_13,
2260 CVT_95_addPKHASRImmOperands,
2261 CVT_imm_95_4,
2262 CVT_95_addImm1_95_32Operands,
2263 CVT_imm_95_5,
2264 CVT_95_addMveSaturateOperands,
2265 CVT_95_addShifterImmOperands,
2266 CVT_95_addImm1_95_16Operands,
2267 CVT_95_addRotImmOperands,
2268 CVT_95_addMemTBBOperands,
2269 CVT_95_addMemTBHOperands,
2270 CVT_95_addTraceSyncBarrierOptOperands,
2271 CVT_95_addVPTPredNOperands_95_defaultVPTPredOp,
2272 CVT_95_addVPTPredROperands_95_defaultVPTPredOp,
2273 CVT_95_addNEONi16splatNotOperands,
2274 CVT_95_addNEONi32splatNotOperands,
2275 CVT_95_addNEONi16splatOperands,
2276 CVT_95_addNEONi32splatOperands,
2277 CVT_95_addComplexRotationOddOperands,
2278 CVT_95_addComplexRotationEvenOperands,
2279 CVT_95_addVectorIndex64Operands,
2280 CVT_95_addVectorIndex32Operands,
2281 CVT_95_addFBits16Operands,
2282 CVT_95_addFBits32Operands,
2283 CVT_95_addPowerTwoOperands,
2284 CVT_95_addVectorIndex16Operands,
2285 CVT_95_addVectorIndex8Operands,
2286 CVT_95_addVecListOperands,
2287 CVT_95_addDupAlignedMemory16Operands,
2288 CVT_95_addAlignedMemory64or128Operands,
2289 CVT_95_addAlignedMemory64or128or256Operands,
2290 CVT_95_addAlignedMemory64Operands,
2291 CVT_95_addVecListIndexedOperands,
2292 CVT_95_addAlignedMemory16Operands,
2293 CVT_95_addDupAlignedMemory32Operands,
2294 CVT_95_addAlignedMemory32Operands,
2295 CVT_95_addDupAlignedMemoryNoneOperands,
2296 CVT_95_addAlignedMemoryNoneOperands,
2297 CVT_95_addAlignedMemoryOperands,
2298 CVT_95_addDupAlignedMemory64Operands,
2299 CVT_95_addMVEVecListOperands,
2300 CVT_95_addMemNoOffsetT2Operands,
2301 CVT_95_addMemNoOffsetT2NoSpOperands,
2302 CVT_95_addDupAlignedMemory64or128Operands,
2303 CVT_95_addSPRRegListOperands,
2304 CVT_95_addMemImm7s4OffsetOperands,
2305 CVT_95_addAddrMode5FP16Operands,
2306 CVT_95_addImm7s4Operands,
2307 CVT_95_addMemRegRQOffsetOperands,
2308 CVT_95_addMemNoOffsetTOperands,
2309 CVT_95_addImm7Shift0Operands,
2310 CVT_95_addImm7Shift1Operands,
2311 CVT_95_addImm7Shift2Operands,
2312 CVT_95_addNEONi32vmovOperands,
2313 CVT_95_addNEONvmovi8ReplicateOperands,
2314 CVT_95_addNEONvmovi16ReplicateOperands,
2315 CVT_95_addNEONi32vmovNegOperands,
2316 CVT_95_addNEONvmovi32ReplicateOperands,
2317 CVT_95_addNEONi64splatOperands,
2318 CVT_95_addNEONi8splatOperands,
2319 CVT_95_addMVEVectorIndexOperands,
2320 CVT_95_addMVEPairVectorIndexOperands,
2321 CVT_cvtMVEVMOVQtoDReg,
2322 CVT_95_addNEONinvi8ReplicateOperands,
2323 CVT_95_addFPDRegListWithVPROperands,
2324 CVT_95_addFPSRegListWithVPROperands,
2325 CVT_imm_95_2,
2326 CVT_imm_95_3,
2327 CVT_NUM_CONVERTERS
2328};
2329
2330enum InstructionConversionKind {
2331 Convert_NoOperands,
2332 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1,
2333 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
2334 Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
2335 Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
2336 Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
2337 Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
2338 Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
2339 Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
2340 Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
2341 Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
2342 Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
2343 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
2344 Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
2345 Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
2346 Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
2347 Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0,
2348 Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0,
2349 Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0,
2350 Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
2351 Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0,
2352 Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0,
2353 Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0,
2354 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0,
2355 Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1,
2356 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_255Expr1_3__CondCode2_1,
2357 Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1,
2358 Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0,
2359 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0,
2360 Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0,
2361 Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0,
2362 Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1,
2363 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1,
2364 Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1,
2365 Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0,
2366 Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0,
2367 Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0,
2368 Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0,
2369 Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0,
2370 Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0,
2371 Convert__Reg1_1__Imm0_40951_3__CondCode2_0,
2372 Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
2373 Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0,
2374 Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0,
2375 Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0,
2376 Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0,
2377 Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0,
2378 Convert__Reg1_1__Imm1_2__CondCode2_0,
2379 Convert__Reg1_1__AdrLabel1_2__CondCode2_0,
2380 Convert__Reg1_2__Imm1_3__CondCode2_0,
2381 Convert__Reg1_1__Tie0_1_1__Reg1_2,
2382 Convert__Reg1_1__Reg1_2,
2383 Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0,
2384 Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0,
2385 Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1,
2386 Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1,
2387 Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0,
2388 Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0,
2389 Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
2390 Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0,
2391 Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0,
2392 Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0,
2393 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0,
2394 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0,
2395 Convert__imm_95_45__CondCode2_0,
2396 Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3,
2397 ConvertCustom_cvtThumbBranches,
2398 Convert__ARMBranchTarget1_1__CondCode2_0,
2399 Convert__Imm1_1__Imm1_2__CondCode2_0,
2400 Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0,
2401 Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3,
2402 Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0,
2403 Convert__Imm1_1__Reg1_2__CondCode2_0,
2404 Convert__imm_95_0,
2405 Convert__Imm0_2551_0,
2406 Convert__Imm0_655351_0,
2407 Convert__ARMBranchTarget1_0,
2408 Convert__CondCode2_0__ThumbBranchTarget1_1,
2409 Convert__CondCode2_0__ThumbBranchTarget1_2,
2410 Convert__CondCode2_0__Reg1_1,
2411 Convert__Reg1_0,
2412 Convert__ThumbBranchTarget1_0,
2413 Convert__Reg1_1__CondCode2_0,
2414 Convert__CondCode2_0__ARMBranchTarget1_1,
2415 Convert__imm_95_15__CondCode2_0,
2416 Convert__CondCode2_0,
2417 Convert__Reg1_0__ThumbBranchTarget1_1,
2418 Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
2419 Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
2420 Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2,
2421 Convert__imm_95_22__CondCode2_0,
2422 Convert__CondCode2_0__RegListWithAPSR1_1,
2423 Convert__Reg1_1__Reg1_2__CondCode2_0,
2424 Convert__Reg1_1__ModImmNeg1_2__CondCode2_0,
2425 Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0,
2426 Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0,
2427 Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0,
2428 Convert__Reg1_1__T2SOImm1_2__CondCode2_0,
2429 Convert__Reg1_1__ModImm1_2__CondCode2_0,
2430 Convert__Reg1_2__Reg1_3__CondCode2_0,
2431 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0,
2432 Convert__Reg1_2__T2SOImm1_3__CondCode2_0,
2433 Convert__Reg1_1__Imm0_2551_2__CondCode2_0,
2434 Convert__Imm1_0__ProcIFlags1_1,
2435 Convert__Imm0_311_0,
2436 Convert__Imm0_311_1,
2437 Convert__Imm1_0__ProcIFlags1_2,
2438 Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2,
2439 Convert__Imm1_0__ProcIFlags1_1__Imm1_2,
2440 Convert__Imm1_0__ProcIFlags1_2__Imm1_3,
2441 Convert__Reg1_0__Reg1_1__Reg1_2,
2442 Convert__imm_95_20__CondCode2_0,
2443 Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3,
2444 Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1,
2445 Convert__Reg1_1__CoprocNum1_0__Imm13b1_2,
2446 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0,
2447 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3,
2448 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0,
2449 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4,
2450 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0,
2451 Convert__Imm0_151_1__CondCode2_0,
2452 Convert__Imm0_151_2__CondCode2_0,
2453 Convert__imm_95_12,
2454 Convert__imm_95_12__CondCode2_0,
2455 Convert__Reg1_0__Reg1_1,
2456 Convert__imm_95_15,
2457 Convert__MemBarrierOpt1_0,
2458 Convert__MemBarrierOpt1_1__CondCode2_0,
2459 Convert__MemBarrierOpt1_2__CondCode2_0,
2460 Convert__imm_95_0__CondCode2_0,
2461 Convert__imm_95_16__CondCode2_0,
2462 Convert__Reg1_1__FPImm1_2__CondCode2_0,
2463 Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3,
2464 Convert__Reg1_1__CondCode2_0__DPRRegList1_2,
2465 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0,
2466 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0,
2467 Convert__Imm0_2391_1__CondCode2_0,
2468 Convert__Imm0_2391_2__CondCode2_0,
2469 Convert__Imm0_631_0,
2470 Convert__Imm0_655351_1,
2471 Convert__InstSyncBarrierOpt1_0,
2472 Convert__InstSyncBarrierOpt1_1__CondCode2_0,
2473 Convert__InstSyncBarrierOpt1_2__CondCode2_0,
2474 Convert__ITCondCode1_1__ITMask1_0,
2475 Convert__Reg1_1__MemNoOffset1_2__CondCode2_0,
2476 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0,
2477 Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0,
2478 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0,
2479 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0,
2480 Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2,
2481 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3,
2482 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3,
2483 Convert__Reg1_1__CondCode2_0__RegList1_2,
2484 Convert__Reg1_1__CondCode2_0__RegList1_3,
2485 Convert__Reg1_2__CondCode2_0__RegList1_3,
2486 Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3,
2487 Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4,
2488 Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0,
2489 Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0,
2490 Convert__Reg1_1__MemThumbRR2_2__CondCode2_0,
2491 Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0,
2492 Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0,
2493 Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0,
2494 Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0,
2495 Convert__Reg1_1__MemRegOffset3_2__CondCode2_0,
2496 Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0,
2497 Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0,
2498 Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0,
2499 Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0,
2500 Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0,
2501 Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0,
2502 Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0,
2503 Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0,
2504 Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0,
2505 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0,
2506 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0,
2507 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0,
2508 Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0,
2509 Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0,
2510 Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0,
2511 Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0,
2512 Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0,
2513 Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0,
2514 Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
2515 Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
2516 Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0,
2517 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm8s41_4__CondCode2_0,
2518 Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0,
2519 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0,
2520 Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0,
2521 Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0,
2522 Convert__Reg1_1__AddrMode33_2__CondCode2_0,
2523 Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0,
2524 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0,
2525 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0,
2526 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0,
2527 Convert__LELabel1_0,
2528 Convert__imm_95_0__Reg1_0__LELabel1_1,
2529 Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1,
2530 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1,
2531 Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0,
2532 Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0,
2533 Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
2534 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0,
2535 Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0,
2536 Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0,
2537 Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0,
2538 Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0,
2539 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
2540 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
2541 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0,
2542 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
2543 Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0,
2544 Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4,
2545 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
2546 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0,
2547 Convert__Reg1_2__CCOut1_0__Imm0_255Expr1_3__CondCode2_1,
2548 Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0,
2549 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0,
2550 Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0,
2551 Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0,
2552 Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0,
2553 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0,
2554 Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0,
2555 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0,
2556 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0,
2557 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0,
2558 Convert__Reg1_2__Reg1_3__CondCode2_0__reg0,
2559 Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0,
2560 Convert__Reg1_0__regCPSR__Imm0_255Expr1_1__imm_95_14__reg0,
2561 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR,
2562 Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR,
2563 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR,
2564 Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR,
2565 Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0,
2566 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0,
2567 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0,
2568 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0,
2569 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5,
2570 Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0,
2571 Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4,
2572 Convert__Reg1_1__BankedReg1_2__CondCode2_0,
2573 Convert__Reg1_1__MSRMask1_2__CondCode2_0,
2574 Convert__BankedReg1_1__Reg1_2__CondCode2_0,
2575 Convert__MSRMask1_1__Reg1_2__CondCode2_0,
2576 Convert__MSRMask1_1__ModImm1_2__CondCode2_0,
2577 ConvertCustom_cvtThumbMultiply,
2578 Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0,
2579 Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1,
2580 Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0,
2581 Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0,
2582 Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0,
2583 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0,
2584 Convert__regR8__regR8__imm_95_14__reg0,
2585 Convert__regR0__regR0__CondCode2_0__reg0,
2586 Convert__imm_95_29__CondCode2_0,
2587 Convert__imm_95_13__CondCode2_0,
2588 Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3,
2589 Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
2590 Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0,
2591 Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0,
2592 Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0,
2593 Convert__MemImm12Offset2_0,
2594 Convert__MemRegOffset3_0,
2595 Convert__Imm1_1__CondCode2_0,
2596 Convert__MemNegImm8Offset2_1__CondCode2_0,
2597 Convert__MemUImm12Offset2_1__CondCode2_0,
2598 Convert__T2MemRegOffset3_1__CondCode2_0,
2599 Convert__MemPCRelImm121_1__CondCode2_0,
2600 Convert__Imm1_2__CondCode2_0,
2601 Convert__MemNegImm8Offset2_2__CondCode2_0,
2602 Convert__MemUImm12Offset2_2__CondCode2_0,
2603 Convert__T2MemRegOffset3_2__CondCode2_0,
2604 Convert__MemPCRelImm121_2__CondCode2_0,
2605 Convert__CondCode2_0__RegList1_1,
2606 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1,
2607 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2,
2608 Convert__imm_95_4__imm_95_14__reg0,
2609 Convert__imm_95_4,
2610 Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0,
2611 Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0,
2612 Convert__SetEndImm1_0,
2613 Convert__Imm0_11_0,
2614 Convert__imm_95_4__CondCode2_0,
2615 Convert__imm_95_5__CondCode2_0,
2616 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3,
2617 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0,
2618 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0,
2619 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0,
2620 Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0,
2621 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0,
2622 Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0,
2623 Convert__Imm0_311_2,
2624 Convert__Imm0_311_1__CondCode2_0,
2625 Convert__Imm0_311_2__CondCode2_0,
2626 Convert__Imm0_311_3__CondCode2_0,
2627 Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0,
2628 Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0,
2629 Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0,
2630 Convert__imm_95_0__imm_95_14__reg0,
2631 Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0,
2632 Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0,
2633 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0,
2634 Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0,
2635 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0,
2636 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0,
2637 Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0,
2638 Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0,
2639 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm8s41_4__CondCode2_0,
2640 Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0,
2641 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0,
2642 Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0,
2643 Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0,
2644 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0,
2645 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0,
2646 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0,
2647 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1,
2648 Convert__Imm0_2551_3__CondCode2_0,
2649 Convert__Imm0_2551_1__CondCode2_0,
2650 Convert__Imm24bit1_1__CondCode2_0,
2651 Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
2652 Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0,
2653 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0,
2654 Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0,
2655 Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0,
2656 Convert__MemTBB2_1__CondCode2_0,
2657 Convert__MemTBH2_1__CondCode2_0,
2658 Convert__TraceSyncBarrierOpt1_0,
2659 Convert__TraceSyncBarrierOpt1_1__CondCode2_0,
2660 Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0,
2661 Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0,
2662 Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0,
2663 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0,
2664 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0,
2665 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0,
2666 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0,
2667 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0,
2668 Convert__Reg1_2__Reg1_3__VPTPredR4_0,
2669 Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0,
2670 Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0,
2671 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0,
2672 Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0,
2673 Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0,
2674 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0,
2675 Convert__Reg1_2__Reg1_3__VPTPredN3_0,
2676 Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0,
2677 Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0,
2678 Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0,
2679 Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0,
2680 Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0,
2681 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0,
2682 Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0,
2683 Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0,
2684 Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0,
2685 Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0,
2686 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0,
2687 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0,
2688 Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4,
2689 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0,
2690 Convert__Reg1_2__Reg1_2__CondCode2_0,
2691 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4,
2692 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5,
2693 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5,
2694 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0,
2695 Convert__Reg1_2__CondCode2_0,
2696 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0,
2697 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0,
2698 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0,
2699 Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0,
2700 Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0,
2701 Convert__imm_95_0__Reg1_2__VPTPredN3_0,
2702 Convert__Reg1_3__Reg1_4__CondCode2_0,
2703 Convert__Reg1_3__Reg1_4__VPTPredR4_0,
2704 Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0,
2705 Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0,
2706 Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0,
2707 Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0,
2708 Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0,
2709 Convert__Reg1_2__Reg1_3,
2710 Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0,
2711 Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0,
2712 Convert__Reg1_1__CoprocNum1_0__Imm11b1_2,
2713 Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0,
2714 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2,
2715 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0,
2716 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3,
2717 Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0,
2718 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3,
2719 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0,
2720 Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4,
2721 Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0,
2722 Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4,
2723 Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0,
2724 Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0,
2725 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3,
2726 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4,
2727 Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
2728 Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
2729 Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0,
2730 Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0,
2731 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0,
2732 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0,
2733 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0,
2734 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0,
2735 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0,
2736 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0,
2737 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0,
2738 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0,
2739 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4,
2740 Convert__Reg1_1__Reg1_2__Reg1_3,
2741 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4,
2742 Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4,
2743 Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
2744 Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0,
2745 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0,
2746 Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
2747 Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0,
2748 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0,
2749 Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0,
2750 Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2751 Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2752 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
2753 Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2754 Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2755 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2756 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
2757 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
2758 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
2759 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2760 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0,
2761 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2762 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
2763 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
2764 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
2765 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
2766 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
2767 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0,
2768 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0,
2769 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
2770 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2771 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
2772 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2773 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2774 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
2775 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2776 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0,
2777 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2778 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2779 Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0,
2780 Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
2781 Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0,
2782 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2783 Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0,
2784 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
2785 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0,
2786 Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2787 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2788 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2789 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2790 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0,
2791 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0,
2792 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0,
2793 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2794 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0,
2795 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2796 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2797 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2798 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
2799 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2800 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0,
2801 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2802 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2803 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2804 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0,
2805 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0,
2806 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0,
2807 Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2,
2808 Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3,
2809 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2810 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2811 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0,
2812 Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0,
2813 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2814 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2815 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2816 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0,
2817 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2818 Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2819 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2820 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2821 Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2822 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2823 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2824 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2825 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0,
2826 Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0,
2827 Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0,
2828 Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0,
2829 Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0,
2830 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2831 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2832 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0,
2833 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0,
2834 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0,
2835 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2836 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2837 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0,
2838 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0,
2839 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2840 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0,
2841 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0,
2842 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2843 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2844 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2845 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0,
2846 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0,
2847 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0,
2848 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2849 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2850 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2851 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0,
2852 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2853 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0,
2854 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0,
2855 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0,
2856 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0,
2857 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0,
2858 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0,
2859 Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2,
2860 Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3,
2861 Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3,
2862 Convert__Reg1_1__CondCode2_0__SPRRegList1_2,
2863 Convert__MemImm7s4Offset2_2__CondCode2_0,
2864 Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0,
2865 Convert__Reg1_1__AddrMode52_2__CondCode2_0,
2866 Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0,
2867 Convert__Reg1_2__AddrMode52_3__CondCode2_0,
2868 Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0,
2869 Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0,
2870 Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0,
2871 Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0,
2872 Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0,
2873 Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0,
2874 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0,
2875 Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0,
2876 Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0,
2877 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0,
2878 Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0,
2879 Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0,
2880 Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0,
2881 Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0,
2882 Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0,
2883 Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0,
2884 Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0,
2885 Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0,
2886 Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0,
2887 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0,
2888 Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0,
2889 Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0,
2890 Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0,
2891 Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0,
2892 Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0,
2893 Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0,
2894 Convert__Reg1_1__CondCode2_0__imm_95_0,
2895 Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0,
2896 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2897 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2898 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0,
2899 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0,
2900 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0,
2901 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0,
2902 Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0,
2903 Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0,
2904 Convert__Reg1_2__FPImm1_3__CondCode2_0,
2905 Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0,
2906 Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0,
2907 Convert__Reg1_2__NEONi16splat1_3__CondCode2_0,
2908 Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0,
2909 Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0,
2910 Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0,
2911 Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0,
2912 Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0,
2913 Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0,
2914 Convert__Reg1_2__NEONi64splat1_3__CondCode2_0,
2915 Convert__Reg1_2__NEONi8splat1_3__CondCode2_0,
2916 Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0,
2917 Convert__Reg1_1__Reg1_2__VectorIndex321_3__CondCode2_0,
2918 Convert__Reg1_1__Tie0_2_2__Reg1_3__VectorIndex321_2__CondCode2_0,
2919 Convert__Reg1_2__FPImm1_3__VPTPredR4_0,
2920 Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0,
2921 Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0,
2922 Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0,
2923 Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0,
2924 Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0,
2925 Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0,
2926 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0,
2927 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0,
2928 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0,
2929 Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0,
2930 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0,
2931 Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0,
2932 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0,
2933 Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0,
2934 ConvertCustom_cvtMVEVMOVQtoDReg,
2935 Convert__Reg1_1__imm_95_0__CondCode2_0,
2936 Convert__imm_95_0__Reg1_2__CondCode2_0,
2937 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0,
2938 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0,
2939 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0,
2940 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0,
2941 Convert__Reg1_1__Reg1_2__VPTPredR4_0,
2942 Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0,
2943 Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0,
2944 Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0,
2945 Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0,
2946 Convert__imm_95_0__imm_95_0__VPTPredN3_0,
2947 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1,
2948 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1,
2949 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2,
2950 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2,
2951 Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0,
2952 Convert__ITMask1_0,
2953 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2,
2954 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2,
2955 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2,
2956 Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2,
2957 Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0,
2958 Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0,
2959 Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0,
2960 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0,
2961 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0,
2962 Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0,
2963 Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0,
2964 Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0,
2965 Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0,
2966 Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0,
2967 Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0,
2968 Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0,
2969 Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0,
2970 Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0,
2971 Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0,
2972 Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0,
2973 Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0,
2974 Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0,
2975 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0,
2976 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0,
2977 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0,
2978 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0,
2979 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0,
2980 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0,
2981 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0,
2982 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0,
2983 Convert__CondCode2_0__FPDRegListWithVPR1_1,
2984 Convert__CondCode2_0__FPSRegListWithVPR1_1,
2985 Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0,
2986 Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0,
2987 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0,
2988 Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0,
2989 Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0,
2990 Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0,
2991 Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0,
2992 Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0,
2993 Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0,
2994 Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0,
2995 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0,
2996 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0,
2997 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0,
2998 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0,
2999 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0,
3000 Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
3001 Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
3002 Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
3003 Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
3004 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0,
3005 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0,
3006 Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0,
3007 Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0,
3008 Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0,
3009 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0,
3010 Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0,
3011 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0,
3012 Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0,
3013 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
3014 Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0,
3015 Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0,
3016 Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
3017 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0,
3018 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0,
3019 Convert__VecListTwoMQ1_1__MemNoOffsetT21_2,
3020 Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3,
3021 Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
3022 Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0,
3023 Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
3024 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0,
3025 Convert__VecListFourMQ1_1__MemNoOffsetT21_2,
3026 Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3,
3027 Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0,
3028 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0,
3029 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0,
3030 Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0,
3031 Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0,
3032 Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0,
3033 Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0,
3034 Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0,
3035 Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0,
3036 Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0,
3037 Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0,
3038 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0,
3039 Convert__imm_95_2__CondCode2_0,
3040 Convert__imm_95_3__CondCode2_0,
3041 Convert__Reg1_0__Reg1_1__WLSLabel1_2,
3042 Convert__Reg1_1__Reg1_2__WLSLabel1_3,
3043 Convert__imm_95_1__CondCode2_0,
3044 CVT_NUM_SIGNATURES
3045};
3046
3047} // end anonymous namespace
3048
3049static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = {
3050 // Convert_NoOperands
3051 { CVT_Done },
3052 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1
3053 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3054 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
3055 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3056 // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
3057 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3058 // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
3059 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3060 // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
3061 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3062 // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
3063 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3064 // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
3065 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3066 // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
3067 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3068 // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
3069 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3070 // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
3071 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3072 // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
3073 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3074 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
3075 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3076 // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
3077 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3078 // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
3079 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3080 // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
3081 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3082 // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0
3083 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3084 // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0
3085 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3086 // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0
3087 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3088 // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
3089 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3090 // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0
3091 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3092 // Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0
3093 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3094 // Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0
3095 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3096 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0
3097 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3098 // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1
3099 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3100 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_255Expr1_3__CondCode2_1
3101 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3102 // Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1
3103 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_3_3, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3104 // Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0
3105 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3106 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0
3107 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3108 // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0
3109 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3110 // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0
3111 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3112 // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1
3113 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3114 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1
3115 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3116 // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1
3117 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3118 // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0
3119 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3120 // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0
3121 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3122 // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0
3123 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3124 // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0
3125 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3126 // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0
3127 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3128 // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0
3129 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3130 // Convert__Reg1_1__Imm0_40951_3__CondCode2_0
3131 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3132 // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
3133 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3134 // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0
3135 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3136 // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0
3137 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3138 // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0
3139 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3140 // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0
3141 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3142 // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0
3143 { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3144 // Convert__Reg1_1__Imm1_2__CondCode2_0
3145 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3146 // Convert__Reg1_1__AdrLabel1_2__CondCode2_0
3147 { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3148 // Convert__Reg1_2__Imm1_3__CondCode2_0
3149 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3150 // Convert__Reg1_1__Tie0_1_1__Reg1_2
3151 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done },
3152 // Convert__Reg1_1__Reg1_2
3153 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3154 // Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0
3155 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3156 // Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0
3157 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNotOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3158 // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1
3159 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3160 // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1
3161 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3162 // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0
3163 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3164 // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0
3165 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3166 // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
3167 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3168 // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0
3169 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3170 // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0
3171 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3172 // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0
3173 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3174 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0
3175 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3176 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0
3177 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3178 // Convert__imm_95_45__CondCode2_0
3179 { CVT_imm_95_45, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3180 // Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3
3181 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3182 // ConvertCustom_cvtThumbBranches
3183 { CVT_cvtThumbBranches, 0, CVT_Done },
3184 // Convert__ARMBranchTarget1_1__CondCode2_0
3185 { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3186 // Convert__Imm1_1__Imm1_2__CondCode2_0
3187 { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3188 // Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0
3189 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3190 // Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3
3191 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done },
3192 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0
3193 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3194 // Convert__Imm1_1__Reg1_2__CondCode2_0
3195 { CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3196 // Convert__imm_95_0
3197 { CVT_imm_95_0, 0, CVT_Done },
3198 // Convert__Imm0_2551_0
3199 { CVT_95_addImmOperands, 1, CVT_Done },
3200 // Convert__Imm0_655351_0
3201 { CVT_95_addImmOperands, 1, CVT_Done },
3202 // Convert__ARMBranchTarget1_0
3203 { CVT_95_addARMBranchTargetOperands, 1, CVT_Done },
3204 // Convert__CondCode2_0__ThumbBranchTarget1_1
3205 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
3206 // Convert__CondCode2_0__ThumbBranchTarget1_2
3207 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addThumbBranchTargetOperands, 3, CVT_Done },
3208 // Convert__CondCode2_0__Reg1_1
3209 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_Reg, 2, CVT_Done },
3210 // Convert__Reg1_0
3211 { CVT_95_Reg, 1, CVT_Done },
3212 // Convert__ThumbBranchTarget1_0
3213 { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done },
3214 // Convert__Reg1_1__CondCode2_0
3215 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3216 // Convert__CondCode2_0__ARMBranchTarget1_1
3217 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done },
3218 // Convert__imm_95_15__CondCode2_0
3219 { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3220 // Convert__CondCode2_0
3221 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3222 // Convert__Reg1_0__ThumbBranchTarget1_1
3223 { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done },
3224 // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
3225 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3226 // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
3227 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3228 // Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2
3229 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addITCondCodeInvOperands, 3, CVT_Done },
3230 // Convert__imm_95_22__CondCode2_0
3231 { CVT_imm_95_22, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3232 // Convert__CondCode2_0__RegListWithAPSR1_1
3233 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListWithAPSROperands, 2, CVT_Done },
3234 // Convert__Reg1_1__Reg1_2__CondCode2_0
3235 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3236 // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0
3237 { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3238 // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0
3239 { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3240 // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0
3241 { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3242 // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0
3243 { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3244 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0
3245 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3246 // Convert__Reg1_1__ModImm1_2__CondCode2_0
3247 { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3248 // Convert__Reg1_2__Reg1_3__CondCode2_0
3249 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3250 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0
3251 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3252 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0
3253 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3254 // Convert__Reg1_1__Imm0_2551_2__CondCode2_0
3255 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3256 // Convert__Imm1_0__ProcIFlags1_1
3257 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done },
3258 // Convert__Imm0_311_0
3259 { CVT_95_addImmOperands, 1, CVT_Done },
3260 // Convert__Imm0_311_1
3261 { CVT_95_addImmOperands, 2, CVT_Done },
3262 // Convert__Imm1_0__ProcIFlags1_2
3263 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done },
3264 // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2
3265 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3266 // Convert__Imm1_0__ProcIFlags1_1__Imm1_2
3267 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
3268 // Convert__Imm1_0__ProcIFlags1_2__Imm1_3
3269 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done },
3270 // Convert__Reg1_0__Reg1_1__Reg1_2
3271 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
3272 // Convert__imm_95_20__CondCode2_0
3273 { CVT_imm_95_20, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3274 // Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3
3275 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addITCondCodeOperands, 4, CVT_Done },
3276 // Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1
3277 { CVT_95_Reg, 1, CVT_regZR, 0, CVT_regZR, 0, CVT_95_addITCondCodeInvOperands, 2, CVT_Done },
3278 // Convert__Reg1_1__CoprocNum1_0__Imm13b1_2
3279 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
3280 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0
3281 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3282 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3
3283 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3284 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0
3285 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3286 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4
3287 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
3288 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0
3289 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3290 // Convert__Imm0_151_1__CondCode2_0
3291 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3292 // Convert__Imm0_151_2__CondCode2_0
3293 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3294 // Convert__imm_95_12
3295 { CVT_imm_95_12, 0, CVT_Done },
3296 // Convert__imm_95_12__CondCode2_0
3297 { CVT_imm_95_12, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3298 // Convert__Reg1_0__Reg1_1
3299 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
3300 // Convert__imm_95_15
3301 { CVT_imm_95_15, 0, CVT_Done },
3302 // Convert__MemBarrierOpt1_0
3303 { CVT_95_addMemBarrierOptOperands, 1, CVT_Done },
3304 // Convert__MemBarrierOpt1_1__CondCode2_0
3305 { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3306 // Convert__MemBarrierOpt1_2__CondCode2_0
3307 { CVT_95_addMemBarrierOptOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3308 // Convert__imm_95_0__CondCode2_0
3309 { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3310 // Convert__imm_95_16__CondCode2_0
3311 { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3312 // Convert__Reg1_1__FPImm1_2__CondCode2_0
3313 { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3314 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3
3315 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done },
3316 // Convert__Reg1_1__CondCode2_0__DPRRegList1_2
3317 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
3318 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0
3319 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3320 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0
3321 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3322 // Convert__Imm0_2391_1__CondCode2_0
3323 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3324 // Convert__Imm0_2391_2__CondCode2_0
3325 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3326 // Convert__Imm0_631_0
3327 { CVT_95_addImmOperands, 1, CVT_Done },
3328 // Convert__Imm0_655351_1
3329 { CVT_95_addImmOperands, 2, CVT_Done },
3330 // Convert__InstSyncBarrierOpt1_0
3331 { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done },
3332 // Convert__InstSyncBarrierOpt1_1__CondCode2_0
3333 { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3334 // Convert__InstSyncBarrierOpt1_2__CondCode2_0
3335 { CVT_95_addInstSyncBarrierOptOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3336 // Convert__ITCondCode1_1__ITMask1_0
3337 { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done },
3338 // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0
3339 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3340 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0
3341 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3342 // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0
3343 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3344 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0
3345 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3346 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0
3347 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3348 // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2
3349 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done },
3350 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3
3351 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done },
3352 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3
3353 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done },
3354 // Convert__Reg1_1__CondCode2_0__RegList1_2
3355 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 3, CVT_Done },
3356 // Convert__Reg1_1__CondCode2_0__RegList1_3
3357 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 4, CVT_Done },
3358 // Convert__Reg1_2__CondCode2_0__RegList1_3
3359 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 4, CVT_Done },
3360 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3
3361 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 4, CVT_Done },
3362 // Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4
3363 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 5, CVT_Done },
3364 // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0
3365 { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3366 // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0
3367 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3368 // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0
3369 { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3370 // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0
3371 { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3372 // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0
3373 { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3374 // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0
3375 { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3376 // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0
3377 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3378 // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0
3379 { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3380 // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0
3381 { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3382 // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0
3383 { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3384 // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0
3385 { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3386 // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0
3387 { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3388 // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0
3389 { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3390 // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0
3391 { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3392 // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0
3393 { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3394 // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0
3395 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3396 // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0
3397 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3398 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0
3399 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3400 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0
3401 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3402 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0
3403 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3404 // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0
3405 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3406 // Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0
3407 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3408 // Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0
3409 { CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3410 // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0
3411 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3412 // Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0
3413 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3414 // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0
3415 { CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3416 // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
3417 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3418 // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
3419 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3420 // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0
3421 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3422 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm8s41_4__CondCode2_0
3423 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addImm8s4Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3424 // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0
3425 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3426 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0
3427 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3428 // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0
3429 { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3430 // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0
3431 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3432 // Convert__Reg1_1__AddrMode33_2__CondCode2_0
3433 { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3434 // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0
3435 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3436 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0
3437 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3438 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0
3439 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3440 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0
3441 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3442 // Convert__LELabel1_0
3443 { CVT_95_addImmOperands, 1, CVT_Done },
3444 // Convert__imm_95_0__Reg1_0__LELabel1_1
3445 { CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
3446 // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1
3447 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3448 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1
3449 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3450 // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0
3451 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3452 // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0
3453 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3454 // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
3455 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3456 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0
3457 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3458 // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0
3459 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3460 // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0
3461 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3462 // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0
3463 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3464 // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0
3465 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3466 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
3467 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3468 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
3469 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3470 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0
3471 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
3472 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
3473 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3474 // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0
3475 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3476 // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4
3477 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done },
3478 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
3479 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3480 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0
3481 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3482 // Convert__Reg1_2__CCOut1_0__Imm0_255Expr1_3__CondCode2_1
3483 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3484 // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0
3485 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3486 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0
3487 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3488 // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0
3489 { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3490 // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0
3491 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3492 // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0
3493 { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3494 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0
3495 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3496 // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0
3497 { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3498 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0
3499 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3500 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0
3501 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3502 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0
3503 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3504 // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0
3505 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3506 // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0
3507 { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3508 // Convert__Reg1_0__regCPSR__Imm0_255Expr1_1__imm_95_14__reg0
3509 { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3510 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR
3511 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3512 // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR
3513 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3514 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR
3515 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3516 // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR
3517 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_regCPSR, 0, CVT_Done },
3518 // Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0
3519 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3520 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0
3521 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3522 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0
3523 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3524 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0
3525 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done },
3526 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5
3527 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done },
3528 // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0
3529 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3530 // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4
3531 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done },
3532 // Convert__Reg1_1__BankedReg1_2__CondCode2_0
3533 { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3534 // Convert__Reg1_1__MSRMask1_2__CondCode2_0
3535 { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3536 // Convert__BankedReg1_1__Reg1_2__CondCode2_0
3537 { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3538 // Convert__MSRMask1_1__Reg1_2__CondCode2_0
3539 { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3540 // Convert__MSRMask1_1__ModImm1_2__CondCode2_0
3541 { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3542 // ConvertCustom_cvtThumbMultiply
3543 { CVT_cvtThumbMultiply, 0, CVT_Done },
3544 // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0
3545 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3546 // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1
3547 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3548 // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0
3549 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3550 // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0
3551 { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3552 // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0
3553 { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3554 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0
3555 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3556 // Convert__regR8__regR8__imm_95_14__reg0
3557 { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3558 // Convert__regR0__regR0__CondCode2_0__reg0
3559 { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_reg0, 0, CVT_Done },
3560 // Convert__imm_95_29__CondCode2_0
3561 { CVT_imm_95_29, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3562 // Convert__imm_95_13__CondCode2_0
3563 { CVT_imm_95_13, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3564 // Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3
3565 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3566 // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
3567 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3568 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0
3569 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3570 // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0
3571 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3572 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0
3573 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3574 // Convert__MemImm12Offset2_0
3575 { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done },
3576 // Convert__MemRegOffset3_0
3577 { CVT_95_addMemRegOffsetOperands, 1, CVT_Done },
3578 // Convert__Imm1_1__CondCode2_0
3579 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3580 // Convert__MemNegImm8Offset2_1__CondCode2_0
3581 { CVT_95_addMemImmOffsetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3582 // Convert__MemUImm12Offset2_1__CondCode2_0
3583 { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3584 // Convert__T2MemRegOffset3_1__CondCode2_0
3585 { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3586 // Convert__MemPCRelImm121_1__CondCode2_0
3587 { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3588 // Convert__Imm1_2__CondCode2_0
3589 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3590 // Convert__MemNegImm8Offset2_2__CondCode2_0
3591 { CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3592 // Convert__MemUImm12Offset2_2__CondCode2_0
3593 { CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3594 // Convert__T2MemRegOffset3_2__CondCode2_0
3595 { CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3596 // Convert__MemPCRelImm121_2__CondCode2_0
3597 { CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3598 // Convert__CondCode2_0__RegList1_1
3599 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 2, CVT_Done },
3600 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1
3601 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 2, CVT_Done },
3602 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2
3603 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addRegListOperands, 3, CVT_Done },
3604 // Convert__imm_95_4__imm_95_14__reg0
3605 { CVT_imm_95_4, 0, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3606 // Convert__imm_95_4
3607 { CVT_imm_95_4, 0, CVT_Done },
3608 // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0
3609 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3610 // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0
3611 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3612 // Convert__SetEndImm1_0
3613 { CVT_95_addImmOperands, 1, CVT_Done },
3614 // Convert__Imm0_11_0
3615 { CVT_95_addImmOperands, 1, CVT_Done },
3616 // Convert__imm_95_4__CondCode2_0
3617 { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3618 // Convert__imm_95_5__CondCode2_0
3619 { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3620 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3
3621 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3622 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0
3623 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3624 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0
3625 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3626 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0
3627 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Done },
3628 // Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0
3629 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3630 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0
3631 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addMveSaturateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3632 // Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0
3633 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3634 // Convert__Imm0_311_2
3635 { CVT_95_addImmOperands, 3, CVT_Done },
3636 // Convert__Imm0_311_1__CondCode2_0
3637 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3638 // Convert__Imm0_311_2__CondCode2_0
3639 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3640 // Convert__Imm0_311_3__CondCode2_0
3641 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3642 // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0
3643 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3644 // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0
3645 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3646 // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0
3647 { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3648 // Convert__imm_95_0__imm_95_14__reg0
3649 { CVT_imm_95_0, 0, CVT_imm_95_14, 0, CVT_reg0, 0, CVT_Done },
3650 // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0
3651 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3652 // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0
3653 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImmOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3654 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0
3655 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3656 // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0
3657 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3658 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0
3659 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3660 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0
3661 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3662 // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0
3663 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3664 // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0
3665 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3666 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm8s41_4__CondCode2_0
3667 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm8s4Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3668 // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0
3669 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3670 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0
3671 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3672 // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0
3673 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3674 // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0
3675 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3676 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0
3677 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3678 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0
3679 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3680 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0
3681 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3682 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1
3683 { CVT_95_Reg, 3, CVT_95_addCCOutOperands_95_defaultCCOutOp, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 2, CVT_Done },
3684 // Convert__Imm0_2551_3__CondCode2_0
3685 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3686 // Convert__Imm0_2551_1__CondCode2_0
3687 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3688 // Convert__Imm24bit1_1__CondCode2_0
3689 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3690 // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
3691 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3692 // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0
3693 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3694 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0
3695 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3696 // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0
3697 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3698 // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0
3699 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3700 // Convert__MemTBB2_1__CondCode2_0
3701 { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3702 // Convert__MemTBH2_1__CondCode2_0
3703 { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3704 // Convert__TraceSyncBarrierOpt1_0
3705 { CVT_95_addTraceSyncBarrierOptOperands, 1, CVT_Done },
3706 // Convert__TraceSyncBarrierOpt1_1__CondCode2_0
3707 { CVT_95_addTraceSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3708 // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0
3709 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3710 // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0
3711 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3712 // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0
3713 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3714 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0
3715 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3716 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0
3717 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3718 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0
3719 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3720 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0
3721 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3722 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0
3723 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3724 // Convert__Reg1_2__Reg1_3__VPTPredR4_0
3725 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3726 // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0
3727 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3728 // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0
3729 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3730 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0
3731 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_imm_95_0, 0, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3732 // Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0
3733 { CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3734 // Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0
3735 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3736 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0
3737 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3738 // Convert__Reg1_2__Reg1_3__VPTPredN3_0
3739 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3740 // Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0
3741 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3742 // Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0
3743 { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3744 // Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0
3745 { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3746 // Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0
3747 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addNEONi16splatNotOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3748 // Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0
3749 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addNEONi32splatNotOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3750 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0
3751 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3752 // Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0
3753 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3754 // Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0
3755 { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3756 // Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0
3757 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addNEONi16splatOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3758 // Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0
3759 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addNEONi32splatOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3760 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0
3761 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3762 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0
3763 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3764 // Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4
3765 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done },
3766 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0
3767 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationOddOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3768 // Convert__Reg1_2__Reg1_2__CondCode2_0
3769 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3770 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4
3771 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done },
3772 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5
3773 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex64Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
3774 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5
3775 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done },
3776 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0
3777 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3778 // Convert__Reg1_2__CondCode2_0
3779 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3780 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0
3781 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3782 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0
3783 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3784 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0
3785 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3786 // Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0
3787 { CVT_imm_95_0, 0, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3788 // Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0
3789 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3790 // Convert__imm_95_0__Reg1_2__VPTPredN3_0
3791 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3792 // Convert__Reg1_3__Reg1_4__CondCode2_0
3793 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3794 // Convert__Reg1_3__Reg1_4__VPTPredR4_0
3795 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3796 // Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0
3797 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3798 // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0
3799 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3800 // Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0
3801 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3802 // Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0
3803 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3804 // Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0
3805 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3806 // Convert__Reg1_2__Reg1_3
3807 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3808 // Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0
3809 { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3810 // Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0
3811 { CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3812 // Convert__Reg1_1__CoprocNum1_0__Imm11b1_2
3813 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
3814 // Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0
3815 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3816 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2
3817 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_Done },
3818 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0
3819 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3820 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3
3821 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3822 // Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0
3823 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3824 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3
3825 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
3826 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0
3827 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3828 // Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4
3829 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
3830 // Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0
3831 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3832 // Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4
3833 { CVT_95_Reg, 2, CVT_95_addCoprocNumOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
3834 // Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0
3835 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
3836 // Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0
3837 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_addPowerTwoOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3838 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3
3839 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3840 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4
3841 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
3842 // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
3843 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3844 // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
3845 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3846 // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0
3847 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3848 // Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0
3849 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_addPowerTwoOperands, 6, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
3850 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0
3851 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3852 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0
3853 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3854 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0
3855 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3856 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0
3857 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3858 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0
3859 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3860 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0
3861 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3862 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0
3863 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3864 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0
3865 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3866 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4
3867 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done },
3868 // Convert__Reg1_1__Reg1_2__Reg1_3
3869 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done },
3870 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4
3871 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_Done },
3872 // Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4
3873 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done },
3874 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
3875 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3876 // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0
3877 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3878 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0
3879 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3880 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
3881 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3882 // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0
3883 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3884 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0
3885 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3886 // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0
3887 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3888 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3889 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3890 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3891 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3892 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0
3893 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3894 // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
3895 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3896 // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
3897 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3898 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
3899 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3900 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
3901 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3902 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
3903 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3904 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
3905 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3906 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3907 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3908 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0
3909 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3910 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
3911 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3912 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
3913 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3914 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
3915 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3916 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
3917 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3918 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
3919 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3920 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
3921 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3922 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0
3923 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3924 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0
3925 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3926 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
3927 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3928 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3929 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3930 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
3931 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3932 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3933 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3934 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3935 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3936 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
3937 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3938 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
3939 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3940 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0
3941 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3942 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
3943 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3944 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
3945 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3946 // Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0
3947 { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3948 // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
3949 { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3950 // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0
3951 { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3952 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
3953 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3954 // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0
3955 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3956 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
3957 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3958 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0
3959 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3960 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
3961 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3962 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
3963 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3964 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0
3965 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3966 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0
3967 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3968 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0
3969 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3970 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0
3971 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3972 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0
3973 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3974 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0
3975 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3976 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0
3977 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3978 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
3979 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3980 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3981 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3982 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
3983 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3984 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
3985 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3986 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3987 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3988 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0
3989 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3990 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0
3991 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3992 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3993 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3994 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
3995 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3996 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0
3997 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
3998 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0
3999 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4000 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0
4001 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4002 // Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2
4003 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4004 // Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3
4005 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done },
4006 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
4007 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4008 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4009 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4010 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0
4011 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4012 // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0
4013 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4014 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4015 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4016 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4017 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4018 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4019 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4020 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0
4021 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4022 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
4023 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4024 // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4025 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4026 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4027 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4028 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0
4029 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4030 // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4031 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4032 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4033 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4034 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4035 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4036 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4037 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4038 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0
4039 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4040 // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0
4041 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4042 // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0
4043 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4044 // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0
4045 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4046 // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0
4047 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4048 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
4049 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4050 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
4051 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4052 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0
4053 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4054 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0
4055 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4056 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0
4057 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4058 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
4059 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4060 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
4061 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4062 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0
4063 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4064 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0
4065 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4066 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
4067 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4068 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0
4069 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4070 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0
4071 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4072 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
4073 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4074 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
4075 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4076 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4077 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4078 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0
4079 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4080 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0
4081 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4082 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0
4083 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4084 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
4085 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4086 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
4087 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4088 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0
4089 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4090 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0
4091 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4092 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
4093 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4094 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0
4095 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4096 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0
4097 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4098 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0
4099 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4100 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0
4101 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4102 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0
4103 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4104 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0
4105 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4106 // Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2
4107 { CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4108 // Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3
4109 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_3_3, CVT_Done },
4110 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3
4111 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done },
4112 // Convert__Reg1_1__CondCode2_0__SPRRegList1_2
4113 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
4114 // Convert__MemImm7s4Offset2_2__CondCode2_0
4115 { CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4116 // Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0
4117 { CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4118 // Convert__Reg1_1__AddrMode52_2__CondCode2_0
4119 { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4120 // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0
4121 { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4122 // Convert__Reg1_2__AddrMode52_3__CondCode2_0
4123 { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4124 // Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0
4125 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4126 // Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0
4127 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addMemImm7s4OffsetOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4128 // Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0
4129 { CVT_imm_95_0, 0, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4130 // Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0
4131 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4132 // Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0
4133 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4134 // Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0
4135 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4136 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0
4137 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4138 // Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0
4139 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4140 // Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0
4141 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4142 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0
4143 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift0Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4144 // Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0
4145 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4146 // Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0
4147 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4148 // Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0
4149 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4150 // Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0
4151 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4152 // Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0
4153 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4154 // Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0
4155 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4156 // Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0
4157 { CVT_95_addMemNoOffsetTOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4158 // Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0
4159 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4160 // Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0
4161 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4162 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0
4163 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift1Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4164 // Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0
4165 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4166 // Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0
4167 { CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4168 // Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0
4169 { CVT_95_Reg, 3, CVT_95_addMemRegRQOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4170 // Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0
4171 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4172 // Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0
4173 { CVT_95_addMemNoOffsetT2NoSpOperands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImm7Shift2Operands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4174 // Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0
4175 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addMemImmOffsetOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4176 // Convert__Reg1_1__CondCode2_0__imm_95_0
4177 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_imm_95_0, 0, CVT_Done },
4178 // Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0
4179 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4180 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
4181 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4182 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
4183 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4184 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0
4185 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4186 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0
4187 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4188 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0
4189 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4190 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0
4191 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4192 // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0
4193 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4194 // Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0
4195 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4196 // Convert__Reg1_2__FPImm1_3__CondCode2_0
4197 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4198 // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0
4199 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4200 // Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0
4201 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4202 // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0
4203 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4204 // Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0
4205 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4206 // Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0
4207 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4208 // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0
4209 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4210 // Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0
4211 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4212 // Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0
4213 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4214 // Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0
4215 { CVT_95_Reg, 3, CVT_95_addNEONvmovi32ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4216 // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0
4217 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4218 // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0
4219 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4220 // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0
4221 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4222 // Convert__Reg1_1__Reg1_2__VectorIndex321_3__CondCode2_0
4223 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4224 // Convert__Reg1_1__Tie0_2_2__Reg1_3__VectorIndex321_2__CondCode2_0
4225 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4226 // Convert__Reg1_2__FPImm1_3__VPTPredR4_0
4227 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4228 // Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0
4229 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4230 // Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0
4231 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4232 // Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0
4233 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4234 // Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0
4235 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4236 // Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0
4237 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4238 // Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0
4239 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4240 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0
4241 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4242 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0
4243 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4244 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0
4245 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4246 // Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0
4247 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMVEVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4248 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0
4249 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4250 // Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0
4251 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addMVEVectorIndexOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4252 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0
4253 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4254 // Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0
4255 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_4, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addMVEPairVectorIndexOperands, 3, CVT_95_addMVEPairVectorIndexOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4256 // ConvertCustom_cvtMVEVMOVQtoDReg
4257 { CVT_cvtMVEVMOVQtoDReg, 0, CVT_Done },
4258 // Convert__Reg1_1__imm_95_0__CondCode2_0
4259 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4260 // Convert__imm_95_0__Reg1_2__CondCode2_0
4261 { CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4262 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0
4263 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4264 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0
4265 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4266 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0
4267 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4268 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0
4269 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4270 // Convert__Reg1_1__Reg1_2__VPTPredR4_0
4271 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4272 // Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0
4273 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4274 // Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0
4275 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4276 // Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0
4277 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4278 // Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0
4279 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4280 // Convert__imm_95_0__imm_95_0__VPTPredN3_0
4281 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4282 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1
4283 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done },
4284 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1
4285 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done },
4286 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2
4287 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done },
4288 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2
4289 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done },
4290 // Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0
4291 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4292 // Convert__ITMask1_0
4293 { CVT_95_addITMaskOperands, 1, CVT_Done },
4294 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2
4295 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4296 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2
4297 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4298 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2
4299 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4300 // Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2
4301 { CVT_95_addITMaskOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addITCondCodeOperands, 3, CVT_Done },
4302 // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0
4303 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4304 // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0
4305 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4306 // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0
4307 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4308 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0
4309 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4310 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0
4311 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4312 // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0
4313 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4314 // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0
4315 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4316 // Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0
4317 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4318 // Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0
4319 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4320 // Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0
4321 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4322 // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0
4323 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4324 // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0
4325 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4326 // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0
4327 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4328 // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0
4329 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4330 // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0
4331 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4332 // Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0
4333 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4334 // Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0
4335 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4336 // Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0
4337 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4338 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0
4339 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4340 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0
4341 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4342 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0
4343 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4344 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0
4345 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4346 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0
4347 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4348 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0
4349 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4350 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0
4351 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4352 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0
4353 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4354 // Convert__CondCode2_0__FPDRegListWithVPR1_1
4355 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addFPDRegListWithVPROperands, 2, CVT_Done },
4356 // Convert__CondCode2_0__FPSRegListWithVPR1_1
4357 { CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_95_addFPSRegListWithVPROperands, 2, CVT_Done },
4358 // Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0
4359 { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, Tie1_2_2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4360 // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0
4361 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4362 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0
4363 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4364 // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0
4365 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4366 // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0
4367 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4368 // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0
4369 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4370 // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0
4371 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4372 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0
4373 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4374 // Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0
4375 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredROperands_95_defaultVPTPredOp, 1, CVT_Done },
4376 // Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0
4377 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4378 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0
4379 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4380 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0
4381 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4382 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0
4383 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4384 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0
4385 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4386 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0
4387 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addVPTPredNOperands_95_defaultVPTPredOp, 1, CVT_Done },
4388 // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
4389 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4390 // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
4391 { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4392 // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
4393 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4394 // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
4395 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4396 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0
4397 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4398 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0
4399 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4400 // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0
4401 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4402 // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0
4403 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4404 // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0
4405 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4406 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0
4407 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4408 // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0
4409 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4410 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0
4411 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4412 // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0
4413 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4414 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
4415 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4416 // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0
4417 { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4418 // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0
4419 { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4420 // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
4421 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4422 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0
4423 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4424 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0
4425 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4426 // Convert__VecListTwoMQ1_1__MemNoOffsetT21_2
4427 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4428 // Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3
4429 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done },
4430 // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
4431 { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4432 // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0
4433 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4434 // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
4435 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4436 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0
4437 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4438 // Convert__VecListFourMQ1_1__MemNoOffsetT21_2
4439 { CVT_95_addMVEVecListOperands, 2, CVT_95_addMemNoOffsetT2Operands, 3, CVT_Done },
4440 // Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3
4441 { CVT_95_addMemNoOffsetT2NoSpOperands, 3, CVT_95_addMVEVecListOperands, 2, CVT_Tied, Tie0_3_3, CVT_Done },
4442 // Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0
4443 { CVT_95_addMemNoOffsetT2Operands, 3, CVT_imm_95_0, 0, CVT_Tied, Tie0_3_3, CVT_95_addImm7s4Operands, 4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4444 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0
4445 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4446 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0
4447 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4448 // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0
4449 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4450 // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0
4451 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4452 // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0
4453 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4454 // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0
4455 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4456 // Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0
4457 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4458 // Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0
4459 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4460 // Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0
4461 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4462 // Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0
4463 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4464 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0
4465 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4466 // Convert__imm_95_2__CondCode2_0
4467 { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4468 // Convert__imm_95_3__CondCode2_0
4469 { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4470 // Convert__Reg1_0__Reg1_1__WLSLabel1_2
4471 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
4472 // Convert__Reg1_1__Reg1_2__WLSLabel1_3
4473 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
4474 // Convert__imm_95_1__CondCode2_0
4475 { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands_95_defaultCondCodeOp, 1, CVT_Done },
4476};
4477
4478void ARMAsmParser::
4479convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
4480 const OperandVector &Operands,
4481 const SmallBitVector &OptionalOperandsMask,
4482 ArrayRef<unsigned> DefaultsOffset) {
4483 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4484 const uint8_t *Converter = ConversionTable[Kind];
4485 Inst.setOpcode(Opcode);
4486 for (const uint8_t *p = Converter; *p; p += 2) {
4487 unsigned OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
4488 switch (*p) {
4489 default: llvm_unreachable("invalid conversion entry!");
4490 case CVT_Reg:
4491 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4492 break;
4493 case CVT_Tied: {
4494 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
4495 std::begin(TiedAsmOperandTable)) &&
4496 "Tied operand not found");
4497 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
4498 if (TiedResOpnd != (uint8_t)-1)
4499 Inst.addOperand(Inst.getOperand(TiedResOpnd));
4500 break;
4501 }
4502 case CVT_95_Reg:
4503 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
4504 break;
4505 case CVT_95_addCCOutOperands_95_defaultCCOutOp:
4506 if (OptionalOperandsMask[*(p + 1)]) {
4507 defaultCCOutOp()->addCCOutOperands(Inst, 1);
4508 } else {
4509 static_cast<ARMOperand &>(*Operands[OpIdx]).addCCOutOperands(Inst, 1);
4510 }
4511 break;
4512 case CVT_95_addCondCodeOperands_95_defaultCondCodeOp:
4513 if (OptionalOperandsMask[*(p + 1)]) {
4514 defaultCondCodeOp()->addCondCodeOperands(Inst, 2);
4515 } else {
4516 static_cast<ARMOperand &>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2);
4517 }
4518 break;
4519 case CVT_95_addRegShiftedImmOperands:
4520 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2);
4521 break;
4522 case CVT_95_addImmOperands:
4523 static_cast<ARMOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
4524 break;
4525 case CVT_95_addT2SOImmNotOperands:
4526 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1);
4527 break;
4528 case CVT_95_addRegShiftedRegOperands:
4529 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3);
4530 break;
4531 case CVT_95_addModImmOperands:
4532 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmOperands(Inst, 1);
4533 break;
4534 case CVT_95_addModImmNotOperands:
4535 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1);
4536 break;
4537 case CVT_95_addImm0_95_508s4Operands:
4538 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1);
4539 break;
4540 case CVT_regSP:
4541 Inst.addOperand(MCOperand::createReg(ARM::SP));
4542 break;
4543 case CVT_95_addImm0_95_508s4NegOperands:
4544 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1);
4545 break;
4546 case CVT_95_addThumbModImmNeg8_95_255Operands:
4547 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1);
4548 break;
4549 case CVT_95_addImm0_95_1020s4Operands:
4550 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1);
4551 break;
4552 case CVT_95_addThumbModImmNeg1_95_7Operands:
4553 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1);
4554 break;
4555 case CVT_95_addImm0_95_4095NegOperands:
4556 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1);
4557 break;
4558 case CVT_95_addT2SOImmNegOperands:
4559 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1);
4560 break;
4561 case CVT_95_addModImmNegOperands:
4562 static_cast<ARMOperand &>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1);
4563 break;
4564 case CVT_95_addUnsignedOffset_95_b8s2Operands:
4565 static_cast<ARMOperand &>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1);
4566 break;
4567 case CVT_95_addAdrLabelOperands:
4568 static_cast<ARMOperand &>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1);
4569 break;
4570 case CVT_imm_95_45:
4571 Inst.addOperand(MCOperand::createImm(45));
4572 break;
4573 case CVT_cvtThumbBranches:
4574 cvtThumbBranches(Inst, Operands);
4575 break;
4576 case CVT_95_addARMBranchTargetOperands:
4577 static_cast<ARMOperand &>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1);
4578 break;
4579 case CVT_95_addBitfieldOperands:
4580 static_cast<ARMOperand &>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1);
4581 break;
4582 case CVT_95_addITCondCodeOperands:
4583 static_cast<ARMOperand &>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1);
4584 break;
4585 case CVT_imm_95_0:
4586 Inst.addOperand(MCOperand::createImm(0));
4587 break;
4588 case CVT_95_addThumbBranchTargetOperands:
4589 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1);
4590 break;
4591 case CVT_imm_95_15:
4592 Inst.addOperand(MCOperand::createImm(15));
4593 break;
4594 case CVT_95_addCoprocNumOperands:
4595 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1);
4596 break;
4597 case CVT_95_addCoprocRegOperands:
4598 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1);
4599 break;
4600 case CVT_95_addITCondCodeInvOperands:
4601 static_cast<ARMOperand &>(*Operands[OpIdx]).addITCondCodeInvOperands(Inst, 1);
4602 break;
4603 case CVT_imm_95_22:
4604 Inst.addOperand(MCOperand::createImm(22));
4605 break;
4606 case CVT_95_addRegListWithAPSROperands:
4607 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegListWithAPSROperands(Inst, 1);
4608 break;
4609 case CVT_95_addProcIFlagsOperands:
4610 static_cast<ARMOperand &>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1);
4611 break;
4612 case CVT_imm_95_20:
4613 Inst.addOperand(MCOperand::createImm(20));
4614 break;
4615 case CVT_regZR:
4616 Inst.addOperand(MCOperand::createReg(ARM::ZR));
4617 break;
4618 case CVT_imm_95_12:
4619 Inst.addOperand(MCOperand::createImm(12));
4620 break;
4621 case CVT_95_addMemBarrierOptOperands:
4622 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1);
4623 break;
4624 case CVT_imm_95_16:
4625 Inst.addOperand(MCOperand::createImm(16));
4626 break;
4627 case CVT_95_addFPImmOperands:
4628 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPImmOperands(Inst, 1);
4629 break;
4630 case CVT_95_addDPRRegListOperands:
4631 static_cast<ARMOperand &>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1);
4632 break;
4633 case CVT_imm_95_1:
4634 Inst.addOperand(MCOperand::createImm(1));
4635 break;
4636 case CVT_95_addInstSyncBarrierOptOperands:
4637 static_cast<ARMOperand &>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1);
4638 break;
4639 case CVT_95_addITMaskOperands:
4640 static_cast<ARMOperand &>(*Operands[OpIdx]).addITMaskOperands(Inst, 1);
4641 break;
4642 case CVT_95_addMemNoOffsetOperands:
4643 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1);
4644 break;
4645 case CVT_95_addAddrMode5Operands:
4646 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2);
4647 break;
4648 case CVT_95_addCoprocOptionOperands:
4649 static_cast<ARMOperand &>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1);
4650 break;
4651 case CVT_95_addPostIdxImm8s4Operands:
4652 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1);
4653 break;
4654 case CVT_95_addRegListOperands:
4655 static_cast<ARMOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
4656 break;
4657 case CVT_95_addThumbMemPCOperands:
4658 static_cast<ARMOperand &>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1);
4659 break;
4660 case CVT_95_addMemThumbRIs4Operands:
4661 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2);
4662 break;
4663 case CVT_95_addMemThumbRROperands:
4664 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2);
4665 break;
4666 case CVT_95_addMemThumbSPIOperands:
4667 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2);
4668 break;
4669 case CVT_95_addConstPoolAsmImmOperands:
4670 static_cast<ARMOperand &>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1);
4671 break;
4672 case CVT_95_addMemImm12OffsetOperands:
4673 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2);
4674 break;
4675 case CVT_95_addMemImmOffsetOperands:
4676 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImmOffsetOperands(Inst, 2);
4677 break;
4678 case CVT_95_addMemRegOffsetOperands:
4679 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3);
4680 break;
4681 case CVT_95_addMemUImm12OffsetOperands:
4682 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2);
4683 break;
4684 case CVT_95_addT2MemRegOffsetOperands:
4685 static_cast<ARMOperand &>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3);
4686 break;
4687 case CVT_95_addMemPCRelImm12Operands:
4688 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1);
4689 break;
4690 case CVT_95_addAM2OffsetImmOperands:
4691 static_cast<ARMOperand &>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2);
4692 break;
4693 case CVT_95_addPostIdxRegShiftedOperands:
4694 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2);
4695 break;
4696 case CVT_95_addMemThumbRIs1Operands:
4697 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2);
4698 break;
4699 case CVT_95_addMemImm8s4OffsetOperands:
4700 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2);
4701 break;
4702 case CVT_95_addAddrMode3Operands:
4703 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3);
4704 break;
4705 case CVT_95_addImm8s4Operands:
4706 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm8s4Operands(Inst, 1);
4707 break;
4708 case CVT_95_addAM3OffsetOperands:
4709 static_cast<ARMOperand &>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2);
4710 break;
4711 case CVT_95_addMemImm0_95_1020s4OffsetOperands:
4712 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2);
4713 break;
4714 case CVT_95_addMemThumbRIs2Operands:
4715 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2);
4716 break;
4717 case CVT_95_addPostIdxRegOperands:
4718 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2);
4719 break;
4720 case CVT_95_addPostIdxImm8Operands:
4721 static_cast<ARMOperand &>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1);
4722 break;
4723 case CVT_reg0:
4724 Inst.addOperand(MCOperand::createReg(0));
4725 break;
4726 case CVT_regCPSR:
4727 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
4728 break;
4729 case CVT_imm_95_14:
4730 Inst.addOperand(MCOperand::createImm(14));
4731 break;
4732 case CVT_95_addBankedRegOperands:
4733 static_cast<ARMOperand &>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1);
4734 break;
4735 case CVT_95_addMSRMaskOperands:
4736 static_cast<ARMOperand &>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1);
4737 break;
4738 case CVT_cvtThumbMultiply:
4739 cvtThumbMultiply(Inst, Operands);
4740 break;
4741 case CVT_regR8:
4742 Inst.addOperand(MCOperand::createReg(ARM::R8));
4743 break;
4744 case CVT_regR0:
4745 Inst.addOperand(MCOperand::createReg(ARM::R0));
4746 break;
4747 case CVT_imm_95_29:
4748 Inst.addOperand(MCOperand::createImm(29));
4749 break;
4750 case CVT_imm_95_13:
4751 Inst.addOperand(MCOperand::createImm(13));
4752 break;
4753 case CVT_95_addPKHASRImmOperands:
4754 static_cast<ARMOperand &>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1);
4755 break;
4756 case CVT_imm_95_4:
4757 Inst.addOperand(MCOperand::createImm(4));
4758 break;
4759 case CVT_95_addImm1_95_32Operands:
4760 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1);
4761 break;
4762 case CVT_imm_95_5:
4763 Inst.addOperand(MCOperand::createImm(5));
4764 break;
4765 case CVT_95_addMveSaturateOperands:
4766 static_cast<ARMOperand &>(*Operands[OpIdx]).addMveSaturateOperands(Inst, 1);
4767 break;
4768 case CVT_95_addShifterImmOperands:
4769 static_cast<ARMOperand &>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1);
4770 break;
4771 case CVT_95_addImm1_95_16Operands:
4772 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1);
4773 break;
4774 case CVT_95_addRotImmOperands:
4775 static_cast<ARMOperand &>(*Operands[OpIdx]).addRotImmOperands(Inst, 1);
4776 break;
4777 case CVT_95_addMemTBBOperands:
4778 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2);
4779 break;
4780 case CVT_95_addMemTBHOperands:
4781 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2);
4782 break;
4783 case CVT_95_addTraceSyncBarrierOptOperands:
4784 static_cast<ARMOperand &>(*Operands[OpIdx]).addTraceSyncBarrierOptOperands(Inst, 1);
4785 break;
4786 case CVT_95_addVPTPredNOperands_95_defaultVPTPredOp:
4787 if (OptionalOperandsMask[*(p + 1)]) {
4788 defaultVPTPredOp()->addVPTPredNOperands(Inst, 3);
4789 } else {
4790 static_cast<ARMOperand &>(*Operands[OpIdx]).addVPTPredNOperands(Inst, 3);
4791 }
4792 break;
4793 case CVT_95_addVPTPredROperands_95_defaultVPTPredOp:
4794 if (OptionalOperandsMask[*(p + 1)]) {
4795 defaultVPTPredOp()->addVPTPredROperands(Inst, 4);
4796 } else {
4797 static_cast<ARMOperand &>(*Operands[OpIdx]).addVPTPredROperands(Inst, 4);
4798 }
4799 break;
4800 case CVT_95_addNEONi16splatNotOperands:
4801 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1);
4802 break;
4803 case CVT_95_addNEONi32splatNotOperands:
4804 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1);
4805 break;
4806 case CVT_95_addNEONi16splatOperands:
4807 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1);
4808 break;
4809 case CVT_95_addNEONi32splatOperands:
4810 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1);
4811 break;
4812 case CVT_95_addComplexRotationOddOperands:
4813 static_cast<ARMOperand &>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1);
4814 break;
4815 case CVT_95_addComplexRotationEvenOperands:
4816 static_cast<ARMOperand &>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1);
4817 break;
4818 case CVT_95_addVectorIndex64Operands:
4819 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex64Operands(Inst, 1);
4820 break;
4821 case CVT_95_addVectorIndex32Operands:
4822 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1);
4823 break;
4824 case CVT_95_addFBits16Operands:
4825 static_cast<ARMOperand &>(*Operands[OpIdx]).addFBits16Operands(Inst, 1);
4826 break;
4827 case CVT_95_addFBits32Operands:
4828 static_cast<ARMOperand &>(*Operands[OpIdx]).addFBits32Operands(Inst, 1);
4829 break;
4830 case CVT_95_addPowerTwoOperands:
4831 static_cast<ARMOperand &>(*Operands[OpIdx]).addPowerTwoOperands(Inst, 1);
4832 break;
4833 case CVT_95_addVectorIndex16Operands:
4834 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1);
4835 break;
4836 case CVT_95_addVectorIndex8Operands:
4837 static_cast<ARMOperand &>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1);
4838 break;
4839 case CVT_95_addVecListOperands:
4840 static_cast<ARMOperand &>(*Operands[OpIdx]).addVecListOperands(Inst, 1);
4841 break;
4842 case CVT_95_addDupAlignedMemory16Operands:
4843 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2);
4844 break;
4845 case CVT_95_addAlignedMemory64or128Operands:
4846 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2);
4847 break;
4848 case CVT_95_addAlignedMemory64or128or256Operands:
4849 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2);
4850 break;
4851 case CVT_95_addAlignedMemory64Operands:
4852 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2);
4853 break;
4854 case CVT_95_addVecListIndexedOperands:
4855 static_cast<ARMOperand &>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2);
4856 break;
4857 case CVT_95_addAlignedMemory16Operands:
4858 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2);
4859 break;
4860 case CVT_95_addDupAlignedMemory32Operands:
4861 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2);
4862 break;
4863 case CVT_95_addAlignedMemory32Operands:
4864 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2);
4865 break;
4866 case CVT_95_addDupAlignedMemoryNoneOperands:
4867 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2);
4868 break;
4869 case CVT_95_addAlignedMemoryNoneOperands:
4870 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2);
4871 break;
4872 case CVT_95_addAlignedMemoryOperands:
4873 static_cast<ARMOperand &>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2);
4874 break;
4875 case CVT_95_addDupAlignedMemory64Operands:
4876 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2);
4877 break;
4878 case CVT_95_addMVEVecListOperands:
4879 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEVecListOperands(Inst, 1);
4880 break;
4881 case CVT_95_addMemNoOffsetT2Operands:
4882 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetT2Operands(Inst, 1);
4883 break;
4884 case CVT_95_addMemNoOffsetT2NoSpOperands:
4885 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetT2NoSpOperands(Inst, 1);
4886 break;
4887 case CVT_95_addDupAlignedMemory64or128Operands:
4888 static_cast<ARMOperand &>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2);
4889 break;
4890 case CVT_95_addSPRRegListOperands:
4891 static_cast<ARMOperand &>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1);
4892 break;
4893 case CVT_95_addMemImm7s4OffsetOperands:
4894 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemImm7s4OffsetOperands(Inst, 2);
4895 break;
4896 case CVT_95_addAddrMode5FP16Operands:
4897 static_cast<ARMOperand &>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2);
4898 break;
4899 case CVT_95_addImm7s4Operands:
4900 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7s4Operands(Inst, 1);
4901 break;
4902 case CVT_95_addMemRegRQOffsetOperands:
4903 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemRegRQOffsetOperands(Inst, 2);
4904 break;
4905 case CVT_95_addMemNoOffsetTOperands:
4906 static_cast<ARMOperand &>(*Operands[OpIdx]).addMemNoOffsetTOperands(Inst, 1);
4907 break;
4908 case CVT_95_addImm7Shift0Operands:
4909 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift0Operands(Inst, 1);
4910 break;
4911 case CVT_95_addImm7Shift1Operands:
4912 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift1Operands(Inst, 1);
4913 break;
4914 case CVT_95_addImm7Shift2Operands:
4915 static_cast<ARMOperand &>(*Operands[OpIdx]).addImm7Shift2Operands(Inst, 1);
4916 break;
4917 case CVT_95_addNEONi32vmovOperands:
4918 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1);
4919 break;
4920 case CVT_95_addNEONvmovi8ReplicateOperands:
4921 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi8ReplicateOperands(Inst, 1);
4922 break;
4923 case CVT_95_addNEONvmovi16ReplicateOperands:
4924 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi16ReplicateOperands(Inst, 1);
4925 break;
4926 case CVT_95_addNEONi32vmovNegOperands:
4927 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1);
4928 break;
4929 case CVT_95_addNEONvmovi32ReplicateOperands:
4930 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONvmovi32ReplicateOperands(Inst, 1);
4931 break;
4932 case CVT_95_addNEONi64splatOperands:
4933 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1);
4934 break;
4935 case CVT_95_addNEONi8splatOperands:
4936 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1);
4937 break;
4938 case CVT_95_addMVEVectorIndexOperands:
4939 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEVectorIndexOperands(Inst, 1);
4940 break;
4941 case CVT_95_addMVEPairVectorIndexOperands:
4942 static_cast<ARMOperand &>(*Operands[OpIdx]).addMVEPairVectorIndexOperands(Inst, 1);
4943 break;
4944 case CVT_cvtMVEVMOVQtoDReg:
4945 cvtMVEVMOVQtoDReg(Inst, Operands);
4946 break;
4947 case CVT_95_addNEONinvi8ReplicateOperands:
4948 static_cast<ARMOperand &>(*Operands[OpIdx]).addNEONinvi8ReplicateOperands(Inst, 1);
4949 break;
4950 case CVT_95_addFPDRegListWithVPROperands:
4951 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPDRegListWithVPROperands(Inst, 1);
4952 break;
4953 case CVT_95_addFPSRegListWithVPROperands:
4954 static_cast<ARMOperand &>(*Operands[OpIdx]).addFPSRegListWithVPROperands(Inst, 1);
4955 break;
4956 case CVT_imm_95_2:
4957 Inst.addOperand(MCOperand::createImm(2));
4958 break;
4959 case CVT_imm_95_3:
4960 Inst.addOperand(MCOperand::createImm(3));
4961 break;
4962 }
4963 }
4964}
4965
4966void ARMAsmParser::
4967convertToMapAndConstraints(unsigned Kind,
4968 const OperandVector &Operands) {
4969 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4970 unsigned NumMCOperands = 0;
4971 const uint8_t *Converter = ConversionTable[Kind];
4972 for (const uint8_t *p = Converter; *p; p += 2) {
4973 switch (*p) {
4974 default: llvm_unreachable("invalid conversion entry!");
4975 case CVT_Reg:
4976 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4977 Operands[*(p + 1)]->setConstraint("r");
4978 ++NumMCOperands;
4979 break;
4980 case CVT_Tied:
4981 ++NumMCOperands;
4982 break;
4983 case CVT_95_Reg:
4984 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4985 Operands[*(p + 1)]->setConstraint("r");
4986 NumMCOperands += 1;
4987 break;
4988 case CVT_95_addCCOutOperands_95_defaultCCOutOp:
4989 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4990 Operands[*(p + 1)]->setConstraint("m");
4991 NumMCOperands += 1;
4992 break;
4993 case CVT_95_addCondCodeOperands_95_defaultCondCodeOp:
4994 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
4995 Operands[*(p + 1)]->setConstraint("m");
4996 NumMCOperands += 2;
4997 break;
4998 case CVT_95_addRegShiftedImmOperands:
4999 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5000 Operands[*(p + 1)]->setConstraint("m");
5001 NumMCOperands += 2;
5002 break;
5003 case CVT_95_addImmOperands:
5004 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5005 Operands[*(p + 1)]->setConstraint("m");
5006 NumMCOperands += 1;
5007 break;
5008 case CVT_95_addT2SOImmNotOperands:
5009 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5010 Operands[*(p + 1)]->setConstraint("m");
5011 NumMCOperands += 1;
5012 break;
5013 case CVT_95_addRegShiftedRegOperands:
5014 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5015 Operands[*(p + 1)]->setConstraint("m");
5016 NumMCOperands += 3;
5017 break;
5018 case CVT_95_addModImmOperands:
5019 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5020 Operands[*(p + 1)]->setConstraint("m");
5021 NumMCOperands += 1;
5022 break;
5023 case CVT_95_addModImmNotOperands:
5024 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5025 Operands[*(p + 1)]->setConstraint("m");
5026 NumMCOperands += 1;
5027 break;
5028 case CVT_95_addImm0_95_508s4Operands:
5029 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5030 Operands[*(p + 1)]->setConstraint("m");
5031 NumMCOperands += 1;
5032 break;
5033 case CVT_regSP:
5034 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5035 Operands[*(p + 1)]->setConstraint("m");
5036 ++NumMCOperands;
5037 break;
5038 case CVT_95_addImm0_95_508s4NegOperands:
5039 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5040 Operands[*(p + 1)]->setConstraint("m");
5041 NumMCOperands += 1;
5042 break;
5043 case CVT_95_addThumbModImmNeg8_95_255Operands:
5044 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5045 Operands[*(p + 1)]->setConstraint("m");
5046 NumMCOperands += 1;
5047 break;
5048 case CVT_95_addImm0_95_1020s4Operands:
5049 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5050 Operands[*(p + 1)]->setConstraint("m");
5051 NumMCOperands += 1;
5052 break;
5053 case CVT_95_addThumbModImmNeg1_95_7Operands:
5054 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5055 Operands[*(p + 1)]->setConstraint("m");
5056 NumMCOperands += 1;
5057 break;
5058 case CVT_95_addImm0_95_4095NegOperands:
5059 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5060 Operands[*(p + 1)]->setConstraint("m");
5061 NumMCOperands += 1;
5062 break;
5063 case CVT_95_addT2SOImmNegOperands:
5064 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5065 Operands[*(p + 1)]->setConstraint("m");
5066 NumMCOperands += 1;
5067 break;
5068 case CVT_95_addModImmNegOperands:
5069 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5070 Operands[*(p + 1)]->setConstraint("m");
5071 NumMCOperands += 1;
5072 break;
5073 case CVT_95_addUnsignedOffset_95_b8s2Operands:
5074 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5075 Operands[*(p + 1)]->setConstraint("m");
5076 NumMCOperands += 1;
5077 break;
5078 case CVT_95_addAdrLabelOperands:
5079 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5080 Operands[*(p + 1)]->setConstraint("m");
5081 NumMCOperands += 1;
5082 break;
5083 case CVT_imm_95_45:
5084 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5085 Operands[*(p + 1)]->setConstraint("");
5086 ++NumMCOperands;
5087 break;
5088 case CVT_95_addARMBranchTargetOperands:
5089 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5090 Operands[*(p + 1)]->setConstraint("m");
5091 NumMCOperands += 1;
5092 break;
5093 case CVT_95_addBitfieldOperands:
5094 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5095 Operands[*(p + 1)]->setConstraint("m");
5096 NumMCOperands += 1;
5097 break;
5098 case CVT_95_addITCondCodeOperands:
5099 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5100 Operands[*(p + 1)]->setConstraint("m");
5101 NumMCOperands += 1;
5102 break;
5103 case CVT_imm_95_0:
5104 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5105 Operands[*(p + 1)]->setConstraint("");
5106 ++NumMCOperands;
5107 break;
5108 case CVT_95_addThumbBranchTargetOperands:
5109 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5110 Operands[*(p + 1)]->setConstraint("m");
5111 NumMCOperands += 1;
5112 break;
5113 case CVT_imm_95_15:
5114 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5115 Operands[*(p + 1)]->setConstraint("");
5116 ++NumMCOperands;
5117 break;
5118 case CVT_95_addCoprocNumOperands:
5119 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5120 Operands[*(p + 1)]->setConstraint("m");
5121 NumMCOperands += 1;
5122 break;
5123 case CVT_95_addCoprocRegOperands:
5124 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5125 Operands[*(p + 1)]->setConstraint("m");
5126 NumMCOperands += 1;
5127 break;
5128 case CVT_95_addITCondCodeInvOperands:
5129 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5130 Operands[*(p + 1)]->setConstraint("m");
5131 NumMCOperands += 1;
5132 break;
5133 case CVT_imm_95_22:
5134 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5135 Operands[*(p + 1)]->setConstraint("");
5136 ++NumMCOperands;
5137 break;
5138 case CVT_95_addRegListWithAPSROperands:
5139 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5140 Operands[*(p + 1)]->setConstraint("m");
5141 NumMCOperands += 1;
5142 break;
5143 case CVT_95_addProcIFlagsOperands:
5144 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5145 Operands[*(p + 1)]->setConstraint("m");
5146 NumMCOperands += 1;
5147 break;
5148 case CVT_imm_95_20:
5149 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5150 Operands[*(p + 1)]->setConstraint("");
5151 ++NumMCOperands;
5152 break;
5153 case CVT_regZR:
5154 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5155 Operands[*(p + 1)]->setConstraint("m");
5156 ++NumMCOperands;
5157 break;
5158 case CVT_imm_95_12:
5159 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5160 Operands[*(p + 1)]->setConstraint("");
5161 ++NumMCOperands;
5162 break;
5163 case CVT_95_addMemBarrierOptOperands:
5164 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5165 Operands[*(p + 1)]->setConstraint("m");
5166 NumMCOperands += 1;
5167 break;
5168 case CVT_imm_95_16:
5169 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5170 Operands[*(p + 1)]->setConstraint("");
5171 ++NumMCOperands;
5172 break;
5173 case CVT_95_addFPImmOperands:
5174 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5175 Operands[*(p + 1)]->setConstraint("m");
5176 NumMCOperands += 1;
5177 break;
5178 case CVT_95_addDPRRegListOperands:
5179 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5180 Operands[*(p + 1)]->setConstraint("m");
5181 NumMCOperands += 1;
5182 break;
5183 case CVT_imm_95_1:
5184 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5185 Operands[*(p + 1)]->setConstraint("");
5186 ++NumMCOperands;
5187 break;
5188 case CVT_95_addInstSyncBarrierOptOperands:
5189 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5190 Operands[*(p + 1)]->setConstraint("m");
5191 NumMCOperands += 1;
5192 break;
5193 case CVT_95_addITMaskOperands:
5194 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5195 Operands[*(p + 1)]->setConstraint("m");
5196 NumMCOperands += 1;
5197 break;
5198 case CVT_95_addMemNoOffsetOperands:
5199 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5200 Operands[*(p + 1)]->setConstraint("m");
5201 NumMCOperands += 1;
5202 break;
5203 case CVT_95_addAddrMode5Operands:
5204 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5205 Operands[*(p + 1)]->setConstraint("m");
5206 NumMCOperands += 2;
5207 break;
5208 case CVT_95_addCoprocOptionOperands:
5209 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5210 Operands[*(p + 1)]->setConstraint("m");
5211 NumMCOperands += 1;
5212 break;
5213 case CVT_95_addPostIdxImm8s4Operands:
5214 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5215 Operands[*(p + 1)]->setConstraint("m");
5216 NumMCOperands += 1;
5217 break;
5218 case CVT_95_addRegListOperands:
5219 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5220 Operands[*(p + 1)]->setConstraint("m");
5221 NumMCOperands += 1;
5222 break;
5223 case CVT_95_addThumbMemPCOperands:
5224 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5225 Operands[*(p + 1)]->setConstraint("m");
5226 NumMCOperands += 1;
5227 break;
5228 case CVT_95_addMemThumbRIs4Operands:
5229 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5230 Operands[*(p + 1)]->setConstraint("m");
5231 NumMCOperands += 2;
5232 break;
5233 case CVT_95_addMemThumbRROperands:
5234 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5235 Operands[*(p + 1)]->setConstraint("m");
5236 NumMCOperands += 2;
5237 break;
5238 case CVT_95_addMemThumbSPIOperands:
5239 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5240 Operands[*(p + 1)]->setConstraint("m");
5241 NumMCOperands += 2;
5242 break;
5243 case CVT_95_addConstPoolAsmImmOperands:
5244 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5245 Operands[*(p + 1)]->setConstraint("m");
5246 NumMCOperands += 1;
5247 break;
5248 case CVT_95_addMemImm12OffsetOperands:
5249 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5250 Operands[*(p + 1)]->setConstraint("m");
5251 NumMCOperands += 2;
5252 break;
5253 case CVT_95_addMemImmOffsetOperands:
5254 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5255 Operands[*(p + 1)]->setConstraint("m");
5256 NumMCOperands += 2;
5257 break;
5258 case CVT_95_addMemRegOffsetOperands:
5259 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5260 Operands[*(p + 1)]->setConstraint("m");
5261 NumMCOperands += 3;
5262 break;
5263 case CVT_95_addMemUImm12OffsetOperands:
5264 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5265 Operands[*(p + 1)]->setConstraint("m");
5266 NumMCOperands += 2;
5267 break;
5268 case CVT_95_addT2MemRegOffsetOperands:
5269 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5270 Operands[*(p + 1)]->setConstraint("m");
5271 NumMCOperands += 3;
5272 break;
5273 case CVT_95_addMemPCRelImm12Operands:
5274 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5275 Operands[*(p + 1)]->setConstraint("m");
5276 NumMCOperands += 1;
5277 break;
5278 case CVT_95_addAM2OffsetImmOperands:
5279 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5280 Operands[*(p + 1)]->setConstraint("m");
5281 NumMCOperands += 2;
5282 break;
5283 case CVT_95_addPostIdxRegShiftedOperands:
5284 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5285 Operands[*(p + 1)]->setConstraint("m");
5286 NumMCOperands += 2;
5287 break;
5288 case CVT_95_addMemThumbRIs1Operands:
5289 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5290 Operands[*(p + 1)]->setConstraint("m");
5291 NumMCOperands += 2;
5292 break;
5293 case CVT_95_addMemImm8s4OffsetOperands:
5294 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5295 Operands[*(p + 1)]->setConstraint("m");
5296 NumMCOperands += 2;
5297 break;
5298 case CVT_95_addAddrMode3Operands:
5299 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5300 Operands[*(p + 1)]->setConstraint("m");
5301 NumMCOperands += 3;
5302 break;
5303 case CVT_95_addImm8s4Operands:
5304 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5305 Operands[*(p + 1)]->setConstraint("m");
5306 NumMCOperands += 1;
5307 break;
5308 case CVT_95_addAM3OffsetOperands:
5309 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5310 Operands[*(p + 1)]->setConstraint("m");
5311 NumMCOperands += 2;
5312 break;
5313 case CVT_95_addMemImm0_95_1020s4OffsetOperands:
5314 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5315 Operands[*(p + 1)]->setConstraint("m");
5316 NumMCOperands += 2;
5317 break;
5318 case CVT_95_addMemThumbRIs2Operands:
5319 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5320 Operands[*(p + 1)]->setConstraint("m");
5321 NumMCOperands += 2;
5322 break;
5323 case CVT_95_addPostIdxRegOperands:
5324 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5325 Operands[*(p + 1)]->setConstraint("m");
5326 NumMCOperands += 2;
5327 break;
5328 case CVT_95_addPostIdxImm8Operands:
5329 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5330 Operands[*(p + 1)]->setConstraint("m");
5331 NumMCOperands += 1;
5332 break;
5333 case CVT_reg0:
5334 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5335 Operands[*(p + 1)]->setConstraint("m");
5336 ++NumMCOperands;
5337 break;
5338 case CVT_regCPSR:
5339 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5340 Operands[*(p + 1)]->setConstraint("m");
5341 ++NumMCOperands;
5342 break;
5343 case CVT_imm_95_14:
5344 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5345 Operands[*(p + 1)]->setConstraint("");
5346 ++NumMCOperands;
5347 break;
5348 case CVT_95_addBankedRegOperands:
5349 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5350 Operands[*(p + 1)]->setConstraint("m");
5351 NumMCOperands += 1;
5352 break;
5353 case CVT_95_addMSRMaskOperands:
5354 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5355 Operands[*(p + 1)]->setConstraint("m");
5356 NumMCOperands += 1;
5357 break;
5358 case CVT_regR8:
5359 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5360 Operands[*(p + 1)]->setConstraint("m");
5361 ++NumMCOperands;
5362 break;
5363 case CVT_regR0:
5364 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5365 Operands[*(p + 1)]->setConstraint("m");
5366 ++NumMCOperands;
5367 break;
5368 case CVT_imm_95_29:
5369 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5370 Operands[*(p + 1)]->setConstraint("");
5371 ++NumMCOperands;
5372 break;
5373 case CVT_imm_95_13:
5374 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5375 Operands[*(p + 1)]->setConstraint("");
5376 ++NumMCOperands;
5377 break;
5378 case CVT_95_addPKHASRImmOperands:
5379 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5380 Operands[*(p + 1)]->setConstraint("m");
5381 NumMCOperands += 1;
5382 break;
5383 case CVT_imm_95_4:
5384 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5385 Operands[*(p + 1)]->setConstraint("");
5386 ++NumMCOperands;
5387 break;
5388 case CVT_95_addImm1_95_32Operands:
5389 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5390 Operands[*(p + 1)]->setConstraint("m");
5391 NumMCOperands += 1;
5392 break;
5393 case CVT_imm_95_5:
5394 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5395 Operands[*(p + 1)]->setConstraint("");
5396 ++NumMCOperands;
5397 break;
5398 case CVT_95_addMveSaturateOperands:
5399 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5400 Operands[*(p + 1)]->setConstraint("m");
5401 NumMCOperands += 1;
5402 break;
5403 case CVT_95_addShifterImmOperands:
5404 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5405 Operands[*(p + 1)]->setConstraint("m");
5406 NumMCOperands += 1;
5407 break;
5408 case CVT_95_addImm1_95_16Operands:
5409 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5410 Operands[*(p + 1)]->setConstraint("m");
5411 NumMCOperands += 1;
5412 break;
5413 case CVT_95_addRotImmOperands:
5414 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5415 Operands[*(p + 1)]->setConstraint("m");
5416 NumMCOperands += 1;
5417 break;
5418 case CVT_95_addMemTBBOperands:
5419 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5420 Operands[*(p + 1)]->setConstraint("m");
5421 NumMCOperands += 2;
5422 break;
5423 case CVT_95_addMemTBHOperands:
5424 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5425 Operands[*(p + 1)]->setConstraint("m");
5426 NumMCOperands += 2;
5427 break;
5428 case CVT_95_addTraceSyncBarrierOptOperands:
5429 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5430 Operands[*(p + 1)]->setConstraint("m");
5431 NumMCOperands += 1;
5432 break;
5433 case CVT_95_addVPTPredNOperands_95_defaultVPTPredOp:
5434 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5435 Operands[*(p + 1)]->setConstraint("m");
5436 NumMCOperands += 3;
5437 break;
5438 case CVT_95_addVPTPredROperands_95_defaultVPTPredOp:
5439 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5440 Operands[*(p + 1)]->setConstraint("m");
5441 NumMCOperands += 4;
5442 break;
5443 case CVT_95_addNEONi16splatNotOperands:
5444 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5445 Operands[*(p + 1)]->setConstraint("m");
5446 NumMCOperands += 1;
5447 break;
5448 case CVT_95_addNEONi32splatNotOperands:
5449 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5450 Operands[*(p + 1)]->setConstraint("m");
5451 NumMCOperands += 1;
5452 break;
5453 case CVT_95_addNEONi16splatOperands:
5454 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5455 Operands[*(p + 1)]->setConstraint("m");
5456 NumMCOperands += 1;
5457 break;
5458 case CVT_95_addNEONi32splatOperands:
5459 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5460 Operands[*(p + 1)]->setConstraint("m");
5461 NumMCOperands += 1;
5462 break;
5463 case CVT_95_addComplexRotationOddOperands:
5464 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5465 Operands[*(p + 1)]->setConstraint("m");
5466 NumMCOperands += 1;
5467 break;
5468 case CVT_95_addComplexRotationEvenOperands:
5469 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5470 Operands[*(p + 1)]->setConstraint("m");
5471 NumMCOperands += 1;
5472 break;
5473 case CVT_95_addVectorIndex64Operands:
5474 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5475 Operands[*(p + 1)]->setConstraint("m");
5476 NumMCOperands += 1;
5477 break;
5478 case CVT_95_addVectorIndex32Operands:
5479 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5480 Operands[*(p + 1)]->setConstraint("m");
5481 NumMCOperands += 1;
5482 break;
5483 case CVT_95_addFBits16Operands:
5484 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5485 Operands[*(p + 1)]->setConstraint("m");
5486 NumMCOperands += 1;
5487 break;
5488 case CVT_95_addFBits32Operands:
5489 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5490 Operands[*(p + 1)]->setConstraint("m");
5491 NumMCOperands += 1;
5492 break;
5493 case CVT_95_addPowerTwoOperands:
5494 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5495 Operands[*(p + 1)]->setConstraint("m");
5496 NumMCOperands += 1;
5497 break;
5498 case CVT_95_addVectorIndex16Operands:
5499 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5500 Operands[*(p + 1)]->setConstraint("m");
5501 NumMCOperands += 1;
5502 break;
5503 case CVT_95_addVectorIndex8Operands:
5504 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5505 Operands[*(p + 1)]->setConstraint("m");
5506 NumMCOperands += 1;
5507 break;
5508 case CVT_95_addVecListOperands:
5509 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5510 Operands[*(p + 1)]->setConstraint("m");
5511 NumMCOperands += 1;
5512 break;
5513 case CVT_95_addDupAlignedMemory16Operands:
5514 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5515 Operands[*(p + 1)]->setConstraint("m");
5516 NumMCOperands += 2;
5517 break;
5518 case CVT_95_addAlignedMemory64or128Operands:
5519 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5520 Operands[*(p + 1)]->setConstraint("m");
5521 NumMCOperands += 2;
5522 break;
5523 case CVT_95_addAlignedMemory64or128or256Operands:
5524 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5525 Operands[*(p + 1)]->setConstraint("m");
5526 NumMCOperands += 2;
5527 break;
5528 case CVT_95_addAlignedMemory64Operands:
5529 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5530 Operands[*(p + 1)]->setConstraint("m");
5531 NumMCOperands += 2;
5532 break;
5533 case CVT_95_addVecListIndexedOperands:
5534 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5535 Operands[*(p + 1)]->setConstraint("m");
5536 NumMCOperands += 2;
5537 break;
5538 case CVT_95_addAlignedMemory16Operands:
5539 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5540 Operands[*(p + 1)]->setConstraint("m");
5541 NumMCOperands += 2;
5542 break;
5543 case CVT_95_addDupAlignedMemory32Operands:
5544 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5545 Operands[*(p + 1)]->setConstraint("m");
5546 NumMCOperands += 2;
5547 break;
5548 case CVT_95_addAlignedMemory32Operands:
5549 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5550 Operands[*(p + 1)]->setConstraint("m");
5551 NumMCOperands += 2;
5552 break;
5553 case CVT_95_addDupAlignedMemoryNoneOperands:
5554 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5555 Operands[*(p + 1)]->setConstraint("m");
5556 NumMCOperands += 2;
5557 break;
5558 case CVT_95_addAlignedMemoryNoneOperands:
5559 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5560 Operands[*(p + 1)]->setConstraint("m");
5561 NumMCOperands += 2;
5562 break;
5563 case CVT_95_addAlignedMemoryOperands:
5564 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5565 Operands[*(p + 1)]->setConstraint("m");
5566 NumMCOperands += 2;
5567 break;
5568 case CVT_95_addDupAlignedMemory64Operands:
5569 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5570 Operands[*(p + 1)]->setConstraint("m");
5571 NumMCOperands += 2;
5572 break;
5573 case CVT_95_addMVEVecListOperands:
5574 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5575 Operands[*(p + 1)]->setConstraint("m");
5576 NumMCOperands += 1;
5577 break;
5578 case CVT_95_addMemNoOffsetT2Operands:
5579 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5580 Operands[*(p + 1)]->setConstraint("m");
5581 NumMCOperands += 1;
5582 break;
5583 case CVT_95_addMemNoOffsetT2NoSpOperands:
5584 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5585 Operands[*(p + 1)]->setConstraint("m");
5586 NumMCOperands += 1;
5587 break;
5588 case CVT_95_addDupAlignedMemory64or128Operands:
5589 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5590 Operands[*(p + 1)]->setConstraint("m");
5591 NumMCOperands += 2;
5592 break;
5593 case CVT_95_addSPRRegListOperands:
5594 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5595 Operands[*(p + 1)]->setConstraint("m");
5596 NumMCOperands += 1;
5597 break;
5598 case CVT_95_addMemImm7s4OffsetOperands:
5599 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5600 Operands[*(p + 1)]->setConstraint("m");
5601 NumMCOperands += 2;
5602 break;
5603 case CVT_95_addAddrMode5FP16Operands:
5604 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5605 Operands[*(p + 1)]->setConstraint("m");
5606 NumMCOperands += 2;
5607 break;
5608 case CVT_95_addImm7s4Operands:
5609 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5610 Operands[*(p + 1)]->setConstraint("m");
5611 NumMCOperands += 1;
5612 break;
5613 case CVT_95_addMemRegRQOffsetOperands:
5614 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5615 Operands[*(p + 1)]->setConstraint("m");
5616 NumMCOperands += 2;
5617 break;
5618 case CVT_95_addMemNoOffsetTOperands:
5619 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5620 Operands[*(p + 1)]->setConstraint("m");
5621 NumMCOperands += 1;
5622 break;
5623 case CVT_95_addImm7Shift0Operands:
5624 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5625 Operands[*(p + 1)]->setConstraint("m");
5626 NumMCOperands += 1;
5627 break;
5628 case CVT_95_addImm7Shift1Operands:
5629 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5630 Operands[*(p + 1)]->setConstraint("m");
5631 NumMCOperands += 1;
5632 break;
5633 case CVT_95_addImm7Shift2Operands:
5634 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5635 Operands[*(p + 1)]->setConstraint("m");
5636 NumMCOperands += 1;
5637 break;
5638 case CVT_95_addNEONi32vmovOperands:
5639 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5640 Operands[*(p + 1)]->setConstraint("m");
5641 NumMCOperands += 1;
5642 break;
5643 case CVT_95_addNEONvmovi8ReplicateOperands:
5644 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5645 Operands[*(p + 1)]->setConstraint("m");
5646 NumMCOperands += 1;
5647 break;
5648 case CVT_95_addNEONvmovi16ReplicateOperands:
5649 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5650 Operands[*(p + 1)]->setConstraint("m");
5651 NumMCOperands += 1;
5652 break;
5653 case CVT_95_addNEONi32vmovNegOperands:
5654 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5655 Operands[*(p + 1)]->setConstraint("m");
5656 NumMCOperands += 1;
5657 break;
5658 case CVT_95_addNEONvmovi32ReplicateOperands:
5659 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5660 Operands[*(p + 1)]->setConstraint("m");
5661 NumMCOperands += 1;
5662 break;
5663 case CVT_95_addNEONi64splatOperands:
5664 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5665 Operands[*(p + 1)]->setConstraint("m");
5666 NumMCOperands += 1;
5667 break;
5668 case CVT_95_addNEONi8splatOperands:
5669 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5670 Operands[*(p + 1)]->setConstraint("m");
5671 NumMCOperands += 1;
5672 break;
5673 case CVT_95_addMVEVectorIndexOperands:
5674 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5675 Operands[*(p + 1)]->setConstraint("m");
5676 NumMCOperands += 1;
5677 break;
5678 case CVT_95_addMVEPairVectorIndexOperands:
5679 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5680 Operands[*(p + 1)]->setConstraint("m");
5681 NumMCOperands += 1;
5682 break;
5683 case CVT_95_addNEONinvi8ReplicateOperands:
5684 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5685 Operands[*(p + 1)]->setConstraint("m");
5686 NumMCOperands += 1;
5687 break;
5688 case CVT_95_addFPDRegListWithVPROperands:
5689 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5690 Operands[*(p + 1)]->setConstraint("m");
5691 NumMCOperands += 1;
5692 break;
5693 case CVT_95_addFPSRegListWithVPROperands:
5694 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5695 Operands[*(p + 1)]->setConstraint("m");
5696 NumMCOperands += 1;
5697 break;
5698 case CVT_imm_95_2:
5699 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5700 Operands[*(p + 1)]->setConstraint("");
5701 ++NumMCOperands;
5702 break;
5703 case CVT_imm_95_3:
5704 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
5705 Operands[*(p + 1)]->setConstraint("");
5706 ++NumMCOperands;
5707 break;
5708 }
5709 }
5710}
5711
5712namespace {
5713
5714/// MatchClassKind - The kinds of classes which participate in
5715/// instruction matching.
5716enum MatchClassKind {
5717 InvalidMatchClass = 0,
5718 OptionalMatchClass = 1,
5719 MCK__DOT_d, // '.d'
5720 MCK__DOT_f, // '.f'
5721 MCK__DOT_s16, // '.s16'
5722 MCK__DOT_s32, // '.s32'
5723 MCK__DOT_s64, // '.s64'
5724 MCK__DOT_s8, // '.s8'
5725 MCK__DOT_u16, // '.u16'
5726 MCK__DOT_u32, // '.u32'
5727 MCK__DOT_u64, // '.u64'
5728 MCK__DOT_u8, // '.u8'
5729 MCK__DOT_f32, // '.f32'
5730 MCK__DOT_f64, // '.f64'
5731 MCK__DOT_i16, // '.i16'
5732 MCK__DOT_i32, // '.i32'
5733 MCK__DOT_i64, // '.i64'
5734 MCK__DOT_i8, // '.i8'
5735 MCK__DOT_p16, // '.p16'
5736 MCK__DOT_p8, // '.p8'
5737 MCK__EXCLAIM_, // '!'
5738 MCK__HASH_0, // '#0'
5739 MCK__HASH_16, // '#16'
5740 MCK__HASH_8, // '#8'
5741 MCK__DOT_16, // '.16'
5742 MCK__DOT_32, // '.32'
5743 MCK__DOT_64, // '.64'
5744 MCK__DOT_8, // '.8'
5745 MCK__DOT_bf16, // '.bf16'
5746 MCK__DOT_f16, // '.f16'
5747 MCK__DOT_p64, // '.p64'
5748 MCK__DOT_w, // '.w'
5749 MCK__91_, // '['
5750 MCK__93_, // ']'
5751 MCK__94_, // '^'
5752 MCK__123_, // '{'
5753 MCK__125_, // '}'
5754 MCK_LAST_TOKEN = MCK__125_,
5755 MCK_Reg108, // derived register class
5756 MCK_Reg92, // derived register class
5757 MCK_APSR, // register class 'APSR'
5758 MCK_APSR_NZCV, // register class 'APSR_NZCV'
5759 MCK_CCR, // register class 'CCR,CPSR'
5760 MCK_FPCXTRegs, // register class 'FPCXTRegs,FPCXTNS'
5761 MCK_FPCXTS, // register class 'FPCXTS'
5762 MCK_FPEXC, // register class 'FPEXC'
5763 MCK_FPINST, // register class 'FPINST'
5764 MCK_FPINST2, // register class 'FPINST2'
5765 MCK_FPSCR, // register class 'FPSCR'
5766 MCK_FPSCR_NZCVQC, // register class 'FPSCR_NZCVQC'
5767 MCK_FPSID, // register class 'FPSID'
5768 MCK_GPRlr, // register class 'GPRlr,LR'
5769 MCK_GPRsp, // register class 'GPRsp,SP'
5770 MCK_MVFR0, // register class 'MVFR0'
5771 MCK_MVFR1, // register class 'MVFR1'
5772 MCK_MVFR2, // register class 'MVFR2'
5773 MCK_P0, // register class 'P0'
5774 MCK_PC, // register class 'PC'
5775 MCK_R12, // register class 'R12'
5776 MCK_SPSR, // register class 'SPSR'
5777 MCK_VCCR, // register class 'VCCR,VPR'
5778 MCK_cl_FPSCR_NZCV, // register class 'cl_FPSCR_NZCV'
5779 MCK_Reg133, // derived register class
5780 MCK_Reg106, // derived register class
5781 MCK_Reg101, // derived register class
5782 MCK_Reg93, // derived register class
5783 MCK_Reg35, // derived register class
5784 MCK_Reg33, // derived register class
5785 MCK_Reg22, // derived register class
5786 MCK_Reg17, // derived register class
5787 MCK_FP_STATUS_REGS, // register class 'FP_STATUS_REGS'
5788 MCK_Reg134, // derived register class
5789 MCK_Reg121, // derived register class
5790 MCK_Reg116, // derived register class
5791 MCK_Reg107, // derived register class
5792 MCK_Reg105, // derived register class
5793 MCK_Reg94, // derived register class
5794 MCK_Reg78, // derived register class
5795 MCK_Reg21, // derived register class
5796 MCK_Reg135, // derived register class
5797 MCK_Reg126, // derived register class
5798 MCK_Reg122, // derived register class
5799 MCK_Reg117, // derived register class
5800 MCK_Reg102, // derived register class
5801 MCK_Reg95, // derived register class
5802 MCK_Reg79, // derived register class
5803 MCK_Reg34, // derived register class
5804 MCK_Reg25, // derived register class
5805 MCK_Reg23, // derived register class
5806 MCK_Reg18, // derived register class
5807 MCK_QPR_8, // register class 'QPR_8'
5808 MCK_tcGPRnotr12, // register class 'tcGPRnotr12'
5809 MCK_Reg90, // derived register class
5810 MCK_Reg32, // derived register class
5811 MCK_Reg30, // derived register class
5812 MCK_MQQQQPR, // register class 'MQQQQPR'
5813 MCK_tcGPR, // register class 'tcGPR'
5814 MCK_Reg136, // derived register class
5815 MCK_Reg127, // derived register class
5816 MCK_Reg109, // derived register class
5817 MCK_Reg97, // derived register class
5818 MCK_Reg91, // derived register class
5819 MCK_Reg73, // derived register class
5820 MCK_Reg31, // derived register class
5821 MCK_Reg28, // derived register class
5822 MCK_Reg19, // derived register class
5823 MCK_GPRPairnosp, // register class 'GPRPairnosp'
5824 MCK_tGPROdd, // register class 'tGPROdd'
5825 MCK_Reg137, // derived register class
5826 MCK_Reg123, // derived register class
5827 MCK_Reg118, // derived register class
5828 MCK_Reg110, // derived register class
5829 MCK_Reg98, // derived register class
5830 MCK_Reg88, // derived register class
5831 MCK_Reg52, // derived register class
5832 MCK_Reg29, // derived register class
5833 MCK_Reg26, // derived register class
5834 MCK_GPRPair, // register class 'GPRPair'
5835 MCK_MQQPR, // register class 'MQQPR'
5836 MCK_Reg138, // derived register class
5837 MCK_Reg128, // derived register class
5838 MCK_Reg124, // derived register class
5839 MCK_Reg119, // derived register class
5840 MCK_Reg111, // derived register class
5841 MCK_Reg99, // derived register class
5842 MCK_Reg89, // derived register class
5843 MCK_Reg81, // derived register class
5844 MCK_Reg74, // derived register class
5845 MCK_Reg53, // derived register class
5846 MCK_DPR_8, // register class 'DPR_8'
5847 MCK_MQPR, // register class 'MQPR,QPR_VFP2'
5848 MCK_hGPR, // register class 'hGPR'
5849 MCK_tGPR, // register class 'tGPR'
5850 MCK_tGPREven, // register class 'tGPREven'
5851 MCK_tGPRwithpc, // register class 'tGPRwithpc'
5852 MCK_Reg129, // derived register class
5853 MCK_Reg2, // derived register class
5854 MCK_Reg86, // derived register class
5855 MCK_Reg14, // derived register class
5856 MCK_Reg12, // derived register class
5857 MCK_QQQQPR, // register class 'QQQQPR'
5858 MCK_Reg139, // derived register class
5859 MCK_Reg130, // derived register class
5860 MCK_Reg112, // derived register class
5861 MCK_Reg87, // derived register class
5862 MCK_Reg75, // derived register class
5863 MCK_GPRnoip, // register class 'GPRnoip'
5864 MCK_rGPR, // register class 'rGPR'
5865 MCK_Reg125, // derived register class
5866 MCK_Reg120, // derived register class
5867 MCK_Reg113, // derived register class
5868 MCK_Reg84, // derived register class
5869 MCK_Reg50, // derived register class
5870 MCK_GPRnopc, // register class 'GPRnopc'
5871 MCK_GPRnosp, // register class 'GPRnosp'
5872 MCK_GPRwithAPSR_NZCVnosp, // register class 'GPRwithAPSR_NZCVnosp'
5873 MCK_GPRwithAPSRnosp, // register class 'GPRwithAPSRnosp'
5874 MCK_GPRwithZRnosp, // register class 'GPRwithZRnosp'
5875 MCK_QQPR, // register class 'QQPR'
5876 MCK_Reg131, // derived register class
5877 MCK_Reg114, // derived register class
5878 MCK_Reg85, // derived register class
5879 MCK_Reg76, // derived register class
5880 MCK_Reg51, // derived register class
5881 MCK_DPR_VFP2, // register class 'DPR_VFP2'
5882 MCK_GPR, // register class 'GPR'
5883 MCK_GPRwithAPSR, // register class 'GPRwithAPSR'
5884 MCK_GPRwithZR, // register class 'GPRwithZR'
5885 MCK_QPR, // register class 'QPR'
5886 MCK_SPR_8, // register class 'SPR_8'
5887 MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc'
5888 MCK_DQuad, // register class 'DQuad'
5889 MCK_DPairSpc, // register class 'DPairSpc'
5890 MCK_DTriple, // register class 'DTriple'
5891 MCK_DPair, // register class 'DPair'
5892 MCK_DPR, // register class 'DPR'
5893 MCK_HPR, // register class 'HPR,SPR'
5894 MCK_FPWithVPR, // register class 'FPWithVPR'
5895 MCK_LAST_REGISTER = MCK_FPWithVPR,
5896 MCK_RegByHwMode_arm_ptr_rc, // register class by hwmode
5897 MCK_LAST_REGCLASS_BY_HWMODE = MCK_RegByHwMode_arm_ptr_rc,
5898 MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand'
5899 MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand'
5900 MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget'
5901 MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand'
5902 MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand'
5903 MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand'
5904 MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand'
5905 MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand'
5906 MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand'
5907 MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand'
5908 MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand'
5909 MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand'
5910 MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand'
5911 MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand'
5912 MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand'
5913 MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand'
5914 MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand'
5915 MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand'
5916 MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand'
5917 MCK_BankedReg, // user defined class 'BankedRegOperand'
5918 MCK_Bitfield, // user defined class 'BitfieldAsmOperand'
5919 MCK_CCOut, // user defined class 'CCOutOperand'
5920 MCK_CondCode, // user defined class 'CondCodeOperand'
5921 MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand'
5922 MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand'
5923 MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand'
5924 MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand'
5925 MCK_FPDRegListWithVPR, // user defined class 'FPDRegListWithVPRAsmOperand'
5926 MCK_FPImm, // user defined class 'FPImmOperand'
5927 MCK_FPSRegListWithVPR, // user defined class 'FPSRegListWithVPRAsmOperand'
5928 MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand'
5929 MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand'
5930 MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand'
5931 MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand'
5932 MCK_Imm0_255Expr, // user defined class 'Imm0_255ExprAsmOperand'
5933 MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand'
5934 MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand'
5935 MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand'
5936 MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand'
5937 MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand'
5938 MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand'
5939 MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand'
5940 MCK_Imm16, // user defined class 'Imm16AsmOperand'
5941 MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand'
5942 MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand'
5943 MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand'
5944 MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand'
5945 MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand'
5946 MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand'
5947 MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand'
5948 MCK_Imm32, // user defined class 'Imm32AsmOperand'
5949 MCK_Imm8, // user defined class 'Imm8AsmOperand'
5950 MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand'
5951 MCK_Imm, // user defined class 'ImmAsmOperand'
5952 MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand'
5953 MCK_MSRMask, // user defined class 'MSRMaskOperand'
5954 MCK_MVEShiftImm1_15, // user defined class 'MVEShiftImm1_15AsmOperand'
5955 MCK_MVEShiftImm1_7, // user defined class 'MVEShiftImm1_7AsmOperand'
5956 MCK_VIDUP_imm, // user defined class 'MVE_VIDUP_imm_asmoperand'
5957 MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand'
5958 MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand'
5959 MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand'
5960 MCK_MemImm7Shift0Offset, // user defined class 'MemImm7Shift0OffsetAsmOperand'
5961 MCK_MemImm7Shift0OffsetWB, // user defined class 'MemImm7Shift0OffsetWBAsmOperand'
5962 MCK_MemImm7Shift1Offset, // user defined class 'MemImm7Shift1OffsetAsmOperand'
5963 MCK_MemImm7Shift1OffsetWB, // user defined class 'MemImm7Shift1OffsetWBAsmOperand'
5964 MCK_MemImm7Shift2Offset, // user defined class 'MemImm7Shift2OffsetAsmOperand'
5965 MCK_MemImm7Shift2OffsetWB, // user defined class 'MemImm7Shift2OffsetWBAsmOperand'
5966 MCK_MemImm7s4Offset, // user defined class 'MemImm7s4OffsetAsmOperand'
5967 MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand'
5968 MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand'
5969 MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand'
5970 MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand'
5971 MCK_MemNoOffsetT2, // user defined class 'MemNoOffsetT2AsmOperand'
5972 MCK_MemNoOffsetT2NoSp, // user defined class 'MemNoOffsetT2NoSpAsmOperand'
5973 MCK_MemNoOffsetT, // user defined class 'MemNoOffsetTAsmOperand'
5974 MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand'
5975 MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand'
5976 MCK_MemRegQS2Offset, // user defined class 'MemRegQS2OffsetAsmOperand'
5977 MCK_MemRegQS3Offset, // user defined class 'MemRegQS3OffsetAsmOperand'
5978 MCK_MemRegRQS0Offset, // user defined class 'MemRegRQS0OffsetAsmOperand'
5979 MCK_MemRegRQS1Offset, // user defined class 'MemRegRQS1OffsetAsmOperand'
5980 MCK_MemRegRQS2Offset, // user defined class 'MemRegRQS2OffsetAsmOperand'
5981 MCK_MemRegRQS3Offset, // user defined class 'MemRegRQS3OffsetAsmOperand'
5982 MCK_ModImm, // user defined class 'ModImmAsmOperand'
5983 MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand'
5984 MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand'
5985 MCK_MveSaturate, // user defined class 'MveSaturateOperand'
5986 MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand'
5987 MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand'
5988 MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand'
5989 MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand'
5990 MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand'
5991 MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand'
5992 MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand'
5993 MCK_RegList, // user defined class 'RegListAsmOperand'
5994 MCK_RegListWithAPSR, // user defined class 'RegListWithAPSRAsmOperand'
5995 MCK_RotImm, // user defined class 'RotImmAsmOperand'
5996 MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand'
5997 MCK_SetEndImm, // user defined class 'SetEndAsmOperand'
5998 MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand'
5999 MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand'
6000 MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand'
6001 MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget'
6002 MCK_ThumbMemPC, // user defined class 'ThumbMemPC'
6003 MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand'
6004 MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand'
6005 MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand'
6006 MCK_TraceSyncBarrierOpt, // user defined class 'TraceSyncBarrierOptOperand'
6007 MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2'
6008 MCK_VPTPredN, // user defined class 'VPTPredNOperand'
6009 MCK_VPTPredR, // user defined class 'VPTPredROperand'
6010 MCK_VecListTwoMQ, // user defined class 'VecList2QAsmOperand'
6011 MCK_VecListFourMQ, // user defined class 'VecList4QAsmOperand'
6012 MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand'
6013 MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand'
6014 MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand'
6015 MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand'
6016 MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand'
6017 MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand'
6018 MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand'
6019 MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand'
6020 MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand'
6021 MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand'
6022 MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand'
6023 MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand'
6024 MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand'
6025 MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand'
6026 MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand'
6027 MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand'
6028 MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand'
6029 MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand'
6030 MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand'
6031 MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand'
6032 MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand'
6033 MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand'
6034 MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand'
6035 MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand'
6036 MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand'
6037 MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand'
6038 MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand'
6039 MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand'
6040 MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand'
6041 MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand'
6042 MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand'
6043 MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand'
6044 MCK_VectorIndex16, // user defined class 'VectorIndex16Operand'
6045 MCK_VectorIndex32, // user defined class 'VectorIndex32Operand'
6046 MCK_VectorIndex64, // user defined class 'VectorIndex64Operand'
6047 MCK_VectorIndex8, // user defined class 'VectorIndex8Operand'
6048 MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand'
6049 MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand'
6050 MCK_MVEPairVectorIndex0, // user defined class 'anonymous_14431'
6051 MCK_MVEPairVectorIndex2, // user defined class 'anonymous_14432'
6052 MCK_ComplexRotationEven, // user defined class 'anonymous_14441'
6053 MCK_ComplexRotationOdd, // user defined class 'anonymous_14442'
6054 MCK_NEONi16vmovi8Replicate, // user defined class 'anonymous_15824'
6055 MCK_NEONi16invi8Replicate, // user defined class 'anonymous_15826'
6056 MCK_NEONi32vmovi8Replicate, // user defined class 'anonymous_15829'
6057 MCK_NEONi32invi8Replicate, // user defined class 'anonymous_15831'
6058 MCK_NEONi64vmovi8Replicate, // user defined class 'anonymous_15838'
6059 MCK_NEONi64invi8Replicate, // user defined class 'anonymous_15840'
6060 MCK_NEONi32vmovi16Replicate, // user defined class 'anonymous_15851'
6061 MCK_NEONi64vmovi16Replicate, // user defined class 'anonymous_15854'
6062 MCK_NEONi64vmovi32Replicate, // user defined class 'anonymous_15861'
6063 MCK_MVEVectorIndex4, // user defined class 'anonymous_17138'
6064 MCK_MVEVectorIndex8, // user defined class 'anonymous_17140'
6065 MCK_MVEVectorIndex16, // user defined class 'anonymous_17142'
6066 MCK_MVEVcvtImm32, // user defined class 'anonymous_17908'
6067 MCK_MVEVcvtImm16, // user defined class 'anonymous_17910'
6068 MCK_TMemImm7Shift2Offset, // user defined class 'anonymous_18163'
6069 MCK_TMemImm7Shift0Offset, // user defined class 'anonymous_18914'
6070 MCK_TMemImm7Shift1Offset, // user defined class 'anonymous_18917'
6071 MCK_Imm3b, // user defined class 'anonymous_19449'
6072 MCK_Imm4b, // user defined class 'anonymous_19450'
6073 MCK_Imm6b, // user defined class 'anonymous_19451'
6074 MCK_Imm7b, // user defined class 'anonymous_19452'
6075 MCK_Imm9b, // user defined class 'anonymous_19453'
6076 MCK_Imm11b, // user defined class 'anonymous_19454'
6077 MCK_Imm12b, // user defined class 'anonymous_19455'
6078 MCK_Imm13b, // user defined class 'anonymous_19456'
6079 MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand'
6080 MCK_FBits16, // user defined class 'fbits16_asm_operand'
6081 MCK_FBits32, // user defined class 'fbits32_asm_operand'
6082 MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand'
6083 MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand'
6084 MCK_ITMask, // user defined class 'it_mask_asmoperand'
6085 MCK_ITCondCode, // user defined class 'it_pred_asmoperand'
6086 MCK_LELabel, // user defined class 'lelabel_u11_asmoperand'
6087 MCK_MVELongShift, // user defined class 'mve_shift_imm'
6088 MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand'
6089 MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand'
6090 MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand'
6091 MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand'
6092 MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand'
6093 MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand'
6094 MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand'
6095 MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand'
6096 MCK_CondCodeNoAL, // user defined class 'pred_noal_asmoperand'
6097 MCK_CondCodeNoALInv, // user defined class 'pred_noal_inv_asmoperand'
6098 MCK_CondCodeRestrictedFP, // user defined class 'pred_restricted_fp_asmoperand'
6099 MCK_CondCodeRestrictedI, // user defined class 'pred_restricted_i_asmoperand'
6100 MCK_CondCodeRestrictedS, // user defined class 'pred_restricted_s_asmoperand'
6101 MCK_CondCodeRestrictedU, // user defined class 'pred_restricted_u_asmoperand'
6102 MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand'
6103 MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand'
6104 MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand'
6105 MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand'
6106 MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand'
6107 MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand'
6108 MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand'
6109 MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand'
6110 MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand'
6111 MCK_Imm7s4, // user defined class 't2am_imm7s4_offset_asmoperand'
6112 MCK_Imm7Shift0, // user defined class 't2am_imm7shift0OffsetAsmOperand'
6113 MCK_Imm7Shift1, // user defined class 't2am_imm7shift1OffsetAsmOperand'
6114 MCK_Imm7Shift2, // user defined class 't2am_imm7shift2OffsetAsmOperand'
6115 MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand'
6116 MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand'
6117 MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand'
6118 MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand'
6119 MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand'
6120 MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand'
6121 MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand'
6122 MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand'
6123 MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand'
6124 MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand'
6125 MCK_WLSLabel, // user defined class 'wlslabel_u11_asmoperand'
6126 NumMatchClassKinds
6127};
6128
6129} // end anonymous namespace
6130
6131static const char *getMatchKindDiag(ARMAsmParser::ARMMatchResultTy MatchResult) {
6132 switch (MatchResult) {
6133 case ARMAsmParser::Match_GPRsp:
6134 return "operand must be a register sp";
6135 case ARMAsmParser::Match_QPR_8:
6136 return "operand must be a register in range [q0, q3]";
6137 case ARMAsmParser::Match_tGPROdd:
6138 return "operand must be an odd-numbered register in range [r1,r11]";
6139 case ARMAsmParser::Match_DPR_8:
6140 return "operand must be a register in range [d0, d7]";
6141 case ARMAsmParser::Match_QPR_VFP2:
6142 return "operand must be a register in range [q0, q7]";
6143 case ARMAsmParser::Match_hGPR:
6144 return "operand must be a register in range [r8, r15]";
6145 case ARMAsmParser::Match_tGPR:
6146 return "operand must be a register in range [r0, r7]";
6147 case ARMAsmParser::Match_tGPREven:
6148 return "operand must be an even-numbered register";
6149 case ARMAsmParser::Match_GPRnoip:
6150 return "operand must be a register in range [r0, r14]";
6151 case ARMAsmParser::Match_GPRnopc:
6152 return "operand must be a register in range [r0, r14]";
6153 case ARMAsmParser::Match_GPRnosp:
6154 return "operand must be a register in range [r0, r12] or LR or PC";
6155 case ARMAsmParser::Match_GPRwithAPSR_NZCVnosp:
6156 return "operand must be a register in the range [r0, r12], r14 or apsr_nzcv";
6157 case ARMAsmParser::Match_GPRwithZRnosp:
6158 return "operand must be a register in range [r0, r12] or r14 or zr";
6159 case ARMAsmParser::Match_DPR_VFP2:
6160 return "operand must be a register in range [d0, d15]";
6161 case ARMAsmParser::Match_GPR:
6162 return "operand must be a register in range [r0, r15]";
6163 case ARMAsmParser::Match_GPRwithAPSR:
6164 return "operand must be a register in range [r0, r14] or apsr_nzcv";
6165 case ARMAsmParser::Match_GPRwithZR:
6166 return "operand must be a register in range [r0, r14] or zr";
6167 case ARMAsmParser::Match_QPR:
6168 return "operand must be a register in range [q0, q15]";
6169 case ARMAsmParser::Match_SPR_8:
6170 return "operand must be a register in range [s0, s15]";
6171 case ARMAsmParser::Match_SPR:
6172 return "operand must be a register in range [s0, s31]";
6173 case ARMAsmParser::Match_AlignedMemory16:
6174 return "alignment must be 16 or omitted";
6175 case ARMAsmParser::Match_AlignedMemory32:
6176 return "alignment must be 32 or omitted";
6177 case ARMAsmParser::Match_AlignedMemory64:
6178 return "alignment must be 64 or omitted";
6179 case ARMAsmParser::Match_AlignedMemory64or128:
6180 return "alignment must be 64, 128 or omitted";
6181 case ARMAsmParser::Match_AlignedMemory64or128or256:
6182 return "alignment must be 64, 128, 256 or omitted";
6183 case ARMAsmParser::Match_AlignedMemoryNone:
6184 return "alignment must be omitted";
6185 case ARMAsmParser::Match_DupAlignedMemory16:
6186 return "alignment must be 16 or omitted";
6187 case ARMAsmParser::Match_DupAlignedMemory32:
6188 return "alignment must be 32 or omitted";
6189 case ARMAsmParser::Match_DupAlignedMemory64:
6190 return "alignment must be 64 or omitted";
6191 case ARMAsmParser::Match_DupAlignedMemory64or128:
6192 return "alignment must be 64, 128 or omitted";
6193 case ARMAsmParser::Match_DupAlignedMemoryNone:
6194 return "alignment must be omitted";
6195 case ARMAsmParser::Match_Imm0_15:
6196 return "operand must be an immediate in the range [0,15]";
6197 case ARMAsmParser::Match_Imm0_1:
6198 return "operand must be an immediate in the range [0,1]";
6199 case ARMAsmParser::Match_Imm0_239:
6200 return "operand must be an immediate in the range [0,239]";
6201 case ARMAsmParser::Match_Imm0_255:
6202 return "operand must be an immediate in the range [0,255]";
6203 case ARMAsmParser::Match_Imm0_255Expr:
6204 return "operand must be an immediate in the range [0,255] or a relocatable expression";
6205 case ARMAsmParser::Match_Imm0_31:
6206 return "operand must be an immediate in the range [0,31]";
6207 case ARMAsmParser::Match_Imm0_32:
6208 return "operand must be an immediate in the range [0,32]";
6209 case ARMAsmParser::Match_Imm0_3:
6210 return "operand must be an immediate in the range [0,3]";
6211 case ARMAsmParser::Match_Imm0_63:
6212 return "operand must be an immediate in the range [0,63]";
6213 case ARMAsmParser::Match_Imm0_65535:
6214 return "operand must be an immediate in the range [0,65535]";
6215 case ARMAsmParser::Match_Imm0_65535Expr:
6216 return "operand must be an immediate in the range [0,0xffff] or a relocatable expression";
6217 case ARMAsmParser::Match_Imm0_7:
6218 return "operand must be an immediate in the range [0,7]";
6219 case ARMAsmParser::Match_Imm16:
6220 return "operand must be an immediate in the range [16,16]";
6221 case ARMAsmParser::Match_Imm1_15:
6222 return "operand must be an immediate in the range [1,15]";
6223 case ARMAsmParser::Match_ImmRange1_16:
6224 return "operand must be an immediate in the range [1,16]";
6225 case ARMAsmParser::Match_Imm1_31:
6226 return "operand must be an immediate in the range [1,31]";
6227 case ARMAsmParser::Match_ImmRange1_32:
6228 return "operand must be an immediate in the range [1,32]";
6229 case ARMAsmParser::Match_Imm1_7:
6230 return "operand must be an immediate in the range [1,7]";
6231 case ARMAsmParser::Match_Imm24bit:
6232 return "operand must be an immediate in the range [0,0xffffff]";
6233 case ARMAsmParser::Match_Imm256_65535Expr:
6234 return "operand must be an immediate in the range [256,65535]";
6235 case ARMAsmParser::Match_Imm32:
6236 return "operand must be an immediate in the range [32,32]";
6237 case ARMAsmParser::Match_Imm8:
6238 return "operand must be an immediate in the range [8,8]";
6239 case ARMAsmParser::Match_Imm8_255:
6240 return "operand must be an immediate in the range [8,255]";
6241 case ARMAsmParser::Match_MVEShiftImm1_15:
6242 return "operand must be an immediate in the range [1,16]";
6243 case ARMAsmParser::Match_MVEShiftImm1_7:
6244 return "operand must be an immediate in the range [1,8]";
6245 case ARMAsmParser::Match_VIDUP_imm:
6246 return "vector increment immediate must be 1, 2, 4 or 8";
6247 case ARMAsmParser::Match_MveSaturate:
6248 return "saturate operand must be 48 or 64";
6249 case ARMAsmParser::Match_PKHLSLImm:
6250 return "operand must be an immediate in the range [0,31]";
6251 case ARMAsmParser::Match_SPRRegList:
6252 return "operand must be a list of registers in range [s0, s31]";
6253 case ARMAsmParser::Match_SetEndImm:
6254 return "operand must be an immediate in the range [0,1]";
6255 case ARMAsmParser::Match_ImmThumbSR:
6256 return "operand must be an immediate in the range [1,32]";
6257 case ARMAsmParser::Match_VecListTwoMQ:
6258 return "operand must be a list of two consecutive q-registers in range [q0,q7]";
6259 case ARMAsmParser::Match_VecListFourMQ:
6260 return "operand must be a list of four consecutive q-registers in range [q0,q7]";
6261 case ARMAsmParser::Match_ComplexRotationEven:
6262 return "complex rotation must be 0, 90, 180 or 270";
6263 case ARMAsmParser::Match_ComplexRotationOdd:
6264 return "complex rotation must be 90 or 270";
6265 case ARMAsmParser::Match_MVEVcvtImm32:
6266 return "MVE fixed-point immediate operand must be between 1 and 32";
6267 case ARMAsmParser::Match_MVEVcvtImm16:
6268 return "MVE fixed-point immediate operand must be between 1 and 16";
6269 case ARMAsmParser::Match_Imm3b:
6270 return "operand must be an immediate in the range [0,7]";
6271 case ARMAsmParser::Match_Imm4b:
6272 return "operand must be an immediate in the range [0,15]";
6273 case ARMAsmParser::Match_Imm6b:
6274 return "operand must be an immediate in the range [0,63]";
6275 case ARMAsmParser::Match_Imm7b:
6276 return "operand must be an immediate in the range [0,127]";
6277 case ARMAsmParser::Match_Imm9b:
6278 return "operand must be an immediate in the range [0,511]";
6279 case ARMAsmParser::Match_Imm11b:
6280 return "operand must be an immediate in the range [0,2047]";
6281 case ARMAsmParser::Match_Imm12b:
6282 return "operand must be an immediate in the range [0,4095]";
6283 case ARMAsmParser::Match_Imm13b:
6284 return "operand must be an immediate in the range [0,8191]";
6285 case ARMAsmParser::Match_Imm0_4095:
6286 return "operand must be an immediate in the range [0,4095]";
6287 case ARMAsmParser::Match_LELabel:
6288 return "loop start is out of range or not a negative multiple of 2";
6289 case ARMAsmParser::Match_MVELongShift:
6290 return "operand must be an immediate in the range [1,32]";
6291 case ARMAsmParser::Match_CondCodeRestrictedFP:
6292 return "condition code for floating-point comparison must be EQ, NE, LT, GT, LE or GE";
6293 case ARMAsmParser::Match_CondCodeRestrictedI:
6294 return "condition code for sign-independent integer comparison must be EQ or NE";
6295 case ARMAsmParser::Match_CondCodeRestrictedS:
6296 return "condition code for signed integer comparison must be EQ, NE, LT, GT, LE or GE";
6297 case ARMAsmParser::Match_CondCodeRestrictedU:
6298 return "condition code for unsigned integer comparison must be EQ, NE, HS or HI";
6299 case ARMAsmParser::Match_ShrImm16:
6300 return "operand must be an immediate in the range [1,16]";
6301 case ARMAsmParser::Match_ShrImm32:
6302 return "operand must be an immediate in the range [1,32]";
6303 case ARMAsmParser::Match_ShrImm64:
6304 return "operand must be an immediate in the range [1,64]";
6305 case ARMAsmParser::Match_ShrImm8:
6306 return "operand must be an immediate in the range [1,8]";
6307 case ARMAsmParser::Match_WLSLabel:
6308 return "loop end is out of range or not a positive multiple of 2";
6309 default:
6310 return nullptr;
6311 }
6312}
6313
6314static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
6315 switch (RegisterClass) {
6316 case MCK_GPRsp:
6317 return ARMAsmParser::Match_GPRsp;
6318 case MCK_QPR_8:
6319 return ARMAsmParser::Match_QPR_8;
6320 case MCK_tGPROdd:
6321 return ARMAsmParser::Match_tGPROdd;
6322 case MCK_DPR_8:
6323 return ARMAsmParser::Match_DPR_8;
6324 case MCK_MQPR:
6325 return ARMAsmParser::Match_QPR_VFP2;
6326 case MCK_hGPR:
6327 return ARMAsmParser::Match_hGPR;
6328 case MCK_tGPR:
6329 return ARMAsmParser::Match_tGPR;
6330 case MCK_tGPREven:
6331 return ARMAsmParser::Match_tGPREven;
6332 case MCK_GPRnoip:
6333 return ARMAsmParser::Match_GPRnoip;
6334 case MCK_rGPR:
6335 return ARMAsmParser::Match_rGPR;
6336 case MCK_GPRnopc:
6337 return ARMAsmParser::Match_GPRnopc;
6338 case MCK_GPRnosp:
6339 return ARMAsmParser::Match_GPRnosp;
6340 case MCK_GPRwithAPSR_NZCVnosp:
6341 return ARMAsmParser::Match_GPRwithAPSR_NZCVnosp;
6342 case MCK_GPRwithZRnosp:
6343 return ARMAsmParser::Match_GPRwithZRnosp;
6344 case MCK_DPR_VFP2:
6345 return ARMAsmParser::Match_DPR_VFP2;
6346 case MCK_GPR:
6347 return ARMAsmParser::Match_GPR;
6348 case MCK_GPRwithAPSR:
6349 return ARMAsmParser::Match_GPRwithAPSR;
6350 case MCK_GPRwithZR:
6351 return ARMAsmParser::Match_GPRwithZR;
6352 case MCK_QPR:
6353 return ARMAsmParser::Match_QPR;
6354 case MCK_SPR_8:
6355 return ARMAsmParser::Match_SPR_8;
6356 case MCK_DPR:
6357 return ARMAsmParser::Match_DPR;
6358 case MCK_HPR:
6359 return ARMAsmParser::Match_SPR;
6360 default:
6361 return MCTargetAsmParser::Match_InvalidOperand;
6362 }
6363}
6364
6365[[maybe_unused]] static const MCRegisterClass *getRegClassFromMatchKind(MatchClassKind Kind) {
6366 switch (Kind) {
6367 case MCK_CCR:
6368 return &getARMMCRegisterClass(ARM::CCRRegClassID);
6369 case MCK_FPCXTRegs:
6370 return &getARMMCRegisterClass(ARM::FPCXTRegsRegClassID);
6371 case MCK_GPRlr:
6372 return &getARMMCRegisterClass(ARM::GPRlrRegClassID);
6373 case MCK_GPRsp:
6374 return &getARMMCRegisterClass(ARM::GPRspRegClassID);
6375 case MCK_VCCR:
6376 return &getARMMCRegisterClass(ARM::VCCRRegClassID);
6377 case MCK_cl_FPSCR_NZCV:
6378 return &getARMMCRegisterClass(ARM::cl_FPSCR_NZCVRegClassID);
6379 case MCK_FP_STATUS_REGS:
6380 return &getARMMCRegisterClass(ARM::FP_STATUS_REGSRegClassID);
6381 case MCK_QPR_8:
6382 return &getARMMCRegisterClass(ARM::QPR_8RegClassID);
6383 case MCK_tcGPRnotr12:
6384 return &getARMMCRegisterClass(ARM::tcGPRnotr12RegClassID);
6385 case MCK_MQQQQPR:
6386 return &getARMMCRegisterClass(ARM::MQQQQPRRegClassID);
6387 case MCK_tcGPR:
6388 return &getARMMCRegisterClass(ARM::tcGPRRegClassID);
6389 case MCK_GPRPairnosp:
6390 return &getARMMCRegisterClass(ARM::GPRPairnospRegClassID);
6391 case MCK_tGPROdd:
6392 return &getARMMCRegisterClass(ARM::tGPROddRegClassID);
6393 case MCK_GPRPair:
6394 return &getARMMCRegisterClass(ARM::GPRPairRegClassID);
6395 case MCK_MQQPR:
6396 return &getARMMCRegisterClass(ARM::MQQPRRegClassID);
6397 case MCK_DPR_8:
6398 return &getARMMCRegisterClass(ARM::DPR_8RegClassID);
6399 case MCK_MQPR:
6400 return &getARMMCRegisterClass(ARM::MQPRRegClassID);
6401 case MCK_hGPR:
6402 return &getARMMCRegisterClass(ARM::hGPRRegClassID);
6403 case MCK_tGPR:
6404 return &getARMMCRegisterClass(ARM::tGPRRegClassID);
6405 case MCK_tGPREven:
6406 return &getARMMCRegisterClass(ARM::tGPREvenRegClassID);
6407 case MCK_tGPRwithpc:
6408 return &getARMMCRegisterClass(ARM::tGPRwithpcRegClassID);
6409 case MCK_QQQQPR:
6410 return &getARMMCRegisterClass(ARM::QQQQPRRegClassID);
6411 case MCK_GPRnoip:
6412 return &getARMMCRegisterClass(ARM::GPRnoipRegClassID);
6413 case MCK_rGPR:
6414 return &getARMMCRegisterClass(ARM::rGPRRegClassID);
6415 case MCK_GPRnopc:
6416 return &getARMMCRegisterClass(ARM::GPRnopcRegClassID);
6417 case MCK_GPRnosp:
6418 return &getARMMCRegisterClass(ARM::GPRnospRegClassID);
6419 case MCK_GPRwithAPSR_NZCVnosp:
6420 return &getARMMCRegisterClass(ARM::GPRwithAPSR_NZCVnospRegClassID);
6421 case MCK_GPRwithAPSRnosp:
6422 return &getARMMCRegisterClass(ARM::GPRwithAPSRnospRegClassID);
6423 case MCK_GPRwithZRnosp:
6424 return &getARMMCRegisterClass(ARM::GPRwithZRnospRegClassID);
6425 case MCK_QQPR:
6426 return &getARMMCRegisterClass(ARM::QQPRRegClassID);
6427 case MCK_DPR_VFP2:
6428 return &getARMMCRegisterClass(ARM::DPR_VFP2RegClassID);
6429 case MCK_GPR:
6430 return &getARMMCRegisterClass(ARM::GPRRegClassID);
6431 case MCK_GPRwithAPSR:
6432 return &getARMMCRegisterClass(ARM::GPRwithAPSRRegClassID);
6433 case MCK_GPRwithZR:
6434 return &getARMMCRegisterClass(ARM::GPRwithZRRegClassID);
6435 case MCK_QPR:
6436 return &getARMMCRegisterClass(ARM::QPRRegClassID);
6437 case MCK_SPR_8:
6438 return &getARMMCRegisterClass(ARM::SPR_8RegClassID);
6439 case MCK_DTripleSpc:
6440 return &getARMMCRegisterClass(ARM::DTripleSpcRegClassID);
6441 case MCK_DQuad:
6442 return &getARMMCRegisterClass(ARM::DQuadRegClassID);
6443 case MCK_DPairSpc:
6444 return &getARMMCRegisterClass(ARM::DPairSpcRegClassID);
6445 case MCK_DTriple:
6446 return &getARMMCRegisterClass(ARM::DTripleRegClassID);
6447 case MCK_DPair:
6448 return &getARMMCRegisterClass(ARM::DPairRegClassID);
6449 case MCK_DPR:
6450 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6451 case MCK_HPR:
6452 return &getARMMCRegisterClass(ARM::HPRRegClassID);
6453 case MCK_FPWithVPR:
6454 return &getARMMCRegisterClass(ARM::FPWithVPRRegClassID);
6455 case MCK_VecListTwoMQ:
6456 return &getARMMCRegisterClass(ARM::MQQPRRegClassID);
6457 case MCK_VecListFourMQ:
6458 return &getARMMCRegisterClass(ARM::MQQQQPRRegClassID);
6459 case MCK_VecListDPairAllLanes:
6460 return &getARMMCRegisterClass(ARM::DPairRegClassID);
6461 case MCK_VecListDPair:
6462 return &getARMMCRegisterClass(ARM::DPairRegClassID);
6463 case MCK_VecListDPairSpacedAllLanes:
6464 return &getARMMCRegisterClass(ARM::DPairSpcRegClassID);
6465 case MCK_VecListDPairSpaced:
6466 return &getARMMCRegisterClass(ARM::DPairRegClassID);
6467 case MCK_VecListFourDAllLanes:
6468 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6469 case MCK_VecListFourD:
6470 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6471 case MCK_VecListFourQAllLanes:
6472 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6473 case MCK_VecListFourQ:
6474 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6475 case MCK_VecListOneDAllLanes:
6476 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6477 case MCK_VecListOneD:
6478 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6479 case MCK_VecListThreeDAllLanes:
6480 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6481 case MCK_VecListThreeD:
6482 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6483 case MCK_VecListThreeQAllLanes:
6484 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6485 case MCK_VecListThreeQ:
6486 return &getARMMCRegisterClass(ARM::DPRRegClassID);
6487 default:
6488 return nullptr;
6489 }
6490}
6491
6492static MatchClassKind matchTokenString(StringRef Name) {
6493 switch (Name.size()) {
6494 default: break;
6495 case 1: // 6 strings to match.
6496 switch (Name[0]) {
6497 default: break;
6498 case '!': // 1 string to match.
6499 return MCK__EXCLAIM_; // "!"
6500 case '[': // 1 string to match.
6501 return MCK__91_; // "["
6502 case ']': // 1 string to match.
6503 return MCK__93_; // "]"
6504 case '^': // 1 string to match.
6505 return MCK__94_; // "^"
6506 case '{': // 1 string to match.
6507 return MCK__123_; // "{"
6508 case '}': // 1 string to match.
6509 return MCK__125_; // "}"
6510 }
6511 break;
6512 case 2: // 6 strings to match.
6513 switch (Name[0]) {
6514 default: break;
6515 case '#': // 2 strings to match.
6516 switch (Name[1]) {
6517 default: break;
6518 case '0': // 1 string to match.
6519 return MCK__HASH_0; // "#0"
6520 case '8': // 1 string to match.
6521 return MCK__HASH_8; // "#8"
6522 }
6523 break;
6524 case '.': // 4 strings to match.
6525 switch (Name[1]) {
6526 default: break;
6527 case '8': // 1 string to match.
6528 return MCK__DOT_8; // ".8"
6529 case 'd': // 1 string to match.
6530 return MCK__DOT_d; // ".d"
6531 case 'f': // 1 string to match.
6532 return MCK__DOT_f; // ".f"
6533 case 'w': // 1 string to match.
6534 return MCK__DOT_w; // ".w"
6535 }
6536 break;
6537 }
6538 break;
6539 case 3: // 8 strings to match.
6540 switch (Name[0]) {
6541 default: break;
6542 case '#': // 1 string to match.
6543 if (memcmp(Name.data()+1, "16", 2) != 0)
6544 break;
6545 return MCK__HASH_16; // "#16"
6546 case '.': // 7 strings to match.
6547 switch (Name[1]) {
6548 default: break;
6549 case '1': // 1 string to match.
6550 if (Name[2] != '6')
6551 break;
6552 return MCK__DOT_16; // ".16"
6553 case '3': // 1 string to match.
6554 if (Name[2] != '2')
6555 break;
6556 return MCK__DOT_32; // ".32"
6557 case '6': // 1 string to match.
6558 if (Name[2] != '4')
6559 break;
6560 return MCK__DOT_64; // ".64"
6561 case 'i': // 1 string to match.
6562 if (Name[2] != '8')
6563 break;
6564 return MCK__DOT_i8; // ".i8"
6565 case 'p': // 1 string to match.
6566 if (Name[2] != '8')
6567 break;
6568 return MCK__DOT_p8; // ".p8"
6569 case 's': // 1 string to match.
6570 if (Name[2] != '8')
6571 break;
6572 return MCK__DOT_s8; // ".s8"
6573 case 'u': // 1 string to match.
6574 if (Name[2] != '8')
6575 break;
6576 return MCK__DOT_u8; // ".u8"
6577 }
6578 break;
6579 }
6580 break;
6581 case 4: // 14 strings to match.
6582 if (Name[0] != '.')
6583 break;
6584 switch (Name[1]) {
6585 default: break;
6586 case 'f': // 3 strings to match.
6587 switch (Name[2]) {
6588 default: break;
6589 case '1': // 1 string to match.
6590 if (Name[3] != '6')
6591 break;
6592 return MCK__DOT_f16; // ".f16"
6593 case '3': // 1 string to match.
6594 if (Name[3] != '2')
6595 break;
6596 return MCK__DOT_f32; // ".f32"
6597 case '6': // 1 string to match.
6598 if (Name[3] != '4')
6599 break;
6600 return MCK__DOT_f64; // ".f64"
6601 }
6602 break;
6603 case 'i': // 3 strings to match.
6604 switch (Name[2]) {
6605 default: break;
6606 case '1': // 1 string to match.
6607 if (Name[3] != '6')
6608 break;
6609 return MCK__DOT_i16; // ".i16"
6610 case '3': // 1 string to match.
6611 if (Name[3] != '2')
6612 break;
6613 return MCK__DOT_i32; // ".i32"
6614 case '6': // 1 string to match.
6615 if (Name[3] != '4')
6616 break;
6617 return MCK__DOT_i64; // ".i64"
6618 }
6619 break;
6620 case 'p': // 2 strings to match.
6621 switch (Name[2]) {
6622 default: break;
6623 case '1': // 1 string to match.
6624 if (Name[3] != '6')
6625 break;
6626 return MCK__DOT_p16; // ".p16"
6627 case '6': // 1 string to match.
6628 if (Name[3] != '4')
6629 break;
6630 return MCK__DOT_p64; // ".p64"
6631 }
6632 break;
6633 case 's': // 3 strings to match.
6634 switch (Name[2]) {
6635 default: break;
6636 case '1': // 1 string to match.
6637 if (Name[3] != '6')
6638 break;
6639 return MCK__DOT_s16; // ".s16"
6640 case '3': // 1 string to match.
6641 if (Name[3] != '2')
6642 break;
6643 return MCK__DOT_s32; // ".s32"
6644 case '6': // 1 string to match.
6645 if (Name[3] != '4')
6646 break;
6647 return MCK__DOT_s64; // ".s64"
6648 }
6649 break;
6650 case 'u': // 3 strings to match.
6651 switch (Name[2]) {
6652 default: break;
6653 case '1': // 1 string to match.
6654 if (Name[3] != '6')
6655 break;
6656 return MCK__DOT_u16; // ".u16"
6657 case '3': // 1 string to match.
6658 if (Name[3] != '2')
6659 break;
6660 return MCK__DOT_u32; // ".u32"
6661 case '6': // 1 string to match.
6662 if (Name[3] != '4')
6663 break;
6664 return MCK__DOT_u64; // ".u64"
6665 }
6666 break;
6667 }
6668 break;
6669 case 5: // 1 string to match.
6670 if (memcmp(Name.data()+0, ".bf16", 5) != 0)
6671 break;
6672 return MCK__DOT_bf16; // ".bf16"
6673 }
6674 return InvalidMatchClass;
6675}
6676
6677/// isSubclass - Compute whether \p A is a subclass of \p B.
6678static bool isSubclass(MatchClassKind A, MatchClassKind B) {
6679 if (A == B)
6680 return true;
6681
6682 [[maybe_unused]] static constexpr struct {
6683 uint32_t Offset;
6684 uint16_t Start;
6685 uint16_t Length;
6686 } Table[] = {
6687 {0, 0, 0},
6688 {0, 0, 0},
6689 {0, 13, 14},
6690 {14, 12, 14},
6691 {28, 14, 11},
6692 {39, 15, 11},
6693 {50, 16, 11},
6694 {61, 17, 11},
6695 {72, 14, 11},
6696 {83, 15, 11},
6697 {94, 16, 11},
6698 {105, 17, 11},
6699 {116, 25, 1},
6700 {117, 26, 1},
6701 {118, 24, 1},
6702 {119, 25, 1},
6703 {120, 26, 1},
6704 {121, 27, 1},
6705 {122, 24, 1},
6706 {123, 27, 1},
6707 {124, 0, 0},
6708 {124, 0, 0},
6709 {124, 0, 0},
6710 {124, 0, 0},
6711 {124, 0, 0},
6712 {124, 0, 0},
6713 {124, 0, 0},
6714 {124, 0, 0},
6715 {124, 0, 0},
6716 {124, 0, 0},
6717 {124, 0, 0},
6718 {124, 0, 0},
6719 {124, 0, 0},
6720 {124, 0, 0},
6721 {124, 0, 0},
6722 {124, 0, 0},
6723 {124, 0, 0},
6724 {124, 73, 44},
6725 {168, 64, 76},
6726 {244, 155, 1},
6727 {245, 154, 12},
6728 {257, 0, 0},
6729 {257, 0, 0},
6730 {257, 0, 0},
6731 {257, 69, 1},
6732 {258, 0, 0},
6733 {258, 0, 0},
6734 {258, 69, 1},
6735 {259, 0, 0},
6736 {259, 0, 0},
6737 {259, 85, 82},
6738 {341, 93, 74},
6739 {415, 0, 0},
6740 {415, 0, 0},
6741 {415, 0, 0},
6742 {415, 0, 0},
6743 {415, 92, 73},
6744 {488, 77, 90},
6745 {578, 0, 0},
6746 {578, 176, 1},
6747 {579, 0, 0},
6748 {579, 70, 101},
6749 {680, 73, 44},
6750 {724, 74, 43},
6751 {767, 75, 65},
6752 {832, 86, 81},
6753 {913, 85, 82},
6754 {995, 87, 80},
6755 {1075, 77, 90},
6756 {1165, 0, 0},
6757 {1165, 78, 93},
6758 {1258, 80, 93},
6759 {1351, 81, 92},
6760 {1443, 116, 1},
6761 {1444, 116, 1},
6762 {1445, 83, 57},
6763 {1502, 84, 87},
6764 {1589, 95, 72},
6765 {1661, 96, 75},
6766 {1736, 97, 73},
6767 {1809, 108, 65},
6768 {1874, 109, 64},
6769 {1938, 105, 12},
6770 {1950, 94, 46},
6771 {1996, 112, 59},
6772 {2055, 103, 64},
6773 {2119, 92, 75},
6774 {2194, 106, 61},
6775 {2255, 104, 63},
6776 {2318, 113, 61},
6777 {2379, 95, 72},
6778 {2451, 100, 71},
6779 {2522, 102, 63},
6780 {2585, 102, 65},
6781 {2650, 99, 41},
6782 {2691, 146, 21},
6783 {2712, 107, 64},
6784 {2776, 119, 51},
6785 {2827, 110, 63},
6786 {2890, 111, 29},
6787 {2919, 112, 59},
6788 {2978, 126, 46},
6789 {3024, 130, 35},
6790 {3059, 114, 53},
6791 {3112, 132, 35},
6792 {3147, 116, 1},
6793 {3148, 135, 32},
6794 {3180, 118, 53},
6795 {3233, 120, 53},
6796 {3286, 121, 52},
6797 {3338, 122, 51},
6798 {3389, 123, 17},
6799 {3406, 124, 47},
6800 {3453, 127, 47},
6801 {3500, 130, 35},
6802 {3535, 130, 37},
6803 {3572, 0, 0},
6804 {3572, 125, 46},
6805 {3618, 140, 31},
6806 {3649, 134, 36},
6807 {3685, 147, 26},
6808 {3711, 148, 25},
6809 {3736, 142, 31},
6810 {3767, 139, 1},
6811 {3768, 136, 35},
6812 {3803, 150, 21},
6813 {3824, 144, 28},
6814 {3852, 151, 23},
6815 {3875, 163, 14},
6816 {3889, 151, 23},
6817 {3912, 164, 1},
6818 {3913, 133, 34},
6819 {3947, 146, 21},
6820 {3968, 137, 28},
6821 {3996, 141, 29},
6822 {4025, 137, 30},
6823 {4055, 143, 28},
6824 {4083, 145, 20},
6825 {4103, 145, 22},
6826 {4125, 0, 0},
6827 {4125, 170, 1},
6828 {4126, 158, 12},
6829 {4138, 149, 24},
6830 {4162, 150, 21},
6831 {4183, 161, 11},
6832 {4194, 164, 1},
6833 {4195, 152, 15},
6834 {4210, 172, 1},
6835 {4211, 172, 1},
6836 {4212, 159, 14},
6837 {4226, 160, 11},
6838 {4237, 162, 12},
6839 {4249, 164, 3},
6840 {4252, 164, 1},
6841 {4253, 165, 1},
6842 {4254, 0, 0},
6843 {4254, 166, 1},
6844 {4255, 170, 1},
6845 {4256, 169, 1},
6846 {4257, 172, 1},
6847 {4258, 170, 1},
6848 {4259, 171, 1},
6849 {4260, 173, 1},
6850 {4261, 174, 3},
6851 {4264, 0, 0},
6852 {4264, 0, 0},
6853 {4264, 0, 0},
6854 {4264, 173, 1},
6855 {4265, 175, 2},
6856 {4267, 0, 0},
6857 {4267, 0, 0},
6858 {4267, 0, 0},
6859 {4267, 0, 0},
6860 {4267, 0, 0},
6861 {4267, 176, 1},
6862 {4268, 176, 1},
6863 {4269, 0, 0},
6864 {4269, 0, 0},
6865 {4269, 0, 0},
6866 {4269, 0, 0},
6867 {4269, 0, 0},
6868 {4269, 0, 0},
6869 {4269, 0, 0},
6870 {4269, 0, 0},
6871 {4269, 0, 0},
6872 {4269, 0, 0},
6873 {4269, 0, 0},
6874 {4269, 0, 0},
6875 {4269, 0, 0},
6876 {4269, 0, 0},
6877 {4269, 0, 0},
6878 {4269, 0, 0},
6879 {4269, 0, 0},
6880 {4269, 0, 0},
6881 {4269, 0, 0},
6882 {4269, 0, 0},
6883 {4269, 0, 0},
6884 {4269, 0, 0},
6885 {4269, 0, 0},
6886 {4269, 1, 1},
6887 {4270, 1, 1},
6888 {4271, 0, 0},
6889 {4271, 0, 0},
6890 {4271, 0, 0},
6891 {4271, 0, 0},
6892 {4271, 0, 0},
6893 {4271, 0, 0},
6894 {4271, 0, 0},
6895 {4271, 0, 0},
6896 {4271, 0, 0},
6897 {4271, 0, 0},
6898 {4271, 0, 0},
6899 {4271, 0, 0},
6900 {4271, 0, 0},
6901 {4271, 0, 0},
6902 {4271, 0, 0},
6903 {4271, 0, 0},
6904 {4271, 0, 0},
6905 {4271, 0, 0},
6906 {4271, 0, 0},
6907 {4271, 0, 0},
6908 {4271, 0, 0},
6909 {4271, 0, 0},
6910 {4271, 0, 0},
6911 {4271, 0, 0},
6912 {4271, 0, 0},
6913 {4271, 0, 0},
6914 {4271, 0, 0},
6915 {4271, 0, 0},
6916 {4271, 0, 0},
6917 {4271, 0, 0},
6918 {4271, 0, 0},
6919 {4271, 0, 0},
6920 {4271, 0, 0},
6921 {4271, 0, 0},
6922 {4271, 0, 0},
6923 {4271, 0, 0},
6924 {4271, 0, 0},
6925 {4271, 0, 0},
6926 {4271, 0, 0},
6927 {4271, 0, 0},
6928 {4271, 0, 0},
6929 {4271, 0, 0},
6930 {4271, 0, 0},
6931 {4271, 0, 0},
6932 {4271, 0, 0},
6933 {4271, 0, 0},
6934 {4271, 0, 0},
6935 {4271, 0, 0},
6936 {4271, 0, 0},
6937 {4271, 0, 0},
6938 {4271, 0, 0},
6939 {4271, 0, 0},
6940 {4271, 0, 0},
6941 {4271, 0, 0},
6942 {4271, 0, 0},
6943 {4271, 0, 0},
6944 {4271, 0, 0},
6945 {4271, 0, 0},
6946 {4271, 0, 0},
6947 {4271, 0, 0},
6948 {4271, 0, 0},
6949 {4271, 0, 0},
6950 {4271, 0, 0},
6951 {4271, 0, 0},
6952 {4271, 0, 0},
6953 {4271, 0, 0},
6954 {4271, 0, 0},
6955 {4271, 0, 0},
6956 {4271, 0, 0},
6957 {4271, 0, 0},
6958 {4271, 0, 0},
6959 {4271, 0, 0},
6960 {4271, 0, 0},
6961 {4271, 0, 0},
6962 {4271, 0, 0},
6963 {4271, 0, 0},
6964 {4271, 0, 0},
6965 {4271, 0, 0},
6966 {4271, 0, 0},
6967 {4271, 0, 0},
6968 {4271, 0, 0},
6969 {4271, 0, 0},
6970 {4271, 0, 0},
6971 {4271, 0, 0},
6972 {4271, 0, 0},
6973 {4271, 0, 0},
6974 {4271, 0, 0},
6975 {4271, 1, 1},
6976 {4272, 1, 1},
6977 {4273, 0, 0},
6978 {4273, 0, 0},
6979 {4273, 0, 0},
6980 {4273, 0, 0},
6981 {4273, 0, 0},
6982 {4273, 0, 0},
6983 {4273, 0, 0},
6984 {4273, 0, 0},
6985 {4273, 0, 0},
6986 {4273, 0, 0},
6987 {4273, 0, 0},
6988 {4273, 0, 0},
6989 {4273, 0, 0},
6990 {4273, 0, 0},
6991 {4273, 0, 0},
6992 {4273, 0, 0},
6993 {4273, 0, 0},
6994 {4273, 0, 0},
6995 {4273, 0, 0},
6996 {4273, 0, 0},
6997 {4273, 0, 0},
6998 {4273, 0, 0},
6999 {4273, 0, 0},
7000 {4273, 0, 0},
7001 {4273, 0, 0},
7002 {4273, 0, 0},
7003 {4273, 0, 0},
7004 {4273, 0, 0},
7005 {4273, 0, 0},
7006 {4273, 0, 0},
7007 {4273, 0, 0},
7008 {4273, 0, 0},
7009 {4273, 0, 0},
7010 {4273, 0, 0},
7011 {4273, 0, 0},
7012 {4273, 0, 0},
7013 {4273, 0, 0},
7014 {4273, 0, 0},
7015 {4273, 0, 0},
7016 {4273, 0, 0},
7017 {4273, 0, 0},
7018 {4273, 0, 0},
7019 {4273, 0, 0},
7020 {4273, 0, 0},
7021 {4273, 0, 0},
7022 {4273, 0, 0},
7023 {4273, 0, 0},
7024 {4273, 0, 0},
7025 {4273, 0, 0},
7026 {4273, 0, 0},
7027 {4273, 0, 0},
7028 {4273, 0, 0},
7029 {4273, 0, 0},
7030 {4273, 0, 0},
7031 {4273, 0, 0},
7032 {4273, 0, 0},
7033 {4273, 0, 0},
7034 {4273, 0, 0},
7035 {4273, 0, 0},
7036 {4273, 0, 0},
7037 {4273, 0, 0},
7038 {4273, 0, 0},
7039 {4273, 0, 0},
7040 {4273, 0, 0},
7041 {4273, 0, 0},
7042 {4273, 0, 0},
7043 {4273, 0, 0},
7044 {4273, 0, 0},
7045 {4273, 0, 0},
7046 {4273, 0, 0},
7047 {4273, 0, 0},
7048 {4273, 0, 0},
7049 {4273, 0, 0},
7050 {4273, 0, 0},
7051 {4273, 0, 0},
7052 {4273, 0, 0},
7053 {4273, 0, 0},
7054 {4273, 0, 0},
7055 {4273, 0, 0},
7056 {4273, 0, 0},
7057 {4273, 0, 0},
7058 {4273, 0, 0},
7059 {4273, 0, 0},
7060 {4273, 0, 0},
7061 {4273, 0, 0},
7062 {4273, 0, 0},
7063 {4273, 0, 0},
7064 {4273, 0, 0},
7065 {4273, 0, 0},
7066 {4273, 0, 0},
7067 {4273, 0, 0},
7068 {4273, 0, 0},
7069 {4273, 0, 0},
7070 {4273, 0, 0},
7071 {4273, 0, 0},
7072 {4273, 0, 0},
7073 {4273, 0, 0},
7074 {4273, 0, 0},
7075 {4273, 0, 0},
7076 {4273, 0, 0},
7077 {4273, 0, 0},
7078 {4273, 0, 0},
7079 {4273, 0, 0},
7080 {4273, 0, 0},
7081 {4273, 0, 0},
7082 {4273, 0, 0},
7083 {4273, 0, 0},
7084 {4273, 0, 0},
7085 {4273, 0, 0},
7086 {4273, 0, 0},
7087 {4273, 0, 0},
7088 {4273, 0, 0},
7089 {4273, 0, 0},
7090 {4273, 0, 0},
7091 {4273, 0, 0},
7092 {4273, 0, 0},
7093 };
7094
7095 static constexpr uint8_t Data[] = {
7096 0x01,
7097 0x60,
7098 0x00,
7099 0x18,
7100 0xC0,
7101 0x00,
7102 0x06,
7103 0x30,
7104 0x80,
7105 0x01,
7106 0x0C,
7107 0x60,
7108 0x00,
7109 0x03,
7110 0xF8,
7111 0x3F,
7112 0x00,
7113 0x00,
7114 0x00,
7115 0x00,
7116 0x80,
7117 0x01,
7118 0x08,
7119 0x08,
7120 0x40,
7121 0x08,
7122 0x80,
7123 0x00,
7124 0x08,
7125 0x00,
7126 0x38,
7127 0x00,
7128 0x0F,
7129 0x00,
7130 0x20,
7131 0x00,
7132 0x03,
7133 0x00,
7134 0x05,
7135 0x00,
7136 0xC1,
7137 0x07,
7138 0x3C,
7139 0x40,
7140 0x00,
7141 0x08,
7142 0x00,
7143 0x04,
7144 0x04,
7145 0x02,
7146 0x01,
7147 0xF0,
7148 0x00,
7149 0x02,
7150 0x20,
7151 0x00,
7152 0x20,
7153 0x11,
7154 0x10,
7155 0x10,
7156 0x80,
7157 0x01,
7158 0x01,
7159 0x04,
7160 0x04,
7161 0x60,
7162 0x00,
7163 0xA0,
7164 0x00,
7165 0x20,
7166 0xF8,
7167 0x80,
7168 0x0F,
7169 0x08,
7170 0x00,
7171 0x21,
7172 0x02,
7173 0x21,
7174 0x08,
7175 0x02,
7176 0x20,
7177 0x12,
7178 0x08,
7179 0x20,
7180 0x80,
7181 0x01,
7182 0x00,
7183 0x00,
7184 0x00,
7185 0x01,
7186 0x18,
7187 0x10,
7188 0x00,
7189 0x00,
7190 0x08,
7191 0xC0,
7192 0x80,
7193 0x00,
7194 0x84,
7195 0x00,
7196 0x08,
7197 0x80,
7198 0x00,
7199 0x80,
7200 0xC1,
7201 0x00,
7202 0x13,
7203 0x30,
7204 0x00,
7205 0x10,
7206 0x1A,
7207 0x18,
7208 0x7C,
7209 0xC0,
7210 0x07,
7211 0x03,
7212 0x1C,
7213 0xC0,
7214 0x00,
7215 0x40,
7216 0x69,
7217 0x60,
7218 0xF0,
7219 0x01,
7220 0x4F,
7221 0x08,
7222 0x40,
7223 0x00,
7224 0x00,
7225 0x80,
7226 0x6A,
7227 0x60,
7228 0xF0,
7229 0x01,
7230 0x0F,
7231 0x40,
7232 0x21,
7233 0x40,
7234 0x00,
7235 0x00,
7236 0x00,
7237 0xAE,
7238 0x81,
7239 0xC1,
7240 0x07,
7241 0x3C,
7242 0x00,
7243 0x80,
7244 0x08,
7245 0x84,
7246 0x20,
7247 0x08,
7248 0x80,
7249 0x48,
7250 0x20,
7251 0x80,
7252 0x00,
7253 0x06,
7254 0x00,
7255 0x10,
7256 0x40,
7257 0x01,
7258 0x14,
7259 0x00,
7260 0x00,
7261 0xA1,
7262 0x00,
7263 0x02,
7264 0xC0,
7265 0x00,
7266 0x00,
7267 0x01,
7268 0x18,
7269 0x80,
7270 0x01,
7271 0x00,
7272 0x10,
7273 0x0C,
7274 0x20,
7275 0x00,
7276 0x3C,
7277 0x00,
7278 0x21,
7279 0x00,
7280 0x02,
7281 0x20,
7282 0x00,
7283 0x60,
7284 0x20,
7285 0x40,
7286 0x00,
7287 0x84,
7288 0xC0,
7289 0x00,
7290 0x04,
7291 0x02,
7292 0x81,
7293 0x04,
7294 0x30,
7295 0x00,
7296 0x00,
7297 0x00,
7298 0x00,
7299 0x04,
7300 0x00,
7301 0xC1,
7302 0x07,
7303 0x3C,
7304 0x00,
7305 0x01,
7306 0x08,
7307 0x02,
7308 0x20,
7309 0x12,
7310 0x08,
7311 0x20,
7312 0x80,
7313 0x01,
7314 0x00,
7315 0x40,
7316 0x00,
7317 0x20,
7318 0x10,
7319 0x00,
7320 0x20,
7321 0x00,
7322 0x03,
7323 0xA0,
7324 0x00,
7325 0x00,
7326 0x08,
7327 0x05,
7328 0x10,
7329 0x00,
7330 0x0E,
7331 0xC0,
7332 0x00,
7333 0x00,
7334 0x08,
7335 0x06,
7336 0x10,
7337 0x00,
7338 0x06,
7339 0x60,
7340 0x08,
7341 0x80,
7342 0x00,
7343 0x08,
7344 0x00,
7345 0x18,
7346 0x02,
7347 0x03,
7348 0x10,
7349 0x08,
7350 0x04,
7351 0x12,
7352 0xC0,
7353 0x00,
7354 0x0C,
7355 0x00,
7356 0x14,
7357 0x00,
7358 0x04,
7359 0x1F,
7360 0xF0,
7361 0x01,
7362 0x06,
7363 0x60,
7364 0x00,
7365 0x20,
7366 0x34,
7367 0x30,
7368 0xF8,
7369 0x80,
7370 0x07,
7371 0x00,
7372 0x00,
7373 0xA8,
7374 0x06,
7375 0x06,
7376 0x1F,
7377 0xF0,
7378 0x00,
7379 0x00,
7380 0x00,
7381 0x5C,
7382 0x03,
7383 0x83,
7384 0x0F,
7385 0x78,
7386 0x00,
7387 0x50,
7388 0x00,
7389 0x00,
7390 0x10,
7391 0x80,
7392 0x10,
7393 0x0C,
7394 0x00,
7395 0x00,
7396 0x00,
7397 0x80,
7398 0x6A,
7399 0x60,
7400 0xF0,
7401 0x01,
7402 0x0F,
7403 0x80,
7404 0x00,
7405 0x08,
7406 0x80,
7407 0x40,
7408 0x20,
7409 0x80,
7410 0x00,
7411 0x06,
7412 0x40,
7413 0x00,
7414 0x40,
7415 0x20,
7416 0x20,
7417 0x20,
7418 0x00,
7419 0x03,
7420 0x40,
7421 0x00,
7422 0x20,
7423 0x20,
7424 0x10,
7425 0x08,
7426 0x80,
7427 0x07,
7428 0x40,
7429 0x00,
7430 0x04,
7431 0x00,
7432 0x0C,
7433 0x3E,
7434 0xE0,
7435 0x01,
7436 0x08,
7437 0x00,
7438 0x20,
7439 0x12,
7440 0x08,
7441 0x20,
7442 0x80,
7443 0x01,
7444 0x80,
7445 0x40,
7446 0x00,
7447 0x80,
7448 0x00,
7449 0x0C,
7450 0x80,
7451 0x00,
7452 0x00,
7453 0x08,
7454 0x04,
7455 0x10,
7456 0x00,
7457 0x06,
7458 0x40,
7459 0x00,
7460 0xC0,
7461 0x00,
7462 0x08,
7463 0x80,
7464 0x40,
7465 0x20,
7466 0x80,
7467 0x00,
7468 0x06,
7469 0x00,
7470 0x10,
7471 0x00,
7472 0x20,
7473 0x80,
7474 0x01,
7475 0x80,
7476 0x00,
7477 0x00,
7478 0x1C,
7479 0x00,
7480 0x08,
7481 0x00,
7482 0x08,
7483 0x3E,
7484 0xE0,
7485 0x69,
7486 0x60,
7487 0xF0,
7488 0x01,
7489 0xDF,
7490 0xC0,
7491 0xE0,
7492 0x03,
7493 0x1E,
7494 0x00,
7495 0x00,
7496 0x24,
7497 0x10,
7498 0x40,
7499 0x00,
7500 0x03,
7501 0x00,
7502 0x80,
7503 0x50,
7504 0x00,
7505 0x01,
7506 0x60,
7507 0x00,
7508 0x00,
7509 0x08,
7510 0x06,
7511 0x10,
7512 0x00,
7513 0x06,
7514 0x00,
7515 0x40,
7516 0x20,
7517 0x80,
7518 0x00,
7519 0x30,
7520 0x00,
7521 0x60,
7522 0x00,
7523 0x04,
7524 0x02,
7525 0x01,
7526 0x04,
7527 0x30,
7528 0x00,
7529 0x00,
7530 0x20,
7531 0x00,
7532 0x01,
7533 0x18,
7534 0x00,
7535 0x00,
7536 0x08,
7537 0xC0,
7538 0x00,
7539 0x00,
7540 0x20,
7541 0x00,
7542 0x1E,
7543 0x80,
7544 0x40,
7545 0x20,
7546 0x90,
7547 0x00,
7548 0x06,
7549 0x00,
7550 0x40,
7551 0x00,
7552 0x03,
7553 0x01,
7554 0x00,
7555 0x02,
7556 0x30,
7557 0x00,
7558 0x02,
7559 0xC0,
7560 0x01,
7561 0x04,
7562 0x80,
7563 0x81,
7564 0x00,
7565 0x02,
7566 0xC0,
7567 0x81,
7568 0x40,
7569 0x00,
7570 0x01,
7571 0x0C,
7572 0x24,
7573 0x80,
7574 0x01,
7575 0x00,
7576 0x02,
7577 0x18,
7578 0x80,
7579 0x00,
7580 0x0C,
7581 0x40,
7582 0x03,
7583 0x10,
7584 0x82,
7585 0x6B,
7586 0x60,
7587 0xF0,
7588 0x01,
7589 0x0F,
7590 0x3E,
7591 0xE0,
7592 0x01,
7593 0x01,
7594 0x01,
7595 0x18,
7596 0x00,
7597 0x20,
7598 0x00,
7599 0x07,
7600 0x06,
7601 0x1F,
7602 0xF0,
7603 0x40,
7604 0x00,
7605 0x01,
7606 0x0C,
7607 0x08,
7608 0xC0,
7609 0x40,
7610 0x00,
7611 0x7C,
7612 0x00,
7613 0x06,
7614 0x10,
7615 0x00,
7616 0x06,
7617 0x10,
7618 0xC0,
7619 0x00,
7620 0xFE,
7621 0x80,
7622 0x1F,
7623 0x00,
7624 0x06,
7625 0x30,
7626 0x00,
7627 0xFF,
7628 0xBF,
7629 0xFF,
7630 0x01,
7631 };
7632
7633 auto &Entry = Table[A];
7634 unsigned Idx = B - Entry.Start;
7635 if (Idx >= Entry.Length)
7636 return false;
7637 Idx += Entry.Offset;
7638 return (Data[Idx / 8] >> (Idx % 8)) & 1;
7639}
7640
7641static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
7642 ARMOperand &Operand = (ARMOperand &)GOp;
7643 if (Kind == InvalidMatchClass)
7644 return MCTargetAsmParser::Match_InvalidOperand;
7645
7646 if (Kind <= MCK_LAST_TOKEN) {
7647 if (Operand.isToken() &&
7648 isSubclass(matchTokenString(Operand.getToken()), Kind))
7649 return MCTargetAsmParser::Match_Success;
7650 return MCTargetAsmParser::Match_InvalidOperand;
7651 }
7652
7653 switch (Kind) {
7654 default: break;
7655 case MCK_AM2OffsetImm: {
7656 DiagnosticPredicate DP(Operand.isAM2OffsetImm());
7657 if (DP.isMatch())
7658 return MCTargetAsmParser::Match_Success;
7659 break;
7660 }
7661 case MCK_AM3Offset: {
7662 DiagnosticPredicate DP(Operand.isAM3Offset());
7663 if (DP.isMatch())
7664 return MCTargetAsmParser::Match_Success;
7665 break;
7666 }
7667 case MCK_ARMBranchTarget: {
7668 DiagnosticPredicate DP(Operand.isARMBranchTarget());
7669 if (DP.isMatch())
7670 return MCTargetAsmParser::Match_Success;
7671 break;
7672 }
7673 case MCK_AddrMode3: {
7674 DiagnosticPredicate DP(Operand.isAddrMode3());
7675 if (DP.isMatch())
7676 return MCTargetAsmParser::Match_Success;
7677 break;
7678 }
7679 case MCK_AddrMode5: {
7680 DiagnosticPredicate DP(Operand.isAddrMode5());
7681 if (DP.isMatch())
7682 return MCTargetAsmParser::Match_Success;
7683 break;
7684 }
7685 case MCK_AddrMode5FP16: {
7686 DiagnosticPredicate DP(Operand.isAddrMode5FP16());
7687 if (DP.isMatch())
7688 return MCTargetAsmParser::Match_Success;
7689 break;
7690 }
7691 case MCK_AlignedMemory16: {
7692 DiagnosticPredicate DP(Operand.isAlignedMemory16());
7693 if (DP.isMatch())
7694 return MCTargetAsmParser::Match_Success;
7695 if (DP.isNearMatch())
7696 return ARMAsmParser::Match_AlignedMemory16;
7697 break;
7698 }
7699 case MCK_AlignedMemory32: {
7700 DiagnosticPredicate DP(Operand.isAlignedMemory32());
7701 if (DP.isMatch())
7702 return MCTargetAsmParser::Match_Success;
7703 if (DP.isNearMatch())
7704 return ARMAsmParser::Match_AlignedMemory32;
7705 break;
7706 }
7707 case MCK_AlignedMemory64: {
7708 DiagnosticPredicate DP(Operand.isAlignedMemory64());
7709 if (DP.isMatch())
7710 return MCTargetAsmParser::Match_Success;
7711 if (DP.isNearMatch())
7712 return ARMAsmParser::Match_AlignedMemory64;
7713 break;
7714 }
7715 case MCK_AlignedMemory64or128: {
7716 DiagnosticPredicate DP(Operand.isAlignedMemory64or128());
7717 if (DP.isMatch())
7718 return MCTargetAsmParser::Match_Success;
7719 if (DP.isNearMatch())
7720 return ARMAsmParser::Match_AlignedMemory64or128;
7721 break;
7722 }
7723 case MCK_AlignedMemory64or128or256: {
7724 DiagnosticPredicate DP(Operand.isAlignedMemory64or128or256());
7725 if (DP.isMatch())
7726 return MCTargetAsmParser::Match_Success;
7727 if (DP.isNearMatch())
7728 return ARMAsmParser::Match_AlignedMemory64or128or256;
7729 break;
7730 }
7731 case MCK_AlignedMemoryNone: {
7732 DiagnosticPredicate DP(Operand.isAlignedMemoryNone());
7733 if (DP.isMatch())
7734 return MCTargetAsmParser::Match_Success;
7735 if (DP.isNearMatch())
7736 return ARMAsmParser::Match_AlignedMemoryNone;
7737 break;
7738 }
7739 case MCK_AlignedMemory: {
7740 DiagnosticPredicate DP(Operand.isAlignedMemory());
7741 if (DP.isMatch())
7742 return MCTargetAsmParser::Match_Success;
7743 break;
7744 }
7745 case MCK_DupAlignedMemory16: {
7746 DiagnosticPredicate DP(Operand.isDupAlignedMemory16());
7747 if (DP.isMatch())
7748 return MCTargetAsmParser::Match_Success;
7749 if (DP.isNearMatch())
7750 return ARMAsmParser::Match_DupAlignedMemory16;
7751 break;
7752 }
7753 case MCK_DupAlignedMemory32: {
7754 DiagnosticPredicate DP(Operand.isDupAlignedMemory32());
7755 if (DP.isMatch())
7756 return MCTargetAsmParser::Match_Success;
7757 if (DP.isNearMatch())
7758 return ARMAsmParser::Match_DupAlignedMemory32;
7759 break;
7760 }
7761 case MCK_DupAlignedMemory64: {
7762 DiagnosticPredicate DP(Operand.isDupAlignedMemory64());
7763 if (DP.isMatch())
7764 return MCTargetAsmParser::Match_Success;
7765 if (DP.isNearMatch())
7766 return ARMAsmParser::Match_DupAlignedMemory64;
7767 break;
7768 }
7769 case MCK_DupAlignedMemory64or128: {
7770 DiagnosticPredicate DP(Operand.isDupAlignedMemory64or128());
7771 if (DP.isMatch())
7772 return MCTargetAsmParser::Match_Success;
7773 if (DP.isNearMatch())
7774 return ARMAsmParser::Match_DupAlignedMemory64or128;
7775 break;
7776 }
7777 case MCK_DupAlignedMemoryNone: {
7778 DiagnosticPredicate DP(Operand.isDupAlignedMemoryNone());
7779 if (DP.isMatch())
7780 return MCTargetAsmParser::Match_Success;
7781 if (DP.isNearMatch())
7782 return ARMAsmParser::Match_DupAlignedMemoryNone;
7783 break;
7784 }
7785 case MCK_AdrLabel: {
7786 DiagnosticPredicate DP(Operand.isAdrLabel());
7787 if (DP.isMatch())
7788 return MCTargetAsmParser::Match_Success;
7789 break;
7790 }
7791 case MCK_BankedReg: {
7792 DiagnosticPredicate DP(Operand.isBankedReg());
7793 if (DP.isMatch())
7794 return MCTargetAsmParser::Match_Success;
7795 break;
7796 }
7797 case MCK_Bitfield: {
7798 DiagnosticPredicate DP(Operand.isBitfield());
7799 if (DP.isMatch())
7800 return MCTargetAsmParser::Match_Success;
7801 break;
7802 }
7803 case MCK_CCOut: {
7804 DiagnosticPredicate DP(Operand.isCCOut());
7805 if (DP.isMatch())
7806 return MCTargetAsmParser::Match_Success;
7807 break;
7808 }
7809 case MCK_CondCode: {
7810 DiagnosticPredicate DP(Operand.isCondCode());
7811 if (DP.isMatch())
7812 return MCTargetAsmParser::Match_Success;
7813 break;
7814 }
7815 case MCK_CoprocNum: {
7816 DiagnosticPredicate DP(Operand.isCoprocNum());
7817 if (DP.isMatch())
7818 return MCTargetAsmParser::Match_Success;
7819 break;
7820 }
7821 case MCK_CoprocOption: {
7822 DiagnosticPredicate DP(Operand.isCoprocOption());
7823 if (DP.isMatch())
7824 return MCTargetAsmParser::Match_Success;
7825 break;
7826 }
7827 case MCK_CoprocReg: {
7828 DiagnosticPredicate DP(Operand.isCoprocReg());
7829 if (DP.isMatch())
7830 return MCTargetAsmParser::Match_Success;
7831 break;
7832 }
7833 case MCK_DPRRegList: {
7834 DiagnosticPredicate DP(Operand.isDPRRegList());
7835 if (DP.isMatch())
7836 return MCTargetAsmParser::Match_Success;
7837 if (DP.isNearMatch())
7838 return ARMAsmParser::Match_DPR_RegList;
7839 break;
7840 }
7841 case MCK_FPDRegListWithVPR: {
7842 DiagnosticPredicate DP(Operand.isFPDRegListWithVPR());
7843 if (DP.isMatch())
7844 return MCTargetAsmParser::Match_Success;
7845 break;
7846 }
7847 case MCK_FPImm: {
7848 DiagnosticPredicate DP(Operand.isFPImm());
7849 if (DP.isMatch())
7850 return MCTargetAsmParser::Match_Success;
7851 break;
7852 }
7853 case MCK_FPSRegListWithVPR: {
7854 DiagnosticPredicate DP(Operand.isFPSRegListWithVPR());
7855 if (DP.isMatch())
7856 return MCTargetAsmParser::Match_Success;
7857 break;
7858 }
7859 case MCK_Imm0_15: {
7860 DiagnosticPredicate DP(Operand.isImmediate<0,15>());
7861 if (DP.isMatch())
7862 return MCTargetAsmParser::Match_Success;
7863 if (DP.isNearMatch())
7864 return ARMAsmParser::Match_Imm0_15;
7865 break;
7866 }
7867 case MCK_Imm0_1: {
7868 DiagnosticPredicate DP(Operand.isImmediate<0,1>());
7869 if (DP.isMatch())
7870 return MCTargetAsmParser::Match_Success;
7871 if (DP.isNearMatch())
7872 return ARMAsmParser::Match_Imm0_1;
7873 break;
7874 }
7875 case MCK_Imm0_239: {
7876 DiagnosticPredicate DP(Operand.isImmediate<0,239>());
7877 if (DP.isMatch())
7878 return MCTargetAsmParser::Match_Success;
7879 if (DP.isNearMatch())
7880 return ARMAsmParser::Match_Imm0_239;
7881 break;
7882 }
7883 case MCK_Imm0_255: {
7884 DiagnosticPredicate DP(Operand.isImmediate<0,255>());
7885 if (DP.isMatch())
7886 return MCTargetAsmParser::Match_Success;
7887 if (DP.isNearMatch())
7888 return ARMAsmParser::Match_Imm0_255;
7889 break;
7890 }
7891 case MCK_Imm0_255Expr: {
7892 DiagnosticPredicate DP(Operand.isImm0_255Expr());
7893 if (DP.isMatch())
7894 return MCTargetAsmParser::Match_Success;
7895 if (DP.isNearMatch())
7896 return ARMAsmParser::Match_Imm0_255Expr;
7897 break;
7898 }
7899 case MCK_Imm0_31: {
7900 DiagnosticPredicate DP(Operand.isImmediate<0,31>());
7901 if (DP.isMatch())
7902 return MCTargetAsmParser::Match_Success;
7903 if (DP.isNearMatch())
7904 return ARMAsmParser::Match_Imm0_31;
7905 break;
7906 }
7907 case MCK_Imm0_32: {
7908 DiagnosticPredicate DP(Operand.isImmediate<0,32>());
7909 if (DP.isMatch())
7910 return MCTargetAsmParser::Match_Success;
7911 if (DP.isNearMatch())
7912 return ARMAsmParser::Match_Imm0_32;
7913 break;
7914 }
7915 case MCK_Imm0_3: {
7916 DiagnosticPredicate DP(Operand.isImmediate<0,3>());
7917 if (DP.isMatch())
7918 return MCTargetAsmParser::Match_Success;
7919 if (DP.isNearMatch())
7920 return ARMAsmParser::Match_Imm0_3;
7921 break;
7922 }
7923 case MCK_Imm0_63: {
7924 DiagnosticPredicate DP(Operand.isImmediate<0,63>());
7925 if (DP.isMatch())
7926 return MCTargetAsmParser::Match_Success;
7927 if (DP.isNearMatch())
7928 return ARMAsmParser::Match_Imm0_63;
7929 break;
7930 }
7931 case MCK_Imm0_65535: {
7932 DiagnosticPredicate DP(Operand.isImmediate<0,65535>());
7933 if (DP.isMatch())
7934 return MCTargetAsmParser::Match_Success;
7935 if (DP.isNearMatch())
7936 return ARMAsmParser::Match_Imm0_65535;
7937 break;
7938 }
7939 case MCK_Imm0_65535Expr: {
7940 DiagnosticPredicate DP(Operand.isImm0_65535Expr());
7941 if (DP.isMatch())
7942 return MCTargetAsmParser::Match_Success;
7943 if (DP.isNearMatch())
7944 return ARMAsmParser::Match_Imm0_65535Expr;
7945 break;
7946 }
7947 case MCK_Imm0_7: {
7948 DiagnosticPredicate DP(Operand.isImmediate<0,7>());
7949 if (DP.isMatch())
7950 return MCTargetAsmParser::Match_Success;
7951 if (DP.isNearMatch())
7952 return ARMAsmParser::Match_Imm0_7;
7953 break;
7954 }
7955 case MCK_Imm16: {
7956 DiagnosticPredicate DP(Operand.isImmediate<16,16>());
7957 if (DP.isMatch())
7958 return MCTargetAsmParser::Match_Success;
7959 if (DP.isNearMatch())
7960 return ARMAsmParser::Match_Imm16;
7961 break;
7962 }
7963 case MCK_Imm1_15: {
7964 DiagnosticPredicate DP(Operand.isImmediate<1,15>());
7965 if (DP.isMatch())
7966 return MCTargetAsmParser::Match_Success;
7967 if (DP.isNearMatch())
7968 return ARMAsmParser::Match_Imm1_15;
7969 break;
7970 }
7971 case MCK_Imm1_16: {
7972 DiagnosticPredicate DP(Operand.isImmediate<1,16>());
7973 if (DP.isMatch())
7974 return MCTargetAsmParser::Match_Success;
7975 if (DP.isNearMatch())
7976 return ARMAsmParser::Match_ImmRange1_16;
7977 break;
7978 }
7979 case MCK_Imm1_31: {
7980 DiagnosticPredicate DP(Operand.isImmediate<1,31>());
7981 if (DP.isMatch())
7982 return MCTargetAsmParser::Match_Success;
7983 if (DP.isNearMatch())
7984 return ARMAsmParser::Match_Imm1_31;
7985 break;
7986 }
7987 case MCK_Imm1_32: {
7988 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
7989 if (DP.isMatch())
7990 return MCTargetAsmParser::Match_Success;
7991 if (DP.isNearMatch())
7992 return ARMAsmParser::Match_ImmRange1_32;
7993 break;
7994 }
7995 case MCK_Imm1_7: {
7996 DiagnosticPredicate DP(Operand.isImmediate<1,7>());
7997 if (DP.isMatch())
7998 return MCTargetAsmParser::Match_Success;
7999 if (DP.isNearMatch())
8000 return ARMAsmParser::Match_Imm1_7;
8001 break;
8002 }
8003 case MCK_Imm24bit: {
8004 DiagnosticPredicate DP(Operand.isImmediate<0,16777215>());
8005 if (DP.isMatch())
8006 return MCTargetAsmParser::Match_Success;
8007 if (DP.isNearMatch())
8008 return ARMAsmParser::Match_Imm24bit;
8009 break;
8010 }
8011 case MCK_Imm256_65535Expr: {
8012 DiagnosticPredicate DP(Operand.isImmediate<256,65535>());
8013 if (DP.isMatch())
8014 return MCTargetAsmParser::Match_Success;
8015 if (DP.isNearMatch())
8016 return ARMAsmParser::Match_Imm256_65535Expr;
8017 break;
8018 }
8019 case MCK_Imm32: {
8020 DiagnosticPredicate DP(Operand.isImmediate<32,32>());
8021 if (DP.isMatch())
8022 return MCTargetAsmParser::Match_Success;
8023 if (DP.isNearMatch())
8024 return ARMAsmParser::Match_Imm32;
8025 break;
8026 }
8027 case MCK_Imm8: {
8028 DiagnosticPredicate DP(Operand.isImmediate<8,8>());
8029 if (DP.isMatch())
8030 return MCTargetAsmParser::Match_Success;
8031 if (DP.isNearMatch())
8032 return ARMAsmParser::Match_Imm8;
8033 break;
8034 }
8035 case MCK_Imm8_255: {
8036 DiagnosticPredicate DP(Operand.isImmediate<8,255>());
8037 if (DP.isMatch())
8038 return MCTargetAsmParser::Match_Success;
8039 if (DP.isNearMatch())
8040 return ARMAsmParser::Match_Imm8_255;
8041 break;
8042 }
8043 case MCK_Imm: {
8044 DiagnosticPredicate DP(Operand.isImm());
8045 if (DP.isMatch())
8046 return MCTargetAsmParser::Match_Success;
8047 break;
8048 }
8049 case MCK_InstSyncBarrierOpt: {
8050 DiagnosticPredicate DP(Operand.isInstSyncBarrierOpt());
8051 if (DP.isMatch())
8052 return MCTargetAsmParser::Match_Success;
8053 break;
8054 }
8055 case MCK_MSRMask: {
8056 DiagnosticPredicate DP(Operand.isMSRMask());
8057 if (DP.isMatch())
8058 return MCTargetAsmParser::Match_Success;
8059 break;
8060 }
8061 case MCK_MVEShiftImm1_15: {
8062 DiagnosticPredicate DP(Operand.isImmediate<1,15>());
8063 if (DP.isMatch())
8064 return MCTargetAsmParser::Match_Success;
8065 if (DP.isNearMatch())
8066 return ARMAsmParser::Match_MVEShiftImm1_15;
8067 break;
8068 }
8069 case MCK_MVEShiftImm1_7: {
8070 DiagnosticPredicate DP(Operand.isImmediate<1,7>());
8071 if (DP.isMatch())
8072 return MCTargetAsmParser::Match_Success;
8073 if (DP.isNearMatch())
8074 return ARMAsmParser::Match_MVEShiftImm1_7;
8075 break;
8076 }
8077 case MCK_VIDUP_imm: {
8078 DiagnosticPredicate DP(Operand.isPowerTwoInRange<1,8>());
8079 if (DP.isMatch())
8080 return MCTargetAsmParser::Match_Success;
8081 if (DP.isNearMatch())
8082 return ARMAsmParser::Match_VIDUP_imm;
8083 break;
8084 }
8085 case MCK_MemBarrierOpt: {
8086 DiagnosticPredicate DP(Operand.isMemBarrierOpt());
8087 if (DP.isMatch())
8088 return MCTargetAsmParser::Match_Success;
8089 break;
8090 }
8091 case MCK_MemImm0_1020s4Offset: {
8092 DiagnosticPredicate DP(Operand.isMemImm0_1020s4Offset());
8093 if (DP.isMatch())
8094 return MCTargetAsmParser::Match_Success;
8095 break;
8096 }
8097 case MCK_MemImm12Offset: {
8098 DiagnosticPredicate DP(Operand.isMemImm12Offset());
8099 if (DP.isMatch())
8100 return MCTargetAsmParser::Match_Success;
8101 break;
8102 }
8103 case MCK_MemImm7Shift0Offset: {
8104 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::GPRnopcRegClassID>());
8105 if (DP.isMatch())
8106 return MCTargetAsmParser::Match_Success;
8107 break;
8108 }
8109 case MCK_MemImm7Shift0OffsetWB: {
8110 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::rGPRRegClassID>());
8111 if (DP.isMatch())
8112 return MCTargetAsmParser::Match_Success;
8113 break;
8114 }
8115 case MCK_MemImm7Shift1Offset: {
8116 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::GPRnopcRegClassID>());
8117 if (DP.isMatch())
8118 return MCTargetAsmParser::Match_Success;
8119 break;
8120 }
8121 case MCK_MemImm7Shift1OffsetWB: {
8122 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::rGPRRegClassID>());
8123 if (DP.isMatch())
8124 return MCTargetAsmParser::Match_Success;
8125 break;
8126 }
8127 case MCK_MemImm7Shift2Offset: {
8128 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::GPRnopcRegClassID>());
8129 if (DP.isMatch())
8130 return MCTargetAsmParser::Match_Success;
8131 break;
8132 }
8133 case MCK_MemImm7Shift2OffsetWB: {
8134 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::rGPRRegClassID>());
8135 if (DP.isMatch())
8136 return MCTargetAsmParser::Match_Success;
8137 break;
8138 }
8139 case MCK_MemImm7s4Offset: {
8140 DiagnosticPredicate DP(Operand.isMemImm7s4Offset());
8141 if (DP.isMatch())
8142 return MCTargetAsmParser::Match_Success;
8143 break;
8144 }
8145 case MCK_MemImm8Offset: {
8146 DiagnosticPredicate DP(Operand.isMemImm8Offset());
8147 if (DP.isMatch())
8148 return MCTargetAsmParser::Match_Success;
8149 break;
8150 }
8151 case MCK_MemImm8s4Offset: {
8152 DiagnosticPredicate DP(Operand.isMemImm8s4Offset());
8153 if (DP.isMatch())
8154 return MCTargetAsmParser::Match_Success;
8155 break;
8156 }
8157 case MCK_MemNegImm8Offset: {
8158 DiagnosticPredicate DP(Operand.isMemNegImm8Offset());
8159 if (DP.isMatch())
8160 return MCTargetAsmParser::Match_Success;
8161 break;
8162 }
8163 case MCK_MemNoOffset: {
8164 DiagnosticPredicate DP(Operand.isMemNoOffset());
8165 if (DP.isMatch())
8166 return MCTargetAsmParser::Match_Success;
8167 break;
8168 }
8169 case MCK_MemNoOffsetT2: {
8170 DiagnosticPredicate DP(Operand.isMemNoOffsetT2());
8171 if (DP.isMatch())
8172 return MCTargetAsmParser::Match_Success;
8173 break;
8174 }
8175 case MCK_MemNoOffsetT2NoSp: {
8176 DiagnosticPredicate DP(Operand.isMemNoOffsetT2NoSp());
8177 if (DP.isMatch())
8178 return MCTargetAsmParser::Match_Success;
8179 break;
8180 }
8181 case MCK_MemNoOffsetT: {
8182 DiagnosticPredicate DP(Operand.isMemNoOffsetT());
8183 if (DP.isMatch())
8184 return MCTargetAsmParser::Match_Success;
8185 break;
8186 }
8187 case MCK_MemPosImm8Offset: {
8188 DiagnosticPredicate DP(Operand.isMemPosImm8Offset());
8189 if (DP.isMatch())
8190 return MCTargetAsmParser::Match_Success;
8191 break;
8192 }
8193 case MCK_MemRegOffset: {
8194 DiagnosticPredicate DP(Operand.isMemRegOffset());
8195 if (DP.isMatch())
8196 return MCTargetAsmParser::Match_Success;
8197 break;
8198 }
8199 case MCK_MemRegQS2Offset: {
8200 DiagnosticPredicate DP(Operand.isMemRegQOffset<2>());
8201 if (DP.isMatch())
8202 return MCTargetAsmParser::Match_Success;
8203 break;
8204 }
8205 case MCK_MemRegQS3Offset: {
8206 DiagnosticPredicate DP(Operand.isMemRegQOffset<3>());
8207 if (DP.isMatch())
8208 return MCTargetAsmParser::Match_Success;
8209 break;
8210 }
8211 case MCK_MemRegRQS0Offset: {
8212 DiagnosticPredicate DP(Operand.isMemRegRQOffset<0>());
8213 if (DP.isMatch())
8214 return MCTargetAsmParser::Match_Success;
8215 break;
8216 }
8217 case MCK_MemRegRQS1Offset: {
8218 DiagnosticPredicate DP(Operand.isMemRegRQOffset<1>());
8219 if (DP.isMatch())
8220 return MCTargetAsmParser::Match_Success;
8221 break;
8222 }
8223 case MCK_MemRegRQS2Offset: {
8224 DiagnosticPredicate DP(Operand.isMemRegRQOffset<2>());
8225 if (DP.isMatch())
8226 return MCTargetAsmParser::Match_Success;
8227 break;
8228 }
8229 case MCK_MemRegRQS3Offset: {
8230 DiagnosticPredicate DP(Operand.isMemRegRQOffset<3>());
8231 if (DP.isMatch())
8232 return MCTargetAsmParser::Match_Success;
8233 break;
8234 }
8235 case MCK_ModImm: {
8236 DiagnosticPredicate DP(Operand.isModImm());
8237 if (DP.isMatch())
8238 return MCTargetAsmParser::Match_Success;
8239 break;
8240 }
8241 case MCK_ModImmNeg: {
8242 DiagnosticPredicate DP(Operand.isModImmNeg());
8243 if (DP.isMatch())
8244 return MCTargetAsmParser::Match_Success;
8245 break;
8246 }
8247 case MCK_ModImmNot: {
8248 DiagnosticPredicate DP(Operand.isModImmNot());
8249 if (DP.isMatch())
8250 return MCTargetAsmParser::Match_Success;
8251 break;
8252 }
8253 case MCK_MveSaturate: {
8254 DiagnosticPredicate DP(Operand.isMveSaturateOp());
8255 if (DP.isMatch())
8256 return MCTargetAsmParser::Match_Success;
8257 if (DP.isNearMatch())
8258 return ARMAsmParser::Match_MveSaturate;
8259 break;
8260 }
8261 case MCK_PKHASRImm: {
8262 DiagnosticPredicate DP(Operand.isPKHASRImm());
8263 if (DP.isMatch())
8264 return MCTargetAsmParser::Match_Success;
8265 break;
8266 }
8267 case MCK_PKHLSLImm: {
8268 DiagnosticPredicate DP(Operand.isImmediate<0,31>());
8269 if (DP.isMatch())
8270 return MCTargetAsmParser::Match_Success;
8271 if (DP.isNearMatch())
8272 return ARMAsmParser::Match_PKHLSLImm;
8273 break;
8274 }
8275 case MCK_PostIdxImm8: {
8276 DiagnosticPredicate DP(Operand.isPostIdxImm8());
8277 if (DP.isMatch())
8278 return MCTargetAsmParser::Match_Success;
8279 break;
8280 }
8281 case MCK_PostIdxImm8s4: {
8282 DiagnosticPredicate DP(Operand.isPostIdxImm8s4());
8283 if (DP.isMatch())
8284 return MCTargetAsmParser::Match_Success;
8285 break;
8286 }
8287 case MCK_PostIdxReg: {
8288 DiagnosticPredicate DP(Operand.isPostIdxReg());
8289 if (DP.isMatch())
8290 return MCTargetAsmParser::Match_Success;
8291 break;
8292 }
8293 case MCK_PostIdxRegShifted: {
8294 DiagnosticPredicate DP(Operand.isPostIdxRegShifted());
8295 if (DP.isMatch())
8296 return MCTargetAsmParser::Match_Success;
8297 break;
8298 }
8299 case MCK_ProcIFlags: {
8300 DiagnosticPredicate DP(Operand.isProcIFlags());
8301 if (DP.isMatch())
8302 return MCTargetAsmParser::Match_Success;
8303 break;
8304 }
8305 case MCK_RegList: {
8306 DiagnosticPredicate DP(Operand.isRegList());
8307 if (DP.isMatch())
8308 return MCTargetAsmParser::Match_Success;
8309 break;
8310 }
8311 case MCK_RegListWithAPSR: {
8312 DiagnosticPredicate DP(Operand.isRegListWithAPSR());
8313 if (DP.isMatch())
8314 return MCTargetAsmParser::Match_Success;
8315 break;
8316 }
8317 case MCK_RotImm: {
8318 DiagnosticPredicate DP(Operand.isRotImm());
8319 if (DP.isMatch())
8320 return MCTargetAsmParser::Match_Success;
8321 break;
8322 }
8323 case MCK_SPRRegList: {
8324 DiagnosticPredicate DP(Operand.isSPRRegList());
8325 if (DP.isMatch())
8326 return MCTargetAsmParser::Match_Success;
8327 if (DP.isNearMatch())
8328 return ARMAsmParser::Match_SPRRegList;
8329 break;
8330 }
8331 case MCK_SetEndImm: {
8332 DiagnosticPredicate DP(Operand.isImmediate<0,1>());
8333 if (DP.isMatch())
8334 return MCTargetAsmParser::Match_Success;
8335 if (DP.isNearMatch())
8336 return ARMAsmParser::Match_SetEndImm;
8337 break;
8338 }
8339 case MCK_RegShiftedImm: {
8340 DiagnosticPredicate DP(Operand.isRegShiftedImm());
8341 if (DP.isMatch())
8342 return MCTargetAsmParser::Match_Success;
8343 break;
8344 }
8345 case MCK_RegShiftedReg: {
8346 DiagnosticPredicate DP(Operand.isRegShiftedReg());
8347 if (DP.isMatch())
8348 return MCTargetAsmParser::Match_Success;
8349 break;
8350 }
8351 case MCK_ShifterImm: {
8352 DiagnosticPredicate DP(Operand.isShifterImm());
8353 if (DP.isMatch())
8354 return MCTargetAsmParser::Match_Success;
8355 break;
8356 }
8357 case MCK_ThumbBranchTarget: {
8358 DiagnosticPredicate DP(Operand.isThumbBranchTarget());
8359 if (DP.isMatch())
8360 return MCTargetAsmParser::Match_Success;
8361 break;
8362 }
8363 case MCK_ThumbMemPC: {
8364 DiagnosticPredicate DP(Operand.isThumbMemPC());
8365 if (DP.isMatch())
8366 return MCTargetAsmParser::Match_Success;
8367 break;
8368 }
8369 case MCK_ThumbModImmNeg1_7: {
8370 DiagnosticPredicate DP(Operand.isThumbModImmNeg1_7());
8371 if (DP.isMatch())
8372 return MCTargetAsmParser::Match_Success;
8373 break;
8374 }
8375 case MCK_ThumbModImmNeg8_255: {
8376 DiagnosticPredicate DP(Operand.isThumbModImmNeg8_255());
8377 if (DP.isMatch())
8378 return MCTargetAsmParser::Match_Success;
8379 break;
8380 }
8381 case MCK_ImmThumbSR: {
8382 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
8383 if (DP.isMatch())
8384 return MCTargetAsmParser::Match_Success;
8385 if (DP.isNearMatch())
8386 return ARMAsmParser::Match_ImmThumbSR;
8387 break;
8388 }
8389 case MCK_TraceSyncBarrierOpt: {
8390 DiagnosticPredicate DP(Operand.isTraceSyncBarrierOpt());
8391 if (DP.isMatch())
8392 return MCTargetAsmParser::Match_Success;
8393 break;
8394 }
8395 case MCK_UnsignedOffset_b8s2: {
8396 DiagnosticPredicate DP(Operand.isUnsignedOffset<8, 2>());
8397 if (DP.isMatch())
8398 return MCTargetAsmParser::Match_Success;
8399 break;
8400 }
8401 case MCK_VPTPredN: {
8402 DiagnosticPredicate DP(Operand.isVPTPred());
8403 if (DP.isMatch())
8404 return MCTargetAsmParser::Match_Success;
8405 break;
8406 }
8407 case MCK_VPTPredR: {
8408 DiagnosticPredicate DP(Operand.isVPTPred());
8409 if (DP.isMatch())
8410 return MCTargetAsmParser::Match_Success;
8411 break;
8412 }
8413 case MCK_VecListTwoMQ: {
8414 DiagnosticPredicate DP(Operand.isVecListTwoMQ());
8415 if (DP.isMatch())
8416 return MCTargetAsmParser::Match_Success;
8417 if (DP.isNearMatch())
8418 return ARMAsmParser::Match_VecListTwoMQ;
8419 break;
8420 }
8421 case MCK_VecListFourMQ: {
8422 DiagnosticPredicate DP(Operand.isVecListFourMQ());
8423 if (DP.isMatch())
8424 return MCTargetAsmParser::Match_Success;
8425 if (DP.isNearMatch())
8426 return ARMAsmParser::Match_VecListFourMQ;
8427 break;
8428 }
8429 case MCK_VecListDPairAllLanes: {
8430 DiagnosticPredicate DP(Operand.isVecListDPairAllLanes());
8431 if (DP.isMatch())
8432 return MCTargetAsmParser::Match_Success;
8433 break;
8434 }
8435 case MCK_VecListDPair: {
8436 DiagnosticPredicate DP(Operand.isVecListDPair());
8437 if (DP.isMatch())
8438 return MCTargetAsmParser::Match_Success;
8439 break;
8440 }
8441 case MCK_VecListDPairSpacedAllLanes: {
8442 DiagnosticPredicate DP(Operand.isVecListDPairSpacedAllLanes());
8443 if (DP.isMatch())
8444 return MCTargetAsmParser::Match_Success;
8445 break;
8446 }
8447 case MCK_VecListDPairSpaced: {
8448 DiagnosticPredicate DP(Operand.isVecListDPairSpaced());
8449 if (DP.isMatch())
8450 return MCTargetAsmParser::Match_Success;
8451 break;
8452 }
8453 case MCK_VecListFourDAllLanes: {
8454 DiagnosticPredicate DP(Operand.isVecListFourDAllLanes());
8455 if (DP.isMatch())
8456 return MCTargetAsmParser::Match_Success;
8457 break;
8458 }
8459 case MCK_VecListFourD: {
8460 DiagnosticPredicate DP(Operand.isVecListFourD());
8461 if (DP.isMatch())
8462 return MCTargetAsmParser::Match_Success;
8463 break;
8464 }
8465 case MCK_VecListFourDByteIndexed: {
8466 DiagnosticPredicate DP(Operand.isVecListFourDByteIndexed());
8467 if (DP.isMatch())
8468 return MCTargetAsmParser::Match_Success;
8469 break;
8470 }
8471 case MCK_VecListFourDHWordIndexed: {
8472 DiagnosticPredicate DP(Operand.isVecListFourDHWordIndexed());
8473 if (DP.isMatch())
8474 return MCTargetAsmParser::Match_Success;
8475 break;
8476 }
8477 case MCK_VecListFourDWordIndexed: {
8478 DiagnosticPredicate DP(Operand.isVecListFourDWordIndexed());
8479 if (DP.isMatch())
8480 return MCTargetAsmParser::Match_Success;
8481 break;
8482 }
8483 case MCK_VecListFourQAllLanes: {
8484 DiagnosticPredicate DP(Operand.isVecListFourQAllLanes());
8485 if (DP.isMatch())
8486 return MCTargetAsmParser::Match_Success;
8487 break;
8488 }
8489 case MCK_VecListFourQ: {
8490 DiagnosticPredicate DP(Operand.isVecListFourQ());
8491 if (DP.isMatch())
8492 return MCTargetAsmParser::Match_Success;
8493 break;
8494 }
8495 case MCK_VecListFourQHWordIndexed: {
8496 DiagnosticPredicate DP(Operand.isVecListFourQHWordIndexed());
8497 if (DP.isMatch())
8498 return MCTargetAsmParser::Match_Success;
8499 break;
8500 }
8501 case MCK_VecListFourQWordIndexed: {
8502 DiagnosticPredicate DP(Operand.isVecListFourQWordIndexed());
8503 if (DP.isMatch())
8504 return MCTargetAsmParser::Match_Success;
8505 break;
8506 }
8507 case MCK_VecListOneDAllLanes: {
8508 DiagnosticPredicate DP(Operand.isVecListOneDAllLanes());
8509 if (DP.isMatch())
8510 return MCTargetAsmParser::Match_Success;
8511 break;
8512 }
8513 case MCK_VecListOneD: {
8514 DiagnosticPredicate DP(Operand.isVecListOneD());
8515 if (DP.isMatch())
8516 return MCTargetAsmParser::Match_Success;
8517 break;
8518 }
8519 case MCK_VecListOneDByteIndexed: {
8520 DiagnosticPredicate DP(Operand.isVecListOneDByteIndexed());
8521 if (DP.isMatch())
8522 return MCTargetAsmParser::Match_Success;
8523 break;
8524 }
8525 case MCK_VecListOneDHWordIndexed: {
8526 DiagnosticPredicate DP(Operand.isVecListOneDHWordIndexed());
8527 if (DP.isMatch())
8528 return MCTargetAsmParser::Match_Success;
8529 break;
8530 }
8531 case MCK_VecListOneDWordIndexed: {
8532 DiagnosticPredicate DP(Operand.isVecListOneDWordIndexed());
8533 if (DP.isMatch())
8534 return MCTargetAsmParser::Match_Success;
8535 break;
8536 }
8537 case MCK_VecListThreeDAllLanes: {
8538 DiagnosticPredicate DP(Operand.isVecListThreeDAllLanes());
8539 if (DP.isMatch())
8540 return MCTargetAsmParser::Match_Success;
8541 break;
8542 }
8543 case MCK_VecListThreeD: {
8544 DiagnosticPredicate DP(Operand.isVecListThreeD());
8545 if (DP.isMatch())
8546 return MCTargetAsmParser::Match_Success;
8547 break;
8548 }
8549 case MCK_VecListThreeDByteIndexed: {
8550 DiagnosticPredicate DP(Operand.isVecListThreeDByteIndexed());
8551 if (DP.isMatch())
8552 return MCTargetAsmParser::Match_Success;
8553 break;
8554 }
8555 case MCK_VecListThreeDHWordIndexed: {
8556 DiagnosticPredicate DP(Operand.isVecListThreeDHWordIndexed());
8557 if (DP.isMatch())
8558 return MCTargetAsmParser::Match_Success;
8559 break;
8560 }
8561 case MCK_VecListThreeDWordIndexed: {
8562 DiagnosticPredicate DP(Operand.isVecListThreeDWordIndexed());
8563 if (DP.isMatch())
8564 return MCTargetAsmParser::Match_Success;
8565 break;
8566 }
8567 case MCK_VecListThreeQAllLanes: {
8568 DiagnosticPredicate DP(Operand.isVecListThreeQAllLanes());
8569 if (DP.isMatch())
8570 return MCTargetAsmParser::Match_Success;
8571 break;
8572 }
8573 case MCK_VecListThreeQ: {
8574 DiagnosticPredicate DP(Operand.isVecListThreeQ());
8575 if (DP.isMatch())
8576 return MCTargetAsmParser::Match_Success;
8577 break;
8578 }
8579 case MCK_VecListThreeQHWordIndexed: {
8580 DiagnosticPredicate DP(Operand.isVecListThreeQHWordIndexed());
8581 if (DP.isMatch())
8582 return MCTargetAsmParser::Match_Success;
8583 break;
8584 }
8585 case MCK_VecListThreeQWordIndexed: {
8586 DiagnosticPredicate DP(Operand.isVecListThreeQWordIndexed());
8587 if (DP.isMatch())
8588 return MCTargetAsmParser::Match_Success;
8589 break;
8590 }
8591 case MCK_VecListTwoDByteIndexed: {
8592 DiagnosticPredicate DP(Operand.isVecListTwoDByteIndexed());
8593 if (DP.isMatch())
8594 return MCTargetAsmParser::Match_Success;
8595 break;
8596 }
8597 case MCK_VecListTwoDHWordIndexed: {
8598 DiagnosticPredicate DP(Operand.isVecListTwoDHWordIndexed());
8599 if (DP.isMatch())
8600 return MCTargetAsmParser::Match_Success;
8601 break;
8602 }
8603 case MCK_VecListTwoDWordIndexed: {
8604 DiagnosticPredicate DP(Operand.isVecListTwoDWordIndexed());
8605 if (DP.isMatch())
8606 return MCTargetAsmParser::Match_Success;
8607 break;
8608 }
8609 case MCK_VecListTwoQHWordIndexed: {
8610 DiagnosticPredicate DP(Operand.isVecListTwoQHWordIndexed());
8611 if (DP.isMatch())
8612 return MCTargetAsmParser::Match_Success;
8613 break;
8614 }
8615 case MCK_VecListTwoQWordIndexed: {
8616 DiagnosticPredicate DP(Operand.isVecListTwoQWordIndexed());
8617 if (DP.isMatch())
8618 return MCTargetAsmParser::Match_Success;
8619 break;
8620 }
8621 case MCK_VectorIndex16: {
8622 DiagnosticPredicate DP(Operand.isVectorIndex16());
8623 if (DP.isMatch())
8624 return MCTargetAsmParser::Match_Success;
8625 break;
8626 }
8627 case MCK_VectorIndex32: {
8628 DiagnosticPredicate DP(Operand.isVectorIndex32());
8629 if (DP.isMatch())
8630 return MCTargetAsmParser::Match_Success;
8631 break;
8632 }
8633 case MCK_VectorIndex64: {
8634 DiagnosticPredicate DP(Operand.isVectorIndex64());
8635 if (DP.isMatch())
8636 return MCTargetAsmParser::Match_Success;
8637 break;
8638 }
8639 case MCK_VectorIndex8: {
8640 DiagnosticPredicate DP(Operand.isVectorIndex8());
8641 if (DP.isMatch())
8642 return MCTargetAsmParser::Match_Success;
8643 break;
8644 }
8645 case MCK_MemTBB: {
8646 DiagnosticPredicate DP(Operand.isMemTBB());
8647 if (DP.isMatch())
8648 return MCTargetAsmParser::Match_Success;
8649 break;
8650 }
8651 case MCK_MemTBH: {
8652 DiagnosticPredicate DP(Operand.isMemTBH());
8653 if (DP.isMatch())
8654 return MCTargetAsmParser::Match_Success;
8655 break;
8656 }
8657 case MCK_MVEPairVectorIndex0: {
8658 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<0, 1>());
8659 if (DP.isMatch())
8660 return MCTargetAsmParser::Match_Success;
8661 break;
8662 }
8663 case MCK_MVEPairVectorIndex2: {
8664 DiagnosticPredicate DP(Operand.isMVEPairVectorIndex<2, 3>());
8665 if (DP.isMatch())
8666 return MCTargetAsmParser::Match_Success;
8667 break;
8668 }
8669 case MCK_ComplexRotationEven: {
8670 DiagnosticPredicate DP(Operand.isComplexRotation<90, 0>());
8671 if (DP.isMatch())
8672 return MCTargetAsmParser::Match_Success;
8673 if (DP.isNearMatch())
8674 return ARMAsmParser::Match_ComplexRotationEven;
8675 break;
8676 }
8677 case MCK_ComplexRotationOdd: {
8678 DiagnosticPredicate DP(Operand.isComplexRotation<180, 90>());
8679 if (DP.isMatch())
8680 return MCTargetAsmParser::Match_Success;
8681 if (DP.isNearMatch())
8682 return ARMAsmParser::Match_ComplexRotationOdd;
8683 break;
8684 }
8685 case MCK_NEONi16vmovi8Replicate: {
8686 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 16>());
8687 if (DP.isMatch())
8688 return MCTargetAsmParser::Match_Success;
8689 break;
8690 }
8691 case MCK_NEONi16invi8Replicate: {
8692 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 16>());
8693 if (DP.isMatch())
8694 return MCTargetAsmParser::Match_Success;
8695 break;
8696 }
8697 case MCK_NEONi32vmovi8Replicate: {
8698 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 32>());
8699 if (DP.isMatch())
8700 return MCTargetAsmParser::Match_Success;
8701 break;
8702 }
8703 case MCK_NEONi32invi8Replicate: {
8704 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 32>());
8705 if (DP.isMatch())
8706 return MCTargetAsmParser::Match_Success;
8707 break;
8708 }
8709 case MCK_NEONi64vmovi8Replicate: {
8710 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 64>());
8711 if (DP.isMatch())
8712 return MCTargetAsmParser::Match_Success;
8713 break;
8714 }
8715 case MCK_NEONi64invi8Replicate: {
8716 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 64>());
8717 if (DP.isMatch())
8718 return MCTargetAsmParser::Match_Success;
8719 break;
8720 }
8721 case MCK_NEONi32vmovi16Replicate: {
8722 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 32>());
8723 if (DP.isMatch())
8724 return MCTargetAsmParser::Match_Success;
8725 break;
8726 }
8727 case MCK_NEONi64vmovi16Replicate: {
8728 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 64>());
8729 if (DP.isMatch())
8730 return MCTargetAsmParser::Match_Success;
8731 break;
8732 }
8733 case MCK_NEONi64vmovi32Replicate: {
8734 DiagnosticPredicate DP(Operand.isNEONmovReplicate<32, 64>());
8735 if (DP.isMatch())
8736 return MCTargetAsmParser::Match_Success;
8737 break;
8738 }
8739 case MCK_MVEVectorIndex4: {
8740 DiagnosticPredicate DP(Operand.isVectorIndexInRange<4>());
8741 if (DP.isMatch())
8742 return MCTargetAsmParser::Match_Success;
8743 break;
8744 }
8745 case MCK_MVEVectorIndex8: {
8746 DiagnosticPredicate DP(Operand.isVectorIndexInRange<8>());
8747 if (DP.isMatch())
8748 return MCTargetAsmParser::Match_Success;
8749 break;
8750 }
8751 case MCK_MVEVectorIndex16: {
8752 DiagnosticPredicate DP(Operand.isVectorIndexInRange<16>());
8753 if (DP.isMatch())
8754 return MCTargetAsmParser::Match_Success;
8755 break;
8756 }
8757 case MCK_MVEVcvtImm32: {
8758 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
8759 if (DP.isMatch())
8760 return MCTargetAsmParser::Match_Success;
8761 if (DP.isNearMatch())
8762 return ARMAsmParser::Match_MVEVcvtImm32;
8763 break;
8764 }
8765 case MCK_MVEVcvtImm16: {
8766 DiagnosticPredicate DP(Operand.isImmediate<1,16>());
8767 if (DP.isMatch())
8768 return MCTargetAsmParser::Match_Success;
8769 if (DP.isNearMatch())
8770 return ARMAsmParser::Match_MVEVcvtImm16;
8771 break;
8772 }
8773 case MCK_TMemImm7Shift2Offset: {
8774 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::tGPRRegClassID>());
8775 if (DP.isMatch())
8776 return MCTargetAsmParser::Match_Success;
8777 break;
8778 }
8779 case MCK_TMemImm7Shift0Offset: {
8780 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::tGPRRegClassID>());
8781 if (DP.isMatch())
8782 return MCTargetAsmParser::Match_Success;
8783 break;
8784 }
8785 case MCK_TMemImm7Shift1Offset: {
8786 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::tGPRRegClassID>());
8787 if (DP.isMatch())
8788 return MCTargetAsmParser::Match_Success;
8789 break;
8790 }
8791 case MCK_Imm3b: {
8792 DiagnosticPredicate DP(Operand.isImmediate<0,7>());
8793 if (DP.isMatch())
8794 return MCTargetAsmParser::Match_Success;
8795 if (DP.isNearMatch())
8796 return ARMAsmParser::Match_Imm3b;
8797 break;
8798 }
8799 case MCK_Imm4b: {
8800 DiagnosticPredicate DP(Operand.isImmediate<0,15>());
8801 if (DP.isMatch())
8802 return MCTargetAsmParser::Match_Success;
8803 if (DP.isNearMatch())
8804 return ARMAsmParser::Match_Imm4b;
8805 break;
8806 }
8807 case MCK_Imm6b: {
8808 DiagnosticPredicate DP(Operand.isImmediate<0,63>());
8809 if (DP.isMatch())
8810 return MCTargetAsmParser::Match_Success;
8811 if (DP.isNearMatch())
8812 return ARMAsmParser::Match_Imm6b;
8813 break;
8814 }
8815 case MCK_Imm7b: {
8816 DiagnosticPredicate DP(Operand.isImmediate<0,127>());
8817 if (DP.isMatch())
8818 return MCTargetAsmParser::Match_Success;
8819 if (DP.isNearMatch())
8820 return ARMAsmParser::Match_Imm7b;
8821 break;
8822 }
8823 case MCK_Imm9b: {
8824 DiagnosticPredicate DP(Operand.isImmediate<0,511>());
8825 if (DP.isMatch())
8826 return MCTargetAsmParser::Match_Success;
8827 if (DP.isNearMatch())
8828 return ARMAsmParser::Match_Imm9b;
8829 break;
8830 }
8831 case MCK_Imm11b: {
8832 DiagnosticPredicate DP(Operand.isImmediate<0,2047>());
8833 if (DP.isMatch())
8834 return MCTargetAsmParser::Match_Success;
8835 if (DP.isNearMatch())
8836 return ARMAsmParser::Match_Imm11b;
8837 break;
8838 }
8839 case MCK_Imm12b: {
8840 DiagnosticPredicate DP(Operand.isImmediate<0,4095>());
8841 if (DP.isMatch())
8842 return MCTargetAsmParser::Match_Success;
8843 if (DP.isNearMatch())
8844 return ARMAsmParser::Match_Imm12b;
8845 break;
8846 }
8847 case MCK_Imm13b: {
8848 DiagnosticPredicate DP(Operand.isImmediate<0,8191>());
8849 if (DP.isMatch())
8850 return MCTargetAsmParser::Match_Success;
8851 if (DP.isNearMatch())
8852 return ARMAsmParser::Match_Imm13b;
8853 break;
8854 }
8855 case MCK_ConstPoolAsmImm: {
8856 DiagnosticPredicate DP(Operand.isConstPoolAsmImm());
8857 if (DP.isMatch())
8858 return MCTargetAsmParser::Match_Success;
8859 break;
8860 }
8861 case MCK_FBits16: {
8862 DiagnosticPredicate DP(Operand.isFBits16());
8863 if (DP.isMatch())
8864 return MCTargetAsmParser::Match_Success;
8865 break;
8866 }
8867 case MCK_FBits32: {
8868 DiagnosticPredicate DP(Operand.isFBits32());
8869 if (DP.isMatch())
8870 return MCTargetAsmParser::Match_Success;
8871 break;
8872 }
8873 case MCK_Imm0_4095: {
8874 DiagnosticPredicate DP(Operand.isImmediate<0,4095>());
8875 if (DP.isMatch())
8876 return MCTargetAsmParser::Match_Success;
8877 if (DP.isNearMatch())
8878 return ARMAsmParser::Match_Imm0_4095;
8879 break;
8880 }
8881 case MCK_Imm0_4095Neg: {
8882 DiagnosticPredicate DP(Operand.isImm0_4095Neg());
8883 if (DP.isMatch())
8884 return MCTargetAsmParser::Match_Success;
8885 break;
8886 }
8887 case MCK_ITMask: {
8888 DiagnosticPredicate DP(Operand.isITMask());
8889 if (DP.isMatch())
8890 return MCTargetAsmParser::Match_Success;
8891 break;
8892 }
8893 case MCK_ITCondCode: {
8894 DiagnosticPredicate DP(Operand.isITCondCode());
8895 if (DP.isMatch())
8896 return MCTargetAsmParser::Match_Success;
8897 break;
8898 }
8899 case MCK_LELabel: {
8900 DiagnosticPredicate DP(Operand.isLEOffset());
8901 if (DP.isMatch())
8902 return MCTargetAsmParser::Match_Success;
8903 if (DP.isNearMatch())
8904 return ARMAsmParser::Match_LELabel;
8905 break;
8906 }
8907 case MCK_MVELongShift: {
8908 DiagnosticPredicate DP(Operand.isMVELongShift());
8909 if (DP.isMatch())
8910 return MCTargetAsmParser::Match_Success;
8911 if (DP.isNearMatch())
8912 return ARMAsmParser::Match_MVELongShift;
8913 break;
8914 }
8915 case MCK_NEONi16splat: {
8916 DiagnosticPredicate DP(Operand.isNEONi16splat());
8917 if (DP.isMatch())
8918 return MCTargetAsmParser::Match_Success;
8919 break;
8920 }
8921 case MCK_NEONi32splat: {
8922 DiagnosticPredicate DP(Operand.isNEONi32splat());
8923 if (DP.isMatch())
8924 return MCTargetAsmParser::Match_Success;
8925 break;
8926 }
8927 case MCK_NEONi64splat: {
8928 DiagnosticPredicate DP(Operand.isNEONi64splat());
8929 if (DP.isMatch())
8930 return MCTargetAsmParser::Match_Success;
8931 break;
8932 }
8933 case MCK_NEONi8splat: {
8934 DiagnosticPredicate DP(Operand.isNEONi8splat());
8935 if (DP.isMatch())
8936 return MCTargetAsmParser::Match_Success;
8937 break;
8938 }
8939 case MCK_NEONi16splatNot: {
8940 DiagnosticPredicate DP(Operand.isNEONi16splatNot());
8941 if (DP.isMatch())
8942 return MCTargetAsmParser::Match_Success;
8943 break;
8944 }
8945 case MCK_NEONi32splatNot: {
8946 DiagnosticPredicate DP(Operand.isNEONi32splatNot());
8947 if (DP.isMatch())
8948 return MCTargetAsmParser::Match_Success;
8949 break;
8950 }
8951 case MCK_NEONi32vmov: {
8952 DiagnosticPredicate DP(Operand.isNEONi32vmov());
8953 if (DP.isMatch())
8954 return MCTargetAsmParser::Match_Success;
8955 break;
8956 }
8957 case MCK_NEONi32vmovNeg: {
8958 DiagnosticPredicate DP(Operand.isNEONi32vmovNeg());
8959 if (DP.isMatch())
8960 return MCTargetAsmParser::Match_Success;
8961 break;
8962 }
8963 case MCK_CondCodeNoAL: {
8964 DiagnosticPredicate DP(Operand.isITCondCodeNoAL());
8965 if (DP.isMatch())
8966 return MCTargetAsmParser::Match_Success;
8967 break;
8968 }
8969 case MCK_CondCodeNoALInv: {
8970 DiagnosticPredicate DP(Operand.isITCondCodeNoAL());
8971 if (DP.isMatch())
8972 return MCTargetAsmParser::Match_Success;
8973 break;
8974 }
8975 case MCK_CondCodeRestrictedFP: {
8976 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedFP());
8977 if (DP.isMatch())
8978 return MCTargetAsmParser::Match_Success;
8979 if (DP.isNearMatch())
8980 return ARMAsmParser::Match_CondCodeRestrictedFP;
8981 break;
8982 }
8983 case MCK_CondCodeRestrictedI: {
8984 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedI());
8985 if (DP.isMatch())
8986 return MCTargetAsmParser::Match_Success;
8987 if (DP.isNearMatch())
8988 return ARMAsmParser::Match_CondCodeRestrictedI;
8989 break;
8990 }
8991 case MCK_CondCodeRestrictedS: {
8992 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedS());
8993 if (DP.isMatch())
8994 return MCTargetAsmParser::Match_Success;
8995 if (DP.isNearMatch())
8996 return ARMAsmParser::Match_CondCodeRestrictedS;
8997 break;
8998 }
8999 case MCK_CondCodeRestrictedU: {
9000 DiagnosticPredicate DP(Operand.isITCondCodeRestrictedU());
9001 if (DP.isMatch())
9002 return MCTargetAsmParser::Match_Success;
9003 if (DP.isNearMatch())
9004 return ARMAsmParser::Match_CondCodeRestrictedU;
9005 break;
9006 }
9007 case MCK_ShrImm16: {
9008 DiagnosticPredicate DP(Operand.isImmediate<1,16>());
9009 if (DP.isMatch())
9010 return MCTargetAsmParser::Match_Success;
9011 if (DP.isNearMatch())
9012 return ARMAsmParser::Match_ShrImm16;
9013 break;
9014 }
9015 case MCK_ShrImm32: {
9016 DiagnosticPredicate DP(Operand.isImmediate<1,32>());
9017 if (DP.isMatch())
9018 return MCTargetAsmParser::Match_Success;
9019 if (DP.isNearMatch())
9020 return ARMAsmParser::Match_ShrImm32;
9021 break;
9022 }
9023 case MCK_ShrImm64: {
9024 DiagnosticPredicate DP(Operand.isImmediate<1,64>());
9025 if (DP.isMatch())
9026 return MCTargetAsmParser::Match_Success;
9027 if (DP.isNearMatch())
9028 return ARMAsmParser::Match_ShrImm64;
9029 break;
9030 }
9031 case MCK_ShrImm8: {
9032 DiagnosticPredicate DP(Operand.isImmediate<1,8>());
9033 if (DP.isMatch())
9034 return MCTargetAsmParser::Match_Success;
9035 if (DP.isNearMatch())
9036 return ARMAsmParser::Match_ShrImm8;
9037 break;
9038 }
9039 case MCK_T2SOImm: {
9040 DiagnosticPredicate DP(Operand.isT2SOImm());
9041 if (DP.isMatch())
9042 return MCTargetAsmParser::Match_Success;
9043 break;
9044 }
9045 case MCK_T2SOImmNeg: {
9046 DiagnosticPredicate DP(Operand.isT2SOImmNeg());
9047 if (DP.isMatch())
9048 return MCTargetAsmParser::Match_Success;
9049 break;
9050 }
9051 case MCK_T2SOImmNot: {
9052 DiagnosticPredicate DP(Operand.isT2SOImmNot());
9053 if (DP.isMatch())
9054 return MCTargetAsmParser::Match_Success;
9055 break;
9056 }
9057 case MCK_MemUImm12Offset: {
9058 DiagnosticPredicate DP(Operand.isMemUImm12Offset());
9059 if (DP.isMatch())
9060 return MCTargetAsmParser::Match_Success;
9061 break;
9062 }
9063 case MCK_T2MemRegOffset: {
9064 DiagnosticPredicate DP(Operand.isT2MemRegOffset());
9065 if (DP.isMatch())
9066 return MCTargetAsmParser::Match_Success;
9067 break;
9068 }
9069 case MCK_Imm7s4: {
9070 DiagnosticPredicate DP(Operand.isImm7s4());
9071 if (DP.isMatch())
9072 return MCTargetAsmParser::Match_Success;
9073 break;
9074 }
9075 case MCK_Imm7Shift0: {
9076 DiagnosticPredicate DP(Operand.isImm7Shift0());
9077 if (DP.isMatch())
9078 return MCTargetAsmParser::Match_Success;
9079 break;
9080 }
9081 case MCK_Imm7Shift1: {
9082 DiagnosticPredicate DP(Operand.isImm7Shift1());
9083 if (DP.isMatch())
9084 return MCTargetAsmParser::Match_Success;
9085 break;
9086 }
9087 case MCK_Imm7Shift2: {
9088 DiagnosticPredicate DP(Operand.isImm7Shift2());
9089 if (DP.isMatch())
9090 return MCTargetAsmParser::Match_Success;
9091 break;
9092 }
9093 case MCK_Imm8s4: {
9094 DiagnosticPredicate DP(Operand.isImm8s4());
9095 if (DP.isMatch())
9096 return MCTargetAsmParser::Match_Success;
9097 break;
9098 }
9099 case MCK_MemPCRelImm12: {
9100 DiagnosticPredicate DP(Operand.isMemPCRelImm12());
9101 if (DP.isMatch())
9102 return MCTargetAsmParser::Match_Success;
9103 break;
9104 }
9105 case MCK_MemThumbRIs1: {
9106 DiagnosticPredicate DP(Operand.isMemThumbRIs1());
9107 if (DP.isMatch())
9108 return MCTargetAsmParser::Match_Success;
9109 break;
9110 }
9111 case MCK_MemThumbRIs2: {
9112 DiagnosticPredicate DP(Operand.isMemThumbRIs2());
9113 if (DP.isMatch())
9114 return MCTargetAsmParser::Match_Success;
9115 break;
9116 }
9117 case MCK_MemThumbRIs4: {
9118 DiagnosticPredicate DP(Operand.isMemThumbRIs4());
9119 if (DP.isMatch())
9120 return MCTargetAsmParser::Match_Success;
9121 break;
9122 }
9123 case MCK_MemThumbRR: {
9124 DiagnosticPredicate DP(Operand.isMemThumbRR());
9125 if (DP.isMatch())
9126 return MCTargetAsmParser::Match_Success;
9127 break;
9128 }
9129 case MCK_MemThumbSPI: {
9130 DiagnosticPredicate DP(Operand.isMemThumbSPI());
9131 if (DP.isMatch())
9132 return MCTargetAsmParser::Match_Success;
9133 break;
9134 }
9135 case MCK_Imm0_1020s4: {
9136 DiagnosticPredicate DP(Operand.isImm0_1020s4());
9137 if (DP.isMatch())
9138 return MCTargetAsmParser::Match_Success;
9139 break;
9140 }
9141 case MCK_Imm0_508s4: {
9142 DiagnosticPredicate DP(Operand.isImm0_508s4());
9143 if (DP.isMatch())
9144 return MCTargetAsmParser::Match_Success;
9145 break;
9146 }
9147 case MCK_Imm0_508s4Neg: {
9148 DiagnosticPredicate DP(Operand.isImm0_508s4Neg());
9149 if (DP.isMatch())
9150 return MCTargetAsmParser::Match_Success;
9151 break;
9152 }
9153 case MCK_WLSLabel: {
9154 DiagnosticPredicate DP(Operand.isUnsignedOffset<11, 1>());
9155 if (DP.isMatch())
9156 return MCTargetAsmParser::Match_Success;
9157 if (DP.isNearMatch())
9158 return ARMAsmParser::Match_WLSLabel;
9159 break;
9160 }
9161 } // end switch (Kind)
9162
9163 if (Kind > MCK_LAST_REGISTER && Kind <= MCK_LAST_REGCLASS_BY_HWMODE) {
9164 static constexpr MatchClassKind RegClassByHwModeMatchTable[2][1] = {
9165 { // DefaultMode
9166 MCK_GPR, // arm_ptr_rc
9167 },
9168 { // Thumb1OnlyMode
9169 MCK_tGPR, // arm_ptr_rc
9170 },
9171 };
9172
9173 static_assert(MCK_LAST_REGCLASS_BY_HWMODE - MCK_LAST_REGISTER == 1);
9174 const unsigned HwMode = STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo);
9175 Kind = RegClassByHwModeMatchTable[HwMode][Kind - (MCK_LAST_REGISTER + 1)];
9176 }
9177
9178 if (Operand.isReg()) {
9179 static constexpr uint16_t Table[ARM::NUM_TARGET_REGS] = {
9180 InvalidMatchClass,
9181 MCK_APSR,
9182 MCK_APSR_NZCV,
9183 MCK_CCR,
9184 MCK_FPCXTRegs,
9185 MCK_FPCXTS,
9186 MCK_FPEXC,
9187 MCK_FPINST,
9188 MCK_FPSCR,
9189 MCK_cl_FPSCR_NZCV,
9190 MCK_FPSCR_NZCVQC,
9191 InvalidMatchClass,
9192 MCK_FPSID,
9193 InvalidMatchClass,
9194 MCK_GPRlr,
9195 MCK_PC,
9196 InvalidMatchClass,
9197 MCK_GPRsp,
9198 MCK_SPSR,
9199 MCK_VCCR,
9200 MCK_GPRwithZRnosp,
9201 MCK_DPR_8,
9202 MCK_DPR_8,
9203 MCK_DPR_8,
9204 MCK_DPR_8,
9205 MCK_DPR_8,
9206 MCK_DPR_8,
9207 MCK_DPR_8,
9208 MCK_DPR_8,
9209 MCK_DPR_VFP2,
9210 MCK_DPR_VFP2,
9211 MCK_DPR_VFP2,
9212 MCK_DPR_VFP2,
9213 MCK_DPR_VFP2,
9214 MCK_DPR_VFP2,
9215 MCK_DPR_VFP2,
9216 MCK_DPR_VFP2,
9217 MCK_DPR,
9218 MCK_DPR,
9219 MCK_DPR,
9220 MCK_DPR,
9221 MCK_DPR,
9222 MCK_DPR,
9223 MCK_DPR,
9224 MCK_DPR,
9225 MCK_DPR,
9226 MCK_DPR,
9227 MCK_DPR,
9228 MCK_DPR,
9229 MCK_DPR,
9230 MCK_DPR,
9231 MCK_DPR,
9232 MCK_DPR,
9233 MCK_FPINST2,
9234 MCK_MVFR0,
9235 MCK_MVFR1,
9236 MCK_MVFR2,
9237 MCK_P0,
9238 MCK_QPR_8,
9239 MCK_QPR_8,
9240 MCK_QPR_8,
9241 MCK_QPR_8,
9242 MCK_MQPR,
9243 MCK_MQPR,
9244 MCK_MQPR,
9245 MCK_MQPR,
9246 MCK_QPR,
9247 MCK_QPR,
9248 MCK_QPR,
9249 MCK_QPR,
9250 MCK_QPR,
9251 MCK_QPR,
9252 MCK_QPR,
9253 MCK_QPR,
9254 MCK_Reg17,
9255 MCK_Reg22,
9256 MCK_Reg17,
9257 MCK_Reg22,
9258 MCK_Reg18,
9259 MCK_Reg23,
9260 MCK_Reg18,
9261 MCK_Reg23,
9262 MCK_Reg33,
9263 MCK_Reg35,
9264 MCK_Reg33,
9265 MCK_Reg35,
9266 MCK_R12,
9267 MCK_SPR_8,
9268 MCK_SPR_8,
9269 MCK_SPR_8,
9270 MCK_SPR_8,
9271 MCK_SPR_8,
9272 MCK_SPR_8,
9273 MCK_SPR_8,
9274 MCK_SPR_8,
9275 MCK_SPR_8,
9276 MCK_SPR_8,
9277 MCK_SPR_8,
9278 MCK_SPR_8,
9279 MCK_SPR_8,
9280 MCK_SPR_8,
9281 MCK_SPR_8,
9282 MCK_SPR_8,
9283 MCK_HPR,
9284 MCK_HPR,
9285 MCK_HPR,
9286 MCK_HPR,
9287 MCK_HPR,
9288 MCK_HPR,
9289 MCK_HPR,
9290 MCK_HPR,
9291 MCK_HPR,
9292 MCK_HPR,
9293 MCK_HPR,
9294 MCK_HPR,
9295 MCK_HPR,
9296 MCK_HPR,
9297 MCK_HPR,
9298 MCK_HPR,
9299 MCK_Reg73,
9300 MCK_Reg73,
9301 MCK_Reg73,
9302 MCK_Reg73,
9303 MCK_Reg73,
9304 MCK_Reg73,
9305 MCK_Reg74,
9306 MCK_Reg74,
9307 MCK_Reg75,
9308 MCK_Reg75,
9309 MCK_Reg75,
9310 MCK_Reg75,
9311 MCK_Reg75,
9312 MCK_Reg75,
9313 MCK_Reg76,
9314 MCK_Reg76,
9315 MCK_DPairSpc,
9316 MCK_DPairSpc,
9317 MCK_DPairSpc,
9318 MCK_DPairSpc,
9319 MCK_DPairSpc,
9320 MCK_DPairSpc,
9321 MCK_DPairSpc,
9322 MCK_DPairSpc,
9323 MCK_DPairSpc,
9324 MCK_DPairSpc,
9325 MCK_DPairSpc,
9326 MCK_DPairSpc,
9327 MCK_DPairSpc,
9328 MCK_DPairSpc,
9329 MCK_Reg78,
9330 MCK_Reg78,
9331 MCK_Reg78,
9332 MCK_Reg79,
9333 MCK_MQQPR,
9334 MCK_MQQPR,
9335 MCK_MQQPR,
9336 MCK_Reg81,
9337 MCK_QQPR,
9338 MCK_QQPR,
9339 MCK_QQPR,
9340 MCK_QQPR,
9341 MCK_QQPR,
9342 MCK_QQPR,
9343 MCK_QQPR,
9344 MCK_Reg92,
9345 MCK_Reg93,
9346 MCK_Reg94,
9347 MCK_Reg95,
9348 MCK_MQQQQPR,
9349 MCK_Reg97,
9350 MCK_Reg98,
9351 MCK_Reg99,
9352 MCK_QQQQPR,
9353 MCK_QQQQPR,
9354 MCK_QQQQPR,
9355 MCK_QQQQPR,
9356 MCK_QQQQPR,
9357 MCK_Reg101,
9358 MCK_Reg101,
9359 MCK_Reg102,
9360 MCK_Reg102,
9361 MCK_Reg106,
9362 MCK_Reg106,
9363 MCK_Reg108,
9364 MCK_Reg116,
9365 MCK_Reg121,
9366 MCK_Reg116,
9367 MCK_Reg121,
9368 MCK_Reg116,
9369 MCK_Reg121,
9370 MCK_Reg117,
9371 MCK_Reg122,
9372 MCK_Reg118,
9373 MCK_Reg123,
9374 MCK_Reg118,
9375 MCK_Reg123,
9376 MCK_Reg118,
9377 MCK_Reg123,
9378 MCK_Reg119,
9379 MCK_Reg124,
9380 MCK_Reg120,
9381 MCK_Reg125,
9382 MCK_Reg120,
9383 MCK_Reg125,
9384 MCK_Reg120,
9385 MCK_Reg125,
9386 MCK_Reg120,
9387 MCK_Reg125,
9388 MCK_Reg120,
9389 MCK_Reg125,
9390 MCK_Reg120,
9391 MCK_Reg125,
9392 MCK_Reg120,
9393 MCK_Reg125,
9394 MCK_Reg126,
9395 MCK_Reg126,
9396 MCK_Reg126,
9397 MCK_Reg126,
9398 MCK_Reg127,
9399 MCK_Reg127,
9400 MCK_Reg128,
9401 MCK_Reg128,
9402 MCK_Reg129,
9403 MCK_Reg129,
9404 MCK_Reg129,
9405 MCK_Reg129,
9406 MCK_Reg130,
9407 MCK_Reg130,
9408 MCK_Reg131,
9409 MCK_Reg131,
9410 MCK_DTripleSpc,
9411 MCK_DTripleSpc,
9412 MCK_DTripleSpc,
9413 MCK_DTripleSpc,
9414 MCK_DTripleSpc,
9415 MCK_DTripleSpc,
9416 MCK_DTripleSpc,
9417 MCK_DTripleSpc,
9418 MCK_DTripleSpc,
9419 MCK_DTripleSpc,
9420 MCK_DTripleSpc,
9421 MCK_DTripleSpc,
9422 InvalidMatchClass,
9423 InvalidMatchClass,
9424 InvalidMatchClass,
9425 InvalidMatchClass,
9426 InvalidMatchClass,
9427 InvalidMatchClass,
9428 InvalidMatchClass,
9429 InvalidMatchClass,
9430 InvalidMatchClass,
9431 InvalidMatchClass,
9432 InvalidMatchClass,
9433 InvalidMatchClass,
9434 InvalidMatchClass,
9435 InvalidMatchClass,
9436 InvalidMatchClass,
9437 InvalidMatchClass,
9438 InvalidMatchClass,
9439 InvalidMatchClass,
9440 InvalidMatchClass,
9441 InvalidMatchClass,
9442 InvalidMatchClass,
9443 InvalidMatchClass,
9444 InvalidMatchClass,
9445 InvalidMatchClass,
9446 InvalidMatchClass,
9447 InvalidMatchClass,
9448 MCK_Reg52,
9449 MCK_Reg52,
9450 MCK_Reg52,
9451 MCK_Reg53,
9452 MCK_Reg50,
9453 MCK_Reg50,
9454 MCK_Reg50,
9455 MCK_Reg51,
9456 MCK_DPair,
9457 MCK_DPair,
9458 MCK_DPair,
9459 MCK_DPair,
9460 MCK_DPair,
9461 MCK_DPair,
9462 MCK_DPair,
9463 MCK_Reg133,
9464 MCK_Reg133,
9465 MCK_Reg134,
9466 MCK_Reg135,
9467 MCK_Reg136,
9468 MCK_Reg136,
9469 MCK_Reg137,
9470 MCK_Reg138,
9471 MCK_Reg139,
9472 MCK_Reg139,
9473 MCK_Reg139,
9474 MCK_Reg139,
9475 MCK_Reg139,
9476 MCK_Reg139,
9477 };
9478
9479 MCRegister Reg = Operand.getReg();
9480 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
9481 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
9482 getDiagKindFromRegisterClass(Kind);
9483 }
9484
9485 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
9486 return getDiagKindFromRegisterClass(Kind);
9487
9488 return MCTargetAsmParser::Match_InvalidOperand;
9489}
9490
9491#ifndef NDEBUG
9492const char *getMatchClassName(MatchClassKind Kind) {
9493 switch (Kind) {
9494 case InvalidMatchClass: return "InvalidMatchClass";
9495 case OptionalMatchClass: return "OptionalMatchClass";
9496 case MCK__DOT_d: return "MCK__DOT_d";
9497 case MCK__DOT_f: return "MCK__DOT_f";
9498 case MCK__DOT_s16: return "MCK__DOT_s16";
9499 case MCK__DOT_s32: return "MCK__DOT_s32";
9500 case MCK__DOT_s64: return "MCK__DOT_s64";
9501 case MCK__DOT_s8: return "MCK__DOT_s8";
9502 case MCK__DOT_u16: return "MCK__DOT_u16";
9503 case MCK__DOT_u32: return "MCK__DOT_u32";
9504 case MCK__DOT_u64: return "MCK__DOT_u64";
9505 case MCK__DOT_u8: return "MCK__DOT_u8";
9506 case MCK__DOT_f32: return "MCK__DOT_f32";
9507 case MCK__DOT_f64: return "MCK__DOT_f64";
9508 case MCK__DOT_i16: return "MCK__DOT_i16";
9509 case MCK__DOT_i32: return "MCK__DOT_i32";
9510 case MCK__DOT_i64: return "MCK__DOT_i64";
9511 case MCK__DOT_i8: return "MCK__DOT_i8";
9512 case MCK__DOT_p16: return "MCK__DOT_p16";
9513 case MCK__DOT_p8: return "MCK__DOT_p8";
9514 case MCK__EXCLAIM_: return "MCK__EXCLAIM_";
9515 case MCK__HASH_0: return "MCK__HASH_0";
9516 case MCK__HASH_16: return "MCK__HASH_16";
9517 case MCK__HASH_8: return "MCK__HASH_8";
9518 case MCK__DOT_16: return "MCK__DOT_16";
9519 case MCK__DOT_32: return "MCK__DOT_32";
9520 case MCK__DOT_64: return "MCK__DOT_64";
9521 case MCK__DOT_8: return "MCK__DOT_8";
9522 case MCK__DOT_bf16: return "MCK__DOT_bf16";
9523 case MCK__DOT_f16: return "MCK__DOT_f16";
9524 case MCK__DOT_p64: return "MCK__DOT_p64";
9525 case MCK__DOT_w: return "MCK__DOT_w";
9526 case MCK__91_: return "MCK__91_";
9527 case MCK__93_: return "MCK__93_";
9528 case MCK__94_: return "MCK__94_";
9529 case MCK__123_: return "MCK__123_";
9530 case MCK__125_: return "MCK__125_";
9531 case MCK_Reg108: return "MCK_Reg108";
9532 case MCK_Reg92: return "MCK_Reg92";
9533 case MCK_APSR: return "MCK_APSR";
9534 case MCK_APSR_NZCV: return "MCK_APSR_NZCV";
9535 case MCK_CCR: return "MCK_CCR";
9536 case MCK_FPCXTRegs: return "MCK_FPCXTRegs";
9537 case MCK_FPCXTS: return "MCK_FPCXTS";
9538 case MCK_FPEXC: return "MCK_FPEXC";
9539 case MCK_FPINST: return "MCK_FPINST";
9540 case MCK_FPINST2: return "MCK_FPINST2";
9541 case MCK_FPSCR: return "MCK_FPSCR";
9542 case MCK_FPSCR_NZCVQC: return "MCK_FPSCR_NZCVQC";
9543 case MCK_FPSID: return "MCK_FPSID";
9544 case MCK_GPRlr: return "MCK_GPRlr";
9545 case MCK_GPRsp: return "MCK_GPRsp";
9546 case MCK_MVFR0: return "MCK_MVFR0";
9547 case MCK_MVFR1: return "MCK_MVFR1";
9548 case MCK_MVFR2: return "MCK_MVFR2";
9549 case MCK_P0: return "MCK_P0";
9550 case MCK_PC: return "MCK_PC";
9551 case MCK_R12: return "MCK_R12";
9552 case MCK_SPSR: return "MCK_SPSR";
9553 case MCK_VCCR: return "MCK_VCCR";
9554 case MCK_cl_FPSCR_NZCV: return "MCK_cl_FPSCR_NZCV";
9555 case MCK_Reg133: return "MCK_Reg133";
9556 case MCK_Reg106: return "MCK_Reg106";
9557 case MCK_Reg101: return "MCK_Reg101";
9558 case MCK_Reg93: return "MCK_Reg93";
9559 case MCK_Reg35: return "MCK_Reg35";
9560 case MCK_Reg33: return "MCK_Reg33";
9561 case MCK_Reg22: return "MCK_Reg22";
9562 case MCK_Reg17: return "MCK_Reg17";
9563 case MCK_FP_STATUS_REGS: return "MCK_FP_STATUS_REGS";
9564 case MCK_Reg134: return "MCK_Reg134";
9565 case MCK_Reg121: return "MCK_Reg121";
9566 case MCK_Reg116: return "MCK_Reg116";
9567 case MCK_Reg107: return "MCK_Reg107";
9568 case MCK_Reg105: return "MCK_Reg105";
9569 case MCK_Reg94: return "MCK_Reg94";
9570 case MCK_Reg78: return "MCK_Reg78";
9571 case MCK_Reg21: return "MCK_Reg21";
9572 case MCK_Reg135: return "MCK_Reg135";
9573 case MCK_Reg126: return "MCK_Reg126";
9574 case MCK_Reg122: return "MCK_Reg122";
9575 case MCK_Reg117: return "MCK_Reg117";
9576 case MCK_Reg102: return "MCK_Reg102";
9577 case MCK_Reg95: return "MCK_Reg95";
9578 case MCK_Reg79: return "MCK_Reg79";
9579 case MCK_Reg34: return "MCK_Reg34";
9580 case MCK_Reg25: return "MCK_Reg25";
9581 case MCK_Reg23: return "MCK_Reg23";
9582 case MCK_Reg18: return "MCK_Reg18";
9583 case MCK_QPR_8: return "MCK_QPR_8";
9584 case MCK_tcGPRnotr12: return "MCK_tcGPRnotr12";
9585 case MCK_Reg90: return "MCK_Reg90";
9586 case MCK_Reg32: return "MCK_Reg32";
9587 case MCK_Reg30: return "MCK_Reg30";
9588 case MCK_MQQQQPR: return "MCK_MQQQQPR";
9589 case MCK_tcGPR: return "MCK_tcGPR";
9590 case MCK_Reg136: return "MCK_Reg136";
9591 case MCK_Reg127: return "MCK_Reg127";
9592 case MCK_Reg109: return "MCK_Reg109";
9593 case MCK_Reg97: return "MCK_Reg97";
9594 case MCK_Reg91: return "MCK_Reg91";
9595 case MCK_Reg73: return "MCK_Reg73";
9596 case MCK_Reg31: return "MCK_Reg31";
9597 case MCK_Reg28: return "MCK_Reg28";
9598 case MCK_Reg19: return "MCK_Reg19";
9599 case MCK_GPRPairnosp: return "MCK_GPRPairnosp";
9600 case MCK_tGPROdd: return "MCK_tGPROdd";
9601 case MCK_Reg137: return "MCK_Reg137";
9602 case MCK_Reg123: return "MCK_Reg123";
9603 case MCK_Reg118: return "MCK_Reg118";
9604 case MCK_Reg110: return "MCK_Reg110";
9605 case MCK_Reg98: return "MCK_Reg98";
9606 case MCK_Reg88: return "MCK_Reg88";
9607 case MCK_Reg52: return "MCK_Reg52";
9608 case MCK_Reg29: return "MCK_Reg29";
9609 case MCK_Reg26: return "MCK_Reg26";
9610 case MCK_GPRPair: return "MCK_GPRPair";
9611 case MCK_MQQPR: return "MCK_MQQPR";
9612 case MCK_Reg138: return "MCK_Reg138";
9613 case MCK_Reg128: return "MCK_Reg128";
9614 case MCK_Reg124: return "MCK_Reg124";
9615 case MCK_Reg119: return "MCK_Reg119";
9616 case MCK_Reg111: return "MCK_Reg111";
9617 case MCK_Reg99: return "MCK_Reg99";
9618 case MCK_Reg89: return "MCK_Reg89";
9619 case MCK_Reg81: return "MCK_Reg81";
9620 case MCK_Reg74: return "MCK_Reg74";
9621 case MCK_Reg53: return "MCK_Reg53";
9622 case MCK_DPR_8: return "MCK_DPR_8";
9623 case MCK_MQPR: return "MCK_MQPR";
9624 case MCK_hGPR: return "MCK_hGPR";
9625 case MCK_tGPR: return "MCK_tGPR";
9626 case MCK_tGPREven: return "MCK_tGPREven";
9627 case MCK_tGPRwithpc: return "MCK_tGPRwithpc";
9628 case MCK_Reg129: return "MCK_Reg129";
9629 case MCK_Reg2: return "MCK_Reg2";
9630 case MCK_Reg86: return "MCK_Reg86";
9631 case MCK_Reg14: return "MCK_Reg14";
9632 case MCK_Reg12: return "MCK_Reg12";
9633 case MCK_QQQQPR: return "MCK_QQQQPR";
9634 case MCK_Reg139: return "MCK_Reg139";
9635 case MCK_Reg130: return "MCK_Reg130";
9636 case MCK_Reg112: return "MCK_Reg112";
9637 case MCK_Reg87: return "MCK_Reg87";
9638 case MCK_Reg75: return "MCK_Reg75";
9639 case MCK_GPRnoip: return "MCK_GPRnoip";
9640 case MCK_rGPR: return "MCK_rGPR";
9641 case MCK_Reg125: return "MCK_Reg125";
9642 case MCK_Reg120: return "MCK_Reg120";
9643 case MCK_Reg113: return "MCK_Reg113";
9644 case MCK_Reg84: return "MCK_Reg84";
9645 case MCK_Reg50: return "MCK_Reg50";
9646 case MCK_GPRnopc: return "MCK_GPRnopc";
9647 case MCK_GPRnosp: return "MCK_GPRnosp";
9648 case MCK_GPRwithAPSR_NZCVnosp: return "MCK_GPRwithAPSR_NZCVnosp";
9649 case MCK_GPRwithAPSRnosp: return "MCK_GPRwithAPSRnosp";
9650 case MCK_GPRwithZRnosp: return "MCK_GPRwithZRnosp";
9651 case MCK_QQPR: return "MCK_QQPR";
9652 case MCK_Reg131: return "MCK_Reg131";
9653 case MCK_Reg114: return "MCK_Reg114";
9654 case MCK_Reg85: return "MCK_Reg85";
9655 case MCK_Reg76: return "MCK_Reg76";
9656 case MCK_Reg51: return "MCK_Reg51";
9657 case MCK_DPR_VFP2: return "MCK_DPR_VFP2";
9658 case MCK_GPR: return "MCK_GPR";
9659 case MCK_GPRwithAPSR: return "MCK_GPRwithAPSR";
9660 case MCK_GPRwithZR: return "MCK_GPRwithZR";
9661 case MCK_QPR: return "MCK_QPR";
9662 case MCK_SPR_8: return "MCK_SPR_8";
9663 case MCK_DTripleSpc: return "MCK_DTripleSpc";
9664 case MCK_DQuad: return "MCK_DQuad";
9665 case MCK_DPairSpc: return "MCK_DPairSpc";
9666 case MCK_DTriple: return "MCK_DTriple";
9667 case MCK_DPair: return "MCK_DPair";
9668 case MCK_DPR: return "MCK_DPR";
9669 case MCK_HPR: return "MCK_HPR";
9670 case MCK_FPWithVPR: return "MCK_FPWithVPR";
9671 case MCK_RegByHwMode_arm_ptr_rc: return "MCK_RegByHwMode_arm_ptr_rc";
9672 case MCK_AM2OffsetImm: return "MCK_AM2OffsetImm";
9673 case MCK_AM3Offset: return "MCK_AM3Offset";
9674 case MCK_ARMBranchTarget: return "MCK_ARMBranchTarget";
9675 case MCK_AddrMode3: return "MCK_AddrMode3";
9676 case MCK_AddrMode5: return "MCK_AddrMode5";
9677 case MCK_AddrMode5FP16: return "MCK_AddrMode5FP16";
9678 case MCK_AlignedMemory16: return "MCK_AlignedMemory16";
9679 case MCK_AlignedMemory32: return "MCK_AlignedMemory32";
9680 case MCK_AlignedMemory64: return "MCK_AlignedMemory64";
9681 case MCK_AlignedMemory64or128: return "MCK_AlignedMemory64or128";
9682 case MCK_AlignedMemory64or128or256: return "MCK_AlignedMemory64or128or256";
9683 case MCK_AlignedMemoryNone: return "MCK_AlignedMemoryNone";
9684 case MCK_AlignedMemory: return "MCK_AlignedMemory";
9685 case MCK_DupAlignedMemory16: return "MCK_DupAlignedMemory16";
9686 case MCK_DupAlignedMemory32: return "MCK_DupAlignedMemory32";
9687 case MCK_DupAlignedMemory64: return "MCK_DupAlignedMemory64";
9688 case MCK_DupAlignedMemory64or128: return "MCK_DupAlignedMemory64or128";
9689 case MCK_DupAlignedMemoryNone: return "MCK_DupAlignedMemoryNone";
9690 case MCK_AdrLabel: return "MCK_AdrLabel";
9691 case MCK_BankedReg: return "MCK_BankedReg";
9692 case MCK_Bitfield: return "MCK_Bitfield";
9693 case MCK_CCOut: return "MCK_CCOut";
9694 case MCK_CondCode: return "MCK_CondCode";
9695 case MCK_CoprocNum: return "MCK_CoprocNum";
9696 case MCK_CoprocOption: return "MCK_CoprocOption";
9697 case MCK_CoprocReg: return "MCK_CoprocReg";
9698 case MCK_DPRRegList: return "MCK_DPRRegList";
9699 case MCK_FPDRegListWithVPR: return "MCK_FPDRegListWithVPR";
9700 case MCK_FPImm: return "MCK_FPImm";
9701 case MCK_FPSRegListWithVPR: return "MCK_FPSRegListWithVPR";
9702 case MCK_Imm0_15: return "MCK_Imm0_15";
9703 case MCK_Imm0_1: return "MCK_Imm0_1";
9704 case MCK_Imm0_239: return "MCK_Imm0_239";
9705 case MCK_Imm0_255: return "MCK_Imm0_255";
9706 case MCK_Imm0_255Expr: return "MCK_Imm0_255Expr";
9707 case MCK_Imm0_31: return "MCK_Imm0_31";
9708 case MCK_Imm0_32: return "MCK_Imm0_32";
9709 case MCK_Imm0_3: return "MCK_Imm0_3";
9710 case MCK_Imm0_63: return "MCK_Imm0_63";
9711 case MCK_Imm0_65535: return "MCK_Imm0_65535";
9712 case MCK_Imm0_65535Expr: return "MCK_Imm0_65535Expr";
9713 case MCK_Imm0_7: return "MCK_Imm0_7";
9714 case MCK_Imm16: return "MCK_Imm16";
9715 case MCK_Imm1_15: return "MCK_Imm1_15";
9716 case MCK_Imm1_16: return "MCK_Imm1_16";
9717 case MCK_Imm1_31: return "MCK_Imm1_31";
9718 case MCK_Imm1_32: return "MCK_Imm1_32";
9719 case MCK_Imm1_7: return "MCK_Imm1_7";
9720 case MCK_Imm24bit: return "MCK_Imm24bit";
9721 case MCK_Imm256_65535Expr: return "MCK_Imm256_65535Expr";
9722 case MCK_Imm32: return "MCK_Imm32";
9723 case MCK_Imm8: return "MCK_Imm8";
9724 case MCK_Imm8_255: return "MCK_Imm8_255";
9725 case MCK_Imm: return "MCK_Imm";
9726 case MCK_InstSyncBarrierOpt: return "MCK_InstSyncBarrierOpt";
9727 case MCK_MSRMask: return "MCK_MSRMask";
9728 case MCK_MVEShiftImm1_15: return "MCK_MVEShiftImm1_15";
9729 case MCK_MVEShiftImm1_7: return "MCK_MVEShiftImm1_7";
9730 case MCK_VIDUP_imm: return "MCK_VIDUP_imm";
9731 case MCK_MemBarrierOpt: return "MCK_MemBarrierOpt";
9732 case MCK_MemImm0_1020s4Offset: return "MCK_MemImm0_1020s4Offset";
9733 case MCK_MemImm12Offset: return "MCK_MemImm12Offset";
9734 case MCK_MemImm7Shift0Offset: return "MCK_MemImm7Shift0Offset";
9735 case MCK_MemImm7Shift0OffsetWB: return "MCK_MemImm7Shift0OffsetWB";
9736 case MCK_MemImm7Shift1Offset: return "MCK_MemImm7Shift1Offset";
9737 case MCK_MemImm7Shift1OffsetWB: return "MCK_MemImm7Shift1OffsetWB";
9738 case MCK_MemImm7Shift2Offset: return "MCK_MemImm7Shift2Offset";
9739 case MCK_MemImm7Shift2OffsetWB: return "MCK_MemImm7Shift2OffsetWB";
9740 case MCK_MemImm7s4Offset: return "MCK_MemImm7s4Offset";
9741 case MCK_MemImm8Offset: return "MCK_MemImm8Offset";
9742 case MCK_MemImm8s4Offset: return "MCK_MemImm8s4Offset";
9743 case MCK_MemNegImm8Offset: return "MCK_MemNegImm8Offset";
9744 case MCK_MemNoOffset: return "MCK_MemNoOffset";
9745 case MCK_MemNoOffsetT2: return "MCK_MemNoOffsetT2";
9746 case MCK_MemNoOffsetT2NoSp: return "MCK_MemNoOffsetT2NoSp";
9747 case MCK_MemNoOffsetT: return "MCK_MemNoOffsetT";
9748 case MCK_MemPosImm8Offset: return "MCK_MemPosImm8Offset";
9749 case MCK_MemRegOffset: return "MCK_MemRegOffset";
9750 case MCK_MemRegQS2Offset: return "MCK_MemRegQS2Offset";
9751 case MCK_MemRegQS3Offset: return "MCK_MemRegQS3Offset";
9752 case MCK_MemRegRQS0Offset: return "MCK_MemRegRQS0Offset";
9753 case MCK_MemRegRQS1Offset: return "MCK_MemRegRQS1Offset";
9754 case MCK_MemRegRQS2Offset: return "MCK_MemRegRQS2Offset";
9755 case MCK_MemRegRQS3Offset: return "MCK_MemRegRQS3Offset";
9756 case MCK_ModImm: return "MCK_ModImm";
9757 case MCK_ModImmNeg: return "MCK_ModImmNeg";
9758 case MCK_ModImmNot: return "MCK_ModImmNot";
9759 case MCK_MveSaturate: return "MCK_MveSaturate";
9760 case MCK_PKHASRImm: return "MCK_PKHASRImm";
9761 case MCK_PKHLSLImm: return "MCK_PKHLSLImm";
9762 case MCK_PostIdxImm8: return "MCK_PostIdxImm8";
9763 case MCK_PostIdxImm8s4: return "MCK_PostIdxImm8s4";
9764 case MCK_PostIdxReg: return "MCK_PostIdxReg";
9765 case MCK_PostIdxRegShifted: return "MCK_PostIdxRegShifted";
9766 case MCK_ProcIFlags: return "MCK_ProcIFlags";
9767 case MCK_RegList: return "MCK_RegList";
9768 case MCK_RegListWithAPSR: return "MCK_RegListWithAPSR";
9769 case MCK_RotImm: return "MCK_RotImm";
9770 case MCK_SPRRegList: return "MCK_SPRRegList";
9771 case MCK_SetEndImm: return "MCK_SetEndImm";
9772 case MCK_RegShiftedImm: return "MCK_RegShiftedImm";
9773 case MCK_RegShiftedReg: return "MCK_RegShiftedReg";
9774 case MCK_ShifterImm: return "MCK_ShifterImm";
9775 case MCK_ThumbBranchTarget: return "MCK_ThumbBranchTarget";
9776 case MCK_ThumbMemPC: return "MCK_ThumbMemPC";
9777 case MCK_ThumbModImmNeg1_7: return "MCK_ThumbModImmNeg1_7";
9778 case MCK_ThumbModImmNeg8_255: return "MCK_ThumbModImmNeg8_255";
9779 case MCK_ImmThumbSR: return "MCK_ImmThumbSR";
9780 case MCK_TraceSyncBarrierOpt: return "MCK_TraceSyncBarrierOpt";
9781 case MCK_UnsignedOffset_b8s2: return "MCK_UnsignedOffset_b8s2";
9782 case MCK_VPTPredN: return "MCK_VPTPredN";
9783 case MCK_VPTPredR: return "MCK_VPTPredR";
9784 case MCK_VecListTwoMQ: return "MCK_VecListTwoMQ";
9785 case MCK_VecListFourMQ: return "MCK_VecListFourMQ";
9786 case MCK_VecListDPairAllLanes: return "MCK_VecListDPairAllLanes";
9787 case MCK_VecListDPair: return "MCK_VecListDPair";
9788 case MCK_VecListDPairSpacedAllLanes: return "MCK_VecListDPairSpacedAllLanes";
9789 case MCK_VecListDPairSpaced: return "MCK_VecListDPairSpaced";
9790 case MCK_VecListFourDAllLanes: return "MCK_VecListFourDAllLanes";
9791 case MCK_VecListFourD: return "MCK_VecListFourD";
9792 case MCK_VecListFourDByteIndexed: return "MCK_VecListFourDByteIndexed";
9793 case MCK_VecListFourDHWordIndexed: return "MCK_VecListFourDHWordIndexed";
9794 case MCK_VecListFourDWordIndexed: return "MCK_VecListFourDWordIndexed";
9795 case MCK_VecListFourQAllLanes: return "MCK_VecListFourQAllLanes";
9796 case MCK_VecListFourQ: return "MCK_VecListFourQ";
9797 case MCK_VecListFourQHWordIndexed: return "MCK_VecListFourQHWordIndexed";
9798 case MCK_VecListFourQWordIndexed: return "MCK_VecListFourQWordIndexed";
9799 case MCK_VecListOneDAllLanes: return "MCK_VecListOneDAllLanes";
9800 case MCK_VecListOneD: return "MCK_VecListOneD";
9801 case MCK_VecListOneDByteIndexed: return "MCK_VecListOneDByteIndexed";
9802 case MCK_VecListOneDHWordIndexed: return "MCK_VecListOneDHWordIndexed";
9803 case MCK_VecListOneDWordIndexed: return "MCK_VecListOneDWordIndexed";
9804 case MCK_VecListThreeDAllLanes: return "MCK_VecListThreeDAllLanes";
9805 case MCK_VecListThreeD: return "MCK_VecListThreeD";
9806 case MCK_VecListThreeDByteIndexed: return "MCK_VecListThreeDByteIndexed";
9807 case MCK_VecListThreeDHWordIndexed: return "MCK_VecListThreeDHWordIndexed";
9808 case MCK_VecListThreeDWordIndexed: return "MCK_VecListThreeDWordIndexed";
9809 case MCK_VecListThreeQAllLanes: return "MCK_VecListThreeQAllLanes";
9810 case MCK_VecListThreeQ: return "MCK_VecListThreeQ";
9811 case MCK_VecListThreeQHWordIndexed: return "MCK_VecListThreeQHWordIndexed";
9812 case MCK_VecListThreeQWordIndexed: return "MCK_VecListThreeQWordIndexed";
9813 case MCK_VecListTwoDByteIndexed: return "MCK_VecListTwoDByteIndexed";
9814 case MCK_VecListTwoDHWordIndexed: return "MCK_VecListTwoDHWordIndexed";
9815 case MCK_VecListTwoDWordIndexed: return "MCK_VecListTwoDWordIndexed";
9816 case MCK_VecListTwoQHWordIndexed: return "MCK_VecListTwoQHWordIndexed";
9817 case MCK_VecListTwoQWordIndexed: return "MCK_VecListTwoQWordIndexed";
9818 case MCK_VectorIndex16: return "MCK_VectorIndex16";
9819 case MCK_VectorIndex32: return "MCK_VectorIndex32";
9820 case MCK_VectorIndex64: return "MCK_VectorIndex64";
9821 case MCK_VectorIndex8: return "MCK_VectorIndex8";
9822 case MCK_MemTBB: return "MCK_MemTBB";
9823 case MCK_MemTBH: return "MCK_MemTBH";
9824 case MCK_MVEPairVectorIndex0: return "MCK_MVEPairVectorIndex0";
9825 case MCK_MVEPairVectorIndex2: return "MCK_MVEPairVectorIndex2";
9826 case MCK_ComplexRotationEven: return "MCK_ComplexRotationEven";
9827 case MCK_ComplexRotationOdd: return "MCK_ComplexRotationOdd";
9828 case MCK_NEONi16vmovi8Replicate: return "MCK_NEONi16vmovi8Replicate";
9829 case MCK_NEONi16invi8Replicate: return "MCK_NEONi16invi8Replicate";
9830 case MCK_NEONi32vmovi8Replicate: return "MCK_NEONi32vmovi8Replicate";
9831 case MCK_NEONi32invi8Replicate: return "MCK_NEONi32invi8Replicate";
9832 case MCK_NEONi64vmovi8Replicate: return "MCK_NEONi64vmovi8Replicate";
9833 case MCK_NEONi64invi8Replicate: return "MCK_NEONi64invi8Replicate";
9834 case MCK_NEONi32vmovi16Replicate: return "MCK_NEONi32vmovi16Replicate";
9835 case MCK_NEONi64vmovi16Replicate: return "MCK_NEONi64vmovi16Replicate";
9836 case MCK_NEONi64vmovi32Replicate: return "MCK_NEONi64vmovi32Replicate";
9837 case MCK_MVEVectorIndex4: return "MCK_MVEVectorIndex4";
9838 case MCK_MVEVectorIndex8: return "MCK_MVEVectorIndex8";
9839 case MCK_MVEVectorIndex16: return "MCK_MVEVectorIndex16";
9840 case MCK_MVEVcvtImm32: return "MCK_MVEVcvtImm32";
9841 case MCK_MVEVcvtImm16: return "MCK_MVEVcvtImm16";
9842 case MCK_TMemImm7Shift2Offset: return "MCK_TMemImm7Shift2Offset";
9843 case MCK_TMemImm7Shift0Offset: return "MCK_TMemImm7Shift0Offset";
9844 case MCK_TMemImm7Shift1Offset: return "MCK_TMemImm7Shift1Offset";
9845 case MCK_Imm3b: return "MCK_Imm3b";
9846 case MCK_Imm4b: return "MCK_Imm4b";
9847 case MCK_Imm6b: return "MCK_Imm6b";
9848 case MCK_Imm7b: return "MCK_Imm7b";
9849 case MCK_Imm9b: return "MCK_Imm9b";
9850 case MCK_Imm11b: return "MCK_Imm11b";
9851 case MCK_Imm12b: return "MCK_Imm12b";
9852 case MCK_Imm13b: return "MCK_Imm13b";
9853 case MCK_ConstPoolAsmImm: return "MCK_ConstPoolAsmImm";
9854 case MCK_FBits16: return "MCK_FBits16";
9855 case MCK_FBits32: return "MCK_FBits32";
9856 case MCK_Imm0_4095: return "MCK_Imm0_4095";
9857 case MCK_Imm0_4095Neg: return "MCK_Imm0_4095Neg";
9858 case MCK_ITMask: return "MCK_ITMask";
9859 case MCK_ITCondCode: return "MCK_ITCondCode";
9860 case MCK_LELabel: return "MCK_LELabel";
9861 case MCK_MVELongShift: return "MCK_MVELongShift";
9862 case MCK_NEONi16splat: return "MCK_NEONi16splat";
9863 case MCK_NEONi32splat: return "MCK_NEONi32splat";
9864 case MCK_NEONi64splat: return "MCK_NEONi64splat";
9865 case MCK_NEONi8splat: return "MCK_NEONi8splat";
9866 case MCK_NEONi16splatNot: return "MCK_NEONi16splatNot";
9867 case MCK_NEONi32splatNot: return "MCK_NEONi32splatNot";
9868 case MCK_NEONi32vmov: return "MCK_NEONi32vmov";
9869 case MCK_NEONi32vmovNeg: return "MCK_NEONi32vmovNeg";
9870 case MCK_CondCodeNoAL: return "MCK_CondCodeNoAL";
9871 case MCK_CondCodeNoALInv: return "MCK_CondCodeNoALInv";
9872 case MCK_CondCodeRestrictedFP: return "MCK_CondCodeRestrictedFP";
9873 case MCK_CondCodeRestrictedI: return "MCK_CondCodeRestrictedI";
9874 case MCK_CondCodeRestrictedS: return "MCK_CondCodeRestrictedS";
9875 case MCK_CondCodeRestrictedU: return "MCK_CondCodeRestrictedU";
9876 case MCK_ShrImm16: return "MCK_ShrImm16";
9877 case MCK_ShrImm32: return "MCK_ShrImm32";
9878 case MCK_ShrImm64: return "MCK_ShrImm64";
9879 case MCK_ShrImm8: return "MCK_ShrImm8";
9880 case MCK_T2SOImm: return "MCK_T2SOImm";
9881 case MCK_T2SOImmNeg: return "MCK_T2SOImmNeg";
9882 case MCK_T2SOImmNot: return "MCK_T2SOImmNot";
9883 case MCK_MemUImm12Offset: return "MCK_MemUImm12Offset";
9884 case MCK_T2MemRegOffset: return "MCK_T2MemRegOffset";
9885 case MCK_Imm7s4: return "MCK_Imm7s4";
9886 case MCK_Imm7Shift0: return "MCK_Imm7Shift0";
9887 case MCK_Imm7Shift1: return "MCK_Imm7Shift1";
9888 case MCK_Imm7Shift2: return "MCK_Imm7Shift2";
9889 case MCK_Imm8s4: return "MCK_Imm8s4";
9890 case MCK_MemPCRelImm12: return "MCK_MemPCRelImm12";
9891 case MCK_MemThumbRIs1: return "MCK_MemThumbRIs1";
9892 case MCK_MemThumbRIs2: return "MCK_MemThumbRIs2";
9893 case MCK_MemThumbRIs4: return "MCK_MemThumbRIs4";
9894 case MCK_MemThumbRR: return "MCK_MemThumbRR";
9895 case MCK_MemThumbSPI: return "MCK_MemThumbSPI";
9896 case MCK_Imm0_1020s4: return "MCK_Imm0_1020s4";
9897 case MCK_Imm0_508s4: return "MCK_Imm0_508s4";
9898 case MCK_Imm0_508s4Neg: return "MCK_Imm0_508s4Neg";
9899 case MCK_WLSLabel: return "MCK_WLSLabel";
9900 case NumMatchClassKinds: return "NumMatchClassKinds";
9901 }
9902 llvm_unreachable("unhandled MatchClassKind!");
9903}
9904
9905#endif // NDEBUG
9906FeatureBitset ARMAsmParser::
9907ComputeAvailableFeatures(const FeatureBitset &FB) const {
9908 FeatureBitset Features;
9909 if (FB[ARM::HasV4TOps])
9910 Features.set(Feature_HasV4TBit);
9911 if (FB[ARM::HasV5TOps])
9912 Features.set(Feature_HasV5TBit);
9913 if (FB[ARM::HasV5TEOps])
9914 Features.set(Feature_HasV5TEBit);
9915 if (FB[ARM::HasV6Ops])
9916 Features.set(Feature_HasV6Bit);
9917 if (FB[ARM::HasV6MOps])
9918 Features.set(Feature_HasV6MBit);
9919 if (FB[ARM::HasV8MBaselineOps])
9920 Features.set(Feature_HasV8MBaselineBit);
9921 if (FB[ARM::HasV8MMainlineOps])
9922 Features.set(Feature_HasV8MMainlineBit);
9923 if (FB[ARM::HasV8_1MMainlineOps])
9924 Features.set(Feature_HasV8_1MMainlineBit);
9925 if (FB[ARM::HasMVEIntegerOps])
9926 Features.set(Feature_HasMVEIntBit);
9927 if (FB[ARM::HasMVEFloatOps])
9928 Features.set(Feature_HasMVEFloatBit);
9929 if (FB[ARM::HasCDEOps])
9930 Features.set(Feature_HasCDEBit);
9931 if (FB[ARM::FeatureFPRegs])
9932 Features.set(Feature_HasFPRegsBit);
9933 if (FB[ARM::FeatureFPRegs16])
9934 Features.set(Feature_HasFPRegs16Bit);
9935 if (!(FB[ARM::FeatureFPRegs16]))
9936 Features.set(Feature_HasNoFPRegs16Bit);
9937 if (FB[ARM::FeatureFPRegs64])
9938 Features.set(Feature_HasFPRegs64Bit);
9939 if (FB[ARM::FeatureFPRegs] && FB[ARM::HasV8_1MMainlineOps])
9940 Features.set(Feature_HasFPRegsV8_1MBit);
9941 if (FB[ARM::HasV6T2Ops])
9942 Features.set(Feature_HasV6T2Bit);
9943 if (FB[ARM::HasV6KOps])
9944 Features.set(Feature_HasV6KBit);
9945 if (FB[ARM::HasV7Ops])
9946 Features.set(Feature_HasV7Bit);
9947 if (FB[ARM::HasV8Ops])
9948 Features.set(Feature_HasV8Bit);
9949 if (!(FB[ARM::HasV8Ops]))
9950 Features.set(Feature_PreV8Bit);
9951 if (FB[ARM::HasV8_1aOps])
9952 Features.set(Feature_HasV8_1aBit);
9953 if (FB[ARM::HasV8_2aOps])
9954 Features.set(Feature_HasV8_2aBit);
9955 if (FB[ARM::HasV8_3aOps])
9956 Features.set(Feature_HasV8_3aBit);
9957 if (FB[ARM::HasV8_4aOps])
9958 Features.set(Feature_HasV8_4aBit);
9959 if (FB[ARM::HasV8_5aOps])
9960 Features.set(Feature_HasV8_5aBit);
9961 if (FB[ARM::HasV8_6aOps])
9962 Features.set(Feature_HasV8_6aBit);
9963 if (FB[ARM::HasV8_7aOps])
9964 Features.set(Feature_HasV8_7aBit);
9965 if (FB[ARM::FeatureVFP2_SP])
9966 Features.set(Feature_HasVFP2Bit);
9967 if (FB[ARM::FeatureVFP3_D16_SP])
9968 Features.set(Feature_HasVFP3Bit);
9969 if (FB[ARM::FeatureVFP4_D16_SP])
9970 Features.set(Feature_HasVFP4Bit);
9971 if (FB[ARM::FeatureFP64])
9972 Features.set(Feature_HasDPVFPBit);
9973 if (FB[ARM::FeatureFPARMv8_D16_SP])
9974 Features.set(Feature_HasFPARMv8Bit);
9975 if (FB[ARM::FeatureNEON])
9976 Features.set(Feature_HasNEONBit);
9977 if (FB[ARM::FeatureSHA2])
9978 Features.set(Feature_HasSHA2Bit);
9979 if (FB[ARM::FeatureAES])
9980 Features.set(Feature_HasAESBit);
9981 if (FB[ARM::FeatureCrypto])
9982 Features.set(Feature_HasCryptoBit);
9983 if (FB[ARM::FeatureDotProd])
9984 Features.set(Feature_HasDotProdBit);
9985 if (FB[ARM::FeatureCRC])
9986 Features.set(Feature_HasCRCBit);
9987 if (FB[ARM::FeatureRAS])
9988 Features.set(Feature_HasRASBit);
9989 if (FB[ARM::FeatureLOB])
9990 Features.set(Feature_HasLOBBit);
9991 if (FB[ARM::FeaturePACBTI])
9992 Features.set(Feature_HasPACBTIBit);
9993 if (FB[ARM::FeatureFP16])
9994 Features.set(Feature_HasFP16Bit);
9995 if (FB[ARM::FeatureFullFP16])
9996 Features.set(Feature_HasFullFP16Bit);
9997 if (FB[ARM::FeatureFP16FML])
9998 Features.set(Feature_HasFP16FMLBit);
9999 if (FB[ARM::FeatureBF16])
10000 Features.set(Feature_HasBF16Bit);
10001 if (FB[ARM::FeatureMatMulInt8])
10002 Features.set(Feature_HasMatMulInt8Bit);
10003 if (FB[ARM::FeatureHWDivThumb])
10004 Features.set(Feature_HasDivideInThumbBit);
10005 if (FB[ARM::FeatureHWDivARM])
10006 Features.set(Feature_HasDivideInARMBit);
10007 if (FB[ARM::FeatureDSP])
10008 Features.set(Feature_HasDSPBit);
10009 if (FB[ARM::FeatureDB])
10010 Features.set(Feature_HasDBBit);
10011 if (FB[ARM::FeatureDFB])
10012 Features.set(Feature_HasDFBBit);
10013 if (FB[ARM::FeatureV7Clrex])
10014 Features.set(Feature_HasV7ClrexBit);
10015 if (FB[ARM::FeatureAcquireRelease])
10016 Features.set(Feature_HasAcquireReleaseBit);
10017 if (FB[ARM::FeatureMP])
10018 Features.set(Feature_HasMPBit);
10019 if (FB[ARM::FeatureVirtualization])
10020 Features.set(Feature_HasVirtualizationBit);
10021 if (FB[ARM::FeatureTrustZone])
10022 Features.set(Feature_HasTrustZoneBit);
10023 if (FB[ARM::Feature8MSecExt])
10024 Features.set(Feature_Has8MSecExtBit);
10025 if (FB[ARM::ModeThumb])
10026 Features.set(Feature_IsThumbBit);
10027 if (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2])
10028 Features.set(Feature_IsThumb2Bit);
10029 if (FB[ARM::FeatureMClass])
10030 Features.set(Feature_IsMClassBit);
10031 if (!(FB[ARM::FeatureMClass]))
10032 Features.set(Feature_IsNotMClassBit);
10033 if (!(FB[ARM::ModeThumb]))
10034 Features.set(Feature_IsARMBit);
10035 if (!(FB[ARM::FeatureNoNegativeImmediates]))
10036 Features.set(Feature_UseNegativeImmediatesBit);
10037 if (FB[ARM::FeatureSB])
10038 Features.set(Feature_HasSBBit);
10039 if (FB[ARM::FeatureCLRBHB])
10040 Features.set(Feature_HasCLRBHBBit);
10041 return Features;
10042}
10043
10044static const char MnemonicTable[] =
10045 "\t__brkdiv0\003adc\003add\004addw\003adr\004aesd\004aese\006aesimc\005a"
10046 "esmc\003and\003asr\004asrl\003aut\004autg\001b\002bf\003bfc\006bfcsel\003"
10047 "bfi\003bfl\004bflx\003bfx\003bic\004bkpt\002bl\003blx\005blxns\003bti\002"
10048 "bx\005bxaut\003bxj\004bxns\004cbnz\003cbz\003cdp\004cdp2\004cinc\004cin"
10049 "v\006clrbhb\005clrex\004clrm\003clz\003cmn\003cmp\004cneg\003cps\006crc"
10050 "32b\007crc32cb\007crc32ch\007crc32cw\006crc32h\006crc32w\004csdb\004cse"
10051 "l\004cset\005csetm\005csinc\005csinv\005csneg\003cx1\004cx1a\004cx1d\005"
10052 "cx1da\003cx2\004cx2a\004cx2d\005cx2da\003cx3\004cx3a\004cx3d\005cx3da\003"
10053 "dbg\005dcps1\005dcps2\005dcps3\003dfb\003dls\005dlstp\003dmb\003dsb\003"
10054 "eor\004eret\003esb\005faddd\005fadds\006fcmpzd\006fcmpzs\007fconstd\007"
10055 "fconsts\007fldmdbx\007fldmiax\005fmdhr\005fmdlr\006fmstat\007fstmdbx\007"
10056 "fstmiax\005fsubd\005fsubs\004hint\003hlt\003hvc\003isb\002it\004lctp\003"
10057 "lda\004ldab\005ldaex\006ldaexb\006ldaexd\006ldaexh\004ldah\003ldc\004ld"
10058 "c2\005ldc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004ldrb\005"
10059 "ldrbt\004ldrd\005ldrex\006ldrexb\006ldrexd\006ldrexh\004ldrh\005ldrht\005"
10060 "ldrsb\006ldrsbt\005ldrsh\006ldrsht\004ldrt\002le\004letp\003lsl\004lsll"
10061 "\003lsr\004lsrl\003mcr\004mcr2\004mcrr\005mcrr2\003mla\003mls\003mov\004"
10062 "movs\004movt\004movw\003mrc\004mrc2\004mrrc\005mrrc2\003mrs\003msr\003m"
10063 "ul\003mvn\003neg\003nop\003orn\003orr\003pac\006pacbti\004pacg\005pkhbt"
10064 "\005pkhtb\003pld\004pldw\003pli\003pop\005pssbb\004push\004qadd\006qadd"
10065 "16\005qadd8\004qasx\005qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub"
10066 "8\004rbit\003rev\005rev16\005revsh\005rfeda\005rfedb\005rfeia\005rfeib\003"
10067 "ror\003rrx\003rsb\003rsc\006sadd16\005sadd8\004sasx\002sb\003sbc\004sbf"
10068 "x\004sdiv\003sel\006setend\006setpan\003sev\004sevl\002sg\005sha1c\005s"
10069 "ha1h\005sha1m\005sha1p\007sha1su0\007sha1su1\007sha256h\010sha256h2\tsh"
10070 "a256su0\tsha256su1\007shadd16\006shadd8\005shasx\005shsax\007shsub16\006"
10071 "shsub8\003smc\006smlabb\006smlabt\005smlad\006smladx\005smlal\007smlalb"
10072 "b\007smlalbt\006smlald\007smlaldx\007smlaltb\007smlaltt\006smlatb\006sm"
10073 "latt\006smlawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smm"
10074 "la\006smmlar\005smmls\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006"
10075 "smulbb\006smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005sm"
10076 "usd\006smusdx\006sqrshr\007sqrshrl\005sqshl\006sqshll\005srsda\005srsdb"
10077 "\005srshr\006srshrl\005srsia\005srsib\004ssat\006ssat16\004ssax\004ssbb"
10078 "\006ssub16\005ssub8\003stc\004stc2\005stc2l\004stcl\003stl\004stlb\005s"
10079 "tlex\006stlexb\006stlexd\006stlexh\004stlh\003stm\005stmda\005stmdb\005"
10080 "stmib\003str\004strb\005strbt\004strd\005strex\006strexb\006strexd\006s"
10081 "trexh\004strh\005strht\004strt\003sub\004subs\004subw\003svc\003swp\004"
10082 "swpb\005sxtab\007sxtab16\005sxtah\004sxtb\006sxtb16\004sxth\003tbb\003t"
10083 "bh\003teq\004trap\003tsb\003tst\002tt\003tta\004ttat\003ttt\006uadd16\005"
10084 "uadd8\004uasx\004ubfx\003udf\004udiv\007uhadd16\006uhadd8\005uhasx\005u"
10085 "hsax\007uhsub16\006uhsub8\005umaal\005umlal\005umull\007uqadd16\006uqad"
10086 "d8\005uqasx\006uqrshl\007uqrshll\005uqsax\005uqshl\006uqshll\007uqsub16"
10087 "\006uqsub8\005urshr\006urshrl\005usad8\006usada8\004usat\006usat16\004u"
10088 "sax\006usub16\005usub8\005uxtab\007uxtab16\005uxtah\004uxtb\006uxtb16\004"
10089 "uxth\004vaba\005vabal\005vabav\004vabd\005vabdl\004vabs\005vacge\005vac"
10090 "gt\005vacle\005vaclt\004vadc\005vadci\004vadd\006vaddhn\005vaddl\006vad"
10091 "dlv\007vaddlva\005vaddv\006vaddva\005vaddw\004vand\004vbic\004vbif\004v"
10092 "bit\005vbrsr\004vbsl\005vcadd\004vceq\004vcge\004vcgt\004vcle\004vcls\004"
10093 "vclt\004vclz\005vcmla\004vcmp\005vcmpe\005vcmul\004vcnt\004vctp\004vcvt"
10094 "\005vcvta\005vcvtb\005vcvtm\005vcvtn\005vcvtp\005vcvtr\005vcvtt\004vcx1"
10095 "\005vcx1a\004vcx2\005vcx2a\004vcx3\005vcx3a\005vddup\004vdiv\004vdot\004"
10096 "vdup\006vdwdup\004veor\004vext\004vfma\005vfmab\005vfmal\005vfmas\005vf"
10097 "mat\004vfms\005vfmsl\005vfnma\005vfnms\005vhadd\006vhcadd\005vhsub\005v"
10098 "idup\004vins\006viwdup\005vjcvt\004vld1\004vld2\005vld20\005vld21\004vl"
10099 "d3\004vld4\005vld40\005vld41\005vld42\005vld43\006vldmdb\006vldmia\004v"
10100 "ldr\005vldrb\005vldrd\005vldrh\005vldrw\005vlldm\005vlstm\004vmax\005vm"
10101 "axa\006vmaxav\006vmaxnm\007vmaxnma\010vmaxnmav\007vmaxnmv\005vmaxv\004v"
10102 "min\005vmina\006vminav\006vminnm\007vminnma\010vminnmav\007vminnmv\005v"
10103 "minv\004vmla\007vmladav\010vmladava\tvmladavax\010vmladavx\005vmlal\010"
10104 "vmlaldav\tvmlaldava\nvmlaldavax\tvmlaldavx\006vmlalv\007vmlalva\005vmla"
10105 "s\005vmlav\006vmlava\004vmls\007vmlsdav\010vmlsdava\tvmlsdavax\010vmlsd"
10106 "avx\005vmlsl\010vmlsldav\tvmlsldava\nvmlsldavax\tvmlsldavx\005vmmla\004"
10107 "vmov\005vmovl\006vmovlb\006vmovlt\005vmovn\006vmovnb\006vmovnt\005vmovx"
10108 "\004vmrs\004vmsr\004vmul\005vmulh\005vmull\006vmullb\006vmullt\004vmvn\004"
10109 "vneg\005vnmla\005vnmls\005vnmul\004vorn\004vorr\006vpadal\005vpadd\006v"
10110 "paddl\005vpmax\005vpmin\005vpnot\004vpop\005vpsel\004vpst\003vpt\005vpu"
10111 "sh\005vqabs\005vqadd\010vqdmladh\tvqdmladhx\007vqdmlah\007vqdmlal\010vq"
10112 "dmlash\010vqdmlsdh\tvqdmlsdhx\007vqdmlsl\007vqdmulh\007vqdmull\010vqdmu"
10113 "llb\010vqdmullt\006vqmovn\007vqmovnb\007vqmovnt\007vqmovun\010vqmovunb\010"
10114 "vqmovunt\005vqneg\tvqrdmladh\nvqrdmladhx\010vqrdmlah\tvqrdmlash\tvqrdml"
10115 "sdh\nvqrdmlsdhx\010vqrdmlsh\010vqrdmulh\006vqrshl\007vqrshrn\010vqrshrn"
10116 "b\010vqrshrnt\010vqrshrun\tvqrshrunb\tvqrshrunt\005vqshl\006vqshlu\006v"
10117 "qshrn\007vqshrnb\007vqshrnt\007vqshrun\010vqshrunb\010vqshrunt\005vqsub"
10118 "\007vraddhn\006vrecpe\006vrecps\006vrev16\006vrev32\006vrev64\006vrhadd"
10119 "\006vrinta\006vrintm\006vrintn\006vrintp\006vrintr\006vrintx\006vrintz\n"
10120 "vrmlaldavh\013vrmlaldavha\014vrmlaldavhax\013vrmlaldavhx\010vrmlalvh\tv"
10121 "rmlalvha\nvrmlsldavh\013vrmlsldavha\014vrmlsldavhax\013vrmlsldavhx\006v"
10122 "rmulh\005vrshl\005vrshr\006vrshrn\007vrshrnb\007vrshrnt\007vrsqrte\007v"
10123 "rsqrts\005vrsra\007vrsubhn\004vsbc\005vsbci\007vscclrm\005vsdot\006vsel"
10124 "eq\006vselge\006vselgt\006vselvs\004vshl\005vshlc\005vshll\006vshllb\006"
10125 "vshllt\004vshr\005vshrn\006vshrnb\006vshrnt\004vsli\006vsmmla\005vsqrt\004"
10126 "vsra\004vsri\004vst1\004vst2\005vst20\005vst21\004vst3\004vst4\005vst40"
10127 "\005vst41\005vst42\005vst43\006vstmdb\006vstmia\004vstr\005vstrb\005vst"
10128 "rd\005vstrh\005vstrw\004vsub\006vsubhn\005vsubl\005vsubw\006vsudot\004v"
10129 "swp\004vtbl\004vtbx\004vtrn\004vtst\005vudot\006vummla\006vusdot\007vus"
10130 "mmla\004vuzp\004vzip\003wfe\003wfi\003wls\005wlstp\005yield";
10131
10132// Feature bitsets.
10133enum : uint8_t {
10134 AMFBS_None,
10135 AMFBS_Has8MSecExt,
10136 AMFBS_HasBF16,
10137 AMFBS_HasCDE,
10138 AMFBS_HasDB,
10139 AMFBS_HasDFB,
10140 AMFBS_HasDotProd,
10141 AMFBS_HasFP16,
10142 AMFBS_HasFPARMv8,
10143 AMFBS_HasFPRegs,
10144 AMFBS_HasFPRegs16,
10145 AMFBS_HasFPRegs64,
10146 AMFBS_HasFPRegsV8_1M,
10147 AMFBS_HasFullFP16,
10148 AMFBS_HasMVEFloat,
10149 AMFBS_HasMVEInt,
10150 AMFBS_HasMatMulInt8,
10151 AMFBS_HasNEON,
10152 AMFBS_HasV8_1MMainline,
10153 AMFBS_HasVFP2,
10154 AMFBS_HasVFP3,
10155 AMFBS_HasVFP4,
10156 AMFBS_IsARM,
10157 AMFBS_IsThumb,
10158 AMFBS_IsThumb2,
10159 AMFBS_HasBF16_HasNEON,
10160 AMFBS_HasCDE_HasFPRegs,
10161 AMFBS_HasCDE_HasMVEInt,
10162 AMFBS_HasDB_IsThumb2,
10163 AMFBS_HasDSP_IsThumb2,
10164 AMFBS_HasFPARMv8_HasDPVFP,
10165 AMFBS_HasFPARMv8_HasNEON,
10166 AMFBS_HasFPARMv8_HasV8_3a,
10167 AMFBS_HasFPRegs_HasV8_1MMainline,
10168 AMFBS_HasMVEInt_IsThumb,
10169 AMFBS_HasNEON_HasFP16,
10170 AMFBS_HasNEON_HasFP16FML,
10171 AMFBS_HasNEON_HasFullFP16,
10172 AMFBS_HasNEON_HasV8_1a,
10173 AMFBS_HasNEON_HasV8_3a,
10174 AMFBS_HasNEON_HasVFP4,
10175 AMFBS_HasV7_IsMClass,
10176 AMFBS_HasV8_HasAES,
10177 AMFBS_HasV8_HasNEON,
10178 AMFBS_HasV8_HasSHA2,
10179 AMFBS_HasV8MMainline_Has8MSecExt,
10180 AMFBS_HasV8_1MMainline_Has8MSecExt,
10181 AMFBS_HasV8_1MMainline_HasFPRegs,
10182 AMFBS_HasV8_1MMainline_HasMVEInt,
10183 AMFBS_HasVFP2_HasDPVFP,
10184 AMFBS_HasVFP3_HasDPVFP,
10185 AMFBS_HasVFP4_HasDPVFP,
10186 AMFBS_IsARM_HasAcquireRelease,
10187 AMFBS_IsARM_HasCRC,
10188 AMFBS_IsARM_HasDB,
10189 AMFBS_IsARM_HasDFB,
10190 AMFBS_IsARM_HasDivideInARM,
10191 AMFBS_IsARM_HasRAS,
10192 AMFBS_IsARM_HasSB,
10193 AMFBS_IsARM_HasTrustZone,
10194 AMFBS_IsARM_HasV4T,
10195 AMFBS_IsARM_HasV5T,
10196 AMFBS_IsARM_HasV5TE,
10197 AMFBS_IsARM_HasV6,
10198 AMFBS_IsARM_HasV6K,
10199 AMFBS_IsARM_HasV6T2,
10200 AMFBS_IsARM_HasV7,
10201 AMFBS_IsARM_HasV8,
10202 AMFBS_IsARM_HasV8_4a,
10203 AMFBS_IsARM_HasVirtualization,
10204 AMFBS_IsARM_PreV8,
10205 AMFBS_IsARM_UseNegativeImmediates,
10206 AMFBS_IsThumb_Has8MSecExt,
10207 AMFBS_IsThumb_HasAcquireRelease,
10208 AMFBS_IsThumb_HasDB,
10209 AMFBS_IsThumb_HasV5T,
10210 AMFBS_IsThumb_HasV6,
10211 AMFBS_IsThumb_HasV6M,
10212 AMFBS_IsThumb_HasV7Clrex,
10213 AMFBS_IsThumb_HasV8,
10214 AMFBS_IsThumb_HasV8MBaseline,
10215 AMFBS_IsThumb_HasV8_4a,
10216 AMFBS_IsThumb_HasVirtualization,
10217 AMFBS_IsThumb_IsMClass,
10218 AMFBS_IsThumb_IsNotMClass,
10219 AMFBS_IsThumb_UseNegativeImmediates,
10220 AMFBS_IsThumb2_HasCRC,
10221 AMFBS_IsThumb2_HasDSP,
10222 AMFBS_IsThumb2_HasRAS,
10223 AMFBS_IsThumb2_HasSB,
10224 AMFBS_IsThumb2_HasTrustZone,
10225 AMFBS_IsThumb2_HasV7,
10226 AMFBS_IsThumb2_HasV8,
10227 AMFBS_IsThumb2_HasVirtualization,
10228 AMFBS_IsThumb2_IsNotMClass,
10229 AMFBS_IsThumb2_PreV8,
10230 AMFBS_IsThumb2_UseNegativeImmediates,
10231 AMFBS_PreV8_IsThumb2,
10232 AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline,
10233 AMFBS_HasFPARMv8_HasNEON_HasFullFP16,
10234 AMFBS_HasNEON_HasV8_3a_HasFullFP16,
10235 AMFBS_HasV8_HasNEON_HasFullFP16,
10236 AMFBS_IsARM_HasAcquireRelease_HasV7Clrex,
10237 AMFBS_IsARM_HasV7_HasMP,
10238 AMFBS_IsARM_HasV8_HasCLRBHB,
10239 AMFBS_IsARM_HasV8_HasV8_1a,
10240 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex,
10241 AMFBS_IsThumb_HasV5T_IsNotMClass,
10242 AMFBS_IsThumb2_HasV7_HasMP,
10243 AMFBS_IsThumb2_HasV8_HasCLRBHB,
10244 AMFBS_IsThumb2_HasV8_HasV8_1a,
10245 AMFBS_IsThumb2_HasV8_1MMainline_HasLOB,
10246 AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI,
10247 AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass,
10248};
10249
10250static constexpr FeatureBitset FeatureBitsets[] = {
10251 {}, // AMFBS_None
10252 {Feature_Has8MSecExtBit, }, // AMFBS_Has8MSecExt
10253 {Feature_HasBF16Bit, }, // AMFBS_HasBF16
10254 {Feature_HasCDEBit, }, // AMFBS_HasCDE
10255 {Feature_HasDBBit, }, // AMFBS_HasDB
10256 {Feature_HasDFBBit, }, // AMFBS_HasDFB
10257 {Feature_HasDotProdBit, }, // AMFBS_HasDotProd
10258 {Feature_HasFP16Bit, }, // AMFBS_HasFP16
10259 {Feature_HasFPARMv8Bit, }, // AMFBS_HasFPARMv8
10260 {Feature_HasFPRegsBit, }, // AMFBS_HasFPRegs
10261 {Feature_HasFPRegs16Bit, }, // AMFBS_HasFPRegs16
10262 {Feature_HasFPRegs64Bit, }, // AMFBS_HasFPRegs64
10263 {Feature_HasFPRegsV8_1MBit, }, // AMFBS_HasFPRegsV8_1M
10264 {Feature_HasFullFP16Bit, }, // AMFBS_HasFullFP16
10265 {Feature_HasMVEFloatBit, }, // AMFBS_HasMVEFloat
10266 {Feature_HasMVEIntBit, }, // AMFBS_HasMVEInt
10267 {Feature_HasMatMulInt8Bit, }, // AMFBS_HasMatMulInt8
10268 {Feature_HasNEONBit, }, // AMFBS_HasNEON
10269 {Feature_HasV8_1MMainlineBit, }, // AMFBS_HasV8_1MMainline
10270 {Feature_HasVFP2Bit, }, // AMFBS_HasVFP2
10271 {Feature_HasVFP3Bit, }, // AMFBS_HasVFP3
10272 {Feature_HasVFP4Bit, }, // AMFBS_HasVFP4
10273 {Feature_IsARMBit, }, // AMFBS_IsARM
10274 {Feature_IsThumbBit, }, // AMFBS_IsThumb
10275 {Feature_IsThumb2Bit, }, // AMFBS_IsThumb2
10276 {Feature_HasBF16Bit, Feature_HasNEONBit, }, // AMFBS_HasBF16_HasNEON
10277 {Feature_HasCDEBit, Feature_HasFPRegsBit, }, // AMFBS_HasCDE_HasFPRegs
10278 {Feature_HasCDEBit, Feature_HasMVEIntBit, }, // AMFBS_HasCDE_HasMVEInt
10279 {Feature_HasDBBit, Feature_IsThumb2Bit, }, // AMFBS_HasDB_IsThumb2
10280 {Feature_HasDSPBit, Feature_IsThumb2Bit, }, // AMFBS_HasDSP_IsThumb2
10281 {Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, }, // AMFBS_HasFPARMv8_HasDPVFP
10282 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, // AMFBS_HasFPARMv8_HasNEON
10283 {Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, }, // AMFBS_HasFPARMv8_HasV8_3a
10284 {Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, }, // AMFBS_HasFPRegs_HasV8_1MMainline
10285 {Feature_HasMVEIntBit, Feature_IsThumbBit, }, // AMFBS_HasMVEInt_IsThumb
10286 {Feature_HasNEONBit, Feature_HasFP16Bit, }, // AMFBS_HasNEON_HasFP16
10287 {Feature_HasNEONBit, Feature_HasFP16FMLBit, }, // AMFBS_HasNEON_HasFP16FML
10288 {Feature_HasNEONBit, Feature_HasFullFP16Bit, }, // AMFBS_HasNEON_HasFullFP16
10289 {Feature_HasNEONBit, Feature_HasV8_1aBit, }, // AMFBS_HasNEON_HasV8_1a
10290 {Feature_HasNEONBit, Feature_HasV8_3aBit, }, // AMFBS_HasNEON_HasV8_3a
10291 {Feature_HasNEONBit, Feature_HasVFP4Bit, }, // AMFBS_HasNEON_HasVFP4
10292 {Feature_HasV7Bit, Feature_IsMClassBit, }, // AMFBS_HasV7_IsMClass
10293 {Feature_HasV8Bit, Feature_HasAESBit, }, // AMFBS_HasV8_HasAES
10294 {Feature_HasV8Bit, Feature_HasNEONBit, }, // AMFBS_HasV8_HasNEON
10295 {Feature_HasV8Bit, Feature_HasSHA2Bit, }, // AMFBS_HasV8_HasSHA2
10296 {Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, }, // AMFBS_HasV8MMainline_Has8MSecExt
10297 {Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, }, // AMFBS_HasV8_1MMainline_Has8MSecExt
10298 {Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, }, // AMFBS_HasV8_1MMainline_HasFPRegs
10299 {Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, }, // AMFBS_HasV8_1MMainline_HasMVEInt
10300 {Feature_HasVFP2Bit, Feature_HasDPVFPBit, }, // AMFBS_HasVFP2_HasDPVFP
10301 {Feature_HasVFP3Bit, Feature_HasDPVFPBit, }, // AMFBS_HasVFP3_HasDPVFP
10302 {Feature_HasVFP4Bit, Feature_HasDPVFPBit, }, // AMFBS_HasVFP4_HasDPVFP
10303 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, }, // AMFBS_IsARM_HasAcquireRelease
10304 {Feature_IsARMBit, Feature_HasCRCBit, }, // AMFBS_IsARM_HasCRC
10305 {Feature_IsARMBit, Feature_HasDBBit, }, // AMFBS_IsARM_HasDB
10306 {Feature_IsARMBit, Feature_HasDFBBit, }, // AMFBS_IsARM_HasDFB
10307 {Feature_IsARMBit, Feature_HasDivideInARMBit, }, // AMFBS_IsARM_HasDivideInARM
10308 {Feature_IsARMBit, Feature_HasRASBit, }, // AMFBS_IsARM_HasRAS
10309 {Feature_IsARMBit, Feature_HasSBBit, }, // AMFBS_IsARM_HasSB
10310 {Feature_IsARMBit, Feature_HasTrustZoneBit, }, // AMFBS_IsARM_HasTrustZone
10311 {Feature_IsARMBit, Feature_HasV4TBit, }, // AMFBS_IsARM_HasV4T
10312 {Feature_IsARMBit, Feature_HasV5TBit, }, // AMFBS_IsARM_HasV5T
10313 {Feature_IsARMBit, Feature_HasV5TEBit, }, // AMFBS_IsARM_HasV5TE
10314 {Feature_IsARMBit, Feature_HasV6Bit, }, // AMFBS_IsARM_HasV6
10315 {Feature_IsARMBit, Feature_HasV6KBit, }, // AMFBS_IsARM_HasV6K
10316 {Feature_IsARMBit, Feature_HasV6T2Bit, }, // AMFBS_IsARM_HasV6T2
10317 {Feature_IsARMBit, Feature_HasV7Bit, }, // AMFBS_IsARM_HasV7
10318 {Feature_IsARMBit, Feature_HasV8Bit, }, // AMFBS_IsARM_HasV8
10319 {Feature_IsARMBit, Feature_HasV8_4aBit, }, // AMFBS_IsARM_HasV8_4a
10320 {Feature_IsARMBit, Feature_HasVirtualizationBit, }, // AMFBS_IsARM_HasVirtualization
10321 {Feature_IsARMBit, Feature_PreV8Bit, }, // AMFBS_IsARM_PreV8
10322 {Feature_IsARMBit, Feature_UseNegativeImmediatesBit, }, // AMFBS_IsARM_UseNegativeImmediates
10323 {Feature_IsThumbBit, Feature_Has8MSecExtBit, }, // AMFBS_IsThumb_Has8MSecExt
10324 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, }, // AMFBS_IsThumb_HasAcquireRelease
10325 {Feature_IsThumbBit, Feature_HasDBBit, }, // AMFBS_IsThumb_HasDB
10326 {Feature_IsThumbBit, Feature_HasV5TBit, }, // AMFBS_IsThumb_HasV5T
10327 {Feature_IsThumbBit, Feature_HasV6Bit, }, // AMFBS_IsThumb_HasV6
10328 {Feature_IsThumbBit, Feature_HasV6MBit, }, // AMFBS_IsThumb_HasV6M
10329 {Feature_IsThumbBit, Feature_HasV7ClrexBit, }, // AMFBS_IsThumb_HasV7Clrex
10330 {Feature_IsThumbBit, Feature_HasV8Bit, }, // AMFBS_IsThumb_HasV8
10331 {Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, // AMFBS_IsThumb_HasV8MBaseline
10332 {Feature_IsThumbBit, Feature_HasV8_4aBit, }, // AMFBS_IsThumb_HasV8_4a
10333 {Feature_IsThumbBit, Feature_HasVirtualizationBit, }, // AMFBS_IsThumb_HasVirtualization
10334 {Feature_IsThumbBit, Feature_IsMClassBit, }, // AMFBS_IsThumb_IsMClass
10335 {Feature_IsThumbBit, Feature_IsNotMClassBit, }, // AMFBS_IsThumb_IsNotMClass
10336 {Feature_IsThumbBit, Feature_UseNegativeImmediatesBit, }, // AMFBS_IsThumb_UseNegativeImmediates
10337 {Feature_IsThumb2Bit, Feature_HasCRCBit, }, // AMFBS_IsThumb2_HasCRC
10338 {Feature_IsThumb2Bit, Feature_HasDSPBit, }, // AMFBS_IsThumb2_HasDSP
10339 {Feature_IsThumb2Bit, Feature_HasRASBit, }, // AMFBS_IsThumb2_HasRAS
10340 {Feature_IsThumb2Bit, Feature_HasSBBit, }, // AMFBS_IsThumb2_HasSB
10341 {Feature_IsThumb2Bit, Feature_HasTrustZoneBit, }, // AMFBS_IsThumb2_HasTrustZone
10342 {Feature_IsThumb2Bit, Feature_HasV7Bit, }, // AMFBS_IsThumb2_HasV7
10343 {Feature_IsThumb2Bit, Feature_HasV8Bit, }, // AMFBS_IsThumb2_HasV8
10344 {Feature_IsThumb2Bit, Feature_HasVirtualizationBit, }, // AMFBS_IsThumb2_HasVirtualization
10345 {Feature_IsThumb2Bit, Feature_IsNotMClassBit, }, // AMFBS_IsThumb2_IsNotMClass
10346 {Feature_IsThumb2Bit, Feature_PreV8Bit, }, // AMFBS_IsThumb2_PreV8
10347 {Feature_IsThumb2Bit, Feature_UseNegativeImmediatesBit, }, // AMFBS_IsThumb2_UseNegativeImmediates
10348 {Feature_PreV8Bit, Feature_IsThumb2Bit, }, // AMFBS_PreV8_IsThumb2
10349 {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, // AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline
10350 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, // AMFBS_HasFPARMv8_HasNEON_HasFullFP16
10351 {Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, }, // AMFBS_HasNEON_HasV8_3a_HasFullFP16
10352 {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, // AMFBS_HasV8_HasNEON_HasFullFP16
10353 {Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, // AMFBS_IsARM_HasAcquireRelease_HasV7Clrex
10354 {Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, }, // AMFBS_IsARM_HasV7_HasMP
10355 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasCLRBHBBit, }, // AMFBS_IsARM_HasV8_HasCLRBHB
10356 {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, // AMFBS_IsARM_HasV8_HasV8_1a
10357 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, // AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex
10358 {Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, }, // AMFBS_IsThumb_HasV5T_IsNotMClass
10359 {Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, }, // AMFBS_IsThumb2_HasV7_HasMP
10360 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasCLRBHBBit, }, // AMFBS_IsThumb2_HasV8_HasCLRBHB
10361 {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, // AMFBS_IsThumb2_HasV8_HasV8_1a
10362 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, }, // AMFBS_IsThumb2_HasV8_1MMainline_HasLOB
10363 {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasPACBTIBit, }, // AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI
10364 {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, }, // AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass
10365};
10366
10367namespace {
10368 struct MatchEntry {
10369 uint16_t Mnemonic;
10370 uint32_t Opcode;
10371 uint16_t ConvertFn;
10372 uint8_t RequiredFeaturesIdx;
10373 uint16_t Classes[18];
10374 StringRef getMnemonic() const {
10375 return StringRef(MnemonicTable + Mnemonic + 1,
10376 MnemonicTable[Mnemonic]);
10377 }
10378 };
10379
10380 // Predicate for searching for an opcode.
10381 struct LessOpcode {
10382 bool operator()(const MatchEntry &LHS, StringRef RHS) {
10383 return LHS.getMnemonic() < RHS;
10384 }
10385 bool operator()(StringRef LHS, const MatchEntry &RHS) {
10386 return LHS < RHS.getMnemonic();
10387 }
10388 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
10389 return LHS.getMnemonic() < RHS.getMnemonic();
10390 }
10391 };
10392} // end anonymous namespace
10393
10394static const MatchEntry MatchTable0[] = {
10395 { 0 /* __brkdiv0 */, ARM::t__brkdiv0, Convert_NoOperands, AMFBS_IsThumb, { }, },
10396 { 10 /* adc */, ARM::tADC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10397 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10398 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10399 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10400 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10401 { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10402 { 10 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10403 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10404 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10405 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10406 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10407 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10408 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10409 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10410 { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10411 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10412 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10413 { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10414 { 10 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10415 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
10416 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10417 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10418 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
10419 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10420 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10421 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10422 { 14 /* add */, ARM::tADDspr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPR }, },
10423 { 14 /* add */, ARM::tADDspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
10424 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
10425 { 14 /* add */, ARM::tADDhirr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10426 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10427 { 14 /* add */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_255Expr1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255Expr }, },
10428 { 14 /* add */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
10429 { 14 /* add */, ARM::tADDspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
10430 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4Neg }, },
10431 { 14 /* add */, ARM::tADDrSPi, Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_GPRsp, MCK_Imm0_1020s4 }, },
10432 { 14 /* add */, ARM::tADDrSP, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPRsp, MCK_GPR }, },
10433 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
10434 { 14 /* add */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
10435 { 14 /* add */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
10436 { 14 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
10437 { 14 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10438 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
10439 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, },
10440 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, },
10441 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, },
10442 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImmNeg }, },
10443 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10444 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10445 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10446 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
10447 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
10448 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10449 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10450 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
10451 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10452 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10453 { 14 /* add */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
10454 { 14 /* add */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10455 { 14 /* add */, ARM::t2ADR, Convert__Reg1_1__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_PC, MCK_Imm0_4095 }, },
10456 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
10457 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, },
10458 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, },
10459 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImmNeg }, },
10460 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNeg }, },
10461 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
10462 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10463 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10464 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
10465 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10466 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10467 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
10468 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
10469 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10470 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10471 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
10472 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10473 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10474 { 14 /* add */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
10475 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10476 { 14 /* add */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
10477 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
10478 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10479 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
10480 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
10481 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
10482 { 18 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
10483 { 18 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10484 { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
10485 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095Neg }, },
10486 { 18 /* addw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
10487 { 18 /* addw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
10488 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_4095Neg }, },
10489 { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
10490 { 23 /* adr */, ARM::tADR, Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_UnsignedOffset_b8s2 }, },
10491 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10492 { 23 /* adr */, ARM::ADR, Convert__Reg1_1__AdrLabel1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AdrLabel }, },
10493 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm }, },
10494 { 27 /* aesd */, ARM::AESD, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10495 { 32 /* aese */, ARM::AESE, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10496 { 37 /* aesimc */, ARM::AESIMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10497 { 44 /* aesmc */, ARM::AESMC, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasAES, { MCK__DOT_8, MCK_QPR, MCK_QPR }, },
10498 { 50 /* and */, ARM::tAND, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10499 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10500 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10501 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10502 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10503 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10504 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10505 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10506 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10507 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10508 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10509 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10510 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10511 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, },
10512 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10513 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10514 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10515 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10516 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10517 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10518 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
10519 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10520 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10521 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10522 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10523 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10524 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10525 { 54 /* asr */, ARM::tASRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10526 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
10527 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
10528 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10529 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
10530 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
10531 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
10532 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10533 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
10534 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10535 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
10536 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10537 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
10538 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10539 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
10540 { 58 /* asrl */, ARM::MVE_ASRLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, },
10541 { 58 /* asrl */, ARM::MVE_ASRLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
10542 { 63 /* aut */, ARM::t2AUT, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
10543 { 63 /* aut */, ARM::t2HINT, Convert__imm_95_45__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
10544 { 67 /* autg */, ARM::t2AUTG, Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_GPRnosp, MCK_GPRnopc, MCK_GPRnopc }, },
10545 { 72 /* b */, ARM::tB, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm }, },
10546 { 72 /* b */, ARM::tBcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
10547 { 72 /* b */, ARM::Bcc, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
10548 { 72 /* b */, ARM::t2Bcc, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
10549 { 72 /* b */, ARM::t2B, ConvertCustom_cvtThumbBranches, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, },
10550 { 74 /* bf */, ARM::t2BFi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, },
10551 { 77 /* bfc */, ARM::t2BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Bitfield }, },
10552 { 77 /* bfc */, ARM::BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Bitfield }, },
10553 { 81 /* bfcsel */, ARM::t2BFic, Convert__Imm1_0__Imm1_1__Imm1_2__CondCodeNoAL1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_Imm, MCK_Imm, MCK_Imm, MCK_CondCodeNoAL }, },
10554 { 88 /* bfi */, ARM::t2BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Bitfield }, },
10555 { 88 /* bfi */, ARM::BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Bitfield }, },
10556 { 92 /* bfl */, ARM::t2BFLi, Convert__Imm1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_Imm }, },
10557 { 96 /* bflx */, ARM::t2BFLr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, },
10558 { 101 /* bfx */, ARM::t2BFr, Convert__Imm1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_CondCode, MCK_Imm, MCK_rGPR }, },
10559 { 105 /* bic */, ARM::tBIC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10560 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10561 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10562 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10563 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
10564 { 105 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10565 { 105 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10566 { 105 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10567 { 105 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10568 { 105 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10569 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10570 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10571 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10572 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, },
10573 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10574 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10575 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10576 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10577 { 105 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10578 { 105 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10579 { 105 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
10580 { 105 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10581 { 105 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10582 { 105 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10583 { 105 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10584 { 105 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10585 { 105 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
10586 { 109 /* bkpt */, ARM::tBKPT, Convert__imm_95_0, AMFBS_IsThumb, { }, },
10587 { 109 /* bkpt */, ARM::tBKPT, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, },
10588 { 109 /* bkpt */, ARM::BKPT, Convert__imm_95_0, AMFBS_IsARM, { }, },
10589 { 109 /* bkpt */, ARM::BKPT, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, },
10590 { 114 /* bl */, ARM::BL, Convert__ARMBranchTarget1_0, AMFBS_IsARM, { MCK_ARMBranchTarget }, },
10591 { 114 /* bl */, ARM::BL_pred, Convert__ARMBranchTarget1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, },
10592 { 114 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, },
10593 { 114 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, },
10594 { 117 /* blx */, ARM::tBLXr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_HasV5T, { MCK_CondCode, MCK_GPR }, },
10595 { 117 /* blx */, ARM::BLX, Convert__Reg1_0, AMFBS_IsARM_HasV5T, { MCK_GPR }, },
10596 { 117 /* blx */, ARM::BLXi, Convert__ThumbBranchTarget1_0, AMFBS_IsARM_HasV5T, { MCK_ThumbBranchTarget }, },
10597 { 117 /* blx */, ARM::BLX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR }, },
10598 { 117 /* blx */, ARM::tBLXi, Convert__CondCode2_0__ARMBranchTarget1_1, AMFBS_IsThumb_HasV5T_IsNotMClass, { MCK_CondCode, MCK_ARMBranchTarget }, },
10599 { 121 /* blxns */, ARM::tBLXNSr, Convert__CondCode2_0__Reg1_1, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
10600 { 127 /* bti */, ARM::t2BTI, Convert_NoOperands, AMFBS_HasV7_IsMClass, { }, },
10601 { 127 /* bti */, ARM::t2HINT, Convert__imm_95_15__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode }, },
10602 { 131 /* bx */, ARM::tBX, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR }, },
10603 { 131 /* bx */, ARM::BX, Convert__Reg1_0, AMFBS_IsARM_HasV4T, { MCK_GPR }, },
10604 { 131 /* bx */, ARM::BX_RET, Convert__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPRlr }, },
10605 { 131 /* bx */, ARM::BX_pred, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM_HasV4T, { MCK_CondCode, MCK_GPR }, },
10606 { 134 /* bxaut */, ARM::t2BXAUT, Convert__CondCode2_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_GPRnosp, MCK_rGPR, MCK_GPRnopc }, },
10607 { 140 /* bxj */, ARM::t2BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRnopc }, },
10608 { 140 /* bxj */, ARM::BXJ, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR }, },
10609 { 144 /* bxns */, ARM::tBXNS, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_GPR }, },
10610 { 149 /* cbnz */, ARM::tCBNZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
10611 { 154 /* cbz */, ARM::tCBZ, Convert__Reg1_0__ThumbBranchTarget1_1, AMFBS_IsThumb_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, },
10612 { 158 /* cdp */, ARM::CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10613 { 158 /* cdp */, ARM::t2CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10614 { 162 /* cdp2 */, ARM::CDP2, Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10615 { 162 /* cdp2 */, ARM::t2CDP2, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
10616 { 167 /* cinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, },
10617 { 172 /* cinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, },
10618 { 177 /* clrbhb */, ARM::HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsARM_HasV8_HasCLRBHB, { MCK_CondCode }, },
10619 { 177 /* clrbhb */, ARM::t2HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsThumb2_HasV8_HasCLRBHB, { MCK_CondCode }, },
10620 { 177 /* clrbhb */, ARM::HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsARM_HasV8, { MCK_CondCode }, },
10621 { 177 /* clrbhb */, ARM::t2HINT, Convert__imm_95_22__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
10622 { 184 /* clrex */, ARM::CLREX, Convert_NoOperands, AMFBS_IsARM_HasV6K, { }, },
10623 { 184 /* clrex */, ARM::t2CLREX, Convert__CondCode2_0, AMFBS_IsThumb_HasV7Clrex, { MCK_CondCode }, },
10624 { 190 /* clrm */, ARM::t2CLRM, Convert__CondCode2_0__RegListWithAPSR1_1, AMFBS_HasV8_1MMainline, { MCK_CondCode, MCK_RegListWithAPSR }, },
10625 { 195 /* clz */, ARM::t2CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10626 { 195 /* clz */, ARM::CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV5T, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10627 { 199 /* cmn */, ARM::tCMN, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10628 { 199 /* cmn */, ARM::CMPri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
10629 { 199 /* cmn */, ARM::t2CMPri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10630 { 199 /* cmn */, ARM::t2CMNrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
10631 { 199 /* cmn */, ARM::t2CMNrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
10632 { 199 /* cmn */, ARM::CMNrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10633 { 199 /* cmn */, ARM::t2CMNri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
10634 { 199 /* cmn */, ARM::CMNrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10635 { 199 /* cmn */, ARM::CMNri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10636 { 199 /* cmn */, ARM::CMNrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10637 { 199 /* cmn */, ARM::t2CMNrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
10638 { 199 /* cmn */, ARM::t2CMNrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
10639 { 199 /* cmn */, ARM::t2CMNri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
10640 { 203 /* cmp */, ARM::tCMPr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10641 { 203 /* cmp */, ARM::tCMPi8, Convert__Reg1_1__Imm0_2551_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
10642 { 203 /* cmp */, ARM::tCMPhir, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10643 { 203 /* cmp */, ARM::CMNri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, },
10644 { 203 /* cmp */, ARM::t2CMNri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, },
10645 { 203 /* cmp */, ARM::t2CMPrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
10646 { 203 /* cmp */, ARM::CMPrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
10647 { 203 /* cmp */, ARM::t2CMPri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, },
10648 { 203 /* cmp */, ARM::CMPrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
10649 { 203 /* cmp */, ARM::CMPri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10650 { 203 /* cmp */, ARM::CMPrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10651 { 203 /* cmp */, ARM::t2CMPrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
10652 { 203 /* cmp */, ARM::t2CMPrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, },
10653 { 203 /* cmp */, ARM::t2CMPri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, },
10654 { 207 /* cneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_1__CondCodeNoALInv1_2, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_CondCodeNoALInv }, },
10655 { 212 /* cps */, ARM::tCPS, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsThumb, { MCK_Imm, MCK_ProcIFlags }, },
10656 { 212 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_0, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm0_31 }, },
10657 { 212 /* cps */, ARM::CPS1p, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
10658 { 212 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_31 }, },
10659 { 212 /* cps */, ARM::CPS2p, Convert__Imm1_0__ProcIFlags1_1, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags }, },
10660 { 212 /* cps */, ARM::t2CPS2p, Convert__Imm1_0__ProcIFlags1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags }, },
10661 { 212 /* cps */, ARM::CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, AMFBS_IsARM, { MCK_Imm, MCK_ProcIFlags, MCK_Imm0_31 }, },
10662 { 212 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm1_2, AMFBS_IsThumb2_IsNotMClass, { MCK_Imm, MCK_ProcIFlags, MCK_Imm }, },
10663 { 212 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_2__Imm1_3, AMFBS_IsThumb2, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags, MCK_Imm }, },
10664 { 216 /* crc32b */, ARM::t2CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10665 { 216 /* crc32b */, ARM::CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10666 { 223 /* crc32cb */, ARM::t2CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10667 { 223 /* crc32cb */, ARM::CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10668 { 231 /* crc32ch */, ARM::t2CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10669 { 231 /* crc32ch */, ARM::CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10670 { 239 /* crc32cw */, ARM::t2CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10671 { 239 /* crc32cw */, ARM::CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10672 { 247 /* crc32h */, ARM::t2CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10673 { 247 /* crc32h */, ARM::CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10674 { 254 /* crc32w */, ARM::t2CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsThumb2_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10675 { 254 /* crc32w */, ARM::CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsARM_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
10676 { 261 /* csdb */, ARM::HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
10677 { 261 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode }, },
10678 { 261 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
10679 { 266 /* csel */, ARM::t2CSEL, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
10680 { 271 /* cset */, ARM::t2CSINC, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, },
10681 { 276 /* csetm */, ARM::t2CSINV, Convert__Reg1_0__regZR__regZR__CondCodeNoALInv1_1, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_CondCodeNoALInv }, },
10682 { 282 /* csinc */, ARM::t2CSINC, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
10683 { 288 /* csinv */, ARM::t2CSINV, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
10684 { 294 /* csneg */, ARM::t2CSNEG, Convert__Reg1_0__Reg1_1__Reg1_2__CondCodeNoAL1_3, AMFBS_HasV8_1MMainline, { MCK_rGPR, MCK_GPRwithZRnosp, MCK_GPRwithZRnosp, MCK_CondCodeNoAL }, },
10685 { 300 /* cx1 */, ARM::CDE_CX1, Convert__Reg1_1__CoprocNum1_0__Imm13b1_2, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm13b }, },
10686 { 304 /* cx1a */, ARM::CDE_CX1A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm13b }, },
10687 { 309 /* cx1d */, ARM::CDE_CX1D, Convert__Reg1_1__CoprocNum1_0__Imm13b1_2, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_Imm13b }, },
10688 { 314 /* cx1da */, ARM::CDE_CX1DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm13b1_3__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_Imm13b }, },
10689 { 320 /* cx2 */, ARM::CDE_CX2, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
10690 { 324 /* cx2a */, ARM::CDE_CX2A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
10691 { 329 /* cx2d */, ARM::CDE_CX2D, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm9b1_3, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
10692 { 334 /* cx2da */, ARM::CDE_CX2DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm9b1_4__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm9b }, },
10693 { 340 /* cx3 */, ARM::CDE_CX3, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
10694 { 344 /* cx3a */, ARM::CDE_CX3A, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
10695 { 349 /* cx3d */, ARM::CDE_CX3D, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm6b1_4, AMFBS_HasCDE, { MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
10696 { 354 /* cx3da */, ARM::CDE_CX3DA, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm6b1_5__CondCode2_0, AMFBS_HasCDE, { MCK_CondCode, MCK_CoprocNum, MCK_GPRPairnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_GPRwithAPSR_NZCVnosp, MCK_Imm6b }, },
10697 { 360 /* dbg */, ARM::DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasV7, { MCK_CondCode, MCK_Imm0_15 }, },
10698 { 360 /* dbg */, ARM::t2DBG, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_15 }, },
10699 { 360 /* dbg */, ARM::t2DBG, Convert__Imm0_151_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_15 }, },
10700 { 364 /* dcps1 */, ARM::t2DCPS1, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
10701 { 370 /* dcps2 */, ARM::t2DCPS2, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
10702 { 376 /* dcps3 */, ARM::t2DCPS3, Convert__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
10703 { 382 /* dfb */, ARM::DSB, Convert__imm_95_12, AMFBS_IsARM_HasDFB, { }, },
10704 { 382 /* dfb */, ARM::t2DSB, Convert__imm_95_12__CondCode2_0, AMFBS_HasDFB, { MCK_CondCode }, },
10705 { 386 /* dls */, ARM::t2DLS, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR }, },
10706 { 390 /* dlstp */, ARM::MVE_DLSTP_16, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR }, },
10707 { 390 /* dlstp */, ARM::MVE_DLSTP_32, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR }, },
10708 { 390 /* dlstp */, ARM::MVE_DLSTP_64, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR }, },
10709 { 390 /* dlstp */, ARM::MVE_DLSTP_8, Convert__Reg1_1__Reg1_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR }, },
10710 { 396 /* dmb */, ARM::DMB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, },
10711 { 396 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, },
10712 { 396 /* dmb */, ARM::DMB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, },
10713 { 396 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, },
10714 { 396 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
10715 { 396 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_MemBarrierOpt }, },
10716 { 400 /* dsb */, ARM::DSB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, },
10717 { 400 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, },
10718 { 400 /* dsb */, ARM::DSB, Convert__MemBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_MemBarrierOpt }, },
10719 { 400 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, },
10720 { 400 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, },
10721 { 400 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_MemBarrierOpt }, },
10722 { 404 /* eor */, ARM::tEOR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10723 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
10724 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
10725 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
10726 { 404 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
10727 { 404 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10728 { 404 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
10729 { 404 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
10730 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
10731 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
10732 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
10733 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10734 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10735 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10736 { 404 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
10737 { 404 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10738 { 404 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
10739 { 404 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
10740 { 404 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
10741 { 404 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
10742 { 404 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
10743 { 408 /* eret */, ARM::ERET, Convert__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode }, },
10744 { 408 /* eret */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2_HasVirtualization, { MCK_CondCode }, },
10745 { 413 /* esb */, ARM::HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsARM_HasRAS, { MCK_CondCode }, },
10746 { 413 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode }, },
10747 { 413 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, AMFBS_IsThumb2_HasRAS, { MCK_CondCode, MCK__DOT_w }, },
10748 { 417 /* faddd */, ARM::VADDD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
10749 { 423 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
10750 { 429 /* fcmpzd */, ARM::VCMPZD, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR }, },
10751 { 436 /* fcmpzs */, ARM::VCMPZS, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR }, },
10752 { 443 /* fconstd */, ARM::FCONSTD, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_DPR, MCK_FPImm }, },
10753 { 451 /* fconsts */, ARM::FCONSTS, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_HPR, MCK_FPImm }, },
10754 { 459 /* fldmdbx */, ARM::FLDMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10755 { 467 /* fldmiax */, ARM::FLDMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
10756 { 467 /* fldmiax */, ARM::FLDMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10757 { 475 /* fmdhr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
10758 { 481 /* fmdlr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, },
10759 { 487 /* fmstat */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode }, },
10760 { 494 /* fstmdbx */, ARM::FSTMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10761 { 502 /* fstmiax */, ARM::FSTMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
10762 { 502 /* fstmiax */, ARM::FSTMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10763 { 510 /* fsubd */, ARM::VSUBD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
10764 { 516 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
10765 { 522 /* hint */, ARM::tHINT, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode, MCK_Imm0_15 }, },
10766 { 522 /* hint */, ARM::HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_Imm0_239 }, },
10767 { 522 /* hint */, ARM::t2HINT, Convert__Imm0_2391_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_239 }, },
10768 { 522 /* hint */, ARM::t2HINT, Convert__Imm0_2391_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_239 }, },
10769 { 527 /* hlt */, ARM::tHLT, Convert__Imm0_631_0, AMFBS_IsThumb_HasV8, { MCK_Imm0_63 }, },
10770 { 527 /* hlt */, ARM::HLT, Convert__Imm0_655351_0, AMFBS_IsARM_HasV8, { MCK_Imm0_65535 }, },
10771 { 531 /* hvc */, ARM::HVC, Convert__Imm0_655351_0, AMFBS_IsARM_HasVirtualization, { MCK_Imm0_65535 }, },
10772 { 531 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_0, AMFBS_IsThumb2_HasVirtualization, { MCK_Imm0_65535 }, },
10773 { 531 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_1, AMFBS_IsThumb2_HasVirtualization, { MCK__DOT_w, MCK_Imm0_65535 }, },
10774 { 535 /* isb */, ARM::ISB, Convert__imm_95_15, AMFBS_IsARM_HasDB, { }, },
10775 { 535 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode }, },
10776 { 535 /* isb */, ARM::ISB, Convert__InstSyncBarrierOpt1_0, AMFBS_IsARM_HasDB, { MCK_InstSyncBarrierOpt }, },
10777 { 535 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w }, },
10778 { 535 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasDB, { MCK_CondCode, MCK_InstSyncBarrierOpt }, },
10779 { 535 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_2__CondCode2_0, AMFBS_HasDB, { MCK_CondCode, MCK__DOT_w, MCK_InstSyncBarrierOpt }, },
10780 { 539 /* it */, ARM::t2IT, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsThumb2, { MCK_ITMask, MCK_ITCondCode }, },
10781 { 539 /* it */, ARM::ITasm, Convert__ITCondCode1_1__ITMask1_0, AMFBS_IsARM, { MCK_ITMask, MCK_ITCondCode }, },
10782 { 542 /* lctp */, ARM::MVE_LCTP, Convert__CondCode2_0, AMFBS_HasMVEInt, { MCK_CondCode }, },
10783 { 547 /* lda */, ARM::t2LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10784 { 547 /* lda */, ARM::LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10785 { 551 /* ldab */, ARM::t2LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10786 { 551 /* ldab */, ARM::LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10787 { 556 /* ldaex */, ARM::t2LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10788 { 556 /* ldaex */, ARM::LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10789 { 562 /* ldaexb */, ARM::t2LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10790 { 562 /* ldaexb */, ARM::LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10791 { 569 /* ldaexd */, ARM::LDAEXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
10792 { 569 /* ldaexd */, ARM::t2LDAEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
10793 { 576 /* ldaexh */, ARM::t2LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10794 { 576 /* ldaexh */, ARM::LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10795 { 583 /* ldah */, ARM::t2LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10796 { 583 /* ldah */, ARM::LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10797 { 588 /* ldc */, ARM::LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10798 { 588 /* ldc */, ARM::t2LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10799 { 588 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10800 { 588 /* ldc */, ARM::t2LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10801 { 588 /* ldc */, ARM::LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10802 { 588 /* ldc */, ARM::t2LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10803 { 588 /* ldc */, ARM::LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10804 { 588 /* ldc */, ARM::t2LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10805 { 592 /* ldc2 */, ARM::LDC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10806 { 592 /* ldc2 */, ARM::t2LDC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10807 { 592 /* ldc2 */, ARM::LDC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10808 { 592 /* ldc2 */, ARM::LDC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10809 { 592 /* ldc2 */, ARM::LDC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10810 { 592 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10811 { 592 /* ldc2 */, ARM::t2LDC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10812 { 592 /* ldc2 */, ARM::t2LDC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10813 { 597 /* ldc2l */, ARM::LDC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10814 { 597 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10815 { 597 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10816 { 597 /* ldc2l */, ARM::LDC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10817 { 597 /* ldc2l */, ARM::LDC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10818 { 597 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10819 { 597 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10820 { 597 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10821 { 603 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10822 { 603 /* ldcl */, ARM::t2LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
10823 { 603 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10824 { 603 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10825 { 603 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10826 { 603 /* ldcl */, ARM::t2LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
10827 { 603 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10828 { 603 /* ldcl */, ARM::t2LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
10829 { 608 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_RegList }, },
10830 { 608 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
10831 { 608 /* ldm */, ARM::LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10832 { 608 /* ldm */, ARM::t2LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10833 { 608 /* ldm */, ARM::t2LDMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
10834 { 608 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10835 { 608 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10836 { 608 /* ldm */, ARM::sysLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10837 { 608 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10838 { 608 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10839 { 612 /* ldmda */, ARM::LDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10840 { 612 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10841 { 612 /* ldmda */, ARM::sysLDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10842 { 612 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10843 { 618 /* ldmdb */, ARM::LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10844 { 618 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10845 { 618 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
10846 { 618 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10847 { 618 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10848 { 618 /* ldmdb */, ARM::sysLDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10849 { 618 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10850 { 618 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10851 { 624 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
10852 { 624 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10853 { 624 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
10854 { 624 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10855 { 630 /* ldr */, ARM::tLDRpci, Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ThumbMemPC }, },
10856 { 630 /* ldr */, ARM::tLDRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
10857 { 630 /* ldr */, ARM::tLDRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10858 { 630 /* ldr */, ARM::tLDRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
10859 { 630 /* ldr */, ARM::tLDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ConstPoolAsmImm }, },
10860 { 630 /* ldr */, ARM::t2LDRpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_Imm }, },
10861 { 630 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
10862 { 630 /* ldr */, ARM::t2LDRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
10863 { 630 /* ldr */, ARM::LDRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
10864 { 630 /* ldr */, ARM::LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
10865 { 630 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, },
10866 { 630 /* ldr */, ARM::t2LDRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
10867 { 630 /* ldr */, ARM::t2LDRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
10868 { 630 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemPCRelImm12 }, },
10869 { 630 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_ConstPoolAsmImm }, },
10870 { 630 /* ldr */, ARM::t2LDRpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_Imm }, },
10871 { 630 /* ldr */, ARM::t2LDRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
10872 { 630 /* ldr */, ARM::t2LDRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
10873 { 630 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemPCRelImm12 }, },
10874 { 630 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
10875 { 630 /* ldr */, ARM::t2LDR_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10876 { 630 /* ldr */, ARM::LDR_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10877 { 630 /* ldr */, ARM::t2LDR_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10878 { 630 /* ldr */, ARM::LDR_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10879 { 630 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
10880 { 630 /* ldr */, ARM::t2LDR_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10881 { 630 /* ldr */, ARM::t2LDR_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10882 { 634 /* ldrb */, ARM::tLDRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
10883 { 634 /* ldrb */, ARM::tLDRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10884 { 634 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10885 { 634 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
10886 { 634 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
10887 { 634 /* ldrb */, ARM::LDRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
10888 { 634 /* ldrb */, ARM::t2LDRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
10889 { 634 /* ldrb */, ARM::LDRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
10890 { 634 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10891 { 634 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
10892 { 634 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
10893 { 634 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
10894 { 634 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10895 { 634 /* ldrb */, ARM::t2LDRB_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
10896 { 634 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
10897 { 634 /* ldrb */, ARM::t2LDRB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10898 { 634 /* ldrb */, ARM::LDRB_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10899 { 634 /* ldrb */, ARM::t2LDRB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10900 { 634 /* ldrb */, ARM::LDRB_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10901 { 634 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
10902 { 634 /* ldrb */, ARM::t2LDRB_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10903 { 634 /* ldrb */, ARM::t2LDRB_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10904 { 639 /* ldrbt */, ARM::t2LDRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10905 { 639 /* ldrbt */, ARM::LDRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10906 { 639 /* ldrbt */, ARM::LDRBT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10907 { 639 /* ldrbt */, ARM::LDRBT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10908 { 645 /* ldrd */, ARM::t2LDRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
10909 { 645 /* ldrd */, ARM::LDRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
10910 { 645 /* ldrd */, ARM::t2LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
10911 { 645 /* ldrd */, ARM::t2LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm8s4 }, },
10912 { 645 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10913 { 645 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10914 { 650 /* ldrex */, ARM::t2LDREX, Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
10915 { 650 /* ldrex */, ARM::LDREX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10916 { 656 /* ldrexb */, ARM::t2LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10917 { 656 /* ldrexb */, ARM::LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10918 { 663 /* ldrexd */, ARM::LDREXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, },
10919 { 663 /* ldrexd */, ARM::t2LDREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
10920 { 670 /* ldrexh */, ARM::t2LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
10921 { 670 /* ldrexh */, ARM::LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10922 { 677 /* ldrh */, ARM::tLDRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
10923 { 677 /* ldrh */, ARM::tLDRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10924 { 677 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10925 { 677 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
10926 { 677 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
10927 { 677 /* ldrh */, ARM::t2LDRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
10928 { 677 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10929 { 677 /* ldrh */, ARM::LDRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
10930 { 677 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
10931 { 677 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
10932 { 677 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
10933 { 677 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10934 { 677 /* ldrh */, ARM::t2LDRH_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
10935 { 677 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10936 { 677 /* ldrh */, ARM::t2LDRH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10937 { 677 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10938 { 677 /* ldrh */, ARM::t2LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10939 { 677 /* ldrh */, ARM::t2LDRH_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10940 { 677 /* ldrh */, ARM::t2LDRH_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10941 { 682 /* ldrht */, ARM::t2LDRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10942 { 682 /* ldrht */, ARM::LDRHTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10943 { 682 /* ldrht */, ARM::LDRHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
10944 { 682 /* ldrht */, ARM::LDRHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
10945 { 688 /* ldrsb */, ARM::tLDRSB, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10946 { 688 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10947 { 688 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
10948 { 688 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
10949 { 688 /* ldrsb */, ARM::t2LDRSBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
10950 { 688 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10951 { 688 /* ldrsb */, ARM::LDRSB, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
10952 { 688 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
10953 { 688 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
10954 { 688 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
10955 { 688 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10956 { 688 /* ldrsb */, ARM::t2LDRSB_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
10957 { 688 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10958 { 688 /* ldrsb */, ARM::t2LDRSB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10959 { 688 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10960 { 688 /* ldrsb */, ARM::t2LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10961 { 688 /* ldrsb */, ARM::t2LDRSB_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10962 { 688 /* ldrsb */, ARM::t2LDRSB_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10963 { 694 /* ldrsbt */, ARM::t2LDRSBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10964 { 694 /* ldrsbt */, ARM::LDRSBTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10965 { 694 /* ldrsbt */, ARM::LDRSBTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
10966 { 694 /* ldrsbt */, ARM::LDRSBTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
10967 { 701 /* ldrsh */, ARM::tLDRSH, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
10968 { 701 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, },
10969 { 701 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
10970 { 701 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
10971 { 701 /* ldrsh */, ARM::t2LDRSHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, },
10972 { 701 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10973 { 701 /* ldrsh */, ARM::LDRSH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
10974 { 701 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, },
10975 { 701 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, },
10976 { 701 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, },
10977 { 701 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, },
10978 { 701 /* ldrsh */, ARM::t2LDRSH_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
10979 { 701 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10980 { 701 /* ldrsh */, ARM::t2LDRSH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10981 { 701 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
10982 { 701 /* ldrsh */, ARM::t2LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10983 { 701 /* ldrsh */, ARM::t2LDRSH_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10984 { 701 /* ldrsh */, ARM::t2LDRSH_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
10985 { 707 /* ldrsht */, ARM::t2LDRSHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10986 { 707 /* ldrsht */, ARM::LDRSHTii, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10987 { 707 /* ldrsht */, ARM::LDRSHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, },
10988 { 707 /* ldrsht */, ARM::LDRSHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
10989 { 714 /* ldrt */, ARM::t2LDRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
10990 { 714 /* ldrt */, ARM::LDRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
10991 { 714 /* ldrt */, ARM::LDRT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
10992 { 714 /* ldrt */, ARM::LDRT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
10993 { 719 /* le */, ARM::t2LE, Convert__LELabel1_0, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_LELabel }, },
10994 { 719 /* le */, ARM::t2LEUpdate, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_LELabel }, },
10995 { 722 /* letp */, ARM::MVE_LETP, Convert__imm_95_0__Reg1_0__LELabel1_1, AMFBS_HasMVEInt, { MCK_GPRlr, MCK_LELabel }, },
10996 { 727 /* lsl */, ARM::tLSLrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
10997 { 727 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_31 }, },
10998 { 727 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_31 }, },
10999 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11000 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, },
11001 { 727 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11002 { 727 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
11003 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11004 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, },
11005 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11006 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11007 { 727 /* lsl */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, },
11008 { 727 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11009 { 727 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
11010 { 727 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11011 { 727 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11012 { 727 /* lsl */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK__HASH_0 }, },
11013 { 731 /* lsll */, ARM::MVE_LSLLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_rGPR }, },
11014 { 731 /* lsll */, ARM::MVE_LSLLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11015 { 736 /* lsr */, ARM::tLSRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11016 { 736 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, },
11017 { 736 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, },
11018 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11019 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, },
11020 { 736 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11021 { 736 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, },
11022 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11023 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, },
11024 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11025 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
11026 { 736 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11027 { 736 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, },
11028 { 736 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11029 { 736 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, },
11030 { 740 /* lsrl */, ARM::MVE_LSRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11031 { 745 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
11032 { 745 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
11033 { 745 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11034 { 745 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11035 { 749 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
11036 { 749 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, },
11037 { 749 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11038 { 749 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11039 { 754 /* mcrr */, ARM::MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
11040 { 754 /* mcrr */, ARM::t2MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
11041 { 759 /* mcrr2 */, ARM::MCRR2, Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
11042 { 759 /* mcrr2 */, ARM::t2MCRR2, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
11043 { 765 /* mla */, ARM::t2MLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11044 { 765 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11045 { 765 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11046 { 769 /* mls */, ARM::t2MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11047 { 769 /* mls */, ARM::MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11048 { 773 /* mov */, ARM::tMOVr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11049 { 773 /* mov */, ARM::tMOVi8, Convert__Reg1_2__CCOut1_0__Imm0_255Expr1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255Expr }, },
11050 { 773 /* mov */, ARM::MOVPCLR, Convert__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_PC, MCK_GPRlr }, },
11051 { 773 /* mov */, ARM::t2MOVi16, Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm256_65535Expr }, },
11052 { 773 /* mov */, ARM::t2MOVsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11053 { 773 /* mov */, ARM::t2MOVsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
11054 { 773 /* mov */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11055 { 773 /* mov */, ARM::t2MVNi, Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11056 { 773 /* mov */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
11057 { 773 /* mov */, ARM::MOVr_TC, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_tcGPR, MCK_tcGPR }, },
11058 { 773 /* mov */, ARM::MVNi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
11059 { 773 /* mov */, ARM::MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11060 { 773 /* mov */, ARM::MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11061 { 773 /* mov */, ARM::MOVi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11062 { 773 /* mov */, ARM::MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11063 { 773 /* mov */, ARM::t2MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11064 { 773 /* mov */, ARM::t2MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
11065 { 773 /* mov */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11066 { 773 /* mov */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
11067 { 773 /* mov */, ARM::t2MOVi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11068 { 773 /* mov */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
11069 { 777 /* movs */, ARM::tMOVSr, Convert__Reg1_0__Reg1_1, AMFBS_IsThumb, { MCK_tGPR, MCK_tGPR }, },
11070 { 777 /* movs */, ARM::tMOVi8, Convert__Reg1_0__regCPSR__Imm0_255Expr1_1__imm_95_14__reg0, AMFBS_IsThumb, { MCK_tGPR, MCK_Imm0_255Expr }, },
11071 { 777 /* movs */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_PC, MCK_GPRlr }, },
11072 { 777 /* movs */, ARM::t2MOVSsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11073 { 777 /* movs */, ARM::t2MOVSsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, },
11074 { 777 /* movs */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11075 { 777 /* movs */, ARM::t2MOVr, Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11076 { 777 /* movs */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_PC, MCK_GPRlr }, },
11077 { 777 /* movs */, ARM::t2MOVSsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11078 { 777 /* movs */, ARM::t2MOVSsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, },
11079 { 777 /* movs */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11080 { 777 /* movs */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, },
11081 { 782 /* movt */, ARM::t2MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
11082 { 782 /* movt */, ARM::MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_65535Expr }, },
11083 { 787 /* movw */, ARM::t2MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, },
11084 { 787 /* movw */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, },
11085 { 792 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
11086 { 792 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
11087 { 792 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11088 { 792 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11089 { 796 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, AMFBS_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
11090 { 796 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, },
11091 { 796 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11092 { 796 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, },
11093 { 801 /* mrrc */, ARM::MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
11094 { 801 /* mrrc */, ARM::t2MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
11095 { 806 /* mrrc2 */, ARM::MRRC2, Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, },
11096 { 806 /* mrrc2 */, ARM::t2MRRC2, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, AMFBS_IsThumb2_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, },
11097 { 812 /* mrs */, ARM::t2MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_rGPR, MCK_BankedReg }, },
11098 { 812 /* mrs */, ARM::t2MRS_M, Convert__Reg1_1__MSRMask1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_rGPR, MCK_MSRMask }, },
11099 { 812 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_APSR }, },
11100 { 812 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_CCR }, },
11101 { 812 /* mrs */, ARM::MRSsys, Convert__Reg1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_SPSR }, },
11102 { 812 /* mrs */, ARM::MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_GPRnopc, MCK_BankedReg }, },
11103 { 812 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_APSR }, },
11104 { 812 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_CCR }, },
11105 { 812 /* mrs */, ARM::t2MRSsys_AR, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_SPSR }, },
11106 { 816 /* msr */, ARM::t2MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_rGPR }, },
11107 { 816 /* msr */, ARM::MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_GPRnopc }, },
11108 { 816 /* msr */, ARM::t2MSR_AR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
11109 { 816 /* msr */, ARM::t2MSR_M, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_IsMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, },
11110 { 816 /* msr */, ARM::MSR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_GPR }, },
11111 { 816 /* msr */, ARM::MSRi, Convert__MSRMask1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_ModImm }, },
11112 { 820 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11113 { 820 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
11114 { 820 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11115 { 820 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11116 { 820 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11117 { 820 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11118 { 820 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11119 { 824 /* mvn */, ARM::tMVN, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11120 { 824 /* mvn */, ARM::t2MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11121 { 824 /* mvn */, ARM::MOVi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, },
11122 { 824 /* mvn */, ARM::t2MVNs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11123 { 824 /* mvn */, ARM::t2MVNi, Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11124 { 824 /* mvn */, ARM::t2MOVi, Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11125 { 824 /* mvn */, ARM::MVNsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11126 { 824 /* mvn */, ARM::MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11127 { 824 /* mvn */, ARM::MVNi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11128 { 824 /* mvn */, ARM::MVNsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11129 { 824 /* mvn */, ARM::t2MVNr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11130 { 824 /* mvn */, ARM::t2MVNs, Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11131 { 824 /* mvn */, ARM::t2MVNi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11132 { 828 /* neg */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11133 { 828 /* neg */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11134 { 828 /* neg */, ARM::RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11135 { 832 /* nop */, ARM::tMOVr, Convert__regR8__regR8__imm_95_14__reg0, AMFBS_IsThumb, { }, },
11136 { 832 /* nop */, ARM::tHINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
11137 { 832 /* nop */, ARM::HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
11138 { 832 /* nop */, ARM::MOVr, Convert__regR0__regR0__CondCode2_0__reg0, AMFBS_IsARM, { MCK_CondCode }, },
11139 { 832 /* nop */, ARM::t2HINT, Convert__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
11140 { 836 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11141 { 836 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11142 { 836 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11143 { 836 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11144 { 836 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11145 { 836 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11146 { 836 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11147 { 836 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
11148 { 836 /* orn */, ARM::t2ORNrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11149 { 836 /* orn */, ARM::t2ORNrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11150 { 836 /* orn */, ARM::t2ORNri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11151 { 840 /* orr */, ARM::tORR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11152 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11153 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11154 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11155 { 840 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11156 { 840 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11157 { 840 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11158 { 840 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11159 { 840 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11160 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11161 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11162 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11163 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11164 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11165 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11166 { 840 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
11167 { 840 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11168 { 840 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11169 { 840 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11170 { 840 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11171 { 840 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11172 { 840 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11173 { 840 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11174 { 844 /* pac */, ARM::t2PAC, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11175 { 844 /* pac */, ARM::t2HINT, Convert__imm_95_29__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11176 { 848 /* pacbti */, ARM::t2PACBTI, Convert_NoOperands, AMFBS_HasV7_IsMClass, { MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11177 { 848 /* pacbti */, ARM::t2HINT, Convert__imm_95_13__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_R12, MCK_GPRlr, MCK_GPRsp }, },
11178 { 855 /* pacg */, ARM::t2PACG, Convert__Reg1_1__CondCode2_0__Reg1_2__Reg1_3, AMFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_GPRnopc }, },
11179 { 860 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11180 { 860 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11181 { 860 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHLSLImm }, },
11182 { 860 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHLSLImm }, },
11183 { 866 /* pkhtb */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11184 { 866 /* pkhtb */, ARM::PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11185 { 866 /* pkhtb */, ARM::t2PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHASRImm }, },
11186 { 866 /* pkhtb */, ARM::PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHASRImm }, },
11187 { 872 /* pld */, ARM::PLDi12, Convert__MemImm12Offset2_0, AMFBS_IsARM, { MCK_MemImm12Offset }, },
11188 { 872 /* pld */, ARM::PLDrs, Convert__MemRegOffset3_0, AMFBS_IsARM, { MCK_MemRegOffset }, },
11189 { 872 /* pld */, ARM::t2PLDpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm }, },
11190 { 872 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemNegImm8Offset }, },
11191 { 872 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemUImm12Offset }, },
11192 { 872 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_T2MemRegOffset }, },
11193 { 872 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemPCRelImm12 }, },
11194 { 872 /* pld */, ARM::t2PLDpci, Convert__Imm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
11195 { 872 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, },
11196 { 872 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, },
11197 { 872 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, },
11198 { 872 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_MemPCRelImm12 }, },
11199 { 876 /* pldw */, ARM::PLDWi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemImm12Offset }, },
11200 { 876 /* pldw */, ARM::PLDWrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7_HasMP, { MCK_MemRegOffset }, },
11201 { 876 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemNegImm8Offset }, },
11202 { 876 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_MemUImm12Offset }, },
11203 { 876 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK_T2MemRegOffset }, },
11204 { 876 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, },
11205 { 876 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, },
11206 { 876 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2_HasV7_HasMP, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, },
11207 { 881 /* pli */, ARM::PLIi12, Convert__MemImm12Offset2_0, AMFBS_IsARM_HasV7, { MCK_MemImm12Offset }, },
11208 { 881 /* pli */, ARM::PLIrs, Convert__MemRegOffset3_0, AMFBS_IsARM_HasV7, { MCK_MemRegOffset }, },
11209 { 881 /* pli */, ARM::t2PLIpci, Convert__Imm1_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_Imm }, },
11210 { 881 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemNegImm8Offset }, },
11211 { 881 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemUImm12Offset }, },
11212 { 881 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_T2MemRegOffset }, },
11213 { 881 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_1__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK_MemPCRelImm12 }, },
11214 { 881 /* pli */, ARM::t2PLIpci, Convert__Imm1_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, },
11215 { 881 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemNegImm8Offset }, },
11216 { 881 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemUImm12Offset }, },
11217 { 881 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_T2MemRegOffset }, },
11218 { 881 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_2__CondCode2_0, AMFBS_IsThumb2_HasV7, { MCK_CondCode, MCK__DOT_w, MCK_MemPCRelImm12 }, },
11219 { 885 /* pop */, ARM::tPOP, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, },
11220 { 885 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, },
11221 { 885 /* pop */, ARM::LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, },
11222 { 885 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
11223 { 889 /* pssbb */, ARM::t2DSB, Convert__imm_95_4__imm_95_14__reg0, AMFBS_HasDB_IsThumb2, { }, },
11224 { 889 /* pssbb */, ARM::DSB, Convert__imm_95_4, AMFBS_IsARM_HasDB, { }, },
11225 { 895 /* push */, ARM::tPUSH, Convert__CondCode2_0__RegList1_1, AMFBS_IsThumb, { MCK_CondCode, MCK_RegList }, },
11226 { 895 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsThumb2, { MCK_CondCode, MCK_RegList }, },
11227 { 895 /* push */, ARM::STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, AMFBS_IsARM, { MCK_CondCode, MCK_RegList }, },
11228 { 895 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, },
11229 { 900 /* qadd */, ARM::t2QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11230 { 900 /* qadd */, ARM::QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11231 { 905 /* qadd16 */, ARM::t2QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11232 { 905 /* qadd16 */, ARM::QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11233 { 912 /* qadd8 */, ARM::t2QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11234 { 912 /* qadd8 */, ARM::QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11235 { 918 /* qasx */, ARM::t2QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11236 { 918 /* qasx */, ARM::QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11237 { 923 /* qdadd */, ARM::t2QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11238 { 923 /* qdadd */, ARM::QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11239 { 929 /* qdsub */, ARM::t2QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11240 { 929 /* qdsub */, ARM::QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11241 { 935 /* qsax */, ARM::t2QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11242 { 935 /* qsax */, ARM::QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11243 { 940 /* qsub */, ARM::t2QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11244 { 940 /* qsub */, ARM::QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11245 { 945 /* qsub16 */, ARM::t2QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11246 { 945 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11247 { 952 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11248 { 952 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11249 { 958 /* rbit */, ARM::t2RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11250 { 958 /* rbit */, ARM::RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11251 { 963 /* rev */, ARM::tREV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11252 { 963 /* rev */, ARM::t2REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11253 { 963 /* rev */, ARM::REV, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11254 { 963 /* rev */, ARM::t2REV, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11255 { 967 /* rev16 */, ARM::tREV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11256 { 967 /* rev16 */, ARM::t2REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11257 { 967 /* rev16 */, ARM::REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11258 { 967 /* rev16 */, ARM::t2REV16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11259 { 973 /* revsh */, ARM::tREVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11260 { 973 /* revsh */, ARM::t2REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11261 { 973 /* revsh */, ARM::REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11262 { 973 /* revsh */, ARM::t2REVSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11263 { 979 /* rfeda */, ARM::RFEDA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11264 { 979 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11265 { 985 /* rfedb */, ARM::RFEDB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11266 { 985 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11267 { 985 /* rfedb */, ARM::t2RFEDB, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
11268 { 985 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
11269 { 991 /* rfeia */, ARM::RFEIA, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11270 { 991 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11271 { 991 /* rfeia */, ARM::t2RFEIA, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR }, },
11272 { 991 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
11273 { 997 /* rfeib */, ARM::RFEIB, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR }, },
11274 { 997 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11275 { 1003 /* ror */, ARM::tROR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11276 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11277 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, },
11278 { 1003 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11279 { 1003 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, },
11280 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11281 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, },
11282 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11283 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11284 { 1003 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11285 { 1003 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, },
11286 { 1003 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11287 { 1003 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, },
11288 { 1007 /* rrx */, ARM::t2RRX, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11289 { 1007 /* rrx */, ARM::RRXi, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11290 { 1011 /* rsb */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK__HASH_0 }, },
11291 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11292 { 1011 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11293 { 1011 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11294 { 1011 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11295 { 1011 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11296 { 1011 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11297 { 1011 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11298 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11299 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11300 { 1011 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11301 { 1011 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11302 { 1011 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11303 { 1011 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11304 { 1011 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11305 { 1011 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11306 { 1011 /* rsb */, ARM::t2RSBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11307 { 1011 /* rsb */, ARM::t2RSBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11308 { 1011 /* rsb */, ARM::t2RSBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11309 { 1015 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11310 { 1015 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11311 { 1015 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11312 { 1015 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11313 { 1015 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11314 { 1015 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11315 { 1015 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11316 { 1015 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11317 { 1019 /* sadd16 */, ARM::t2SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11318 { 1019 /* sadd16 */, ARM::SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11319 { 1026 /* sadd8 */, ARM::t2SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11320 { 1026 /* sadd8 */, ARM::SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11321 { 1032 /* sasx */, ARM::t2SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11322 { 1032 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11323 { 1037 /* sb */, ARM::SB, Convert_NoOperands, AMFBS_IsARM_HasSB, { }, },
11324 { 1037 /* sb */, ARM::t2SB, Convert_NoOperands, AMFBS_IsThumb2_HasSB, { }, },
11325 { 1040 /* sbc */, ARM::tSBC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11326 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11327 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11328 { 1040 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11329 { 1040 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, },
11330 { 1040 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11331 { 1040 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11332 { 1040 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11333 { 1040 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
11334 { 1040 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11335 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11336 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11337 { 1040 /* sbc */, ARM::t2SBCri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11338 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11339 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11340 { 1040 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, },
11341 { 1040 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, },
11342 { 1040 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, },
11343 { 1040 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11344 { 1040 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11345 { 1040 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
11346 { 1040 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11347 { 1040 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11348 { 1040 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, },
11349 { 1044 /* sbfx */, ARM::t2SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
11350 { 1044 /* sbfx */, ARM::SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
11351 { 1049 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11352 { 1049 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11353 { 1049 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11354 { 1049 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11355 { 1054 /* sel */, ARM::SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11356 { 1054 /* sel */, ARM::t2SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11357 { 1058 /* setend */, ARM::tSETEND, Convert__SetEndImm1_0, AMFBS_IsThumb_IsNotMClass, { MCK_SetEndImm }, },
11358 { 1058 /* setend */, ARM::SETEND, Convert__SetEndImm1_0, AMFBS_IsARM, { MCK_SetEndImm }, },
11359 { 1065 /* setpan */, ARM::t2SETPAN, Convert__Imm0_11_0, AMFBS_IsThumb2_HasV8_HasV8_1a, { MCK_Imm0_1 }, },
11360 { 1065 /* setpan */, ARM::SETPAN, Convert__Imm0_11_0, AMFBS_IsARM_HasV8_HasV8_1a, { MCK_Imm0_1 }, },
11361 { 1072 /* sev */, ARM::tHINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
11362 { 1072 /* sev */, ARM::HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
11363 { 1072 /* sev */, ARM::t2HINT, Convert__imm_95_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
11364 { 1076 /* sevl */, ARM::tHINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode }, },
11365 { 1076 /* sevl */, ARM::HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsARM_HasV8, { MCK_CondCode }, },
11366 { 1076 /* sevl */, ARM::t2HINT, Convert__imm_95_5__CondCode2_0, AMFBS_IsThumb2_HasV8, { MCK_CondCode, MCK__DOT_w }, },
11367 { 1081 /* sg */, ARM::t2SG, Convert__CondCode2_0, AMFBS_Has8MSecExt, { MCK_CondCode }, },
11368 { 1084 /* sha1c */, ARM::SHA1C, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11369 { 1090 /* sha1h */, ARM::SHA1H, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11370 { 1096 /* sha1m */, ARM::SHA1M, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11371 { 1102 /* sha1p */, ARM::SHA1P, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11372 { 1108 /* sha1su0 */, ARM::SHA1SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11373 { 1116 /* sha1su1 */, ARM::SHA1SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11374 { 1124 /* sha256h */, ARM::SHA256H, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11375 { 1132 /* sha256h2 */, ARM::SHA256H2, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11376 { 1141 /* sha256su0 */, ARM::SHA256SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR }, },
11377 { 1151 /* sha256su1 */, ARM::SHA256SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasSHA2, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11378 { 1161 /* shadd16 */, ARM::t2SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11379 { 1161 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11380 { 1169 /* shadd8 */, ARM::t2SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11381 { 1169 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11382 { 1176 /* shasx */, ARM::t2SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11383 { 1176 /* shasx */, ARM::SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11384 { 1182 /* shsax */, ARM::t2SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11385 { 1182 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11386 { 1188 /* shsub16 */, ARM::t2SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11387 { 1188 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11388 { 1196 /* shsub8 */, ARM::t2SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11389 { 1196 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11390 { 1203 /* smc */, ARM::SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsARM_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
11391 { 1203 /* smc */, ARM::t2SMC, Convert__Imm0_151_1__CondCode2_0, AMFBS_IsThumb2_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, },
11392 { 1207 /* smlabb */, ARM::t2SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11393 { 1207 /* smlabb */, ARM::SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11394 { 1214 /* smlabt */, ARM::t2SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11395 { 1214 /* smlabt */, ARM::SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11396 { 1221 /* smlad */, ARM::t2SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11397 { 1221 /* smlad */, ARM::SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11398 { 1227 /* smladx */, ARM::t2SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11399 { 1227 /* smladx */, ARM::SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11400 { 1234 /* smlal */, ARM::t2SMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11401 { 1234 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11402 { 1234 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11403 { 1240 /* smlalbb */, ARM::t2SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11404 { 1240 /* smlalbb */, ARM::SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11405 { 1248 /* smlalbt */, ARM::t2SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11406 { 1248 /* smlalbt */, ARM::SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11407 { 1256 /* smlald */, ARM::t2SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11408 { 1256 /* smlald */, ARM::SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11409 { 1263 /* smlaldx */, ARM::t2SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11410 { 1263 /* smlaldx */, ARM::SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11411 { 1271 /* smlaltb */, ARM::t2SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11412 { 1271 /* smlaltb */, ARM::SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11413 { 1279 /* smlaltt */, ARM::t2SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11414 { 1279 /* smlaltt */, ARM::SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11415 { 1287 /* smlatb */, ARM::t2SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11416 { 1287 /* smlatb */, ARM::SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11417 { 1294 /* smlatt */, ARM::t2SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11418 { 1294 /* smlatt */, ARM::SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11419 { 1301 /* smlawb */, ARM::t2SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11420 { 1301 /* smlawb */, ARM::SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11421 { 1308 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11422 { 1308 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11423 { 1315 /* smlsd */, ARM::t2SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11424 { 1315 /* smlsd */, ARM::SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11425 { 1321 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11426 { 1321 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, },
11427 { 1328 /* smlsld */, ARM::t2SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11428 { 1328 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11429 { 1335 /* smlsldx */, ARM::t2SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11430 { 1335 /* smlsldx */, ARM::SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11431 { 1343 /* smmla */, ARM::t2SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11432 { 1343 /* smmla */, ARM::SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11433 { 1349 /* smmlar */, ARM::t2SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11434 { 1349 /* smmlar */, ARM::SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11435 { 1356 /* smmls */, ARM::t2SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11436 { 1356 /* smmls */, ARM::SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11437 { 1362 /* smmlsr */, ARM::t2SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11438 { 1362 /* smmlsr */, ARM::SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11439 { 1369 /* smmul */, ARM::t2SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11440 { 1369 /* smmul */, ARM::SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11441 { 1375 /* smmulr */, ARM::t2SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11442 { 1375 /* smmulr */, ARM::SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11443 { 1382 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11444 { 1382 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11445 { 1388 /* smuadx */, ARM::t2SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11446 { 1388 /* smuadx */, ARM::SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11447 { 1395 /* smulbb */, ARM::t2SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11448 { 1395 /* smulbb */, ARM::SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11449 { 1402 /* smulbt */, ARM::t2SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11450 { 1402 /* smulbt */, ARM::SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11451 { 1409 /* smull */, ARM::t2SMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11452 { 1409 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11453 { 1409 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11454 { 1415 /* smultb */, ARM::t2SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11455 { 1415 /* smultb */, ARM::SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11456 { 1422 /* smultt */, ARM::t2SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11457 { 1422 /* smultt */, ARM::SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11458 { 1429 /* smulwb */, ARM::t2SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11459 { 1429 /* smulwb */, ARM::SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11460 { 1436 /* smulwt */, ARM::t2SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11461 { 1436 /* smulwt */, ARM::SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11462 { 1443 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11463 { 1443 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11464 { 1449 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11465 { 1449 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11466 { 1456 /* sqrshr */, ARM::MVE_SQRSHR, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11467 { 1463 /* sqrshrl */, ARM::MVE_SQRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, },
11468 { 1471 /* sqshl */, ARM::MVE_SQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11469 { 1477 /* sqshll */, ARM::MVE_SQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11470 { 1484 /* srsda */, ARM::SRSDA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11471 { 1484 /* srsda */, ARM::SRSDA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11472 { 1484 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11473 { 1484 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11474 { 1490 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11475 { 1490 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11476 { 1490 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
11477 { 1490 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11478 { 1490 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11479 { 1490 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
11480 { 1490 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
11481 { 1490 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11482 { 1496 /* srshr */, ARM::MVE_SRSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11483 { 1502 /* srshrl */, ARM::MVE_SRSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11484 { 1509 /* srsia */, ARM::SRSIA, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11485 { 1509 /* srsia */, ARM::SRSIA, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11486 { 1509 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, },
11487 { 1509 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11488 { 1509 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11489 { 1509 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_2__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, },
11490 { 1509 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
11491 { 1509 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11492 { 1515 /* srsib */, ARM::SRSIB, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31 }, },
11493 { 1515 /* srsib */, ARM::SRSIB, Convert__Imm0_311_1, AMFBS_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, },
11494 { 1515 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11495 { 1515 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11496 { 1521 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR }, },
11497 { 1521 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc }, },
11498 { 1521 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR, MCK_ShifterImm }, },
11499 { 1521 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc, MCK_ShifterImm }, },
11500 { 1526 /* ssat16 */, ARM::t2SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm1_16, MCK_rGPR }, },
11501 { 1526 /* ssat16 */, ARM::SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_16, MCK_GPRnopc }, },
11502 { 1533 /* ssax */, ARM::t2SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11503 { 1533 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11504 { 1538 /* ssbb */, ARM::t2DSB, Convert__imm_95_0__imm_95_14__reg0, AMFBS_HasDB_IsThumb2, { }, },
11505 { 1538 /* ssbb */, ARM::DSB, Convert__imm_95_0, AMFBS_IsARM_HasDB, { }, },
11506 { 1543 /* ssub16 */, ARM::t2SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11507 { 1543 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11508 { 1550 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11509 { 1550 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11510 { 1556 /* stc */, ARM::STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11511 { 1556 /* stc */, ARM::t2STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11512 { 1556 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11513 { 1556 /* stc */, ARM::t2STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11514 { 1556 /* stc */, ARM::STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11515 { 1556 /* stc */, ARM::t2STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11516 { 1556 /* stc */, ARM::STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11517 { 1556 /* stc */, ARM::t2STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11518 { 1560 /* stc2 */, ARM::STC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11519 { 1560 /* stc2 */, ARM::t2STC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11520 { 1560 /* stc2 */, ARM::STC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11521 { 1560 /* stc2 */, ARM::STC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11522 { 1560 /* stc2 */, ARM::STC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11523 { 1560 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11524 { 1560 /* stc2 */, ARM::t2STC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11525 { 1560 /* stc2 */, ARM::t2STC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11526 { 1565 /* stc2l */, ARM::STC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11527 { 1565 /* stc2l */, ARM::t2STC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11528 { 1565 /* stc2l */, ARM::STC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11529 { 1565 /* stc2l */, ARM::STC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11530 { 1565 /* stc2l */, ARM::STC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11531 { 1565 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11532 { 1565 /* stc2l */, ARM::t2STC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11533 { 1565 /* stc2l */, ARM::t2STC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11534 { 1571 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11535 { 1571 /* stcl */, ARM::t2STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, },
11536 { 1571 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11537 { 1571 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11538 { 1571 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11539 { 1571 /* stcl */, ARM::t2STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, },
11540 { 1571 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11541 { 1571 /* stcl */, ARM::t2STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, },
11542 { 1576 /* stl */, ARM::t2STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11543 { 1576 /* stl */, ARM::STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11544 { 1580 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11545 { 1580 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11546 { 1585 /* stlex */, ARM::t2STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11547 { 1585 /* stlex */, ARM::STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11548 { 1591 /* stlexb */, ARM::t2STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11549 { 1591 /* stlexb */, ARM::STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11550 { 1598 /* stlexd */, ARM::STLEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
11551 { 1598 /* stlexd */, ARM::t2STLEXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11552 { 1605 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11553 { 1605 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_HasAcquireRelease_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11554 { 1612 /* stlh */, ARM::t2STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsThumb_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, },
11555 { 1612 /* stlh */, ARM::STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11556 { 1617 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
11557 { 1617 /* stm */, ARM::STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11558 { 1617 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11559 { 1617 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11560 { 1617 /* stm */, ARM::t2STMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
11561 { 1617 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11562 { 1617 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11563 { 1617 /* stm */, ARM::sysSTMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11564 { 1617 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11565 { 1617 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11566 { 1621 /* stmda */, ARM::STMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11567 { 1621 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11568 { 1621 /* stmda */, ARM::sysSTMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11569 { 1621 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11570 { 1627 /* stmdb */, ARM::STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11571 { 1627 /* stmdb */, ARM::t2STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11572 { 1627 /* stmdb */, ARM::t2STMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, },
11573 { 1627 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11574 { 1627 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11575 { 1627 /* stmdb */, ARM::sysSTMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11576 { 1627 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11577 { 1627 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11578 { 1633 /* stmib */, ARM::STMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, },
11579 { 1633 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11580 { 1633 /* stmib */, ARM::sysSTMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, },
11581 { 1633 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11582 { 1639 /* str */, ARM::tSTRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, },
11583 { 1639 /* str */, ARM::tSTRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11584 { 1639 /* str */, ARM::tSTRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, },
11585 { 1639 /* str */, ARM::STRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, },
11586 { 1639 /* str */, ARM::t2STRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, },
11587 { 1639 /* str */, ARM::STRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, },
11588 { 1639 /* str */, ARM::t2STRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, },
11589 { 1639 /* str */, ARM::t2STRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, },
11590 { 1639 /* str */, ARM::t2STRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, },
11591 { 1639 /* str */, ARM::t2STRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, },
11592 { 1639 /* str */, ARM::t2STR_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11593 { 1639 /* str */, ARM::t2STR_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_Imm }, },
11594 { 1639 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11595 { 1639 /* str */, ARM::STR_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11596 { 1639 /* str */, ARM::STR_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11597 { 1639 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11598 { 1639 /* str */, ARM::t2STR_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11599 { 1639 /* str */, ARM::t2STR_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11600 { 1643 /* strb */, ARM::tSTRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, },
11601 { 1643 /* strb */, ARM::tSTRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11602 { 1643 /* strb */, ARM::t2STRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
11603 { 1643 /* strb */, ARM::t2STRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
11604 { 1643 /* strb */, ARM::t2STRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
11605 { 1643 /* strb */, ARM::STRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, },
11606 { 1643 /* strb */, ARM::STRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, },
11607 { 1643 /* strb */, ARM::t2STRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
11608 { 1643 /* strb */, ARM::t2STRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
11609 { 1643 /* strb */, ARM::t2STRB_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
11610 { 1643 /* strb */, ARM::t2STRB_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11611 { 1643 /* strb */, ARM::t2STRB_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
11612 { 1643 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11613 { 1643 /* strb */, ARM::STRB_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11614 { 1643 /* strb */, ARM::STRB_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11615 { 1643 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11616 { 1643 /* strb */, ARM::t2STRB_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11617 { 1643 /* strb */, ARM::t2STRB_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11618 { 1648 /* strbt */, ARM::t2STRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11619 { 1648 /* strbt */, ARM::STRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11620 { 1648 /* strbt */, ARM::STRBT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11621 { 1648 /* strbt */, ARM::STRBT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11622 { 1654 /* strd */, ARM::t2STRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, },
11623 { 1654 /* strd */, ARM::STRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, },
11624 { 1654 /* strd */, ARM::t2STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
11625 { 1654 /* strd */, ARM::t2STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm8s41_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm8s4 }, },
11626 { 1654 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11627 { 1654 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11628 { 1659 /* strex */, ARM::t2STREX, Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm0_1020s4Offset }, },
11629 { 1659 /* strex */, ARM::STREX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11630 { 1665 /* strexb */, ARM::t2STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11631 { 1665 /* strexb */, ARM::STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11632 { 1672 /* strexd */, ARM::STREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, },
11633 { 1672 /* strexd */, ARM::t2STREXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11634 { 1679 /* strexh */, ARM::t2STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, },
11635 { 1679 /* strexh */, ARM::STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, },
11636 { 1686 /* strh */, ARM::tSTRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, },
11637 { 1686 /* strh */, ARM::tSTRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, },
11638 { 1686 /* strh */, ARM::t2STRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, },
11639 { 1686 /* strh */, ARM::t2STRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, },
11640 { 1686 /* strh */, ARM::t2STRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, },
11641 { 1686 /* strh */, ARM::STRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, },
11642 { 1686 /* strh */, ARM::t2STRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, },
11643 { 1686 /* strh */, ARM::t2STRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, },
11644 { 1686 /* strh */, ARM::t2STRH_OFFSET_imm, Convert__Reg1_2__MemNegImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNegImm8Offset }, },
11645 { 1686 /* strh */, ARM::t2STRH_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11646 { 1686 /* strh */, ARM::t2STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, },
11647 { 1686 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11648 { 1686 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, },
11649 { 1686 /* strh */, ARM::t2STRH_PRE_imm, Convert__Reg1_2__MemImm8Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11650 { 1686 /* strh */, ARM::t2STRH_POST_imm, Convert__Reg1_2__MemNoOffset1_3__Imm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, },
11651 { 1691 /* strht */, ARM::t2STRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11652 { 1691 /* strht */, ARM::STRHTi, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, },
11653 { 1691 /* strht */, ARM::STRHTr, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxReg }, },
11654 { 1697 /* strt */, ARM::t2STRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, },
11655 { 1697 /* strt */, ARM::STRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, },
11656 { 1697 /* strt */, ARM::STRT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, },
11657 { 1697 /* strt */, ARM::STRT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, },
11658 { 1702 /* sub */, ARM::tSUBspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, },
11659 { 1702 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11660 { 1702 /* sub */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, },
11661 { 1702 /* sub */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, },
11662 { 1702 /* sub */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, },
11663 { 1702 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, },
11664 { 1702 /* sub */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, AMFBS_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, },
11665 { 1702 /* sub */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, AMFBS_IsThumb_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, },
11666 { 1702 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
11667 { 1702 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
11668 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_T2SOImm }, },
11669 { 1702 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11670 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, },
11671 { 1702 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, },
11672 { 1702 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, },
11673 { 1702 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11674 { 1702 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, },
11675 { 1702 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11676 { 1702 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, },
11677 { 1702 /* sub */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
11678 { 1702 /* sub */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
11679 { 1702 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
11680 { 1702 /* sub */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, },
11681 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_T2SOImm }, },
11682 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, },
11683 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
11684 { 1702 /* sub */, ARM::t2ADDspImm, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
11685 { 1702 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
11686 { 1702 /* sub */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
11687 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
11688 { 1702 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
11689 { 1702 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11690 { 1702 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
11691 { 1702 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, },
11692 { 1702 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, },
11693 { 1702 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, },
11694 { 1702 /* sub */, ARM::t2SUBspImm, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImm }, },
11695 { 1702 /* sub */, ARM::t2ADDspImm, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRsp, MCK_GPRsp, MCK_T2SOImmNeg }, },
11696 { 1702 /* sub */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImm }, },
11697 { 1702 /* sub */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_GPRnopc, MCK_T2SOImmNeg }, },
11698 { 1702 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, },
11699 { 1702 /* sub */, ARM::t2SUBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, AMFBS_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, },
11700 { 1706 /* subs */, ARM::t2SUBS_PC_LR, Convert__Imm0_2551_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_PC, MCK_GPRlr, MCK_Imm0_255 }, },
11701 { 1711 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_4095 }, },
11702 { 1711 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_4095 }, },
11703 { 1711 /* subw */, ARM::t2SUBspImm12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095 }, },
11704 { 1711 /* subw */, ARM::t2ADDspImm12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_4095Neg }, },
11705 { 1711 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095 }, },
11706 { 1711 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_GPR, MCK_Imm0_4095Neg }, },
11707 { 1716 /* svc */, ARM::tSVC, Convert__Imm0_2551_1__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_Imm0_255 }, },
11708 { 1716 /* svc */, ARM::SVC, Convert__Imm24bit1_1__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_Imm24bit }, },
11709 { 1720 /* swp */, ARM::SWP, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
11710 { 1724 /* swpb */, ARM::SWPB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, AMFBS_IsARM_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, },
11711 { 1729 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11712 { 1729 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11713 { 1729 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11714 { 1729 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11715 { 1735 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11716 { 1735 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11717 { 1735 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11718 { 1735 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11719 { 1743 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11720 { 1743 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11721 { 1743 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11722 { 1743 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11723 { 1749 /* sxtb */, ARM::tSXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11724 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11725 { 1749 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11726 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11727 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11728 { 1749 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11729 { 1749 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11730 { 1754 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11731 { 1754 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11732 { 1754 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11733 { 1754 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11734 { 1754 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11735 { 1761 /* sxth */, ARM::tSXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11736 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11737 { 1761 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11738 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11739 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11740 { 1761 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11741 { 1761 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11742 { 1766 /* tbb */, ARM::t2TBB, Convert__MemTBB2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBB }, },
11743 { 1770 /* tbh */, ARM::t2TBH, Convert__MemTBH2_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_MemTBH }, },
11744 { 1774 /* teq */, ARM::t2TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11745 { 1774 /* teq */, ARM::t2TEQrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11746 { 1774 /* teq */, ARM::t2TEQri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11747 { 1774 /* teq */, ARM::TEQrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11748 { 1774 /* teq */, ARM::TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11749 { 1774 /* teq */, ARM::TEQri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11750 { 1774 /* teq */, ARM::TEQrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11751 { 1774 /* teq */, ARM::t2TEQrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11752 { 1774 /* teq */, ARM::t2TEQrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11753 { 1774 /* teq */, ARM::t2TEQri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11754 { 1778 /* trap */, ARM::tTRAP, Convert_NoOperands, AMFBS_IsThumb, { }, },
11755 { 1778 /* trap */, ARM::TRAP, Convert_NoOperands, AMFBS_IsARM, { }, },
11756 { 1783 /* tsb */, ARM::TSB, Convert__TraceSyncBarrierOpt1_0, AMFBS_IsARM_HasV8_4a, { MCK_TraceSyncBarrierOpt }, },
11757 { 1783 /* tsb */, ARM::t2TSB, Convert__TraceSyncBarrierOpt1_1__CondCode2_0, AMFBS_IsThumb_HasV8_4a, { MCK_CondCode, MCK_TraceSyncBarrierOpt }, },
11758 { 1787 /* tst */, ARM::tTST, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11759 { 1787 /* tst */, ARM::t2TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11760 { 1787 /* tst */, ARM::t2TSTrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, },
11761 { 1787 /* tst */, ARM::t2TSTri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, },
11762 { 1787 /* tst */, ARM::TSTrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, },
11763 { 1787 /* tst */, ARM::TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11764 { 1787 /* tst */, ARM::TSTri, Convert__Reg1_1__ModImm1_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, },
11765 { 1787 /* tst */, ARM::TSTrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, },
11766 { 1787 /* tst */, ARM::t2TSTrr, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11767 { 1787 /* tst */, ARM::t2TSTrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, },
11768 { 1787 /* tst */, ARM::t2TSTri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, },
11769 { 1791 /* tt */, ARM::t2TT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
11770 { 1794 /* tta */, ARM::t2TTA, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
11771 { 1798 /* ttat */, ARM::t2TTAT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
11772 { 1803 /* ttt */, ARM::t2TTT, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, },
11773 { 1807 /* uadd16 */, ARM::t2UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11774 { 1807 /* uadd16 */, ARM::UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11775 { 1814 /* uadd8 */, ARM::t2UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11776 { 1814 /* uadd8 */, ARM::UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11777 { 1820 /* uasx */, ARM::t2UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11778 { 1820 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11779 { 1825 /* ubfx */, ARM::t2UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, },
11780 { 1825 /* ubfx */, ARM::UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, AMFBS_IsARM_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, },
11781 { 1830 /* udf */, ARM::tUDF, Convert__Imm0_2551_0, AMFBS_IsThumb, { MCK_Imm0_255 }, },
11782 { 1830 /* udf */, ARM::UDF, Convert__Imm0_655351_0, AMFBS_IsARM, { MCK_Imm0_65535 }, },
11783 { 1830 /* udf */, ARM::t2UDF, Convert__Imm0_655351_1, AMFBS_IsThumb2, { MCK__DOT_w, MCK_Imm0_65535 }, },
11784 { 1834 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11785 { 1834 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, },
11786 { 1834 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11787 { 1834 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11788 { 1839 /* uhadd16 */, ARM::t2UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11789 { 1839 /* uhadd16 */, ARM::UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11790 { 1847 /* uhadd8 */, ARM::t2UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11791 { 1847 /* uhadd8 */, ARM::UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11792 { 1854 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11793 { 1854 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11794 { 1860 /* uhsax */, ARM::t2UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11795 { 1860 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11796 { 1866 /* uhsub16 */, ARM::t2UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11797 { 1866 /* uhsub16 */, ARM::UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11798 { 1874 /* uhsub8 */, ARM::t2UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11799 { 1874 /* uhsub8 */, ARM::UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11800 { 1881 /* umaal */, ARM::t2UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11801 { 1881 /* umaal */, ARM::UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11802 { 1887 /* umlal */, ARM::t2UMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11803 { 1887 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11804 { 1887 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11805 { 1893 /* umull */, ARM::t2UMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11806 { 1893 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11807 { 1893 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11808 { 1899 /* uqadd16 */, ARM::t2UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11809 { 1899 /* uqadd16 */, ARM::UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11810 { 1907 /* uqadd8 */, ARM::t2UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11811 { 1907 /* uqadd8 */, ARM::UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11812 { 1914 /* uqasx */, ARM::t2UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11813 { 1914 /* uqasx */, ARM::UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11814 { 1920 /* uqrshl */, ARM::MVE_UQRSHL, Convert__Reg1_1__Tie0_2_2__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11815 { 1927 /* uqrshll */, ARM::MVE_UQRSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_4__MveSaturate1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MveSaturate, MCK_rGPR }, },
11816 { 1935 /* uqsax */, ARM::t2UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11817 { 1935 /* uqsax */, ARM::UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11818 { 1941 /* uqshl */, ARM::MVE_UQSHL, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11819 { 1947 /* uqshll */, ARM::MVE_UQSHLL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11820 { 1954 /* uqsub16 */, ARM::t2UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11821 { 1954 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11822 { 1962 /* uqsub8 */, ARM::t2UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11823 { 1962 /* uqsub8 */, ARM::UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11824 { 1969 /* urshr */, ARM::MVE_URSHR, Convert__Reg1_1__Tie0_2_2__MVELongShift1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_MVELongShift }, },
11825 { 1975 /* urshrl */, ARM::MVE_URSHRL, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_tGPREven, MCK_tGPROdd, MCK_MVELongShift }, },
11826 { 1982 /* usad8 */, ARM::t2USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11827 { 1982 /* usad8 */, ARM::USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
11828 { 1988 /* usada8 */, ARM::t2USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11829 { 1988 /* usada8 */, ARM::USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, },
11830 { 1995 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR }, },
11831 { 1995 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc }, },
11832 { 1995 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR, MCK_ShifterImm }, },
11833 { 1995 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc, MCK_ShifterImm }, },
11834 { 2000 /* usat16 */, ARM::t2USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm0_15, MCK_rGPR }, },
11835 { 2000 /* usat16 */, ARM::USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_15, MCK_GPRnopc }, },
11836 { 2007 /* usax */, ARM::t2USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11837 { 2007 /* usax */, ARM::USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11838 { 2012 /* usub16 */, ARM::t2USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11839 { 2012 /* usub16 */, ARM::USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11840 { 2019 /* usub8 */, ARM::t2USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11841 { 2019 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, },
11842 { 2025 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11843 { 2025 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11844 { 2025 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11845 { 2025 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11846 { 2031 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11847 { 2031 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11848 { 2031 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11849 { 2031 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11850 { 2039 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, },
11851 { 2039 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, },
11852 { 2039 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11853 { 2039 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11854 { 2045 /* uxtb */, ARM::tUXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11855 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11856 { 2045 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11857 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11858 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11859 { 2045 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11860 { 2045 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11861 { 2050 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11862 { 2050 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11863 { 2050 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11864 { 2050 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11865 { 2050 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11866 { 2057 /* uxth */, ARM::tUXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_IsThumb_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, },
11867 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, },
11868 { 2057 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, },
11869 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, },
11870 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11871 { 2057 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11872 { 2057 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11873 { 2062 /* vaba */, ARM::VABAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11874 { 2062 /* vaba */, ARM::VABAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11875 { 2062 /* vaba */, ARM::VABAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11876 { 2062 /* vaba */, ARM::VABAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11877 { 2062 /* vaba */, ARM::VABAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11878 { 2062 /* vaba */, ARM::VABAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11879 { 2062 /* vaba */, ARM::VABAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11880 { 2062 /* vaba */, ARM::VABAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11881 { 2062 /* vaba */, ARM::VABAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11882 { 2062 /* vaba */, ARM::VABAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11883 { 2062 /* vaba */, ARM::VABAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11884 { 2062 /* vaba */, ARM::VABAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11885 { 2067 /* vabal */, ARM::VABALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11886 { 2067 /* vabal */, ARM::VABALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11887 { 2067 /* vabal */, ARM::VABALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11888 { 2067 /* vabal */, ARM::VABALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11889 { 2067 /* vabal */, ARM::VABALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11890 { 2067 /* vabal */, ARM::VABALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11891 { 2073 /* vabav */, ARM::MVE_VABAVs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11892 { 2073 /* vabav */, ARM::MVE_VABAVs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11893 { 2073 /* vabav */, ARM::MVE_VABAVs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11894 { 2073 /* vabav */, ARM::MVE_VABAVu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11895 { 2073 /* vabav */, ARM::MVE_VABAVu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11896 { 2073 /* vabav */, ARM::MVE_VABAVu8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11897 { 2079 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
11898 { 2079 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
11899 { 2079 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11900 { 2079 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11901 { 2079 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
11902 { 2079 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
11903 { 2079 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
11904 { 2079 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
11905 { 2079 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
11906 { 2079 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
11907 { 2079 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
11908 { 2079 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
11909 { 2079 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11910 { 2079 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11911 { 2079 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11912 { 2079 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11913 { 2079 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11914 { 2079 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11915 { 2079 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11916 { 2079 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11917 { 2079 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11918 { 2079 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11919 { 2079 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11920 { 2079 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11921 { 2079 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11922 { 2079 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11923 { 2079 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
11924 { 2079 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
11925 { 2079 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11926 { 2079 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11927 { 2079 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11928 { 2079 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11929 { 2079 /* vabd */, ARM::MVE_VABDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11930 { 2079 /* vabd */, ARM::MVE_VABDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11931 { 2079 /* vabd */, ARM::MVE_VABDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11932 { 2079 /* vabd */, ARM::MVE_VABDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11933 { 2079 /* vabd */, ARM::MVE_VABDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11934 { 2079 /* vabd */, ARM::MVE_VABDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11935 { 2079 /* vabd */, ARM::MVE_VABDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11936 { 2079 /* vabd */, ARM::MVE_VABDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11937 { 2084 /* vabdl */, ARM::VABDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11938 { 2084 /* vabdl */, ARM::VABDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11939 { 2084 /* vabdl */, ARM::VABDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11940 { 2084 /* vabdl */, ARM::VABDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
11941 { 2084 /* vabdl */, ARM::VABDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11942 { 2084 /* vabdl */, ARM::VABDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
11943 { 2090 /* vabs */, ARM::VABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
11944 { 2090 /* vabs */, ARM::VABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
11945 { 2090 /* vabs */, ARM::VABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11946 { 2090 /* vabs */, ARM::VABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11947 { 2090 /* vabs */, ARM::VABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
11948 { 2090 /* vabs */, ARM::VABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
11949 { 2090 /* vabs */, ARM::VABSfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11950 { 2090 /* vabs */, ARM::VABSfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11951 { 2090 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11952 { 2090 /* vabs */, ARM::VABSD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11953 { 2090 /* vabs */, ARM::VABShq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11954 { 2090 /* vabs */, ARM::VABShd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11955 { 2090 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11956 { 2090 /* vabs */, ARM::MVE_VABSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
11957 { 2090 /* vabs */, ARM::MVE_VABSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
11958 { 2090 /* vabs */, ARM::MVE_VABSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
11959 { 2090 /* vabs */, ARM::MVE_VABSf32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
11960 { 2090 /* vabs */, ARM::MVE_VABSf16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
11961 { 2095 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11962 { 2095 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11963 { 2095 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11964 { 2095 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11965 { 2095 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11966 { 2095 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11967 { 2095 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11968 { 2095 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11969 { 2101 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11970 { 2101 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11971 { 2101 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11972 { 2101 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11973 { 2101 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11974 { 2101 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11975 { 2101 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11976 { 2101 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11977 { 2107 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11978 { 2107 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11979 { 2107 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11980 { 2107 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11981 { 2107 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11982 { 2107 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11983 { 2107 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11984 { 2107 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11985 { 2113 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11986 { 2113 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11987 { 2113 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
11988 { 2113 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
11989 { 2113 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11990 { 2113 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11991 { 2113 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11992 { 2113 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11993 { 2119 /* vadc */, ARM::MVE_VADC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11994 { 2124 /* vadci */, ARM::MVE_VADCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11995 { 2130 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
11996 { 2130 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
11997 { 2130 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11998 { 2130 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
11999 { 2130 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
12000 { 2130 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
12001 { 2130 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
12002 { 2130 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
12003 { 2130 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, },
12004 { 2130 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, },
12005 { 2130 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
12006 { 2130 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
12007 { 2130 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12008 { 2130 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12009 { 2130 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12010 { 2130 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12011 { 2130 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12012 { 2130 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12013 { 2130 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12014 { 2130 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12015 { 2130 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12016 { 2130 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12017 { 2130 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12018 { 2130 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12019 { 2130 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12020 { 2130 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12021 { 2130 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12022 { 2130 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12023 { 2130 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12024 { 2130 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12025 { 2130 /* vadd */, ARM::MVE_VADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12026 { 2130 /* vadd */, ARM::MVE_VADD_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12027 { 2130 /* vadd */, ARM::MVE_VADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12028 { 2130 /* vadd */, ARM::MVE_VADD_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12029 { 2130 /* vadd */, ARM::MVE_VADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12030 { 2130 /* vadd */, ARM::MVE_VADD_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12031 { 2130 /* vadd */, ARM::MVE_VADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12032 { 2130 /* vadd */, ARM::MVE_VADD_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12033 { 2130 /* vadd */, ARM::MVE_VADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12034 { 2130 /* vadd */, ARM::MVE_VADD_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12035 { 2135 /* vaddhn */, ARM::VADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
12036 { 2135 /* vaddhn */, ARM::VADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
12037 { 2135 /* vaddhn */, ARM::VADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
12038 { 2142 /* vaddl */, ARM::VADDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12039 { 2142 /* vaddl */, ARM::VADDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
12040 { 2142 /* vaddl */, ARM::VADDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
12041 { 2142 /* vaddl */, ARM::VADDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12042 { 2142 /* vaddl */, ARM::VADDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
12043 { 2142 /* vaddl */, ARM::VADDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
12044 { 2148 /* vaddlv */, ARM::MVE_VADDLVs32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
12045 { 2148 /* vaddlv */, ARM::MVE_VADDLVu32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
12046 { 2155 /* vaddlva */, ARM::MVE_VADDLVs32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
12047 { 2155 /* vaddlva */, ARM::MVE_VADDLVu32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
12048 { 2163 /* vaddv */, ARM::MVE_VADDVs16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, },
12049 { 2163 /* vaddv */, ARM::MVE_VADDVs32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, },
12050 { 2163 /* vaddv */, ARM::MVE_VADDVs8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, },
12051 { 2163 /* vaddv */, ARM::MVE_VADDVu16no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, },
12052 { 2163 /* vaddv */, ARM::MVE_VADDVu32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, },
12053 { 2163 /* vaddv */, ARM::MVE_VADDVu8no_acc, Convert__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, },
12054 { 2169 /* vaddva */, ARM::MVE_VADDVs16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR }, },
12055 { 2169 /* vaddva */, ARM::MVE_VADDVs32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, },
12056 { 2169 /* vaddva */, ARM::MVE_VADDVs8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR }, },
12057 { 2169 /* vaddva */, ARM::MVE_VADDVu16acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR }, },
12058 { 2169 /* vaddva */, ARM::MVE_VADDVu32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR }, },
12059 { 2169 /* vaddva */, ARM::MVE_VADDVu8acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR }, },
12060 { 2176 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
12061 { 2176 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
12062 { 2176 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
12063 { 2176 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
12064 { 2176 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
12065 { 2176 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
12066 { 2176 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, },
12067 { 2176 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
12068 { 2176 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, },
12069 { 2176 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, },
12070 { 2176 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, },
12071 { 2176 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, },
12072 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
12073 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
12074 { 2182 /* vand */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splatNot }, },
12075 { 2182 /* vand */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splatNot }, },
12076 { 2182 /* vand */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splatNot }, },
12077 { 2182 /* vand */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splatNot }, },
12078 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
12079 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
12080 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
12081 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
12082 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
12083 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
12084 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
12085 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
12086 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12087 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12088 { 2182 /* vand */, ARM::MVE_VBICimmi16, Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splatNot }, },
12089 { 2182 /* vand */, ARM::MVE_VBICimmi32, Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splatNot }, },
12090 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12091 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12092 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12093 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12094 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12095 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12096 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12097 { 2182 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12098 { 2182 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12099 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12100 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12101 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12102 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12103 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12104 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12105 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12106 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12107 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12108 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12109 { 2182 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12110 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
12111 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
12112 { 2187 /* vbic */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
12113 { 2187 /* vbic */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
12114 { 2187 /* vbic */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, },
12115 { 2187 /* vbic */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, },
12116 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12117 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12118 { 2187 /* vbic */, ARM::MVE_VBICimmi16, Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
12119 { 2187 /* vbic */, ARM::MVE_VBICimmi32, Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splat }, },
12120 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12121 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12122 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12123 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12124 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12125 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12126 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12127 { 2187 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12128 { 2187 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12129 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12130 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12131 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12132 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12133 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12134 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12135 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12136 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12137 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12138 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12139 { 2187 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12140 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12141 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12142 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12143 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12144 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12145 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12146 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12147 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12148 { 2192 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12149 { 2192 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12150 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12151 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12152 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12153 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12154 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12155 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12156 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12157 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12158 { 2197 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12159 { 2197 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12160 { 2202 /* vbrsr */, ARM::MVE_VBRSR16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12161 { 2202 /* vbrsr */, ARM::MVE_VBRSR32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12162 { 2202 /* vbrsr */, ARM::MVE_VBRSR8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12163 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12164 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12165 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12166 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12167 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12168 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12169 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12170 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12171 { 2208 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12172 { 2208 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12173 { 2213 /* vcadd */, ARM::VCADDv4f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, },
12174 { 2213 /* vcadd */, ARM::VCADDv2f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, },
12175 { 2213 /* vcadd */, ARM::VCADDv8f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, },
12176 { 2213 /* vcadd */, ARM::VCADDv4f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, },
12177 { 2213 /* vcadd */, ARM::MVE_VCADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12178 { 2213 /* vcadd */, ARM::MVE_VCADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12179 { 2213 /* vcadd */, ARM::MVE_VCADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12180 { 2213 /* vcadd */, ARM::MVE_VCADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12181 { 2213 /* vcadd */, ARM::MVE_VCADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12182 { 2219 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12183 { 2219 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12184 { 2219 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12185 { 2219 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12186 { 2219 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK__HASH_0 }, },
12187 { 2219 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
12188 { 2219 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK__HASH_0 }, },
12189 { 2219 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
12190 { 2219 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK__HASH_0 }, },
12191 { 2219 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
12192 { 2219 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK__HASH_0 }, },
12193 { 2219 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
12194 { 2219 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK__HASH_0 }, },
12195 { 2219 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
12196 { 2219 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK__HASH_0 }, },
12197 { 2219 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
12198 { 2219 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12199 { 2219 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12200 { 2219 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12201 { 2219 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12202 { 2219 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12203 { 2219 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12204 { 2219 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12205 { 2219 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12206 { 2219 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12207 { 2219 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12208 { 2219 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12209 { 2219 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12210 { 2219 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12211 { 2219 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12212 { 2219 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12213 { 2219 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12214 { 2219 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12215 { 2219 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12216 { 2219 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12217 { 2219 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12218 { 2219 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12219 { 2219 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12220 { 2219 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12221 { 2219 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12222 { 2224 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12223 { 2224 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12224 { 2224 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12225 { 2224 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12226 { 2224 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12227 { 2224 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12228 { 2224 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12229 { 2224 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12230 { 2224 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12231 { 2224 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12232 { 2224 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12233 { 2224 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12234 { 2224 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12235 { 2224 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12236 { 2224 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12237 { 2224 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12238 { 2224 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12239 { 2224 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12240 { 2224 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12241 { 2224 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12242 { 2224 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12243 { 2224 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12244 { 2224 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12245 { 2224 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12246 { 2224 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12247 { 2224 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12248 { 2224 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12249 { 2224 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12250 { 2224 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12251 { 2224 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12252 { 2224 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12253 { 2224 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12254 { 2224 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12255 { 2224 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12256 { 2224 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12257 { 2224 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12258 { 2224 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12259 { 2224 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12260 { 2224 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12261 { 2224 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12262 { 2224 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12263 { 2224 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12264 { 2224 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12265 { 2224 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12266 { 2224 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12267 { 2224 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12268 { 2224 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12269 { 2224 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12270 { 2224 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12271 { 2224 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12272 { 2224 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12273 { 2224 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12274 { 2229 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12275 { 2229 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12276 { 2229 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12277 { 2229 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12278 { 2229 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12279 { 2229 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12280 { 2229 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12281 { 2229 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12282 { 2229 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12283 { 2229 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12284 { 2229 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12285 { 2229 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12286 { 2229 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12287 { 2229 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12288 { 2229 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12289 { 2229 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12290 { 2229 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12291 { 2229 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12292 { 2229 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12293 { 2229 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12294 { 2229 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12295 { 2229 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12296 { 2229 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12297 { 2229 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12298 { 2229 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12299 { 2229 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12300 { 2229 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12301 { 2229 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12302 { 2229 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12303 { 2229 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12304 { 2229 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12305 { 2229 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12306 { 2229 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12307 { 2229 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12308 { 2229 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12309 { 2229 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12310 { 2229 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12311 { 2229 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12312 { 2229 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12313 { 2229 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12314 { 2229 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12315 { 2229 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12316 { 2229 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12317 { 2229 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12318 { 2229 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12319 { 2229 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12320 { 2229 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12321 { 2229 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12322 { 2229 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12323 { 2229 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12324 { 2229 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12325 { 2229 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12326 { 2234 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12327 { 2234 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12328 { 2234 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12329 { 2234 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12330 { 2234 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12331 { 2234 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12332 { 2234 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12333 { 2234 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12334 { 2234 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12335 { 2234 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12336 { 2234 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12337 { 2234 /* vcle */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12338 { 2234 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12339 { 2234 /* vcle */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12340 { 2234 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12341 { 2234 /* vcle */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12342 { 2234 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12343 { 2234 /* vcle */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12344 { 2234 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12345 { 2234 /* vcle */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12346 { 2234 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12347 { 2234 /* vcle */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12348 { 2234 /* vcle */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12349 { 2234 /* vcle */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12350 { 2234 /* vcle */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12351 { 2234 /* vcle */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12352 { 2234 /* vcle */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12353 { 2234 /* vcle */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12354 { 2234 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12355 { 2234 /* vcle */, ARM::VCGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12356 { 2234 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12357 { 2234 /* vcle */, ARM::VCGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12358 { 2234 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12359 { 2234 /* vcle */, ARM::VCGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12360 { 2234 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12361 { 2234 /* vcle */, ARM::VCGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12362 { 2239 /* vcls */, ARM::VCLSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12363 { 2239 /* vcls */, ARM::VCLSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12364 { 2239 /* vcls */, ARM::VCLSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12365 { 2239 /* vcls */, ARM::VCLSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12366 { 2239 /* vcls */, ARM::VCLSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12367 { 2239 /* vcls */, ARM::VCLSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12368 { 2239 /* vcls */, ARM::MVE_VCLSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
12369 { 2239 /* vcls */, ARM::MVE_VCLSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12370 { 2239 /* vcls */, ARM::MVE_VCLSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
12371 { 2244 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__HASH_0 }, },
12372 { 2244 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__HASH_0 }, },
12373 { 2244 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12374 { 2244 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12375 { 2244 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__HASH_0 }, },
12376 { 2244 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__HASH_0 }, },
12377 { 2244 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__HASH_0 }, },
12378 { 2244 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__HASH_0 }, },
12379 { 2244 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__HASH_0 }, },
12380 { 2244 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__HASH_0 }, },
12381 { 2244 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12382 { 2244 /* vclt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12383 { 2244 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12384 { 2244 /* vclt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12385 { 2244 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12386 { 2244 /* vclt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12387 { 2244 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12388 { 2244 /* vclt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12389 { 2244 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12390 { 2244 /* vclt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12391 { 2244 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12392 { 2244 /* vclt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12393 { 2244 /* vclt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12394 { 2244 /* vclt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12395 { 2244 /* vclt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12396 { 2244 /* vclt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12397 { 2244 /* vclt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12398 { 2244 /* vclt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12399 { 2244 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12400 { 2244 /* vclt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12401 { 2244 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12402 { 2244 /* vclt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12403 { 2244 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12404 { 2244 /* vclt */, ARM::VCGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12405 { 2244 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12406 { 2244 /* vclt */, ARM::VCGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12407 { 2249 /* vclz */, ARM::VCLZv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
12408 { 2249 /* vclz */, ARM::VCLZv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
12409 { 2249 /* vclz */, ARM::VCLZv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
12410 { 2249 /* vclz */, ARM::VCLZv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
12411 { 2249 /* vclz */, ARM::VCLZv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
12412 { 2249 /* vclz */, ARM::VCLZv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
12413 { 2249 /* vclz */, ARM::MVE_VCLZs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
12414 { 2249 /* vclz */, ARM::MVE_VCLZs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
12415 { 2249 /* vclz */, ARM::MVE_VCLZs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR }, },
12416 { 2254 /* vcmla */, ARM::VCMLAv4f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, },
12417 { 2254 /* vcmla */, ARM::VCMLAv2f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, },
12418 { 2254 /* vcmla */, ARM::VCMLAv8f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, },
12419 { 2254 /* vcmla */, ARM::VCMLAv4f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, },
12420 { 2254 /* vcmla */, ARM::VCMLAv4f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, },
12421 { 2254 /* vcmla */, ARM::VCMLAv2f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, },
12422 { 2254 /* vcmla */, ARM::VCMLAv8f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, },
12423 { 2254 /* vcmla */, ARM::VCMLAv4f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, AMFBS_HasNEON_HasV8_3a_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, },
12424 { 2254 /* vcmla */, ARM::MVE_VCMLAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12425 { 2254 /* vcmla */, ARM::MVE_VCMLAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12426 { 2260 /* vcmp */, ARM::VCMPZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, },
12427 { 2260 /* vcmp */, ARM::VCMPS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12428 { 2260 /* vcmp */, ARM::VCMPZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, },
12429 { 2260 /* vcmp */, ARM::VCMPD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12430 { 2260 /* vcmp */, ARM::VCMPZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, },
12431 { 2260 /* vcmp */, ARM::VCMPH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12432 { 2260 /* vcmp */, ARM::MVE_VCMPs16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12433 { 2260 /* vcmp */, ARM::MVE_VCMPs16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12434 { 2260 /* vcmp */, ARM::MVE_VCMPs32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12435 { 2260 /* vcmp */, ARM::MVE_VCMPs32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12436 { 2260 /* vcmp */, ARM::MVE_VCMPs8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12437 { 2260 /* vcmp */, ARM::MVE_VCMPs8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12438 { 2260 /* vcmp */, ARM::MVE_VCMPu16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
12439 { 2260 /* vcmp */, ARM::MVE_VCMPu16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
12440 { 2260 /* vcmp */, ARM::MVE_VCMPu32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
12441 { 2260 /* vcmp */, ARM::MVE_VCMPu32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
12442 { 2260 /* vcmp */, ARM::MVE_VCMPu8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
12443 { 2260 /* vcmp */, ARM::MVE_VCMPu8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
12444 { 2260 /* vcmp */, ARM::MVE_VCMPf32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
12445 { 2260 /* vcmp */, ARM::MVE_VCMPf32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
12446 { 2260 /* vcmp */, ARM::MVE_VCMPi16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
12447 { 2260 /* vcmp */, ARM::MVE_VCMPi16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
12448 { 2260 /* vcmp */, ARM::MVE_VCMPi32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
12449 { 2260 /* vcmp */, ARM::MVE_VCMPi32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
12450 { 2260 /* vcmp */, ARM::MVE_VCMPi8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
12451 { 2260 /* vcmp */, ARM::MVE_VCMPi8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
12452 { 2260 /* vcmp */, ARM::MVE_VCMPf16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
12453 { 2260 /* vcmp */, ARM::MVE_VCMPf16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
12454 { 2265 /* vcmpe */, ARM::VCMPEZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, },
12455 { 2265 /* vcmpe */, ARM::VCMPES, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12456 { 2265 /* vcmpe */, ARM::VCMPEZD, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__HASH_0 }, },
12457 { 2265 /* vcmpe */, ARM::VCMPED, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12458 { 2265 /* vcmpe */, ARM::VCMPEZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, },
12459 { 2265 /* vcmpe */, ARM::VCMPEH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12460 { 2271 /* vcmul */, ARM::MVE_VCMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12461 { 2271 /* vcmul */, ARM::MVE_VCMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12462 { 2277 /* vcnt */, ARM::VCNTq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
12463 { 2277 /* vcnt */, ARM::VCNTd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
12464 { 2282 /* vctp */, ARM::MVE_VCTP16, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_rGPR }, },
12465 { 2282 /* vctp */, ARM::MVE_VCTP32, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_rGPR }, },
12466 { 2282 /* vctp */, ARM::MVE_VCTP64, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_rGPR }, },
12467 { 2282 /* vctp */, ARM::MVE_VCTP8, Convert__imm_95_0__Reg1_2__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_rGPR }, },
12468 { 2287 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12469 { 2287 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12470 { 2287 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12471 { 2287 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12472 { 2287 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12473 { 2287 /* vcvt */, ARM::VTOSIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12474 { 2287 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12475 { 2287 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12476 { 2287 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12477 { 2287 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12478 { 2287 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12479 { 2287 /* vcvt */, ARM::VTOUIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12480 { 2287 /* vcvt */, ARM::VTOUIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12481 { 2287 /* vcvt */, ARM::VTOUIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12482 { 2287 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12483 { 2287 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12484 { 2287 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12485 { 2287 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12486 { 2287 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12487 { 2287 /* vcvt */, ARM::VUITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12488 { 2287 /* vcvt */, ARM::VCVTSD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12489 { 2287 /* vcvt */, ARM::VCVTh2f, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_QPR, MCK_DPR }, },
12490 { 2287 /* vcvt */, ARM::VSITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_HPR }, },
12491 { 2287 /* vcvt */, ARM::VUITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_HPR }, },
12492 { 2287 /* vcvt */, ARM::VCVTDS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f32, MCK_DPR, MCK_HPR }, },
12493 { 2287 /* vcvt */, ARM::BF16_VCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasBF16_HasNEON, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, },
12494 { 2287 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12495 { 2287 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12496 { 2287 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12497 { 2287 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12498 { 2287 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12499 { 2287 /* vcvt */, ARM::VUITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12500 { 2287 /* vcvt */, ARM::VCVTf2h, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, },
12501 { 2287 /* vcvt */, ARM::MVE_VCVTs16f16z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12502 { 2287 /* vcvt */, ARM::MVE_VCVTs32f32z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12503 { 2287 /* vcvt */, ARM::MVE_VCVTu16f16z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12504 { 2287 /* vcvt */, ARM::MVE_VCVTu32f32z, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12505 { 2287 /* vcvt */, ARM::MVE_VCVTf32s32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12506 { 2287 /* vcvt */, ARM::MVE_VCVTf32u32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
12507 { 2287 /* vcvt */, ARM::MVE_VCVTf16s16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
12508 { 2287 /* vcvt */, ARM::MVE_VCVTf16u16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
12509 { 2287 /* vcvt */, ARM::VTOSHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12510 { 2287 /* vcvt */, ARM::VTOSHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12511 { 2287 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12512 { 2287 /* vcvt */, ARM::VCVTh2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12513 { 2287 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12514 { 2287 /* vcvt */, ARM::VCVTh2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12515 { 2287 /* vcvt */, ARM::VTOSHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12516 { 2287 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12517 { 2287 /* vcvt */, ARM::VCVTf2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12518 { 2287 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12519 { 2287 /* vcvt */, ARM::VCVTf2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12520 { 2287 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12521 { 2287 /* vcvt */, ARM::VTOSLD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12522 { 2287 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12523 { 2287 /* vcvt */, ARM::VTOUHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12524 { 2287 /* vcvt */, ARM::VTOUHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12525 { 2287 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12526 { 2287 /* vcvt */, ARM::VCVTh2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12527 { 2287 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12528 { 2287 /* vcvt */, ARM::VCVTh2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12529 { 2287 /* vcvt */, ARM::VTOUHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12530 { 2287 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12531 { 2287 /* vcvt */, ARM::VCVTf2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12532 { 2287 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12533 { 2287 /* vcvt */, ARM::VCVTf2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12534 { 2287 /* vcvt */, ARM::VTOULS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12535 { 2287 /* vcvt */, ARM::VTOULD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12536 { 2287 /* vcvt */, ARM::VTOULH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12537 { 2287 /* vcvt */, ARM::VSHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12538 { 2287 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12539 { 2287 /* vcvt */, ARM::VCVTxs2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12540 { 2287 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12541 { 2287 /* vcvt */, ARM::VCVTxs2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12542 { 2287 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12543 { 2287 /* vcvt */, ARM::VUHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12544 { 2287 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12545 { 2287 /* vcvt */, ARM::VCVTxu2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12546 { 2287 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12547 { 2287 /* vcvt */, ARM::VCVTxu2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12548 { 2287 /* vcvt */, ARM::VULTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12549 { 2287 /* vcvt */, ARM::VSHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12550 { 2287 /* vcvt */, ARM::VSLTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12551 { 2287 /* vcvt */, ARM::VUHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_FBits16 }, },
12552 { 2287 /* vcvt */, ARM::VULTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12553 { 2287 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12554 { 2287 /* vcvt */, ARM::VCVTxs2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12555 { 2287 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12556 { 2287 /* vcvt */, ARM::VCVTxs2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12557 { 2287 /* vcvt */, ARM::VSHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12558 { 2287 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12559 { 2287 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12560 { 2287 /* vcvt */, ARM::VCVTxu2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, },
12561 { 2287 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12562 { 2287 /* vcvt */, ARM::VCVTxu2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, },
12563 { 2287 /* vcvt */, ARM::VUHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12564 { 2287 /* vcvt */, ARM::VULTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12565 { 2287 /* vcvt */, ARM::MVE_VCVTs16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12566 { 2287 /* vcvt */, ARM::MVE_VCVTs32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12567 { 2287 /* vcvt */, ARM::MVE_VCVTu16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12568 { 2287 /* vcvt */, ARM::MVE_VCVTu32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12569 { 2287 /* vcvt */, ARM::MVE_VCVTf32s32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12570 { 2287 /* vcvt */, ARM::MVE_VCVTf32u32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12571 { 2287 /* vcvt */, ARM::MVE_VCVTf16s16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12572 { 2287 /* vcvt */, ARM::MVE_VCVTf16u16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12573 { 2292 /* vcvta */, ARM::VCVTANSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12574 { 2292 /* vcvta */, ARM::VCVTANSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12575 { 2292 /* vcvta */, ARM::VCVTANSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12576 { 2292 /* vcvta */, ARM::VCVTANSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12577 { 2292 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12578 { 2292 /* vcvta */, ARM::VCVTASD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12579 { 2292 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12580 { 2292 /* vcvta */, ARM::VCVTANUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12581 { 2292 /* vcvta */, ARM::VCVTANUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12582 { 2292 /* vcvta */, ARM::VCVTANUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12583 { 2292 /* vcvta */, ARM::VCVTANUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12584 { 2292 /* vcvta */, ARM::VCVTAUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12585 { 2292 /* vcvta */, ARM::VCVTAUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12586 { 2292 /* vcvta */, ARM::VCVTAUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12587 { 2292 /* vcvta */, ARM::MVE_VCVTs16f16a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12588 { 2292 /* vcvta */, ARM::MVE_VCVTs32f32a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12589 { 2292 /* vcvta */, ARM::MVE_VCVTu16f16a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12590 { 2292 /* vcvta */, ARM::MVE_VCVTu32f32a, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12591 { 2298 /* vcvtb */, ARM::VCVTBHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12592 { 2298 /* vcvtb */, ARM::VCVTBHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
12593 { 2298 /* vcvtb */, ARM::BF16_VCVTB, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasBF16, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12594 { 2298 /* vcvtb */, ARM::VCVTBSH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12595 { 2298 /* vcvtb */, ARM::VCVTBDH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12596 { 2298 /* vcvtb */, ARM::MVE_VCVTf16f32bh, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12597 { 2298 /* vcvtb */, ARM::MVE_VCVTf32f16bh, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12598 { 2304 /* vcvtm */, ARM::VCVTMNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12599 { 2304 /* vcvtm */, ARM::VCVTMNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12600 { 2304 /* vcvtm */, ARM::VCVTMNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12601 { 2304 /* vcvtm */, ARM::VCVTMNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12602 { 2304 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12603 { 2304 /* vcvtm */, ARM::VCVTMSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12604 { 2304 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12605 { 2304 /* vcvtm */, ARM::VCVTMNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12606 { 2304 /* vcvtm */, ARM::VCVTMNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12607 { 2304 /* vcvtm */, ARM::VCVTMNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12608 { 2304 /* vcvtm */, ARM::VCVTMNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12609 { 2304 /* vcvtm */, ARM::VCVTMUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12610 { 2304 /* vcvtm */, ARM::VCVTMUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12611 { 2304 /* vcvtm */, ARM::VCVTMUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12612 { 2304 /* vcvtm */, ARM::MVE_VCVTs16f16m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12613 { 2304 /* vcvtm */, ARM::MVE_VCVTs32f32m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12614 { 2304 /* vcvtm */, ARM::MVE_VCVTu16f16m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12615 { 2304 /* vcvtm */, ARM::MVE_VCVTu32f32m, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12616 { 2310 /* vcvtn */, ARM::VCVTNNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12617 { 2310 /* vcvtn */, ARM::VCVTNNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12618 { 2310 /* vcvtn */, ARM::VCVTNNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12619 { 2310 /* vcvtn */, ARM::VCVTNNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12620 { 2310 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12621 { 2310 /* vcvtn */, ARM::VCVTNSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12622 { 2310 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12623 { 2310 /* vcvtn */, ARM::VCVTNNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12624 { 2310 /* vcvtn */, ARM::VCVTNNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12625 { 2310 /* vcvtn */, ARM::VCVTNNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12626 { 2310 /* vcvtn */, ARM::VCVTNNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12627 { 2310 /* vcvtn */, ARM::VCVTNUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12628 { 2310 /* vcvtn */, ARM::VCVTNUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12629 { 2310 /* vcvtn */, ARM::VCVTNUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12630 { 2310 /* vcvtn */, ARM::MVE_VCVTs16f16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12631 { 2310 /* vcvtn */, ARM::MVE_VCVTs32f32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12632 { 2310 /* vcvtn */, ARM::MVE_VCVTu16f16n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12633 { 2310 /* vcvtn */, ARM::MVE_VCVTu32f32n, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12634 { 2316 /* vcvtp */, ARM::VCVTPNSQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12635 { 2316 /* vcvtp */, ARM::VCVTPNSDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12636 { 2316 /* vcvtp */, ARM::VCVTPNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12637 { 2316 /* vcvtp */, ARM::VCVTPNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12638 { 2316 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12639 { 2316 /* vcvtp */, ARM::VCVTPSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12640 { 2316 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12641 { 2316 /* vcvtp */, ARM::VCVTPNUQh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
12642 { 2316 /* vcvtp */, ARM::VCVTPNUDh, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
12643 { 2316 /* vcvtp */, ARM::VCVTPNUQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12644 { 2316 /* vcvtp */, ARM::VCVTPNUDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12645 { 2316 /* vcvtp */, ARM::VCVTPUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12646 { 2316 /* vcvtp */, ARM::VCVTPUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12647 { 2316 /* vcvtp */, ARM::VCVTPUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12648 { 2316 /* vcvtp */, ARM::MVE_VCVTs16f16p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12649 { 2316 /* vcvtp */, ARM::MVE_VCVTs32f32p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12650 { 2316 /* vcvtp */, ARM::MVE_VCVTu16f16p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12651 { 2316 /* vcvtp */, ARM::MVE_VCVTu32f32p, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12652 { 2322 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12653 { 2322 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12654 { 2322 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12655 { 2322 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12656 { 2322 /* vcvtr */, ARM::VTOUIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12657 { 2322 /* vcvtr */, ARM::VTOUIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12658 { 2328 /* vcvtt */, ARM::VCVTTHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12659 { 2328 /* vcvtt */, ARM::VCVTTHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
12660 { 2328 /* vcvtt */, ARM::BF16_VCVTT, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasBF16, { MCK_CondCode, MCK__DOT_bf16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12661 { 2328 /* vcvtt */, ARM::VCVTTSH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12662 { 2328 /* vcvtt */, ARM::VCVTTDH, Convert__Reg1_3__Tie0_1_1__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12663 { 2328 /* vcvtt */, ARM::MVE_VCVTf16f32th, Convert__Reg1_3__Tie0_1_1__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12664 { 2328 /* vcvtt */, ARM::MVE_VCVTf32f16th, Convert__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12665 { 2334 /* vcx1 */, ARM::CDE_VCX1_fpdp, Convert__Reg1_1__CoprocNum1_0__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_Imm11b }, },
12666 { 2334 /* vcx1 */, ARM::CDE_VCX1_fpsp, Convert__Reg1_1__CoprocNum1_0__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_Imm11b }, },
12667 { 2334 /* vcx1 */, ARM::CDE_VCX1_vec, Convert__Reg1_2__CoprocNum1_1__Imm12b1_3__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_Imm12b }, },
12668 { 2339 /* vcx1a */, ARM::CDE_VCX1A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_Imm11b }, },
12669 { 2339 /* vcx1a */, ARM::CDE_VCX1A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Imm11b1_2, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_Imm11b }, },
12670 { 2339 /* vcx1a */, ARM::CDE_VCX1A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Imm12b1_3__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_Imm12b }, },
12671 { 2345 /* vcx2 */, ARM::CDE_VCX2_fpdp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm6b }, },
12672 { 2345 /* vcx2 */, ARM::CDE_VCX2_fpsp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_Imm6b }, },
12673 { 2345 /* vcx2 */, ARM::CDE_VCX2_vec, Convert__Reg1_2__CoprocNum1_1__Reg1_3__Imm7b1_4__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_Imm7b }, },
12674 { 2350 /* vcx2a */, ARM::CDE_VCX2A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm6b }, },
12675 { 2350 /* vcx2a */, ARM::CDE_VCX2A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Imm6b1_3, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_Imm6b }, },
12676 { 2350 /* vcx2a */, ARM::CDE_VCX2A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Imm7b1_4__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_Imm7b }, },
12677 { 2356 /* vcx3 */, ARM::CDE_VCX3_fpdp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm3b }, },
12678 { 2356 /* vcx3 */, ARM::CDE_VCX3_fpsp, Convert__Reg1_1__CoprocNum1_0__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_HPR, MCK_Imm3b }, },
12679 { 2356 /* vcx3 */, ARM::CDE_VCX3_vec, Convert__Reg1_2__CoprocNum1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredR4_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredR, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_Imm4b }, },
12680 { 2361 /* vcx3a */, ARM::CDE_VCX3A_fpdp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_DPR_VFP2, MCK_Imm3b }, },
12681 { 2361 /* vcx3a */, ARM::CDE_VCX3A_fpsp, Convert__Reg1_1__CoprocNum1_0__Tie0_1_1__Reg1_2__Reg1_3__Imm3b1_4, AMFBS_HasCDE_HasFPRegs, { MCK_CoprocNum, MCK_HPR, MCK_HPR, MCK_HPR, MCK_Imm3b }, },
12682 { 2361 /* vcx3a */, ARM::CDE_VCX3A_vec, Convert__Reg1_2__CoprocNum1_1__Tie0_1_1__Reg1_3__Reg1_4__Imm4b1_5__VPTPredN3_0, AMFBS_HasCDE_HasMVEInt, { MCK_VPTPredN, MCK_CoprocNum, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_Imm4b }, },
12683 { 2367 /* vddup */, ARM::MVE_VDDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12684 { 2367 /* vddup */, ARM::MVE_VDDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12685 { 2367 /* vddup */, ARM::MVE_VDDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12686 { 2373 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12687 { 2373 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
12688 { 2373 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12689 { 2373 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12690 { 2373 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12691 { 2373 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12692 { 2378 /* vdot */, ARM::BF16VDOTS_VDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12693 { 2378 /* vdot */, ARM::BF16VDOTS_VDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12694 { 2378 /* vdot */, ARM::BF16VDOTI_VDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
12695 { 2378 /* vdot */, ARM::BF16VDOTI_VDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
12696 { 2383 /* vdup */, ARM::VDUP16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_GPR }, },
12697 { 2383 /* vdup */, ARM::VDUP16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_GPR }, },
12698 { 2383 /* vdup */, ARM::VDUP32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_GPR }, },
12699 { 2383 /* vdup */, ARM::VDUP32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_GPR }, },
12700 { 2383 /* vdup */, ARM::VDUP8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_GPR }, },
12701 { 2383 /* vdup */, ARM::VDUP8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_GPR }, },
12702 { 2383 /* vdup */, ARM::MVE_VDUP16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_rGPR }, },
12703 { 2383 /* vdup */, ARM::MVE_VDUP32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_rGPR }, },
12704 { 2383 /* vdup */, ARM::MVE_VDUP8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_rGPR }, },
12705 { 2383 /* vdup */, ARM::VDUPLN16q, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_DPR, MCK_VectorIndex16 }, },
12706 { 2383 /* vdup */, ARM::VDUPLN16d, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_VectorIndex16 }, },
12707 { 2383 /* vdup */, ARM::VDUPLN32q, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_DPR, MCK_VectorIndex32 }, },
12708 { 2383 /* vdup */, ARM::VDUPLN32d, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_VectorIndex32 }, },
12709 { 2383 /* vdup */, ARM::VDUPLN8q, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_DPR, MCK_VectorIndex8 }, },
12710 { 2383 /* vdup */, ARM::VDUPLN8d, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_VectorIndex8 }, },
12711 { 2388 /* vdwdup */, ARM::MVE_VDWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12712 { 2388 /* vdwdup */, ARM::MVE_VDWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12713 { 2388 /* vdwdup */, ARM::MVE_VDWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12714 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
12715 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
12716 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
12717 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
12718 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
12719 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
12720 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
12721 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
12722 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
12723 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
12724 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
12725 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
12726 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12727 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12728 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12729 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12730 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12731 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
12732 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12733 { 2395 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12734 { 2395 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12735 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12736 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12737 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12738 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12739 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12740 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12741 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12742 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12743 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12744 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12745 { 2395 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12746 { 2400 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm0_7 }, },
12747 { 2400 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, },
12748 { 2400 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm0_3 }, },
12749 { 2400 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, },
12750 { 2400 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm0_1 }, },
12751 { 2400 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
12752 { 2400 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, },
12753 { 2400 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_7 }, },
12754 { 2400 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, },
12755 { 2400 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_3 }, },
12756 { 2400 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, },
12757 { 2400 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_1 }, },
12758 { 2400 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, },
12759 { 2400 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, },
12760 { 2405 /* vfma */, ARM::VFMAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12761 { 2405 /* vfma */, ARM::VFMAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12762 { 2405 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12763 { 2405 /* vfma */, ARM::VFMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12764 { 2405 /* vfma */, ARM::VFMAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12765 { 2405 /* vfma */, ARM::VFMAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12766 { 2405 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12767 { 2405 /* vfma */, ARM::MVE_VFMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12768 { 2405 /* vfma */, ARM::MVE_VFMA_qr_f32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12769 { 2405 /* vfma */, ARM::MVE_VFMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12770 { 2405 /* vfma */, ARM::MVE_VFMA_qr_f16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12771 { 2410 /* vfmab */, ARM::VBF16MALBQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12772 { 2410 /* vfmab */, ARM::VBF16MALBQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
12773 { 2416 /* vfmal */, ARM::VFMALQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12774 { 2416 /* vfmal */, ARM::VFMALD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
12775 { 2416 /* vfmal */, ARM::VFMALQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
12776 { 2416 /* vfmal */, ARM::VFMALDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, },
12777 { 2422 /* vfmas */, ARM::MVE_VFMA_qr_Sf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12778 { 2422 /* vfmas */, ARM::MVE_VFMA_qr_Sf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12779 { 2428 /* vfmat */, ARM::VBF16MALTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12780 { 2428 /* vfmat */, ARM::VBF16MALTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
12781 { 2434 /* vfms */, ARM::VFMSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12782 { 2434 /* vfms */, ARM::VFMSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12783 { 2434 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12784 { 2434 /* vfms */, ARM::VFMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12785 { 2434 /* vfms */, ARM::VFMShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12786 { 2434 /* vfms */, ARM::VFMShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12787 { 2434 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12788 { 2434 /* vfms */, ARM::MVE_VFMSf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12789 { 2434 /* vfms */, ARM::MVE_VFMSf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12790 { 2439 /* vfmsl */, ARM::VFMSLQ, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR }, },
12791 { 2439 /* vfmsl */, ARM::VFMSLD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
12792 { 2439 /* vfmsl */, ARM::VFMSLQI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex161_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
12793 { 2439 /* vfmsl */, ARM::VFMSLDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, },
12794 { 2445 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12795 { 2445 /* vfnma */, ARM::VFNMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12796 { 2445 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12797 { 2451 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12798 { 2451 /* vfnms */, ARM::VFNMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
12799 { 2451 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12800 { 2457 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12801 { 2457 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12802 { 2457 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12803 { 2457 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12804 { 2457 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12805 { 2457 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12806 { 2457 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12807 { 2457 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12808 { 2457 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12809 { 2457 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12810 { 2457 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12811 { 2457 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12812 { 2457 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12813 { 2457 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12814 { 2457 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12815 { 2457 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12816 { 2457 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12817 { 2457 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12818 { 2457 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12819 { 2457 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12820 { 2457 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12821 { 2457 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12822 { 2457 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12823 { 2457 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12824 { 2457 /* vhadd */, ARM::MVE_VHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12825 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12826 { 2457 /* vhadd */, ARM::MVE_VHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12827 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12828 { 2457 /* vhadd */, ARM::MVE_VHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12829 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12830 { 2457 /* vhadd */, ARM::MVE_VHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12831 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12832 { 2457 /* vhadd */, ARM::MVE_VHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12833 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12834 { 2457 /* vhadd */, ARM::MVE_VHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12835 { 2457 /* vhadd */, ARM::MVE_VHADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12836 { 2463 /* vhcadd */, ARM::MVE_VHCADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12837 { 2463 /* vhcadd */, ARM::MVE_VHCADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12838 { 2463 /* vhcadd */, ARM::MVE_VHCADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12839 { 2470 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
12840 { 2470 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
12841 { 2470 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12842 { 2470 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12843 { 2470 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
12844 { 2470 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
12845 { 2470 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
12846 { 2470 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
12847 { 2470 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
12848 { 2470 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
12849 { 2470 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
12850 { 2470 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
12851 { 2470 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12852 { 2470 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12853 { 2470 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12854 { 2470 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12855 { 2470 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12856 { 2470 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12857 { 2470 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
12858 { 2470 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
12859 { 2470 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12860 { 2470 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12861 { 2470 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
12862 { 2470 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
12863 { 2470 /* vhsub */, ARM::MVE_VHSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12864 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12865 { 2470 /* vhsub */, ARM::MVE_VHSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12866 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12867 { 2470 /* vhsub */, ARM::MVE_VHSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12868 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12869 { 2470 /* vhsub */, ARM::MVE_VHSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12870 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12871 { 2470 /* vhsub */, ARM::MVE_VHSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12872 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12873 { 2470 /* vhsub */, ARM::MVE_VHSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12874 { 2470 /* vhsub */, ARM::MVE_VHSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12875 { 2476 /* vidup */, ARM::MVE_VIDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12876 { 2476 /* vidup */, ARM::MVE_VIDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12877 { 2476 /* vidup */, ARM::MVE_VIDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12878 { 2482 /* vins */, ARM::VINSH, Convert__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12879 { 2487 /* viwdup */, ARM::MVE_VIWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12880 { 2487 /* viwdup */, ARM::MVE_VIWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12881 { 2487 /* viwdup */, ARM::MVE_VIWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12882 { 2494 /* vjcvt */, ARM::VJCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasV8_3a, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12883 { 2500 /* vld1 */, ARM::VLD1DUPq16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, },
12884 { 2500 /* vld1 */, ARM::VLD1q16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12885 { 2500 /* vld1 */, ARM::VLD1d16Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12886 { 2500 /* vld1 */, ARM::VLD1DUPd16, Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16 }, },
12887 { 2500 /* vld1 */, ARM::VLD1d16, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, },
12888 { 2500 /* vld1 */, ARM::VLD1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, },
12889 { 2500 /* vld1 */, ARM::VLD1d16T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12890 { 2500 /* vld1 */, ARM::VLD1DUPq32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, },
12891 { 2500 /* vld1 */, ARM::VLD1q32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12892 { 2500 /* vld1 */, ARM::VLD1d32Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12893 { 2500 /* vld1 */, ARM::VLD1DUPd32, Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32 }, },
12894 { 2500 /* vld1 */, ARM::VLD1d32, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, },
12895 { 2500 /* vld1 */, ARM::VLD1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, },
12896 { 2500 /* vld1 */, ARM::VLD1d32T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12897 { 2500 /* vld1 */, ARM::VLD1q64, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12898 { 2500 /* vld1 */, ARM::VLD1d64Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12899 { 2500 /* vld1 */, ARM::VLD1d64, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, },
12900 { 2500 /* vld1 */, ARM::VLD1d64T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12901 { 2500 /* vld1 */, ARM::VLD1DUPq8, Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone }, },
12902 { 2500 /* vld1 */, ARM::VLD1q8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12903 { 2500 /* vld1 */, ARM::VLD1d8Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12904 { 2500 /* vld1 */, ARM::VLD1DUPd8, Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone }, },
12905 { 2500 /* vld1 */, ARM::VLD1d8, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, },
12906 { 2500 /* vld1 */, ARM::VLD1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, },
12907 { 2500 /* vld1 */, ARM::VLD1d8T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
12908 { 2500 /* vld1 */, ARM::VLD1DUPq16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12909 { 2500 /* vld1 */, ARM::VLD1DUPq16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
12910 { 2500 /* vld1 */, ARM::VLD1q16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12911 { 2500 /* vld1 */, ARM::VLD1q16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12912 { 2500 /* vld1 */, ARM::VLD1d16Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12913 { 2500 /* vld1 */, ARM::VLD1d16Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12914 { 2500 /* vld1 */, ARM::VLD1DUPd16wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12915 { 2500 /* vld1 */, ARM::VLD1DUPd16wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
12916 { 2500 /* vld1 */, ARM::VLD1d16wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12917 { 2500 /* vld1 */, ARM::VLD1d16wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
12918 { 2500 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
12919 { 2500 /* vld1 */, ARM::VLD1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
12920 { 2500 /* vld1 */, ARM::VLD1d16Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12921 { 2500 /* vld1 */, ARM::VLD1d16Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12922 { 2500 /* vld1 */, ARM::VLD1DUPq32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12923 { 2500 /* vld1 */, ARM::VLD1DUPq32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
12924 { 2500 /* vld1 */, ARM::VLD1q32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12925 { 2500 /* vld1 */, ARM::VLD1q32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12926 { 2500 /* vld1 */, ARM::VLD1d32Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12927 { 2500 /* vld1 */, ARM::VLD1d32Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12928 { 2500 /* vld1 */, ARM::VLD1DUPd32wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12929 { 2500 /* vld1 */, ARM::VLD1DUPd32wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
12930 { 2500 /* vld1 */, ARM::VLD1d32wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12931 { 2500 /* vld1 */, ARM::VLD1d32wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
12932 { 2500 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12933 { 2500 /* vld1 */, ARM::VLD1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
12934 { 2500 /* vld1 */, ARM::VLD1d32Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12935 { 2500 /* vld1 */, ARM::VLD1d32Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12936 { 2500 /* vld1 */, ARM::VLD1q64wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12937 { 2500 /* vld1 */, ARM::VLD1q64wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12938 { 2500 /* vld1 */, ARM::VLD1d64Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12939 { 2500 /* vld1 */, ARM::VLD1d64Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12940 { 2500 /* vld1 */, ARM::VLD1d64wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12941 { 2500 /* vld1 */, ARM::VLD1d64wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
12942 { 2500 /* vld1 */, ARM::VLD1d64Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12943 { 2500 /* vld1 */, ARM::VLD1d64Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12944 { 2500 /* vld1 */, ARM::VLD1DUPq8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12945 { 2500 /* vld1 */, ARM::VLD1DUPq8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12946 { 2500 /* vld1 */, ARM::VLD1q8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12947 { 2500 /* vld1 */, ARM::VLD1q8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12948 { 2500 /* vld1 */, ARM::VLD1d8Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12949 { 2500 /* vld1 */, ARM::VLD1d8Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12950 { 2500 /* vld1 */, ARM::VLD1DUPd8wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12951 { 2500 /* vld1 */, ARM::VLD1DUPd8wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12952 { 2500 /* vld1 */, ARM::VLD1d8wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12953 { 2500 /* vld1 */, ARM::VLD1d8wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
12954 { 2500 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12955 { 2500 /* vld1 */, ARM::VLD1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
12956 { 2500 /* vld1 */, ARM::VLD1d8Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12957 { 2500 /* vld1 */, ARM::VLD1d8Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
12958 { 2500 /* vld1 */, ARM::VLD1LNd16, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12959 { 2500 /* vld1 */, ARM::VLD1LNd8, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
12960 { 2500 /* vld1 */, ARM::VLD1LNd16_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12961 { 2500 /* vld1 */, ARM::VLD1LNd32, Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, },
12962 { 2500 /* vld1 */, ARM::VLD1LNd32_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12963 { 2500 /* vld1 */, ARM::VLD1LNd8_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
12964 { 2505 /* vld2 */, ARM::VLD2DUPd16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, },
12965 { 2505 /* vld2 */, ARM::VLD2d16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12966 { 2505 /* vld2 */, ARM::VLD2DUPd16x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32 }, },
12967 { 2505 /* vld2 */, ARM::VLD2b16, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
12968 { 2505 /* vld2 */, ARM::VLD2q16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12969 { 2505 /* vld2 */, ARM::VLD2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, },
12970 { 2505 /* vld2 */, ARM::VLD2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, },
12971 { 2505 /* vld2 */, ARM::VLD2DUPd32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64 }, },
12972 { 2505 /* vld2 */, ARM::VLD2d32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12973 { 2505 /* vld2 */, ARM::VLD2DUPd32x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64 }, },
12974 { 2505 /* vld2 */, ARM::VLD2b32, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
12975 { 2505 /* vld2 */, ARM::VLD2q32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12976 { 2505 /* vld2 */, ARM::VLD2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, },
12977 { 2505 /* vld2 */, ARM::VLD2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, },
12978 { 2505 /* vld2 */, ARM::VLD2DUPd8, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, },
12979 { 2505 /* vld2 */, ARM::VLD2d8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
12980 { 2505 /* vld2 */, ARM::VLD2DUPd8x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16 }, },
12981 { 2505 /* vld2 */, ARM::VLD2b8, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
12982 { 2505 /* vld2 */, ARM::VLD2q8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
12983 { 2505 /* vld2 */, ARM::VLD2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, },
12984 { 2505 /* vld2 */, ARM::VLD2DUPd16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12985 { 2505 /* vld2 */, ARM::VLD2DUPd16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
12986 { 2505 /* vld2 */, ARM::VLD2d16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12987 { 2505 /* vld2 */, ARM::VLD2d16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
12988 { 2505 /* vld2 */, ARM::VLD2DUPd16x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12989 { 2505 /* vld2 */, ARM::VLD2DUPd16x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
12990 { 2505 /* vld2 */, ARM::VLD2b16wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12991 { 2505 /* vld2 */, ARM::VLD2b16wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
12992 { 2505 /* vld2 */, ARM::VLD2q16wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12993 { 2505 /* vld2 */, ARM::VLD2q16wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
12994 { 2505 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12995 { 2505 /* vld2 */, ARM::VLD2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
12996 { 2505 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12997 { 2505 /* vld2 */, ARM::VLD2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
12998 { 2505 /* vld2 */, ARM::VLD2DUPd32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12999 { 2505 /* vld2 */, ARM::VLD2DUPd32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
13000 { 2505 /* vld2 */, ARM::VLD2d32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13001 { 2505 /* vld2 */, ARM::VLD2d32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
13002 { 2505 /* vld2 */, ARM::VLD2DUPd32x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
13003 { 2505 /* vld2 */, ARM::VLD2DUPd32x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
13004 { 2505 /* vld2 */, ARM::VLD2b32wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13005 { 2505 /* vld2 */, ARM::VLD2b32wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
13006 { 2505 /* vld2 */, ARM::VLD2q32wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13007 { 2505 /* vld2 */, ARM::VLD2q32wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13008 { 2505 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13009 { 2505 /* vld2 */, ARM::VLD2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
13010 { 2505 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13011 { 2505 /* vld2 */, ARM::VLD2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
13012 { 2505 /* vld2 */, ARM::VLD2DUPd8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
13013 { 2505 /* vld2 */, ARM::VLD2DUPd8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
13014 { 2505 /* vld2 */, ARM::VLD2d8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13015 { 2505 /* vld2 */, ARM::VLD2d8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
13016 { 2505 /* vld2 */, ARM::VLD2DUPd8x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
13017 { 2505 /* vld2 */, ARM::VLD2DUPd8x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, },
13018 { 2505 /* vld2 */, ARM::VLD2b8wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13019 { 2505 /* vld2 */, ARM::VLD2b8wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
13020 { 2505 /* vld2 */, ARM::VLD2q8wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13021 { 2505 /* vld2 */, ARM::VLD2q8wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13022 { 2505 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
13023 { 2505 /* vld2 */, ARM::VLD2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
13024 { 2510 /* vld20 */, ARM::MVE_VLD20_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13025 { 2510 /* vld20 */, ARM::MVE_VLD20_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13026 { 2510 /* vld20 */, ARM::MVE_VLD20_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13027 { 2510 /* vld20 */, ARM::MVE_VLD20_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13028 { 2510 /* vld20 */, ARM::MVE_VLD20_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13029 { 2510 /* vld20 */, ARM::MVE_VLD20_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13030 { 2516 /* vld21 */, ARM::MVE_VLD21_16, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13031 { 2516 /* vld21 */, ARM::MVE_VLD21_32, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13032 { 2516 /* vld21 */, ARM::MVE_VLD21_8, Convert__VecListTwoMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
13033 { 2516 /* vld21 */, ARM::MVE_VLD21_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13034 { 2516 /* vld21 */, ARM::MVE_VLD21_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13035 { 2516 /* vld21 */, ARM::MVE_VLD21_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13036 { 2522 /* vld3 */, ARM::VLD3DUPdAsm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
13037 { 2522 /* vld3 */, ARM::VLD3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13038 { 2522 /* vld3 */, ARM::VLD3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, },
13039 { 2522 /* vld3 */, ARM::VLD3DUPqAsm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
13040 { 2522 /* vld3 */, ARM::VLD3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
13041 { 2522 /* vld3 */, ARM::VLD3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, },
13042 { 2522 /* vld3 */, ARM::VLD3DUPdAsm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
13043 { 2522 /* vld3 */, ARM::VLD3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13044 { 2522 /* vld3 */, ARM::VLD3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, },
13045 { 2522 /* vld3 */, ARM::VLD3DUPqAsm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
13046 { 2522 /* vld3 */, ARM::VLD3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
13047 { 2522 /* vld3 */, ARM::VLD3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, },
13048 { 2522 /* vld3 */, ARM::VLD3DUPdAsm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, },
13049 { 2522 /* vld3 */, ARM::VLD3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
13050 { 2522 /* vld3 */, ARM::VLD3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, },
13051 { 2522 /* vld3 */, ARM::VLD3DUPqAsm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
13052 { 2522 /* vld3 */, ARM::VLD3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
13053 { 2522 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13054 { 2522 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13055 { 2522 /* vld3 */, ARM::VLD3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13056 { 2522 /* vld3 */, ARM::VLD3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13057 { 2522 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13058 { 2522 /* vld3 */, ARM::VLD3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13059 { 2522 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13060 { 2522 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13061 { 2522 /* vld3 */, ARM::VLD3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13062 { 2522 /* vld3 */, ARM::VLD3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
13063 { 2522 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13064 { 2522 /* vld3 */, ARM::VLD3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13065 { 2522 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13066 { 2522 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13067 { 2522 /* vld3 */, ARM::VLD3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13068 { 2522 /* vld3 */, ARM::VLD3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13069 { 2522 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13070 { 2522 /* vld3 */, ARM::VLD3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13071 { 2522 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13072 { 2522 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13073 { 2522 /* vld3 */, ARM::VLD3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13074 { 2522 /* vld3 */, ARM::VLD3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
13075 { 2522 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13076 { 2522 /* vld3 */, ARM::VLD3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13077 { 2522 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13078 { 2522 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13079 { 2522 /* vld3 */, ARM::VLD3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13080 { 2522 /* vld3 */, ARM::VLD3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
13081 { 2522 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
13082 { 2522 /* vld3 */, ARM::VLD3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
13083 { 2522 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
13084 { 2522 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
13085 { 2522 /* vld3 */, ARM::VLD3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13086 { 2522 /* vld3 */, ARM::VLD3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
13087 { 2522 /* vld3 */, ARM::VLD3d16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13088 { 2522 /* vld3 */, ARM::VLD3q16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13089 { 2522 /* vld3 */, ARM::VLD3d32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13090 { 2522 /* vld3 */, ARM::VLD3q32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13091 { 2522 /* vld3 */, ARM::VLD3d8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13092 { 2522 /* vld3 */, ARM::VLD3q8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13093 { 2522 /* vld3 */, ARM::VLD3d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13094 { 2522 /* vld3 */, ARM::VLD3q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13095 { 2522 /* vld3 */, ARM::VLD3d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13096 { 2522 /* vld3 */, ARM::VLD3q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13097 { 2522 /* vld3 */, ARM::VLD3d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13098 { 2522 /* vld3 */, ARM::VLD3q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13099 { 2522 /* vld3 */, ARM::VLD3DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13100 { 2522 /* vld3 */, ARM::VLD3DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13101 { 2522 /* vld3 */, ARM::VLD3DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13102 { 2522 /* vld3 */, ARM::VLD3DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13103 { 2522 /* vld3 */, ARM::VLD3DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13104 { 2522 /* vld3 */, ARM::VLD3DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13105 { 2522 /* vld3 */, ARM::VLD3DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13106 { 2522 /* vld3 */, ARM::VLD3DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13107 { 2522 /* vld3 */, ARM::VLD3DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13108 { 2522 /* vld3 */, ARM::VLD3DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13109 { 2522 /* vld3 */, ARM::VLD3DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13110 { 2522 /* vld3 */, ARM::VLD3DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, },
13111 { 2527 /* vld4 */, ARM::VLD4DUPdAsm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64 }, },
13112 { 2527 /* vld4 */, ARM::VLD4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13113 { 2527 /* vld4 */, ARM::VLD4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, },
13114 { 2527 /* vld4 */, ARM::VLD4DUPqAsm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64 }, },
13115 { 2527 /* vld4 */, ARM::VLD4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
13116 { 2527 /* vld4 */, ARM::VLD4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, },
13117 { 2527 /* vld4 */, ARM::VLD4DUPdAsm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128 }, },
13118 { 2527 /* vld4 */, ARM::VLD4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13119 { 2527 /* vld4 */, ARM::VLD4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, },
13120 { 2527 /* vld4 */, ARM::VLD4DUPqAsm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128 }, },
13121 { 2527 /* vld4 */, ARM::VLD4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
13122 { 2527 /* vld4 */, ARM::VLD4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, },
13123 { 2527 /* vld4 */, ARM::VLD4DUPdAsm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32 }, },
13124 { 2527 /* vld4 */, ARM::VLD4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
13125 { 2527 /* vld4 */, ARM::VLD4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, },
13126 { 2527 /* vld4 */, ARM::VLD4DUPqAsm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32 }, },
13127 { 2527 /* vld4 */, ARM::VLD4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
13128 { 2527 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
13129 { 2527 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
13130 { 2527 /* vld4 */, ARM::VLD4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13131 { 2527 /* vld4 */, ARM::VLD4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13132 { 2527 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13133 { 2527 /* vld4 */, ARM::VLD4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
13134 { 2527 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
13135 { 2527 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
13136 { 2527 /* vld4 */, ARM::VLD4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13137 { 2527 /* vld4 */, ARM::VLD4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13138 { 2527 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
13139 { 2527 /* vld4 */, ARM::VLD4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
13140 { 2527 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
13141 { 2527 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
13142 { 2527 /* vld4 */, ARM::VLD4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13143 { 2527 /* vld4 */, ARM::VLD4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13144 { 2527 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13145 { 2527 /* vld4 */, ARM::VLD4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
13146 { 2527 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
13147 { 2527 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
13148 { 2527 /* vld4 */, ARM::VLD4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13149 { 2527 /* vld4 */, ARM::VLD4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13150 { 2527 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
13151 { 2527 /* vld4 */, ARM::VLD4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
13152 { 2527 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
13153 { 2527 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
13154 { 2527 /* vld4 */, ARM::VLD4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13155 { 2527 /* vld4 */, ARM::VLD4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13156 { 2527 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
13157 { 2527 /* vld4 */, ARM::VLD4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
13158 { 2527 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
13159 { 2527 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
13160 { 2527 /* vld4 */, ARM::VLD4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
13161 { 2527 /* vld4 */, ARM::VLD4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
13162 { 2527 /* vld4 */, ARM::VLD4d16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13163 { 2527 /* vld4 */, ARM::VLD4q16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13164 { 2527 /* vld4 */, ARM::VLD4d32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13165 { 2527 /* vld4 */, ARM::VLD4q32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13166 { 2527 /* vld4 */, ARM::VLD4d8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13167 { 2527 /* vld4 */, ARM::VLD4q8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
13168 { 2527 /* vld4 */, ARM::VLD4d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13169 { 2527 /* vld4 */, ARM::VLD4q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13170 { 2527 /* vld4 */, ARM::VLD4d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13171 { 2527 /* vld4 */, ARM::VLD4q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13172 { 2527 /* vld4 */, ARM::VLD4d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13173 { 2527 /* vld4 */, ARM::VLD4q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13174 { 2527 /* vld4 */, ARM::VLD4DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13175 { 2527 /* vld4 */, ARM::VLD4DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13176 { 2527 /* vld4 */, ARM::VLD4DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13177 { 2527 /* vld4 */, ARM::VLD4DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13178 { 2527 /* vld4 */, ARM::VLD4DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13179 { 2527 /* vld4 */, ARM::VLD4DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
13180 { 2527 /* vld4 */, ARM::VLD4DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13181 { 2527 /* vld4 */, ARM::VLD4DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13182 { 2527 /* vld4 */, ARM::VLD4DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13183 { 2527 /* vld4 */, ARM::VLD4DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13184 { 2527 /* vld4 */, ARM::VLD4DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13185 { 2527 /* vld4 */, ARM::VLD4DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
13186 { 2532 /* vld40 */, ARM::MVE_VLD40_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13187 { 2532 /* vld40 */, ARM::MVE_VLD40_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13188 { 2532 /* vld40 */, ARM::MVE_VLD40_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13189 { 2532 /* vld40 */, ARM::MVE_VLD40_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13190 { 2532 /* vld40 */, ARM::MVE_VLD40_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13191 { 2532 /* vld40 */, ARM::MVE_VLD40_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13192 { 2538 /* vld41 */, ARM::MVE_VLD41_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13193 { 2538 /* vld41 */, ARM::MVE_VLD41_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13194 { 2538 /* vld41 */, ARM::MVE_VLD41_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13195 { 2538 /* vld41 */, ARM::MVE_VLD41_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13196 { 2538 /* vld41 */, ARM::MVE_VLD41_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13197 { 2538 /* vld41 */, ARM::MVE_VLD41_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13198 { 2544 /* vld42 */, ARM::MVE_VLD42_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13199 { 2544 /* vld42 */, ARM::MVE_VLD42_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13200 { 2544 /* vld42 */, ARM::MVE_VLD42_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13201 { 2544 /* vld42 */, ARM::MVE_VLD42_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13202 { 2544 /* vld42 */, ARM::MVE_VLD42_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13203 { 2544 /* vld42 */, ARM::MVE_VLD42_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13204 { 2550 /* vld43 */, ARM::MVE_VLD43_16, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13205 { 2550 /* vld43 */, ARM::MVE_VLD43_32, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13206 { 2550 /* vld43 */, ARM::MVE_VLD43_8, Convert__VecListFourMQ1_1__Tie0_1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
13207 { 2550 /* vld43 */, ARM::MVE_VLD43_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13208 { 2550 /* vld43 */, ARM::MVE_VLD43_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13209 { 2550 /* vld43 */, ARM::MVE_VLD43_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
13210 { 2556 /* vldmdb */, ARM::VLDMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
13211 { 2556 /* vldmdb */, ARM::VLDMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
13212 { 2563 /* vldmia */, ARM::VLDMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
13213 { 2563 /* vldmia */, ARM::VLDMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, },
13214 { 2563 /* vldmia */, ARM::VLDMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
13215 { 2563 /* vldmia */, ARM::VLDMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
13216 { 2570 /* vldr */, ARM::VLDR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset }, },
13217 { 2570 /* vldr */, ARM::VLDR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, },
13218 { 2570 /* vldr */, ARM::VLDR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, },
13219 { 2570 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, },
13220 { 2570 /* vldr */, ARM::VLDR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, },
13221 { 2570 /* vldr */, ARM::VLDR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, },
13222 { 2570 /* vldr */, ARM::VLDRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, },
13223 { 2570 /* vldr */, ARM::VLDRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
13224 { 2570 /* vldr */, ARM::VLDRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
13225 { 2570 /* vldr */, ARM::VLDRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
13226 { 2570 /* vldr */, ARM::VLDRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, },
13227 { 2570 /* vldr */, ARM::VLDR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13228 { 2570 /* vldr */, ARM::VLDR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13229 { 2570 /* vldr */, ARM::VLDR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13230 { 2570 /* vldr */, ARM::VLDR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13231 { 2570 /* vldr */, ARM::VLDR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13232 { 2570 /* vldr */, ARM::VLDR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13233 { 2570 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13234 { 2570 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_post, Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13235 { 2570 /* vldr */, ARM::VLDR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13236 { 2570 /* vldr */, ARM::VLDR_P0_post, Convert__imm_95_0__MemNoOffsetT21_2__Tie1_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13237 { 2570 /* vldr */, ARM::VLDR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
13238 { 2570 /* vldr */, ARM::VLDR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
13239 { 2575 /* vldrb */, ARM::MVE_VLDRBS16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13240 { 2575 /* vldrb */, ARM::MVE_VLDRBS16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13241 { 2575 /* vldrb */, ARM::MVE_VLDRBS32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13242 { 2575 /* vldrb */, ARM::MVE_VLDRBS32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13243 { 2575 /* vldrb */, ARM::MVE_VLDRBU16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13244 { 2575 /* vldrb */, ARM::MVE_VLDRBU16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13245 { 2575 /* vldrb */, ARM::MVE_VLDRBU32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13246 { 2575 /* vldrb */, ARM::MVE_VLDRBU32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
13247 { 2575 /* vldrb */, ARM::MVE_VLDRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0Offset }, },
13248 { 2575 /* vldrb */, ARM::MVE_VLDRBU8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13249 { 2575 /* vldrb */, ARM::MVE_VLDRBS16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13250 { 2575 /* vldrb */, ARM::MVE_VLDRBS16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13251 { 2575 /* vldrb */, ARM::MVE_VLDRBS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13252 { 2575 /* vldrb */, ARM::MVE_VLDRBS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13253 { 2575 /* vldrb */, ARM::MVE_VLDRBU16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13254 { 2575 /* vldrb */, ARM::MVE_VLDRBU16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13255 { 2575 /* vldrb */, ARM::MVE_VLDRBU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
13256 { 2575 /* vldrb */, ARM::MVE_VLDRBU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
13257 { 2575 /* vldrb */, ARM::MVE_VLDRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, },
13258 { 2575 /* vldrb */, ARM::MVE_VLDRBU8_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift0 }, },
13259 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset }, },
13260 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13261 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS3Offset }, },
13262 { 2581 /* vldrd */, ARM::MVE_VLDRDU64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, },
13263 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13264 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
13265 { 2587 /* vldrh */, ARM::MVE_VLDRHS32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
13266 { 2587 /* vldrh */, ARM::MVE_VLDRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1Offset }, },
13267 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13268 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS1Offset }, },
13269 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13270 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
13271 { 2587 /* vldrh */, ARM::MVE_VLDRHU32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
13272 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
13273 { 2587 /* vldrh */, ARM::MVE_VLDRHS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
13274 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, },
13275 { 2587 /* vldrh */, ARM::MVE_VLDRHU16_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift1 }, },
13276 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
13277 { 2587 /* vldrh */, ARM::MVE_VLDRHU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
13278 { 2593 /* vldrw */, ARM::MVE_VLDRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2Offset }, },
13279 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset }, },
13280 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
13281 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS2Offset }, },
13282 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, },
13283 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift2 }, },
13284 { 2593 /* vldrw */, ARM::MVE_VLDRWU32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, },
13285 { 2599 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0__imm_95_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
13286 { 2599 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13287 { 2599 /* vlldm */, ARM::VLLDM_T2, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13288 { 2605 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0__imm_95_0, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, },
13289 { 2605 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13290 { 2605 /* vlstm */, ARM::VLSTM_T2, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc, MCK_DPRRegList }, },
13291 { 2611 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13292 { 2611 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13293 { 2611 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13294 { 2611 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13295 { 2611 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13296 { 2611 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13297 { 2611 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13298 { 2611 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13299 { 2611 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13300 { 2611 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13301 { 2611 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13302 { 2611 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13303 { 2611 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13304 { 2611 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13305 { 2611 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13306 { 2611 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13307 { 2611 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13308 { 2611 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13309 { 2611 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13310 { 2611 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13311 { 2611 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13312 { 2611 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13313 { 2611 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13314 { 2611 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13315 { 2611 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13316 { 2611 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13317 { 2611 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13318 { 2611 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13319 { 2611 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13320 { 2611 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13321 { 2611 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13322 { 2611 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13323 { 2611 /* vmax */, ARM::MVE_VMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13324 { 2611 /* vmax */, ARM::MVE_VMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13325 { 2611 /* vmax */, ARM::MVE_VMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13326 { 2611 /* vmax */, ARM::MVE_VMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13327 { 2611 /* vmax */, ARM::MVE_VMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13328 { 2611 /* vmax */, ARM::MVE_VMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13329 { 2616 /* vmaxa */, ARM::MVE_VMAXAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13330 { 2616 /* vmaxa */, ARM::MVE_VMAXAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13331 { 2616 /* vmaxa */, ARM::MVE_VMAXAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13332 { 2622 /* vmaxav */, ARM::MVE_VMAXAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13333 { 2622 /* vmaxav */, ARM::MVE_VMAXAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13334 { 2622 /* vmaxav */, ARM::MVE_VMAXAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13335 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13336 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13337 { 2629 /* vmaxnm */, ARM::VFP_VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13338 { 2629 /* vmaxnm */, ARM::VFP_VMAXNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13339 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13340 { 2629 /* vmaxnm */, ARM::NEON_VMAXNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13341 { 2629 /* vmaxnm */, ARM::VFP_VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13342 { 2629 /* vmaxnm */, ARM::MVE_VMAXNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13343 { 2629 /* vmaxnm */, ARM::MVE_VMAXNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13344 { 2636 /* vmaxnma */, ARM::MVE_VMAXNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13345 { 2636 /* vmaxnma */, ARM::MVE_VMAXNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13346 { 2644 /* vmaxnmav */, ARM::MVE_VMAXNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13347 { 2644 /* vmaxnmav */, ARM::MVE_VMAXNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13348 { 2653 /* vmaxnmv */, ARM::MVE_VMAXNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13349 { 2653 /* vmaxnmv */, ARM::MVE_VMAXNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13350 { 2661 /* vmaxv */, ARM::MVE_VMAXVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13351 { 2661 /* vmaxv */, ARM::MVE_VMAXVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13352 { 2661 /* vmaxv */, ARM::MVE_VMAXVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13353 { 2661 /* vmaxv */, ARM::MVE_VMAXVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, },
13354 { 2661 /* vmaxv */, ARM::MVE_VMAXVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, },
13355 { 2661 /* vmaxv */, ARM::MVE_VMAXVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, },
13356 { 2667 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13357 { 2667 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13358 { 2667 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13359 { 2667 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13360 { 2667 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13361 { 2667 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13362 { 2667 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13363 { 2667 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13364 { 2667 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13365 { 2667 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13366 { 2667 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13367 { 2667 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13368 { 2667 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13369 { 2667 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13370 { 2667 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13371 { 2667 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13372 { 2667 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13373 { 2667 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13374 { 2667 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13375 { 2667 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13376 { 2667 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13377 { 2667 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13378 { 2667 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13379 { 2667 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13380 { 2667 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13381 { 2667 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13382 { 2667 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13383 { 2667 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13384 { 2667 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13385 { 2667 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13386 { 2667 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13387 { 2667 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13388 { 2667 /* vmin */, ARM::MVE_VMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13389 { 2667 /* vmin */, ARM::MVE_VMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13390 { 2667 /* vmin */, ARM::MVE_VMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13391 { 2667 /* vmin */, ARM::MVE_VMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13392 { 2667 /* vmin */, ARM::MVE_VMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13393 { 2667 /* vmin */, ARM::MVE_VMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13394 { 2672 /* vmina */, ARM::MVE_VMINAs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13395 { 2672 /* vmina */, ARM::MVE_VMINAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13396 { 2672 /* vmina */, ARM::MVE_VMINAs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13397 { 2678 /* vminav */, ARM::MVE_VMINAVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13398 { 2678 /* vminav */, ARM::MVE_VMINAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13399 { 2678 /* vminav */, ARM::MVE_VMINAVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13400 { 2685 /* vminnm */, ARM::NEON_VMINNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13401 { 2685 /* vminnm */, ARM::NEON_VMINNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13402 { 2685 /* vminnm */, ARM::VFP_VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13403 { 2685 /* vminnm */, ARM::VFP_VMINNMD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13404 { 2685 /* vminnm */, ARM::NEON_VMINNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13405 { 2685 /* vminnm */, ARM::NEON_VMINNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13406 { 2685 /* vminnm */, ARM::VFP_VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13407 { 2685 /* vminnm */, ARM::MVE_VMINNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13408 { 2685 /* vminnm */, ARM::MVE_VMINNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13409 { 2692 /* vminnma */, ARM::MVE_VMINNMAf32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13410 { 2692 /* vminnma */, ARM::MVE_VMINNMAf16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13411 { 2700 /* vminnmav */, ARM::MVE_VMINNMAVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13412 { 2700 /* vminnmav */, ARM::MVE_VMINNMAVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13413 { 2709 /* vminnmv */, ARM::MVE_VMINNMVf32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_rGPR, MCK_MQPR }, },
13414 { 2709 /* vminnmv */, ARM::MVE_VMINNMVf16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_rGPR, MCK_MQPR }, },
13415 { 2717 /* vminv */, ARM::MVE_VMINVs16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_rGPR, MCK_MQPR }, },
13416 { 2717 /* vminv */, ARM::MVE_VMINVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13417 { 2717 /* vminv */, ARM::MVE_VMINVs8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_rGPR, MCK_MQPR }, },
13418 { 2717 /* vminv */, ARM::MVE_VMINVu16, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_rGPR, MCK_MQPR }, },
13419 { 2717 /* vminv */, ARM::MVE_VMINVu32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_rGPR, MCK_MQPR }, },
13420 { 2717 /* vminv */, ARM::MVE_VMINVu8, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_rGPR, MCK_MQPR }, },
13421 { 2723 /* vmla */, ARM::VMLAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13422 { 2723 /* vmla */, ARM::VMLAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13423 { 2723 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13424 { 2723 /* vmla */, ARM::VMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13425 { 2723 /* vmla */, ARM::VMLAv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13426 { 2723 /* vmla */, ARM::VMLAv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13427 { 2723 /* vmla */, ARM::VMLAv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13428 { 2723 /* vmla */, ARM::VMLAv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13429 { 2723 /* vmla */, ARM::VMLAv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13430 { 2723 /* vmla */, ARM::VMLAv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13431 { 2723 /* vmla */, ARM::VMLAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13432 { 2723 /* vmla */, ARM::VMLAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13433 { 2723 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13434 { 2723 /* vmla */, ARM::MVE_VMLA_qr_i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13435 { 2723 /* vmla */, ARM::MVE_VMLA_qr_i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13436 { 2723 /* vmla */, ARM::MVE_VMLA_qr_i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13437 { 2723 /* vmla */, ARM::VMLAslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13438 { 2723 /* vmla */, ARM::VMLAslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13439 { 2723 /* vmla */, ARM::VMLAslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13440 { 2723 /* vmla */, ARM::VMLAslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13441 { 2723 /* vmla */, ARM::VMLAslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13442 { 2723 /* vmla */, ARM::VMLAslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13443 { 2723 /* vmla */, ARM::VMLAslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13444 { 2723 /* vmla */, ARM::VMLAslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13445 { 2728 /* vmladav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13446 { 2728 /* vmladav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13447 { 2728 /* vmladav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13448 { 2728 /* vmladav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13449 { 2728 /* vmladav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13450 { 2728 /* vmladav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13451 { 2736 /* vmladava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13452 { 2736 /* vmladava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13453 { 2736 /* vmladava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13454 { 2736 /* vmladava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13455 { 2736 /* vmladava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13456 { 2736 /* vmladava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13457 { 2745 /* vmladavax */, ARM::MVE_VMLADAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13458 { 2745 /* vmladavax */, ARM::MVE_VMLADAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13459 { 2745 /* vmladavax */, ARM::MVE_VMLADAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13460 { 2755 /* vmladavx */, ARM::MVE_VMLADAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13461 { 2755 /* vmladavx */, ARM::MVE_VMLADAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13462 { 2755 /* vmladavx */, ARM::MVE_VMLADAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13463 { 2764 /* vmlal */, ARM::VMLALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13464 { 2764 /* vmlal */, ARM::VMLALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13465 { 2764 /* vmlal */, ARM::VMLALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13466 { 2764 /* vmlal */, ARM::VMLALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13467 { 2764 /* vmlal */, ARM::VMLALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13468 { 2764 /* vmlal */, ARM::VMLALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13469 { 2764 /* vmlal */, ARM::VMLALslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13470 { 2764 /* vmlal */, ARM::VMLALslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13471 { 2764 /* vmlal */, ARM::VMLALsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13472 { 2764 /* vmlal */, ARM::VMLALsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13473 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13474 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13475 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13476 { 2770 /* vmlaldav */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13477 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13478 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13479 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13480 { 2779 /* vmlaldava */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13481 { 2789 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13482 { 2789 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13483 { 2800 /* vmlaldavx */, ARM::MVE_VMLALDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13484 { 2800 /* vmlaldavx */, ARM::MVE_VMLALDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13485 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13486 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13487 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13488 { 2810 /* vmlalv */, ARM::MVE_VMLALDAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13489 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVas16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13490 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13491 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVau16, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13492 { 2817 /* vmlalva */, ARM::MVE_VMLALDAVau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13493 { 2825 /* vmlas */, ARM::MVE_VMLAS_qr_i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13494 { 2825 /* vmlas */, ARM::MVE_VMLAS_qr_i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13495 { 2825 /* vmlas */, ARM::MVE_VMLAS_qr_i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13496 { 2831 /* vmlav */, ARM::MVE_VMLADAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13497 { 2831 /* vmlav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13498 { 2831 /* vmlav */, ARM::MVE_VMLADAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13499 { 2831 /* vmlav */, ARM::MVE_VMLADAVu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13500 { 2831 /* vmlav */, ARM::MVE_VMLADAVu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13501 { 2831 /* vmlav */, ARM::MVE_VMLADAVu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13502 { 2837 /* vmlava */, ARM::MVE_VMLADAVas16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13503 { 2837 /* vmlava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13504 { 2837 /* vmlava */, ARM::MVE_VMLADAVas8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13505 { 2837 /* vmlava */, ARM::MVE_VMLADAVau16, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13506 { 2837 /* vmlava */, ARM::MVE_VMLADAVau32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13507 { 2837 /* vmlava */, ARM::MVE_VMLADAVau8, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13508 { 2844 /* vmls */, ARM::VMLSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13509 { 2844 /* vmls */, ARM::VMLSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13510 { 2844 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13511 { 2844 /* vmls */, ARM::VMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13512 { 2844 /* vmls */, ARM::VMLSv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13513 { 2844 /* vmls */, ARM::VMLSv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13514 { 2844 /* vmls */, ARM::VMLSv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13515 { 2844 /* vmls */, ARM::VMLSv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13516 { 2844 /* vmls */, ARM::VMLSv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13517 { 2844 /* vmls */, ARM::VMLSv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13518 { 2844 /* vmls */, ARM::VMLShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13519 { 2844 /* vmls */, ARM::VMLShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13520 { 2844 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13521 { 2844 /* vmls */, ARM::VMLSslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13522 { 2844 /* vmls */, ARM::VMLSslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13523 { 2844 /* vmls */, ARM::VMLSslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13524 { 2844 /* vmls */, ARM::VMLSslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13525 { 2844 /* vmls */, ARM::VMLSslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13526 { 2844 /* vmls */, ARM::VMLSslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13527 { 2844 /* vmls */, ARM::VMLSslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13528 { 2844 /* vmls */, ARM::VMLSslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13529 { 2849 /* vmlsdav */, ARM::MVE_VMLSDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13530 { 2849 /* vmlsdav */, ARM::MVE_VMLSDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13531 { 2849 /* vmlsdav */, ARM::MVE_VMLSDAVs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13532 { 2857 /* vmlsdava */, ARM::MVE_VMLSDAVas16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13533 { 2857 /* vmlsdava */, ARM::MVE_VMLSDAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13534 { 2857 /* vmlsdava */, ARM::MVE_VMLSDAVas8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13535 { 2866 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13536 { 2866 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13537 { 2866 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13538 { 2876 /* vmlsdavx */, ARM::MVE_VMLSDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13539 { 2876 /* vmlsdavx */, ARM::MVE_VMLSDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13540 { 2876 /* vmlsdavx */, ARM::MVE_VMLSDAVxs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13541 { 2885 /* vmlsl */, ARM::VMLSLsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13542 { 2885 /* vmlsl */, ARM::VMLSLsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13543 { 2885 /* vmlsl */, ARM::VMLSLsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13544 { 2885 /* vmlsl */, ARM::VMLSLuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13545 { 2885 /* vmlsl */, ARM::VMLSLuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13546 { 2885 /* vmlsl */, ARM::VMLSLuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13547 { 2885 /* vmlsl */, ARM::VMLSLslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13548 { 2885 /* vmlsl */, ARM::VMLSLslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13549 { 2885 /* vmlsl */, ARM::VMLSLsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13550 { 2885 /* vmlsl */, ARM::VMLSLsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13551 { 2891 /* vmlsldav */, ARM::MVE_VMLSLDAVs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13552 { 2891 /* vmlsldav */, ARM::MVE_VMLSLDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13553 { 2900 /* vmlsldava */, ARM::MVE_VMLSLDAVas16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13554 { 2900 /* vmlsldava */, ARM::MVE_VMLSLDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13555 { 2910 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13556 { 2910 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13557 { 2921 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs16, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13558 { 2921 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13559 { 2931 /* vmmla */, ARM::VMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasBF16_HasNEON, { MCK__DOT_bf16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13560 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_HPR }, },
13561 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
13562 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
13563 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_GPR }, },
13564 { 2937 /* vmov */, ARM::VMOVS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
13565 { 2937 /* vmov */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, },
13566 { 2937 /* vmov */, ARM::VMOVv4f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_FPImm }, },
13567 { 2937 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_NEONi32vmov }, },
13568 { 2937 /* vmov */, ARM::VMOVv2f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_FPImm }, },
13569 { 2937 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_NEONi32vmov }, },
13570 { 2937 /* vmov */, ARM::VMOVS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13571 { 2937 /* vmov */, ARM::FCONSTS, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_FPImm }, },
13572 { 2937 /* vmov */, ARM::VMOVD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs64, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13573 { 2937 /* vmov */, ARM::FCONSTD, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_FPImm }, },
13574 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16vmovi8Replicate }, },
13575 { 2937 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
13576 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16vmovi8Replicate }, },
13577 { 2937 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
13578 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi8Replicate }, },
13579 { 2937 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, },
13580 { 2937 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, },
13581 { 2937 /* vmov */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, },
13582 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi8Replicate }, },
13583 { 2937 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, },
13584 { 2937 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, },
13585 { 2937 /* vmov */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, },
13586 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi8Replicate }, },
13587 { 2937 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, },
13588 { 2937 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, },
13589 { 2937 /* vmov */, ARM::VMOVv2i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64splat }, },
13590 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi8Replicate }, },
13591 { 2937 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, },
13592 { 2937 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, },
13593 { 2937 /* vmov */, ARM::VMOVv1i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64splat }, },
13594 { 2937 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_NEONi8splat }, },
13595 { 2937 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_NEONi8splat }, },
13596 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_GPR, MCK_HPR }, },
13597 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
13598 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
13599 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_GPR }, },
13600 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_HPR }, },
13601 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
13602 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
13603 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_GPR }, },
13604 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
13605 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
13606 { 2937 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_GPR, MCK_HPR }, },
13607 { 2937 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
13608 { 2937 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
13609 { 2937 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_HPR, MCK_GPR }, },
13610 { 2937 /* vmov */, ARM::VMOVRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_rGPR, MCK_HPR }, },
13611 { 2937 /* vmov */, ARM::VMOVHR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_rGPR }, },
13612 { 2937 /* vmov */, ARM::FCONSTH, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_FPImm }, },
13613 { 2937 /* vmov */, ARM::VMOVRRD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_DPR }, },
13614 { 2937 /* vmov */, ARM::VGETLNi32, Convert__Reg1_1__Reg1_2__VectorIndex321_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, },
13615 { 2937 /* vmov */, ARM::VMOVDRR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_GPR, MCK_GPR }, },
13616 { 2937 /* vmov */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_3__VectorIndex321_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, },
13617 { 2937 /* vmov */, ARM::MVE_VMOVimmf32, Convert__Reg1_2__FPImm1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_FPImm }, },
13618 { 2937 /* vmov */, ARM::MVE_VMOVimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
13619 { 2937 /* vmov */, ARM::MVE_VMOVimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, },
13620 { 2937 /* vmov */, ARM::MVE_VMOVimmi64, Convert__Reg1_2__NEONi64splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i64, MCK_MQPR, MCK_NEONi64splat }, },
13621 { 2937 /* vmov */, ARM::MVE_VMOVimmi8, Convert__Reg1_2__NEONi8splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_NEONi8splat }, },
13622 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_s16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, },
13623 { 2937 /* vmov */, ARM::VGETLNs16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, },
13624 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_s8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_s8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, },
13625 { 2937 /* vmov */, ARM::VGETLNs8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, },
13626 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_u16, Convert__Reg1_2__Reg1_3__MVEVectorIndex81_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u16, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex8 }, },
13627 { 2937 /* vmov */, ARM::VGETLNu16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, },
13628 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_u8, Convert__Reg1_2__Reg1_3__MVEVectorIndex161_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_u8, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex16 }, },
13629 { 2937 /* vmov */, ARM::VGETLNu8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, },
13630 { 2937 /* vmov */, ARM::VMOVRRD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_GPR, MCK_GPR, MCK_DPR }, },
13631 { 2937 /* vmov */, ARM::VMOVDRR, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_GPR, MCK_GPR }, },
13632 { 2937 /* vmov */, ARM::MVE_VMOV_to_lane_16, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex81_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_16, MCK_MQPR, MCK_MVEVectorIndex8, MCK_rGPR }, },
13633 { 2937 /* vmov */, ARM::VSETLNi16, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_VectorIndex16, MCK_GPR }, },
13634 { 2937 /* vmov */, ARM::MVE_VMOV_to_lane_32, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex41_3__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_MQPR, MCK_MVEVectorIndex4, MCK_rGPR }, },
13635 { 2937 /* vmov */, ARM::MVE_VMOV_from_lane_32, Convert__Reg1_2__Reg1_3__MVEVectorIndex41_4__CondCode2_0, AMFBS_HasFPRegsV8_1M, { MCK_CondCode, MCK__DOT_32, MCK_rGPR, MCK_MQPR, MCK_MVEVectorIndex4 }, },
13636 { 2937 /* vmov */, ARM::VGETLNi32, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, },
13637 { 2937 /* vmov */, ARM::VSETLNi32, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, },
13638 { 2937 /* vmov */, ARM::MVE_VMOV_to_lane_8, Convert__Reg1_2__Tie0_1_1__Reg1_4__MVEVectorIndex161_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK__DOT_8, MCK_MQPR, MCK_MVEVectorIndex16, MCK_rGPR }, },
13639 { 2937 /* vmov */, ARM::VSETLNi8, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VectorIndex8, MCK_GPR }, },
13640 { 2937 /* vmov */, ARM::VMOVRRS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_HPR, MCK_HPR }, },
13641 { 2937 /* vmov */, ARM::VMOVSRR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_GPR, MCK_GPR }, },
13642 { 2937 /* vmov */, ARM::MVE_VMOV_q_rr, Convert__Reg1_1__Tie0_2_4__Reg1_5__Reg1_6__MVEPairVectorIndex21_2__MVEPairVectorIndex01_4__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0, MCK_rGPR, MCK_rGPR }, },
13643 { 2937 /* vmov */, ARM::MVE_VMOV_rr_q, ConvertCustom_cvtMVEVMOVQtoDReg, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MQPR, MCK_MVEPairVectorIndex2, MCK_MQPR, MCK_MVEPairVectorIndex0 }, },
13644 { 2942 /* vmovl */, ARM::VMOVLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
13645 { 2942 /* vmovl */, ARM::VMOVLsv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
13646 { 2942 /* vmovl */, ARM::VMOVLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
13647 { 2942 /* vmovl */, ARM::VMOVLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
13648 { 2942 /* vmovl */, ARM::VMOVLuv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
13649 { 2942 /* vmovl */, ARM::VMOVLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
13650 { 2948 /* vmovlb */, ARM::MVE_VMOVLs16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13651 { 2948 /* vmovlb */, ARM::MVE_VMOVLs8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13652 { 2948 /* vmovlb */, ARM::MVE_VMOVLu16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
13653 { 2948 /* vmovlb */, ARM::MVE_VMOVLu8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, },
13654 { 2955 /* vmovlt */, ARM::MVE_VMOVLs16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13655 { 2955 /* vmovlt */, ARM::MVE_VMOVLs8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13656 { 2955 /* vmovlt */, ARM::MVE_VMOVLu16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
13657 { 2955 /* vmovlt */, ARM::MVE_VMOVLu8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, },
13658 { 2962 /* vmovn */, ARM::VMOVNv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR }, },
13659 { 2962 /* vmovn */, ARM::VMOVNv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR }, },
13660 { 2962 /* vmovn */, ARM::VMOVNv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR }, },
13661 { 2968 /* vmovnb */, ARM::MVE_VMOVNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
13662 { 2968 /* vmovnb */, ARM::MVE_VMOVNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
13663 { 2975 /* vmovnt */, ARM::MVE_VMOVNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
13664 { 2975 /* vmovnt */, ARM::MVE_VMOVNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
13665 { 2982 /* vmovx */, ARM::VMOVH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13666 { 2988 /* vmrs */, ARM::FMSTAT, Convert__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_APSR_NZCV, MCK_FPSCR }, },
13667 { 2988 /* vmrs */, ARM::VMRS_FPEXC, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPEXC }, },
13668 { 2988 /* vmrs */, ARM::VMRS_FPINST, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST }, },
13669 { 2988 /* vmrs */, ARM::VMRS_FPINST2, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST2 }, },
13670 { 2988 /* vmrs */, ARM::VMRS, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPRnopc, MCK_FPSCR }, },
13671 { 2988 /* vmrs */, ARM::VMRS_FPSID, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPSID }, },
13672 { 2988 /* vmrs */, ARM::VMRS_MVFR0, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR0 }, },
13673 { 2988 /* vmrs */, ARM::VMRS_MVFR1, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR1 }, },
13674 { 2988 /* vmrs */, ARM::VMRS_MVFR2, Convert__Reg1_1__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR2 }, },
13675 { 2988 /* vmrs */, ARM::VMRS_FPCXTNS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTRegs }, },
13676 { 2988 /* vmrs */, ARM::VMRS_FPCXTS, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_GPR, MCK_FPCXTS }, },
13677 { 2988 /* vmrs */, ARM::VMRS_FPSCR_NZCVQC, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_FPSCR_NZCVQC }, },
13678 { 2988 /* vmrs */, ARM::VMRS_P0, Convert__Reg1_1__imm_95_0__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_P0 }, },
13679 { 2988 /* vmrs */, ARM::VMRS_VPR, Convert__Reg1_1__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_GPR, MCK_VCCR }, },
13680 { 2993 /* vmsr */, ARM::VMSR_FPCXTNS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_GPR }, },
13681 { 2993 /* vmsr */, ARM::VMSR_FPCXTS, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_GPR }, },
13682 { 2993 /* vmsr */, ARM::VMSR_FPEXC, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPEXC, MCK_GPRnopc }, },
13683 { 2993 /* vmsr */, ARM::VMSR_FPINST, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST, MCK_GPRnopc }, },
13684 { 2993 /* vmsr */, ARM::VMSR_FPINST2, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPINST2, MCK_GPRnopc }, },
13685 { 2993 /* vmsr */, ARM::VMSR, Convert__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_FPSCR, MCK_GPRnopc }, },
13686 { 2993 /* vmsr */, ARM::VMSR_FPSCR_NZCVQC, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasFPRegs, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_GPR }, },
13687 { 2993 /* vmsr */, ARM::VMSR_FPSID, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_FPSID, MCK_GPRnopc }, },
13688 { 2993 /* vmsr */, ARM::VMSR_P0, Convert__imm_95_0__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_GPR }, },
13689 { 2993 /* vmsr */, ARM::VMSR_VPR, Convert__Reg1_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_GPR }, },
13690 { 2998 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13691 { 2998 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13692 { 2998 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13693 { 2998 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13694 { 2998 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
13695 { 2998 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
13696 { 2998 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
13697 { 2998 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
13698 { 2998 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
13699 { 2998 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
13700 { 2998 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR }, },
13701 { 2998 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR }, },
13702 { 2998 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13703 { 2998 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13704 { 2998 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13705 { 2998 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13706 { 2998 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13707 { 2998 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13708 { 2998 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13709 { 2998 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13710 { 2998 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13711 { 2998 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13712 { 2998 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13713 { 2998 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13714 { 2998 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13715 { 2998 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13716 { 2998 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13717 { 2998 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13718 { 2998 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13719 { 2998 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13720 { 2998 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13721 { 2998 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13722 { 2998 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13723 { 2998 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13724 { 2998 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13725 { 2998 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13726 { 2998 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13727 { 2998 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13728 { 2998 /* vmul */, ARM::MVE_VMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13729 { 2998 /* vmul */, ARM::MVE_VMUL_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13730 { 2998 /* vmul */, ARM::MVE_VMULi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13731 { 2998 /* vmul */, ARM::MVE_VMUL_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13732 { 2998 /* vmul */, ARM::MVE_VMULi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13733 { 2998 /* vmul */, ARM::MVE_VMUL_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13734 { 2998 /* vmul */, ARM::MVE_VMULi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13735 { 2998 /* vmul */, ARM::MVE_VMUL_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13736 { 2998 /* vmul */, ARM::MVE_VMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13737 { 2998 /* vmul */, ARM::MVE_VMUL_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13738 { 2998 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13739 { 2998 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13740 { 2998 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13741 { 2998 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13742 { 2998 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13743 { 2998 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13744 { 2998 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13745 { 2998 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13746 { 3003 /* vmulh */, ARM::MVE_VMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13747 { 3003 /* vmulh */, ARM::MVE_VMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13748 { 3003 /* vmulh */, ARM::MVE_VMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13749 { 3003 /* vmulh */, ARM::MVE_VMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13750 { 3003 /* vmulh */, ARM::MVE_VMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13751 { 3003 /* vmulh */, ARM::MVE_VMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13752 { 3009 /* vmull */, ARM::VMULLp64, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasV8_HasAES, { MCK__DOT_p64, MCK_QPR, MCK_DPR, MCK_DPR }, },
13753 { 3009 /* vmull */, ARM::VMULLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13754 { 3009 /* vmull */, ARM::VMULLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13755 { 3009 /* vmull */, ARM::VMULLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13756 { 3009 /* vmull */, ARM::VMULLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
13757 { 3009 /* vmull */, ARM::VMULLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13758 { 3009 /* vmull */, ARM::VMULLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13759 { 3009 /* vmull */, ARM::VMULLp8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_DPR, MCK_DPR }, },
13760 { 3009 /* vmull */, ARM::VMULLslsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13761 { 3009 /* vmull */, ARM::VMULLslsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13762 { 3009 /* vmull */, ARM::VMULLsluv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
13763 { 3009 /* vmull */, ARM::VMULLsluv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13764 { 3015 /* vmullb */, ARM::MVE_VMULLBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13765 { 3015 /* vmullb */, ARM::MVE_VMULLBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13766 { 3015 /* vmullb */, ARM::MVE_VMULLBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13767 { 3015 /* vmullb */, ARM::MVE_VMULLBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13768 { 3015 /* vmullb */, ARM::MVE_VMULLBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13769 { 3015 /* vmullb */, ARM::MVE_VMULLBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13770 { 3015 /* vmullb */, ARM::MVE_VMULLBp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13771 { 3015 /* vmullb */, ARM::MVE_VMULLBp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13772 { 3022 /* vmullt */, ARM::MVE_VMULLTs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13773 { 3022 /* vmullt */, ARM::MVE_VMULLTs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13774 { 3022 /* vmullt */, ARM::MVE_VMULLTs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13775 { 3022 /* vmullt */, ARM::MVE_VMULLTu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13776 { 3022 /* vmullt */, ARM::MVE_VMULLTu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13777 { 3022 /* vmullt */, ARM::MVE_VMULLTu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13778 { 3022 /* vmullt */, ARM::MVE_VMULLTp16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13779 { 3022 /* vmullt */, ARM::MVE_VMULLTp8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13780 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
13781 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
13782 { 3029 /* vmvn */, ARM::MVE_VMVN, Convert__Reg1_1__Reg1_2__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, },
13783 { 3029 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16invi8Replicate }, },
13784 { 3029 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
13785 { 3029 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16invi8Replicate }, },
13786 { 3029 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
13787 { 3029 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32invi8Replicate }, },
13788 { 3029 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, },
13789 { 3029 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, },
13790 { 3029 /* vmvn */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, },
13791 { 3029 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32invi8Replicate }, },
13792 { 3029 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, },
13793 { 3029 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, },
13794 { 3029 /* vmvn */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, },
13795 { 3029 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64invi8Replicate }, },
13796 { 3029 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, },
13797 { 3029 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, },
13798 { 3029 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64invi8Replicate }, },
13799 { 3029 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, },
13800 { 3029 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, },
13801 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
13802 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
13803 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
13804 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
13805 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
13806 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
13807 { 3029 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
13808 { 3029 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
13809 { 3029 /* vmvn */, ARM::MVE_VMVNimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
13810 { 3029 /* vmvn */, ARM::MVE_VMVNimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, },
13811 { 3034 /* vneg */, ARM::VNEGs16q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13812 { 3034 /* vneg */, ARM::VNEGs16d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13813 { 3034 /* vneg */, ARM::VNEGs32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13814 { 3034 /* vneg */, ARM::VNEGs32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13815 { 3034 /* vneg */, ARM::VNEGs8q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13816 { 3034 /* vneg */, ARM::VNEGs8d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13817 { 3034 /* vneg */, ARM::VNEGf32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
13818 { 3034 /* vneg */, ARM::VNEGfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13819 { 3034 /* vneg */, ARM::VNEGS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13820 { 3034 /* vneg */, ARM::VNEGD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13821 { 3034 /* vneg */, ARM::VNEGhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
13822 { 3034 /* vneg */, ARM::VNEGhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13823 { 3034 /* vneg */, ARM::VNEGH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13824 { 3034 /* vneg */, ARM::MVE_VNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13825 { 3034 /* vneg */, ARM::MVE_VNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13826 { 3034 /* vneg */, ARM::MVE_VNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13827 { 3034 /* vneg */, ARM::MVE_VNEGf32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13828 { 3034 /* vneg */, ARM::MVE_VNEGf16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13829 { 3039 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13830 { 3039 /* vnmla */, ARM::VNMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13831 { 3039 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13832 { 3045 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13833 { 3045 /* vnmls */, ARM::VNMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13834 { 3045 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13835 { 3051 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13836 { 3051 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
13837 { 3051 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13838 { 3051 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13839 { 3051 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13840 { 3051 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13841 { 3057 /* vorn */, ARM::VORNq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
13842 { 3057 /* vorn */, ARM::VORNd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
13843 { 3057 /* vorn */, ARM::MVE_VORRimmi16, Convert__Reg1_2__Tie0_3_3__NEONi16splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splatNot }, },
13844 { 3057 /* vorn */, ARM::MVE_VORRimmi32, Convert__Reg1_2__Tie0_3_3__NEONi32splatNot1_3__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splatNot }, },
13845 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13846 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13847 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13848 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13849 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13850 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13851 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13852 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13853 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13854 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13855 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13856 { 3057 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13857 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
13858 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
13859 { 3062 /* vorr */, ARM::VORRiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, },
13860 { 3062 /* vorr */, ARM::VORRiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, },
13861 { 3062 /* vorr */, ARM::VORRiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, },
13862 { 3062 /* vorr */, ARM::VORRiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, },
13863 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
13864 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
13865 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
13866 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
13867 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
13868 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
13869 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
13870 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
13871 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
13872 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
13873 { 3062 /* vorr */, ARM::MVE_VORRimmi16, Convert__Reg1_2__Tie0_1_1__NEONi16splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
13874 { 3062 /* vorr */, ARM::MVE_VORRimmi32, Convert__Reg1_2__Tie0_1_1__NEONi32splat1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32splat }, },
13875 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13876 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
13877 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13878 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13879 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13880 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
13881 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
13882 { 3062 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
13883 { 3062 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13884 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13885 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13886 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13887 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13888 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13889 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13890 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13891 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13892 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13893 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13894 { 3062 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13895 { 3067 /* vpadal */, ARM::VPADALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13896 { 3067 /* vpadal */, ARM::VPADALsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13897 { 3067 /* vpadal */, ARM::VPADALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13898 { 3067 /* vpadal */, ARM::VPADALsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13899 { 3067 /* vpadal */, ARM::VPADALsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13900 { 3067 /* vpadal */, ARM::VPADALsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13901 { 3067 /* vpadal */, ARM::VPADALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13902 { 3067 /* vpadal */, ARM::VPADALuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13903 { 3067 /* vpadal */, ARM::VPADALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13904 { 3067 /* vpadal */, ARM::VPADALuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13905 { 3067 /* vpadal */, ARM::VPADALuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13906 { 3067 /* vpadal */, ARM::VPADALuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13907 { 3074 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13908 { 3074 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
13909 { 3074 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
13910 { 3074 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
13911 { 3074 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13912 { 3074 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13913 { 3074 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13914 { 3074 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13915 { 3074 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13916 { 3074 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13917 { 3080 /* vpaddl */, ARM::VPADDLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
13918 { 3080 /* vpaddl */, ARM::VPADDLsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13919 { 3080 /* vpaddl */, ARM::VPADDLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13920 { 3080 /* vpaddl */, ARM::VPADDLsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13921 { 3080 /* vpaddl */, ARM::VPADDLsv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
13922 { 3080 /* vpaddl */, ARM::VPADDLsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13923 { 3080 /* vpaddl */, ARM::VPADDLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
13924 { 3080 /* vpaddl */, ARM::VPADDLuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13925 { 3080 /* vpaddl */, ARM::VPADDLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
13926 { 3080 /* vpaddl */, ARM::VPADDLuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13927 { 3080 /* vpaddl */, ARM::VPADDLuv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
13928 { 3080 /* vpaddl */, ARM::VPADDLuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13929 { 3087 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13930 { 3087 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13931 { 3087 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13932 { 3087 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13933 { 3087 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13934 { 3087 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13935 { 3087 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13936 { 3087 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13937 { 3087 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13938 { 3087 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13939 { 3087 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13940 { 3087 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13941 { 3087 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13942 { 3087 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13943 { 3087 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13944 { 3087 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13945 { 3093 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
13946 { 3093 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13947 { 3093 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
13948 { 3093 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
13949 { 3093 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
13950 { 3093 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
13951 { 3093 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
13952 { 3093 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
13953 { 3093 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13954 { 3093 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13955 { 3093 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13956 { 3093 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13957 { 3093 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13958 { 3093 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
13959 { 3093 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13960 { 3093 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
13961 { 3099 /* vpnot */, ARM::MVE_VPNOT, Convert__imm_95_0__imm_95_0__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN }, },
13962 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, },
13963 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, },
13964 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, },
13965 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, },
13966 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, },
13967 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, },
13968 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, },
13969 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, },
13970 { 3105 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, },
13971 { 3105 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, },
13972 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13973 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13974 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13975 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13976 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13977 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13978 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13979 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13980 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13981 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13982 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13983 { 3110 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13984 { 3116 /* vpst */, ARM::MVE_VPST, Convert__ITMask1_0, AMFBS_HasMVEInt, { MCK_ITMask }, },
13985 { 3121 /* vpt */, ARM::MVE_VPTv8s16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
13986 { 3121 /* vpt */, ARM::MVE_VPTv8s16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
13987 { 3121 /* vpt */, ARM::MVE_VPTv4s32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
13988 { 3121 /* vpt */, ARM::MVE_VPTv4s32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
13989 { 3121 /* vpt */, ARM::MVE_VPTv16s8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
13990 { 3121 /* vpt */, ARM::MVE_VPTv16s8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
13991 { 3121 /* vpt */, ARM::MVE_VPTv8u16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
13992 { 3121 /* vpt */, ARM::MVE_VPTv8u16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
13993 { 3121 /* vpt */, ARM::MVE_VPTv4u32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
13994 { 3121 /* vpt */, ARM::MVE_VPTv4u32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
13995 { 3121 /* vpt */, ARM::MVE_VPTv16u8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_MQPR }, },
13996 { 3121 /* vpt */, ARM::MVE_VPTv16u8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, },
13997 { 3121 /* vpt */, ARM::MVE_VPTv4f32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
13998 { 3121 /* vpt */, ARM::MVE_VPTv4f32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
13999 { 3121 /* vpt */, ARM::MVE_VPTv8i16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
14000 { 3121 /* vpt */, ARM::MVE_VPTv8i16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
14001 { 3121 /* vpt */, ARM::MVE_VPTv4i32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
14002 { 3121 /* vpt */, ARM::MVE_VPTv4i32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
14003 { 3121 /* vpt */, ARM::MVE_VPTv16i8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_MQPR }, },
14004 { 3121 /* vpt */, ARM::MVE_VPTv16i8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, },
14005 { 3121 /* vpt */, ARM::MVE_VPTv8f16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_MQPR }, },
14006 { 3121 /* vpt */, ARM::MVE_VPTv8f16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },
14007 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPRRegList }, },
14008 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, AMFBS_HasFPRegs, { MCK_CondCode, MCK_SPRRegList }, },
14009 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, },
14010 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, },
14011 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, },
14012 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, },
14013 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, },
14014 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, },
14015 { 3125 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, },
14016 { 3125 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, },
14017 { 3131 /* vqabs */, ARM::VQABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14018 { 3131 /* vqabs */, ARM::VQABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14019 { 3131 /* vqabs */, ARM::VQABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14020 { 3131 /* vqabs */, ARM::VQABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14021 { 3131 /* vqabs */, ARM::VQABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14022 { 3131 /* vqabs */, ARM::VQABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14023 { 3131 /* vqabs */, ARM::MVE_VQABSs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14024 { 3131 /* vqabs */, ARM::MVE_VQABSs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14025 { 3131 /* vqabs */, ARM::MVE_VQABSs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
14026 { 3137 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14027 { 3137 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14028 { 3137 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14029 { 3137 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14030 { 3137 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14031 { 3137 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14032 { 3137 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14033 { 3137 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14034 { 3137 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14035 { 3137 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14036 { 3137 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14037 { 3137 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14038 { 3137 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14039 { 3137 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14040 { 3137 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14041 { 3137 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14042 { 3137 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14043 { 3137 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14044 { 3137 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14045 { 3137 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14046 { 3137 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14047 { 3137 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14048 { 3137 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14049 { 3137 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14050 { 3137 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14051 { 3137 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14052 { 3137 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14053 { 3137 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14054 { 3137 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14055 { 3137 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14056 { 3137 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14057 { 3137 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14058 { 3137 /* vqadd */, ARM::MVE_VQADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14059 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14060 { 3137 /* vqadd */, ARM::MVE_VQADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14061 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14062 { 3137 /* vqadd */, ARM::MVE_VQADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14063 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14064 { 3137 /* vqadd */, ARM::MVE_VQADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14065 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14066 { 3137 /* vqadd */, ARM::MVE_VQADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14067 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14068 { 3137 /* vqadd */, ARM::MVE_VQADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14069 { 3137 /* vqadd */, ARM::MVE_VQADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14070 { 3143 /* vqdmladh */, ARM::MVE_VQDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14071 { 3143 /* vqdmladh */, ARM::MVE_VQDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14072 { 3143 /* vqdmladh */, ARM::MVE_VQDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14073 { 3152 /* vqdmladhx */, ARM::MVE_VQDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14074 { 3152 /* vqdmladhx */, ARM::MVE_VQDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14075 { 3152 /* vqdmladhx */, ARM::MVE_VQDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14076 { 3162 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14077 { 3162 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14078 { 3162 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14079 { 3170 /* vqdmlal */, ARM::VQDMLALv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
14080 { 3170 /* vqdmlal */, ARM::VQDMLALv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
14081 { 3170 /* vqdmlal */, ARM::VQDMLALslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14082 { 3170 /* vqdmlal */, ARM::VQDMLALslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14083 { 3178 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14084 { 3178 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14085 { 3178 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14086 { 3187 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14087 { 3187 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14088 { 3187 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14089 { 3196 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14090 { 3196 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14091 { 3196 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14092 { 3206 /* vqdmlsl */, ARM::VQDMLSLv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
14093 { 3206 /* vqdmlsl */, ARM::VQDMLSLv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
14094 { 3206 /* vqdmlsl */, ARM::VQDMLSLslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14095 { 3206 /* vqdmlsl */, ARM::VQDMLSLslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14096 { 3214 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14097 { 3214 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14098 { 3214 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14099 { 3214 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14100 { 3214 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14101 { 3214 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14102 { 3214 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14103 { 3214 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14104 { 3214 /* vqdmulh */, ARM::MVE_VQDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14105 { 3214 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14106 { 3214 /* vqdmulh */, ARM::MVE_VQDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14107 { 3214 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14108 { 3214 /* vqdmulh */, ARM::MVE_VQDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14109 { 3214 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14110 { 3214 /* vqdmulh */, ARM::VQDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14111 { 3214 /* vqdmulh */, ARM::VQDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14112 { 3214 /* vqdmulh */, ARM::VQDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14113 { 3214 /* vqdmulh */, ARM::VQDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14114 { 3222 /* vqdmull */, ARM::VQDMULLv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
14115 { 3222 /* vqdmull */, ARM::VQDMULLv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
14116 { 3222 /* vqdmull */, ARM::VQDMULLslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14117 { 3222 /* vqdmull */, ARM::VQDMULLslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14118 { 3230 /* vqdmullb */, ARM::MVE_VQDMULLs16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14119 { 3230 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14120 { 3230 /* vqdmullb */, ARM::MVE_VQDMULLs32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14121 { 3230 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14122 { 3239 /* vqdmullt */, ARM::MVE_VQDMULLs16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14123 { 3239 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14124 { 3239 /* vqdmullt */, ARM::MVE_VQDMULLs32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14125 { 3239 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14126 { 3248 /* vqmovn */, ARM::VQMOVNsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, },
14127 { 3248 /* vqmovn */, ARM::VQMOVNsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
14128 { 3248 /* vqmovn */, ARM::VQMOVNsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, },
14129 { 3248 /* vqmovn */, ARM::VQMOVNuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR }, },
14130 { 3248 /* vqmovn */, ARM::VQMOVNuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR }, },
14131 { 3248 /* vqmovn */, ARM::VQMOVNuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR }, },
14132 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14133 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14134 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNu16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
14135 { 3255 /* vqmovnb */, ARM::MVE_VQMOVNu32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
14136 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14137 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14138 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNu16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
14139 { 3263 /* vqmovnt */, ARM::MVE_VQMOVNu32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
14140 { 3271 /* vqmovun */, ARM::VQMOVNsuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, },
14141 { 3271 /* vqmovun */, ARM::VQMOVNsuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
14142 { 3271 /* vqmovun */, ARM::VQMOVNsuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, },
14143 { 3279 /* vqmovunb */, ARM::MVE_VQMOVUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14144 { 3279 /* vqmovunb */, ARM::MVE_VQMOVUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14145 { 3288 /* vqmovunt */, ARM::MVE_VQMOVUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14146 { 3288 /* vqmovunt */, ARM::MVE_VQMOVUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14147 { 3297 /* vqneg */, ARM::VQNEGv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14148 { 3297 /* vqneg */, ARM::VQNEGv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14149 { 3297 /* vqneg */, ARM::VQNEGv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14150 { 3297 /* vqneg */, ARM::VQNEGv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14151 { 3297 /* vqneg */, ARM::VQNEGv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14152 { 3297 /* vqneg */, ARM::VQNEGv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14153 { 3297 /* vqneg */, ARM::MVE_VQNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
14154 { 3297 /* vqneg */, ARM::MVE_VQNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
14155 { 3297 /* vqneg */, ARM::MVE_VQNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
14156 { 3303 /* vqrdmladh */, ARM::MVE_VQRDMLADHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14157 { 3303 /* vqrdmladh */, ARM::MVE_VQRDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14158 { 3303 /* vqrdmladh */, ARM::MVE_VQRDMLADHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14159 { 3313 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14160 { 3313 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14161 { 3313 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14162 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14163 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14164 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14165 { 3324 /* vqrdmlah */, ARM::VQRDMLAHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14166 { 3324 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14167 { 3324 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14168 { 3324 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14169 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14170 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14171 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14172 { 3324 /* vqrdmlah */, ARM::VQRDMLAHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14173 { 3333 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14174 { 3333 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14175 { 3333 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14176 { 3343 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14177 { 3343 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14178 { 3343 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14179 { 3353 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14180 { 3353 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14181 { 3353 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14182 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14183 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14184 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14185 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14186 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14187 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14188 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14189 { 3364 /* vqrdmlsh */, ARM::VQRDMLSHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14190 { 3373 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14191 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14192 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14193 { 3373 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14194 { 3373 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14195 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14196 { 3373 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14197 { 3373 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14198 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14199 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14200 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14201 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14202 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14203 { 3373 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14204 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14205 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, },
14206 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14207 { 3373 /* vqrdmulh */, ARM::VQRDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14208 { 3382 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14209 { 3382 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14210 { 3382 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14211 { 3382 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14212 { 3382 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14213 { 3382 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14214 { 3382 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14215 { 3382 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14216 { 3382 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14217 { 3382 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14218 { 3382 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14219 { 3382 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14220 { 3382 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14221 { 3382 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14222 { 3382 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14223 { 3382 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14224 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14225 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14226 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14227 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14228 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14229 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14230 { 3382 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14231 { 3382 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14232 { 3382 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14233 { 3382 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14234 { 3382 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14235 { 3382 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14236 { 3382 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14237 { 3382 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14238 { 3382 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14239 { 3382 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14240 { 3382 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14241 { 3382 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14242 { 3382 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14243 { 3382 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14244 { 3382 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14245 { 3382 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14246 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14247 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14248 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14249 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14250 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14251 { 3382 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14252 { 3389 /* vqrshrn */, ARM::VQRSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14253 { 3389 /* vqrshrn */, ARM::VQRSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14254 { 3389 /* vqrshrn */, ARM::VQRSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14255 { 3389 /* vqrshrn */, ARM::VQRSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14256 { 3389 /* vqrshrn */, ARM::VQRSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14257 { 3389 /* vqrshrn */, ARM::VQRSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14258 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14259 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14260 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14261 { 3397 /* vqrshrnb */, ARM::MVE_VQRSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14262 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14263 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14264 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14265 { 3406 /* vqrshrnt */, ARM::MVE_VQRSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14266 { 3415 /* vqrshrun */, ARM::VQRSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14267 { 3415 /* vqrshrun */, ARM::VQRSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14268 { 3415 /* vqrshrun */, ARM::VQRSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14269 { 3424 /* vqrshrunb */, ARM::MVE_VQRSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14270 { 3424 /* vqrshrunb */, ARM::MVE_VQRSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14271 { 3434 /* vqrshrunt */, ARM::MVE_VQRSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14272 { 3434 /* vqrshrunt */, ARM::MVE_VQRSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14273 { 3444 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14274 { 3444 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, },
14275 { 3444 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14276 { 3444 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, },
14277 { 3444 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14278 { 3444 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
14279 { 3444 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14280 { 3444 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
14281 { 3444 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14282 { 3444 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, },
14283 { 3444 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14284 { 3444 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, },
14285 { 3444 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14286 { 3444 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, },
14287 { 3444 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14288 { 3444 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, },
14289 { 3444 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14290 { 3444 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_Imm }, },
14291 { 3444 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14292 { 3444 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_Imm }, },
14293 { 3444 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14294 { 3444 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_Imm }, },
14295 { 3444 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14296 { 3444 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_Imm }, },
14297 { 3444 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14298 { 3444 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_Imm }, },
14299 { 3444 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14300 { 3444 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_Imm }, },
14301 { 3444 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14302 { 3444 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_Imm }, },
14303 { 3444 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14304 { 3444 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_Imm }, },
14305 { 3444 /* vqshl */, ARM::MVE_VQSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14306 { 3444 /* vqshl */, ARM::MVE_VQSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14307 { 3444 /* vqshl */, ARM::MVE_VQSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14308 { 3444 /* vqshl */, ARM::MVE_VQSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14309 { 3444 /* vqshl */, ARM::MVE_VQSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14310 { 3444 /* vqshl */, ARM::MVE_VQSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14311 { 3444 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14312 { 3444 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14313 { 3444 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14314 { 3444 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14315 { 3444 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14316 { 3444 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14317 { 3444 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14318 { 3444 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14319 { 3444 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14320 { 3444 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14321 { 3444 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14322 { 3444 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14323 { 3444 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14324 { 3444 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14325 { 3444 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14326 { 3444 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14327 { 3444 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14328 { 3444 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14329 { 3444 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14330 { 3444 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14331 { 3444 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14332 { 3444 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14333 { 3444 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14334 { 3444 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14335 { 3444 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14336 { 3444 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14337 { 3444 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14338 { 3444 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14339 { 3444 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14340 { 3444 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14341 { 3444 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14342 { 3444 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14343 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14344 { 3444 /* vqshl */, ARM::MVE_VQSHLimms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14345 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14346 { 3444 /* vqshl */, ARM::MVE_VQSHLimms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14347 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14348 { 3444 /* vqshl */, ARM::MVE_VQSHLimms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14349 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14350 { 3444 /* vqshl */, ARM::MVE_VQSHLimmu16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14351 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14352 { 3444 /* vqshl */, ARM::MVE_VQSHLimmu32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14353 { 3444 /* vqshl */, ARM::MVE_VQSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14354 { 3444 /* vqshl */, ARM::MVE_VQSHLimmu8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14355 { 3450 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, },
14356 { 3450 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, },
14357 { 3450 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
14358 { 3450 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
14359 { 3450 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, },
14360 { 3450 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, },
14361 { 3450 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, },
14362 { 3450 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, },
14363 { 3450 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14364 { 3450 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14365 { 3450 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14366 { 3450 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14367 { 3450 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14368 { 3450 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14369 { 3450 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14370 { 3450 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14371 { 3450 /* vqshlu */, ARM::MVE_VQSHLU_imms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14372 { 3450 /* vqshlu */, ARM::MVE_VQSHLU_imms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14373 { 3450 /* vqshlu */, ARM::MVE_VQSHLU_imms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14374 { 3457 /* vqshrn */, ARM::VQSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14375 { 3457 /* vqshrn */, ARM::VQSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14376 { 3457 /* vqshrn */, ARM::VQSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14377 { 3457 /* vqshrn */, ARM::VQSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14378 { 3457 /* vqshrn */, ARM::VQSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14379 { 3457 /* vqshrn */, ARM::VQSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14380 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14381 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14382 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14383 { 3464 /* vqshrnb */, ARM::MVE_VQSHRNbhu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14384 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNths16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14385 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14386 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNthu16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14387 { 3472 /* vqshrnt */, ARM::MVE_VQSHRNthu32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14388 { 3480 /* vqshrun */, ARM::VQSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14389 { 3480 /* vqshrun */, ARM::VQSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14390 { 3480 /* vqshrun */, ARM::VQSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14391 { 3488 /* vqshrunb */, ARM::MVE_VQSHRUNs16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14392 { 3488 /* vqshrunb */, ARM::MVE_VQSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14393 { 3497 /* vqshrunt */, ARM::MVE_VQSHRUNs16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14394 { 3497 /* vqshrunt */, ARM::MVE_VQSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14395 { 3506 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14396 { 3506 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14397 { 3506 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14398 { 3506 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14399 { 3506 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14400 { 3506 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14401 { 3506 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14402 { 3506 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14403 { 3506 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14404 { 3506 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14405 { 3506 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14406 { 3506 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14407 { 3506 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14408 { 3506 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14409 { 3506 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14410 { 3506 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14411 { 3506 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14412 { 3506 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14413 { 3506 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14414 { 3506 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14415 { 3506 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14416 { 3506 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14417 { 3506 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14418 { 3506 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14419 { 3506 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14420 { 3506 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14421 { 3506 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14422 { 3506 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14423 { 3506 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14424 { 3506 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14425 { 3506 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14426 { 3506 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14427 { 3506 /* vqsub */, ARM::MVE_VQSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14428 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14429 { 3506 /* vqsub */, ARM::MVE_VQSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14430 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14431 { 3506 /* vqsub */, ARM::MVE_VQSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14432 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14433 { 3506 /* vqsub */, ARM::MVE_VQSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14434 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14435 { 3506 /* vqsub */, ARM::MVE_VQSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14436 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14437 { 3506 /* vqsub */, ARM::MVE_VQSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14438 { 3506 /* vqsub */, ARM::MVE_VQSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14439 { 3512 /* vraddhn */, ARM::VRADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
14440 { 3512 /* vraddhn */, ARM::VRADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
14441 { 3512 /* vraddhn */, ARM::VRADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
14442 { 3520 /* vrecpe */, ARM::VRECPEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14443 { 3520 /* vrecpe */, ARM::VRECPEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14444 { 3520 /* vrecpe */, ARM::VRECPEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14445 { 3520 /* vrecpe */, ARM::VRECPEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14446 { 3520 /* vrecpe */, ARM::VRECPEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14447 { 3520 /* vrecpe */, ARM::VRECPEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14448 { 3527 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14449 { 3527 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14450 { 3527 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14451 { 3527 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14452 { 3527 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14453 { 3527 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14454 { 3527 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14455 { 3527 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14456 { 3534 /* vrev16 */, ARM::VREV16q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14457 { 3534 /* vrev16 */, ARM::VREV16d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14458 { 3534 /* vrev16 */, ARM::MVE_VREV16_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14459 { 3541 /* vrev32 */, ARM::VREV32q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
14460 { 3541 /* vrev32 */, ARM::VREV32d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
14461 { 3541 /* vrev32 */, ARM::VREV32q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14462 { 3541 /* vrev32 */, ARM::VREV32d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14463 { 3541 /* vrev32 */, ARM::MVE_VREV32_16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, },
14464 { 3541 /* vrev32 */, ARM::MVE_VREV32_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14465 { 3548 /* vrev64 */, ARM::VREV64q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
14466 { 3548 /* vrev64 */, ARM::VREV64d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
14467 { 3548 /* vrev64 */, ARM::VREV64q32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
14468 { 3548 /* vrev64 */, ARM::VREV64d32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
14469 { 3548 /* vrev64 */, ARM::VREV64q8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
14470 { 3548 /* vrev64 */, ARM::VREV64d8, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
14471 { 3548 /* vrev64 */, ARM::MVE_VREV64_16, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, },
14472 { 3548 /* vrev64 */, ARM::MVE_VREV64_32, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR }, },
14473 { 3548 /* vrev64 */, ARM::MVE_VREV64_8, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14474 { 3555 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14475 { 3555 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14476 { 3555 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14477 { 3555 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14478 { 3555 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14479 { 3555 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14480 { 3555 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14481 { 3555 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14482 { 3555 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14483 { 3555 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14484 { 3555 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14485 { 3555 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14486 { 3555 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14487 { 3555 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14488 { 3555 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14489 { 3555 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14490 { 3555 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14491 { 3555 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14492 { 3555 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14493 { 3555 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14494 { 3555 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14495 { 3555 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14496 { 3555 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14497 { 3555 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14498 { 3555 /* vrhadd */, ARM::MVE_VRHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14499 { 3555 /* vrhadd */, ARM::MVE_VRHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14500 { 3555 /* vrhadd */, ARM::MVE_VRHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14501 { 3555 /* vrhadd */, ARM::MVE_VRHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14502 { 3555 /* vrhadd */, ARM::MVE_VRHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14503 { 3555 /* vrhadd */, ARM::MVE_VRHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14504 { 3562 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14505 { 3562 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14506 { 3562 /* vrinta */, ARM::VRINTAS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14507 { 3562 /* vrinta */, ARM::VRINTAD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14508 { 3562 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14509 { 3562 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14510 { 3562 /* vrinta */, ARM::VRINTAH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14511 { 3562 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14512 { 3562 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14513 { 3562 /* vrinta */, ARM::VRINTAS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14514 { 3562 /* vrinta */, ARM::VRINTAD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14515 { 3562 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14516 { 3562 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14517 { 3562 /* vrinta */, ARM::VRINTAH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14518 { 3562 /* vrinta */, ARM::MVE_VRINTf32A, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14519 { 3562 /* vrinta */, ARM::MVE_VRINTf16A, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14520 { 3569 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14521 { 3569 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14522 { 3569 /* vrintm */, ARM::VRINTMS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14523 { 3569 /* vrintm */, ARM::VRINTMD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14524 { 3569 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14525 { 3569 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14526 { 3569 /* vrintm */, ARM::VRINTMH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14527 { 3569 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14528 { 3569 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14529 { 3569 /* vrintm */, ARM::VRINTMS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14530 { 3569 /* vrintm */, ARM::VRINTMD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14531 { 3569 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14532 { 3569 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14533 { 3569 /* vrintm */, ARM::VRINTMH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14534 { 3569 /* vrintm */, ARM::MVE_VRINTf32M, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14535 { 3569 /* vrintm */, ARM::MVE_VRINTf16M, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14536 { 3576 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14537 { 3576 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14538 { 3576 /* vrintn */, ARM::VRINTNS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14539 { 3576 /* vrintn */, ARM::VRINTND, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14540 { 3576 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14541 { 3576 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14542 { 3576 /* vrintn */, ARM::VRINTNH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14543 { 3576 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14544 { 3576 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14545 { 3576 /* vrintn */, ARM::VRINTNS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14546 { 3576 /* vrintn */, ARM::VRINTND, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14547 { 3576 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14548 { 3576 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14549 { 3576 /* vrintn */, ARM::VRINTNH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14550 { 3576 /* vrintn */, ARM::MVE_VRINTf32N, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14551 { 3576 /* vrintn */, ARM::MVE_VRINTf16N, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14552 { 3583 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14553 { 3583 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14554 { 3583 /* vrintp */, ARM::VRINTPS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14555 { 3583 /* vrintp */, ARM::VRINTPD, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14556 { 3583 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14557 { 3583 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14558 { 3583 /* vrintp */, ARM::VRINTPH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14559 { 3583 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14560 { 3583 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14561 { 3583 /* vrintp */, ARM::VRINTPS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14562 { 3583 /* vrintp */, ARM::VRINTPD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14563 { 3583 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14564 { 3583 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14565 { 3583 /* vrintp */, ARM::VRINTPH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14566 { 3583 /* vrintp */, ARM::MVE_VRINTf32P, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14567 { 3583 /* vrintp */, ARM::MVE_VRINTf16P, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14568 { 3590 /* vrintr */, ARM::VRINTRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14569 { 3590 /* vrintr */, ARM::VRINTRD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14570 { 3590 /* vrintr */, ARM::VRINTRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14571 { 3590 /* vrintr */, ARM::VRINTRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14572 { 3590 /* vrintr */, ARM::VRINTRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14573 { 3590 /* vrintr */, ARM::VRINTRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14574 { 3597 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14575 { 3597 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14576 { 3597 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14577 { 3597 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14578 { 3597 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14579 { 3597 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14580 { 3597 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14581 { 3597 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14582 { 3597 /* vrintx */, ARM::VRINTXS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14583 { 3597 /* vrintx */, ARM::VRINTXD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14584 { 3597 /* vrintx */, ARM::VRINTXH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14585 { 3597 /* vrintx */, ARM::MVE_VRINTf32X, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14586 { 3597 /* vrintx */, ARM::MVE_VRINTf16X, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14587 { 3597 /* vrintx */, ARM::VRINTXS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14588 { 3597 /* vrintx */, ARM::VRINTXD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14589 { 3597 /* vrintx */, ARM::VRINTXH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14590 { 3604 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14591 { 3604 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14592 { 3604 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14593 { 3604 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_1__Reg1_2, AMFBS_HasV8_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14594 { 3604 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14595 { 3604 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14596 { 3604 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14597 { 3604 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14598 { 3604 /* vrintz */, ARM::VRINTZS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14599 { 3604 /* vrintz */, ARM::VRINTZD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14600 { 3604 /* vrintz */, ARM::VRINTZH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14601 { 3604 /* vrintz */, ARM::MVE_VRINTf32Z, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14602 { 3604 /* vrintz */, ARM::MVE_VRINTf16Z, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14603 { 3604 /* vrintz */, ARM::VRINTZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14604 { 3604 /* vrintz */, ARM::VRINTZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14605 { 3604 /* vrintz */, ARM::VRINTZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14606 { 3611 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14607 { 3611 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14608 { 3622 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14609 { 3622 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14610 { 3634 /* vrmlaldavhax */, ARM::MVE_VRMLALDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14611 { 3647 /* vrmlaldavhx */, ARM::MVE_VRMLALDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14612 { 3659 /* vrmlalvh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14613 { 3659 /* vrmlalvh */, ARM::MVE_VRMLALDAVHu32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14614 { 3668 /* vrmlalvha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14615 { 3668 /* vrmlalvha */, ARM::MVE_VRMLALDAVHau32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_u32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14616 { 3678 /* vrmlsldavh */, ARM::MVE_VRMLSLDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14617 { 3689 /* vrmlsldavha */, ARM::MVE_VRMLSLDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14618 { 3701 /* vrmlsldavhax */, ARM::MVE_VRMLSLDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14619 { 3714 /* vrmlsldavhx */, ARM::MVE_VRMLSLDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14620 { 3726 /* vrmulh */, ARM::MVE_VRMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14621 { 3726 /* vrmulh */, ARM::MVE_VRMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14622 { 3726 /* vrmulh */, ARM::MVE_VRMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14623 { 3726 /* vrmulh */, ARM::MVE_VRMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14624 { 3726 /* vrmulh */, ARM::MVE_VRMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14625 { 3726 /* vrmulh */, ARM::MVE_VRMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14626 { 3733 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14627 { 3733 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14628 { 3733 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14629 { 3733 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14630 { 3733 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14631 { 3733 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14632 { 3733 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14633 { 3733 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14634 { 3733 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14635 { 3733 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14636 { 3733 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14637 { 3733 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14638 { 3733 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14639 { 3733 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14640 { 3733 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14641 { 3733 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14642 { 3733 /* vrshl */, ARM::MVE_VRSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14643 { 3733 /* vrshl */, ARM::MVE_VRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14644 { 3733 /* vrshl */, ARM::MVE_VRSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14645 { 3733 /* vrshl */, ARM::MVE_VRSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14646 { 3733 /* vrshl */, ARM::MVE_VRSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14647 { 3733 /* vrshl */, ARM::MVE_VRSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14648 { 3733 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14649 { 3733 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14650 { 3733 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14651 { 3733 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14652 { 3733 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14653 { 3733 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14654 { 3733 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14655 { 3733 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14656 { 3733 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14657 { 3733 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14658 { 3733 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14659 { 3733 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14660 { 3733 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14661 { 3733 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14662 { 3733 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14663 { 3733 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14664 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14665 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14666 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14667 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14668 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14669 { 3733 /* vrshl */, ARM::MVE_VRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14670 { 3739 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
14671 { 3739 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
14672 { 3739 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14673 { 3739 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14674 { 3739 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
14675 { 3739 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
14676 { 3739 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
14677 { 3739 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
14678 { 3739 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
14679 { 3739 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
14680 { 3739 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
14681 { 3739 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
14682 { 3739 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
14683 { 3739 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
14684 { 3739 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
14685 { 3739 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
14686 { 3739 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14687 { 3739 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14688 { 3739 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14689 { 3739 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14690 { 3739 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14691 { 3739 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14692 { 3739 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14693 { 3739 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14694 { 3739 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14695 { 3739 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14696 { 3739 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14697 { 3739 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14698 { 3739 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14699 { 3739 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14700 { 3739 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14701 { 3739 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14702 { 3739 /* vrshr */, ARM::MVE_VRSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14703 { 3739 /* vrshr */, ARM::MVE_VRSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14704 { 3739 /* vrshr */, ARM::MVE_VRSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14705 { 3739 /* vrshr */, ARM::MVE_VRSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14706 { 3739 /* vrshr */, ARM::MVE_VRSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14707 { 3739 /* vrshr */, ARM::MVE_VRSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14708 { 3745 /* vrshrn */, ARM::VRSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14709 { 3745 /* vrshrn */, ARM::VRSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14710 { 3745 /* vrshrn */, ARM::VRSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14711 { 3752 /* vrshrnb */, ARM::MVE_VRSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14712 { 3752 /* vrshrnb */, ARM::MVE_VRSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14713 { 3760 /* vrshrnt */, ARM::MVE_VRSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14714 { 3760 /* vrshrnt */, ARM::MVE_VRSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14715 { 3768 /* vrsqrte */, ARM::VRSQRTEq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14716 { 3768 /* vrsqrte */, ARM::VRSQRTEd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14717 { 3768 /* vrsqrte */, ARM::VRSQRTEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14718 { 3768 /* vrsqrte */, ARM::VRSQRTEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14719 { 3768 /* vrsqrte */, ARM::VRSQRTEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14720 { 3768 /* vrsqrte */, ARM::VRSQRTEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14721 { 3776 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
14722 { 3776 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
14723 { 3776 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
14724 { 3776 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
14725 { 3776 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14726 { 3776 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14727 { 3776 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14728 { 3776 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14729 { 3784 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
14730 { 3784 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
14731 { 3784 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14732 { 3784 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14733 { 3784 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
14734 { 3784 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
14735 { 3784 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
14736 { 3784 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
14737 { 3784 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
14738 { 3784 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
14739 { 3784 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
14740 { 3784 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
14741 { 3784 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
14742 { 3784 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
14743 { 3784 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
14744 { 3784 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
14745 { 3784 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14746 { 3784 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14747 { 3784 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14748 { 3784 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14749 { 3784 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14750 { 3784 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14751 { 3784 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14752 { 3784 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14753 { 3784 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14754 { 3784 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14755 { 3784 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14756 { 3784 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14757 { 3784 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14758 { 3784 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14759 { 3784 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14760 { 3784 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14761 { 3790 /* vrsubhn */, ARM::VRSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
14762 { 3790 /* vrsubhn */, ARM::VRSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
14763 { 3790 /* vrsubhn */, ARM::VRSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
14764 { 3798 /* vsbc */, ARM::MVE_VSBC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14765 { 3803 /* vsbci */, ARM::MVE_VSBCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14766 { 3809 /* vscclrm */, ARM::VSCCLRMD, Convert__CondCode2_0__FPDRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPDRegListWithVPR }, },
14767 { 3809 /* vscclrm */, ARM::VSCCLRMS, Convert__CondCode2_0__FPSRegListWithVPR1_1, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPSRegListWithVPR }, },
14768 { 3817 /* vsdot */, ARM::VSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14769 { 3817 /* vsdot */, ARM::VSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14770 { 3817 /* vsdot */, ARM::VSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14771 { 3817 /* vsdot */, ARM::VSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
14772 { 3823 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14773 { 3823 /* vseleq */, ARM::VSELEQD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14774 { 3823 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14775 { 3830 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14776 { 3830 /* vselge */, ARM::VSELGED, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14777 { 3830 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14778 { 3837 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14779 { 3837 /* vselgt */, ARM::VSELGTD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14780 { 3837 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14781 { 3844 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14782 { 3844 /* vselvs */, ARM::VSELVSD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14783 { 3844 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14784 { 3851 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, },
14785 { 3851 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, },
14786 { 3851 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14787 { 3851 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14788 { 3851 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, },
14789 { 3851 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, },
14790 { 3851 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, },
14791 { 3851 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, },
14792 { 3851 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, },
14793 { 3851 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, },
14794 { 3851 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, },
14795 { 3851 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, },
14796 { 3851 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, },
14797 { 3851 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, },
14798 { 3851 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, },
14799 { 3851 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, },
14800 { 3851 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_Imm }, },
14801 { 3851 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_Imm }, },
14802 { 3851 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_Imm }, },
14803 { 3851 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_Imm }, },
14804 { 3851 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_Imm }, },
14805 { 3851 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_Imm }, },
14806 { 3851 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_Imm }, },
14807 { 3851 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_Imm }, },
14808 { 3851 /* vshl */, ARM::MVE_VSHL_qrs16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_rGPR }, },
14809 { 3851 /* vshl */, ARM::MVE_VSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14810 { 3851 /* vshl */, ARM::MVE_VSHL_qrs8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_MQPR, MCK_rGPR }, },
14811 { 3851 /* vshl */, ARM::MVE_VSHL_qru16, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_rGPR }, },
14812 { 3851 /* vshl */, ARM::MVE_VSHL_qru32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_rGPR }, },
14813 { 3851 /* vshl */, ARM::MVE_VSHL_qru8, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_rGPR }, },
14814 { 3851 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14815 { 3851 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14816 { 3851 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14817 { 3851 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14818 { 3851 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14819 { 3851 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14820 { 3851 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14821 { 3851 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14822 { 3851 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, },
14823 { 3851 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, },
14824 { 3851 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14825 { 3851 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14826 { 3851 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, },
14827 { 3851 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, },
14828 { 3851 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14829 { 3851 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
14830 { 3851 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14831 { 3851 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14832 { 3851 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14833 { 3851 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14834 { 3851 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14835 { 3851 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14836 { 3851 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14837 { 3851 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14838 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14839 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14840 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14841 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14842 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14843 { 3851 /* vshl */, ARM::MVE_VSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14844 { 3851 /* vshl */, ARM::MVE_VSHL_immi16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14845 { 3851 /* vshl */, ARM::MVE_VSHL_immi32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14846 { 3851 /* vshl */, ARM::MVE_VSHL_immi8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14847 { 3856 /* vshlc */, ARM::MVE_VSHLC, Convert__Reg1_2__Reg1_1__Tie1_2_2__Tie0_3_3__MVELongShift1_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK_MQPR, MCK_rGPR, MCK_MVELongShift }, },
14848 { 3862 /* vshll */, ARM::VSHLLsv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, },
14849 { 3862 /* vshll */, ARM::VSHLLsv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, },
14850 { 3862 /* vshll */, ARM::VSHLLsv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, },
14851 { 3862 /* vshll */, ARM::VSHLLuv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, },
14852 { 3862 /* vshll */, ARM::VSHLLuv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, },
14853 { 3862 /* vshll */, ARM::VSHLLuv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, },
14854 { 3862 /* vshll */, ARM::VSHLLi16, Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR, MCK_Imm16 }, },
14855 { 3862 /* vshll */, ARM::VSHLLi32, Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR, MCK_Imm32 }, },
14856 { 3862 /* vshll */, ARM::VSHLLi8, Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_DPR, MCK_Imm8 }, },
14857 { 3868 /* vshllb */, ARM::MVE_VSHLL_lws16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14858 { 3868 /* vshllb */, ARM::MVE_VSHLL_imms16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14859 { 3868 /* vshllb */, ARM::MVE_VSHLL_lws8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14860 { 3868 /* vshllb */, ARM::MVE_VSHLL_imms8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14861 { 3868 /* vshllb */, ARM::MVE_VSHLL_lwu16bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14862 { 3868 /* vshllb */, ARM::MVE_VSHLL_immu16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14863 { 3868 /* vshllb */, ARM::MVE_VSHLL_lwu8bh, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14864 { 3868 /* vshllb */, ARM::MVE_VSHLL_immu8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14865 { 3875 /* vshllt */, ARM::MVE_VSHLL_lws16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14866 { 3875 /* vshllt */, ARM::MVE_VSHLL_imms16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14867 { 3875 /* vshllt */, ARM::MVE_VSHLL_lws8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14868 { 3875 /* vshllt */, ARM::MVE_VSHLL_imms8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14869 { 3875 /* vshllt */, ARM::MVE_VSHLL_lwu16th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14870 { 3875 /* vshllt */, ARM::MVE_VSHLL_immu16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14871 { 3875 /* vshllt */, ARM::MVE_VSHLL_lwu8th, Convert__Reg1_2__Reg1_3__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14872 { 3875 /* vshllt */, ARM::MVE_VSHLL_immu8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14873 { 3882 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
14874 { 3882 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
14875 { 3882 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14876 { 3882 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14877 { 3882 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
14878 { 3882 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
14879 { 3882 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
14880 { 3882 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
14881 { 3882 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
14882 { 3882 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
14883 { 3882 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
14884 { 3882 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
14885 { 3882 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
14886 { 3882 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
14887 { 3882 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
14888 { 3882 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
14889 { 3882 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14890 { 3882 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14891 { 3882 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14892 { 3882 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14893 { 3882 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14894 { 3882 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14895 { 3882 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14896 { 3882 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14897 { 3882 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14898 { 3882 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14899 { 3882 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14900 { 3882 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14901 { 3882 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14902 { 3882 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14903 { 3882 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14904 { 3882 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14905 { 3882 /* vshr */, ARM::MVE_VSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14906 { 3882 /* vshr */, ARM::MVE_VSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14907 { 3882 /* vshr */, ARM::MVE_VSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14908 { 3882 /* vshr */, ARM::MVE_VSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14909 { 3882 /* vshr */, ARM::MVE_VSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14910 { 3882 /* vshr */, ARM::MVE_VSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14911 { 3887 /* vshrn */, ARM::VSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, },
14912 { 3887 /* vshrn */, ARM::VSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14913 { 3887 /* vshrn */, ARM::VSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, },
14914 { 3893 /* vshrnb */, ARM::MVE_VSHRNi16bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14915 { 3893 /* vshrnb */, ARM::MVE_VSHRNi32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14916 { 3900 /* vshrnt */, ARM::MVE_VSHRNi16th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14917 { 3900 /* vshrnt */, ARM::MVE_VSHRNi32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14918 { 3907 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_Imm }, },
14919 { 3907 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_Imm }, },
14920 { 3907 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_Imm }, },
14921 { 3907 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_Imm }, },
14922 { 3907 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_Imm }, },
14923 { 3907 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_Imm }, },
14924 { 3907 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_Imm }, },
14925 { 3907 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_Imm }, },
14926 { 3907 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm }, },
14927 { 3907 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm }, },
14928 { 3907 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14929 { 3907 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14930 { 3907 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm }, },
14931 { 3907 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_Imm }, },
14932 { 3907 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm }, },
14933 { 3907 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm }, },
14934 { 3907 /* vsli */, ARM::MVE_VSLIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_151_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14935 { 3907 /* vsli */, ARM::MVE_VSLIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_311_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14936 { 3907 /* vsli */, ARM::MVE_VSLIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm0_71_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14937 { 3912 /* vsmmla */, ARM::VSMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
14938 { 3919 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
14939 { 3919 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
14940 { 3919 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14941 { 3919 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
14942 { 3919 /* vsqrt */, ARM::VSQRTH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14943 { 3925 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, },
14944 { 3925 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, },
14945 { 3925 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14946 { 3925 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14947 { 3925 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, },
14948 { 3925 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, },
14949 { 3925 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, },
14950 { 3925 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, },
14951 { 3925 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, },
14952 { 3925 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, },
14953 { 3925 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, },
14954 { 3925 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, },
14955 { 3925 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, },
14956 { 3925 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, },
14957 { 3925 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, },
14958 { 3925 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, },
14959 { 3925 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14960 { 3925 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14961 { 3925 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14962 { 3925 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14963 { 3925 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14964 { 3925 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14965 { 3925 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14966 { 3925 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14967 { 3925 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14968 { 3925 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14969 { 3925 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14970 { 3925 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14971 { 3925 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14972 { 3925 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14973 { 3925 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14974 { 3925 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14975 { 3930 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_ShrImm16 }, },
14976 { 3930 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_ShrImm16 }, },
14977 { 3930 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_ShrImm32 }, },
14978 { 3930 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_ShrImm32 }, },
14979 { 3930 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_ShrImm64 }, },
14980 { 3930 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_ShrImm64 }, },
14981 { 3930 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_ShrImm8 }, },
14982 { 3930 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_ShrImm8 }, },
14983 { 3930 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, },
14984 { 3930 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, },
14985 { 3930 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14986 { 3930 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14987 { 3930 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, },
14988 { 3930 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, },
14989 { 3930 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, },
14990 { 3930 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, },
14991 { 3930 /* vsri */, ARM::MVE_VSRIimm16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14992 { 3930 /* vsri */, ARM::MVE_VSRIimm32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14993 { 3930 /* vsri */, ARM::MVE_VSRIimm8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14994 { 3935 /* vst1 */, ARM::VST1q16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
14995 { 3935 /* vst1 */, ARM::VST1d16Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
14996 { 3935 /* vst1 */, ARM::VST1d16, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, },
14997 { 3935 /* vst1 */, ARM::VST1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, },
14998 { 3935 /* vst1 */, ARM::VST1d16T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
14999 { 3935 /* vst1 */, ARM::VST1q32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15000 { 3935 /* vst1 */, ARM::VST1d32Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15001 { 3935 /* vst1 */, ARM::VST1d32, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, },
15002 { 3935 /* vst1 */, ARM::VST1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, },
15003 { 3935 /* vst1 */, ARM::VST1d32T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15004 { 3935 /* vst1 */, ARM::VST1q64, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15005 { 3935 /* vst1 */, ARM::VST1d64Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15006 { 3935 /* vst1 */, ARM::VST1d64, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, },
15007 { 3935 /* vst1 */, ARM::VST1d64T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15008 { 3935 /* vst1 */, ARM::VST1q8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15009 { 3935 /* vst1 */, ARM::VST1d8Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15010 { 3935 /* vst1 */, ARM::VST1d8, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, },
15011 { 3935 /* vst1 */, ARM::VST1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, },
15012 { 3935 /* vst1 */, ARM::VST1d8T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15013 { 3935 /* vst1 */, ARM::VST1q16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15014 { 3935 /* vst1 */, ARM::VST1q16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15015 { 3935 /* vst1 */, ARM::VST1d16Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15016 { 3935 /* vst1 */, ARM::VST1d16Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15017 { 3935 /* vst1 */, ARM::VST1d16wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15018 { 3935 /* vst1 */, ARM::VST1d16wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
15019 { 3935 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
15020 { 3935 /* vst1 */, ARM::VST1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
15021 { 3935 /* vst1 */, ARM::VST1d16Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15022 { 3935 /* vst1 */, ARM::VST1d16Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15023 { 3935 /* vst1 */, ARM::VST1q32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15024 { 3935 /* vst1 */, ARM::VST1q32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15025 { 3935 /* vst1 */, ARM::VST1d32Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15026 { 3935 /* vst1 */, ARM::VST1d32Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15027 { 3935 /* vst1 */, ARM::VST1d32wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15028 { 3935 /* vst1 */, ARM::VST1d32wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
15029 { 3935 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
15030 { 3935 /* vst1 */, ARM::VST1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
15031 { 3935 /* vst1 */, ARM::VST1d32Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15032 { 3935 /* vst1 */, ARM::VST1d32Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15033 { 3935 /* vst1 */, ARM::VST1q64wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15034 { 3935 /* vst1 */, ARM::VST1q64wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15035 { 3935 /* vst1 */, ARM::VST1d64Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15036 { 3935 /* vst1 */, ARM::VST1d64Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15037 { 3935 /* vst1 */, ARM::VST1d64wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15038 { 3935 /* vst1 */, ARM::VST1d64wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
15039 { 3935 /* vst1 */, ARM::VST1d64Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15040 { 3935 /* vst1 */, ARM::VST1d64Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15041 { 3935 /* vst1 */, ARM::VST1q8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15042 { 3935 /* vst1 */, ARM::VST1q8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15043 { 3935 /* vst1 */, ARM::VST1d8Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15044 { 3935 /* vst1 */, ARM::VST1d8Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15045 { 3935 /* vst1 */, ARM::VST1d8wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15046 { 3935 /* vst1 */, ARM::VST1d8wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, },
15047 { 3935 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15048 { 3935 /* vst1 */, ARM::VST1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15049 { 3935 /* vst1 */, ARM::VST1d8Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15050 { 3935 /* vst1 */, ARM::VST1d8Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15051 { 3935 /* vst1 */, ARM::VST1LNd16, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
15052 { 3935 /* vst1 */, ARM::VST1LNd8, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, },
15053 { 3935 /* vst1 */, ARM::VST1LNd16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15054 { 3935 /* vst1 */, ARM::VST1LNd32, Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, },
15055 { 3935 /* vst1 */, ARM::VST1LNd8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15056 { 3935 /* vst1 */, ARM::VST1LNd32_UPD, Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm, MCK_Imm }, },
15057 { 3940 /* vst2 */, ARM::VST2d16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15058 { 3940 /* vst2 */, ARM::VST2b16, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
15059 { 3940 /* vst2 */, ARM::VST2q16, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15060 { 3940 /* vst2 */, ARM::VST2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, },
15061 { 3940 /* vst2 */, ARM::VST2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, },
15062 { 3940 /* vst2 */, ARM::VST2d32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15063 { 3940 /* vst2 */, ARM::VST2b32, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
15064 { 3940 /* vst2 */, ARM::VST2q32, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15065 { 3940 /* vst2 */, ARM::VST2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, },
15066 { 3940 /* vst2 */, ARM::VST2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, },
15067 { 3940 /* vst2 */, ARM::VST2d8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, },
15068 { 3940 /* vst2 */, ARM::VST2b8, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, },
15069 { 3940 /* vst2 */, ARM::VST2q8, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15070 { 3940 /* vst2 */, ARM::VST2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, },
15071 { 3940 /* vst2 */, ARM::VST2d16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15072 { 3940 /* vst2 */, ARM::VST2d16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15073 { 3940 /* vst2 */, ARM::VST2b16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15074 { 3940 /* vst2 */, ARM::VST2b16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
15075 { 3940 /* vst2 */, ARM::VST2q16wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15076 { 3940 /* vst2 */, ARM::VST2q16wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15077 { 3940 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
15078 { 3940 /* vst2 */, ARM::VST2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
15079 { 3940 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
15080 { 3940 /* vst2 */, ARM::VST2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
15081 { 3940 /* vst2 */, ARM::VST2d32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15082 { 3940 /* vst2 */, ARM::VST2d32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15083 { 3940 /* vst2 */, ARM::VST2b32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15084 { 3940 /* vst2 */, ARM::VST2b32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
15085 { 3940 /* vst2 */, ARM::VST2q32wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15086 { 3940 /* vst2 */, ARM::VST2q32wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15087 { 3940 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15088 { 3940 /* vst2 */, ARM::VST2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15089 { 3940 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15090 { 3940 /* vst2 */, ARM::VST2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15091 { 3940 /* vst2 */, ARM::VST2d8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15092 { 3940 /* vst2 */, ARM::VST2d8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, },
15093 { 3940 /* vst2 */, ARM::VST2b8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15094 { 3940 /* vst2 */, ARM::VST2b8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, },
15095 { 3940 /* vst2 */, ARM::VST2q8wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15096 { 3940 /* vst2 */, ARM::VST2q8wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15097 { 3940 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
15098 { 3940 /* vst2 */, ARM::VST2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, },
15099 { 3945 /* vst20 */, ARM::MVE_VST20_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15100 { 3945 /* vst20 */, ARM::MVE_VST20_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15101 { 3945 /* vst20 */, ARM::MVE_VST20_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15102 { 3945 /* vst20 */, ARM::MVE_VST20_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15103 { 3945 /* vst20 */, ARM::MVE_VST20_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15104 { 3945 /* vst20 */, ARM::MVE_VST20_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15105 { 3951 /* vst21 */, ARM::MVE_VST21_16, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15106 { 3951 /* vst21 */, ARM::MVE_VST21_32, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15107 { 3951 /* vst21 */, ARM::MVE_VST21_8, Convert__VecListTwoMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2 }, },
15108 { 3951 /* vst21 */, ARM::MVE_VST21_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15109 { 3951 /* vst21 */, ARM::MVE_VST21_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15110 { 3951 /* vst21 */, ARM::MVE_VST21_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15111 { 3957 /* vst3 */, ARM::VST3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15112 { 3957 /* vst3 */, ARM::VST3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, },
15113 { 3957 /* vst3 */, ARM::VST3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
15114 { 3957 /* vst3 */, ARM::VST3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, },
15115 { 3957 /* vst3 */, ARM::VST3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15116 { 3957 /* vst3 */, ARM::VST3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, },
15117 { 3957 /* vst3 */, ARM::VST3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
15118 { 3957 /* vst3 */, ARM::VST3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, },
15119 { 3957 /* vst3 */, ARM::VST3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, },
15120 { 3957 /* vst3 */, ARM::VST3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, },
15121 { 3957 /* vst3 */, ARM::VST3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, },
15122 { 3957 /* vst3 */, ARM::VST3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15123 { 3957 /* vst3 */, ARM::VST3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15124 { 3957 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15125 { 3957 /* vst3 */, ARM::VST3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15126 { 3957 /* vst3 */, ARM::VST3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15127 { 3957 /* vst3 */, ARM::VST3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
15128 { 3957 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15129 { 3957 /* vst3 */, ARM::VST3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15130 { 3957 /* vst3 */, ARM::VST3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15131 { 3957 /* vst3 */, ARM::VST3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15132 { 3957 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15133 { 3957 /* vst3 */, ARM::VST3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15134 { 3957 /* vst3 */, ARM::VST3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15135 { 3957 /* vst3 */, ARM::VST3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
15136 { 3957 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15137 { 3957 /* vst3 */, ARM::VST3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15138 { 3957 /* vst3 */, ARM::VST3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15139 { 3957 /* vst3 */, ARM::VST3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, },
15140 { 3957 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
15141 { 3957 /* vst3 */, ARM::VST3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, },
15142 { 3957 /* vst3 */, ARM::VST3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15143 { 3957 /* vst3 */, ARM::VST3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, },
15144 { 3957 /* vst3 */, ARM::VST3d16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15145 { 3957 /* vst3 */, ARM::VST3q16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15146 { 3957 /* vst3 */, ARM::VST3d32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15147 { 3957 /* vst3 */, ARM::VST3q32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15148 { 3957 /* vst3 */, ARM::VST3d8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15149 { 3957 /* vst3 */, ARM::VST3q8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15150 { 3957 /* vst3 */, ARM::VST3d16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15151 { 3957 /* vst3 */, ARM::VST3q16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15152 { 3957 /* vst3 */, ARM::VST3d32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15153 { 3957 /* vst3 */, ARM::VST3q32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15154 { 3957 /* vst3 */, ARM::VST3d8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15155 { 3957 /* vst3 */, ARM::VST3q8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15156 { 3962 /* vst4 */, ARM::VST4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15157 { 3962 /* vst4 */, ARM::VST4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, },
15158 { 3962 /* vst4 */, ARM::VST4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
15159 { 3962 /* vst4 */, ARM::VST4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, },
15160 { 3962 /* vst4 */, ARM::VST4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15161 { 3962 /* vst4 */, ARM::VST4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, },
15162 { 3962 /* vst4 */, ARM::VST4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
15163 { 3962 /* vst4 */, ARM::VST4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, },
15164 { 3962 /* vst4 */, ARM::VST4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, },
15165 { 3962 /* vst4 */, ARM::VST4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, },
15166 { 3962 /* vst4 */, ARM::VST4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, },
15167 { 3962 /* vst4 */, ARM::VST4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15168 { 3962 /* vst4 */, ARM::VST4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15169 { 3962 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15170 { 3962 /* vst4 */, ARM::VST4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15171 { 3962 /* vst4 */, ARM::VST4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15172 { 3962 /* vst4 */, ARM::VST4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15173 { 3962 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
15174 { 3962 /* vst4 */, ARM::VST4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, },
15175 { 3962 /* vst4 */, ARM::VST4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15176 { 3962 /* vst4 */, ARM::VST4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15177 { 3962 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15178 { 3962 /* vst4 */, ARM::VST4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
15179 { 3962 /* vst4 */, ARM::VST4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15180 { 3962 /* vst4 */, ARM::VST4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15181 { 3962 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
15182 { 3962 /* vst4 */, ARM::VST4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, },
15183 { 3962 /* vst4 */, ARM::VST4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15184 { 3962 /* vst4 */, ARM::VST4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15185 { 3962 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
15186 { 3962 /* vst4 */, ARM::VST4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, },
15187 { 3962 /* vst4 */, ARM::VST4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
15188 { 3962 /* vst4 */, ARM::VST4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, },
15189 { 3962 /* vst4 */, ARM::VST4d16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15190 { 3962 /* vst4 */, ARM::VST4q16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15191 { 3962 /* vst4 */, ARM::VST4d32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15192 { 3962 /* vst4 */, ARM::VST4q32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15193 { 3962 /* vst4 */, ARM::VST4d8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15194 { 3962 /* vst4 */, ARM::VST4q8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, },
15195 { 3962 /* vst4 */, ARM::VST4d16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15196 { 3962 /* vst4 */, ARM::VST4q16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15197 { 3962 /* vst4 */, ARM::VST4d32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15198 { 3962 /* vst4 */, ARM::VST4q32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15199 { 3962 /* vst4 */, ARM::VST4d8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15200 { 3962 /* vst4 */, ARM::VST4q8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, },
15201 { 3967 /* vst40 */, ARM::MVE_VST40_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15202 { 3967 /* vst40 */, ARM::MVE_VST40_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15203 { 3967 /* vst40 */, ARM::MVE_VST40_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15204 { 3967 /* vst40 */, ARM::MVE_VST40_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15205 { 3967 /* vst40 */, ARM::MVE_VST40_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15206 { 3967 /* vst40 */, ARM::MVE_VST40_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15207 { 3973 /* vst41 */, ARM::MVE_VST41_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15208 { 3973 /* vst41 */, ARM::MVE_VST41_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15209 { 3973 /* vst41 */, ARM::MVE_VST41_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15210 { 3973 /* vst41 */, ARM::MVE_VST41_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15211 { 3973 /* vst41 */, ARM::MVE_VST41_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15212 { 3973 /* vst41 */, ARM::MVE_VST41_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15213 { 3979 /* vst42 */, ARM::MVE_VST42_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15214 { 3979 /* vst42 */, ARM::MVE_VST42_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15215 { 3979 /* vst42 */, ARM::MVE_VST42_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15216 { 3979 /* vst42 */, ARM::MVE_VST42_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15217 { 3979 /* vst42 */, ARM::MVE_VST42_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15218 { 3979 /* vst42 */, ARM::MVE_VST42_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15219 { 3985 /* vst43 */, ARM::MVE_VST43_16, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15220 { 3985 /* vst43 */, ARM::MVE_VST43_32, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15221 { 3985 /* vst43 */, ARM::MVE_VST43_8, Convert__VecListFourMQ1_1__MemNoOffsetT21_2, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2 }, },
15222 { 3985 /* vst43 */, ARM::MVE_VST43_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15223 { 3985 /* vst43 */, ARM::MVE_VST43_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15224 { 3985 /* vst43 */, ARM::MVE_VST43_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
15225 { 3991 /* vstmdb */, ARM::VSTMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
15226 { 3991 /* vstmdb */, ARM::VSTMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
15227 { 3998 /* vstmia */, ARM::VSTMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, },
15228 { 3998 /* vstmia */, ARM::VSTMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, },
15229 { 3998 /* vstmia */, ARM::VSTMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
15230 { 3998 /* vstmia */, ARM::VSTMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
15231 { 4005 /* vstr */, ARM::VSTR_FPCXTNS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset }, },
15232 { 4005 /* vstr */, ARM::VSTR_FPCXTS_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset }, },
15233 { 4005 /* vstr */, ARM::VSTR_FPSCR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset }, },
15234 { 4005 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset }, },
15235 { 4005 /* vstr */, ARM::VSTR_P0_off, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset }, },
15236 { 4005 /* vstr */, ARM::VSTR_VPR_off, Convert__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset }, },
15237 { 4005 /* vstr */, ARM::VSTRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, },
15238 { 4005 /* vstr */, ARM::VSTRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
15239 { 4005 /* vstr */, ARM::VSTRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
15240 { 4005 /* vstr */, ARM::VSTRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
15241 { 4005 /* vstr */, ARM::VSTRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, },
15242 { 4005 /* vstr */, ARM::VSTR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15243 { 4005 /* vstr */, ARM::VSTR_FPCXTNS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTRegs, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15244 { 4005 /* vstr */, ARM::VSTR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15245 { 4005 /* vstr */, ARM::VSTR_FPCXTS_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15246 { 4005 /* vstr */, ARM::VSTR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15247 { 4005 /* vstr */, ARM::VSTR_FPSCR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15248 { 4005 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15249 { 4005 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_post, Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15250 { 4005 /* vstr */, ARM::VSTR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15251 { 4005 /* vstr */, ARM::VSTR_P0_post, Convert__MemNoOffsetT21_2__imm_95_0__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15252 { 4005 /* vstr */, ARM::VSTR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
15253 { 4005 /* vstr */, ARM::VSTR_VPR_post, Convert__MemNoOffsetT21_2__Tie0_3_3__Imm7s41_3__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemNoOffsetT2, MCK_Imm7s4 }, },
15254 { 4010 /* vstrb */, ARM::MVE_VSTRB16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15255 { 4010 /* vstrb */, ARM::MVE_VSTRB16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
15256 { 4010 /* vstrb */, ARM::MVE_VSTRB32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15257 { 4010 /* vstrb */, ARM::MVE_VSTRB32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
15258 { 4010 /* vstrb */, ARM::MVE_VSTRBU8, Convert__Reg1_2__MemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0Offset }, },
15259 { 4010 /* vstrb */, ARM::MVE_VSTRB8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15260 { 4010 /* vstrb */, ARM::MVE_VSTRB16_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
15261 { 4010 /* vstrb */, ARM::MVE_VSTRB16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
15262 { 4010 /* vstrb */, ARM::MVE_VSTRB32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
15263 { 4010 /* vstrb */, ARM::MVE_VSTRB32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
15264 { 4010 /* vstrb */, ARM::MVE_VSTRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, },
15265 { 4010 /* vstrb */, ARM::MVE_VSTRBU8_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift0 }, },
15266 { 4016 /* vstrd */, ARM::MVE_VSTRD64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset }, },
15267 { 4016 /* vstrd */, ARM::MVE_VSTRD64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15268 { 4016 /* vstrd */, ARM::MVE_VSTRD64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS3Offset }, },
15269 { 4016 /* vstrd */, ARM::MVE_VSTRD64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, },
15270 { 4022 /* vstrh */, ARM::MVE_VSTRHU16, Convert__Reg1_2__MemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1Offset }, },
15271 { 4022 /* vstrh */, ARM::MVE_VSTRH16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15272 { 4022 /* vstrh */, ARM::MVE_VSTRH16_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS1Offset }, },
15273 { 4022 /* vstrh */, ARM::MVE_VSTRH32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15274 { 4022 /* vstrh */, ARM::MVE_VSTRH32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
15275 { 4022 /* vstrh */, ARM::MVE_VSTRH32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
15276 { 4022 /* vstrh */, ARM::MVE_VSTRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, },
15277 { 4022 /* vstrh */, ARM::MVE_VSTRHU16_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift1 }, },
15278 { 4022 /* vstrh */, ARM::MVE_VSTRH32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
15279 { 4022 /* vstrh */, ARM::MVE_VSTRH32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
15280 { 4028 /* vstrw */, ARM::MVE_VSTRWU32, Convert__Reg1_2__MemImm7Shift2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2Offset }, },
15281 { 4028 /* vstrw */, ARM::MVE_VSTRW32_qi, Convert__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset }, },
15282 { 4028 /* vstrw */, ARM::MVE_VSTRW32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
15283 { 4028 /* vstrw */, ARM::MVE_VSTRW32_rq, Convert__Reg1_2__MemRegRQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS2Offset }, },
15284 { 4028 /* vstrw */, ARM::MVE_VSTRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, },
15285 { 4028 /* vstrw */, ARM::MVE_VSTRWU32_post, Convert__MemNoOffsetT2NoSp1_3__Reg1_2__Tie0_4_4__Imm7Shift21_4__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemNoOffsetT2NoSp, MCK_Imm7Shift2 }, },
15286 { 4028 /* vstrw */, ARM::MVE_VSTRW32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN3_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, },
15287 { 4034 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
15288 { 4034 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
15289 { 4034 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
15290 { 4034 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, },
15291 { 4034 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, },
15292 { 4034 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, },
15293 { 4034 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, },
15294 { 4034 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, },
15295 { 4034 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, },
15296 { 4034 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, },
15297 { 4034 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, },
15298 { 4034 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, },
15299 { 4034 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, },
15300 { 4034 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, },
15301 { 4034 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
15302 { 4034 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15303 { 4034 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15304 { 4034 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
15305 { 4034 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15306 { 4034 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15307 { 4034 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15308 { 4034 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15309 { 4034 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15310 { 4034 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, },
15311 { 4034 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, },
15312 { 4034 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15313 { 4034 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15314 { 4034 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15315 { 4034 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15316 { 4034 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
15317 { 4034 /* vsub */, ARM::MVE_VSUBf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15318 { 4034 /* vsub */, ARM::MVE_VSUB_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15319 { 4034 /* vsub */, ARM::MVE_VSUBi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15320 { 4034 /* vsub */, ARM::MVE_VSUB_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15321 { 4034 /* vsub */, ARM::MVE_VSUBi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15322 { 4034 /* vsub */, ARM::MVE_VSUB_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15323 { 4034 /* vsub */, ARM::MVE_VSUBi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15324 { 4034 /* vsub */, ARM::MVE_VSUB_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15325 { 4034 /* vsub */, ARM::MVE_VSUBf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
15326 { 4034 /* vsub */, ARM::MVE_VSUB_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR4_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
15327 { 4039 /* vsubhn */, ARM::VSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, },
15328 { 4039 /* vsubhn */, ARM::VSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, },
15329 { 4039 /* vsubhn */, ARM::VSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, },
15330 { 4046 /* vsubl */, ARM::VSUBLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, },
15331 { 4046 /* vsubl */, ARM::VSUBLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
15332 { 4046 /* vsubl */, ARM::VSUBLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, },
15333 { 4046 /* vsubl */, ARM::VSUBLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, },
15334 { 4046 /* vsubl */, ARM::VSUBLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, },
15335 { 4046 /* vsubl */, ARM::VSUBLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, },
15336 { 4052 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, },
15337 { 4052 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
15338 { 4052 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, },
15339 { 4052 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, },
15340 { 4052 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, },
15341 { 4052 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, },
15342 { 4052 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, },
15343 { 4052 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
15344 { 4052 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, },
15345 { 4052 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, },
15346 { 4052 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, },
15347 { 4052 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, },
15348 { 4058 /* vsudot */, ARM::VSUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15349 { 4058 /* vsudot */, ARM::VSUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15350 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, },
15351 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, },
15352 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15353 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15354 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15355 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15356 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, },
15357 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, },
15358 { 4065 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15359 { 4065 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15360 { 4070 /* vtbl */, ARM::VTBL2, Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, },
15361 { 4070 /* vtbl */, ARM::VTBL4, Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, },
15362 { 4070 /* vtbl */, ARM::VTBL1, Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, },
15363 { 4070 /* vtbl */, ARM::VTBL3, Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, },
15364 { 4075 /* vtbx */, ARM::VTBX2, Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, },
15365 { 4075 /* vtbx */, ARM::VTBX4, Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, },
15366 { 4075 /* vtbx */, ARM::VTBX1, Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, },
15367 { 4075 /* vtbx */, ARM::VTBX3, Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, },
15368 { 4080 /* vtrn */, ARM::VTRNq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15369 { 4080 /* vtrn */, ARM::VTRNd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15370 { 4080 /* vtrn */, ARM::VTRNq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15371 { 4080 /* vtrn */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15372 { 4080 /* vtrn */, ARM::VTRNq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15373 { 4080 /* vtrn */, ARM::VTRNd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15374 { 4085 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15375 { 4085 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15376 { 4085 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15377 { 4085 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15378 { 4085 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15379 { 4085 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15380 { 4085 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
15381 { 4085 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
15382 { 4085 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
15383 { 4085 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
15384 { 4085 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15385 { 4085 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15386 { 4090 /* vudot */, ARM::VUDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15387 { 4090 /* vudot */, ARM::VUDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15388 { 4090 /* vudot */, ARM::VUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15389 { 4090 /* vudot */, ARM::VUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15390 { 4096 /* vummla */, ARM::VUMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15391 { 4103 /* vusdot */, ARM::VUSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15392 { 4103 /* vusdot */, ARM::VUSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, },
15393 { 4103 /* vusdot */, ARM::VUSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15394 { 4103 /* vusdot */, ARM::VUSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
15395 { 4110 /* vusmmla */, ARM::VUSMMLA, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, AMFBS_HasMatMulInt8, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, },
15396 { 4118 /* vuzp */, ARM::VUZPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15397 { 4118 /* vuzp */, ARM::VUZPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15398 { 4118 /* vuzp */, ARM::VUZPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15399 { 4118 /* vuzp */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15400 { 4118 /* vuzp */, ARM::VUZPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15401 { 4118 /* vuzp */, ARM::VUZPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15402 { 4123 /* vzip */, ARM::VZIPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
15403 { 4123 /* vzip */, ARM::VZIPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
15404 { 4123 /* vzip */, ARM::VZIPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
15405 { 4123 /* vzip */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
15406 { 4123 /* vzip */, ARM::VZIPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, },
15407 { 4123 /* vzip */, ARM::VZIPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, },
15408 { 4128 /* wfe */, ARM::tHINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
15409 { 4128 /* wfe */, ARM::HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
15410 { 4128 /* wfe */, ARM::t2HINT, Convert__imm_95_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
15411 { 4132 /* wfi */, ARM::tHINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
15412 { 4132 /* wfi */, ARM::HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
15413 { 4132 /* wfi */, ARM::t2HINT, Convert__imm_95_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
15414 { 4136 /* wls */, ARM::t2WLS, Convert__Reg1_0__Reg1_1__WLSLabel1_2, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB, { MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15415 { 4140 /* wlstp */, ARM::MVE_WLSTP_16, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15416 { 4140 /* wlstp */, ARM::MVE_WLSTP_32, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15417 { 4140 /* wlstp */, ARM::MVE_WLSTP_64, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_64, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15418 { 4140 /* wlstp */, ARM::MVE_WLSTP_8, Convert__Reg1_1__Reg1_2__WLSLabel1_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_GPRlr, MCK_rGPR, MCK_WLSLabel }, },
15419 { 4146 /* yield */, ARM::tHINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb_HasV6M, { MCK_CondCode }, },
15420 { 4146 /* yield */, ARM::HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsARM_HasV6K, { MCK_CondCode }, },
15421 { 4146 /* yield */, ARM::t2HINT, Convert__imm_95_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w }, },
15422};
15423
15424#include "llvm/Support/Debug.h"
15425#include "llvm/Support/Format.h"
15426
15427unsigned ARMAsmParser::
15428MatchInstructionImpl(const OperandVector &Operands,
15429 MCInst &Inst,
15430 SmallVectorImpl<NearMissInfo> *NearMisses,
15431 bool matchingInlineAsm, unsigned VariantID) {
15432 // Get the current feature set.
15433 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
15434
15435 // Get the instruction mnemonic, which is the first token.
15436 StringRef Mnemonic = ((ARMOperand &)*Operands[0]).getToken();
15437
15438 // Process all MnemonicAliases to remap the mnemonic.
15439 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
15440
15441 SmallBitVector OptionalOperandsMask(19);
15442 // Find the appropriate table for this asm variant.
15443 const MatchEntry *Start, *End;
15444 switch (VariantID) {
15445 default: llvm_unreachable("invalid variant!");
15446 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
15447 }
15448 // Search the table.
15449 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
15450
15451 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
15452 std::distance(MnemonicRange.first, MnemonicRange.second) <<
15453 " encodings with mnemonic '" << Mnemonic << "'\n");
15454
15455 // Return a more specific error code if no mnemonics match.
15456 if (MnemonicRange.first == MnemonicRange.second)
15457 return Match_MnemonicFail;
15458
15459 // First operand near-miss of each opcode that mismatched in
15460 // more than one operand. Used only if no opcode yields a
15461 // near-miss of its own (see below).
15462 SmallVector<NearMissInfo, 4> MultiMismatchFallback;
15463
15464 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
15465 it != ie; ++it) {
15466 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
15467 bool HasRequiredFeatures =
15468 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
15469 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
15470 << MII.getName(it->Opcode) << "\n");
15471 // Some state to record ways in which this instruction did not match.
15472 NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();
15473 NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();
15474 NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();
15475 NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();
15476 bool MultipleInvalidOperands = false;
15477 // equal_range guarantees that instruction mnemonic matches.
15478 assert(Mnemonic == it->getMnemonic());
15479 OptionalOperandsMask.reset(0, 19);
15480 unsigned ActualIdx = 1;
15481 for (unsigned FormalIdx = 0; FormalIdx != 18; ++FormalIdx) {
15482 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
15483 DEBUG_WITH_TYPE("asm-matcher",
15484 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
15485 << " against actual operand at index " << ActualIdx);
15486 if (ActualIdx < Operands.size())
15487 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
15488 Operands[ActualIdx]->print(dbgs(), getContext().getAsmInfo()); dbgs() << "): ");
15489 else
15490 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
15491 if (ActualIdx >= Operands.size()) {
15492 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
15493 bool ThisOperandValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
15494 if (!ThisOperandValid) {
15495 if (!OperandNearMiss) {
15496 // Record info about match failure for later use.
15497 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "recording too-few-operands near miss\n");
15498 OperandNearMiss =
15499 NearMissInfo::getTooFewOperands(Formal, it->Opcode);
15500 } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {
15501 // If more than one operand is invalid, give up on this match entry.
15502 DEBUG_WITH_TYPE(
15503 "asm-matcher",
15504 dbgs() << "second invalid operand, giving up on this opcode\n");
15505 MultipleInvalidOperands = true;
15506 break;
15507 }
15508 } else {
15509 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "but formal operand not required\n");
15510 if (isSubclass(Formal, OptionalMatchClass)) {
15511 OptionalOperandsMask.set(FormalIdx + 1);
15512 }
15513 }
15514 continue;
15515 }
15516 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
15517 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
15518 if (Diag == Match_Success) {
15519 DEBUG_WITH_TYPE("asm-matcher",
15520 dbgs() << "match success using generic matcher\n");
15521 ++ActualIdx;
15522 continue;
15523 }
15524 // If the generic handler indicates an invalid operand
15525 // failure, check for a special case.
15526 if (Diag != Match_Success) {
15527 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
15528 if (TargetDiag == Match_Success) {
15529 DEBUG_WITH_TYPE("asm-matcher",
15530 dbgs() << "match success using target matcher\n");
15531 ++ActualIdx;
15532 continue;
15533 }
15534 // If the target matcher returned a specific error code use
15535 // that, else use the one from the generic matcher.
15536 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
15537 Diag = TargetDiag;
15538 }
15539 // If current formal operand wasn't matched and it is optional
15540 // then try to match next formal operand
15541 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
15542 OptionalOperandsMask.set(FormalIdx + 1);
15543 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
15544 continue;
15545 }
15546 if (!OperandNearMiss) {
15547 // If this is the first invalid operand we have seen, record some
15548 // information about it.
15549 DEBUG_WITH_TYPE(
15550 "asm-matcher",
15551 dbgs()
15552 << "operand match failed, recording near-miss with diag code "
15553 << Diag << "\n");
15554 OperandNearMiss =
15555 NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);
15556 ++ActualIdx;
15557 } else {
15558 // If more than one operand is invalid, give up on this match entry.
15559 DEBUG_WITH_TYPE(
15560 "asm-matcher",
15561 dbgs() << "second operand mismatch, skipping this opcode\n");
15562 MultipleInvalidOperands = true;
15563 break;
15564 }
15565 }
15566
15567 // Reject surplus operands as one more operand mismatch.
15568 if (!MultipleInvalidOperands && ActualIdx < Operands.size()) {
15569 if (!OperandNearMiss) {
15570 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "too many operands, recording near-miss at index "
15571 << ActualIdx << "\n");
15572 OperandNearMiss = NearMissInfo::getMissedOperand(
15573 Match_InvalidOperand, InvalidMatchClass, it->Opcode, ActualIdx);
15574 } else {
15575 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "too many operands after an earlier mismatch, skipping this opcode\n");
15576 MultipleInvalidOperands = true;
15577 }
15578 }
15579
15580 if (MultipleInvalidOperands) {
15581 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
15582 "operand mismatches, ignoring "
15583 "this opcode\n");
15584 // Too many invalid operands to report a single near-miss;
15585 // keep the first one as a fallback in case no opcode
15586 // matches more closely.
15587 if (OperandNearMiss)
15588 MultiMismatchFallback.push_back(OperandNearMiss);
15589 continue;
15590 }
15591 if (!HasRequiredFeatures) {
15592 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
15593 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
15594 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
15595 if (NewMissingFeatures[I])
15596 dbgs() << ' ' << I;
15597 dbgs() << "\n");
15598 FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);
15599 }
15600
15601 Inst.clear();
15602
15603 Inst.setOpcode(it->Opcode);
15604 // We have a potential match but have not rendered the operands.
15605 // Check the target predicate to handle any context sensitive
15606 // constraints.
15607 // For example, Ties that are referenced multiple times must be
15608 // checked here to ensure the input is the same for each match
15609 // constraints. If we leave it any later the ties will have been
15610 // canonicalized
15611 unsigned MatchResult;
15612 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
15613 Inst.clear();
15614 DEBUG_WITH_TYPE(
15615 "asm-matcher",
15616 dbgs() << "Early target match predicate failed with diag code "
15617 << MatchResult << "\n");
15618 EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
15619 }
15620
15621 // If we did not successfully match the operands, then we can't convert to
15622 // an MCInst, so bail out on this instruction variant now.
15623 if (OperandNearMiss) {
15624 // If the operand mismatch was the only problem, report it as a near-miss.
15625 if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) {
15626 DEBUG_WITH_TYPE(
15627 "asm-matcher",
15628 dbgs()
15629 << "Opcode result: one mismatched operand, adding near-miss\n");
15630 NearMisses->push_back(OperandNearMiss);
15631 } else {
15632 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
15633 "types of mismatch, so not "
15634 "reporting near-miss\n");
15635 }
15636 continue;
15637 }
15638
15639 unsigned DefaultsOffset[19] = { 0 };
15640 assert(OptionalOperandsMask.size() == 19);
15641 for (unsigned i = 0, NumDefaults = 0; i < 18; ++i) {
15642 NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
15643 DefaultsOffset[i + 1] = NumDefaults;
15644 }
15645
15646 if (matchingInlineAsm) {
15647 convertToMapAndConstraints(it->ConvertFn, Operands);
15648 return Match_Success;
15649 }
15650
15651 // We have selected a definite instruction, convert the parsed
15652 // operands into the appropriate MCInst.
15653 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,
15654 OptionalOperandsMask, DefaultsOffset);
15655
15656 // We have a potential match. Check the target predicate to
15657 // handle any context sensitive constraints.
15658 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
15659 DEBUG_WITH_TYPE("asm-matcher",
15660 dbgs() << "Target match predicate failed with diag code "
15661 << MatchResult << "\n");
15662 Inst.clear();
15663 LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);
15664 }
15665
15666 int NumNearMisses = ((int)(bool)OperandNearMiss +
15667 (int)(bool)FeaturesNearMiss +
15668 (int)(bool)EarlyPredicateNearMiss +
15669 (int)(bool)LatePredicateNearMiss);
15670 if (NumNearMisses == 1) {
15671 // We had exactly one type of near-miss, so add that to the list.
15672 assert(!OperandNearMiss && "OperandNearMiss was handled earlier");
15673 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: found one type of "
15674 "mismatch, so reporting a "
15675 "near-miss\n");
15676 if (NearMisses && FeaturesNearMiss)
15677 NearMisses->push_back(FeaturesNearMiss);
15678 else if (NearMisses && EarlyPredicateNearMiss)
15679 NearMisses->push_back(EarlyPredicateNearMiss);
15680 else if (NearMisses && LatePredicateNearMiss)
15681 NearMisses->push_back(LatePredicateNearMiss);
15682
15683 continue;
15684 } else if (NumNearMisses > 1) {
15685 // This instruction missed in more than one way, so ignore it.
15686 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
15687 "types of mismatch, so not "
15688 "reporting near-miss\n");
15689 continue;
15690 }
15691 std::string Info;
15692 if (!getParser().getTargetParser().getTargetOptions().MCNoDeprecatedWarn &&
15693 MII.getDeprecatedInfo(Inst, getSTI(), Info)) {
15694 SMLoc Loc = ((ARMOperand &)*Operands[0]).getStartLoc();
15695 getParser().Warning(Loc, Info, {});
15696 }
15697 DEBUG_WITH_TYPE(
15698 "asm-matcher",
15699 dbgs() << "Opcode result: complete match, selecting this opcode\n");
15700 return Match_Success;
15701 }
15702
15703 // No instruction variants matched exactly. If nothing produced
15704 // a near-miss, fall back to the multi-mismatch list so we can
15705 // still give a specific diagnostic rather than a generic
15706 // "invalid instruction".
15707 if (NearMisses && NearMisses->empty())
15708 NearMisses->append(MultiMismatchFallback.begin(),
15709 MultiMismatchFallback.end());
15710 return Match_NearMisses;
15711}
15712
15713namespace {
15714 struct OperandMatchEntry {
15715 uint16_t Mnemonic;
15716 uint8_t OperandMask;
15717 uint16_t Class;
15718 uint8_t RequiredFeaturesIdx;
15719
15720 StringRef getMnemonic() const {
15721 return StringRef(MnemonicTable + Mnemonic + 1,
15722 MnemonicTable[Mnemonic]);
15723 }
15724 };
15725
15726 // Predicate for searching for an opcode.
15727 struct LessOpcodeOperand {
15728 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
15729 return LHS.getMnemonic() < RHS;
15730 }
15731 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
15732 return LHS < RHS.getMnemonic();
15733 }
15734 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
15735 return LHS.getMnemonic() < RHS.getMnemonic();
15736 }
15737 };
15738} // end anonymous namespace
15739
15740static const OperandMatchEntry OperandMatchTable[891] = {
15741 /* Operand List Mnemonic, Mask, Operand Class, Features */
15742 { 10 /* adc */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15743 { 10 /* adc */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15744 { 14 /* add */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15745 { 14 /* add */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15746 { 50 /* and */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15747 { 50 /* and */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15748 { 77 /* bfc */, 6 /* 1, 2 */, MCK_Bitfield, AMFBS_IsThumb2 },
15749 { 77 /* bfc */, 6 /* 1, 2 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 },
15750 { 81 /* bfcsel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_IsThumb2_HasV8_1MMainline_HasLOB },
15751 { 88 /* bfi */, 12 /* 2, 3 */, MCK_Bitfield, AMFBS_IsThumb2 },
15752 { 88 /* bfi */, 12 /* 2, 3 */, MCK_Bitfield, AMFBS_IsARM_HasV6T2 },
15753 { 105 /* bic */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15754 { 105 /* bic */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15755 { 158 /* cdp */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15756 { 158 /* cdp */, 60 /* 2, 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15757 { 158 /* cdp */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15758 { 158 /* cdp */, 60 /* 2, 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15759 { 162 /* cdp2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15760 { 162 /* cdp2 */, 28 /* 2, 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15761 { 162 /* cdp2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15762 { 162 /* cdp2 */, 60 /* 2, 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15763 { 167 /* cinc */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15764 { 172 /* cinv */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15765 { 199 /* cmn */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
15766 { 203 /* cmp */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
15767 { 207 /* cneg */, 4 /* 2 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15768 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb },
15769 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM },
15770 { 212 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass },
15771 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsARM },
15772 { 212 /* cps */, 2 /* 1 */, MCK_ProcIFlags, AMFBS_IsThumb2_IsNotMClass },
15773 { 212 /* cps */, 4 /* 2 */, MCK_ProcIFlags, AMFBS_IsThumb2 },
15774 { 266 /* csel */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
15775 { 271 /* cset */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15776 { 276 /* csetm */, 2 /* 1 */, MCK_CondCodeNoALInv, AMFBS_HasV8_1MMainline },
15777 { 282 /* csinc */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
15778 { 288 /* csinv */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
15779 { 294 /* csneg */, 8 /* 3 */, MCK_CondCodeNoAL, AMFBS_HasV8_1MMainline },
15780 { 300 /* cx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15781 { 304 /* cx1a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15782 { 309 /* cx1d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15783 { 314 /* cx1da */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15784 { 320 /* cx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15785 { 324 /* cx2a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15786 { 329 /* cx2d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15787 { 334 /* cx2da */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15788 { 340 /* cx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15789 { 344 /* cx3a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15790 { 349 /* cx3d */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE },
15791 { 354 /* cx3da */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE },
15792 { 396 /* dmb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB },
15793 { 396 /* dmb */, 3 /* 0, 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB },
15794 { 396 /* dmb */, 6 /* 1, 2 */, MCK_MemBarrierOpt, AMFBS_HasDB },
15795 { 400 /* dsb */, 1 /* 0 */, MCK_MemBarrierOpt, AMFBS_IsARM_HasDB },
15796 { 400 /* dsb */, 3 /* 0, 1 */, MCK_MemBarrierOpt, AMFBS_IsThumb_HasDB },
15797 { 400 /* dsb */, 6 /* 1, 2 */, MCK_MemBarrierOpt, AMFBS_HasDB },
15798 { 404 /* eor */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15799 { 404 /* eor */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15800 { 443 /* fconstd */, 6 /* 1, 2 */, MCK_FPImm, AMFBS_HasVFP3 },
15801 { 451 /* fconsts */, 6 /* 1, 2 */, MCK_FPImm, AMFBS_HasVFP3 },
15802 { 535 /* isb */, 1 /* 0 */, MCK_InstSyncBarrierOpt, AMFBS_IsARM_HasDB },
15803 { 535 /* isb */, 3 /* 0, 1 */, MCK_InstSyncBarrierOpt, AMFBS_IsThumb_HasDB },
15804 { 535 /* isb */, 6 /* 1, 2 */, MCK_InstSyncBarrierOpt, AMFBS_HasDB },
15805 { 539 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsThumb2 },
15806 { 539 /* it */, 2 /* 1 */, MCK_ITCondCode, AMFBS_IsARM },
15807 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15808 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15809 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15810 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15811 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15812 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15813 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15814 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15815 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15816 { 588 /* ldc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
15817 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15818 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15819 { 588 /* ldc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
15820 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15821 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15822 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15823 { 588 /* ldc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15824 { 588 /* ldc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15825 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15826 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15827 { 592 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15828 { 592 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15829 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15830 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15831 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15832 { 592 /* ldc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
15833 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15834 { 592 /* ldc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15835 { 592 /* ldc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15836 { 592 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15837 { 592 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15838 { 592 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15839 { 592 /* ldc2 */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15840 { 592 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15841 { 592 /* ldc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15842 { 592 /* ldc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15843 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15844 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15845 { 597 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15846 { 597 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15847 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15848 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15849 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15850 { 597 /* ldc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
15851 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15852 { 597 /* ldc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15853 { 597 /* ldc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15854 { 597 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15855 { 597 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15856 { 597 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15857 { 597 /* ldc2l */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15858 { 597 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15859 { 597 /* ldc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15860 { 597 /* ldc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15861 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15862 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15863 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15864 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15865 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15866 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15867 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15868 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15869 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15870 { 603 /* ldcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
15871 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15872 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15873 { 603 /* ldcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
15874 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15875 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15876 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15877 { 603 /* ldcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15878 { 603 /* ldcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15879 { 630 /* ldr */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15880 { 634 /* ldrb */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15881 { 639 /* ldrbt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15882 { 645 /* ldrd */, 24 /* 3, 4 */, MCK_AM3Offset, AMFBS_IsARM },
15883 { 677 /* ldrh */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
15884 { 682 /* ldrht */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15885 { 688 /* ldrsb */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
15886 { 694 /* ldrsbt */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15887 { 701 /* ldrsh */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
15888 { 707 /* ldrsht */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
15889 { 714 /* ldrt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
15890 { 745 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15891 { 745 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15892 { 745 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15893 { 745 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15894 { 745 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15895 { 745 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15896 { 745 /* mcr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15897 { 745 /* mcr */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15898 { 749 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM },
15899 { 749 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM },
15900 { 749 /* mcr2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15901 { 749 /* mcr2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15902 { 749 /* mcr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15903 { 749 /* mcr2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15904 { 749 /* mcr2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15905 { 749 /* mcr2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15906 { 754 /* mcrr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15907 { 754 /* mcrr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15908 { 754 /* mcrr */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15909 { 754 /* mcrr */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15910 { 759 /* mcrr2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15911 { 759 /* mcrr2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15912 { 759 /* mcrr2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15913 { 759 /* mcrr2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15914 { 773 /* mov */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15915 { 792 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15916 { 792 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15917 { 792 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15918 { 792 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15919 { 792 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15920 { 792 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15921 { 792 /* mrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15922 { 792 /* mrc */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15923 { 796 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM },
15924 { 796 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM },
15925 { 796 /* mrc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15926 { 796 /* mrc2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15927 { 796 /* mrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15928 { 796 /* mrc2 */, 24 /* 3, 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15929 { 796 /* mrc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15930 { 796 /* mrc2 */, 56 /* 3, 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15931 { 801 /* mrrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15932 { 801 /* mrrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsARM },
15933 { 801 /* mrrc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15934 { 801 /* mrrc */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15935 { 806 /* mrrc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15936 { 806 /* mrrc2 */, 16 /* 4 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15937 { 806 /* mrrc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2_PreV8 },
15938 { 806 /* mrrc2 */, 48 /* 4, 5 */, MCK_CoprocReg, AMFBS_IsThumb2_PreV8 },
15939 { 812 /* mrs */, 6 /* 1, 2 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization },
15940 { 812 /* mrs */, 6 /* 1, 2 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass },
15941 { 812 /* mrs */, 6 /* 1, 2 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization },
15942 { 816 /* msr */, 3 /* 0, 1 */, MCK_BankedReg, AMFBS_IsThumb_HasVirtualization },
15943 { 816 /* msr */, 3 /* 0, 1 */, MCK_BankedReg, AMFBS_IsARM_HasVirtualization },
15944 { 816 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsThumb2_IsNotMClass },
15945 { 816 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsThumb_IsMClass },
15946 { 816 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsARM },
15947 { 816 /* msr */, 3 /* 0, 1 */, MCK_MSRMask, AMFBS_IsARM },
15948 { 816 /* msr */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
15949 { 824 /* mvn */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15950 { 840 /* orr */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15951 { 840 /* orr */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15952 { 860 /* pkhbt */, 24 /* 3, 4 */, MCK_PKHLSLImm, AMFBS_HasDSP_IsThumb2 },
15953 { 860 /* pkhbt */, 24 /* 3, 4 */, MCK_PKHLSLImm, AMFBS_IsARM_HasV6 },
15954 { 866 /* pkhtb */, 24 /* 3, 4 */, MCK_PKHASRImm, AMFBS_HasDSP_IsThumb2 },
15955 { 866 /* pkhtb */, 24 /* 3, 4 */, MCK_PKHASRImm, AMFBS_IsARM_HasV6 },
15956 { 1011 /* rsb */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15957 { 1011 /* rsb */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15958 { 1015 /* rsc */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15959 { 1015 /* rsc */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15960 { 1040 /* sbc */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
15961 { 1040 /* sbc */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
15962 { 1058 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsThumb_IsNotMClass },
15963 { 1058 /* setend */, 1 /* 0 */, MCK_SetEndImm, AMFBS_IsARM },
15964 { 1521 /* ssat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsThumb2 },
15965 { 1521 /* ssat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 },
15966 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15967 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15968 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15969 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15970 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15971 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15972 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15973 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15974 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15975 { 1556 /* stc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
15976 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15977 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15978 { 1556 /* stc */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
15979 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15980 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
15981 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
15982 { 1556 /* stc */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
15983 { 1556 /* stc */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
15984 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15985 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15986 { 1560 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15987 { 1560 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15988 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15989 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15990 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15991 { 1560 /* stc2 */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
15992 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15993 { 1560 /* stc2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
15994 { 1560 /* stc2 */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
15995 { 1560 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15996 { 1560 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
15997 { 1560 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
15998 { 1560 /* stc2 */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
15999 { 1560 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16000 { 1560 /* stc2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16001 { 1560 /* stc2 */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16002 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16003 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16004 { 1565 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16005 { 1565 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16006 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16007 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16008 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16009 { 1565 /* stc2l */, 8 /* 3 */, MCK_CoprocOption, AMFBS_IsARM_PreV8 },
16010 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16011 { 1565 /* stc2l */, 1 /* 0 */, MCK_CoprocNum, AMFBS_IsARM_PreV8 },
16012 { 1565 /* stc2l */, 2 /* 1 */, MCK_CoprocReg, AMFBS_IsARM_PreV8 },
16013 { 1565 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16014 { 1565 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16015 { 1565 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16016 { 1565 /* stc2l */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_PreV8_IsThumb2 },
16017 { 1565 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16018 { 1565 /* stc2l */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_PreV8_IsThumb2 },
16019 { 1565 /* stc2l */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_PreV8_IsThumb2 },
16020 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16021 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16022 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16023 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16024 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16025 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16026 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16027 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16028 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16029 { 1571 /* stcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsARM },
16030 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16031 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16032 { 1571 /* stcl */, 24 /* 3, 4 */, MCK_CoprocOption, AMFBS_IsThumb2 },
16033 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16034 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsARM },
16035 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsARM },
16036 { 1571 /* stcl */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_IsThumb2 },
16037 { 1571 /* stcl */, 6 /* 1, 2 */, MCK_CoprocReg, AMFBS_IsThumb2 },
16038 { 1639 /* str */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16039 { 1643 /* strb */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16040 { 1648 /* strbt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16041 { 1654 /* strd */, 24 /* 3, 4 */, MCK_AM3Offset, AMFBS_IsARM },
16042 { 1686 /* strh */, 12 /* 2, 3 */, MCK_AM3Offset, AMFBS_IsARM },
16043 { 1691 /* strht */, 12 /* 2, 3 */, MCK_PostIdxReg, AMFBS_IsARM },
16044 { 1697 /* strt */, 12 /* 2, 3 */, MCK_PostIdxRegShifted, AMFBS_IsARM },
16045 { 1702 /* sub */, 14 /* 1, 2, 3 */, MCK_ModImm, AMFBS_IsARM },
16046 { 1702 /* sub */, 28 /* 2, 3, 4 */, MCK_ModImm, AMFBS_IsARM },
16047 { 1729 /* sxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16048 { 1729 /* sxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16049 { 1735 /* sxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16050 { 1735 /* sxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16051 { 1743 /* sxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16052 { 1743 /* sxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16053 { 1749 /* sxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
16054 { 1749 /* sxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16055 { 1749 /* sxtb */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
16056 { 1754 /* sxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16057 { 1754 /* sxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16058 { 1754 /* sxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16059 { 1761 /* sxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
16060 { 1761 /* sxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16061 { 1761 /* sxth */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
16062 { 1774 /* teq */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
16063 { 1783 /* tsb */, 1 /* 0 */, MCK_TraceSyncBarrierOpt, AMFBS_IsARM_HasV8_4a },
16064 { 1783 /* tsb */, 3 /* 0, 1 */, MCK_TraceSyncBarrierOpt, AMFBS_IsThumb_HasV8_4a },
16065 { 1787 /* tst */, 6 /* 1, 2 */, MCK_ModImm, AMFBS_IsARM },
16066 { 1995 /* usat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsThumb2 },
16067 { 1995 /* usat */, 24 /* 3, 4 */, MCK_ShifterImm, AMFBS_IsARM_HasV6 },
16068 { 2025 /* uxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16069 { 2025 /* uxtab */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16070 { 2031 /* uxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16071 { 2031 /* uxtab16 */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16072 { 2039 /* uxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16073 { 2039 /* uxtah */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16074 { 2045 /* uxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
16075 { 2045 /* uxtb */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16076 { 2045 /* uxtb */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
16077 { 2050 /* uxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16078 { 2050 /* uxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
16079 { 2050 /* uxtb16 */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16080 { 2057 /* uxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsThumb2 },
16081 { 2057 /* uxth */, 12 /* 2, 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
16082 { 2057 /* uxth */, 24 /* 3, 4 */, MCK_RotImm, AMFBS_IsThumb2 },
16083 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16084 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16085 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16086 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16087 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16088 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16089 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16090 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16091 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16092 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16093 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16094 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16095 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16096 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16097 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16098 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16099 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16100 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16101 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16102 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16103 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16104 { 2260 /* vcmp */, 6 /* 1, 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16105 { 2334 /* vcx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16106 { 2334 /* vcx1 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16107 { 2334 /* vcx1 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16108 { 2339 /* vcx1a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16109 { 2339 /* vcx1a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16110 { 2339 /* vcx1a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16111 { 2345 /* vcx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16112 { 2345 /* vcx2 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16113 { 2345 /* vcx2 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16114 { 2350 /* vcx2a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16115 { 2350 /* vcx2a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16116 { 2350 /* vcx2a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16117 { 2356 /* vcx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16118 { 2356 /* vcx3 */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16119 { 2356 /* vcx3 */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16120 { 2361 /* vcx3a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16121 { 2361 /* vcx3a */, 1 /* 0 */, MCK_CoprocNum, AMFBS_HasCDE_HasFPRegs },
16122 { 2361 /* vcx3a */, 3 /* 0, 1 */, MCK_CoprocNum, AMFBS_HasCDE_HasMVEInt },
16123 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16124 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16125 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16126 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16127 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16128 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16129 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16130 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16131 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16132 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16133 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16134 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16135 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16136 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16137 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16138 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16139 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16140 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16141 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16142 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16143 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16144 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16145 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16146 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16147 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16148 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16149 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16150 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16151 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16152 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16153 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16154 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16155 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16156 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16157 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16158 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16159 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16160 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16161 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16162 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16163 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16164 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16165 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16166 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16167 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16168 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16169 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16170 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16171 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16172 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16173 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16174 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16175 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16176 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16177 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16178 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16179 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16180 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16181 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16182 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16183 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16184 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16185 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16186 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16187 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16188 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16189 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16190 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16191 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDAllLanes, AMFBS_HasNEON },
16192 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16193 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16194 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16195 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16196 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16197 { 2500 /* vld1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16198 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16199 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16200 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16201 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16202 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16203 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16204 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16205 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16206 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16207 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16208 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16209 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16210 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16211 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16212 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16213 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16214 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16215 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16216 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16217 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16218 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16219 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16220 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16221 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16222 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16223 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16224 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16225 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16226 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16227 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16228 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16229 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16230 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16231 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16232 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16233 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16234 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16235 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16236 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16237 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16238 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16239 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16240 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16241 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16242 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16243 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16244 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16245 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16246 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16247 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON },
16248 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16249 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16250 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16251 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpacedAllLanes, AMFBS_HasNEON },
16252 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16253 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16254 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16255 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16256 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16257 { 2505 /* vld2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16258 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16259 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16260 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16261 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16262 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16263 { 2510 /* vld20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16264 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16265 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16266 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16267 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16268 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16269 { 2516 /* vld21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16270 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16271 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16272 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16273 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16274 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16275 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16276 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16277 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16278 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16279 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16280 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16281 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16282 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16283 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16284 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16285 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16286 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16287 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16288 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16289 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16290 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16291 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16292 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16293 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16294 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16295 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16296 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16297 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16298 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16299 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16300 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16301 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16302 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16303 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16304 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16305 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16306 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16307 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16308 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16309 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16310 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16311 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16312 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDAllLanes, AMFBS_HasNEON },
16313 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16314 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16315 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16316 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16317 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16318 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16319 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16320 { 2522 /* vld3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16321 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16322 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16323 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16324 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16325 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16326 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16327 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16328 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16329 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16330 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16331 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16332 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16333 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16334 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16335 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16336 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16337 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16338 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16339 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16340 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16341 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16342 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16343 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16344 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16345 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16346 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16347 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16348 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16349 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16350 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16351 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16352 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16353 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16354 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16355 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16356 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16357 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16358 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16359 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16360 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16361 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16362 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16363 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16364 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16365 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16366 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16367 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16368 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16369 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16370 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16371 { 2527 /* vld4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16372 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16373 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16374 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16375 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16376 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16377 { 2532 /* vld40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16378 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16379 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16380 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16381 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16382 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16383 { 2538 /* vld41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16384 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16385 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16386 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16387 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16388 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16389 { 2544 /* vld42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16390 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16391 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16392 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16393 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16394 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16395 { 2550 /* vld43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16396 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasNEON },
16397 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasNEON },
16398 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasVFP3 },
16399 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasVFP3_HasDPVFP },
16400 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasFullFP16 },
16401 { 2937 /* vmov */, 12 /* 2, 3 */, MCK_FPImm, AMFBS_HasMVEInt },
16402 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16403 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16404 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16405 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16406 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16407 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt },
16408 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16409 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16410 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16411 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16412 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16413 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedU, AMFBS_HasMVEInt },
16414 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16415 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16416 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16417 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16418 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16419 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16420 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16421 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedI, AMFBS_HasMVEInt },
16422 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16423 { 3121 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedFP, AMFBS_HasMVEFloat },
16424 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16425 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16426 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16427 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16428 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16429 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16430 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16431 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16432 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16433 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16434 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16435 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16436 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16437 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16438 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16439 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16440 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16441 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16442 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16443 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16444 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16445 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16446 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16447 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16448 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16449 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16450 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDHWordIndexed, AMFBS_HasNEON },
16451 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16452 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16453 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16454 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16455 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16456 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16457 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16458 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16459 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16460 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDWordIndexed, AMFBS_HasNEON },
16461 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16462 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16463 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16464 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16465 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16466 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16467 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16468 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16469 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16470 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16471 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16472 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16473 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16474 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16475 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16476 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneD, AMFBS_HasNEON },
16477 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16478 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListOneDByteIndexed, AMFBS_HasNEON },
16479 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16480 { 3935 /* vst1 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16481 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16482 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16483 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16484 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16485 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16486 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16487 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16488 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16489 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16490 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16491 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16492 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16493 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16494 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16495 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16496 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16497 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16498 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16499 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16500 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16501 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16502 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDHWordIndexed, AMFBS_HasNEON },
16503 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16504 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQHWordIndexed, AMFBS_HasNEON },
16505 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16506 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16507 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16508 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16509 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16510 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16511 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16512 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDWordIndexed, AMFBS_HasNEON },
16513 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16514 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoQWordIndexed, AMFBS_HasNEON },
16515 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16516 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPair, AMFBS_HasNEON },
16517 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16518 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListDPairSpaced, AMFBS_HasNEON },
16519 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16520 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16521 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16522 { 3940 /* vst2 */, 6 /* 1, 2 */, MCK_VecListTwoDByteIndexed, AMFBS_HasNEON },
16523 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16524 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16525 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16526 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16527 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16528 { 3945 /* vst20 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16529 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16530 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16531 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16532 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16533 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16534 { 3951 /* vst21 */, 2 /* 1 */, MCK_VecListTwoMQ, AMFBS_HasMVEInt },
16535 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16536 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16537 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16538 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16539 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16540 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16541 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16542 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16543 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16544 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16545 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16546 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16547 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16548 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16549 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDHWordIndexed, AMFBS_HasNEON },
16550 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16551 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16552 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16553 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQHWordIndexed, AMFBS_HasNEON },
16554 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16555 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16556 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16557 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDWordIndexed, AMFBS_HasNEON },
16558 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16559 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16560 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16561 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQWordIndexed, AMFBS_HasNEON },
16562 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16563 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeD, AMFBS_HasNEON },
16564 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16565 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeDByteIndexed, AMFBS_HasNEON },
16566 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16567 { 3957 /* vst3 */, 6 /* 1, 2 */, MCK_VecListThreeQ, AMFBS_HasNEON },
16568 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16569 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16570 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16571 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16572 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16573 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16574 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16575 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16576 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16577 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16578 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16579 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16580 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16581 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16582 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDHWordIndexed, AMFBS_HasNEON },
16583 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16584 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16585 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16586 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQHWordIndexed, AMFBS_HasNEON },
16587 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16588 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16589 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16590 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDWordIndexed, AMFBS_HasNEON },
16591 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16592 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16593 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16594 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQWordIndexed, AMFBS_HasNEON },
16595 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16596 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourD, AMFBS_HasNEON },
16597 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16598 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourDByteIndexed, AMFBS_HasNEON },
16599 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16600 { 3962 /* vst4 */, 6 /* 1, 2 */, MCK_VecListFourQ, AMFBS_HasNEON },
16601 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16602 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16603 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16604 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16605 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16606 { 3967 /* vst40 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16607 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16608 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16609 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16610 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16611 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16612 { 3973 /* vst41 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16613 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16614 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16615 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16616 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16617 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16618 { 3979 /* vst42 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16619 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16620 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16621 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16622 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16623 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16624 { 3985 /* vst43 */, 2 /* 1 */, MCK_VecListFourMQ, AMFBS_HasMVEInt },
16625 { 4070 /* vtbl */, 12 /* 2, 3 */, MCK_VecListDPair, AMFBS_HasNEON },
16626 { 4070 /* vtbl */, 12 /* 2, 3 */, MCK_VecListFourD, AMFBS_HasNEON },
16627 { 4070 /* vtbl */, 12 /* 2, 3 */, MCK_VecListOneD, AMFBS_HasNEON },
16628 { 4070 /* vtbl */, 12 /* 2, 3 */, MCK_VecListThreeD, AMFBS_HasNEON },
16629 { 4075 /* vtbx */, 12 /* 2, 3 */, MCK_VecListDPair, AMFBS_HasNEON },
16630 { 4075 /* vtbx */, 12 /* 2, 3 */, MCK_VecListFourD, AMFBS_HasNEON },
16631 { 4075 /* vtbx */, 12 /* 2, 3 */, MCK_VecListOneD, AMFBS_HasNEON },
16632 { 4075 /* vtbx */, 12 /* 2, 3 */, MCK_VecListThreeD, AMFBS_HasNEON },
16633};
16634
16635ParseStatus ARMAsmParser::
16636tryCustomParseOperand(OperandVector &Operands,
16637 unsigned MCK) {
16638
16639 switch(MCK) {
16640 case MCK_AM3Offset:
16641 return parseAM3Offset(Operands);
16642 case MCK_BankedReg:
16643 return parseBankedRegOperand(Operands);
16644 case MCK_Bitfield:
16645 return parseBitfield(Operands);
16646 case MCK_CoprocNum:
16647 return parseCoprocNumOperand(Operands);
16648 case MCK_CoprocOption:
16649 return parseCoprocOptionOperand(Operands);
16650 case MCK_CoprocReg:
16651 return parseCoprocRegOperand(Operands);
16652 case MCK_FPImm:
16653 return parseFPImm(Operands);
16654 case MCK_InstSyncBarrierOpt:
16655 return parseInstSyncBarrierOptOperand(Operands);
16656 case MCK_MSRMask:
16657 return parseMSRMaskOperand(Operands);
16658 case MCK_MemBarrierOpt:
16659 return parseMemBarrierOptOperand(Operands);
16660 case MCK_ModImm:
16661 return parseModImm(Operands);
16662 case MCK_PKHASRImm:
16663 return parsePKHASRImm(Operands);
16664 case MCK_PKHLSLImm:
16665 return parsePKHLSLImm(Operands);
16666 case MCK_PostIdxReg:
16667 return parsePostIdxReg(Operands);
16668 case MCK_PostIdxRegShifted:
16669 return parsePostIdxReg(Operands);
16670 case MCK_ProcIFlags:
16671 return parseProcIFlagsOperand(Operands);
16672 case MCK_RotImm:
16673 return parseRotImm(Operands);
16674 case MCK_SetEndImm:
16675 return parseSetEndImm(Operands);
16676 case MCK_ShifterImm:
16677 return parseShifterImm(Operands);
16678 case MCK_TraceSyncBarrierOpt:
16679 return parseTraceSyncBarrierOptOperand(Operands);
16680 case MCK_VecListTwoMQ:
16681 return parseVectorList(Operands);
16682 case MCK_VecListFourMQ:
16683 return parseVectorList(Operands);
16684 case MCK_VecListDPairAllLanes:
16685 return parseVectorList(Operands);
16686 case MCK_VecListDPair:
16687 return parseVectorList(Operands);
16688 case MCK_VecListDPairSpacedAllLanes:
16689 return parseVectorList(Operands);
16690 case MCK_VecListDPairSpaced:
16691 return parseVectorList(Operands);
16692 case MCK_VecListFourDAllLanes:
16693 return parseVectorList(Operands);
16694 case MCK_VecListFourD:
16695 return parseVectorList(Operands);
16696 case MCK_VecListFourDByteIndexed:
16697 return parseVectorList(Operands);
16698 case MCK_VecListFourDHWordIndexed:
16699 return parseVectorList(Operands);
16700 case MCK_VecListFourDWordIndexed:
16701 return parseVectorList(Operands);
16702 case MCK_VecListFourQAllLanes:
16703 return parseVectorList(Operands);
16704 case MCK_VecListFourQ:
16705 return parseVectorList(Operands);
16706 case MCK_VecListFourQHWordIndexed:
16707 return parseVectorList(Operands);
16708 case MCK_VecListFourQWordIndexed:
16709 return parseVectorList(Operands);
16710 case MCK_VecListOneDAllLanes:
16711 return parseVectorList(Operands);
16712 case MCK_VecListOneD:
16713 return parseVectorList(Operands);
16714 case MCK_VecListOneDByteIndexed:
16715 return parseVectorList(Operands);
16716 case MCK_VecListOneDHWordIndexed:
16717 return parseVectorList(Operands);
16718 case MCK_VecListOneDWordIndexed:
16719 return parseVectorList(Operands);
16720 case MCK_VecListThreeDAllLanes:
16721 return parseVectorList(Operands);
16722 case MCK_VecListThreeD:
16723 return parseVectorList(Operands);
16724 case MCK_VecListThreeDByteIndexed:
16725 return parseVectorList(Operands);
16726 case MCK_VecListThreeDHWordIndexed:
16727 return parseVectorList(Operands);
16728 case MCK_VecListThreeDWordIndexed:
16729 return parseVectorList(Operands);
16730 case MCK_VecListThreeQAllLanes:
16731 return parseVectorList(Operands);
16732 case MCK_VecListThreeQ:
16733 return parseVectorList(Operands);
16734 case MCK_VecListThreeQHWordIndexed:
16735 return parseVectorList(Operands);
16736 case MCK_VecListThreeQWordIndexed:
16737 return parseVectorList(Operands);
16738 case MCK_VecListTwoDByteIndexed:
16739 return parseVectorList(Operands);
16740 case MCK_VecListTwoDHWordIndexed:
16741 return parseVectorList(Operands);
16742 case MCK_VecListTwoDWordIndexed:
16743 return parseVectorList(Operands);
16744 case MCK_VecListTwoQHWordIndexed:
16745 return parseVectorList(Operands);
16746 case MCK_VecListTwoQWordIndexed:
16747 return parseVectorList(Operands);
16748 case MCK_ITCondCode:
16749 return parseITCondCode(Operands);
16750 case MCK_CondCodeNoAL:
16751 return parseITCondCode(Operands);
16752 case MCK_CondCodeNoALInv:
16753 return parseITCondCode(Operands);
16754 case MCK_CondCodeRestrictedFP:
16755 return parseITCondCode(Operands);
16756 case MCK_CondCodeRestrictedI:
16757 return parseITCondCode(Operands);
16758 case MCK_CondCodeRestrictedS:
16759 return parseITCondCode(Operands);
16760 case MCK_CondCodeRestrictedU:
16761 return parseITCondCode(Operands);
16762 default:
16763 return ParseStatus::NoMatch;
16764 }
16765 return ParseStatus::NoMatch;
16766}
16767
16768ParseStatus ARMAsmParser::
16769MatchOperandParserImpl(OperandVector &Operands,
16770 StringRef Mnemonic,
16771 bool ParseForAllFeatures) {
16772 // Get the current feature set.
16773 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
16774
16775 // Get the next operand index.
16776 unsigned NextOpNum = Operands.size() - 1;
16777 // Search the table.
16778 auto MnemonicRange =
16779 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
16780 Mnemonic, LessOpcodeOperand());
16781
16782 if (MnemonicRange.first == MnemonicRange.second)
16783 return ParseStatus::NoMatch;
16784
16785 for (const OperandMatchEntry *it = MnemonicRange.first,
16786 *ie = MnemonicRange.second; it != ie; ++it) {
16787 // equal_range guarantees that instruction mnemonic matches.
16788 assert(Mnemonic == it->getMnemonic());
16789
16790 // check if the available features match
16791 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
16792 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
16793 continue;
16794
16795 // check if the operand in question has a custom parser.
16796 if (!(it->OperandMask & (1 << NextOpNum)))
16797 continue;
16798
16799 // call custom parse method to handle the operand
16800 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
16801 if (!Result.isNoMatch())
16802 return Result;
16803 }
16804
16805 // Okay, we had no match.
16806 return ParseStatus::NoMatch;
16807}
16808
16809#endif // GET_MATCHER_IMPLEMENTATION
16810
16811
16812#ifdef GET_MNEMONIC_SPELL_CHECKER
16813#undef GET_MNEMONIC_SPELL_CHECKER
16814
16815static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
16816 const unsigned MaxEditDist = 2;
16817 std::vector<StringRef> Candidates;
16818 StringRef Prev = "";
16819
16820 // Find the appropriate table for this asm variant.
16821 const MatchEntry *Start, *End;
16822 switch (VariantID) {
16823 default: llvm_unreachable("invalid variant!");
16824 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
16825 }
16826
16827 for (auto I = Start; I < End; I++) {
16828 // Ignore unsupported instructions.
16829 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
16830 if ((FBS & RequiredFeatures) != RequiredFeatures)
16831 continue;
16832
16833 StringRef T = I->getMnemonic();
16834 // Avoid recomputing the edit distance for the same string.
16835 if (T == Prev)
16836 continue;
16837
16838 Prev = T;
16839 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
16840 if (Dist <= MaxEditDist)
16841 Candidates.push_back(T);
16842 }
16843
16844 if (Candidates.empty())
16845 return "";
16846
16847 std::string Res = ", did you mean: ";
16848 unsigned i = 0;
16849 for (; i < Candidates.size() - 1; i++)
16850 Res += Candidates[i].str() + ", ";
16851 return Res + Candidates[i].str() + "?";
16852}
16853
16854#endif // GET_MNEMONIC_SPELL_CHECKER
16855
16856
16857#ifdef GET_MNEMONIC_CHECKER
16858#undef GET_MNEMONIC_CHECKER
16859
16860static bool ARMCheckMnemonic(StringRef Mnemonic,
16861 const FeatureBitset &AvailableFeatures,
16862 unsigned VariantID) {
16863 // Process all MnemonicAliases to remap the mnemonic.
16864 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
16865
16866 // Find the appropriate table for this asm variant.
16867 const MatchEntry *Start, *End;
16868 switch (VariantID) {
16869 default: llvm_unreachable("invalid variant!");
16870 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
16871 }
16872
16873 // Search the table.
16874 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
16875
16876 if (MnemonicRange.first == MnemonicRange.second)
16877 return false;
16878
16879 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
16880 it != ie; ++it) {
16881 const FeatureBitset &RequiredFeatures =
16882 FeatureBitsets[it->RequiredFeaturesIdx];
16883 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
16884 return true;
16885 }
16886 return false;
16887}
16888
16889#endif // GET_MNEMONIC_CHECKER
16890
16891