| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* * ARM Disassembler *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | |
| 10 | #include "llvm/MC/MCInst.h" |
| 11 | #include "llvm/MC/MCSubtargetInfo.h" |
| 12 | #include "llvm/Support/DataTypes.h" |
| 13 | #include "llvm/Support/Debug.h" |
| 14 | #include "llvm/Support/LEB128.h" |
| 15 | #include "llvm/Support/raw_ostream.h" |
| 16 | #include "llvm/TargetParser/SubtargetFeature.h" |
| 17 | #include <assert.h> |
| 18 | |
| 19 | namespace { |
| 20 | |
| 21 | // InsnBitWidth is essentially a type trait used by the decoder emitter to query |
| 22 | // the supported bitwidth for a given type. But default, the value is 0, making |
| 23 | // it an invalid type for use as `InsnType` when instantiating the decoder. |
| 24 | // Individual targets are expected to provide specializations for these based |
| 25 | // on their usage. |
| 26 | template <typename T> constexpr uint32_t InsnBitWidth = 0; |
| 27 | |
| 28 | [[maybe_unused]] |
| 29 | static DecodeStatus Decodearm_ptr_rcRegClassByHwMode(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder) { |
| 30 | switch (Decoder->getSubtargetInfo().getHwMode(type: MCSubtargetInfo::HwMode_RegInfo)) { |
| 31 | case 0: // DefaultMode |
| 32 | return DecodeGPRRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder); |
| 33 | case 1: // Thumb1OnlyMode |
| 34 | return DecodetGPRRegisterClass(Inst, RegNo: Imm, Address: Addr, Decoder); |
| 35 | default: |
| 36 | llvm_unreachable("no decoder for hwmode"); |
| 37 | } |
| 38 | } |
| 39 | |
| 40 | |
| 41 | static const uint8_t DecoderTableThumb16[699] = { |
| 42 | OPC_SwitchField, 12, 4, // 0: switch Inst[15:12] { |
| 43 | 0, 10, // 3: case 0x0: { |
| 44 | OPC_CheckPredicate, 0, // 5: check predicate 0 |
| 45 | OPC_CheckField, 6, 6, 0, // 7: check Inst[11:6] == 0x0 |
| 46 | OPC_Decode, 131, 35, 0, // 11: decode to tMOVSr using decoder 0 |
| 47 | // 11: } |
| 48 | 2, 10, // 15: case 0x2: { |
| 49 | OPC_CheckPredicate, 0, // 17: check predicate 0 |
| 50 | OPC_CheckField, 11, 1, 1, // 19: check Inst[11] == 0x1 |
| 51 | OPC_Decode, 235, 34, 1, // 23: decode to tCMPi8 using decoder 1 |
| 52 | // 23: } |
| 53 | 4, 157, 1, // 27: case 0x4: { |
| 54 | OPC_SwitchField, 11, 1, // 30: switch Inst[11] { |
| 55 | 0, 143, 1, // 33: case 0x0: { |
| 56 | OPC_SwitchField, 8, 3, // 36: switch Inst[10:8] { |
| 57 | 2, 27, // 39: case 0x2: { |
| 58 | OPC_SwitchField, 6, 2, // 41: switch Inst[7:6] { |
| 59 | 0, 6, // 44: case 0x0: { |
| 60 | OPC_CheckPredicate, 0, // 46: check predicate 0 |
| 61 | OPC_Decode, 163, 35, 2, // 48: decode to tTST using decoder 2 |
| 62 | // 48: } |
| 63 | 2, 6, // 52: case 0x2: { |
| 64 | OPC_CheckPredicate, 0, // 54: check predicate 0 |
| 65 | OPC_Decode, 236, 34, 2, // 56: decode to tCMPr using decoder 2 |
| 66 | // 56: } |
| 67 | 3, 0, // 60: case 0x3: { |
| 68 | OPC_CheckPredicate, 0, // 62: check predicate 0 |
| 69 | OPC_Decode, 233, 34, 2, // 64: decode to tCMNz using decoder 2 |
| 70 | // 64: } |
| 71 | // 64: } // switch Inst[7:6] |
| 72 | // 64: } |
| 73 | 4, 34, // 68: case 0x4: { |
| 74 | OPC_Scope, 10, // 70: try { |
| 75 | OPC_CheckField, 3, 4, 13, // 72: check Inst[6:3] == 0xd |
| 76 | OPC_CheckPredicate, 0, // 76: check predicate 0 |
| 77 | OPC_Decode, 212, 34, 3, // 78: decode to tADDrSP using decoder 3 |
| 78 | OPC_Scope, 14, // 82: } else try { |
| 79 | OPC_CheckField, 0, 3, 5, // 84: check Inst[2:0] == 0x5 |
| 80 | OPC_CheckPredicate, 0, // 88: check predicate 0 |
| 81 | OPC_CheckField, 7, 1, 1, // 90: check Inst[7] == 0x1 |
| 82 | OPC_Decode, 216, 34, 3, // 94: decode to tADDspr using decoder 3 |
| 83 | // 94: } else try { |
| 84 | OPC_CheckPredicate, 0, // 98: check predicate 0 |
| 85 | OPC_Decode, 209, 34, 4, // 100: decode to tADDhirr using decoder 4 |
| 86 | // 100: } |
| 87 | // 100: } |
| 88 | 5, 6, // 104: case 0x5: { |
| 89 | OPC_CheckPredicate, 0, // 106: check predicate 0 |
| 90 | OPC_Decode, 234, 34, 5, // 108: decode to tCMPhir using decoder 5 |
| 91 | // 108: } |
| 92 | 6, 6, // 112: case 0x6: { |
| 93 | OPC_CheckPredicate, 0, // 114: check predicate 0 |
| 94 | OPC_Decode, 133, 35, 5, // 116: decode to tMOVr using decoder 5 |
| 95 | // 116: } |
| 96 | 7, 0, // 120: case 0x7: { |
| 97 | OPC_SwitchField, 7, 1, // 122: switch Inst[7] { |
| 98 | 0, 24, // 125: case 0x0: { |
| 99 | OPC_Scope, 13, // 127: try { |
| 100 | OPC_CheckField, 2, 1, 1, // 129: check Inst[2] == 0x1 |
| 101 | OPC_CheckPredicate, 1, // 133: check predicate 1 |
| 102 | OPC_SoftFail, 3, 0, // 135: softfail pos=0x00000003 neg=0x00000000 |
| 103 | OPC_Decode, 229, 34, 6, // 138: decode to tBXNS using decoder 6 |
| 104 | // 138: } else try { |
| 105 | OPC_CheckPredicate, 0, // 142: check predicate 0 |
| 106 | OPC_SoftFail, 7, 0, // 144: softfail pos=0x00000007 neg=0x00000000 |
| 107 | OPC_Decode, 228, 34, 6, // 147: decode to tBX using decoder 6 |
| 108 | // 147: } |
| 109 | // 147: } |
| 110 | 1, 0, // 151: case 0x1: { |
| 111 | OPC_SwitchField, 2, 1, // 153: switch Inst[2] { |
| 112 | 0, 10, // 156: case 0x0: { |
| 113 | OPC_CheckPredicate, 2, // 158: check predicate 2 |
| 114 | OPC_CheckField, 0, 2, 0, // 160: check Inst[1:0] == 0x0 |
| 115 | OPC_Decode, 227, 34, 7, // 164: decode to tBLXr using decoder 7 |
| 116 | // 164: } |
| 117 | 1, 0, // 168: case 0x1: { |
| 118 | OPC_CheckPredicate, 1, // 170: check predicate 1 |
| 119 | OPC_SoftFail, 3, 0, // 172: softfail pos=0x00000003 neg=0x00000000 |
| 120 | OPC_Decode, 225, 34, 8, // 175: decode to tBLXNSr using decoder 8 |
| 121 | // 175: } |
| 122 | // 175: } // switch Inst[2] |
| 123 | // 175: } |
| 124 | // 175: } // switch Inst[7] |
| 125 | // 175: } |
| 126 | // 175: } // switch Inst[10:8] |
| 127 | // 175: } |
| 128 | 1, 0, // 179: case 0x1: { |
| 129 | OPC_CheckPredicate, 0, // 181: check predicate 0 |
| 130 | OPC_Decode, 252, 34, 9, // 183: decode to tLDRpci using decoder 9 |
| 131 | // 183: } |
| 132 | // 183: } // switch Inst[11] |
| 133 | // 183: } |
| 134 | 5, 67, // 187: case 0x5: { |
| 135 | OPC_SwitchField, 9, 3, // 189: switch Inst[11:9] { |
| 136 | 0, 6, // 192: case 0x0: { |
| 137 | OPC_CheckPredicate, 0, // 194: check predicate 0 |
| 138 | OPC_Decode, 153, 35, 10, // 196: decode to tSTRr using decoder 10 |
| 139 | // 196: } |
| 140 | 1, 6, // 200: case 0x1: { |
| 141 | OPC_CheckPredicate, 0, // 202: check predicate 0 |
| 142 | OPC_Decode, 151, 35, 10, // 204: decode to tSTRHr using decoder 10 |
| 143 | // 204: } |
| 144 | 2, 6, // 208: case 0x2: { |
| 145 | OPC_CheckPredicate, 0, // 210: check predicate 0 |
| 146 | OPC_Decode, 149, 35, 10, // 212: decode to tSTRBr using decoder 10 |
| 147 | // 212: } |
| 148 | 3, 6, // 216: case 0x3: { |
| 149 | OPC_CheckPredicate, 0, // 218: check predicate 0 |
| 150 | OPC_Decode, 249, 34, 10, // 220: decode to tLDRSB using decoder 10 |
| 151 | // 220: } |
| 152 | 4, 6, // 224: case 0x4: { |
| 153 | OPC_CheckPredicate, 0, // 226: check predicate 0 |
| 154 | OPC_Decode, 253, 34, 10, // 228: decode to tLDRr using decoder 10 |
| 155 | // 228: } |
| 156 | 5, 6, // 232: case 0x5: { |
| 157 | OPC_CheckPredicate, 0, // 234: check predicate 0 |
| 158 | OPC_Decode, 248, 34, 10, // 236: decode to tLDRHr using decoder 10 |
| 159 | // 236: } |
| 160 | 6, 6, // 240: case 0x6: { |
| 161 | OPC_CheckPredicate, 0, // 242: check predicate 0 |
| 162 | OPC_Decode, 246, 34, 10, // 244: decode to tLDRBr using decoder 10 |
| 163 | // 244: } |
| 164 | 7, 0, // 248: case 0x7: { |
| 165 | OPC_CheckPredicate, 0, // 250: check predicate 0 |
| 166 | OPC_Decode, 250, 34, 10, // 252: decode to tLDRSH using decoder 10 |
| 167 | // 252: } |
| 168 | // 252: } // switch Inst[11:9] |
| 169 | // 252: } |
| 170 | 6, 19, // 256: case 0x6: { |
| 171 | OPC_SwitchField, 11, 1, // 258: switch Inst[11] { |
| 172 | 0, 6, // 261: case 0x0: { |
| 173 | OPC_CheckPredicate, 0, // 263: check predicate 0 |
| 174 | OPC_Decode, 152, 35, 11, // 265: decode to tSTRi using decoder 11 |
| 175 | // 265: } |
| 176 | 1, 0, // 269: case 0x1: { |
| 177 | OPC_CheckPredicate, 0, // 271: check predicate 0 |
| 178 | OPC_Decode, 251, 34, 11, // 273: decode to tLDRi using decoder 11 |
| 179 | // 273: } |
| 180 | // 273: } // switch Inst[11] |
| 181 | // 273: } |
| 182 | 7, 19, // 277: case 0x7: { |
| 183 | OPC_SwitchField, 11, 1, // 279: switch Inst[11] { |
| 184 | 0, 6, // 282: case 0x0: { |
| 185 | OPC_CheckPredicate, 0, // 284: check predicate 0 |
| 186 | OPC_Decode, 148, 35, 11, // 286: decode to tSTRBi using decoder 11 |
| 187 | // 286: } |
| 188 | 1, 0, // 290: case 0x1: { |
| 189 | OPC_CheckPredicate, 0, // 292: check predicate 0 |
| 190 | OPC_Decode, 245, 34, 11, // 294: decode to tLDRBi using decoder 11 |
| 191 | // 294: } |
| 192 | // 294: } // switch Inst[11] |
| 193 | // 294: } |
| 194 | 8, 19, // 298: case 0x8: { |
| 195 | OPC_SwitchField, 11, 1, // 300: switch Inst[11] { |
| 196 | 0, 6, // 303: case 0x0: { |
| 197 | OPC_CheckPredicate, 0, // 305: check predicate 0 |
| 198 | OPC_Decode, 150, 35, 11, // 307: decode to tSTRHi using decoder 11 |
| 199 | // 307: } |
| 200 | 1, 0, // 311: case 0x1: { |
| 201 | OPC_CheckPredicate, 0, // 313: check predicate 0 |
| 202 | OPC_Decode, 247, 34, 11, // 315: decode to tLDRHi using decoder 11 |
| 203 | // 315: } |
| 204 | // 315: } // switch Inst[11] |
| 205 | // 315: } |
| 206 | 9, 19, // 319: case 0x9: { |
| 207 | OPC_SwitchField, 11, 1, // 321: switch Inst[11] { |
| 208 | 0, 6, // 324: case 0x0: { |
| 209 | OPC_CheckPredicate, 0, // 326: check predicate 0 |
| 210 | OPC_Decode, 154, 35, 12, // 328: decode to tSTRspi using decoder 12 |
| 211 | // 328: } |
| 212 | 1, 0, // 332: case 0x1: { |
| 213 | OPC_CheckPredicate, 0, // 334: check predicate 0 |
| 214 | OPC_Decode, 254, 34, 12, // 336: decode to tLDRspi using decoder 12 |
| 215 | // 336: } |
| 216 | // 336: } // switch Inst[11] |
| 217 | // 336: } |
| 218 | 10, 19, // 340: case 0xa: { |
| 219 | OPC_SwitchField, 11, 1, // 342: switch Inst[11] { |
| 220 | 0, 6, // 345: case 0x0: { |
| 221 | OPC_CheckPredicate, 0, // 347: check predicate 0 |
| 222 | OPC_Decode, 217, 34, 13, // 349: decode to tADR using decoder 13 |
| 223 | // 349: } |
| 224 | 1, 0, // 353: case 0x1: { |
| 225 | OPC_CheckPredicate, 0, // 355: check predicate 0 |
| 226 | OPC_Decode, 213, 34, 13, // 357: decode to tADDrSPi using decoder 13 |
| 227 | // 357: } |
| 228 | // 357: } // switch Inst[11] |
| 229 | // 357: } |
| 230 | 11, 250, 1, // 361: case 0xb: { |
| 231 | OPC_SwitchField, 10, 2, // 364: switch Inst[11:10] { |
| 232 | 0, 84, // 367: case 0x0: { |
| 233 | OPC_SwitchField, 8, 1, // 369: switch Inst[8] { |
| 234 | 0, 71, // 372: case 0x0: { |
| 235 | OPC_SwitchField, 7, 1, // 374: switch Inst[7] { |
| 236 | 0, 32, // 377: case 0x0: { |
| 237 | OPC_SwitchField, 9, 1, // 379: switch Inst[9] { |
| 238 | 0, 6, // 382: case 0x0: { |
| 239 | OPC_CheckPredicate, 0, // 384: check predicate 0 |
| 240 | OPC_Decode, 215, 34, 14, // 386: decode to tADDspi using decoder 14 |
| 241 | // 386: } |
| 242 | 1, 0, // 390: case 0x1: { |
| 243 | OPC_SwitchField, 6, 1, // 392: switch Inst[6] { |
| 244 | 0, 6, // 395: case 0x0: { |
| 245 | OPC_CheckPredicate, 3, // 397: check predicate 3 |
| 246 | OPC_Decode, 161, 35, 2, // 399: decode to tSXTH using decoder 2 |
| 247 | // 399: } |
| 248 | 1, 0, // 403: case 0x1: { |
| 249 | OPC_CheckPredicate, 3, // 405: check predicate 3 |
| 250 | OPC_Decode, 160, 35, 2, // 407: decode to tSXTB using decoder 2 |
| 251 | // 407: } |
| 252 | // 407: } // switch Inst[6] |
| 253 | // 407: } |
| 254 | // 407: } // switch Inst[9] |
| 255 | // 407: } |
| 256 | 1, 0, // 411: case 0x1: { |
| 257 | OPC_SwitchField, 9, 1, // 413: switch Inst[9] { |
| 258 | 0, 6, // 416: case 0x0: { |
| 259 | OPC_CheckPredicate, 0, // 418: check predicate 0 |
| 260 | OPC_Decode, 158, 35, 14, // 420: decode to tSUBspi using decoder 14 |
| 261 | // 420: } |
| 262 | 1, 0, // 424: case 0x1: { |
| 263 | OPC_SwitchField, 6, 1, // 426: switch Inst[6] { |
| 264 | 0, 6, // 429: case 0x0: { |
| 265 | OPC_CheckPredicate, 3, // 431: check predicate 3 |
| 266 | OPC_Decode, 166, 35, 2, // 433: decode to tUXTH using decoder 2 |
| 267 | // 433: } |
| 268 | 1, 0, // 437: case 0x1: { |
| 269 | OPC_CheckPredicate, 3, // 439: check predicate 3 |
| 270 | OPC_Decode, 165, 35, 2, // 441: decode to tUXTB using decoder 2 |
| 271 | // 441: } |
| 272 | // 441: } // switch Inst[6] |
| 273 | // 441: } |
| 274 | // 441: } // switch Inst[9] |
| 275 | // 441: } |
| 276 | // 441: } // switch Inst[7] |
| 277 | // 441: } |
| 278 | 1, 0, // 445: case 0x1: { |
| 279 | OPC_CheckPredicate, 4, // 447: check predicate 4 |
| 280 | OPC_Decode, 232, 34, 15, // 449: decode to tCBZ using decoder 15 |
| 281 | // 449: } |
| 282 | // 449: } // switch Inst[8] |
| 283 | // 449: } |
| 284 | 1, 55, // 453: case 0x1: { |
| 285 | OPC_SwitchField, 9, 1, // 455: switch Inst[9] { |
| 286 | 0, 6, // 458: case 0x0: { |
| 287 | OPC_CheckPredicate, 0, // 460: check predicate 0 |
| 288 | OPC_Decode, 139, 35, 16, // 462: decode to tPUSH using decoder 16 |
| 289 | // 462: } |
| 290 | 1, 0, // 466: case 0x1: { |
| 291 | OPC_SwitchField, 5, 4, // 468: switch Inst[8:5] { |
| 292 | 0, 9, // 471: case 0x0: { |
| 293 | OPC_CheckPredicate, 5, // 473: check predicate 5 |
| 294 | OPC_SoftFail, 7, 16, // 475: softfail pos=0x00000007 neg=0x00000010 |
| 295 | OPC_Decode, 169, 33, 17, // 478: decode to t2SETPAN using decoder 17 |
| 296 | // 478: } |
| 297 | 2, 14, // 482: case 0x2: { |
| 298 | OPC_CheckPredicate, 6, // 484: check predicate 6 |
| 299 | OPC_CheckField, 4, 1, 1, // 486: check Inst[4] == 0x1 |
| 300 | OPC_CheckField, 0, 3, 0, // 490: check Inst[2:0] == 0x0 |
| 301 | OPC_Decode, 146, 35, 17, // 494: decode to tSETEND using decoder 17 |
| 302 | // 494: } |
| 303 | 3, 0, // 498: case 0x3: { |
| 304 | OPC_CheckPredicate, 0, // 500: check predicate 0 |
| 305 | OPC_CheckField, 3, 1, 0, // 502: check Inst[3] == 0x0 |
| 306 | OPC_Decode, 237, 34, 18, // 506: decode to tCPS using decoder 18 |
| 307 | // 506: } |
| 308 | // 506: } // switch Inst[8:5] |
| 309 | // 506: } |
| 310 | // 506: } // switch Inst[9] |
| 311 | // 506: } |
| 312 | 2, 64, // 510: case 0x2: { |
| 313 | OPC_SwitchField, 8, 1, // 512: switch Inst[8] { |
| 314 | 0, 51, // 515: case 0x0: { |
| 315 | OPC_SwitchField, 6, 2, // 517: switch Inst[7:6] { |
| 316 | 0, 10, // 520: case 0x0: { |
| 317 | OPC_CheckPredicate, 3, // 522: check predicate 3 |
| 318 | OPC_CheckField, 9, 1, 1, // 524: check Inst[9] == 0x1 |
| 319 | OPC_Decode, 140, 35, 2, // 528: decode to tREV using decoder 2 |
| 320 | // 528: } |
| 321 | 1, 10, // 532: case 0x1: { |
| 322 | OPC_CheckPredicate, 3, // 534: check predicate 3 |
| 323 | OPC_CheckField, 9, 1, 1, // 536: check Inst[9] == 0x1 |
| 324 | OPC_Decode, 141, 35, 2, // 540: decode to tREV16 using decoder 2 |
| 325 | // 540: } |
| 326 | 2, 10, // 544: case 0x2: { |
| 327 | OPC_CheckPredicate, 7, // 546: check predicate 7 |
| 328 | OPC_CheckField, 9, 1, 1, // 548: check Inst[9] == 0x1 |
| 329 | OPC_Decode, 240, 34, 19, // 552: decode to tHLT using decoder 19 |
| 330 | // 552: } |
| 331 | 3, 0, // 556: case 0x3: { |
| 332 | OPC_CheckPredicate, 3, // 558: check predicate 3 |
| 333 | OPC_CheckField, 9, 1, 1, // 560: check Inst[9] == 0x1 |
| 334 | OPC_Decode, 142, 35, 2, // 564: decode to tREVSH using decoder 2 |
| 335 | // 564: } |
| 336 | // 564: } // switch Inst[7:6] |
| 337 | // 564: } |
| 338 | 1, 0, // 568: case 0x1: { |
| 339 | OPC_CheckPredicate, 4, // 570: check predicate 4 |
| 340 | OPC_Decode, 231, 34, 15, // 572: decode to tCBNZ using decoder 15 |
| 341 | // 572: } |
| 342 | // 572: } // switch Inst[8] |
| 343 | // 572: } |
| 344 | 3, 0, // 576: case 0x3: { |
| 345 | OPC_SwitchField, 9, 1, // 578: switch Inst[9] { |
| 346 | 0, 6, // 581: case 0x0: { |
| 347 | OPC_CheckPredicate, 0, // 583: check predicate 0 |
| 348 | OPC_Decode, 138, 35, 20, // 585: decode to tPOP using decoder 20 |
| 349 | // 585: } |
| 350 | 1, 0, // 589: case 0x1: { |
| 351 | OPC_SwitchField, 8, 1, // 591: switch Inst[8] { |
| 352 | 0, 6, // 594: case 0x0: { |
| 353 | OPC_CheckPredicate, 0, // 596: check predicate 0 |
| 354 | OPC_Decode, 223, 34, 21, // 598: decode to tBKPT using decoder 21 |
| 355 | // 598: } |
| 356 | 1, 0, // 602: case 0x1: { |
| 357 | OPC_CheckPredicate, 8, // 604: check predicate 8 |
| 358 | OPC_CheckField, 0, 4, 0, // 606: check Inst[3:0] == 0x0 |
| 359 | OPC_Decode, 239, 34, 22, // 610: decode to tHINT using decoder 22 |
| 360 | // 610: } |
| 361 | // 610: } // switch Inst[8] |
| 362 | // 610: } |
| 363 | // 610: } // switch Inst[9] |
| 364 | // 610: } |
| 365 | // 610: } // switch Inst[11:10] |
| 366 | // 610: } |
| 367 | 12, 19, // 614: case 0xc: { |
| 368 | OPC_SwitchField, 11, 1, // 616: switch Inst[11] { |
| 369 | 0, 6, // 619: case 0x0: { |
| 370 | OPC_CheckPredicate, 0, // 621: check predicate 0 |
| 371 | OPC_Decode, 147, 35, 23, // 623: decode to tSTMIA_UPD using decoder 23 |
| 372 | // 623: } |
| 373 | 1, 0, // 627: case 0x1: { |
| 374 | OPC_CheckPredicate, 0, // 629: check predicate 0 |
| 375 | OPC_Decode, 244, 34, 24, // 631: decode to tLDMIA using decoder 24 |
| 376 | // 631: } |
| 377 | // 631: } // switch Inst[11] |
| 378 | // 631: } |
| 379 | 13, 50, // 635: case 0xd: { |
| 380 | OPC_Scope, 21, // 637: try { |
| 381 | OPC_SwitchField, 0, 12, // 639: switch Inst[11:0] { |
| 382 | 249, 29, 6, // 642: case 0xef9: { |
| 383 | OPC_CheckPredicate, 0, // 645: check predicate 0 |
| 384 | OPC_Decode, 167, 35, 25, // 647: decode to t__brkdiv0 using decoder 25 |
| 385 | // 647: } |
| 386 | 254, 29, 0, // 651: case 0xefe: { |
| 387 | OPC_CheckPredicate, 0, // 654: check predicate 0 |
| 388 | OPC_Decode, 162, 35, 25, // 656: decode to tTRAP using decoder 25 |
| 389 | // 656: } |
| 390 | // 656: } // switch Inst[11:0] |
| 391 | OPC_Scope, 19, // 660: } else try { |
| 392 | OPC_SwitchField, 8, 4, // 662: switch Inst[11:8] { |
| 393 | 14, 6, // 665: case 0xe: { |
| 394 | OPC_CheckPredicate, 0, // 667: check predicate 0 |
| 395 | OPC_Decode, 164, 35, 21, // 669: decode to tUDF using decoder 21 |
| 396 | // 669: } |
| 397 | 15, 0, // 673: case 0xf: { |
| 398 | OPC_CheckPredicate, 0, // 675: check predicate 0 |
| 399 | OPC_Decode, 159, 35, 26, // 677: decode to tSVC using decoder 26 |
| 400 | // 677: } |
| 401 | // 677: } // switch Inst[11:8] |
| 402 | // 677: } else try { |
| 403 | OPC_CheckPredicate, 0, // 681: check predicate 0 |
| 404 | OPC_Decode, 230, 34, 27, // 683: decode to tBcc using decoder 27 |
| 405 | // 683: } |
| 406 | // 683: } |
| 407 | 14, 0, // 687: case 0xe: { |
| 408 | OPC_CheckPredicate, 0, // 689: check predicate 0 |
| 409 | OPC_CheckField, 11, 1, 0, // 691: check Inst[11] == 0x0 |
| 410 | OPC_Decode, 221, 34, 28, // 695: decode to tB using decoder 28 |
| 411 | // 695: } |
| 412 | // 695: } // switch Inst[15:12] |
| 413 | }; |
| 414 | static const uint8_t DecoderTableThumb216[11] = { |
| 415 | OPC_CheckPredicate, 9, // 0: check predicate 9 |
| 416 | OPC_CheckField, 8, 8, 191, 1, // 2: check Inst[15:8] == 0xbf |
| 417 | OPC_Decode, 137, 32, 29, // 7: decode to t2IT using decoder 29 |
| 418 | }; |
| 419 | static const uint8_t DecoderTableThumbSBit16[197] = { |
| 420 | OPC_SwitchField, 11, 5, // 0: switch Inst[15:11] { |
| 421 | 0, 6, // 3: case 0x0: { |
| 422 | OPC_CheckPredicate, 0, // 5: check predicate 0 |
| 423 | OPC_Decode, 255, 34, 30, // 7: decode to tLSLri using decoder 30 |
| 424 | // 7: } |
| 425 | 1, 6, // 11: case 0x1: { |
| 426 | OPC_CheckPredicate, 0, // 13: check predicate 0 |
| 427 | OPC_Decode, 129, 35, 30, // 15: decode to tLSRri using decoder 30 |
| 428 | // 15: } |
| 429 | 2, 6, // 19: case 0x2: { |
| 430 | OPC_CheckPredicate, 0, // 21: check predicate 0 |
| 431 | OPC_Decode, 219, 34, 30, // 23: decode to tASRri using decoder 30 |
| 432 | // 23: } |
| 433 | 3, 35, // 27: case 0x3: { |
| 434 | OPC_SwitchField, 9, 2, // 29: switch Inst[10:9] { |
| 435 | 0, 6, // 32: case 0x0: { |
| 436 | OPC_CheckPredicate, 0, // 34: check predicate 0 |
| 437 | OPC_Decode, 214, 34, 31, // 36: decode to tADDrr using decoder 31 |
| 438 | // 36: } |
| 439 | 1, 6, // 40: case 0x1: { |
| 440 | OPC_CheckPredicate, 0, // 42: check predicate 0 |
| 441 | OPC_Decode, 157, 35, 31, // 44: decode to tSUBrr using decoder 31 |
| 442 | // 44: } |
| 443 | 2, 6, // 48: case 0x2: { |
| 444 | OPC_CheckPredicate, 0, // 50: check predicate 0 |
| 445 | OPC_Decode, 210, 34, 32, // 52: decode to tADDi3 using decoder 32 |
| 446 | // 52: } |
| 447 | 3, 0, // 56: case 0x3: { |
| 448 | OPC_CheckPredicate, 0, // 58: check predicate 0 |
| 449 | OPC_Decode, 155, 35, 32, // 60: decode to tSUBi3 using decoder 32 |
| 450 | // 60: } |
| 451 | // 60: } // switch Inst[10:9] |
| 452 | // 60: } |
| 453 | 4, 6, // 64: case 0x4: { |
| 454 | OPC_CheckPredicate, 0, // 66: check predicate 0 |
| 455 | OPC_Decode, 132, 35, 33, // 68: decode to tMOVi8 using decoder 33 |
| 456 | // 68: } |
| 457 | 6, 6, // 72: case 0x6: { |
| 458 | OPC_CheckPredicate, 0, // 74: check predicate 0 |
| 459 | OPC_Decode, 211, 34, 34, // 76: decode to tADDi8 using decoder 34 |
| 460 | // 76: } |
| 461 | 7, 6, // 80: case 0x7: { |
| 462 | OPC_CheckPredicate, 0, // 82: check predicate 0 |
| 463 | OPC_Decode, 156, 35, 34, // 84: decode to tSUBi8 using decoder 34 |
| 464 | // 84: } |
| 465 | 8, 0, // 88: case 0x8: { |
| 466 | OPC_SwitchField, 6, 5, // 90: switch Inst[10:6] { |
| 467 | 0, 6, // 93: case 0x0: { |
| 468 | OPC_CheckPredicate, 0, // 95: check predicate 0 |
| 469 | OPC_Decode, 218, 34, 35, // 97: decode to tAND using decoder 35 |
| 470 | // 97: } |
| 471 | 1, 6, // 101: case 0x1: { |
| 472 | OPC_CheckPredicate, 0, // 103: check predicate 0 |
| 473 | OPC_Decode, 238, 34, 35, // 105: decode to tEOR using decoder 35 |
| 474 | // 105: } |
| 475 | 2, 6, // 109: case 0x2: { |
| 476 | OPC_CheckPredicate, 0, // 111: check predicate 0 |
| 477 | OPC_Decode, 128, 35, 35, // 113: decode to tLSLrr using decoder 35 |
| 478 | // 113: } |
| 479 | 3, 6, // 117: case 0x3: { |
| 480 | OPC_CheckPredicate, 0, // 119: check predicate 0 |
| 481 | OPC_Decode, 130, 35, 35, // 121: decode to tLSRrr using decoder 35 |
| 482 | // 121: } |
| 483 | 4, 6, // 125: case 0x4: { |
| 484 | OPC_CheckPredicate, 0, // 127: check predicate 0 |
| 485 | OPC_Decode, 220, 34, 35, // 129: decode to tASRrr using decoder 35 |
| 486 | // 129: } |
| 487 | 5, 6, // 133: case 0x5: { |
| 488 | OPC_CheckPredicate, 0, // 135: check predicate 0 |
| 489 | OPC_Decode, 208, 34, 35, // 137: decode to tADC using decoder 35 |
| 490 | // 137: } |
| 491 | 6, 6, // 141: case 0x6: { |
| 492 | OPC_CheckPredicate, 0, // 143: check predicate 0 |
| 493 | OPC_Decode, 145, 35, 35, // 145: decode to tSBC using decoder 35 |
| 494 | // 145: } |
| 495 | 7, 6, // 149: case 0x7: { |
| 496 | OPC_CheckPredicate, 0, // 151: check predicate 0 |
| 497 | OPC_Decode, 143, 35, 35, // 153: decode to tROR using decoder 35 |
| 498 | // 153: } |
| 499 | 9, 6, // 157: case 0x9: { |
| 500 | OPC_CheckPredicate, 0, // 159: check predicate 0 |
| 501 | OPC_Decode, 144, 35, 36, // 161: decode to tRSB using decoder 36 |
| 502 | // 161: } |
| 503 | 12, 6, // 165: case 0xc: { |
| 504 | OPC_CheckPredicate, 0, // 167: check predicate 0 |
| 505 | OPC_Decode, 136, 35, 35, // 169: decode to tORR using decoder 35 |
| 506 | // 169: } |
| 507 | 13, 6, // 173: case 0xd: { |
| 508 | OPC_CheckPredicate, 0, // 175: check predicate 0 |
| 509 | OPC_Decode, 134, 35, 37, // 177: decode to tMUL using decoder 37 |
| 510 | // 177: } |
| 511 | 14, 6, // 181: case 0xe: { |
| 512 | OPC_CheckPredicate, 0, // 183: check predicate 0 |
| 513 | OPC_Decode, 222, 34, 35, // 185: decode to tBIC using decoder 35 |
| 514 | // 185: } |
| 515 | 15, 0, // 189: case 0xf: { |
| 516 | OPC_CheckPredicate, 0, // 191: check predicate 0 |
| 517 | OPC_Decode, 135, 35, 36, // 193: decode to tMVN using decoder 36 |
| 518 | // 193: } |
| 519 | // 193: } // switch Inst[10:6] |
| 520 | // 193: } |
| 521 | // 193: } // switch Inst[15:11] |
| 522 | }; |
| 523 | static const uint8_t DecoderTableARM32[5252] = { |
| 524 | OPC_SwitchField, 25, 3, // 0: switch Inst[27:25] { |
| 525 | 0, 220, 17, // 3: case 0x0: { |
| 526 | OPC_SwitchField, 21, 1, // 6: switch Inst[21] { |
| 527 | 0, 164, 9, // 9: case 0x0: { |
| 528 | OPC_SwitchField, 24, 1, // 12: switch Inst[24] { |
| 529 | 0, 244, 1, // 15: case 0x0: { |
| 530 | OPC_SwitchField, 4, 1, // 18: switch Inst[4] { |
| 531 | 0, 83, // 21: case 0x0: { |
| 532 | OPC_SwitchField, 22, 2, // 23: switch Inst[23:22] { |
| 533 | 0, 18, // 26: case 0x0: { |
| 534 | OPC_Scope, 10, // 28: try { |
| 535 | OPC_CheckField, 5, 7, 0, // 30: check Inst[11:5] == 0x0 |
| 536 | OPC_CheckPredicate, 10, // 34: check predicate 10 |
| 537 | OPC_Decode, 176, 6, 38, // 36: decode to ANDrr using decoder 38 |
| 538 | // 36: } else try { |
| 539 | OPC_CheckPredicate, 10, // 40: check predicate 10 |
| 540 | OPC_Decode, 177, 6, 39, // 42: decode to ANDrsi using decoder 39 |
| 541 | // 42: } |
| 542 | // 42: } |
| 543 | 1, 18, // 46: case 0x1: { |
| 544 | OPC_Scope, 10, // 48: try { |
| 545 | OPC_CheckField, 5, 7, 0, // 50: check Inst[11:5] == 0x0 |
| 546 | OPC_CheckPredicate, 10, // 54: check predicate 10 |
| 547 | OPC_Decode, 253, 15, 38, // 56: decode to SUBrr using decoder 38 |
| 548 | // 56: } else try { |
| 549 | OPC_CheckPredicate, 10, // 60: check predicate 10 |
| 550 | OPC_Decode, 254, 15, 39, // 62: decode to SUBrsi using decoder 39 |
| 551 | // 62: } |
| 552 | // 62: } |
| 553 | 2, 18, // 66: case 0x2: { |
| 554 | OPC_Scope, 10, // 68: try { |
| 555 | OPC_CheckField, 5, 7, 0, // 70: check Inst[11:5] == 0x0 |
| 556 | OPC_CheckPredicate, 10, // 74: check predicate 10 |
| 557 | OPC_Decode, 167, 6, 38, // 76: decode to ADDrr using decoder 38 |
| 558 | // 76: } else try { |
| 559 | OPC_CheckPredicate, 10, // 80: check predicate 10 |
| 560 | OPC_Decode, 168, 6, 39, // 82: decode to ADDrsi using decoder 39 |
| 561 | // 82: } |
| 562 | // 82: } |
| 563 | 3, 0, // 86: case 0x3: { |
| 564 | OPC_Scope, 10, // 88: try { |
| 565 | OPC_CheckField, 5, 7, 0, // 90: check Inst[11:5] == 0x0 |
| 566 | OPC_CheckPredicate, 10, // 94: check predicate 10 |
| 567 | OPC_Decode, 247, 14, 38, // 96: decode to SBCrr using decoder 38 |
| 568 | // 96: } else try { |
| 569 | OPC_CheckPredicate, 10, // 100: check predicate 10 |
| 570 | OPC_Decode, 248, 14, 39, // 102: decode to SBCrsi using decoder 39 |
| 571 | // 102: } |
| 572 | // 102: } |
| 573 | // 102: } // switch Inst[23:22] |
| 574 | // 102: } |
| 575 | 1, 0, // 106: case 0x1: { |
| 576 | OPC_SwitchField, 7, 1, // 108: switch Inst[7] { |
| 577 | 0, 35, // 111: case 0x0: { |
| 578 | OPC_SwitchField, 22, 2, // 113: switch Inst[23:22] { |
| 579 | 0, 6, // 116: case 0x0: { |
| 580 | OPC_CheckPredicate, 10, // 118: check predicate 10 |
| 581 | OPC_Decode, 178, 6, 40, // 120: decode to ANDrsr using decoder 40 |
| 582 | // 120: } |
| 583 | 1, 6, // 124: case 0x1: { |
| 584 | OPC_CheckPredicate, 10, // 126: check predicate 10 |
| 585 | OPC_Decode, 255, 15, 40, // 128: decode to SUBrsr using decoder 40 |
| 586 | // 128: } |
| 587 | 2, 6, // 132: case 0x2: { |
| 588 | OPC_CheckPredicate, 10, // 134: check predicate 10 |
| 589 | OPC_Decode, 169, 6, 40, // 136: decode to ADDrsr using decoder 40 |
| 590 | // 136: } |
| 591 | 3, 0, // 140: case 0x3: { |
| 592 | OPC_CheckPredicate, 10, // 142: check predicate 10 |
| 593 | OPC_Decode, 249, 14, 41, // 144: decode to SBCrsr using decoder 41 |
| 594 | // 144: } |
| 595 | // 144: } // switch Inst[23:22] |
| 596 | // 144: } |
| 597 | 1, 0, // 148: case 0x1: { |
| 598 | OPC_SwitchField, 5, 2, // 150: switch Inst[6:5] { |
| 599 | 0, 44, // 153: case 0x0: { |
| 600 | OPC_SwitchField, 22, 2, // 155: switch Inst[23:22] { |
| 601 | 0, 11, // 158: case 0x0: { |
| 602 | OPC_CheckPredicate, 11, // 160: check predicate 11 |
| 603 | OPC_SoftFail, 128, 224, 3, 0, // 162: softfail pos=0x0000f000 neg=0x00000000 |
| 604 | OPC_Decode, 242, 7, 42, // 167: decode to MUL using decoder 42 |
| 605 | // 167: } |
| 606 | 1, 10, // 171: case 0x1: { |
| 607 | OPC_CheckPredicate, 11, // 173: check predicate 11 |
| 608 | OPC_CheckField, 20, 1, 0, // 175: check Inst[20] == 0x0 |
| 609 | OPC_Decode, 159, 16, 43, // 179: decode to UMAAL using decoder 43 |
| 610 | // 179: } |
| 611 | 2, 6, // 183: case 0x2: { |
| 612 | OPC_CheckPredicate, 11, // 185: check predicate 11 |
| 613 | OPC_Decode, 161, 16, 44, // 187: decode to UMULL using decoder 44 |
| 614 | // 187: } |
| 615 | 3, 0, // 191: case 0x3: { |
| 616 | OPC_CheckPredicate, 11, // 193: check predicate 11 |
| 617 | OPC_Decode, 173, 15, 44, // 195: decode to SMULL using decoder 44 |
| 618 | // 195: } |
| 619 | // 195: } // switch Inst[23:22] |
| 620 | // 195: } |
| 621 | 1, 19, // 199: case 0x1: { |
| 622 | OPC_SwitchField, 20, 1, // 201: switch Inst[20] { |
| 623 | 0, 6, // 204: case 0x0: { |
| 624 | OPC_CheckPredicate, 10, // 206: check predicate 10 |
| 625 | OPC_Decode, 242, 15, 45, // 208: decode to STRH_POST using decoder 45 |
| 626 | // 208: } |
| 627 | 1, 0, // 212: case 0x1: { |
| 628 | OPC_CheckPredicate, 10, // 214: check predicate 10 |
| 629 | OPC_Decode, 197, 7, 45, // 216: decode to LDRH_POST using decoder 45 |
| 630 | // 216: } |
| 631 | // 216: } // switch Inst[20] |
| 632 | // 216: } |
| 633 | 2, 19, // 220: case 0x2: { |
| 634 | OPC_SwitchField, 20, 1, // 222: switch Inst[20] { |
| 635 | 0, 6, // 225: case 0x0: { |
| 636 | OPC_CheckPredicate, 10, // 227: check predicate 10 |
| 637 | OPC_Decode, 188, 7, 45, // 229: decode to LDRD_POST using decoder 45 |
| 638 | // 229: } |
| 639 | 1, 0, // 233: case 0x1: { |
| 640 | OPC_CheckPredicate, 10, // 235: check predicate 10 |
| 641 | OPC_Decode, 202, 7, 45, // 237: decode to LDRSB_POST using decoder 45 |
| 642 | // 237: } |
| 643 | // 237: } // switch Inst[20] |
| 644 | // 237: } |
| 645 | 3, 0, // 241: case 0x3: { |
| 646 | OPC_SwitchField, 20, 1, // 243: switch Inst[20] { |
| 647 | 0, 6, // 246: case 0x0: { |
| 648 | OPC_CheckPredicate, 10, // 248: check predicate 10 |
| 649 | OPC_Decode, 233, 15, 45, // 250: decode to STRD_POST using decoder 45 |
| 650 | // 250: } |
| 651 | 1, 0, // 254: case 0x1: { |
| 652 | OPC_CheckPredicate, 10, // 256: check predicate 10 |
| 653 | OPC_Decode, 207, 7, 45, // 258: decode to LDRSH_POST using decoder 45 |
| 654 | // 258: } |
| 655 | // 258: } // switch Inst[20] |
| 656 | // 258: } |
| 657 | // 258: } // switch Inst[6:5] |
| 658 | // 258: } |
| 659 | // 258: } // switch Inst[7] |
| 660 | // 258: } |
| 661 | // 258: } // switch Inst[4] |
| 662 | // 258: } |
| 663 | 1, 0, // 262: case 0x1: { |
| 664 | OPC_Scope, 203, 6, // 264: try { |
| 665 | OPC_SwitchField, 22, 2, // 267: switch Inst[23:22] { |
| 666 | 0, 204, 2, // 270: case 0x0: { |
| 667 | OPC_SwitchField, 20, 1, // 273: switch Inst[20] { |
| 668 | 0, 253, 1, // 276: case 0x0: { |
| 669 | OPC_SwitchField, 5, 1, // 279: switch Inst[5] { |
| 670 | 0, 202, 1, // 282: case 0x0: { |
| 671 | OPC_Scope, 118, // 285: try { |
| 672 | OPC_SwitchField, 28, 4, // 287: switch Inst[31:28] { |
| 673 | 14, 43, // 290: case 0xe: { |
| 674 | OPC_SwitchField, 9, 1, // 292: switch Inst[9] { |
| 675 | 0, 18, // 295: case 0x0: { |
| 676 | OPC_CheckPredicate, 12, // 297: check predicate 12 |
| 677 | OPC_CheckField, 6, 2, 1, // 299: check Inst[7:6] == 0x1 |
| 678 | OPC_CheckField, 4, 1, 0, // 303: check Inst[4] == 0x0 |
| 679 | OPC_SoftFail, 128, 26, 0, // 307: softfail pos=0x00000d00 neg=0x00000000 |
| 680 | OPC_Decode, 248, 6, 46, // 311: decode to CRC32B using decoder 46 |
| 681 | // 311: } |
| 682 | 1, 0, // 315: case 0x1: { |
| 683 | OPC_CheckPredicate, 12, // 317: check predicate 12 |
| 684 | OPC_CheckField, 6, 2, 1, // 319: check Inst[7:6] == 0x1 |
| 685 | OPC_CheckField, 4, 1, 0, // 323: check Inst[4] == 0x0 |
| 686 | OPC_SoftFail, 128, 26, 0, // 327: softfail pos=0x00000d00 neg=0x00000000 |
| 687 | OPC_Decode, 249, 6, 46, // 331: decode to CRC32CB using decoder 46 |
| 688 | // 331: } |
| 689 | // 331: } // switch Inst[9] |
| 690 | // 331: } |
| 691 | 15, 0, // 335: case 0xf: { |
| 692 | OPC_SwitchField, 10, 8, // 337: switch Inst[17:10] { |
| 693 | 0, 14, // 340: case 0x0: { |
| 694 | OPC_CheckPredicate, 10, // 342: check predicate 10 |
| 695 | OPC_CheckField, 9, 1, 0, // 344: check Inst[9] == 0x0 |
| 696 | OPC_CheckField, 0, 5, 0, // 348: check Inst[4:0] == 0x0 |
| 697 | OPC_Decode, 246, 6, 47, // 352: decode to CPS2p using decoder 47 |
| 698 | // 352: } |
| 699 | 64, 18, // 356: case 0x40: { |
| 700 | OPC_CheckPredicate, 10, // 358: check predicate 10 |
| 701 | OPC_CheckField, 18, 2, 0, // 360: check Inst[19:18] == 0x0 |
| 702 | OPC_CheckField, 6, 3, 0, // 364: check Inst[8:6] == 0x0 |
| 703 | OPC_CheckField, 0, 5, 0, // 368: check Inst[4:0] == 0x0 |
| 704 | OPC_Decode, 253, 14, 48, // 372: decode to SETEND using decoder 48 |
| 705 | // 372: } |
| 706 | 128, 1, 0, // 376: case 0x80: { |
| 707 | OPC_CheckField, 9, 1, 0, // 379: check Inst[9] == 0x0 |
| 708 | OPC_Scope, 14, // 383: try { |
| 709 | OPC_CheckField, 6, 3, 0, // 385: check Inst[8:6] == 0x0 |
| 710 | OPC_CheckPredicate, 10, // 389: check predicate 10 |
| 711 | OPC_CheckField, 18, 2, 0, // 391: check Inst[19:18] == 0x0 |
| 712 | OPC_Decode, 245, 6, 47, // 395: decode to CPS1p using decoder 47 |
| 713 | // 395: } else try { |
| 714 | OPC_CheckPredicate, 10, // 399: check predicate 10 |
| 715 | OPC_Decode, 247, 6, 47, // 401: decode to CPS3p using decoder 47 |
| 716 | // 401: } |
| 717 | // 401: } |
| 718 | // 401: } // switch Inst[17:10] |
| 719 | // 401: } |
| 720 | // 401: } // switch Inst[31:28] |
| 721 | // 401: } else try { |
| 722 | OPC_SwitchField, 6, 2, // 405: switch Inst[7:6] { |
| 723 | 0, 24, // 408: case 0x0: { |
| 724 | OPC_CheckPredicate, 10, // 410: check predicate 10 |
| 725 | OPC_CheckField, 16, 1, 1, // 412: check Inst[16] == 0x1 |
| 726 | OPC_CheckField, 9, 1, 0, // 416: check Inst[9] == 0x0 |
| 727 | OPC_CheckField, 4, 1, 0, // 420: check Inst[4] == 0x0 |
| 728 | OPC_SoftFail, 143, 26, 128, 128, 56, // 424: softfail pos=0x00000d0f neg=0x000e0000 |
| 729 | OPC_Decode, 236, 7, 49, // 430: decode to MRS using decoder 49 |
| 730 | // 430: } |
| 731 | 1, 14, // 434: case 0x1: { |
| 732 | OPC_CheckPredicate, 10, // 436: check predicate 10 |
| 733 | OPC_CheckField, 4, 1, 1, // 438: check Inst[4] == 0x1 |
| 734 | OPC_SoftFail, 128, 30, 0, // 442: softfail pos=0x00000f00 neg=0x00000000 |
| 735 | OPC_Decode, 212, 14, 50, // 446: decode to QADD using decoder 50 |
| 736 | // 446: } |
| 737 | 2, 23, // 450: case 0x2: { |
| 738 | OPC_SwitchField, 4, 1, // 452: switch Inst[4] { |
| 739 | 0, 6, // 455: case 0x0: { |
| 740 | OPC_CheckPredicate, 13, // 457: check predicate 13 |
| 741 | OPC_Decode, 144, 15, 51, // 459: decode to SMLABB using decoder 51 |
| 742 | // 459: } |
| 743 | 1, 0, // 463: case 0x1: { |
| 744 | OPC_CheckPredicate, 14, // 465: check predicate 14 |
| 745 | OPC_SoftFail, 128, 30, 0, // 467: softfail pos=0x00000f00 neg=0x00000000 |
| 746 | OPC_Decode, 129, 16, 52, // 471: decode to SWP using decoder 52 |
| 747 | // 471: } |
| 748 | // 471: } // switch Inst[4] |
| 749 | // 471: } |
| 750 | 3, 0, // 475: case 0x3: { |
| 751 | OPC_CheckPredicate, 13, // 477: check predicate 13 |
| 752 | OPC_CheckField, 4, 1, 0, // 479: check Inst[4] == 0x0 |
| 753 | OPC_Decode, 145, 15, 51, // 483: decode to SMLABT using decoder 51 |
| 754 | // 483: } |
| 755 | // 483: } // switch Inst[7:6] |
| 756 | // 483: } |
| 757 | // 483: } |
| 758 | 1, 0, // 487: case 0x1: { |
| 759 | OPC_SwitchField, 6, 2, // 489: switch Inst[7:6] { |
| 760 | 1, 14, // 492: case 0x1: { |
| 761 | OPC_CheckPredicate, 15, // 494: check predicate 15 |
| 762 | OPC_CheckField, 28, 4, 14, // 496: check Inst[31:28] == 0xe |
| 763 | OPC_CheckField, 4, 1, 1, // 500: check Inst[4] == 0x1 |
| 764 | OPC_Decode, 145, 7, 53, // 504: decode to HLT using decoder 53 |
| 765 | // 504: } |
| 766 | 2, 10, // 508: case 0x2: { |
| 767 | OPC_CheckPredicate, 13, // 510: check predicate 13 |
| 768 | OPC_CheckField, 4, 1, 0, // 512: check Inst[4] == 0x0 |
| 769 | OPC_Decode, 155, 15, 51, // 516: decode to SMLATB using decoder 51 |
| 770 | // 516: } |
| 771 | 3, 0, // 520: case 0x3: { |
| 772 | OPC_CheckPredicate, 13, // 522: check predicate 13 |
| 773 | OPC_CheckField, 4, 1, 0, // 524: check Inst[4] == 0x0 |
| 774 | OPC_Decode, 156, 15, 51, // 528: decode to SMLATT using decoder 51 |
| 775 | // 528: } |
| 776 | // 528: } // switch Inst[7:6] |
| 777 | // 528: } |
| 778 | // 528: } // switch Inst[5] |
| 779 | // 528: } |
| 780 | 1, 0, // 532: case 0x1: { |
| 781 | OPC_SwitchField, 4, 1, // 534: switch Inst[4] { |
| 782 | 0, 49, // 537: case 0x0: { |
| 783 | OPC_Scope, 15, // 539: try { |
| 784 | OPC_CheckField, 5, 7, 0, // 541: check Inst[11:5] == 0x0 |
| 785 | OPC_CheckPredicate, 10, // 545: check predicate 10 |
| 786 | OPC_SoftFail, 128, 224, 3, 0, // 547: softfail pos=0x0000f000 neg=0x00000000 |
| 787 | OPC_Decode, 144, 16, 54, // 552: decode to TSTrr using decoder 54 |
| 788 | OPC_Scope, 19, // 556: } else try { |
| 789 | OPC_CheckField, 5, 3, 0, // 558: check Inst[7:5] == 0x0 |
| 790 | OPC_CheckPredicate, 16, // 562: check predicate 16 |
| 791 | OPC_CheckField, 28, 4, 15, // 564: check Inst[31:28] == 0xf |
| 792 | OPC_SoftFail, 143, 250, 63, 0, // 568: softfail pos=0x000ffd0f neg=0x00000000 |
| 793 | OPC_Decode, 254, 14, 48, // 573: decode to SETPAN using decoder 48 |
| 794 | // 573: } else try { |
| 795 | OPC_CheckPredicate, 10, // 577: check predicate 10 |
| 796 | OPC_SoftFail, 128, 224, 3, 0, // 579: softfail pos=0x0000f000 neg=0x00000000 |
| 797 | OPC_Decode, 145, 16, 55, // 584: decode to TSTrsi using decoder 55 |
| 798 | // 584: } |
| 799 | // 584: } |
| 800 | 1, 0, // 588: case 0x1: { |
| 801 | OPC_CheckPredicate, 10, // 590: check predicate 10 |
| 802 | OPC_CheckField, 7, 1, 0, // 592: check Inst[7] == 0x0 |
| 803 | OPC_SoftFail, 128, 224, 3, 0, // 596: softfail pos=0x0000f000 neg=0x00000000 |
| 804 | OPC_Decode, 146, 16, 56, // 601: decode to TSTrsr using decoder 56 |
| 805 | // 601: } |
| 806 | // 601: } // switch Inst[4] |
| 807 | // 601: } |
| 808 | // 601: } // switch Inst[20] |
| 809 | // 601: } |
| 810 | 1, 209, 1, // 605: case 0x1: { |
| 811 | OPC_SwitchField, 4, 1, // 608: switch Inst[4] { |
| 812 | 0, 125, // 611: case 0x0: { |
| 813 | OPC_SwitchField, 20, 1, // 613: switch Inst[20] { |
| 814 | 0, 90, // 616: case 0x0: { |
| 815 | OPC_SwitchField, 5, 3, // 618: switch Inst[7:5] { |
| 816 | 0, 16, // 621: case 0x0: { |
| 817 | OPC_CheckPredicate, 10, // 623: check predicate 10 |
| 818 | OPC_CheckField, 9, 1, 0, // 625: check Inst[9] == 0x0 |
| 819 | OPC_SoftFail, 143, 26, 128, 128, 60, // 629: softfail pos=0x00000d0f neg=0x000f0000 |
| 820 | OPC_Decode, 238, 7, 49, // 635: decode to MRSsys using decoder 49 |
| 821 | // 635: } |
| 822 | 2, 35, // 639: case 0x2: { |
| 823 | OPC_SwitchField, 9, 1, // 641: switch Inst[9] { |
| 824 | 0, 14, // 644: case 0x0: { |
| 825 | OPC_CheckPredicate, 12, // 646: check predicate 12 |
| 826 | OPC_CheckField, 28, 4, 14, // 648: check Inst[31:28] == 0xe |
| 827 | OPC_SoftFail, 128, 26, 0, // 652: softfail pos=0x00000d00 neg=0x00000000 |
| 828 | OPC_Decode, 253, 6, 46, // 656: decode to CRC32W using decoder 46 |
| 829 | // 656: } |
| 830 | 1, 0, // 660: case 0x1: { |
| 831 | OPC_CheckPredicate, 12, // 662: check predicate 12 |
| 832 | OPC_CheckField, 28, 4, 14, // 664: check Inst[31:28] == 0xe |
| 833 | OPC_SoftFail, 128, 26, 0, // 668: softfail pos=0x00000d00 neg=0x00000000 |
| 834 | OPC_Decode, 251, 6, 46, // 672: decode to CRC32CW using decoder 46 |
| 835 | // 672: } |
| 836 | // 672: } // switch Inst[9] |
| 837 | // 672: } |
| 838 | 4, 6, // 676: case 0x4: { |
| 839 | OPC_CheckPredicate, 13, // 678: check predicate 13 |
| 840 | OPC_Decode, 149, 15, 57, // 680: decode to SMLALBB using decoder 57 |
| 841 | // 680: } |
| 842 | 5, 6, // 684: case 0x5: { |
| 843 | OPC_CheckPredicate, 13, // 686: check predicate 13 |
| 844 | OPC_Decode, 153, 15, 57, // 688: decode to SMLALTB using decoder 57 |
| 845 | // 688: } |
| 846 | 6, 6, // 692: case 0x6: { |
| 847 | OPC_CheckPredicate, 13, // 694: check predicate 13 |
| 848 | OPC_Decode, 150, 15, 57, // 696: decode to SMLALBT using decoder 57 |
| 849 | // 696: } |
| 850 | 7, 0, // 700: case 0x7: { |
| 851 | OPC_CheckPredicate, 13, // 702: check predicate 13 |
| 852 | OPC_Decode, 154, 15, 57, // 704: decode to SMLALTT using decoder 57 |
| 853 | // 704: } |
| 854 | // 704: } // switch Inst[7:5] |
| 855 | // 704: } |
| 856 | 1, 0, // 708: case 0x1: { |
| 857 | OPC_Scope, 15, // 710: try { |
| 858 | OPC_CheckField, 5, 7, 0, // 712: check Inst[11:5] == 0x0 |
| 859 | OPC_CheckPredicate, 10, // 716: check predicate 10 |
| 860 | OPC_SoftFail, 128, 224, 3, 0, // 718: softfail pos=0x0000f000 neg=0x00000000 |
| 861 | OPC_Decode, 242, 6, 58, // 723: decode to CMPrr using decoder 58 |
| 862 | // 723: } else try { |
| 863 | OPC_CheckPredicate, 10, // 727: check predicate 10 |
| 864 | OPC_SoftFail, 128, 224, 3, 0, // 729: softfail pos=0x0000f000 neg=0x00000000 |
| 865 | OPC_Decode, 243, 6, 55, // 734: decode to CMPrsi using decoder 55 |
| 866 | // 734: } |
| 867 | // 734: } |
| 868 | // 734: } // switch Inst[20] |
| 869 | // 734: } |
| 870 | 1, 0, // 738: case 0x1: { |
| 871 | OPC_SwitchField, 7, 1, // 740: switch Inst[7] { |
| 872 | 0, 52, // 743: case 0x0: { |
| 873 | OPC_SwitchField, 20, 1, // 745: switch Inst[20] { |
| 874 | 0, 34, // 748: case 0x0: { |
| 875 | OPC_SwitchField, 5, 2, // 750: switch Inst[6:5] { |
| 876 | 2, 10, // 753: case 0x2: { |
| 877 | OPC_CheckPredicate, 10, // 755: check predicate 10 |
| 878 | OPC_SoftFail, 128, 30, 0, // 757: softfail pos=0x00000f00 neg=0x00000000 |
| 879 | OPC_Decode, 216, 14, 59, // 761: decode to QDADD using decoder 59 |
| 880 | // 761: } |
| 881 | 3, 0, // 765: case 0x3: { |
| 882 | OPC_CheckPredicate, 17, // 767: check predicate 17 |
| 883 | OPC_SoftFail, 128, 128, 128, 128, 1, 128, 128, 128, 128, 14, |
| 884 | // 769: softfail pos=0x10000000 neg=0xe0000000 |
| 885 | OPC_Decode, 146, 7, 53, // 780: decode to HVC using decoder 53 |
| 886 | // 780: } |
| 887 | // 780: } // switch Inst[6:5] |
| 888 | // 780: } |
| 889 | 1, 0, // 784: case 0x1: { |
| 890 | OPC_CheckPredicate, 10, // 786: check predicate 10 |
| 891 | OPC_SoftFail, 128, 224, 3, 0, // 788: softfail pos=0x0000f000 neg=0x00000000 |
| 892 | OPC_Decode, 244, 6, 56, // 793: decode to CMPrsr using decoder 56 |
| 893 | // 793: } |
| 894 | // 793: } // switch Inst[20] |
| 895 | // 793: } |
| 896 | 1, 0, // 797: case 0x1: { |
| 897 | OPC_CheckPredicate, 14, // 799: check predicate 14 |
| 898 | OPC_CheckField, 20, 1, 0, // 801: check Inst[20] == 0x0 |
| 899 | OPC_CheckField, 5, 2, 0, // 805: check Inst[6:5] == 0x0 |
| 900 | OPC_SoftFail, 128, 30, 0, // 809: softfail pos=0x00000f00 neg=0x00000000 |
| 901 | OPC_Decode, 130, 16, 52, // 813: decode to SWPB using decoder 52 |
| 902 | // 813: } |
| 903 | // 813: } // switch Inst[7] |
| 904 | // 813: } |
| 905 | // 813: } // switch Inst[4] |
| 906 | // 813: } |
| 907 | 2, 144, 1, // 817: case 0x2: { |
| 908 | OPC_SwitchField, 4, 1, // 820: switch Inst[4] { |
| 909 | 0, 18, // 823: case 0x0: { |
| 910 | OPC_Scope, 10, // 825: try { |
| 911 | OPC_CheckField, 5, 7, 0, // 827: check Inst[11:5] == 0x0 |
| 912 | OPC_CheckPredicate, 10, // 831: check predicate 10 |
| 913 | OPC_Decode, 201, 14, 38, // 833: decode to ORRrr using decoder 38 |
| 914 | // 833: } else try { |
| 915 | OPC_CheckPredicate, 10, // 837: check predicate 10 |
| 916 | OPC_Decode, 202, 14, 39, // 839: decode to ORRrsi using decoder 39 |
| 917 | // 839: } |
| 918 | // 839: } |
| 919 | 1, 0, // 843: case 0x1: { |
| 920 | OPC_SwitchField, 7, 1, // 845: switch Inst[7] { |
| 921 | 0, 6, // 848: case 0x0: { |
| 922 | OPC_CheckPredicate, 10, // 850: check predicate 10 |
| 923 | OPC_Decode, 203, 14, 40, // 852: decode to ORRrsr using decoder 40 |
| 924 | // 852: } |
| 925 | 1, 0, // 856: case 0x1: { |
| 926 | OPC_SwitchField, 8, 4, // 858: switch Inst[11:8] { |
| 927 | 12, 35, // 861: case 0xc: { |
| 928 | OPC_SwitchField, 20, 1, // 863: switch Inst[20] { |
| 929 | 0, 14, // 866: case 0x0: { |
| 930 | OPC_CheckPredicate, 18, // 868: check predicate 18 |
| 931 | OPC_CheckField, 12, 4, 15, // 870: check Inst[15:12] == 0xf |
| 932 | OPC_CheckField, 5, 2, 0, // 874: check Inst[6:5] == 0x0 |
| 933 | OPC_Decode, 209, 15, 60, // 878: decode to STL using decoder 60 |
| 934 | // 878: } |
| 935 | 1, 0, // 882: case 0x1: { |
| 936 | OPC_CheckPredicate, 18, // 884: check predicate 18 |
| 937 | OPC_CheckField, 5, 2, 0, // 886: check Inst[6:5] == 0x0 |
| 938 | OPC_CheckField, 0, 4, 15, // 890: check Inst[3:0] == 0xf |
| 939 | OPC_Decode, 148, 7, 61, // 894: decode to LDA using decoder 61 |
| 940 | // 894: } |
| 941 | // 894: } // switch Inst[20] |
| 942 | // 894: } |
| 943 | 14, 31, // 898: case 0xe: { |
| 944 | OPC_SwitchField, 20, 1, // 900: switch Inst[20] { |
| 945 | 0, 10, // 903: case 0x0: { |
| 946 | OPC_CheckPredicate, 19, // 905: check predicate 19 |
| 947 | OPC_CheckField, 5, 2, 0, // 907: check Inst[6:5] == 0x0 |
| 948 | OPC_Decode, 211, 15, 62, // 911: decode to STLEX using decoder 62 |
| 949 | // 911: } |
| 950 | 1, 0, // 915: case 0x1: { |
| 951 | OPC_CheckPredicate, 19, // 917: check predicate 19 |
| 952 | OPC_CheckField, 5, 2, 0, // 919: check Inst[6:5] == 0x0 |
| 953 | OPC_CheckField, 0, 4, 15, // 923: check Inst[3:0] == 0xf |
| 954 | OPC_Decode, 150, 7, 61, // 927: decode to LDAEX using decoder 61 |
| 955 | // 927: } |
| 956 | // 927: } // switch Inst[20] |
| 957 | // 927: } |
| 958 | 15, 0, // 931: case 0xf: { |
| 959 | OPC_SwitchField, 20, 1, // 933: switch Inst[20] { |
| 960 | 0, 10, // 936: case 0x0: { |
| 961 | OPC_CheckPredicate, 10, // 938: check predicate 10 |
| 962 | OPC_CheckField, 5, 2, 0, // 940: check Inst[6:5] == 0x0 |
| 963 | OPC_Decode, 235, 15, 62, // 944: decode to STREX using decoder 62 |
| 964 | // 944: } |
| 965 | 1, 0, // 948: case 0x1: { |
| 966 | OPC_CheckPredicate, 10, // 950: check predicate 10 |
| 967 | OPC_CheckField, 5, 2, 0, // 952: check Inst[6:5] == 0x0 |
| 968 | OPC_CheckField, 0, 4, 15, // 956: check Inst[3:0] == 0xf |
| 969 | OPC_Decode, 190, 7, 61, // 960: decode to LDREX using decoder 61 |
| 970 | // 960: } |
| 971 | // 960: } // switch Inst[20] |
| 972 | // 960: } |
| 973 | // 960: } // switch Inst[11:8] |
| 974 | // 960: } |
| 975 | // 960: } // switch Inst[7] |
| 976 | // 960: } |
| 977 | // 960: } // switch Inst[4] |
| 978 | // 960: } |
| 979 | 3, 0, // 964: case 0x3: { |
| 980 | OPC_SwitchField, 4, 1, // 966: switch Inst[4] { |
| 981 | 0, 18, // 969: case 0x0: { |
| 982 | OPC_Scope, 10, // 971: try { |
| 983 | OPC_CheckField, 5, 7, 0, // 973: check Inst[11:5] == 0x0 |
| 984 | OPC_CheckPredicate, 10, // 977: check predicate 10 |
| 985 | OPC_Decode, 189, 6, 38, // 979: decode to BICrr using decoder 38 |
| 986 | // 979: } else try { |
| 987 | OPC_CheckPredicate, 10, // 983: check predicate 10 |
| 988 | OPC_Decode, 190, 6, 39, // 985: decode to BICrsi using decoder 39 |
| 989 | // 985: } |
| 990 | // 985: } |
| 991 | 1, 0, // 989: case 0x1: { |
| 992 | OPC_SwitchField, 7, 1, // 991: switch Inst[7] { |
| 993 | 0, 6, // 994: case 0x0: { |
| 994 | OPC_CheckPredicate, 10, // 996: check predicate 10 |
| 995 | OPC_Decode, 191, 6, 40, // 998: decode to BICrsr using decoder 40 |
| 996 | // 998: } |
| 997 | 1, 0, // 1002: case 0x1: { |
| 998 | OPC_SwitchField, 8, 4, // 1004: switch Inst[11:8] { |
| 999 | 12, 35, // 1007: case 0xc: { |
| 1000 | OPC_SwitchField, 20, 1, // 1009: switch Inst[20] { |
| 1001 | 0, 14, // 1012: case 0x0: { |
| 1002 | OPC_CheckPredicate, 18, // 1014: check predicate 18 |
| 1003 | OPC_CheckField, 12, 4, 15, // 1016: check Inst[15:12] == 0xf |
| 1004 | OPC_CheckField, 5, 2, 0, // 1020: check Inst[6:5] == 0x0 |
| 1005 | OPC_Decode, 210, 15, 60, // 1024: decode to STLB using decoder 60 |
| 1006 | // 1024: } |
| 1007 | 1, 0, // 1028: case 0x1: { |
| 1008 | OPC_CheckPredicate, 18, // 1030: check predicate 18 |
| 1009 | OPC_CheckField, 5, 2, 0, // 1032: check Inst[6:5] == 0x0 |
| 1010 | OPC_CheckField, 0, 4, 15, // 1036: check Inst[3:0] == 0xf |
| 1011 | OPC_Decode, 149, 7, 61, // 1040: decode to LDAB using decoder 61 |
| 1012 | // 1040: } |
| 1013 | // 1040: } // switch Inst[20] |
| 1014 | // 1040: } |
| 1015 | 14, 31, // 1044: case 0xe: { |
| 1016 | OPC_SwitchField, 20, 1, // 1046: switch Inst[20] { |
| 1017 | 0, 10, // 1049: case 0x0: { |
| 1018 | OPC_CheckPredicate, 19, // 1051: check predicate 19 |
| 1019 | OPC_CheckField, 5, 2, 0, // 1053: check Inst[6:5] == 0x0 |
| 1020 | OPC_Decode, 212, 15, 62, // 1057: decode to STLEXB using decoder 62 |
| 1021 | // 1057: } |
| 1022 | 1, 0, // 1061: case 0x1: { |
| 1023 | OPC_CheckPredicate, 19, // 1063: check predicate 19 |
| 1024 | OPC_CheckField, 5, 2, 0, // 1065: check Inst[6:5] == 0x0 |
| 1025 | OPC_CheckField, 0, 4, 15, // 1069: check Inst[3:0] == 0xf |
| 1026 | OPC_Decode, 151, 7, 61, // 1073: decode to LDAEXB using decoder 61 |
| 1027 | // 1073: } |
| 1028 | // 1073: } // switch Inst[20] |
| 1029 | // 1073: } |
| 1030 | 15, 0, // 1077: case 0xf: { |
| 1031 | OPC_SwitchField, 20, 1, // 1079: switch Inst[20] { |
| 1032 | 0, 10, // 1082: case 0x0: { |
| 1033 | OPC_CheckPredicate, 10, // 1084: check predicate 10 |
| 1034 | OPC_CheckField, 5, 2, 0, // 1086: check Inst[6:5] == 0x0 |
| 1035 | OPC_Decode, 236, 15, 62, // 1090: decode to STREXB using decoder 62 |
| 1036 | // 1090: } |
| 1037 | 1, 0, // 1094: case 0x1: { |
| 1038 | OPC_CheckPredicate, 10, // 1096: check predicate 10 |
| 1039 | OPC_CheckField, 5, 2, 0, // 1098: check Inst[6:5] == 0x0 |
| 1040 | OPC_CheckField, 0, 4, 15, // 1102: check Inst[3:0] == 0xf |
| 1041 | OPC_Decode, 191, 7, 61, // 1106: decode to LDREXB using decoder 61 |
| 1042 | // 1106: } |
| 1043 | // 1106: } // switch Inst[20] |
| 1044 | // 1106: } |
| 1045 | // 1106: } // switch Inst[11:8] |
| 1046 | // 1106: } |
| 1047 | // 1106: } // switch Inst[7] |
| 1048 | // 1106: } |
| 1049 | // 1106: } // switch Inst[4] |
| 1050 | // 1106: } |
| 1051 | // 1106: } // switch Inst[23:22] |
| 1052 | // 1106: } else try { |
| 1053 | OPC_SwitchField, 4, 4, // 1110: switch Inst[7:4] { |
| 1054 | 0, 22, // 1113: case 0x0: { |
| 1055 | OPC_CheckPredicate, 17, // 1115: check predicate 17 |
| 1056 | OPC_CheckField, 23, 1, 0, // 1117: check Inst[23] == 0x0 |
| 1057 | OPC_CheckField, 20, 1, 0, // 1121: check Inst[20] == 0x0 |
| 1058 | OPC_CheckField, 9, 3, 1, // 1125: check Inst[11:9] == 0x1 |
| 1059 | OPC_CheckField, 0, 4, 0, // 1129: check Inst[3:0] == 0x0 |
| 1060 | OPC_Decode, 237, 7, 63, // 1133: decode to MRSbanked using decoder 63 |
| 1061 | // 1133: } |
| 1062 | 11, 19, // 1137: case 0xb: { |
| 1063 | OPC_SwitchField, 20, 1, // 1139: switch Inst[20] { |
| 1064 | 0, 6, // 1142: case 0x0: { |
| 1065 | OPC_CheckPredicate, 10, // 1144: check predicate 10 |
| 1066 | OPC_Decode, 239, 15, 45, // 1146: decode to STRH using decoder 45 |
| 1067 | // 1146: } |
| 1068 | 1, 0, // 1150: case 0x1: { |
| 1069 | OPC_CheckPredicate, 10, // 1152: check predicate 10 |
| 1070 | OPC_Decode, 194, 7, 45, // 1154: decode to LDRH using decoder 45 |
| 1071 | // 1154: } |
| 1072 | // 1154: } // switch Inst[20] |
| 1073 | // 1154: } |
| 1074 | 13, 19, // 1158: case 0xd: { |
| 1075 | OPC_SwitchField, 20, 1, // 1160: switch Inst[20] { |
| 1076 | 0, 6, // 1163: case 0x0: { |
| 1077 | OPC_CheckPredicate, 13, // 1165: check predicate 13 |
| 1078 | OPC_Decode, 187, 7, 45, // 1167: decode to LDRD using decoder 45 |
| 1079 | // 1167: } |
| 1080 | 1, 0, // 1171: case 0x1: { |
| 1081 | OPC_CheckPredicate, 10, // 1173: check predicate 10 |
| 1082 | OPC_Decode, 199, 7, 45, // 1175: decode to LDRSB using decoder 45 |
| 1083 | // 1175: } |
| 1084 | // 1175: } // switch Inst[20] |
| 1085 | // 1175: } |
| 1086 | 15, 0, // 1179: case 0xf: { |
| 1087 | OPC_SwitchField, 20, 1, // 1181: switch Inst[20] { |
| 1088 | 0, 6, // 1184: case 0x0: { |
| 1089 | OPC_CheckPredicate, 13, // 1186: check predicate 13 |
| 1090 | OPC_Decode, 232, 15, 45, // 1188: decode to STRD using decoder 45 |
| 1091 | // 1188: } |
| 1092 | 1, 0, // 1192: case 0x1: { |
| 1093 | OPC_CheckPredicate, 10, // 1194: check predicate 10 |
| 1094 | OPC_Decode, 204, 7, 45, // 1196: decode to LDRSH using decoder 45 |
| 1095 | // 1196: } |
| 1096 | // 1196: } // switch Inst[20] |
| 1097 | // 1196: } |
| 1098 | // 1196: } // switch Inst[7:4] |
| 1099 | // 1196: } |
| 1100 | // 1196: } |
| 1101 | // 1196: } // switch Inst[24] |
| 1102 | // 1196: } |
| 1103 | 1, 0, // 1200: case 0x1: { |
| 1104 | OPC_SwitchField, 4, 1, // 1202: switch Inst[4] { |
| 1105 | 0, 193, 3, // 1205: case 0x0: { |
| 1106 | OPC_SwitchField, 23, 2, // 1208: switch Inst[24:23] { |
| 1107 | 0, 43, // 1211: case 0x0: { |
| 1108 | OPC_SwitchField, 22, 1, // 1213: switch Inst[22] { |
| 1109 | 0, 18, // 1216: case 0x0: { |
| 1110 | OPC_Scope, 10, // 1218: try { |
| 1111 | OPC_CheckField, 5, 7, 0, // 1220: check Inst[11:5] == 0x0 |
| 1112 | OPC_CheckPredicate, 10, // 1224: check predicate 10 |
| 1113 | OPC_Decode, 130, 7, 38, // 1226: decode to EORrr using decoder 38 |
| 1114 | // 1226: } else try { |
| 1115 | OPC_CheckPredicate, 10, // 1230: check predicate 10 |
| 1116 | OPC_Decode, 131, 7, 39, // 1232: decode to EORrsi using decoder 39 |
| 1117 | // 1232: } |
| 1118 | // 1232: } |
| 1119 | 1, 0, // 1236: case 0x1: { |
| 1120 | OPC_Scope, 10, // 1238: try { |
| 1121 | OPC_CheckField, 5, 7, 0, // 1240: check Inst[11:5] == 0x0 |
| 1122 | OPC_CheckPredicate, 10, // 1244: check predicate 10 |
| 1123 | OPC_Decode, 235, 14, 38, // 1246: decode to RSBrr using decoder 38 |
| 1124 | // 1246: } else try { |
| 1125 | OPC_CheckPredicate, 10, // 1250: check predicate 10 |
| 1126 | OPC_Decode, 236, 14, 39, // 1252: decode to RSBrsi using decoder 39 |
| 1127 | // 1252: } |
| 1128 | // 1252: } |
| 1129 | // 1252: } // switch Inst[22] |
| 1130 | // 1252: } |
| 1131 | 1, 43, // 1256: case 0x1: { |
| 1132 | OPC_SwitchField, 22, 1, // 1258: switch Inst[22] { |
| 1133 | 0, 18, // 1261: case 0x0: { |
| 1134 | OPC_Scope, 10, // 1263: try { |
| 1135 | OPC_CheckField, 5, 7, 0, // 1265: check Inst[11:5] == 0x0 |
| 1136 | OPC_CheckPredicate, 10, // 1269: check predicate 10 |
| 1137 | OPC_Decode, 163, 6, 38, // 1271: decode to ADCrr using decoder 38 |
| 1138 | // 1271: } else try { |
| 1139 | OPC_CheckPredicate, 10, // 1275: check predicate 10 |
| 1140 | OPC_Decode, 164, 6, 39, // 1277: decode to ADCrsi using decoder 39 |
| 1141 | // 1277: } |
| 1142 | // 1277: } |
| 1143 | 1, 0, // 1281: case 0x1: { |
| 1144 | OPC_Scope, 10, // 1283: try { |
| 1145 | OPC_CheckField, 5, 7, 0, // 1285: check Inst[11:5] == 0x0 |
| 1146 | OPC_CheckPredicate, 10, // 1289: check predicate 10 |
| 1147 | OPC_Decode, 239, 14, 38, // 1291: decode to RSCrr using decoder 38 |
| 1148 | // 1291: } else try { |
| 1149 | OPC_CheckPredicate, 10, // 1295: check predicate 10 |
| 1150 | OPC_Decode, 240, 14, 39, // 1297: decode to RSCrsi using decoder 39 |
| 1151 | // 1297: } |
| 1152 | // 1297: } |
| 1153 | // 1297: } // switch Inst[22] |
| 1154 | // 1297: } |
| 1155 | 2, 137, 2, // 1301: case 0x2: { |
| 1156 | OPC_SwitchField, 20, 1, // 1304: switch Inst[20] { |
| 1157 | 0, 194, 1, // 1307: case 0x0: { |
| 1158 | OPC_SwitchField, 5, 3, // 1310: switch Inst[7:5] { |
| 1159 | 0, 23, // 1313: case 0x0: { |
| 1160 | OPC_SwitchField, 9, 7, // 1315: switch Inst[15:9] { |
| 1161 | 120, 10, // 1318: case 0x78: { |
| 1162 | OPC_CheckPredicate, 10, // 1320: check predicate 10 |
| 1163 | OPC_CheckField, 8, 1, 0, // 1322: check Inst[8] == 0x0 |
| 1164 | OPC_Decode, 239, 7, 64, // 1326: decode to MSR using decoder 64 |
| 1165 | // 1326: } |
| 1166 | 121, 0, // 1330: case 0x79: { |
| 1167 | OPC_CheckPredicate, 17, // 1332: check predicate 17 |
| 1168 | OPC_Decode, 240, 7, 65, // 1334: decode to MSRbanked using decoder 65 |
| 1169 | // 1334: } |
| 1170 | // 1334: } // switch Inst[15:9] |
| 1171 | // 1334: } |
| 1172 | 1, 15, // 1338: case 0x1: { |
| 1173 | OPC_CheckPredicate, 10, // 1340: check predicate 10 |
| 1174 | OPC_CheckField, 22, 1, 0, // 1342: check Inst[22] == 0x0 |
| 1175 | OPC_CheckField, 8, 12, 255, 31, // 1346: check Inst[19:8] == 0xfff |
| 1176 | OPC_Decode, 199, 6, 66, // 1351: decode to BXJ using decoder 66 |
| 1177 | // 1351: } |
| 1178 | 2, 43, // 1355: case 0x2: { |
| 1179 | OPC_SwitchField, 9, 1, // 1357: switch Inst[9] { |
| 1180 | 0, 18, // 1360: case 0x0: { |
| 1181 | OPC_CheckPredicate, 12, // 1362: check predicate 12 |
| 1182 | OPC_CheckField, 28, 4, 14, // 1364: check Inst[31:28] == 0xe |
| 1183 | OPC_CheckField, 22, 1, 0, // 1368: check Inst[22] == 0x0 |
| 1184 | OPC_SoftFail, 128, 26, 0, // 1372: softfail pos=0x00000d00 neg=0x00000000 |
| 1185 | OPC_Decode, 252, 6, 46, // 1376: decode to CRC32H using decoder 46 |
| 1186 | // 1376: } |
| 1187 | 1, 0, // 1380: case 0x1: { |
| 1188 | OPC_CheckPredicate, 12, // 1382: check predicate 12 |
| 1189 | OPC_CheckField, 28, 4, 14, // 1384: check Inst[31:28] == 0xe |
| 1190 | OPC_CheckField, 22, 1, 0, // 1388: check Inst[22] == 0x0 |
| 1191 | OPC_SoftFail, 128, 26, 0, // 1392: softfail pos=0x00000d00 neg=0x00000000 |
| 1192 | OPC_Decode, 250, 6, 46, // 1396: decode to CRC32CH using decoder 46 |
| 1193 | // 1396: } |
| 1194 | // 1396: } // switch Inst[9] |
| 1195 | // 1396: } |
| 1196 | 3, 18, // 1400: case 0x3: { |
| 1197 | OPC_CheckPredicate, 17, // 1402: check predicate 17 |
| 1198 | OPC_CheckField, 22, 1, 1, // 1404: check Inst[22] == 0x1 |
| 1199 | OPC_CheckField, 8, 12, 0, // 1408: check Inst[19:8] == 0x0 |
| 1200 | OPC_CheckField, 0, 4, 14, // 1412: check Inst[3:0] == 0xe |
| 1201 | OPC_Decode, 133, 7, 67, // 1416: decode to ERET using decoder 67 |
| 1202 | // 1416: } |
| 1203 | 4, 19, // 1420: case 0x4: { |
| 1204 | OPC_SwitchField, 22, 1, // 1422: switch Inst[22] { |
| 1205 | 0, 6, // 1425: case 0x0: { |
| 1206 | OPC_CheckPredicate, 13, // 1427: check predicate 13 |
| 1207 | OPC_Decode, 157, 15, 51, // 1429: decode to SMLAWB using decoder 51 |
| 1208 | // 1429: } |
| 1209 | 1, 0, // 1433: case 0x1: { |
| 1210 | OPC_CheckPredicate, 13, // 1435: check predicate 13 |
| 1211 | OPC_Decode, 171, 15, 68, // 1437: decode to SMULBB using decoder 68 |
| 1212 | // 1437: } |
| 1213 | // 1437: } // switch Inst[22] |
| 1214 | // 1437: } |
| 1215 | 5, 19, // 1441: case 0x5: { |
| 1216 | OPC_SwitchField, 22, 1, // 1443: switch Inst[22] { |
| 1217 | 0, 6, // 1446: case 0x0: { |
| 1218 | OPC_CheckPredicate, 13, // 1448: check predicate 13 |
| 1219 | OPC_Decode, 176, 15, 68, // 1450: decode to SMULWB using decoder 68 |
| 1220 | // 1450: } |
| 1221 | 1, 0, // 1454: case 0x1: { |
| 1222 | OPC_CheckPredicate, 13, // 1456: check predicate 13 |
| 1223 | OPC_Decode, 174, 15, 68, // 1458: decode to SMULTB using decoder 68 |
| 1224 | // 1458: } |
| 1225 | // 1458: } // switch Inst[22] |
| 1226 | // 1458: } |
| 1227 | 6, 19, // 1462: case 0x6: { |
| 1228 | OPC_SwitchField, 22, 1, // 1464: switch Inst[22] { |
| 1229 | 0, 6, // 1467: case 0x0: { |
| 1230 | OPC_CheckPredicate, 13, // 1469: check predicate 13 |
| 1231 | OPC_Decode, 158, 15, 51, // 1471: decode to SMLAWT using decoder 51 |
| 1232 | // 1471: } |
| 1233 | 1, 0, // 1475: case 0x1: { |
| 1234 | OPC_CheckPredicate, 13, // 1477: check predicate 13 |
| 1235 | OPC_Decode, 172, 15, 68, // 1479: decode to SMULBT using decoder 68 |
| 1236 | // 1479: } |
| 1237 | // 1479: } // switch Inst[22] |
| 1238 | // 1479: } |
| 1239 | 7, 0, // 1483: case 0x7: { |
| 1240 | OPC_SwitchField, 22, 1, // 1485: switch Inst[22] { |
| 1241 | 0, 6, // 1488: case 0x0: { |
| 1242 | OPC_CheckPredicate, 13, // 1490: check predicate 13 |
| 1243 | OPC_Decode, 177, 15, 68, // 1492: decode to SMULWT using decoder 68 |
| 1244 | // 1492: } |
| 1245 | 1, 0, // 1496: case 0x1: { |
| 1246 | OPC_CheckPredicate, 13, // 1498: check predicate 13 |
| 1247 | OPC_Decode, 175, 15, 68, // 1500: decode to SMULTT using decoder 68 |
| 1248 | // 1500: } |
| 1249 | // 1500: } // switch Inst[22] |
| 1250 | // 1500: } |
| 1251 | // 1500: } // switch Inst[7:5] |
| 1252 | // 1500: } |
| 1253 | 1, 0, // 1504: case 0x1: { |
| 1254 | OPC_SwitchField, 22, 1, // 1506: switch Inst[22] { |
| 1255 | 0, 28, // 1509: case 0x0: { |
| 1256 | OPC_Scope, 15, // 1511: try { |
| 1257 | OPC_CheckField, 5, 7, 0, // 1513: check Inst[11:5] == 0x0 |
| 1258 | OPC_CheckPredicate, 10, // 1517: check predicate 10 |
| 1259 | OPC_SoftFail, 128, 224, 3, 0, // 1519: softfail pos=0x0000f000 neg=0x00000000 |
| 1260 | OPC_Decode, 138, 16, 58, // 1524: decode to TEQrr using decoder 58 |
| 1261 | // 1524: } else try { |
| 1262 | OPC_CheckPredicate, 10, // 1528: check predicate 10 |
| 1263 | OPC_SoftFail, 128, 224, 3, 0, // 1530: softfail pos=0x0000f000 neg=0x00000000 |
| 1264 | OPC_Decode, 139, 16, 55, // 1535: decode to TEQrsi using decoder 55 |
| 1265 | // 1535: } |
| 1266 | // 1535: } |
| 1267 | 1, 0, // 1539: case 0x1: { |
| 1268 | OPC_Scope, 15, // 1541: try { |
| 1269 | OPC_CheckField, 5, 7, 0, // 1543: check Inst[11:5] == 0x0 |
| 1270 | OPC_CheckPredicate, 10, // 1547: check predicate 10 |
| 1271 | OPC_SoftFail, 128, 224, 3, 0, // 1549: softfail pos=0x0000f000 neg=0x00000000 |
| 1272 | OPC_Decode, 238, 6, 58, // 1554: decode to CMNzrr using decoder 58 |
| 1273 | // 1554: } else try { |
| 1274 | OPC_CheckPredicate, 10, // 1558: check predicate 10 |
| 1275 | OPC_SoftFail, 128, 224, 3, 0, // 1560: softfail pos=0x0000f000 neg=0x00000000 |
| 1276 | OPC_Decode, 239, 6, 55, // 1565: decode to CMNzrsi using decoder 55 |
| 1277 | // 1565: } |
| 1278 | // 1565: } |
| 1279 | // 1565: } // switch Inst[22] |
| 1280 | // 1565: } |
| 1281 | // 1565: } // switch Inst[20] |
| 1282 | // 1565: } |
| 1283 | 3, 0, // 1569: case 0x3: { |
| 1284 | OPC_SwitchField, 22, 1, // 1571: switch Inst[22] { |
| 1285 | 0, 51, // 1574: case 0x0: { |
| 1286 | OPC_Scope, 15, // 1576: try { |
| 1287 | OPC_CheckField, 0, 4, 14, // 1578: check Inst[3:0] == 0xe |
| 1288 | OPC_CheckPredicate, 10, // 1582: check predicate 10 |
| 1289 | OPC_CheckField, 5, 16, 128, 15, // 1584: check Inst[20:5] == 0x780 |
| 1290 | OPC_Decode, 224, 7, 67, // 1589: decode to MOVPCLR using decoder 67 |
| 1291 | OPC_Scope, 22, // 1593: } else try { |
| 1292 | OPC_CheckField, 5, 7, 0, // 1595: check Inst[11:5] == 0x0 |
| 1293 | OPC_Scope, 10, // 1599: try { |
| 1294 | OPC_CheckField, 16, 4, 0, // 1601: check Inst[19:16] == 0x0 |
| 1295 | OPC_CheckPredicate, 10, // 1605: check predicate 10 |
| 1296 | OPC_Decode, 228, 7, 69, // 1607: decode to MOVr using decoder 69 |
| 1297 | // 1607: } else try { |
| 1298 | OPC_CheckPredicate, 10, // 1611: check predicate 10 |
| 1299 | OPC_Decode, 229, 7, 70, // 1613: decode to MOVr_TC using decoder 70 |
| 1300 | // 1613: } |
| 1301 | // 1613: } else try { |
| 1302 | OPC_CheckPredicate, 10, // 1617: check predicate 10 |
| 1303 | OPC_CheckField, 16, 4, 0, // 1619: check Inst[19:16] == 0x0 |
| 1304 | OPC_Decode, 230, 7, 71, // 1623: decode to MOVsi using decoder 71 |
| 1305 | // 1623: } |
| 1306 | // 1623: } |
| 1307 | 1, 0, // 1627: case 0x1: { |
| 1308 | OPC_Scope, 15, // 1629: try { |
| 1309 | OPC_CheckField, 5, 7, 0, // 1631: check Inst[11:5] == 0x0 |
| 1310 | OPC_CheckPredicate, 10, // 1635: check predicate 10 |
| 1311 | OPC_SoftFail, 128, 128, 60, 0, // 1637: softfail pos=0x000f0000 neg=0x00000000 |
| 1312 | OPC_Decode, 189, 14, 69, // 1642: decode to MVNr using decoder 69 |
| 1313 | // 1642: } else try { |
| 1314 | OPC_CheckPredicate, 10, // 1646: check predicate 10 |
| 1315 | OPC_SoftFail, 128, 128, 60, 0, // 1648: softfail pos=0x000f0000 neg=0x00000000 |
| 1316 | OPC_Decode, 190, 14, 71, // 1653: decode to MVNsi using decoder 71 |
| 1317 | // 1653: } |
| 1318 | // 1653: } |
| 1319 | // 1653: } // switch Inst[22] |
| 1320 | // 1653: } |
| 1321 | // 1653: } // switch Inst[24:23] |
| 1322 | // 1653: } |
| 1323 | 1, 0, // 1657: case 0x1: { |
| 1324 | OPC_SwitchField, 7, 1, // 1659: switch Inst[7] { |
| 1325 | 0, 232, 1, // 1662: case 0x0: { |
| 1326 | OPC_SwitchField, 22, 3, // 1665: switch Inst[24:22] { |
| 1327 | 0, 6, // 1668: case 0x0: { |
| 1328 | OPC_CheckPredicate, 10, // 1670: check predicate 10 |
| 1329 | OPC_Decode, 132, 7, 40, // 1672: decode to EORrsr using decoder 40 |
| 1330 | // 1672: } |
| 1331 | 1, 6, // 1676: case 0x1: { |
| 1332 | OPC_CheckPredicate, 10, // 1678: check predicate 10 |
| 1333 | OPC_Decode, 237, 14, 40, // 1680: decode to RSBrsr using decoder 40 |
| 1334 | // 1680: } |
| 1335 | 2, 6, // 1684: case 0x2: { |
| 1336 | OPC_CheckPredicate, 10, // 1686: check predicate 10 |
| 1337 | OPC_Decode, 165, 6, 41, // 1688: decode to ADCrsr using decoder 41 |
| 1338 | // 1688: } |
| 1339 | 3, 6, // 1692: case 0x3: { |
| 1340 | OPC_CheckPredicate, 10, // 1694: check predicate 10 |
| 1341 | OPC_Decode, 241, 14, 40, // 1696: decode to RSCrsr using decoder 40 |
| 1342 | // 1696: } |
| 1343 | 4, 107, // 1700: case 0x4: { |
| 1344 | OPC_SwitchField, 20, 1, // 1702: switch Inst[20] { |
| 1345 | 0, 89, // 1705: case 0x0: { |
| 1346 | OPC_SwitchField, 5, 2, // 1707: switch Inst[6:5] { |
| 1347 | 0, 35, // 1710: case 0x0: { |
| 1348 | OPC_CheckField, 8, 12, 255, 31, // 1712: check Inst[19:8] == 0xfff |
| 1349 | OPC_Scope, 10, // 1717: try { |
| 1350 | OPC_CheckField, 0, 4, 14, // 1719: check Inst[3:0] == 0xe |
| 1351 | OPC_CheckPredicate, 20, // 1723: check predicate 20 |
| 1352 | OPC_Decode, 200, 6, 67, // 1725: decode to BX_RET using decoder 67 |
| 1353 | OPC_Scope, 10, // 1729: } else try { |
| 1354 | OPC_CheckField, 28, 4, 14, // 1731: check Inst[31:28] == 0xe |
| 1355 | OPC_CheckPredicate, 20, // 1735: check predicate 20 |
| 1356 | OPC_Decode, 198, 6, 72, // 1737: decode to BX using decoder 72 |
| 1357 | // 1737: } else try { |
| 1358 | OPC_CheckPredicate, 20, // 1741: check predicate 20 |
| 1359 | OPC_Decode, 201, 6, 66, // 1743: decode to BX_pred using decoder 66 |
| 1360 | // 1743: } |
| 1361 | // 1743: } |
| 1362 | 1, 23, // 1747: case 0x1: { |
| 1363 | OPC_CheckField, 8, 12, 255, 31, // 1749: check Inst[19:8] == 0xfff |
| 1364 | OPC_Scope, 10, // 1754: try { |
| 1365 | OPC_CheckField, 28, 4, 14, // 1756: check Inst[31:28] == 0xe |
| 1366 | OPC_CheckPredicate, 21, // 1760: check predicate 21 |
| 1367 | OPC_Decode, 194, 6, 72, // 1762: decode to BLX using decoder 72 |
| 1368 | // 1762: } else try { |
| 1369 | OPC_CheckPredicate, 21, // 1766: check predicate 21 |
| 1370 | OPC_Decode, 195, 6, 66, // 1768: decode to BLX_pred using decoder 66 |
| 1371 | // 1768: } |
| 1372 | // 1768: } |
| 1373 | 2, 10, // 1772: case 0x2: { |
| 1374 | OPC_CheckPredicate, 10, // 1774: check predicate 10 |
| 1375 | OPC_SoftFail, 128, 30, 0, // 1776: softfail pos=0x00000f00 neg=0x00000000 |
| 1376 | OPC_Decode, 219, 14, 59, // 1780: decode to QSUB using decoder 59 |
| 1377 | // 1780: } |
| 1378 | 3, 0, // 1784: case 0x3: { |
| 1379 | OPC_CheckPredicate, 10, // 1786: check predicate 10 |
| 1380 | OPC_CheckField, 28, 4, 14, // 1788: check Inst[31:28] == 0xe |
| 1381 | OPC_Decode, 192, 6, 53, // 1792: decode to BKPT using decoder 53 |
| 1382 | // 1792: } |
| 1383 | // 1792: } // switch Inst[6:5] |
| 1384 | // 1792: } |
| 1385 | 1, 0, // 1796: case 0x1: { |
| 1386 | OPC_CheckPredicate, 10, // 1798: check predicate 10 |
| 1387 | OPC_SoftFail, 128, 224, 3, 0, // 1800: softfail pos=0x0000f000 neg=0x00000000 |
| 1388 | OPC_Decode, 140, 16, 56, // 1805: decode to TEQrsr using decoder 56 |
| 1389 | // 1805: } |
| 1390 | // 1805: } // switch Inst[20] |
| 1391 | // 1805: } |
| 1392 | 5, 61, // 1809: case 0x5: { |
| 1393 | OPC_SwitchField, 20, 1, // 1811: switch Inst[20] { |
| 1394 | 0, 43, // 1814: case 0x0: { |
| 1395 | OPC_SwitchField, 5, 2, // 1816: switch Inst[6:5] { |
| 1396 | 0, 14, // 1819: case 0x0: { |
| 1397 | OPC_CheckPredicate, 21, // 1821: check predicate 21 |
| 1398 | OPC_CheckField, 16, 4, 15, // 1823: check Inst[19:16] == 0xf |
| 1399 | OPC_CheckField, 8, 4, 15, // 1827: check Inst[11:8] == 0xf |
| 1400 | OPC_Decode, 236, 6, 73, // 1831: decode to CLZ using decoder 73 |
| 1401 | // 1831: } |
| 1402 | 2, 10, // 1835: case 0x2: { |
| 1403 | OPC_CheckPredicate, 10, // 1837: check predicate 10 |
| 1404 | OPC_SoftFail, 128, 30, 0, // 1839: softfail pos=0x00000f00 neg=0x00000000 |
| 1405 | OPC_Decode, 217, 14, 59, // 1843: decode to QDSUB using decoder 59 |
| 1406 | // 1843: } |
| 1407 | 3, 0, // 1847: case 0x3: { |
| 1408 | OPC_CheckPredicate, 22, // 1849: check predicate 22 |
| 1409 | OPC_CheckField, 8, 12, 0, // 1851: check Inst[19:8] == 0x0 |
| 1410 | OPC_Decode, 143, 15, 74, // 1855: decode to SMC using decoder 74 |
| 1411 | // 1855: } |
| 1412 | // 1855: } // switch Inst[6:5] |
| 1413 | // 1855: } |
| 1414 | 1, 0, // 1859: case 0x1: { |
| 1415 | OPC_CheckPredicate, 10, // 1861: check predicate 10 |
| 1416 | OPC_SoftFail, 128, 224, 3, 0, // 1863: softfail pos=0x0000f000 neg=0x00000000 |
| 1417 | OPC_Decode, 240, 6, 56, // 1868: decode to CMNzrsr using decoder 56 |
| 1418 | // 1868: } |
| 1419 | // 1868: } // switch Inst[20] |
| 1420 | // 1868: } |
| 1421 | 6, 10, // 1872: case 0x6: { |
| 1422 | OPC_CheckPredicate, 10, // 1874: check predicate 10 |
| 1423 | OPC_CheckField, 16, 4, 0, // 1876: check Inst[19:16] == 0x0 |
| 1424 | OPC_Decode, 231, 7, 75, // 1880: decode to MOVsr using decoder 75 |
| 1425 | // 1880: } |
| 1426 | 7, 0, // 1884: case 0x7: { |
| 1427 | OPC_CheckPredicate, 10, // 1886: check predicate 10 |
| 1428 | OPC_SoftFail, 128, 128, 60, 0, // 1888: softfail pos=0x000f0000 neg=0x00000000 |
| 1429 | OPC_Decode, 191, 14, 75, // 1893: decode to MVNsr using decoder 75 |
| 1430 | // 1893: } |
| 1431 | // 1893: } // switch Inst[24:22] |
| 1432 | // 1893: } |
| 1433 | 1, 0, // 1897: case 0x1: { |
| 1434 | OPC_SwitchField, 5, 2, // 1899: switch Inst[6:5] { |
| 1435 | 0, 178, 1, // 1902: case 0x0: { |
| 1436 | OPC_SwitchField, 22, 3, // 1905: switch Inst[24:22] { |
| 1437 | 0, 6, // 1908: case 0x0: { |
| 1438 | OPC_CheckPredicate, 11, // 1910: check predicate 11 |
| 1439 | OPC_Decode, 222, 7, 76, // 1912: decode to MLA using decoder 76 |
| 1440 | // 1912: } |
| 1441 | 1, 10, // 1916: case 0x1: { |
| 1442 | OPC_CheckPredicate, 23, // 1918: check predicate 23 |
| 1443 | OPC_CheckField, 20, 1, 0, // 1920: check Inst[20] == 0x0 |
| 1444 | OPC_Decode, 223, 7, 77, // 1924: decode to MLS using decoder 77 |
| 1445 | // 1924: } |
| 1446 | 2, 6, // 1928: case 0x2: { |
| 1447 | OPC_CheckPredicate, 11, // 1930: check predicate 11 |
| 1448 | OPC_Decode, 160, 16, 78, // 1932: decode to UMLAL using decoder 78 |
| 1449 | // 1932: } |
| 1450 | 3, 6, // 1936: case 0x3: { |
| 1451 | OPC_CheckPredicate, 11, // 1938: check predicate 11 |
| 1452 | OPC_Decode, 148, 15, 78, // 1940: decode to SMLAL using decoder 78 |
| 1453 | // 1940: } |
| 1454 | 6, 53, // 1944: case 0x6: { |
| 1455 | OPC_SwitchField, 8, 4, // 1946: switch Inst[11:8] { |
| 1456 | 14, 23, // 1949: case 0xe: { |
| 1457 | OPC_SwitchField, 20, 1, // 1951: switch Inst[20] { |
| 1458 | 0, 6, // 1954: case 0x0: { |
| 1459 | OPC_CheckPredicate, 19, // 1956: check predicate 19 |
| 1460 | OPC_Decode, 213, 15, 79, // 1958: decode to STLEXD using decoder 79 |
| 1461 | // 1958: } |
| 1462 | 1, 0, // 1962: case 0x1: { |
| 1463 | OPC_CheckPredicate, 19, // 1964: check predicate 19 |
| 1464 | OPC_CheckField, 0, 4, 15, // 1966: check Inst[3:0] == 0xf |
| 1465 | OPC_Decode, 152, 7, 80, // 1970: decode to LDAEXD using decoder 80 |
| 1466 | // 1970: } |
| 1467 | // 1970: } // switch Inst[20] |
| 1468 | // 1970: } |
| 1469 | 15, 0, // 1974: case 0xf: { |
| 1470 | OPC_SwitchField, 20, 1, // 1976: switch Inst[20] { |
| 1471 | 0, 6, // 1979: case 0x0: { |
| 1472 | OPC_CheckPredicate, 10, // 1981: check predicate 10 |
| 1473 | OPC_Decode, 237, 15, 79, // 1983: decode to STREXD using decoder 79 |
| 1474 | // 1983: } |
| 1475 | 1, 0, // 1987: case 0x1: { |
| 1476 | OPC_CheckPredicate, 10, // 1989: check predicate 10 |
| 1477 | OPC_CheckField, 0, 4, 15, // 1991: check Inst[3:0] == 0xf |
| 1478 | OPC_Decode, 192, 7, 80, // 1995: decode to LDREXD using decoder 80 |
| 1479 | // 1995: } |
| 1480 | // 1995: } // switch Inst[20] |
| 1481 | // 1995: } |
| 1482 | // 1995: } // switch Inst[11:8] |
| 1483 | // 1995: } |
| 1484 | 7, 0, // 1999: case 0x7: { |
| 1485 | OPC_SwitchField, 8, 4, // 2001: switch Inst[11:8] { |
| 1486 | 12, 27, // 2004: case 0xc: { |
| 1487 | OPC_SwitchField, 20, 1, // 2006: switch Inst[20] { |
| 1488 | 0, 10, // 2009: case 0x0: { |
| 1489 | OPC_CheckPredicate, 18, // 2011: check predicate 18 |
| 1490 | OPC_CheckField, 12, 4, 15, // 2013: check Inst[15:12] == 0xf |
| 1491 | OPC_Decode, 215, 15, 60, // 2017: decode to STLH using decoder 60 |
| 1492 | // 2017: } |
| 1493 | 1, 0, // 2021: case 0x1: { |
| 1494 | OPC_CheckPredicate, 18, // 2023: check predicate 18 |
| 1495 | OPC_CheckField, 0, 4, 15, // 2025: check Inst[3:0] == 0xf |
| 1496 | OPC_Decode, 154, 7, 61, // 2029: decode to LDAH using decoder 61 |
| 1497 | // 2029: } |
| 1498 | // 2029: } // switch Inst[20] |
| 1499 | // 2029: } |
| 1500 | 14, 23, // 2033: case 0xe: { |
| 1501 | OPC_SwitchField, 20, 1, // 2035: switch Inst[20] { |
| 1502 | 0, 6, // 2038: case 0x0: { |
| 1503 | OPC_CheckPredicate, 19, // 2040: check predicate 19 |
| 1504 | OPC_Decode, 214, 15, 62, // 2042: decode to STLEXH using decoder 62 |
| 1505 | // 2042: } |
| 1506 | 1, 0, // 2046: case 0x1: { |
| 1507 | OPC_CheckPredicate, 19, // 2048: check predicate 19 |
| 1508 | OPC_CheckField, 0, 4, 15, // 2050: check Inst[3:0] == 0xf |
| 1509 | OPC_Decode, 153, 7, 61, // 2054: decode to LDAEXH using decoder 61 |
| 1510 | // 2054: } |
| 1511 | // 2054: } // switch Inst[20] |
| 1512 | // 2054: } |
| 1513 | 15, 0, // 2058: case 0xf: { |
| 1514 | OPC_SwitchField, 20, 1, // 2060: switch Inst[20] { |
| 1515 | 0, 6, // 2063: case 0x0: { |
| 1516 | OPC_CheckPredicate, 10, // 2065: check predicate 10 |
| 1517 | OPC_Decode, 238, 15, 62, // 2067: decode to STREXH using decoder 62 |
| 1518 | // 2067: } |
| 1519 | 1, 0, // 2071: case 0x1: { |
| 1520 | OPC_CheckPredicate, 10, // 2073: check predicate 10 |
| 1521 | OPC_CheckField, 0, 4, 15, // 2075: check Inst[3:0] == 0xf |
| 1522 | OPC_Decode, 193, 7, 61, // 2079: decode to LDREXH using decoder 61 |
| 1523 | // 2079: } |
| 1524 | // 2079: } // switch Inst[20] |
| 1525 | // 2079: } |
| 1526 | // 2079: } // switch Inst[11:8] |
| 1527 | // 2079: } |
| 1528 | // 2079: } // switch Inst[24:22] |
| 1529 | // 2079: } |
| 1530 | 1, 79, // 2083: case 0x1: { |
| 1531 | OPC_SwitchField, 20, 1, // 2085: switch Inst[20] { |
| 1532 | 0, 36, // 2088: case 0x0: { |
| 1533 | OPC_SwitchField, 24, 1, // 2090: switch Inst[24] { |
| 1534 | 0, 23, // 2093: case 0x0: { |
| 1535 | OPC_SwitchField, 22, 1, // 2095: switch Inst[22] { |
| 1536 | 0, 10, // 2098: case 0x0: { |
| 1537 | OPC_CheckPredicate, 10, // 2100: check predicate 10 |
| 1538 | OPC_CheckField, 8, 4, 0, // 2102: check Inst[11:8] == 0x0 |
| 1539 | OPC_Decode, 241, 15, 81, // 2106: decode to STRHTr using decoder 81 |
| 1540 | // 2106: } |
| 1541 | 1, 0, // 2110: case 0x1: { |
| 1542 | OPC_CheckPredicate, 10, // 2112: check predicate 10 |
| 1543 | OPC_Decode, 240, 15, 82, // 2114: decode to STRHTi using decoder 82 |
| 1544 | // 2114: } |
| 1545 | // 2114: } // switch Inst[22] |
| 1546 | // 2114: } |
| 1547 | 1, 0, // 2118: case 0x1: { |
| 1548 | OPC_CheckPredicate, 10, // 2120: check predicate 10 |
| 1549 | OPC_Decode, 243, 15, 45, // 2122: decode to STRH_PRE using decoder 45 |
| 1550 | // 2122: } |
| 1551 | // 2122: } // switch Inst[24] |
| 1552 | // 2122: } |
| 1553 | 1, 0, // 2126: case 0x1: { |
| 1554 | OPC_SwitchField, 24, 1, // 2128: switch Inst[24] { |
| 1555 | 0, 23, // 2131: case 0x0: { |
| 1556 | OPC_SwitchField, 22, 1, // 2133: switch Inst[22] { |
| 1557 | 0, 10, // 2136: case 0x0: { |
| 1558 | OPC_CheckPredicate, 10, // 2138: check predicate 10 |
| 1559 | OPC_SoftFail, 128, 30, 0, // 2140: softfail pos=0x00000f00 neg=0x00000000 |
| 1560 | OPC_Decode, 196, 7, 83, // 2144: decode to LDRHTr using decoder 83 |
| 1561 | // 2144: } |
| 1562 | 1, 0, // 2148: case 0x1: { |
| 1563 | OPC_CheckPredicate, 10, // 2150: check predicate 10 |
| 1564 | OPC_Decode, 195, 7, 84, // 2152: decode to LDRHTi using decoder 84 |
| 1565 | // 2152: } |
| 1566 | // 2152: } // switch Inst[22] |
| 1567 | // 2152: } |
| 1568 | 1, 0, // 2156: case 0x1: { |
| 1569 | OPC_CheckPredicate, 10, // 2158: check predicate 10 |
| 1570 | OPC_Decode, 198, 7, 45, // 2160: decode to LDRH_PRE using decoder 45 |
| 1571 | // 2160: } |
| 1572 | // 2160: } // switch Inst[24] |
| 1573 | // 2160: } |
| 1574 | // 2160: } // switch Inst[20] |
| 1575 | // 2160: } |
| 1576 | 2, 53, // 2164: case 0x2: { |
| 1577 | OPC_SwitchField, 20, 1, // 2166: switch Inst[20] { |
| 1578 | 0, 10, // 2169: case 0x0: { |
| 1579 | OPC_CheckPredicate, 10, // 2171: check predicate 10 |
| 1580 | OPC_CheckField, 24, 1, 1, // 2173: check Inst[24] == 0x1 |
| 1581 | OPC_Decode, 189, 7, 45, // 2177: decode to LDRD_PRE using decoder 45 |
| 1582 | // 2177: } |
| 1583 | 1, 0, // 2181: case 0x1: { |
| 1584 | OPC_SwitchField, 24, 1, // 2183: switch Inst[24] { |
| 1585 | 0, 23, // 2186: case 0x0: { |
| 1586 | OPC_SwitchField, 22, 1, // 2188: switch Inst[22] { |
| 1587 | 0, 10, // 2191: case 0x0: { |
| 1588 | OPC_CheckPredicate, 10, // 2193: check predicate 10 |
| 1589 | OPC_SoftFail, 128, 30, 0, // 2195: softfail pos=0x00000f00 neg=0x00000000 |
| 1590 | OPC_Decode, 201, 7, 83, // 2199: decode to LDRSBTr using decoder 83 |
| 1591 | // 2199: } |
| 1592 | 1, 0, // 2203: case 0x1: { |
| 1593 | OPC_CheckPredicate, 10, // 2205: check predicate 10 |
| 1594 | OPC_Decode, 200, 7, 84, // 2207: decode to LDRSBTi using decoder 84 |
| 1595 | // 2207: } |
| 1596 | // 2207: } // switch Inst[22] |
| 1597 | // 2207: } |
| 1598 | 1, 0, // 2211: case 0x1: { |
| 1599 | OPC_CheckPredicate, 10, // 2213: check predicate 10 |
| 1600 | OPC_Decode, 203, 7, 45, // 2215: decode to LDRSB_PRE using decoder 45 |
| 1601 | // 2215: } |
| 1602 | // 2215: } // switch Inst[24] |
| 1603 | // 2215: } |
| 1604 | // 2215: } // switch Inst[20] |
| 1605 | // 2215: } |
| 1606 | 3, 0, // 2219: case 0x3: { |
| 1607 | OPC_SwitchField, 20, 1, // 2221: switch Inst[20] { |
| 1608 | 0, 10, // 2224: case 0x0: { |
| 1609 | OPC_CheckPredicate, 10, // 2226: check predicate 10 |
| 1610 | OPC_CheckField, 24, 1, 1, // 2228: check Inst[24] == 0x1 |
| 1611 | OPC_Decode, 234, 15, 45, // 2232: decode to STRD_PRE using decoder 45 |
| 1612 | // 2232: } |
| 1613 | 1, 0, // 2236: case 0x1: { |
| 1614 | OPC_SwitchField, 24, 1, // 2238: switch Inst[24] { |
| 1615 | 0, 23, // 2241: case 0x0: { |
| 1616 | OPC_SwitchField, 22, 1, // 2243: switch Inst[22] { |
| 1617 | 0, 10, // 2246: case 0x0: { |
| 1618 | OPC_CheckPredicate, 10, // 2248: check predicate 10 |
| 1619 | OPC_SoftFail, 128, 30, 0, // 2250: softfail pos=0x00000f00 neg=0x00000000 |
| 1620 | OPC_Decode, 206, 7, 83, // 2254: decode to LDRSHTr using decoder 83 |
| 1621 | // 2254: } |
| 1622 | 1, 0, // 2258: case 0x1: { |
| 1623 | OPC_CheckPredicate, 10, // 2260: check predicate 10 |
| 1624 | OPC_Decode, 205, 7, 84, // 2262: decode to LDRSHTi using decoder 84 |
| 1625 | // 2262: } |
| 1626 | // 2262: } // switch Inst[22] |
| 1627 | // 2262: } |
| 1628 | 1, 0, // 2266: case 0x1: { |
| 1629 | OPC_CheckPredicate, 10, // 2268: check predicate 10 |
| 1630 | OPC_Decode, 208, 7, 45, // 2270: decode to LDRSH_PRE using decoder 45 |
| 1631 | // 2270: } |
| 1632 | // 2270: } // switch Inst[24] |
| 1633 | // 2270: } |
| 1634 | // 2270: } // switch Inst[20] |
| 1635 | // 2270: } |
| 1636 | // 2270: } // switch Inst[6:5] |
| 1637 | // 2270: } |
| 1638 | // 2270: } // switch Inst[7] |
| 1639 | // 2270: } |
| 1640 | // 2270: } // switch Inst[4] |
| 1641 | // 2270: } |
| 1642 | // 2270: } // switch Inst[21] |
| 1643 | // 2270: } |
| 1644 | 1, 190, 2, // 2274: case 0x1: { |
| 1645 | OPC_SwitchField, 21, 1, // 2277: switch Inst[21] { |
| 1646 | 0, 125, // 2280: case 0x0: { |
| 1647 | OPC_SwitchField, 24, 1, // 2282: switch Inst[24] { |
| 1648 | 0, 47, // 2285: case 0x0: { |
| 1649 | OPC_Scope, 35, // 2287: try { |
| 1650 | OPC_SwitchField, 22, 2, // 2289: switch Inst[23:22] { |
| 1651 | 0, 6, // 2292: case 0x0: { |
| 1652 | OPC_CheckPredicate, 10, // 2294: check predicate 10 |
| 1653 | OPC_Decode, 175, 6, 85, // 2296: decode to ANDri using decoder 85 |
| 1654 | // 2296: } |
| 1655 | 1, 6, // 2300: case 0x1: { |
| 1656 | OPC_CheckPredicate, 10, // 2302: check predicate 10 |
| 1657 | OPC_Decode, 252, 15, 85, // 2304: decode to SUBri using decoder 85 |
| 1658 | // 2304: } |
| 1659 | 2, 6, // 2308: case 0x2: { |
| 1660 | OPC_CheckPredicate, 10, // 2310: check predicate 10 |
| 1661 | OPC_Decode, 166, 6, 85, // 2312: decode to ADDri using decoder 85 |
| 1662 | // 2312: } |
| 1663 | 3, 0, // 2316: case 0x3: { |
| 1664 | OPC_CheckPredicate, 10, // 2318: check predicate 10 |
| 1665 | OPC_Decode, 246, 14, 85, // 2320: decode to SBCri using decoder 85 |
| 1666 | // 2320: } |
| 1667 | // 2320: } // switch Inst[23:22] |
| 1668 | // 2320: } else try { |
| 1669 | OPC_CheckPredicate, 10, // 2324: check predicate 10 |
| 1670 | OPC_CheckField, 16, 5, 15, // 2326: check Inst[20:16] == 0xf |
| 1671 | OPC_Decode, 170, 6, 86, // 2330: decode to ADR using decoder 86 |
| 1672 | // 2330: } |
| 1673 | // 2330: } |
| 1674 | 1, 0, // 2334: case 0x1: { |
| 1675 | OPC_SwitchField, 22, 2, // 2336: switch Inst[23:22] { |
| 1676 | 0, 24, // 2339: case 0x0: { |
| 1677 | OPC_SwitchField, 20, 1, // 2341: switch Inst[20] { |
| 1678 | 0, 6, // 2344: case 0x0: { |
| 1679 | OPC_CheckPredicate, 23, // 2346: check predicate 23 |
| 1680 | OPC_Decode, 227, 7, 87, // 2348: decode to MOVi16 using decoder 87 |
| 1681 | // 2348: } |
| 1682 | 1, 0, // 2352: case 0x1: { |
| 1683 | OPC_CheckPredicate, 10, // 2354: check predicate 10 |
| 1684 | OPC_SoftFail, 128, 224, 3, 0, // 2356: softfail pos=0x0000f000 neg=0x00000000 |
| 1685 | OPC_Decode, 143, 16, 88, // 2361: decode to TSTri using decoder 88 |
| 1686 | // 2361: } |
| 1687 | // 2361: } // switch Inst[20] |
| 1688 | // 2361: } |
| 1689 | 1, 24, // 2365: case 0x1: { |
| 1690 | OPC_SwitchField, 20, 1, // 2367: switch Inst[20] { |
| 1691 | 0, 6, // 2370: case 0x0: { |
| 1692 | OPC_CheckPredicate, 23, // 2372: check predicate 23 |
| 1693 | OPC_Decode, 225, 7, 87, // 2374: decode to MOVTi16 using decoder 87 |
| 1694 | // 2374: } |
| 1695 | 1, 0, // 2378: case 0x1: { |
| 1696 | OPC_CheckPredicate, 10, // 2380: check predicate 10 |
| 1697 | OPC_SoftFail, 128, 224, 3, 0, // 2382: softfail pos=0x0000f000 neg=0x00000000 |
| 1698 | OPC_Decode, 241, 6, 88, // 2387: decode to CMPri using decoder 88 |
| 1699 | // 2387: } |
| 1700 | // 2387: } // switch Inst[20] |
| 1701 | // 2387: } |
| 1702 | 2, 6, // 2391: case 0x2: { |
| 1703 | OPC_CheckPredicate, 10, // 2393: check predicate 10 |
| 1704 | OPC_Decode, 200, 14, 85, // 2395: decode to ORRri using decoder 85 |
| 1705 | // 2395: } |
| 1706 | 3, 0, // 2399: case 0x3: { |
| 1707 | OPC_CheckPredicate, 10, // 2401: check predicate 10 |
| 1708 | OPC_Decode, 188, 6, 85, // 2403: decode to BICri using decoder 85 |
| 1709 | // 2403: } |
| 1710 | // 2403: } // switch Inst[23:22] |
| 1711 | // 2403: } |
| 1712 | // 2403: } // switch Inst[24] |
| 1713 | // 2403: } |
| 1714 | 1, 0, // 2407: case 0x1: { |
| 1715 | OPC_SwitchField, 23, 2, // 2409: switch Inst[24:23] { |
| 1716 | 0, 19, // 2412: case 0x0: { |
| 1717 | OPC_SwitchField, 22, 1, // 2414: switch Inst[22] { |
| 1718 | 0, 6, // 2417: case 0x0: { |
| 1719 | OPC_CheckPredicate, 10, // 2419: check predicate 10 |
| 1720 | OPC_Decode, 129, 7, 85, // 2421: decode to EORri using decoder 85 |
| 1721 | // 2421: } |
| 1722 | 1, 0, // 2425: case 0x1: { |
| 1723 | OPC_CheckPredicate, 10, // 2427: check predicate 10 |
| 1724 | OPC_Decode, 234, 14, 85, // 2429: decode to RSBri using decoder 85 |
| 1725 | // 2429: } |
| 1726 | // 2429: } // switch Inst[22] |
| 1727 | // 2429: } |
| 1728 | 1, 19, // 2433: case 0x1: { |
| 1729 | OPC_SwitchField, 22, 1, // 2435: switch Inst[22] { |
| 1730 | 0, 6, // 2438: case 0x0: { |
| 1731 | OPC_CheckPredicate, 10, // 2440: check predicate 10 |
| 1732 | OPC_Decode, 162, 6, 85, // 2442: decode to ADCri using decoder 85 |
| 1733 | // 2442: } |
| 1734 | 1, 0, // 2446: case 0x1: { |
| 1735 | OPC_CheckPredicate, 10, // 2448: check predicate 10 |
| 1736 | OPC_Decode, 238, 14, 85, // 2450: decode to RSCri using decoder 85 |
| 1737 | // 2450: } |
| 1738 | // 2450: } // switch Inst[22] |
| 1739 | // 2450: } |
| 1740 | 2, 110, // 2454: case 0x2: { |
| 1741 | OPC_SwitchField, 20, 1, // 2456: switch Inst[20] { |
| 1742 | 0, 74, // 2459: case 0x0: { |
| 1743 | OPC_CheckField, 12, 4, 15, // 2461: check Inst[15:12] == 0xf |
| 1744 | OPC_Scope, 22, // 2465: try { |
| 1745 | OPC_CheckField, 0, 12, 18, // 2467: check Inst[11:0] == 0x12 |
| 1746 | OPC_CheckPredicate, 24, // 2471: check predicate 24 |
| 1747 | OPC_CheckField, 28, 4, 14, // 2473: check Inst[31:28] == 0xe |
| 1748 | OPC_CheckField, 22, 1, 0, // 2477: check Inst[22] == 0x0 |
| 1749 | OPC_CheckField, 16, 4, 0, // 2481: check Inst[19:16] == 0x0 |
| 1750 | OPC_Decode, 142, 16, 89, // 2485: decode to TSB using decoder 89 |
| 1751 | OPC_Scope, 18, // 2489: } else try { |
| 1752 | OPC_CheckField, 4, 8, 15, // 2491: check Inst[11:4] == 0xf |
| 1753 | OPC_CheckPredicate, 25, // 2495: check predicate 25 |
| 1754 | OPC_CheckField, 22, 1, 0, // 2497: check Inst[22] == 0x0 |
| 1755 | OPC_CheckField, 16, 4, 0, // 2501: check Inst[19:16] == 0x0 |
| 1756 | OPC_Decode, 254, 6, 74, // 2505: decode to DBG using decoder 74 |
| 1757 | OPC_Scope, 18, // 2509: } else try { |
| 1758 | OPC_CheckField, 8, 4, 0, // 2511: check Inst[11:8] == 0x0 |
| 1759 | OPC_CheckPredicate, 11, // 2515: check predicate 11 |
| 1760 | OPC_CheckField, 22, 1, 0, // 2517: check Inst[22] == 0x0 |
| 1761 | OPC_CheckField, 16, 4, 0, // 2521: check Inst[19:16] == 0x0 |
| 1762 | OPC_Decode, 144, 7, 90, // 2525: decode to HINT using decoder 90 |
| 1763 | // 2525: } else try { |
| 1764 | OPC_CheckPredicate, 10, // 2529: check predicate 10 |
| 1765 | OPC_Decode, 241, 7, 91, // 2531: decode to MSRi using decoder 91 |
| 1766 | // 2531: } |
| 1767 | // 2531: } |
| 1768 | 1, 0, // 2535: case 0x1: { |
| 1769 | OPC_SwitchField, 22, 1, // 2537: switch Inst[22] { |
| 1770 | 0, 11, // 2540: case 0x0: { |
| 1771 | OPC_CheckPredicate, 10, // 2542: check predicate 10 |
| 1772 | OPC_SoftFail, 128, 224, 3, 0, // 2544: softfail pos=0x0000f000 neg=0x00000000 |
| 1773 | OPC_Decode, 137, 16, 88, // 2549: decode to TEQri using decoder 88 |
| 1774 | // 2549: } |
| 1775 | 1, 0, // 2553: case 0x1: { |
| 1776 | OPC_CheckPredicate, 10, // 2555: check predicate 10 |
| 1777 | OPC_SoftFail, 128, 224, 3, 0, // 2557: softfail pos=0x0000f000 neg=0x00000000 |
| 1778 | OPC_Decode, 237, 6, 88, // 2562: decode to CMNri using decoder 88 |
| 1779 | // 2562: } |
| 1780 | // 2562: } // switch Inst[22] |
| 1781 | // 2562: } |
| 1782 | // 2562: } // switch Inst[20] |
| 1783 | // 2562: } |
| 1784 | 3, 0, // 2566: case 0x3: { |
| 1785 | OPC_SwitchField, 22, 1, // 2568: switch Inst[22] { |
| 1786 | 0, 10, // 2571: case 0x0: { |
| 1787 | OPC_CheckPredicate, 10, // 2573: check predicate 10 |
| 1788 | OPC_CheckField, 16, 4, 0, // 2575: check Inst[19:16] == 0x0 |
| 1789 | OPC_Decode, 226, 7, 92, // 2579: decode to MOVi using decoder 92 |
| 1790 | // 2579: } |
| 1791 | 1, 0, // 2583: case 0x1: { |
| 1792 | OPC_CheckPredicate, 10, // 2585: check predicate 10 |
| 1793 | OPC_CheckField, 16, 4, 0, // 2587: check Inst[19:16] == 0x0 |
| 1794 | OPC_Decode, 188, 14, 92, // 2591: decode to MVNi using decoder 92 |
| 1795 | // 2591: } |
| 1796 | // 2591: } // switch Inst[22] |
| 1797 | // 2591: } |
| 1798 | // 2591: } // switch Inst[24:23] |
| 1799 | // 2591: } |
| 1800 | // 2591: } // switch Inst[21] |
| 1801 | // 2591: } |
| 1802 | 2, 198, 2, // 2595: case 0x2: { |
| 1803 | OPC_SwitchField, 20, 3, // 2598: switch Inst[22:20] { |
| 1804 | 0, 19, // 2601: case 0x0: { |
| 1805 | OPC_SwitchField, 24, 1, // 2603: switch Inst[24] { |
| 1806 | 0, 6, // 2606: case 0x0: { |
| 1807 | OPC_CheckPredicate, 10, // 2608: check predicate 10 |
| 1808 | OPC_Decode, 246, 15, 93, // 2610: decode to STR_POST_IMM using decoder 93 |
| 1809 | // 2610: } |
| 1810 | 1, 0, // 2614: case 0x1: { |
| 1811 | OPC_CheckPredicate, 10, // 2616: check predicate 10 |
| 1812 | OPC_Decode, 250, 15, 94, // 2618: decode to STRi12 using decoder 94 |
| 1813 | // 2618: } |
| 1814 | // 2618: } // switch Inst[24] |
| 1815 | // 2618: } |
| 1816 | 1, 35, // 2622: case 0x1: { |
| 1817 | OPC_SwitchField, 24, 1, // 2624: switch Inst[24] { |
| 1818 | 0, 6, // 2627: case 0x0: { |
| 1819 | OPC_CheckPredicate, 10, // 2629: check predicate 10 |
| 1820 | OPC_Decode, 211, 7, 93, // 2631: decode to LDR_POST_IMM using decoder 93 |
| 1821 | // 2631: } |
| 1822 | 1, 0, // 2635: case 0x1: { |
| 1823 | OPC_Scope, 14, // 2637: try { |
| 1824 | OPC_CheckField, 12, 4, 15, // 2639: check Inst[15:12] == 0xf |
| 1825 | OPC_CheckPredicate, 26, // 2643: check predicate 26 |
| 1826 | OPC_CheckField, 28, 4, 15, // 2645: check Inst[31:28] == 0xf |
| 1827 | OPC_Decode, 206, 14, 95, // 2649: decode to PLDWi12 using decoder 95 |
| 1828 | // 2649: } else try { |
| 1829 | OPC_CheckPredicate, 10, // 2653: check predicate 10 |
| 1830 | OPC_Decode, 216, 7, 94, // 2655: decode to LDRi12 using decoder 94 |
| 1831 | // 2655: } |
| 1832 | // 2655: } |
| 1833 | // 2655: } // switch Inst[24] |
| 1834 | // 2655: } |
| 1835 | 2, 19, // 2659: case 0x2: { |
| 1836 | OPC_SwitchField, 24, 1, // 2661: switch Inst[24] { |
| 1837 | 0, 6, // 2664: case 0x0: { |
| 1838 | OPC_CheckPredicate, 10, // 2666: check predicate 10 |
| 1839 | OPC_Decode, 244, 15, 93, // 2668: decode to STRT_POST_IMM using decoder 93 |
| 1840 | // 2668: } |
| 1841 | 1, 0, // 2672: case 0x1: { |
| 1842 | OPC_CheckPredicate, 10, // 2674: check predicate 10 |
| 1843 | OPC_Decode, 248, 15, 96, // 2676: decode to STR_PRE_IMM using decoder 96 |
| 1844 | // 2676: } |
| 1845 | // 2676: } // switch Inst[24] |
| 1846 | // 2676: } |
| 1847 | 3, 19, // 2680: case 0x3: { |
| 1848 | OPC_SwitchField, 24, 1, // 2682: switch Inst[24] { |
| 1849 | 0, 6, // 2685: case 0x0: { |
| 1850 | OPC_CheckPredicate, 10, // 2687: check predicate 10 |
| 1851 | OPC_Decode, 209, 7, 93, // 2689: decode to LDRT_POST_IMM using decoder 93 |
| 1852 | // 2689: } |
| 1853 | 1, 0, // 2693: case 0x1: { |
| 1854 | OPC_CheckPredicate, 10, // 2695: check predicate 10 |
| 1855 | OPC_Decode, 213, 7, 97, // 2697: decode to LDR_PRE_IMM using decoder 97 |
| 1856 | // 2697: } |
| 1857 | // 2697: } // switch Inst[24] |
| 1858 | // 2697: } |
| 1859 | 4, 19, // 2701: case 0x4: { |
| 1860 | OPC_SwitchField, 24, 1, // 2703: switch Inst[24] { |
| 1861 | 0, 6, // 2706: case 0x0: { |
| 1862 | OPC_CheckPredicate, 10, // 2708: check predicate 10 |
| 1863 | OPC_Decode, 226, 15, 93, // 2710: decode to STRB_POST_IMM using decoder 93 |
| 1864 | // 2710: } |
| 1865 | 1, 0, // 2714: case 0x1: { |
| 1866 | OPC_CheckPredicate, 10, // 2716: check predicate 10 |
| 1867 | OPC_Decode, 230, 15, 98, // 2718: decode to STRBi12 using decoder 98 |
| 1868 | // 2718: } |
| 1869 | // 2718: } // switch Inst[24] |
| 1870 | // 2718: } |
| 1871 | 5, 51, // 2722: case 0x5: { |
| 1872 | OPC_SwitchField, 24, 1, // 2724: switch Inst[24] { |
| 1873 | 0, 22, // 2727: case 0x0: { |
| 1874 | OPC_Scope, 14, // 2729: try { |
| 1875 | OPC_CheckField, 12, 4, 15, // 2731: check Inst[15:12] == 0xf |
| 1876 | OPC_CheckPredicate, 25, // 2735: check predicate 25 |
| 1877 | OPC_CheckField, 28, 4, 15, // 2737: check Inst[31:28] == 0xf |
| 1878 | OPC_Decode, 210, 14, 95, // 2741: decode to PLIi12 using decoder 95 |
| 1879 | // 2741: } else try { |
| 1880 | OPC_CheckPredicate, 10, // 2745: check predicate 10 |
| 1881 | OPC_Decode, 181, 7, 93, // 2747: decode to LDRB_POST_IMM using decoder 93 |
| 1882 | // 2747: } |
| 1883 | // 2747: } |
| 1884 | 1, 0, // 2751: case 0x1: { |
| 1885 | OPC_Scope, 14, // 2753: try { |
| 1886 | OPC_CheckField, 12, 4, 15, // 2755: check Inst[15:12] == 0xf |
| 1887 | OPC_CheckPredicate, 10, // 2759: check predicate 10 |
| 1888 | OPC_CheckField, 28, 4, 15, // 2761: check Inst[31:28] == 0xf |
| 1889 | OPC_Decode, 208, 14, 95, // 2765: decode to PLDi12 using decoder 95 |
| 1890 | // 2765: } else try { |
| 1891 | OPC_CheckPredicate, 10, // 2769: check predicate 10 |
| 1892 | OPC_Decode, 185, 7, 98, // 2771: decode to LDRBi12 using decoder 98 |
| 1893 | // 2771: } |
| 1894 | // 2771: } |
| 1895 | // 2771: } // switch Inst[24] |
| 1896 | // 2771: } |
| 1897 | 6, 19, // 2775: case 0x6: { |
| 1898 | OPC_SwitchField, 24, 1, // 2777: switch Inst[24] { |
| 1899 | 0, 6, // 2780: case 0x0: { |
| 1900 | OPC_CheckPredicate, 10, // 2782: check predicate 10 |
| 1901 | OPC_Decode, 224, 15, 93, // 2784: decode to STRBT_POST_IMM using decoder 93 |
| 1902 | // 2784: } |
| 1903 | 1, 0, // 2788: case 0x1: { |
| 1904 | OPC_CheckPredicate, 10, // 2790: check predicate 10 |
| 1905 | OPC_Decode, 228, 15, 96, // 2792: decode to STRB_PRE_IMM using decoder 96 |
| 1906 | // 2792: } |
| 1907 | // 2792: } // switch Inst[24] |
| 1908 | // 2792: } |
| 1909 | 7, 0, // 2796: case 0x7: { |
| 1910 | OPC_SwitchField, 24, 1, // 2798: switch Inst[24] { |
| 1911 | 0, 6, // 2801: case 0x0: { |
| 1912 | OPC_CheckPredicate, 10, // 2803: check predicate 10 |
| 1913 | OPC_Decode, 179, 7, 93, // 2805: decode to LDRBT_POST_IMM using decoder 93 |
| 1914 | // 2805: } |
| 1915 | 1, 0, // 2809: case 0x1: { |
| 1916 | OPC_Scope, 20, // 2811: try { |
| 1917 | OPC_CheckField, 0, 20, 159, 224, 63, // 2813: check Inst[19:0] == 0xff01f |
| 1918 | OPC_CheckPredicate, 27, // 2819: check predicate 27 |
| 1919 | OPC_CheckField, 28, 4, 15, // 2821: check Inst[31:28] == 0xf |
| 1920 | OPC_CheckField, 23, 1, 0, // 2825: check Inst[23] == 0x0 |
| 1921 | OPC_Decode, 235, 6, 25, // 2829: decode to CLREX using decoder 25 |
| 1922 | OPC_Scope, 57, // 2833: } else try { |
| 1923 | OPC_SwitchField, 4, 16, // 2835: switch Inst[19:4] { |
| 1924 | 132, 254, 3, 14, // 2838: case 0xff04: { |
| 1925 | OPC_CheckPredicate, 28, // 2842: check predicate 28 |
| 1926 | OPC_CheckField, 28, 4, 15, // 2844: check Inst[31:28] == 0xf |
| 1927 | OPC_CheckField, 23, 1, 0, // 2848: check Inst[23] == 0x0 |
| 1928 | OPC_Decode, 128, 7, 99, // 2852: decode to DSB using decoder 99 |
| 1929 | // 2852: } |
| 1930 | 133, 254, 3, 14, // 2856: case 0xff05: { |
| 1931 | OPC_CheckPredicate, 28, // 2860: check predicate 28 |
| 1932 | OPC_CheckField, 28, 4, 15, // 2862: check Inst[31:28] == 0xf |
| 1933 | OPC_CheckField, 23, 1, 0, // 2866: check Inst[23] == 0x0 |
| 1934 | OPC_Decode, 255, 6, 99, // 2870: decode to DMB using decoder 99 |
| 1935 | // 2870: } |
| 1936 | 134, 254, 3, 0, // 2874: case 0xff06: { |
| 1937 | OPC_CheckPredicate, 28, // 2878: check predicate 28 |
| 1938 | OPC_CheckField, 28, 4, 15, // 2880: check Inst[31:28] == 0xf |
| 1939 | OPC_CheckField, 23, 1, 0, // 2884: check Inst[23] == 0x0 |
| 1940 | OPC_Decode, 147, 7, 100, // 2888: decode to ISB using decoder 100 |
| 1941 | // 2888: } |
| 1942 | // 2888: } // switch Inst[19:4] |
| 1943 | OPC_Scope, 24, // 2892: } else try { |
| 1944 | OPC_CheckField, 4, 4, 7, // 2894: check Inst[7:4] == 0x7 |
| 1945 | OPC_CheckPredicate, 29, // 2898: check predicate 29 |
| 1946 | OPC_CheckField, 28, 4, 15, // 2900: check Inst[31:28] == 0xf |
| 1947 | OPC_CheckField, 23, 1, 0, // 2904: check Inst[23] == 0x0 |
| 1948 | OPC_SoftFail, 143, 30, 128, 224, 63, // 2908: softfail pos=0x00000f0f neg=0x000ff000 |
| 1949 | OPC_Decode, 245, 14, 25, // 2914: decode to SB using decoder 25 |
| 1950 | // 2914: } else try { |
| 1951 | OPC_CheckPredicate, 10, // 2918: check predicate 10 |
| 1952 | OPC_Decode, 183, 7, 97, // 2920: decode to LDRB_PRE_IMM using decoder 97 |
| 1953 | // 2920: } |
| 1954 | // 2920: } |
| 1955 | // 2920: } // switch Inst[24] |
| 1956 | // 2920: } |
| 1957 | // 2920: } // switch Inst[22:20] |
| 1958 | // 2920: } |
| 1959 | 3, 145, 13, // 2924: case 0x3: { |
| 1960 | OPC_SwitchField, 21, 2, // 2927: switch Inst[22:21] { |
| 1961 | 0, 186, 3, // 2930: case 0x0: { |
| 1962 | OPC_SwitchField, 4, 1, // 2933: switch Inst[4] { |
| 1963 | 0, 61, // 2936: case 0x0: { |
| 1964 | OPC_SwitchField, 20, 1, // 2938: switch Inst[20] { |
| 1965 | 0, 19, // 2941: case 0x0: { |
| 1966 | OPC_SwitchField, 24, 1, // 2943: switch Inst[24] { |
| 1967 | 0, 6, // 2946: case 0x0: { |
| 1968 | OPC_CheckPredicate, 10, // 2948: check predicate 10 |
| 1969 | OPC_Decode, 247, 15, 93, // 2950: decode to STR_POST_REG using decoder 93 |
| 1970 | // 2950: } |
| 1971 | 1, 0, // 2954: case 0x1: { |
| 1972 | OPC_CheckPredicate, 10, // 2956: check predicate 10 |
| 1973 | OPC_Decode, 251, 15, 101, // 2958: decode to STRrs using decoder 101 |
| 1974 | // 2958: } |
| 1975 | // 2958: } // switch Inst[24] |
| 1976 | // 2958: } |
| 1977 | 1, 0, // 2962: case 0x1: { |
| 1978 | OPC_SwitchField, 24, 1, // 2964: switch Inst[24] { |
| 1979 | 0, 6, // 2967: case 0x0: { |
| 1980 | OPC_CheckPredicate, 10, // 2969: check predicate 10 |
| 1981 | OPC_Decode, 212, 7, 93, // 2971: decode to LDR_POST_REG using decoder 93 |
| 1982 | // 2971: } |
| 1983 | 1, 0, // 2975: case 0x1: { |
| 1984 | OPC_Scope, 14, // 2977: try { |
| 1985 | OPC_CheckField, 12, 4, 15, // 2979: check Inst[15:12] == 0xf |
| 1986 | OPC_CheckPredicate, 26, // 2983: check predicate 26 |
| 1987 | OPC_CheckField, 28, 4, 15, // 2985: check Inst[31:28] == 0xf |
| 1988 | OPC_Decode, 207, 14, 102, // 2989: decode to PLDWrs using decoder 102 |
| 1989 | // 2989: } else try { |
| 1990 | OPC_CheckPredicate, 10, // 2993: check predicate 10 |
| 1991 | OPC_Decode, 217, 7, 101, // 2995: decode to LDRrs using decoder 101 |
| 1992 | // 2995: } |
| 1993 | // 2995: } |
| 1994 | // 2995: } // switch Inst[24] |
| 1995 | // 2995: } |
| 1996 | // 2995: } // switch Inst[20] |
| 1997 | // 2995: } |
| 1998 | 1, 0, // 2999: case 0x1: { |
| 1999 | OPC_SwitchField, 5, 2, // 3001: switch Inst[6:5] { |
| 2000 | 0, 125, // 3004: case 0x0: { |
| 2001 | OPC_SwitchField, 23, 2, // 3006: switch Inst[24:23] { |
| 2002 | 0, 35, // 3009: case 0x0: { |
| 2003 | OPC_SwitchField, 7, 1, // 3011: switch Inst[7] { |
| 2004 | 0, 14, // 3014: case 0x0: { |
| 2005 | OPC_CheckPredicate, 10, // 3016: check predicate 10 |
| 2006 | OPC_CheckField, 20, 1, 1, // 3018: check Inst[20] == 0x1 |
| 2007 | OPC_SoftFail, 0, 128, 30, // 3022: softfail pos=0x00000000 neg=0x00000f00 |
| 2008 | OPC_Decode, 242, 14, 103, // 3026: decode to SADD16 using decoder 103 |
| 2009 | // 3026: } |
| 2010 | 1, 0, // 3030: case 0x1: { |
| 2011 | OPC_CheckPredicate, 10, // 3032: check predicate 10 |
| 2012 | OPC_CheckField, 20, 1, 1, // 3034: check Inst[20] == 0x1 |
| 2013 | OPC_SoftFail, 0, 128, 30, // 3038: softfail pos=0x00000000 neg=0x00000f00 |
| 2014 | OPC_Decode, 243, 14, 103, // 3042: decode to SADD8 using decoder 103 |
| 2015 | // 3042: } |
| 2016 | // 3042: } // switch Inst[7] |
| 2017 | // 3042: } |
| 2018 | 1, 10, // 3046: case 0x1: { |
| 2019 | OPC_CheckPredicate, 11, // 3048: check predicate 11 |
| 2020 | OPC_CheckField, 20, 1, 0, // 3050: check Inst[20] == 0x0 |
| 2021 | OPC_Decode, 204, 14, 104, // 3054: decode to PKHBT using decoder 104 |
| 2022 | // 3054: } |
| 2023 | 2, 43, // 3058: case 0x2: { |
| 2024 | OPC_SwitchField, 20, 1, // 3060: switch Inst[20] { |
| 2025 | 0, 22, // 3063: case 0x0: { |
| 2026 | OPC_CheckField, 7, 1, 0, // 3065: check Inst[7] == 0x0 |
| 2027 | OPC_Scope, 10, // 3069: try { |
| 2028 | OPC_CheckField, 12, 4, 15, // 3071: check Inst[15:12] == 0xf |
| 2029 | OPC_CheckPredicate, 11, // 3075: check predicate 11 |
| 2030 | OPC_Decode, 169, 15, 105, // 3077: decode to SMUAD using decoder 105 |
| 2031 | // 3077: } else try { |
| 2032 | OPC_CheckPredicate, 11, // 3081: check predicate 11 |
| 2033 | OPC_Decode, 146, 15, 106, // 3083: decode to SMLAD using decoder 106 |
| 2034 | // 3083: } |
| 2035 | // 3083: } |
| 2036 | 1, 0, // 3087: case 0x1: { |
| 2037 | OPC_CheckPredicate, 30, // 3089: check predicate 30 |
| 2038 | OPC_CheckField, 12, 4, 15, // 3091: check Inst[15:12] == 0xf |
| 2039 | OPC_CheckField, 7, 1, 0, // 3095: check Inst[7] == 0x0 |
| 2040 | OPC_Decode, 251, 14, 68, // 3099: decode to SDIV using decoder 68 |
| 2041 | // 3099: } |
| 2042 | // 3099: } // switch Inst[20] |
| 2043 | // 3099: } |
| 2044 | 3, 0, // 3103: case 0x3: { |
| 2045 | OPC_CheckField, 7, 1, 0, // 3105: check Inst[7] == 0x0 |
| 2046 | OPC_CheckField, 20, 1, 0, // 3109: check Inst[20] == 0x0 |
| 2047 | OPC_Scope, 10, // 3113: try { |
| 2048 | OPC_CheckField, 12, 4, 15, // 3115: check Inst[15:12] == 0xf |
| 2049 | OPC_CheckPredicate, 11, // 3119: check predicate 11 |
| 2050 | OPC_Decode, 168, 16, 68, // 3121: decode to USAD8 using decoder 68 |
| 2051 | // 3121: } else try { |
| 2052 | OPC_CheckPredicate, 11, // 3125: check predicate 11 |
| 2053 | OPC_Decode, 169, 16, 77, // 3127: decode to USADA8 using decoder 77 |
| 2054 | // 3127: } |
| 2055 | // 3127: } |
| 2056 | // 3127: } // switch Inst[24:23] |
| 2057 | // 3127: } |
| 2058 | 1, 71, // 3131: case 0x1: { |
| 2059 | OPC_SwitchField, 23, 2, // 3133: switch Inst[24:23] { |
| 2060 | 0, 18, // 3136: case 0x0: { |
| 2061 | OPC_CheckPredicate, 10, // 3138: check predicate 10 |
| 2062 | OPC_CheckField, 20, 1, 1, // 3140: check Inst[20] == 0x1 |
| 2063 | OPC_CheckField, 7, 1, 0, // 3144: check Inst[7] == 0x0 |
| 2064 | OPC_SoftFail, 0, 128, 30, // 3148: softfail pos=0x00000000 neg=0x00000f00 |
| 2065 | OPC_Decode, 244, 14, 103, // 3152: decode to SASX using decoder 103 |
| 2066 | // 3152: } |
| 2067 | 1, 18, // 3156: case 0x1: { |
| 2068 | OPC_CheckPredicate, 11, // 3158: check predicate 11 |
| 2069 | OPC_CheckField, 20, 1, 0, // 3160: check Inst[20] == 0x0 |
| 2070 | OPC_CheckField, 7, 1, 1, // 3164: check Inst[7] == 0x1 |
| 2071 | OPC_SoftFail, 0, 128, 30, // 3168: softfail pos=0x00000000 neg=0x00000f00 |
| 2072 | OPC_Decode, 252, 14, 107, // 3172: decode to SEL using decoder 107 |
| 2073 | // 3172: } |
| 2074 | 2, 0, // 3176: case 0x2: { |
| 2075 | OPC_CheckField, 7, 1, 0, // 3178: check Inst[7] == 0x0 |
| 2076 | OPC_CheckField, 20, 1, 0, // 3182: check Inst[20] == 0x0 |
| 2077 | OPC_Scope, 10, // 3186: try { |
| 2078 | OPC_CheckField, 12, 4, 15, // 3188: check Inst[15:12] == 0xf |
| 2079 | OPC_CheckPredicate, 11, // 3192: check predicate 11 |
| 2080 | OPC_Decode, 170, 15, 105, // 3194: decode to SMUADX using decoder 105 |
| 2081 | // 3194: } else try { |
| 2082 | OPC_CheckPredicate, 11, // 3198: check predicate 11 |
| 2083 | OPC_Decode, 147, 15, 106, // 3200: decode to SMLADX using decoder 106 |
| 2084 | // 3200: } |
| 2085 | // 3200: } |
| 2086 | // 3200: } // switch Inst[24:23] |
| 2087 | // 3200: } |
| 2088 | 2, 63, // 3204: case 0x2: { |
| 2089 | OPC_SwitchField, 23, 2, // 3206: switch Inst[24:23] { |
| 2090 | 0, 18, // 3209: case 0x0: { |
| 2091 | OPC_CheckPredicate, 10, // 3211: check predicate 10 |
| 2092 | OPC_CheckField, 20, 1, 1, // 3213: check Inst[20] == 0x1 |
| 2093 | OPC_CheckField, 7, 1, 0, // 3217: check Inst[7] == 0x0 |
| 2094 | OPC_SoftFail, 0, 128, 30, // 3221: softfail pos=0x00000000 neg=0x00000f00 |
| 2095 | OPC_Decode, 190, 15, 103, // 3225: decode to SSAX using decoder 103 |
| 2096 | // 3225: } |
| 2097 | 1, 10, // 3229: case 0x1: { |
| 2098 | OPC_CheckPredicate, 11, // 3231: check predicate 11 |
| 2099 | OPC_CheckField, 20, 1, 0, // 3233: check Inst[20] == 0x0 |
| 2100 | OPC_Decode, 205, 14, 104, // 3237: decode to PKHTB using decoder 104 |
| 2101 | // 3237: } |
| 2102 | 2, 0, // 3241: case 0x2: { |
| 2103 | OPC_CheckField, 7, 1, 0, // 3243: check Inst[7] == 0x0 |
| 2104 | OPC_CheckField, 20, 1, 0, // 3247: check Inst[20] == 0x0 |
| 2105 | OPC_Scope, 10, // 3251: try { |
| 2106 | OPC_CheckField, 12, 4, 15, // 3253: check Inst[15:12] == 0xf |
| 2107 | OPC_CheckPredicate, 11, // 3257: check predicate 11 |
| 2108 | OPC_Decode, 178, 15, 105, // 3259: decode to SMUSD using decoder 105 |
| 2109 | // 3259: } else try { |
| 2110 | OPC_CheckPredicate, 11, // 3263: check predicate 11 |
| 2111 | OPC_Decode, 159, 15, 106, // 3265: decode to SMLSD using decoder 106 |
| 2112 | // 3265: } |
| 2113 | // 3265: } |
| 2114 | // 3265: } // switch Inst[24:23] |
| 2115 | // 3265: } |
| 2116 | 3, 0, // 3269: case 0x3: { |
| 2117 | OPC_SwitchField, 23, 2, // 3271: switch Inst[24:23] { |
| 2118 | 0, 35, // 3274: case 0x0: { |
| 2119 | OPC_SwitchField, 7, 1, // 3276: switch Inst[7] { |
| 2120 | 0, 14, // 3279: case 0x0: { |
| 2121 | OPC_CheckPredicate, 10, // 3281: check predicate 10 |
| 2122 | OPC_CheckField, 20, 1, 1, // 3283: check Inst[20] == 0x1 |
| 2123 | OPC_SoftFail, 0, 128, 30, // 3287: softfail pos=0x00000000 neg=0x00000f00 |
| 2124 | OPC_Decode, 191, 15, 103, // 3291: decode to SSUB16 using decoder 103 |
| 2125 | // 3291: } |
| 2126 | 1, 0, // 3295: case 0x1: { |
| 2127 | OPC_CheckPredicate, 10, // 3297: check predicate 10 |
| 2128 | OPC_CheckField, 20, 1, 1, // 3299: check Inst[20] == 0x1 |
| 2129 | OPC_SoftFail, 0, 128, 30, // 3303: softfail pos=0x00000000 neg=0x00000f00 |
| 2130 | OPC_Decode, 192, 15, 103, // 3307: decode to SSUB8 using decoder 103 |
| 2131 | // 3307: } |
| 2132 | // 3307: } // switch Inst[7] |
| 2133 | // 3307: } |
| 2134 | 1, 34, // 3311: case 0x1: { |
| 2135 | OPC_CheckField, 7, 1, 0, // 3313: check Inst[7] == 0x0 |
| 2136 | OPC_CheckField, 20, 1, 0, // 3317: check Inst[20] == 0x0 |
| 2137 | OPC_Scope, 14, // 3321: try { |
| 2138 | OPC_CheckField, 16, 4, 15, // 3323: check Inst[19:16] == 0xf |
| 2139 | OPC_CheckPredicate, 11, // 3327: check predicate 11 |
| 2140 | OPC_SoftFail, 128, 6, 0, // 3329: softfail pos=0x00000300 neg=0x00000000 |
| 2141 | OPC_Decode, 135, 16, 108, // 3333: decode to SXTB16 using decoder 108 |
| 2142 | // 3333: } else try { |
| 2143 | OPC_CheckPredicate, 11, // 3337: check predicate 11 |
| 2144 | OPC_SoftFail, 128, 6, 0, // 3339: softfail pos=0x00000300 neg=0x00000000 |
| 2145 | OPC_Decode, 132, 16, 109, // 3343: decode to SXTAB16 using decoder 109 |
| 2146 | // 3343: } |
| 2147 | // 3343: } |
| 2148 | 2, 0, // 3347: case 0x2: { |
| 2149 | OPC_CheckField, 7, 1, 0, // 3349: check Inst[7] == 0x0 |
| 2150 | OPC_CheckField, 20, 1, 0, // 3353: check Inst[20] == 0x0 |
| 2151 | OPC_Scope, 10, // 3357: try { |
| 2152 | OPC_CheckField, 12, 4, 15, // 3359: check Inst[15:12] == 0xf |
| 2153 | OPC_CheckPredicate, 11, // 3363: check predicate 11 |
| 2154 | OPC_Decode, 179, 15, 105, // 3365: decode to SMUSDX using decoder 105 |
| 2155 | // 3365: } else try { |
| 2156 | OPC_CheckPredicate, 11, // 3369: check predicate 11 |
| 2157 | OPC_Decode, 160, 15, 106, // 3371: decode to SMLSDX using decoder 106 |
| 2158 | // 3371: } |
| 2159 | // 3371: } |
| 2160 | // 3371: } // switch Inst[24:23] |
| 2161 | // 3371: } |
| 2162 | // 3371: } // switch Inst[6:5] |
| 2163 | // 3371: } |
| 2164 | // 3371: } // switch Inst[4] |
| 2165 | // 3371: } |
| 2166 | 1, 139, 3, // 3375: case 0x1: { |
| 2167 | OPC_SwitchField, 4, 1, // 3378: switch Inst[4] { |
| 2168 | 0, 45, // 3381: case 0x0: { |
| 2169 | OPC_SwitchField, 20, 1, // 3383: switch Inst[20] { |
| 2170 | 0, 19, // 3386: case 0x0: { |
| 2171 | OPC_SwitchField, 24, 1, // 3388: switch Inst[24] { |
| 2172 | 0, 6, // 3391: case 0x0: { |
| 2173 | OPC_CheckPredicate, 10, // 3393: check predicate 10 |
| 2174 | OPC_Decode, 245, 15, 93, // 3395: decode to STRT_POST_REG using decoder 93 |
| 2175 | // 3395: } |
| 2176 | 1, 0, // 3399: case 0x1: { |
| 2177 | OPC_CheckPredicate, 10, // 3401: check predicate 10 |
| 2178 | OPC_Decode, 249, 15, 110, // 3403: decode to STR_PRE_REG using decoder 110 |
| 2179 | // 3403: } |
| 2180 | // 3403: } // switch Inst[24] |
| 2181 | // 3403: } |
| 2182 | 1, 0, // 3407: case 0x1: { |
| 2183 | OPC_SwitchField, 24, 1, // 3409: switch Inst[24] { |
| 2184 | 0, 6, // 3412: case 0x0: { |
| 2185 | OPC_CheckPredicate, 10, // 3414: check predicate 10 |
| 2186 | OPC_Decode, 210, 7, 93, // 3416: decode to LDRT_POST_REG using decoder 93 |
| 2187 | // 3416: } |
| 2188 | 1, 0, // 3420: case 0x1: { |
| 2189 | OPC_CheckPredicate, 10, // 3422: check predicate 10 |
| 2190 | OPC_Decode, 214, 7, 111, // 3424: decode to LDR_PRE_REG using decoder 111 |
| 2191 | // 3424: } |
| 2192 | // 3424: } // switch Inst[24] |
| 2193 | // 3424: } |
| 2194 | // 3424: } // switch Inst[20] |
| 2195 | // 3424: } |
| 2196 | 1, 0, // 3428: case 0x1: { |
| 2197 | OPC_SwitchField, 23, 2, // 3430: switch Inst[24:23] { |
| 2198 | 0, 177, 1, // 3433: case 0x0: { |
| 2199 | OPC_SwitchField, 5, 3, // 3436: switch Inst[7:5] { |
| 2200 | 0, 27, // 3439: case 0x0: { |
| 2201 | OPC_SwitchField, 20, 1, // 3441: switch Inst[20] { |
| 2202 | 0, 10, // 3444: case 0x0: { |
| 2203 | OPC_CheckPredicate, 10, // 3446: check predicate 10 |
| 2204 | OPC_SoftFail, 0, 128, 30, // 3448: softfail pos=0x00000000 neg=0x00000f00 |
| 2205 | OPC_Decode, 213, 14, 103, // 3452: decode to QADD16 using decoder 103 |
| 2206 | // 3452: } |
| 2207 | 1, 0, // 3456: case 0x1: { |
| 2208 | OPC_CheckPredicate, 10, // 3458: check predicate 10 |
| 2209 | OPC_SoftFail, 0, 128, 30, // 3460: softfail pos=0x00000000 neg=0x00000f00 |
| 2210 | OPC_Decode, 137, 15, 103, // 3464: decode to SHADD16 using decoder 103 |
| 2211 | // 3464: } |
| 2212 | // 3464: } // switch Inst[20] |
| 2213 | // 3464: } |
| 2214 | 1, 27, // 3468: case 0x1: { |
| 2215 | OPC_SwitchField, 20, 1, // 3470: switch Inst[20] { |
| 2216 | 0, 10, // 3473: case 0x0: { |
| 2217 | OPC_CheckPredicate, 10, // 3475: check predicate 10 |
| 2218 | OPC_SoftFail, 0, 128, 30, // 3477: softfail pos=0x00000000 neg=0x00000f00 |
| 2219 | OPC_Decode, 215, 14, 103, // 3481: decode to QASX using decoder 103 |
| 2220 | // 3481: } |
| 2221 | 1, 0, // 3485: case 0x1: { |
| 2222 | OPC_CheckPredicate, 10, // 3487: check predicate 10 |
| 2223 | OPC_SoftFail, 0, 128, 30, // 3489: softfail pos=0x00000000 neg=0x00000f00 |
| 2224 | OPC_Decode, 139, 15, 103, // 3493: decode to SHASX using decoder 103 |
| 2225 | // 3493: } |
| 2226 | // 3493: } // switch Inst[20] |
| 2227 | // 3493: } |
| 2228 | 2, 27, // 3497: case 0x2: { |
| 2229 | OPC_SwitchField, 20, 1, // 3499: switch Inst[20] { |
| 2230 | 0, 10, // 3502: case 0x0: { |
| 2231 | OPC_CheckPredicate, 10, // 3504: check predicate 10 |
| 2232 | OPC_SoftFail, 0, 128, 30, // 3506: softfail pos=0x00000000 neg=0x00000f00 |
| 2233 | OPC_Decode, 218, 14, 103, // 3510: decode to QSAX using decoder 103 |
| 2234 | // 3510: } |
| 2235 | 1, 0, // 3514: case 0x1: { |
| 2236 | OPC_CheckPredicate, 10, // 3516: check predicate 10 |
| 2237 | OPC_SoftFail, 0, 128, 30, // 3518: softfail pos=0x00000000 neg=0x00000f00 |
| 2238 | OPC_Decode, 140, 15, 103, // 3522: decode to SHSAX using decoder 103 |
| 2239 | // 3522: } |
| 2240 | // 3522: } // switch Inst[20] |
| 2241 | // 3522: } |
| 2242 | 3, 27, // 3526: case 0x3: { |
| 2243 | OPC_SwitchField, 20, 1, // 3528: switch Inst[20] { |
| 2244 | 0, 10, // 3531: case 0x0: { |
| 2245 | OPC_CheckPredicate, 10, // 3533: check predicate 10 |
| 2246 | OPC_SoftFail, 0, 128, 30, // 3535: softfail pos=0x00000000 neg=0x00000f00 |
| 2247 | OPC_Decode, 220, 14, 103, // 3539: decode to QSUB16 using decoder 103 |
| 2248 | // 3539: } |
| 2249 | 1, 0, // 3543: case 0x1: { |
| 2250 | OPC_CheckPredicate, 10, // 3545: check predicate 10 |
| 2251 | OPC_SoftFail, 0, 128, 30, // 3547: softfail pos=0x00000000 neg=0x00000f00 |
| 2252 | OPC_Decode, 141, 15, 103, // 3551: decode to SHSUB16 using decoder 103 |
| 2253 | // 3551: } |
| 2254 | // 3551: } // switch Inst[20] |
| 2255 | // 3551: } |
| 2256 | 4, 27, // 3555: case 0x4: { |
| 2257 | OPC_SwitchField, 20, 1, // 3557: switch Inst[20] { |
| 2258 | 0, 10, // 3560: case 0x0: { |
| 2259 | OPC_CheckPredicate, 10, // 3562: check predicate 10 |
| 2260 | OPC_SoftFail, 0, 128, 30, // 3564: softfail pos=0x00000000 neg=0x00000f00 |
| 2261 | OPC_Decode, 214, 14, 103, // 3568: decode to QADD8 using decoder 103 |
| 2262 | // 3568: } |
| 2263 | 1, 0, // 3572: case 0x1: { |
| 2264 | OPC_CheckPredicate, 10, // 3574: check predicate 10 |
| 2265 | OPC_SoftFail, 0, 128, 30, // 3576: softfail pos=0x00000000 neg=0x00000f00 |
| 2266 | OPC_Decode, 138, 15, 103, // 3580: decode to SHADD8 using decoder 103 |
| 2267 | // 3580: } |
| 2268 | // 3580: } // switch Inst[20] |
| 2269 | // 3580: } |
| 2270 | 7, 0, // 3584: case 0x7: { |
| 2271 | OPC_SwitchField, 20, 1, // 3586: switch Inst[20] { |
| 2272 | 0, 10, // 3589: case 0x0: { |
| 2273 | OPC_CheckPredicate, 10, // 3591: check predicate 10 |
| 2274 | OPC_SoftFail, 0, 128, 30, // 3593: softfail pos=0x00000000 neg=0x00000f00 |
| 2275 | OPC_Decode, 221, 14, 103, // 3597: decode to QSUB8 using decoder 103 |
| 2276 | // 3597: } |
| 2277 | 1, 0, // 3601: case 0x1: { |
| 2278 | OPC_CheckPredicate, 10, // 3603: check predicate 10 |
| 2279 | OPC_SoftFail, 0, 128, 30, // 3605: softfail pos=0x00000000 neg=0x00000f00 |
| 2280 | OPC_Decode, 142, 15, 103, // 3609: decode to SHSUB8 using decoder 103 |
| 2281 | // 3609: } |
| 2282 | // 3609: } // switch Inst[20] |
| 2283 | // 3609: } |
| 2284 | // 3609: } // switch Inst[7:5] |
| 2285 | // 3609: } |
| 2286 | 1, 126, // 3613: case 0x1: { |
| 2287 | OPC_SwitchField, 5, 1, // 3615: switch Inst[5] { |
| 2288 | 0, 6, // 3618: case 0x0: { |
| 2289 | OPC_CheckPredicate, 11, // 3620: check predicate 11 |
| 2290 | OPC_Decode, 188, 15, 112, // 3622: decode to SSAT using decoder 112 |
| 2291 | // 3622: } |
| 2292 | 1, 0, // 3626: case 0x1: { |
| 2293 | OPC_SwitchField, 6, 2, // 3628: switch Inst[7:6] { |
| 2294 | 0, 31, // 3631: case 0x0: { |
| 2295 | OPC_SwitchField, 20, 1, // 3633: switch Inst[20] { |
| 2296 | 0, 10, // 3636: case 0x0: { |
| 2297 | OPC_CheckPredicate, 11, // 3638: check predicate 11 |
| 2298 | OPC_CheckField, 8, 4, 15, // 3640: check Inst[11:8] == 0xf |
| 2299 | OPC_Decode, 189, 15, 113, // 3644: decode to SSAT16 using decoder 113 |
| 2300 | // 3644: } |
| 2301 | 1, 0, // 3648: case 0x1: { |
| 2302 | OPC_CheckPredicate, 11, // 3650: check predicate 11 |
| 2303 | OPC_CheckField, 16, 4, 15, // 3652: check Inst[19:16] == 0xf |
| 2304 | OPC_CheckField, 8, 4, 15, // 3656: check Inst[11:8] == 0xf |
| 2305 | OPC_Decode, 223, 14, 73, // 3660: decode to REV using decoder 73 |
| 2306 | // 3660: } |
| 2307 | // 3660: } // switch Inst[20] |
| 2308 | // 3660: } |
| 2309 | 1, 59, // 3664: case 0x1: { |
| 2310 | OPC_SwitchField, 20, 1, // 3666: switch Inst[20] { |
| 2311 | 0, 26, // 3669: case 0x0: { |
| 2312 | OPC_Scope, 14, // 3671: try { |
| 2313 | OPC_CheckField, 16, 4, 15, // 3673: check Inst[19:16] == 0xf |
| 2314 | OPC_CheckPredicate, 11, // 3677: check predicate 11 |
| 2315 | OPC_SoftFail, 128, 6, 0, // 3679: softfail pos=0x00000300 neg=0x00000000 |
| 2316 | OPC_Decode, 134, 16, 108, // 3683: decode to SXTB using decoder 108 |
| 2317 | // 3683: } else try { |
| 2318 | OPC_CheckPredicate, 11, // 3687: check predicate 11 |
| 2319 | OPC_SoftFail, 128, 6, 0, // 3689: softfail pos=0x00000300 neg=0x00000000 |
| 2320 | OPC_Decode, 131, 16, 109, // 3693: decode to SXTAB using decoder 109 |
| 2321 | // 3693: } |
| 2322 | // 3693: } |
| 2323 | 1, 0, // 3697: case 0x1: { |
| 2324 | OPC_Scope, 14, // 3699: try { |
| 2325 | OPC_CheckField, 16, 4, 15, // 3701: check Inst[19:16] == 0xf |
| 2326 | OPC_CheckPredicate, 11, // 3705: check predicate 11 |
| 2327 | OPC_SoftFail, 128, 6, 0, // 3707: softfail pos=0x00000300 neg=0x00000000 |
| 2328 | OPC_Decode, 136, 16, 108, // 3711: decode to SXTH using decoder 108 |
| 2329 | // 3711: } else try { |
| 2330 | OPC_CheckPredicate, 11, // 3715: check predicate 11 |
| 2331 | OPC_SoftFail, 128, 6, 0, // 3717: softfail pos=0x00000300 neg=0x00000000 |
| 2332 | OPC_Decode, 133, 16, 109, // 3721: decode to SXTAH using decoder 109 |
| 2333 | // 3721: } |
| 2334 | // 3721: } |
| 2335 | // 3721: } // switch Inst[20] |
| 2336 | // 3721: } |
| 2337 | 2, 0, // 3725: case 0x2: { |
| 2338 | OPC_CheckPredicate, 11, // 3727: check predicate 11 |
| 2339 | OPC_CheckField, 16, 5, 31, // 3729: check Inst[20:16] == 0x1f |
| 2340 | OPC_CheckField, 8, 4, 15, // 3733: check Inst[11:8] == 0xf |
| 2341 | OPC_Decode, 224, 14, 73, // 3737: decode to REV16 using decoder 73 |
| 2342 | // 3737: } |
| 2343 | // 3737: } // switch Inst[7:6] |
| 2344 | // 3737: } |
| 2345 | // 3737: } // switch Inst[5] |
| 2346 | // 3737: } |
| 2347 | 2, 18, // 3741: case 0x2: { |
| 2348 | OPC_CheckPredicate, 30, // 3743: check predicate 30 |
| 2349 | OPC_CheckField, 20, 1, 1, // 3745: check Inst[20] == 0x1 |
| 2350 | OPC_CheckField, 12, 4, 15, // 3749: check Inst[15:12] == 0xf |
| 2351 | OPC_CheckField, 5, 3, 0, // 3753: check Inst[7:5] == 0x0 |
| 2352 | OPC_Decode, 152, 16, 68, // 3757: decode to UDIV using decoder 68 |
| 2353 | // 3757: } |
| 2354 | 3, 0, // 3761: case 0x3: { |
| 2355 | OPC_CheckPredicate, 23, // 3763: check predicate 23 |
| 2356 | OPC_CheckField, 5, 2, 2, // 3765: check Inst[6:5] == 0x2 |
| 2357 | OPC_Decode, 250, 14, 114, // 3769: decode to SBFX using decoder 114 |
| 2358 | // 3769: } |
| 2359 | // 3769: } // switch Inst[24:23] |
| 2360 | // 3769: } |
| 2361 | // 3769: } // switch Inst[4] |
| 2362 | // 3769: } |
| 2363 | 2, 161, 3, // 3773: case 0x2: { |
| 2364 | OPC_SwitchField, 4, 1, // 3776: switch Inst[4] { |
| 2365 | 0, 77, // 3779: case 0x0: { |
| 2366 | OPC_SwitchField, 20, 1, // 3781: switch Inst[20] { |
| 2367 | 0, 19, // 3784: case 0x0: { |
| 2368 | OPC_SwitchField, 24, 1, // 3786: switch Inst[24] { |
| 2369 | 0, 6, // 3789: case 0x0: { |
| 2370 | OPC_CheckPredicate, 10, // 3791: check predicate 10 |
| 2371 | OPC_Decode, 227, 15, 93, // 3793: decode to STRB_POST_REG using decoder 93 |
| 2372 | // 3793: } |
| 2373 | 1, 0, // 3797: case 0x1: { |
| 2374 | OPC_CheckPredicate, 10, // 3799: check predicate 10 |
| 2375 | OPC_Decode, 231, 15, 115, // 3801: decode to STRBrs using decoder 115 |
| 2376 | // 3801: } |
| 2377 | // 3801: } // switch Inst[24] |
| 2378 | // 3801: } |
| 2379 | 1, 0, // 3805: case 0x1: { |
| 2380 | OPC_SwitchField, 24, 1, // 3807: switch Inst[24] { |
| 2381 | 0, 22, // 3810: case 0x0: { |
| 2382 | OPC_Scope, 14, // 3812: try { |
| 2383 | OPC_CheckField, 12, 4, 15, // 3814: check Inst[15:12] == 0xf |
| 2384 | OPC_CheckPredicate, 25, // 3818: check predicate 25 |
| 2385 | OPC_CheckField, 28, 4, 15, // 3820: check Inst[31:28] == 0xf |
| 2386 | OPC_Decode, 211, 14, 102, // 3824: decode to PLIrs using decoder 102 |
| 2387 | // 3824: } else try { |
| 2388 | OPC_CheckPredicate, 10, // 3828: check predicate 10 |
| 2389 | OPC_Decode, 182, 7, 93, // 3830: decode to LDRB_POST_REG using decoder 93 |
| 2390 | // 3830: } |
| 2391 | // 3830: } |
| 2392 | 1, 0, // 3834: case 0x1: { |
| 2393 | OPC_Scope, 14, // 3836: try { |
| 2394 | OPC_CheckField, 12, 4, 15, // 3838: check Inst[15:12] == 0xf |
| 2395 | OPC_CheckPredicate, 10, // 3842: check predicate 10 |
| 2396 | OPC_CheckField, 28, 4, 15, // 3844: check Inst[31:28] == 0xf |
| 2397 | OPC_Decode, 209, 14, 102, // 3848: decode to PLDrs using decoder 102 |
| 2398 | // 3848: } else try { |
| 2399 | OPC_CheckPredicate, 10, // 3852: check predicate 10 |
| 2400 | OPC_Decode, 186, 7, 115, // 3854: decode to LDRBrs using decoder 115 |
| 2401 | // 3854: } |
| 2402 | // 3854: } |
| 2403 | // 3854: } // switch Inst[24] |
| 2404 | // 3854: } |
| 2405 | // 3854: } // switch Inst[20] |
| 2406 | // 3854: } |
| 2407 | 1, 0, // 3858: case 0x1: { |
| 2408 | OPC_SwitchField, 5, 2, // 3860: switch Inst[6:5] { |
| 2409 | 0, 101, // 3863: case 0x0: { |
| 2410 | OPC_SwitchField, 23, 2, // 3865: switch Inst[24:23] { |
| 2411 | 0, 35, // 3868: case 0x0: { |
| 2412 | OPC_SwitchField, 7, 1, // 3870: switch Inst[7] { |
| 2413 | 0, 14, // 3873: case 0x0: { |
| 2414 | OPC_CheckPredicate, 10, // 3875: check predicate 10 |
| 2415 | OPC_CheckField, 20, 1, 1, // 3877: check Inst[20] == 0x1 |
| 2416 | OPC_SoftFail, 0, 128, 30, // 3881: softfail pos=0x00000000 neg=0x00000f00 |
| 2417 | OPC_Decode, 147, 16, 103, // 3885: decode to UADD16 using decoder 103 |
| 2418 | // 3885: } |
| 2419 | 1, 0, // 3889: case 0x1: { |
| 2420 | OPC_CheckPredicate, 10, // 3891: check predicate 10 |
| 2421 | OPC_CheckField, 20, 1, 1, // 3893: check Inst[20] == 0x1 |
| 2422 | OPC_SoftFail, 0, 128, 30, // 3897: softfail pos=0x00000000 neg=0x00000f00 |
| 2423 | OPC_Decode, 148, 16, 103, // 3901: decode to UADD8 using decoder 103 |
| 2424 | // 3901: } |
| 2425 | // 3901: } // switch Inst[7] |
| 2426 | // 3901: } |
| 2427 | 2, 39, // 3905: case 0x2: { |
| 2428 | OPC_SwitchField, 20, 1, // 3907: switch Inst[20] { |
| 2429 | 0, 10, // 3910: case 0x0: { |
| 2430 | OPC_CheckPredicate, 11, // 3912: check predicate 11 |
| 2431 | OPC_CheckField, 7, 1, 0, // 3914: check Inst[7] == 0x0 |
| 2432 | OPC_Decode, 151, 15, 57, // 3918: decode to SMLALD using decoder 57 |
| 2433 | // 3918: } |
| 2434 | 1, 0, // 3922: case 0x1: { |
| 2435 | OPC_CheckField, 7, 1, 0, // 3924: check Inst[7] == 0x0 |
| 2436 | OPC_Scope, 10, // 3928: try { |
| 2437 | OPC_CheckField, 12, 4, 15, // 3930: check Inst[15:12] == 0xf |
| 2438 | OPC_CheckPredicate, 11, // 3934: check predicate 11 |
| 2439 | OPC_Decode, 167, 15, 68, // 3936: decode to SMMUL using decoder 68 |
| 2440 | // 3936: } else try { |
| 2441 | OPC_CheckPredicate, 11, // 3940: check predicate 11 |
| 2442 | OPC_Decode, 163, 15, 77, // 3942: decode to SMMLA using decoder 77 |
| 2443 | // 3942: } |
| 2444 | // 3942: } |
| 2445 | // 3942: } // switch Inst[20] |
| 2446 | // 3942: } |
| 2447 | 3, 0, // 3946: case 0x3: { |
| 2448 | OPC_Scope, 10, // 3948: try { |
| 2449 | OPC_CheckField, 0, 4, 15, // 3950: check Inst[3:0] == 0xf |
| 2450 | OPC_CheckPredicate, 23, // 3954: check predicate 23 |
| 2451 | OPC_Decode, 186, 6, 116, // 3956: decode to BFC using decoder 116 |
| 2452 | // 3956: } else try { |
| 2453 | OPC_CheckPredicate, 23, // 3960: check predicate 23 |
| 2454 | OPC_Decode, 187, 6, 117, // 3962: decode to BFI using decoder 117 |
| 2455 | // 3962: } |
| 2456 | // 3962: } |
| 2457 | // 3962: } // switch Inst[24:23] |
| 2458 | // 3962: } |
| 2459 | 1, 64, // 3966: case 0x1: { |
| 2460 | OPC_SwitchField, 20, 1, // 3968: switch Inst[20] { |
| 2461 | 0, 14, // 3971: case 0x0: { |
| 2462 | OPC_CheckPredicate, 11, // 3973: check predicate 11 |
| 2463 | OPC_CheckField, 23, 2, 2, // 3975: check Inst[24:23] == 0x2 |
| 2464 | OPC_CheckField, 7, 1, 0, // 3979: check Inst[7] == 0x0 |
| 2465 | OPC_Decode, 152, 15, 57, // 3983: decode to SMLALDX using decoder 57 |
| 2466 | // 3983: } |
| 2467 | 1, 0, // 3987: case 0x1: { |
| 2468 | OPC_SwitchField, 23, 2, // 3989: switch Inst[24:23] { |
| 2469 | 0, 14, // 3992: case 0x0: { |
| 2470 | OPC_CheckPredicate, 10, // 3994: check predicate 10 |
| 2471 | OPC_CheckField, 7, 1, 0, // 3996: check Inst[7] == 0x0 |
| 2472 | OPC_SoftFail, 0, 128, 30, // 4000: softfail pos=0x00000000 neg=0x00000f00 |
| 2473 | OPC_Decode, 149, 16, 103, // 4004: decode to UASX using decoder 103 |
| 2474 | // 4004: } |
| 2475 | 2, 0, // 4008: case 0x2: { |
| 2476 | OPC_CheckField, 7, 1, 0, // 4010: check Inst[7] == 0x0 |
| 2477 | OPC_Scope, 10, // 4014: try { |
| 2478 | OPC_CheckField, 12, 4, 15, // 4016: check Inst[15:12] == 0xf |
| 2479 | OPC_CheckPredicate, 11, // 4020: check predicate 11 |
| 2480 | OPC_Decode, 168, 15, 68, // 4022: decode to SMMULR using decoder 68 |
| 2481 | // 4022: } else try { |
| 2482 | OPC_CheckPredicate, 11, // 4026: check predicate 11 |
| 2483 | OPC_Decode, 164, 15, 77, // 4028: decode to SMMLAR using decoder 77 |
| 2484 | // 4028: } |
| 2485 | // 4028: } |
| 2486 | // 4028: } // switch Inst[24:23] |
| 2487 | // 4028: } |
| 2488 | // 4028: } // switch Inst[20] |
| 2489 | // 4028: } |
| 2490 | 2, 52, // 4032: case 0x2: { |
| 2491 | OPC_SwitchField, 7, 1, // 4034: switch Inst[7] { |
| 2492 | 0, 31, // 4037: case 0x0: { |
| 2493 | OPC_SwitchField, 20, 1, // 4039: switch Inst[20] { |
| 2494 | 0, 10, // 4042: case 0x0: { |
| 2495 | OPC_CheckPredicate, 11, // 4044: check predicate 11 |
| 2496 | OPC_CheckField, 23, 2, 2, // 4046: check Inst[24:23] == 0x2 |
| 2497 | OPC_Decode, 161, 15, 57, // 4050: decode to SMLSLD using decoder 57 |
| 2498 | // 4050: } |
| 2499 | 1, 0, // 4054: case 0x1: { |
| 2500 | OPC_CheckPredicate, 10, // 4056: check predicate 10 |
| 2501 | OPC_CheckField, 23, 2, 0, // 4058: check Inst[24:23] == 0x0 |
| 2502 | OPC_SoftFail, 0, 128, 30, // 4062: softfail pos=0x00000000 neg=0x00000f00 |
| 2503 | OPC_Decode, 172, 16, 103, // 4066: decode to USAX using decoder 103 |
| 2504 | // 4066: } |
| 2505 | // 4066: } // switch Inst[20] |
| 2506 | // 4066: } |
| 2507 | 1, 0, // 4070: case 0x1: { |
| 2508 | OPC_CheckPredicate, 11, // 4072: check predicate 11 |
| 2509 | OPC_CheckField, 23, 2, 2, // 4074: check Inst[24:23] == 0x2 |
| 2510 | OPC_CheckField, 20, 1, 1, // 4078: check Inst[20] == 0x1 |
| 2511 | OPC_Decode, 165, 15, 77, // 4082: decode to SMMLS using decoder 77 |
| 2512 | // 4082: } |
| 2513 | // 4082: } // switch Inst[7] |
| 2514 | // 4082: } |
| 2515 | 3, 0, // 4086: case 0x3: { |
| 2516 | OPC_SwitchField, 23, 2, // 4088: switch Inst[24:23] { |
| 2517 | 0, 35, // 4091: case 0x0: { |
| 2518 | OPC_SwitchField, 7, 1, // 4093: switch Inst[7] { |
| 2519 | 0, 14, // 4096: case 0x0: { |
| 2520 | OPC_CheckPredicate, 10, // 4098: check predicate 10 |
| 2521 | OPC_CheckField, 20, 1, 1, // 4100: check Inst[20] == 0x1 |
| 2522 | OPC_SoftFail, 0, 128, 30, // 4104: softfail pos=0x00000000 neg=0x00000f00 |
| 2523 | OPC_Decode, 173, 16, 103, // 4108: decode to USUB16 using decoder 103 |
| 2524 | // 4108: } |
| 2525 | 1, 0, // 4112: case 0x1: { |
| 2526 | OPC_CheckPredicate, 10, // 4114: check predicate 10 |
| 2527 | OPC_CheckField, 20, 1, 1, // 4116: check Inst[20] == 0x1 |
| 2528 | OPC_SoftFail, 0, 128, 30, // 4120: softfail pos=0x00000000 neg=0x00000f00 |
| 2529 | OPC_Decode, 174, 16, 103, // 4124: decode to USUB8 using decoder 103 |
| 2530 | // 4124: } |
| 2531 | // 4124: } // switch Inst[7] |
| 2532 | // 4124: } |
| 2533 | 1, 34, // 4128: case 0x1: { |
| 2534 | OPC_CheckField, 7, 1, 0, // 4130: check Inst[7] == 0x0 |
| 2535 | OPC_CheckField, 20, 1, 0, // 4134: check Inst[20] == 0x0 |
| 2536 | OPC_Scope, 14, // 4138: try { |
| 2537 | OPC_CheckField, 16, 4, 15, // 4140: check Inst[19:16] == 0xf |
| 2538 | OPC_CheckPredicate, 11, // 4144: check predicate 11 |
| 2539 | OPC_SoftFail, 128, 6, 0, // 4146: softfail pos=0x00000300 neg=0x00000000 |
| 2540 | OPC_Decode, 179, 16, 108, // 4150: decode to UXTB16 using decoder 108 |
| 2541 | // 4150: } else try { |
| 2542 | OPC_CheckPredicate, 11, // 4154: check predicate 11 |
| 2543 | OPC_SoftFail, 128, 6, 0, // 4156: softfail pos=0x00000300 neg=0x00000000 |
| 2544 | OPC_Decode, 176, 16, 109, // 4160: decode to UXTAB16 using decoder 109 |
| 2545 | // 4160: } |
| 2546 | // 4160: } |
| 2547 | 2, 0, // 4164: case 0x2: { |
| 2548 | OPC_SwitchField, 7, 1, // 4166: switch Inst[7] { |
| 2549 | 0, 10, // 4169: case 0x0: { |
| 2550 | OPC_CheckPredicate, 11, // 4171: check predicate 11 |
| 2551 | OPC_CheckField, 20, 1, 0, // 4173: check Inst[20] == 0x0 |
| 2552 | OPC_Decode, 162, 15, 57, // 4177: decode to SMLSLDX using decoder 57 |
| 2553 | // 4177: } |
| 2554 | 1, 0, // 4181: case 0x1: { |
| 2555 | OPC_CheckPredicate, 11, // 4183: check predicate 11 |
| 2556 | OPC_CheckField, 20, 1, 1, // 4185: check Inst[20] == 0x1 |
| 2557 | OPC_Decode, 166, 15, 77, // 4189: decode to SMMLSR using decoder 77 |
| 2558 | // 4189: } |
| 2559 | // 4189: } // switch Inst[7] |
| 2560 | // 4189: } |
| 2561 | // 4189: } // switch Inst[24:23] |
| 2562 | // 4189: } |
| 2563 | // 4189: } // switch Inst[6:5] |
| 2564 | // 4189: } |
| 2565 | // 4189: } // switch Inst[4] |
| 2566 | // 4189: } |
| 2567 | 3, 0, // 4193: case 0x3: { |
| 2568 | OPC_SwitchField, 4, 1, // 4195: switch Inst[4] { |
| 2569 | 0, 45, // 4198: case 0x0: { |
| 2570 | OPC_SwitchField, 20, 1, // 4200: switch Inst[20] { |
| 2571 | 0, 19, // 4203: case 0x0: { |
| 2572 | OPC_SwitchField, 24, 1, // 4205: switch Inst[24] { |
| 2573 | 0, 6, // 4208: case 0x0: { |
| 2574 | OPC_CheckPredicate, 10, // 4210: check predicate 10 |
| 2575 | OPC_Decode, 225, 15, 93, // 4212: decode to STRBT_POST_REG using decoder 93 |
| 2576 | // 4212: } |
| 2577 | 1, 0, // 4216: case 0x1: { |
| 2578 | OPC_CheckPredicate, 10, // 4218: check predicate 10 |
| 2579 | OPC_Decode, 229, 15, 110, // 4220: decode to STRB_PRE_REG using decoder 110 |
| 2580 | // 4220: } |
| 2581 | // 4220: } // switch Inst[24] |
| 2582 | // 4220: } |
| 2583 | 1, 0, // 4224: case 0x1: { |
| 2584 | OPC_SwitchField, 24, 1, // 4226: switch Inst[24] { |
| 2585 | 0, 6, // 4229: case 0x0: { |
| 2586 | OPC_CheckPredicate, 10, // 4231: check predicate 10 |
| 2587 | OPC_Decode, 180, 7, 93, // 4233: decode to LDRBT_POST_REG using decoder 93 |
| 2588 | // 4233: } |
| 2589 | 1, 0, // 4237: case 0x1: { |
| 2590 | OPC_CheckPredicate, 10, // 4239: check predicate 10 |
| 2591 | OPC_Decode, 184, 7, 111, // 4241: decode to LDRB_PRE_REG using decoder 111 |
| 2592 | // 4241: } |
| 2593 | // 4241: } // switch Inst[24] |
| 2594 | // 4241: } |
| 2595 | // 4241: } // switch Inst[20] |
| 2596 | // 4241: } |
| 2597 | 1, 0, // 4245: case 0x1: { |
| 2598 | OPC_SwitchField, 23, 2, // 4247: switch Inst[24:23] { |
| 2599 | 0, 177, 1, // 4250: case 0x0: { |
| 2600 | OPC_SwitchField, 5, 3, // 4253: switch Inst[7:5] { |
| 2601 | 0, 27, // 4256: case 0x0: { |
| 2602 | OPC_SwitchField, 20, 1, // 4258: switch Inst[20] { |
| 2603 | 0, 10, // 4261: case 0x0: { |
| 2604 | OPC_CheckPredicate, 10, // 4263: check predicate 10 |
| 2605 | OPC_SoftFail, 0, 128, 30, // 4265: softfail pos=0x00000000 neg=0x00000f00 |
| 2606 | OPC_Decode, 162, 16, 103, // 4269: decode to UQADD16 using decoder 103 |
| 2607 | // 4269: } |
| 2608 | 1, 0, // 4273: case 0x1: { |
| 2609 | OPC_CheckPredicate, 10, // 4275: check predicate 10 |
| 2610 | OPC_SoftFail, 0, 128, 30, // 4277: softfail pos=0x00000000 neg=0x00000f00 |
| 2611 | OPC_Decode, 153, 16, 103, // 4281: decode to UHADD16 using decoder 103 |
| 2612 | // 4281: } |
| 2613 | // 4281: } // switch Inst[20] |
| 2614 | // 4281: } |
| 2615 | 1, 27, // 4285: case 0x1: { |
| 2616 | OPC_SwitchField, 20, 1, // 4287: switch Inst[20] { |
| 2617 | 0, 10, // 4290: case 0x0: { |
| 2618 | OPC_CheckPredicate, 10, // 4292: check predicate 10 |
| 2619 | OPC_SoftFail, 0, 128, 30, // 4294: softfail pos=0x00000000 neg=0x00000f00 |
| 2620 | OPC_Decode, 164, 16, 103, // 4298: decode to UQASX using decoder 103 |
| 2621 | // 4298: } |
| 2622 | 1, 0, // 4302: case 0x1: { |
| 2623 | OPC_CheckPredicate, 10, // 4304: check predicate 10 |
| 2624 | OPC_SoftFail, 0, 128, 30, // 4306: softfail pos=0x00000000 neg=0x00000f00 |
| 2625 | OPC_Decode, 155, 16, 103, // 4310: decode to UHASX using decoder 103 |
| 2626 | // 4310: } |
| 2627 | // 4310: } // switch Inst[20] |
| 2628 | // 4310: } |
| 2629 | 2, 27, // 4314: case 0x2: { |
| 2630 | OPC_SwitchField, 20, 1, // 4316: switch Inst[20] { |
| 2631 | 0, 10, // 4319: case 0x0: { |
| 2632 | OPC_CheckPredicate, 10, // 4321: check predicate 10 |
| 2633 | OPC_SoftFail, 0, 128, 30, // 4323: softfail pos=0x00000000 neg=0x00000f00 |
| 2634 | OPC_Decode, 165, 16, 103, // 4327: decode to UQSAX using decoder 103 |
| 2635 | // 4327: } |
| 2636 | 1, 0, // 4331: case 0x1: { |
| 2637 | OPC_CheckPredicate, 10, // 4333: check predicate 10 |
| 2638 | OPC_SoftFail, 0, 128, 30, // 4335: softfail pos=0x00000000 neg=0x00000f00 |
| 2639 | OPC_Decode, 156, 16, 103, // 4339: decode to UHSAX using decoder 103 |
| 2640 | // 4339: } |
| 2641 | // 4339: } // switch Inst[20] |
| 2642 | // 4339: } |
| 2643 | 3, 27, // 4343: case 0x3: { |
| 2644 | OPC_SwitchField, 20, 1, // 4345: switch Inst[20] { |
| 2645 | 0, 10, // 4348: case 0x0: { |
| 2646 | OPC_CheckPredicate, 10, // 4350: check predicate 10 |
| 2647 | OPC_SoftFail, 0, 128, 30, // 4352: softfail pos=0x00000000 neg=0x00000f00 |
| 2648 | OPC_Decode, 166, 16, 103, // 4356: decode to UQSUB16 using decoder 103 |
| 2649 | // 4356: } |
| 2650 | 1, 0, // 4360: case 0x1: { |
| 2651 | OPC_CheckPredicate, 10, // 4362: check predicate 10 |
| 2652 | OPC_SoftFail, 0, 128, 30, // 4364: softfail pos=0x00000000 neg=0x00000f00 |
| 2653 | OPC_Decode, 157, 16, 103, // 4368: decode to UHSUB16 using decoder 103 |
| 2654 | // 4368: } |
| 2655 | // 4368: } // switch Inst[20] |
| 2656 | // 4368: } |
| 2657 | 4, 27, // 4372: case 0x4: { |
| 2658 | OPC_SwitchField, 20, 1, // 4374: switch Inst[20] { |
| 2659 | 0, 10, // 4377: case 0x0: { |
| 2660 | OPC_CheckPredicate, 10, // 4379: check predicate 10 |
| 2661 | OPC_SoftFail, 0, 128, 30, // 4381: softfail pos=0x00000000 neg=0x00000f00 |
| 2662 | OPC_Decode, 163, 16, 103, // 4385: decode to UQADD8 using decoder 103 |
| 2663 | // 4385: } |
| 2664 | 1, 0, // 4389: case 0x1: { |
| 2665 | OPC_CheckPredicate, 10, // 4391: check predicate 10 |
| 2666 | OPC_SoftFail, 0, 128, 30, // 4393: softfail pos=0x00000000 neg=0x00000f00 |
| 2667 | OPC_Decode, 154, 16, 103, // 4397: decode to UHADD8 using decoder 103 |
| 2668 | // 4397: } |
| 2669 | // 4397: } // switch Inst[20] |
| 2670 | // 4397: } |
| 2671 | 7, 0, // 4401: case 0x7: { |
| 2672 | OPC_SwitchField, 20, 1, // 4403: switch Inst[20] { |
| 2673 | 0, 10, // 4406: case 0x0: { |
| 2674 | OPC_CheckPredicate, 10, // 4408: check predicate 10 |
| 2675 | OPC_SoftFail, 0, 128, 30, // 4410: softfail pos=0x00000000 neg=0x00000f00 |
| 2676 | OPC_Decode, 167, 16, 103, // 4414: decode to UQSUB8 using decoder 103 |
| 2677 | // 4414: } |
| 2678 | 1, 0, // 4418: case 0x1: { |
| 2679 | OPC_CheckPredicate, 10, // 4420: check predicate 10 |
| 2680 | OPC_SoftFail, 0, 128, 30, // 4422: softfail pos=0x00000000 neg=0x00000f00 |
| 2681 | OPC_Decode, 158, 16, 103, // 4426: decode to UHSUB8 using decoder 103 |
| 2682 | // 4426: } |
| 2683 | // 4426: } // switch Inst[20] |
| 2684 | // 4426: } |
| 2685 | // 4426: } // switch Inst[7:5] |
| 2686 | // 4426: } |
| 2687 | 1, 126, // 4430: case 0x1: { |
| 2688 | OPC_SwitchField, 5, 1, // 4432: switch Inst[5] { |
| 2689 | 0, 6, // 4435: case 0x0: { |
| 2690 | OPC_CheckPredicate, 11, // 4437: check predicate 11 |
| 2691 | OPC_Decode, 170, 16, 112, // 4439: decode to USAT using decoder 112 |
| 2692 | // 4439: } |
| 2693 | 1, 0, // 4443: case 0x1: { |
| 2694 | OPC_SwitchField, 6, 2, // 4445: switch Inst[7:6] { |
| 2695 | 0, 31, // 4448: case 0x0: { |
| 2696 | OPC_SwitchField, 20, 1, // 4450: switch Inst[20] { |
| 2697 | 0, 10, // 4453: case 0x0: { |
| 2698 | OPC_CheckPredicate, 11, // 4455: check predicate 11 |
| 2699 | OPC_CheckField, 8, 4, 15, // 4457: check Inst[11:8] == 0xf |
| 2700 | OPC_Decode, 171, 16, 113, // 4461: decode to USAT16 using decoder 113 |
| 2701 | // 4461: } |
| 2702 | 1, 0, // 4465: case 0x1: { |
| 2703 | OPC_CheckPredicate, 23, // 4467: check predicate 23 |
| 2704 | OPC_CheckField, 16, 4, 15, // 4469: check Inst[19:16] == 0xf |
| 2705 | OPC_CheckField, 8, 4, 15, // 4473: check Inst[11:8] == 0xf |
| 2706 | OPC_Decode, 222, 14, 73, // 4477: decode to RBIT using decoder 73 |
| 2707 | // 4477: } |
| 2708 | // 4477: } // switch Inst[20] |
| 2709 | // 4477: } |
| 2710 | 1, 59, // 4481: case 0x1: { |
| 2711 | OPC_SwitchField, 20, 1, // 4483: switch Inst[20] { |
| 2712 | 0, 26, // 4486: case 0x0: { |
| 2713 | OPC_Scope, 14, // 4488: try { |
| 2714 | OPC_CheckField, 16, 4, 15, // 4490: check Inst[19:16] == 0xf |
| 2715 | OPC_CheckPredicate, 11, // 4494: check predicate 11 |
| 2716 | OPC_SoftFail, 128, 6, 0, // 4496: softfail pos=0x00000300 neg=0x00000000 |
| 2717 | OPC_Decode, 178, 16, 108, // 4500: decode to UXTB using decoder 108 |
| 2718 | // 4500: } else try { |
| 2719 | OPC_CheckPredicate, 11, // 4504: check predicate 11 |
| 2720 | OPC_SoftFail, 128, 6, 0, // 4506: softfail pos=0x00000300 neg=0x00000000 |
| 2721 | OPC_Decode, 175, 16, 109, // 4510: decode to UXTAB using decoder 109 |
| 2722 | // 4510: } |
| 2723 | // 4510: } |
| 2724 | 1, 0, // 4514: case 0x1: { |
| 2725 | OPC_Scope, 14, // 4516: try { |
| 2726 | OPC_CheckField, 16, 4, 15, // 4518: check Inst[19:16] == 0xf |
| 2727 | OPC_CheckPredicate, 11, // 4522: check predicate 11 |
| 2728 | OPC_SoftFail, 128, 6, 0, // 4524: softfail pos=0x00000300 neg=0x00000000 |
| 2729 | OPC_Decode, 180, 16, 108, // 4528: decode to UXTH using decoder 108 |
| 2730 | // 4528: } else try { |
| 2731 | OPC_CheckPredicate, 11, // 4532: check predicate 11 |
| 2732 | OPC_SoftFail, 128, 6, 0, // 4534: softfail pos=0x00000300 neg=0x00000000 |
| 2733 | OPC_Decode, 177, 16, 109, // 4538: decode to UXTAH using decoder 109 |
| 2734 | // 4538: } |
| 2735 | // 4538: } |
| 2736 | // 4538: } // switch Inst[20] |
| 2737 | // 4538: } |
| 2738 | 2, 0, // 4542: case 0x2: { |
| 2739 | OPC_CheckPredicate, 11, // 4544: check predicate 11 |
| 2740 | OPC_CheckField, 16, 5, 31, // 4546: check Inst[20:16] == 0x1f |
| 2741 | OPC_CheckField, 8, 4, 15, // 4550: check Inst[11:8] == 0xf |
| 2742 | OPC_Decode, 225, 14, 73, // 4554: decode to REVSH using decoder 73 |
| 2743 | // 4554: } |
| 2744 | // 4554: } // switch Inst[7:6] |
| 2745 | // 4554: } |
| 2746 | // 4554: } // switch Inst[5] |
| 2747 | // 4554: } |
| 2748 | 3, 0, // 4558: case 0x3: { |
| 2749 | OPC_SwitchField, 5, 2, // 4560: switch Inst[6:5] { |
| 2750 | 2, 6, // 4563: case 0x2: { |
| 2751 | OPC_CheckPredicate, 23, // 4565: check predicate 23 |
| 2752 | OPC_Decode, 150, 16, 114, // 4567: decode to UBFX using decoder 114 |
| 2753 | // 4567: } |
| 2754 | 3, 0, // 4571: case 0x3: { |
| 2755 | OPC_CheckField, 7, 1, 1, // 4573: check Inst[7] == 0x1 |
| 2756 | OPC_CheckField, 20, 1, 1, // 4577: check Inst[20] == 0x1 |
| 2757 | OPC_CheckField, 28, 4, 14, // 4581: check Inst[31:28] == 0xe |
| 2758 | OPC_Scope, 15, // 4585: try { |
| 2759 | OPC_CheckField, 0, 4, 14, // 4587: check Inst[3:0] == 0xe |
| 2760 | OPC_CheckPredicate, 10, // 4591: check predicate 10 |
| 2761 | OPC_CheckField, 8, 12, 222, 31, // 4593: check Inst[19:8] == 0xfde |
| 2762 | OPC_Decode, 141, 16, 25, // 4598: decode to TRAP using decoder 25 |
| 2763 | // 4598: } else try { |
| 2764 | OPC_CheckPredicate, 10, // 4602: check predicate 10 |
| 2765 | OPC_Decode, 151, 16, 53, // 4604: decode to UDF using decoder 53 |
| 2766 | // 4604: } |
| 2767 | // 4604: } |
| 2768 | // 4604: } // switch Inst[6:5] |
| 2769 | // 4604: } |
| 2770 | // 4604: } // switch Inst[24:23] |
| 2771 | // 4604: } |
| 2772 | // 4604: } // switch Inst[4] |
| 2773 | // 4604: } |
| 2774 | // 4604: } // switch Inst[22:21] |
| 2775 | // 4604: } |
| 2776 | 4, 155, 4, // 4608: case 0x4: { |
| 2777 | OPC_SwitchField, 20, 5, // 4611: switch Inst[24:20] { |
| 2778 | 0, 6, // 4614: case 0x0: { |
| 2779 | OPC_CheckPredicate, 10, // 4616: check predicate 10 |
| 2780 | OPC_Decode, 216, 15, 118, // 4618: decode to STMDA using decoder 118 |
| 2781 | // 4618: } |
| 2782 | 1, 23, // 4622: case 0x1: { |
| 2783 | OPC_Scope, 15, // 4624: try { |
| 2784 | OPC_CheckField, 0, 16, 128, 20, // 4626: check Inst[15:0] == 0xa00 |
| 2785 | OPC_CheckPredicate, 10, // 4631: check predicate 10 |
| 2786 | OPC_CheckField, 28, 4, 15, // 4633: check Inst[31:28] == 0xf |
| 2787 | OPC_Decode, 226, 14, 119, // 4637: decode to RFEDA using decoder 119 |
| 2788 | // 4637: } else try { |
| 2789 | OPC_CheckPredicate, 10, // 4641: check predicate 10 |
| 2790 | OPC_Decode, 171, 7, 118, // 4643: decode to LDMDA using decoder 118 |
| 2791 | // 4643: } |
| 2792 | // 4643: } |
| 2793 | 2, 6, // 4647: case 0x2: { |
| 2794 | OPC_CheckPredicate, 10, // 4649: check predicate 10 |
| 2795 | OPC_Decode, 217, 15, 120, // 4651: decode to STMDA_UPD using decoder 120 |
| 2796 | // 4651: } |
| 2797 | 3, 23, // 4655: case 0x3: { |
| 2798 | OPC_Scope, 15, // 4657: try { |
| 2799 | OPC_CheckField, 0, 16, 128, 20, // 4659: check Inst[15:0] == 0xa00 |
| 2800 | OPC_CheckPredicate, 10, // 4664: check predicate 10 |
| 2801 | OPC_CheckField, 28, 4, 15, // 4666: check Inst[31:28] == 0xf |
| 2802 | OPC_Decode, 227, 14, 119, // 4670: decode to RFEDA_UPD using decoder 119 |
| 2803 | // 4670: } else try { |
| 2804 | OPC_CheckPredicate, 10, // 4674: check predicate 10 |
| 2805 | OPC_Decode, 172, 7, 120, // 4676: decode to LDMDA_UPD using decoder 120 |
| 2806 | // 4676: } |
| 2807 | // 4676: } |
| 2808 | 4, 24, // 4680: case 0x4: { |
| 2809 | OPC_Scope, 16, // 4682: try { |
| 2810 | OPC_CheckField, 5, 15, 168, 208, 1, // 4684: check Inst[19:5] == 0x6828 |
| 2811 | OPC_CheckPredicate, 10, // 4690: check predicate 10 |
| 2812 | OPC_CheckField, 28, 4, 15, // 4692: check Inst[31:28] == 0xf |
| 2813 | OPC_Decode, 180, 15, 121, // 4696: decode to SRSDA using decoder 121 |
| 2814 | // 4696: } else try { |
| 2815 | OPC_CheckPredicate, 10, // 4700: check predicate 10 |
| 2816 | OPC_Decode, 187, 31, 118, // 4702: decode to sysSTMDA using decoder 118 |
| 2817 | // 4702: } |
| 2818 | // 4702: } |
| 2819 | 5, 6, // 4706: case 0x5: { |
| 2820 | OPC_CheckPredicate, 10, // 4708: check predicate 10 |
| 2821 | OPC_Decode, 179, 31, 118, // 4710: decode to sysLDMDA using decoder 118 |
| 2822 | // 4710: } |
| 2823 | 6, 24, // 4714: case 0x6: { |
| 2824 | OPC_Scope, 16, // 4716: try { |
| 2825 | OPC_CheckField, 5, 15, 168, 208, 1, // 4718: check Inst[19:5] == 0x6828 |
| 2826 | OPC_CheckPredicate, 10, // 4724: check predicate 10 |
| 2827 | OPC_CheckField, 28, 4, 15, // 4726: check Inst[31:28] == 0xf |
| 2828 | OPC_Decode, 181, 15, 121, // 4730: decode to SRSDA_UPD using decoder 121 |
| 2829 | // 4730: } else try { |
| 2830 | OPC_CheckPredicate, 10, // 4734: check predicate 10 |
| 2831 | OPC_Decode, 188, 31, 120, // 4736: decode to sysSTMDA_UPD using decoder 120 |
| 2832 | // 4736: } |
| 2833 | // 4736: } |
| 2834 | 7, 6, // 4740: case 0x7: { |
| 2835 | OPC_CheckPredicate, 10, // 4742: check predicate 10 |
| 2836 | OPC_Decode, 180, 31, 120, // 4744: decode to sysLDMDA_UPD using decoder 120 |
| 2837 | // 4744: } |
| 2838 | 8, 6, // 4748: case 0x8: { |
| 2839 | OPC_CheckPredicate, 10, // 4750: check predicate 10 |
| 2840 | OPC_Decode, 220, 15, 118, // 4752: decode to STMIA using decoder 118 |
| 2841 | // 4752: } |
| 2842 | 9, 23, // 4756: case 0x9: { |
| 2843 | OPC_Scope, 15, // 4758: try { |
| 2844 | OPC_CheckField, 0, 16, 128, 20, // 4760: check Inst[15:0] == 0xa00 |
| 2845 | OPC_CheckPredicate, 10, // 4765: check predicate 10 |
| 2846 | OPC_CheckField, 28, 4, 15, // 4767: check Inst[31:28] == 0xf |
| 2847 | OPC_Decode, 230, 14, 119, // 4771: decode to RFEIA using decoder 119 |
| 2848 | // 4771: } else try { |
| 2849 | OPC_CheckPredicate, 10, // 4775: check predicate 10 |
| 2850 | OPC_Decode, 175, 7, 118, // 4777: decode to LDMIA using decoder 118 |
| 2851 | // 4777: } |
| 2852 | // 4777: } |
| 2853 | 10, 6, // 4781: case 0xa: { |
| 2854 | OPC_CheckPredicate, 10, // 4783: check predicate 10 |
| 2855 | OPC_Decode, 221, 15, 120, // 4785: decode to STMIA_UPD using decoder 120 |
| 2856 | // 4785: } |
| 2857 | 11, 23, // 4789: case 0xb: { |
| 2858 | OPC_Scope, 15, // 4791: try { |
| 2859 | OPC_CheckField, 0, 16, 128, 20, // 4793: check Inst[15:0] == 0xa00 |
| 2860 | OPC_CheckPredicate, 10, // 4798: check predicate 10 |
| 2861 | OPC_CheckField, 28, 4, 15, // 4800: check Inst[31:28] == 0xf |
| 2862 | OPC_Decode, 231, 14, 119, // 4804: decode to RFEIA_UPD using decoder 119 |
| 2863 | // 4804: } else try { |
| 2864 | OPC_CheckPredicate, 10, // 4808: check predicate 10 |
| 2865 | OPC_Decode, 176, 7, 120, // 4810: decode to LDMIA_UPD using decoder 120 |
| 2866 | // 4810: } |
| 2867 | // 4810: } |
| 2868 | 12, 24, // 4814: case 0xc: { |
| 2869 | OPC_Scope, 16, // 4816: try { |
| 2870 | OPC_CheckField, 5, 15, 168, 208, 1, // 4818: check Inst[19:5] == 0x6828 |
| 2871 | OPC_CheckPredicate, 10, // 4824: check predicate 10 |
| 2872 | OPC_CheckField, 28, 4, 15, // 4826: check Inst[31:28] == 0xf |
| 2873 | OPC_Decode, 184, 15, 121, // 4830: decode to SRSIA using decoder 121 |
| 2874 | // 4830: } else try { |
| 2875 | OPC_CheckPredicate, 10, // 4834: check predicate 10 |
| 2876 | OPC_Decode, 191, 31, 118, // 4836: decode to sysSTMIA using decoder 118 |
| 2877 | // 4836: } |
| 2878 | // 4836: } |
| 2879 | 13, 6, // 4840: case 0xd: { |
| 2880 | OPC_CheckPredicate, 10, // 4842: check predicate 10 |
| 2881 | OPC_Decode, 183, 31, 118, // 4844: decode to sysLDMIA using decoder 118 |
| 2882 | // 4844: } |
| 2883 | 14, 24, // 4848: case 0xe: { |
| 2884 | OPC_Scope, 16, // 4850: try { |
| 2885 | OPC_CheckField, 5, 15, 168, 208, 1, // 4852: check Inst[19:5] == 0x6828 |
| 2886 | OPC_CheckPredicate, 10, // 4858: check predicate 10 |
| 2887 | OPC_CheckField, 28, 4, 15, // 4860: check Inst[31:28] == 0xf |
| 2888 | OPC_Decode, 185, 15, 121, // 4864: decode to SRSIA_UPD using decoder 121 |
| 2889 | // 4864: } else try { |
| 2890 | OPC_CheckPredicate, 10, // 4868: check predicate 10 |
| 2891 | OPC_Decode, 192, 31, 120, // 4870: decode to sysSTMIA_UPD using decoder 120 |
| 2892 | // 4870: } |
| 2893 | // 4870: } |
| 2894 | 15, 6, // 4874: case 0xf: { |
| 2895 | OPC_CheckPredicate, 10, // 4876: check predicate 10 |
| 2896 | OPC_Decode, 184, 31, 120, // 4878: decode to sysLDMIA_UPD using decoder 120 |
| 2897 | // 4878: } |
| 2898 | 16, 6, // 4882: case 0x10: { |
| 2899 | OPC_CheckPredicate, 10, // 4884: check predicate 10 |
| 2900 | OPC_Decode, 218, 15, 118, // 4886: decode to STMDB using decoder 118 |
| 2901 | // 4886: } |
| 2902 | 17, 23, // 4890: case 0x11: { |
| 2903 | OPC_Scope, 15, // 4892: try { |
| 2904 | OPC_CheckField, 0, 16, 128, 20, // 4894: check Inst[15:0] == 0xa00 |
| 2905 | OPC_CheckPredicate, 10, // 4899: check predicate 10 |
| 2906 | OPC_CheckField, 28, 4, 15, // 4901: check Inst[31:28] == 0xf |
| 2907 | OPC_Decode, 228, 14, 119, // 4905: decode to RFEDB using decoder 119 |
| 2908 | // 4905: } else try { |
| 2909 | OPC_CheckPredicate, 10, // 4909: check predicate 10 |
| 2910 | OPC_Decode, 173, 7, 118, // 4911: decode to LDMDB using decoder 118 |
| 2911 | // 4911: } |
| 2912 | // 4911: } |
| 2913 | 18, 6, // 4915: case 0x12: { |
| 2914 | OPC_CheckPredicate, 10, // 4917: check predicate 10 |
| 2915 | OPC_Decode, 219, 15, 120, // 4919: decode to STMDB_UPD using decoder 120 |
| 2916 | // 4919: } |
| 2917 | 19, 23, // 4923: case 0x13: { |
| 2918 | OPC_Scope, 15, // 4925: try { |
| 2919 | OPC_CheckField, 0, 16, 128, 20, // 4927: check Inst[15:0] == 0xa00 |
| 2920 | OPC_CheckPredicate, 10, // 4932: check predicate 10 |
| 2921 | OPC_CheckField, 28, 4, 15, // 4934: check Inst[31:28] == 0xf |
| 2922 | OPC_Decode, 229, 14, 119, // 4938: decode to RFEDB_UPD using decoder 119 |
| 2923 | // 4938: } else try { |
| 2924 | OPC_CheckPredicate, 10, // 4942: check predicate 10 |
| 2925 | OPC_Decode, 174, 7, 120, // 4944: decode to LDMDB_UPD using decoder 120 |
| 2926 | // 4944: } |
| 2927 | // 4944: } |
| 2928 | 20, 24, // 4948: case 0x14: { |
| 2929 | OPC_Scope, 16, // 4950: try { |
| 2930 | OPC_CheckField, 5, 15, 168, 208, 1, // 4952: check Inst[19:5] == 0x6828 |
| 2931 | OPC_CheckPredicate, 10, // 4958: check predicate 10 |
| 2932 | OPC_CheckField, 28, 4, 15, // 4960: check Inst[31:28] == 0xf |
| 2933 | OPC_Decode, 182, 15, 121, // 4964: decode to SRSDB using decoder 121 |
| 2934 | // 4964: } else try { |
| 2935 | OPC_CheckPredicate, 10, // 4968: check predicate 10 |
| 2936 | OPC_Decode, 189, 31, 118, // 4970: decode to sysSTMDB using decoder 118 |
| 2937 | // 4970: } |
| 2938 | // 4970: } |
| 2939 | 21, 6, // 4974: case 0x15: { |
| 2940 | OPC_CheckPredicate, 10, // 4976: check predicate 10 |
| 2941 | OPC_Decode, 181, 31, 118, // 4978: decode to sysLDMDB using decoder 118 |
| 2942 | // 4978: } |
| 2943 | 22, 24, // 4982: case 0x16: { |
| 2944 | OPC_Scope, 16, // 4984: try { |
| 2945 | OPC_CheckField, 5, 15, 168, 208, 1, // 4986: check Inst[19:5] == 0x6828 |
| 2946 | OPC_CheckPredicate, 10, // 4992: check predicate 10 |
| 2947 | OPC_CheckField, 28, 4, 15, // 4994: check Inst[31:28] == 0xf |
| 2948 | OPC_Decode, 183, 15, 121, // 4998: decode to SRSDB_UPD using decoder 121 |
| 2949 | // 4998: } else try { |
| 2950 | OPC_CheckPredicate, 10, // 5002: check predicate 10 |
| 2951 | OPC_Decode, 190, 31, 120, // 5004: decode to sysSTMDB_UPD using decoder 120 |
| 2952 | // 5004: } |
| 2953 | // 5004: } |
| 2954 | 23, 6, // 5008: case 0x17: { |
| 2955 | OPC_CheckPredicate, 10, // 5010: check predicate 10 |
| 2956 | OPC_Decode, 182, 31, 120, // 5012: decode to sysLDMDB_UPD using decoder 120 |
| 2957 | // 5012: } |
| 2958 | 24, 6, // 5016: case 0x18: { |
| 2959 | OPC_CheckPredicate, 10, // 5018: check predicate 10 |
| 2960 | OPC_Decode, 222, 15, 118, // 5020: decode to STMIB using decoder 118 |
| 2961 | // 5020: } |
| 2962 | 25, 23, // 5024: case 0x19: { |
| 2963 | OPC_Scope, 15, // 5026: try { |
| 2964 | OPC_CheckField, 0, 16, 128, 20, // 5028: check Inst[15:0] == 0xa00 |
| 2965 | OPC_CheckPredicate, 10, // 5033: check predicate 10 |
| 2966 | OPC_CheckField, 28, 4, 15, // 5035: check Inst[31:28] == 0xf |
| 2967 | OPC_Decode, 232, 14, 119, // 5039: decode to RFEIB using decoder 119 |
| 2968 | // 5039: } else try { |
| 2969 | OPC_CheckPredicate, 10, // 5043: check predicate 10 |
| 2970 | OPC_Decode, 177, 7, 118, // 5045: decode to LDMIB using decoder 118 |
| 2971 | // 5045: } |
| 2972 | // 5045: } |
| 2973 | 26, 6, // 5049: case 0x1a: { |
| 2974 | OPC_CheckPredicate, 10, // 5051: check predicate 10 |
| 2975 | OPC_Decode, 223, 15, 120, // 5053: decode to STMIB_UPD using decoder 120 |
| 2976 | // 5053: } |
| 2977 | 27, 23, // 5057: case 0x1b: { |
| 2978 | OPC_Scope, 15, // 5059: try { |
| 2979 | OPC_CheckField, 0, 16, 128, 20, // 5061: check Inst[15:0] == 0xa00 |
| 2980 | OPC_CheckPredicate, 10, // 5066: check predicate 10 |
| 2981 | OPC_CheckField, 28, 4, 15, // 5068: check Inst[31:28] == 0xf |
| 2982 | OPC_Decode, 233, 14, 119, // 5072: decode to RFEIB_UPD using decoder 119 |
| 2983 | // 5072: } else try { |
| 2984 | OPC_CheckPredicate, 10, // 5076: check predicate 10 |
| 2985 | OPC_Decode, 178, 7, 120, // 5078: decode to LDMIB_UPD using decoder 120 |
| 2986 | // 5078: } |
| 2987 | // 5078: } |
| 2988 | 28, 24, // 5082: case 0x1c: { |
| 2989 | OPC_Scope, 16, // 5084: try { |
| 2990 | OPC_CheckField, 5, 15, 168, 208, 1, // 5086: check Inst[19:5] == 0x6828 |
| 2991 | OPC_CheckPredicate, 10, // 5092: check predicate 10 |
| 2992 | OPC_CheckField, 28, 4, 15, // 5094: check Inst[31:28] == 0xf |
| 2993 | OPC_Decode, 186, 15, 121, // 5098: decode to SRSIB using decoder 121 |
| 2994 | // 5098: } else try { |
| 2995 | OPC_CheckPredicate, 10, // 5102: check predicate 10 |
| 2996 | OPC_Decode, 193, 31, 118, // 5104: decode to sysSTMIB using decoder 118 |
| 2997 | // 5104: } |
| 2998 | // 5104: } |
| 2999 | 29, 6, // 5108: case 0x1d: { |
| 3000 | OPC_CheckPredicate, 10, // 5110: check predicate 10 |
| 3001 | OPC_Decode, 185, 31, 118, // 5112: decode to sysLDMIB using decoder 118 |
| 3002 | // 5112: } |
| 3003 | 30, 24, // 5116: case 0x1e: { |
| 3004 | OPC_Scope, 16, // 5118: try { |
| 3005 | OPC_CheckField, 5, 15, 168, 208, 1, // 5120: check Inst[19:5] == 0x6828 |
| 3006 | OPC_CheckPredicate, 10, // 5126: check predicate 10 |
| 3007 | OPC_CheckField, 28, 4, 15, // 5128: check Inst[31:28] == 0xf |
| 3008 | OPC_Decode, 187, 15, 121, // 5132: decode to SRSIB_UPD using decoder 121 |
| 3009 | // 5132: } else try { |
| 3010 | OPC_CheckPredicate, 10, // 5136: check predicate 10 |
| 3011 | OPC_Decode, 194, 31, 120, // 5138: decode to sysSTMIB_UPD using decoder 120 |
| 3012 | // 5138: } |
| 3013 | // 5138: } |
| 3014 | 31, 0, // 5142: case 0x1f: { |
| 3015 | OPC_CheckPredicate, 10, // 5144: check predicate 10 |
| 3016 | OPC_Decode, 186, 31, 120, // 5146: decode to sysLDMIB_UPD using decoder 120 |
| 3017 | // 5146: } |
| 3018 | // 5146: } // switch Inst[24:20] |
| 3019 | // 5146: } |
| 3020 | 5, 43, // 5150: case 0x5: { |
| 3021 | OPC_Scope, 31, // 5152: try { |
| 3022 | OPC_SwitchField, 24, 1, // 5154: switch Inst[24] { |
| 3023 | 0, 6, // 5157: case 0x0: { |
| 3024 | OPC_CheckPredicate, 10, // 5159: check predicate 10 |
| 3025 | OPC_Decode, 202, 6, 122, // 5161: decode to Bcc using decoder 122 |
| 3026 | // 5161: } |
| 3027 | 1, 0, // 5165: case 0x1: { |
| 3028 | OPC_Scope, 10, // 5167: try { |
| 3029 | OPC_CheckField, 28, 4, 14, // 5169: check Inst[31:28] == 0xe |
| 3030 | OPC_CheckPredicate, 10, // 5173: check predicate 10 |
| 3031 | OPC_Decode, 193, 6, 122, // 5175: decode to BL using decoder 122 |
| 3032 | // 5175: } else try { |
| 3033 | OPC_CheckPredicate, 10, // 5179: check predicate 10 |
| 3034 | OPC_Decode, 197, 6, 122, // 5181: decode to BL_pred using decoder 122 |
| 3035 | // 5181: } |
| 3036 | // 5181: } |
| 3037 | // 5181: } // switch Inst[24] |
| 3038 | // 5181: } else try { |
| 3039 | OPC_CheckPredicate, 21, // 5185: check predicate 21 |
| 3040 | OPC_CheckField, 28, 4, 15, // 5187: check Inst[31:28] == 0xf |
| 3041 | OPC_Decode, 196, 6, 123, // 5191: decode to BLXi using decoder 123 |
| 3042 | // 5191: } |
| 3043 | // 5191: } |
| 3044 | 6, 43, // 5195: case 0x6: { |
| 3045 | OPC_SwitchField, 20, 5, // 5197: switch Inst[24:20] { |
| 3046 | 4, 18, // 5200: case 0x4: { |
| 3047 | OPC_Scope, 10, // 5202: try { |
| 3048 | OPC_CheckField, 28, 4, 15, // 5204: check Inst[31:28] == 0xf |
| 3049 | OPC_CheckPredicate, 14, // 5208: check predicate 14 |
| 3050 | OPC_Decode, 221, 7, 124, // 5210: decode to MCRR2 using decoder 124 |
| 3051 | // 5210: } else try { |
| 3052 | OPC_CheckPredicate, 10, // 5214: check predicate 10 |
| 3053 | OPC_Decode, 220, 7, 125, // 5216: decode to MCRR using decoder 125 |
| 3054 | // 5216: } |
| 3055 | // 5216: } |
| 3056 | 5, 0, // 5220: case 0x5: { |
| 3057 | OPC_Scope, 10, // 5222: try { |
| 3058 | OPC_CheckField, 28, 4, 15, // 5224: check Inst[31:28] == 0xf |
| 3059 | OPC_CheckPredicate, 14, // 5228: check predicate 14 |
| 3060 | OPC_Decode, 235, 7, 124, // 5230: decode to MRRC2 using decoder 124 |
| 3061 | // 5230: } else try { |
| 3062 | OPC_CheckPredicate, 10, // 5234: check predicate 10 |
| 3063 | OPC_Decode, 234, 7, 126, // 5236: decode to MRRC using decoder 126 |
| 3064 | // 5236: } |
| 3065 | // 5236: } |
| 3066 | // 5236: } // switch Inst[24:20] |
| 3067 | // 5236: } |
| 3068 | 7, 0, // 5240: case 0x7: { |
| 3069 | OPC_CheckPredicate, 10, // 5242: check predicate 10 |
| 3070 | OPC_CheckField, 24, 1, 1, // 5244: check Inst[24] == 0x1 |
| 3071 | OPC_Decode, 128, 16, 127, // 5248: decode to SVC using decoder 127 |
| 3072 | // 5248: } |
| 3073 | // 5248: } // switch Inst[27:25] |
| 3074 | }; |
| 3075 | static const uint8_t DecoderTableCoProc32[459] = { |
| 3076 | OPC_SwitchField, 24, 4, // 0: switch Inst[27:24] { |
| 3077 | 12, 195, 1, // 3: case 0xc: { |
| 3078 | OPC_SwitchField, 20, 3, // 6: switch Inst[22:20] { |
| 3079 | 0, 24, // 9: case 0x0: { |
| 3080 | OPC_CheckField, 23, 1, 1, // 11: check Inst[23] == 0x1 |
| 3081 | OPC_Scope, 11, // 15: try { |
| 3082 | OPC_CheckField, 28, 4, 15, // 17: check Inst[31:28] == 0xf |
| 3083 | OPC_CheckPredicate, 14, // 21: check predicate 14 |
| 3084 | OPC_Decode, 198, 15, 128, 1, // 23: decode to STC2_OPTION using decoder 128 |
| 3085 | // 23: } else try { |
| 3086 | OPC_CheckPredicate, 10, // 28: check predicate 10 |
| 3087 | OPC_Decode, 206, 15, 128, 1, // 30: decode to STC_OPTION using decoder 128 |
| 3088 | // 30: } |
| 3089 | // 30: } |
| 3090 | 1, 24, // 35: case 0x1: { |
| 3091 | OPC_CheckField, 23, 1, 1, // 37: check Inst[23] == 0x1 |
| 3092 | OPC_Scope, 11, // 41: try { |
| 3093 | OPC_CheckField, 28, 4, 15, // 43: check Inst[31:28] == 0xf |
| 3094 | OPC_CheckPredicate, 14, // 47: check predicate 14 |
| 3095 | OPC_Decode, 160, 7, 128, 1, // 49: decode to LDC2_OPTION using decoder 128 |
| 3096 | // 49: } else try { |
| 3097 | OPC_CheckPredicate, 10, // 54: check predicate 10 |
| 3098 | OPC_Decode, 168, 7, 128, 1, // 56: decode to LDC_OPTION using decoder 128 |
| 3099 | // 56: } |
| 3100 | // 56: } |
| 3101 | 2, 20, // 61: case 0x2: { |
| 3102 | OPC_Scope, 11, // 63: try { |
| 3103 | OPC_CheckField, 28, 4, 15, // 65: check Inst[31:28] == 0xf |
| 3104 | OPC_CheckPredicate, 14, // 69: check predicate 14 |
| 3105 | OPC_Decode, 199, 15, 128, 1, // 71: decode to STC2_POST using decoder 128 |
| 3106 | // 71: } else try { |
| 3107 | OPC_CheckPredicate, 10, // 76: check predicate 10 |
| 3108 | OPC_Decode, 207, 15, 128, 1, // 78: decode to STC_POST using decoder 128 |
| 3109 | // 78: } |
| 3110 | // 78: } |
| 3111 | 3, 20, // 83: case 0x3: { |
| 3112 | OPC_Scope, 11, // 85: try { |
| 3113 | OPC_CheckField, 28, 4, 15, // 87: check Inst[31:28] == 0xf |
| 3114 | OPC_CheckPredicate, 14, // 91: check predicate 14 |
| 3115 | OPC_Decode, 161, 7, 128, 1, // 93: decode to LDC2_POST using decoder 128 |
| 3116 | // 93: } else try { |
| 3117 | OPC_CheckPredicate, 10, // 98: check predicate 10 |
| 3118 | OPC_Decode, 169, 7, 128, 1, // 100: decode to LDC_POST using decoder 128 |
| 3119 | // 100: } |
| 3120 | // 100: } |
| 3121 | 4, 24, // 105: case 0x4: { |
| 3122 | OPC_CheckField, 23, 1, 1, // 107: check Inst[23] == 0x1 |
| 3123 | OPC_Scope, 11, // 111: try { |
| 3124 | OPC_CheckField, 28, 4, 15, // 113: check Inst[31:28] == 0xf |
| 3125 | OPC_CheckPredicate, 14, // 117: check predicate 14 |
| 3126 | OPC_Decode, 194, 15, 128, 1, // 119: decode to STC2L_OPTION using decoder 128 |
| 3127 | // 119: } else try { |
| 3128 | OPC_CheckPredicate, 10, // 124: check predicate 10 |
| 3129 | OPC_Decode, 202, 15, 128, 1, // 126: decode to STCL_OPTION using decoder 128 |
| 3130 | // 126: } |
| 3131 | // 126: } |
| 3132 | 5, 24, // 131: case 0x5: { |
| 3133 | OPC_CheckField, 23, 1, 1, // 133: check Inst[23] == 0x1 |
| 3134 | OPC_Scope, 11, // 137: try { |
| 3135 | OPC_CheckField, 28, 4, 15, // 139: check Inst[31:28] == 0xf |
| 3136 | OPC_CheckPredicate, 14, // 143: check predicate 14 |
| 3137 | OPC_Decode, 156, 7, 128, 1, // 145: decode to LDC2L_OPTION using decoder 128 |
| 3138 | // 145: } else try { |
| 3139 | OPC_CheckPredicate, 10, // 150: check predicate 10 |
| 3140 | OPC_Decode, 164, 7, 128, 1, // 152: decode to LDCL_OPTION using decoder 128 |
| 3141 | // 152: } |
| 3142 | // 152: } |
| 3143 | 6, 20, // 157: case 0x6: { |
| 3144 | OPC_Scope, 11, // 159: try { |
| 3145 | OPC_CheckField, 28, 4, 15, // 161: check Inst[31:28] == 0xf |
| 3146 | OPC_CheckPredicate, 14, // 165: check predicate 14 |
| 3147 | OPC_Decode, 195, 15, 128, 1, // 167: decode to STC2L_POST using decoder 128 |
| 3148 | // 167: } else try { |
| 3149 | OPC_CheckPredicate, 10, // 172: check predicate 10 |
| 3150 | OPC_Decode, 203, 15, 128, 1, // 174: decode to STCL_POST using decoder 128 |
| 3151 | // 174: } |
| 3152 | // 174: } |
| 3153 | 7, 0, // 179: case 0x7: { |
| 3154 | OPC_Scope, 11, // 181: try { |
| 3155 | OPC_CheckField, 28, 4, 15, // 183: check Inst[31:28] == 0xf |
| 3156 | OPC_CheckPredicate, 14, // 187: check predicate 14 |
| 3157 | OPC_Decode, 157, 7, 128, 1, // 189: decode to LDC2L_POST using decoder 128 |
| 3158 | // 189: } else try { |
| 3159 | OPC_CheckPredicate, 10, // 194: check predicate 10 |
| 3160 | OPC_Decode, 165, 7, 128, 1, // 196: decode to LDCL_POST using decoder 128 |
| 3161 | // 196: } |
| 3162 | // 196: } |
| 3163 | // 196: } // switch Inst[22:20] |
| 3164 | // 196: } |
| 3165 | 13, 179, 1, // 201: case 0xd: { |
| 3166 | OPC_SwitchField, 20, 3, // 204: switch Inst[22:20] { |
| 3167 | 0, 20, // 207: case 0x0: { |
| 3168 | OPC_Scope, 11, // 209: try { |
| 3169 | OPC_CheckField, 28, 4, 15, // 211: check Inst[31:28] == 0xf |
| 3170 | OPC_CheckPredicate, 14, // 215: check predicate 14 |
| 3171 | OPC_Decode, 197, 15, 128, 1, // 217: decode to STC2_OFFSET using decoder 128 |
| 3172 | // 217: } else try { |
| 3173 | OPC_CheckPredicate, 10, // 222: check predicate 10 |
| 3174 | OPC_Decode, 205, 15, 128, 1, // 224: decode to STC_OFFSET using decoder 128 |
| 3175 | // 224: } |
| 3176 | // 224: } |
| 3177 | 1, 20, // 229: case 0x1: { |
| 3178 | OPC_Scope, 11, // 231: try { |
| 3179 | OPC_CheckField, 28, 4, 15, // 233: check Inst[31:28] == 0xf |
| 3180 | OPC_CheckPredicate, 14, // 237: check predicate 14 |
| 3181 | OPC_Decode, 159, 7, 128, 1, // 239: decode to LDC2_OFFSET using decoder 128 |
| 3182 | // 239: } else try { |
| 3183 | OPC_CheckPredicate, 10, // 244: check predicate 10 |
| 3184 | OPC_Decode, 167, 7, 128, 1, // 246: decode to LDC_OFFSET using decoder 128 |
| 3185 | // 246: } |
| 3186 | // 246: } |
| 3187 | 2, 20, // 251: case 0x2: { |
| 3188 | OPC_Scope, 11, // 253: try { |
| 3189 | OPC_CheckField, 28, 4, 15, // 255: check Inst[31:28] == 0xf |
| 3190 | OPC_CheckPredicate, 14, // 259: check predicate 14 |
| 3191 | OPC_Decode, 200, 15, 128, 1, // 261: decode to STC2_PRE using decoder 128 |
| 3192 | // 261: } else try { |
| 3193 | OPC_CheckPredicate, 10, // 266: check predicate 10 |
| 3194 | OPC_Decode, 208, 15, 128, 1, // 268: decode to STC_PRE using decoder 128 |
| 3195 | // 268: } |
| 3196 | // 268: } |
| 3197 | 3, 20, // 273: case 0x3: { |
| 3198 | OPC_Scope, 11, // 275: try { |
| 3199 | OPC_CheckField, 28, 4, 15, // 277: check Inst[31:28] == 0xf |
| 3200 | OPC_CheckPredicate, 14, // 281: check predicate 14 |
| 3201 | OPC_Decode, 162, 7, 128, 1, // 283: decode to LDC2_PRE using decoder 128 |
| 3202 | // 283: } else try { |
| 3203 | OPC_CheckPredicate, 10, // 288: check predicate 10 |
| 3204 | OPC_Decode, 170, 7, 128, 1, // 290: decode to LDC_PRE using decoder 128 |
| 3205 | // 290: } |
| 3206 | // 290: } |
| 3207 | 4, 20, // 295: case 0x4: { |
| 3208 | OPC_Scope, 11, // 297: try { |
| 3209 | OPC_CheckField, 28, 4, 15, // 299: check Inst[31:28] == 0xf |
| 3210 | OPC_CheckPredicate, 14, // 303: check predicate 14 |
| 3211 | OPC_Decode, 193, 15, 128, 1, // 305: decode to STC2L_OFFSET using decoder 128 |
| 3212 | // 305: } else try { |
| 3213 | OPC_CheckPredicate, 10, // 310: check predicate 10 |
| 3214 | OPC_Decode, 201, 15, 128, 1, // 312: decode to STCL_OFFSET using decoder 128 |
| 3215 | // 312: } |
| 3216 | // 312: } |
| 3217 | 5, 20, // 317: case 0x5: { |
| 3218 | OPC_Scope, 11, // 319: try { |
| 3219 | OPC_CheckField, 28, 4, 15, // 321: check Inst[31:28] == 0xf |
| 3220 | OPC_CheckPredicate, 14, // 325: check predicate 14 |
| 3221 | OPC_Decode, 155, 7, 128, 1, // 327: decode to LDC2L_OFFSET using decoder 128 |
| 3222 | // 327: } else try { |
| 3223 | OPC_CheckPredicate, 10, // 332: check predicate 10 |
| 3224 | OPC_Decode, 163, 7, 128, 1, // 334: decode to LDCL_OFFSET using decoder 128 |
| 3225 | // 334: } |
| 3226 | // 334: } |
| 3227 | 6, 20, // 339: case 0x6: { |
| 3228 | OPC_Scope, 11, // 341: try { |
| 3229 | OPC_CheckField, 28, 4, 15, // 343: check Inst[31:28] == 0xf |
| 3230 | OPC_CheckPredicate, 14, // 347: check predicate 14 |
| 3231 | OPC_Decode, 196, 15, 128, 1, // 349: decode to STC2L_PRE using decoder 128 |
| 3232 | // 349: } else try { |
| 3233 | OPC_CheckPredicate, 10, // 354: check predicate 10 |
| 3234 | OPC_Decode, 204, 15, 128, 1, // 356: decode to STCL_PRE using decoder 128 |
| 3235 | // 356: } |
| 3236 | // 356: } |
| 3237 | 7, 0, // 361: case 0x7: { |
| 3238 | OPC_Scope, 11, // 363: try { |
| 3239 | OPC_CheckField, 28, 4, 15, // 365: check Inst[31:28] == 0xf |
| 3240 | OPC_CheckPredicate, 14, // 369: check predicate 14 |
| 3241 | OPC_Decode, 158, 7, 128, 1, // 371: decode to LDC2L_PRE using decoder 128 |
| 3242 | // 371: } else try { |
| 3243 | OPC_CheckPredicate, 10, // 376: check predicate 10 |
| 3244 | OPC_Decode, 166, 7, 128, 1, // 378: decode to LDCL_PRE using decoder 128 |
| 3245 | // 378: } |
| 3246 | // 378: } |
| 3247 | // 378: } // switch Inst[22:20] |
| 3248 | // 378: } |
| 3249 | 14, 0, // 383: case 0xe: { |
| 3250 | OPC_SwitchField, 4, 1, // 385: switch Inst[4] { |
| 3251 | 0, 20, // 388: case 0x0: { |
| 3252 | OPC_Scope, 11, // 390: try { |
| 3253 | OPC_CheckField, 28, 4, 15, // 392: check Inst[31:28] == 0xf |
| 3254 | OPC_CheckPredicate, 14, // 396: check predicate 14 |
| 3255 | OPC_Decode, 234, 6, 129, 1, // 398: decode to CDP2 using decoder 129 |
| 3256 | // 398: } else try { |
| 3257 | OPC_CheckPredicate, 14, // 403: check predicate 14 |
| 3258 | OPC_Decode, 233, 6, 130, 1, // 405: decode to CDP using decoder 130 |
| 3259 | // 405: } |
| 3260 | // 405: } |
| 3261 | 1, 0, // 410: case 0x1: { |
| 3262 | OPC_SwitchField, 20, 1, // 412: switch Inst[20] { |
| 3263 | 0, 20, // 415: case 0x0: { |
| 3264 | OPC_Scope, 11, // 417: try { |
| 3265 | OPC_CheckField, 28, 4, 15, // 419: check Inst[31:28] == 0xf |
| 3266 | OPC_CheckPredicate, 14, // 423: check predicate 14 |
| 3267 | OPC_Decode, 219, 7, 131, 1, // 425: decode to MCR2 using decoder 131 |
| 3268 | // 425: } else try { |
| 3269 | OPC_CheckPredicate, 10, // 430: check predicate 10 |
| 3270 | OPC_Decode, 218, 7, 132, 1, // 432: decode to MCR using decoder 132 |
| 3271 | // 432: } |
| 3272 | // 432: } |
| 3273 | 1, 0, // 437: case 0x1: { |
| 3274 | OPC_Scope, 11, // 439: try { |
| 3275 | OPC_CheckField, 28, 4, 15, // 441: check Inst[31:28] == 0xf |
| 3276 | OPC_CheckPredicate, 14, // 445: check predicate 14 |
| 3277 | OPC_Decode, 233, 7, 133, 1, // 447: decode to MRC2 using decoder 133 |
| 3278 | // 447: } else try { |
| 3279 | OPC_CheckPredicate, 10, // 452: check predicate 10 |
| 3280 | OPC_Decode, 232, 7, 134, 1, // 454: decode to MRC using decoder 134 |
| 3281 | // 454: } |
| 3282 | // 454: } |
| 3283 | // 454: } // switch Inst[20] |
| 3284 | // 454: } |
| 3285 | // 454: } // switch Inst[4] |
| 3286 | // 454: } |
| 3287 | // 454: } // switch Inst[27:24] |
| 3288 | }; |
| 3289 | static const uint8_t DecoderTableMVE32[15451] = { |
| 3290 | OPC_SwitchField, 25, 3, // 0: switch Inst[27:25] { |
| 3291 | 0, 87, // 3: case 0x0: { |
| 3292 | OPC_SwitchField, 20, 5, // 5: switch Inst[24:20] { |
| 3293 | 0, 19, // 8: case 0x0: { |
| 3294 | OPC_CheckPredicate, 31, // 10: check predicate 31 |
| 3295 | OPC_CheckField, 28, 4, 15, // 12: check Inst[31:28] == 0xf |
| 3296 | OPC_CheckField, 11, 5, 29, // 16: check Inst[15:11] == 0x1d |
| 3297 | OPC_SoftFail, 254, 15, 1, // 20: softfail pos=0x000007fe neg=0x00000001 |
| 3298 | OPC_Decode, 232, 8, 135, 1, // 24: decode to MVE_VCTP8 using decoder 135 |
| 3299 | // 24: } |
| 3300 | 1, 19, // 29: case 0x1: { |
| 3301 | OPC_CheckPredicate, 31, // 31: check predicate 31 |
| 3302 | OPC_CheckField, 28, 4, 15, // 33: check Inst[31:28] == 0xf |
| 3303 | OPC_CheckField, 11, 5, 29, // 37: check Inst[15:11] == 0x1d |
| 3304 | OPC_SoftFail, 254, 15, 1, // 41: softfail pos=0x000007fe neg=0x00000001 |
| 3305 | OPC_Decode, 229, 8, 135, 1, // 45: decode to MVE_VCTP16 using decoder 135 |
| 3306 | // 45: } |
| 3307 | 2, 19, // 50: case 0x2: { |
| 3308 | OPC_CheckPredicate, 31, // 52: check predicate 31 |
| 3309 | OPC_CheckField, 28, 4, 15, // 54: check Inst[31:28] == 0xf |
| 3310 | OPC_CheckField, 11, 5, 29, // 58: check Inst[15:11] == 0x1d |
| 3311 | OPC_SoftFail, 254, 15, 1, // 62: softfail pos=0x000007fe neg=0x00000001 |
| 3312 | OPC_Decode, 230, 8, 135, 1, // 66: decode to MVE_VCTP32 using decoder 135 |
| 3313 | // 66: } |
| 3314 | 3, 0, // 71: case 0x3: { |
| 3315 | OPC_CheckPredicate, 31, // 73: check predicate 31 |
| 3316 | OPC_CheckField, 28, 4, 15, // 75: check Inst[31:28] == 0xf |
| 3317 | OPC_CheckField, 11, 5, 29, // 79: check Inst[15:11] == 0x1d |
| 3318 | OPC_SoftFail, 254, 15, 1, // 83: softfail pos=0x000007fe neg=0x00000001 |
| 3319 | OPC_Decode, 231, 8, 135, 1, // 87: decode to MVE_VCTP64 using decoder 135 |
| 3320 | // 87: } |
| 3321 | // 87: } // switch Inst[24:20] |
| 3322 | // 87: } |
| 3323 | 5, 192, 2, // 92: case 0x5: { |
| 3324 | OPC_SwitchField, 0, 6, // 95: switch Inst[5:0] { |
| 3325 | 13, 59, // 98: case 0xd: { |
| 3326 | OPC_CheckField, 20, 5, 5, // 100: check Inst[24:20] == 0x5 |
| 3327 | OPC_CheckField, 28, 4, 14, // 104: check Inst[31:28] == 0xe |
| 3328 | OPC_Scope, 33, // 108: try { |
| 3329 | OPC_SwitchField, 16, 1, // 110: switch Inst[16] { |
| 3330 | 0, 11, // 113: case 0x0: { |
| 3331 | OPC_CheckPredicate, 32, // 115: check predicate 32 |
| 3332 | OPC_CheckField, 6, 3, 4, // 117: check Inst[8:6] == 0x4 |
| 3333 | OPC_Decode, 252, 7, 136, 1, // 121: decode to MVE_LSLLr using decoder 136 |
| 3334 | // 121: } |
| 3335 | 1, 0, // 126: case 0x1: { |
| 3336 | OPC_CheckPredicate, 32, // 128: check predicate 32 |
| 3337 | OPC_CheckField, 8, 1, 1, // 130: check Inst[8] == 0x1 |
| 3338 | OPC_CheckField, 6, 1, 0, // 134: check Inst[6] == 0x0 |
| 3339 | OPC_Decode, 133, 8, 136, 1, // 138: decode to MVE_UQRSHLL using decoder 136 |
| 3340 | // 138: } |
| 3341 | // 138: } // switch Inst[16] |
| 3342 | // 138: } else try { |
| 3343 | OPC_CheckPredicate, 32, // 143: check predicate 32 |
| 3344 | OPC_CheckField, 9, 3, 7, // 145: check Inst[11:9] == 0x7 |
| 3345 | OPC_SoftFail, 192, 1, 128, 2, // 149: softfail pos=0x000000c0 neg=0x00000100 |
| 3346 | OPC_Decode, 132, 8, 137, 1, // 154: decode to MVE_UQRSHL using decoder 137 |
| 3347 | // 154: } |
| 3348 | // 154: } |
| 3349 | 15, 49, // 159: case 0xf: { |
| 3350 | OPC_CheckField, 8, 1, 1, // 161: check Inst[8] == 0x1 |
| 3351 | OPC_CheckField, 15, 1, 0, // 165: check Inst[15] == 0x0 |
| 3352 | OPC_CheckField, 20, 5, 5, // 169: check Inst[24:20] == 0x5 |
| 3353 | OPC_CheckField, 28, 4, 14, // 173: check Inst[31:28] == 0xe |
| 3354 | OPC_Scope, 11, // 177: try { |
| 3355 | OPC_CheckField, 9, 3, 7, // 179: check Inst[11:9] == 0x7 |
| 3356 | OPC_CheckPredicate, 32, // 183: check predicate 32 |
| 3357 | OPC_Decode, 134, 8, 138, 1, // 185: decode to MVE_UQSHL using decoder 138 |
| 3358 | OPC_Scope, 11, // 190: } else try { |
| 3359 | OPC_CheckField, 16, 1, 1, // 192: check Inst[16] == 0x1 |
| 3360 | OPC_CheckPredicate, 32, // 196: check predicate 32 |
| 3361 | OPC_Decode, 135, 8, 139, 1, // 198: decode to MVE_UQSHLL using decoder 139 |
| 3362 | // 198: } else try { |
| 3363 | OPC_CheckPredicate, 32, // 203: check predicate 32 |
| 3364 | OPC_Decode, 251, 7, 139, 1, // 205: decode to MVE_LSLLi using decoder 139 |
| 3365 | // 205: } |
| 3366 | // 205: } |
| 3367 | 31, 49, // 210: case 0x1f: { |
| 3368 | OPC_CheckField, 8, 1, 1, // 212: check Inst[8] == 0x1 |
| 3369 | OPC_CheckField, 15, 1, 0, // 216: check Inst[15] == 0x0 |
| 3370 | OPC_CheckField, 20, 5, 5, // 220: check Inst[24:20] == 0x5 |
| 3371 | OPC_CheckField, 28, 4, 14, // 224: check Inst[31:28] == 0xe |
| 3372 | OPC_Scope, 11, // 228: try { |
| 3373 | OPC_CheckField, 9, 3, 7, // 230: check Inst[11:9] == 0x7 |
| 3374 | OPC_CheckPredicate, 32, // 234: check predicate 32 |
| 3375 | OPC_Decode, 136, 8, 138, 1, // 236: decode to MVE_URSHR using decoder 138 |
| 3376 | OPC_Scope, 11, // 241: } else try { |
| 3377 | OPC_CheckField, 16, 1, 1, // 243: check Inst[16] == 0x1 |
| 3378 | OPC_CheckPredicate, 32, // 247: check predicate 32 |
| 3379 | OPC_Decode, 137, 8, 139, 1, // 249: decode to MVE_URSHRL using decoder 139 |
| 3380 | // 249: } else try { |
| 3381 | OPC_CheckPredicate, 32, // 254: check predicate 32 |
| 3382 | OPC_Decode, 253, 7, 139, 1, // 256: decode to MVE_LSRL using decoder 139 |
| 3383 | // 256: } |
| 3384 | // 256: } |
| 3385 | 45, 59, // 261: case 0x2d: { |
| 3386 | OPC_CheckField, 20, 5, 5, // 263: check Inst[24:20] == 0x5 |
| 3387 | OPC_CheckField, 28, 4, 14, // 267: check Inst[31:28] == 0xe |
| 3388 | OPC_Scope, 33, // 271: try { |
| 3389 | OPC_SwitchField, 16, 1, // 273: switch Inst[16] { |
| 3390 | 0, 11, // 276: case 0x0: { |
| 3391 | OPC_CheckPredicate, 32, // 278: check predicate 32 |
| 3392 | OPC_CheckField, 6, 3, 4, // 280: check Inst[8:6] == 0x4 |
| 3393 | OPC_Decode, 244, 7, 136, 1, // 284: decode to MVE_ASRLr using decoder 136 |
| 3394 | // 284: } |
| 3395 | 1, 0, // 289: case 0x1: { |
| 3396 | OPC_CheckPredicate, 32, // 291: check predicate 32 |
| 3397 | OPC_CheckField, 8, 1, 1, // 293: check Inst[8] == 0x1 |
| 3398 | OPC_CheckField, 6, 1, 0, // 297: check Inst[6] == 0x0 |
| 3399 | OPC_Decode, 255, 7, 136, 1, // 301: decode to MVE_SQRSHRL using decoder 136 |
| 3400 | // 301: } |
| 3401 | // 301: } // switch Inst[16] |
| 3402 | // 301: } else try { |
| 3403 | OPC_CheckPredicate, 32, // 306: check predicate 32 |
| 3404 | OPC_CheckField, 9, 3, 7, // 308: check Inst[11:9] == 0x7 |
| 3405 | OPC_SoftFail, 192, 1, 128, 2, // 312: softfail pos=0x000000c0 neg=0x00000100 |
| 3406 | OPC_Decode, 254, 7, 137, 1, // 317: decode to MVE_SQRSHR using decoder 137 |
| 3407 | // 317: } |
| 3408 | // 317: } |
| 3409 | 47, 49, // 322: case 0x2f: { |
| 3410 | OPC_CheckField, 8, 1, 1, // 324: check Inst[8] == 0x1 |
| 3411 | OPC_CheckField, 15, 1, 0, // 328: check Inst[15] == 0x0 |
| 3412 | OPC_CheckField, 20, 5, 5, // 332: check Inst[24:20] == 0x5 |
| 3413 | OPC_CheckField, 28, 4, 14, // 336: check Inst[31:28] == 0xe |
| 3414 | OPC_Scope, 11, // 340: try { |
| 3415 | OPC_CheckField, 9, 3, 7, // 342: check Inst[11:9] == 0x7 |
| 3416 | OPC_CheckPredicate, 32, // 346: check predicate 32 |
| 3417 | OPC_Decode, 130, 8, 138, 1, // 348: decode to MVE_SRSHR using decoder 138 |
| 3418 | OPC_Scope, 11, // 353: } else try { |
| 3419 | OPC_CheckField, 16, 1, 1, // 355: check Inst[16] == 0x1 |
| 3420 | OPC_CheckPredicate, 32, // 359: check predicate 32 |
| 3421 | OPC_Decode, 131, 8, 139, 1, // 361: decode to MVE_SRSHRL using decoder 139 |
| 3422 | // 361: } else try { |
| 3423 | OPC_CheckPredicate, 32, // 366: check predicate 32 |
| 3424 | OPC_Decode, 243, 7, 139, 1, // 368: decode to MVE_ASRLi using decoder 139 |
| 3425 | // 368: } |
| 3426 | // 368: } |
| 3427 | 63, 0, // 373: case 0x3f: { |
| 3428 | OPC_CheckField, 8, 1, 1, // 375: check Inst[8] == 0x1 |
| 3429 | OPC_CheckField, 15, 1, 0, // 379: check Inst[15] == 0x0 |
| 3430 | OPC_CheckField, 20, 5, 5, // 383: check Inst[24:20] == 0x5 |
| 3431 | OPC_CheckField, 28, 4, 14, // 387: check Inst[31:28] == 0xe |
| 3432 | OPC_Scope, 11, // 391: try { |
| 3433 | OPC_CheckField, 9, 3, 7, // 393: check Inst[11:9] == 0x7 |
| 3434 | OPC_CheckPredicate, 32, // 397: check predicate 32 |
| 3435 | OPC_Decode, 128, 8, 138, 1, // 399: decode to MVE_SQSHL using decoder 138 |
| 3436 | // 399: } else try { |
| 3437 | OPC_CheckPredicate, 32, // 404: check predicate 32 |
| 3438 | OPC_CheckField, 16, 1, 1, // 406: check Inst[16] == 0x1 |
| 3439 | OPC_Decode, 129, 8, 139, 1, // 410: decode to MVE_SQSHLL using decoder 139 |
| 3440 | // 410: } |
| 3441 | // 410: } |
| 3442 | // 410: } // switch Inst[5:0] |
| 3443 | // 410: } |
| 3444 | 6, 164, 23, // 415: case 0x6: { |
| 3445 | OPC_SwitchField, 8, 5, // 418: switch Inst[12:8] { |
| 3446 | 8, 127, // 421: case 0x8: { |
| 3447 | OPC_SwitchField, 20, 2, // 423: switch Inst[21:20] { |
| 3448 | 0, 31, // 426: case 0x0: { |
| 3449 | OPC_CheckPredicate, 33, // 428: check predicate 33 |
| 3450 | OPC_CheckField, 28, 4, 15, // 430: check Inst[31:28] == 0xf |
| 3451 | OPC_CheckField, 23, 1, 1, // 434: check Inst[23] == 0x1 |
| 3452 | OPC_CheckField, 16, 1, 0, // 438: check Inst[16] == 0x0 |
| 3453 | OPC_CheckField, 6, 1, 1, // 442: check Inst[6] == 0x1 |
| 3454 | OPC_CheckField, 4, 1, 0, // 446: check Inst[4] == 0x0 |
| 3455 | OPC_CheckField, 0, 1, 0, // 450: check Inst[0] == 0x0 |
| 3456 | OPC_Decode, 192, 8, 140, 1, // 454: decode to MVE_VCADDf16 using decoder 140 |
| 3457 | // 454: } |
| 3458 | 1, 31, // 459: case 0x1: { |
| 3459 | OPC_CheckPredicate, 33, // 461: check predicate 33 |
| 3460 | OPC_CheckField, 28, 4, 15, // 463: check Inst[31:28] == 0xf |
| 3461 | OPC_CheckField, 23, 1, 1, // 467: check Inst[23] == 0x1 |
| 3462 | OPC_CheckField, 16, 1, 0, // 471: check Inst[16] == 0x0 |
| 3463 | OPC_CheckField, 6, 1, 1, // 475: check Inst[6] == 0x1 |
| 3464 | OPC_CheckField, 4, 1, 0, // 479: check Inst[4] == 0x0 |
| 3465 | OPC_CheckField, 0, 1, 0, // 483: check Inst[0] == 0x0 |
| 3466 | OPC_Decode, 193, 8, 140, 1, // 487: decode to MVE_VCADDf32 using decoder 140 |
| 3467 | // 487: } |
| 3468 | 2, 27, // 492: case 0x2: { |
| 3469 | OPC_CheckPredicate, 33, // 494: check predicate 33 |
| 3470 | OPC_CheckField, 28, 4, 15, // 496: check Inst[31:28] == 0xf |
| 3471 | OPC_CheckField, 16, 1, 0, // 500: check Inst[16] == 0x0 |
| 3472 | OPC_CheckField, 6, 1, 1, // 504: check Inst[6] == 0x1 |
| 3473 | OPC_CheckField, 4, 1, 0, // 508: check Inst[4] == 0x0 |
| 3474 | OPC_CheckField, 0, 1, 0, // 512: check Inst[0] == 0x0 |
| 3475 | OPC_Decode, 203, 8, 141, 1, // 516: decode to MVE_VCMLAf16 using decoder 141 |
| 3476 | // 516: } |
| 3477 | 3, 0, // 521: case 0x3: { |
| 3478 | OPC_CheckPredicate, 33, // 523: check predicate 33 |
| 3479 | OPC_CheckField, 28, 4, 15, // 525: check Inst[31:28] == 0xf |
| 3480 | OPC_CheckField, 16, 1, 0, // 529: check Inst[16] == 0x0 |
| 3481 | OPC_CheckField, 6, 1, 1, // 533: check Inst[6] == 0x1 |
| 3482 | OPC_CheckField, 4, 1, 0, // 537: check Inst[4] == 0x0 |
| 3483 | OPC_CheckField, 0, 1, 0, // 541: check Inst[0] == 0x0 |
| 3484 | OPC_Decode, 204, 8, 141, 1, // 545: decode to MVE_VCMLAf32 using decoder 141 |
| 3485 | // 545: } |
| 3486 | // 545: } // switch Inst[21:20] |
| 3487 | // 545: } |
| 3488 | 14, 140, 3, // 550: case 0xe: { |
| 3489 | OPC_SwitchField, 20, 3, // 553: switch Inst[22:20] { |
| 3490 | 0, 115, // 556: case 0x0: { |
| 3491 | OPC_SwitchField, 7, 1, // 558: switch Inst[7] { |
| 3492 | 0, 23, // 561: case 0x0: { |
| 3493 | OPC_CheckPredicate, 31, // 563: check predicate 31 |
| 3494 | OPC_CheckField, 28, 4, 14, // 565: check Inst[31:28] == 0xe |
| 3495 | OPC_CheckField, 23, 2, 1, // 569: check Inst[24:23] == 0x1 |
| 3496 | OPC_CheckField, 4, 3, 0, // 573: check Inst[6:4] == 0x0 |
| 3497 | OPC_CheckField, 0, 1, 0, // 577: check Inst[0] == 0x0 |
| 3498 | OPC_Decode, 149, 14, 142, 1, // 581: decode to MVE_VSTRB8_rq using decoder 142 |
| 3499 | // 581: } |
| 3500 | 1, 0, // 586: case 0x1: { |
| 3501 | OPC_SwitchField, 24, 1, // 588: switch Inst[24] { |
| 3502 | 0, 63, // 591: case 0x0: { |
| 3503 | OPC_SwitchField, 0, 1, // 593: switch Inst[0] { |
| 3504 | 0, 37, // 596: case 0x0: { |
| 3505 | OPC_SwitchField, 4, 3, // 598: switch Inst[6:4] { |
| 3506 | 0, 15, // 601: case 0x0: { |
| 3507 | OPC_CheckPredicate, 31, // 603: check predicate 31 |
| 3508 | OPC_CheckField, 28, 4, 14, // 605: check Inst[31:28] == 0xe |
| 3509 | OPC_CheckField, 23, 1, 1, // 609: check Inst[23] == 0x1 |
| 3510 | OPC_Decode, 144, 14, 142, 1, // 613: decode to MVE_VSTRB16_rq using decoder 142 |
| 3511 | // 613: } |
| 3512 | 1, 0, // 618: case 0x1: { |
| 3513 | OPC_CheckPredicate, 31, // 620: check predicate 31 |
| 3514 | OPC_CheckField, 28, 4, 14, // 622: check Inst[31:28] == 0xe |
| 3515 | OPC_CheckField, 23, 1, 1, // 626: check Inst[23] == 0x1 |
| 3516 | OPC_Decode, 158, 14, 142, 1, // 630: decode to MVE_VSTRH16_rq_u using decoder 142 |
| 3517 | // 630: } |
| 3518 | // 630: } // switch Inst[6:4] |
| 3519 | // 630: } |
| 3520 | 1, 0, // 635: case 0x1: { |
| 3521 | OPC_CheckPredicate, 31, // 637: check predicate 31 |
| 3522 | OPC_CheckField, 28, 4, 14, // 639: check Inst[31:28] == 0xe |
| 3523 | OPC_CheckField, 23, 1, 1, // 643: check Inst[23] == 0x1 |
| 3524 | OPC_CheckField, 4, 3, 1, // 647: check Inst[6:4] == 0x1 |
| 3525 | OPC_Decode, 157, 14, 142, 1, // 651: decode to MVE_VSTRH16_rq using decoder 142 |
| 3526 | // 651: } |
| 3527 | // 651: } // switch Inst[0] |
| 3528 | // 651: } |
| 3529 | 1, 0, // 656: case 0x1: { |
| 3530 | OPC_CheckPredicate, 31, // 658: check predicate 31 |
| 3531 | OPC_CheckField, 28, 4, 14, // 660: check Inst[31:28] == 0xe |
| 3532 | OPC_CheckField, 19, 1, 0, // 664: check Inst[19] == 0x0 |
| 3533 | OPC_Decode, 141, 14, 143, 1, // 668: decode to MVE_VSTRB16 using decoder 143 |
| 3534 | // 668: } |
| 3535 | // 668: } // switch Inst[24] |
| 3536 | // 668: } |
| 3537 | // 668: } // switch Inst[7] |
| 3538 | // 668: } |
| 3539 | 1, 143, 1, // 673: case 0x1: { |
| 3540 | OPC_SwitchField, 7, 1, // 676: switch Inst[7] { |
| 3541 | 0, 23, // 679: case 0x0: { |
| 3542 | OPC_CheckPredicate, 31, // 681: check predicate 31 |
| 3543 | OPC_CheckField, 28, 4, 15, // 683: check Inst[31:28] == 0xf |
| 3544 | OPC_CheckField, 23, 2, 1, // 687: check Inst[24:23] == 0x1 |
| 3545 | OPC_CheckField, 4, 3, 0, // 691: check Inst[6:4] == 0x0 |
| 3546 | OPC_CheckField, 0, 1, 0, // 695: check Inst[0] == 0x0 |
| 3547 | OPC_Decode, 247, 9, 142, 1, // 699: decode to MVE_VLDRBU8_rq using decoder 142 |
| 3548 | // 699: } |
| 3549 | 1, 0, // 704: case 0x1: { |
| 3550 | OPC_SwitchField, 24, 1, // 706: switch Inst[24] { |
| 3551 | 0, 77, // 709: case 0x0: { |
| 3552 | OPC_SwitchField, 0, 1, // 711: switch Inst[0] { |
| 3553 | 0, 51, // 714: case 0x0: { |
| 3554 | OPC_SwitchField, 4, 3, // 716: switch Inst[6:4] { |
| 3555 | 0, 29, // 719: case 0x0: { |
| 3556 | OPC_SwitchField, 28, 4, // 721: switch Inst[31:28] { |
| 3557 | 14, 11, // 724: case 0xe: { |
| 3558 | OPC_CheckPredicate, 31, // 726: check predicate 31 |
| 3559 | OPC_CheckField, 23, 1, 1, // 728: check Inst[23] == 0x1 |
| 3560 | OPC_Decode, 231, 9, 142, 1, // 732: decode to MVE_VLDRBS16_rq using decoder 142 |
| 3561 | // 732: } |
| 3562 | 15, 0, // 737: case 0xf: { |
| 3563 | OPC_CheckPredicate, 31, // 739: check predicate 31 |
| 3564 | OPC_CheckField, 23, 1, 1, // 741: check Inst[23] == 0x1 |
| 3565 | OPC_Decode, 239, 9, 142, 1, // 745: decode to MVE_VLDRBU16_rq using decoder 142 |
| 3566 | // 745: } |
| 3567 | // 745: } // switch Inst[31:28] |
| 3568 | // 745: } |
| 3569 | 1, 0, // 750: case 0x1: { |
| 3570 | OPC_CheckPredicate, 31, // 752: check predicate 31 |
| 3571 | OPC_CheckField, 28, 4, 15, // 754: check Inst[31:28] == 0xf |
| 3572 | OPC_CheckField, 23, 1, 1, // 758: check Inst[23] == 0x1 |
| 3573 | OPC_Decode, 133, 10, 142, 1, // 762: decode to MVE_VLDRHU16_rq_u using decoder 142 |
| 3574 | // 762: } |
| 3575 | // 762: } // switch Inst[6:4] |
| 3576 | // 762: } |
| 3577 | 1, 0, // 767: case 0x1: { |
| 3578 | OPC_CheckPredicate, 31, // 769: check predicate 31 |
| 3579 | OPC_CheckField, 28, 4, 15, // 771: check Inst[31:28] == 0xf |
| 3580 | OPC_CheckField, 23, 1, 1, // 775: check Inst[23] == 0x1 |
| 3581 | OPC_CheckField, 4, 3, 1, // 779: check Inst[6:4] == 0x1 |
| 3582 | OPC_Decode, 132, 10, 142, 1, // 783: decode to MVE_VLDRHU16_rq using decoder 142 |
| 3583 | // 783: } |
| 3584 | // 783: } // switch Inst[0] |
| 3585 | // 783: } |
| 3586 | 1, 0, // 788: case 0x1: { |
| 3587 | OPC_SwitchField, 28, 4, // 790: switch Inst[31:28] { |
| 3588 | 14, 11, // 793: case 0xe: { |
| 3589 | OPC_CheckPredicate, 31, // 795: check predicate 31 |
| 3590 | OPC_CheckField, 19, 1, 0, // 797: check Inst[19] == 0x0 |
| 3591 | OPC_Decode, 228, 9, 143, 1, // 801: decode to MVE_VLDRBS16 using decoder 143 |
| 3592 | // 801: } |
| 3593 | 15, 0, // 806: case 0xf: { |
| 3594 | OPC_CheckPredicate, 31, // 808: check predicate 31 |
| 3595 | OPC_CheckField, 19, 1, 0, // 810: check Inst[19] == 0x0 |
| 3596 | OPC_Decode, 236, 9, 143, 1, // 814: decode to MVE_VLDRBU16 using decoder 143 |
| 3597 | // 814: } |
| 3598 | // 814: } // switch Inst[31:28] |
| 3599 | // 814: } |
| 3600 | // 814: } // switch Inst[24] |
| 3601 | // 814: } |
| 3602 | // 814: } // switch Inst[7] |
| 3603 | // 814: } |
| 3604 | 2, 45, // 819: case 0x2: { |
| 3605 | OPC_SwitchField, 24, 1, // 821: switch Inst[24] { |
| 3606 | 0, 19, // 824: case 0x0: { |
| 3607 | OPC_CheckPredicate, 31, // 826: check predicate 31 |
| 3608 | OPC_CheckField, 28, 4, 14, // 828: check Inst[31:28] == 0xe |
| 3609 | OPC_CheckField, 19, 1, 0, // 832: check Inst[19] == 0x0 |
| 3610 | OPC_CheckField, 7, 1, 1, // 836: check Inst[7] == 0x1 |
| 3611 | OPC_Decode, 142, 14, 144, 1, // 840: decode to MVE_VSTRB16_post using decoder 144 |
| 3612 | // 840: } |
| 3613 | 1, 0, // 845: case 0x1: { |
| 3614 | OPC_CheckPredicate, 31, // 847: check predicate 31 |
| 3615 | OPC_CheckField, 28, 4, 14, // 849: check Inst[31:28] == 0xe |
| 3616 | OPC_CheckField, 19, 1, 0, // 853: check Inst[19] == 0x0 |
| 3617 | OPC_CheckField, 7, 1, 1, // 857: check Inst[7] == 0x1 |
| 3618 | OPC_Decode, 143, 14, 145, 1, // 861: decode to MVE_VSTRB16_pre using decoder 145 |
| 3619 | // 861: } |
| 3620 | // 861: } // switch Inst[24] |
| 3621 | // 861: } |
| 3622 | 3, 0, // 866: case 0x3: { |
| 3623 | OPC_SwitchField, 24, 1, // 868: switch Inst[24] { |
| 3624 | 0, 37, // 871: case 0x0: { |
| 3625 | OPC_SwitchField, 28, 4, // 873: switch Inst[31:28] { |
| 3626 | 14, 15, // 876: case 0xe: { |
| 3627 | OPC_CheckPredicate, 31, // 878: check predicate 31 |
| 3628 | OPC_CheckField, 19, 1, 0, // 880: check Inst[19] == 0x0 |
| 3629 | OPC_CheckField, 7, 1, 1, // 884: check Inst[7] == 0x1 |
| 3630 | OPC_Decode, 229, 9, 144, 1, // 888: decode to MVE_VLDRBS16_post using decoder 144 |
| 3631 | // 888: } |
| 3632 | 15, 0, // 893: case 0xf: { |
| 3633 | OPC_CheckPredicate, 31, // 895: check predicate 31 |
| 3634 | OPC_CheckField, 19, 1, 0, // 897: check Inst[19] == 0x0 |
| 3635 | OPC_CheckField, 7, 1, 1, // 901: check Inst[7] == 0x1 |
| 3636 | OPC_Decode, 237, 9, 144, 1, // 905: decode to MVE_VLDRBU16_post using decoder 144 |
| 3637 | // 905: } |
| 3638 | // 905: } // switch Inst[31:28] |
| 3639 | // 905: } |
| 3640 | 1, 0, // 910: case 0x1: { |
| 3641 | OPC_SwitchField, 28, 4, // 912: switch Inst[31:28] { |
| 3642 | 14, 15, // 915: case 0xe: { |
| 3643 | OPC_CheckPredicate, 31, // 917: check predicate 31 |
| 3644 | OPC_CheckField, 19, 1, 0, // 919: check Inst[19] == 0x0 |
| 3645 | OPC_CheckField, 7, 1, 1, // 923: check Inst[7] == 0x1 |
| 3646 | OPC_Decode, 230, 9, 145, 1, // 927: decode to MVE_VLDRBS16_pre using decoder 145 |
| 3647 | // 927: } |
| 3648 | 15, 0, // 932: case 0xf: { |
| 3649 | OPC_CheckPredicate, 31, // 934: check predicate 31 |
| 3650 | OPC_CheckField, 19, 1, 0, // 936: check Inst[19] == 0x0 |
| 3651 | OPC_CheckField, 7, 1, 1, // 940: check Inst[7] == 0x1 |
| 3652 | OPC_Decode, 238, 9, 145, 1, // 944: decode to MVE_VLDRBU16_pre using decoder 145 |
| 3653 | // 944: } |
| 3654 | // 944: } // switch Inst[31:28] |
| 3655 | // 944: } |
| 3656 | // 944: } // switch Inst[24] |
| 3657 | // 944: } |
| 3658 | // 944: } // switch Inst[22:20] |
| 3659 | // 944: } |
| 3660 | 15, 175, 6, // 949: case 0xf: { |
| 3661 | OPC_SwitchField, 20, 2, // 952: switch Inst[21:20] { |
| 3662 | 0, 231, 1, // 955: case 0x0: { |
| 3663 | OPC_SwitchField, 7, 1, // 958: switch Inst[7] { |
| 3664 | 0, 178, 1, // 961: case 0x0: { |
| 3665 | OPC_SwitchField, 24, 1, // 964: switch Inst[24] { |
| 3666 | 0, 133, 1, // 967: case 0x0: { |
| 3667 | OPC_SwitchField, 5, 2, // 970: switch Inst[6:5] { |
| 3668 | 0, 81, // 973: case 0x0: { |
| 3669 | OPC_SwitchField, 23, 1, // 975: switch Inst[23] { |
| 3670 | 0, 11, // 978: case 0x0: { |
| 3671 | OPC_CheckPredicate, 32, // 980: check predicate 32 |
| 3672 | OPC_CheckField, 28, 4, 14, // 982: check Inst[31:28] == 0xe |
| 3673 | OPC_Decode, 144, 11, 146, 1, // 986: decode to MVE_VMOV_rr_q using decoder 146 |
| 3674 | // 986: } |
| 3675 | 1, 0, // 991: case 0x1: { |
| 3676 | OPC_SwitchField, 0, 1, // 993: switch Inst[0] { |
| 3677 | 0, 37, // 996: case 0x0: { |
| 3678 | OPC_SwitchField, 4, 1, // 998: switch Inst[4] { |
| 3679 | 0, 15, // 1001: case 0x0: { |
| 3680 | OPC_CheckPredicate, 31, // 1003: check predicate 31 |
| 3681 | OPC_CheckField, 28, 4, 14, // 1005: check Inst[31:28] == 0xe |
| 3682 | OPC_CheckField, 22, 1, 0, // 1009: check Inst[22] == 0x0 |
| 3683 | OPC_Decode, 148, 14, 142, 1, // 1013: decode to MVE_VSTRB32_rq using decoder 142 |
| 3684 | // 1013: } |
| 3685 | 1, 0, // 1018: case 0x1: { |
| 3686 | OPC_CheckPredicate, 31, // 1020: check predicate 31 |
| 3687 | OPC_CheckField, 28, 4, 14, // 1022: check Inst[31:28] == 0xe |
| 3688 | OPC_CheckField, 22, 1, 0, // 1026: check Inst[22] == 0x0 |
| 3689 | OPC_Decode, 163, 14, 142, 1, // 1030: decode to MVE_VSTRH32_rq_u using decoder 142 |
| 3690 | // 1030: } |
| 3691 | // 1030: } // switch Inst[4] |
| 3692 | // 1030: } |
| 3693 | 1, 0, // 1035: case 0x1: { |
| 3694 | OPC_CheckPredicate, 31, // 1037: check predicate 31 |
| 3695 | OPC_CheckField, 28, 4, 14, // 1039: check Inst[31:28] == 0xe |
| 3696 | OPC_CheckField, 22, 1, 0, // 1043: check Inst[22] == 0x0 |
| 3697 | OPC_CheckField, 4, 1, 1, // 1047: check Inst[4] == 0x1 |
| 3698 | OPC_Decode, 162, 14, 142, 1, // 1051: decode to MVE_VSTRH32_rq using decoder 142 |
| 3699 | // 1051: } |
| 3700 | // 1051: } // switch Inst[0] |
| 3701 | // 1051: } |
| 3702 | // 1051: } // switch Inst[23] |
| 3703 | // 1051: } |
| 3704 | 2, 0, // 1056: case 0x2: { |
| 3705 | OPC_SwitchField, 0, 1, // 1058: switch Inst[0] { |
| 3706 | 0, 19, // 1061: case 0x0: { |
| 3707 | OPC_CheckPredicate, 31, // 1063: check predicate 31 |
| 3708 | OPC_CheckField, 28, 4, 14, // 1065: check Inst[31:28] == 0xe |
| 3709 | OPC_CheckField, 22, 2, 2, // 1069: check Inst[23:22] == 0x2 |
| 3710 | OPC_CheckField, 4, 1, 0, // 1073: check Inst[4] == 0x0 |
| 3711 | OPC_Decode, 170, 14, 142, 1, // 1077: decode to MVE_VSTRW32_rq_u using decoder 142 |
| 3712 | // 1077: } |
| 3713 | 1, 0, // 1082: case 0x1: { |
| 3714 | OPC_CheckPredicate, 31, // 1084: check predicate 31 |
| 3715 | OPC_CheckField, 28, 4, 14, // 1086: check Inst[31:28] == 0xe |
| 3716 | OPC_CheckField, 22, 2, 2, // 1090: check Inst[23:22] == 0x2 |
| 3717 | OPC_CheckField, 4, 1, 0, // 1094: check Inst[4] == 0x0 |
| 3718 | OPC_Decode, 169, 14, 142, 1, // 1098: decode to MVE_VSTRW32_rq using decoder 142 |
| 3719 | // 1098: } |
| 3720 | // 1098: } // switch Inst[0] |
| 3721 | // 1098: } |
| 3722 | // 1098: } // switch Inst[6:5] |
| 3723 | // 1098: } |
| 3724 | 1, 0, // 1103: case 0x1: { |
| 3725 | OPC_SwitchField, 19, 1, // 1105: switch Inst[19] { |
| 3726 | 0, 15, // 1108: case 0x0: { |
| 3727 | OPC_CheckPredicate, 31, // 1110: check predicate 31 |
| 3728 | OPC_CheckField, 28, 4, 14, // 1112: check Inst[31:28] == 0xe |
| 3729 | OPC_CheckField, 22, 1, 0, // 1116: check Inst[22] == 0x0 |
| 3730 | OPC_Decode, 145, 14, 143, 1, // 1120: decode to MVE_VSTRB32 using decoder 143 |
| 3731 | // 1120: } |
| 3732 | 1, 0, // 1125: case 0x1: { |
| 3733 | OPC_CheckPredicate, 31, // 1127: check predicate 31 |
| 3734 | OPC_CheckField, 28, 4, 14, // 1129: check Inst[31:28] == 0xe |
| 3735 | OPC_CheckField, 22, 1, 0, // 1133: check Inst[22] == 0x0 |
| 3736 | OPC_Decode, 159, 14, 147, 1, // 1137: decode to MVE_VSTRH32 using decoder 147 |
| 3737 | // 1137: } |
| 3738 | // 1137: } // switch Inst[19] |
| 3739 | // 1137: } |
| 3740 | // 1137: } // switch Inst[24] |
| 3741 | // 1137: } |
| 3742 | 1, 0, // 1142: case 0x1: { |
| 3743 | OPC_SwitchField, 0, 1, // 1144: switch Inst[0] { |
| 3744 | 0, 19, // 1147: case 0x0: { |
| 3745 | OPC_CheckPredicate, 31, // 1149: check predicate 31 |
| 3746 | OPC_CheckField, 28, 4, 14, // 1151: check Inst[31:28] == 0xe |
| 3747 | OPC_CheckField, 22, 3, 2, // 1155: check Inst[24:22] == 0x2 |
| 3748 | OPC_CheckField, 4, 3, 5, // 1159: check Inst[6:4] == 0x5 |
| 3749 | OPC_Decode, 156, 14, 142, 1, // 1163: decode to MVE_VSTRD64_rq_u using decoder 142 |
| 3750 | // 1163: } |
| 3751 | 1, 0, // 1168: case 0x1: { |
| 3752 | OPC_CheckPredicate, 31, // 1170: check predicate 31 |
| 3753 | OPC_CheckField, 28, 4, 14, // 1172: check Inst[31:28] == 0xe |
| 3754 | OPC_CheckField, 22, 3, 2, // 1176: check Inst[24:22] == 0x2 |
| 3755 | OPC_CheckField, 4, 3, 5, // 1180: check Inst[6:4] == 0x5 |
| 3756 | OPC_Decode, 155, 14, 142, 1, // 1184: decode to MVE_VSTRD64_rq using decoder 142 |
| 3757 | // 1184: } |
| 3758 | // 1184: } // switch Inst[0] |
| 3759 | // 1184: } |
| 3760 | // 1184: } // switch Inst[7] |
| 3761 | // 1184: } |
| 3762 | 1, 177, 2, // 1189: case 0x1: { |
| 3763 | OPC_SwitchField, 7, 1, // 1192: switch Inst[7] { |
| 3764 | 0, 252, 1, // 1195: case 0x0: { |
| 3765 | OPC_SwitchField, 24, 1, // 1198: switch Inst[24] { |
| 3766 | 0, 179, 1, // 1201: case 0x0: { |
| 3767 | OPC_SwitchField, 5, 2, // 1204: switch Inst[6:5] { |
| 3768 | 0, 127, // 1207: case 0x0: { |
| 3769 | OPC_SwitchField, 23, 1, // 1209: switch Inst[23] { |
| 3770 | 0, 11, // 1212: case 0x0: { |
| 3771 | OPC_CheckPredicate, 32, // 1214: check predicate 32 |
| 3772 | OPC_CheckField, 28, 4, 14, // 1216: check Inst[31:28] == 0xe |
| 3773 | OPC_Decode, 143, 11, 148, 1, // 1220: decode to MVE_VMOV_q_rr using decoder 148 |
| 3774 | // 1220: } |
| 3775 | 1, 0, // 1225: case 0x1: { |
| 3776 | OPC_SwitchField, 0, 1, // 1227: switch Inst[0] { |
| 3777 | 0, 65, // 1230: case 0x0: { |
| 3778 | OPC_SwitchField, 4, 1, // 1232: switch Inst[4] { |
| 3779 | 0, 29, // 1235: case 0x0: { |
| 3780 | OPC_SwitchField, 28, 4, // 1237: switch Inst[31:28] { |
| 3781 | 14, 11, // 1240: case 0xe: { |
| 3782 | OPC_CheckPredicate, 31, // 1242: check predicate 31 |
| 3783 | OPC_CheckField, 22, 1, 0, // 1244: check Inst[22] == 0x0 |
| 3784 | OPC_Decode, 235, 9, 142, 1, // 1248: decode to MVE_VLDRBS32_rq using decoder 142 |
| 3785 | // 1248: } |
| 3786 | 15, 0, // 1253: case 0xf: { |
| 3787 | OPC_CheckPredicate, 31, // 1255: check predicate 31 |
| 3788 | OPC_CheckField, 22, 1, 0, // 1257: check Inst[22] == 0x0 |
| 3789 | OPC_Decode, 243, 9, 142, 1, // 1261: decode to MVE_VLDRBU32_rq using decoder 142 |
| 3790 | // 1261: } |
| 3791 | // 1261: } // switch Inst[31:28] |
| 3792 | // 1261: } |
| 3793 | 1, 0, // 1266: case 0x1: { |
| 3794 | OPC_SwitchField, 28, 4, // 1268: switch Inst[31:28] { |
| 3795 | 14, 11, // 1271: case 0xe: { |
| 3796 | OPC_CheckPredicate, 31, // 1273: check predicate 31 |
| 3797 | OPC_CheckField, 22, 1, 0, // 1275: check Inst[22] == 0x0 |
| 3798 | OPC_Decode, 128, 10, 142, 1, // 1279: decode to MVE_VLDRHS32_rq_u using decoder 142 |
| 3799 | // 1279: } |
| 3800 | 15, 0, // 1284: case 0xf: { |
| 3801 | OPC_CheckPredicate, 31, // 1286: check predicate 31 |
| 3802 | OPC_CheckField, 22, 1, 0, // 1288: check Inst[22] == 0x0 |
| 3803 | OPC_Decode, 138, 10, 142, 1, // 1292: decode to MVE_VLDRHU32_rq_u using decoder 142 |
| 3804 | // 1292: } |
| 3805 | // 1292: } // switch Inst[31:28] |
| 3806 | // 1292: } |
| 3807 | // 1292: } // switch Inst[4] |
| 3808 | // 1292: } |
| 3809 | 1, 0, // 1297: case 0x1: { |
| 3810 | OPC_SwitchField, 28, 4, // 1299: switch Inst[31:28] { |
| 3811 | 14, 15, // 1302: case 0xe: { |
| 3812 | OPC_CheckPredicate, 31, // 1304: check predicate 31 |
| 3813 | OPC_CheckField, 22, 1, 0, // 1306: check Inst[22] == 0x0 |
| 3814 | OPC_CheckField, 4, 1, 1, // 1310: check Inst[4] == 0x1 |
| 3815 | OPC_Decode, 255, 9, 142, 1, // 1314: decode to MVE_VLDRHS32_rq using decoder 142 |
| 3816 | // 1314: } |
| 3817 | 15, 0, // 1319: case 0xf: { |
| 3818 | OPC_CheckPredicate, 31, // 1321: check predicate 31 |
| 3819 | OPC_CheckField, 22, 1, 0, // 1323: check Inst[22] == 0x0 |
| 3820 | OPC_CheckField, 4, 1, 1, // 1327: check Inst[4] == 0x1 |
| 3821 | OPC_Decode, 137, 10, 142, 1, // 1331: decode to MVE_VLDRHU32_rq using decoder 142 |
| 3822 | // 1331: } |
| 3823 | // 1331: } // switch Inst[31:28] |
| 3824 | // 1331: } |
| 3825 | // 1331: } // switch Inst[0] |
| 3826 | // 1331: } |
| 3827 | // 1331: } // switch Inst[23] |
| 3828 | // 1331: } |
| 3829 | 2, 0, // 1336: case 0x2: { |
| 3830 | OPC_SwitchField, 0, 1, // 1338: switch Inst[0] { |
| 3831 | 0, 19, // 1341: case 0x0: { |
| 3832 | OPC_CheckPredicate, 31, // 1343: check predicate 31 |
| 3833 | OPC_CheckField, 28, 4, 15, // 1345: check Inst[31:28] == 0xf |
| 3834 | OPC_CheckField, 22, 2, 2, // 1349: check Inst[23:22] == 0x2 |
| 3835 | OPC_CheckField, 4, 1, 0, // 1353: check Inst[4] == 0x0 |
| 3836 | OPC_Decode, 145, 10, 142, 1, // 1357: decode to MVE_VLDRWU32_rq_u using decoder 142 |
| 3837 | // 1357: } |
| 3838 | 1, 0, // 1362: case 0x1: { |
| 3839 | OPC_CheckPredicate, 31, // 1364: check predicate 31 |
| 3840 | OPC_CheckField, 28, 4, 15, // 1366: check Inst[31:28] == 0xf |
| 3841 | OPC_CheckField, 22, 2, 2, // 1370: check Inst[23:22] == 0x2 |
| 3842 | OPC_CheckField, 4, 1, 0, // 1374: check Inst[4] == 0x0 |
| 3843 | OPC_Decode, 144, 10, 142, 1, // 1378: decode to MVE_VLDRWU32_rq using decoder 142 |
| 3844 | // 1378: } |
| 3845 | // 1378: } // switch Inst[0] |
| 3846 | // 1378: } |
| 3847 | // 1378: } // switch Inst[6:5] |
| 3848 | // 1378: } |
| 3849 | 1, 0, // 1383: case 0x1: { |
| 3850 | OPC_SwitchField, 19, 1, // 1385: switch Inst[19] { |
| 3851 | 0, 29, // 1388: case 0x0: { |
| 3852 | OPC_SwitchField, 28, 4, // 1390: switch Inst[31:28] { |
| 3853 | 14, 11, // 1393: case 0xe: { |
| 3854 | OPC_CheckPredicate, 31, // 1395: check predicate 31 |
| 3855 | OPC_CheckField, 22, 1, 0, // 1397: check Inst[22] == 0x0 |
| 3856 | OPC_Decode, 232, 9, 143, 1, // 1401: decode to MVE_VLDRBS32 using decoder 143 |
| 3857 | // 1401: } |
| 3858 | 15, 0, // 1406: case 0xf: { |
| 3859 | OPC_CheckPredicate, 31, // 1408: check predicate 31 |
| 3860 | OPC_CheckField, 22, 1, 0, // 1410: check Inst[22] == 0x0 |
| 3861 | OPC_Decode, 240, 9, 143, 1, // 1414: decode to MVE_VLDRBU32 using decoder 143 |
| 3862 | // 1414: } |
| 3863 | // 1414: } // switch Inst[31:28] |
| 3864 | // 1414: } |
| 3865 | 1, 0, // 1419: case 0x1: { |
| 3866 | OPC_SwitchField, 28, 4, // 1421: switch Inst[31:28] { |
| 3867 | 14, 11, // 1424: case 0xe: { |
| 3868 | OPC_CheckPredicate, 31, // 1426: check predicate 31 |
| 3869 | OPC_CheckField, 22, 1, 0, // 1428: check Inst[22] == 0x0 |
| 3870 | OPC_Decode, 252, 9, 147, 1, // 1432: decode to MVE_VLDRHS32 using decoder 147 |
| 3871 | // 1432: } |
| 3872 | 15, 0, // 1437: case 0xf: { |
| 3873 | OPC_CheckPredicate, 31, // 1439: check predicate 31 |
| 3874 | OPC_CheckField, 22, 1, 0, // 1441: check Inst[22] == 0x0 |
| 3875 | OPC_Decode, 134, 10, 147, 1, // 1445: decode to MVE_VLDRHU32 using decoder 147 |
| 3876 | // 1445: } |
| 3877 | // 1445: } // switch Inst[31:28] |
| 3878 | // 1445: } |
| 3879 | // 1445: } // switch Inst[19] |
| 3880 | // 1445: } |
| 3881 | // 1445: } // switch Inst[24] |
| 3882 | // 1445: } |
| 3883 | 1, 0, // 1450: case 0x1: { |
| 3884 | OPC_SwitchField, 0, 1, // 1452: switch Inst[0] { |
| 3885 | 0, 19, // 1455: case 0x0: { |
| 3886 | OPC_CheckPredicate, 31, // 1457: check predicate 31 |
| 3887 | OPC_CheckField, 28, 4, 15, // 1459: check Inst[31:28] == 0xf |
| 3888 | OPC_CheckField, 22, 3, 2, // 1463: check Inst[24:22] == 0x2 |
| 3889 | OPC_CheckField, 4, 3, 5, // 1467: check Inst[6:4] == 0x5 |
| 3890 | OPC_Decode, 251, 9, 142, 1, // 1471: decode to MVE_VLDRDU64_rq_u using decoder 142 |
| 3891 | // 1471: } |
| 3892 | 1, 0, // 1476: case 0x1: { |
| 3893 | OPC_CheckPredicate, 31, // 1478: check predicate 31 |
| 3894 | OPC_CheckField, 28, 4, 15, // 1480: check Inst[31:28] == 0xf |
| 3895 | OPC_CheckField, 22, 3, 2, // 1484: check Inst[24:22] == 0x2 |
| 3896 | OPC_CheckField, 4, 3, 5, // 1488: check Inst[6:4] == 0x5 |
| 3897 | OPC_Decode, 250, 9, 142, 1, // 1492: decode to MVE_VLDRDU64_rq using decoder 142 |
| 3898 | // 1492: } |
| 3899 | // 1492: } // switch Inst[0] |
| 3900 | // 1492: } |
| 3901 | // 1492: } // switch Inst[7] |
| 3902 | // 1492: } |
| 3903 | 2, 97, // 1497: case 0x2: { |
| 3904 | OPC_SwitchField, 19, 1, // 1499: switch Inst[19] { |
| 3905 | 0, 45, // 1502: case 0x0: { |
| 3906 | OPC_SwitchField, 24, 1, // 1504: switch Inst[24] { |
| 3907 | 0, 19, // 1507: case 0x0: { |
| 3908 | OPC_CheckPredicate, 31, // 1509: check predicate 31 |
| 3909 | OPC_CheckField, 28, 4, 14, // 1511: check Inst[31:28] == 0xe |
| 3910 | OPC_CheckField, 22, 1, 0, // 1515: check Inst[22] == 0x0 |
| 3911 | OPC_CheckField, 7, 1, 0, // 1519: check Inst[7] == 0x0 |
| 3912 | OPC_Decode, 146, 14, 144, 1, // 1523: decode to MVE_VSTRB32_post using decoder 144 |
| 3913 | // 1523: } |
| 3914 | 1, 0, // 1528: case 0x1: { |
| 3915 | OPC_CheckPredicate, 31, // 1530: check predicate 31 |
| 3916 | OPC_CheckField, 28, 4, 14, // 1532: check Inst[31:28] == 0xe |
| 3917 | OPC_CheckField, 22, 1, 0, // 1536: check Inst[22] == 0x0 |
| 3918 | OPC_CheckField, 7, 1, 0, // 1540: check Inst[7] == 0x0 |
| 3919 | OPC_Decode, 147, 14, 145, 1, // 1544: decode to MVE_VSTRB32_pre using decoder 145 |
| 3920 | // 1544: } |
| 3921 | // 1544: } // switch Inst[24] |
| 3922 | // 1544: } |
| 3923 | 1, 0, // 1549: case 0x1: { |
| 3924 | OPC_SwitchField, 24, 1, // 1551: switch Inst[24] { |
| 3925 | 0, 19, // 1554: case 0x0: { |
| 3926 | OPC_CheckPredicate, 31, // 1556: check predicate 31 |
| 3927 | OPC_CheckField, 28, 4, 14, // 1558: check Inst[31:28] == 0xe |
| 3928 | OPC_CheckField, 22, 1, 0, // 1562: check Inst[22] == 0x0 |
| 3929 | OPC_CheckField, 7, 1, 0, // 1566: check Inst[7] == 0x0 |
| 3930 | OPC_Decode, 160, 14, 149, 1, // 1570: decode to MVE_VSTRH32_post using decoder 149 |
| 3931 | // 1570: } |
| 3932 | 1, 0, // 1575: case 0x1: { |
| 3933 | OPC_CheckPredicate, 31, // 1577: check predicate 31 |
| 3934 | OPC_CheckField, 28, 4, 14, // 1579: check Inst[31:28] == 0xe |
| 3935 | OPC_CheckField, 22, 1, 0, // 1583: check Inst[22] == 0x0 |
| 3936 | OPC_CheckField, 7, 1, 0, // 1587: check Inst[7] == 0x0 |
| 3937 | OPC_Decode, 161, 14, 150, 1, // 1591: decode to MVE_VSTRH32_pre using decoder 150 |
| 3938 | // 1591: } |
| 3939 | // 1591: } // switch Inst[24] |
| 3940 | // 1591: } |
| 3941 | // 1591: } // switch Inst[19] |
| 3942 | // 1591: } |
| 3943 | 3, 0, // 1596: case 0x3: { |
| 3944 | OPC_SwitchField, 19, 1, // 1598: switch Inst[19] { |
| 3945 | 0, 81, // 1601: case 0x0: { |
| 3946 | OPC_SwitchField, 24, 1, // 1603: switch Inst[24] { |
| 3947 | 0, 37, // 1606: case 0x0: { |
| 3948 | OPC_SwitchField, 28, 4, // 1608: switch Inst[31:28] { |
| 3949 | 14, 15, // 1611: case 0xe: { |
| 3950 | OPC_CheckPredicate, 31, // 1613: check predicate 31 |
| 3951 | OPC_CheckField, 22, 1, 0, // 1615: check Inst[22] == 0x0 |
| 3952 | OPC_CheckField, 7, 1, 0, // 1619: check Inst[7] == 0x0 |
| 3953 | OPC_Decode, 233, 9, 144, 1, // 1623: decode to MVE_VLDRBS32_post using decoder 144 |
| 3954 | // 1623: } |
| 3955 | 15, 0, // 1628: case 0xf: { |
| 3956 | OPC_CheckPredicate, 31, // 1630: check predicate 31 |
| 3957 | OPC_CheckField, 22, 1, 0, // 1632: check Inst[22] == 0x0 |
| 3958 | OPC_CheckField, 7, 1, 0, // 1636: check Inst[7] == 0x0 |
| 3959 | OPC_Decode, 241, 9, 144, 1, // 1640: decode to MVE_VLDRBU32_post using decoder 144 |
| 3960 | // 1640: } |
| 3961 | // 1640: } // switch Inst[31:28] |
| 3962 | // 1640: } |
| 3963 | 1, 0, // 1645: case 0x1: { |
| 3964 | OPC_SwitchField, 28, 4, // 1647: switch Inst[31:28] { |
| 3965 | 14, 15, // 1650: case 0xe: { |
| 3966 | OPC_CheckPredicate, 31, // 1652: check predicate 31 |
| 3967 | OPC_CheckField, 22, 1, 0, // 1654: check Inst[22] == 0x0 |
| 3968 | OPC_CheckField, 7, 1, 0, // 1658: check Inst[7] == 0x0 |
| 3969 | OPC_Decode, 234, 9, 145, 1, // 1662: decode to MVE_VLDRBS32_pre using decoder 145 |
| 3970 | // 1662: } |
| 3971 | 15, 0, // 1667: case 0xf: { |
| 3972 | OPC_CheckPredicate, 31, // 1669: check predicate 31 |
| 3973 | OPC_CheckField, 22, 1, 0, // 1671: check Inst[22] == 0x0 |
| 3974 | OPC_CheckField, 7, 1, 0, // 1675: check Inst[7] == 0x0 |
| 3975 | OPC_Decode, 242, 9, 145, 1, // 1679: decode to MVE_VLDRBU32_pre using decoder 145 |
| 3976 | // 1679: } |
| 3977 | // 1679: } // switch Inst[31:28] |
| 3978 | // 1679: } |
| 3979 | // 1679: } // switch Inst[24] |
| 3980 | // 1679: } |
| 3981 | 1, 0, // 1684: case 0x1: { |
| 3982 | OPC_SwitchField, 24, 1, // 1686: switch Inst[24] { |
| 3983 | 0, 37, // 1689: case 0x0: { |
| 3984 | OPC_SwitchField, 28, 4, // 1691: switch Inst[31:28] { |
| 3985 | 14, 15, // 1694: case 0xe: { |
| 3986 | OPC_CheckPredicate, 31, // 1696: check predicate 31 |
| 3987 | OPC_CheckField, 22, 1, 0, // 1698: check Inst[22] == 0x0 |
| 3988 | OPC_CheckField, 7, 1, 0, // 1702: check Inst[7] == 0x0 |
| 3989 | OPC_Decode, 253, 9, 149, 1, // 1706: decode to MVE_VLDRHS32_post using decoder 149 |
| 3990 | // 1706: } |
| 3991 | 15, 0, // 1711: case 0xf: { |
| 3992 | OPC_CheckPredicate, 31, // 1713: check predicate 31 |
| 3993 | OPC_CheckField, 22, 1, 0, // 1715: check Inst[22] == 0x0 |
| 3994 | OPC_CheckField, 7, 1, 0, // 1719: check Inst[7] == 0x0 |
| 3995 | OPC_Decode, 135, 10, 149, 1, // 1723: decode to MVE_VLDRHU32_post using decoder 149 |
| 3996 | // 1723: } |
| 3997 | // 1723: } // switch Inst[31:28] |
| 3998 | // 1723: } |
| 3999 | 1, 0, // 1728: case 0x1: { |
| 4000 | OPC_SwitchField, 28, 4, // 1730: switch Inst[31:28] { |
| 4001 | 14, 15, // 1733: case 0xe: { |
| 4002 | OPC_CheckPredicate, 31, // 1735: check predicate 31 |
| 4003 | OPC_CheckField, 22, 1, 0, // 1737: check Inst[22] == 0x0 |
| 4004 | OPC_CheckField, 7, 1, 0, // 1741: check Inst[7] == 0x0 |
| 4005 | OPC_Decode, 254, 9, 150, 1, // 1745: decode to MVE_VLDRHS32_pre using decoder 150 |
| 4006 | // 1745: } |
| 4007 | 15, 0, // 1750: case 0xf: { |
| 4008 | OPC_CheckPredicate, 31, // 1752: check predicate 31 |
| 4009 | OPC_CheckField, 22, 1, 0, // 1754: check Inst[22] == 0x0 |
| 4010 | OPC_CheckField, 7, 1, 0, // 1758: check Inst[7] == 0x0 |
| 4011 | OPC_Decode, 136, 10, 150, 1, // 1762: decode to MVE_VLDRHU32_pre using decoder 150 |
| 4012 | // 1762: } |
| 4013 | // 1762: } // switch Inst[31:28] |
| 4014 | // 1762: } |
| 4015 | // 1762: } // switch Inst[24] |
| 4016 | // 1762: } |
| 4017 | // 1762: } // switch Inst[19] |
| 4018 | // 1762: } |
| 4019 | // 1762: } // switch Inst[21:20] |
| 4020 | // 1762: } |
| 4021 | 30, 148, 8, // 1767: case 0x1e: { |
| 4022 | OPC_SwitchField, 20, 3, // 1770: switch Inst[22:20] { |
| 4023 | 0, 140, 2, // 1773: case 0x0: { |
| 4024 | OPC_SwitchField, 7, 1, // 1776: switch Inst[7] { |
| 4025 | 0, 137, 1, // 1779: case 0x0: { |
| 4026 | OPC_SwitchField, 24, 1, // 1782: switch Inst[24] { |
| 4027 | 0, 105, // 1785: case 0x0: { |
| 4028 | OPC_SwitchField, 0, 7, // 1787: switch Inst[6:0] { |
| 4029 | 0, 15, // 1790: case 0x0: { |
| 4030 | OPC_CheckPredicate, 31, // 1792: check predicate 31 |
| 4031 | OPC_CheckField, 28, 4, 15, // 1794: check Inst[31:28] == 0xf |
| 4032 | OPC_CheckField, 23, 1, 1, // 1798: check Inst[23] == 0x1 |
| 4033 | OPC_Decode, 237, 13, 151, 1, // 1802: decode to MVE_VST20_8 using decoder 151 |
| 4034 | // 1802: } |
| 4035 | 1, 15, // 1807: case 0x1: { |
| 4036 | OPC_CheckPredicate, 31, // 1809: check predicate 31 |
| 4037 | OPC_CheckField, 28, 4, 15, // 1811: check Inst[31:28] == 0xf |
| 4038 | OPC_CheckField, 23, 1, 1, // 1815: check Inst[23] == 0x1 |
| 4039 | OPC_Decode, 249, 13, 152, 1, // 1819: decode to MVE_VST40_8 using decoder 152 |
| 4040 | // 1819: } |
| 4041 | 32, 15, // 1824: case 0x20: { |
| 4042 | OPC_CheckPredicate, 31, // 1826: check predicate 31 |
| 4043 | OPC_CheckField, 28, 4, 15, // 1828: check Inst[31:28] == 0xf |
| 4044 | OPC_CheckField, 23, 1, 1, // 1832: check Inst[23] == 0x1 |
| 4045 | OPC_Decode, 243, 13, 151, 1, // 1836: decode to MVE_VST21_8 using decoder 151 |
| 4046 | // 1836: } |
| 4047 | 33, 15, // 1841: case 0x21: { |
| 4048 | OPC_CheckPredicate, 31, // 1843: check predicate 31 |
| 4049 | OPC_CheckField, 28, 4, 15, // 1845: check Inst[31:28] == 0xf |
| 4050 | OPC_CheckField, 23, 1, 1, // 1849: check Inst[23] == 0x1 |
| 4051 | OPC_Decode, 255, 13, 152, 1, // 1853: decode to MVE_VST41_8 using decoder 152 |
| 4052 | // 1853: } |
| 4053 | 65, 15, // 1858: case 0x41: { |
| 4054 | OPC_CheckPredicate, 31, // 1860: check predicate 31 |
| 4055 | OPC_CheckField, 28, 4, 15, // 1862: check Inst[31:28] == 0xf |
| 4056 | OPC_CheckField, 23, 1, 1, // 1866: check Inst[23] == 0x1 |
| 4057 | OPC_Decode, 133, 14, 152, 1, // 1870: decode to MVE_VST42_8 using decoder 152 |
| 4058 | // 1870: } |
| 4059 | 97, 0, // 1875: case 0x61: { |
| 4060 | OPC_CheckPredicate, 31, // 1877: check predicate 31 |
| 4061 | OPC_CheckField, 28, 4, 15, // 1879: check Inst[31:28] == 0xf |
| 4062 | OPC_CheckField, 23, 1, 1, // 1883: check Inst[23] == 0x1 |
| 4063 | OPC_Decode, 139, 14, 152, 1, // 1887: decode to MVE_VST43_8 using decoder 152 |
| 4064 | // 1887: } |
| 4065 | // 1887: } // switch Inst[6:0] |
| 4066 | // 1887: } |
| 4067 | 1, 0, // 1892: case 0x1: { |
| 4068 | OPC_SwitchField, 28, 4, // 1894: switch Inst[31:28] { |
| 4069 | 14, 7, // 1897: case 0xe: { |
| 4070 | OPC_CheckPredicate, 31, // 1899: check predicate 31 |
| 4071 | OPC_Decode, 150, 14, 153, 1, // 1901: decode to MVE_VSTRBU8 using decoder 153 |
| 4072 | // 1901: } |
| 4073 | 15, 0, // 1906: case 0xf: { |
| 4074 | OPC_CheckPredicate, 31, // 1908: check predicate 31 |
| 4075 | OPC_CheckField, 16, 1, 0, // 1910: check Inst[16] == 0x0 |
| 4076 | OPC_Decode, 167, 14, 154, 1, // 1914: decode to MVE_VSTRW32_qi using decoder 154 |
| 4077 | // 1914: } |
| 4078 | // 1914: } // switch Inst[31:28] |
| 4079 | // 1914: } |
| 4080 | // 1914: } // switch Inst[24] |
| 4081 | // 1914: } |
| 4082 | 1, 0, // 1919: case 0x1: { |
| 4083 | OPC_SwitchField, 24, 1, // 1921: switch Inst[24] { |
| 4084 | 0, 105, // 1924: case 0x0: { |
| 4085 | OPC_SwitchField, 0, 7, // 1926: switch Inst[6:0] { |
| 4086 | 0, 15, // 1929: case 0x0: { |
| 4087 | OPC_CheckPredicate, 31, // 1931: check predicate 31 |
| 4088 | OPC_CheckField, 28, 4, 15, // 1933: check Inst[31:28] == 0xf |
| 4089 | OPC_CheckField, 23, 1, 1, // 1937: check Inst[23] == 0x1 |
| 4090 | OPC_Decode, 233, 13, 151, 1, // 1941: decode to MVE_VST20_16 using decoder 151 |
| 4091 | // 1941: } |
| 4092 | 1, 15, // 1946: case 0x1: { |
| 4093 | OPC_CheckPredicate, 31, // 1948: check predicate 31 |
| 4094 | OPC_CheckField, 28, 4, 15, // 1950: check Inst[31:28] == 0xf |
| 4095 | OPC_CheckField, 23, 1, 1, // 1954: check Inst[23] == 0x1 |
| 4096 | OPC_Decode, 245, 13, 152, 1, // 1958: decode to MVE_VST40_16 using decoder 152 |
| 4097 | // 1958: } |
| 4098 | 32, 15, // 1963: case 0x20: { |
| 4099 | OPC_CheckPredicate, 31, // 1965: check predicate 31 |
| 4100 | OPC_CheckField, 28, 4, 15, // 1967: check Inst[31:28] == 0xf |
| 4101 | OPC_CheckField, 23, 1, 1, // 1971: check Inst[23] == 0x1 |
| 4102 | OPC_Decode, 239, 13, 151, 1, // 1975: decode to MVE_VST21_16 using decoder 151 |
| 4103 | // 1975: } |
| 4104 | 33, 15, // 1980: case 0x21: { |
| 4105 | OPC_CheckPredicate, 31, // 1982: check predicate 31 |
| 4106 | OPC_CheckField, 28, 4, 15, // 1984: check Inst[31:28] == 0xf |
| 4107 | OPC_CheckField, 23, 1, 1, // 1988: check Inst[23] == 0x1 |
| 4108 | OPC_Decode, 251, 13, 152, 1, // 1992: decode to MVE_VST41_16 using decoder 152 |
| 4109 | // 1992: } |
| 4110 | 65, 15, // 1997: case 0x41: { |
| 4111 | OPC_CheckPredicate, 31, // 1999: check predicate 31 |
| 4112 | OPC_CheckField, 28, 4, 15, // 2001: check Inst[31:28] == 0xf |
| 4113 | OPC_CheckField, 23, 1, 1, // 2005: check Inst[23] == 0x1 |
| 4114 | OPC_Decode, 129, 14, 152, 1, // 2009: decode to MVE_VST42_16 using decoder 152 |
| 4115 | // 2009: } |
| 4116 | 97, 0, // 2014: case 0x61: { |
| 4117 | OPC_CheckPredicate, 31, // 2016: check predicate 31 |
| 4118 | OPC_CheckField, 28, 4, 15, // 2018: check Inst[31:28] == 0xf |
| 4119 | OPC_CheckField, 23, 1, 1, // 2022: check Inst[23] == 0x1 |
| 4120 | OPC_Decode, 135, 14, 152, 1, // 2026: decode to MVE_VST43_16 using decoder 152 |
| 4121 | // 2026: } |
| 4122 | // 2026: } // switch Inst[6:0] |
| 4123 | // 2026: } |
| 4124 | 1, 0, // 2031: case 0x1: { |
| 4125 | OPC_CheckPredicate, 31, // 2033: check predicate 31 |
| 4126 | OPC_CheckField, 28, 4, 14, // 2035: check Inst[31:28] == 0xe |
| 4127 | OPC_Decode, 164, 14, 155, 1, // 2039: decode to MVE_VSTRHU16 using decoder 155 |
| 4128 | // 2039: } |
| 4129 | // 2039: } // switch Inst[24] |
| 4130 | // 2039: } |
| 4131 | // 2039: } // switch Inst[7] |
| 4132 | // 2039: } |
| 4133 | 1, 140, 2, // 2044: case 0x1: { |
| 4134 | OPC_SwitchField, 7, 1, // 2047: switch Inst[7] { |
| 4135 | 0, 137, 1, // 2050: case 0x0: { |
| 4136 | OPC_SwitchField, 24, 1, // 2053: switch Inst[24] { |
| 4137 | 0, 105, // 2056: case 0x0: { |
| 4138 | OPC_SwitchField, 0, 7, // 2058: switch Inst[6:0] { |
| 4139 | 0, 15, // 2061: case 0x0: { |
| 4140 | OPC_CheckPredicate, 31, // 2063: check predicate 31 |
| 4141 | OPC_CheckField, 28, 4, 15, // 2065: check Inst[31:28] == 0xf |
| 4142 | OPC_CheckField, 23, 1, 1, // 2069: check Inst[23] == 0x1 |
| 4143 | OPC_Decode, 196, 9, 156, 1, // 2073: decode to MVE_VLD20_8 using decoder 156 |
| 4144 | // 2073: } |
| 4145 | 1, 15, // 2078: case 0x1: { |
| 4146 | OPC_CheckPredicate, 31, // 2080: check predicate 31 |
| 4147 | OPC_CheckField, 28, 4, 15, // 2082: check Inst[31:28] == 0xf |
| 4148 | OPC_CheckField, 23, 1, 1, // 2086: check Inst[23] == 0x1 |
| 4149 | OPC_Decode, 208, 9, 157, 1, // 2090: decode to MVE_VLD40_8 using decoder 157 |
| 4150 | // 2090: } |
| 4151 | 32, 15, // 2095: case 0x20: { |
| 4152 | OPC_CheckPredicate, 31, // 2097: check predicate 31 |
| 4153 | OPC_CheckField, 28, 4, 15, // 2099: check Inst[31:28] == 0xf |
| 4154 | OPC_CheckField, 23, 1, 1, // 2103: check Inst[23] == 0x1 |
| 4155 | OPC_Decode, 202, 9, 156, 1, // 2107: decode to MVE_VLD21_8 using decoder 156 |
| 4156 | // 2107: } |
| 4157 | 33, 15, // 2112: case 0x21: { |
| 4158 | OPC_CheckPredicate, 31, // 2114: check predicate 31 |
| 4159 | OPC_CheckField, 28, 4, 15, // 2116: check Inst[31:28] == 0xf |
| 4160 | OPC_CheckField, 23, 1, 1, // 2120: check Inst[23] == 0x1 |
| 4161 | OPC_Decode, 214, 9, 157, 1, // 2124: decode to MVE_VLD41_8 using decoder 157 |
| 4162 | // 2124: } |
| 4163 | 65, 15, // 2129: case 0x41: { |
| 4164 | OPC_CheckPredicate, 31, // 2131: check predicate 31 |
| 4165 | OPC_CheckField, 28, 4, 15, // 2133: check Inst[31:28] == 0xf |
| 4166 | OPC_CheckField, 23, 1, 1, // 2137: check Inst[23] == 0x1 |
| 4167 | OPC_Decode, 220, 9, 157, 1, // 2141: decode to MVE_VLD42_8 using decoder 157 |
| 4168 | // 2141: } |
| 4169 | 97, 0, // 2146: case 0x61: { |
| 4170 | OPC_CheckPredicate, 31, // 2148: check predicate 31 |
| 4171 | OPC_CheckField, 28, 4, 15, // 2150: check Inst[31:28] == 0xf |
| 4172 | OPC_CheckField, 23, 1, 1, // 2154: check Inst[23] == 0x1 |
| 4173 | OPC_Decode, 226, 9, 157, 1, // 2158: decode to MVE_VLD43_8 using decoder 157 |
| 4174 | // 2158: } |
| 4175 | // 2158: } // switch Inst[6:0] |
| 4176 | // 2158: } |
| 4177 | 1, 0, // 2163: case 0x1: { |
| 4178 | OPC_SwitchField, 28, 4, // 2165: switch Inst[31:28] { |
| 4179 | 14, 7, // 2168: case 0xe: { |
| 4180 | OPC_CheckPredicate, 31, // 2170: check predicate 31 |
| 4181 | OPC_Decode, 244, 9, 153, 1, // 2172: decode to MVE_VLDRBU8 using decoder 153 |
| 4182 | // 2172: } |
| 4183 | 15, 0, // 2177: case 0xf: { |
| 4184 | OPC_CheckPredicate, 31, // 2179: check predicate 31 |
| 4185 | OPC_CheckField, 16, 1, 0, // 2181: check Inst[16] == 0x0 |
| 4186 | OPC_Decode, 142, 10, 154, 1, // 2185: decode to MVE_VLDRWU32_qi using decoder 154 |
| 4187 | // 2185: } |
| 4188 | // 2185: } // switch Inst[31:28] |
| 4189 | // 2185: } |
| 4190 | // 2185: } // switch Inst[24] |
| 4191 | // 2185: } |
| 4192 | 1, 0, // 2190: case 0x1: { |
| 4193 | OPC_SwitchField, 24, 1, // 2192: switch Inst[24] { |
| 4194 | 0, 105, // 2195: case 0x0: { |
| 4195 | OPC_SwitchField, 0, 7, // 2197: switch Inst[6:0] { |
| 4196 | 0, 15, // 2200: case 0x0: { |
| 4197 | OPC_CheckPredicate, 31, // 2202: check predicate 31 |
| 4198 | OPC_CheckField, 28, 4, 15, // 2204: check Inst[31:28] == 0xf |
| 4199 | OPC_CheckField, 23, 1, 1, // 2208: check Inst[23] == 0x1 |
| 4200 | OPC_Decode, 192, 9, 156, 1, // 2212: decode to MVE_VLD20_16 using decoder 156 |
| 4201 | // 2212: } |
| 4202 | 1, 15, // 2217: case 0x1: { |
| 4203 | OPC_CheckPredicate, 31, // 2219: check predicate 31 |
| 4204 | OPC_CheckField, 28, 4, 15, // 2221: check Inst[31:28] == 0xf |
| 4205 | OPC_CheckField, 23, 1, 1, // 2225: check Inst[23] == 0x1 |
| 4206 | OPC_Decode, 204, 9, 157, 1, // 2229: decode to MVE_VLD40_16 using decoder 157 |
| 4207 | // 2229: } |
| 4208 | 32, 15, // 2234: case 0x20: { |
| 4209 | OPC_CheckPredicate, 31, // 2236: check predicate 31 |
| 4210 | OPC_CheckField, 28, 4, 15, // 2238: check Inst[31:28] == 0xf |
| 4211 | OPC_CheckField, 23, 1, 1, // 2242: check Inst[23] == 0x1 |
| 4212 | OPC_Decode, 198, 9, 156, 1, // 2246: decode to MVE_VLD21_16 using decoder 156 |
| 4213 | // 2246: } |
| 4214 | 33, 15, // 2251: case 0x21: { |
| 4215 | OPC_CheckPredicate, 31, // 2253: check predicate 31 |
| 4216 | OPC_CheckField, 28, 4, 15, // 2255: check Inst[31:28] == 0xf |
| 4217 | OPC_CheckField, 23, 1, 1, // 2259: check Inst[23] == 0x1 |
| 4218 | OPC_Decode, 210, 9, 157, 1, // 2263: decode to MVE_VLD41_16 using decoder 157 |
| 4219 | // 2263: } |
| 4220 | 65, 15, // 2268: case 0x41: { |
| 4221 | OPC_CheckPredicate, 31, // 2270: check predicate 31 |
| 4222 | OPC_CheckField, 28, 4, 15, // 2272: check Inst[31:28] == 0xf |
| 4223 | OPC_CheckField, 23, 1, 1, // 2276: check Inst[23] == 0x1 |
| 4224 | OPC_Decode, 216, 9, 157, 1, // 2280: decode to MVE_VLD42_16 using decoder 157 |
| 4225 | // 2280: } |
| 4226 | 97, 0, // 2285: case 0x61: { |
| 4227 | OPC_CheckPredicate, 31, // 2287: check predicate 31 |
| 4228 | OPC_CheckField, 28, 4, 15, // 2289: check Inst[31:28] == 0xf |
| 4229 | OPC_CheckField, 23, 1, 1, // 2293: check Inst[23] == 0x1 |
| 4230 | OPC_Decode, 222, 9, 157, 1, // 2297: decode to MVE_VLD43_16 using decoder 157 |
| 4231 | // 2297: } |
| 4232 | // 2297: } // switch Inst[6:0] |
| 4233 | // 2297: } |
| 4234 | 1, 0, // 2302: case 0x1: { |
| 4235 | OPC_CheckPredicate, 31, // 2304: check predicate 31 |
| 4236 | OPC_CheckField, 28, 4, 14, // 2306: check Inst[31:28] == 0xe |
| 4237 | OPC_Decode, 129, 10, 155, 1, // 2310: decode to MVE_VLDRHU16 using decoder 155 |
| 4238 | // 2310: } |
| 4239 | // 2310: } // switch Inst[24] |
| 4240 | // 2310: } |
| 4241 | // 2310: } // switch Inst[7] |
| 4242 | // 2310: } |
| 4243 | 2, 247, 1, // 2315: case 0x2: { |
| 4244 | OPC_SwitchField, 7, 1, // 2318: switch Inst[7] { |
| 4245 | 0, 127, // 2321: case 0x0: { |
| 4246 | OPC_SwitchField, 24, 1, // 2323: switch Inst[24] { |
| 4247 | 0, 95, // 2326: case 0x0: { |
| 4248 | OPC_SwitchField, 28, 4, // 2328: switch Inst[31:28] { |
| 4249 | 14, 7, // 2331: case 0xe: { |
| 4250 | OPC_CheckPredicate, 31, // 2333: check predicate 31 |
| 4251 | OPC_Decode, 151, 14, 158, 1, // 2335: decode to MVE_VSTRBU8_post using decoder 158 |
| 4252 | // 2335: } |
| 4253 | 15, 0, // 2340: case 0xf: { |
| 4254 | OPC_SwitchField, 0, 7, // 2342: switch Inst[6:0] { |
| 4255 | 0, 11, // 2345: case 0x0: { |
| 4256 | OPC_CheckPredicate, 31, // 2347: check predicate 31 |
| 4257 | OPC_CheckField, 23, 1, 1, // 2349: check Inst[23] == 0x1 |
| 4258 | OPC_Decode, 238, 13, 159, 1, // 2353: decode to MVE_VST20_8_wb using decoder 159 |
| 4259 | // 2353: } |
| 4260 | 1, 11, // 2358: case 0x1: { |
| 4261 | OPC_CheckPredicate, 31, // 2360: check predicate 31 |
| 4262 | OPC_CheckField, 23, 1, 1, // 2362: check Inst[23] == 0x1 |
| 4263 | OPC_Decode, 250, 13, 160, 1, // 2366: decode to MVE_VST40_8_wb using decoder 160 |
| 4264 | // 2366: } |
| 4265 | 32, 11, // 2371: case 0x20: { |
| 4266 | OPC_CheckPredicate, 31, // 2373: check predicate 31 |
| 4267 | OPC_CheckField, 23, 1, 1, // 2375: check Inst[23] == 0x1 |
| 4268 | OPC_Decode, 244, 13, 159, 1, // 2379: decode to MVE_VST21_8_wb using decoder 159 |
| 4269 | // 2379: } |
| 4270 | 33, 11, // 2384: case 0x21: { |
| 4271 | OPC_CheckPredicate, 31, // 2386: check predicate 31 |
| 4272 | OPC_CheckField, 23, 1, 1, // 2388: check Inst[23] == 0x1 |
| 4273 | OPC_Decode, 128, 14, 160, 1, // 2392: decode to MVE_VST41_8_wb using decoder 160 |
| 4274 | // 2392: } |
| 4275 | 65, 11, // 2397: case 0x41: { |
| 4276 | OPC_CheckPredicate, 31, // 2399: check predicate 31 |
| 4277 | OPC_CheckField, 23, 1, 1, // 2401: check Inst[23] == 0x1 |
| 4278 | OPC_Decode, 134, 14, 160, 1, // 2405: decode to MVE_VST42_8_wb using decoder 160 |
| 4279 | // 2405: } |
| 4280 | 97, 0, // 2410: case 0x61: { |
| 4281 | OPC_CheckPredicate, 31, // 2412: check predicate 31 |
| 4282 | OPC_CheckField, 23, 1, 1, // 2414: check Inst[23] == 0x1 |
| 4283 | OPC_Decode, 140, 14, 160, 1, // 2418: decode to MVE_VST43_8_wb using decoder 160 |
| 4284 | // 2418: } |
| 4285 | // 2418: } // switch Inst[6:0] |
| 4286 | // 2418: } |
| 4287 | // 2418: } // switch Inst[31:28] |
| 4288 | // 2418: } |
| 4289 | 1, 0, // 2423: case 0x1: { |
| 4290 | OPC_SwitchField, 28, 4, // 2425: switch Inst[31:28] { |
| 4291 | 14, 7, // 2428: case 0xe: { |
| 4292 | OPC_CheckPredicate, 31, // 2430: check predicate 31 |
| 4293 | OPC_Decode, 152, 14, 161, 1, // 2432: decode to MVE_VSTRBU8_pre using decoder 161 |
| 4294 | // 2432: } |
| 4295 | 15, 0, // 2437: case 0xf: { |
| 4296 | OPC_CheckPredicate, 31, // 2439: check predicate 31 |
| 4297 | OPC_CheckField, 16, 1, 0, // 2441: check Inst[16] == 0x0 |
| 4298 | OPC_Decode, 168, 14, 162, 1, // 2445: decode to MVE_VSTRW32_qi_pre using decoder 162 |
| 4299 | // 2445: } |
| 4300 | // 2445: } // switch Inst[31:28] |
| 4301 | // 2445: } |
| 4302 | // 2445: } // switch Inst[24] |
| 4303 | // 2445: } |
| 4304 | 1, 0, // 2450: case 0x1: { |
| 4305 | OPC_SwitchField, 24, 1, // 2452: switch Inst[24] { |
| 4306 | 0, 95, // 2455: case 0x0: { |
| 4307 | OPC_SwitchField, 28, 4, // 2457: switch Inst[31:28] { |
| 4308 | 14, 7, // 2460: case 0xe: { |
| 4309 | OPC_CheckPredicate, 31, // 2462: check predicate 31 |
| 4310 | OPC_Decode, 165, 14, 163, 1, // 2464: decode to MVE_VSTRHU16_post using decoder 163 |
| 4311 | // 2464: } |
| 4312 | 15, 0, // 2469: case 0xf: { |
| 4313 | OPC_SwitchField, 0, 7, // 2471: switch Inst[6:0] { |
| 4314 | 0, 11, // 2474: case 0x0: { |
| 4315 | OPC_CheckPredicate, 31, // 2476: check predicate 31 |
| 4316 | OPC_CheckField, 23, 1, 1, // 2478: check Inst[23] == 0x1 |
| 4317 | OPC_Decode, 234, 13, 159, 1, // 2482: decode to MVE_VST20_16_wb using decoder 159 |
| 4318 | // 2482: } |
| 4319 | 1, 11, // 2487: case 0x1: { |
| 4320 | OPC_CheckPredicate, 31, // 2489: check predicate 31 |
| 4321 | OPC_CheckField, 23, 1, 1, // 2491: check Inst[23] == 0x1 |
| 4322 | OPC_Decode, 246, 13, 160, 1, // 2495: decode to MVE_VST40_16_wb using decoder 160 |
| 4323 | // 2495: } |
| 4324 | 32, 11, // 2500: case 0x20: { |
| 4325 | OPC_CheckPredicate, 31, // 2502: check predicate 31 |
| 4326 | OPC_CheckField, 23, 1, 1, // 2504: check Inst[23] == 0x1 |
| 4327 | OPC_Decode, 240, 13, 159, 1, // 2508: decode to MVE_VST21_16_wb using decoder 159 |
| 4328 | // 2508: } |
| 4329 | 33, 11, // 2513: case 0x21: { |
| 4330 | OPC_CheckPredicate, 31, // 2515: check predicate 31 |
| 4331 | OPC_CheckField, 23, 1, 1, // 2517: check Inst[23] == 0x1 |
| 4332 | OPC_Decode, 252, 13, 160, 1, // 2521: decode to MVE_VST41_16_wb using decoder 160 |
| 4333 | // 2521: } |
| 4334 | 65, 11, // 2526: case 0x41: { |
| 4335 | OPC_CheckPredicate, 31, // 2528: check predicate 31 |
| 4336 | OPC_CheckField, 23, 1, 1, // 2530: check Inst[23] == 0x1 |
| 4337 | OPC_Decode, 130, 14, 160, 1, // 2534: decode to MVE_VST42_16_wb using decoder 160 |
| 4338 | // 2534: } |
| 4339 | 97, 0, // 2539: case 0x61: { |
| 4340 | OPC_CheckPredicate, 31, // 2541: check predicate 31 |
| 4341 | OPC_CheckField, 23, 1, 1, // 2543: check Inst[23] == 0x1 |
| 4342 | OPC_Decode, 136, 14, 160, 1, // 2547: decode to MVE_VST43_16_wb using decoder 160 |
| 4343 | // 2547: } |
| 4344 | // 2547: } // switch Inst[6:0] |
| 4345 | // 2547: } |
| 4346 | // 2547: } // switch Inst[31:28] |
| 4347 | // 2547: } |
| 4348 | 1, 0, // 2552: case 0x1: { |
| 4349 | OPC_CheckPredicate, 31, // 2554: check predicate 31 |
| 4350 | OPC_CheckField, 28, 4, 14, // 2556: check Inst[31:28] == 0xe |
| 4351 | OPC_Decode, 166, 14, 164, 1, // 2560: decode to MVE_VSTRHU16_pre using decoder 164 |
| 4352 | // 2560: } |
| 4353 | // 2560: } // switch Inst[24] |
| 4354 | // 2560: } |
| 4355 | // 2560: } // switch Inst[7] |
| 4356 | // 2560: } |
| 4357 | 3, 0, // 2565: case 0x3: { |
| 4358 | OPC_SwitchField, 7, 1, // 2567: switch Inst[7] { |
| 4359 | 0, 127, // 2570: case 0x0: { |
| 4360 | OPC_SwitchField, 24, 1, // 2572: switch Inst[24] { |
| 4361 | 0, 95, // 2575: case 0x0: { |
| 4362 | OPC_SwitchField, 28, 4, // 2577: switch Inst[31:28] { |
| 4363 | 14, 7, // 2580: case 0xe: { |
| 4364 | OPC_CheckPredicate, 31, // 2582: check predicate 31 |
| 4365 | OPC_Decode, 245, 9, 158, 1, // 2584: decode to MVE_VLDRBU8_post using decoder 158 |
| 4366 | // 2584: } |
| 4367 | 15, 0, // 2589: case 0xf: { |
| 4368 | OPC_SwitchField, 0, 7, // 2591: switch Inst[6:0] { |
| 4369 | 0, 11, // 2594: case 0x0: { |
| 4370 | OPC_CheckPredicate, 31, // 2596: check predicate 31 |
| 4371 | OPC_CheckField, 23, 1, 1, // 2598: check Inst[23] == 0x1 |
| 4372 | OPC_Decode, 197, 9, 165, 1, // 2602: decode to MVE_VLD20_8_wb using decoder 165 |
| 4373 | // 2602: } |
| 4374 | 1, 11, // 2607: case 0x1: { |
| 4375 | OPC_CheckPredicate, 31, // 2609: check predicate 31 |
| 4376 | OPC_CheckField, 23, 1, 1, // 2611: check Inst[23] == 0x1 |
| 4377 | OPC_Decode, 209, 9, 166, 1, // 2615: decode to MVE_VLD40_8_wb using decoder 166 |
| 4378 | // 2615: } |
| 4379 | 32, 11, // 2620: case 0x20: { |
| 4380 | OPC_CheckPredicate, 31, // 2622: check predicate 31 |
| 4381 | OPC_CheckField, 23, 1, 1, // 2624: check Inst[23] == 0x1 |
| 4382 | OPC_Decode, 203, 9, 165, 1, // 2628: decode to MVE_VLD21_8_wb using decoder 165 |
| 4383 | // 2628: } |
| 4384 | 33, 11, // 2633: case 0x21: { |
| 4385 | OPC_CheckPredicate, 31, // 2635: check predicate 31 |
| 4386 | OPC_CheckField, 23, 1, 1, // 2637: check Inst[23] == 0x1 |
| 4387 | OPC_Decode, 215, 9, 166, 1, // 2641: decode to MVE_VLD41_8_wb using decoder 166 |
| 4388 | // 2641: } |
| 4389 | 65, 11, // 2646: case 0x41: { |
| 4390 | OPC_CheckPredicate, 31, // 2648: check predicate 31 |
| 4391 | OPC_CheckField, 23, 1, 1, // 2650: check Inst[23] == 0x1 |
| 4392 | OPC_Decode, 221, 9, 166, 1, // 2654: decode to MVE_VLD42_8_wb using decoder 166 |
| 4393 | // 2654: } |
| 4394 | 97, 0, // 2659: case 0x61: { |
| 4395 | OPC_CheckPredicate, 31, // 2661: check predicate 31 |
| 4396 | OPC_CheckField, 23, 1, 1, // 2663: check Inst[23] == 0x1 |
| 4397 | OPC_Decode, 227, 9, 166, 1, // 2667: decode to MVE_VLD43_8_wb using decoder 166 |
| 4398 | // 2667: } |
| 4399 | // 2667: } // switch Inst[6:0] |
| 4400 | // 2667: } |
| 4401 | // 2667: } // switch Inst[31:28] |
| 4402 | // 2667: } |
| 4403 | 1, 0, // 2672: case 0x1: { |
| 4404 | OPC_SwitchField, 28, 4, // 2674: switch Inst[31:28] { |
| 4405 | 14, 7, // 2677: case 0xe: { |
| 4406 | OPC_CheckPredicate, 31, // 2679: check predicate 31 |
| 4407 | OPC_Decode, 246, 9, 161, 1, // 2681: decode to MVE_VLDRBU8_pre using decoder 161 |
| 4408 | // 2681: } |
| 4409 | 15, 0, // 2686: case 0xf: { |
| 4410 | OPC_CheckPredicate, 31, // 2688: check predicate 31 |
| 4411 | OPC_CheckField, 16, 1, 0, // 2690: check Inst[16] == 0x0 |
| 4412 | OPC_Decode, 143, 10, 162, 1, // 2694: decode to MVE_VLDRWU32_qi_pre using decoder 162 |
| 4413 | // 2694: } |
| 4414 | // 2694: } // switch Inst[31:28] |
| 4415 | // 2694: } |
| 4416 | // 2694: } // switch Inst[24] |
| 4417 | // 2694: } |
| 4418 | 1, 0, // 2699: case 0x1: { |
| 4419 | OPC_SwitchField, 24, 1, // 2701: switch Inst[24] { |
| 4420 | 0, 95, // 2704: case 0x0: { |
| 4421 | OPC_SwitchField, 28, 4, // 2706: switch Inst[31:28] { |
| 4422 | 14, 7, // 2709: case 0xe: { |
| 4423 | OPC_CheckPredicate, 31, // 2711: check predicate 31 |
| 4424 | OPC_Decode, 130, 10, 163, 1, // 2713: decode to MVE_VLDRHU16_post using decoder 163 |
| 4425 | // 2713: } |
| 4426 | 15, 0, // 2718: case 0xf: { |
| 4427 | OPC_SwitchField, 0, 7, // 2720: switch Inst[6:0] { |
| 4428 | 0, 11, // 2723: case 0x0: { |
| 4429 | OPC_CheckPredicate, 31, // 2725: check predicate 31 |
| 4430 | OPC_CheckField, 23, 1, 1, // 2727: check Inst[23] == 0x1 |
| 4431 | OPC_Decode, 193, 9, 165, 1, // 2731: decode to MVE_VLD20_16_wb using decoder 165 |
| 4432 | // 2731: } |
| 4433 | 1, 11, // 2736: case 0x1: { |
| 4434 | OPC_CheckPredicate, 31, // 2738: check predicate 31 |
| 4435 | OPC_CheckField, 23, 1, 1, // 2740: check Inst[23] == 0x1 |
| 4436 | OPC_Decode, 205, 9, 166, 1, // 2744: decode to MVE_VLD40_16_wb using decoder 166 |
| 4437 | // 2744: } |
| 4438 | 32, 11, // 2749: case 0x20: { |
| 4439 | OPC_CheckPredicate, 31, // 2751: check predicate 31 |
| 4440 | OPC_CheckField, 23, 1, 1, // 2753: check Inst[23] == 0x1 |
| 4441 | OPC_Decode, 199, 9, 165, 1, // 2757: decode to MVE_VLD21_16_wb using decoder 165 |
| 4442 | // 2757: } |
| 4443 | 33, 11, // 2762: case 0x21: { |
| 4444 | OPC_CheckPredicate, 31, // 2764: check predicate 31 |
| 4445 | OPC_CheckField, 23, 1, 1, // 2766: check Inst[23] == 0x1 |
| 4446 | OPC_Decode, 211, 9, 166, 1, // 2770: decode to MVE_VLD41_16_wb using decoder 166 |
| 4447 | // 2770: } |
| 4448 | 65, 11, // 2775: case 0x41: { |
| 4449 | OPC_CheckPredicate, 31, // 2777: check predicate 31 |
| 4450 | OPC_CheckField, 23, 1, 1, // 2779: check Inst[23] == 0x1 |
| 4451 | OPC_Decode, 217, 9, 166, 1, // 2783: decode to MVE_VLD42_16_wb using decoder 166 |
| 4452 | // 2783: } |
| 4453 | 97, 0, // 2788: case 0x61: { |
| 4454 | OPC_CheckPredicate, 31, // 2790: check predicate 31 |
| 4455 | OPC_CheckField, 23, 1, 1, // 2792: check Inst[23] == 0x1 |
| 4456 | OPC_Decode, 223, 9, 166, 1, // 2796: decode to MVE_VLD43_16_wb using decoder 166 |
| 4457 | // 2796: } |
| 4458 | // 2796: } // switch Inst[6:0] |
| 4459 | // 2796: } |
| 4460 | // 2796: } // switch Inst[31:28] |
| 4461 | // 2796: } |
| 4462 | 1, 0, // 2801: case 0x1: { |
| 4463 | OPC_CheckPredicate, 31, // 2803: check predicate 31 |
| 4464 | OPC_CheckField, 28, 4, 14, // 2805: check Inst[31:28] == 0xe |
| 4465 | OPC_Decode, 131, 10, 164, 1, // 2809: decode to MVE_VLDRHU16_pre using decoder 164 |
| 4466 | // 2809: } |
| 4467 | // 2809: } // switch Inst[24] |
| 4468 | // 2809: } |
| 4469 | // 2809: } // switch Inst[7] |
| 4470 | // 2809: } |
| 4471 | // 2809: } // switch Inst[22:20] |
| 4472 | // 2809: } |
| 4473 | 31, 0, // 2814: case 0x1f: { |
| 4474 | OPC_SwitchField, 20, 3, // 2816: switch Inst[22:20] { |
| 4475 | 0, 145, 1, // 2819: case 0x0: { |
| 4476 | OPC_SwitchField, 24, 1, // 2822: switch Inst[24] { |
| 4477 | 0, 105, // 2825: case 0x0: { |
| 4478 | OPC_SwitchField, 0, 8, // 2827: switch Inst[7:0] { |
| 4479 | 0, 15, // 2830: case 0x0: { |
| 4480 | OPC_CheckPredicate, 31, // 2832: check predicate 31 |
| 4481 | OPC_CheckField, 28, 4, 15, // 2834: check Inst[31:28] == 0xf |
| 4482 | OPC_CheckField, 23, 1, 1, // 2838: check Inst[23] == 0x1 |
| 4483 | OPC_Decode, 235, 13, 151, 1, // 2842: decode to MVE_VST20_32 using decoder 151 |
| 4484 | // 2842: } |
| 4485 | 1, 15, // 2847: case 0x1: { |
| 4486 | OPC_CheckPredicate, 31, // 2849: check predicate 31 |
| 4487 | OPC_CheckField, 28, 4, 15, // 2851: check Inst[31:28] == 0xf |
| 4488 | OPC_CheckField, 23, 1, 1, // 2855: check Inst[23] == 0x1 |
| 4489 | OPC_Decode, 247, 13, 152, 1, // 2859: decode to MVE_VST40_32 using decoder 152 |
| 4490 | // 2859: } |
| 4491 | 32, 15, // 2864: case 0x20: { |
| 4492 | OPC_CheckPredicate, 31, // 2866: check predicate 31 |
| 4493 | OPC_CheckField, 28, 4, 15, // 2868: check Inst[31:28] == 0xf |
| 4494 | OPC_CheckField, 23, 1, 1, // 2872: check Inst[23] == 0x1 |
| 4495 | OPC_Decode, 241, 13, 151, 1, // 2876: decode to MVE_VST21_32 using decoder 151 |
| 4496 | // 2876: } |
| 4497 | 33, 15, // 2881: case 0x21: { |
| 4498 | OPC_CheckPredicate, 31, // 2883: check predicate 31 |
| 4499 | OPC_CheckField, 28, 4, 15, // 2885: check Inst[31:28] == 0xf |
| 4500 | OPC_CheckField, 23, 1, 1, // 2889: check Inst[23] == 0x1 |
| 4501 | OPC_Decode, 253, 13, 152, 1, // 2893: decode to MVE_VST41_32 using decoder 152 |
| 4502 | // 2893: } |
| 4503 | 65, 15, // 2898: case 0x41: { |
| 4504 | OPC_CheckPredicate, 31, // 2900: check predicate 31 |
| 4505 | OPC_CheckField, 28, 4, 15, // 2902: check Inst[31:28] == 0xf |
| 4506 | OPC_CheckField, 23, 1, 1, // 2906: check Inst[23] == 0x1 |
| 4507 | OPC_Decode, 131, 14, 152, 1, // 2910: decode to MVE_VST42_32 using decoder 152 |
| 4508 | // 2910: } |
| 4509 | 97, 0, // 2915: case 0x61: { |
| 4510 | OPC_CheckPredicate, 31, // 2917: check predicate 31 |
| 4511 | OPC_CheckField, 28, 4, 15, // 2919: check Inst[31:28] == 0xf |
| 4512 | OPC_CheckField, 23, 1, 1, // 2923: check Inst[23] == 0x1 |
| 4513 | OPC_Decode, 137, 14, 152, 1, // 2927: decode to MVE_VST43_32 using decoder 152 |
| 4514 | // 2927: } |
| 4515 | // 2927: } // switch Inst[7:0] |
| 4516 | // 2927: } |
| 4517 | 1, 0, // 2932: case 0x1: { |
| 4518 | OPC_SwitchField, 28, 4, // 2934: switch Inst[31:28] { |
| 4519 | 14, 11, // 2937: case 0xe: { |
| 4520 | OPC_CheckPredicate, 31, // 2939: check predicate 31 |
| 4521 | OPC_CheckField, 7, 1, 0, // 2941: check Inst[7] == 0x0 |
| 4522 | OPC_Decode, 171, 14, 167, 1, // 2945: decode to MVE_VSTRWU32 using decoder 167 |
| 4523 | // 2945: } |
| 4524 | 15, 0, // 2950: case 0xf: { |
| 4525 | OPC_CheckPredicate, 31, // 2952: check predicate 31 |
| 4526 | OPC_CheckField, 16, 1, 0, // 2954: check Inst[16] == 0x0 |
| 4527 | OPC_CheckField, 7, 1, 0, // 2958: check Inst[7] == 0x0 |
| 4528 | OPC_Decode, 153, 14, 168, 1, // 2962: decode to MVE_VSTRD64_qi using decoder 168 |
| 4529 | // 2962: } |
| 4530 | // 2962: } // switch Inst[31:28] |
| 4531 | // 2962: } |
| 4532 | // 2962: } // switch Inst[24] |
| 4533 | // 2962: } |
| 4534 | 1, 145, 1, // 2967: case 0x1: { |
| 4535 | OPC_SwitchField, 24, 1, // 2970: switch Inst[24] { |
| 4536 | 0, 105, // 2973: case 0x0: { |
| 4537 | OPC_SwitchField, 0, 8, // 2975: switch Inst[7:0] { |
| 4538 | 0, 15, // 2978: case 0x0: { |
| 4539 | OPC_CheckPredicate, 31, // 2980: check predicate 31 |
| 4540 | OPC_CheckField, 28, 4, 15, // 2982: check Inst[31:28] == 0xf |
| 4541 | OPC_CheckField, 23, 1, 1, // 2986: check Inst[23] == 0x1 |
| 4542 | OPC_Decode, 194, 9, 156, 1, // 2990: decode to MVE_VLD20_32 using decoder 156 |
| 4543 | // 2990: } |
| 4544 | 1, 15, // 2995: case 0x1: { |
| 4545 | OPC_CheckPredicate, 31, // 2997: check predicate 31 |
| 4546 | OPC_CheckField, 28, 4, 15, // 2999: check Inst[31:28] == 0xf |
| 4547 | OPC_CheckField, 23, 1, 1, // 3003: check Inst[23] == 0x1 |
| 4548 | OPC_Decode, 206, 9, 157, 1, // 3007: decode to MVE_VLD40_32 using decoder 157 |
| 4549 | // 3007: } |
| 4550 | 32, 15, // 3012: case 0x20: { |
| 4551 | OPC_CheckPredicate, 31, // 3014: check predicate 31 |
| 4552 | OPC_CheckField, 28, 4, 15, // 3016: check Inst[31:28] == 0xf |
| 4553 | OPC_CheckField, 23, 1, 1, // 3020: check Inst[23] == 0x1 |
| 4554 | OPC_Decode, 200, 9, 156, 1, // 3024: decode to MVE_VLD21_32 using decoder 156 |
| 4555 | // 3024: } |
| 4556 | 33, 15, // 3029: case 0x21: { |
| 4557 | OPC_CheckPredicate, 31, // 3031: check predicate 31 |
| 4558 | OPC_CheckField, 28, 4, 15, // 3033: check Inst[31:28] == 0xf |
| 4559 | OPC_CheckField, 23, 1, 1, // 3037: check Inst[23] == 0x1 |
| 4560 | OPC_Decode, 212, 9, 157, 1, // 3041: decode to MVE_VLD41_32 using decoder 157 |
| 4561 | // 3041: } |
| 4562 | 65, 15, // 3046: case 0x41: { |
| 4563 | OPC_CheckPredicate, 31, // 3048: check predicate 31 |
| 4564 | OPC_CheckField, 28, 4, 15, // 3050: check Inst[31:28] == 0xf |
| 4565 | OPC_CheckField, 23, 1, 1, // 3054: check Inst[23] == 0x1 |
| 4566 | OPC_Decode, 218, 9, 157, 1, // 3058: decode to MVE_VLD42_32 using decoder 157 |
| 4567 | // 3058: } |
| 4568 | 97, 0, // 3063: case 0x61: { |
| 4569 | OPC_CheckPredicate, 31, // 3065: check predicate 31 |
| 4570 | OPC_CheckField, 28, 4, 15, // 3067: check Inst[31:28] == 0xf |
| 4571 | OPC_CheckField, 23, 1, 1, // 3071: check Inst[23] == 0x1 |
| 4572 | OPC_Decode, 224, 9, 157, 1, // 3075: decode to MVE_VLD43_32 using decoder 157 |
| 4573 | // 3075: } |
| 4574 | // 3075: } // switch Inst[7:0] |
| 4575 | // 3075: } |
| 4576 | 1, 0, // 3080: case 0x1: { |
| 4577 | OPC_SwitchField, 28, 4, // 3082: switch Inst[31:28] { |
| 4578 | 14, 11, // 3085: case 0xe: { |
| 4579 | OPC_CheckPredicate, 31, // 3087: check predicate 31 |
| 4580 | OPC_CheckField, 7, 1, 0, // 3089: check Inst[7] == 0x0 |
| 4581 | OPC_Decode, 139, 10, 167, 1, // 3093: decode to MVE_VLDRWU32 using decoder 167 |
| 4582 | // 3093: } |
| 4583 | 15, 0, // 3098: case 0xf: { |
| 4584 | OPC_CheckPredicate, 31, // 3100: check predicate 31 |
| 4585 | OPC_CheckField, 16, 1, 0, // 3102: check Inst[16] == 0x0 |
| 4586 | OPC_CheckField, 7, 1, 0, // 3106: check Inst[7] == 0x0 |
| 4587 | OPC_Decode, 248, 9, 168, 1, // 3110: decode to MVE_VLDRDU64_qi using decoder 168 |
| 4588 | // 3110: } |
| 4589 | // 3110: } // switch Inst[31:28] |
| 4590 | // 3110: } |
| 4591 | // 3110: } // switch Inst[24] |
| 4592 | // 3110: } |
| 4593 | 2, 139, 1, // 3115: case 0x2: { |
| 4594 | OPC_SwitchField, 24, 1, // 3118: switch Inst[24] { |
| 4595 | 0, 99, // 3121: case 0x0: { |
| 4596 | OPC_SwitchField, 28, 4, // 3123: switch Inst[31:28] { |
| 4597 | 14, 11, // 3126: case 0xe: { |
| 4598 | OPC_CheckPredicate, 31, // 3128: check predicate 31 |
| 4599 | OPC_CheckField, 7, 1, 0, // 3130: check Inst[7] == 0x0 |
| 4600 | OPC_Decode, 172, 14, 169, 1, // 3134: decode to MVE_VSTRWU32_post using decoder 169 |
| 4601 | // 3134: } |
| 4602 | 15, 0, // 3139: case 0xf: { |
| 4603 | OPC_SwitchField, 0, 8, // 3141: switch Inst[7:0] { |
| 4604 | 0, 11, // 3144: case 0x0: { |
| 4605 | OPC_CheckPredicate, 31, // 3146: check predicate 31 |
| 4606 | OPC_CheckField, 23, 1, 1, // 3148: check Inst[23] == 0x1 |
| 4607 | OPC_Decode, 236, 13, 159, 1, // 3152: decode to MVE_VST20_32_wb using decoder 159 |
| 4608 | // 3152: } |
| 4609 | 1, 11, // 3157: case 0x1: { |
| 4610 | OPC_CheckPredicate, 31, // 3159: check predicate 31 |
| 4611 | OPC_CheckField, 23, 1, 1, // 3161: check Inst[23] == 0x1 |
| 4612 | OPC_Decode, 248, 13, 160, 1, // 3165: decode to MVE_VST40_32_wb using decoder 160 |
| 4613 | // 3165: } |
| 4614 | 32, 11, // 3170: case 0x20: { |
| 4615 | OPC_CheckPredicate, 31, // 3172: check predicate 31 |
| 4616 | OPC_CheckField, 23, 1, 1, // 3174: check Inst[23] == 0x1 |
| 4617 | OPC_Decode, 242, 13, 159, 1, // 3178: decode to MVE_VST21_32_wb using decoder 159 |
| 4618 | // 3178: } |
| 4619 | 33, 11, // 3183: case 0x21: { |
| 4620 | OPC_CheckPredicate, 31, // 3185: check predicate 31 |
| 4621 | OPC_CheckField, 23, 1, 1, // 3187: check Inst[23] == 0x1 |
| 4622 | OPC_Decode, 254, 13, 160, 1, // 3191: decode to MVE_VST41_32_wb using decoder 160 |
| 4623 | // 3191: } |
| 4624 | 65, 11, // 3196: case 0x41: { |
| 4625 | OPC_CheckPredicate, 31, // 3198: check predicate 31 |
| 4626 | OPC_CheckField, 23, 1, 1, // 3200: check Inst[23] == 0x1 |
| 4627 | OPC_Decode, 132, 14, 160, 1, // 3204: decode to MVE_VST42_32_wb using decoder 160 |
| 4628 | // 3204: } |
| 4629 | 97, 0, // 3209: case 0x61: { |
| 4630 | OPC_CheckPredicate, 31, // 3211: check predicate 31 |
| 4631 | OPC_CheckField, 23, 1, 1, // 3213: check Inst[23] == 0x1 |
| 4632 | OPC_Decode, 138, 14, 160, 1, // 3217: decode to MVE_VST43_32_wb using decoder 160 |
| 4633 | // 3217: } |
| 4634 | // 3217: } // switch Inst[7:0] |
| 4635 | // 3217: } |
| 4636 | // 3217: } // switch Inst[31:28] |
| 4637 | // 3217: } |
| 4638 | 1, 0, // 3222: case 0x1: { |
| 4639 | OPC_SwitchField, 28, 4, // 3224: switch Inst[31:28] { |
| 4640 | 14, 11, // 3227: case 0xe: { |
| 4641 | OPC_CheckPredicate, 31, // 3229: check predicate 31 |
| 4642 | OPC_CheckField, 7, 1, 0, // 3231: check Inst[7] == 0x0 |
| 4643 | OPC_Decode, 173, 14, 170, 1, // 3235: decode to MVE_VSTRWU32_pre using decoder 170 |
| 4644 | // 3235: } |
| 4645 | 15, 0, // 3240: case 0xf: { |
| 4646 | OPC_CheckPredicate, 31, // 3242: check predicate 31 |
| 4647 | OPC_CheckField, 16, 1, 0, // 3244: check Inst[16] == 0x0 |
| 4648 | OPC_CheckField, 7, 1, 0, // 3248: check Inst[7] == 0x0 |
| 4649 | OPC_Decode, 154, 14, 171, 1, // 3252: decode to MVE_VSTRD64_qi_pre using decoder 171 |
| 4650 | // 3252: } |
| 4651 | // 3252: } // switch Inst[31:28] |
| 4652 | // 3252: } |
| 4653 | // 3252: } // switch Inst[24] |
| 4654 | // 3252: } |
| 4655 | 3, 0, // 3257: case 0x3: { |
| 4656 | OPC_SwitchField, 24, 1, // 3259: switch Inst[24] { |
| 4657 | 0, 99, // 3262: case 0x0: { |
| 4658 | OPC_SwitchField, 28, 4, // 3264: switch Inst[31:28] { |
| 4659 | 14, 11, // 3267: case 0xe: { |
| 4660 | OPC_CheckPredicate, 31, // 3269: check predicate 31 |
| 4661 | OPC_CheckField, 7, 1, 0, // 3271: check Inst[7] == 0x0 |
| 4662 | OPC_Decode, 140, 10, 169, 1, // 3275: decode to MVE_VLDRWU32_post using decoder 169 |
| 4663 | // 3275: } |
| 4664 | 15, 0, // 3280: case 0xf: { |
| 4665 | OPC_SwitchField, 0, 8, // 3282: switch Inst[7:0] { |
| 4666 | 0, 11, // 3285: case 0x0: { |
| 4667 | OPC_CheckPredicate, 31, // 3287: check predicate 31 |
| 4668 | OPC_CheckField, 23, 1, 1, // 3289: check Inst[23] == 0x1 |
| 4669 | OPC_Decode, 195, 9, 165, 1, // 3293: decode to MVE_VLD20_32_wb using decoder 165 |
| 4670 | // 3293: } |
| 4671 | 1, 11, // 3298: case 0x1: { |
| 4672 | OPC_CheckPredicate, 31, // 3300: check predicate 31 |
| 4673 | OPC_CheckField, 23, 1, 1, // 3302: check Inst[23] == 0x1 |
| 4674 | OPC_Decode, 207, 9, 166, 1, // 3306: decode to MVE_VLD40_32_wb using decoder 166 |
| 4675 | // 3306: } |
| 4676 | 32, 11, // 3311: case 0x20: { |
| 4677 | OPC_CheckPredicate, 31, // 3313: check predicate 31 |
| 4678 | OPC_CheckField, 23, 1, 1, // 3315: check Inst[23] == 0x1 |
| 4679 | OPC_Decode, 201, 9, 165, 1, // 3319: decode to MVE_VLD21_32_wb using decoder 165 |
| 4680 | // 3319: } |
| 4681 | 33, 11, // 3324: case 0x21: { |
| 4682 | OPC_CheckPredicate, 31, // 3326: check predicate 31 |
| 4683 | OPC_CheckField, 23, 1, 1, // 3328: check Inst[23] == 0x1 |
| 4684 | OPC_Decode, 213, 9, 166, 1, // 3332: decode to MVE_VLD41_32_wb using decoder 166 |
| 4685 | // 3332: } |
| 4686 | 65, 11, // 3337: case 0x41: { |
| 4687 | OPC_CheckPredicate, 31, // 3339: check predicate 31 |
| 4688 | OPC_CheckField, 23, 1, 1, // 3341: check Inst[23] == 0x1 |
| 4689 | OPC_Decode, 219, 9, 166, 1, // 3345: decode to MVE_VLD42_32_wb using decoder 166 |
| 4690 | // 3345: } |
| 4691 | 97, 0, // 3350: case 0x61: { |
| 4692 | OPC_CheckPredicate, 31, // 3352: check predicate 31 |
| 4693 | OPC_CheckField, 23, 1, 1, // 3354: check Inst[23] == 0x1 |
| 4694 | OPC_Decode, 225, 9, 166, 1, // 3358: decode to MVE_VLD43_32_wb using decoder 166 |
| 4695 | // 3358: } |
| 4696 | // 3358: } // switch Inst[7:0] |
| 4697 | // 3358: } |
| 4698 | // 3358: } // switch Inst[31:28] |
| 4699 | // 3358: } |
| 4700 | 1, 0, // 3363: case 0x1: { |
| 4701 | OPC_SwitchField, 28, 4, // 3365: switch Inst[31:28] { |
| 4702 | 14, 11, // 3368: case 0xe: { |
| 4703 | OPC_CheckPredicate, 31, // 3370: check predicate 31 |
| 4704 | OPC_CheckField, 7, 1, 0, // 3372: check Inst[7] == 0x0 |
| 4705 | OPC_Decode, 141, 10, 170, 1, // 3376: decode to MVE_VLDRWU32_pre using decoder 170 |
| 4706 | // 3376: } |
| 4707 | 15, 0, // 3381: case 0xf: { |
| 4708 | OPC_CheckPredicate, 31, // 3383: check predicate 31 |
| 4709 | OPC_CheckField, 16, 1, 0, // 3385: check Inst[16] == 0x0 |
| 4710 | OPC_CheckField, 7, 1, 0, // 3389: check Inst[7] == 0x0 |
| 4711 | OPC_Decode, 249, 9, 171, 1, // 3393: decode to MVE_VLDRDU64_qi_pre using decoder 171 |
| 4712 | // 3393: } |
| 4713 | // 3393: } // switch Inst[31:28] |
| 4714 | // 3393: } |
| 4715 | // 3393: } // switch Inst[24] |
| 4716 | // 3393: } |
| 4717 | // 3393: } // switch Inst[22:20] |
| 4718 | // 3393: } |
| 4719 | // 3393: } // switch Inst[12:8] |
| 4720 | // 3393: } |
| 4721 | 7, 0, // 3398: case 0x7: { |
| 4722 | OPC_SwitchField, 23, 2, // 3400: switch Inst[24:23] { |
| 4723 | 0, 160, 35, // 3403: case 0x0: { |
| 4724 | OPC_SwitchField, 8, 4, // 3406: switch Inst[11:8] { |
| 4725 | 11, 117, // 3409: case 0xb: { |
| 4726 | OPC_SwitchField, 20, 1, // 3411: switch Inst[20] { |
| 4727 | 0, 55, // 3414: case 0x0: { |
| 4728 | OPC_SwitchField, 22, 1, // 3416: switch Inst[22] { |
| 4729 | 0, 33, // 3419: case 0x0: { |
| 4730 | OPC_SwitchField, 0, 6, // 3421: switch Inst[5:0] { |
| 4731 | 16, 15, // 3424: case 0x10: { |
| 4732 | OPC_CheckPredicate, 34, // 3426: check predicate 34 |
| 4733 | OPC_CheckField, 28, 4, 14, // 3428: check Inst[31:28] == 0xe |
| 4734 | OPC_CheckField, 6, 1, 0, // 3432: check Inst[6] == 0x0 |
| 4735 | OPC_Decode, 146, 11, 172, 1, // 3436: decode to MVE_VMOV_to_lane_32 using decoder 172 |
| 4736 | // 3436: } |
| 4737 | 48, 0, // 3441: case 0x30: { |
| 4738 | OPC_CheckPredicate, 32, // 3443: check predicate 32 |
| 4739 | OPC_CheckField, 28, 4, 14, // 3445: check Inst[31:28] == 0xe |
| 4740 | OPC_Decode, 145, 11, 173, 1, // 3449: decode to MVE_VMOV_to_lane_16 using decoder 173 |
| 4741 | // 3449: } |
| 4742 | // 3449: } // switch Inst[5:0] |
| 4743 | // 3449: } |
| 4744 | 1, 0, // 3454: case 0x1: { |
| 4745 | OPC_CheckPredicate, 32, // 3456: check predicate 32 |
| 4746 | OPC_CheckField, 28, 4, 14, // 3458: check Inst[31:28] == 0xe |
| 4747 | OPC_CheckField, 0, 5, 16, // 3462: check Inst[4:0] == 0x10 |
| 4748 | OPC_Decode, 147, 11, 174, 1, // 3466: decode to MVE_VMOV_to_lane_8 using decoder 174 |
| 4749 | // 3466: } |
| 4750 | // 3466: } // switch Inst[22] |
| 4751 | // 3466: } |
| 4752 | 1, 0, // 3471: case 0x1: { |
| 4753 | OPC_SwitchField, 22, 1, // 3473: switch Inst[22] { |
| 4754 | 0, 33, // 3476: case 0x0: { |
| 4755 | OPC_SwitchField, 0, 6, // 3478: switch Inst[5:0] { |
| 4756 | 16, 15, // 3481: case 0x10: { |
| 4757 | OPC_CheckPredicate, 34, // 3483: check predicate 34 |
| 4758 | OPC_CheckField, 28, 4, 14, // 3485: check Inst[31:28] == 0xe |
| 4759 | OPC_CheckField, 6, 1, 0, // 3489: check Inst[6] == 0x0 |
| 4760 | OPC_Decode, 138, 11, 175, 1, // 3493: decode to MVE_VMOV_from_lane_32 using decoder 175 |
| 4761 | // 3493: } |
| 4762 | 48, 0, // 3498: case 0x30: { |
| 4763 | OPC_CheckPredicate, 32, // 3500: check predicate 32 |
| 4764 | OPC_CheckField, 28, 4, 14, // 3502: check Inst[31:28] == 0xe |
| 4765 | OPC_Decode, 139, 11, 176, 1, // 3506: decode to MVE_VMOV_from_lane_s16 using decoder 176 |
| 4766 | // 3506: } |
| 4767 | // 3506: } // switch Inst[5:0] |
| 4768 | // 3506: } |
| 4769 | 1, 0, // 3511: case 0x1: { |
| 4770 | OPC_CheckPredicate, 32, // 3513: check predicate 32 |
| 4771 | OPC_CheckField, 28, 4, 14, // 3515: check Inst[31:28] == 0xe |
| 4772 | OPC_CheckField, 0, 5, 16, // 3519: check Inst[4:0] == 0x10 |
| 4773 | OPC_Decode, 140, 11, 177, 1, // 3523: decode to MVE_VMOV_from_lane_s8 using decoder 177 |
| 4774 | // 3523: } |
| 4775 | // 3523: } // switch Inst[22] |
| 4776 | // 3523: } |
| 4777 | // 3523: } // switch Inst[20] |
| 4778 | // 3523: } |
| 4779 | 14, 147, 20, // 3528: case 0xe: { |
| 4780 | OPC_SwitchField, 20, 2, // 3531: switch Inst[21:20] { |
| 4781 | 0, 191, 3, // 3534: case 0x0: { |
| 4782 | OPC_SwitchField, 6, 1, // 3537: switch Inst[6] { |
| 4783 | 0, 154, 2, // 3540: case 0x0: { |
| 4784 | OPC_SwitchField, 0, 1, // 3543: switch Inst[0] { |
| 4785 | 0, 137, 1, // 3546: case 0x0: { |
| 4786 | OPC_SwitchField, 12, 1, // 3549: switch Inst[12] { |
| 4787 | 0, 65, // 3552: case 0x0: { |
| 4788 | OPC_SwitchField, 16, 1, // 3554: switch Inst[16] { |
| 4789 | 0, 29, // 3557: case 0x0: { |
| 4790 | OPC_SwitchField, 28, 4, // 3559: switch Inst[31:28] { |
| 4791 | 14, 11, // 3562: case 0xe: { |
| 4792 | OPC_CheckPredicate, 31, // 3564: check predicate 31 |
| 4793 | OPC_CheckField, 4, 1, 0, // 3566: check Inst[4] == 0x0 |
| 4794 | OPC_Decode, 242, 11, 178, 1, // 3570: decode to MVE_VQDMLADHs8 using decoder 178 |
| 4795 | // 3570: } |
| 4796 | 15, 0, // 3575: case 0xf: { |
| 4797 | OPC_CheckPredicate, 31, // 3577: check predicate 31 |
| 4798 | OPC_CheckField, 4, 1, 0, // 3579: check Inst[4] == 0x0 |
| 4799 | OPC_Decode, 254, 11, 178, 1, // 3583: decode to MVE_VQDMLSDHs8 using decoder 178 |
| 4800 | // 3583: } |
| 4801 | // 3583: } // switch Inst[31:28] |
| 4802 | // 3583: } |
| 4803 | 1, 0, // 3588: case 0x1: { |
| 4804 | OPC_SwitchField, 28, 4, // 3590: switch Inst[31:28] { |
| 4805 | 14, 11, // 3593: case 0xe: { |
| 4806 | OPC_CheckPredicate, 31, // 3595: check predicate 31 |
| 4807 | OPC_CheckField, 4, 1, 0, // 3597: check Inst[4] == 0x0 |
| 4808 | OPC_Decode, 163, 11, 179, 1, // 3601: decode to MVE_VMULLBs8 using decoder 179 |
| 4809 | // 3601: } |
| 4810 | 15, 0, // 3606: case 0xf: { |
| 4811 | OPC_CheckPredicate, 31, // 3608: check predicate 31 |
| 4812 | OPC_CheckField, 4, 1, 0, // 3610: check Inst[4] == 0x0 |
| 4813 | OPC_Decode, 166, 11, 179, 1, // 3614: decode to MVE_VMULLBu8 using decoder 179 |
| 4814 | // 3614: } |
| 4815 | // 3614: } // switch Inst[31:28] |
| 4816 | // 3614: } |
| 4817 | // 3614: } // switch Inst[16] |
| 4818 | // 3614: } |
| 4819 | 1, 0, // 3619: case 0x1: { |
| 4820 | OPC_SwitchField, 16, 1, // 3621: switch Inst[16] { |
| 4821 | 0, 29, // 3624: case 0x0: { |
| 4822 | OPC_SwitchField, 28, 4, // 3626: switch Inst[31:28] { |
| 4823 | 14, 11, // 3629: case 0xe: { |
| 4824 | OPC_CheckPredicate, 31, // 3631: check predicate 31 |
| 4825 | OPC_CheckField, 4, 1, 0, // 3633: check Inst[4] == 0x0 |
| 4826 | OPC_Decode, 239, 11, 178, 1, // 3637: decode to MVE_VQDMLADHXs8 using decoder 178 |
| 4827 | // 3637: } |
| 4828 | 15, 0, // 3642: case 0xf: { |
| 4829 | OPC_CheckPredicate, 31, // 3644: check predicate 31 |
| 4830 | OPC_CheckField, 4, 1, 0, // 3646: check Inst[4] == 0x0 |
| 4831 | OPC_Decode, 251, 11, 178, 1, // 3650: decode to MVE_VQDMLSDHXs8 using decoder 178 |
| 4832 | // 3650: } |
| 4833 | // 3650: } // switch Inst[31:28] |
| 4834 | // 3650: } |
| 4835 | 1, 0, // 3655: case 0x1: { |
| 4836 | OPC_SwitchField, 28, 4, // 3657: switch Inst[31:28] { |
| 4837 | 14, 11, // 3660: case 0xe: { |
| 4838 | OPC_CheckPredicate, 31, // 3662: check predicate 31 |
| 4839 | OPC_CheckField, 4, 1, 0, // 3664: check Inst[4] == 0x0 |
| 4840 | OPC_Decode, 171, 11, 179, 1, // 3668: decode to MVE_VMULLTs8 using decoder 179 |
| 4841 | // 3668: } |
| 4842 | 15, 0, // 3673: case 0xf: { |
| 4843 | OPC_CheckPredicate, 31, // 3675: check predicate 31 |
| 4844 | OPC_CheckField, 4, 1, 0, // 3677: check Inst[4] == 0x0 |
| 4845 | OPC_Decode, 174, 11, 179, 1, // 3681: decode to MVE_VMULLTu8 using decoder 179 |
| 4846 | // 3681: } |
| 4847 | // 3681: } // switch Inst[31:28] |
| 4848 | // 3681: } |
| 4849 | // 3681: } // switch Inst[16] |
| 4850 | // 3681: } |
| 4851 | // 3681: } // switch Inst[12] |
| 4852 | // 3681: } |
| 4853 | 1, 0, // 3686: case 0x1: { |
| 4854 | OPC_SwitchField, 12, 1, // 3688: switch Inst[12] { |
| 4855 | 0, 65, // 3691: case 0x0: { |
| 4856 | OPC_SwitchField, 16, 1, // 3693: switch Inst[16] { |
| 4857 | 0, 29, // 3696: case 0x0: { |
| 4858 | OPC_SwitchField, 28, 4, // 3698: switch Inst[31:28] { |
| 4859 | 14, 11, // 3701: case 0xe: { |
| 4860 | OPC_CheckPredicate, 31, // 3703: check predicate 31 |
| 4861 | OPC_CheckField, 4, 1, 0, // 3705: check Inst[4] == 0x0 |
| 4862 | OPC_Decode, 161, 12, 178, 1, // 3709: decode to MVE_VQRDMLADHs8 using decoder 178 |
| 4863 | // 3709: } |
| 4864 | 15, 0, // 3714: case 0xf: { |
| 4865 | OPC_CheckPredicate, 31, // 3716: check predicate 31 |
| 4866 | OPC_CheckField, 4, 1, 0, // 3718: check Inst[4] == 0x0 |
| 4867 | OPC_Decode, 173, 12, 178, 1, // 3722: decode to MVE_VQRDMLSDHs8 using decoder 178 |
| 4868 | // 3722: } |
| 4869 | // 3722: } // switch Inst[31:28] |
| 4870 | // 3722: } |
| 4871 | 1, 0, // 3727: case 0x1: { |
| 4872 | OPC_SwitchField, 28, 4, // 3729: switch Inst[31:28] { |
| 4873 | 14, 11, // 3732: case 0xe: { |
| 4874 | OPC_CheckPredicate, 31, // 3734: check predicate 31 |
| 4875 | OPC_CheckField, 4, 1, 0, // 3736: check Inst[4] == 0x0 |
| 4876 | OPC_Decode, 155, 11, 179, 1, // 3740: decode to MVE_VMULHs8 using decoder 179 |
| 4877 | // 3740: } |
| 4878 | 15, 0, // 3745: case 0xf: { |
| 4879 | OPC_CheckPredicate, 31, // 3747: check predicate 31 |
| 4880 | OPC_CheckField, 4, 1, 0, // 3749: check Inst[4] == 0x0 |
| 4881 | OPC_Decode, 158, 11, 179, 1, // 3753: decode to MVE_VMULHu8 using decoder 179 |
| 4882 | // 3753: } |
| 4883 | // 3753: } // switch Inst[31:28] |
| 4884 | // 3753: } |
| 4885 | // 3753: } // switch Inst[16] |
| 4886 | // 3753: } |
| 4887 | 1, 0, // 3758: case 0x1: { |
| 4888 | OPC_SwitchField, 16, 1, // 3760: switch Inst[16] { |
| 4889 | 0, 29, // 3763: case 0x0: { |
| 4890 | OPC_SwitchField, 28, 4, // 3765: switch Inst[31:28] { |
| 4891 | 14, 11, // 3768: case 0xe: { |
| 4892 | OPC_CheckPredicate, 31, // 3770: check predicate 31 |
| 4893 | OPC_CheckField, 4, 1, 0, // 3772: check Inst[4] == 0x0 |
| 4894 | OPC_Decode, 158, 12, 178, 1, // 3776: decode to MVE_VQRDMLADHXs8 using decoder 178 |
| 4895 | // 3776: } |
| 4896 | 15, 0, // 3781: case 0xf: { |
| 4897 | OPC_CheckPredicate, 31, // 3783: check predicate 31 |
| 4898 | OPC_CheckField, 4, 1, 0, // 3785: check Inst[4] == 0x0 |
| 4899 | OPC_Decode, 170, 12, 178, 1, // 3789: decode to MVE_VQRDMLSDHXs8 using decoder 178 |
| 4900 | // 3789: } |
| 4901 | // 3789: } // switch Inst[31:28] |
| 4902 | // 3789: } |
| 4903 | 1, 0, // 3794: case 0x1: { |
| 4904 | OPC_SwitchField, 28, 4, // 3796: switch Inst[31:28] { |
| 4905 | 14, 11, // 3799: case 0xe: { |
| 4906 | OPC_CheckPredicate, 31, // 3801: check predicate 31 |
| 4907 | OPC_CheckField, 4, 1, 0, // 3803: check Inst[4] == 0x0 |
| 4908 | OPC_Decode, 157, 13, 179, 1, // 3807: decode to MVE_VRMULHs8 using decoder 179 |
| 4909 | // 3807: } |
| 4910 | 15, 0, // 3812: case 0xf: { |
| 4911 | OPC_CheckPredicate, 31, // 3814: check predicate 31 |
| 4912 | OPC_CheckField, 4, 1, 0, // 3816: check Inst[4] == 0x0 |
| 4913 | OPC_Decode, 160, 13, 179, 1, // 3820: decode to MVE_VRMULHu8 using decoder 179 |
| 4914 | // 3820: } |
| 4915 | // 3820: } // switch Inst[31:28] |
| 4916 | // 3820: } |
| 4917 | // 3820: } // switch Inst[16] |
| 4918 | // 3820: } |
| 4919 | // 3820: } // switch Inst[12] |
| 4920 | // 3820: } |
| 4921 | // 3820: } // switch Inst[0] |
| 4922 | // 3820: } |
| 4923 | 1, 0, // 3825: case 0x1: { |
| 4924 | OPC_SwitchField, 4, 2, // 3827: switch Inst[5:4] { |
| 4925 | 0, 65, // 3830: case 0x0: { |
| 4926 | OPC_SwitchField, 12, 1, // 3832: switch Inst[12] { |
| 4927 | 0, 29, // 3835: case 0x0: { |
| 4928 | OPC_SwitchField, 16, 1, // 3837: switch Inst[16] { |
| 4929 | 0, 11, // 3840: case 0x0: { |
| 4930 | OPC_CheckPredicate, 31, // 3842: check predicate 31 |
| 4931 | OPC_CheckField, 28, 4, 14, // 3844: check Inst[31:28] == 0xe |
| 4932 | OPC_Decode, 164, 12, 180, 1, // 3848: decode to MVE_VQRDMLAH_qrs8 using decoder 180 |
| 4933 | // 3848: } |
| 4934 | 1, 0, // 3853: case 0x1: { |
| 4935 | OPC_CheckPredicate, 31, // 3855: check predicate 31 |
| 4936 | OPC_CheckField, 28, 4, 14, // 3857: check Inst[31:28] == 0xe |
| 4937 | OPC_Decode, 233, 10, 180, 1, // 3861: decode to MVE_VMLA_qr_i8 using decoder 180 |
| 4938 | // 3861: } |
| 4939 | // 3861: } // switch Inst[16] |
| 4940 | // 3861: } |
| 4941 | 1, 0, // 3866: case 0x1: { |
| 4942 | OPC_SwitchField, 16, 1, // 3868: switch Inst[16] { |
| 4943 | 0, 11, // 3871: case 0x0: { |
| 4944 | OPC_CheckPredicate, 31, // 3873: check predicate 31 |
| 4945 | OPC_CheckField, 28, 4, 14, // 3875: check Inst[31:28] == 0xe |
| 4946 | OPC_Decode, 167, 12, 180, 1, // 3879: decode to MVE_VQRDMLASH_qrs8 using decoder 180 |
| 4947 | // 3879: } |
| 4948 | 1, 0, // 3884: case 0x1: { |
| 4949 | OPC_CheckPredicate, 31, // 3886: check predicate 31 |
| 4950 | OPC_CheckField, 28, 4, 14, // 3888: check Inst[31:28] == 0xe |
| 4951 | OPC_Decode, 230, 10, 180, 1, // 3892: decode to MVE_VMLAS_qr_i8 using decoder 180 |
| 4952 | // 3892: } |
| 4953 | // 3892: } // switch Inst[16] |
| 4954 | // 3892: } |
| 4955 | // 3892: } // switch Inst[12] |
| 4956 | // 3892: } |
| 4957 | 2, 0, // 3897: case 0x2: { |
| 4958 | OPC_SwitchField, 12, 1, // 3899: switch Inst[12] { |
| 4959 | 0, 39, // 3902: case 0x0: { |
| 4960 | OPC_SwitchField, 16, 1, // 3904: switch Inst[16] { |
| 4961 | 0, 11, // 3907: case 0x0: { |
| 4962 | OPC_CheckPredicate, 31, // 3909: check predicate 31 |
| 4963 | OPC_CheckField, 28, 4, 14, // 3911: check Inst[31:28] == 0xe |
| 4964 | OPC_Decode, 245, 11, 180, 1, // 3915: decode to MVE_VQDMLAH_qrs8 using decoder 180 |
| 4965 | // 3915: } |
| 4966 | 1, 0, // 3920: case 0x1: { |
| 4967 | OPC_SwitchField, 28, 4, // 3922: switch Inst[31:28] { |
| 4968 | 14, 7, // 3925: case 0xe: { |
| 4969 | OPC_CheckPredicate, 31, // 3927: check predicate 31 |
| 4970 | OPC_Decode, 129, 12, 181, 1, // 3929: decode to MVE_VQDMULH_qr_s8 using decoder 181 |
| 4971 | // 3929: } |
| 4972 | 15, 0, // 3934: case 0xf: { |
| 4973 | OPC_CheckPredicate, 31, // 3936: check predicate 31 |
| 4974 | OPC_Decode, 176, 12, 181, 1, // 3938: decode to MVE_VQRDMULH_qr_s8 using decoder 181 |
| 4975 | // 3938: } |
| 4976 | // 3938: } // switch Inst[31:28] |
| 4977 | // 3938: } |
| 4978 | // 3938: } // switch Inst[16] |
| 4979 | // 3938: } |
| 4980 | 1, 0, // 3943: case 0x1: { |
| 4981 | OPC_SwitchField, 16, 1, // 3945: switch Inst[16] { |
| 4982 | 0, 11, // 3948: case 0x0: { |
| 4983 | OPC_CheckPredicate, 31, // 3950: check predicate 31 |
| 4984 | OPC_CheckField, 28, 4, 14, // 3952: check Inst[31:28] == 0xe |
| 4985 | OPC_Decode, 248, 11, 180, 1, // 3956: decode to MVE_VQDMLASH_qrs8 using decoder 180 |
| 4986 | // 3956: } |
| 4987 | 1, 0, // 3961: case 0x1: { |
| 4988 | OPC_SwitchField, 28, 4, // 3963: switch Inst[31:28] { |
| 4989 | 14, 7, // 3966: case 0xe: { |
| 4990 | OPC_CheckPredicate, 31, // 3968: check predicate 31 |
| 4991 | OPC_Decode, 179, 11, 181, 1, // 3970: decode to MVE_VMUL_qr_i8 using decoder 181 |
| 4992 | // 3970: } |
| 4993 | 15, 0, // 3975: case 0xf: { |
| 4994 | OPC_CheckPredicate, 31, // 3977: check predicate 31 |
| 4995 | OPC_Decode, 191, 8, 181, 1, // 3979: decode to MVE_VBRSR8 using decoder 181 |
| 4996 | // 3979: } |
| 4997 | // 3979: } // switch Inst[31:28] |
| 4998 | // 3979: } |
| 4999 | // 3979: } // switch Inst[16] |
| 5000 | // 3979: } |
| 5001 | // 3979: } // switch Inst[12] |
| 5002 | // 3979: } |
| 5003 | // 3979: } // switch Inst[5:4] |
| 5004 | // 3979: } |
| 5005 | // 3979: } // switch Inst[6] |
| 5006 | // 3979: } |
| 5007 | 1, 191, 3, // 3984: case 0x1: { |
| 5008 | OPC_SwitchField, 6, 1, // 3987: switch Inst[6] { |
| 5009 | 0, 154, 2, // 3990: case 0x0: { |
| 5010 | OPC_SwitchField, 0, 1, // 3993: switch Inst[0] { |
| 5011 | 0, 137, 1, // 3996: case 0x0: { |
| 5012 | OPC_SwitchField, 12, 1, // 3999: switch Inst[12] { |
| 5013 | 0, 65, // 4002: case 0x0: { |
| 5014 | OPC_SwitchField, 16, 1, // 4004: switch Inst[16] { |
| 5015 | 0, 29, // 4007: case 0x0: { |
| 5016 | OPC_SwitchField, 28, 4, // 4009: switch Inst[31:28] { |
| 5017 | 14, 11, // 4012: case 0xe: { |
| 5018 | OPC_CheckPredicate, 31, // 4014: check predicate 31 |
| 5019 | OPC_CheckField, 4, 1, 0, // 4016: check Inst[4] == 0x0 |
| 5020 | OPC_Decode, 240, 11, 178, 1, // 4020: decode to MVE_VQDMLADHs16 using decoder 178 |
| 5021 | // 4020: } |
| 5022 | 15, 0, // 4025: case 0xf: { |
| 5023 | OPC_CheckPredicate, 31, // 4027: check predicate 31 |
| 5024 | OPC_CheckField, 4, 1, 0, // 4029: check Inst[4] == 0x0 |
| 5025 | OPC_Decode, 252, 11, 178, 1, // 4033: decode to MVE_VQDMLSDHs16 using decoder 178 |
| 5026 | // 4033: } |
| 5027 | // 4033: } // switch Inst[31:28] |
| 5028 | // 4033: } |
| 5029 | 1, 0, // 4038: case 0x1: { |
| 5030 | OPC_SwitchField, 28, 4, // 4040: switch Inst[31:28] { |
| 5031 | 14, 11, // 4043: case 0xe: { |
| 5032 | OPC_CheckPredicate, 31, // 4045: check predicate 31 |
| 5033 | OPC_CheckField, 4, 1, 0, // 4047: check Inst[4] == 0x0 |
| 5034 | OPC_Decode, 161, 11, 179, 1, // 4051: decode to MVE_VMULLBs16 using decoder 179 |
| 5035 | // 4051: } |
| 5036 | 15, 0, // 4056: case 0xf: { |
| 5037 | OPC_CheckPredicate, 31, // 4058: check predicate 31 |
| 5038 | OPC_CheckField, 4, 1, 0, // 4060: check Inst[4] == 0x0 |
| 5039 | OPC_Decode, 164, 11, 179, 1, // 4064: decode to MVE_VMULLBu16 using decoder 179 |
| 5040 | // 4064: } |
| 5041 | // 4064: } // switch Inst[31:28] |
| 5042 | // 4064: } |
| 5043 | // 4064: } // switch Inst[16] |
| 5044 | // 4064: } |
| 5045 | 1, 0, // 4069: case 0x1: { |
| 5046 | OPC_SwitchField, 16, 1, // 4071: switch Inst[16] { |
| 5047 | 0, 29, // 4074: case 0x0: { |
| 5048 | OPC_SwitchField, 28, 4, // 4076: switch Inst[31:28] { |
| 5049 | 14, 11, // 4079: case 0xe: { |
| 5050 | OPC_CheckPredicate, 31, // 4081: check predicate 31 |
| 5051 | OPC_CheckField, 4, 1, 0, // 4083: check Inst[4] == 0x0 |
| 5052 | OPC_Decode, 237, 11, 178, 1, // 4087: decode to MVE_VQDMLADHXs16 using decoder 178 |
| 5053 | // 4087: } |
| 5054 | 15, 0, // 4092: case 0xf: { |
| 5055 | OPC_CheckPredicate, 31, // 4094: check predicate 31 |
| 5056 | OPC_CheckField, 4, 1, 0, // 4096: check Inst[4] == 0x0 |
| 5057 | OPC_Decode, 249, 11, 178, 1, // 4100: decode to MVE_VQDMLSDHXs16 using decoder 178 |
| 5058 | // 4100: } |
| 5059 | // 4100: } // switch Inst[31:28] |
| 5060 | // 4100: } |
| 5061 | 1, 0, // 4105: case 0x1: { |
| 5062 | OPC_SwitchField, 28, 4, // 4107: switch Inst[31:28] { |
| 5063 | 14, 11, // 4110: case 0xe: { |
| 5064 | OPC_CheckPredicate, 31, // 4112: check predicate 31 |
| 5065 | OPC_CheckField, 4, 1, 0, // 4114: check Inst[4] == 0x0 |
| 5066 | OPC_Decode, 169, 11, 179, 1, // 4118: decode to MVE_VMULLTs16 using decoder 179 |
| 5067 | // 4118: } |
| 5068 | 15, 0, // 4123: case 0xf: { |
| 5069 | OPC_CheckPredicate, 31, // 4125: check predicate 31 |
| 5070 | OPC_CheckField, 4, 1, 0, // 4127: check Inst[4] == 0x0 |
| 5071 | OPC_Decode, 172, 11, 179, 1, // 4131: decode to MVE_VMULLTu16 using decoder 179 |
| 5072 | // 4131: } |
| 5073 | // 4131: } // switch Inst[31:28] |
| 5074 | // 4131: } |
| 5075 | // 4131: } // switch Inst[16] |
| 5076 | // 4131: } |
| 5077 | // 4131: } // switch Inst[12] |
| 5078 | // 4131: } |
| 5079 | 1, 0, // 4136: case 0x1: { |
| 5080 | OPC_SwitchField, 12, 1, // 4138: switch Inst[12] { |
| 5081 | 0, 65, // 4141: case 0x0: { |
| 5082 | OPC_SwitchField, 16, 1, // 4143: switch Inst[16] { |
| 5083 | 0, 29, // 4146: case 0x0: { |
| 5084 | OPC_SwitchField, 28, 4, // 4148: switch Inst[31:28] { |
| 5085 | 14, 11, // 4151: case 0xe: { |
| 5086 | OPC_CheckPredicate, 31, // 4153: check predicate 31 |
| 5087 | OPC_CheckField, 4, 1, 0, // 4155: check Inst[4] == 0x0 |
| 5088 | OPC_Decode, 159, 12, 178, 1, // 4159: decode to MVE_VQRDMLADHs16 using decoder 178 |
| 5089 | // 4159: } |
| 5090 | 15, 0, // 4164: case 0xf: { |
| 5091 | OPC_CheckPredicate, 31, // 4166: check predicate 31 |
| 5092 | OPC_CheckField, 4, 1, 0, // 4168: check Inst[4] == 0x0 |
| 5093 | OPC_Decode, 171, 12, 178, 1, // 4172: decode to MVE_VQRDMLSDHs16 using decoder 178 |
| 5094 | // 4172: } |
| 5095 | // 4172: } // switch Inst[31:28] |
| 5096 | // 4172: } |
| 5097 | 1, 0, // 4177: case 0x1: { |
| 5098 | OPC_SwitchField, 28, 4, // 4179: switch Inst[31:28] { |
| 5099 | 14, 11, // 4182: case 0xe: { |
| 5100 | OPC_CheckPredicate, 31, // 4184: check predicate 31 |
| 5101 | OPC_CheckField, 4, 1, 0, // 4186: check Inst[4] == 0x0 |
| 5102 | OPC_Decode, 153, 11, 179, 1, // 4190: decode to MVE_VMULHs16 using decoder 179 |
| 5103 | // 4190: } |
| 5104 | 15, 0, // 4195: case 0xf: { |
| 5105 | OPC_CheckPredicate, 31, // 4197: check predicate 31 |
| 5106 | OPC_CheckField, 4, 1, 0, // 4199: check Inst[4] == 0x0 |
| 5107 | OPC_Decode, 156, 11, 179, 1, // 4203: decode to MVE_VMULHu16 using decoder 179 |
| 5108 | // 4203: } |
| 5109 | // 4203: } // switch Inst[31:28] |
| 5110 | // 4203: } |
| 5111 | // 4203: } // switch Inst[16] |
| 5112 | // 4203: } |
| 5113 | 1, 0, // 4208: case 0x1: { |
| 5114 | OPC_SwitchField, 16, 1, // 4210: switch Inst[16] { |
| 5115 | 0, 29, // 4213: case 0x0: { |
| 5116 | OPC_SwitchField, 28, 4, // 4215: switch Inst[31:28] { |
| 5117 | 14, 11, // 4218: case 0xe: { |
| 5118 | OPC_CheckPredicate, 31, // 4220: check predicate 31 |
| 5119 | OPC_CheckField, 4, 1, 0, // 4222: check Inst[4] == 0x0 |
| 5120 | OPC_Decode, 156, 12, 178, 1, // 4226: decode to MVE_VQRDMLADHXs16 using decoder 178 |
| 5121 | // 4226: } |
| 5122 | 15, 0, // 4231: case 0xf: { |
| 5123 | OPC_CheckPredicate, 31, // 4233: check predicate 31 |
| 5124 | OPC_CheckField, 4, 1, 0, // 4235: check Inst[4] == 0x0 |
| 5125 | OPC_Decode, 168, 12, 178, 1, // 4239: decode to MVE_VQRDMLSDHXs16 using decoder 178 |
| 5126 | // 4239: } |
| 5127 | // 4239: } // switch Inst[31:28] |
| 5128 | // 4239: } |
| 5129 | 1, 0, // 4244: case 0x1: { |
| 5130 | OPC_SwitchField, 28, 4, // 4246: switch Inst[31:28] { |
| 5131 | 14, 11, // 4249: case 0xe: { |
| 5132 | OPC_CheckPredicate, 31, // 4251: check predicate 31 |
| 5133 | OPC_CheckField, 4, 1, 0, // 4253: check Inst[4] == 0x0 |
| 5134 | OPC_Decode, 155, 13, 179, 1, // 4257: decode to MVE_VRMULHs16 using decoder 179 |
| 5135 | // 4257: } |
| 5136 | 15, 0, // 4262: case 0xf: { |
| 5137 | OPC_CheckPredicate, 31, // 4264: check predicate 31 |
| 5138 | OPC_CheckField, 4, 1, 0, // 4266: check Inst[4] == 0x0 |
| 5139 | OPC_Decode, 158, 13, 179, 1, // 4270: decode to MVE_VRMULHu16 using decoder 179 |
| 5140 | // 4270: } |
| 5141 | // 4270: } // switch Inst[31:28] |
| 5142 | // 4270: } |
| 5143 | // 4270: } // switch Inst[16] |
| 5144 | // 4270: } |
| 5145 | // 4270: } // switch Inst[12] |
| 5146 | // 4270: } |
| 5147 | // 4270: } // switch Inst[0] |
| 5148 | // 4270: } |
| 5149 | 1, 0, // 4275: case 0x1: { |
| 5150 | OPC_SwitchField, 4, 2, // 4277: switch Inst[5:4] { |
| 5151 | 0, 65, // 4280: case 0x0: { |
| 5152 | OPC_SwitchField, 12, 1, // 4282: switch Inst[12] { |
| 5153 | 0, 29, // 4285: case 0x0: { |
| 5154 | OPC_SwitchField, 16, 1, // 4287: switch Inst[16] { |
| 5155 | 0, 11, // 4290: case 0x0: { |
| 5156 | OPC_CheckPredicate, 31, // 4292: check predicate 31 |
| 5157 | OPC_CheckField, 28, 4, 14, // 4294: check Inst[31:28] == 0xe |
| 5158 | OPC_Decode, 162, 12, 180, 1, // 4298: decode to MVE_VQRDMLAH_qrs16 using decoder 180 |
| 5159 | // 4298: } |
| 5160 | 1, 0, // 4303: case 0x1: { |
| 5161 | OPC_CheckPredicate, 31, // 4305: check predicate 31 |
| 5162 | OPC_CheckField, 28, 4, 14, // 4307: check Inst[31:28] == 0xe |
| 5163 | OPC_Decode, 231, 10, 180, 1, // 4311: decode to MVE_VMLA_qr_i16 using decoder 180 |
| 5164 | // 4311: } |
| 5165 | // 4311: } // switch Inst[16] |
| 5166 | // 4311: } |
| 5167 | 1, 0, // 4316: case 0x1: { |
| 5168 | OPC_SwitchField, 16, 1, // 4318: switch Inst[16] { |
| 5169 | 0, 11, // 4321: case 0x0: { |
| 5170 | OPC_CheckPredicate, 31, // 4323: check predicate 31 |
| 5171 | OPC_CheckField, 28, 4, 14, // 4325: check Inst[31:28] == 0xe |
| 5172 | OPC_Decode, 165, 12, 180, 1, // 4329: decode to MVE_VQRDMLASH_qrs16 using decoder 180 |
| 5173 | // 4329: } |
| 5174 | 1, 0, // 4334: case 0x1: { |
| 5175 | OPC_CheckPredicate, 31, // 4336: check predicate 31 |
| 5176 | OPC_CheckField, 28, 4, 14, // 4338: check Inst[31:28] == 0xe |
| 5177 | OPC_Decode, 228, 10, 180, 1, // 4342: decode to MVE_VMLAS_qr_i16 using decoder 180 |
| 5178 | // 4342: } |
| 5179 | // 4342: } // switch Inst[16] |
| 5180 | // 4342: } |
| 5181 | // 4342: } // switch Inst[12] |
| 5182 | // 4342: } |
| 5183 | 2, 0, // 4347: case 0x2: { |
| 5184 | OPC_SwitchField, 12, 1, // 4349: switch Inst[12] { |
| 5185 | 0, 39, // 4352: case 0x0: { |
| 5186 | OPC_SwitchField, 16, 1, // 4354: switch Inst[16] { |
| 5187 | 0, 11, // 4357: case 0x0: { |
| 5188 | OPC_CheckPredicate, 31, // 4359: check predicate 31 |
| 5189 | OPC_CheckField, 28, 4, 14, // 4361: check Inst[31:28] == 0xe |
| 5190 | OPC_Decode, 243, 11, 180, 1, // 4365: decode to MVE_VQDMLAH_qrs16 using decoder 180 |
| 5191 | // 4365: } |
| 5192 | 1, 0, // 4370: case 0x1: { |
| 5193 | OPC_SwitchField, 28, 4, // 4372: switch Inst[31:28] { |
| 5194 | 14, 7, // 4375: case 0xe: { |
| 5195 | OPC_CheckPredicate, 31, // 4377: check predicate 31 |
| 5196 | OPC_Decode, 255, 11, 181, 1, // 4379: decode to MVE_VQDMULH_qr_s16 using decoder 181 |
| 5197 | // 4379: } |
| 5198 | 15, 0, // 4384: case 0xf: { |
| 5199 | OPC_CheckPredicate, 31, // 4386: check predicate 31 |
| 5200 | OPC_Decode, 174, 12, 181, 1, // 4388: decode to MVE_VQRDMULH_qr_s16 using decoder 181 |
| 5201 | // 4388: } |
| 5202 | // 4388: } // switch Inst[31:28] |
| 5203 | // 4388: } |
| 5204 | // 4388: } // switch Inst[16] |
| 5205 | // 4388: } |
| 5206 | 1, 0, // 4393: case 0x1: { |
| 5207 | OPC_SwitchField, 16, 1, // 4395: switch Inst[16] { |
| 5208 | 0, 11, // 4398: case 0x0: { |
| 5209 | OPC_CheckPredicate, 31, // 4400: check predicate 31 |
| 5210 | OPC_CheckField, 28, 4, 14, // 4402: check Inst[31:28] == 0xe |
| 5211 | OPC_Decode, 246, 11, 180, 1, // 4406: decode to MVE_VQDMLASH_qrs16 using decoder 180 |
| 5212 | // 4406: } |
| 5213 | 1, 0, // 4411: case 0x1: { |
| 5214 | OPC_SwitchField, 28, 4, // 4413: switch Inst[31:28] { |
| 5215 | 14, 7, // 4416: case 0xe: { |
| 5216 | OPC_CheckPredicate, 31, // 4418: check predicate 31 |
| 5217 | OPC_Decode, 177, 11, 181, 1, // 4420: decode to MVE_VMUL_qr_i16 using decoder 181 |
| 5218 | // 4420: } |
| 5219 | 15, 0, // 4425: case 0xf: { |
| 5220 | OPC_CheckPredicate, 31, // 4427: check predicate 31 |
| 5221 | OPC_Decode, 189, 8, 181, 1, // 4429: decode to MVE_VBRSR16 using decoder 181 |
| 5222 | // 4429: } |
| 5223 | // 4429: } // switch Inst[31:28] |
| 5224 | // 4429: } |
| 5225 | // 4429: } // switch Inst[16] |
| 5226 | // 4429: } |
| 5227 | // 4429: } // switch Inst[12] |
| 5228 | // 4429: } |
| 5229 | // 4429: } // switch Inst[5:4] |
| 5230 | // 4429: } |
| 5231 | // 4429: } // switch Inst[6] |
| 5232 | // 4429: } |
| 5233 | 2, 191, 3, // 4434: case 0x2: { |
| 5234 | OPC_SwitchField, 6, 1, // 4437: switch Inst[6] { |
| 5235 | 0, 154, 2, // 4440: case 0x0: { |
| 5236 | OPC_SwitchField, 0, 1, // 4443: switch Inst[0] { |
| 5237 | 0, 137, 1, // 4446: case 0x0: { |
| 5238 | OPC_SwitchField, 12, 1, // 4449: switch Inst[12] { |
| 5239 | 0, 65, // 4452: case 0x0: { |
| 5240 | OPC_SwitchField, 16, 1, // 4454: switch Inst[16] { |
| 5241 | 0, 29, // 4457: case 0x0: { |
| 5242 | OPC_SwitchField, 28, 4, // 4459: switch Inst[31:28] { |
| 5243 | 14, 11, // 4462: case 0xe: { |
| 5244 | OPC_CheckPredicate, 31, // 4464: check predicate 31 |
| 5245 | OPC_CheckField, 4, 1, 0, // 4466: check Inst[4] == 0x0 |
| 5246 | OPC_Decode, 241, 11, 178, 1, // 4470: decode to MVE_VQDMLADHs32 using decoder 178 |
| 5247 | // 4470: } |
| 5248 | 15, 0, // 4475: case 0xf: { |
| 5249 | OPC_CheckPredicate, 31, // 4477: check predicate 31 |
| 5250 | OPC_CheckField, 4, 1, 0, // 4479: check Inst[4] == 0x0 |
| 5251 | OPC_Decode, 253, 11, 178, 1, // 4483: decode to MVE_VQDMLSDHs32 using decoder 178 |
| 5252 | // 4483: } |
| 5253 | // 4483: } // switch Inst[31:28] |
| 5254 | // 4483: } |
| 5255 | 1, 0, // 4488: case 0x1: { |
| 5256 | OPC_SwitchField, 28, 4, // 4490: switch Inst[31:28] { |
| 5257 | 14, 11, // 4493: case 0xe: { |
| 5258 | OPC_CheckPredicate, 31, // 4495: check predicate 31 |
| 5259 | OPC_CheckField, 4, 1, 0, // 4497: check Inst[4] == 0x0 |
| 5260 | OPC_Decode, 162, 11, 179, 1, // 4501: decode to MVE_VMULLBs32 using decoder 179 |
| 5261 | // 4501: } |
| 5262 | 15, 0, // 4506: case 0xf: { |
| 5263 | OPC_CheckPredicate, 31, // 4508: check predicate 31 |
| 5264 | OPC_CheckField, 4, 1, 0, // 4510: check Inst[4] == 0x0 |
| 5265 | OPC_Decode, 165, 11, 179, 1, // 4514: decode to MVE_VMULLBu32 using decoder 179 |
| 5266 | // 4514: } |
| 5267 | // 4514: } // switch Inst[31:28] |
| 5268 | // 4514: } |
| 5269 | // 4514: } // switch Inst[16] |
| 5270 | // 4514: } |
| 5271 | 1, 0, // 4519: case 0x1: { |
| 5272 | OPC_SwitchField, 16, 1, // 4521: switch Inst[16] { |
| 5273 | 0, 29, // 4524: case 0x0: { |
| 5274 | OPC_SwitchField, 28, 4, // 4526: switch Inst[31:28] { |
| 5275 | 14, 11, // 4529: case 0xe: { |
| 5276 | OPC_CheckPredicate, 31, // 4531: check predicate 31 |
| 5277 | OPC_CheckField, 4, 1, 0, // 4533: check Inst[4] == 0x0 |
| 5278 | OPC_Decode, 238, 11, 178, 1, // 4537: decode to MVE_VQDMLADHXs32 using decoder 178 |
| 5279 | // 4537: } |
| 5280 | 15, 0, // 4542: case 0xf: { |
| 5281 | OPC_CheckPredicate, 31, // 4544: check predicate 31 |
| 5282 | OPC_CheckField, 4, 1, 0, // 4546: check Inst[4] == 0x0 |
| 5283 | OPC_Decode, 250, 11, 178, 1, // 4550: decode to MVE_VQDMLSDHXs32 using decoder 178 |
| 5284 | // 4550: } |
| 5285 | // 4550: } // switch Inst[31:28] |
| 5286 | // 4550: } |
| 5287 | 1, 0, // 4555: case 0x1: { |
| 5288 | OPC_SwitchField, 28, 4, // 4557: switch Inst[31:28] { |
| 5289 | 14, 11, // 4560: case 0xe: { |
| 5290 | OPC_CheckPredicate, 31, // 4562: check predicate 31 |
| 5291 | OPC_CheckField, 4, 1, 0, // 4564: check Inst[4] == 0x0 |
| 5292 | OPC_Decode, 170, 11, 179, 1, // 4568: decode to MVE_VMULLTs32 using decoder 179 |
| 5293 | // 4568: } |
| 5294 | 15, 0, // 4573: case 0xf: { |
| 5295 | OPC_CheckPredicate, 31, // 4575: check predicate 31 |
| 5296 | OPC_CheckField, 4, 1, 0, // 4577: check Inst[4] == 0x0 |
| 5297 | OPC_Decode, 173, 11, 179, 1, // 4581: decode to MVE_VMULLTu32 using decoder 179 |
| 5298 | // 4581: } |
| 5299 | // 4581: } // switch Inst[31:28] |
| 5300 | // 4581: } |
| 5301 | // 4581: } // switch Inst[16] |
| 5302 | // 4581: } |
| 5303 | // 4581: } // switch Inst[12] |
| 5304 | // 4581: } |
| 5305 | 1, 0, // 4586: case 0x1: { |
| 5306 | OPC_SwitchField, 12, 1, // 4588: switch Inst[12] { |
| 5307 | 0, 65, // 4591: case 0x0: { |
| 5308 | OPC_SwitchField, 16, 1, // 4593: switch Inst[16] { |
| 5309 | 0, 29, // 4596: case 0x0: { |
| 5310 | OPC_SwitchField, 28, 4, // 4598: switch Inst[31:28] { |
| 5311 | 14, 11, // 4601: case 0xe: { |
| 5312 | OPC_CheckPredicate, 31, // 4603: check predicate 31 |
| 5313 | OPC_CheckField, 4, 1, 0, // 4605: check Inst[4] == 0x0 |
| 5314 | OPC_Decode, 160, 12, 178, 1, // 4609: decode to MVE_VQRDMLADHs32 using decoder 178 |
| 5315 | // 4609: } |
| 5316 | 15, 0, // 4614: case 0xf: { |
| 5317 | OPC_CheckPredicate, 31, // 4616: check predicate 31 |
| 5318 | OPC_CheckField, 4, 1, 0, // 4618: check Inst[4] == 0x0 |
| 5319 | OPC_Decode, 172, 12, 178, 1, // 4622: decode to MVE_VQRDMLSDHs32 using decoder 178 |
| 5320 | // 4622: } |
| 5321 | // 4622: } // switch Inst[31:28] |
| 5322 | // 4622: } |
| 5323 | 1, 0, // 4627: case 0x1: { |
| 5324 | OPC_SwitchField, 28, 4, // 4629: switch Inst[31:28] { |
| 5325 | 14, 11, // 4632: case 0xe: { |
| 5326 | OPC_CheckPredicate, 31, // 4634: check predicate 31 |
| 5327 | OPC_CheckField, 4, 1, 0, // 4636: check Inst[4] == 0x0 |
| 5328 | OPC_Decode, 154, 11, 179, 1, // 4640: decode to MVE_VMULHs32 using decoder 179 |
| 5329 | // 4640: } |
| 5330 | 15, 0, // 4645: case 0xf: { |
| 5331 | OPC_CheckPredicate, 31, // 4647: check predicate 31 |
| 5332 | OPC_CheckField, 4, 1, 0, // 4649: check Inst[4] == 0x0 |
| 5333 | OPC_Decode, 157, 11, 179, 1, // 4653: decode to MVE_VMULHu32 using decoder 179 |
| 5334 | // 4653: } |
| 5335 | // 4653: } // switch Inst[31:28] |
| 5336 | // 4653: } |
| 5337 | // 4653: } // switch Inst[16] |
| 5338 | // 4653: } |
| 5339 | 1, 0, // 4658: case 0x1: { |
| 5340 | OPC_SwitchField, 16, 1, // 4660: switch Inst[16] { |
| 5341 | 0, 29, // 4663: case 0x0: { |
| 5342 | OPC_SwitchField, 28, 4, // 4665: switch Inst[31:28] { |
| 5343 | 14, 11, // 4668: case 0xe: { |
| 5344 | OPC_CheckPredicate, 31, // 4670: check predicate 31 |
| 5345 | OPC_CheckField, 4, 1, 0, // 4672: check Inst[4] == 0x0 |
| 5346 | OPC_Decode, 157, 12, 178, 1, // 4676: decode to MVE_VQRDMLADHXs32 using decoder 178 |
| 5347 | // 4676: } |
| 5348 | 15, 0, // 4681: case 0xf: { |
| 5349 | OPC_CheckPredicate, 31, // 4683: check predicate 31 |
| 5350 | OPC_CheckField, 4, 1, 0, // 4685: check Inst[4] == 0x0 |
| 5351 | OPC_Decode, 169, 12, 178, 1, // 4689: decode to MVE_VQRDMLSDHXs32 using decoder 178 |
| 5352 | // 4689: } |
| 5353 | // 4689: } // switch Inst[31:28] |
| 5354 | // 4689: } |
| 5355 | 1, 0, // 4694: case 0x1: { |
| 5356 | OPC_SwitchField, 28, 4, // 4696: switch Inst[31:28] { |
| 5357 | 14, 11, // 4699: case 0xe: { |
| 5358 | OPC_CheckPredicate, 31, // 4701: check predicate 31 |
| 5359 | OPC_CheckField, 4, 1, 0, // 4703: check Inst[4] == 0x0 |
| 5360 | OPC_Decode, 156, 13, 179, 1, // 4707: decode to MVE_VRMULHs32 using decoder 179 |
| 5361 | // 4707: } |
| 5362 | 15, 0, // 4712: case 0xf: { |
| 5363 | OPC_CheckPredicate, 31, // 4714: check predicate 31 |
| 5364 | OPC_CheckField, 4, 1, 0, // 4716: check Inst[4] == 0x0 |
| 5365 | OPC_Decode, 159, 13, 179, 1, // 4720: decode to MVE_VRMULHu32 using decoder 179 |
| 5366 | // 4720: } |
| 5367 | // 4720: } // switch Inst[31:28] |
| 5368 | // 4720: } |
| 5369 | // 4720: } // switch Inst[16] |
| 5370 | // 4720: } |
| 5371 | // 4720: } // switch Inst[12] |
| 5372 | // 4720: } |
| 5373 | // 4720: } // switch Inst[0] |
| 5374 | // 4720: } |
| 5375 | 1, 0, // 4725: case 0x1: { |
| 5376 | OPC_SwitchField, 4, 2, // 4727: switch Inst[5:4] { |
| 5377 | 0, 65, // 4730: case 0x0: { |
| 5378 | OPC_SwitchField, 12, 1, // 4732: switch Inst[12] { |
| 5379 | 0, 29, // 4735: case 0x0: { |
| 5380 | OPC_SwitchField, 16, 1, // 4737: switch Inst[16] { |
| 5381 | 0, 11, // 4740: case 0x0: { |
| 5382 | OPC_CheckPredicate, 31, // 4742: check predicate 31 |
| 5383 | OPC_CheckField, 28, 4, 14, // 4744: check Inst[31:28] == 0xe |
| 5384 | OPC_Decode, 163, 12, 180, 1, // 4748: decode to MVE_VQRDMLAH_qrs32 using decoder 180 |
| 5385 | // 4748: } |
| 5386 | 1, 0, // 4753: case 0x1: { |
| 5387 | OPC_CheckPredicate, 31, // 4755: check predicate 31 |
| 5388 | OPC_CheckField, 28, 4, 14, // 4757: check Inst[31:28] == 0xe |
| 5389 | OPC_Decode, 232, 10, 180, 1, // 4761: decode to MVE_VMLA_qr_i32 using decoder 180 |
| 5390 | // 4761: } |
| 5391 | // 4761: } // switch Inst[16] |
| 5392 | // 4761: } |
| 5393 | 1, 0, // 4766: case 0x1: { |
| 5394 | OPC_SwitchField, 16, 1, // 4768: switch Inst[16] { |
| 5395 | 0, 11, // 4771: case 0x0: { |
| 5396 | OPC_CheckPredicate, 31, // 4773: check predicate 31 |
| 5397 | OPC_CheckField, 28, 4, 14, // 4775: check Inst[31:28] == 0xe |
| 5398 | OPC_Decode, 166, 12, 180, 1, // 4779: decode to MVE_VQRDMLASH_qrs32 using decoder 180 |
| 5399 | // 4779: } |
| 5400 | 1, 0, // 4784: case 0x1: { |
| 5401 | OPC_CheckPredicate, 31, // 4786: check predicate 31 |
| 5402 | OPC_CheckField, 28, 4, 14, // 4788: check Inst[31:28] == 0xe |
| 5403 | OPC_Decode, 229, 10, 180, 1, // 4792: decode to MVE_VMLAS_qr_i32 using decoder 180 |
| 5404 | // 4792: } |
| 5405 | // 4792: } // switch Inst[16] |
| 5406 | // 4792: } |
| 5407 | // 4792: } // switch Inst[12] |
| 5408 | // 4792: } |
| 5409 | 2, 0, // 4797: case 0x2: { |
| 5410 | OPC_SwitchField, 12, 1, // 4799: switch Inst[12] { |
| 5411 | 0, 39, // 4802: case 0x0: { |
| 5412 | OPC_SwitchField, 16, 1, // 4804: switch Inst[16] { |
| 5413 | 0, 11, // 4807: case 0x0: { |
| 5414 | OPC_CheckPredicate, 31, // 4809: check predicate 31 |
| 5415 | OPC_CheckField, 28, 4, 14, // 4811: check Inst[31:28] == 0xe |
| 5416 | OPC_Decode, 244, 11, 180, 1, // 4815: decode to MVE_VQDMLAH_qrs32 using decoder 180 |
| 5417 | // 4815: } |
| 5418 | 1, 0, // 4820: case 0x1: { |
| 5419 | OPC_SwitchField, 28, 4, // 4822: switch Inst[31:28] { |
| 5420 | 14, 7, // 4825: case 0xe: { |
| 5421 | OPC_CheckPredicate, 31, // 4827: check predicate 31 |
| 5422 | OPC_Decode, 128, 12, 181, 1, // 4829: decode to MVE_VQDMULH_qr_s32 using decoder 181 |
| 5423 | // 4829: } |
| 5424 | 15, 0, // 4834: case 0xf: { |
| 5425 | OPC_CheckPredicate, 31, // 4836: check predicate 31 |
| 5426 | OPC_Decode, 175, 12, 181, 1, // 4838: decode to MVE_VQRDMULH_qr_s32 using decoder 181 |
| 5427 | // 4838: } |
| 5428 | // 4838: } // switch Inst[31:28] |
| 5429 | // 4838: } |
| 5430 | // 4838: } // switch Inst[16] |
| 5431 | // 4838: } |
| 5432 | 1, 0, // 4843: case 0x1: { |
| 5433 | OPC_SwitchField, 16, 1, // 4845: switch Inst[16] { |
| 5434 | 0, 11, // 4848: case 0x0: { |
| 5435 | OPC_CheckPredicate, 31, // 4850: check predicate 31 |
| 5436 | OPC_CheckField, 28, 4, 14, // 4852: check Inst[31:28] == 0xe |
| 5437 | OPC_Decode, 247, 11, 180, 1, // 4856: decode to MVE_VQDMLASH_qrs32 using decoder 180 |
| 5438 | // 4856: } |
| 5439 | 1, 0, // 4861: case 0x1: { |
| 5440 | OPC_SwitchField, 28, 4, // 4863: switch Inst[31:28] { |
| 5441 | 14, 7, // 4866: case 0xe: { |
| 5442 | OPC_CheckPredicate, 31, // 4868: check predicate 31 |
| 5443 | OPC_Decode, 178, 11, 181, 1, // 4870: decode to MVE_VMUL_qr_i32 using decoder 181 |
| 5444 | // 4870: } |
| 5445 | 15, 0, // 4875: case 0xf: { |
| 5446 | OPC_CheckPredicate, 31, // 4877: check predicate 31 |
| 5447 | OPC_Decode, 190, 8, 181, 1, // 4879: decode to MVE_VBRSR32 using decoder 181 |
| 5448 | // 4879: } |
| 5449 | // 4879: } // switch Inst[31:28] |
| 5450 | // 4879: } |
| 5451 | // 4879: } // switch Inst[16] |
| 5452 | // 4879: } |
| 5453 | // 4879: } // switch Inst[12] |
| 5454 | // 4879: } |
| 5455 | // 4879: } // switch Inst[5:4] |
| 5456 | // 4879: } |
| 5457 | // 4879: } // switch Inst[6] |
| 5458 | // 4879: } |
| 5459 | 3, 0, // 4884: case 0x3: { |
| 5460 | OPC_SwitchField, 6, 1, // 4886: switch Inst[6] { |
| 5461 | 0, 159, 6, // 4889: case 0x0: { |
| 5462 | OPC_SwitchField, 16, 1, // 4892: switch Inst[16] { |
| 5463 | 0, 29, // 4895: case 0x0: { |
| 5464 | OPC_SwitchField, 28, 4, // 4897: switch Inst[31:28] { |
| 5465 | 14, 11, // 4900: case 0xe: { |
| 5466 | OPC_CheckPredicate, 33, // 4902: check predicate 33 |
| 5467 | OPC_CheckField, 4, 1, 0, // 4904: check Inst[4] == 0x0 |
| 5468 | OPC_Decode, 227, 8, 182, 1, // 4908: decode to MVE_VCMULf16 using decoder 182 |
| 5469 | // 4908: } |
| 5470 | 15, 0, // 4913: case 0xf: { |
| 5471 | OPC_CheckPredicate, 33, // 4915: check predicate 33 |
| 5472 | OPC_CheckField, 4, 1, 0, // 4917: check Inst[4] == 0x0 |
| 5473 | OPC_Decode, 228, 8, 182, 1, // 4921: decode to MVE_VCMULf32 using decoder 182 |
| 5474 | // 4921: } |
| 5475 | // 4921: } // switch Inst[31:28] |
| 5476 | // 4921: } |
| 5477 | 1, 0, // 4926: case 0x1: { |
| 5478 | OPC_SwitchField, 0, 1, // 4928: switch Inst[0] { |
| 5479 | 0, 65, // 4931: case 0x0: { |
| 5480 | OPC_SwitchField, 12, 1, // 4933: switch Inst[12] { |
| 5481 | 0, 29, // 4936: case 0x0: { |
| 5482 | OPC_SwitchField, 28, 4, // 4938: switch Inst[31:28] { |
| 5483 | 14, 11, // 4941: case 0xe: { |
| 5484 | OPC_CheckPredicate, 31, // 4943: check predicate 31 |
| 5485 | OPC_CheckField, 4, 1, 0, // 4945: check Inst[4] == 0x0 |
| 5486 | OPC_Decode, 160, 11, 179, 1, // 4949: decode to MVE_VMULLBp8 using decoder 179 |
| 5487 | // 4949: } |
| 5488 | 15, 0, // 4954: case 0xf: { |
| 5489 | OPC_CheckPredicate, 31, // 4956: check predicate 31 |
| 5490 | OPC_CheckField, 4, 1, 0, // 4958: check Inst[4] == 0x0 |
| 5491 | OPC_Decode, 159, 11, 179, 1, // 4962: decode to MVE_VMULLBp16 using decoder 179 |
| 5492 | // 4962: } |
| 5493 | // 4962: } // switch Inst[31:28] |
| 5494 | // 4962: } |
| 5495 | 1, 0, // 4967: case 0x1: { |
| 5496 | OPC_SwitchField, 28, 4, // 4969: switch Inst[31:28] { |
| 5497 | 14, 11, // 4972: case 0xe: { |
| 5498 | OPC_CheckPredicate, 31, // 4974: check predicate 31 |
| 5499 | OPC_CheckField, 4, 1, 0, // 4976: check Inst[4] == 0x0 |
| 5500 | OPC_Decode, 168, 11, 179, 1, // 4980: decode to MVE_VMULLTp8 using decoder 179 |
| 5501 | // 4980: } |
| 5502 | 15, 0, // 4985: case 0xf: { |
| 5503 | OPC_CheckPredicate, 31, // 4987: check predicate 31 |
| 5504 | OPC_CheckField, 4, 1, 0, // 4989: check Inst[4] == 0x0 |
| 5505 | OPC_Decode, 167, 11, 179, 1, // 4993: decode to MVE_VMULLTp16 using decoder 179 |
| 5506 | // 4993: } |
| 5507 | // 4993: } // switch Inst[31:28] |
| 5508 | // 4993: } |
| 5509 | // 4993: } // switch Inst[12] |
| 5510 | // 4993: } |
| 5511 | 1, 0, // 4998: case 0x1: { |
| 5512 | OPC_SwitchField, 17, 3, // 5000: switch Inst[19:17] { |
| 5513 | 0, 137, 1, // 5003: case 0x0: { |
| 5514 | OPC_SwitchField, 7, 1, // 5006: switch Inst[7] { |
| 5515 | 0, 65, // 5009: case 0x0: { |
| 5516 | OPC_SwitchField, 12, 1, // 5011: switch Inst[12] { |
| 5517 | 0, 29, // 5014: case 0x0: { |
| 5518 | OPC_SwitchField, 28, 4, // 5016: switch Inst[31:28] { |
| 5519 | 14, 11, // 5019: case 0xe: { |
| 5520 | OPC_CheckPredicate, 31, // 5021: check predicate 31 |
| 5521 | OPC_CheckField, 4, 1, 0, // 5023: check Inst[4] == 0x0 |
| 5522 | OPC_Decode, 196, 13, 183, 1, // 5027: decode to MVE_VSHLL_lws8bh using decoder 183 |
| 5523 | // 5027: } |
| 5524 | 15, 0, // 5032: case 0xf: { |
| 5525 | OPC_CheckPredicate, 31, // 5034: check predicate 31 |
| 5526 | OPC_CheckField, 4, 1, 0, // 5036: check Inst[4] == 0x0 |
| 5527 | OPC_Decode, 200, 13, 183, 1, // 5040: decode to MVE_VSHLL_lwu8bh using decoder 183 |
| 5528 | // 5040: } |
| 5529 | // 5040: } // switch Inst[31:28] |
| 5530 | // 5040: } |
| 5531 | 1, 0, // 5045: case 0x1: { |
| 5532 | OPC_SwitchField, 28, 4, // 5047: switch Inst[31:28] { |
| 5533 | 14, 11, // 5050: case 0xe: { |
| 5534 | OPC_CheckPredicate, 31, // 5052: check predicate 31 |
| 5535 | OPC_CheckField, 4, 1, 0, // 5054: check Inst[4] == 0x0 |
| 5536 | OPC_Decode, 197, 13, 183, 1, // 5058: decode to MVE_VSHLL_lws8th using decoder 183 |
| 5537 | // 5058: } |
| 5538 | 15, 0, // 5063: case 0xf: { |
| 5539 | OPC_CheckPredicate, 31, // 5065: check predicate 31 |
| 5540 | OPC_CheckField, 4, 1, 0, // 5067: check Inst[4] == 0x0 |
| 5541 | OPC_Decode, 201, 13, 183, 1, // 5071: decode to MVE_VSHLL_lwu8th using decoder 183 |
| 5542 | // 5071: } |
| 5543 | // 5071: } // switch Inst[31:28] |
| 5544 | // 5071: } |
| 5545 | // 5071: } // switch Inst[12] |
| 5546 | // 5071: } |
| 5547 | 1, 0, // 5076: case 0x1: { |
| 5548 | OPC_SwitchField, 12, 1, // 5078: switch Inst[12] { |
| 5549 | 0, 29, // 5081: case 0x0: { |
| 5550 | OPC_SwitchField, 28, 4, // 5083: switch Inst[31:28] { |
| 5551 | 14, 11, // 5086: case 0xe: { |
| 5552 | OPC_CheckPredicate, 31, // 5088: check predicate 31 |
| 5553 | OPC_CheckField, 4, 1, 0, // 5090: check Inst[4] == 0x0 |
| 5554 | OPC_Decode, 149, 12, 184, 1, // 5094: decode to MVE_VQMOVUNs16bh using decoder 184 |
| 5555 | // 5094: } |
| 5556 | 15, 0, // 5099: case 0xf: { |
| 5557 | OPC_CheckPredicate, 31, // 5101: check predicate 31 |
| 5558 | OPC_CheckField, 4, 1, 0, // 5103: check Inst[4] == 0x0 |
| 5559 | OPC_Decode, 134, 11, 184, 1, // 5107: decode to MVE_VMOVNi16bh using decoder 184 |
| 5560 | // 5107: } |
| 5561 | // 5107: } // switch Inst[31:28] |
| 5562 | // 5107: } |
| 5563 | 1, 0, // 5112: case 0x1: { |
| 5564 | OPC_SwitchField, 28, 4, // 5114: switch Inst[31:28] { |
| 5565 | 14, 11, // 5117: case 0xe: { |
| 5566 | OPC_CheckPredicate, 31, // 5119: check predicate 31 |
| 5567 | OPC_CheckField, 4, 1, 0, // 5121: check Inst[4] == 0x0 |
| 5568 | OPC_Decode, 150, 12, 184, 1, // 5125: decode to MVE_VQMOVUNs16th using decoder 184 |
| 5569 | // 5125: } |
| 5570 | 15, 0, // 5130: case 0xf: { |
| 5571 | OPC_CheckPredicate, 31, // 5132: check predicate 31 |
| 5572 | OPC_CheckField, 4, 1, 0, // 5134: check Inst[4] == 0x0 |
| 5573 | OPC_Decode, 135, 11, 184, 1, // 5138: decode to MVE_VMOVNi16th using decoder 184 |
| 5574 | // 5138: } |
| 5575 | // 5138: } // switch Inst[31:28] |
| 5576 | // 5138: } |
| 5577 | // 5138: } // switch Inst[12] |
| 5578 | // 5138: } |
| 5579 | // 5138: } // switch Inst[7] |
| 5580 | // 5138: } |
| 5581 | 1, 109, // 5143: case 0x1: { |
| 5582 | OPC_SwitchField, 7, 1, // 5145: switch Inst[7] { |
| 5583 | 0, 65, // 5148: case 0x0: { |
| 5584 | OPC_SwitchField, 12, 1, // 5150: switch Inst[12] { |
| 5585 | 0, 29, // 5153: case 0x0: { |
| 5586 | OPC_SwitchField, 28, 4, // 5155: switch Inst[31:28] { |
| 5587 | 14, 11, // 5158: case 0xe: { |
| 5588 | OPC_CheckPredicate, 31, // 5160: check predicate 31 |
| 5589 | OPC_CheckField, 4, 1, 0, // 5162: check Inst[4] == 0x0 |
| 5590 | OPC_Decode, 141, 12, 184, 1, // 5166: decode to MVE_VQMOVNs16bh using decoder 184 |
| 5591 | // 5166: } |
| 5592 | 15, 0, // 5171: case 0xf: { |
| 5593 | OPC_CheckPredicate, 31, // 5173: check predicate 31 |
| 5594 | OPC_CheckField, 4, 1, 0, // 5175: check Inst[4] == 0x0 |
| 5595 | OPC_Decode, 145, 12, 184, 1, // 5179: decode to MVE_VQMOVNu16bh using decoder 184 |
| 5596 | // 5179: } |
| 5597 | // 5179: } // switch Inst[31:28] |
| 5598 | // 5179: } |
| 5599 | 1, 0, // 5184: case 0x1: { |
| 5600 | OPC_SwitchField, 28, 4, // 5186: switch Inst[31:28] { |
| 5601 | 14, 11, // 5189: case 0xe: { |
| 5602 | OPC_CheckPredicate, 31, // 5191: check predicate 31 |
| 5603 | OPC_CheckField, 4, 1, 0, // 5193: check Inst[4] == 0x0 |
| 5604 | OPC_Decode, 142, 12, 184, 1, // 5197: decode to MVE_VQMOVNs16th using decoder 184 |
| 5605 | // 5197: } |
| 5606 | 15, 0, // 5202: case 0xf: { |
| 5607 | OPC_CheckPredicate, 31, // 5204: check predicate 31 |
| 5608 | OPC_CheckField, 4, 1, 0, // 5206: check Inst[4] == 0x0 |
| 5609 | OPC_Decode, 146, 12, 184, 1, // 5210: decode to MVE_VQMOVNu16th using decoder 184 |
| 5610 | // 5210: } |
| 5611 | // 5210: } // switch Inst[31:28] |
| 5612 | // 5210: } |
| 5613 | // 5210: } // switch Inst[12] |
| 5614 | // 5210: } |
| 5615 | 1, 0, // 5215: case 0x1: { |
| 5616 | OPC_SwitchField, 12, 1, // 5217: switch Inst[12] { |
| 5617 | 0, 15, // 5220: case 0x0: { |
| 5618 | OPC_CheckPredicate, 31, // 5222: check predicate 31 |
| 5619 | OPC_CheckField, 28, 4, 14, // 5224: check Inst[31:28] == 0xe |
| 5620 | OPC_CheckField, 4, 1, 0, // 5228: check Inst[4] == 0x0 |
| 5621 | OPC_Decode, 151, 10, 184, 1, // 5232: decode to MVE_VMAXAs8 using decoder 184 |
| 5622 | // 5232: } |
| 5623 | 1, 0, // 5237: case 0x1: { |
| 5624 | OPC_CheckPredicate, 31, // 5239: check predicate 31 |
| 5625 | OPC_CheckField, 28, 4, 14, // 5241: check Inst[31:28] == 0xe |
| 5626 | OPC_CheckField, 4, 1, 0, // 5245: check Inst[4] == 0x0 |
| 5627 | OPC_Decode, 177, 10, 184, 1, // 5249: decode to MVE_VMINAs8 using decoder 184 |
| 5628 | // 5249: } |
| 5629 | // 5249: } // switch Inst[12] |
| 5630 | // 5249: } |
| 5631 | // 5249: } // switch Inst[7] |
| 5632 | // 5249: } |
| 5633 | 2, 137, 1, // 5254: case 0x2: { |
| 5634 | OPC_SwitchField, 7, 1, // 5257: switch Inst[7] { |
| 5635 | 0, 65, // 5260: case 0x0: { |
| 5636 | OPC_SwitchField, 12, 1, // 5262: switch Inst[12] { |
| 5637 | 0, 29, // 5265: case 0x0: { |
| 5638 | OPC_SwitchField, 28, 4, // 5267: switch Inst[31:28] { |
| 5639 | 14, 11, // 5270: case 0xe: { |
| 5640 | OPC_CheckPredicate, 31, // 5272: check predicate 31 |
| 5641 | OPC_CheckField, 4, 1, 0, // 5274: check Inst[4] == 0x0 |
| 5642 | OPC_Decode, 194, 13, 183, 1, // 5278: decode to MVE_VSHLL_lws16bh using decoder 183 |
| 5643 | // 5278: } |
| 5644 | 15, 0, // 5283: case 0xf: { |
| 5645 | OPC_CheckPredicate, 31, // 5285: check predicate 31 |
| 5646 | OPC_CheckField, 4, 1, 0, // 5287: check Inst[4] == 0x0 |
| 5647 | OPC_Decode, 198, 13, 183, 1, // 5291: decode to MVE_VSHLL_lwu16bh using decoder 183 |
| 5648 | // 5291: } |
| 5649 | // 5291: } // switch Inst[31:28] |
| 5650 | // 5291: } |
| 5651 | 1, 0, // 5296: case 0x1: { |
| 5652 | OPC_SwitchField, 28, 4, // 5298: switch Inst[31:28] { |
| 5653 | 14, 11, // 5301: case 0xe: { |
| 5654 | OPC_CheckPredicate, 31, // 5303: check predicate 31 |
| 5655 | OPC_CheckField, 4, 1, 0, // 5305: check Inst[4] == 0x0 |
| 5656 | OPC_Decode, 195, 13, 183, 1, // 5309: decode to MVE_VSHLL_lws16th using decoder 183 |
| 5657 | // 5309: } |
| 5658 | 15, 0, // 5314: case 0xf: { |
| 5659 | OPC_CheckPredicate, 31, // 5316: check predicate 31 |
| 5660 | OPC_CheckField, 4, 1, 0, // 5318: check Inst[4] == 0x0 |
| 5661 | OPC_Decode, 199, 13, 183, 1, // 5322: decode to MVE_VSHLL_lwu16th using decoder 183 |
| 5662 | // 5322: } |
| 5663 | // 5322: } // switch Inst[31:28] |
| 5664 | // 5322: } |
| 5665 | // 5322: } // switch Inst[12] |
| 5666 | // 5322: } |
| 5667 | 1, 0, // 5327: case 0x1: { |
| 5668 | OPC_SwitchField, 12, 1, // 5329: switch Inst[12] { |
| 5669 | 0, 29, // 5332: case 0x0: { |
| 5670 | OPC_SwitchField, 28, 4, // 5334: switch Inst[31:28] { |
| 5671 | 14, 11, // 5337: case 0xe: { |
| 5672 | OPC_CheckPredicate, 31, // 5339: check predicate 31 |
| 5673 | OPC_CheckField, 4, 1, 0, // 5341: check Inst[4] == 0x0 |
| 5674 | OPC_Decode, 151, 12, 184, 1, // 5345: decode to MVE_VQMOVUNs32bh using decoder 184 |
| 5675 | // 5345: } |
| 5676 | 15, 0, // 5350: case 0xf: { |
| 5677 | OPC_CheckPredicate, 31, // 5352: check predicate 31 |
| 5678 | OPC_CheckField, 4, 1, 0, // 5354: check Inst[4] == 0x0 |
| 5679 | OPC_Decode, 136, 11, 184, 1, // 5358: decode to MVE_VMOVNi32bh using decoder 184 |
| 5680 | // 5358: } |
| 5681 | // 5358: } // switch Inst[31:28] |
| 5682 | // 5358: } |
| 5683 | 1, 0, // 5363: case 0x1: { |
| 5684 | OPC_SwitchField, 28, 4, // 5365: switch Inst[31:28] { |
| 5685 | 14, 11, // 5368: case 0xe: { |
| 5686 | OPC_CheckPredicate, 31, // 5370: check predicate 31 |
| 5687 | OPC_CheckField, 4, 1, 0, // 5372: check Inst[4] == 0x0 |
| 5688 | OPC_Decode, 152, 12, 184, 1, // 5376: decode to MVE_VQMOVUNs32th using decoder 184 |
| 5689 | // 5376: } |
| 5690 | 15, 0, // 5381: case 0xf: { |
| 5691 | OPC_CheckPredicate, 31, // 5383: check predicate 31 |
| 5692 | OPC_CheckField, 4, 1, 0, // 5385: check Inst[4] == 0x0 |
| 5693 | OPC_Decode, 137, 11, 184, 1, // 5389: decode to MVE_VMOVNi32th using decoder 184 |
| 5694 | // 5389: } |
| 5695 | // 5389: } // switch Inst[31:28] |
| 5696 | // 5389: } |
| 5697 | // 5389: } // switch Inst[12] |
| 5698 | // 5389: } |
| 5699 | // 5389: } // switch Inst[7] |
| 5700 | // 5389: } |
| 5701 | 3, 109, // 5394: case 0x3: { |
| 5702 | OPC_SwitchField, 7, 1, // 5396: switch Inst[7] { |
| 5703 | 0, 65, // 5399: case 0x0: { |
| 5704 | OPC_SwitchField, 12, 1, // 5401: switch Inst[12] { |
| 5705 | 0, 29, // 5404: case 0x0: { |
| 5706 | OPC_SwitchField, 28, 4, // 5406: switch Inst[31:28] { |
| 5707 | 14, 11, // 5409: case 0xe: { |
| 5708 | OPC_CheckPredicate, 31, // 5411: check predicate 31 |
| 5709 | OPC_CheckField, 4, 1, 0, // 5413: check Inst[4] == 0x0 |
| 5710 | OPC_Decode, 143, 12, 184, 1, // 5417: decode to MVE_VQMOVNs32bh using decoder 184 |
| 5711 | // 5417: } |
| 5712 | 15, 0, // 5422: case 0xf: { |
| 5713 | OPC_CheckPredicate, 31, // 5424: check predicate 31 |
| 5714 | OPC_CheckField, 4, 1, 0, // 5426: check Inst[4] == 0x0 |
| 5715 | OPC_Decode, 147, 12, 184, 1, // 5430: decode to MVE_VQMOVNu32bh using decoder 184 |
| 5716 | // 5430: } |
| 5717 | // 5430: } // switch Inst[31:28] |
| 5718 | // 5430: } |
| 5719 | 1, 0, // 5435: case 0x1: { |
| 5720 | OPC_SwitchField, 28, 4, // 5437: switch Inst[31:28] { |
| 5721 | 14, 11, // 5440: case 0xe: { |
| 5722 | OPC_CheckPredicate, 31, // 5442: check predicate 31 |
| 5723 | OPC_CheckField, 4, 1, 0, // 5444: check Inst[4] == 0x0 |
| 5724 | OPC_Decode, 144, 12, 184, 1, // 5448: decode to MVE_VQMOVNs32th using decoder 184 |
| 5725 | // 5448: } |
| 5726 | 15, 0, // 5453: case 0xf: { |
| 5727 | OPC_CheckPredicate, 31, // 5455: check predicate 31 |
| 5728 | OPC_CheckField, 4, 1, 0, // 5457: check Inst[4] == 0x0 |
| 5729 | OPC_Decode, 148, 12, 184, 1, // 5461: decode to MVE_VQMOVNu32th using decoder 184 |
| 5730 | // 5461: } |
| 5731 | // 5461: } // switch Inst[31:28] |
| 5732 | // 5461: } |
| 5733 | // 5461: } // switch Inst[12] |
| 5734 | // 5461: } |
| 5735 | 1, 0, // 5466: case 0x1: { |
| 5736 | OPC_SwitchField, 12, 1, // 5468: switch Inst[12] { |
| 5737 | 0, 15, // 5471: case 0x0: { |
| 5738 | OPC_CheckPredicate, 31, // 5473: check predicate 31 |
| 5739 | OPC_CheckField, 28, 4, 14, // 5475: check Inst[31:28] == 0xe |
| 5740 | OPC_CheckField, 4, 1, 0, // 5479: check Inst[4] == 0x0 |
| 5741 | OPC_Decode, 149, 10, 184, 1, // 5483: decode to MVE_VMAXAs16 using decoder 184 |
| 5742 | // 5483: } |
| 5743 | 1, 0, // 5488: case 0x1: { |
| 5744 | OPC_CheckPredicate, 31, // 5490: check predicate 31 |
| 5745 | OPC_CheckField, 28, 4, 14, // 5492: check Inst[31:28] == 0xe |
| 5746 | OPC_CheckField, 4, 1, 0, // 5496: check Inst[4] == 0x0 |
| 5747 | OPC_Decode, 175, 10, 184, 1, // 5500: decode to MVE_VMINAs16 using decoder 184 |
| 5748 | // 5500: } |
| 5749 | // 5500: } // switch Inst[12] |
| 5750 | // 5500: } |
| 5751 | // 5500: } // switch Inst[7] |
| 5752 | // 5500: } |
| 5753 | 5, 45, // 5505: case 0x5: { |
| 5754 | OPC_SwitchField, 12, 1, // 5507: switch Inst[12] { |
| 5755 | 0, 19, // 5510: case 0x0: { |
| 5756 | OPC_CheckPredicate, 31, // 5512: check predicate 31 |
| 5757 | OPC_CheckField, 28, 4, 14, // 5514: check Inst[31:28] == 0xe |
| 5758 | OPC_CheckField, 7, 1, 1, // 5518: check Inst[7] == 0x1 |
| 5759 | OPC_CheckField, 4, 1, 0, // 5522: check Inst[4] == 0x0 |
| 5760 | OPC_Decode, 150, 10, 184, 1, // 5526: decode to MVE_VMAXAs32 using decoder 184 |
| 5761 | // 5526: } |
| 5762 | 1, 0, // 5531: case 0x1: { |
| 5763 | OPC_CheckPredicate, 31, // 5533: check predicate 31 |
| 5764 | OPC_CheckField, 28, 4, 14, // 5535: check Inst[31:28] == 0xe |
| 5765 | OPC_CheckField, 7, 1, 1, // 5539: check Inst[7] == 0x1 |
| 5766 | OPC_CheckField, 4, 1, 0, // 5543: check Inst[4] == 0x0 |
| 5767 | OPC_Decode, 176, 10, 184, 1, // 5547: decode to MVE_VMINAs32 using decoder 184 |
| 5768 | // 5547: } |
| 5769 | // 5547: } // switch Inst[12] |
| 5770 | // 5547: } |
| 5771 | 7, 0, // 5552: case 0x7: { |
| 5772 | OPC_SwitchField, 7, 1, // 5554: switch Inst[7] { |
| 5773 | 0, 65, // 5557: case 0x0: { |
| 5774 | OPC_SwitchField, 12, 1, // 5559: switch Inst[12] { |
| 5775 | 0, 29, // 5562: case 0x0: { |
| 5776 | OPC_SwitchField, 28, 4, // 5564: switch Inst[31:28] { |
| 5777 | 14, 11, // 5567: case 0xe: { |
| 5778 | OPC_CheckPredicate, 33, // 5569: check predicate 33 |
| 5779 | OPC_CheckField, 4, 1, 0, // 5571: check Inst[4] == 0x0 |
| 5780 | OPC_Decode, 233, 8, 184, 1, // 5575: decode to MVE_VCVTf16f32bh using decoder 184 |
| 5781 | // 5575: } |
| 5782 | 15, 0, // 5580: case 0xf: { |
| 5783 | OPC_CheckPredicate, 33, // 5582: check predicate 33 |
| 5784 | OPC_CheckField, 4, 1, 0, // 5584: check Inst[4] == 0x0 |
| 5785 | OPC_Decode, 239, 8, 183, 1, // 5588: decode to MVE_VCVTf32f16bh using decoder 183 |
| 5786 | // 5588: } |
| 5787 | // 5588: } // switch Inst[31:28] |
| 5788 | // 5588: } |
| 5789 | 1, 0, // 5593: case 0x1: { |
| 5790 | OPC_SwitchField, 28, 4, // 5595: switch Inst[31:28] { |
| 5791 | 14, 11, // 5598: case 0xe: { |
| 5792 | OPC_CheckPredicate, 33, // 5600: check predicate 33 |
| 5793 | OPC_CheckField, 4, 1, 0, // 5602: check Inst[4] == 0x0 |
| 5794 | OPC_Decode, 234, 8, 184, 1, // 5606: decode to MVE_VCVTf16f32th using decoder 184 |
| 5795 | // 5606: } |
| 5796 | 15, 0, // 5611: case 0xf: { |
| 5797 | OPC_CheckPredicate, 33, // 5613: check predicate 33 |
| 5798 | OPC_CheckField, 4, 1, 0, // 5615: check Inst[4] == 0x0 |
| 5799 | OPC_Decode, 240, 8, 183, 1, // 5619: decode to MVE_VCVTf32f16th using decoder 183 |
| 5800 | // 5619: } |
| 5801 | // 5619: } // switch Inst[31:28] |
| 5802 | // 5619: } |
| 5803 | // 5619: } // switch Inst[12] |
| 5804 | // 5619: } |
| 5805 | 1, 0, // 5624: case 0x1: { |
| 5806 | OPC_SwitchField, 12, 1, // 5626: switch Inst[12] { |
| 5807 | 0, 29, // 5629: case 0x0: { |
| 5808 | OPC_SwitchField, 28, 4, // 5631: switch Inst[31:28] { |
| 5809 | 14, 11, // 5634: case 0xe: { |
| 5810 | OPC_CheckPredicate, 33, // 5636: check predicate 33 |
| 5811 | OPC_CheckField, 4, 1, 0, // 5638: check Inst[4] == 0x0 |
| 5812 | OPC_Decode, 155, 10, 184, 1, // 5642: decode to MVE_VMAXNMAf32 using decoder 184 |
| 5813 | // 5642: } |
| 5814 | 15, 0, // 5647: case 0xf: { |
| 5815 | OPC_CheckPredicate, 33, // 5649: check predicate 33 |
| 5816 | OPC_CheckField, 4, 1, 0, // 5651: check Inst[4] == 0x0 |
| 5817 | OPC_Decode, 154, 10, 184, 1, // 5655: decode to MVE_VMAXNMAf16 using decoder 184 |
| 5818 | // 5655: } |
| 5819 | // 5655: } // switch Inst[31:28] |
| 5820 | // 5655: } |
| 5821 | 1, 0, // 5660: case 0x1: { |
| 5822 | OPC_SwitchField, 28, 4, // 5662: switch Inst[31:28] { |
| 5823 | 14, 11, // 5665: case 0xe: { |
| 5824 | OPC_CheckPredicate, 33, // 5667: check predicate 33 |
| 5825 | OPC_CheckField, 4, 1, 0, // 5669: check Inst[4] == 0x0 |
| 5826 | OPC_Decode, 181, 10, 184, 1, // 5673: decode to MVE_VMINNMAf32 using decoder 184 |
| 5827 | // 5673: } |
| 5828 | 15, 0, // 5678: case 0xf: { |
| 5829 | OPC_CheckPredicate, 33, // 5680: check predicate 33 |
| 5830 | OPC_CheckField, 4, 1, 0, // 5682: check Inst[4] == 0x0 |
| 5831 | OPC_Decode, 180, 10, 184, 1, // 5686: decode to MVE_VMINNMAf16 using decoder 184 |
| 5832 | // 5686: } |
| 5833 | // 5686: } // switch Inst[31:28] |
| 5834 | // 5686: } |
| 5835 | // 5686: } // switch Inst[12] |
| 5836 | // 5686: } |
| 5837 | // 5686: } // switch Inst[7] |
| 5838 | // 5686: } |
| 5839 | // 5686: } // switch Inst[19:17] |
| 5840 | // 5686: } |
| 5841 | // 5686: } // switch Inst[0] |
| 5842 | // 5686: } |
| 5843 | // 5686: } // switch Inst[16] |
| 5844 | // 5686: } |
| 5845 | 1, 0, // 5691: case 0x1: { |
| 5846 | OPC_SwitchField, 4, 2, // 5693: switch Inst[5:4] { |
| 5847 | 0, 65, // 5696: case 0x0: { |
| 5848 | OPC_SwitchField, 12, 1, // 5698: switch Inst[12] { |
| 5849 | 0, 29, // 5701: case 0x0: { |
| 5850 | OPC_SwitchField, 28, 4, // 5703: switch Inst[31:28] { |
| 5851 | 14, 11, // 5706: case 0xe: { |
| 5852 | OPC_CheckPredicate, 33, // 5708: check predicate 33 |
| 5853 | OPC_CheckField, 16, 1, 1, // 5710: check Inst[16] == 0x1 |
| 5854 | OPC_Decode, 154, 9, 180, 1, // 5714: decode to MVE_VFMA_qr_f32 using decoder 180 |
| 5855 | // 5714: } |
| 5856 | 15, 0, // 5719: case 0xf: { |
| 5857 | OPC_CheckPredicate, 33, // 5721: check predicate 33 |
| 5858 | OPC_CheckField, 16, 1, 1, // 5723: check Inst[16] == 0x1 |
| 5859 | OPC_Decode, 153, 9, 180, 1, // 5727: decode to MVE_VFMA_qr_f16 using decoder 180 |
| 5860 | // 5727: } |
| 5861 | // 5727: } // switch Inst[31:28] |
| 5862 | // 5727: } |
| 5863 | 1, 0, // 5732: case 0x1: { |
| 5864 | OPC_SwitchField, 28, 4, // 5734: switch Inst[31:28] { |
| 5865 | 14, 11, // 5737: case 0xe: { |
| 5866 | OPC_CheckPredicate, 33, // 5739: check predicate 33 |
| 5867 | OPC_CheckField, 16, 1, 1, // 5741: check Inst[16] == 0x1 |
| 5868 | OPC_Decode, 152, 9, 180, 1, // 5745: decode to MVE_VFMA_qr_Sf32 using decoder 180 |
| 5869 | // 5745: } |
| 5870 | 15, 0, // 5750: case 0xf: { |
| 5871 | OPC_CheckPredicate, 33, // 5752: check predicate 33 |
| 5872 | OPC_CheckField, 16, 1, 1, // 5754: check Inst[16] == 0x1 |
| 5873 | OPC_Decode, 151, 9, 180, 1, // 5758: decode to MVE_VFMA_qr_Sf16 using decoder 180 |
| 5874 | // 5758: } |
| 5875 | // 5758: } // switch Inst[31:28] |
| 5876 | // 5758: } |
| 5877 | // 5758: } // switch Inst[12] |
| 5878 | // 5758: } |
| 5879 | 2, 0, // 5763: case 0x2: { |
| 5880 | OPC_SwitchField, 12, 1, // 5765: switch Inst[12] { |
| 5881 | 0, 29, // 5768: case 0x0: { |
| 5882 | OPC_SwitchField, 28, 4, // 5770: switch Inst[31:28] { |
| 5883 | 14, 11, // 5773: case 0xe: { |
| 5884 | OPC_CheckPredicate, 33, // 5775: check predicate 33 |
| 5885 | OPC_CheckField, 16, 1, 1, // 5777: check Inst[16] == 0x1 |
| 5886 | OPC_Decode, 176, 11, 181, 1, // 5781: decode to MVE_VMUL_qr_f32 using decoder 181 |
| 5887 | // 5781: } |
| 5888 | 15, 0, // 5786: case 0xf: { |
| 5889 | OPC_CheckPredicate, 33, // 5788: check predicate 33 |
| 5890 | OPC_CheckField, 16, 1, 1, // 5790: check Inst[16] == 0x1 |
| 5891 | OPC_Decode, 175, 11, 181, 1, // 5794: decode to MVE_VMUL_qr_f16 using decoder 181 |
| 5892 | // 5794: } |
| 5893 | // 5794: } // switch Inst[31:28] |
| 5894 | // 5794: } |
| 5895 | 1, 0, // 5799: case 0x1: { |
| 5896 | OPC_SwitchField, 16, 4, // 5801: switch Inst[19:16] { |
| 5897 | 1, 49, // 5804: case 0x1: { |
| 5898 | OPC_SwitchField, 7, 1, // 5806: switch Inst[7] { |
| 5899 | 0, 21, // 5809: case 0x0: { |
| 5900 | OPC_SwitchField, 28, 4, // 5811: switch Inst[31:28] { |
| 5901 | 14, 7, // 5814: case 0xe: { |
| 5902 | OPC_CheckPredicate, 31, // 5816: check predicate 31 |
| 5903 | OPC_Decode, 213, 13, 185, 1, // 5818: decode to MVE_VSHL_qrs8 using decoder 185 |
| 5904 | // 5818: } |
| 5905 | 15, 0, // 5823: case 0xf: { |
| 5906 | OPC_CheckPredicate, 31, // 5825: check predicate 31 |
| 5907 | OPC_Decode, 216, 13, 185, 1, // 5827: decode to MVE_VSHL_qru8 using decoder 185 |
| 5908 | // 5827: } |
| 5909 | // 5827: } // switch Inst[31:28] |
| 5910 | // 5827: } |
| 5911 | 1, 0, // 5832: case 0x1: { |
| 5912 | OPC_SwitchField, 28, 4, // 5834: switch Inst[31:28] { |
| 5913 | 14, 7, // 5837: case 0xe: { |
| 5914 | OPC_CheckPredicate, 31, // 5839: check predicate 31 |
| 5915 | OPC_Decode, 215, 12, 185, 1, // 5841: decode to MVE_VQSHL_qrs8 using decoder 185 |
| 5916 | // 5841: } |
| 5917 | 15, 0, // 5846: case 0xf: { |
| 5918 | OPC_CheckPredicate, 31, // 5848: check predicate 31 |
| 5919 | OPC_Decode, 218, 12, 185, 1, // 5850: decode to MVE_VQSHL_qru8 using decoder 185 |
| 5920 | // 5850: } |
| 5921 | // 5850: } // switch Inst[31:28] |
| 5922 | // 5850: } |
| 5923 | // 5850: } // switch Inst[7] |
| 5924 | // 5850: } |
| 5925 | 3, 49, // 5855: case 0x3: { |
| 5926 | OPC_SwitchField, 7, 1, // 5857: switch Inst[7] { |
| 5927 | 0, 21, // 5860: case 0x0: { |
| 5928 | OPC_SwitchField, 28, 4, // 5862: switch Inst[31:28] { |
| 5929 | 14, 7, // 5865: case 0xe: { |
| 5930 | OPC_CheckPredicate, 31, // 5867: check predicate 31 |
| 5931 | OPC_Decode, 169, 13, 185, 1, // 5869: decode to MVE_VRSHL_qrs8 using decoder 185 |
| 5932 | // 5869: } |
| 5933 | 15, 0, // 5874: case 0xf: { |
| 5934 | OPC_CheckPredicate, 31, // 5876: check predicate 31 |
| 5935 | OPC_Decode, 172, 13, 185, 1, // 5878: decode to MVE_VRSHL_qru8 using decoder 185 |
| 5936 | // 5878: } |
| 5937 | // 5878: } // switch Inst[31:28] |
| 5938 | // 5878: } |
| 5939 | 1, 0, // 5883: case 0x1: { |
| 5940 | OPC_SwitchField, 28, 4, // 5885: switch Inst[31:28] { |
| 5941 | 14, 7, // 5888: case 0xe: { |
| 5942 | OPC_CheckPredicate, 31, // 5890: check predicate 31 |
| 5943 | OPC_Decode, 188, 12, 185, 1, // 5892: decode to MVE_VQRSHL_qrs8 using decoder 185 |
| 5944 | // 5892: } |
| 5945 | 15, 0, // 5897: case 0xf: { |
| 5946 | OPC_CheckPredicate, 31, // 5899: check predicate 31 |
| 5947 | OPC_Decode, 191, 12, 185, 1, // 5901: decode to MVE_VQRSHL_qru8 using decoder 185 |
| 5948 | // 5901: } |
| 5949 | // 5901: } // switch Inst[31:28] |
| 5950 | // 5901: } |
| 5951 | // 5901: } // switch Inst[7] |
| 5952 | // 5901: } |
| 5953 | 5, 49, // 5906: case 0x5: { |
| 5954 | OPC_SwitchField, 7, 1, // 5908: switch Inst[7] { |
| 5955 | 0, 21, // 5911: case 0x0: { |
| 5956 | OPC_SwitchField, 28, 4, // 5913: switch Inst[31:28] { |
| 5957 | 14, 7, // 5916: case 0xe: { |
| 5958 | OPC_CheckPredicate, 31, // 5918: check predicate 31 |
| 5959 | OPC_Decode, 211, 13, 185, 1, // 5920: decode to MVE_VSHL_qrs16 using decoder 185 |
| 5960 | // 5920: } |
| 5961 | 15, 0, // 5925: case 0xf: { |
| 5962 | OPC_CheckPredicate, 31, // 5927: check predicate 31 |
| 5963 | OPC_Decode, 214, 13, 185, 1, // 5929: decode to MVE_VSHL_qru16 using decoder 185 |
| 5964 | // 5929: } |
| 5965 | // 5929: } // switch Inst[31:28] |
| 5966 | // 5929: } |
| 5967 | 1, 0, // 5934: case 0x1: { |
| 5968 | OPC_SwitchField, 28, 4, // 5936: switch Inst[31:28] { |
| 5969 | 14, 7, // 5939: case 0xe: { |
| 5970 | OPC_CheckPredicate, 31, // 5941: check predicate 31 |
| 5971 | OPC_Decode, 213, 12, 185, 1, // 5943: decode to MVE_VQSHL_qrs16 using decoder 185 |
| 5972 | // 5943: } |
| 5973 | 15, 0, // 5948: case 0xf: { |
| 5974 | OPC_CheckPredicate, 31, // 5950: check predicate 31 |
| 5975 | OPC_Decode, 216, 12, 185, 1, // 5952: decode to MVE_VQSHL_qru16 using decoder 185 |
| 5976 | // 5952: } |
| 5977 | // 5952: } // switch Inst[31:28] |
| 5978 | // 5952: } |
| 5979 | // 5952: } // switch Inst[7] |
| 5980 | // 5952: } |
| 5981 | 7, 49, // 5957: case 0x7: { |
| 5982 | OPC_SwitchField, 7, 1, // 5959: switch Inst[7] { |
| 5983 | 0, 21, // 5962: case 0x0: { |
| 5984 | OPC_SwitchField, 28, 4, // 5964: switch Inst[31:28] { |
| 5985 | 14, 7, // 5967: case 0xe: { |
| 5986 | OPC_CheckPredicate, 31, // 5969: check predicate 31 |
| 5987 | OPC_Decode, 167, 13, 185, 1, // 5971: decode to MVE_VRSHL_qrs16 using decoder 185 |
| 5988 | // 5971: } |
| 5989 | 15, 0, // 5976: case 0xf: { |
| 5990 | OPC_CheckPredicate, 31, // 5978: check predicate 31 |
| 5991 | OPC_Decode, 170, 13, 185, 1, // 5980: decode to MVE_VRSHL_qru16 using decoder 185 |
| 5992 | // 5980: } |
| 5993 | // 5980: } // switch Inst[31:28] |
| 5994 | // 5980: } |
| 5995 | 1, 0, // 5985: case 0x1: { |
| 5996 | OPC_SwitchField, 28, 4, // 5987: switch Inst[31:28] { |
| 5997 | 14, 7, // 5990: case 0xe: { |
| 5998 | OPC_CheckPredicate, 31, // 5992: check predicate 31 |
| 5999 | OPC_Decode, 186, 12, 185, 1, // 5994: decode to MVE_VQRSHL_qrs16 using decoder 185 |
| 6000 | // 5994: } |
| 6001 | 15, 0, // 5999: case 0xf: { |
| 6002 | OPC_CheckPredicate, 31, // 6001: check predicate 31 |
| 6003 | OPC_Decode, 189, 12, 185, 1, // 6003: decode to MVE_VQRSHL_qru16 using decoder 185 |
| 6004 | // 6003: } |
| 6005 | // 6003: } // switch Inst[31:28] |
| 6006 | // 6003: } |
| 6007 | // 6003: } // switch Inst[7] |
| 6008 | // 6003: } |
| 6009 | 9, 49, // 6008: case 0x9: { |
| 6010 | OPC_SwitchField, 7, 1, // 6010: switch Inst[7] { |
| 6011 | 0, 21, // 6013: case 0x0: { |
| 6012 | OPC_SwitchField, 28, 4, // 6015: switch Inst[31:28] { |
| 6013 | 14, 7, // 6018: case 0xe: { |
| 6014 | OPC_CheckPredicate, 31, // 6020: check predicate 31 |
| 6015 | OPC_Decode, 212, 13, 185, 1, // 6022: decode to MVE_VSHL_qrs32 using decoder 185 |
| 6016 | // 6022: } |
| 6017 | 15, 0, // 6027: case 0xf: { |
| 6018 | OPC_CheckPredicate, 31, // 6029: check predicate 31 |
| 6019 | OPC_Decode, 215, 13, 185, 1, // 6031: decode to MVE_VSHL_qru32 using decoder 185 |
| 6020 | // 6031: } |
| 6021 | // 6031: } // switch Inst[31:28] |
| 6022 | // 6031: } |
| 6023 | 1, 0, // 6036: case 0x1: { |
| 6024 | OPC_SwitchField, 28, 4, // 6038: switch Inst[31:28] { |
| 6025 | 14, 7, // 6041: case 0xe: { |
| 6026 | OPC_CheckPredicate, 31, // 6043: check predicate 31 |
| 6027 | OPC_Decode, 214, 12, 185, 1, // 6045: decode to MVE_VQSHL_qrs32 using decoder 185 |
| 6028 | // 6045: } |
| 6029 | 15, 0, // 6050: case 0xf: { |
| 6030 | OPC_CheckPredicate, 31, // 6052: check predicate 31 |
| 6031 | OPC_Decode, 217, 12, 185, 1, // 6054: decode to MVE_VQSHL_qru32 using decoder 185 |
| 6032 | // 6054: } |
| 6033 | // 6054: } // switch Inst[31:28] |
| 6034 | // 6054: } |
| 6035 | // 6054: } // switch Inst[7] |
| 6036 | // 6054: } |
| 6037 | 11, 0, // 6059: case 0xb: { |
| 6038 | OPC_SwitchField, 7, 1, // 6061: switch Inst[7] { |
| 6039 | 0, 21, // 6064: case 0x0: { |
| 6040 | OPC_SwitchField, 28, 4, // 6066: switch Inst[31:28] { |
| 6041 | 14, 7, // 6069: case 0xe: { |
| 6042 | OPC_CheckPredicate, 31, // 6071: check predicate 31 |
| 6043 | OPC_Decode, 168, 13, 185, 1, // 6073: decode to MVE_VRSHL_qrs32 using decoder 185 |
| 6044 | // 6073: } |
| 6045 | 15, 0, // 6078: case 0xf: { |
| 6046 | OPC_CheckPredicate, 31, // 6080: check predicate 31 |
| 6047 | OPC_Decode, 171, 13, 185, 1, // 6082: decode to MVE_VRSHL_qru32 using decoder 185 |
| 6048 | // 6082: } |
| 6049 | // 6082: } // switch Inst[31:28] |
| 6050 | // 6082: } |
| 6051 | 1, 0, // 6087: case 0x1: { |
| 6052 | OPC_SwitchField, 28, 4, // 6089: switch Inst[31:28] { |
| 6053 | 14, 7, // 6092: case 0xe: { |
| 6054 | OPC_CheckPredicate, 31, // 6094: check predicate 31 |
| 6055 | OPC_Decode, 187, 12, 185, 1, // 6096: decode to MVE_VQRSHL_qrs32 using decoder 185 |
| 6056 | // 6096: } |
| 6057 | 15, 0, // 6101: case 0xf: { |
| 6058 | OPC_CheckPredicate, 31, // 6103: check predicate 31 |
| 6059 | OPC_Decode, 190, 12, 185, 1, // 6105: decode to MVE_VQRSHL_qru32 using decoder 185 |
| 6060 | // 6105: } |
| 6061 | // 6105: } // switch Inst[31:28] |
| 6062 | // 6105: } |
| 6063 | // 6105: } // switch Inst[7] |
| 6064 | // 6105: } |
| 6065 | // 6105: } // switch Inst[19:16] |
| 6066 | // 6105: } |
| 6067 | // 6105: } // switch Inst[12] |
| 6068 | // 6105: } |
| 6069 | // 6105: } // switch Inst[5:4] |
| 6070 | // 6105: } |
| 6071 | // 6105: } // switch Inst[6] |
| 6072 | // 6105: } |
| 6073 | // 6105: } // switch Inst[21:20] |
| 6074 | // 6105: } |
| 6075 | 15, 0, // 6110: case 0xf: { |
| 6076 | OPC_SwitchField, 20, 2, // 6112: switch Inst[21:20] { |
| 6077 | 0, 191, 3, // 6115: case 0x0: { |
| 6078 | OPC_SwitchField, 6, 1, // 6118: switch Inst[6] { |
| 6079 | 0, 154, 1, // 6121: case 0x0: { |
| 6080 | OPC_SwitchField, 16, 1, // 6124: switch Inst[16] { |
| 6081 | 0, 37, // 6127: case 0x0: { |
| 6082 | OPC_SwitchField, 28, 4, // 6129: switch Inst[31:28] { |
| 6083 | 14, 15, // 6132: case 0xe: { |
| 6084 | OPC_CheckPredicate, 31, // 6134: check predicate 31 |
| 6085 | OPC_CheckField, 4, 1, 0, // 6136: check Inst[4] == 0x0 |
| 6086 | OPC_CheckField, 0, 1, 0, // 6140: check Inst[0] == 0x0 |
| 6087 | OPC_Decode, 173, 9, 186, 1, // 6144: decode to MVE_VHCADDs8 using decoder 186 |
| 6088 | // 6144: } |
| 6089 | 15, 0, // 6149: case 0xf: { |
| 6090 | OPC_CheckPredicate, 31, // 6151: check predicate 31 |
| 6091 | OPC_CheckField, 4, 1, 0, // 6153: check Inst[4] == 0x0 |
| 6092 | OPC_CheckField, 0, 1, 0, // 6157: check Inst[0] == 0x0 |
| 6093 | OPC_Decode, 196, 8, 186, 1, // 6161: decode to MVE_VCADDi8 using decoder 186 |
| 6094 | // 6161: } |
| 6095 | // 6161: } // switch Inst[31:28] |
| 6096 | // 6161: } |
| 6097 | 1, 0, // 6166: case 0x1: { |
| 6098 | OPC_SwitchField, 12, 1, // 6168: switch Inst[12] { |
| 6099 | 0, 71, // 6171: case 0x0: { |
| 6100 | OPC_SwitchField, 0, 1, // 6173: switch Inst[0] { |
| 6101 | 0, 32, // 6176: case 0x0: { |
| 6102 | OPC_CheckField, 4, 1, 0, // 6178: check Inst[4] == 0x0 |
| 6103 | OPC_CheckField, 28, 4, 15, // 6182: check Inst[31:28] == 0xf |
| 6104 | OPC_Scope, 15, // 6186: try { |
| 6105 | OPC_CheckField, 13, 3, 0, // 6188: check Inst[15:13] == 0x0 |
| 6106 | OPC_CheckPredicate, 31, // 6192: check predicate 31 |
| 6107 | OPC_CheckField, 22, 1, 0, // 6194: check Inst[22] == 0x0 |
| 6108 | OPC_Decode, 213, 8, 187, 1, // 6198: decode to MVE_VCMPi8 using decoder 187 |
| 6109 | // 6198: } else try { |
| 6110 | OPC_CheckPredicate, 31, // 6203: check predicate 31 |
| 6111 | OPC_Decode, 200, 11, 188, 1, // 6205: decode to MVE_VPTv16i8 using decoder 188 |
| 6112 | // 6205: } |
| 6113 | // 6205: } |
| 6114 | 1, 0, // 6210: case 0x1: { |
| 6115 | OPC_CheckField, 4, 1, 0, // 6212: check Inst[4] == 0x0 |
| 6116 | OPC_CheckField, 28, 4, 15, // 6216: check Inst[31:28] == 0xf |
| 6117 | OPC_Scope, 15, // 6220: try { |
| 6118 | OPC_CheckField, 13, 3, 0, // 6222: check Inst[15:13] == 0x0 |
| 6119 | OPC_CheckPredicate, 31, // 6226: check predicate 31 |
| 6120 | OPC_CheckField, 22, 1, 0, // 6228: check Inst[22] == 0x0 |
| 6121 | OPC_Decode, 225, 8, 189, 1, // 6232: decode to MVE_VCMPu8 using decoder 189 |
| 6122 | // 6232: } else try { |
| 6123 | OPC_CheckPredicate, 31, // 6237: check predicate 31 |
| 6124 | OPC_Decode, 204, 11, 190, 1, // 6239: decode to MVE_VPTv16u8 using decoder 190 |
| 6125 | // 6239: } |
| 6126 | // 6239: } |
| 6127 | // 6239: } // switch Inst[0] |
| 6128 | // 6239: } |
| 6129 | 1, 0, // 6244: case 0x1: { |
| 6130 | OPC_CheckField, 4, 1, 0, // 6246: check Inst[4] == 0x0 |
| 6131 | OPC_CheckField, 28, 4, 15, // 6250: check Inst[31:28] == 0xf |
| 6132 | OPC_Scope, 15, // 6254: try { |
| 6133 | OPC_CheckField, 13, 3, 0, // 6256: check Inst[15:13] == 0x0 |
| 6134 | OPC_CheckPredicate, 31, // 6260: check predicate 31 |
| 6135 | OPC_CheckField, 22, 1, 0, // 6262: check Inst[22] == 0x0 |
| 6136 | OPC_Decode, 219, 8, 191, 1, // 6266: decode to MVE_VCMPs8 using decoder 191 |
| 6137 | // 6266: } else try { |
| 6138 | OPC_CheckPredicate, 31, // 6271: check predicate 31 |
| 6139 | OPC_Decode, 202, 11, 192, 1, // 6273: decode to MVE_VPTv16s8 using decoder 192 |
| 6140 | // 6273: } |
| 6141 | // 6273: } |
| 6142 | // 6273: } // switch Inst[12] |
| 6143 | // 6273: } |
| 6144 | // 6273: } // switch Inst[16] |
| 6145 | // 6273: } |
| 6146 | 1, 0, // 6278: case 0x1: { |
| 6147 | OPC_SwitchField, 12, 1, // 6280: switch Inst[12] { |
| 6148 | 0, 152, 1, // 6283: case 0x0: { |
| 6149 | OPC_SwitchField, 4, 2, // 6286: switch Inst[5:4] { |
| 6150 | 0, 66, // 6289: case 0x0: { |
| 6151 | OPC_SwitchField, 16, 1, // 6291: switch Inst[16] { |
| 6152 | 0, 21, // 6294: case 0x0: { |
| 6153 | OPC_SwitchField, 28, 4, // 6296: switch Inst[31:28] { |
| 6154 | 14, 7, // 6299: case 0xe: { |
| 6155 | OPC_CheckPredicate, 31, // 6301: check predicate 31 |
| 6156 | OPC_Decode, 161, 9, 181, 1, // 6303: decode to MVE_VHADD_qr_s8 using decoder 181 |
| 6157 | // 6303: } |
| 6158 | 15, 0, // 6308: case 0xf: { |
| 6159 | OPC_CheckPredicate, 31, // 6310: check predicate 31 |
| 6160 | OPC_Decode, 164, 9, 181, 1, // 6312: decode to MVE_VHADD_qr_u8 using decoder 181 |
| 6161 | // 6312: } |
| 6162 | // 6312: } // switch Inst[31:28] |
| 6163 | // 6312: } |
| 6164 | 1, 0, // 6317: case 0x1: { |
| 6165 | OPC_SwitchField, 28, 4, // 6319: switch Inst[31:28] { |
| 6166 | 14, 7, // 6322: case 0xe: { |
| 6167 | OPC_CheckPredicate, 31, // 6324: check predicate 31 |
| 6168 | OPC_Decode, 179, 8, 181, 1, // 6326: decode to MVE_VADD_qr_i8 using decoder 181 |
| 6169 | // 6326: } |
| 6170 | 15, 0, // 6331: case 0xf: { |
| 6171 | OPC_Scope, 15, // 6333: try { |
| 6172 | OPC_CheckField, 13, 3, 0, // 6335: check Inst[15:13] == 0x0 |
| 6173 | OPC_CheckPredicate, 31, // 6339: check predicate 31 |
| 6174 | OPC_CheckField, 22, 1, 0, // 6341: check Inst[22] == 0x0 |
| 6175 | OPC_Decode, 214, 8, 193, 1, // 6345: decode to MVE_VCMPi8r using decoder 193 |
| 6176 | // 6345: } else try { |
| 6177 | OPC_CheckPredicate, 31, // 6350: check predicate 31 |
| 6178 | OPC_Decode, 201, 11, 194, 1, // 6352: decode to MVE_VPTv16i8r using decoder 194 |
| 6179 | // 6352: } |
| 6180 | // 6352: } |
| 6181 | // 6352: } // switch Inst[31:28] |
| 6182 | // 6352: } |
| 6183 | // 6352: } // switch Inst[16] |
| 6184 | // 6352: } |
| 6185 | 2, 0, // 6357: case 0x2: { |
| 6186 | OPC_SwitchField, 16, 1, // 6359: switch Inst[16] { |
| 6187 | 0, 21, // 6362: case 0x0: { |
| 6188 | OPC_SwitchField, 28, 4, // 6364: switch Inst[31:28] { |
| 6189 | 14, 7, // 6367: case 0xe: { |
| 6190 | OPC_CheckPredicate, 31, // 6369: check predicate 31 |
| 6191 | OPC_Decode, 227, 11, 181, 1, // 6371: decode to MVE_VQADD_qr_s8 using decoder 181 |
| 6192 | // 6371: } |
| 6193 | 15, 0, // 6376: case 0xf: { |
| 6194 | OPC_CheckPredicate, 31, // 6378: check predicate 31 |
| 6195 | OPC_Decode, 230, 11, 181, 1, // 6380: decode to MVE_VQADD_qr_u8 using decoder 181 |
| 6196 | // 6380: } |
| 6197 | // 6380: } // switch Inst[31:28] |
| 6198 | // 6380: } |
| 6199 | 1, 0, // 6385: case 0x1: { |
| 6200 | OPC_SwitchField, 28, 4, // 6387: switch Inst[31:28] { |
| 6201 | 14, 20, // 6390: case 0xe: { |
| 6202 | OPC_Scope, 11, // 6392: try { |
| 6203 | OPC_CheckField, 1, 3, 7, // 6394: check Inst[3:1] == 0x7 |
| 6204 | OPC_CheckPredicate, 31, // 6398: check predicate 31 |
| 6205 | OPC_Decode, 188, 9, 195, 1, // 6400: decode to MVE_VIDUPu8 using decoder 195 |
| 6206 | // 6400: } else try { |
| 6207 | OPC_CheckPredicate, 31, // 6405: check predicate 31 |
| 6208 | OPC_Decode, 191, 9, 196, 1, // 6407: decode to MVE_VIWDUPu8 using decoder 196 |
| 6209 | // 6407: } |
| 6210 | // 6407: } |
| 6211 | 15, 0, // 6412: case 0xf: { |
| 6212 | OPC_Scope, 15, // 6414: try { |
| 6213 | OPC_CheckField, 13, 3, 0, // 6416: check Inst[15:13] == 0x0 |
| 6214 | OPC_CheckPredicate, 31, // 6420: check predicate 31 |
| 6215 | OPC_CheckField, 22, 1, 0, // 6422: check Inst[22] == 0x0 |
| 6216 | OPC_Decode, 226, 8, 197, 1, // 6426: decode to MVE_VCMPu8r using decoder 197 |
| 6217 | // 6426: } else try { |
| 6218 | OPC_CheckPredicate, 31, // 6431: check predicate 31 |
| 6219 | OPC_Decode, 205, 11, 198, 1, // 6433: decode to MVE_VPTv16u8r using decoder 198 |
| 6220 | // 6433: } |
| 6221 | // 6433: } |
| 6222 | // 6433: } // switch Inst[31:28] |
| 6223 | // 6433: } |
| 6224 | // 6433: } // switch Inst[16] |
| 6225 | // 6433: } |
| 6226 | // 6433: } // switch Inst[5:4] |
| 6227 | // 6433: } |
| 6228 | 1, 0, // 6438: case 0x1: { |
| 6229 | OPC_SwitchField, 16, 1, // 6440: switch Inst[16] { |
| 6230 | 0, 49, // 6443: case 0x0: { |
| 6231 | OPC_SwitchField, 4, 2, // 6445: switch Inst[5:4] { |
| 6232 | 0, 21, // 6448: case 0x0: { |
| 6233 | OPC_SwitchField, 28, 4, // 6450: switch Inst[31:28] { |
| 6234 | 14, 7, // 6453: case 0xe: { |
| 6235 | OPC_CheckPredicate, 31, // 6455: check predicate 31 |
| 6236 | OPC_Decode, 176, 9, 181, 1, // 6457: decode to MVE_VHSUB_qr_s8 using decoder 181 |
| 6237 | // 6457: } |
| 6238 | 15, 0, // 6462: case 0xf: { |
| 6239 | OPC_CheckPredicate, 31, // 6464: check predicate 31 |
| 6240 | OPC_Decode, 179, 9, 181, 1, // 6466: decode to MVE_VHSUB_qr_u8 using decoder 181 |
| 6241 | // 6466: } |
| 6242 | // 6466: } // switch Inst[31:28] |
| 6243 | // 6466: } |
| 6244 | 2, 0, // 6471: case 0x2: { |
| 6245 | OPC_SwitchField, 28, 4, // 6473: switch Inst[31:28] { |
| 6246 | 14, 7, // 6476: case 0xe: { |
| 6247 | OPC_CheckPredicate, 31, // 6478: check predicate 31 |
| 6248 | OPC_Decode, 239, 12, 181, 1, // 6480: decode to MVE_VQSUB_qr_s8 using decoder 181 |
| 6249 | // 6480: } |
| 6250 | 15, 0, // 6485: case 0xf: { |
| 6251 | OPC_CheckPredicate, 31, // 6487: check predicate 31 |
| 6252 | OPC_Decode, 242, 12, 181, 1, // 6489: decode to MVE_VQSUB_qr_u8 using decoder 181 |
| 6253 | // 6489: } |
| 6254 | // 6489: } // switch Inst[31:28] |
| 6255 | // 6489: } |
| 6256 | // 6489: } // switch Inst[5:4] |
| 6257 | // 6489: } |
| 6258 | 1, 0, // 6494: case 0x1: { |
| 6259 | OPC_SwitchField, 28, 4, // 6496: switch Inst[31:28] { |
| 6260 | 14, 34, // 6499: case 0xe: { |
| 6261 | OPC_SwitchField, 4, 2, // 6501: switch Inst[5:4] { |
| 6262 | 0, 7, // 6504: case 0x0: { |
| 6263 | OPC_CheckPredicate, 31, // 6506: check predicate 31 |
| 6264 | OPC_Decode, 178, 14, 181, 1, // 6508: decode to MVE_VSUB_qr_i8 using decoder 181 |
| 6265 | // 6508: } |
| 6266 | 2, 0, // 6513: case 0x2: { |
| 6267 | OPC_Scope, 11, // 6515: try { |
| 6268 | OPC_CheckField, 1, 3, 7, // 6517: check Inst[3:1] == 0x7 |
| 6269 | OPC_CheckPredicate, 31, // 6521: check predicate 31 |
| 6270 | OPC_Decode, 143, 9, 195, 1, // 6523: decode to MVE_VDDUPu8 using decoder 195 |
| 6271 | // 6523: } else try { |
| 6272 | OPC_CheckPredicate, 31, // 6528: check predicate 31 |
| 6273 | OPC_Decode, 149, 9, 196, 1, // 6530: decode to MVE_VDWDUPu8 using decoder 196 |
| 6274 | // 6530: } |
| 6275 | // 6530: } |
| 6276 | // 6530: } // switch Inst[5:4] |
| 6277 | // 6530: } |
| 6278 | 15, 0, // 6535: case 0xf: { |
| 6279 | OPC_CheckField, 4, 1, 0, // 6537: check Inst[4] == 0x0 |
| 6280 | OPC_Scope, 15, // 6541: try { |
| 6281 | OPC_CheckField, 13, 3, 0, // 6543: check Inst[15:13] == 0x0 |
| 6282 | OPC_CheckPredicate, 31, // 6547: check predicate 31 |
| 6283 | OPC_CheckField, 22, 1, 0, // 6549: check Inst[22] == 0x0 |
| 6284 | OPC_Decode, 220, 8, 199, 1, // 6553: decode to MVE_VCMPs8r using decoder 199 |
| 6285 | // 6553: } else try { |
| 6286 | OPC_CheckPredicate, 31, // 6558: check predicate 31 |
| 6287 | OPC_Decode, 203, 11, 200, 1, // 6560: decode to MVE_VPTv16s8r using decoder 200 |
| 6288 | // 6560: } |
| 6289 | // 6560: } |
| 6290 | // 6560: } // switch Inst[31:28] |
| 6291 | // 6560: } |
| 6292 | // 6560: } // switch Inst[16] |
| 6293 | // 6560: } |
| 6294 | // 6560: } // switch Inst[12] |
| 6295 | // 6560: } |
| 6296 | // 6560: } // switch Inst[6] |
| 6297 | // 6560: } |
| 6298 | 1, 191, 3, // 6565: case 0x1: { |
| 6299 | OPC_SwitchField, 6, 1, // 6568: switch Inst[6] { |
| 6300 | 0, 154, 1, // 6571: case 0x0: { |
| 6301 | OPC_SwitchField, 16, 1, // 6574: switch Inst[16] { |
| 6302 | 0, 37, // 6577: case 0x0: { |
| 6303 | OPC_SwitchField, 28, 4, // 6579: switch Inst[31:28] { |
| 6304 | 14, 15, // 6582: case 0xe: { |
| 6305 | OPC_CheckPredicate, 31, // 6584: check predicate 31 |
| 6306 | OPC_CheckField, 4, 1, 0, // 6586: check Inst[4] == 0x0 |
| 6307 | OPC_CheckField, 0, 1, 0, // 6590: check Inst[0] == 0x0 |
| 6308 | OPC_Decode, 171, 9, 186, 1, // 6594: decode to MVE_VHCADDs16 using decoder 186 |
| 6309 | // 6594: } |
| 6310 | 15, 0, // 6599: case 0xf: { |
| 6311 | OPC_CheckPredicate, 31, // 6601: check predicate 31 |
| 6312 | OPC_CheckField, 4, 1, 0, // 6603: check Inst[4] == 0x0 |
| 6313 | OPC_CheckField, 0, 1, 0, // 6607: check Inst[0] == 0x0 |
| 6314 | OPC_Decode, 194, 8, 186, 1, // 6611: decode to MVE_VCADDi16 using decoder 186 |
| 6315 | // 6611: } |
| 6316 | // 6611: } // switch Inst[31:28] |
| 6317 | // 6611: } |
| 6318 | 1, 0, // 6616: case 0x1: { |
| 6319 | OPC_SwitchField, 12, 1, // 6618: switch Inst[12] { |
| 6320 | 0, 71, // 6621: case 0x0: { |
| 6321 | OPC_SwitchField, 0, 1, // 6623: switch Inst[0] { |
| 6322 | 0, 32, // 6626: case 0x0: { |
| 6323 | OPC_CheckField, 4, 1, 0, // 6628: check Inst[4] == 0x0 |
| 6324 | OPC_CheckField, 28, 4, 15, // 6632: check Inst[31:28] == 0xf |
| 6325 | OPC_Scope, 15, // 6636: try { |
| 6326 | OPC_CheckField, 13, 3, 0, // 6638: check Inst[15:13] == 0x0 |
| 6327 | OPC_CheckPredicate, 31, // 6642: check predicate 31 |
| 6328 | OPC_CheckField, 22, 1, 0, // 6644: check Inst[22] == 0x0 |
| 6329 | OPC_Decode, 209, 8, 187, 1, // 6648: decode to MVE_VCMPi16 using decoder 187 |
| 6330 | // 6648: } else try { |
| 6331 | OPC_CheckPredicate, 31, // 6653: check predicate 31 |
| 6332 | OPC_Decode, 216, 11, 188, 1, // 6655: decode to MVE_VPTv8i16 using decoder 188 |
| 6333 | // 6655: } |
| 6334 | // 6655: } |
| 6335 | 1, 0, // 6660: case 0x1: { |
| 6336 | OPC_CheckField, 4, 1, 0, // 6662: check Inst[4] == 0x0 |
| 6337 | OPC_CheckField, 28, 4, 15, // 6666: check Inst[31:28] == 0xf |
| 6338 | OPC_Scope, 15, // 6670: try { |
| 6339 | OPC_CheckField, 13, 3, 0, // 6672: check Inst[15:13] == 0x0 |
| 6340 | OPC_CheckPredicate, 31, // 6676: check predicate 31 |
| 6341 | OPC_CheckField, 22, 1, 0, // 6678: check Inst[22] == 0x0 |
| 6342 | OPC_Decode, 221, 8, 189, 1, // 6682: decode to MVE_VCMPu16 using decoder 189 |
| 6343 | // 6682: } else try { |
| 6344 | OPC_CheckPredicate, 31, // 6687: check predicate 31 |
| 6345 | OPC_Decode, 220, 11, 190, 1, // 6689: decode to MVE_VPTv8u16 using decoder 190 |
| 6346 | // 6689: } |
| 6347 | // 6689: } |
| 6348 | // 6689: } // switch Inst[0] |
| 6349 | // 6689: } |
| 6350 | 1, 0, // 6694: case 0x1: { |
| 6351 | OPC_CheckField, 4, 1, 0, // 6696: check Inst[4] == 0x0 |
| 6352 | OPC_CheckField, 28, 4, 15, // 6700: check Inst[31:28] == 0xf |
| 6353 | OPC_Scope, 15, // 6704: try { |
| 6354 | OPC_CheckField, 13, 3, 0, // 6706: check Inst[15:13] == 0x0 |
| 6355 | OPC_CheckPredicate, 31, // 6710: check predicate 31 |
| 6356 | OPC_CheckField, 22, 1, 0, // 6712: check Inst[22] == 0x0 |
| 6357 | OPC_Decode, 215, 8, 191, 1, // 6716: decode to MVE_VCMPs16 using decoder 191 |
| 6358 | // 6716: } else try { |
| 6359 | OPC_CheckPredicate, 31, // 6721: check predicate 31 |
| 6360 | OPC_Decode, 218, 11, 192, 1, // 6723: decode to MVE_VPTv8s16 using decoder 192 |
| 6361 | // 6723: } |
| 6362 | // 6723: } |
| 6363 | // 6723: } // switch Inst[12] |
| 6364 | // 6723: } |
| 6365 | // 6723: } // switch Inst[16] |
| 6366 | // 6723: } |
| 6367 | 1, 0, // 6728: case 0x1: { |
| 6368 | OPC_SwitchField, 12, 1, // 6730: switch Inst[12] { |
| 6369 | 0, 152, 1, // 6733: case 0x0: { |
| 6370 | OPC_SwitchField, 4, 2, // 6736: switch Inst[5:4] { |
| 6371 | 0, 66, // 6739: case 0x0: { |
| 6372 | OPC_SwitchField, 16, 1, // 6741: switch Inst[16] { |
| 6373 | 0, 21, // 6744: case 0x0: { |
| 6374 | OPC_SwitchField, 28, 4, // 6746: switch Inst[31:28] { |
| 6375 | 14, 7, // 6749: case 0xe: { |
| 6376 | OPC_CheckPredicate, 31, // 6751: check predicate 31 |
| 6377 | OPC_Decode, 159, 9, 181, 1, // 6753: decode to MVE_VHADD_qr_s16 using decoder 181 |
| 6378 | // 6753: } |
| 6379 | 15, 0, // 6758: case 0xf: { |
| 6380 | OPC_CheckPredicate, 31, // 6760: check predicate 31 |
| 6381 | OPC_Decode, 162, 9, 181, 1, // 6762: decode to MVE_VHADD_qr_u16 using decoder 181 |
| 6382 | // 6762: } |
| 6383 | // 6762: } // switch Inst[31:28] |
| 6384 | // 6762: } |
| 6385 | 1, 0, // 6767: case 0x1: { |
| 6386 | OPC_SwitchField, 28, 4, // 6769: switch Inst[31:28] { |
| 6387 | 14, 7, // 6772: case 0xe: { |
| 6388 | OPC_CheckPredicate, 31, // 6774: check predicate 31 |
| 6389 | OPC_Decode, 177, 8, 181, 1, // 6776: decode to MVE_VADD_qr_i16 using decoder 181 |
| 6390 | // 6776: } |
| 6391 | 15, 0, // 6781: case 0xf: { |
| 6392 | OPC_Scope, 15, // 6783: try { |
| 6393 | OPC_CheckField, 13, 3, 0, // 6785: check Inst[15:13] == 0x0 |
| 6394 | OPC_CheckPredicate, 31, // 6789: check predicate 31 |
| 6395 | OPC_CheckField, 22, 1, 0, // 6791: check Inst[22] == 0x0 |
| 6396 | OPC_Decode, 210, 8, 193, 1, // 6795: decode to MVE_VCMPi16r using decoder 193 |
| 6397 | // 6795: } else try { |
| 6398 | OPC_CheckPredicate, 31, // 6800: check predicate 31 |
| 6399 | OPC_Decode, 217, 11, 194, 1, // 6802: decode to MVE_VPTv8i16r using decoder 194 |
| 6400 | // 6802: } |
| 6401 | // 6802: } |
| 6402 | // 6802: } // switch Inst[31:28] |
| 6403 | // 6802: } |
| 6404 | // 6802: } // switch Inst[16] |
| 6405 | // 6802: } |
| 6406 | 2, 0, // 6807: case 0x2: { |
| 6407 | OPC_SwitchField, 16, 1, // 6809: switch Inst[16] { |
| 6408 | 0, 21, // 6812: case 0x0: { |
| 6409 | OPC_SwitchField, 28, 4, // 6814: switch Inst[31:28] { |
| 6410 | 14, 7, // 6817: case 0xe: { |
| 6411 | OPC_CheckPredicate, 31, // 6819: check predicate 31 |
| 6412 | OPC_Decode, 225, 11, 181, 1, // 6821: decode to MVE_VQADD_qr_s16 using decoder 181 |
| 6413 | // 6821: } |
| 6414 | 15, 0, // 6826: case 0xf: { |
| 6415 | OPC_CheckPredicate, 31, // 6828: check predicate 31 |
| 6416 | OPC_Decode, 228, 11, 181, 1, // 6830: decode to MVE_VQADD_qr_u16 using decoder 181 |
| 6417 | // 6830: } |
| 6418 | // 6830: } // switch Inst[31:28] |
| 6419 | // 6830: } |
| 6420 | 1, 0, // 6835: case 0x1: { |
| 6421 | OPC_SwitchField, 28, 4, // 6837: switch Inst[31:28] { |
| 6422 | 14, 20, // 6840: case 0xe: { |
| 6423 | OPC_Scope, 11, // 6842: try { |
| 6424 | OPC_CheckField, 1, 3, 7, // 6844: check Inst[3:1] == 0x7 |
| 6425 | OPC_CheckPredicate, 31, // 6848: check predicate 31 |
| 6426 | OPC_Decode, 186, 9, 195, 1, // 6850: decode to MVE_VIDUPu16 using decoder 195 |
| 6427 | // 6850: } else try { |
| 6428 | OPC_CheckPredicate, 31, // 6855: check predicate 31 |
| 6429 | OPC_Decode, 189, 9, 196, 1, // 6857: decode to MVE_VIWDUPu16 using decoder 196 |
| 6430 | // 6857: } |
| 6431 | // 6857: } |
| 6432 | 15, 0, // 6862: case 0xf: { |
| 6433 | OPC_Scope, 15, // 6864: try { |
| 6434 | OPC_CheckField, 13, 3, 0, // 6866: check Inst[15:13] == 0x0 |
| 6435 | OPC_CheckPredicate, 31, // 6870: check predicate 31 |
| 6436 | OPC_CheckField, 22, 1, 0, // 6872: check Inst[22] == 0x0 |
| 6437 | OPC_Decode, 222, 8, 197, 1, // 6876: decode to MVE_VCMPu16r using decoder 197 |
| 6438 | // 6876: } else try { |
| 6439 | OPC_CheckPredicate, 31, // 6881: check predicate 31 |
| 6440 | OPC_Decode, 221, 11, 198, 1, // 6883: decode to MVE_VPTv8u16r using decoder 198 |
| 6441 | // 6883: } |
| 6442 | // 6883: } |
| 6443 | // 6883: } // switch Inst[31:28] |
| 6444 | // 6883: } |
| 6445 | // 6883: } // switch Inst[16] |
| 6446 | // 6883: } |
| 6447 | // 6883: } // switch Inst[5:4] |
| 6448 | // 6883: } |
| 6449 | 1, 0, // 6888: case 0x1: { |
| 6450 | OPC_SwitchField, 16, 1, // 6890: switch Inst[16] { |
| 6451 | 0, 49, // 6893: case 0x0: { |
| 6452 | OPC_SwitchField, 4, 2, // 6895: switch Inst[5:4] { |
| 6453 | 0, 21, // 6898: case 0x0: { |
| 6454 | OPC_SwitchField, 28, 4, // 6900: switch Inst[31:28] { |
| 6455 | 14, 7, // 6903: case 0xe: { |
| 6456 | OPC_CheckPredicate, 31, // 6905: check predicate 31 |
| 6457 | OPC_Decode, 174, 9, 181, 1, // 6907: decode to MVE_VHSUB_qr_s16 using decoder 181 |
| 6458 | // 6907: } |
| 6459 | 15, 0, // 6912: case 0xf: { |
| 6460 | OPC_CheckPredicate, 31, // 6914: check predicate 31 |
| 6461 | OPC_Decode, 177, 9, 181, 1, // 6916: decode to MVE_VHSUB_qr_u16 using decoder 181 |
| 6462 | // 6916: } |
| 6463 | // 6916: } // switch Inst[31:28] |
| 6464 | // 6916: } |
| 6465 | 2, 0, // 6921: case 0x2: { |
| 6466 | OPC_SwitchField, 28, 4, // 6923: switch Inst[31:28] { |
| 6467 | 14, 7, // 6926: case 0xe: { |
| 6468 | OPC_CheckPredicate, 31, // 6928: check predicate 31 |
| 6469 | OPC_Decode, 237, 12, 181, 1, // 6930: decode to MVE_VQSUB_qr_s16 using decoder 181 |
| 6470 | // 6930: } |
| 6471 | 15, 0, // 6935: case 0xf: { |
| 6472 | OPC_CheckPredicate, 31, // 6937: check predicate 31 |
| 6473 | OPC_Decode, 240, 12, 181, 1, // 6939: decode to MVE_VQSUB_qr_u16 using decoder 181 |
| 6474 | // 6939: } |
| 6475 | // 6939: } // switch Inst[31:28] |
| 6476 | // 6939: } |
| 6477 | // 6939: } // switch Inst[5:4] |
| 6478 | // 6939: } |
| 6479 | 1, 0, // 6944: case 0x1: { |
| 6480 | OPC_SwitchField, 28, 4, // 6946: switch Inst[31:28] { |
| 6481 | 14, 34, // 6949: case 0xe: { |
| 6482 | OPC_SwitchField, 4, 2, // 6951: switch Inst[5:4] { |
| 6483 | 0, 7, // 6954: case 0x0: { |
| 6484 | OPC_CheckPredicate, 31, // 6956: check predicate 31 |
| 6485 | OPC_Decode, 176, 14, 181, 1, // 6958: decode to MVE_VSUB_qr_i16 using decoder 181 |
| 6486 | // 6958: } |
| 6487 | 2, 0, // 6963: case 0x2: { |
| 6488 | OPC_Scope, 11, // 6965: try { |
| 6489 | OPC_CheckField, 1, 3, 7, // 6967: check Inst[3:1] == 0x7 |
| 6490 | OPC_CheckPredicate, 31, // 6971: check predicate 31 |
| 6491 | OPC_Decode, 141, 9, 195, 1, // 6973: decode to MVE_VDDUPu16 using decoder 195 |
| 6492 | // 6973: } else try { |
| 6493 | OPC_CheckPredicate, 31, // 6978: check predicate 31 |
| 6494 | OPC_Decode, 147, 9, 196, 1, // 6980: decode to MVE_VDWDUPu16 using decoder 196 |
| 6495 | // 6980: } |
| 6496 | // 6980: } |
| 6497 | // 6980: } // switch Inst[5:4] |
| 6498 | // 6980: } |
| 6499 | 15, 0, // 6985: case 0xf: { |
| 6500 | OPC_CheckField, 4, 1, 0, // 6987: check Inst[4] == 0x0 |
| 6501 | OPC_Scope, 15, // 6991: try { |
| 6502 | OPC_CheckField, 13, 3, 0, // 6993: check Inst[15:13] == 0x0 |
| 6503 | OPC_CheckPredicate, 31, // 6997: check predicate 31 |
| 6504 | OPC_CheckField, 22, 1, 0, // 6999: check Inst[22] == 0x0 |
| 6505 | OPC_Decode, 216, 8, 199, 1, // 7003: decode to MVE_VCMPs16r using decoder 199 |
| 6506 | // 7003: } else try { |
| 6507 | OPC_CheckPredicate, 31, // 7008: check predicate 31 |
| 6508 | OPC_Decode, 219, 11, 200, 1, // 7010: decode to MVE_VPTv8s16r using decoder 200 |
| 6509 | // 7010: } |
| 6510 | // 7010: } |
| 6511 | // 7010: } // switch Inst[31:28] |
| 6512 | // 7010: } |
| 6513 | // 7010: } // switch Inst[16] |
| 6514 | // 7010: } |
| 6515 | // 7010: } // switch Inst[12] |
| 6516 | // 7010: } |
| 6517 | // 7010: } // switch Inst[6] |
| 6518 | // 7010: } |
| 6519 | 2, 191, 3, // 7015: case 0x2: { |
| 6520 | OPC_SwitchField, 6, 1, // 7018: switch Inst[6] { |
| 6521 | 0, 154, 1, // 7021: case 0x0: { |
| 6522 | OPC_SwitchField, 16, 1, // 7024: switch Inst[16] { |
| 6523 | 0, 37, // 7027: case 0x0: { |
| 6524 | OPC_SwitchField, 28, 4, // 7029: switch Inst[31:28] { |
| 6525 | 14, 15, // 7032: case 0xe: { |
| 6526 | OPC_CheckPredicate, 31, // 7034: check predicate 31 |
| 6527 | OPC_CheckField, 4, 1, 0, // 7036: check Inst[4] == 0x0 |
| 6528 | OPC_CheckField, 0, 1, 0, // 7040: check Inst[0] == 0x0 |
| 6529 | OPC_Decode, 172, 9, 186, 1, // 7044: decode to MVE_VHCADDs32 using decoder 186 |
| 6530 | // 7044: } |
| 6531 | 15, 0, // 7049: case 0xf: { |
| 6532 | OPC_CheckPredicate, 31, // 7051: check predicate 31 |
| 6533 | OPC_CheckField, 4, 1, 0, // 7053: check Inst[4] == 0x0 |
| 6534 | OPC_CheckField, 0, 1, 0, // 7057: check Inst[0] == 0x0 |
| 6535 | OPC_Decode, 195, 8, 186, 1, // 7061: decode to MVE_VCADDi32 using decoder 186 |
| 6536 | // 7061: } |
| 6537 | // 7061: } // switch Inst[31:28] |
| 6538 | // 7061: } |
| 6539 | 1, 0, // 7066: case 0x1: { |
| 6540 | OPC_SwitchField, 12, 1, // 7068: switch Inst[12] { |
| 6541 | 0, 71, // 7071: case 0x0: { |
| 6542 | OPC_SwitchField, 0, 1, // 7073: switch Inst[0] { |
| 6543 | 0, 32, // 7076: case 0x0: { |
| 6544 | OPC_CheckField, 4, 1, 0, // 7078: check Inst[4] == 0x0 |
| 6545 | OPC_CheckField, 28, 4, 15, // 7082: check Inst[31:28] == 0xf |
| 6546 | OPC_Scope, 15, // 7086: try { |
| 6547 | OPC_CheckField, 13, 3, 0, // 7088: check Inst[15:13] == 0x0 |
| 6548 | OPC_CheckPredicate, 31, // 7092: check predicate 31 |
| 6549 | OPC_CheckField, 22, 1, 0, // 7094: check Inst[22] == 0x0 |
| 6550 | OPC_Decode, 211, 8, 187, 1, // 7098: decode to MVE_VCMPi32 using decoder 187 |
| 6551 | // 7098: } else try { |
| 6552 | OPC_CheckPredicate, 31, // 7103: check predicate 31 |
| 6553 | OPC_Decode, 208, 11, 188, 1, // 7105: decode to MVE_VPTv4i32 using decoder 188 |
| 6554 | // 7105: } |
| 6555 | // 7105: } |
| 6556 | 1, 0, // 7110: case 0x1: { |
| 6557 | OPC_CheckField, 4, 1, 0, // 7112: check Inst[4] == 0x0 |
| 6558 | OPC_CheckField, 28, 4, 15, // 7116: check Inst[31:28] == 0xf |
| 6559 | OPC_Scope, 15, // 7120: try { |
| 6560 | OPC_CheckField, 13, 3, 0, // 7122: check Inst[15:13] == 0x0 |
| 6561 | OPC_CheckPredicate, 31, // 7126: check predicate 31 |
| 6562 | OPC_CheckField, 22, 1, 0, // 7128: check Inst[22] == 0x0 |
| 6563 | OPC_Decode, 223, 8, 189, 1, // 7132: decode to MVE_VCMPu32 using decoder 189 |
| 6564 | // 7132: } else try { |
| 6565 | OPC_CheckPredicate, 31, // 7137: check predicate 31 |
| 6566 | OPC_Decode, 212, 11, 190, 1, // 7139: decode to MVE_VPTv4u32 using decoder 190 |
| 6567 | // 7139: } |
| 6568 | // 7139: } |
| 6569 | // 7139: } // switch Inst[0] |
| 6570 | // 7139: } |
| 6571 | 1, 0, // 7144: case 0x1: { |
| 6572 | OPC_CheckField, 4, 1, 0, // 7146: check Inst[4] == 0x0 |
| 6573 | OPC_CheckField, 28, 4, 15, // 7150: check Inst[31:28] == 0xf |
| 6574 | OPC_Scope, 15, // 7154: try { |
| 6575 | OPC_CheckField, 13, 3, 0, // 7156: check Inst[15:13] == 0x0 |
| 6576 | OPC_CheckPredicate, 31, // 7160: check predicate 31 |
| 6577 | OPC_CheckField, 22, 1, 0, // 7162: check Inst[22] == 0x0 |
| 6578 | OPC_Decode, 217, 8, 191, 1, // 7166: decode to MVE_VCMPs32 using decoder 191 |
| 6579 | // 7166: } else try { |
| 6580 | OPC_CheckPredicate, 31, // 7171: check predicate 31 |
| 6581 | OPC_Decode, 210, 11, 192, 1, // 7173: decode to MVE_VPTv4s32 using decoder 192 |
| 6582 | // 7173: } |
| 6583 | // 7173: } |
| 6584 | // 7173: } // switch Inst[12] |
| 6585 | // 7173: } |
| 6586 | // 7173: } // switch Inst[16] |
| 6587 | // 7173: } |
| 6588 | 1, 0, // 7178: case 0x1: { |
| 6589 | OPC_SwitchField, 12, 1, // 7180: switch Inst[12] { |
| 6590 | 0, 152, 1, // 7183: case 0x0: { |
| 6591 | OPC_SwitchField, 4, 2, // 7186: switch Inst[5:4] { |
| 6592 | 0, 66, // 7189: case 0x0: { |
| 6593 | OPC_SwitchField, 16, 1, // 7191: switch Inst[16] { |
| 6594 | 0, 21, // 7194: case 0x0: { |
| 6595 | OPC_SwitchField, 28, 4, // 7196: switch Inst[31:28] { |
| 6596 | 14, 7, // 7199: case 0xe: { |
| 6597 | OPC_CheckPredicate, 31, // 7201: check predicate 31 |
| 6598 | OPC_Decode, 160, 9, 181, 1, // 7203: decode to MVE_VHADD_qr_s32 using decoder 181 |
| 6599 | // 7203: } |
| 6600 | 15, 0, // 7208: case 0xf: { |
| 6601 | OPC_CheckPredicate, 31, // 7210: check predicate 31 |
| 6602 | OPC_Decode, 163, 9, 181, 1, // 7212: decode to MVE_VHADD_qr_u32 using decoder 181 |
| 6603 | // 7212: } |
| 6604 | // 7212: } // switch Inst[31:28] |
| 6605 | // 7212: } |
| 6606 | 1, 0, // 7217: case 0x1: { |
| 6607 | OPC_SwitchField, 28, 4, // 7219: switch Inst[31:28] { |
| 6608 | 14, 7, // 7222: case 0xe: { |
| 6609 | OPC_CheckPredicate, 31, // 7224: check predicate 31 |
| 6610 | OPC_Decode, 178, 8, 181, 1, // 7226: decode to MVE_VADD_qr_i32 using decoder 181 |
| 6611 | // 7226: } |
| 6612 | 15, 0, // 7231: case 0xf: { |
| 6613 | OPC_Scope, 15, // 7233: try { |
| 6614 | OPC_CheckField, 13, 3, 0, // 7235: check Inst[15:13] == 0x0 |
| 6615 | OPC_CheckPredicate, 31, // 7239: check predicate 31 |
| 6616 | OPC_CheckField, 22, 1, 0, // 7241: check Inst[22] == 0x0 |
| 6617 | OPC_Decode, 212, 8, 193, 1, // 7245: decode to MVE_VCMPi32r using decoder 193 |
| 6618 | // 7245: } else try { |
| 6619 | OPC_CheckPredicate, 31, // 7250: check predicate 31 |
| 6620 | OPC_Decode, 209, 11, 194, 1, // 7252: decode to MVE_VPTv4i32r using decoder 194 |
| 6621 | // 7252: } |
| 6622 | // 7252: } |
| 6623 | // 7252: } // switch Inst[31:28] |
| 6624 | // 7252: } |
| 6625 | // 7252: } // switch Inst[16] |
| 6626 | // 7252: } |
| 6627 | 2, 0, // 7257: case 0x2: { |
| 6628 | OPC_SwitchField, 16, 1, // 7259: switch Inst[16] { |
| 6629 | 0, 21, // 7262: case 0x0: { |
| 6630 | OPC_SwitchField, 28, 4, // 7264: switch Inst[31:28] { |
| 6631 | 14, 7, // 7267: case 0xe: { |
| 6632 | OPC_CheckPredicate, 31, // 7269: check predicate 31 |
| 6633 | OPC_Decode, 226, 11, 181, 1, // 7271: decode to MVE_VQADD_qr_s32 using decoder 181 |
| 6634 | // 7271: } |
| 6635 | 15, 0, // 7276: case 0xf: { |
| 6636 | OPC_CheckPredicate, 31, // 7278: check predicate 31 |
| 6637 | OPC_Decode, 229, 11, 181, 1, // 7280: decode to MVE_VQADD_qr_u32 using decoder 181 |
| 6638 | // 7280: } |
| 6639 | // 7280: } // switch Inst[31:28] |
| 6640 | // 7280: } |
| 6641 | 1, 0, // 7285: case 0x1: { |
| 6642 | OPC_SwitchField, 28, 4, // 7287: switch Inst[31:28] { |
| 6643 | 14, 20, // 7290: case 0xe: { |
| 6644 | OPC_Scope, 11, // 7292: try { |
| 6645 | OPC_CheckField, 1, 3, 7, // 7294: check Inst[3:1] == 0x7 |
| 6646 | OPC_CheckPredicate, 31, // 7298: check predicate 31 |
| 6647 | OPC_Decode, 187, 9, 195, 1, // 7300: decode to MVE_VIDUPu32 using decoder 195 |
| 6648 | // 7300: } else try { |
| 6649 | OPC_CheckPredicate, 31, // 7305: check predicate 31 |
| 6650 | OPC_Decode, 190, 9, 196, 1, // 7307: decode to MVE_VIWDUPu32 using decoder 196 |
| 6651 | // 7307: } |
| 6652 | // 7307: } |
| 6653 | 15, 0, // 7312: case 0xf: { |
| 6654 | OPC_Scope, 15, // 7314: try { |
| 6655 | OPC_CheckField, 13, 3, 0, // 7316: check Inst[15:13] == 0x0 |
| 6656 | OPC_CheckPredicate, 31, // 7320: check predicate 31 |
| 6657 | OPC_CheckField, 22, 1, 0, // 7322: check Inst[22] == 0x0 |
| 6658 | OPC_Decode, 224, 8, 197, 1, // 7326: decode to MVE_VCMPu32r using decoder 197 |
| 6659 | // 7326: } else try { |
| 6660 | OPC_CheckPredicate, 31, // 7331: check predicate 31 |
| 6661 | OPC_Decode, 213, 11, 198, 1, // 7333: decode to MVE_VPTv4u32r using decoder 198 |
| 6662 | // 7333: } |
| 6663 | // 7333: } |
| 6664 | // 7333: } // switch Inst[31:28] |
| 6665 | // 7333: } |
| 6666 | // 7333: } // switch Inst[16] |
| 6667 | // 7333: } |
| 6668 | // 7333: } // switch Inst[5:4] |
| 6669 | // 7333: } |
| 6670 | 1, 0, // 7338: case 0x1: { |
| 6671 | OPC_SwitchField, 16, 1, // 7340: switch Inst[16] { |
| 6672 | 0, 49, // 7343: case 0x0: { |
| 6673 | OPC_SwitchField, 4, 2, // 7345: switch Inst[5:4] { |
| 6674 | 0, 21, // 7348: case 0x0: { |
| 6675 | OPC_SwitchField, 28, 4, // 7350: switch Inst[31:28] { |
| 6676 | 14, 7, // 7353: case 0xe: { |
| 6677 | OPC_CheckPredicate, 31, // 7355: check predicate 31 |
| 6678 | OPC_Decode, 175, 9, 181, 1, // 7357: decode to MVE_VHSUB_qr_s32 using decoder 181 |
| 6679 | // 7357: } |
| 6680 | 15, 0, // 7362: case 0xf: { |
| 6681 | OPC_CheckPredicate, 31, // 7364: check predicate 31 |
| 6682 | OPC_Decode, 178, 9, 181, 1, // 7366: decode to MVE_VHSUB_qr_u32 using decoder 181 |
| 6683 | // 7366: } |
| 6684 | // 7366: } // switch Inst[31:28] |
| 6685 | // 7366: } |
| 6686 | 2, 0, // 7371: case 0x2: { |
| 6687 | OPC_SwitchField, 28, 4, // 7373: switch Inst[31:28] { |
| 6688 | 14, 7, // 7376: case 0xe: { |
| 6689 | OPC_CheckPredicate, 31, // 7378: check predicate 31 |
| 6690 | OPC_Decode, 238, 12, 181, 1, // 7380: decode to MVE_VQSUB_qr_s32 using decoder 181 |
| 6691 | // 7380: } |
| 6692 | 15, 0, // 7385: case 0xf: { |
| 6693 | OPC_CheckPredicate, 31, // 7387: check predicate 31 |
| 6694 | OPC_Decode, 241, 12, 181, 1, // 7389: decode to MVE_VQSUB_qr_u32 using decoder 181 |
| 6695 | // 7389: } |
| 6696 | // 7389: } // switch Inst[31:28] |
| 6697 | // 7389: } |
| 6698 | // 7389: } // switch Inst[5:4] |
| 6699 | // 7389: } |
| 6700 | 1, 0, // 7394: case 0x1: { |
| 6701 | OPC_SwitchField, 28, 4, // 7396: switch Inst[31:28] { |
| 6702 | 14, 34, // 7399: case 0xe: { |
| 6703 | OPC_SwitchField, 4, 2, // 7401: switch Inst[5:4] { |
| 6704 | 0, 7, // 7404: case 0x0: { |
| 6705 | OPC_CheckPredicate, 31, // 7406: check predicate 31 |
| 6706 | OPC_Decode, 177, 14, 181, 1, // 7408: decode to MVE_VSUB_qr_i32 using decoder 181 |
| 6707 | // 7408: } |
| 6708 | 2, 0, // 7413: case 0x2: { |
| 6709 | OPC_Scope, 11, // 7415: try { |
| 6710 | OPC_CheckField, 1, 3, 7, // 7417: check Inst[3:1] == 0x7 |
| 6711 | OPC_CheckPredicate, 31, // 7421: check predicate 31 |
| 6712 | OPC_Decode, 142, 9, 195, 1, // 7423: decode to MVE_VDDUPu32 using decoder 195 |
| 6713 | // 7423: } else try { |
| 6714 | OPC_CheckPredicate, 31, // 7428: check predicate 31 |
| 6715 | OPC_Decode, 148, 9, 196, 1, // 7430: decode to MVE_VDWDUPu32 using decoder 196 |
| 6716 | // 7430: } |
| 6717 | // 7430: } |
| 6718 | // 7430: } // switch Inst[5:4] |
| 6719 | // 7430: } |
| 6720 | 15, 0, // 7435: case 0xf: { |
| 6721 | OPC_CheckField, 4, 1, 0, // 7437: check Inst[4] == 0x0 |
| 6722 | OPC_Scope, 15, // 7441: try { |
| 6723 | OPC_CheckField, 13, 3, 0, // 7443: check Inst[15:13] == 0x0 |
| 6724 | OPC_CheckPredicate, 31, // 7447: check predicate 31 |
| 6725 | OPC_CheckField, 22, 1, 0, // 7449: check Inst[22] == 0x0 |
| 6726 | OPC_Decode, 218, 8, 199, 1, // 7453: decode to MVE_VCMPs32r using decoder 199 |
| 6727 | // 7453: } else try { |
| 6728 | OPC_CheckPredicate, 31, // 7458: check predicate 31 |
| 6729 | OPC_Decode, 211, 11, 200, 1, // 7460: decode to MVE_VPTv4s32r using decoder 200 |
| 6730 | // 7460: } |
| 6731 | // 7460: } |
| 6732 | // 7460: } // switch Inst[31:28] |
| 6733 | // 7460: } |
| 6734 | // 7460: } // switch Inst[16] |
| 6735 | // 7460: } |
| 6736 | // 7460: } // switch Inst[12] |
| 6737 | // 7460: } |
| 6738 | // 7460: } // switch Inst[6] |
| 6739 | // 7460: } |
| 6740 | 3, 0, // 7465: case 0x3: { |
| 6741 | OPC_SwitchField, 6, 1, // 7467: switch Inst[6] { |
| 6742 | 0, 225, 1, // 7470: case 0x0: { |
| 6743 | OPC_SwitchField, 16, 1, // 7473: switch Inst[16] { |
| 6744 | 0, 137, 1, // 7476: case 0x0: { |
| 6745 | OPC_SwitchField, 0, 1, // 7479: switch Inst[0] { |
| 6746 | 0, 65, // 7482: case 0x0: { |
| 6747 | OPC_SwitchField, 12, 1, // 7484: switch Inst[12] { |
| 6748 | 0, 29, // 7487: case 0x0: { |
| 6749 | OPC_SwitchField, 28, 4, // 7489: switch Inst[31:28] { |
| 6750 | 14, 11, // 7492: case 0xe: { |
| 6751 | OPC_CheckPredicate, 31, // 7494: check predicate 31 |
| 6752 | OPC_CheckField, 4, 1, 0, // 7496: check Inst[4] == 0x0 |
| 6753 | OPC_Decode, 157, 8, 201, 1, // 7500: decode to MVE_VADC using decoder 201 |
| 6754 | // 7500: } |
| 6755 | 15, 0, // 7505: case 0xf: { |
| 6756 | OPC_CheckPredicate, 31, // 7507: check predicate 31 |
| 6757 | OPC_CheckField, 4, 1, 0, // 7509: check Inst[4] == 0x0 |
| 6758 | OPC_Decode, 183, 13, 201, 1, // 7513: decode to MVE_VSBC using decoder 201 |
| 6759 | // 7513: } |
| 6760 | // 7513: } // switch Inst[31:28] |
| 6761 | // 7513: } |
| 6762 | 1, 0, // 7518: case 0x1: { |
| 6763 | OPC_SwitchField, 28, 4, // 7520: switch Inst[31:28] { |
| 6764 | 14, 11, // 7523: case 0xe: { |
| 6765 | OPC_CheckPredicate, 31, // 7525: check predicate 31 |
| 6766 | OPC_CheckField, 4, 1, 0, // 7527: check Inst[4] == 0x0 |
| 6767 | OPC_Decode, 158, 8, 201, 1, // 7531: decode to MVE_VADCI using decoder 201 |
| 6768 | // 7531: } |
| 6769 | 15, 0, // 7536: case 0xf: { |
| 6770 | OPC_CheckPredicate, 31, // 7538: check predicate 31 |
| 6771 | OPC_CheckField, 4, 1, 0, // 7540: check Inst[4] == 0x0 |
| 6772 | OPC_Decode, 184, 13, 201, 1, // 7544: decode to MVE_VSBCI using decoder 201 |
| 6773 | // 7544: } |
| 6774 | // 7544: } // switch Inst[31:28] |
| 6775 | // 7544: } |
| 6776 | // 7544: } // switch Inst[12] |
| 6777 | // 7544: } |
| 6778 | 1, 0, // 7549: case 0x1: { |
| 6779 | OPC_SwitchField, 12, 1, // 7551: switch Inst[12] { |
| 6780 | 0, 29, // 7554: case 0x0: { |
| 6781 | OPC_SwitchField, 28, 4, // 7556: switch Inst[31:28] { |
| 6782 | 14, 11, // 7559: case 0xe: { |
| 6783 | OPC_CheckPredicate, 31, // 7561: check predicate 31 |
| 6784 | OPC_CheckField, 4, 1, 0, // 7563: check Inst[4] == 0x0 |
| 6785 | OPC_Decode, 137, 12, 179, 1, // 7567: decode to MVE_VQDMULLs16bh using decoder 179 |
| 6786 | // 7567: } |
| 6787 | 15, 0, // 7572: case 0xf: { |
| 6788 | OPC_CheckPredicate, 31, // 7574: check predicate 31 |
| 6789 | OPC_CheckField, 4, 1, 0, // 7576: check Inst[4] == 0x0 |
| 6790 | OPC_Decode, 139, 12, 179, 1, // 7580: decode to MVE_VQDMULLs32bh using decoder 179 |
| 6791 | // 7580: } |
| 6792 | // 7580: } // switch Inst[31:28] |
| 6793 | // 7580: } |
| 6794 | 1, 0, // 7585: case 0x1: { |
| 6795 | OPC_SwitchField, 28, 4, // 7587: switch Inst[31:28] { |
| 6796 | 14, 11, // 7590: case 0xe: { |
| 6797 | OPC_CheckPredicate, 31, // 7592: check predicate 31 |
| 6798 | OPC_CheckField, 4, 1, 0, // 7594: check Inst[4] == 0x0 |
| 6799 | OPC_Decode, 138, 12, 179, 1, // 7598: decode to MVE_VQDMULLs16th using decoder 179 |
| 6800 | // 7598: } |
| 6801 | 15, 0, // 7603: case 0xf: { |
| 6802 | OPC_CheckPredicate, 31, // 7605: check predicate 31 |
| 6803 | OPC_CheckField, 4, 1, 0, // 7607: check Inst[4] == 0x0 |
| 6804 | OPC_Decode, 140, 12, 179, 1, // 7611: decode to MVE_VQDMULLs32th using decoder 179 |
| 6805 | // 7611: } |
| 6806 | // 7611: } // switch Inst[31:28] |
| 6807 | // 7611: } |
| 6808 | // 7611: } // switch Inst[12] |
| 6809 | // 7611: } |
| 6810 | // 7611: } // switch Inst[0] |
| 6811 | // 7611: } |
| 6812 | 1, 0, // 7616: case 0x1: { |
| 6813 | OPC_SwitchField, 28, 4, // 7618: switch Inst[31:28] { |
| 6814 | 14, 28, // 7621: case 0xe: { |
| 6815 | OPC_CheckField, 4, 1, 0, // 7623: check Inst[4] == 0x0 |
| 6816 | OPC_Scope, 15, // 7627: try { |
| 6817 | OPC_CheckField, 13, 3, 0, // 7629: check Inst[15:13] == 0x0 |
| 6818 | OPC_CheckPredicate, 33, // 7633: check predicate 33 |
| 6819 | OPC_CheckField, 22, 1, 0, // 7635: check Inst[22] == 0x0 |
| 6820 | OPC_Decode, 207, 8, 202, 1, // 7639: decode to MVE_VCMPf32 using decoder 202 |
| 6821 | // 7639: } else try { |
| 6822 | OPC_CheckPredicate, 33, // 7644: check predicate 33 |
| 6823 | OPC_Decode, 206, 11, 203, 1, // 7646: decode to MVE_VPTv4f32 using decoder 203 |
| 6824 | // 7646: } |
| 6825 | // 7646: } |
| 6826 | 15, 0, // 7651: case 0xf: { |
| 6827 | OPC_CheckField, 4, 1, 0, // 7653: check Inst[4] == 0x0 |
| 6828 | OPC_Scope, 15, // 7657: try { |
| 6829 | OPC_CheckField, 0, 1, 1, // 7659: check Inst[0] == 0x1 |
| 6830 | OPC_CheckPredicate, 31, // 7663: check predicate 31 |
| 6831 | OPC_CheckField, 12, 1, 0, // 7665: check Inst[12] == 0x0 |
| 6832 | OPC_Decode, 198, 11, 204, 1, // 7669: decode to MVE_VPSEL using decoder 204 |
| 6833 | OPC_Scope, 15, // 7674: } else try { |
| 6834 | OPC_CheckField, 13, 3, 0, // 7676: check Inst[15:13] == 0x0 |
| 6835 | OPC_CheckPredicate, 33, // 7680: check predicate 33 |
| 6836 | OPC_CheckField, 22, 1, 0, // 7682: check Inst[22] == 0x0 |
| 6837 | OPC_Decode, 205, 8, 202, 1, // 7686: decode to MVE_VCMPf16 using decoder 202 |
| 6838 | // 7686: } else try { |
| 6839 | OPC_CheckPredicate, 33, // 7691: check predicate 33 |
| 6840 | OPC_Decode, 214, 11, 203, 1, // 7693: decode to MVE_VPTv8f16 using decoder 203 |
| 6841 | // 7693: } |
| 6842 | // 7693: } |
| 6843 | // 7693: } // switch Inst[31:28] |
| 6844 | // 7693: } |
| 6845 | // 7693: } // switch Inst[16] |
| 6846 | // 7693: } |
| 6847 | 1, 0, // 7698: case 0x1: { |
| 6848 | OPC_SwitchField, 16, 1, // 7700: switch Inst[16] { |
| 6849 | 0, 105, // 7703: case 0x0: { |
| 6850 | OPC_SwitchField, 4, 2, // 7705: switch Inst[5:4] { |
| 6851 | 0, 49, // 7708: case 0x0: { |
| 6852 | OPC_SwitchField, 12, 1, // 7710: switch Inst[12] { |
| 6853 | 0, 21, // 7713: case 0x0: { |
| 6854 | OPC_SwitchField, 28, 4, // 7715: switch Inst[31:28] { |
| 6855 | 14, 7, // 7718: case 0xe: { |
| 6856 | OPC_CheckPredicate, 33, // 7720: check predicate 33 |
| 6857 | OPC_Decode, 176, 8, 181, 1, // 7722: decode to MVE_VADD_qr_f32 using decoder 181 |
| 6858 | // 7722: } |
| 6859 | 15, 0, // 7727: case 0xf: { |
| 6860 | OPC_CheckPredicate, 33, // 7729: check predicate 33 |
| 6861 | OPC_Decode, 175, 8, 181, 1, // 7731: decode to MVE_VADD_qr_f16 using decoder 181 |
| 6862 | // 7731: } |
| 6863 | // 7731: } // switch Inst[31:28] |
| 6864 | // 7731: } |
| 6865 | 1, 0, // 7736: case 0x1: { |
| 6866 | OPC_SwitchField, 28, 4, // 7738: switch Inst[31:28] { |
| 6867 | 14, 7, // 7741: case 0xe: { |
| 6868 | OPC_CheckPredicate, 33, // 7743: check predicate 33 |
| 6869 | OPC_Decode, 175, 14, 181, 1, // 7745: decode to MVE_VSUB_qr_f32 using decoder 181 |
| 6870 | // 7745: } |
| 6871 | 15, 0, // 7750: case 0xf: { |
| 6872 | OPC_CheckPredicate, 33, // 7752: check predicate 33 |
| 6873 | OPC_Decode, 174, 14, 181, 1, // 7754: decode to MVE_VSUB_qr_f16 using decoder 181 |
| 6874 | // 7754: } |
| 6875 | // 7754: } // switch Inst[31:28] |
| 6876 | // 7754: } |
| 6877 | // 7754: } // switch Inst[12] |
| 6878 | // 7754: } |
| 6879 | 2, 0, // 7759: case 0x2: { |
| 6880 | OPC_SwitchField, 12, 1, // 7761: switch Inst[12] { |
| 6881 | 0, 21, // 7764: case 0x0: { |
| 6882 | OPC_SwitchField, 28, 4, // 7766: switch Inst[31:28] { |
| 6883 | 14, 7, // 7769: case 0xe: { |
| 6884 | OPC_CheckPredicate, 31, // 7771: check predicate 31 |
| 6885 | OPC_Decode, 133, 12, 181, 1, // 7773: decode to MVE_VQDMULL_qr_s16bh using decoder 181 |
| 6886 | // 7773: } |
| 6887 | 15, 0, // 7778: case 0xf: { |
| 6888 | OPC_CheckPredicate, 31, // 7780: check predicate 31 |
| 6889 | OPC_Decode, 135, 12, 181, 1, // 7782: decode to MVE_VQDMULL_qr_s32bh using decoder 181 |
| 6890 | // 7782: } |
| 6891 | // 7782: } // switch Inst[31:28] |
| 6892 | // 7782: } |
| 6893 | 1, 0, // 7787: case 0x1: { |
| 6894 | OPC_SwitchField, 28, 4, // 7789: switch Inst[31:28] { |
| 6895 | 14, 7, // 7792: case 0xe: { |
| 6896 | OPC_CheckPredicate, 31, // 7794: check predicate 31 |
| 6897 | OPC_Decode, 134, 12, 181, 1, // 7796: decode to MVE_VQDMULL_qr_s16th using decoder 181 |
| 6898 | // 7796: } |
| 6899 | 15, 0, // 7801: case 0xf: { |
| 6900 | OPC_CheckPredicate, 31, // 7803: check predicate 31 |
| 6901 | OPC_Decode, 136, 12, 181, 1, // 7805: decode to MVE_VQDMULL_qr_s32th using decoder 181 |
| 6902 | // 7805: } |
| 6903 | // 7805: } // switch Inst[31:28] |
| 6904 | // 7805: } |
| 6905 | // 7805: } // switch Inst[12] |
| 6906 | // 7805: } |
| 6907 | // 7805: } // switch Inst[5:4] |
| 6908 | // 7805: } |
| 6909 | 1, 0, // 7810: case 0x1: { |
| 6910 | OPC_SwitchField, 28, 4, // 7812: switch Inst[31:28] { |
| 6911 | 14, 28, // 7815: case 0xe: { |
| 6912 | OPC_CheckField, 4, 1, 0, // 7817: check Inst[4] == 0x0 |
| 6913 | OPC_Scope, 15, // 7821: try { |
| 6914 | OPC_CheckField, 13, 3, 0, // 7823: check Inst[15:13] == 0x0 |
| 6915 | OPC_CheckPredicate, 33, // 7827: check predicate 33 |
| 6916 | OPC_CheckField, 22, 1, 0, // 7829: check Inst[22] == 0x0 |
| 6917 | OPC_Decode, 208, 8, 205, 1, // 7833: decode to MVE_VCMPf32r using decoder 205 |
| 6918 | // 7833: } else try { |
| 6919 | OPC_CheckPredicate, 33, // 7838: check predicate 33 |
| 6920 | OPC_Decode, 207, 11, 206, 1, // 7840: decode to MVE_VPTv4f32r using decoder 206 |
| 6921 | // 7840: } |
| 6922 | // 7840: } |
| 6923 | 15, 0, // 7845: case 0xf: { |
| 6924 | OPC_CheckField, 4, 1, 0, // 7847: check Inst[4] == 0x0 |
| 6925 | OPC_Scope, 41, // 7851: try { |
| 6926 | OPC_CheckField, 0, 4, 13, // 7853: check Inst[3:0] == 0xd |
| 6927 | OPC_Scope, 20, // 7857: try { |
| 6928 | OPC_CheckField, 13, 3, 0, // 7859: check Inst[15:13] == 0x0 |
| 6929 | OPC_CheckPredicate, 31, // 7863: check predicate 31 |
| 6930 | OPC_CheckField, 22, 1, 0, // 7865: check Inst[22] == 0x0 |
| 6931 | OPC_SoftFail, 160, 161, 56, 0, // 7869: softfail pos=0x000e10a0 neg=0x00000000 |
| 6932 | OPC_Decode, 197, 11, 207, 1, // 7874: decode to MVE_VPNOT using decoder 207 |
| 6933 | // 7874: } else try { |
| 6934 | OPC_CheckPredicate, 31, // 7879: check predicate 31 |
| 6935 | OPC_CheckField, 17, 3, 0, // 7881: check Inst[19:17] == 0x0 |
| 6936 | OPC_SoftFail, 160, 33, 0, // 7885: softfail pos=0x000010a0 neg=0x00000000 |
| 6937 | OPC_Decode, 199, 11, 208, 1, // 7889: decode to MVE_VPST using decoder 208 |
| 6938 | // 7889: } |
| 6939 | OPC_Scope, 15, // 7894: } else try { |
| 6940 | OPC_CheckField, 13, 3, 0, // 7896: check Inst[15:13] == 0x0 |
| 6941 | OPC_CheckPredicate, 33, // 7900: check predicate 33 |
| 6942 | OPC_CheckField, 22, 1, 0, // 7902: check Inst[22] == 0x0 |
| 6943 | OPC_Decode, 206, 8, 205, 1, // 7906: decode to MVE_VCMPf16r using decoder 205 |
| 6944 | // 7906: } else try { |
| 6945 | OPC_CheckPredicate, 33, // 7911: check predicate 33 |
| 6946 | OPC_Decode, 215, 11, 206, 1, // 7913: decode to MVE_VPTv8f16r using decoder 206 |
| 6947 | // 7913: } |
| 6948 | // 7913: } |
| 6949 | // 7913: } // switch Inst[31:28] |
| 6950 | // 7913: } |
| 6951 | // 7913: } // switch Inst[16] |
| 6952 | // 7913: } |
| 6953 | // 7913: } // switch Inst[6] |
| 6954 | // 7913: } |
| 6955 | // 7913: } // switch Inst[21:20] |
| 6956 | // 7913: } |
| 6957 | // 7913: } // switch Inst[11:8] |
| 6958 | // 7913: } |
| 6959 | 1, 208, 20, // 7918: case 0x1: { |
| 6960 | OPC_SwitchField, 8, 4, // 7921: switch Inst[11:8] { |
| 6961 | 11, 107, // 7924: case 0xb: { |
| 6962 | OPC_SwitchField, 20, 1, // 7926: switch Inst[20] { |
| 6963 | 0, 63, // 7929: case 0x0: { |
| 6964 | OPC_SwitchField, 0, 7, // 7931: switch Inst[6:0] { |
| 6965 | 16, 37, // 7934: case 0x10: { |
| 6966 | OPC_SwitchField, 21, 2, // 7936: switch Inst[22:21] { |
| 6967 | 1, 15, // 7939: case 0x1: { |
| 6968 | OPC_CheckPredicate, 31, // 7941: check predicate 31 |
| 6969 | OPC_CheckField, 28, 4, 14, // 7943: check Inst[31:28] == 0xe |
| 6970 | OPC_CheckField, 16, 1, 0, // 7947: check Inst[16] == 0x0 |
| 6971 | OPC_Decode, 145, 9, 209, 1, // 7951: decode to MVE_VDUP32 using decoder 209 |
| 6972 | // 7951: } |
| 6973 | 3, 0, // 7956: case 0x3: { |
| 6974 | OPC_CheckPredicate, 31, // 7958: check predicate 31 |
| 6975 | OPC_CheckField, 28, 4, 14, // 7960: check Inst[31:28] == 0xe |
| 6976 | OPC_CheckField, 16, 1, 0, // 7964: check Inst[16] == 0x0 |
| 6977 | OPC_Decode, 146, 9, 209, 1, // 7968: decode to MVE_VDUP8 using decoder 209 |
| 6978 | // 7968: } |
| 6979 | // 7968: } // switch Inst[22:21] |
| 6980 | // 7968: } |
| 6981 | 48, 0, // 7973: case 0x30: { |
| 6982 | OPC_CheckPredicate, 31, // 7975: check predicate 31 |
| 6983 | OPC_CheckField, 28, 4, 14, // 7977: check Inst[31:28] == 0xe |
| 6984 | OPC_CheckField, 21, 2, 1, // 7981: check Inst[22:21] == 0x1 |
| 6985 | OPC_CheckField, 16, 1, 0, // 7985: check Inst[16] == 0x0 |
| 6986 | OPC_Decode, 144, 9, 209, 1, // 7989: decode to MVE_VDUP16 using decoder 209 |
| 6987 | // 7989: } |
| 6988 | // 7989: } // switch Inst[6:0] |
| 6989 | // 7989: } |
| 6990 | 1, 0, // 7994: case 0x1: { |
| 6991 | OPC_SwitchField, 22, 1, // 7996: switch Inst[22] { |
| 6992 | 0, 15, // 7999: case 0x0: { |
| 6993 | OPC_CheckPredicate, 32, // 8001: check predicate 32 |
| 6994 | OPC_CheckField, 28, 4, 14, // 8003: check Inst[31:28] == 0xe |
| 6995 | OPC_CheckField, 0, 6, 48, // 8007: check Inst[5:0] == 0x30 |
| 6996 | OPC_Decode, 141, 11, 176, 1, // 8011: decode to MVE_VMOV_from_lane_u16 using decoder 176 |
| 6997 | // 8011: } |
| 6998 | 1, 0, // 8016: case 0x1: { |
| 6999 | OPC_CheckPredicate, 32, // 8018: check predicate 32 |
| 7000 | OPC_CheckField, 28, 4, 14, // 8020: check Inst[31:28] == 0xe |
| 7001 | OPC_CheckField, 0, 5, 16, // 8024: check Inst[4:0] == 0x10 |
| 7002 | OPC_Decode, 142, 11, 177, 1, // 8028: decode to MVE_VMOV_from_lane_u8 using decoder 177 |
| 7003 | // 8028: } |
| 7004 | // 8028: } // switch Inst[22] |
| 7005 | // 8028: } |
| 7006 | // 8028: } // switch Inst[20] |
| 7007 | // 8028: } |
| 7008 | 14, 164, 5, // 8033: case 0xe: { |
| 7009 | OPC_SwitchField, 0, 1, // 8036: switch Inst[0] { |
| 7010 | 0, 206, 2, // 8039: case 0x0: { |
| 7011 | OPC_SwitchField, 4, 4, // 8042: switch Inst[7:4] { |
| 7012 | 0, 163, 1, // 8045: case 0x0: { |
| 7013 | OPC_SwitchField, 12, 1, // 8048: switch Inst[12] { |
| 7014 | 0, 101, // 8051: case 0x0: { |
| 7015 | OPC_SwitchField, 16, 1, // 8053: switch Inst[16] { |
| 7016 | 0, 47, // 8056: case 0x0: { |
| 7017 | OPC_SwitchField, 28, 4, // 8058: switch Inst[31:28] { |
| 7018 | 14, 20, // 8061: case 0xe: { |
| 7019 | OPC_Scope, 11, // 8063: try { |
| 7020 | OPC_CheckField, 20, 3, 7, // 8065: check Inst[22:20] == 0x7 |
| 7021 | OPC_CheckPredicate, 31, // 8069: check predicate 31 |
| 7022 | OPC_Decode, 207, 10, 210, 1, // 8071: decode to MVE_VMLADAVs16 using decoder 210 |
| 7023 | // 8071: } else try { |
| 7024 | OPC_CheckPredicate, 31, // 8076: check predicate 31 |
| 7025 | OPC_Decode, 222, 10, 211, 1, // 8078: decode to MVE_VMLALDAVs16 using decoder 211 |
| 7026 | // 8078: } |
| 7027 | // 8078: } |
| 7028 | 15, 0, // 8083: case 0xf: { |
| 7029 | OPC_Scope, 11, // 8085: try { |
| 7030 | OPC_CheckField, 20, 3, 7, // 8087: check Inst[22:20] == 0x7 |
| 7031 | OPC_CheckPredicate, 31, // 8091: check predicate 31 |
| 7032 | OPC_Decode, 210, 10, 210, 1, // 8093: decode to MVE_VMLADAVu16 using decoder 210 |
| 7033 | // 8093: } else try { |
| 7034 | OPC_CheckPredicate, 31, // 8098: check predicate 31 |
| 7035 | OPC_Decode, 224, 10, 211, 1, // 8100: decode to MVE_VMLALDAVu16 using decoder 211 |
| 7036 | // 8100: } |
| 7037 | // 8100: } |
| 7038 | // 8100: } // switch Inst[31:28] |
| 7039 | // 8100: } |
| 7040 | 1, 0, // 8105: case 0x1: { |
| 7041 | OPC_SwitchField, 28, 4, // 8107: switch Inst[31:28] { |
| 7042 | 14, 20, // 8110: case 0xe: { |
| 7043 | OPC_Scope, 11, // 8112: try { |
| 7044 | OPC_CheckField, 20, 3, 7, // 8114: check Inst[22:20] == 0x7 |
| 7045 | OPC_CheckPredicate, 31, // 8118: check predicate 31 |
| 7046 | OPC_Decode, 208, 10, 210, 1, // 8120: decode to MVE_VMLADAVs32 using decoder 210 |
| 7047 | // 8120: } else try { |
| 7048 | OPC_CheckPredicate, 31, // 8125: check predicate 31 |
| 7049 | OPC_Decode, 223, 10, 211, 1, // 8127: decode to MVE_VMLALDAVs32 using decoder 211 |
| 7050 | // 8127: } |
| 7051 | // 8127: } |
| 7052 | 15, 0, // 8132: case 0xf: { |
| 7053 | OPC_Scope, 11, // 8134: try { |
| 7054 | OPC_CheckField, 20, 3, 7, // 8136: check Inst[22:20] == 0x7 |
| 7055 | OPC_CheckPredicate, 31, // 8140: check predicate 31 |
| 7056 | OPC_Decode, 211, 10, 210, 1, // 8142: decode to MVE_VMLADAVu32 using decoder 210 |
| 7057 | // 8142: } else try { |
| 7058 | OPC_CheckPredicate, 31, // 8147: check predicate 31 |
| 7059 | OPC_Decode, 225, 10, 211, 1, // 8149: decode to MVE_VMLALDAVu32 using decoder 211 |
| 7060 | // 8149: } |
| 7061 | // 8149: } |
| 7062 | // 8149: } // switch Inst[31:28] |
| 7063 | // 8149: } |
| 7064 | // 8149: } // switch Inst[16] |
| 7065 | // 8149: } |
| 7066 | 1, 0, // 8154: case 0x1: { |
| 7067 | OPC_SwitchField, 16, 1, // 8156: switch Inst[16] { |
| 7068 | 0, 24, // 8159: case 0x0: { |
| 7069 | OPC_CheckField, 28, 4, 14, // 8161: check Inst[31:28] == 0xe |
| 7070 | OPC_Scope, 11, // 8165: try { |
| 7071 | OPC_CheckField, 20, 3, 7, // 8167: check Inst[22:20] == 0x7 |
| 7072 | OPC_CheckPredicate, 31, // 8171: check predicate 31 |
| 7073 | OPC_Decode, 213, 10, 210, 1, // 8173: decode to MVE_VMLADAVxs16 using decoder 210 |
| 7074 | // 8173: } else try { |
| 7075 | OPC_CheckPredicate, 31, // 8178: check predicate 31 |
| 7076 | OPC_Decode, 226, 10, 211, 1, // 8180: decode to MVE_VMLALDAVxs16 using decoder 211 |
| 7077 | // 8180: } |
| 7078 | // 8180: } |
| 7079 | 1, 0, // 8185: case 0x1: { |
| 7080 | OPC_CheckField, 28, 4, 14, // 8187: check Inst[31:28] == 0xe |
| 7081 | OPC_Scope, 11, // 8191: try { |
| 7082 | OPC_CheckField, 20, 3, 7, // 8193: check Inst[22:20] == 0x7 |
| 7083 | OPC_CheckPredicate, 31, // 8197: check predicate 31 |
| 7084 | OPC_Decode, 214, 10, 210, 1, // 8199: decode to MVE_VMLADAVxs32 using decoder 210 |
| 7085 | // 8199: } else try { |
| 7086 | OPC_CheckPredicate, 31, // 8204: check predicate 31 |
| 7087 | OPC_Decode, 227, 10, 211, 1, // 8206: decode to MVE_VMLALDAVxs32 using decoder 211 |
| 7088 | // 8206: } |
| 7089 | // 8206: } |
| 7090 | // 8206: } // switch Inst[16] |
| 7091 | // 8206: } |
| 7092 | // 8206: } // switch Inst[12] |
| 7093 | // 8206: } |
| 7094 | 2, 0, // 8211: case 0x2: { |
| 7095 | OPC_SwitchField, 12, 1, // 8213: switch Inst[12] { |
| 7096 | 0, 101, // 8216: case 0x0: { |
| 7097 | OPC_SwitchField, 16, 1, // 8218: switch Inst[16] { |
| 7098 | 0, 47, // 8221: case 0x0: { |
| 7099 | OPC_SwitchField, 28, 4, // 8223: switch Inst[31:28] { |
| 7100 | 14, 20, // 8226: case 0xe: { |
| 7101 | OPC_Scope, 11, // 8228: try { |
| 7102 | OPC_CheckField, 20, 3, 7, // 8230: check Inst[22:20] == 0x7 |
| 7103 | OPC_CheckPredicate, 31, // 8234: check predicate 31 |
| 7104 | OPC_Decode, 198, 10, 212, 1, // 8236: decode to MVE_VMLADAVas16 using decoder 212 |
| 7105 | // 8236: } else try { |
| 7106 | OPC_CheckPredicate, 31, // 8241: check predicate 31 |
| 7107 | OPC_Decode, 216, 10, 213, 1, // 8243: decode to MVE_VMLALDAVas16 using decoder 213 |
| 7108 | // 8243: } |
| 7109 | // 8243: } |
| 7110 | 15, 0, // 8248: case 0xf: { |
| 7111 | OPC_Scope, 11, // 8250: try { |
| 7112 | OPC_CheckField, 20, 3, 7, // 8252: check Inst[22:20] == 0x7 |
| 7113 | OPC_CheckPredicate, 31, // 8256: check predicate 31 |
| 7114 | OPC_Decode, 201, 10, 212, 1, // 8258: decode to MVE_VMLADAVau16 using decoder 212 |
| 7115 | // 8258: } else try { |
| 7116 | OPC_CheckPredicate, 31, // 8263: check predicate 31 |
| 7117 | OPC_Decode, 218, 10, 213, 1, // 8265: decode to MVE_VMLALDAVau16 using decoder 213 |
| 7118 | // 8265: } |
| 7119 | // 8265: } |
| 7120 | // 8265: } // switch Inst[31:28] |
| 7121 | // 8265: } |
| 7122 | 1, 0, // 8270: case 0x1: { |
| 7123 | OPC_SwitchField, 28, 4, // 8272: switch Inst[31:28] { |
| 7124 | 14, 20, // 8275: case 0xe: { |
| 7125 | OPC_Scope, 11, // 8277: try { |
| 7126 | OPC_CheckField, 20, 3, 7, // 8279: check Inst[22:20] == 0x7 |
| 7127 | OPC_CheckPredicate, 31, // 8283: check predicate 31 |
| 7128 | OPC_Decode, 199, 10, 212, 1, // 8285: decode to MVE_VMLADAVas32 using decoder 212 |
| 7129 | // 8285: } else try { |
| 7130 | OPC_CheckPredicate, 31, // 8290: check predicate 31 |
| 7131 | OPC_Decode, 217, 10, 213, 1, // 8292: decode to MVE_VMLALDAVas32 using decoder 213 |
| 7132 | // 8292: } |
| 7133 | // 8292: } |
| 7134 | 15, 0, // 8297: case 0xf: { |
| 7135 | OPC_Scope, 11, // 8299: try { |
| 7136 | OPC_CheckField, 20, 3, 7, // 8301: check Inst[22:20] == 0x7 |
| 7137 | OPC_CheckPredicate, 31, // 8305: check predicate 31 |
| 7138 | OPC_Decode, 202, 10, 212, 1, // 8307: decode to MVE_VMLADAVau32 using decoder 212 |
| 7139 | // 8307: } else try { |
| 7140 | OPC_CheckPredicate, 31, // 8312: check predicate 31 |
| 7141 | OPC_Decode, 219, 10, 213, 1, // 8314: decode to MVE_VMLALDAVau32 using decoder 213 |
| 7142 | // 8314: } |
| 7143 | // 8314: } |
| 7144 | // 8314: } // switch Inst[31:28] |
| 7145 | // 8314: } |
| 7146 | // 8314: } // switch Inst[16] |
| 7147 | // 8314: } |
| 7148 | 1, 0, // 8319: case 0x1: { |
| 7149 | OPC_SwitchField, 16, 1, // 8321: switch Inst[16] { |
| 7150 | 0, 24, // 8324: case 0x0: { |
| 7151 | OPC_CheckField, 28, 4, 14, // 8326: check Inst[31:28] == 0xe |
| 7152 | OPC_Scope, 11, // 8330: try { |
| 7153 | OPC_CheckField, 20, 3, 7, // 8332: check Inst[22:20] == 0x7 |
| 7154 | OPC_CheckPredicate, 31, // 8336: check predicate 31 |
| 7155 | OPC_Decode, 204, 10, 212, 1, // 8338: decode to MVE_VMLADAVaxs16 using decoder 212 |
| 7156 | // 8338: } else try { |
| 7157 | OPC_CheckPredicate, 31, // 8343: check predicate 31 |
| 7158 | OPC_Decode, 220, 10, 213, 1, // 8345: decode to MVE_VMLALDAVaxs16 using decoder 213 |
| 7159 | // 8345: } |
| 7160 | // 8345: } |
| 7161 | 1, 0, // 8350: case 0x1: { |
| 7162 | OPC_CheckField, 28, 4, 14, // 8352: check Inst[31:28] == 0xe |
| 7163 | OPC_Scope, 11, // 8356: try { |
| 7164 | OPC_CheckField, 20, 3, 7, // 8358: check Inst[22:20] == 0x7 |
| 7165 | OPC_CheckPredicate, 31, // 8362: check predicate 31 |
| 7166 | OPC_Decode, 205, 10, 212, 1, // 8364: decode to MVE_VMLADAVaxs32 using decoder 212 |
| 7167 | // 8364: } else try { |
| 7168 | OPC_CheckPredicate, 31, // 8369: check predicate 31 |
| 7169 | OPC_Decode, 221, 10, 213, 1, // 8371: decode to MVE_VMLALDAVaxs32 using decoder 213 |
| 7170 | // 8371: } |
| 7171 | // 8371: } |
| 7172 | // 8371: } // switch Inst[16] |
| 7173 | // 8371: } |
| 7174 | // 8371: } // switch Inst[12] |
| 7175 | // 8371: } |
| 7176 | // 8371: } // switch Inst[7:4] |
| 7177 | // 8371: } |
| 7178 | 1, 0, // 8376: case 0x1: { |
| 7179 | OPC_SwitchField, 4, 4, // 8378: switch Inst[7:4] { |
| 7180 | 0, 163, 1, // 8381: case 0x0: { |
| 7181 | OPC_SwitchField, 12, 1, // 8384: switch Inst[12] { |
| 7182 | 0, 78, // 8387: case 0x0: { |
| 7183 | OPC_SwitchField, 16, 1, // 8389: switch Inst[16] { |
| 7184 | 0, 47, // 8392: case 0x0: { |
| 7185 | OPC_SwitchField, 28, 4, // 8394: switch Inst[31:28] { |
| 7186 | 14, 20, // 8397: case 0xe: { |
| 7187 | OPC_Scope, 11, // 8399: try { |
| 7188 | OPC_CheckField, 20, 3, 7, // 8401: check Inst[22:20] == 0x7 |
| 7189 | OPC_CheckPredicate, 31, // 8405: check predicate 31 |
| 7190 | OPC_Decode, 240, 10, 210, 1, // 8407: decode to MVE_VMLSDAVs16 using decoder 210 |
| 7191 | // 8407: } else try { |
| 7192 | OPC_CheckPredicate, 31, // 8412: check predicate 31 |
| 7193 | OPC_Decode, 250, 10, 211, 1, // 8414: decode to MVE_VMLSLDAVs16 using decoder 211 |
| 7194 | // 8414: } |
| 7195 | // 8414: } |
| 7196 | 15, 0, // 8419: case 0xf: { |
| 7197 | OPC_Scope, 11, // 8421: try { |
| 7198 | OPC_CheckField, 20, 3, 7, // 8423: check Inst[22:20] == 0x7 |
| 7199 | OPC_CheckPredicate, 31, // 8427: check predicate 31 |
| 7200 | OPC_Decode, 242, 10, 210, 1, // 8429: decode to MVE_VMLSDAVs8 using decoder 210 |
| 7201 | // 8429: } else try { |
| 7202 | OPC_CheckPredicate, 31, // 8434: check predicate 31 |
| 7203 | OPC_Decode, 153, 13, 211, 1, // 8436: decode to MVE_VRMLSLDAVHs32 using decoder 211 |
| 7204 | // 8436: } |
| 7205 | // 8436: } |
| 7206 | // 8436: } // switch Inst[31:28] |
| 7207 | // 8436: } |
| 7208 | 1, 0, // 8441: case 0x1: { |
| 7209 | OPC_CheckField, 28, 4, 14, // 8443: check Inst[31:28] == 0xe |
| 7210 | OPC_Scope, 11, // 8447: try { |
| 7211 | OPC_CheckField, 20, 3, 7, // 8449: check Inst[22:20] == 0x7 |
| 7212 | OPC_CheckPredicate, 31, // 8453: check predicate 31 |
| 7213 | OPC_Decode, 241, 10, 210, 1, // 8455: decode to MVE_VMLSDAVs32 using decoder 210 |
| 7214 | // 8455: } else try { |
| 7215 | OPC_CheckPredicate, 31, // 8460: check predicate 31 |
| 7216 | OPC_Decode, 251, 10, 211, 1, // 8462: decode to MVE_VMLSLDAVs32 using decoder 211 |
| 7217 | // 8462: } |
| 7218 | // 8462: } |
| 7219 | // 8462: } // switch Inst[16] |
| 7220 | // 8462: } |
| 7221 | 1, 0, // 8467: case 0x1: { |
| 7222 | OPC_SwitchField, 16, 1, // 8469: switch Inst[16] { |
| 7223 | 0, 47, // 8472: case 0x0: { |
| 7224 | OPC_SwitchField, 28, 4, // 8474: switch Inst[31:28] { |
| 7225 | 14, 20, // 8477: case 0xe: { |
| 7226 | OPC_Scope, 11, // 8479: try { |
| 7227 | OPC_CheckField, 20, 3, 7, // 8481: check Inst[22:20] == 0x7 |
| 7228 | OPC_CheckPredicate, 31, // 8485: check predicate 31 |
| 7229 | OPC_Decode, 243, 10, 210, 1, // 8487: decode to MVE_VMLSDAVxs16 using decoder 210 |
| 7230 | // 8487: } else try { |
| 7231 | OPC_CheckPredicate, 31, // 8492: check predicate 31 |
| 7232 | OPC_Decode, 252, 10, 211, 1, // 8494: decode to MVE_VMLSLDAVxs16 using decoder 211 |
| 7233 | // 8494: } |
| 7234 | // 8494: } |
| 7235 | 15, 0, // 8499: case 0xf: { |
| 7236 | OPC_Scope, 11, // 8501: try { |
| 7237 | OPC_CheckField, 20, 3, 7, // 8503: check Inst[22:20] == 0x7 |
| 7238 | OPC_CheckPredicate, 31, // 8507: check predicate 31 |
| 7239 | OPC_Decode, 245, 10, 210, 1, // 8509: decode to MVE_VMLSDAVxs8 using decoder 210 |
| 7240 | // 8509: } else try { |
| 7241 | OPC_CheckPredicate, 31, // 8514: check predicate 31 |
| 7242 | OPC_Decode, 154, 13, 211, 1, // 8516: decode to MVE_VRMLSLDAVHxs32 using decoder 211 |
| 7243 | // 8516: } |
| 7244 | // 8516: } |
| 7245 | // 8516: } // switch Inst[31:28] |
| 7246 | // 8516: } |
| 7247 | 1, 0, // 8521: case 0x1: { |
| 7248 | OPC_CheckField, 28, 4, 14, // 8523: check Inst[31:28] == 0xe |
| 7249 | OPC_Scope, 11, // 8527: try { |
| 7250 | OPC_CheckField, 20, 3, 7, // 8529: check Inst[22:20] == 0x7 |
| 7251 | OPC_CheckPredicate, 31, // 8533: check predicate 31 |
| 7252 | OPC_Decode, 244, 10, 210, 1, // 8535: decode to MVE_VMLSDAVxs32 using decoder 210 |
| 7253 | // 8535: } else try { |
| 7254 | OPC_CheckPredicate, 31, // 8540: check predicate 31 |
| 7255 | OPC_Decode, 253, 10, 211, 1, // 8542: decode to MVE_VMLSLDAVxs32 using decoder 211 |
| 7256 | // 8542: } |
| 7257 | // 8542: } |
| 7258 | // 8542: } // switch Inst[16] |
| 7259 | // 8542: } |
| 7260 | // 8542: } // switch Inst[12] |
| 7261 | // 8542: } |
| 7262 | 2, 0, // 8547: case 0x2: { |
| 7263 | OPC_SwitchField, 12, 1, // 8549: switch Inst[12] { |
| 7264 | 0, 78, // 8552: case 0x0: { |
| 7265 | OPC_SwitchField, 16, 1, // 8554: switch Inst[16] { |
| 7266 | 0, 47, // 8557: case 0x0: { |
| 7267 | OPC_SwitchField, 28, 4, // 8559: switch Inst[31:28] { |
| 7268 | 14, 20, // 8562: case 0xe: { |
| 7269 | OPC_Scope, 11, // 8564: try { |
| 7270 | OPC_CheckField, 20, 3, 7, // 8566: check Inst[22:20] == 0x7 |
| 7271 | OPC_CheckPredicate, 31, // 8570: check predicate 31 |
| 7272 | OPC_Decode, 234, 10, 212, 1, // 8572: decode to MVE_VMLSDAVas16 using decoder 212 |
| 7273 | // 8572: } else try { |
| 7274 | OPC_CheckPredicate, 31, // 8577: check predicate 31 |
| 7275 | OPC_Decode, 246, 10, 213, 1, // 8579: decode to MVE_VMLSLDAVas16 using decoder 213 |
| 7276 | // 8579: } |
| 7277 | // 8579: } |
| 7278 | 15, 0, // 8584: case 0xf: { |
| 7279 | OPC_Scope, 11, // 8586: try { |
| 7280 | OPC_CheckField, 20, 3, 7, // 8588: check Inst[22:20] == 0x7 |
| 7281 | OPC_CheckPredicate, 31, // 8592: check predicate 31 |
| 7282 | OPC_Decode, 236, 10, 212, 1, // 8594: decode to MVE_VMLSDAVas8 using decoder 212 |
| 7283 | // 8594: } else try { |
| 7284 | OPC_CheckPredicate, 31, // 8599: check predicate 31 |
| 7285 | OPC_Decode, 151, 13, 213, 1, // 8601: decode to MVE_VRMLSLDAVHas32 using decoder 213 |
| 7286 | // 8601: } |
| 7287 | // 8601: } |
| 7288 | // 8601: } // switch Inst[31:28] |
| 7289 | // 8601: } |
| 7290 | 1, 0, // 8606: case 0x1: { |
| 7291 | OPC_CheckField, 28, 4, 14, // 8608: check Inst[31:28] == 0xe |
| 7292 | OPC_Scope, 11, // 8612: try { |
| 7293 | OPC_CheckField, 20, 3, 7, // 8614: check Inst[22:20] == 0x7 |
| 7294 | OPC_CheckPredicate, 31, // 8618: check predicate 31 |
| 7295 | OPC_Decode, 235, 10, 212, 1, // 8620: decode to MVE_VMLSDAVas32 using decoder 212 |
| 7296 | // 8620: } else try { |
| 7297 | OPC_CheckPredicate, 31, // 8625: check predicate 31 |
| 7298 | OPC_Decode, 247, 10, 213, 1, // 8627: decode to MVE_VMLSLDAVas32 using decoder 213 |
| 7299 | // 8627: } |
| 7300 | // 8627: } |
| 7301 | // 8627: } // switch Inst[16] |
| 7302 | // 8627: } |
| 7303 | 1, 0, // 8632: case 0x1: { |
| 7304 | OPC_SwitchField, 16, 1, // 8634: switch Inst[16] { |
| 7305 | 0, 47, // 8637: case 0x0: { |
| 7306 | OPC_SwitchField, 28, 4, // 8639: switch Inst[31:28] { |
| 7307 | 14, 20, // 8642: case 0xe: { |
| 7308 | OPC_Scope, 11, // 8644: try { |
| 7309 | OPC_CheckField, 20, 3, 7, // 8646: check Inst[22:20] == 0x7 |
| 7310 | OPC_CheckPredicate, 31, // 8650: check predicate 31 |
| 7311 | OPC_Decode, 237, 10, 212, 1, // 8652: decode to MVE_VMLSDAVaxs16 using decoder 212 |
| 7312 | // 8652: } else try { |
| 7313 | OPC_CheckPredicate, 31, // 8657: check predicate 31 |
| 7314 | OPC_Decode, 248, 10, 213, 1, // 8659: decode to MVE_VMLSLDAVaxs16 using decoder 213 |
| 7315 | // 8659: } |
| 7316 | // 8659: } |
| 7317 | 15, 0, // 8664: case 0xf: { |
| 7318 | OPC_Scope, 11, // 8666: try { |
| 7319 | OPC_CheckField, 20, 3, 7, // 8668: check Inst[22:20] == 0x7 |
| 7320 | OPC_CheckPredicate, 31, // 8672: check predicate 31 |
| 7321 | OPC_Decode, 239, 10, 212, 1, // 8674: decode to MVE_VMLSDAVaxs8 using decoder 212 |
| 7322 | // 8674: } else try { |
| 7323 | OPC_CheckPredicate, 31, // 8679: check predicate 31 |
| 7324 | OPC_Decode, 152, 13, 213, 1, // 8681: decode to MVE_VRMLSLDAVHaxs32 using decoder 213 |
| 7325 | // 8681: } |
| 7326 | // 8681: } |
| 7327 | // 8681: } // switch Inst[31:28] |
| 7328 | // 8681: } |
| 7329 | 1, 0, // 8686: case 0x1: { |
| 7330 | OPC_CheckField, 28, 4, 14, // 8688: check Inst[31:28] == 0xe |
| 7331 | OPC_Scope, 11, // 8692: try { |
| 7332 | OPC_CheckField, 20, 3, 7, // 8694: check Inst[22:20] == 0x7 |
| 7333 | OPC_CheckPredicate, 31, // 8698: check predicate 31 |
| 7334 | OPC_Decode, 238, 10, 212, 1, // 8700: decode to MVE_VMLSDAVaxs32 using decoder 212 |
| 7335 | // 8700: } else try { |
| 7336 | OPC_CheckPredicate, 31, // 8705: check predicate 31 |
| 7337 | OPC_Decode, 249, 10, 213, 1, // 8707: decode to MVE_VMLSLDAVaxs32 using decoder 213 |
| 7338 | // 8707: } |
| 7339 | // 8707: } |
| 7340 | // 8707: } // switch Inst[16] |
| 7341 | // 8707: } |
| 7342 | // 8707: } // switch Inst[12] |
| 7343 | // 8707: } |
| 7344 | // 8707: } // switch Inst[7:4] |
| 7345 | // 8707: } |
| 7346 | // 8707: } // switch Inst[0] |
| 7347 | // 8707: } |
| 7348 | 15, 0, // 8712: case 0xf: { |
| 7349 | OPC_SwitchField, 6, 1, // 8714: switch Inst[6] { |
| 7350 | 0, 252, 6, // 8717: case 0x0: { |
| 7351 | OPC_SwitchField, 0, 1, // 8720: switch Inst[0] { |
| 7352 | 0, 252, 5, // 8723: case 0x0: { |
| 7353 | OPC_SwitchField, 4, 2, // 8726: switch Inst[5:4] { |
| 7354 | 0, 132, 4, // 8729: case 0x0: { |
| 7355 | OPC_SwitchField, 7, 1, // 8732: switch Inst[7] { |
| 7356 | 0, 223, 2, // 8735: case 0x0: { |
| 7357 | OPC_SwitchField, 16, 1, // 8738: switch Inst[16] { |
| 7358 | 0, 205, 1, // 8741: case 0x0: { |
| 7359 | OPC_SwitchField, 28, 4, // 8744: switch Inst[31:28] { |
| 7360 | 14, 124, // 8747: case 0xe: { |
| 7361 | OPC_Scope, 75, // 8749: try { |
| 7362 | OPC_SwitchField, 17, 6, // 8751: switch Inst[22:17] { |
| 7363 | 48, 7, // 8754: case 0x30: { |
| 7364 | OPC_CheckPredicate, 31, // 8756: check predicate 31 |
| 7365 | OPC_Decode, 148, 10, 214, 1, // 8758: decode to MVE_VMAXAVs8 using decoder 214 |
| 7366 | // 8758: } |
| 7367 | 49, 7, // 8763: case 0x31: { |
| 7368 | OPC_CheckPredicate, 31, // 8765: check predicate 31 |
| 7369 | OPC_Decode, 162, 10, 214, 1, // 8767: decode to MVE_VMAXVs8 using decoder 214 |
| 7370 | // 8767: } |
| 7371 | 50, 7, // 8772: case 0x32: { |
| 7372 | OPC_CheckPredicate, 31, // 8774: check predicate 31 |
| 7373 | OPC_Decode, 146, 10, 214, 1, // 8776: decode to MVE_VMAXAVs16 using decoder 214 |
| 7374 | // 8776: } |
| 7375 | 51, 7, // 8781: case 0x33: { |
| 7376 | OPC_CheckPredicate, 31, // 8783: check predicate 31 |
| 7377 | OPC_Decode, 160, 10, 214, 1, // 8785: decode to MVE_VMAXVs16 using decoder 214 |
| 7378 | // 8785: } |
| 7379 | 52, 7, // 8790: case 0x34: { |
| 7380 | OPC_CheckPredicate, 31, // 8792: check predicate 31 |
| 7381 | OPC_Decode, 147, 10, 214, 1, // 8794: decode to MVE_VMAXAVs32 using decoder 214 |
| 7382 | // 8794: } |
| 7383 | 53, 7, // 8799: case 0x35: { |
| 7384 | OPC_CheckPredicate, 31, // 8801: check predicate 31 |
| 7385 | OPC_Decode, 161, 10, 214, 1, // 8803: decode to MVE_VMAXVs32 using decoder 214 |
| 7386 | // 8803: } |
| 7387 | 54, 7, // 8808: case 0x36: { |
| 7388 | OPC_CheckPredicate, 33, // 8810: check predicate 33 |
| 7389 | OPC_Decode, 153, 10, 214, 1, // 8812: decode to MVE_VMAXNMAVf32 using decoder 214 |
| 7390 | // 8812: } |
| 7391 | 55, 0, // 8817: case 0x37: { |
| 7392 | OPC_CheckPredicate, 33, // 8819: check predicate 33 |
| 7393 | OPC_Decode, 157, 10, 214, 1, // 8821: decode to MVE_VMAXNMVf32 using decoder 214 |
| 7394 | // 8821: } |
| 7395 | // 8821: } // switch Inst[22:17] |
| 7396 | // 8821: } else try { |
| 7397 | OPC_SwitchField, 12, 1, // 8826: switch Inst[12] { |
| 7398 | 0, 20, // 8829: case 0x0: { |
| 7399 | OPC_Scope, 11, // 8831: try { |
| 7400 | OPC_CheckField, 20, 3, 7, // 8833: check Inst[22:20] == 0x7 |
| 7401 | OPC_CheckPredicate, 31, // 8837: check predicate 31 |
| 7402 | OPC_Decode, 209, 10, 210, 1, // 8839: decode to MVE_VMLADAVs8 using decoder 210 |
| 7403 | // 8839: } else try { |
| 7404 | OPC_CheckPredicate, 31, // 8844: check predicate 31 |
| 7405 | OPC_Decode, 148, 13, 211, 1, // 8846: decode to MVE_VRMLALDAVHs32 using decoder 211 |
| 7406 | // 8846: } |
| 7407 | // 8846: } |
| 7408 | 1, 0, // 8851: case 0x1: { |
| 7409 | OPC_Scope, 11, // 8853: try { |
| 7410 | OPC_CheckField, 20, 3, 7, // 8855: check Inst[22:20] == 0x7 |
| 7411 | OPC_CheckPredicate, 31, // 8859: check predicate 31 |
| 7412 | OPC_Decode, 215, 10, 210, 1, // 8861: decode to MVE_VMLADAVxs8 using decoder 210 |
| 7413 | // 8861: } else try { |
| 7414 | OPC_CheckPredicate, 31, // 8866: check predicate 31 |
| 7415 | OPC_Decode, 150, 13, 211, 1, // 8868: decode to MVE_VRMLALDAVHxs32 using decoder 211 |
| 7416 | // 8868: } |
| 7417 | // 8868: } |
| 7418 | // 8868: } // switch Inst[12] |
| 7419 | // 8868: } |
| 7420 | // 8868: } |
| 7421 | 15, 0, // 8873: case 0xf: { |
| 7422 | OPC_Scope, 48, // 8875: try { |
| 7423 | OPC_SwitchField, 17, 6, // 8877: switch Inst[22:17] { |
| 7424 | 49, 7, // 8880: case 0x31: { |
| 7425 | OPC_CheckPredicate, 31, // 8882: check predicate 31 |
| 7426 | OPC_Decode, 165, 10, 214, 1, // 8884: decode to MVE_VMAXVu8 using decoder 214 |
| 7427 | // 8884: } |
| 7428 | 51, 7, // 8889: case 0x33: { |
| 7429 | OPC_CheckPredicate, 31, // 8891: check predicate 31 |
| 7430 | OPC_Decode, 163, 10, 214, 1, // 8893: decode to MVE_VMAXVu16 using decoder 214 |
| 7431 | // 8893: } |
| 7432 | 53, 7, // 8898: case 0x35: { |
| 7433 | OPC_CheckPredicate, 31, // 8900: check predicate 31 |
| 7434 | OPC_Decode, 164, 10, 214, 1, // 8902: decode to MVE_VMAXVu32 using decoder 214 |
| 7435 | // 8902: } |
| 7436 | 54, 7, // 8907: case 0x36: { |
| 7437 | OPC_CheckPredicate, 33, // 8909: check predicate 33 |
| 7438 | OPC_Decode, 152, 10, 214, 1, // 8911: decode to MVE_VMAXNMAVf16 using decoder 214 |
| 7439 | // 8911: } |
| 7440 | 55, 0, // 8916: case 0x37: { |
| 7441 | OPC_CheckPredicate, 33, // 8918: check predicate 33 |
| 7442 | OPC_Decode, 156, 10, 214, 1, // 8920: decode to MVE_VMAXNMVf16 using decoder 214 |
| 7443 | // 8920: } |
| 7444 | // 8920: } // switch Inst[22:17] |
| 7445 | // 8920: } else try { |
| 7446 | OPC_CheckField, 12, 1, 0, // 8925: check Inst[12] == 0x0 |
| 7447 | OPC_Scope, 11, // 8929: try { |
| 7448 | OPC_CheckField, 20, 3, 7, // 8931: check Inst[22:20] == 0x7 |
| 7449 | OPC_CheckPredicate, 31, // 8935: check predicate 31 |
| 7450 | OPC_Decode, 212, 10, 210, 1, // 8937: decode to MVE_VMLADAVu8 using decoder 210 |
| 7451 | // 8937: } else try { |
| 7452 | OPC_CheckPredicate, 31, // 8942: check predicate 31 |
| 7453 | OPC_Decode, 149, 13, 211, 1, // 8944: decode to MVE_VRMLALDAVHu32 using decoder 211 |
| 7454 | // 8944: } |
| 7455 | // 8944: } |
| 7456 | // 8944: } |
| 7457 | // 8944: } // switch Inst[31:28] |
| 7458 | // 8944: } |
| 7459 | 1, 0, // 8949: case 0x1: { |
| 7460 | OPC_SwitchField, 17, 3, // 8951: switch Inst[19:17] { |
| 7461 | 0, 37, // 8954: case 0x0: { |
| 7462 | OPC_SwitchField, 28, 4, // 8956: switch Inst[31:28] { |
| 7463 | 14, 15, // 8959: case 0xe: { |
| 7464 | OPC_CheckPredicate, 31, // 8961: check predicate 31 |
| 7465 | OPC_CheckField, 20, 3, 7, // 8963: check Inst[22:20] == 0x7 |
| 7466 | OPC_CheckField, 12, 1, 0, // 8967: check Inst[12] == 0x0 |
| 7467 | OPC_Decode, 168, 8, 215, 1, // 8971: decode to MVE_VADDVs8no_acc using decoder 215 |
| 7468 | // 8971: } |
| 7469 | 15, 0, // 8976: case 0xf: { |
| 7470 | OPC_CheckPredicate, 31, // 8978: check predicate 31 |
| 7471 | OPC_CheckField, 20, 3, 7, // 8980: check Inst[22:20] == 0x7 |
| 7472 | OPC_CheckField, 12, 1, 0, // 8984: check Inst[12] == 0x0 |
| 7473 | OPC_Decode, 174, 8, 215, 1, // 8988: decode to MVE_VADDVu8no_acc using decoder 215 |
| 7474 | // 8988: } |
| 7475 | // 8988: } // switch Inst[31:28] |
| 7476 | // 8988: } |
| 7477 | 2, 37, // 8993: case 0x2: { |
| 7478 | OPC_SwitchField, 28, 4, // 8995: switch Inst[31:28] { |
| 7479 | 14, 15, // 8998: case 0xe: { |
| 7480 | OPC_CheckPredicate, 31, // 9000: check predicate 31 |
| 7481 | OPC_CheckField, 20, 3, 7, // 9002: check Inst[22:20] == 0x7 |
| 7482 | OPC_CheckField, 12, 1, 0, // 9006: check Inst[12] == 0x0 |
| 7483 | OPC_Decode, 164, 8, 215, 1, // 9010: decode to MVE_VADDVs16no_acc using decoder 215 |
| 7484 | // 9010: } |
| 7485 | 15, 0, // 9015: case 0xf: { |
| 7486 | OPC_CheckPredicate, 31, // 9017: check predicate 31 |
| 7487 | OPC_CheckField, 20, 3, 7, // 9019: check Inst[22:20] == 0x7 |
| 7488 | OPC_CheckField, 12, 1, 0, // 9023: check Inst[12] == 0x0 |
| 7489 | OPC_Decode, 170, 8, 215, 1, // 9027: decode to MVE_VADDVu16no_acc using decoder 215 |
| 7490 | // 9027: } |
| 7491 | // 9027: } // switch Inst[31:28] |
| 7492 | // 9027: } |
| 7493 | 4, 0, // 9032: case 0x4: { |
| 7494 | OPC_SwitchField, 28, 4, // 9034: switch Inst[31:28] { |
| 7495 | 14, 24, // 9037: case 0xe: { |
| 7496 | OPC_CheckField, 12, 1, 0, // 9039: check Inst[12] == 0x0 |
| 7497 | OPC_Scope, 11, // 9043: try { |
| 7498 | OPC_CheckField, 20, 3, 7, // 9045: check Inst[22:20] == 0x7 |
| 7499 | OPC_CheckPredicate, 31, // 9049: check predicate 31 |
| 7500 | OPC_Decode, 166, 8, 215, 1, // 9051: decode to MVE_VADDVs32no_acc using decoder 215 |
| 7501 | // 9051: } else try { |
| 7502 | OPC_CheckPredicate, 31, // 9056: check predicate 31 |
| 7503 | OPC_Decode, 160, 8, 216, 1, // 9058: decode to MVE_VADDLVs32no_acc using decoder 216 |
| 7504 | // 9058: } |
| 7505 | // 9058: } |
| 7506 | 15, 0, // 9063: case 0xf: { |
| 7507 | OPC_CheckField, 12, 1, 0, // 9065: check Inst[12] == 0x0 |
| 7508 | OPC_Scope, 11, // 9069: try { |
| 7509 | OPC_CheckField, 20, 3, 7, // 9071: check Inst[22:20] == 0x7 |
| 7510 | OPC_CheckPredicate, 31, // 9075: check predicate 31 |
| 7511 | OPC_Decode, 172, 8, 215, 1, // 9077: decode to MVE_VADDVu32no_acc using decoder 215 |
| 7512 | // 9077: } else try { |
| 7513 | OPC_CheckPredicate, 31, // 9082: check predicate 31 |
| 7514 | OPC_Decode, 162, 8, 216, 1, // 9084: decode to MVE_VADDLVu32no_acc using decoder 216 |
| 7515 | // 9084: } |
| 7516 | // 9084: } |
| 7517 | // 9084: } // switch Inst[31:28] |
| 7518 | // 9084: } |
| 7519 | // 9084: } // switch Inst[19:17] |
| 7520 | // 9084: } |
| 7521 | // 9084: } // switch Inst[16] |
| 7522 | // 9084: } |
| 7523 | 1, 0, // 9089: case 0x1: { |
| 7524 | OPC_SwitchField, 16, 7, // 9091: switch Inst[22:16] { |
| 7525 | 96, 11, // 9094: case 0x60: { |
| 7526 | OPC_CheckPredicate, 31, // 9096: check predicate 31 |
| 7527 | OPC_CheckField, 28, 4, 14, // 9098: check Inst[31:28] == 0xe |
| 7528 | OPC_Decode, 174, 10, 214, 1, // 9102: decode to MVE_VMINAVs8 using decoder 214 |
| 7529 | // 9102: } |
| 7530 | 98, 21, // 9107: case 0x62: { |
| 7531 | OPC_SwitchField, 28, 4, // 9109: switch Inst[31:28] { |
| 7532 | 14, 7, // 9112: case 0xe: { |
| 7533 | OPC_CheckPredicate, 31, // 9114: check predicate 31 |
| 7534 | OPC_Decode, 188, 10, 214, 1, // 9116: decode to MVE_VMINVs8 using decoder 214 |
| 7535 | // 9116: } |
| 7536 | 15, 0, // 9121: case 0xf: { |
| 7537 | OPC_CheckPredicate, 31, // 9123: check predicate 31 |
| 7538 | OPC_Decode, 191, 10, 214, 1, // 9125: decode to MVE_VMINVu8 using decoder 214 |
| 7539 | // 9125: } |
| 7540 | // 9125: } // switch Inst[31:28] |
| 7541 | // 9125: } |
| 7542 | 100, 11, // 9130: case 0x64: { |
| 7543 | OPC_CheckPredicate, 31, // 9132: check predicate 31 |
| 7544 | OPC_CheckField, 28, 4, 14, // 9134: check Inst[31:28] == 0xe |
| 7545 | OPC_Decode, 172, 10, 214, 1, // 9138: decode to MVE_VMINAVs16 using decoder 214 |
| 7546 | // 9138: } |
| 7547 | 102, 21, // 9143: case 0x66: { |
| 7548 | OPC_SwitchField, 28, 4, // 9145: switch Inst[31:28] { |
| 7549 | 14, 7, // 9148: case 0xe: { |
| 7550 | OPC_CheckPredicate, 31, // 9150: check predicate 31 |
| 7551 | OPC_Decode, 186, 10, 214, 1, // 9152: decode to MVE_VMINVs16 using decoder 214 |
| 7552 | // 9152: } |
| 7553 | 15, 0, // 9157: case 0xf: { |
| 7554 | OPC_CheckPredicate, 31, // 9159: check predicate 31 |
| 7555 | OPC_Decode, 189, 10, 214, 1, // 9161: decode to MVE_VMINVu16 using decoder 214 |
| 7556 | // 9161: } |
| 7557 | // 9161: } // switch Inst[31:28] |
| 7558 | // 9161: } |
| 7559 | 104, 11, // 9166: case 0x68: { |
| 7560 | OPC_CheckPredicate, 31, // 9168: check predicate 31 |
| 7561 | OPC_CheckField, 28, 4, 14, // 9170: check Inst[31:28] == 0xe |
| 7562 | OPC_Decode, 173, 10, 214, 1, // 9174: decode to MVE_VMINAVs32 using decoder 214 |
| 7563 | // 9174: } |
| 7564 | 106, 21, // 9179: case 0x6a: { |
| 7565 | OPC_SwitchField, 28, 4, // 9181: switch Inst[31:28] { |
| 7566 | 14, 7, // 9184: case 0xe: { |
| 7567 | OPC_CheckPredicate, 31, // 9186: check predicate 31 |
| 7568 | OPC_Decode, 187, 10, 214, 1, // 9188: decode to MVE_VMINVs32 using decoder 214 |
| 7569 | // 9188: } |
| 7570 | 15, 0, // 9193: case 0xf: { |
| 7571 | OPC_CheckPredicate, 31, // 9195: check predicate 31 |
| 7572 | OPC_Decode, 190, 10, 214, 1, // 9197: decode to MVE_VMINVu32 using decoder 214 |
| 7573 | // 9197: } |
| 7574 | // 9197: } // switch Inst[31:28] |
| 7575 | // 9197: } |
| 7576 | 108, 21, // 9202: case 0x6c: { |
| 7577 | OPC_SwitchField, 28, 4, // 9204: switch Inst[31:28] { |
| 7578 | 14, 7, // 9207: case 0xe: { |
| 7579 | OPC_CheckPredicate, 33, // 9209: check predicate 33 |
| 7580 | OPC_Decode, 179, 10, 214, 1, // 9211: decode to MVE_VMINNMAVf32 using decoder 214 |
| 7581 | // 9211: } |
| 7582 | 15, 0, // 9216: case 0xf: { |
| 7583 | OPC_CheckPredicate, 33, // 9218: check predicate 33 |
| 7584 | OPC_Decode, 178, 10, 214, 1, // 9220: decode to MVE_VMINNMAVf16 using decoder 214 |
| 7585 | // 9220: } |
| 7586 | // 9220: } // switch Inst[31:28] |
| 7587 | // 9220: } |
| 7588 | 110, 0, // 9225: case 0x6e: { |
| 7589 | OPC_SwitchField, 28, 4, // 9227: switch Inst[31:28] { |
| 7590 | 14, 7, // 9230: case 0xe: { |
| 7591 | OPC_CheckPredicate, 33, // 9232: check predicate 33 |
| 7592 | OPC_Decode, 183, 10, 214, 1, // 9234: decode to MVE_VMINNMVf32 using decoder 214 |
| 7593 | // 9234: } |
| 7594 | 15, 0, // 9239: case 0xf: { |
| 7595 | OPC_CheckPredicate, 33, // 9241: check predicate 33 |
| 7596 | OPC_Decode, 182, 10, 214, 1, // 9243: decode to MVE_VMINNMVf16 using decoder 214 |
| 7597 | // 9243: } |
| 7598 | // 9243: } // switch Inst[31:28] |
| 7599 | // 9243: } |
| 7600 | // 9243: } // switch Inst[22:16] |
| 7601 | // 9243: } |
| 7602 | // 9243: } // switch Inst[7] |
| 7603 | // 9243: } |
| 7604 | 2, 0, // 9248: case 0x2: { |
| 7605 | OPC_SwitchField, 12, 1, // 9250: switch Inst[12] { |
| 7606 | 0, 200, 1, // 9253: case 0x0: { |
| 7607 | OPC_SwitchField, 16, 1, // 9256: switch Inst[16] { |
| 7608 | 0, 55, // 9259: case 0x0: { |
| 7609 | OPC_SwitchField, 28, 4, // 9261: switch Inst[31:28] { |
| 7610 | 14, 24, // 9264: case 0xe: { |
| 7611 | OPC_CheckField, 7, 1, 0, // 9266: check Inst[7] == 0x0 |
| 7612 | OPC_Scope, 11, // 9270: try { |
| 7613 | OPC_CheckField, 20, 3, 7, // 9272: check Inst[22:20] == 0x7 |
| 7614 | OPC_CheckPredicate, 31, // 9276: check predicate 31 |
| 7615 | OPC_Decode, 200, 10, 212, 1, // 9278: decode to MVE_VMLADAVas8 using decoder 212 |
| 7616 | // 9278: } else try { |
| 7617 | OPC_CheckPredicate, 31, // 9283: check predicate 31 |
| 7618 | OPC_Decode, 145, 13, 213, 1, // 9285: decode to MVE_VRMLALDAVHas32 using decoder 213 |
| 7619 | // 9285: } |
| 7620 | // 9285: } |
| 7621 | 15, 0, // 9290: case 0xf: { |
| 7622 | OPC_CheckField, 7, 1, 0, // 9292: check Inst[7] == 0x0 |
| 7623 | OPC_Scope, 11, // 9296: try { |
| 7624 | OPC_CheckField, 20, 3, 7, // 9298: check Inst[22:20] == 0x7 |
| 7625 | OPC_CheckPredicate, 31, // 9302: check predicate 31 |
| 7626 | OPC_Decode, 203, 10, 212, 1, // 9304: decode to MVE_VMLADAVau8 using decoder 212 |
| 7627 | // 9304: } else try { |
| 7628 | OPC_CheckPredicate, 31, // 9309: check predicate 31 |
| 7629 | OPC_Decode, 146, 13, 213, 1, // 9311: decode to MVE_VRMLALDAVHau32 using decoder 213 |
| 7630 | // 9311: } |
| 7631 | // 9311: } |
| 7632 | // 9311: } // switch Inst[31:28] |
| 7633 | // 9311: } |
| 7634 | 1, 0, // 9316: case 0x1: { |
| 7635 | OPC_SwitchField, 17, 3, // 9318: switch Inst[19:17] { |
| 7636 | 0, 37, // 9321: case 0x0: { |
| 7637 | OPC_SwitchField, 28, 4, // 9323: switch Inst[31:28] { |
| 7638 | 14, 15, // 9326: case 0xe: { |
| 7639 | OPC_CheckPredicate, 31, // 9328: check predicate 31 |
| 7640 | OPC_CheckField, 20, 3, 7, // 9330: check Inst[22:20] == 0x7 |
| 7641 | OPC_CheckField, 7, 1, 0, // 9334: check Inst[7] == 0x0 |
| 7642 | OPC_Decode, 167, 8, 217, 1, // 9338: decode to MVE_VADDVs8acc using decoder 217 |
| 7643 | // 9338: } |
| 7644 | 15, 0, // 9343: case 0xf: { |
| 7645 | OPC_CheckPredicate, 31, // 9345: check predicate 31 |
| 7646 | OPC_CheckField, 20, 3, 7, // 9347: check Inst[22:20] == 0x7 |
| 7647 | OPC_CheckField, 7, 1, 0, // 9351: check Inst[7] == 0x0 |
| 7648 | OPC_Decode, 173, 8, 217, 1, // 9355: decode to MVE_VADDVu8acc using decoder 217 |
| 7649 | // 9355: } |
| 7650 | // 9355: } // switch Inst[31:28] |
| 7651 | // 9355: } |
| 7652 | 2, 37, // 9360: case 0x2: { |
| 7653 | OPC_SwitchField, 28, 4, // 9362: switch Inst[31:28] { |
| 7654 | 14, 15, // 9365: case 0xe: { |
| 7655 | OPC_CheckPredicate, 31, // 9367: check predicate 31 |
| 7656 | OPC_CheckField, 20, 3, 7, // 9369: check Inst[22:20] == 0x7 |
| 7657 | OPC_CheckField, 7, 1, 0, // 9373: check Inst[7] == 0x0 |
| 7658 | OPC_Decode, 163, 8, 217, 1, // 9377: decode to MVE_VADDVs16acc using decoder 217 |
| 7659 | // 9377: } |
| 7660 | 15, 0, // 9382: case 0xf: { |
| 7661 | OPC_CheckPredicate, 31, // 9384: check predicate 31 |
| 7662 | OPC_CheckField, 20, 3, 7, // 9386: check Inst[22:20] == 0x7 |
| 7663 | OPC_CheckField, 7, 1, 0, // 9390: check Inst[7] == 0x0 |
| 7664 | OPC_Decode, 169, 8, 217, 1, // 9394: decode to MVE_VADDVu16acc using decoder 217 |
| 7665 | // 9394: } |
| 7666 | // 9394: } // switch Inst[31:28] |
| 7667 | // 9394: } |
| 7668 | 4, 0, // 9399: case 0x4: { |
| 7669 | OPC_SwitchField, 28, 4, // 9401: switch Inst[31:28] { |
| 7670 | 14, 24, // 9404: case 0xe: { |
| 7671 | OPC_CheckField, 7, 1, 0, // 9406: check Inst[7] == 0x0 |
| 7672 | OPC_Scope, 11, // 9410: try { |
| 7673 | OPC_CheckField, 20, 3, 7, // 9412: check Inst[22:20] == 0x7 |
| 7674 | OPC_CheckPredicate, 31, // 9416: check predicate 31 |
| 7675 | OPC_Decode, 165, 8, 217, 1, // 9418: decode to MVE_VADDVs32acc using decoder 217 |
| 7676 | // 9418: } else try { |
| 7677 | OPC_CheckPredicate, 31, // 9423: check predicate 31 |
| 7678 | OPC_Decode, 159, 8, 218, 1, // 9425: decode to MVE_VADDLVs32acc using decoder 218 |
| 7679 | // 9425: } |
| 7680 | // 9425: } |
| 7681 | 15, 0, // 9430: case 0xf: { |
| 7682 | OPC_CheckField, 7, 1, 0, // 9432: check Inst[7] == 0x0 |
| 7683 | OPC_Scope, 11, // 9436: try { |
| 7684 | OPC_CheckField, 20, 3, 7, // 9438: check Inst[22:20] == 0x7 |
| 7685 | OPC_CheckPredicate, 31, // 9442: check predicate 31 |
| 7686 | OPC_Decode, 171, 8, 217, 1, // 9444: decode to MVE_VADDVu32acc using decoder 217 |
| 7687 | // 9444: } else try { |
| 7688 | OPC_CheckPredicate, 31, // 9449: check predicate 31 |
| 7689 | OPC_Decode, 161, 8, 218, 1, // 9451: decode to MVE_VADDLVu32acc using decoder 218 |
| 7690 | // 9451: } |
| 7691 | // 9451: } |
| 7692 | // 9451: } // switch Inst[31:28] |
| 7693 | // 9451: } |
| 7694 | // 9451: } // switch Inst[19:17] |
| 7695 | // 9451: } |
| 7696 | // 9451: } // switch Inst[16] |
| 7697 | // 9451: } |
| 7698 | 1, 0, // 9456: case 0x1: { |
| 7699 | OPC_CheckField, 7, 1, 0, // 9458: check Inst[7] == 0x0 |
| 7700 | OPC_CheckField, 16, 1, 0, // 9462: check Inst[16] == 0x0 |
| 7701 | OPC_CheckField, 28, 4, 14, // 9466: check Inst[31:28] == 0xe |
| 7702 | OPC_Scope, 11, // 9470: try { |
| 7703 | OPC_CheckField, 20, 3, 7, // 9472: check Inst[22:20] == 0x7 |
| 7704 | OPC_CheckPredicate, 31, // 9476: check predicate 31 |
| 7705 | OPC_Decode, 206, 10, 212, 1, // 9478: decode to MVE_VMLADAVaxs8 using decoder 212 |
| 7706 | // 9478: } else try { |
| 7707 | OPC_CheckPredicate, 31, // 9483: check predicate 31 |
| 7708 | OPC_Decode, 147, 13, 213, 1, // 9485: decode to MVE_VRMLALDAVHaxs32 using decoder 213 |
| 7709 | // 9485: } |
| 7710 | // 9485: } |
| 7711 | // 9485: } // switch Inst[12] |
| 7712 | // 9485: } |
| 7713 | // 9485: } // switch Inst[5:4] |
| 7714 | // 9485: } |
| 7715 | 1, 0, // 9490: case 0x1: { |
| 7716 | OPC_SwitchField, 20, 3, // 9492: switch Inst[22:20] { |
| 7717 | 0, 37, // 9495: case 0x0: { |
| 7718 | OPC_SwitchField, 28, 4, // 9497: switch Inst[31:28] { |
| 7719 | 14, 15, // 9500: case 0xe: { |
| 7720 | OPC_CheckPredicate, 31, // 9502: check predicate 31 |
| 7721 | OPC_CheckField, 16, 1, 0, // 9504: check Inst[16] == 0x0 |
| 7722 | OPC_CheckField, 4, 1, 0, // 9508: check Inst[4] == 0x0 |
| 7723 | OPC_Decode, 140, 8, 219, 1, // 9512: decode to MVE_VABAVs8 using decoder 219 |
| 7724 | // 9512: } |
| 7725 | 15, 0, // 9517: case 0xf: { |
| 7726 | OPC_CheckPredicate, 31, // 9519: check predicate 31 |
| 7727 | OPC_CheckField, 16, 1, 0, // 9521: check Inst[16] == 0x0 |
| 7728 | OPC_CheckField, 4, 1, 0, // 9525: check Inst[4] == 0x0 |
| 7729 | OPC_Decode, 143, 8, 219, 1, // 9529: decode to MVE_VABAVu8 using decoder 219 |
| 7730 | // 9529: } |
| 7731 | // 9529: } // switch Inst[31:28] |
| 7732 | // 9529: } |
| 7733 | 1, 37, // 9534: case 0x1: { |
| 7734 | OPC_SwitchField, 28, 4, // 9536: switch Inst[31:28] { |
| 7735 | 14, 15, // 9539: case 0xe: { |
| 7736 | OPC_CheckPredicate, 31, // 9541: check predicate 31 |
| 7737 | OPC_CheckField, 16, 1, 0, // 9543: check Inst[16] == 0x0 |
| 7738 | OPC_CheckField, 4, 1, 0, // 9547: check Inst[4] == 0x0 |
| 7739 | OPC_Decode, 138, 8, 219, 1, // 9551: decode to MVE_VABAVs16 using decoder 219 |
| 7740 | // 9551: } |
| 7741 | 15, 0, // 9556: case 0xf: { |
| 7742 | OPC_CheckPredicate, 31, // 9558: check predicate 31 |
| 7743 | OPC_CheckField, 16, 1, 0, // 9560: check Inst[16] == 0x0 |
| 7744 | OPC_CheckField, 4, 1, 0, // 9564: check Inst[4] == 0x0 |
| 7745 | OPC_Decode, 141, 8, 219, 1, // 9568: decode to MVE_VABAVu16 using decoder 219 |
| 7746 | // 9568: } |
| 7747 | // 9568: } // switch Inst[31:28] |
| 7748 | // 9568: } |
| 7749 | 2, 0, // 9573: case 0x2: { |
| 7750 | OPC_SwitchField, 28, 4, // 9575: switch Inst[31:28] { |
| 7751 | 14, 15, // 9578: case 0xe: { |
| 7752 | OPC_CheckPredicate, 31, // 9580: check predicate 31 |
| 7753 | OPC_CheckField, 16, 1, 0, // 9582: check Inst[16] == 0x0 |
| 7754 | OPC_CheckField, 4, 1, 0, // 9586: check Inst[4] == 0x0 |
| 7755 | OPC_Decode, 139, 8, 219, 1, // 9590: decode to MVE_VABAVs32 using decoder 219 |
| 7756 | // 9590: } |
| 7757 | 15, 0, // 9595: case 0xf: { |
| 7758 | OPC_CheckPredicate, 31, // 9597: check predicate 31 |
| 7759 | OPC_CheckField, 16, 1, 0, // 9599: check Inst[16] == 0x0 |
| 7760 | OPC_CheckField, 4, 1, 0, // 9603: check Inst[4] == 0x0 |
| 7761 | OPC_Decode, 142, 8, 219, 1, // 9607: decode to MVE_VABAVu32 using decoder 219 |
| 7762 | // 9607: } |
| 7763 | // 9607: } // switch Inst[31:28] |
| 7764 | // 9607: } |
| 7765 | // 9607: } // switch Inst[22:20] |
| 7766 | // 9607: } |
| 7767 | // 9607: } // switch Inst[0] |
| 7768 | // 9607: } |
| 7769 | 1, 0, // 9612: case 0x1: { |
| 7770 | OPC_SwitchField, 7, 1, // 9614: switch Inst[7] { |
| 7771 | 0, 218, 4, // 9617: case 0x0: { |
| 7772 | OPC_SwitchField, 20, 2, // 9620: switch Inst[21:20] { |
| 7773 | 0, 169, 1, // 9623: case 0x0: { |
| 7774 | OPC_SwitchField, 0, 1, // 9626: switch Inst[0] { |
| 7775 | 0, 81, // 9629: case 0x0: { |
| 7776 | OPC_SwitchField, 12, 1, // 9631: switch Inst[12] { |
| 7777 | 0, 37, // 9634: case 0x0: { |
| 7778 | OPC_SwitchField, 28, 4, // 9636: switch Inst[31:28] { |
| 7779 | 14, 15, // 9639: case 0xe: { |
| 7780 | OPC_CheckPredicate, 31, // 9641: check predicate 31 |
| 7781 | OPC_CheckField, 19, 1, 1, // 9643: check Inst[19] == 0x1 |
| 7782 | OPC_CheckField, 4, 1, 0, // 9647: check Inst[4] == 0x0 |
| 7783 | OPC_Decode, 225, 12, 220, 1, // 9651: decode to MVE_VQSHRNbhs16 using decoder 220 |
| 7784 | // 9651: } |
| 7785 | 15, 0, // 9656: case 0xf: { |
| 7786 | OPC_CheckPredicate, 31, // 9658: check predicate 31 |
| 7787 | OPC_CheckField, 19, 1, 1, // 9660: check Inst[19] == 0x1 |
| 7788 | OPC_CheckField, 4, 1, 0, // 9664: check Inst[4] == 0x0 |
| 7789 | OPC_Decode, 227, 12, 220, 1, // 9668: decode to MVE_VQSHRNbhu16 using decoder 220 |
| 7790 | // 9668: } |
| 7791 | // 9668: } // switch Inst[31:28] |
| 7792 | // 9668: } |
| 7793 | 1, 0, // 9673: case 0x1: { |
| 7794 | OPC_SwitchField, 28, 4, // 9675: switch Inst[31:28] { |
| 7795 | 14, 15, // 9678: case 0xe: { |
| 7796 | OPC_CheckPredicate, 31, // 9680: check predicate 31 |
| 7797 | OPC_CheckField, 19, 1, 1, // 9682: check Inst[19] == 0x1 |
| 7798 | OPC_CheckField, 4, 1, 0, // 9686: check Inst[4] == 0x0 |
| 7799 | OPC_Decode, 229, 12, 220, 1, // 9690: decode to MVE_VQSHRNths16 using decoder 220 |
| 7800 | // 9690: } |
| 7801 | 15, 0, // 9695: case 0xf: { |
| 7802 | OPC_CheckPredicate, 31, // 9697: check predicate 31 |
| 7803 | OPC_CheckField, 19, 1, 1, // 9699: check Inst[19] == 0x1 |
| 7804 | OPC_CheckField, 4, 1, 0, // 9703: check Inst[4] == 0x0 |
| 7805 | OPC_Decode, 231, 12, 220, 1, // 9707: decode to MVE_VQSHRNthu16 using decoder 220 |
| 7806 | // 9707: } |
| 7807 | // 9707: } // switch Inst[31:28] |
| 7808 | // 9707: } |
| 7809 | // 9707: } // switch Inst[12] |
| 7810 | // 9707: } |
| 7811 | 1, 0, // 9712: case 0x1: { |
| 7812 | OPC_SwitchField, 12, 1, // 9714: switch Inst[12] { |
| 7813 | 0, 37, // 9717: case 0x0: { |
| 7814 | OPC_SwitchField, 28, 4, // 9719: switch Inst[31:28] { |
| 7815 | 14, 15, // 9722: case 0xe: { |
| 7816 | OPC_CheckPredicate, 31, // 9724: check predicate 31 |
| 7817 | OPC_CheckField, 19, 1, 1, // 9726: check Inst[19] == 0x1 |
| 7818 | OPC_CheckField, 4, 1, 0, // 9730: check Inst[4] == 0x0 |
| 7819 | OPC_Decode, 192, 12, 220, 1, // 9734: decode to MVE_VQRSHRNbhs16 using decoder 220 |
| 7820 | // 9734: } |
| 7821 | 15, 0, // 9739: case 0xf: { |
| 7822 | OPC_CheckPredicate, 31, // 9741: check predicate 31 |
| 7823 | OPC_CheckField, 19, 1, 1, // 9743: check Inst[19] == 0x1 |
| 7824 | OPC_CheckField, 4, 1, 0, // 9747: check Inst[4] == 0x0 |
| 7825 | OPC_Decode, 194, 12, 220, 1, // 9751: decode to MVE_VQRSHRNbhu16 using decoder 220 |
| 7826 | // 9751: } |
| 7827 | // 9751: } // switch Inst[31:28] |
| 7828 | // 9751: } |
| 7829 | 1, 0, // 9756: case 0x1: { |
| 7830 | OPC_SwitchField, 28, 4, // 9758: switch Inst[31:28] { |
| 7831 | 14, 15, // 9761: case 0xe: { |
| 7832 | OPC_CheckPredicate, 31, // 9763: check predicate 31 |
| 7833 | OPC_CheckField, 19, 1, 1, // 9765: check Inst[19] == 0x1 |
| 7834 | OPC_CheckField, 4, 1, 0, // 9769: check Inst[4] == 0x0 |
| 7835 | OPC_Decode, 196, 12, 220, 1, // 9773: decode to MVE_VQRSHRNths16 using decoder 220 |
| 7836 | // 9773: } |
| 7837 | 15, 0, // 9778: case 0xf: { |
| 7838 | OPC_CheckPredicate, 31, // 9780: check predicate 31 |
| 7839 | OPC_CheckField, 19, 1, 1, // 9782: check Inst[19] == 0x1 |
| 7840 | OPC_CheckField, 4, 1, 0, // 9786: check Inst[4] == 0x0 |
| 7841 | OPC_Decode, 198, 12, 220, 1, // 9790: decode to MVE_VQRSHRNthu16 using decoder 220 |
| 7842 | // 9790: } |
| 7843 | // 9790: } // switch Inst[31:28] |
| 7844 | // 9790: } |
| 7845 | // 9790: } // switch Inst[12] |
| 7846 | // 9790: } |
| 7847 | // 9790: } // switch Inst[0] |
| 7848 | // 9790: } |
| 7849 | 1, 137, 1, // 9795: case 0x1: { |
| 7850 | OPC_SwitchField, 0, 1, // 9798: switch Inst[0] { |
| 7851 | 0, 65, // 9801: case 0x0: { |
| 7852 | OPC_SwitchField, 12, 1, // 9803: switch Inst[12] { |
| 7853 | 0, 29, // 9806: case 0x0: { |
| 7854 | OPC_SwitchField, 28, 4, // 9808: switch Inst[31:28] { |
| 7855 | 14, 11, // 9811: case 0xe: { |
| 7856 | OPC_CheckPredicate, 31, // 9813: check predicate 31 |
| 7857 | OPC_CheckField, 4, 1, 0, // 9815: check Inst[4] == 0x0 |
| 7858 | OPC_Decode, 226, 12, 221, 1, // 9819: decode to MVE_VQSHRNbhs32 using decoder 221 |
| 7859 | // 9819: } |
| 7860 | 15, 0, // 9824: case 0xf: { |
| 7861 | OPC_CheckPredicate, 31, // 9826: check predicate 31 |
| 7862 | OPC_CheckField, 4, 1, 0, // 9828: check Inst[4] == 0x0 |
| 7863 | OPC_Decode, 228, 12, 221, 1, // 9832: decode to MVE_VQSHRNbhu32 using decoder 221 |
| 7864 | // 9832: } |
| 7865 | // 9832: } // switch Inst[31:28] |
| 7866 | // 9832: } |
| 7867 | 1, 0, // 9837: case 0x1: { |
| 7868 | OPC_SwitchField, 28, 4, // 9839: switch Inst[31:28] { |
| 7869 | 14, 11, // 9842: case 0xe: { |
| 7870 | OPC_CheckPredicate, 31, // 9844: check predicate 31 |
| 7871 | OPC_CheckField, 4, 1, 0, // 9846: check Inst[4] == 0x0 |
| 7872 | OPC_Decode, 230, 12, 221, 1, // 9850: decode to MVE_VQSHRNths32 using decoder 221 |
| 7873 | // 9850: } |
| 7874 | 15, 0, // 9855: case 0xf: { |
| 7875 | OPC_CheckPredicate, 31, // 9857: check predicate 31 |
| 7876 | OPC_CheckField, 4, 1, 0, // 9859: check Inst[4] == 0x0 |
| 7877 | OPC_Decode, 232, 12, 221, 1, // 9863: decode to MVE_VQSHRNthu32 using decoder 221 |
| 7878 | // 9863: } |
| 7879 | // 9863: } // switch Inst[31:28] |
| 7880 | // 9863: } |
| 7881 | // 9863: } // switch Inst[12] |
| 7882 | // 9863: } |
| 7883 | 1, 0, // 9868: case 0x1: { |
| 7884 | OPC_SwitchField, 12, 1, // 9870: switch Inst[12] { |
| 7885 | 0, 29, // 9873: case 0x0: { |
| 7886 | OPC_SwitchField, 28, 4, // 9875: switch Inst[31:28] { |
| 7887 | 14, 11, // 9878: case 0xe: { |
| 7888 | OPC_CheckPredicate, 31, // 9880: check predicate 31 |
| 7889 | OPC_CheckField, 4, 1, 0, // 9882: check Inst[4] == 0x0 |
| 7890 | OPC_Decode, 193, 12, 221, 1, // 9886: decode to MVE_VQRSHRNbhs32 using decoder 221 |
| 7891 | // 9886: } |
| 7892 | 15, 0, // 9891: case 0xf: { |
| 7893 | OPC_CheckPredicate, 31, // 9893: check predicate 31 |
| 7894 | OPC_CheckField, 4, 1, 0, // 9895: check Inst[4] == 0x0 |
| 7895 | OPC_Decode, 195, 12, 221, 1, // 9899: decode to MVE_VQRSHRNbhu32 using decoder 221 |
| 7896 | // 9899: } |
| 7897 | // 9899: } // switch Inst[31:28] |
| 7898 | // 9899: } |
| 7899 | 1, 0, // 9904: case 0x1: { |
| 7900 | OPC_SwitchField, 28, 4, // 9906: switch Inst[31:28] { |
| 7901 | 14, 11, // 9909: case 0xe: { |
| 7902 | OPC_CheckPredicate, 31, // 9911: check predicate 31 |
| 7903 | OPC_CheckField, 4, 1, 0, // 9913: check Inst[4] == 0x0 |
| 7904 | OPC_Decode, 197, 12, 221, 1, // 9917: decode to MVE_VQRSHRNths32 using decoder 221 |
| 7905 | // 9917: } |
| 7906 | 15, 0, // 9922: case 0xf: { |
| 7907 | OPC_CheckPredicate, 31, // 9924: check predicate 31 |
| 7908 | OPC_CheckField, 4, 1, 0, // 9926: check Inst[4] == 0x0 |
| 7909 | OPC_Decode, 199, 12, 221, 1, // 9930: decode to MVE_VQRSHRNthu32 using decoder 221 |
| 7910 | // 9930: } |
| 7911 | // 9930: } // switch Inst[31:28] |
| 7912 | // 9930: } |
| 7913 | // 9930: } // switch Inst[12] |
| 7914 | // 9930: } |
| 7915 | // 9930: } // switch Inst[0] |
| 7916 | // 9930: } |
| 7917 | 2, 149, 1, // 9935: case 0x2: { |
| 7918 | OPC_SwitchField, 12, 1, // 9938: switch Inst[12] { |
| 7919 | 0, 71, // 9941: case 0x0: { |
| 7920 | OPC_SwitchField, 28, 4, // 9943: switch Inst[31:28] { |
| 7921 | 14, 32, // 9946: case 0xe: { |
| 7922 | OPC_CheckField, 0, 1, 0, // 9948: check Inst[0] == 0x0 |
| 7923 | OPC_CheckField, 4, 1, 0, // 9952: check Inst[4] == 0x0 |
| 7924 | OPC_CheckField, 19, 1, 1, // 9956: check Inst[19] == 0x1 |
| 7925 | OPC_Scope, 11, // 9960: try { |
| 7926 | OPC_CheckField, 16, 3, 0, // 9962: check Inst[18:16] == 0x0 |
| 7927 | OPC_CheckPredicate, 31, // 9966: check predicate 31 |
| 7928 | OPC_Decode, 128, 11, 183, 1, // 9968: decode to MVE_VMOVLs8bh using decoder 183 |
| 7929 | // 9968: } else try { |
| 7930 | OPC_CheckPredicate, 31, // 9973: check predicate 31 |
| 7931 | OPC_Decode, 188, 13, 222, 1, // 9975: decode to MVE_VSHLL_imms8bh using decoder 222 |
| 7932 | // 9975: } |
| 7933 | // 9975: } |
| 7934 | 15, 0, // 9980: case 0xf: { |
| 7935 | OPC_CheckField, 0, 1, 0, // 9982: check Inst[0] == 0x0 |
| 7936 | OPC_CheckField, 4, 1, 0, // 9986: check Inst[4] == 0x0 |
| 7937 | OPC_CheckField, 19, 1, 1, // 9990: check Inst[19] == 0x1 |
| 7938 | OPC_Scope, 11, // 9994: try { |
| 7939 | OPC_CheckField, 16, 3, 0, // 9996: check Inst[18:16] == 0x0 |
| 7940 | OPC_CheckPredicate, 31, // 10000: check predicate 31 |
| 7941 | OPC_Decode, 132, 11, 183, 1, // 10002: decode to MVE_VMOVLu8bh using decoder 183 |
| 7942 | // 10002: } else try { |
| 7943 | OPC_CheckPredicate, 31, // 10007: check predicate 31 |
| 7944 | OPC_Decode, 192, 13, 222, 1, // 10009: decode to MVE_VSHLL_immu8bh using decoder 222 |
| 7945 | // 10009: } |
| 7946 | // 10009: } |
| 7947 | // 10009: } // switch Inst[31:28] |
| 7948 | // 10009: } |
| 7949 | 1, 0, // 10014: case 0x1: { |
| 7950 | OPC_SwitchField, 28, 4, // 10016: switch Inst[31:28] { |
| 7951 | 14, 32, // 10019: case 0xe: { |
| 7952 | OPC_CheckField, 0, 1, 0, // 10021: check Inst[0] == 0x0 |
| 7953 | OPC_CheckField, 4, 1, 0, // 10025: check Inst[4] == 0x0 |
| 7954 | OPC_CheckField, 19, 1, 1, // 10029: check Inst[19] == 0x1 |
| 7955 | OPC_Scope, 11, // 10033: try { |
| 7956 | OPC_CheckField, 16, 3, 0, // 10035: check Inst[18:16] == 0x0 |
| 7957 | OPC_CheckPredicate, 31, // 10039: check predicate 31 |
| 7958 | OPC_Decode, 129, 11, 183, 1, // 10041: decode to MVE_VMOVLs8th using decoder 183 |
| 7959 | // 10041: } else try { |
| 7960 | OPC_CheckPredicate, 31, // 10046: check predicate 31 |
| 7961 | OPC_Decode, 189, 13, 222, 1, // 10048: decode to MVE_VSHLL_imms8th using decoder 222 |
| 7962 | // 10048: } |
| 7963 | // 10048: } |
| 7964 | 15, 0, // 10053: case 0xf: { |
| 7965 | OPC_CheckField, 0, 1, 0, // 10055: check Inst[0] == 0x0 |
| 7966 | OPC_CheckField, 4, 1, 0, // 10059: check Inst[4] == 0x0 |
| 7967 | OPC_CheckField, 19, 1, 1, // 10063: check Inst[19] == 0x1 |
| 7968 | OPC_Scope, 11, // 10067: try { |
| 7969 | OPC_CheckField, 16, 3, 0, // 10069: check Inst[18:16] == 0x0 |
| 7970 | OPC_CheckPredicate, 31, // 10073: check predicate 31 |
| 7971 | OPC_Decode, 133, 11, 183, 1, // 10075: decode to MVE_VMOVLu8th using decoder 183 |
| 7972 | // 10075: } else try { |
| 7973 | OPC_CheckPredicate, 31, // 10080: check predicate 31 |
| 7974 | OPC_Decode, 193, 13, 222, 1, // 10082: decode to MVE_VSHLL_immu8th using decoder 222 |
| 7975 | // 10082: } |
| 7976 | // 10082: } |
| 7977 | // 10082: } // switch Inst[31:28] |
| 7978 | // 10082: } |
| 7979 | // 10082: } // switch Inst[12] |
| 7980 | // 10082: } |
| 7981 | 3, 0, // 10087: case 0x3: { |
| 7982 | OPC_SwitchField, 12, 1, // 10089: switch Inst[12] { |
| 7983 | 0, 63, // 10092: case 0x0: { |
| 7984 | OPC_SwitchField, 28, 4, // 10094: switch Inst[31:28] { |
| 7985 | 14, 28, // 10097: case 0xe: { |
| 7986 | OPC_CheckField, 0, 1, 0, // 10099: check Inst[0] == 0x0 |
| 7987 | OPC_CheckField, 4, 1, 0, // 10103: check Inst[4] == 0x0 |
| 7988 | OPC_Scope, 11, // 10107: try { |
| 7989 | OPC_CheckField, 16, 4, 0, // 10109: check Inst[19:16] == 0x0 |
| 7990 | OPC_CheckPredicate, 31, // 10113: check predicate 31 |
| 7991 | OPC_Decode, 254, 10, 183, 1, // 10115: decode to MVE_VMOVLs16bh using decoder 183 |
| 7992 | // 10115: } else try { |
| 7993 | OPC_CheckPredicate, 31, // 10120: check predicate 31 |
| 7994 | OPC_Decode, 186, 13, 223, 1, // 10122: decode to MVE_VSHLL_imms16bh using decoder 223 |
| 7995 | // 10122: } |
| 7996 | // 10122: } |
| 7997 | 15, 0, // 10127: case 0xf: { |
| 7998 | OPC_CheckField, 0, 1, 0, // 10129: check Inst[0] == 0x0 |
| 7999 | OPC_CheckField, 4, 1, 0, // 10133: check Inst[4] == 0x0 |
| 8000 | OPC_Scope, 11, // 10137: try { |
| 8001 | OPC_CheckField, 16, 4, 0, // 10139: check Inst[19:16] == 0x0 |
| 8002 | OPC_CheckPredicate, 31, // 10143: check predicate 31 |
| 8003 | OPC_Decode, 130, 11, 183, 1, // 10145: decode to MVE_VMOVLu16bh using decoder 183 |
| 8004 | // 10145: } else try { |
| 8005 | OPC_CheckPredicate, 31, // 10150: check predicate 31 |
| 8006 | OPC_Decode, 190, 13, 223, 1, // 10152: decode to MVE_VSHLL_immu16bh using decoder 223 |
| 8007 | // 10152: } |
| 8008 | // 10152: } |
| 8009 | // 10152: } // switch Inst[31:28] |
| 8010 | // 10152: } |
| 8011 | 1, 0, // 10157: case 0x1: { |
| 8012 | OPC_SwitchField, 28, 4, // 10159: switch Inst[31:28] { |
| 8013 | 14, 28, // 10162: case 0xe: { |
| 8014 | OPC_CheckField, 0, 1, 0, // 10164: check Inst[0] == 0x0 |
| 8015 | OPC_CheckField, 4, 1, 0, // 10168: check Inst[4] == 0x0 |
| 8016 | OPC_Scope, 11, // 10172: try { |
| 8017 | OPC_CheckField, 16, 4, 0, // 10174: check Inst[19:16] == 0x0 |
| 8018 | OPC_CheckPredicate, 31, // 10178: check predicate 31 |
| 8019 | OPC_Decode, 255, 10, 183, 1, // 10180: decode to MVE_VMOVLs16th using decoder 183 |
| 8020 | // 10180: } else try { |
| 8021 | OPC_CheckPredicate, 31, // 10185: check predicate 31 |
| 8022 | OPC_Decode, 187, 13, 223, 1, // 10187: decode to MVE_VSHLL_imms16th using decoder 223 |
| 8023 | // 10187: } |
| 8024 | // 10187: } |
| 8025 | 15, 0, // 10192: case 0xf: { |
| 8026 | OPC_CheckField, 0, 1, 0, // 10194: check Inst[0] == 0x0 |
| 8027 | OPC_CheckField, 4, 1, 0, // 10198: check Inst[4] == 0x0 |
| 8028 | OPC_Scope, 11, // 10202: try { |
| 8029 | OPC_CheckField, 16, 4, 0, // 10204: check Inst[19:16] == 0x0 |
| 8030 | OPC_CheckPredicate, 31, // 10208: check predicate 31 |
| 8031 | OPC_Decode, 131, 11, 183, 1, // 10210: decode to MVE_VMOVLu16th using decoder 183 |
| 8032 | // 10210: } else try { |
| 8033 | OPC_CheckPredicate, 31, // 10215: check predicate 31 |
| 8034 | OPC_Decode, 191, 13, 223, 1, // 10217: decode to MVE_VSHLL_immu16th using decoder 223 |
| 8035 | // 10217: } |
| 8036 | // 10217: } |
| 8037 | // 10217: } // switch Inst[31:28] |
| 8038 | // 10217: } |
| 8039 | // 10217: } // switch Inst[12] |
| 8040 | // 10217: } |
| 8041 | // 10217: } // switch Inst[21:20] |
| 8042 | // 10217: } |
| 8043 | 1, 0, // 10222: case 0x1: { |
| 8044 | OPC_SwitchField, 12, 1, // 10224: switch Inst[12] { |
| 8045 | 0, 176, 1, // 10227: case 0x0: { |
| 8046 | OPC_SwitchField, 21, 1, // 10230: switch Inst[21] { |
| 8047 | 0, 153, 1, // 10233: case 0x0: { |
| 8048 | OPC_SwitchField, 0, 1, // 10236: switch Inst[0] { |
| 8049 | 0, 73, // 10239: case 0x0: { |
| 8050 | OPC_SwitchField, 20, 1, // 10241: switch Inst[20] { |
| 8051 | 0, 37, // 10244: case 0x0: { |
| 8052 | OPC_SwitchField, 28, 4, // 10246: switch Inst[31:28] { |
| 8053 | 14, 15, // 10249: case 0xe: { |
| 8054 | OPC_CheckPredicate, 31, // 10251: check predicate 31 |
| 8055 | OPC_CheckField, 19, 1, 1, // 10253: check Inst[19] == 0x1 |
| 8056 | OPC_CheckField, 4, 1, 0, // 10257: check Inst[4] == 0x0 |
| 8057 | OPC_Decode, 233, 12, 220, 1, // 10261: decode to MVE_VQSHRUNs16bh using decoder 220 |
| 8058 | // 10261: } |
| 8059 | 15, 0, // 10266: case 0xf: { |
| 8060 | OPC_CheckPredicate, 31, // 10268: check predicate 31 |
| 8061 | OPC_CheckField, 19, 1, 1, // 10270: check Inst[19] == 0x1 |
| 8062 | OPC_CheckField, 4, 1, 0, // 10274: check Inst[4] == 0x0 |
| 8063 | OPC_Decode, 200, 12, 220, 1, // 10278: decode to MVE_VQRSHRUNs16bh using decoder 220 |
| 8064 | // 10278: } |
| 8065 | // 10278: } // switch Inst[31:28] |
| 8066 | // 10278: } |
| 8067 | 1, 0, // 10283: case 0x1: { |
| 8068 | OPC_SwitchField, 28, 4, // 10285: switch Inst[31:28] { |
| 8069 | 14, 11, // 10288: case 0xe: { |
| 8070 | OPC_CheckPredicate, 31, // 10290: check predicate 31 |
| 8071 | OPC_CheckField, 4, 1, 0, // 10292: check Inst[4] == 0x0 |
| 8072 | OPC_Decode, 235, 12, 221, 1, // 10296: decode to MVE_VQSHRUNs32bh using decoder 221 |
| 8073 | // 10296: } |
| 8074 | 15, 0, // 10301: case 0xf: { |
| 8075 | OPC_CheckPredicate, 31, // 10303: check predicate 31 |
| 8076 | OPC_CheckField, 4, 1, 0, // 10305: check Inst[4] == 0x0 |
| 8077 | OPC_Decode, 202, 12, 221, 1, // 10309: decode to MVE_VQRSHRUNs32bh using decoder 221 |
| 8078 | // 10309: } |
| 8079 | // 10309: } // switch Inst[31:28] |
| 8080 | // 10309: } |
| 8081 | // 10309: } // switch Inst[20] |
| 8082 | // 10309: } |
| 8083 | 1, 0, // 10314: case 0x1: { |
| 8084 | OPC_SwitchField, 20, 1, // 10316: switch Inst[20] { |
| 8085 | 0, 37, // 10319: case 0x0: { |
| 8086 | OPC_SwitchField, 28, 4, // 10321: switch Inst[31:28] { |
| 8087 | 14, 15, // 10324: case 0xe: { |
| 8088 | OPC_CheckPredicate, 31, // 10326: check predicate 31 |
| 8089 | OPC_CheckField, 19, 1, 1, // 10328: check Inst[19] == 0x1 |
| 8090 | OPC_CheckField, 4, 1, 0, // 10332: check Inst[4] == 0x0 |
| 8091 | OPC_Decode, 217, 13, 220, 1, // 10336: decode to MVE_VSHRNi16bh using decoder 220 |
| 8092 | // 10336: } |
| 8093 | 15, 0, // 10341: case 0xf: { |
| 8094 | OPC_CheckPredicate, 31, // 10343: check predicate 31 |
| 8095 | OPC_CheckField, 19, 1, 1, // 10345: check Inst[19] == 0x1 |
| 8096 | OPC_CheckField, 4, 1, 0, // 10349: check Inst[4] == 0x0 |
| 8097 | OPC_Decode, 173, 13, 220, 1, // 10353: decode to MVE_VRSHRNi16bh using decoder 220 |
| 8098 | // 10353: } |
| 8099 | // 10353: } // switch Inst[31:28] |
| 8100 | // 10353: } |
| 8101 | 1, 0, // 10358: case 0x1: { |
| 8102 | OPC_SwitchField, 28, 4, // 10360: switch Inst[31:28] { |
| 8103 | 14, 11, // 10363: case 0xe: { |
| 8104 | OPC_CheckPredicate, 31, // 10365: check predicate 31 |
| 8105 | OPC_CheckField, 4, 1, 0, // 10367: check Inst[4] == 0x0 |
| 8106 | OPC_Decode, 219, 13, 221, 1, // 10371: decode to MVE_VSHRNi32bh using decoder 221 |
| 8107 | // 10371: } |
| 8108 | 15, 0, // 10376: case 0xf: { |
| 8109 | OPC_CheckPredicate, 31, // 10378: check predicate 31 |
| 8110 | OPC_CheckField, 4, 1, 0, // 10380: check Inst[4] == 0x0 |
| 8111 | OPC_Decode, 175, 13, 221, 1, // 10384: decode to MVE_VRSHRNi32bh using decoder 221 |
| 8112 | // 10384: } |
| 8113 | // 10384: } // switch Inst[31:28] |
| 8114 | // 10384: } |
| 8115 | // 10384: } // switch Inst[20] |
| 8116 | // 10384: } |
| 8117 | // 10384: } // switch Inst[0] |
| 8118 | // 10384: } |
| 8119 | 1, 0, // 10389: case 0x1: { |
| 8120 | OPC_CheckPredicate, 31, // 10391: check predicate 31 |
| 8121 | OPC_CheckField, 28, 4, 14, // 10393: check Inst[31:28] == 0xe |
| 8122 | OPC_CheckField, 4, 2, 0, // 10397: check Inst[5:4] == 0x0 |
| 8123 | OPC_Decode, 185, 13, 224, 1, // 10401: decode to MVE_VSHLC using decoder 224 |
| 8124 | // 10401: } |
| 8125 | // 10401: } // switch Inst[21] |
| 8126 | // 10401: } |
| 8127 | 1, 0, // 10406: case 0x1: { |
| 8128 | OPC_SwitchField, 0, 1, // 10408: switch Inst[0] { |
| 8129 | 0, 73, // 10411: case 0x0: { |
| 8130 | OPC_SwitchField, 20, 2, // 10413: switch Inst[21:20] { |
| 8131 | 0, 37, // 10416: case 0x0: { |
| 8132 | OPC_SwitchField, 28, 4, // 10418: switch Inst[31:28] { |
| 8133 | 14, 15, // 10421: case 0xe: { |
| 8134 | OPC_CheckPredicate, 31, // 10423: check predicate 31 |
| 8135 | OPC_CheckField, 19, 1, 1, // 10425: check Inst[19] == 0x1 |
| 8136 | OPC_CheckField, 4, 1, 0, // 10429: check Inst[4] == 0x0 |
| 8137 | OPC_Decode, 234, 12, 220, 1, // 10433: decode to MVE_VQSHRUNs16th using decoder 220 |
| 8138 | // 10433: } |
| 8139 | 15, 0, // 10438: case 0xf: { |
| 8140 | OPC_CheckPredicate, 31, // 10440: check predicate 31 |
| 8141 | OPC_CheckField, 19, 1, 1, // 10442: check Inst[19] == 0x1 |
| 8142 | OPC_CheckField, 4, 1, 0, // 10446: check Inst[4] == 0x0 |
| 8143 | OPC_Decode, 201, 12, 220, 1, // 10450: decode to MVE_VQRSHRUNs16th using decoder 220 |
| 8144 | // 10450: } |
| 8145 | // 10450: } // switch Inst[31:28] |
| 8146 | // 10450: } |
| 8147 | 1, 0, // 10455: case 0x1: { |
| 8148 | OPC_SwitchField, 28, 4, // 10457: switch Inst[31:28] { |
| 8149 | 14, 11, // 10460: case 0xe: { |
| 8150 | OPC_CheckPredicate, 31, // 10462: check predicate 31 |
| 8151 | OPC_CheckField, 4, 1, 0, // 10464: check Inst[4] == 0x0 |
| 8152 | OPC_Decode, 236, 12, 221, 1, // 10468: decode to MVE_VQSHRUNs32th using decoder 221 |
| 8153 | // 10468: } |
| 8154 | 15, 0, // 10473: case 0xf: { |
| 8155 | OPC_CheckPredicate, 31, // 10475: check predicate 31 |
| 8156 | OPC_CheckField, 4, 1, 0, // 10477: check Inst[4] == 0x0 |
| 8157 | OPC_Decode, 203, 12, 221, 1, // 10481: decode to MVE_VQRSHRUNs32th using decoder 221 |
| 8158 | // 10481: } |
| 8159 | // 10481: } // switch Inst[31:28] |
| 8160 | // 10481: } |
| 8161 | // 10481: } // switch Inst[21:20] |
| 8162 | // 10481: } |
| 8163 | 1, 0, // 10486: case 0x1: { |
| 8164 | OPC_SwitchField, 20, 2, // 10488: switch Inst[21:20] { |
| 8165 | 0, 37, // 10491: case 0x0: { |
| 8166 | OPC_SwitchField, 28, 4, // 10493: switch Inst[31:28] { |
| 8167 | 14, 15, // 10496: case 0xe: { |
| 8168 | OPC_CheckPredicate, 31, // 10498: check predicate 31 |
| 8169 | OPC_CheckField, 19, 1, 1, // 10500: check Inst[19] == 0x1 |
| 8170 | OPC_CheckField, 4, 1, 0, // 10504: check Inst[4] == 0x0 |
| 8171 | OPC_Decode, 218, 13, 220, 1, // 10508: decode to MVE_VSHRNi16th using decoder 220 |
| 8172 | // 10508: } |
| 8173 | 15, 0, // 10513: case 0xf: { |
| 8174 | OPC_CheckPredicate, 31, // 10515: check predicate 31 |
| 8175 | OPC_CheckField, 19, 1, 1, // 10517: check Inst[19] == 0x1 |
| 8176 | OPC_CheckField, 4, 1, 0, // 10521: check Inst[4] == 0x0 |
| 8177 | OPC_Decode, 174, 13, 220, 1, // 10525: decode to MVE_VRSHRNi16th using decoder 220 |
| 8178 | // 10525: } |
| 8179 | // 10525: } // switch Inst[31:28] |
| 8180 | // 10525: } |
| 8181 | 1, 0, // 10530: case 0x1: { |
| 8182 | OPC_SwitchField, 28, 4, // 10532: switch Inst[31:28] { |
| 8183 | 14, 11, // 10535: case 0xe: { |
| 8184 | OPC_CheckPredicate, 31, // 10537: check predicate 31 |
| 8185 | OPC_CheckField, 4, 1, 0, // 10539: check Inst[4] == 0x0 |
| 8186 | OPC_Decode, 220, 13, 221, 1, // 10543: decode to MVE_VSHRNi32th using decoder 221 |
| 8187 | // 10543: } |
| 8188 | 15, 0, // 10548: case 0xf: { |
| 8189 | OPC_CheckPredicate, 31, // 10550: check predicate 31 |
| 8190 | OPC_CheckField, 4, 1, 0, // 10552: check Inst[4] == 0x0 |
| 8191 | OPC_Decode, 176, 13, 221, 1, // 10556: decode to MVE_VRSHRNi32th using decoder 221 |
| 8192 | // 10556: } |
| 8193 | // 10556: } // switch Inst[31:28] |
| 8194 | // 10556: } |
| 8195 | // 10556: } // switch Inst[21:20] |
| 8196 | // 10556: } |
| 8197 | // 10556: } // switch Inst[0] |
| 8198 | // 10556: } |
| 8199 | // 10556: } // switch Inst[12] |
| 8200 | // 10556: } |
| 8201 | // 10556: } // switch Inst[7] |
| 8202 | // 10556: } |
| 8203 | // 10556: } // switch Inst[6] |
| 8204 | // 10556: } |
| 8205 | // 10556: } // switch Inst[11:8] |
| 8206 | // 10556: } |
| 8207 | 2, 191, 22, // 10561: case 0x2: { |
| 8208 | OPC_SwitchField, 8, 5, // 10564: switch Inst[12:8] { |
| 8209 | 0, 172, 2, // 10567: case 0x0: { |
| 8210 | OPC_SwitchField, 20, 2, // 10570: switch Inst[21:20] { |
| 8211 | 0, 97, // 10573: case 0x0: { |
| 8212 | OPC_SwitchField, 4, 1, // 10575: switch Inst[4] { |
| 8213 | 0, 45, // 10578: case 0x0: { |
| 8214 | OPC_SwitchField, 28, 4, // 10580: switch Inst[31:28] { |
| 8215 | 14, 19, // 10583: case 0xe: { |
| 8216 | OPC_CheckPredicate, 31, // 10585: check predicate 31 |
| 8217 | OPC_CheckField, 16, 1, 0, // 10587: check Inst[16] == 0x0 |
| 8218 | OPC_CheckField, 6, 1, 1, // 10591: check Inst[6] == 0x1 |
| 8219 | OPC_CheckField, 0, 1, 0, // 10595: check Inst[0] == 0x0 |
| 8220 | OPC_Decode, 167, 9, 179, 1, // 10599: decode to MVE_VHADDs8 using decoder 179 |
| 8221 | // 10599: } |
| 8222 | 15, 0, // 10604: case 0xf: { |
| 8223 | OPC_CheckPredicate, 31, // 10606: check predicate 31 |
| 8224 | OPC_CheckField, 16, 1, 0, // 10608: check Inst[16] == 0x0 |
| 8225 | OPC_CheckField, 6, 1, 1, // 10612: check Inst[6] == 0x1 |
| 8226 | OPC_CheckField, 0, 1, 0, // 10616: check Inst[0] == 0x0 |
| 8227 | OPC_Decode, 170, 9, 179, 1, // 10620: decode to MVE_VHADDu8 using decoder 179 |
| 8228 | // 10620: } |
| 8229 | // 10620: } // switch Inst[31:28] |
| 8230 | // 10620: } |
| 8231 | 1, 0, // 10625: case 0x1: { |
| 8232 | OPC_SwitchField, 28, 4, // 10627: switch Inst[31:28] { |
| 8233 | 14, 19, // 10630: case 0xe: { |
| 8234 | OPC_CheckPredicate, 31, // 10632: check predicate 31 |
| 8235 | OPC_CheckField, 16, 1, 0, // 10634: check Inst[16] == 0x0 |
| 8236 | OPC_CheckField, 6, 1, 1, // 10638: check Inst[6] == 0x1 |
| 8237 | OPC_CheckField, 0, 1, 0, // 10642: check Inst[0] == 0x0 |
| 8238 | OPC_Decode, 233, 11, 179, 1, // 10646: decode to MVE_VQADDs8 using decoder 179 |
| 8239 | // 10646: } |
| 8240 | 15, 0, // 10651: case 0xf: { |
| 8241 | OPC_CheckPredicate, 31, // 10653: check predicate 31 |
| 8242 | OPC_CheckField, 16, 1, 0, // 10655: check Inst[16] == 0x0 |
| 8243 | OPC_CheckField, 6, 1, 1, // 10659: check Inst[6] == 0x1 |
| 8244 | OPC_CheckField, 0, 1, 0, // 10663: check Inst[0] == 0x0 |
| 8245 | OPC_Decode, 236, 11, 179, 1, // 10667: decode to MVE_VQADDu8 using decoder 179 |
| 8246 | // 10667: } |
| 8247 | // 10667: } // switch Inst[31:28] |
| 8248 | // 10667: } |
| 8249 | // 10667: } // switch Inst[4] |
| 8250 | // 10667: } |
| 8251 | 1, 97, // 10672: case 0x1: { |
| 8252 | OPC_SwitchField, 4, 1, // 10674: switch Inst[4] { |
| 8253 | 0, 45, // 10677: case 0x0: { |
| 8254 | OPC_SwitchField, 28, 4, // 10679: switch Inst[31:28] { |
| 8255 | 14, 19, // 10682: case 0xe: { |
| 8256 | OPC_CheckPredicate, 31, // 10684: check predicate 31 |
| 8257 | OPC_CheckField, 16, 1, 0, // 10686: check Inst[16] == 0x0 |
| 8258 | OPC_CheckField, 6, 1, 1, // 10690: check Inst[6] == 0x1 |
| 8259 | OPC_CheckField, 0, 1, 0, // 10694: check Inst[0] == 0x0 |
| 8260 | OPC_Decode, 165, 9, 179, 1, // 10698: decode to MVE_VHADDs16 using decoder 179 |
| 8261 | // 10698: } |
| 8262 | 15, 0, // 10703: case 0xf: { |
| 8263 | OPC_CheckPredicate, 31, // 10705: check predicate 31 |
| 8264 | OPC_CheckField, 16, 1, 0, // 10707: check Inst[16] == 0x0 |
| 8265 | OPC_CheckField, 6, 1, 1, // 10711: check Inst[6] == 0x1 |
| 8266 | OPC_CheckField, 0, 1, 0, // 10715: check Inst[0] == 0x0 |
| 8267 | OPC_Decode, 168, 9, 179, 1, // 10719: decode to MVE_VHADDu16 using decoder 179 |
| 8268 | // 10719: } |
| 8269 | // 10719: } // switch Inst[31:28] |
| 8270 | // 10719: } |
| 8271 | 1, 0, // 10724: case 0x1: { |
| 8272 | OPC_SwitchField, 28, 4, // 10726: switch Inst[31:28] { |
| 8273 | 14, 19, // 10729: case 0xe: { |
| 8274 | OPC_CheckPredicate, 31, // 10731: check predicate 31 |
| 8275 | OPC_CheckField, 16, 1, 0, // 10733: check Inst[16] == 0x0 |
| 8276 | OPC_CheckField, 6, 1, 1, // 10737: check Inst[6] == 0x1 |
| 8277 | OPC_CheckField, 0, 1, 0, // 10741: check Inst[0] == 0x0 |
| 8278 | OPC_Decode, 231, 11, 179, 1, // 10745: decode to MVE_VQADDs16 using decoder 179 |
| 8279 | // 10745: } |
| 8280 | 15, 0, // 10750: case 0xf: { |
| 8281 | OPC_CheckPredicate, 31, // 10752: check predicate 31 |
| 8282 | OPC_CheckField, 16, 1, 0, // 10754: check Inst[16] == 0x0 |
| 8283 | OPC_CheckField, 6, 1, 1, // 10758: check Inst[6] == 0x1 |
| 8284 | OPC_CheckField, 0, 1, 0, // 10762: check Inst[0] == 0x0 |
| 8285 | OPC_Decode, 234, 11, 179, 1, // 10766: decode to MVE_VQADDu16 using decoder 179 |
| 8286 | // 10766: } |
| 8287 | // 10766: } // switch Inst[31:28] |
| 8288 | // 10766: } |
| 8289 | // 10766: } // switch Inst[4] |
| 8290 | // 10766: } |
| 8291 | 2, 0, // 10771: case 0x2: { |
| 8292 | OPC_SwitchField, 4, 1, // 10773: switch Inst[4] { |
| 8293 | 0, 45, // 10776: case 0x0: { |
| 8294 | OPC_SwitchField, 28, 4, // 10778: switch Inst[31:28] { |
| 8295 | 14, 19, // 10781: case 0xe: { |
| 8296 | OPC_CheckPredicate, 31, // 10783: check predicate 31 |
| 8297 | OPC_CheckField, 16, 1, 0, // 10785: check Inst[16] == 0x0 |
| 8298 | OPC_CheckField, 6, 1, 1, // 10789: check Inst[6] == 0x1 |
| 8299 | OPC_CheckField, 0, 1, 0, // 10793: check Inst[0] == 0x0 |
| 8300 | OPC_Decode, 166, 9, 179, 1, // 10797: decode to MVE_VHADDs32 using decoder 179 |
| 8301 | // 10797: } |
| 8302 | 15, 0, // 10802: case 0xf: { |
| 8303 | OPC_CheckPredicate, 31, // 10804: check predicate 31 |
| 8304 | OPC_CheckField, 16, 1, 0, // 10806: check Inst[16] == 0x0 |
| 8305 | OPC_CheckField, 6, 1, 1, // 10810: check Inst[6] == 0x1 |
| 8306 | OPC_CheckField, 0, 1, 0, // 10814: check Inst[0] == 0x0 |
| 8307 | OPC_Decode, 169, 9, 179, 1, // 10818: decode to MVE_VHADDu32 using decoder 179 |
| 8308 | // 10818: } |
| 8309 | // 10818: } // switch Inst[31:28] |
| 8310 | // 10818: } |
| 8311 | 1, 0, // 10823: case 0x1: { |
| 8312 | OPC_SwitchField, 28, 4, // 10825: switch Inst[31:28] { |
| 8313 | 14, 19, // 10828: case 0xe: { |
| 8314 | OPC_CheckPredicate, 31, // 10830: check predicate 31 |
| 8315 | OPC_CheckField, 16, 1, 0, // 10832: check Inst[16] == 0x0 |
| 8316 | OPC_CheckField, 6, 1, 1, // 10836: check Inst[6] == 0x1 |
| 8317 | OPC_CheckField, 0, 1, 0, // 10840: check Inst[0] == 0x0 |
| 8318 | OPC_Decode, 232, 11, 179, 1, // 10844: decode to MVE_VQADDs32 using decoder 179 |
| 8319 | // 10844: } |
| 8320 | 15, 0, // 10849: case 0xf: { |
| 8321 | OPC_CheckPredicate, 31, // 10851: check predicate 31 |
| 8322 | OPC_CheckField, 16, 1, 0, // 10853: check Inst[16] == 0x0 |
| 8323 | OPC_CheckField, 6, 1, 1, // 10857: check Inst[6] == 0x1 |
| 8324 | OPC_CheckField, 0, 1, 0, // 10861: check Inst[0] == 0x0 |
| 8325 | OPC_Decode, 235, 11, 179, 1, // 10865: decode to MVE_VQADDu32 using decoder 179 |
| 8326 | // 10865: } |
| 8327 | // 10865: } // switch Inst[31:28] |
| 8328 | // 10865: } |
| 8329 | // 10865: } // switch Inst[4] |
| 8330 | // 10865: } |
| 8331 | // 10865: } // switch Inst[21:20] |
| 8332 | // 10865: } |
| 8333 | 1, 157, 2, // 10870: case 0x1: { |
| 8334 | OPC_SwitchField, 20, 2, // 10873: switch Inst[21:20] { |
| 8335 | 0, 97, // 10876: case 0x0: { |
| 8336 | OPC_SwitchField, 4, 1, // 10878: switch Inst[4] { |
| 8337 | 0, 45, // 10881: case 0x0: { |
| 8338 | OPC_SwitchField, 28, 4, // 10883: switch Inst[31:28] { |
| 8339 | 14, 19, // 10886: case 0xe: { |
| 8340 | OPC_CheckPredicate, 31, // 10888: check predicate 31 |
| 8341 | OPC_CheckField, 16, 1, 0, // 10890: check Inst[16] == 0x0 |
| 8342 | OPC_CheckField, 6, 1, 1, // 10894: check Inst[6] == 0x1 |
| 8343 | OPC_CheckField, 0, 1, 0, // 10898: check Inst[0] == 0x0 |
| 8344 | OPC_Decode, 129, 13, 179, 1, // 10902: decode to MVE_VRHADDs8 using decoder 179 |
| 8345 | // 10902: } |
| 8346 | 15, 0, // 10907: case 0xf: { |
| 8347 | OPC_CheckPredicate, 31, // 10909: check predicate 31 |
| 8348 | OPC_CheckField, 16, 1, 0, // 10911: check Inst[16] == 0x0 |
| 8349 | OPC_CheckField, 6, 1, 1, // 10915: check Inst[6] == 0x1 |
| 8350 | OPC_CheckField, 0, 1, 0, // 10919: check Inst[0] == 0x0 |
| 8351 | OPC_Decode, 132, 13, 179, 1, // 10923: decode to MVE_VRHADDu8 using decoder 179 |
| 8352 | // 10923: } |
| 8353 | // 10923: } // switch Inst[31:28] |
| 8354 | // 10923: } |
| 8355 | 1, 0, // 10928: case 0x1: { |
| 8356 | OPC_SwitchField, 28, 4, // 10930: switch Inst[31:28] { |
| 8357 | 14, 19, // 10933: case 0xe: { |
| 8358 | OPC_CheckPredicate, 31, // 10935: check predicate 31 |
| 8359 | OPC_CheckField, 16, 1, 0, // 10937: check Inst[16] == 0x0 |
| 8360 | OPC_CheckField, 6, 1, 1, // 10941: check Inst[6] == 0x1 |
| 8361 | OPC_CheckField, 0, 1, 0, // 10945: check Inst[0] == 0x0 |
| 8362 | OPC_Decode, 185, 8, 179, 1, // 10949: decode to MVE_VAND using decoder 179 |
| 8363 | // 10949: } |
| 8364 | 15, 0, // 10954: case 0xf: { |
| 8365 | OPC_CheckPredicate, 31, // 10956: check predicate 31 |
| 8366 | OPC_CheckField, 16, 1, 0, // 10958: check Inst[16] == 0x0 |
| 8367 | OPC_CheckField, 6, 1, 1, // 10962: check Inst[6] == 0x1 |
| 8368 | OPC_CheckField, 0, 1, 0, // 10966: check Inst[0] == 0x0 |
| 8369 | OPC_Decode, 150, 9, 179, 1, // 10970: decode to MVE_VEOR using decoder 179 |
| 8370 | // 10970: } |
| 8371 | // 10970: } // switch Inst[31:28] |
| 8372 | // 10970: } |
| 8373 | // 10970: } // switch Inst[4] |
| 8374 | // 10970: } |
| 8375 | 1, 75, // 10975: case 0x1: { |
| 8376 | OPC_SwitchField, 4, 1, // 10977: switch Inst[4] { |
| 8377 | 0, 45, // 10980: case 0x0: { |
| 8378 | OPC_SwitchField, 28, 4, // 10982: switch Inst[31:28] { |
| 8379 | 14, 19, // 10985: case 0xe: { |
| 8380 | OPC_CheckPredicate, 31, // 10987: check predicate 31 |
| 8381 | OPC_CheckField, 16, 1, 0, // 10989: check Inst[16] == 0x0 |
| 8382 | OPC_CheckField, 6, 1, 1, // 10993: check Inst[6] == 0x1 |
| 8383 | OPC_CheckField, 0, 1, 0, // 10997: check Inst[0] == 0x0 |
| 8384 | OPC_Decode, 255, 12, 179, 1, // 11001: decode to MVE_VRHADDs16 using decoder 179 |
| 8385 | // 11001: } |
| 8386 | 15, 0, // 11006: case 0xf: { |
| 8387 | OPC_CheckPredicate, 31, // 11008: check predicate 31 |
| 8388 | OPC_CheckField, 16, 1, 0, // 11010: check Inst[16] == 0x0 |
| 8389 | OPC_CheckField, 6, 1, 1, // 11014: check Inst[6] == 0x1 |
| 8390 | OPC_CheckField, 0, 1, 0, // 11018: check Inst[0] == 0x0 |
| 8391 | OPC_Decode, 130, 13, 179, 1, // 11022: decode to MVE_VRHADDu16 using decoder 179 |
| 8392 | // 11022: } |
| 8393 | // 11022: } // switch Inst[31:28] |
| 8394 | // 11022: } |
| 8395 | 1, 0, // 11027: case 0x1: { |
| 8396 | OPC_CheckPredicate, 31, // 11029: check predicate 31 |
| 8397 | OPC_CheckField, 28, 4, 14, // 11031: check Inst[31:28] == 0xe |
| 8398 | OPC_CheckField, 16, 1, 0, // 11035: check Inst[16] == 0x0 |
| 8399 | OPC_CheckField, 6, 1, 1, // 11039: check Inst[6] == 0x1 |
| 8400 | OPC_CheckField, 0, 1, 0, // 11043: check Inst[0] == 0x0 |
| 8401 | OPC_Decode, 186, 8, 179, 1, // 11047: decode to MVE_VBIC using decoder 179 |
| 8402 | // 11047: } |
| 8403 | // 11047: } // switch Inst[4] |
| 8404 | // 11047: } |
| 8405 | 2, 75, // 11052: case 0x2: { |
| 8406 | OPC_SwitchField, 4, 1, // 11054: switch Inst[4] { |
| 8407 | 0, 45, // 11057: case 0x0: { |
| 8408 | OPC_SwitchField, 28, 4, // 11059: switch Inst[31:28] { |
| 8409 | 14, 19, // 11062: case 0xe: { |
| 8410 | OPC_CheckPredicate, 31, // 11064: check predicate 31 |
| 8411 | OPC_CheckField, 16, 1, 0, // 11066: check Inst[16] == 0x0 |
| 8412 | OPC_CheckField, 6, 1, 1, // 11070: check Inst[6] == 0x1 |
| 8413 | OPC_CheckField, 0, 1, 0, // 11074: check Inst[0] == 0x0 |
| 8414 | OPC_Decode, 128, 13, 179, 1, // 11078: decode to MVE_VRHADDs32 using decoder 179 |
| 8415 | // 11078: } |
| 8416 | 15, 0, // 11083: case 0xf: { |
| 8417 | OPC_CheckPredicate, 31, // 11085: check predicate 31 |
| 8418 | OPC_CheckField, 16, 1, 0, // 11087: check Inst[16] == 0x0 |
| 8419 | OPC_CheckField, 6, 1, 1, // 11091: check Inst[6] == 0x1 |
| 8420 | OPC_CheckField, 0, 1, 0, // 11095: check Inst[0] == 0x0 |
| 8421 | OPC_Decode, 131, 13, 179, 1, // 11099: decode to MVE_VRHADDu32 using decoder 179 |
| 8422 | // 11099: } |
| 8423 | // 11099: } // switch Inst[31:28] |
| 8424 | // 11099: } |
| 8425 | 1, 0, // 11104: case 0x1: { |
| 8426 | OPC_CheckPredicate, 31, // 11106: check predicate 31 |
| 8427 | OPC_CheckField, 28, 4, 14, // 11108: check Inst[31:28] == 0xe |
| 8428 | OPC_CheckField, 16, 1, 0, // 11112: check Inst[16] == 0x0 |
| 8429 | OPC_CheckField, 6, 1, 1, // 11116: check Inst[6] == 0x1 |
| 8430 | OPC_CheckField, 0, 1, 0, // 11120: check Inst[0] == 0x0 |
| 8431 | OPC_Decode, 194, 11, 179, 1, // 11124: decode to MVE_VORR using decoder 179 |
| 8432 | // 11124: } |
| 8433 | // 11124: } // switch Inst[4] |
| 8434 | // 11124: } |
| 8435 | 3, 0, // 11129: case 0x3: { |
| 8436 | OPC_CheckPredicate, 31, // 11131: check predicate 31 |
| 8437 | OPC_CheckField, 28, 4, 14, // 11133: check Inst[31:28] == 0xe |
| 8438 | OPC_CheckField, 16, 1, 0, // 11137: check Inst[16] == 0x0 |
| 8439 | OPC_CheckField, 6, 1, 1, // 11141: check Inst[6] == 0x1 |
| 8440 | OPC_CheckField, 4, 1, 1, // 11145: check Inst[4] == 0x1 |
| 8441 | OPC_CheckField, 0, 1, 0, // 11149: check Inst[0] == 0x0 |
| 8442 | OPC_Decode, 193, 11, 179, 1, // 11153: decode to MVE_VORN using decoder 179 |
| 8443 | // 11153: } |
| 8444 | // 11153: } // switch Inst[21:20] |
| 8445 | // 11153: } |
| 8446 | 2, 172, 2, // 11158: case 0x2: { |
| 8447 | OPC_SwitchField, 20, 2, // 11161: switch Inst[21:20] { |
| 8448 | 0, 97, // 11164: case 0x0: { |
| 8449 | OPC_SwitchField, 4, 1, // 11166: switch Inst[4] { |
| 8450 | 0, 45, // 11169: case 0x0: { |
| 8451 | OPC_SwitchField, 28, 4, // 11171: switch Inst[31:28] { |
| 8452 | 14, 19, // 11174: case 0xe: { |
| 8453 | OPC_CheckPredicate, 31, // 11176: check predicate 31 |
| 8454 | OPC_CheckField, 16, 1, 0, // 11178: check Inst[16] == 0x0 |
| 8455 | OPC_CheckField, 6, 1, 1, // 11182: check Inst[6] == 0x1 |
| 8456 | OPC_CheckField, 0, 1, 0, // 11186: check Inst[0] == 0x0 |
| 8457 | OPC_Decode, 182, 9, 179, 1, // 11190: decode to MVE_VHSUBs8 using decoder 179 |
| 8458 | // 11190: } |
| 8459 | 15, 0, // 11195: case 0xf: { |
| 8460 | OPC_CheckPredicate, 31, // 11197: check predicate 31 |
| 8461 | OPC_CheckField, 16, 1, 0, // 11199: check Inst[16] == 0x0 |
| 8462 | OPC_CheckField, 6, 1, 1, // 11203: check Inst[6] == 0x1 |
| 8463 | OPC_CheckField, 0, 1, 0, // 11207: check Inst[0] == 0x0 |
| 8464 | OPC_Decode, 185, 9, 179, 1, // 11211: decode to MVE_VHSUBu8 using decoder 179 |
| 8465 | // 11211: } |
| 8466 | // 11211: } // switch Inst[31:28] |
| 8467 | // 11211: } |
| 8468 | 1, 0, // 11216: case 0x1: { |
| 8469 | OPC_SwitchField, 28, 4, // 11218: switch Inst[31:28] { |
| 8470 | 14, 19, // 11221: case 0xe: { |
| 8471 | OPC_CheckPredicate, 31, // 11223: check predicate 31 |
| 8472 | OPC_CheckField, 16, 1, 0, // 11225: check Inst[16] == 0x0 |
| 8473 | OPC_CheckField, 6, 1, 1, // 11229: check Inst[6] == 0x1 |
| 8474 | OPC_CheckField, 0, 1, 0, // 11233: check Inst[0] == 0x0 |
| 8475 | OPC_Decode, 245, 12, 179, 1, // 11237: decode to MVE_VQSUBs8 using decoder 179 |
| 8476 | // 11237: } |
| 8477 | 15, 0, // 11242: case 0xf: { |
| 8478 | OPC_CheckPredicate, 31, // 11244: check predicate 31 |
| 8479 | OPC_CheckField, 16, 1, 0, // 11246: check Inst[16] == 0x0 |
| 8480 | OPC_CheckField, 6, 1, 1, // 11250: check Inst[6] == 0x1 |
| 8481 | OPC_CheckField, 0, 1, 0, // 11254: check Inst[0] == 0x0 |
| 8482 | OPC_Decode, 248, 12, 179, 1, // 11258: decode to MVE_VQSUBu8 using decoder 179 |
| 8483 | // 11258: } |
| 8484 | // 11258: } // switch Inst[31:28] |
| 8485 | // 11258: } |
| 8486 | // 11258: } // switch Inst[4] |
| 8487 | // 11258: } |
| 8488 | 1, 97, // 11263: case 0x1: { |
| 8489 | OPC_SwitchField, 4, 1, // 11265: switch Inst[4] { |
| 8490 | 0, 45, // 11268: case 0x0: { |
| 8491 | OPC_SwitchField, 28, 4, // 11270: switch Inst[31:28] { |
| 8492 | 14, 19, // 11273: case 0xe: { |
| 8493 | OPC_CheckPredicate, 31, // 11275: check predicate 31 |
| 8494 | OPC_CheckField, 16, 1, 0, // 11277: check Inst[16] == 0x0 |
| 8495 | OPC_CheckField, 6, 1, 1, // 11281: check Inst[6] == 0x1 |
| 8496 | OPC_CheckField, 0, 1, 0, // 11285: check Inst[0] == 0x0 |
| 8497 | OPC_Decode, 180, 9, 179, 1, // 11289: decode to MVE_VHSUBs16 using decoder 179 |
| 8498 | // 11289: } |
| 8499 | 15, 0, // 11294: case 0xf: { |
| 8500 | OPC_CheckPredicate, 31, // 11296: check predicate 31 |
| 8501 | OPC_CheckField, 16, 1, 0, // 11298: check Inst[16] == 0x0 |
| 8502 | OPC_CheckField, 6, 1, 1, // 11302: check Inst[6] == 0x1 |
| 8503 | OPC_CheckField, 0, 1, 0, // 11306: check Inst[0] == 0x0 |
| 8504 | OPC_Decode, 183, 9, 179, 1, // 11310: decode to MVE_VHSUBu16 using decoder 179 |
| 8505 | // 11310: } |
| 8506 | // 11310: } // switch Inst[31:28] |
| 8507 | // 11310: } |
| 8508 | 1, 0, // 11315: case 0x1: { |
| 8509 | OPC_SwitchField, 28, 4, // 11317: switch Inst[31:28] { |
| 8510 | 14, 19, // 11320: case 0xe: { |
| 8511 | OPC_CheckPredicate, 31, // 11322: check predicate 31 |
| 8512 | OPC_CheckField, 16, 1, 0, // 11324: check Inst[16] == 0x0 |
| 8513 | OPC_CheckField, 6, 1, 1, // 11328: check Inst[6] == 0x1 |
| 8514 | OPC_CheckField, 0, 1, 0, // 11332: check Inst[0] == 0x0 |
| 8515 | OPC_Decode, 243, 12, 179, 1, // 11336: decode to MVE_VQSUBs16 using decoder 179 |
| 8516 | // 11336: } |
| 8517 | 15, 0, // 11341: case 0xf: { |
| 8518 | OPC_CheckPredicate, 31, // 11343: check predicate 31 |
| 8519 | OPC_CheckField, 16, 1, 0, // 11345: check Inst[16] == 0x0 |
| 8520 | OPC_CheckField, 6, 1, 1, // 11349: check Inst[6] == 0x1 |
| 8521 | OPC_CheckField, 0, 1, 0, // 11353: check Inst[0] == 0x0 |
| 8522 | OPC_Decode, 246, 12, 179, 1, // 11357: decode to MVE_VQSUBu16 using decoder 179 |
| 8523 | // 11357: } |
| 8524 | // 11357: } // switch Inst[31:28] |
| 8525 | // 11357: } |
| 8526 | // 11357: } // switch Inst[4] |
| 8527 | // 11357: } |
| 8528 | 2, 0, // 11362: case 0x2: { |
| 8529 | OPC_SwitchField, 4, 1, // 11364: switch Inst[4] { |
| 8530 | 0, 45, // 11367: case 0x0: { |
| 8531 | OPC_SwitchField, 28, 4, // 11369: switch Inst[31:28] { |
| 8532 | 14, 19, // 11372: case 0xe: { |
| 8533 | OPC_CheckPredicate, 31, // 11374: check predicate 31 |
| 8534 | OPC_CheckField, 16, 1, 0, // 11376: check Inst[16] == 0x0 |
| 8535 | OPC_CheckField, 6, 1, 1, // 11380: check Inst[6] == 0x1 |
| 8536 | OPC_CheckField, 0, 1, 0, // 11384: check Inst[0] == 0x0 |
| 8537 | OPC_Decode, 181, 9, 179, 1, // 11388: decode to MVE_VHSUBs32 using decoder 179 |
| 8538 | // 11388: } |
| 8539 | 15, 0, // 11393: case 0xf: { |
| 8540 | OPC_CheckPredicate, 31, // 11395: check predicate 31 |
| 8541 | OPC_CheckField, 16, 1, 0, // 11397: check Inst[16] == 0x0 |
| 8542 | OPC_CheckField, 6, 1, 1, // 11401: check Inst[6] == 0x1 |
| 8543 | OPC_CheckField, 0, 1, 0, // 11405: check Inst[0] == 0x0 |
| 8544 | OPC_Decode, 184, 9, 179, 1, // 11409: decode to MVE_VHSUBu32 using decoder 179 |
| 8545 | // 11409: } |
| 8546 | // 11409: } // switch Inst[31:28] |
| 8547 | // 11409: } |
| 8548 | 1, 0, // 11414: case 0x1: { |
| 8549 | OPC_SwitchField, 28, 4, // 11416: switch Inst[31:28] { |
| 8550 | 14, 19, // 11419: case 0xe: { |
| 8551 | OPC_CheckPredicate, 31, // 11421: check predicate 31 |
| 8552 | OPC_CheckField, 16, 1, 0, // 11423: check Inst[16] == 0x0 |
| 8553 | OPC_CheckField, 6, 1, 1, // 11427: check Inst[6] == 0x1 |
| 8554 | OPC_CheckField, 0, 1, 0, // 11431: check Inst[0] == 0x0 |
| 8555 | OPC_Decode, 244, 12, 179, 1, // 11435: decode to MVE_VQSUBs32 using decoder 179 |
| 8556 | // 11435: } |
| 8557 | 15, 0, // 11440: case 0xf: { |
| 8558 | OPC_CheckPredicate, 31, // 11442: check predicate 31 |
| 8559 | OPC_CheckField, 16, 1, 0, // 11444: check Inst[16] == 0x0 |
| 8560 | OPC_CheckField, 6, 1, 1, // 11448: check Inst[6] == 0x1 |
| 8561 | OPC_CheckField, 0, 1, 0, // 11452: check Inst[0] == 0x0 |
| 8562 | OPC_Decode, 247, 12, 179, 1, // 11456: decode to MVE_VQSUBu32 using decoder 179 |
| 8563 | // 11456: } |
| 8564 | // 11456: } // switch Inst[31:28] |
| 8565 | // 11456: } |
| 8566 | // 11456: } // switch Inst[4] |
| 8567 | // 11456: } |
| 8568 | // 11456: } // switch Inst[21:20] |
| 8569 | // 11456: } |
| 8570 | 4, 172, 2, // 11461: case 0x4: { |
| 8571 | OPC_SwitchField, 20, 2, // 11464: switch Inst[21:20] { |
| 8572 | 0, 97, // 11467: case 0x0: { |
| 8573 | OPC_SwitchField, 4, 1, // 11469: switch Inst[4] { |
| 8574 | 0, 45, // 11472: case 0x0: { |
| 8575 | OPC_SwitchField, 28, 4, // 11474: switch Inst[31:28] { |
| 8576 | 14, 19, // 11477: case 0xe: { |
| 8577 | OPC_CheckPredicate, 31, // 11479: check predicate 31 |
| 8578 | OPC_CheckField, 16, 1, 0, // 11481: check Inst[16] == 0x0 |
| 8579 | OPC_CheckField, 6, 1, 1, // 11485: check Inst[6] == 0x1 |
| 8580 | OPC_CheckField, 0, 1, 0, // 11489: check Inst[0] == 0x0 |
| 8581 | OPC_Decode, 204, 13, 225, 1, // 11493: decode to MVE_VSHL_by_vecs8 using decoder 225 |
| 8582 | // 11493: } |
| 8583 | 15, 0, // 11498: case 0xf: { |
| 8584 | OPC_CheckPredicate, 31, // 11500: check predicate 31 |
| 8585 | OPC_CheckField, 16, 1, 0, // 11502: check Inst[16] == 0x0 |
| 8586 | OPC_CheckField, 6, 1, 1, // 11506: check Inst[6] == 0x1 |
| 8587 | OPC_CheckField, 0, 1, 0, // 11510: check Inst[0] == 0x0 |
| 8588 | OPC_Decode, 207, 13, 225, 1, // 11514: decode to MVE_VSHL_by_vecu8 using decoder 225 |
| 8589 | // 11514: } |
| 8590 | // 11514: } // switch Inst[31:28] |
| 8591 | // 11514: } |
| 8592 | 1, 0, // 11519: case 0x1: { |
| 8593 | OPC_SwitchField, 28, 4, // 11521: switch Inst[31:28] { |
| 8594 | 14, 19, // 11524: case 0xe: { |
| 8595 | OPC_CheckPredicate, 31, // 11526: check predicate 31 |
| 8596 | OPC_CheckField, 16, 1, 0, // 11528: check Inst[16] == 0x0 |
| 8597 | OPC_CheckField, 6, 1, 1, // 11532: check Inst[6] == 0x1 |
| 8598 | OPC_CheckField, 0, 1, 0, // 11536: check Inst[0] == 0x0 |
| 8599 | OPC_Decode, 209, 12, 225, 1, // 11540: decode to MVE_VQSHL_by_vecs8 using decoder 225 |
| 8600 | // 11540: } |
| 8601 | 15, 0, // 11545: case 0xf: { |
| 8602 | OPC_CheckPredicate, 31, // 11547: check predicate 31 |
| 8603 | OPC_CheckField, 16, 1, 0, // 11549: check Inst[16] == 0x0 |
| 8604 | OPC_CheckField, 6, 1, 1, // 11553: check Inst[6] == 0x1 |
| 8605 | OPC_CheckField, 0, 1, 0, // 11557: check Inst[0] == 0x0 |
| 8606 | OPC_Decode, 212, 12, 225, 1, // 11561: decode to MVE_VQSHL_by_vecu8 using decoder 225 |
| 8607 | // 11561: } |
| 8608 | // 11561: } // switch Inst[31:28] |
| 8609 | // 11561: } |
| 8610 | // 11561: } // switch Inst[4] |
| 8611 | // 11561: } |
| 8612 | 1, 97, // 11566: case 0x1: { |
| 8613 | OPC_SwitchField, 4, 1, // 11568: switch Inst[4] { |
| 8614 | 0, 45, // 11571: case 0x0: { |
| 8615 | OPC_SwitchField, 28, 4, // 11573: switch Inst[31:28] { |
| 8616 | 14, 19, // 11576: case 0xe: { |
| 8617 | OPC_CheckPredicate, 31, // 11578: check predicate 31 |
| 8618 | OPC_CheckField, 16, 1, 0, // 11580: check Inst[16] == 0x0 |
| 8619 | OPC_CheckField, 6, 1, 1, // 11584: check Inst[6] == 0x1 |
| 8620 | OPC_CheckField, 0, 1, 0, // 11588: check Inst[0] == 0x0 |
| 8621 | OPC_Decode, 202, 13, 225, 1, // 11592: decode to MVE_VSHL_by_vecs16 using decoder 225 |
| 8622 | // 11592: } |
| 8623 | 15, 0, // 11597: case 0xf: { |
| 8624 | OPC_CheckPredicate, 31, // 11599: check predicate 31 |
| 8625 | OPC_CheckField, 16, 1, 0, // 11601: check Inst[16] == 0x0 |
| 8626 | OPC_CheckField, 6, 1, 1, // 11605: check Inst[6] == 0x1 |
| 8627 | OPC_CheckField, 0, 1, 0, // 11609: check Inst[0] == 0x0 |
| 8628 | OPC_Decode, 205, 13, 225, 1, // 11613: decode to MVE_VSHL_by_vecu16 using decoder 225 |
| 8629 | // 11613: } |
| 8630 | // 11613: } // switch Inst[31:28] |
| 8631 | // 11613: } |
| 8632 | 1, 0, // 11618: case 0x1: { |
| 8633 | OPC_SwitchField, 28, 4, // 11620: switch Inst[31:28] { |
| 8634 | 14, 19, // 11623: case 0xe: { |
| 8635 | OPC_CheckPredicate, 31, // 11625: check predicate 31 |
| 8636 | OPC_CheckField, 16, 1, 0, // 11627: check Inst[16] == 0x0 |
| 8637 | OPC_CheckField, 6, 1, 1, // 11631: check Inst[6] == 0x1 |
| 8638 | OPC_CheckField, 0, 1, 0, // 11635: check Inst[0] == 0x0 |
| 8639 | OPC_Decode, 207, 12, 225, 1, // 11639: decode to MVE_VQSHL_by_vecs16 using decoder 225 |
| 8640 | // 11639: } |
| 8641 | 15, 0, // 11644: case 0xf: { |
| 8642 | OPC_CheckPredicate, 31, // 11646: check predicate 31 |
| 8643 | OPC_CheckField, 16, 1, 0, // 11648: check Inst[16] == 0x0 |
| 8644 | OPC_CheckField, 6, 1, 1, // 11652: check Inst[6] == 0x1 |
| 8645 | OPC_CheckField, 0, 1, 0, // 11656: check Inst[0] == 0x0 |
| 8646 | OPC_Decode, 210, 12, 225, 1, // 11660: decode to MVE_VQSHL_by_vecu16 using decoder 225 |
| 8647 | // 11660: } |
| 8648 | // 11660: } // switch Inst[31:28] |
| 8649 | // 11660: } |
| 8650 | // 11660: } // switch Inst[4] |
| 8651 | // 11660: } |
| 8652 | 2, 0, // 11665: case 0x2: { |
| 8653 | OPC_SwitchField, 4, 1, // 11667: switch Inst[4] { |
| 8654 | 0, 45, // 11670: case 0x0: { |
| 8655 | OPC_SwitchField, 28, 4, // 11672: switch Inst[31:28] { |
| 8656 | 14, 19, // 11675: case 0xe: { |
| 8657 | OPC_CheckPredicate, 31, // 11677: check predicate 31 |
| 8658 | OPC_CheckField, 16, 1, 0, // 11679: check Inst[16] == 0x0 |
| 8659 | OPC_CheckField, 6, 1, 1, // 11683: check Inst[6] == 0x1 |
| 8660 | OPC_CheckField, 0, 1, 0, // 11687: check Inst[0] == 0x0 |
| 8661 | OPC_Decode, 203, 13, 225, 1, // 11691: decode to MVE_VSHL_by_vecs32 using decoder 225 |
| 8662 | // 11691: } |
| 8663 | 15, 0, // 11696: case 0xf: { |
| 8664 | OPC_CheckPredicate, 31, // 11698: check predicate 31 |
| 8665 | OPC_CheckField, 16, 1, 0, // 11700: check Inst[16] == 0x0 |
| 8666 | OPC_CheckField, 6, 1, 1, // 11704: check Inst[6] == 0x1 |
| 8667 | OPC_CheckField, 0, 1, 0, // 11708: check Inst[0] == 0x0 |
| 8668 | OPC_Decode, 206, 13, 225, 1, // 11712: decode to MVE_VSHL_by_vecu32 using decoder 225 |
| 8669 | // 11712: } |
| 8670 | // 11712: } // switch Inst[31:28] |
| 8671 | // 11712: } |
| 8672 | 1, 0, // 11717: case 0x1: { |
| 8673 | OPC_SwitchField, 28, 4, // 11719: switch Inst[31:28] { |
| 8674 | 14, 19, // 11722: case 0xe: { |
| 8675 | OPC_CheckPredicate, 31, // 11724: check predicate 31 |
| 8676 | OPC_CheckField, 16, 1, 0, // 11726: check Inst[16] == 0x0 |
| 8677 | OPC_CheckField, 6, 1, 1, // 11730: check Inst[6] == 0x1 |
| 8678 | OPC_CheckField, 0, 1, 0, // 11734: check Inst[0] == 0x0 |
| 8679 | OPC_Decode, 208, 12, 225, 1, // 11738: decode to MVE_VQSHL_by_vecs32 using decoder 225 |
| 8680 | // 11738: } |
| 8681 | 15, 0, // 11743: case 0xf: { |
| 8682 | OPC_CheckPredicate, 31, // 11745: check predicate 31 |
| 8683 | OPC_CheckField, 16, 1, 0, // 11747: check Inst[16] == 0x0 |
| 8684 | OPC_CheckField, 6, 1, 1, // 11751: check Inst[6] == 0x1 |
| 8685 | OPC_CheckField, 0, 1, 0, // 11755: check Inst[0] == 0x0 |
| 8686 | OPC_Decode, 211, 12, 225, 1, // 11759: decode to MVE_VQSHL_by_vecu32 using decoder 225 |
| 8687 | // 11759: } |
| 8688 | // 11759: } // switch Inst[31:28] |
| 8689 | // 11759: } |
| 8690 | // 11759: } // switch Inst[4] |
| 8691 | // 11759: } |
| 8692 | // 11759: } // switch Inst[21:20] |
| 8693 | // 11759: } |
| 8694 | 5, 172, 2, // 11764: case 0x5: { |
| 8695 | OPC_SwitchField, 20, 2, // 11767: switch Inst[21:20] { |
| 8696 | 0, 97, // 11770: case 0x0: { |
| 8697 | OPC_SwitchField, 4, 1, // 11772: switch Inst[4] { |
| 8698 | 0, 45, // 11775: case 0x0: { |
| 8699 | OPC_SwitchField, 28, 4, // 11777: switch Inst[31:28] { |
| 8700 | 14, 19, // 11780: case 0xe: { |
| 8701 | OPC_CheckPredicate, 31, // 11782: check predicate 31 |
| 8702 | OPC_CheckField, 16, 1, 0, // 11784: check Inst[16] == 0x0 |
| 8703 | OPC_CheckField, 6, 1, 1, // 11788: check Inst[6] == 0x1 |
| 8704 | OPC_CheckField, 0, 1, 0, // 11792: check Inst[0] == 0x0 |
| 8705 | OPC_Decode, 163, 13, 225, 1, // 11796: decode to MVE_VRSHL_by_vecs8 using decoder 225 |
| 8706 | // 11796: } |
| 8707 | 15, 0, // 11801: case 0xf: { |
| 8708 | OPC_CheckPredicate, 31, // 11803: check predicate 31 |
| 8709 | OPC_CheckField, 16, 1, 0, // 11805: check Inst[16] == 0x0 |
| 8710 | OPC_CheckField, 6, 1, 1, // 11809: check Inst[6] == 0x1 |
| 8711 | OPC_CheckField, 0, 1, 0, // 11813: check Inst[0] == 0x0 |
| 8712 | OPC_Decode, 166, 13, 225, 1, // 11817: decode to MVE_VRSHL_by_vecu8 using decoder 225 |
| 8713 | // 11817: } |
| 8714 | // 11817: } // switch Inst[31:28] |
| 8715 | // 11817: } |
| 8716 | 1, 0, // 11822: case 0x1: { |
| 8717 | OPC_SwitchField, 28, 4, // 11824: switch Inst[31:28] { |
| 8718 | 14, 19, // 11827: case 0xe: { |
| 8719 | OPC_CheckPredicate, 31, // 11829: check predicate 31 |
| 8720 | OPC_CheckField, 16, 1, 0, // 11831: check Inst[16] == 0x0 |
| 8721 | OPC_CheckField, 6, 1, 1, // 11835: check Inst[6] == 0x1 |
| 8722 | OPC_CheckField, 0, 1, 0, // 11839: check Inst[0] == 0x0 |
| 8723 | OPC_Decode, 182, 12, 225, 1, // 11843: decode to MVE_VQRSHL_by_vecs8 using decoder 225 |
| 8724 | // 11843: } |
| 8725 | 15, 0, // 11848: case 0xf: { |
| 8726 | OPC_CheckPredicate, 31, // 11850: check predicate 31 |
| 8727 | OPC_CheckField, 16, 1, 0, // 11852: check Inst[16] == 0x0 |
| 8728 | OPC_CheckField, 6, 1, 1, // 11856: check Inst[6] == 0x1 |
| 8729 | OPC_CheckField, 0, 1, 0, // 11860: check Inst[0] == 0x0 |
| 8730 | OPC_Decode, 185, 12, 225, 1, // 11864: decode to MVE_VQRSHL_by_vecu8 using decoder 225 |
| 8731 | // 11864: } |
| 8732 | // 11864: } // switch Inst[31:28] |
| 8733 | // 11864: } |
| 8734 | // 11864: } // switch Inst[4] |
| 8735 | // 11864: } |
| 8736 | 1, 97, // 11869: case 0x1: { |
| 8737 | OPC_SwitchField, 4, 1, // 11871: switch Inst[4] { |
| 8738 | 0, 45, // 11874: case 0x0: { |
| 8739 | OPC_SwitchField, 28, 4, // 11876: switch Inst[31:28] { |
| 8740 | 14, 19, // 11879: case 0xe: { |
| 8741 | OPC_CheckPredicate, 31, // 11881: check predicate 31 |
| 8742 | OPC_CheckField, 16, 1, 0, // 11883: check Inst[16] == 0x0 |
| 8743 | OPC_CheckField, 6, 1, 1, // 11887: check Inst[6] == 0x1 |
| 8744 | OPC_CheckField, 0, 1, 0, // 11891: check Inst[0] == 0x0 |
| 8745 | OPC_Decode, 161, 13, 225, 1, // 11895: decode to MVE_VRSHL_by_vecs16 using decoder 225 |
| 8746 | // 11895: } |
| 8747 | 15, 0, // 11900: case 0xf: { |
| 8748 | OPC_CheckPredicate, 31, // 11902: check predicate 31 |
| 8749 | OPC_CheckField, 16, 1, 0, // 11904: check Inst[16] == 0x0 |
| 8750 | OPC_CheckField, 6, 1, 1, // 11908: check Inst[6] == 0x1 |
| 8751 | OPC_CheckField, 0, 1, 0, // 11912: check Inst[0] == 0x0 |
| 8752 | OPC_Decode, 164, 13, 225, 1, // 11916: decode to MVE_VRSHL_by_vecu16 using decoder 225 |
| 8753 | // 11916: } |
| 8754 | // 11916: } // switch Inst[31:28] |
| 8755 | // 11916: } |
| 8756 | 1, 0, // 11921: case 0x1: { |
| 8757 | OPC_SwitchField, 28, 4, // 11923: switch Inst[31:28] { |
| 8758 | 14, 19, // 11926: case 0xe: { |
| 8759 | OPC_CheckPredicate, 31, // 11928: check predicate 31 |
| 8760 | OPC_CheckField, 16, 1, 0, // 11930: check Inst[16] == 0x0 |
| 8761 | OPC_CheckField, 6, 1, 1, // 11934: check Inst[6] == 0x1 |
| 8762 | OPC_CheckField, 0, 1, 0, // 11938: check Inst[0] == 0x0 |
| 8763 | OPC_Decode, 180, 12, 225, 1, // 11942: decode to MVE_VQRSHL_by_vecs16 using decoder 225 |
| 8764 | // 11942: } |
| 8765 | 15, 0, // 11947: case 0xf: { |
| 8766 | OPC_CheckPredicate, 31, // 11949: check predicate 31 |
| 8767 | OPC_CheckField, 16, 1, 0, // 11951: check Inst[16] == 0x0 |
| 8768 | OPC_CheckField, 6, 1, 1, // 11955: check Inst[6] == 0x1 |
| 8769 | OPC_CheckField, 0, 1, 0, // 11959: check Inst[0] == 0x0 |
| 8770 | OPC_Decode, 183, 12, 225, 1, // 11963: decode to MVE_VQRSHL_by_vecu16 using decoder 225 |
| 8771 | // 11963: } |
| 8772 | // 11963: } // switch Inst[31:28] |
| 8773 | // 11963: } |
| 8774 | // 11963: } // switch Inst[4] |
| 8775 | // 11963: } |
| 8776 | 2, 0, // 11968: case 0x2: { |
| 8777 | OPC_SwitchField, 4, 1, // 11970: switch Inst[4] { |
| 8778 | 0, 45, // 11973: case 0x0: { |
| 8779 | OPC_SwitchField, 28, 4, // 11975: switch Inst[31:28] { |
| 8780 | 14, 19, // 11978: case 0xe: { |
| 8781 | OPC_CheckPredicate, 31, // 11980: check predicate 31 |
| 8782 | OPC_CheckField, 16, 1, 0, // 11982: check Inst[16] == 0x0 |
| 8783 | OPC_CheckField, 6, 1, 1, // 11986: check Inst[6] == 0x1 |
| 8784 | OPC_CheckField, 0, 1, 0, // 11990: check Inst[0] == 0x0 |
| 8785 | OPC_Decode, 162, 13, 225, 1, // 11994: decode to MVE_VRSHL_by_vecs32 using decoder 225 |
| 8786 | // 11994: } |
| 8787 | 15, 0, // 11999: case 0xf: { |
| 8788 | OPC_CheckPredicate, 31, // 12001: check predicate 31 |
| 8789 | OPC_CheckField, 16, 1, 0, // 12003: check Inst[16] == 0x0 |
| 8790 | OPC_CheckField, 6, 1, 1, // 12007: check Inst[6] == 0x1 |
| 8791 | OPC_CheckField, 0, 1, 0, // 12011: check Inst[0] == 0x0 |
| 8792 | OPC_Decode, 165, 13, 225, 1, // 12015: decode to MVE_VRSHL_by_vecu32 using decoder 225 |
| 8793 | // 12015: } |
| 8794 | // 12015: } // switch Inst[31:28] |
| 8795 | // 12015: } |
| 8796 | 1, 0, // 12020: case 0x1: { |
| 8797 | OPC_SwitchField, 28, 4, // 12022: switch Inst[31:28] { |
| 8798 | 14, 19, // 12025: case 0xe: { |
| 8799 | OPC_CheckPredicate, 31, // 12027: check predicate 31 |
| 8800 | OPC_CheckField, 16, 1, 0, // 12029: check Inst[16] == 0x0 |
| 8801 | OPC_CheckField, 6, 1, 1, // 12033: check Inst[6] == 0x1 |
| 8802 | OPC_CheckField, 0, 1, 0, // 12037: check Inst[0] == 0x0 |
| 8803 | OPC_Decode, 181, 12, 225, 1, // 12041: decode to MVE_VQRSHL_by_vecs32 using decoder 225 |
| 8804 | // 12041: } |
| 8805 | 15, 0, // 12046: case 0xf: { |
| 8806 | OPC_CheckPredicate, 31, // 12048: check predicate 31 |
| 8807 | OPC_CheckField, 16, 1, 0, // 12050: check Inst[16] == 0x0 |
| 8808 | OPC_CheckField, 6, 1, 1, // 12054: check Inst[6] == 0x1 |
| 8809 | OPC_CheckField, 0, 1, 0, // 12058: check Inst[0] == 0x0 |
| 8810 | OPC_Decode, 184, 12, 225, 1, // 12062: decode to MVE_VQRSHL_by_vecu32 using decoder 225 |
| 8811 | // 12062: } |
| 8812 | // 12062: } // switch Inst[31:28] |
| 8813 | // 12062: } |
| 8814 | // 12062: } // switch Inst[4] |
| 8815 | // 12062: } |
| 8816 | // 12062: } // switch Inst[21:20] |
| 8817 | // 12062: } |
| 8818 | 6, 172, 2, // 12067: case 0x6: { |
| 8819 | OPC_SwitchField, 20, 2, // 12070: switch Inst[21:20] { |
| 8820 | 0, 97, // 12073: case 0x0: { |
| 8821 | OPC_SwitchField, 4, 1, // 12075: switch Inst[4] { |
| 8822 | 0, 45, // 12078: case 0x0: { |
| 8823 | OPC_SwitchField, 28, 4, // 12080: switch Inst[31:28] { |
| 8824 | 14, 19, // 12083: case 0xe: { |
| 8825 | OPC_CheckPredicate, 31, // 12085: check predicate 31 |
| 8826 | OPC_CheckField, 16, 1, 0, // 12087: check Inst[16] == 0x0 |
| 8827 | OPC_CheckField, 6, 1, 1, // 12091: check Inst[6] == 0x1 |
| 8828 | OPC_CheckField, 0, 1, 0, // 12095: check Inst[0] == 0x0 |
| 8829 | OPC_Decode, 168, 10, 179, 1, // 12099: decode to MVE_VMAXs8 using decoder 179 |
| 8830 | // 12099: } |
| 8831 | 15, 0, // 12104: case 0xf: { |
| 8832 | OPC_CheckPredicate, 31, // 12106: check predicate 31 |
| 8833 | OPC_CheckField, 16, 1, 0, // 12108: check Inst[16] == 0x0 |
| 8834 | OPC_CheckField, 6, 1, 1, // 12112: check Inst[6] == 0x1 |
| 8835 | OPC_CheckField, 0, 1, 0, // 12116: check Inst[0] == 0x0 |
| 8836 | OPC_Decode, 171, 10, 179, 1, // 12120: decode to MVE_VMAXu8 using decoder 179 |
| 8837 | // 12120: } |
| 8838 | // 12120: } // switch Inst[31:28] |
| 8839 | // 12120: } |
| 8840 | 1, 0, // 12125: case 0x1: { |
| 8841 | OPC_SwitchField, 28, 4, // 12127: switch Inst[31:28] { |
| 8842 | 14, 19, // 12130: case 0xe: { |
| 8843 | OPC_CheckPredicate, 31, // 12132: check predicate 31 |
| 8844 | OPC_CheckField, 16, 1, 0, // 12134: check Inst[16] == 0x0 |
| 8845 | OPC_CheckField, 6, 1, 1, // 12138: check Inst[6] == 0x1 |
| 8846 | OPC_CheckField, 0, 1, 0, // 12142: check Inst[0] == 0x0 |
| 8847 | OPC_Decode, 194, 10, 179, 1, // 12146: decode to MVE_VMINs8 using decoder 179 |
| 8848 | // 12146: } |
| 8849 | 15, 0, // 12151: case 0xf: { |
| 8850 | OPC_CheckPredicate, 31, // 12153: check predicate 31 |
| 8851 | OPC_CheckField, 16, 1, 0, // 12155: check Inst[16] == 0x0 |
| 8852 | OPC_CheckField, 6, 1, 1, // 12159: check Inst[6] == 0x1 |
| 8853 | OPC_CheckField, 0, 1, 0, // 12163: check Inst[0] == 0x0 |
| 8854 | OPC_Decode, 197, 10, 179, 1, // 12167: decode to MVE_VMINu8 using decoder 179 |
| 8855 | // 12167: } |
| 8856 | // 12167: } // switch Inst[31:28] |
| 8857 | // 12167: } |
| 8858 | // 12167: } // switch Inst[4] |
| 8859 | // 12167: } |
| 8860 | 1, 97, // 12172: case 0x1: { |
| 8861 | OPC_SwitchField, 4, 1, // 12174: switch Inst[4] { |
| 8862 | 0, 45, // 12177: case 0x0: { |
| 8863 | OPC_SwitchField, 28, 4, // 12179: switch Inst[31:28] { |
| 8864 | 14, 19, // 12182: case 0xe: { |
| 8865 | OPC_CheckPredicate, 31, // 12184: check predicate 31 |
| 8866 | OPC_CheckField, 16, 1, 0, // 12186: check Inst[16] == 0x0 |
| 8867 | OPC_CheckField, 6, 1, 1, // 12190: check Inst[6] == 0x1 |
| 8868 | OPC_CheckField, 0, 1, 0, // 12194: check Inst[0] == 0x0 |
| 8869 | OPC_Decode, 166, 10, 179, 1, // 12198: decode to MVE_VMAXs16 using decoder 179 |
| 8870 | // 12198: } |
| 8871 | 15, 0, // 12203: case 0xf: { |
| 8872 | OPC_CheckPredicate, 31, // 12205: check predicate 31 |
| 8873 | OPC_CheckField, 16, 1, 0, // 12207: check Inst[16] == 0x0 |
| 8874 | OPC_CheckField, 6, 1, 1, // 12211: check Inst[6] == 0x1 |
| 8875 | OPC_CheckField, 0, 1, 0, // 12215: check Inst[0] == 0x0 |
| 8876 | OPC_Decode, 169, 10, 179, 1, // 12219: decode to MVE_VMAXu16 using decoder 179 |
| 8877 | // 12219: } |
| 8878 | // 12219: } // switch Inst[31:28] |
| 8879 | // 12219: } |
| 8880 | 1, 0, // 12224: case 0x1: { |
| 8881 | OPC_SwitchField, 28, 4, // 12226: switch Inst[31:28] { |
| 8882 | 14, 19, // 12229: case 0xe: { |
| 8883 | OPC_CheckPredicate, 31, // 12231: check predicate 31 |
| 8884 | OPC_CheckField, 16, 1, 0, // 12233: check Inst[16] == 0x0 |
| 8885 | OPC_CheckField, 6, 1, 1, // 12237: check Inst[6] == 0x1 |
| 8886 | OPC_CheckField, 0, 1, 0, // 12241: check Inst[0] == 0x0 |
| 8887 | OPC_Decode, 192, 10, 179, 1, // 12245: decode to MVE_VMINs16 using decoder 179 |
| 8888 | // 12245: } |
| 8889 | 15, 0, // 12250: case 0xf: { |
| 8890 | OPC_CheckPredicate, 31, // 12252: check predicate 31 |
| 8891 | OPC_CheckField, 16, 1, 0, // 12254: check Inst[16] == 0x0 |
| 8892 | OPC_CheckField, 6, 1, 1, // 12258: check Inst[6] == 0x1 |
| 8893 | OPC_CheckField, 0, 1, 0, // 12262: check Inst[0] == 0x0 |
| 8894 | OPC_Decode, 195, 10, 179, 1, // 12266: decode to MVE_VMINu16 using decoder 179 |
| 8895 | // 12266: } |
| 8896 | // 12266: } // switch Inst[31:28] |
| 8897 | // 12266: } |
| 8898 | // 12266: } // switch Inst[4] |
| 8899 | // 12266: } |
| 8900 | 2, 0, // 12271: case 0x2: { |
| 8901 | OPC_SwitchField, 4, 1, // 12273: switch Inst[4] { |
| 8902 | 0, 45, // 12276: case 0x0: { |
| 8903 | OPC_SwitchField, 28, 4, // 12278: switch Inst[31:28] { |
| 8904 | 14, 19, // 12281: case 0xe: { |
| 8905 | OPC_CheckPredicate, 31, // 12283: check predicate 31 |
| 8906 | OPC_CheckField, 16, 1, 0, // 12285: check Inst[16] == 0x0 |
| 8907 | OPC_CheckField, 6, 1, 1, // 12289: check Inst[6] == 0x1 |
| 8908 | OPC_CheckField, 0, 1, 0, // 12293: check Inst[0] == 0x0 |
| 8909 | OPC_Decode, 167, 10, 179, 1, // 12297: decode to MVE_VMAXs32 using decoder 179 |
| 8910 | // 12297: } |
| 8911 | 15, 0, // 12302: case 0xf: { |
| 8912 | OPC_CheckPredicate, 31, // 12304: check predicate 31 |
| 8913 | OPC_CheckField, 16, 1, 0, // 12306: check Inst[16] == 0x0 |
| 8914 | OPC_CheckField, 6, 1, 1, // 12310: check Inst[6] == 0x1 |
| 8915 | OPC_CheckField, 0, 1, 0, // 12314: check Inst[0] == 0x0 |
| 8916 | OPC_Decode, 170, 10, 179, 1, // 12318: decode to MVE_VMAXu32 using decoder 179 |
| 8917 | // 12318: } |
| 8918 | // 12318: } // switch Inst[31:28] |
| 8919 | // 12318: } |
| 8920 | 1, 0, // 12323: case 0x1: { |
| 8921 | OPC_SwitchField, 28, 4, // 12325: switch Inst[31:28] { |
| 8922 | 14, 19, // 12328: case 0xe: { |
| 8923 | OPC_CheckPredicate, 31, // 12330: check predicate 31 |
| 8924 | OPC_CheckField, 16, 1, 0, // 12332: check Inst[16] == 0x0 |
| 8925 | OPC_CheckField, 6, 1, 1, // 12336: check Inst[6] == 0x1 |
| 8926 | OPC_CheckField, 0, 1, 0, // 12340: check Inst[0] == 0x0 |
| 8927 | OPC_Decode, 193, 10, 179, 1, // 12344: decode to MVE_VMINs32 using decoder 179 |
| 8928 | // 12344: } |
| 8929 | 15, 0, // 12349: case 0xf: { |
| 8930 | OPC_CheckPredicate, 31, // 12351: check predicate 31 |
| 8931 | OPC_CheckField, 16, 1, 0, // 12353: check Inst[16] == 0x0 |
| 8932 | OPC_CheckField, 6, 1, 1, // 12357: check Inst[6] == 0x1 |
| 8933 | OPC_CheckField, 0, 1, 0, // 12361: check Inst[0] == 0x0 |
| 8934 | OPC_Decode, 196, 10, 179, 1, // 12365: decode to MVE_VMINu32 using decoder 179 |
| 8935 | // 12365: } |
| 8936 | // 12365: } // switch Inst[31:28] |
| 8937 | // 12365: } |
| 8938 | // 12365: } // switch Inst[4] |
| 8939 | // 12365: } |
| 8940 | // 12365: } // switch Inst[21:20] |
| 8941 | // 12365: } |
| 8942 | 7, 168, 1, // 12370: case 0x7: { |
| 8943 | OPC_SwitchField, 20, 2, // 12373: switch Inst[21:20] { |
| 8944 | 0, 53, // 12376: case 0x0: { |
| 8945 | OPC_SwitchField, 28, 4, // 12378: switch Inst[31:28] { |
| 8946 | 14, 23, // 12381: case 0xe: { |
| 8947 | OPC_CheckPredicate, 31, // 12383: check predicate 31 |
| 8948 | OPC_CheckField, 16, 1, 0, // 12385: check Inst[16] == 0x0 |
| 8949 | OPC_CheckField, 6, 1, 1, // 12389: check Inst[6] == 0x1 |
| 8950 | OPC_CheckField, 4, 1, 0, // 12393: check Inst[4] == 0x0 |
| 8951 | OPC_CheckField, 0, 1, 0, // 12397: check Inst[0] == 0x0 |
| 8952 | OPC_Decode, 148, 8, 179, 1, // 12401: decode to MVE_VABDs8 using decoder 179 |
| 8953 | // 12401: } |
| 8954 | 15, 0, // 12406: case 0xf: { |
| 8955 | OPC_CheckPredicate, 31, // 12408: check predicate 31 |
| 8956 | OPC_CheckField, 16, 1, 0, // 12410: check Inst[16] == 0x0 |
| 8957 | OPC_CheckField, 6, 1, 1, // 12414: check Inst[6] == 0x1 |
| 8958 | OPC_CheckField, 4, 1, 0, // 12418: check Inst[4] == 0x0 |
| 8959 | OPC_CheckField, 0, 1, 0, // 12422: check Inst[0] == 0x0 |
| 8960 | OPC_Decode, 151, 8, 179, 1, // 12426: decode to MVE_VABDu8 using decoder 179 |
| 8961 | // 12426: } |
| 8962 | // 12426: } // switch Inst[31:28] |
| 8963 | // 12426: } |
| 8964 | 1, 53, // 12431: case 0x1: { |
| 8965 | OPC_SwitchField, 28, 4, // 12433: switch Inst[31:28] { |
| 8966 | 14, 23, // 12436: case 0xe: { |
| 8967 | OPC_CheckPredicate, 31, // 12438: check predicate 31 |
| 8968 | OPC_CheckField, 16, 1, 0, // 12440: check Inst[16] == 0x0 |
| 8969 | OPC_CheckField, 6, 1, 1, // 12444: check Inst[6] == 0x1 |
| 8970 | OPC_CheckField, 4, 1, 0, // 12448: check Inst[4] == 0x0 |
| 8971 | OPC_CheckField, 0, 1, 0, // 12452: check Inst[0] == 0x0 |
| 8972 | OPC_Decode, 146, 8, 179, 1, // 12456: decode to MVE_VABDs16 using decoder 179 |
| 8973 | // 12456: } |
| 8974 | 15, 0, // 12461: case 0xf: { |
| 8975 | OPC_CheckPredicate, 31, // 12463: check predicate 31 |
| 8976 | OPC_CheckField, 16, 1, 0, // 12465: check Inst[16] == 0x0 |
| 8977 | OPC_CheckField, 6, 1, 1, // 12469: check Inst[6] == 0x1 |
| 8978 | OPC_CheckField, 4, 1, 0, // 12473: check Inst[4] == 0x0 |
| 8979 | OPC_CheckField, 0, 1, 0, // 12477: check Inst[0] == 0x0 |
| 8980 | OPC_Decode, 149, 8, 179, 1, // 12481: decode to MVE_VABDu16 using decoder 179 |
| 8981 | // 12481: } |
| 8982 | // 12481: } // switch Inst[31:28] |
| 8983 | // 12481: } |
| 8984 | 2, 0, // 12486: case 0x2: { |
| 8985 | OPC_SwitchField, 28, 4, // 12488: switch Inst[31:28] { |
| 8986 | 14, 23, // 12491: case 0xe: { |
| 8987 | OPC_CheckPredicate, 31, // 12493: check predicate 31 |
| 8988 | OPC_CheckField, 16, 1, 0, // 12495: check Inst[16] == 0x0 |
| 8989 | OPC_CheckField, 6, 1, 1, // 12499: check Inst[6] == 0x1 |
| 8990 | OPC_CheckField, 4, 1, 0, // 12503: check Inst[4] == 0x0 |
| 8991 | OPC_CheckField, 0, 1, 0, // 12507: check Inst[0] == 0x0 |
| 8992 | OPC_Decode, 147, 8, 179, 1, // 12511: decode to MVE_VABDs32 using decoder 179 |
| 8993 | // 12511: } |
| 8994 | 15, 0, // 12516: case 0xf: { |
| 8995 | OPC_CheckPredicate, 31, // 12518: check predicate 31 |
| 8996 | OPC_CheckField, 16, 1, 0, // 12520: check Inst[16] == 0x0 |
| 8997 | OPC_CheckField, 6, 1, 1, // 12524: check Inst[6] == 0x1 |
| 8998 | OPC_CheckField, 4, 1, 0, // 12528: check Inst[4] == 0x0 |
| 8999 | OPC_CheckField, 0, 1, 0, // 12532: check Inst[0] == 0x0 |
| 9000 | OPC_Decode, 150, 8, 179, 1, // 12536: decode to MVE_VABDu32 using decoder 179 |
| 9001 | // 12536: } |
| 9002 | // 12536: } // switch Inst[31:28] |
| 9003 | // 12536: } |
| 9004 | // 12536: } // switch Inst[21:20] |
| 9005 | // 12536: } |
| 9006 | 8, 168, 1, // 12541: case 0x8: { |
| 9007 | OPC_SwitchField, 20, 2, // 12544: switch Inst[21:20] { |
| 9008 | 0, 53, // 12547: case 0x0: { |
| 9009 | OPC_SwitchField, 28, 4, // 12549: switch Inst[31:28] { |
| 9010 | 14, 23, // 12552: case 0xe: { |
| 9011 | OPC_CheckPredicate, 31, // 12554: check predicate 31 |
| 9012 | OPC_CheckField, 16, 1, 0, // 12556: check Inst[16] == 0x0 |
| 9013 | OPC_CheckField, 6, 1, 1, // 12560: check Inst[6] == 0x1 |
| 9014 | OPC_CheckField, 4, 1, 0, // 12564: check Inst[4] == 0x0 |
| 9015 | OPC_CheckField, 0, 1, 0, // 12568: check Inst[0] == 0x0 |
| 9016 | OPC_Decode, 184, 8, 179, 1, // 12572: decode to MVE_VADDi8 using decoder 179 |
| 9017 | // 12572: } |
| 9018 | 15, 0, // 12577: case 0xf: { |
| 9019 | OPC_CheckPredicate, 31, // 12579: check predicate 31 |
| 9020 | OPC_CheckField, 16, 1, 0, // 12581: check Inst[16] == 0x0 |
| 9021 | OPC_CheckField, 6, 1, 1, // 12585: check Inst[6] == 0x1 |
| 9022 | OPC_CheckField, 4, 1, 0, // 12589: check Inst[4] == 0x0 |
| 9023 | OPC_CheckField, 0, 1, 0, // 12593: check Inst[0] == 0x0 |
| 9024 | OPC_Decode, 183, 14, 179, 1, // 12597: decode to MVE_VSUBi8 using decoder 179 |
| 9025 | // 12597: } |
| 9026 | // 12597: } // switch Inst[31:28] |
| 9027 | // 12597: } |
| 9028 | 1, 53, // 12602: case 0x1: { |
| 9029 | OPC_SwitchField, 28, 4, // 12604: switch Inst[31:28] { |
| 9030 | 14, 23, // 12607: case 0xe: { |
| 9031 | OPC_CheckPredicate, 31, // 12609: check predicate 31 |
| 9032 | OPC_CheckField, 16, 1, 0, // 12611: check Inst[16] == 0x0 |
| 9033 | OPC_CheckField, 6, 1, 1, // 12615: check Inst[6] == 0x1 |
| 9034 | OPC_CheckField, 4, 1, 0, // 12619: check Inst[4] == 0x0 |
| 9035 | OPC_CheckField, 0, 1, 0, // 12623: check Inst[0] == 0x0 |
| 9036 | OPC_Decode, 182, 8, 179, 1, // 12627: decode to MVE_VADDi16 using decoder 179 |
| 9037 | // 12627: } |
| 9038 | 15, 0, // 12632: case 0xf: { |
| 9039 | OPC_CheckPredicate, 31, // 12634: check predicate 31 |
| 9040 | OPC_CheckField, 16, 1, 0, // 12636: check Inst[16] == 0x0 |
| 9041 | OPC_CheckField, 6, 1, 1, // 12640: check Inst[6] == 0x1 |
| 9042 | OPC_CheckField, 4, 1, 0, // 12644: check Inst[4] == 0x0 |
| 9043 | OPC_CheckField, 0, 1, 0, // 12648: check Inst[0] == 0x0 |
| 9044 | OPC_Decode, 181, 14, 179, 1, // 12652: decode to MVE_VSUBi16 using decoder 179 |
| 9045 | // 12652: } |
| 9046 | // 12652: } // switch Inst[31:28] |
| 9047 | // 12652: } |
| 9048 | 2, 0, // 12657: case 0x2: { |
| 9049 | OPC_SwitchField, 28, 4, // 12659: switch Inst[31:28] { |
| 9050 | 14, 23, // 12662: case 0xe: { |
| 9051 | OPC_CheckPredicate, 31, // 12664: check predicate 31 |
| 9052 | OPC_CheckField, 16, 1, 0, // 12666: check Inst[16] == 0x0 |
| 9053 | OPC_CheckField, 6, 1, 1, // 12670: check Inst[6] == 0x1 |
| 9054 | OPC_CheckField, 4, 1, 0, // 12674: check Inst[4] == 0x0 |
| 9055 | OPC_CheckField, 0, 1, 0, // 12678: check Inst[0] == 0x0 |
| 9056 | OPC_Decode, 183, 8, 179, 1, // 12682: decode to MVE_VADDi32 using decoder 179 |
| 9057 | // 12682: } |
| 9058 | 15, 0, // 12687: case 0xf: { |
| 9059 | OPC_CheckPredicate, 31, // 12689: check predicate 31 |
| 9060 | OPC_CheckField, 16, 1, 0, // 12691: check Inst[16] == 0x0 |
| 9061 | OPC_CheckField, 6, 1, 1, // 12695: check Inst[6] == 0x1 |
| 9062 | OPC_CheckField, 4, 1, 0, // 12699: check Inst[4] == 0x0 |
| 9063 | OPC_CheckField, 0, 1, 0, // 12703: check Inst[0] == 0x0 |
| 9064 | OPC_Decode, 182, 14, 179, 1, // 12707: decode to MVE_VSUBi32 using decoder 179 |
| 9065 | // 12707: } |
| 9066 | // 12707: } // switch Inst[31:28] |
| 9067 | // 12707: } |
| 9068 | // 12707: } // switch Inst[21:20] |
| 9069 | // 12707: } |
| 9070 | 9, 90, // 12712: case 0x9: { |
| 9071 | OPC_SwitchField, 20, 2, // 12714: switch Inst[21:20] { |
| 9072 | 0, 27, // 12717: case 0x0: { |
| 9073 | OPC_CheckPredicate, 31, // 12719: check predicate 31 |
| 9074 | OPC_CheckField, 28, 4, 14, // 12721: check Inst[31:28] == 0xe |
| 9075 | OPC_CheckField, 16, 1, 0, // 12725: check Inst[16] == 0x0 |
| 9076 | OPC_CheckField, 6, 1, 1, // 12729: check Inst[6] == 0x1 |
| 9077 | OPC_CheckField, 4, 1, 1, // 12733: check Inst[4] == 0x1 |
| 9078 | OPC_CheckField, 0, 1, 0, // 12737: check Inst[0] == 0x0 |
| 9079 | OPC_Decode, 184, 11, 179, 1, // 12741: decode to MVE_VMULi8 using decoder 179 |
| 9080 | // 12741: } |
| 9081 | 1, 27, // 12746: case 0x1: { |
| 9082 | OPC_CheckPredicate, 31, // 12748: check predicate 31 |
| 9083 | OPC_CheckField, 28, 4, 14, // 12750: check Inst[31:28] == 0xe |
| 9084 | OPC_CheckField, 16, 1, 0, // 12754: check Inst[16] == 0x0 |
| 9085 | OPC_CheckField, 6, 1, 1, // 12758: check Inst[6] == 0x1 |
| 9086 | OPC_CheckField, 4, 1, 1, // 12762: check Inst[4] == 0x1 |
| 9087 | OPC_CheckField, 0, 1, 0, // 12766: check Inst[0] == 0x0 |
| 9088 | OPC_Decode, 182, 11, 179, 1, // 12770: decode to MVE_VMULi16 using decoder 179 |
| 9089 | // 12770: } |
| 9090 | 2, 0, // 12775: case 0x2: { |
| 9091 | OPC_CheckPredicate, 31, // 12777: check predicate 31 |
| 9092 | OPC_CheckField, 28, 4, 14, // 12779: check Inst[31:28] == 0xe |
| 9093 | OPC_CheckField, 16, 1, 0, // 12783: check Inst[16] == 0x0 |
| 9094 | OPC_CheckField, 6, 1, 1, // 12787: check Inst[6] == 0x1 |
| 9095 | OPC_CheckField, 4, 1, 1, // 12791: check Inst[4] == 0x1 |
| 9096 | OPC_CheckField, 0, 1, 0, // 12795: check Inst[0] == 0x0 |
| 9097 | OPC_Decode, 183, 11, 179, 1, // 12799: decode to MVE_VMULi32 using decoder 179 |
| 9098 | // 12799: } |
| 9099 | // 12799: } // switch Inst[21:20] |
| 9100 | // 12799: } |
| 9101 | 11, 168, 1, // 12804: case 0xb: { |
| 9102 | OPC_SwitchField, 20, 2, // 12807: switch Inst[21:20] { |
| 9103 | 0, 53, // 12810: case 0x0: { |
| 9104 | OPC_SwitchField, 28, 4, // 12812: switch Inst[31:28] { |
| 9105 | 14, 23, // 12815: case 0xe: { |
| 9106 | OPC_CheckPredicate, 31, // 12817: check predicate 31 |
| 9107 | OPC_CheckField, 16, 1, 0, // 12819: check Inst[16] == 0x0 |
| 9108 | OPC_CheckField, 6, 1, 1, // 12823: check Inst[6] == 0x1 |
| 9109 | OPC_CheckField, 4, 1, 0, // 12827: check Inst[4] == 0x0 |
| 9110 | OPC_CheckField, 0, 1, 0, // 12831: check Inst[0] == 0x0 |
| 9111 | OPC_Decode, 132, 12, 179, 1, // 12835: decode to MVE_VQDMULHi8 using decoder 179 |
| 9112 | // 12835: } |
| 9113 | 15, 0, // 12840: case 0xf: { |
| 9114 | OPC_CheckPredicate, 31, // 12842: check predicate 31 |
| 9115 | OPC_CheckField, 16, 1, 0, // 12844: check Inst[16] == 0x0 |
| 9116 | OPC_CheckField, 6, 1, 1, // 12848: check Inst[6] == 0x1 |
| 9117 | OPC_CheckField, 4, 1, 0, // 12852: check Inst[4] == 0x0 |
| 9118 | OPC_CheckField, 0, 1, 0, // 12856: check Inst[0] == 0x0 |
| 9119 | OPC_Decode, 179, 12, 179, 1, // 12860: decode to MVE_VQRDMULHi8 using decoder 179 |
| 9120 | // 12860: } |
| 9121 | // 12860: } // switch Inst[31:28] |
| 9122 | // 12860: } |
| 9123 | 1, 53, // 12865: case 0x1: { |
| 9124 | OPC_SwitchField, 28, 4, // 12867: switch Inst[31:28] { |
| 9125 | 14, 23, // 12870: case 0xe: { |
| 9126 | OPC_CheckPredicate, 31, // 12872: check predicate 31 |
| 9127 | OPC_CheckField, 16, 1, 0, // 12874: check Inst[16] == 0x0 |
| 9128 | OPC_CheckField, 6, 1, 1, // 12878: check Inst[6] == 0x1 |
| 9129 | OPC_CheckField, 4, 1, 0, // 12882: check Inst[4] == 0x0 |
| 9130 | OPC_CheckField, 0, 1, 0, // 12886: check Inst[0] == 0x0 |
| 9131 | OPC_Decode, 130, 12, 179, 1, // 12890: decode to MVE_VQDMULHi16 using decoder 179 |
| 9132 | // 12890: } |
| 9133 | 15, 0, // 12895: case 0xf: { |
| 9134 | OPC_CheckPredicate, 31, // 12897: check predicate 31 |
| 9135 | OPC_CheckField, 16, 1, 0, // 12899: check Inst[16] == 0x0 |
| 9136 | OPC_CheckField, 6, 1, 1, // 12903: check Inst[6] == 0x1 |
| 9137 | OPC_CheckField, 4, 1, 0, // 12907: check Inst[4] == 0x0 |
| 9138 | OPC_CheckField, 0, 1, 0, // 12911: check Inst[0] == 0x0 |
| 9139 | OPC_Decode, 177, 12, 179, 1, // 12915: decode to MVE_VQRDMULHi16 using decoder 179 |
| 9140 | // 12915: } |
| 9141 | // 12915: } // switch Inst[31:28] |
| 9142 | // 12915: } |
| 9143 | 2, 0, // 12920: case 0x2: { |
| 9144 | OPC_SwitchField, 28, 4, // 12922: switch Inst[31:28] { |
| 9145 | 14, 23, // 12925: case 0xe: { |
| 9146 | OPC_CheckPredicate, 31, // 12927: check predicate 31 |
| 9147 | OPC_CheckField, 16, 1, 0, // 12929: check Inst[16] == 0x0 |
| 9148 | OPC_CheckField, 6, 1, 1, // 12933: check Inst[6] == 0x1 |
| 9149 | OPC_CheckField, 4, 1, 0, // 12937: check Inst[4] == 0x0 |
| 9150 | OPC_CheckField, 0, 1, 0, // 12941: check Inst[0] == 0x0 |
| 9151 | OPC_Decode, 131, 12, 179, 1, // 12945: decode to MVE_VQDMULHi32 using decoder 179 |
| 9152 | // 12945: } |
| 9153 | 15, 0, // 12950: case 0xf: { |
| 9154 | OPC_CheckPredicate, 31, // 12952: check predicate 31 |
| 9155 | OPC_CheckField, 16, 1, 0, // 12954: check Inst[16] == 0x0 |
| 9156 | OPC_CheckField, 6, 1, 1, // 12958: check Inst[6] == 0x1 |
| 9157 | OPC_CheckField, 4, 1, 0, // 12962: check Inst[4] == 0x0 |
| 9158 | OPC_CheckField, 0, 1, 0, // 12966: check Inst[0] == 0x0 |
| 9159 | OPC_Decode, 178, 12, 179, 1, // 12970: decode to MVE_VQRDMULHi32 using decoder 179 |
| 9160 | // 12970: } |
| 9161 | // 12970: } // switch Inst[31:28] |
| 9162 | // 12970: } |
| 9163 | // 12970: } // switch Inst[21:20] |
| 9164 | // 12970: } |
| 9165 | 12, 119, // 12975: case 0xc: { |
| 9166 | OPC_SwitchField, 20, 2, // 12977: switch Inst[21:20] { |
| 9167 | 0, 27, // 12980: case 0x0: { |
| 9168 | OPC_CheckPredicate, 33, // 12982: check predicate 33 |
| 9169 | OPC_CheckField, 28, 4, 14, // 12984: check Inst[31:28] == 0xe |
| 9170 | OPC_CheckField, 16, 1, 0, // 12988: check Inst[16] == 0x0 |
| 9171 | OPC_CheckField, 6, 1, 1, // 12992: check Inst[6] == 0x1 |
| 9172 | OPC_CheckField, 4, 1, 1, // 12996: check Inst[4] == 0x1 |
| 9173 | OPC_CheckField, 0, 1, 0, // 13000: check Inst[0] == 0x0 |
| 9174 | OPC_Decode, 156, 9, 178, 1, // 13004: decode to MVE_VFMAf32 using decoder 178 |
| 9175 | // 13004: } |
| 9176 | 1, 27, // 13009: case 0x1: { |
| 9177 | OPC_CheckPredicate, 33, // 13011: check predicate 33 |
| 9178 | OPC_CheckField, 28, 4, 14, // 13013: check Inst[31:28] == 0xe |
| 9179 | OPC_CheckField, 16, 1, 0, // 13017: check Inst[16] == 0x0 |
| 9180 | OPC_CheckField, 6, 1, 1, // 13021: check Inst[6] == 0x1 |
| 9181 | OPC_CheckField, 4, 1, 1, // 13025: check Inst[4] == 0x1 |
| 9182 | OPC_CheckField, 0, 1, 0, // 13029: check Inst[0] == 0x0 |
| 9183 | OPC_Decode, 155, 9, 178, 1, // 13033: decode to MVE_VFMAf16 using decoder 178 |
| 9184 | // 13033: } |
| 9185 | 2, 27, // 13038: case 0x2: { |
| 9186 | OPC_CheckPredicate, 33, // 13040: check predicate 33 |
| 9187 | OPC_CheckField, 28, 4, 14, // 13042: check Inst[31:28] == 0xe |
| 9188 | OPC_CheckField, 16, 1, 0, // 13046: check Inst[16] == 0x0 |
| 9189 | OPC_CheckField, 6, 1, 1, // 13050: check Inst[6] == 0x1 |
| 9190 | OPC_CheckField, 4, 1, 1, // 13054: check Inst[4] == 0x1 |
| 9191 | OPC_CheckField, 0, 1, 0, // 13058: check Inst[0] == 0x0 |
| 9192 | OPC_Decode, 158, 9, 178, 1, // 13062: decode to MVE_VFMSf32 using decoder 178 |
| 9193 | // 13062: } |
| 9194 | 3, 0, // 13067: case 0x3: { |
| 9195 | OPC_CheckPredicate, 33, // 13069: check predicate 33 |
| 9196 | OPC_CheckField, 28, 4, 14, // 13071: check Inst[31:28] == 0xe |
| 9197 | OPC_CheckField, 16, 1, 0, // 13075: check Inst[16] == 0x0 |
| 9198 | OPC_CheckField, 6, 1, 1, // 13079: check Inst[6] == 0x1 |
| 9199 | OPC_CheckField, 4, 1, 1, // 13083: check Inst[4] == 0x1 |
| 9200 | OPC_CheckField, 0, 1, 0, // 13087: check Inst[0] == 0x0 |
| 9201 | OPC_Decode, 157, 9, 178, 1, // 13091: decode to MVE_VFMSf16 using decoder 178 |
| 9202 | // 13091: } |
| 9203 | // 13091: } // switch Inst[21:20] |
| 9204 | // 13091: } |
| 9205 | 13, 223, 1, // 13096: case 0xd: { |
| 9206 | OPC_SwitchField, 20, 2, // 13099: switch Inst[21:20] { |
| 9207 | 0, 53, // 13102: case 0x0: { |
| 9208 | OPC_SwitchField, 4, 1, // 13104: switch Inst[4] { |
| 9209 | 0, 23, // 13107: case 0x0: { |
| 9210 | OPC_CheckPredicate, 33, // 13109: check predicate 33 |
| 9211 | OPC_CheckField, 28, 4, 14, // 13111: check Inst[31:28] == 0xe |
| 9212 | OPC_CheckField, 16, 1, 0, // 13115: check Inst[16] == 0x0 |
| 9213 | OPC_CheckField, 6, 1, 1, // 13119: check Inst[6] == 0x1 |
| 9214 | OPC_CheckField, 0, 1, 0, // 13123: check Inst[0] == 0x0 |
| 9215 | OPC_Decode, 181, 8, 179, 1, // 13127: decode to MVE_VADDf32 using decoder 179 |
| 9216 | // 13127: } |
| 9217 | 1, 0, // 13132: case 0x1: { |
| 9218 | OPC_CheckPredicate, 33, // 13134: check predicate 33 |
| 9219 | OPC_CheckField, 28, 4, 15, // 13136: check Inst[31:28] == 0xf |
| 9220 | OPC_CheckField, 16, 1, 0, // 13140: check Inst[16] == 0x0 |
| 9221 | OPC_CheckField, 6, 1, 1, // 13144: check Inst[6] == 0x1 |
| 9222 | OPC_CheckField, 0, 1, 0, // 13148: check Inst[0] == 0x0 |
| 9223 | OPC_Decode, 181, 11, 179, 1, // 13152: decode to MVE_VMULf32 using decoder 179 |
| 9224 | // 13152: } |
| 9225 | // 13152: } // switch Inst[4] |
| 9226 | // 13152: } |
| 9227 | 1, 53, // 13157: case 0x1: { |
| 9228 | OPC_SwitchField, 4, 1, // 13159: switch Inst[4] { |
| 9229 | 0, 23, // 13162: case 0x0: { |
| 9230 | OPC_CheckPredicate, 33, // 13164: check predicate 33 |
| 9231 | OPC_CheckField, 28, 4, 14, // 13166: check Inst[31:28] == 0xe |
| 9232 | OPC_CheckField, 16, 1, 0, // 13170: check Inst[16] == 0x0 |
| 9233 | OPC_CheckField, 6, 1, 1, // 13174: check Inst[6] == 0x1 |
| 9234 | OPC_CheckField, 0, 1, 0, // 13178: check Inst[0] == 0x0 |
| 9235 | OPC_Decode, 180, 8, 179, 1, // 13182: decode to MVE_VADDf16 using decoder 179 |
| 9236 | // 13182: } |
| 9237 | 1, 0, // 13187: case 0x1: { |
| 9238 | OPC_CheckPredicate, 33, // 13189: check predicate 33 |
| 9239 | OPC_CheckField, 28, 4, 15, // 13191: check Inst[31:28] == 0xf |
| 9240 | OPC_CheckField, 16, 1, 0, // 13195: check Inst[16] == 0x0 |
| 9241 | OPC_CheckField, 6, 1, 1, // 13199: check Inst[6] == 0x1 |
| 9242 | OPC_CheckField, 0, 1, 0, // 13203: check Inst[0] == 0x0 |
| 9243 | OPC_Decode, 180, 11, 179, 1, // 13207: decode to MVE_VMULf16 using decoder 179 |
| 9244 | // 13207: } |
| 9245 | // 13207: } // switch Inst[4] |
| 9246 | // 13207: } |
| 9247 | 2, 53, // 13212: case 0x2: { |
| 9248 | OPC_SwitchField, 28, 4, // 13214: switch Inst[31:28] { |
| 9249 | 14, 23, // 13217: case 0xe: { |
| 9250 | OPC_CheckPredicate, 33, // 13219: check predicate 33 |
| 9251 | OPC_CheckField, 16, 1, 0, // 13221: check Inst[16] == 0x0 |
| 9252 | OPC_CheckField, 6, 1, 1, // 13225: check Inst[6] == 0x1 |
| 9253 | OPC_CheckField, 4, 1, 0, // 13229: check Inst[4] == 0x0 |
| 9254 | OPC_CheckField, 0, 1, 0, // 13233: check Inst[0] == 0x0 |
| 9255 | OPC_Decode, 180, 14, 179, 1, // 13237: decode to MVE_VSUBf32 using decoder 179 |
| 9256 | // 13237: } |
| 9257 | 15, 0, // 13242: case 0xf: { |
| 9258 | OPC_CheckPredicate, 33, // 13244: check predicate 33 |
| 9259 | OPC_CheckField, 16, 1, 0, // 13246: check Inst[16] == 0x0 |
| 9260 | OPC_CheckField, 6, 1, 1, // 13250: check Inst[6] == 0x1 |
| 9261 | OPC_CheckField, 4, 1, 0, // 13254: check Inst[4] == 0x0 |
| 9262 | OPC_CheckField, 0, 1, 0, // 13258: check Inst[0] == 0x0 |
| 9263 | OPC_Decode, 145, 8, 179, 1, // 13262: decode to MVE_VABDf32 using decoder 179 |
| 9264 | // 13262: } |
| 9265 | // 13262: } // switch Inst[31:28] |
| 9266 | // 13262: } |
| 9267 | 3, 0, // 13267: case 0x3: { |
| 9268 | OPC_SwitchField, 28, 4, // 13269: switch Inst[31:28] { |
| 9269 | 14, 23, // 13272: case 0xe: { |
| 9270 | OPC_CheckPredicate, 33, // 13274: check predicate 33 |
| 9271 | OPC_CheckField, 16, 1, 0, // 13276: check Inst[16] == 0x0 |
| 9272 | OPC_CheckField, 6, 1, 1, // 13280: check Inst[6] == 0x1 |
| 9273 | OPC_CheckField, 4, 1, 0, // 13284: check Inst[4] == 0x0 |
| 9274 | OPC_CheckField, 0, 1, 0, // 13288: check Inst[0] == 0x0 |
| 9275 | OPC_Decode, 179, 14, 179, 1, // 13292: decode to MVE_VSUBf16 using decoder 179 |
| 9276 | // 13292: } |
| 9277 | 15, 0, // 13297: case 0xf: { |
| 9278 | OPC_CheckPredicate, 33, // 13299: check predicate 33 |
| 9279 | OPC_CheckField, 16, 1, 0, // 13301: check Inst[16] == 0x0 |
| 9280 | OPC_CheckField, 6, 1, 1, // 13305: check Inst[6] == 0x1 |
| 9281 | OPC_CheckField, 4, 1, 0, // 13309: check Inst[4] == 0x0 |
| 9282 | OPC_CheckField, 0, 1, 0, // 13313: check Inst[0] == 0x0 |
| 9283 | OPC_Decode, 144, 8, 179, 1, // 13317: decode to MVE_VABDf16 using decoder 179 |
| 9284 | // 13317: } |
| 9285 | // 13317: } // switch Inst[31:28] |
| 9286 | // 13317: } |
| 9287 | // 13317: } // switch Inst[21:20] |
| 9288 | // 13317: } |
| 9289 | 15, 0, // 13322: case 0xf: { |
| 9290 | OPC_SwitchField, 20, 2, // 13324: switch Inst[21:20] { |
| 9291 | 0, 27, // 13327: case 0x0: { |
| 9292 | OPC_CheckPredicate, 33, // 13329: check predicate 33 |
| 9293 | OPC_CheckField, 28, 4, 15, // 13331: check Inst[31:28] == 0xf |
| 9294 | OPC_CheckField, 16, 1, 0, // 13335: check Inst[16] == 0x0 |
| 9295 | OPC_CheckField, 6, 1, 1, // 13339: check Inst[6] == 0x1 |
| 9296 | OPC_CheckField, 4, 1, 1, // 13343: check Inst[4] == 0x1 |
| 9297 | OPC_CheckField, 0, 1, 0, // 13347: check Inst[0] == 0x0 |
| 9298 | OPC_Decode, 159, 10, 179, 1, // 13351: decode to MVE_VMAXNMf32 using decoder 179 |
| 9299 | // 13351: } |
| 9300 | 1, 27, // 13356: case 0x1: { |
| 9301 | OPC_CheckPredicate, 33, // 13358: check predicate 33 |
| 9302 | OPC_CheckField, 28, 4, 15, // 13360: check Inst[31:28] == 0xf |
| 9303 | OPC_CheckField, 16, 1, 0, // 13364: check Inst[16] == 0x0 |
| 9304 | OPC_CheckField, 6, 1, 1, // 13368: check Inst[6] == 0x1 |
| 9305 | OPC_CheckField, 4, 1, 1, // 13372: check Inst[4] == 0x1 |
| 9306 | OPC_CheckField, 0, 1, 0, // 13376: check Inst[0] == 0x0 |
| 9307 | OPC_Decode, 158, 10, 179, 1, // 13380: decode to MVE_VMAXNMf16 using decoder 179 |
| 9308 | // 13380: } |
| 9309 | 2, 27, // 13385: case 0x2: { |
| 9310 | OPC_CheckPredicate, 33, // 13387: check predicate 33 |
| 9311 | OPC_CheckField, 28, 4, 15, // 13389: check Inst[31:28] == 0xf |
| 9312 | OPC_CheckField, 16, 1, 0, // 13393: check Inst[16] == 0x0 |
| 9313 | OPC_CheckField, 6, 1, 1, // 13397: check Inst[6] == 0x1 |
| 9314 | OPC_CheckField, 4, 1, 1, // 13401: check Inst[4] == 0x1 |
| 9315 | OPC_CheckField, 0, 1, 0, // 13405: check Inst[0] == 0x0 |
| 9316 | OPC_Decode, 185, 10, 179, 1, // 13409: decode to MVE_VMINNMf32 using decoder 179 |
| 9317 | // 13409: } |
| 9318 | 3, 0, // 13414: case 0x3: { |
| 9319 | OPC_CheckPredicate, 33, // 13416: check predicate 33 |
| 9320 | OPC_CheckField, 28, 4, 15, // 13418: check Inst[31:28] == 0xf |
| 9321 | OPC_CheckField, 16, 1, 0, // 13422: check Inst[16] == 0x0 |
| 9322 | OPC_CheckField, 6, 1, 1, // 13426: check Inst[6] == 0x1 |
| 9323 | OPC_CheckField, 4, 1, 1, // 13430: check Inst[4] == 0x1 |
| 9324 | OPC_CheckField, 0, 1, 0, // 13434: check Inst[0] == 0x0 |
| 9325 | OPC_Decode, 184, 10, 179, 1, // 13438: decode to MVE_VMINNMf16 using decoder 179 |
| 9326 | // 13438: } |
| 9327 | // 13438: } // switch Inst[21:20] |
| 9328 | // 13438: } |
| 9329 | // 13438: } // switch Inst[12:8] |
| 9330 | // 13438: } |
| 9331 | 3, 0, // 13443: case 0x3: { |
| 9332 | OPC_SwitchField, 4, 1, // 13445: switch Inst[4] { |
| 9333 | 0, 164, 9, // 13448: case 0x0: { |
| 9334 | OPC_SwitchField, 6, 7, // 13451: switch Inst[12:6] { |
| 9335 | 1, 88, // 13454: case 0x1: { |
| 9336 | OPC_SwitchField, 16, 6, // 13456: switch Inst[21:16] { |
| 9337 | 48, 15, // 13459: case 0x30: { |
| 9338 | OPC_CheckPredicate, 31, // 13461: check predicate 31 |
| 9339 | OPC_CheckField, 28, 4, 15, // 13463: check Inst[31:28] == 0xf |
| 9340 | OPC_CheckField, 0, 1, 0, // 13467: check Inst[0] == 0x0 |
| 9341 | OPC_Decode, 254, 12, 183, 1, // 13471: decode to MVE_VREV64_8 using decoder 183 |
| 9342 | // 13471: } |
| 9343 | 52, 15, // 13476: case 0x34: { |
| 9344 | OPC_CheckPredicate, 31, // 13478: check predicate 31 |
| 9345 | OPC_CheckField, 28, 4, 15, // 13480: check Inst[31:28] == 0xf |
| 9346 | OPC_CheckField, 0, 1, 0, // 13484: check Inst[0] == 0x0 |
| 9347 | OPC_Decode, 252, 12, 183, 1, // 13488: decode to MVE_VREV64_16 using decoder 183 |
| 9348 | // 13488: } |
| 9349 | 55, 15, // 13493: case 0x37: { |
| 9350 | OPC_CheckPredicate, 33, // 13495: check predicate 33 |
| 9351 | OPC_CheckField, 28, 4, 15, // 13497: check Inst[31:28] == 0xf |
| 9352 | OPC_CheckField, 0, 1, 0, // 13501: check Inst[0] == 0x0 |
| 9353 | OPC_Decode, 246, 8, 183, 1, // 13505: decode to MVE_VCVTs16f16a using decoder 183 |
| 9354 | // 13505: } |
| 9355 | 56, 15, // 13510: case 0x38: { |
| 9356 | OPC_CheckPredicate, 31, // 13512: check predicate 31 |
| 9357 | OPC_CheckField, 28, 4, 15, // 13514: check Inst[31:28] == 0xf |
| 9358 | OPC_CheckField, 0, 1, 0, // 13518: check Inst[0] == 0x0 |
| 9359 | OPC_Decode, 253, 12, 183, 1, // 13522: decode to MVE_VREV64_32 using decoder 183 |
| 9360 | // 13522: } |
| 9361 | 59, 0, // 13527: case 0x3b: { |
| 9362 | OPC_CheckPredicate, 33, // 13529: check predicate 33 |
| 9363 | OPC_CheckField, 28, 4, 15, // 13531: check Inst[31:28] == 0xf |
| 9364 | OPC_CheckField, 0, 1, 0, // 13535: check Inst[0] == 0x0 |
| 9365 | OPC_Decode, 252, 8, 183, 1, // 13539: decode to MVE_VCVTs32f32a using decoder 183 |
| 9366 | // 13539: } |
| 9367 | // 13539: } // switch Inst[21:16] |
| 9368 | // 13539: } |
| 9369 | 3, 71, // 13544: case 0x3: { |
| 9370 | OPC_SwitchField, 16, 6, // 13546: switch Inst[21:16] { |
| 9371 | 48, 15, // 13549: case 0x30: { |
| 9372 | OPC_CheckPredicate, 31, // 13551: check predicate 31 |
| 9373 | OPC_CheckField, 28, 4, 15, // 13553: check Inst[31:28] == 0xf |
| 9374 | OPC_CheckField, 0, 1, 0, // 13557: check Inst[0] == 0x0 |
| 9375 | OPC_Decode, 251, 12, 183, 1, // 13561: decode to MVE_VREV32_8 using decoder 183 |
| 9376 | // 13561: } |
| 9377 | 52, 15, // 13566: case 0x34: { |
| 9378 | OPC_CheckPredicate, 31, // 13568: check predicate 31 |
| 9379 | OPC_CheckField, 28, 4, 15, // 13570: check Inst[31:28] == 0xf |
| 9380 | OPC_CheckField, 0, 1, 0, // 13574: check Inst[0] == 0x0 |
| 9381 | OPC_Decode, 250, 12, 183, 1, // 13578: decode to MVE_VREV32_16 using decoder 183 |
| 9382 | // 13578: } |
| 9383 | 55, 15, // 13583: case 0x37: { |
| 9384 | OPC_CheckPredicate, 33, // 13585: check predicate 33 |
| 9385 | OPC_CheckField, 28, 4, 15, // 13587: check Inst[31:28] == 0xf |
| 9386 | OPC_CheckField, 0, 1, 0, // 13591: check Inst[0] == 0x0 |
| 9387 | OPC_Decode, 130, 9, 183, 1, // 13595: decode to MVE_VCVTu16f16a using decoder 183 |
| 9388 | // 13595: } |
| 9389 | 59, 0, // 13600: case 0x3b: { |
| 9390 | OPC_CheckPredicate, 33, // 13602: check predicate 33 |
| 9391 | OPC_CheckField, 28, 4, 15, // 13604: check Inst[31:28] == 0xf |
| 9392 | OPC_CheckField, 0, 1, 0, // 13608: check Inst[0] == 0x0 |
| 9393 | OPC_Decode, 136, 9, 183, 1, // 13612: decode to MVE_VCVTu32f32a using decoder 183 |
| 9394 | // 13612: } |
| 9395 | // 13612: } // switch Inst[21:16] |
| 9396 | // 13612: } |
| 9397 | 5, 54, // 13617: case 0x5: { |
| 9398 | OPC_SwitchField, 16, 6, // 13619: switch Inst[21:16] { |
| 9399 | 48, 15, // 13622: case 0x30: { |
| 9400 | OPC_CheckPredicate, 31, // 13624: check predicate 31 |
| 9401 | OPC_CheckField, 28, 4, 15, // 13626: check Inst[31:28] == 0xf |
| 9402 | OPC_CheckField, 0, 1, 0, // 13630: check Inst[0] == 0x0 |
| 9403 | OPC_Decode, 249, 12, 183, 1, // 13634: decode to MVE_VREV16_8 using decoder 183 |
| 9404 | // 13634: } |
| 9405 | 55, 15, // 13639: case 0x37: { |
| 9406 | OPC_CheckPredicate, 33, // 13641: check predicate 33 |
| 9407 | OPC_CheckField, 28, 4, 15, // 13643: check Inst[31:28] == 0xf |
| 9408 | OPC_CheckField, 0, 1, 0, // 13647: check Inst[0] == 0x0 |
| 9409 | OPC_Decode, 248, 8, 183, 1, // 13651: decode to MVE_VCVTs16f16n using decoder 183 |
| 9410 | // 13651: } |
| 9411 | 59, 0, // 13656: case 0x3b: { |
| 9412 | OPC_CheckPredicate, 33, // 13658: check predicate 33 |
| 9413 | OPC_CheckField, 28, 4, 15, // 13660: check Inst[31:28] == 0xf |
| 9414 | OPC_CheckField, 0, 1, 0, // 13664: check Inst[0] == 0x0 |
| 9415 | OPC_Decode, 254, 8, 183, 1, // 13668: decode to MVE_VCVTs32f32n using decoder 183 |
| 9416 | // 13668: } |
| 9417 | // 13668: } // switch Inst[21:16] |
| 9418 | // 13668: } |
| 9419 | 7, 37, // 13673: case 0x7: { |
| 9420 | OPC_SwitchField, 16, 6, // 13675: switch Inst[21:16] { |
| 9421 | 55, 15, // 13678: case 0x37: { |
| 9422 | OPC_CheckPredicate, 33, // 13680: check predicate 33 |
| 9423 | OPC_CheckField, 28, 4, 15, // 13682: check Inst[31:28] == 0xf |
| 9424 | OPC_CheckField, 0, 1, 0, // 13686: check Inst[0] == 0x0 |
| 9425 | OPC_Decode, 132, 9, 183, 1, // 13690: decode to MVE_VCVTu16f16n using decoder 183 |
| 9426 | // 13690: } |
| 9427 | 59, 0, // 13695: case 0x3b: { |
| 9428 | OPC_CheckPredicate, 33, // 13697: check predicate 33 |
| 9429 | OPC_CheckField, 28, 4, 15, // 13699: check Inst[31:28] == 0xf |
| 9430 | OPC_CheckField, 0, 1, 0, // 13703: check Inst[0] == 0x0 |
| 9431 | OPC_Decode, 138, 9, 183, 1, // 13707: decode to MVE_VCVTu32f32n using decoder 183 |
| 9432 | // 13707: } |
| 9433 | // 13707: } // switch Inst[21:16] |
| 9434 | // 13707: } |
| 9435 | 9, 37, // 13712: case 0x9: { |
| 9436 | OPC_SwitchField, 16, 6, // 13714: switch Inst[21:16] { |
| 9437 | 55, 15, // 13717: case 0x37: { |
| 9438 | OPC_CheckPredicate, 33, // 13719: check predicate 33 |
| 9439 | OPC_CheckField, 28, 4, 15, // 13721: check Inst[31:28] == 0xf |
| 9440 | OPC_CheckField, 0, 1, 0, // 13725: check Inst[0] == 0x0 |
| 9441 | OPC_Decode, 249, 8, 183, 1, // 13729: decode to MVE_VCVTs16f16p using decoder 183 |
| 9442 | // 13729: } |
| 9443 | 59, 0, // 13734: case 0x3b: { |
| 9444 | OPC_CheckPredicate, 33, // 13736: check predicate 33 |
| 9445 | OPC_CheckField, 28, 4, 15, // 13738: check Inst[31:28] == 0xf |
| 9446 | OPC_CheckField, 0, 1, 0, // 13742: check Inst[0] == 0x0 |
| 9447 | OPC_Decode, 255, 8, 183, 1, // 13746: decode to MVE_VCVTs32f32p using decoder 183 |
| 9448 | // 13746: } |
| 9449 | // 13746: } // switch Inst[21:16] |
| 9450 | // 13746: } |
| 9451 | 11, 37, // 13751: case 0xb: { |
| 9452 | OPC_SwitchField, 16, 6, // 13753: switch Inst[21:16] { |
| 9453 | 55, 15, // 13756: case 0x37: { |
| 9454 | OPC_CheckPredicate, 33, // 13758: check predicate 33 |
| 9455 | OPC_CheckField, 28, 4, 15, // 13760: check Inst[31:28] == 0xf |
| 9456 | OPC_CheckField, 0, 1, 0, // 13764: check Inst[0] == 0x0 |
| 9457 | OPC_Decode, 133, 9, 183, 1, // 13768: decode to MVE_VCVTu16f16p using decoder 183 |
| 9458 | // 13768: } |
| 9459 | 59, 0, // 13773: case 0x3b: { |
| 9460 | OPC_CheckPredicate, 33, // 13775: check predicate 33 |
| 9461 | OPC_CheckField, 28, 4, 15, // 13777: check Inst[31:28] == 0xf |
| 9462 | OPC_CheckField, 0, 1, 0, // 13781: check Inst[0] == 0x0 |
| 9463 | OPC_Decode, 139, 9, 183, 1, // 13785: decode to MVE_VCVTu32f32p using decoder 183 |
| 9464 | // 13785: } |
| 9465 | // 13785: } // switch Inst[21:16] |
| 9466 | // 13785: } |
| 9467 | 13, 88, // 13790: case 0xd: { |
| 9468 | OPC_SwitchField, 16, 6, // 13792: switch Inst[21:16] { |
| 9469 | 49, 15, // 13795: case 0x31: { |
| 9470 | OPC_CheckPredicate, 31, // 13797: check predicate 31 |
| 9471 | OPC_CheckField, 28, 4, 15, // 13799: check Inst[31:28] == 0xf |
| 9472 | OPC_CheckField, 0, 1, 0, // 13803: check Inst[0] == 0x0 |
| 9473 | OPC_Decode, 156, 8, 183, 1, // 13807: decode to MVE_VABSs8 using decoder 183 |
| 9474 | // 13807: } |
| 9475 | 53, 15, // 13812: case 0x35: { |
| 9476 | OPC_CheckPredicate, 31, // 13814: check predicate 31 |
| 9477 | OPC_CheckField, 28, 4, 15, // 13816: check Inst[31:28] == 0xf |
| 9478 | OPC_CheckField, 0, 1, 0, // 13820: check Inst[0] == 0x0 |
| 9479 | OPC_Decode, 154, 8, 183, 1, // 13824: decode to MVE_VABSs16 using decoder 183 |
| 9480 | // 13824: } |
| 9481 | 55, 15, // 13829: case 0x37: { |
| 9482 | OPC_CheckPredicate, 33, // 13831: check predicate 33 |
| 9483 | OPC_CheckField, 28, 4, 15, // 13833: check Inst[31:28] == 0xf |
| 9484 | OPC_CheckField, 0, 1, 0, // 13837: check Inst[0] == 0x0 |
| 9485 | OPC_Decode, 247, 8, 183, 1, // 13841: decode to MVE_VCVTs16f16m using decoder 183 |
| 9486 | // 13841: } |
| 9487 | 57, 15, // 13846: case 0x39: { |
| 9488 | OPC_CheckPredicate, 31, // 13848: check predicate 31 |
| 9489 | OPC_CheckField, 28, 4, 15, // 13850: check Inst[31:28] == 0xf |
| 9490 | OPC_CheckField, 0, 1, 0, // 13854: check Inst[0] == 0x0 |
| 9491 | OPC_Decode, 155, 8, 183, 1, // 13858: decode to MVE_VABSs32 using decoder 183 |
| 9492 | // 13858: } |
| 9493 | 59, 0, // 13863: case 0x3b: { |
| 9494 | OPC_CheckPredicate, 33, // 13865: check predicate 33 |
| 9495 | OPC_CheckField, 28, 4, 15, // 13867: check Inst[31:28] == 0xf |
| 9496 | OPC_CheckField, 0, 1, 0, // 13871: check Inst[0] == 0x0 |
| 9497 | OPC_Decode, 253, 8, 183, 1, // 13875: decode to MVE_VCVTs32f32m using decoder 183 |
| 9498 | // 13875: } |
| 9499 | // 13875: } // switch Inst[21:16] |
| 9500 | // 13875: } |
| 9501 | 15, 88, // 13880: case 0xf: { |
| 9502 | OPC_SwitchField, 16, 6, // 13882: switch Inst[21:16] { |
| 9503 | 49, 15, // 13885: case 0x31: { |
| 9504 | OPC_CheckPredicate, 31, // 13887: check predicate 31 |
| 9505 | OPC_CheckField, 28, 4, 15, // 13889: check Inst[31:28] == 0xf |
| 9506 | OPC_CheckField, 0, 1, 0, // 13893: check Inst[0] == 0x0 |
| 9507 | OPC_Decode, 192, 11, 183, 1, // 13897: decode to MVE_VNEGs8 using decoder 183 |
| 9508 | // 13897: } |
| 9509 | 53, 15, // 13902: case 0x35: { |
| 9510 | OPC_CheckPredicate, 31, // 13904: check predicate 31 |
| 9511 | OPC_CheckField, 28, 4, 15, // 13906: check Inst[31:28] == 0xf |
| 9512 | OPC_CheckField, 0, 1, 0, // 13910: check Inst[0] == 0x0 |
| 9513 | OPC_Decode, 190, 11, 183, 1, // 13914: decode to MVE_VNEGs16 using decoder 183 |
| 9514 | // 13914: } |
| 9515 | 55, 15, // 13919: case 0x37: { |
| 9516 | OPC_CheckPredicate, 33, // 13921: check predicate 33 |
| 9517 | OPC_CheckField, 28, 4, 15, // 13923: check Inst[31:28] == 0xf |
| 9518 | OPC_CheckField, 0, 1, 0, // 13927: check Inst[0] == 0x0 |
| 9519 | OPC_Decode, 131, 9, 183, 1, // 13931: decode to MVE_VCVTu16f16m using decoder 183 |
| 9520 | // 13931: } |
| 9521 | 57, 15, // 13936: case 0x39: { |
| 9522 | OPC_CheckPredicate, 31, // 13938: check predicate 31 |
| 9523 | OPC_CheckField, 28, 4, 15, // 13940: check Inst[31:28] == 0xf |
| 9524 | OPC_CheckField, 0, 1, 0, // 13944: check Inst[0] == 0x0 |
| 9525 | OPC_Decode, 191, 11, 183, 1, // 13948: decode to MVE_VNEGs32 using decoder 183 |
| 9526 | // 13948: } |
| 9527 | 59, 0, // 13953: case 0x3b: { |
| 9528 | OPC_CheckPredicate, 33, // 13955: check predicate 33 |
| 9529 | OPC_CheckField, 28, 4, 15, // 13957: check Inst[31:28] == 0xf |
| 9530 | OPC_CheckField, 0, 1, 0, // 13961: check Inst[0] == 0x0 |
| 9531 | OPC_Decode, 137, 9, 183, 1, // 13965: decode to MVE_VCVTu32f32m using decoder 183 |
| 9532 | // 13965: } |
| 9533 | // 13965: } // switch Inst[21:16] |
| 9534 | // 13965: } |
| 9535 | 17, 88, // 13970: case 0x11: { |
| 9536 | OPC_SwitchField, 16, 6, // 13972: switch Inst[21:16] { |
| 9537 | 48, 15, // 13975: case 0x30: { |
| 9538 | OPC_CheckPredicate, 31, // 13977: check predicate 31 |
| 9539 | OPC_CheckField, 28, 4, 15, // 13979: check Inst[31:28] == 0xf |
| 9540 | OPC_CheckField, 0, 1, 0, // 13983: check Inst[0] == 0x0 |
| 9541 | OPC_Decode, 199, 8, 183, 1, // 13987: decode to MVE_VCLSs8 using decoder 183 |
| 9542 | // 13987: } |
| 9543 | 52, 15, // 13992: case 0x34: { |
| 9544 | OPC_CheckPredicate, 31, // 13994: check predicate 31 |
| 9545 | OPC_CheckField, 28, 4, 15, // 13996: check Inst[31:28] == 0xf |
| 9546 | OPC_CheckField, 0, 1, 0, // 14000: check Inst[0] == 0x0 |
| 9547 | OPC_Decode, 197, 8, 183, 1, // 14004: decode to MVE_VCLSs16 using decoder 183 |
| 9548 | // 14004: } |
| 9549 | 54, 15, // 14009: case 0x36: { |
| 9550 | OPC_CheckPredicate, 33, // 14011: check predicate 33 |
| 9551 | OPC_CheckField, 28, 4, 15, // 14013: check Inst[31:28] == 0xf |
| 9552 | OPC_CheckField, 0, 1, 0, // 14017: check Inst[0] == 0x0 |
| 9553 | OPC_Decode, 135, 13, 183, 1, // 14021: decode to MVE_VRINTf16N using decoder 183 |
| 9554 | // 14021: } |
| 9555 | 56, 15, // 14026: case 0x38: { |
| 9556 | OPC_CheckPredicate, 31, // 14028: check predicate 31 |
| 9557 | OPC_CheckField, 28, 4, 15, // 14030: check Inst[31:28] == 0xf |
| 9558 | OPC_CheckField, 0, 1, 0, // 14034: check Inst[0] == 0x0 |
| 9559 | OPC_Decode, 198, 8, 183, 1, // 14038: decode to MVE_VCLSs32 using decoder 183 |
| 9560 | // 14038: } |
| 9561 | 58, 0, // 14043: case 0x3a: { |
| 9562 | OPC_CheckPredicate, 33, // 14045: check predicate 33 |
| 9563 | OPC_CheckField, 28, 4, 15, // 14047: check Inst[31:28] == 0xf |
| 9564 | OPC_CheckField, 0, 1, 0, // 14051: check Inst[0] == 0x0 |
| 9565 | OPC_Decode, 141, 13, 183, 1, // 14055: decode to MVE_VRINTf32N using decoder 183 |
| 9566 | // 14055: } |
| 9567 | // 14055: } // switch Inst[21:16] |
| 9568 | // 14055: } |
| 9569 | 19, 88, // 14060: case 0x13: { |
| 9570 | OPC_SwitchField, 16, 6, // 14062: switch Inst[21:16] { |
| 9571 | 48, 15, // 14065: case 0x30: { |
| 9572 | OPC_CheckPredicate, 31, // 14067: check predicate 31 |
| 9573 | OPC_CheckField, 28, 4, 15, // 14069: check Inst[31:28] == 0xf |
| 9574 | OPC_CheckField, 0, 1, 0, // 14073: check Inst[0] == 0x0 |
| 9575 | OPC_Decode, 202, 8, 183, 1, // 14077: decode to MVE_VCLZs8 using decoder 183 |
| 9576 | // 14077: } |
| 9577 | 52, 15, // 14082: case 0x34: { |
| 9578 | OPC_CheckPredicate, 31, // 14084: check predicate 31 |
| 9579 | OPC_CheckField, 28, 4, 15, // 14086: check Inst[31:28] == 0xf |
| 9580 | OPC_CheckField, 0, 1, 0, // 14090: check Inst[0] == 0x0 |
| 9581 | OPC_Decode, 200, 8, 183, 1, // 14094: decode to MVE_VCLZs16 using decoder 183 |
| 9582 | // 14094: } |
| 9583 | 54, 15, // 14099: case 0x36: { |
| 9584 | OPC_CheckPredicate, 33, // 14101: check predicate 33 |
| 9585 | OPC_CheckField, 28, 4, 15, // 14103: check Inst[31:28] == 0xf |
| 9586 | OPC_CheckField, 0, 1, 0, // 14107: check Inst[0] == 0x0 |
| 9587 | OPC_Decode, 137, 13, 183, 1, // 14111: decode to MVE_VRINTf16X using decoder 183 |
| 9588 | // 14111: } |
| 9589 | 56, 15, // 14116: case 0x38: { |
| 9590 | OPC_CheckPredicate, 31, // 14118: check predicate 31 |
| 9591 | OPC_CheckField, 28, 4, 15, // 14120: check Inst[31:28] == 0xf |
| 9592 | OPC_CheckField, 0, 1, 0, // 14124: check Inst[0] == 0x0 |
| 9593 | OPC_Decode, 201, 8, 183, 1, // 14128: decode to MVE_VCLZs32 using decoder 183 |
| 9594 | // 14128: } |
| 9595 | 58, 0, // 14133: case 0x3a: { |
| 9596 | OPC_CheckPredicate, 33, // 14135: check predicate 33 |
| 9597 | OPC_CheckField, 28, 4, 15, // 14137: check Inst[31:28] == 0xf |
| 9598 | OPC_CheckField, 0, 1, 0, // 14141: check Inst[0] == 0x0 |
| 9599 | OPC_Decode, 143, 13, 183, 1, // 14145: decode to MVE_VRINTf32X using decoder 183 |
| 9600 | // 14145: } |
| 9601 | // 14145: } // switch Inst[21:16] |
| 9602 | // 14145: } |
| 9603 | 21, 37, // 14150: case 0x15: { |
| 9604 | OPC_SwitchField, 16, 6, // 14152: switch Inst[21:16] { |
| 9605 | 54, 15, // 14155: case 0x36: { |
| 9606 | OPC_CheckPredicate, 33, // 14157: check predicate 33 |
| 9607 | OPC_CheckField, 28, 4, 15, // 14159: check Inst[31:28] == 0xf |
| 9608 | OPC_CheckField, 0, 1, 0, // 14163: check Inst[0] == 0x0 |
| 9609 | OPC_Decode, 133, 13, 183, 1, // 14167: decode to MVE_VRINTf16A using decoder 183 |
| 9610 | // 14167: } |
| 9611 | 58, 0, // 14172: case 0x3a: { |
| 9612 | OPC_CheckPredicate, 33, // 14174: check predicate 33 |
| 9613 | OPC_CheckField, 28, 4, 15, // 14176: check Inst[31:28] == 0xf |
| 9614 | OPC_CheckField, 0, 1, 0, // 14180: check Inst[0] == 0x0 |
| 9615 | OPC_Decode, 139, 13, 183, 1, // 14184: decode to MVE_VRINTf32A using decoder 183 |
| 9616 | // 14184: } |
| 9617 | // 14184: } // switch Inst[21:16] |
| 9618 | // 14184: } |
| 9619 | 23, 54, // 14189: case 0x17: { |
| 9620 | OPC_SwitchField, 16, 6, // 14191: switch Inst[21:16] { |
| 9621 | 48, 15, // 14194: case 0x30: { |
| 9622 | OPC_CheckPredicate, 31, // 14196: check predicate 31 |
| 9623 | OPC_CheckField, 28, 4, 15, // 14198: check Inst[31:28] == 0xf |
| 9624 | OPC_CheckField, 0, 1, 0, // 14202: check Inst[0] == 0x0 |
| 9625 | OPC_Decode, 185, 11, 183, 1, // 14206: decode to MVE_VMVN using decoder 183 |
| 9626 | // 14206: } |
| 9627 | 54, 15, // 14211: case 0x36: { |
| 9628 | OPC_CheckPredicate, 33, // 14213: check predicate 33 |
| 9629 | OPC_CheckField, 28, 4, 15, // 14215: check Inst[31:28] == 0xf |
| 9630 | OPC_CheckField, 0, 1, 0, // 14219: check Inst[0] == 0x0 |
| 9631 | OPC_Decode, 138, 13, 183, 1, // 14223: decode to MVE_VRINTf16Z using decoder 183 |
| 9632 | // 14223: } |
| 9633 | 58, 0, // 14228: case 0x3a: { |
| 9634 | OPC_CheckPredicate, 33, // 14230: check predicate 33 |
| 9635 | OPC_CheckField, 28, 4, 15, // 14232: check Inst[31:28] == 0xf |
| 9636 | OPC_CheckField, 0, 1, 0, // 14236: check Inst[0] == 0x0 |
| 9637 | OPC_Decode, 144, 13, 183, 1, // 14240: decode to MVE_VRINTf32Z using decoder 183 |
| 9638 | // 14240: } |
| 9639 | // 14240: } // switch Inst[21:16] |
| 9640 | // 14240: } |
| 9641 | 25, 37, // 14245: case 0x19: { |
| 9642 | OPC_SwitchField, 16, 6, // 14247: switch Inst[21:16] { |
| 9643 | 55, 15, // 14250: case 0x37: { |
| 9644 | OPC_CheckPredicate, 33, // 14252: check predicate 33 |
| 9645 | OPC_CheckField, 28, 4, 15, // 14254: check Inst[31:28] == 0xf |
| 9646 | OPC_CheckField, 0, 1, 0, // 14258: check Inst[0] == 0x0 |
| 9647 | OPC_Decode, 236, 8, 183, 1, // 14262: decode to MVE_VCVTf16s16n using decoder 183 |
| 9648 | // 14262: } |
| 9649 | 59, 0, // 14267: case 0x3b: { |
| 9650 | OPC_CheckPredicate, 33, // 14269: check predicate 33 |
| 9651 | OPC_CheckField, 28, 4, 15, // 14271: check Inst[31:28] == 0xf |
| 9652 | OPC_CheckField, 0, 1, 0, // 14275: check Inst[0] == 0x0 |
| 9653 | OPC_Decode, 242, 8, 183, 1, // 14279: decode to MVE_VCVTf32s32n using decoder 183 |
| 9654 | // 14279: } |
| 9655 | // 14279: } // switch Inst[21:16] |
| 9656 | // 14279: } |
| 9657 | 27, 71, // 14284: case 0x1b: { |
| 9658 | OPC_SwitchField, 16, 6, // 14286: switch Inst[21:16] { |
| 9659 | 54, 15, // 14289: case 0x36: { |
| 9660 | OPC_CheckPredicate, 33, // 14291: check predicate 33 |
| 9661 | OPC_CheckField, 28, 4, 15, // 14293: check Inst[31:28] == 0xf |
| 9662 | OPC_CheckField, 0, 1, 0, // 14297: check Inst[0] == 0x0 |
| 9663 | OPC_Decode, 134, 13, 183, 1, // 14301: decode to MVE_VRINTf16M using decoder 183 |
| 9664 | // 14301: } |
| 9665 | 55, 15, // 14306: case 0x37: { |
| 9666 | OPC_CheckPredicate, 33, // 14308: check predicate 33 |
| 9667 | OPC_CheckField, 28, 4, 15, // 14310: check Inst[31:28] == 0xf |
| 9668 | OPC_CheckField, 0, 1, 0, // 14314: check Inst[0] == 0x0 |
| 9669 | OPC_Decode, 238, 8, 183, 1, // 14318: decode to MVE_VCVTf16u16n using decoder 183 |
| 9670 | // 14318: } |
| 9671 | 58, 15, // 14323: case 0x3a: { |
| 9672 | OPC_CheckPredicate, 33, // 14325: check predicate 33 |
| 9673 | OPC_CheckField, 28, 4, 15, // 14327: check Inst[31:28] == 0xf |
| 9674 | OPC_CheckField, 0, 1, 0, // 14331: check Inst[0] == 0x0 |
| 9675 | OPC_Decode, 140, 13, 183, 1, // 14335: decode to MVE_VRINTf32M using decoder 183 |
| 9676 | // 14335: } |
| 9677 | 59, 0, // 14340: case 0x3b: { |
| 9678 | OPC_CheckPredicate, 33, // 14342: check predicate 33 |
| 9679 | OPC_CheckField, 28, 4, 15, // 14344: check Inst[31:28] == 0xf |
| 9680 | OPC_CheckField, 0, 1, 0, // 14348: check Inst[0] == 0x0 |
| 9681 | OPC_Decode, 244, 8, 183, 1, // 14352: decode to MVE_VCVTf32u32n using decoder 183 |
| 9682 | // 14352: } |
| 9683 | // 14352: } // switch Inst[21:16] |
| 9684 | // 14352: } |
| 9685 | 29, 122, // 14357: case 0x1d: { |
| 9686 | OPC_SwitchField, 16, 6, // 14359: switch Inst[21:16] { |
| 9687 | 48, 15, // 14362: case 0x30: { |
| 9688 | OPC_CheckPredicate, 31, // 14364: check predicate 31 |
| 9689 | OPC_CheckField, 28, 4, 15, // 14366: check Inst[31:28] == 0xf |
| 9690 | OPC_CheckField, 0, 1, 0, // 14370: check Inst[0] == 0x0 |
| 9691 | OPC_Decode, 224, 11, 183, 1, // 14374: decode to MVE_VQABSs8 using decoder 183 |
| 9692 | // 14374: } |
| 9693 | 52, 15, // 14379: case 0x34: { |
| 9694 | OPC_CheckPredicate, 31, // 14381: check predicate 31 |
| 9695 | OPC_CheckField, 28, 4, 15, // 14383: check Inst[31:28] == 0xf |
| 9696 | OPC_CheckField, 0, 1, 0, // 14387: check Inst[0] == 0x0 |
| 9697 | OPC_Decode, 222, 11, 183, 1, // 14391: decode to MVE_VQABSs16 using decoder 183 |
| 9698 | // 14391: } |
| 9699 | 53, 15, // 14396: case 0x35: { |
| 9700 | OPC_CheckPredicate, 33, // 14398: check predicate 33 |
| 9701 | OPC_CheckField, 28, 4, 15, // 14400: check Inst[31:28] == 0xf |
| 9702 | OPC_CheckField, 0, 1, 0, // 14404: check Inst[0] == 0x0 |
| 9703 | OPC_Decode, 152, 8, 183, 1, // 14408: decode to MVE_VABSf16 using decoder 183 |
| 9704 | // 14408: } |
| 9705 | 55, 15, // 14413: case 0x37: { |
| 9706 | OPC_CheckPredicate, 33, // 14415: check predicate 33 |
| 9707 | OPC_CheckField, 28, 4, 15, // 14417: check Inst[31:28] == 0xf |
| 9708 | OPC_CheckField, 0, 1, 0, // 14421: check Inst[0] == 0x0 |
| 9709 | OPC_Decode, 250, 8, 183, 1, // 14425: decode to MVE_VCVTs16f16z using decoder 183 |
| 9710 | // 14425: } |
| 9711 | 56, 15, // 14430: case 0x38: { |
| 9712 | OPC_CheckPredicate, 31, // 14432: check predicate 31 |
| 9713 | OPC_CheckField, 28, 4, 15, // 14434: check Inst[31:28] == 0xf |
| 9714 | OPC_CheckField, 0, 1, 0, // 14438: check Inst[0] == 0x0 |
| 9715 | OPC_Decode, 223, 11, 183, 1, // 14442: decode to MVE_VQABSs32 using decoder 183 |
| 9716 | // 14442: } |
| 9717 | 57, 15, // 14447: case 0x39: { |
| 9718 | OPC_CheckPredicate, 33, // 14449: check predicate 33 |
| 9719 | OPC_CheckField, 28, 4, 15, // 14451: check Inst[31:28] == 0xf |
| 9720 | OPC_CheckField, 0, 1, 0, // 14455: check Inst[0] == 0x0 |
| 9721 | OPC_Decode, 153, 8, 183, 1, // 14459: decode to MVE_VABSf32 using decoder 183 |
| 9722 | // 14459: } |
| 9723 | 59, 0, // 14464: case 0x3b: { |
| 9724 | OPC_CheckPredicate, 33, // 14466: check predicate 33 |
| 9725 | OPC_CheckField, 28, 4, 15, // 14468: check Inst[31:28] == 0xf |
| 9726 | OPC_CheckField, 0, 1, 0, // 14472: check Inst[0] == 0x0 |
| 9727 | OPC_Decode, 128, 9, 183, 1, // 14476: decode to MVE_VCVTs32f32z using decoder 183 |
| 9728 | // 14476: } |
| 9729 | // 14476: } // switch Inst[21:16] |
| 9730 | // 14476: } |
| 9731 | 31, 0, // 14481: case 0x1f: { |
| 9732 | OPC_SwitchField, 16, 6, // 14483: switch Inst[21:16] { |
| 9733 | 48, 15, // 14486: case 0x30: { |
| 9734 | OPC_CheckPredicate, 31, // 14488: check predicate 31 |
| 9735 | OPC_CheckField, 28, 4, 15, // 14490: check Inst[31:28] == 0xf |
| 9736 | OPC_CheckField, 0, 1, 0, // 14494: check Inst[0] == 0x0 |
| 9737 | OPC_Decode, 155, 12, 183, 1, // 14498: decode to MVE_VQNEGs8 using decoder 183 |
| 9738 | // 14498: } |
| 9739 | 52, 15, // 14503: case 0x34: { |
| 9740 | OPC_CheckPredicate, 31, // 14505: check predicate 31 |
| 9741 | OPC_CheckField, 28, 4, 15, // 14507: check Inst[31:28] == 0xf |
| 9742 | OPC_CheckField, 0, 1, 0, // 14511: check Inst[0] == 0x0 |
| 9743 | OPC_Decode, 153, 12, 183, 1, // 14515: decode to MVE_VQNEGs16 using decoder 183 |
| 9744 | // 14515: } |
| 9745 | 53, 15, // 14520: case 0x35: { |
| 9746 | OPC_CheckPredicate, 33, // 14522: check predicate 33 |
| 9747 | OPC_CheckField, 28, 4, 15, // 14524: check Inst[31:28] == 0xf |
| 9748 | OPC_CheckField, 0, 1, 0, // 14528: check Inst[0] == 0x0 |
| 9749 | OPC_Decode, 188, 11, 183, 1, // 14532: decode to MVE_VNEGf16 using decoder 183 |
| 9750 | // 14532: } |
| 9751 | 54, 15, // 14537: case 0x36: { |
| 9752 | OPC_CheckPredicate, 33, // 14539: check predicate 33 |
| 9753 | OPC_CheckField, 28, 4, 15, // 14541: check Inst[31:28] == 0xf |
| 9754 | OPC_CheckField, 0, 1, 0, // 14545: check Inst[0] == 0x0 |
| 9755 | OPC_Decode, 136, 13, 183, 1, // 14549: decode to MVE_VRINTf16P using decoder 183 |
| 9756 | // 14549: } |
| 9757 | 55, 15, // 14554: case 0x37: { |
| 9758 | OPC_CheckPredicate, 33, // 14556: check predicate 33 |
| 9759 | OPC_CheckField, 28, 4, 15, // 14558: check Inst[31:28] == 0xf |
| 9760 | OPC_CheckField, 0, 1, 0, // 14562: check Inst[0] == 0x0 |
| 9761 | OPC_Decode, 134, 9, 183, 1, // 14566: decode to MVE_VCVTu16f16z using decoder 183 |
| 9762 | // 14566: } |
| 9763 | 56, 15, // 14571: case 0x38: { |
| 9764 | OPC_CheckPredicate, 31, // 14573: check predicate 31 |
| 9765 | OPC_CheckField, 28, 4, 15, // 14575: check Inst[31:28] == 0xf |
| 9766 | OPC_CheckField, 0, 1, 0, // 14579: check Inst[0] == 0x0 |
| 9767 | OPC_Decode, 154, 12, 183, 1, // 14583: decode to MVE_VQNEGs32 using decoder 183 |
| 9768 | // 14583: } |
| 9769 | 57, 15, // 14588: case 0x39: { |
| 9770 | OPC_CheckPredicate, 33, // 14590: check predicate 33 |
| 9771 | OPC_CheckField, 28, 4, 15, // 14592: check Inst[31:28] == 0xf |
| 9772 | OPC_CheckField, 0, 1, 0, // 14596: check Inst[0] == 0x0 |
| 9773 | OPC_Decode, 189, 11, 183, 1, // 14600: decode to MVE_VNEGf32 using decoder 183 |
| 9774 | // 14600: } |
| 9775 | 58, 15, // 14605: case 0x3a: { |
| 9776 | OPC_CheckPredicate, 33, // 14607: check predicate 33 |
| 9777 | OPC_CheckField, 28, 4, 15, // 14609: check Inst[31:28] == 0xf |
| 9778 | OPC_CheckField, 0, 1, 0, // 14613: check Inst[0] == 0x0 |
| 9779 | OPC_Decode, 142, 13, 183, 1, // 14617: decode to MVE_VRINTf32P using decoder 183 |
| 9780 | // 14617: } |
| 9781 | 59, 0, // 14622: case 0x3b: { |
| 9782 | OPC_CheckPredicate, 33, // 14624: check predicate 33 |
| 9783 | OPC_CheckField, 28, 4, 15, // 14626: check Inst[31:28] == 0xf |
| 9784 | OPC_CheckField, 0, 1, 0, // 14630: check Inst[0] == 0x0 |
| 9785 | OPC_Decode, 140, 9, 183, 1, // 14634: decode to MVE_VCVTu32f32z using decoder 183 |
| 9786 | // 14634: } |
| 9787 | // 14634: } // switch Inst[21:16] |
| 9788 | // 14634: } |
| 9789 | // 14634: } // switch Inst[12:6] |
| 9790 | // 14634: } |
| 9791 | 1, 0, // 14639: case 0x1: { |
| 9792 | OPC_SwitchField, 21, 1, // 14641: switch Inst[21] { |
| 9793 | 0, 245, 3, // 14644: case 0x0: { |
| 9794 | OPC_SwitchField, 20, 1, // 14647: switch Inst[20] { |
| 9795 | 0, 204, 2, // 14650: case 0x0: { |
| 9796 | OPC_SwitchField, 19, 1, // 14653: switch Inst[19] { |
| 9797 | 0, 163, 1, // 14656: case 0x0: { |
| 9798 | OPC_SwitchField, 5, 3, // 14659: switch Inst[7:5] { |
| 9799 | 2, 83, // 14662: case 0x2: { |
| 9800 | OPC_CheckField, 12, 1, 0, // 14664: check Inst[12] == 0x0 |
| 9801 | OPC_CheckField, 29, 3, 7, // 14668: check Inst[31:29] == 0x7 |
| 9802 | OPC_Scope, 21, // 14672: try { |
| 9803 | OPC_SwitchField, 8, 4, // 14674: switch Inst[11:8] { |
| 9804 | 14, 7, // 14677: case 0xe: { |
| 9805 | OPC_CheckPredicate, 31, // 14679: check predicate 31 |
| 9806 | OPC_Decode, 152, 11, 226, 1, // 14681: decode to MVE_VMOVimmi8 using decoder 226 |
| 9807 | // 14681: } |
| 9808 | 15, 0, // 14686: case 0xf: { |
| 9809 | OPC_CheckPredicate, 31, // 14688: check predicate 31 |
| 9810 | OPC_Decode, 148, 11, 226, 1, // 14690: decode to MVE_VMOVimmf32 using decoder 226 |
| 9811 | // 14690: } |
| 9812 | // 14690: } // switch Inst[11:8] |
| 9813 | OPC_Scope, 43, // 14695: } else try { |
| 9814 | OPC_SwitchField, 8, 1, // 14697: switch Inst[8] { |
| 9815 | 0, 11, // 14700: case 0x0: { |
| 9816 | OPC_CheckPredicate, 31, // 14702: check predicate 31 |
| 9817 | OPC_CheckField, 10, 2, 2, // 14704: check Inst[11:10] == 0x2 |
| 9818 | OPC_Decode, 149, 11, 226, 1, // 14708: decode to MVE_VMOVimmi16 using decoder 226 |
| 9819 | // 14708: } |
| 9820 | 1, 0, // 14713: case 0x1: { |
| 9821 | OPC_SwitchField, 11, 1, // 14715: switch Inst[11] { |
| 9822 | 0, 7, // 14718: case 0x0: { |
| 9823 | OPC_CheckPredicate, 31, // 14720: check predicate 31 |
| 9824 | OPC_Decode, 196, 11, 227, 1, // 14722: decode to MVE_VORRimmi32 using decoder 227 |
| 9825 | // 14722: } |
| 9826 | 1, 0, // 14727: case 0x1: { |
| 9827 | OPC_CheckPredicate, 31, // 14729: check predicate 31 |
| 9828 | OPC_CheckField, 10, 1, 0, // 14731: check Inst[10] == 0x0 |
| 9829 | OPC_Decode, 195, 11, 228, 1, // 14735: decode to MVE_VORRimmi16 using decoder 228 |
| 9830 | // 14735: } |
| 9831 | // 14735: } // switch Inst[11] |
| 9832 | // 14735: } |
| 9833 | // 14735: } // switch Inst[8] |
| 9834 | // 14735: } else try { |
| 9835 | OPC_CheckPredicate, 31, // 14740: check predicate 31 |
| 9836 | OPC_Decode, 150, 11, 226, 1, // 14742: decode to MVE_VMOVimmi32 using decoder 226 |
| 9837 | // 14742: } |
| 9838 | // 14742: } |
| 9839 | 3, 0, // 14747: case 0x3: { |
| 9840 | OPC_CheckField, 12, 1, 0, // 14749: check Inst[12] == 0x0 |
| 9841 | OPC_CheckField, 29, 3, 7, // 14753: check Inst[31:29] == 0x7 |
| 9842 | OPC_Scope, 11, // 14757: try { |
| 9843 | OPC_CheckField, 8, 4, 14, // 14759: check Inst[11:8] == 0xe |
| 9844 | OPC_CheckPredicate, 31, // 14763: check predicate 31 |
| 9845 | OPC_Decode, 151, 11, 226, 1, // 14765: decode to MVE_VMOVimmi64 using decoder 226 |
| 9846 | OPC_Scope, 43, // 14770: } else try { |
| 9847 | OPC_SwitchField, 8, 1, // 14772: switch Inst[8] { |
| 9848 | 0, 11, // 14775: case 0x0: { |
| 9849 | OPC_CheckPredicate, 31, // 14777: check predicate 31 |
| 9850 | OPC_CheckField, 10, 2, 2, // 14779: check Inst[11:10] == 0x2 |
| 9851 | OPC_Decode, 186, 11, 226, 1, // 14783: decode to MVE_VMVNimmi16 using decoder 226 |
| 9852 | // 14783: } |
| 9853 | 1, 0, // 14788: case 0x1: { |
| 9854 | OPC_SwitchField, 11, 1, // 14790: switch Inst[11] { |
| 9855 | 0, 7, // 14793: case 0x0: { |
| 9856 | OPC_CheckPredicate, 31, // 14795: check predicate 31 |
| 9857 | OPC_Decode, 188, 8, 227, 1, // 14797: decode to MVE_VBICimmi32 using decoder 227 |
| 9858 | // 14797: } |
| 9859 | 1, 0, // 14802: case 0x1: { |
| 9860 | OPC_CheckPredicate, 31, // 14804: check predicate 31 |
| 9861 | OPC_CheckField, 10, 1, 0, // 14806: check Inst[10] == 0x0 |
| 9862 | OPC_Decode, 187, 8, 228, 1, // 14810: decode to MVE_VBICimmi16 using decoder 228 |
| 9863 | // 14810: } |
| 9864 | // 14810: } // switch Inst[11] |
| 9865 | // 14810: } |
| 9866 | // 14810: } // switch Inst[8] |
| 9867 | // 14810: } else try { |
| 9868 | OPC_CheckPredicate, 31, // 14815: check predicate 31 |
| 9869 | OPC_Decode, 187, 11, 226, 1, // 14817: decode to MVE_VMVNimmi32 using decoder 226 |
| 9870 | // 14817: } |
| 9871 | // 14817: } |
| 9872 | // 14817: } // switch Inst[7:5] |
| 9873 | // 14817: } |
| 9874 | 1, 0, // 14822: case 0x1: { |
| 9875 | OPC_SwitchField, 6, 7, // 14824: switch Inst[12:6] { |
| 9876 | 1, 29, // 14827: case 0x1: { |
| 9877 | OPC_SwitchField, 28, 4, // 14829: switch Inst[31:28] { |
| 9878 | 14, 11, // 14832: case 0xe: { |
| 9879 | OPC_CheckPredicate, 31, // 14834: check predicate 31 |
| 9880 | OPC_CheckField, 0, 1, 0, // 14836: check Inst[0] == 0x0 |
| 9881 | OPC_Decode, 223, 13, 229, 1, // 14840: decode to MVE_VSHR_imms8 using decoder 229 |
| 9882 | // 14840: } |
| 9883 | 15, 0, // 14845: case 0xf: { |
| 9884 | OPC_CheckPredicate, 31, // 14847: check predicate 31 |
| 9885 | OPC_CheckField, 0, 1, 0, // 14849: check Inst[0] == 0x0 |
| 9886 | OPC_Decode, 226, 13, 229, 1, // 14853: decode to MVE_VSHR_immu8 using decoder 229 |
| 9887 | // 14853: } |
| 9888 | // 14853: } // switch Inst[31:28] |
| 9889 | // 14853: } |
| 9890 | 9, 29, // 14858: case 0x9: { |
| 9891 | OPC_SwitchField, 28, 4, // 14860: switch Inst[31:28] { |
| 9892 | 14, 11, // 14863: case 0xe: { |
| 9893 | OPC_CheckPredicate, 31, // 14865: check predicate 31 |
| 9894 | OPC_CheckField, 0, 1, 0, // 14867: check Inst[0] == 0x0 |
| 9895 | OPC_Decode, 179, 13, 229, 1, // 14871: decode to MVE_VRSHR_imms8 using decoder 229 |
| 9896 | // 14871: } |
| 9897 | 15, 0, // 14876: case 0xf: { |
| 9898 | OPC_CheckPredicate, 31, // 14878: check predicate 31 |
| 9899 | OPC_CheckField, 0, 1, 0, // 14880: check Inst[0] == 0x0 |
| 9900 | OPC_Decode, 182, 13, 229, 1, // 14884: decode to MVE_VRSHR_immu8 using decoder 229 |
| 9901 | // 14884: } |
| 9902 | // 14884: } // switch Inst[31:28] |
| 9903 | // 14884: } |
| 9904 | 17, 15, // 14889: case 0x11: { |
| 9905 | OPC_CheckPredicate, 31, // 14891: check predicate 31 |
| 9906 | OPC_CheckField, 28, 4, 15, // 14893: check Inst[31:28] == 0xf |
| 9907 | OPC_CheckField, 0, 1, 0, // 14897: check Inst[0] == 0x0 |
| 9908 | OPC_Decode, 232, 13, 220, 1, // 14901: decode to MVE_VSRIimm8 using decoder 220 |
| 9909 | // 14901: } |
| 9910 | 21, 29, // 14906: case 0x15: { |
| 9911 | OPC_SwitchField, 28, 4, // 14908: switch Inst[31:28] { |
| 9912 | 14, 11, // 14911: case 0xe: { |
| 9913 | OPC_CheckPredicate, 31, // 14913: check predicate 31 |
| 9914 | OPC_CheckField, 0, 1, 0, // 14915: check Inst[0] == 0x0 |
| 9915 | OPC_Decode, 210, 13, 222, 1, // 14919: decode to MVE_VSHL_immi8 using decoder 222 |
| 9916 | // 14919: } |
| 9917 | 15, 0, // 14924: case 0xf: { |
| 9918 | OPC_CheckPredicate, 31, // 14926: check predicate 31 |
| 9919 | OPC_CheckField, 0, 1, 0, // 14928: check Inst[0] == 0x0 |
| 9920 | OPC_Decode, 229, 13, 230, 1, // 14932: decode to MVE_VSLIimm8 using decoder 230 |
| 9921 | // 14932: } |
| 9922 | // 14932: } // switch Inst[31:28] |
| 9923 | // 14932: } |
| 9924 | 25, 15, // 14937: case 0x19: { |
| 9925 | OPC_CheckPredicate, 31, // 14939: check predicate 31 |
| 9926 | OPC_CheckField, 28, 4, 15, // 14941: check Inst[31:28] == 0xf |
| 9927 | OPC_CheckField, 0, 1, 0, // 14945: check Inst[0] == 0x0 |
| 9928 | OPC_Decode, 206, 12, 222, 1, // 14949: decode to MVE_VQSHLU_imms8 using decoder 222 |
| 9929 | // 14949: } |
| 9930 | 29, 0, // 14954: case 0x1d: { |
| 9931 | OPC_SwitchField, 28, 4, // 14956: switch Inst[31:28] { |
| 9932 | 14, 11, // 14959: case 0xe: { |
| 9933 | OPC_CheckPredicate, 31, // 14961: check predicate 31 |
| 9934 | OPC_CheckField, 0, 1, 0, // 14963: check Inst[0] == 0x0 |
| 9935 | OPC_Decode, 221, 12, 222, 1, // 14967: decode to MVE_VQSHLimms8 using decoder 222 |
| 9936 | // 14967: } |
| 9937 | 15, 0, // 14972: case 0xf: { |
| 9938 | OPC_CheckPredicate, 31, // 14974: check predicate 31 |
| 9939 | OPC_CheckField, 0, 1, 0, // 14976: check Inst[0] == 0x0 |
| 9940 | OPC_Decode, 224, 12, 222, 1, // 14980: decode to MVE_VQSHLimmu8 using decoder 222 |
| 9941 | // 14980: } |
| 9942 | // 14980: } // switch Inst[31:28] |
| 9943 | // 14980: } |
| 9944 | // 14980: } // switch Inst[12:6] |
| 9945 | // 14980: } |
| 9946 | // 14980: } // switch Inst[19] |
| 9947 | // 14980: } |
| 9948 | 1, 0, // 14985: case 0x1: { |
| 9949 | OPC_SwitchField, 6, 7, // 14987: switch Inst[12:6] { |
| 9950 | 1, 29, // 14990: case 0x1: { |
| 9951 | OPC_SwitchField, 28, 4, // 14992: switch Inst[31:28] { |
| 9952 | 14, 11, // 14995: case 0xe: { |
| 9953 | OPC_CheckPredicate, 31, // 14997: check predicate 31 |
| 9954 | OPC_CheckField, 0, 1, 0, // 14999: check Inst[0] == 0x0 |
| 9955 | OPC_Decode, 221, 13, 231, 1, // 15003: decode to MVE_VSHR_imms16 using decoder 231 |
| 9956 | // 15003: } |
| 9957 | 15, 0, // 15008: case 0xf: { |
| 9958 | OPC_CheckPredicate, 31, // 15010: check predicate 31 |
| 9959 | OPC_CheckField, 0, 1, 0, // 15012: check Inst[0] == 0x0 |
| 9960 | OPC_Decode, 224, 13, 231, 1, // 15016: decode to MVE_VSHR_immu16 using decoder 231 |
| 9961 | // 15016: } |
| 9962 | // 15016: } // switch Inst[31:28] |
| 9963 | // 15016: } |
| 9964 | 9, 29, // 15021: case 0x9: { |
| 9965 | OPC_SwitchField, 28, 4, // 15023: switch Inst[31:28] { |
| 9966 | 14, 11, // 15026: case 0xe: { |
| 9967 | OPC_CheckPredicate, 31, // 15028: check predicate 31 |
| 9968 | OPC_CheckField, 0, 1, 0, // 15030: check Inst[0] == 0x0 |
| 9969 | OPC_Decode, 177, 13, 231, 1, // 15034: decode to MVE_VRSHR_imms16 using decoder 231 |
| 9970 | // 15034: } |
| 9971 | 15, 0, // 15039: case 0xf: { |
| 9972 | OPC_CheckPredicate, 31, // 15041: check predicate 31 |
| 9973 | OPC_CheckField, 0, 1, 0, // 15043: check Inst[0] == 0x0 |
| 9974 | OPC_Decode, 180, 13, 231, 1, // 15047: decode to MVE_VRSHR_immu16 using decoder 231 |
| 9975 | // 15047: } |
| 9976 | // 15047: } // switch Inst[31:28] |
| 9977 | // 15047: } |
| 9978 | 17, 15, // 15052: case 0x11: { |
| 9979 | OPC_CheckPredicate, 31, // 15054: check predicate 31 |
| 9980 | OPC_CheckField, 28, 4, 15, // 15056: check Inst[31:28] == 0xf |
| 9981 | OPC_CheckField, 0, 1, 0, // 15060: check Inst[0] == 0x0 |
| 9982 | OPC_Decode, 230, 13, 221, 1, // 15064: decode to MVE_VSRIimm16 using decoder 221 |
| 9983 | // 15064: } |
| 9984 | 21, 29, // 15069: case 0x15: { |
| 9985 | OPC_SwitchField, 28, 4, // 15071: switch Inst[31:28] { |
| 9986 | 14, 11, // 15074: case 0xe: { |
| 9987 | OPC_CheckPredicate, 31, // 15076: check predicate 31 |
| 9988 | OPC_CheckField, 0, 1, 0, // 15078: check Inst[0] == 0x0 |
| 9989 | OPC_Decode, 208, 13, 223, 1, // 15082: decode to MVE_VSHL_immi16 using decoder 223 |
| 9990 | // 15082: } |
| 9991 | 15, 0, // 15087: case 0xf: { |
| 9992 | OPC_CheckPredicate, 31, // 15089: check predicate 31 |
| 9993 | OPC_CheckField, 0, 1, 0, // 15091: check Inst[0] == 0x0 |
| 9994 | OPC_Decode, 227, 13, 232, 1, // 15095: decode to MVE_VSLIimm16 using decoder 232 |
| 9995 | // 15095: } |
| 9996 | // 15095: } // switch Inst[31:28] |
| 9997 | // 15095: } |
| 9998 | 25, 15, // 15100: case 0x19: { |
| 9999 | OPC_CheckPredicate, 31, // 15102: check predicate 31 |
| 10000 | OPC_CheckField, 28, 4, 15, // 15104: check Inst[31:28] == 0xf |
| 10001 | OPC_CheckField, 0, 1, 0, // 15108: check Inst[0] == 0x0 |
| 10002 | OPC_Decode, 204, 12, 223, 1, // 15112: decode to MVE_VQSHLU_imms16 using decoder 223 |
| 10003 | // 15112: } |
| 10004 | 29, 0, // 15117: case 0x1d: { |
| 10005 | OPC_SwitchField, 28, 4, // 15119: switch Inst[31:28] { |
| 10006 | 14, 11, // 15122: case 0xe: { |
| 10007 | OPC_CheckPredicate, 31, // 15124: check predicate 31 |
| 10008 | OPC_CheckField, 0, 1, 0, // 15126: check Inst[0] == 0x0 |
| 10009 | OPC_Decode, 219, 12, 223, 1, // 15130: decode to MVE_VQSHLimms16 using decoder 223 |
| 10010 | // 15130: } |
| 10011 | 15, 0, // 15135: case 0xf: { |
| 10012 | OPC_CheckPredicate, 31, // 15137: check predicate 31 |
| 10013 | OPC_CheckField, 0, 1, 0, // 15139: check Inst[0] == 0x0 |
| 10014 | OPC_Decode, 222, 12, 223, 1, // 15143: decode to MVE_VQSHLimmu16 using decoder 223 |
| 10015 | // 15143: } |
| 10016 | // 15143: } // switch Inst[31:28] |
| 10017 | // 15143: } |
| 10018 | // 15143: } // switch Inst[12:6] |
| 10019 | // 15143: } |
| 10020 | // 15143: } // switch Inst[20] |
| 10021 | // 15143: } |
| 10022 | 1, 0, // 15148: case 0x1: { |
| 10023 | OPC_SwitchField, 6, 7, // 15150: switch Inst[12:6] { |
| 10024 | 1, 29, // 15153: case 0x1: { |
| 10025 | OPC_SwitchField, 28, 4, // 15155: switch Inst[31:28] { |
| 10026 | 14, 11, // 15158: case 0xe: { |
| 10027 | OPC_CheckPredicate, 31, // 15160: check predicate 31 |
| 10028 | OPC_CheckField, 0, 1, 0, // 15162: check Inst[0] == 0x0 |
| 10029 | OPC_Decode, 222, 13, 233, 1, // 15166: decode to MVE_VSHR_imms32 using decoder 233 |
| 10030 | // 15166: } |
| 10031 | 15, 0, // 15171: case 0xf: { |
| 10032 | OPC_CheckPredicate, 31, // 15173: check predicate 31 |
| 10033 | OPC_CheckField, 0, 1, 0, // 15175: check Inst[0] == 0x0 |
| 10034 | OPC_Decode, 225, 13, 233, 1, // 15179: decode to MVE_VSHR_immu32 using decoder 233 |
| 10035 | // 15179: } |
| 10036 | // 15179: } // switch Inst[31:28] |
| 10037 | // 15179: } |
| 10038 | 9, 29, // 15184: case 0x9: { |
| 10039 | OPC_SwitchField, 28, 4, // 15186: switch Inst[31:28] { |
| 10040 | 14, 11, // 15189: case 0xe: { |
| 10041 | OPC_CheckPredicate, 31, // 15191: check predicate 31 |
| 10042 | OPC_CheckField, 0, 1, 0, // 15193: check Inst[0] == 0x0 |
| 10043 | OPC_Decode, 178, 13, 233, 1, // 15197: decode to MVE_VRSHR_imms32 using decoder 233 |
| 10044 | // 15197: } |
| 10045 | 15, 0, // 15202: case 0xf: { |
| 10046 | OPC_CheckPredicate, 31, // 15204: check predicate 31 |
| 10047 | OPC_CheckField, 0, 1, 0, // 15206: check Inst[0] == 0x0 |
| 10048 | OPC_Decode, 181, 13, 233, 1, // 15210: decode to MVE_VRSHR_immu32 using decoder 233 |
| 10049 | // 15210: } |
| 10050 | // 15210: } // switch Inst[31:28] |
| 10051 | // 15210: } |
| 10052 | 17, 15, // 15215: case 0x11: { |
| 10053 | OPC_CheckPredicate, 31, // 15217: check predicate 31 |
| 10054 | OPC_CheckField, 28, 4, 15, // 15219: check Inst[31:28] == 0xf |
| 10055 | OPC_CheckField, 0, 1, 0, // 15223: check Inst[0] == 0x0 |
| 10056 | OPC_Decode, 231, 13, 234, 1, // 15227: decode to MVE_VSRIimm32 using decoder 234 |
| 10057 | // 15227: } |
| 10058 | 21, 29, // 15232: case 0x15: { |
| 10059 | OPC_SwitchField, 28, 4, // 15234: switch Inst[31:28] { |
| 10060 | 14, 11, // 15237: case 0xe: { |
| 10061 | OPC_CheckPredicate, 31, // 15239: check predicate 31 |
| 10062 | OPC_CheckField, 0, 1, 0, // 15241: check Inst[0] == 0x0 |
| 10063 | OPC_Decode, 209, 13, 235, 1, // 15245: decode to MVE_VSHL_immi32 using decoder 235 |
| 10064 | // 15245: } |
| 10065 | 15, 0, // 15250: case 0xf: { |
| 10066 | OPC_CheckPredicate, 31, // 15252: check predicate 31 |
| 10067 | OPC_CheckField, 0, 1, 0, // 15254: check Inst[0] == 0x0 |
| 10068 | OPC_Decode, 228, 13, 236, 1, // 15258: decode to MVE_VSLIimm32 using decoder 236 |
| 10069 | // 15258: } |
| 10070 | // 15258: } // switch Inst[31:28] |
| 10071 | // 15258: } |
| 10072 | 25, 15, // 15263: case 0x19: { |
| 10073 | OPC_CheckPredicate, 31, // 15265: check predicate 31 |
| 10074 | OPC_CheckField, 28, 4, 15, // 15267: check Inst[31:28] == 0xf |
| 10075 | OPC_CheckField, 0, 1, 0, // 15271: check Inst[0] == 0x0 |
| 10076 | OPC_Decode, 205, 12, 235, 1, // 15275: decode to MVE_VQSHLU_imms32 using decoder 235 |
| 10077 | // 15275: } |
| 10078 | 29, 29, // 15280: case 0x1d: { |
| 10079 | OPC_SwitchField, 28, 4, // 15282: switch Inst[31:28] { |
| 10080 | 14, 11, // 15285: case 0xe: { |
| 10081 | OPC_CheckPredicate, 31, // 15287: check predicate 31 |
| 10082 | OPC_CheckField, 0, 1, 0, // 15289: check Inst[0] == 0x0 |
| 10083 | OPC_Decode, 220, 12, 235, 1, // 15293: decode to MVE_VQSHLimms32 using decoder 235 |
| 10084 | // 15293: } |
| 10085 | 15, 0, // 15298: case 0xf: { |
| 10086 | OPC_CheckPredicate, 31, // 15300: check predicate 31 |
| 10087 | OPC_CheckField, 0, 1, 0, // 15302: check Inst[0] == 0x0 |
| 10088 | OPC_Decode, 223, 12, 235, 1, // 15306: decode to MVE_VQSHLimmu32 using decoder 235 |
| 10089 | // 15306: } |
| 10090 | // 15306: } // switch Inst[31:28] |
| 10091 | // 15306: } |
| 10092 | 49, 37, // 15311: case 0x31: { |
| 10093 | OPC_SwitchField, 28, 4, // 15313: switch Inst[31:28] { |
| 10094 | 14, 15, // 15316: case 0xe: { |
| 10095 | OPC_CheckPredicate, 33, // 15318: check predicate 33 |
| 10096 | OPC_CheckField, 20, 1, 1, // 15320: check Inst[20] == 0x1 |
| 10097 | OPC_CheckField, 0, 1, 0, // 15324: check Inst[0] == 0x0 |
| 10098 | OPC_Decode, 235, 8, 237, 1, // 15328: decode to MVE_VCVTf16s16_fix using decoder 237 |
| 10099 | // 15328: } |
| 10100 | 15, 0, // 15333: case 0xf: { |
| 10101 | OPC_CheckPredicate, 33, // 15335: check predicate 33 |
| 10102 | OPC_CheckField, 20, 1, 1, // 15337: check Inst[20] == 0x1 |
| 10103 | OPC_CheckField, 0, 1, 0, // 15341: check Inst[0] == 0x0 |
| 10104 | OPC_Decode, 237, 8, 237, 1, // 15345: decode to MVE_VCVTf16u16_fix using decoder 237 |
| 10105 | // 15345: } |
| 10106 | // 15345: } // switch Inst[31:28] |
| 10107 | // 15345: } |
| 10108 | 53, 37, // 15350: case 0x35: { |
| 10109 | OPC_SwitchField, 28, 4, // 15352: switch Inst[31:28] { |
| 10110 | 14, 15, // 15355: case 0xe: { |
| 10111 | OPC_CheckPredicate, 33, // 15357: check predicate 33 |
| 10112 | OPC_CheckField, 20, 1, 1, // 15359: check Inst[20] == 0x1 |
| 10113 | OPC_CheckField, 0, 1, 0, // 15363: check Inst[0] == 0x0 |
| 10114 | OPC_Decode, 245, 8, 237, 1, // 15367: decode to MVE_VCVTs16f16_fix using decoder 237 |
| 10115 | // 15367: } |
| 10116 | 15, 0, // 15372: case 0xf: { |
| 10117 | OPC_CheckPredicate, 33, // 15374: check predicate 33 |
| 10118 | OPC_CheckField, 20, 1, 1, // 15376: check Inst[20] == 0x1 |
| 10119 | OPC_CheckField, 0, 1, 0, // 15380: check Inst[0] == 0x0 |
| 10120 | OPC_Decode, 129, 9, 237, 1, // 15384: decode to MVE_VCVTu16f16_fix using decoder 237 |
| 10121 | // 15384: } |
| 10122 | // 15384: } // switch Inst[31:28] |
| 10123 | // 15384: } |
| 10124 | 57, 29, // 15389: case 0x39: { |
| 10125 | OPC_SwitchField, 28, 4, // 15391: switch Inst[31:28] { |
| 10126 | 14, 11, // 15394: case 0xe: { |
| 10127 | OPC_CheckPredicate, 33, // 15396: check predicate 33 |
| 10128 | OPC_CheckField, 0, 1, 0, // 15398: check Inst[0] == 0x0 |
| 10129 | OPC_Decode, 241, 8, 237, 1, // 15402: decode to MVE_VCVTf32s32_fix using decoder 237 |
| 10130 | // 15402: } |
| 10131 | 15, 0, // 15407: case 0xf: { |
| 10132 | OPC_CheckPredicate, 33, // 15409: check predicate 33 |
| 10133 | OPC_CheckField, 0, 1, 0, // 15411: check Inst[0] == 0x0 |
| 10134 | OPC_Decode, 243, 8, 237, 1, // 15415: decode to MVE_VCVTf32u32_fix using decoder 237 |
| 10135 | // 15415: } |
| 10136 | // 15415: } // switch Inst[31:28] |
| 10137 | // 15415: } |
| 10138 | 61, 0, // 15420: case 0x3d: { |
| 10139 | OPC_SwitchField, 28, 4, // 15422: switch Inst[31:28] { |
| 10140 | 14, 11, // 15425: case 0xe: { |
| 10141 | OPC_CheckPredicate, 33, // 15427: check predicate 33 |
| 10142 | OPC_CheckField, 0, 1, 0, // 15429: check Inst[0] == 0x0 |
| 10143 | OPC_Decode, 251, 8, 237, 1, // 15433: decode to MVE_VCVTs32f32_fix using decoder 237 |
| 10144 | // 15433: } |
| 10145 | 15, 0, // 15438: case 0xf: { |
| 10146 | OPC_CheckPredicate, 33, // 15440: check predicate 33 |
| 10147 | OPC_CheckField, 0, 1, 0, // 15442: check Inst[0] == 0x0 |
| 10148 | OPC_Decode, 135, 9, 237, 1, // 15446: decode to MVE_VCVTu32f32_fix using decoder 237 |
| 10149 | // 15446: } |
| 10150 | // 15446: } // switch Inst[31:28] |
| 10151 | // 15446: } |
| 10152 | // 15446: } // switch Inst[12:6] |
| 10153 | // 15446: } |
| 10154 | // 15446: } // switch Inst[21] |
| 10155 | // 15446: } |
| 10156 | // 15446: } // switch Inst[4] |
| 10157 | // 15446: } |
| 10158 | // 15446: } // switch Inst[24:23] |
| 10159 | // 15446: } |
| 10160 | // 15446: } // switch Inst[27:25] |
| 10161 | }; |
| 10162 | static const uint8_t DecoderTableNEONData32[11845] = { |
| 10163 | OPC_SwitchField, 4, 1, // 0: switch Inst[4] { |
| 10164 | 0, 157, 51, // 3: case 0x0: { |
| 10165 | OPC_SwitchField, 20, 2, // 6: switch Inst[21:20] { |
| 10166 | 0, 140, 8, // 9: case 0x0: { |
| 10167 | OPC_SwitchField, 8, 4, // 12: switch Inst[11:8] { |
| 10168 | 0, 79, // 15: case 0x0: { |
| 10169 | OPC_SwitchField, 23, 9, // 17: switch Inst[31:23] { |
| 10170 | 228, 3, 21, // 20: case 0x1e4: { |
| 10171 | OPC_SwitchField, 6, 1, // 23: switch Inst[6] { |
| 10172 | 0, 7, // 26: case 0x0: { |
| 10173 | OPC_CheckPredicate, 35, // 28: check predicate 35 |
| 10174 | OPC_Decode, 206, 19, 238, 1, // 30: decode to VHADDsv8i8 using decoder 238 |
| 10175 | // 30: } |
| 10176 | 1, 0, // 35: case 0x1: { |
| 10177 | OPC_CheckPredicate, 35, // 37: check predicate 35 |
| 10178 | OPC_Decode, 201, 19, 239, 1, // 39: decode to VHADDsv16i8 using decoder 239 |
| 10179 | // 39: } |
| 10180 | // 39: } // switch Inst[6] |
| 10181 | // 39: } |
| 10182 | 229, 3, 11, // 44: case 0x1e5: { |
| 10183 | OPC_CheckPredicate, 35, // 47: check predicate 35 |
| 10184 | OPC_CheckField, 6, 1, 0, // 49: check Inst[6] == 0x0 |
| 10185 | OPC_Decode, 249, 16, 240, 1, // 53: decode to VADDLsv8i16 using decoder 240 |
| 10186 | // 53: } |
| 10187 | 230, 3, 21, // 58: case 0x1e6: { |
| 10188 | OPC_SwitchField, 6, 1, // 61: switch Inst[6] { |
| 10189 | 0, 7, // 64: case 0x0: { |
| 10190 | OPC_CheckPredicate, 35, // 66: check predicate 35 |
| 10191 | OPC_Decode, 212, 19, 238, 1, // 68: decode to VHADDuv8i8 using decoder 238 |
| 10192 | // 68: } |
| 10193 | 1, 0, // 73: case 0x1: { |
| 10194 | OPC_CheckPredicate, 35, // 75: check predicate 35 |
| 10195 | OPC_Decode, 207, 19, 239, 1, // 77: decode to VHADDuv16i8 using decoder 239 |
| 10196 | // 77: } |
| 10197 | // 77: } // switch Inst[6] |
| 10198 | // 77: } |
| 10199 | 231, 3, 0, // 82: case 0x1e7: { |
| 10200 | OPC_CheckPredicate, 35, // 85: check predicate 35 |
| 10201 | OPC_CheckField, 6, 1, 0, // 87: check Inst[6] == 0x0 |
| 10202 | OPC_Decode, 252, 16, 240, 1, // 91: decode to VADDLuv8i16 using decoder 240 |
| 10203 | // 91: } |
| 10204 | // 91: } // switch Inst[31:23] |
| 10205 | // 91: } |
| 10206 | 1, 79, // 96: case 0x1: { |
| 10207 | OPC_SwitchField, 23, 9, // 98: switch Inst[31:23] { |
| 10208 | 228, 3, 21, // 101: case 0x1e4: { |
| 10209 | OPC_SwitchField, 6, 1, // 104: switch Inst[6] { |
| 10210 | 0, 7, // 107: case 0x0: { |
| 10211 | OPC_CheckPredicate, 35, // 109: check predicate 35 |
| 10212 | OPC_Decode, 188, 26, 238, 1, // 111: decode to VRHADDsv8i8 using decoder 238 |
| 10213 | // 111: } |
| 10214 | 1, 0, // 116: case 0x1: { |
| 10215 | OPC_CheckPredicate, 35, // 118: check predicate 35 |
| 10216 | OPC_Decode, 183, 26, 239, 1, // 120: decode to VRHADDsv16i8 using decoder 239 |
| 10217 | // 120: } |
| 10218 | // 120: } // switch Inst[6] |
| 10219 | // 120: } |
| 10220 | 229, 3, 11, // 125: case 0x1e5: { |
| 10221 | OPC_CheckPredicate, 35, // 128: check predicate 35 |
| 10222 | OPC_CheckField, 6, 1, 0, // 130: check Inst[6] == 0x0 |
| 10223 | OPC_Decode, 128, 17, 241, 1, // 134: decode to VADDWsv8i16 using decoder 241 |
| 10224 | // 134: } |
| 10225 | 230, 3, 21, // 139: case 0x1e6: { |
| 10226 | OPC_SwitchField, 6, 1, // 142: switch Inst[6] { |
| 10227 | 0, 7, // 145: case 0x0: { |
| 10228 | OPC_CheckPredicate, 35, // 147: check predicate 35 |
| 10229 | OPC_Decode, 194, 26, 238, 1, // 149: decode to VRHADDuv8i8 using decoder 238 |
| 10230 | // 149: } |
| 10231 | 1, 0, // 154: case 0x1: { |
| 10232 | OPC_CheckPredicate, 35, // 156: check predicate 35 |
| 10233 | OPC_Decode, 189, 26, 239, 1, // 158: decode to VRHADDuv16i8 using decoder 239 |
| 10234 | // 158: } |
| 10235 | // 158: } // switch Inst[6] |
| 10236 | // 158: } |
| 10237 | 231, 3, 0, // 163: case 0x1e7: { |
| 10238 | OPC_CheckPredicate, 35, // 166: check predicate 35 |
| 10239 | OPC_CheckField, 6, 1, 0, // 168: check Inst[6] == 0x0 |
| 10240 | OPC_Decode, 131, 17, 241, 1, // 172: decode to VADDWuv8i16 using decoder 241 |
| 10241 | // 172: } |
| 10242 | // 172: } // switch Inst[31:23] |
| 10243 | // 172: } |
| 10244 | 2, 79, // 177: case 0x2: { |
| 10245 | OPC_SwitchField, 23, 9, // 179: switch Inst[31:23] { |
| 10246 | 228, 3, 21, // 182: case 0x1e4: { |
| 10247 | OPC_SwitchField, 6, 1, // 185: switch Inst[6] { |
| 10248 | 0, 7, // 188: case 0x0: { |
| 10249 | OPC_CheckPredicate, 35, // 190: check predicate 35 |
| 10250 | OPC_Decode, 218, 19, 238, 1, // 192: decode to VHSUBsv8i8 using decoder 238 |
| 10251 | // 192: } |
| 10252 | 1, 0, // 197: case 0x1: { |
| 10253 | OPC_CheckPredicate, 35, // 199: check predicate 35 |
| 10254 | OPC_Decode, 213, 19, 239, 1, // 201: decode to VHSUBsv16i8 using decoder 239 |
| 10255 | // 201: } |
| 10256 | // 201: } // switch Inst[6] |
| 10257 | // 201: } |
| 10258 | 229, 3, 11, // 206: case 0x1e5: { |
| 10259 | OPC_CheckPredicate, 35, // 209: check predicate 35 |
| 10260 | OPC_CheckField, 6, 1, 0, // 211: check Inst[6] == 0x0 |
| 10261 | OPC_Decode, 203, 30, 240, 1, // 215: decode to VSUBLsv8i16 using decoder 240 |
| 10262 | // 215: } |
| 10263 | 230, 3, 21, // 220: case 0x1e6: { |
| 10264 | OPC_SwitchField, 6, 1, // 223: switch Inst[6] { |
| 10265 | 0, 7, // 226: case 0x0: { |
| 10266 | OPC_CheckPredicate, 35, // 228: check predicate 35 |
| 10267 | OPC_Decode, 224, 19, 238, 1, // 230: decode to VHSUBuv8i8 using decoder 238 |
| 10268 | // 230: } |
| 10269 | 1, 0, // 235: case 0x1: { |
| 10270 | OPC_CheckPredicate, 35, // 237: check predicate 35 |
| 10271 | OPC_Decode, 219, 19, 239, 1, // 239: decode to VHSUBuv16i8 using decoder 239 |
| 10272 | // 239: } |
| 10273 | // 239: } // switch Inst[6] |
| 10274 | // 239: } |
| 10275 | 231, 3, 0, // 244: case 0x1e7: { |
| 10276 | OPC_CheckPredicate, 35, // 247: check predicate 35 |
| 10277 | OPC_CheckField, 6, 1, 0, // 249: check Inst[6] == 0x0 |
| 10278 | OPC_Decode, 206, 30, 240, 1, // 253: decode to VSUBLuv8i16 using decoder 240 |
| 10279 | // 253: } |
| 10280 | // 253: } // switch Inst[31:23] |
| 10281 | // 253: } |
| 10282 | 3, 79, // 258: case 0x3: { |
| 10283 | OPC_SwitchField, 23, 9, // 260: switch Inst[31:23] { |
| 10284 | 228, 3, 21, // 263: case 0x1e4: { |
| 10285 | OPC_SwitchField, 6, 1, // 266: switch Inst[6] { |
| 10286 | 0, 7, // 269: case 0x0: { |
| 10287 | OPC_CheckPredicate, 35, // 271: check predicate 35 |
| 10288 | OPC_Decode, 223, 17, 238, 1, // 273: decode to VCGTsv8i8 using decoder 238 |
| 10289 | // 273: } |
| 10290 | 1, 0, // 278: case 0x1: { |
| 10291 | OPC_CheckPredicate, 35, // 280: check predicate 35 |
| 10292 | OPC_Decode, 218, 17, 239, 1, // 282: decode to VCGTsv16i8 using decoder 239 |
| 10293 | // 282: } |
| 10294 | // 282: } // switch Inst[6] |
| 10295 | // 282: } |
| 10296 | 229, 3, 11, // 287: case 0x1e5: { |
| 10297 | OPC_CheckPredicate, 35, // 290: check predicate 35 |
| 10298 | OPC_CheckField, 6, 1, 0, // 292: check Inst[6] == 0x0 |
| 10299 | OPC_Decode, 210, 30, 241, 1, // 296: decode to VSUBWsv8i16 using decoder 241 |
| 10300 | // 296: } |
| 10301 | 230, 3, 21, // 301: case 0x1e6: { |
| 10302 | OPC_SwitchField, 6, 1, // 304: switch Inst[6] { |
| 10303 | 0, 7, // 307: case 0x0: { |
| 10304 | OPC_CheckPredicate, 35, // 309: check predicate 35 |
| 10305 | OPC_Decode, 229, 17, 238, 1, // 311: decode to VCGTuv8i8 using decoder 238 |
| 10306 | // 311: } |
| 10307 | 1, 0, // 316: case 0x1: { |
| 10308 | OPC_CheckPredicate, 35, // 318: check predicate 35 |
| 10309 | OPC_Decode, 224, 17, 239, 1, // 320: decode to VCGTuv16i8 using decoder 239 |
| 10310 | // 320: } |
| 10311 | // 320: } // switch Inst[6] |
| 10312 | // 320: } |
| 10313 | 231, 3, 0, // 325: case 0x1e7: { |
| 10314 | OPC_CheckPredicate, 35, // 328: check predicate 35 |
| 10315 | OPC_CheckField, 6, 1, 0, // 330: check Inst[6] == 0x0 |
| 10316 | OPC_Decode, 213, 30, 241, 1, // 334: decode to VSUBWuv8i16 using decoder 241 |
| 10317 | // 334: } |
| 10318 | // 334: } // switch Inst[31:23] |
| 10319 | // 334: } |
| 10320 | 4, 79, // 339: case 0x4: { |
| 10321 | OPC_SwitchField, 23, 9, // 341: switch Inst[31:23] { |
| 10322 | 228, 3, 21, // 344: case 0x1e4: { |
| 10323 | OPC_SwitchField, 6, 1, // 347: switch Inst[6] { |
| 10324 | 0, 7, // 350: case 0x0: { |
| 10325 | OPC_CheckPredicate, 35, // 352: check predicate 35 |
| 10326 | OPC_Decode, 221, 27, 242, 1, // 354: decode to VSHLsv8i8 using decoder 242 |
| 10327 | // 354: } |
| 10328 | 1, 0, // 359: case 0x1: { |
| 10329 | OPC_CheckPredicate, 35, // 361: check predicate 35 |
| 10330 | OPC_Decode, 214, 27, 243, 1, // 363: decode to VSHLsv16i8 using decoder 243 |
| 10331 | // 363: } |
| 10332 | // 363: } // switch Inst[6] |
| 10333 | // 363: } |
| 10334 | 229, 3, 11, // 368: case 0x1e5: { |
| 10335 | OPC_CheckPredicate, 35, // 371: check predicate 35 |
| 10336 | OPC_CheckField, 6, 1, 0, // 373: check Inst[6] == 0x0 |
| 10337 | OPC_Decode, 246, 16, 244, 1, // 377: decode to VADDHNv8i8 using decoder 244 |
| 10338 | // 377: } |
| 10339 | 230, 3, 21, // 382: case 0x1e6: { |
| 10340 | OPC_SwitchField, 6, 1, // 385: switch Inst[6] { |
| 10341 | 0, 7, // 388: case 0x0: { |
| 10342 | OPC_CheckPredicate, 35, // 390: check predicate 35 |
| 10343 | OPC_Decode, 229, 27, 242, 1, // 392: decode to VSHLuv8i8 using decoder 242 |
| 10344 | // 392: } |
| 10345 | 1, 0, // 397: case 0x1: { |
| 10346 | OPC_CheckPredicate, 35, // 399: check predicate 35 |
| 10347 | OPC_Decode, 222, 27, 243, 1, // 401: decode to VSHLuv16i8 using decoder 243 |
| 10348 | // 401: } |
| 10349 | // 401: } // switch Inst[6] |
| 10350 | // 401: } |
| 10351 | 231, 3, 0, // 406: case 0x1e7: { |
| 10352 | OPC_CheckPredicate, 35, // 409: check predicate 35 |
| 10353 | OPC_CheckField, 6, 1, 0, // 411: check Inst[6] == 0x0 |
| 10354 | OPC_Decode, 160, 26, 244, 1, // 415: decode to VRADDHNv8i8 using decoder 244 |
| 10355 | // 415: } |
| 10356 | // 415: } // switch Inst[31:23] |
| 10357 | // 415: } |
| 10358 | 5, 79, // 420: case 0x5: { |
| 10359 | OPC_SwitchField, 23, 9, // 422: switch Inst[31:23] { |
| 10360 | 228, 3, 21, // 425: case 0x1e4: { |
| 10361 | OPC_SwitchField, 6, 1, // 428: switch Inst[6] { |
| 10362 | 0, 7, // 431: case 0x0: { |
| 10363 | OPC_CheckPredicate, 35, // 433: check predicate 35 |
| 10364 | OPC_Decode, 247, 26, 242, 1, // 435: decode to VRSHLsv8i8 using decoder 242 |
| 10365 | // 435: } |
| 10366 | 1, 0, // 440: case 0x1: { |
| 10367 | OPC_CheckPredicate, 35, // 442: check predicate 35 |
| 10368 | OPC_Decode, 240, 26, 243, 1, // 444: decode to VRSHLsv16i8 using decoder 243 |
| 10369 | // 444: } |
| 10370 | // 444: } // switch Inst[6] |
| 10371 | // 444: } |
| 10372 | 229, 3, 11, // 449: case 0x1e5: { |
| 10373 | OPC_CheckPredicate, 35, // 452: check predicate 35 |
| 10374 | OPC_CheckField, 6, 1, 0, // 454: check Inst[6] == 0x0 |
| 10375 | OPC_Decode, 183, 16, 245, 1, // 458: decode to VABALsv8i16 using decoder 245 |
| 10376 | // 458: } |
| 10377 | 230, 3, 21, // 463: case 0x1e6: { |
| 10378 | OPC_SwitchField, 6, 1, // 466: switch Inst[6] { |
| 10379 | 0, 7, // 469: case 0x0: { |
| 10380 | OPC_CheckPredicate, 35, // 471: check predicate 35 |
| 10381 | OPC_Decode, 255, 26, 242, 1, // 473: decode to VRSHLuv8i8 using decoder 242 |
| 10382 | // 473: } |
| 10383 | 1, 0, // 478: case 0x1: { |
| 10384 | OPC_CheckPredicate, 35, // 480: check predicate 35 |
| 10385 | OPC_Decode, 248, 26, 243, 1, // 482: decode to VRSHLuv16i8 using decoder 243 |
| 10386 | // 482: } |
| 10387 | // 482: } // switch Inst[6] |
| 10388 | // 482: } |
| 10389 | 231, 3, 0, // 487: case 0x1e7: { |
| 10390 | OPC_CheckPredicate, 35, // 490: check predicate 35 |
| 10391 | OPC_CheckField, 6, 1, 0, // 492: check Inst[6] == 0x0 |
| 10392 | OPC_Decode, 186, 16, 245, 1, // 496: decode to VABALuv8i16 using decoder 245 |
| 10393 | // 496: } |
| 10394 | // 496: } // switch Inst[31:23] |
| 10395 | // 496: } |
| 10396 | 6, 79, // 501: case 0x6: { |
| 10397 | OPC_SwitchField, 23, 9, // 503: switch Inst[31:23] { |
| 10398 | 228, 3, 21, // 506: case 0x1e4: { |
| 10399 | OPC_SwitchField, 6, 1, // 509: switch Inst[6] { |
| 10400 | 0, 7, // 512: case 0x0: { |
| 10401 | OPC_CheckPredicate, 35, // 514: check predicate 35 |
| 10402 | OPC_Decode, 244, 22, 238, 1, // 516: decode to VMAXsv8i8 using decoder 238 |
| 10403 | // 516: } |
| 10404 | 1, 0, // 521: case 0x1: { |
| 10405 | OPC_CheckPredicate, 35, // 523: check predicate 35 |
| 10406 | OPC_Decode, 239, 22, 239, 1, // 525: decode to VMAXsv16i8 using decoder 239 |
| 10407 | // 525: } |
| 10408 | // 525: } // switch Inst[6] |
| 10409 | // 525: } |
| 10410 | 229, 3, 11, // 530: case 0x1e5: { |
| 10411 | OPC_CheckPredicate, 35, // 533: check predicate 35 |
| 10412 | OPC_CheckField, 6, 1, 0, // 535: check Inst[6] == 0x0 |
| 10413 | OPC_Decode, 200, 30, 244, 1, // 539: decode to VSUBHNv8i8 using decoder 244 |
| 10414 | // 539: } |
| 10415 | 230, 3, 21, // 544: case 0x1e6: { |
| 10416 | OPC_SwitchField, 6, 1, // 547: switch Inst[6] { |
| 10417 | 0, 7, // 550: case 0x0: { |
| 10418 | OPC_CheckPredicate, 35, // 552: check predicate 35 |
| 10419 | OPC_Decode, 250, 22, 238, 1, // 554: decode to VMAXuv8i8 using decoder 238 |
| 10420 | // 554: } |
| 10421 | 1, 0, // 559: case 0x1: { |
| 10422 | OPC_CheckPredicate, 35, // 561: check predicate 35 |
| 10423 | OPC_Decode, 245, 22, 239, 1, // 563: decode to VMAXuv16i8 using decoder 239 |
| 10424 | // 563: } |
| 10425 | // 563: } // switch Inst[6] |
| 10426 | // 563: } |
| 10427 | 231, 3, 0, // 568: case 0x1e7: { |
| 10428 | OPC_CheckPredicate, 35, // 571: check predicate 35 |
| 10429 | OPC_CheckField, 6, 1, 0, // 573: check Inst[6] == 0x0 |
| 10430 | OPC_Decode, 175, 27, 244, 1, // 577: decode to VRSUBHNv8i8 using decoder 244 |
| 10431 | // 577: } |
| 10432 | // 577: } // switch Inst[31:23] |
| 10433 | // 577: } |
| 10434 | 7, 79, // 582: case 0x7: { |
| 10435 | OPC_SwitchField, 23, 9, // 584: switch Inst[31:23] { |
| 10436 | 228, 3, 21, // 587: case 0x1e4: { |
| 10437 | OPC_SwitchField, 6, 1, // 590: switch Inst[6] { |
| 10438 | 0, 7, // 593: case 0x0: { |
| 10439 | OPC_CheckPredicate, 35, // 595: check predicate 35 |
| 10440 | OPC_Decode, 214, 16, 238, 1, // 597: decode to VABDsv8i8 using decoder 238 |
| 10441 | // 597: } |
| 10442 | 1, 0, // 602: case 0x1: { |
| 10443 | OPC_CheckPredicate, 35, // 604: check predicate 35 |
| 10444 | OPC_Decode, 209, 16, 239, 1, // 606: decode to VABDsv16i8 using decoder 239 |
| 10445 | // 606: } |
| 10446 | // 606: } // switch Inst[6] |
| 10447 | // 606: } |
| 10448 | 229, 3, 11, // 611: case 0x1e5: { |
| 10449 | OPC_CheckPredicate, 35, // 614: check predicate 35 |
| 10450 | OPC_CheckField, 6, 1, 0, // 616: check Inst[6] == 0x0 |
| 10451 | OPC_Decode, 201, 16, 240, 1, // 620: decode to VABDLsv8i16 using decoder 240 |
| 10452 | // 620: } |
| 10453 | 230, 3, 21, // 625: case 0x1e6: { |
| 10454 | OPC_SwitchField, 6, 1, // 628: switch Inst[6] { |
| 10455 | 0, 7, // 631: case 0x0: { |
| 10456 | OPC_CheckPredicate, 35, // 633: check predicate 35 |
| 10457 | OPC_Decode, 220, 16, 238, 1, // 635: decode to VABDuv8i8 using decoder 238 |
| 10458 | // 635: } |
| 10459 | 1, 0, // 640: case 0x1: { |
| 10460 | OPC_CheckPredicate, 35, // 642: check predicate 35 |
| 10461 | OPC_Decode, 215, 16, 239, 1, // 644: decode to VABDuv16i8 using decoder 239 |
| 10462 | // 644: } |
| 10463 | // 644: } // switch Inst[6] |
| 10464 | // 644: } |
| 10465 | 231, 3, 0, // 649: case 0x1e7: { |
| 10466 | OPC_CheckPredicate, 35, // 652: check predicate 35 |
| 10467 | OPC_CheckField, 6, 1, 0, // 654: check Inst[6] == 0x0 |
| 10468 | OPC_Decode, 204, 16, 240, 1, // 658: decode to VABDLuv8i16 using decoder 240 |
| 10469 | // 658: } |
| 10470 | // 658: } // switch Inst[31:23] |
| 10471 | // 658: } |
| 10472 | 8, 79, // 663: case 0x8: { |
| 10473 | OPC_SwitchField, 23, 9, // 665: switch Inst[31:23] { |
| 10474 | 228, 3, 21, // 668: case 0x1e4: { |
| 10475 | OPC_SwitchField, 6, 1, // 671: switch Inst[6] { |
| 10476 | 0, 7, // 674: case 0x0: { |
| 10477 | OPC_CheckPredicate, 35, // 676: check predicate 35 |
| 10478 | OPC_Decode, 143, 17, 238, 1, // 678: decode to VADDv8i8 using decoder 238 |
| 10479 | // 678: } |
| 10480 | 1, 0, // 683: case 0x1: { |
| 10481 | OPC_CheckPredicate, 35, // 685: check predicate 35 |
| 10482 | OPC_Decode, 136, 17, 239, 1, // 687: decode to VADDv16i8 using decoder 239 |
| 10483 | // 687: } |
| 10484 | // 687: } // switch Inst[6] |
| 10485 | // 687: } |
| 10486 | 229, 3, 11, // 692: case 0x1e5: { |
| 10487 | OPC_CheckPredicate, 35, // 695: check predicate 35 |
| 10488 | OPC_CheckField, 6, 1, 0, // 697: check Inst[6] == 0x0 |
| 10489 | OPC_Decode, 147, 23, 245, 1, // 701: decode to VMLALsv8i16 using decoder 245 |
| 10490 | // 701: } |
| 10491 | 230, 3, 21, // 706: case 0x1e6: { |
| 10492 | OPC_SwitchField, 6, 1, // 709: switch Inst[6] { |
| 10493 | 0, 7, // 712: case 0x0: { |
| 10494 | OPC_CheckPredicate, 35, // 714: check predicate 35 |
| 10495 | OPC_Decode, 225, 30, 238, 1, // 716: decode to VSUBv8i8 using decoder 238 |
| 10496 | // 716: } |
| 10497 | 1, 0, // 721: case 0x1: { |
| 10498 | OPC_CheckPredicate, 35, // 723: check predicate 35 |
| 10499 | OPC_Decode, 218, 30, 239, 1, // 725: decode to VSUBv16i8 using decoder 239 |
| 10500 | // 725: } |
| 10501 | // 725: } // switch Inst[6] |
| 10502 | // 725: } |
| 10503 | 231, 3, 0, // 730: case 0x1e7: { |
| 10504 | OPC_CheckPredicate, 35, // 733: check predicate 35 |
| 10505 | OPC_CheckField, 6, 1, 0, // 735: check Inst[6] == 0x0 |
| 10506 | OPC_Decode, 150, 23, 245, 1, // 739: decode to VMLALuv8i16 using decoder 245 |
| 10507 | // 739: } |
| 10508 | // 739: } // switch Inst[31:23] |
| 10509 | // 739: } |
| 10510 | 9, 53, // 744: case 0x9: { |
| 10511 | OPC_SwitchField, 6, 1, // 746: switch Inst[6] { |
| 10512 | 0, 23, // 749: case 0x0: { |
| 10513 | OPC_SwitchField, 23, 9, // 751: switch Inst[31:23] { |
| 10514 | 228, 3, 7, // 754: case 0x1e4: { |
| 10515 | OPC_CheckPredicate, 35, // 757: check predicate 35 |
| 10516 | OPC_Decode, 169, 23, 246, 1, // 759: decode to VMLAv8i8 using decoder 246 |
| 10517 | // 759: } |
| 10518 | 230, 3, 0, // 764: case 0x1e6: { |
| 10519 | OPC_CheckPredicate, 35, // 767: check predicate 35 |
| 10520 | OPC_Decode, 200, 23, 246, 1, // 769: decode to VMLSv8i8 using decoder 246 |
| 10521 | // 769: } |
| 10522 | // 769: } // switch Inst[31:23] |
| 10523 | // 769: } |
| 10524 | 1, 0, // 774: case 0x1: { |
| 10525 | OPC_SwitchField, 23, 9, // 776: switch Inst[31:23] { |
| 10526 | 228, 3, 7, // 779: case 0x1e4: { |
| 10527 | OPC_CheckPredicate, 35, // 782: check predicate 35 |
| 10528 | OPC_Decode, 164, 23, 247, 1, // 784: decode to VMLAv16i8 using decoder 247 |
| 10529 | // 784: } |
| 10530 | 230, 3, 0, // 789: case 0x1e6: { |
| 10531 | OPC_CheckPredicate, 35, // 792: check predicate 35 |
| 10532 | OPC_Decode, 195, 23, 247, 1, // 794: decode to VMLSv16i8 using decoder 247 |
| 10533 | // 794: } |
| 10534 | // 794: } // switch Inst[31:23] |
| 10535 | // 794: } |
| 10536 | // 794: } // switch Inst[6] |
| 10537 | // 794: } |
| 10538 | 10, 59, // 799: case 0xa: { |
| 10539 | OPC_SwitchField, 23, 9, // 801: switch Inst[31:23] { |
| 10540 | 228, 3, 11, // 804: case 0x1e4: { |
| 10541 | OPC_CheckPredicate, 35, // 807: check predicate 35 |
| 10542 | OPC_CheckField, 6, 1, 0, // 809: check Inst[6] == 0x0 |
| 10543 | OPC_Decode, 231, 24, 238, 1, // 813: decode to VPMAXs8 using decoder 238 |
| 10544 | // 813: } |
| 10545 | 229, 3, 11, // 818: case 0x1e5: { |
| 10546 | OPC_CheckPredicate, 35, // 821: check predicate 35 |
| 10547 | OPC_CheckField, 6, 1, 0, // 823: check Inst[6] == 0x0 |
| 10548 | OPC_Decode, 178, 23, 245, 1, // 827: decode to VMLSLsv8i16 using decoder 245 |
| 10549 | // 827: } |
| 10550 | 230, 3, 11, // 832: case 0x1e6: { |
| 10551 | OPC_CheckPredicate, 35, // 835: check predicate 35 |
| 10552 | OPC_CheckField, 6, 1, 0, // 837: check Inst[6] == 0x0 |
| 10553 | OPC_Decode, 234, 24, 238, 1, // 841: decode to VPMAXu8 using decoder 238 |
| 10554 | // 841: } |
| 10555 | 231, 3, 0, // 846: case 0x1e7: { |
| 10556 | OPC_CheckPredicate, 35, // 849: check predicate 35 |
| 10557 | OPC_CheckField, 6, 1, 0, // 851: check Inst[6] == 0x0 |
| 10558 | OPC_Decode, 181, 23, 245, 1, // 855: decode to VMLSLuv8i16 using decoder 245 |
| 10559 | // 855: } |
| 10560 | // 855: } // switch Inst[31:23] |
| 10561 | // 855: } |
| 10562 | 12, 31, // 860: case 0xc: { |
| 10563 | OPC_SwitchField, 23, 9, // 862: switch Inst[31:23] { |
| 10564 | 229, 3, 11, // 865: case 0x1e5: { |
| 10565 | OPC_CheckPredicate, 35, // 868: check predicate 35 |
| 10566 | OPC_CheckField, 6, 1, 0, // 870: check Inst[6] == 0x0 |
| 10567 | OPC_Decode, 137, 24, 240, 1, // 874: decode to VMULLsv8i16 using decoder 240 |
| 10568 | // 874: } |
| 10569 | 231, 3, 0, // 879: case 0x1e7: { |
| 10570 | OPC_CheckPredicate, 35, // 882: check predicate 35 |
| 10571 | OPC_CheckField, 6, 1, 0, // 884: check Inst[6] == 0x0 |
| 10572 | OPC_Decode, 140, 24, 240, 1, // 888: decode to VMULLuv8i16 using decoder 240 |
| 10573 | // 888: } |
| 10574 | // 888: } // switch Inst[31:23] |
| 10575 | // 888: } |
| 10576 | 13, 42, // 893: case 0xd: { |
| 10577 | OPC_SwitchField, 6, 1, // 895: switch Inst[6] { |
| 10578 | 0, 23, // 898: case 0x0: { |
| 10579 | OPC_SwitchField, 23, 9, // 900: switch Inst[31:23] { |
| 10580 | 228, 3, 7, // 903: case 0x1e4: { |
| 10581 | OPC_CheckPredicate, 35, // 906: check predicate 35 |
| 10582 | OPC_Decode, 132, 17, 238, 1, // 908: decode to VADDfd using decoder 238 |
| 10583 | // 908: } |
| 10584 | 230, 3, 0, // 913: case 0x1e6: { |
| 10585 | OPC_CheckPredicate, 35, // 916: check predicate 35 |
| 10586 | OPC_Decode, 222, 24, 238, 1, // 918: decode to VPADDf using decoder 238 |
| 10587 | // 918: } |
| 10588 | // 918: } // switch Inst[31:23] |
| 10589 | // 918: } |
| 10590 | 1, 0, // 923: case 0x1: { |
| 10591 | OPC_CheckPredicate, 35, // 925: check predicate 35 |
| 10592 | OPC_CheckField, 23, 9, 228, 3, // 927: check Inst[31:23] == 0x1e4 |
| 10593 | OPC_Decode, 133, 17, 239, 1, // 932: decode to VADDfq using decoder 239 |
| 10594 | // 932: } |
| 10595 | // 932: } // switch Inst[6] |
| 10596 | // 932: } |
| 10597 | 14, 65, // 937: case 0xe: { |
| 10598 | OPC_SwitchField, 23, 9, // 939: switch Inst[31:23] { |
| 10599 | 228, 3, 21, // 942: case 0x1e4: { |
| 10600 | OPC_SwitchField, 6, 1, // 945: switch Inst[6] { |
| 10601 | 0, 7, // 948: case 0x0: { |
| 10602 | OPC_CheckPredicate, 35, // 950: check predicate 35 |
| 10603 | OPC_Decode, 168, 17, 238, 1, // 952: decode to VCEQfd using decoder 238 |
| 10604 | // 952: } |
| 10605 | 1, 0, // 957: case 0x1: { |
| 10606 | OPC_CheckPredicate, 35, // 959: check predicate 35 |
| 10607 | OPC_Decode, 169, 17, 239, 1, // 961: decode to VCEQfq using decoder 239 |
| 10608 | // 961: } |
| 10609 | // 961: } // switch Inst[6] |
| 10610 | // 961: } |
| 10611 | 229, 3, 11, // 966: case 0x1e5: { |
| 10612 | OPC_CheckPredicate, 35, // 969: check predicate 35 |
| 10613 | OPC_CheckField, 6, 1, 0, // 971: check Inst[6] == 0x0 |
| 10614 | OPC_Decode, 130, 24, 240, 1, // 975: decode to VMULLp8 using decoder 240 |
| 10615 | // 975: } |
| 10616 | 230, 3, 0, // 980: case 0x1e6: { |
| 10617 | OPC_SwitchField, 6, 1, // 983: switch Inst[6] { |
| 10618 | 0, 7, // 986: case 0x0: { |
| 10619 | OPC_CheckPredicate, 35, // 988: check predicate 35 |
| 10620 | OPC_Decode, 188, 17, 238, 1, // 990: decode to VCGEfd using decoder 238 |
| 10621 | // 990: } |
| 10622 | 1, 0, // 995: case 0x1: { |
| 10623 | OPC_CheckPredicate, 35, // 997: check predicate 35 |
| 10624 | OPC_Decode, 189, 17, 239, 1, // 999: decode to VCGEfq using decoder 239 |
| 10625 | // 999: } |
| 10626 | // 999: } // switch Inst[6] |
| 10627 | // 999: } |
| 10628 | // 999: } // switch Inst[31:23] |
| 10629 | // 999: } |
| 10630 | 15, 0, // 1004: case 0xf: { |
| 10631 | OPC_SwitchField, 6, 1, // 1006: switch Inst[6] { |
| 10632 | 0, 23, // 1009: case 0x0: { |
| 10633 | OPC_SwitchField, 23, 9, // 1011: switch Inst[31:23] { |
| 10634 | 228, 3, 7, // 1014: case 0x1e4: { |
| 10635 | OPC_CheckPredicate, 35, // 1017: check predicate 35 |
| 10636 | OPC_Decode, 235, 22, 238, 1, // 1019: decode to VMAXfd using decoder 238 |
| 10637 | // 1019: } |
| 10638 | 230, 3, 0, // 1024: case 0x1e6: { |
| 10639 | OPC_CheckPredicate, 35, // 1027: check predicate 35 |
| 10640 | OPC_Decode, 227, 24, 238, 1, // 1029: decode to VPMAXf using decoder 238 |
| 10641 | // 1029: } |
| 10642 | // 1029: } // switch Inst[31:23] |
| 10643 | // 1029: } |
| 10644 | 1, 0, // 1034: case 0x1: { |
| 10645 | OPC_CheckPredicate, 35, // 1036: check predicate 35 |
| 10646 | OPC_CheckField, 23, 9, 228, 3, // 1038: check Inst[31:23] == 0x1e4 |
| 10647 | OPC_Decode, 236, 22, 239, 1, // 1043: decode to VMAXfq using decoder 239 |
| 10648 | // 1043: } |
| 10649 | // 1043: } // switch Inst[6] |
| 10650 | // 1043: } |
| 10651 | // 1043: } // switch Inst[11:8] |
| 10652 | // 1043: } |
| 10653 | 1, 149, 11, // 1048: case 0x1: { |
| 10654 | OPC_SwitchField, 8, 4, // 1051: switch Inst[11:8] { |
| 10655 | 0, 99, // 1054: case 0x0: { |
| 10656 | OPC_SwitchField, 23, 9, // 1056: switch Inst[31:23] { |
| 10657 | 228, 3, 21, // 1059: case 0x1e4: { |
| 10658 | OPC_SwitchField, 6, 1, // 1062: switch Inst[6] { |
| 10659 | 0, 7, // 1065: case 0x0: { |
| 10660 | OPC_CheckPredicate, 35, // 1067: check predicate 35 |
| 10661 | OPC_Decode, 203, 19, 238, 1, // 1069: decode to VHADDsv4i16 using decoder 238 |
| 10662 | // 1069: } |
| 10663 | 1, 0, // 1074: case 0x1: { |
| 10664 | OPC_CheckPredicate, 35, // 1076: check predicate 35 |
| 10665 | OPC_Decode, 205, 19, 239, 1, // 1078: decode to VHADDsv8i16 using decoder 239 |
| 10666 | // 1078: } |
| 10667 | // 1078: } // switch Inst[6] |
| 10668 | // 1078: } |
| 10669 | 229, 3, 21, // 1083: case 0x1e5: { |
| 10670 | OPC_SwitchField, 6, 1, // 1086: switch Inst[6] { |
| 10671 | 0, 7, // 1089: case 0x0: { |
| 10672 | OPC_CheckPredicate, 35, // 1091: check predicate 35 |
| 10673 | OPC_Decode, 248, 16, 240, 1, // 1093: decode to VADDLsv4i32 using decoder 240 |
| 10674 | // 1093: } |
| 10675 | 1, 0, // 1098: case 0x1: { |
| 10676 | OPC_CheckPredicate, 35, // 1100: check predicate 35 |
| 10677 | OPC_Decode, 161, 23, 248, 1, // 1102: decode to VMLAslv4i16 using decoder 248 |
| 10678 | // 1102: } |
| 10679 | // 1102: } // switch Inst[6] |
| 10680 | // 1102: } |
| 10681 | 230, 3, 21, // 1107: case 0x1e6: { |
| 10682 | OPC_SwitchField, 6, 1, // 1110: switch Inst[6] { |
| 10683 | 0, 7, // 1113: case 0x0: { |
| 10684 | OPC_CheckPredicate, 35, // 1115: check predicate 35 |
| 10685 | OPC_Decode, 209, 19, 238, 1, // 1117: decode to VHADDuv4i16 using decoder 238 |
| 10686 | // 1117: } |
| 10687 | 1, 0, // 1122: case 0x1: { |
| 10688 | OPC_CheckPredicate, 35, // 1124: check predicate 35 |
| 10689 | OPC_Decode, 211, 19, 239, 1, // 1126: decode to VHADDuv8i16 using decoder 239 |
| 10690 | // 1126: } |
| 10691 | // 1126: } // switch Inst[6] |
| 10692 | // 1126: } |
| 10693 | 231, 3, 0, // 1131: case 0x1e7: { |
| 10694 | OPC_SwitchField, 6, 1, // 1134: switch Inst[6] { |
| 10695 | 0, 7, // 1137: case 0x0: { |
| 10696 | OPC_CheckPredicate, 35, // 1139: check predicate 35 |
| 10697 | OPC_Decode, 251, 16, 240, 1, // 1141: decode to VADDLuv4i32 using decoder 240 |
| 10698 | // 1141: } |
| 10699 | 1, 0, // 1146: case 0x1: { |
| 10700 | OPC_CheckPredicate, 35, // 1148: check predicate 35 |
| 10701 | OPC_Decode, 163, 23, 249, 1, // 1150: decode to VMLAslv8i16 using decoder 249 |
| 10702 | // 1150: } |
| 10703 | // 1150: } // switch Inst[6] |
| 10704 | // 1150: } |
| 10705 | // 1150: } // switch Inst[31:23] |
| 10706 | // 1150: } |
| 10707 | 1, 99, // 1155: case 0x1: { |
| 10708 | OPC_SwitchField, 23, 9, // 1157: switch Inst[31:23] { |
| 10709 | 228, 3, 21, // 1160: case 0x1e4: { |
| 10710 | OPC_SwitchField, 6, 1, // 1163: switch Inst[6] { |
| 10711 | 0, 7, // 1166: case 0x0: { |
| 10712 | OPC_CheckPredicate, 35, // 1168: check predicate 35 |
| 10713 | OPC_Decode, 185, 26, 238, 1, // 1170: decode to VRHADDsv4i16 using decoder 238 |
| 10714 | // 1170: } |
| 10715 | 1, 0, // 1175: case 0x1: { |
| 10716 | OPC_CheckPredicate, 35, // 1177: check predicate 35 |
| 10717 | OPC_Decode, 187, 26, 239, 1, // 1179: decode to VRHADDsv8i16 using decoder 239 |
| 10718 | // 1179: } |
| 10719 | // 1179: } // switch Inst[6] |
| 10720 | // 1179: } |
| 10721 | 229, 3, 21, // 1184: case 0x1e5: { |
| 10722 | OPC_SwitchField, 6, 1, // 1187: switch Inst[6] { |
| 10723 | 0, 7, // 1190: case 0x0: { |
| 10724 | OPC_CheckPredicate, 35, // 1192: check predicate 35 |
| 10725 | OPC_Decode, 255, 16, 241, 1, // 1194: decode to VADDWsv4i32 using decoder 241 |
| 10726 | // 1194: } |
| 10727 | 1, 0, // 1199: case 0x1: { |
| 10728 | OPC_CheckPredicate, 36, // 1201: check predicate 36 |
| 10729 | OPC_Decode, 158, 23, 248, 1, // 1203: decode to VMLAslhd using decoder 248 |
| 10730 | // 1203: } |
| 10731 | // 1203: } // switch Inst[6] |
| 10732 | // 1203: } |
| 10733 | 230, 3, 21, // 1208: case 0x1e6: { |
| 10734 | OPC_SwitchField, 6, 1, // 1211: switch Inst[6] { |
| 10735 | 0, 7, // 1214: case 0x0: { |
| 10736 | OPC_CheckPredicate, 35, // 1216: check predicate 35 |
| 10737 | OPC_Decode, 191, 26, 238, 1, // 1218: decode to VRHADDuv4i16 using decoder 238 |
| 10738 | // 1218: } |
| 10739 | 1, 0, // 1223: case 0x1: { |
| 10740 | OPC_CheckPredicate, 35, // 1225: check predicate 35 |
| 10741 | OPC_Decode, 193, 26, 239, 1, // 1227: decode to VRHADDuv8i16 using decoder 239 |
| 10742 | // 1227: } |
| 10743 | // 1227: } // switch Inst[6] |
| 10744 | // 1227: } |
| 10745 | 231, 3, 0, // 1232: case 0x1e7: { |
| 10746 | OPC_SwitchField, 6, 1, // 1235: switch Inst[6] { |
| 10747 | 0, 7, // 1238: case 0x0: { |
| 10748 | OPC_CheckPredicate, 35, // 1240: check predicate 35 |
| 10749 | OPC_Decode, 130, 17, 241, 1, // 1242: decode to VADDWuv4i32 using decoder 241 |
| 10750 | // 1242: } |
| 10751 | 1, 0, // 1247: case 0x1: { |
| 10752 | OPC_CheckPredicate, 36, // 1249: check predicate 36 |
| 10753 | OPC_Decode, 159, 23, 249, 1, // 1251: decode to VMLAslhq using decoder 249 |
| 10754 | // 1251: } |
| 10755 | // 1251: } // switch Inst[6] |
| 10756 | // 1251: } |
| 10757 | // 1251: } // switch Inst[31:23] |
| 10758 | // 1251: } |
| 10759 | 2, 99, // 1256: case 0x2: { |
| 10760 | OPC_SwitchField, 23, 9, // 1258: switch Inst[31:23] { |
| 10761 | 228, 3, 21, // 1261: case 0x1e4: { |
| 10762 | OPC_SwitchField, 6, 1, // 1264: switch Inst[6] { |
| 10763 | 0, 7, // 1267: case 0x0: { |
| 10764 | OPC_CheckPredicate, 35, // 1269: check predicate 35 |
| 10765 | OPC_Decode, 215, 19, 238, 1, // 1271: decode to VHSUBsv4i16 using decoder 238 |
| 10766 | // 1271: } |
| 10767 | 1, 0, // 1276: case 0x1: { |
| 10768 | OPC_CheckPredicate, 35, // 1278: check predicate 35 |
| 10769 | OPC_Decode, 217, 19, 239, 1, // 1280: decode to VHSUBsv8i16 using decoder 239 |
| 10770 | // 1280: } |
| 10771 | // 1280: } // switch Inst[6] |
| 10772 | // 1280: } |
| 10773 | 229, 3, 21, // 1285: case 0x1e5: { |
| 10774 | OPC_SwitchField, 6, 1, // 1288: switch Inst[6] { |
| 10775 | 0, 7, // 1291: case 0x0: { |
| 10776 | OPC_CheckPredicate, 35, // 1293: check predicate 35 |
| 10777 | OPC_Decode, 202, 30, 240, 1, // 1295: decode to VSUBLsv4i32 using decoder 240 |
| 10778 | // 1295: } |
| 10779 | 1, 0, // 1300: case 0x1: { |
| 10780 | OPC_CheckPredicate, 35, // 1302: check predicate 35 |
| 10781 | OPC_Decode, 142, 23, 250, 1, // 1304: decode to VMLALslsv4i16 using decoder 250 |
| 10782 | // 1304: } |
| 10783 | // 1304: } // switch Inst[6] |
| 10784 | // 1304: } |
| 10785 | 230, 3, 21, // 1309: case 0x1e6: { |
| 10786 | OPC_SwitchField, 6, 1, // 1312: switch Inst[6] { |
| 10787 | 0, 7, // 1315: case 0x0: { |
| 10788 | OPC_CheckPredicate, 35, // 1317: check predicate 35 |
| 10789 | OPC_Decode, 221, 19, 238, 1, // 1319: decode to VHSUBuv4i16 using decoder 238 |
| 10790 | // 1319: } |
| 10791 | 1, 0, // 1324: case 0x1: { |
| 10792 | OPC_CheckPredicate, 35, // 1326: check predicate 35 |
| 10793 | OPC_Decode, 223, 19, 239, 1, // 1328: decode to VHSUBuv8i16 using decoder 239 |
| 10794 | // 1328: } |
| 10795 | // 1328: } // switch Inst[6] |
| 10796 | // 1328: } |
| 10797 | 231, 3, 0, // 1333: case 0x1e7: { |
| 10798 | OPC_SwitchField, 6, 1, // 1336: switch Inst[6] { |
| 10799 | 0, 7, // 1339: case 0x0: { |
| 10800 | OPC_CheckPredicate, 35, // 1341: check predicate 35 |
| 10801 | OPC_Decode, 205, 30, 240, 1, // 1343: decode to VSUBLuv4i32 using decoder 240 |
| 10802 | // 1343: } |
| 10803 | 1, 0, // 1348: case 0x1: { |
| 10804 | OPC_CheckPredicate, 35, // 1350: check predicate 35 |
| 10805 | OPC_Decode, 144, 23, 250, 1, // 1352: decode to VMLALsluv4i16 using decoder 250 |
| 10806 | // 1352: } |
| 10807 | // 1352: } // switch Inst[6] |
| 10808 | // 1352: } |
| 10809 | // 1352: } // switch Inst[31:23] |
| 10810 | // 1352: } |
| 10811 | 3, 89, // 1357: case 0x3: { |
| 10812 | OPC_SwitchField, 23, 9, // 1359: switch Inst[31:23] { |
| 10813 | 228, 3, 21, // 1362: case 0x1e4: { |
| 10814 | OPC_SwitchField, 6, 1, // 1365: switch Inst[6] { |
| 10815 | 0, 7, // 1368: case 0x0: { |
| 10816 | OPC_CheckPredicate, 35, // 1370: check predicate 35 |
| 10817 | OPC_Decode, 220, 17, 238, 1, // 1372: decode to VCGTsv4i16 using decoder 238 |
| 10818 | // 1372: } |
| 10819 | 1, 0, // 1377: case 0x1: { |
| 10820 | OPC_CheckPredicate, 35, // 1379: check predicate 35 |
| 10821 | OPC_Decode, 222, 17, 239, 1, // 1381: decode to VCGTsv8i16 using decoder 239 |
| 10822 | // 1381: } |
| 10823 | // 1381: } // switch Inst[6] |
| 10824 | // 1381: } |
| 10825 | 229, 3, 21, // 1386: case 0x1e5: { |
| 10826 | OPC_SwitchField, 6, 1, // 1389: switch Inst[6] { |
| 10827 | 0, 7, // 1392: case 0x0: { |
| 10828 | OPC_CheckPredicate, 35, // 1394: check predicate 35 |
| 10829 | OPC_Decode, 209, 30, 241, 1, // 1396: decode to VSUBWsv4i32 using decoder 241 |
| 10830 | // 1396: } |
| 10831 | 1, 0, // 1401: case 0x1: { |
| 10832 | OPC_CheckPredicate, 35, // 1403: check predicate 35 |
| 10833 | OPC_Decode, 138, 25, 250, 1, // 1405: decode to VQDMLALslv4i16 using decoder 250 |
| 10834 | // 1405: } |
| 10835 | // 1405: } // switch Inst[6] |
| 10836 | // 1405: } |
| 10837 | 230, 3, 21, // 1410: case 0x1e6: { |
| 10838 | OPC_SwitchField, 6, 1, // 1413: switch Inst[6] { |
| 10839 | 0, 7, // 1416: case 0x0: { |
| 10840 | OPC_CheckPredicate, 35, // 1418: check predicate 35 |
| 10841 | OPC_Decode, 226, 17, 238, 1, // 1420: decode to VCGTuv4i16 using decoder 238 |
| 10842 | // 1420: } |
| 10843 | 1, 0, // 1425: case 0x1: { |
| 10844 | OPC_CheckPredicate, 35, // 1427: check predicate 35 |
| 10845 | OPC_Decode, 228, 17, 239, 1, // 1429: decode to VCGTuv8i16 using decoder 239 |
| 10846 | // 1429: } |
| 10847 | // 1429: } // switch Inst[6] |
| 10848 | // 1429: } |
| 10849 | 231, 3, 0, // 1434: case 0x1e7: { |
| 10850 | OPC_CheckPredicate, 35, // 1437: check predicate 35 |
| 10851 | OPC_CheckField, 6, 1, 0, // 1439: check Inst[6] == 0x0 |
| 10852 | OPC_Decode, 212, 30, 241, 1, // 1443: decode to VSUBWuv4i32 using decoder 241 |
| 10853 | // 1443: } |
| 10854 | // 1443: } // switch Inst[31:23] |
| 10855 | // 1443: } |
| 10856 | 4, 99, // 1448: case 0x4: { |
| 10857 | OPC_SwitchField, 23, 9, // 1450: switch Inst[31:23] { |
| 10858 | 228, 3, 21, // 1453: case 0x1e4: { |
| 10859 | OPC_SwitchField, 6, 1, // 1456: switch Inst[6] { |
| 10860 | 0, 7, // 1459: case 0x0: { |
| 10861 | OPC_CheckPredicate, 35, // 1461: check predicate 35 |
| 10862 | OPC_Decode, 218, 27, 242, 1, // 1463: decode to VSHLsv4i16 using decoder 242 |
| 10863 | // 1463: } |
| 10864 | 1, 0, // 1468: case 0x1: { |
| 10865 | OPC_CheckPredicate, 35, // 1470: check predicate 35 |
| 10866 | OPC_Decode, 220, 27, 243, 1, // 1472: decode to VSHLsv8i16 using decoder 243 |
| 10867 | // 1472: } |
| 10868 | // 1472: } // switch Inst[6] |
| 10869 | // 1472: } |
| 10870 | 229, 3, 21, // 1477: case 0x1e5: { |
| 10871 | OPC_SwitchField, 6, 1, // 1480: switch Inst[6] { |
| 10872 | 0, 7, // 1483: case 0x0: { |
| 10873 | OPC_CheckPredicate, 35, // 1485: check predicate 35 |
| 10874 | OPC_Decode, 245, 16, 244, 1, // 1487: decode to VADDHNv4i16 using decoder 244 |
| 10875 | // 1487: } |
| 10876 | 1, 0, // 1492: case 0x1: { |
| 10877 | OPC_CheckPredicate, 35, // 1494: check predicate 35 |
| 10878 | OPC_Decode, 192, 23, 248, 1, // 1496: decode to VMLSslv4i16 using decoder 248 |
| 10879 | // 1496: } |
| 10880 | // 1496: } // switch Inst[6] |
| 10881 | // 1496: } |
| 10882 | 230, 3, 21, // 1501: case 0x1e6: { |
| 10883 | OPC_SwitchField, 6, 1, // 1504: switch Inst[6] { |
| 10884 | 0, 7, // 1507: case 0x0: { |
| 10885 | OPC_CheckPredicate, 35, // 1509: check predicate 35 |
| 10886 | OPC_Decode, 226, 27, 242, 1, // 1511: decode to VSHLuv4i16 using decoder 242 |
| 10887 | // 1511: } |
| 10888 | 1, 0, // 1516: case 0x1: { |
| 10889 | OPC_CheckPredicate, 35, // 1518: check predicate 35 |
| 10890 | OPC_Decode, 228, 27, 243, 1, // 1520: decode to VSHLuv8i16 using decoder 243 |
| 10891 | // 1520: } |
| 10892 | // 1520: } // switch Inst[6] |
| 10893 | // 1520: } |
| 10894 | 231, 3, 0, // 1525: case 0x1e7: { |
| 10895 | OPC_SwitchField, 6, 1, // 1528: switch Inst[6] { |
| 10896 | 0, 7, // 1531: case 0x0: { |
| 10897 | OPC_CheckPredicate, 35, // 1533: check predicate 35 |
| 10898 | OPC_Decode, 159, 26, 244, 1, // 1535: decode to VRADDHNv4i16 using decoder 244 |
| 10899 | // 1535: } |
| 10900 | 1, 0, // 1540: case 0x1: { |
| 10901 | OPC_CheckPredicate, 35, // 1542: check predicate 35 |
| 10902 | OPC_Decode, 194, 23, 249, 1, // 1544: decode to VMLSslv8i16 using decoder 249 |
| 10903 | // 1544: } |
| 10904 | // 1544: } // switch Inst[6] |
| 10905 | // 1544: } |
| 10906 | // 1544: } // switch Inst[31:23] |
| 10907 | // 1544: } |
| 10908 | 5, 99, // 1549: case 0x5: { |
| 10909 | OPC_SwitchField, 23, 9, // 1551: switch Inst[31:23] { |
| 10910 | 228, 3, 21, // 1554: case 0x1e4: { |
| 10911 | OPC_SwitchField, 6, 1, // 1557: switch Inst[6] { |
| 10912 | 0, 7, // 1560: case 0x0: { |
| 10913 | OPC_CheckPredicate, 35, // 1562: check predicate 35 |
| 10914 | OPC_Decode, 244, 26, 242, 1, // 1564: decode to VRSHLsv4i16 using decoder 242 |
| 10915 | // 1564: } |
| 10916 | 1, 0, // 1569: case 0x1: { |
| 10917 | OPC_CheckPredicate, 35, // 1571: check predicate 35 |
| 10918 | OPC_Decode, 246, 26, 243, 1, // 1573: decode to VRSHLsv8i16 using decoder 243 |
| 10919 | // 1573: } |
| 10920 | // 1573: } // switch Inst[6] |
| 10921 | // 1573: } |
| 10922 | 229, 3, 21, // 1578: case 0x1e5: { |
| 10923 | OPC_SwitchField, 6, 1, // 1581: switch Inst[6] { |
| 10924 | 0, 7, // 1584: case 0x0: { |
| 10925 | OPC_CheckPredicate, 35, // 1586: check predicate 35 |
| 10926 | OPC_Decode, 182, 16, 245, 1, // 1588: decode to VABALsv4i32 using decoder 245 |
| 10927 | // 1588: } |
| 10928 | 1, 0, // 1593: case 0x1: { |
| 10929 | OPC_CheckPredicate, 36, // 1595: check predicate 36 |
| 10930 | OPC_Decode, 189, 23, 248, 1, // 1597: decode to VMLSslhd using decoder 248 |
| 10931 | // 1597: } |
| 10932 | // 1597: } // switch Inst[6] |
| 10933 | // 1597: } |
| 10934 | 230, 3, 21, // 1602: case 0x1e6: { |
| 10935 | OPC_SwitchField, 6, 1, // 1605: switch Inst[6] { |
| 10936 | 0, 7, // 1608: case 0x0: { |
| 10937 | OPC_CheckPredicate, 35, // 1610: check predicate 35 |
| 10938 | OPC_Decode, 252, 26, 242, 1, // 1612: decode to VRSHLuv4i16 using decoder 242 |
| 10939 | // 1612: } |
| 10940 | 1, 0, // 1617: case 0x1: { |
| 10941 | OPC_CheckPredicate, 35, // 1619: check predicate 35 |
| 10942 | OPC_Decode, 254, 26, 243, 1, // 1621: decode to VRSHLuv8i16 using decoder 243 |
| 10943 | // 1621: } |
| 10944 | // 1621: } // switch Inst[6] |
| 10945 | // 1621: } |
| 10946 | 231, 3, 0, // 1626: case 0x1e7: { |
| 10947 | OPC_SwitchField, 6, 1, // 1629: switch Inst[6] { |
| 10948 | 0, 7, // 1632: case 0x0: { |
| 10949 | OPC_CheckPredicate, 35, // 1634: check predicate 35 |
| 10950 | OPC_Decode, 185, 16, 245, 1, // 1636: decode to VABALuv4i32 using decoder 245 |
| 10951 | // 1636: } |
| 10952 | 1, 0, // 1641: case 0x1: { |
| 10953 | OPC_CheckPredicate, 36, // 1643: check predicate 36 |
| 10954 | OPC_Decode, 190, 23, 249, 1, // 1645: decode to VMLSslhq using decoder 249 |
| 10955 | // 1645: } |
| 10956 | // 1645: } // switch Inst[6] |
| 10957 | // 1645: } |
| 10958 | // 1645: } // switch Inst[31:23] |
| 10959 | // 1645: } |
| 10960 | 6, 99, // 1650: case 0x6: { |
| 10961 | OPC_SwitchField, 23, 9, // 1652: switch Inst[31:23] { |
| 10962 | 228, 3, 21, // 1655: case 0x1e4: { |
| 10963 | OPC_SwitchField, 6, 1, // 1658: switch Inst[6] { |
| 10964 | 0, 7, // 1661: case 0x0: { |
| 10965 | OPC_CheckPredicate, 35, // 1663: check predicate 35 |
| 10966 | OPC_Decode, 241, 22, 238, 1, // 1665: decode to VMAXsv4i16 using decoder 238 |
| 10967 | // 1665: } |
| 10968 | 1, 0, // 1670: case 0x1: { |
| 10969 | OPC_CheckPredicate, 35, // 1672: check predicate 35 |
| 10970 | OPC_Decode, 243, 22, 239, 1, // 1674: decode to VMAXsv8i16 using decoder 239 |
| 10971 | // 1674: } |
| 10972 | // 1674: } // switch Inst[6] |
| 10973 | // 1674: } |
| 10974 | 229, 3, 21, // 1679: case 0x1e5: { |
| 10975 | OPC_SwitchField, 6, 1, // 1682: switch Inst[6] { |
| 10976 | 0, 7, // 1685: case 0x0: { |
| 10977 | OPC_CheckPredicate, 35, // 1687: check predicate 35 |
| 10978 | OPC_Decode, 199, 30, 244, 1, // 1689: decode to VSUBHNv4i16 using decoder 244 |
| 10979 | // 1689: } |
| 10980 | 1, 0, // 1694: case 0x1: { |
| 10981 | OPC_CheckPredicate, 35, // 1696: check predicate 35 |
| 10982 | OPC_Decode, 173, 23, 250, 1, // 1698: decode to VMLSLslsv4i16 using decoder 250 |
| 10983 | // 1698: } |
| 10984 | // 1698: } // switch Inst[6] |
| 10985 | // 1698: } |
| 10986 | 230, 3, 21, // 1703: case 0x1e6: { |
| 10987 | OPC_SwitchField, 6, 1, // 1706: switch Inst[6] { |
| 10988 | 0, 7, // 1709: case 0x0: { |
| 10989 | OPC_CheckPredicate, 35, // 1711: check predicate 35 |
| 10990 | OPC_Decode, 247, 22, 238, 1, // 1713: decode to VMAXuv4i16 using decoder 238 |
| 10991 | // 1713: } |
| 10992 | 1, 0, // 1718: case 0x1: { |
| 10993 | OPC_CheckPredicate, 35, // 1720: check predicate 35 |
| 10994 | OPC_Decode, 249, 22, 239, 1, // 1722: decode to VMAXuv8i16 using decoder 239 |
| 10995 | // 1722: } |
| 10996 | // 1722: } // switch Inst[6] |
| 10997 | // 1722: } |
| 10998 | 231, 3, 0, // 1727: case 0x1e7: { |
| 10999 | OPC_SwitchField, 6, 1, // 1730: switch Inst[6] { |
| 11000 | 0, 7, // 1733: case 0x0: { |
| 11001 | OPC_CheckPredicate, 35, // 1735: check predicate 35 |
| 11002 | OPC_Decode, 174, 27, 244, 1, // 1737: decode to VRSUBHNv4i16 using decoder 244 |
| 11003 | // 1737: } |
| 11004 | 1, 0, // 1742: case 0x1: { |
| 11005 | OPC_CheckPredicate, 35, // 1744: check predicate 35 |
| 11006 | OPC_Decode, 175, 23, 250, 1, // 1746: decode to VMLSLsluv4i16 using decoder 250 |
| 11007 | // 1746: } |
| 11008 | // 1746: } // switch Inst[6] |
| 11009 | // 1746: } |
| 11010 | // 1746: } // switch Inst[31:23] |
| 11011 | // 1746: } |
| 11012 | 7, 89, // 1751: case 0x7: { |
| 11013 | OPC_SwitchField, 23, 9, // 1753: switch Inst[31:23] { |
| 11014 | 228, 3, 21, // 1756: case 0x1e4: { |
| 11015 | OPC_SwitchField, 6, 1, // 1759: switch Inst[6] { |
| 11016 | 0, 7, // 1762: case 0x0: { |
| 11017 | OPC_CheckPredicate, 35, // 1764: check predicate 35 |
| 11018 | OPC_Decode, 211, 16, 238, 1, // 1766: decode to VABDsv4i16 using decoder 238 |
| 11019 | // 1766: } |
| 11020 | 1, 0, // 1771: case 0x1: { |
| 11021 | OPC_CheckPredicate, 35, // 1773: check predicate 35 |
| 11022 | OPC_Decode, 213, 16, 239, 1, // 1775: decode to VABDsv8i16 using decoder 239 |
| 11023 | // 1775: } |
| 11024 | // 1775: } // switch Inst[6] |
| 11025 | // 1775: } |
| 11026 | 229, 3, 21, // 1780: case 0x1e5: { |
| 11027 | OPC_SwitchField, 6, 1, // 1783: switch Inst[6] { |
| 11028 | 0, 7, // 1786: case 0x0: { |
| 11029 | OPC_CheckPredicate, 35, // 1788: check predicate 35 |
| 11030 | OPC_Decode, 200, 16, 240, 1, // 1790: decode to VABDLsv4i32 using decoder 240 |
| 11031 | // 1790: } |
| 11032 | 1, 0, // 1795: case 0x1: { |
| 11033 | OPC_CheckPredicate, 35, // 1797: check predicate 35 |
| 11034 | OPC_Decode, 142, 25, 250, 1, // 1799: decode to VQDMLSLslv4i16 using decoder 250 |
| 11035 | // 1799: } |
| 11036 | // 1799: } // switch Inst[6] |
| 11037 | // 1799: } |
| 11038 | 230, 3, 21, // 1804: case 0x1e6: { |
| 11039 | OPC_SwitchField, 6, 1, // 1807: switch Inst[6] { |
| 11040 | 0, 7, // 1810: case 0x0: { |
| 11041 | OPC_CheckPredicate, 35, // 1812: check predicate 35 |
| 11042 | OPC_Decode, 217, 16, 238, 1, // 1814: decode to VABDuv4i16 using decoder 238 |
| 11043 | // 1814: } |
| 11044 | 1, 0, // 1819: case 0x1: { |
| 11045 | OPC_CheckPredicate, 35, // 1821: check predicate 35 |
| 11046 | OPC_Decode, 219, 16, 239, 1, // 1823: decode to VABDuv8i16 using decoder 239 |
| 11047 | // 1823: } |
| 11048 | // 1823: } // switch Inst[6] |
| 11049 | // 1823: } |
| 11050 | 231, 3, 0, // 1828: case 0x1e7: { |
| 11051 | OPC_CheckPredicate, 35, // 1831: check predicate 35 |
| 11052 | OPC_CheckField, 6, 1, 0, // 1833: check Inst[6] == 0x0 |
| 11053 | OPC_Decode, 203, 16, 240, 1, // 1837: decode to VABDLuv4i32 using decoder 240 |
| 11054 | // 1837: } |
| 11055 | // 1837: } // switch Inst[31:23] |
| 11056 | // 1837: } |
| 11057 | 8, 99, // 1842: case 0x8: { |
| 11058 | OPC_SwitchField, 23, 9, // 1844: switch Inst[31:23] { |
| 11059 | 228, 3, 21, // 1847: case 0x1e4: { |
| 11060 | OPC_SwitchField, 6, 1, // 1850: switch Inst[6] { |
| 11061 | 0, 7, // 1853: case 0x0: { |
| 11062 | OPC_CheckPredicate, 35, // 1855: check predicate 35 |
| 11063 | OPC_Decode, 140, 17, 238, 1, // 1857: decode to VADDv4i16 using decoder 238 |
| 11064 | // 1857: } |
| 11065 | 1, 0, // 1862: case 0x1: { |
| 11066 | OPC_CheckPredicate, 35, // 1864: check predicate 35 |
| 11067 | OPC_Decode, 142, 17, 239, 1, // 1866: decode to VADDv8i16 using decoder 239 |
| 11068 | // 1866: } |
| 11069 | // 1866: } // switch Inst[6] |
| 11070 | // 1866: } |
| 11071 | 229, 3, 21, // 1871: case 0x1e5: { |
| 11072 | OPC_SwitchField, 6, 1, // 1874: switch Inst[6] { |
| 11073 | 0, 7, // 1877: case 0x0: { |
| 11074 | OPC_CheckPredicate, 35, // 1879: check predicate 35 |
| 11075 | OPC_Decode, 146, 23, 245, 1, // 1881: decode to VMLALsv4i32 using decoder 245 |
| 11076 | // 1881: } |
| 11077 | 1, 0, // 1886: case 0x1: { |
| 11078 | OPC_CheckPredicate, 35, // 1888: check predicate 35 |
| 11079 | OPC_Decode, 153, 24, 251, 1, // 1890: decode to VMULslv4i16 using decoder 251 |
| 11080 | // 1890: } |
| 11081 | // 1890: } // switch Inst[6] |
| 11082 | // 1890: } |
| 11083 | 230, 3, 21, // 1895: case 0x1e6: { |
| 11084 | OPC_SwitchField, 6, 1, // 1898: switch Inst[6] { |
| 11085 | 0, 7, // 1901: case 0x0: { |
| 11086 | OPC_CheckPredicate, 35, // 1903: check predicate 35 |
| 11087 | OPC_Decode, 222, 30, 238, 1, // 1905: decode to VSUBv4i16 using decoder 238 |
| 11088 | // 1905: } |
| 11089 | 1, 0, // 1910: case 0x1: { |
| 11090 | OPC_CheckPredicate, 35, // 1912: check predicate 35 |
| 11091 | OPC_Decode, 224, 30, 239, 1, // 1914: decode to VSUBv8i16 using decoder 239 |
| 11092 | // 1914: } |
| 11093 | // 1914: } // switch Inst[6] |
| 11094 | // 1914: } |
| 11095 | 231, 3, 0, // 1919: case 0x1e7: { |
| 11096 | OPC_SwitchField, 6, 1, // 1922: switch Inst[6] { |
| 11097 | 0, 7, // 1925: case 0x0: { |
| 11098 | OPC_CheckPredicate, 35, // 1927: check predicate 35 |
| 11099 | OPC_Decode, 149, 23, 245, 1, // 1929: decode to VMLALuv4i32 using decoder 245 |
| 11100 | // 1929: } |
| 11101 | 1, 0, // 1934: case 0x1: { |
| 11102 | OPC_CheckPredicate, 35, // 1936: check predicate 35 |
| 11103 | OPC_Decode, 155, 24, 252, 1, // 1938: decode to VMULslv8i16 using decoder 252 |
| 11104 | // 1938: } |
| 11105 | // 1938: } // switch Inst[6] |
| 11106 | // 1938: } |
| 11107 | // 1938: } // switch Inst[31:23] |
| 11108 | // 1938: } |
| 11109 | 9, 89, // 1943: case 0x9: { |
| 11110 | OPC_SwitchField, 23, 9, // 1945: switch Inst[31:23] { |
| 11111 | 228, 3, 21, // 1948: case 0x1e4: { |
| 11112 | OPC_SwitchField, 6, 1, // 1951: switch Inst[6] { |
| 11113 | 0, 7, // 1954: case 0x0: { |
| 11114 | OPC_CheckPredicate, 35, // 1956: check predicate 35 |
| 11115 | OPC_Decode, 166, 23, 246, 1, // 1958: decode to VMLAv4i16 using decoder 246 |
| 11116 | // 1958: } |
| 11117 | 1, 0, // 1963: case 0x1: { |
| 11118 | OPC_CheckPredicate, 35, // 1965: check predicate 35 |
| 11119 | OPC_Decode, 168, 23, 247, 1, // 1967: decode to VMLAv8i16 using decoder 247 |
| 11120 | // 1967: } |
| 11121 | // 1967: } // switch Inst[6] |
| 11122 | // 1967: } |
| 11123 | 229, 3, 21, // 1972: case 0x1e5: { |
| 11124 | OPC_SwitchField, 6, 1, // 1975: switch Inst[6] { |
| 11125 | 0, 7, // 1978: case 0x0: { |
| 11126 | OPC_CheckPredicate, 35, // 1980: check predicate 35 |
| 11127 | OPC_Decode, 140, 25, 245, 1, // 1982: decode to VQDMLALv4i32 using decoder 245 |
| 11128 | // 1982: } |
| 11129 | 1, 0, // 1987: case 0x1: { |
| 11130 | OPC_CheckPredicate, 36, // 1989: check predicate 36 |
| 11131 | OPC_Decode, 150, 24, 251, 1, // 1991: decode to VMULslhd using decoder 251 |
| 11132 | // 1991: } |
| 11133 | // 1991: } // switch Inst[6] |
| 11134 | // 1991: } |
| 11135 | 230, 3, 21, // 1996: case 0x1e6: { |
| 11136 | OPC_SwitchField, 6, 1, // 1999: switch Inst[6] { |
| 11137 | 0, 7, // 2002: case 0x0: { |
| 11138 | OPC_CheckPredicate, 35, // 2004: check predicate 35 |
| 11139 | OPC_Decode, 197, 23, 246, 1, // 2006: decode to VMLSv4i16 using decoder 246 |
| 11140 | // 2006: } |
| 11141 | 1, 0, // 2011: case 0x1: { |
| 11142 | OPC_CheckPredicate, 35, // 2013: check predicate 35 |
| 11143 | OPC_Decode, 199, 23, 247, 1, // 2015: decode to VMLSv8i16 using decoder 247 |
| 11144 | // 2015: } |
| 11145 | // 2015: } // switch Inst[6] |
| 11146 | // 2015: } |
| 11147 | 231, 3, 0, // 2020: case 0x1e7: { |
| 11148 | OPC_CheckPredicate, 36, // 2023: check predicate 36 |
| 11149 | OPC_CheckField, 6, 1, 1, // 2025: check Inst[6] == 0x1 |
| 11150 | OPC_Decode, 151, 24, 252, 1, // 2029: decode to VMULslhq using decoder 252 |
| 11151 | // 2029: } |
| 11152 | // 2029: } // switch Inst[31:23] |
| 11153 | // 2029: } |
| 11154 | 10, 79, // 2034: case 0xa: { |
| 11155 | OPC_SwitchField, 23, 9, // 2036: switch Inst[31:23] { |
| 11156 | 228, 3, 11, // 2039: case 0x1e4: { |
| 11157 | OPC_CheckPredicate, 35, // 2042: check predicate 35 |
| 11158 | OPC_CheckField, 6, 1, 0, // 2044: check Inst[6] == 0x0 |
| 11159 | OPC_Decode, 229, 24, 238, 1, // 2048: decode to VPMAXs16 using decoder 238 |
| 11160 | // 2048: } |
| 11161 | 229, 3, 21, // 2053: case 0x1e5: { |
| 11162 | OPC_SwitchField, 6, 1, // 2056: switch Inst[6] { |
| 11163 | 0, 7, // 2059: case 0x0: { |
| 11164 | OPC_CheckPredicate, 35, // 2061: check predicate 35 |
| 11165 | OPC_Decode, 177, 23, 245, 1, // 2063: decode to VMLSLsv4i32 using decoder 245 |
| 11166 | // 2063: } |
| 11167 | 1, 0, // 2068: case 0x1: { |
| 11168 | OPC_CheckPredicate, 35, // 2070: check predicate 35 |
| 11169 | OPC_Decode, 132, 24, 253, 1, // 2072: decode to VMULLslsv4i16 using decoder 253 |
| 11170 | // 2072: } |
| 11171 | // 2072: } // switch Inst[6] |
| 11172 | // 2072: } |
| 11173 | 230, 3, 11, // 2077: case 0x1e6: { |
| 11174 | OPC_CheckPredicate, 35, // 2080: check predicate 35 |
| 11175 | OPC_CheckField, 6, 1, 0, // 2082: check Inst[6] == 0x0 |
| 11176 | OPC_Decode, 232, 24, 238, 1, // 2086: decode to VPMAXu16 using decoder 238 |
| 11177 | // 2086: } |
| 11178 | 231, 3, 0, // 2091: case 0x1e7: { |
| 11179 | OPC_SwitchField, 6, 1, // 2094: switch Inst[6] { |
| 11180 | 0, 7, // 2097: case 0x0: { |
| 11181 | OPC_CheckPredicate, 35, // 2099: check predicate 35 |
| 11182 | OPC_Decode, 180, 23, 245, 1, // 2101: decode to VMLSLuv4i32 using decoder 245 |
| 11183 | // 2101: } |
| 11184 | 1, 0, // 2106: case 0x1: { |
| 11185 | OPC_CheckPredicate, 35, // 2108: check predicate 35 |
| 11186 | OPC_Decode, 134, 24, 253, 1, // 2110: decode to VMULLsluv4i16 using decoder 253 |
| 11187 | // 2110: } |
| 11188 | // 2110: } // switch Inst[6] |
| 11189 | // 2110: } |
| 11190 | // 2110: } // switch Inst[31:23] |
| 11191 | // 2110: } |
| 11192 | 11, 75, // 2115: case 0xb: { |
| 11193 | OPC_SwitchField, 23, 9, // 2117: switch Inst[31:23] { |
| 11194 | 228, 3, 21, // 2120: case 0x1e4: { |
| 11195 | OPC_SwitchField, 6, 1, // 2123: switch Inst[6] { |
| 11196 | 0, 7, // 2126: case 0x0: { |
| 11197 | OPC_CheckPredicate, 35, // 2128: check predicate 35 |
| 11198 | OPC_Decode, 150, 25, 238, 1, // 2130: decode to VQDMULHv4i16 using decoder 238 |
| 11199 | // 2130: } |
| 11200 | 1, 0, // 2135: case 0x1: { |
| 11201 | OPC_CheckPredicate, 35, // 2137: check predicate 35 |
| 11202 | OPC_Decode, 152, 25, 239, 1, // 2139: decode to VQDMULHv8i16 using decoder 239 |
| 11203 | // 2139: } |
| 11204 | // 2139: } // switch Inst[6] |
| 11205 | // 2139: } |
| 11206 | 229, 3, 21, // 2144: case 0x1e5: { |
| 11207 | OPC_SwitchField, 6, 1, // 2147: switch Inst[6] { |
| 11208 | 0, 7, // 2150: case 0x0: { |
| 11209 | OPC_CheckPredicate, 35, // 2152: check predicate 35 |
| 11210 | OPC_Decode, 144, 25, 245, 1, // 2154: decode to VQDMLSLv4i32 using decoder 245 |
| 11211 | // 2154: } |
| 11212 | 1, 0, // 2159: case 0x1: { |
| 11213 | OPC_CheckPredicate, 35, // 2161: check predicate 35 |
| 11214 | OPC_Decode, 154, 25, 253, 1, // 2163: decode to VQDMULLslv4i16 using decoder 253 |
| 11215 | // 2163: } |
| 11216 | // 2163: } // switch Inst[6] |
| 11217 | // 2163: } |
| 11218 | 230, 3, 0, // 2168: case 0x1e6: { |
| 11219 | OPC_SwitchField, 6, 1, // 2171: switch Inst[6] { |
| 11220 | 0, 7, // 2174: case 0x0: { |
| 11221 | OPC_CheckPredicate, 35, // 2176: check predicate 35 |
| 11222 | OPC_Decode, 193, 25, 238, 1, // 2178: decode to VQRDMULHv4i16 using decoder 238 |
| 11223 | // 2178: } |
| 11224 | 1, 0, // 2183: case 0x1: { |
| 11225 | OPC_CheckPredicate, 35, // 2185: check predicate 35 |
| 11226 | OPC_Decode, 195, 25, 239, 1, // 2187: decode to VQRDMULHv8i16 using decoder 239 |
| 11227 | // 2187: } |
| 11228 | // 2187: } // switch Inst[6] |
| 11229 | // 2187: } |
| 11230 | // 2187: } // switch Inst[31:23] |
| 11231 | // 2187: } |
| 11232 | 12, 53, // 2192: case 0xc: { |
| 11233 | OPC_SwitchField, 6, 1, // 2194: switch Inst[6] { |
| 11234 | 0, 23, // 2197: case 0x0: { |
| 11235 | OPC_SwitchField, 23, 9, // 2199: switch Inst[31:23] { |
| 11236 | 229, 3, 7, // 2202: case 0x1e5: { |
| 11237 | OPC_CheckPredicate, 35, // 2205: check predicate 35 |
| 11238 | OPC_Decode, 136, 24, 240, 1, // 2207: decode to VMULLsv4i32 using decoder 240 |
| 11239 | // 2207: } |
| 11240 | 231, 3, 0, // 2212: case 0x1e7: { |
| 11241 | OPC_CheckPredicate, 35, // 2215: check predicate 35 |
| 11242 | OPC_Decode, 139, 24, 240, 1, // 2217: decode to VMULLuv4i32 using decoder 240 |
| 11243 | // 2217: } |
| 11244 | // 2217: } // switch Inst[31:23] |
| 11245 | // 2217: } |
| 11246 | 1, 0, // 2222: case 0x1: { |
| 11247 | OPC_SwitchField, 23, 9, // 2224: switch Inst[31:23] { |
| 11248 | 229, 3, 7, // 2227: case 0x1e5: { |
| 11249 | OPC_CheckPredicate, 35, // 2230: check predicate 35 |
| 11250 | OPC_Decode, 146, 25, 251, 1, // 2232: decode to VQDMULHslv4i16 using decoder 251 |
| 11251 | // 2232: } |
| 11252 | 231, 3, 0, // 2237: case 0x1e7: { |
| 11253 | OPC_CheckPredicate, 35, // 2240: check predicate 35 |
| 11254 | OPC_Decode, 148, 25, 252, 1, // 2242: decode to VQDMULHslv8i16 using decoder 252 |
| 11255 | // 2242: } |
| 11256 | // 2242: } // switch Inst[31:23] |
| 11257 | // 2242: } |
| 11258 | // 2242: } // switch Inst[6] |
| 11259 | // 2242: } |
| 11260 | 13, 79, // 2247: case 0xd: { |
| 11261 | OPC_SwitchField, 23, 9, // 2249: switch Inst[31:23] { |
| 11262 | 228, 3, 21, // 2252: case 0x1e4: { |
| 11263 | OPC_SwitchField, 6, 1, // 2255: switch Inst[6] { |
| 11264 | 0, 7, // 2258: case 0x0: { |
| 11265 | OPC_CheckPredicate, 36, // 2260: check predicate 36 |
| 11266 | OPC_Decode, 134, 17, 238, 1, // 2262: decode to VADDhd using decoder 238 |
| 11267 | // 2262: } |
| 11268 | 1, 0, // 2267: case 0x1: { |
| 11269 | OPC_CheckPredicate, 36, // 2269: check predicate 36 |
| 11270 | OPC_Decode, 135, 17, 239, 1, // 2271: decode to VADDhq using decoder 239 |
| 11271 | // 2271: } |
| 11272 | // 2271: } // switch Inst[6] |
| 11273 | // 2271: } |
| 11274 | 229, 3, 21, // 2276: case 0x1e5: { |
| 11275 | OPC_SwitchField, 6, 1, // 2279: switch Inst[6] { |
| 11276 | 0, 7, // 2282: case 0x0: { |
| 11277 | OPC_CheckPredicate, 35, // 2284: check predicate 35 |
| 11278 | OPC_Decode, 156, 25, 240, 1, // 2286: decode to VQDMULLv4i32 using decoder 240 |
| 11279 | // 2286: } |
| 11280 | 1, 0, // 2291: case 0x1: { |
| 11281 | OPC_CheckPredicate, 35, // 2293: check predicate 35 |
| 11282 | OPC_Decode, 189, 25, 251, 1, // 2295: decode to VQRDMULHslv4i16 using decoder 251 |
| 11283 | // 2295: } |
| 11284 | // 2295: } // switch Inst[6] |
| 11285 | // 2295: } |
| 11286 | 230, 3, 11, // 2300: case 0x1e6: { |
| 11287 | OPC_CheckPredicate, 36, // 2303: check predicate 36 |
| 11288 | OPC_CheckField, 6, 1, 0, // 2305: check Inst[6] == 0x0 |
| 11289 | OPC_Decode, 223, 24, 238, 1, // 2309: decode to VPADDh using decoder 238 |
| 11290 | // 2309: } |
| 11291 | 231, 3, 0, // 2314: case 0x1e7: { |
| 11292 | OPC_CheckPredicate, 35, // 2317: check predicate 35 |
| 11293 | OPC_CheckField, 6, 1, 1, // 2319: check Inst[6] == 0x1 |
| 11294 | OPC_Decode, 191, 25, 252, 1, // 2323: decode to VQRDMULHslv8i16 using decoder 252 |
| 11295 | // 2323: } |
| 11296 | // 2323: } // switch Inst[31:23] |
| 11297 | // 2323: } |
| 11298 | 14, 79, // 2328: case 0xe: { |
| 11299 | OPC_SwitchField, 23, 9, // 2330: switch Inst[31:23] { |
| 11300 | 228, 3, 21, // 2333: case 0x1e4: { |
| 11301 | OPC_SwitchField, 6, 1, // 2336: switch Inst[6] { |
| 11302 | 0, 7, // 2339: case 0x0: { |
| 11303 | OPC_CheckPredicate, 36, // 2341: check predicate 36 |
| 11304 | OPC_Decode, 170, 17, 238, 1, // 2343: decode to VCEQhd using decoder 238 |
| 11305 | // 2343: } |
| 11306 | 1, 0, // 2348: case 0x1: { |
| 11307 | OPC_CheckPredicate, 36, // 2350: check predicate 36 |
| 11308 | OPC_Decode, 171, 17, 239, 1, // 2352: decode to VCEQhq using decoder 239 |
| 11309 | // 2352: } |
| 11310 | // 2352: } // switch Inst[6] |
| 11311 | // 2352: } |
| 11312 | 229, 3, 11, // 2357: case 0x1e5: { |
| 11313 | OPC_CheckPredicate, 37, // 2360: check predicate 37 |
| 11314 | OPC_CheckField, 6, 1, 1, // 2362: check Inst[6] == 0x1 |
| 11315 | OPC_Decode, 173, 25, 248, 1, // 2366: decode to VQRDMLAHslv4i16 using decoder 248 |
| 11316 | // 2366: } |
| 11317 | 230, 3, 21, // 2371: case 0x1e6: { |
| 11318 | OPC_SwitchField, 6, 1, // 2374: switch Inst[6] { |
| 11319 | 0, 7, // 2377: case 0x0: { |
| 11320 | OPC_CheckPredicate, 36, // 2379: check predicate 36 |
| 11321 | OPC_Decode, 190, 17, 238, 1, // 2381: decode to VCGEhd using decoder 238 |
| 11322 | // 2381: } |
| 11323 | 1, 0, // 2386: case 0x1: { |
| 11324 | OPC_CheckPredicate, 36, // 2388: check predicate 36 |
| 11325 | OPC_Decode, 191, 17, 239, 1, // 2390: decode to VCGEhq using decoder 239 |
| 11326 | // 2390: } |
| 11327 | // 2390: } // switch Inst[6] |
| 11328 | // 2390: } |
| 11329 | 231, 3, 0, // 2395: case 0x1e7: { |
| 11330 | OPC_CheckPredicate, 37, // 2398: check predicate 37 |
| 11331 | OPC_CheckField, 6, 1, 1, // 2400: check Inst[6] == 0x1 |
| 11332 | OPC_Decode, 175, 25, 249, 1, // 2404: decode to VQRDMLAHslv8i16 using decoder 249 |
| 11333 | // 2404: } |
| 11334 | // 2404: } // switch Inst[31:23] |
| 11335 | // 2404: } |
| 11336 | 15, 0, // 2409: case 0xf: { |
| 11337 | OPC_SwitchField, 23, 9, // 2411: switch Inst[31:23] { |
| 11338 | 228, 3, 21, // 2414: case 0x1e4: { |
| 11339 | OPC_SwitchField, 6, 1, // 2417: switch Inst[6] { |
| 11340 | 0, 7, // 2420: case 0x0: { |
| 11341 | OPC_CheckPredicate, 36, // 2422: check predicate 36 |
| 11342 | OPC_Decode, 237, 22, 238, 1, // 2424: decode to VMAXhd using decoder 238 |
| 11343 | // 2424: } |
| 11344 | 1, 0, // 2429: case 0x1: { |
| 11345 | OPC_CheckPredicate, 36, // 2431: check predicate 36 |
| 11346 | OPC_Decode, 238, 22, 239, 1, // 2433: decode to VMAXhq using decoder 239 |
| 11347 | // 2433: } |
| 11348 | // 2433: } // switch Inst[6] |
| 11349 | // 2433: } |
| 11350 | 229, 3, 11, // 2438: case 0x1e5: { |
| 11351 | OPC_CheckPredicate, 37, // 2441: check predicate 37 |
| 11352 | OPC_CheckField, 6, 1, 1, // 2443: check Inst[6] == 0x1 |
| 11353 | OPC_Decode, 181, 25, 248, 1, // 2447: decode to VQRDMLSHslv4i16 using decoder 248 |
| 11354 | // 2447: } |
| 11355 | 230, 3, 11, // 2452: case 0x1e6: { |
| 11356 | OPC_CheckPredicate, 36, // 2455: check predicate 36 |
| 11357 | OPC_CheckField, 6, 1, 0, // 2457: check Inst[6] == 0x0 |
| 11358 | OPC_Decode, 228, 24, 238, 1, // 2461: decode to VPMAXh using decoder 238 |
| 11359 | // 2461: } |
| 11360 | 231, 3, 0, // 2466: case 0x1e7: { |
| 11361 | OPC_CheckPredicate, 37, // 2469: check predicate 37 |
| 11362 | OPC_CheckField, 6, 1, 1, // 2471: check Inst[6] == 0x1 |
| 11363 | OPC_Decode, 183, 25, 249, 1, // 2475: decode to VQRDMLSHslv8i16 using decoder 249 |
| 11364 | // 2475: } |
| 11365 | // 2475: } // switch Inst[31:23] |
| 11366 | // 2475: } |
| 11367 | // 2475: } // switch Inst[11:8] |
| 11368 | // 2475: } |
| 11369 | 2, 145, 11, // 2480: case 0x2: { |
| 11370 | OPC_SwitchField, 8, 4, // 2483: switch Inst[11:8] { |
| 11371 | 0, 99, // 2486: case 0x0: { |
| 11372 | OPC_SwitchField, 23, 9, // 2488: switch Inst[31:23] { |
| 11373 | 228, 3, 21, // 2491: case 0x1e4: { |
| 11374 | OPC_SwitchField, 6, 1, // 2494: switch Inst[6] { |
| 11375 | 0, 7, // 2497: case 0x0: { |
| 11376 | OPC_CheckPredicate, 35, // 2499: check predicate 35 |
| 11377 | OPC_Decode, 202, 19, 238, 1, // 2501: decode to VHADDsv2i32 using decoder 238 |
| 11378 | // 2501: } |
| 11379 | 1, 0, // 2506: case 0x1: { |
| 11380 | OPC_CheckPredicate, 35, // 2508: check predicate 35 |
| 11381 | OPC_Decode, 204, 19, 239, 1, // 2510: decode to VHADDsv4i32 using decoder 239 |
| 11382 | // 2510: } |
| 11383 | // 2510: } // switch Inst[6] |
| 11384 | // 2510: } |
| 11385 | 229, 3, 21, // 2515: case 0x1e5: { |
| 11386 | OPC_SwitchField, 6, 1, // 2518: switch Inst[6] { |
| 11387 | 0, 7, // 2521: case 0x0: { |
| 11388 | OPC_CheckPredicate, 35, // 2523: check predicate 35 |
| 11389 | OPC_Decode, 247, 16, 240, 1, // 2525: decode to VADDLsv2i64 using decoder 240 |
| 11390 | // 2525: } |
| 11391 | 1, 0, // 2530: case 0x1: { |
| 11392 | OPC_CheckPredicate, 35, // 2532: check predicate 35 |
| 11393 | OPC_Decode, 160, 23, 254, 1, // 2534: decode to VMLAslv2i32 using decoder 254 |
| 11394 | // 2534: } |
| 11395 | // 2534: } // switch Inst[6] |
| 11396 | // 2534: } |
| 11397 | 230, 3, 21, // 2539: case 0x1e6: { |
| 11398 | OPC_SwitchField, 6, 1, // 2542: switch Inst[6] { |
| 11399 | 0, 7, // 2545: case 0x0: { |
| 11400 | OPC_CheckPredicate, 35, // 2547: check predicate 35 |
| 11401 | OPC_Decode, 208, 19, 238, 1, // 2549: decode to VHADDuv2i32 using decoder 238 |
| 11402 | // 2549: } |
| 11403 | 1, 0, // 2554: case 0x1: { |
| 11404 | OPC_CheckPredicate, 35, // 2556: check predicate 35 |
| 11405 | OPC_Decode, 210, 19, 239, 1, // 2558: decode to VHADDuv4i32 using decoder 239 |
| 11406 | // 2558: } |
| 11407 | // 2558: } // switch Inst[6] |
| 11408 | // 2558: } |
| 11409 | 231, 3, 0, // 2563: case 0x1e7: { |
| 11410 | OPC_SwitchField, 6, 1, // 2566: switch Inst[6] { |
| 11411 | 0, 7, // 2569: case 0x0: { |
| 11412 | OPC_CheckPredicate, 35, // 2571: check predicate 35 |
| 11413 | OPC_Decode, 250, 16, 240, 1, // 2573: decode to VADDLuv2i64 using decoder 240 |
| 11414 | // 2573: } |
| 11415 | 1, 0, // 2578: case 0x1: { |
| 11416 | OPC_CheckPredicate, 35, // 2580: check predicate 35 |
| 11417 | OPC_Decode, 162, 23, 255, 1, // 2582: decode to VMLAslv4i32 using decoder 255 |
| 11418 | // 2582: } |
| 11419 | // 2582: } // switch Inst[6] |
| 11420 | // 2582: } |
| 11421 | // 2582: } // switch Inst[31:23] |
| 11422 | // 2582: } |
| 11423 | 1, 99, // 2587: case 0x1: { |
| 11424 | OPC_SwitchField, 23, 9, // 2589: switch Inst[31:23] { |
| 11425 | 228, 3, 21, // 2592: case 0x1e4: { |
| 11426 | OPC_SwitchField, 6, 1, // 2595: switch Inst[6] { |
| 11427 | 0, 7, // 2598: case 0x0: { |
| 11428 | OPC_CheckPredicate, 35, // 2600: check predicate 35 |
| 11429 | OPC_Decode, 184, 26, 238, 1, // 2602: decode to VRHADDsv2i32 using decoder 238 |
| 11430 | // 2602: } |
| 11431 | 1, 0, // 2607: case 0x1: { |
| 11432 | OPC_CheckPredicate, 35, // 2609: check predicate 35 |
| 11433 | OPC_Decode, 186, 26, 239, 1, // 2611: decode to VRHADDsv4i32 using decoder 239 |
| 11434 | // 2611: } |
| 11435 | // 2611: } // switch Inst[6] |
| 11436 | // 2611: } |
| 11437 | 229, 3, 21, // 2616: case 0x1e5: { |
| 11438 | OPC_SwitchField, 6, 1, // 2619: switch Inst[6] { |
| 11439 | 0, 7, // 2622: case 0x0: { |
| 11440 | OPC_CheckPredicate, 35, // 2624: check predicate 35 |
| 11441 | OPC_Decode, 254, 16, 241, 1, // 2626: decode to VADDWsv2i64 using decoder 241 |
| 11442 | // 2626: } |
| 11443 | 1, 0, // 2631: case 0x1: { |
| 11444 | OPC_CheckPredicate, 35, // 2633: check predicate 35 |
| 11445 | OPC_Decode, 156, 23, 254, 1, // 2635: decode to VMLAslfd using decoder 254 |
| 11446 | // 2635: } |
| 11447 | // 2635: } // switch Inst[6] |
| 11448 | // 2635: } |
| 11449 | 230, 3, 21, // 2640: case 0x1e6: { |
| 11450 | OPC_SwitchField, 6, 1, // 2643: switch Inst[6] { |
| 11451 | 0, 7, // 2646: case 0x0: { |
| 11452 | OPC_CheckPredicate, 35, // 2648: check predicate 35 |
| 11453 | OPC_Decode, 190, 26, 238, 1, // 2650: decode to VRHADDuv2i32 using decoder 238 |
| 11454 | // 2650: } |
| 11455 | 1, 0, // 2655: case 0x1: { |
| 11456 | OPC_CheckPredicate, 35, // 2657: check predicate 35 |
| 11457 | OPC_Decode, 192, 26, 239, 1, // 2659: decode to VRHADDuv4i32 using decoder 239 |
| 11458 | // 2659: } |
| 11459 | // 2659: } // switch Inst[6] |
| 11460 | // 2659: } |
| 11461 | 231, 3, 0, // 2664: case 0x1e7: { |
| 11462 | OPC_SwitchField, 6, 1, // 2667: switch Inst[6] { |
| 11463 | 0, 7, // 2670: case 0x0: { |
| 11464 | OPC_CheckPredicate, 35, // 2672: check predicate 35 |
| 11465 | OPC_Decode, 129, 17, 241, 1, // 2674: decode to VADDWuv2i64 using decoder 241 |
| 11466 | // 2674: } |
| 11467 | 1, 0, // 2679: case 0x1: { |
| 11468 | OPC_CheckPredicate, 35, // 2681: check predicate 35 |
| 11469 | OPC_Decode, 157, 23, 255, 1, // 2683: decode to VMLAslfq using decoder 255 |
| 11470 | // 2683: } |
| 11471 | // 2683: } // switch Inst[6] |
| 11472 | // 2683: } |
| 11473 | // 2683: } // switch Inst[31:23] |
| 11474 | // 2683: } |
| 11475 | 2, 99, // 2688: case 0x2: { |
| 11476 | OPC_SwitchField, 23, 9, // 2690: switch Inst[31:23] { |
| 11477 | 228, 3, 21, // 2693: case 0x1e4: { |
| 11478 | OPC_SwitchField, 6, 1, // 2696: switch Inst[6] { |
| 11479 | 0, 7, // 2699: case 0x0: { |
| 11480 | OPC_CheckPredicate, 35, // 2701: check predicate 35 |
| 11481 | OPC_Decode, 214, 19, 238, 1, // 2703: decode to VHSUBsv2i32 using decoder 238 |
| 11482 | // 2703: } |
| 11483 | 1, 0, // 2708: case 0x1: { |
| 11484 | OPC_CheckPredicate, 35, // 2710: check predicate 35 |
| 11485 | OPC_Decode, 216, 19, 239, 1, // 2712: decode to VHSUBsv4i32 using decoder 239 |
| 11486 | // 2712: } |
| 11487 | // 2712: } // switch Inst[6] |
| 11488 | // 2712: } |
| 11489 | 229, 3, 21, // 2717: case 0x1e5: { |
| 11490 | OPC_SwitchField, 6, 1, // 2720: switch Inst[6] { |
| 11491 | 0, 7, // 2723: case 0x0: { |
| 11492 | OPC_CheckPredicate, 35, // 2725: check predicate 35 |
| 11493 | OPC_Decode, 201, 30, 240, 1, // 2727: decode to VSUBLsv2i64 using decoder 240 |
| 11494 | // 2727: } |
| 11495 | 1, 0, // 2732: case 0x1: { |
| 11496 | OPC_CheckPredicate, 35, // 2734: check predicate 35 |
| 11497 | OPC_Decode, 141, 23, 128, 2, // 2736: decode to VMLALslsv2i32 using decoder 256 |
| 11498 | // 2736: } |
| 11499 | // 2736: } // switch Inst[6] |
| 11500 | // 2736: } |
| 11501 | 230, 3, 21, // 2741: case 0x1e6: { |
| 11502 | OPC_SwitchField, 6, 1, // 2744: switch Inst[6] { |
| 11503 | 0, 7, // 2747: case 0x0: { |
| 11504 | OPC_CheckPredicate, 35, // 2749: check predicate 35 |
| 11505 | OPC_Decode, 220, 19, 238, 1, // 2751: decode to VHSUBuv2i32 using decoder 238 |
| 11506 | // 2751: } |
| 11507 | 1, 0, // 2756: case 0x1: { |
| 11508 | OPC_CheckPredicate, 35, // 2758: check predicate 35 |
| 11509 | OPC_Decode, 222, 19, 239, 1, // 2760: decode to VHSUBuv4i32 using decoder 239 |
| 11510 | // 2760: } |
| 11511 | // 2760: } // switch Inst[6] |
| 11512 | // 2760: } |
| 11513 | 231, 3, 0, // 2765: case 0x1e7: { |
| 11514 | OPC_SwitchField, 6, 1, // 2768: switch Inst[6] { |
| 11515 | 0, 7, // 2771: case 0x0: { |
| 11516 | OPC_CheckPredicate, 35, // 2773: check predicate 35 |
| 11517 | OPC_Decode, 204, 30, 240, 1, // 2775: decode to VSUBLuv2i64 using decoder 240 |
| 11518 | // 2775: } |
| 11519 | 1, 0, // 2780: case 0x1: { |
| 11520 | OPC_CheckPredicate, 35, // 2782: check predicate 35 |
| 11521 | OPC_Decode, 143, 23, 128, 2, // 2784: decode to VMLALsluv2i32 using decoder 256 |
| 11522 | // 2784: } |
| 11523 | // 2784: } // switch Inst[6] |
| 11524 | // 2784: } |
| 11525 | // 2784: } // switch Inst[31:23] |
| 11526 | // 2784: } |
| 11527 | 3, 89, // 2789: case 0x3: { |
| 11528 | OPC_SwitchField, 23, 9, // 2791: switch Inst[31:23] { |
| 11529 | 228, 3, 21, // 2794: case 0x1e4: { |
| 11530 | OPC_SwitchField, 6, 1, // 2797: switch Inst[6] { |
| 11531 | 0, 7, // 2800: case 0x0: { |
| 11532 | OPC_CheckPredicate, 35, // 2802: check predicate 35 |
| 11533 | OPC_Decode, 219, 17, 238, 1, // 2804: decode to VCGTsv2i32 using decoder 238 |
| 11534 | // 2804: } |
| 11535 | 1, 0, // 2809: case 0x1: { |
| 11536 | OPC_CheckPredicate, 35, // 2811: check predicate 35 |
| 11537 | OPC_Decode, 221, 17, 239, 1, // 2813: decode to VCGTsv4i32 using decoder 239 |
| 11538 | // 2813: } |
| 11539 | // 2813: } // switch Inst[6] |
| 11540 | // 2813: } |
| 11541 | 229, 3, 21, // 2818: case 0x1e5: { |
| 11542 | OPC_SwitchField, 6, 1, // 2821: switch Inst[6] { |
| 11543 | 0, 7, // 2824: case 0x0: { |
| 11544 | OPC_CheckPredicate, 35, // 2826: check predicate 35 |
| 11545 | OPC_Decode, 208, 30, 241, 1, // 2828: decode to VSUBWsv2i64 using decoder 241 |
| 11546 | // 2828: } |
| 11547 | 1, 0, // 2833: case 0x1: { |
| 11548 | OPC_CheckPredicate, 35, // 2835: check predicate 35 |
| 11549 | OPC_Decode, 137, 25, 128, 2, // 2837: decode to VQDMLALslv2i32 using decoder 256 |
| 11550 | // 2837: } |
| 11551 | // 2837: } // switch Inst[6] |
| 11552 | // 2837: } |
| 11553 | 230, 3, 21, // 2842: case 0x1e6: { |
| 11554 | OPC_SwitchField, 6, 1, // 2845: switch Inst[6] { |
| 11555 | 0, 7, // 2848: case 0x0: { |
| 11556 | OPC_CheckPredicate, 35, // 2850: check predicate 35 |
| 11557 | OPC_Decode, 225, 17, 238, 1, // 2852: decode to VCGTuv2i32 using decoder 238 |
| 11558 | // 2852: } |
| 11559 | 1, 0, // 2857: case 0x1: { |
| 11560 | OPC_CheckPredicate, 35, // 2859: check predicate 35 |
| 11561 | OPC_Decode, 227, 17, 239, 1, // 2861: decode to VCGTuv4i32 using decoder 239 |
| 11562 | // 2861: } |
| 11563 | // 2861: } // switch Inst[6] |
| 11564 | // 2861: } |
| 11565 | 231, 3, 0, // 2866: case 0x1e7: { |
| 11566 | OPC_CheckPredicate, 35, // 2869: check predicate 35 |
| 11567 | OPC_CheckField, 6, 1, 0, // 2871: check Inst[6] == 0x0 |
| 11568 | OPC_Decode, 211, 30, 241, 1, // 2875: decode to VSUBWuv2i64 using decoder 241 |
| 11569 | // 2875: } |
| 11570 | // 2875: } // switch Inst[31:23] |
| 11571 | // 2875: } |
| 11572 | 4, 99, // 2880: case 0x4: { |
| 11573 | OPC_SwitchField, 23, 9, // 2882: switch Inst[31:23] { |
| 11574 | 228, 3, 21, // 2885: case 0x1e4: { |
| 11575 | OPC_SwitchField, 6, 1, // 2888: switch Inst[6] { |
| 11576 | 0, 7, // 2891: case 0x0: { |
| 11577 | OPC_CheckPredicate, 35, // 2893: check predicate 35 |
| 11578 | OPC_Decode, 216, 27, 242, 1, // 2895: decode to VSHLsv2i32 using decoder 242 |
| 11579 | // 2895: } |
| 11580 | 1, 0, // 2900: case 0x1: { |
| 11581 | OPC_CheckPredicate, 35, // 2902: check predicate 35 |
| 11582 | OPC_Decode, 219, 27, 243, 1, // 2904: decode to VSHLsv4i32 using decoder 243 |
| 11583 | // 2904: } |
| 11584 | // 2904: } // switch Inst[6] |
| 11585 | // 2904: } |
| 11586 | 229, 3, 21, // 2909: case 0x1e5: { |
| 11587 | OPC_SwitchField, 6, 1, // 2912: switch Inst[6] { |
| 11588 | 0, 7, // 2915: case 0x0: { |
| 11589 | OPC_CheckPredicate, 35, // 2917: check predicate 35 |
| 11590 | OPC_Decode, 244, 16, 244, 1, // 2919: decode to VADDHNv2i32 using decoder 244 |
| 11591 | // 2919: } |
| 11592 | 1, 0, // 2924: case 0x1: { |
| 11593 | OPC_CheckPredicate, 35, // 2926: check predicate 35 |
| 11594 | OPC_Decode, 191, 23, 254, 1, // 2928: decode to VMLSslv2i32 using decoder 254 |
| 11595 | // 2928: } |
| 11596 | // 2928: } // switch Inst[6] |
| 11597 | // 2928: } |
| 11598 | 230, 3, 21, // 2933: case 0x1e6: { |
| 11599 | OPC_SwitchField, 6, 1, // 2936: switch Inst[6] { |
| 11600 | 0, 7, // 2939: case 0x0: { |
| 11601 | OPC_CheckPredicate, 35, // 2941: check predicate 35 |
| 11602 | OPC_Decode, 224, 27, 242, 1, // 2943: decode to VSHLuv2i32 using decoder 242 |
| 11603 | // 2943: } |
| 11604 | 1, 0, // 2948: case 0x1: { |
| 11605 | OPC_CheckPredicate, 35, // 2950: check predicate 35 |
| 11606 | OPC_Decode, 227, 27, 243, 1, // 2952: decode to VSHLuv4i32 using decoder 243 |
| 11607 | // 2952: } |
| 11608 | // 2952: } // switch Inst[6] |
| 11609 | // 2952: } |
| 11610 | 231, 3, 0, // 2957: case 0x1e7: { |
| 11611 | OPC_SwitchField, 6, 1, // 2960: switch Inst[6] { |
| 11612 | 0, 7, // 2963: case 0x0: { |
| 11613 | OPC_CheckPredicate, 35, // 2965: check predicate 35 |
| 11614 | OPC_Decode, 158, 26, 244, 1, // 2967: decode to VRADDHNv2i32 using decoder 244 |
| 11615 | // 2967: } |
| 11616 | 1, 0, // 2972: case 0x1: { |
| 11617 | OPC_CheckPredicate, 35, // 2974: check predicate 35 |
| 11618 | OPC_Decode, 193, 23, 255, 1, // 2976: decode to VMLSslv4i32 using decoder 255 |
| 11619 | // 2976: } |
| 11620 | // 2976: } // switch Inst[6] |
| 11621 | // 2976: } |
| 11622 | // 2976: } // switch Inst[31:23] |
| 11623 | // 2976: } |
| 11624 | 5, 99, // 2981: case 0x5: { |
| 11625 | OPC_SwitchField, 23, 9, // 2983: switch Inst[31:23] { |
| 11626 | 228, 3, 21, // 2986: case 0x1e4: { |
| 11627 | OPC_SwitchField, 6, 1, // 2989: switch Inst[6] { |
| 11628 | 0, 7, // 2992: case 0x0: { |
| 11629 | OPC_CheckPredicate, 35, // 2994: check predicate 35 |
| 11630 | OPC_Decode, 242, 26, 242, 1, // 2996: decode to VRSHLsv2i32 using decoder 242 |
| 11631 | // 2996: } |
| 11632 | 1, 0, // 3001: case 0x1: { |
| 11633 | OPC_CheckPredicate, 35, // 3003: check predicate 35 |
| 11634 | OPC_Decode, 245, 26, 243, 1, // 3005: decode to VRSHLsv4i32 using decoder 243 |
| 11635 | // 3005: } |
| 11636 | // 3005: } // switch Inst[6] |
| 11637 | // 3005: } |
| 11638 | 229, 3, 21, // 3010: case 0x1e5: { |
| 11639 | OPC_SwitchField, 6, 1, // 3013: switch Inst[6] { |
| 11640 | 0, 7, // 3016: case 0x0: { |
| 11641 | OPC_CheckPredicate, 35, // 3018: check predicate 35 |
| 11642 | OPC_Decode, 181, 16, 245, 1, // 3020: decode to VABALsv2i64 using decoder 245 |
| 11643 | // 3020: } |
| 11644 | 1, 0, // 3025: case 0x1: { |
| 11645 | OPC_CheckPredicate, 35, // 3027: check predicate 35 |
| 11646 | OPC_Decode, 187, 23, 254, 1, // 3029: decode to VMLSslfd using decoder 254 |
| 11647 | // 3029: } |
| 11648 | // 3029: } // switch Inst[6] |
| 11649 | // 3029: } |
| 11650 | 230, 3, 21, // 3034: case 0x1e6: { |
| 11651 | OPC_SwitchField, 6, 1, // 3037: switch Inst[6] { |
| 11652 | 0, 7, // 3040: case 0x0: { |
| 11653 | OPC_CheckPredicate, 35, // 3042: check predicate 35 |
| 11654 | OPC_Decode, 250, 26, 242, 1, // 3044: decode to VRSHLuv2i32 using decoder 242 |
| 11655 | // 3044: } |
| 11656 | 1, 0, // 3049: case 0x1: { |
| 11657 | OPC_CheckPredicate, 35, // 3051: check predicate 35 |
| 11658 | OPC_Decode, 253, 26, 243, 1, // 3053: decode to VRSHLuv4i32 using decoder 243 |
| 11659 | // 3053: } |
| 11660 | // 3053: } // switch Inst[6] |
| 11661 | // 3053: } |
| 11662 | 231, 3, 0, // 3058: case 0x1e7: { |
| 11663 | OPC_SwitchField, 6, 1, // 3061: switch Inst[6] { |
| 11664 | 0, 7, // 3064: case 0x0: { |
| 11665 | OPC_CheckPredicate, 35, // 3066: check predicate 35 |
| 11666 | OPC_Decode, 184, 16, 245, 1, // 3068: decode to VABALuv2i64 using decoder 245 |
| 11667 | // 3068: } |
| 11668 | 1, 0, // 3073: case 0x1: { |
| 11669 | OPC_CheckPredicate, 35, // 3075: check predicate 35 |
| 11670 | OPC_Decode, 188, 23, 255, 1, // 3077: decode to VMLSslfq using decoder 255 |
| 11671 | // 3077: } |
| 11672 | // 3077: } // switch Inst[6] |
| 11673 | // 3077: } |
| 11674 | // 3077: } // switch Inst[31:23] |
| 11675 | // 3077: } |
| 11676 | 6, 99, // 3082: case 0x6: { |
| 11677 | OPC_SwitchField, 23, 9, // 3084: switch Inst[31:23] { |
| 11678 | 228, 3, 21, // 3087: case 0x1e4: { |
| 11679 | OPC_SwitchField, 6, 1, // 3090: switch Inst[6] { |
| 11680 | 0, 7, // 3093: case 0x0: { |
| 11681 | OPC_CheckPredicate, 35, // 3095: check predicate 35 |
| 11682 | OPC_Decode, 240, 22, 238, 1, // 3097: decode to VMAXsv2i32 using decoder 238 |
| 11683 | // 3097: } |
| 11684 | 1, 0, // 3102: case 0x1: { |
| 11685 | OPC_CheckPredicate, 35, // 3104: check predicate 35 |
| 11686 | OPC_Decode, 242, 22, 239, 1, // 3106: decode to VMAXsv4i32 using decoder 239 |
| 11687 | // 3106: } |
| 11688 | // 3106: } // switch Inst[6] |
| 11689 | // 3106: } |
| 11690 | 229, 3, 21, // 3111: case 0x1e5: { |
| 11691 | OPC_SwitchField, 6, 1, // 3114: switch Inst[6] { |
| 11692 | 0, 7, // 3117: case 0x0: { |
| 11693 | OPC_CheckPredicate, 35, // 3119: check predicate 35 |
| 11694 | OPC_Decode, 198, 30, 244, 1, // 3121: decode to VSUBHNv2i32 using decoder 244 |
| 11695 | // 3121: } |
| 11696 | 1, 0, // 3126: case 0x1: { |
| 11697 | OPC_CheckPredicate, 35, // 3128: check predicate 35 |
| 11698 | OPC_Decode, 172, 23, 128, 2, // 3130: decode to VMLSLslsv2i32 using decoder 256 |
| 11699 | // 3130: } |
| 11700 | // 3130: } // switch Inst[6] |
| 11701 | // 3130: } |
| 11702 | 230, 3, 21, // 3135: case 0x1e6: { |
| 11703 | OPC_SwitchField, 6, 1, // 3138: switch Inst[6] { |
| 11704 | 0, 7, // 3141: case 0x0: { |
| 11705 | OPC_CheckPredicate, 35, // 3143: check predicate 35 |
| 11706 | OPC_Decode, 246, 22, 238, 1, // 3145: decode to VMAXuv2i32 using decoder 238 |
| 11707 | // 3145: } |
| 11708 | 1, 0, // 3150: case 0x1: { |
| 11709 | OPC_CheckPredicate, 35, // 3152: check predicate 35 |
| 11710 | OPC_Decode, 248, 22, 239, 1, // 3154: decode to VMAXuv4i32 using decoder 239 |
| 11711 | // 3154: } |
| 11712 | // 3154: } // switch Inst[6] |
| 11713 | // 3154: } |
| 11714 | 231, 3, 0, // 3159: case 0x1e7: { |
| 11715 | OPC_SwitchField, 6, 1, // 3162: switch Inst[6] { |
| 11716 | 0, 7, // 3165: case 0x0: { |
| 11717 | OPC_CheckPredicate, 35, // 3167: check predicate 35 |
| 11718 | OPC_Decode, 173, 27, 244, 1, // 3169: decode to VRSUBHNv2i32 using decoder 244 |
| 11719 | // 3169: } |
| 11720 | 1, 0, // 3174: case 0x1: { |
| 11721 | OPC_CheckPredicate, 35, // 3176: check predicate 35 |
| 11722 | OPC_Decode, 174, 23, 128, 2, // 3178: decode to VMLSLsluv2i32 using decoder 256 |
| 11723 | // 3178: } |
| 11724 | // 3178: } // switch Inst[6] |
| 11725 | // 3178: } |
| 11726 | // 3178: } // switch Inst[31:23] |
| 11727 | // 3178: } |
| 11728 | 7, 89, // 3183: case 0x7: { |
| 11729 | OPC_SwitchField, 23, 9, // 3185: switch Inst[31:23] { |
| 11730 | 228, 3, 21, // 3188: case 0x1e4: { |
| 11731 | OPC_SwitchField, 6, 1, // 3191: switch Inst[6] { |
| 11732 | 0, 7, // 3194: case 0x0: { |
| 11733 | OPC_CheckPredicate, 35, // 3196: check predicate 35 |
| 11734 | OPC_Decode, 210, 16, 238, 1, // 3198: decode to VABDsv2i32 using decoder 238 |
| 11735 | // 3198: } |
| 11736 | 1, 0, // 3203: case 0x1: { |
| 11737 | OPC_CheckPredicate, 35, // 3205: check predicate 35 |
| 11738 | OPC_Decode, 212, 16, 239, 1, // 3207: decode to VABDsv4i32 using decoder 239 |
| 11739 | // 3207: } |
| 11740 | // 3207: } // switch Inst[6] |
| 11741 | // 3207: } |
| 11742 | 229, 3, 21, // 3212: case 0x1e5: { |
| 11743 | OPC_SwitchField, 6, 1, // 3215: switch Inst[6] { |
| 11744 | 0, 7, // 3218: case 0x0: { |
| 11745 | OPC_CheckPredicate, 35, // 3220: check predicate 35 |
| 11746 | OPC_Decode, 199, 16, 240, 1, // 3222: decode to VABDLsv2i64 using decoder 240 |
| 11747 | // 3222: } |
| 11748 | 1, 0, // 3227: case 0x1: { |
| 11749 | OPC_CheckPredicate, 35, // 3229: check predicate 35 |
| 11750 | OPC_Decode, 141, 25, 128, 2, // 3231: decode to VQDMLSLslv2i32 using decoder 256 |
| 11751 | // 3231: } |
| 11752 | // 3231: } // switch Inst[6] |
| 11753 | // 3231: } |
| 11754 | 230, 3, 21, // 3236: case 0x1e6: { |
| 11755 | OPC_SwitchField, 6, 1, // 3239: switch Inst[6] { |
| 11756 | 0, 7, // 3242: case 0x0: { |
| 11757 | OPC_CheckPredicate, 35, // 3244: check predicate 35 |
| 11758 | OPC_Decode, 216, 16, 238, 1, // 3246: decode to VABDuv2i32 using decoder 238 |
| 11759 | // 3246: } |
| 11760 | 1, 0, // 3251: case 0x1: { |
| 11761 | OPC_CheckPredicate, 35, // 3253: check predicate 35 |
| 11762 | OPC_Decode, 218, 16, 239, 1, // 3255: decode to VABDuv4i32 using decoder 239 |
| 11763 | // 3255: } |
| 11764 | // 3255: } // switch Inst[6] |
| 11765 | // 3255: } |
| 11766 | 231, 3, 0, // 3260: case 0x1e7: { |
| 11767 | OPC_CheckPredicate, 35, // 3263: check predicate 35 |
| 11768 | OPC_CheckField, 6, 1, 0, // 3265: check Inst[6] == 0x0 |
| 11769 | OPC_Decode, 202, 16, 240, 1, // 3269: decode to VABDLuv2i64 using decoder 240 |
| 11770 | // 3269: } |
| 11771 | // 3269: } // switch Inst[31:23] |
| 11772 | // 3269: } |
| 11773 | 8, 99, // 3274: case 0x8: { |
| 11774 | OPC_SwitchField, 23, 9, // 3276: switch Inst[31:23] { |
| 11775 | 228, 3, 21, // 3279: case 0x1e4: { |
| 11776 | OPC_SwitchField, 6, 1, // 3282: switch Inst[6] { |
| 11777 | 0, 7, // 3285: case 0x0: { |
| 11778 | OPC_CheckPredicate, 35, // 3287: check predicate 35 |
| 11779 | OPC_Decode, 138, 17, 238, 1, // 3289: decode to VADDv2i32 using decoder 238 |
| 11780 | // 3289: } |
| 11781 | 1, 0, // 3294: case 0x1: { |
| 11782 | OPC_CheckPredicate, 35, // 3296: check predicate 35 |
| 11783 | OPC_Decode, 141, 17, 239, 1, // 3298: decode to VADDv4i32 using decoder 239 |
| 11784 | // 3298: } |
| 11785 | // 3298: } // switch Inst[6] |
| 11786 | // 3298: } |
| 11787 | 229, 3, 21, // 3303: case 0x1e5: { |
| 11788 | OPC_SwitchField, 6, 1, // 3306: switch Inst[6] { |
| 11789 | 0, 7, // 3309: case 0x0: { |
| 11790 | OPC_CheckPredicate, 35, // 3311: check predicate 35 |
| 11791 | OPC_Decode, 145, 23, 245, 1, // 3313: decode to VMLALsv2i64 using decoder 245 |
| 11792 | // 3313: } |
| 11793 | 1, 0, // 3318: case 0x1: { |
| 11794 | OPC_CheckPredicate, 35, // 3320: check predicate 35 |
| 11795 | OPC_Decode, 152, 24, 129, 2, // 3322: decode to VMULslv2i32 using decoder 257 |
| 11796 | // 3322: } |
| 11797 | // 3322: } // switch Inst[6] |
| 11798 | // 3322: } |
| 11799 | 230, 3, 21, // 3327: case 0x1e6: { |
| 11800 | OPC_SwitchField, 6, 1, // 3330: switch Inst[6] { |
| 11801 | 0, 7, // 3333: case 0x0: { |
| 11802 | OPC_CheckPredicate, 35, // 3335: check predicate 35 |
| 11803 | OPC_Decode, 220, 30, 238, 1, // 3337: decode to VSUBv2i32 using decoder 238 |
| 11804 | // 3337: } |
| 11805 | 1, 0, // 3342: case 0x1: { |
| 11806 | OPC_CheckPredicate, 35, // 3344: check predicate 35 |
| 11807 | OPC_Decode, 223, 30, 239, 1, // 3346: decode to VSUBv4i32 using decoder 239 |
| 11808 | // 3346: } |
| 11809 | // 3346: } // switch Inst[6] |
| 11810 | // 3346: } |
| 11811 | 231, 3, 0, // 3351: case 0x1e7: { |
| 11812 | OPC_SwitchField, 6, 1, // 3354: switch Inst[6] { |
| 11813 | 0, 7, // 3357: case 0x0: { |
| 11814 | OPC_CheckPredicate, 35, // 3359: check predicate 35 |
| 11815 | OPC_Decode, 148, 23, 245, 1, // 3361: decode to VMLALuv2i64 using decoder 245 |
| 11816 | // 3361: } |
| 11817 | 1, 0, // 3366: case 0x1: { |
| 11818 | OPC_CheckPredicate, 35, // 3368: check predicate 35 |
| 11819 | OPC_Decode, 154, 24, 130, 2, // 3370: decode to VMULslv4i32 using decoder 258 |
| 11820 | // 3370: } |
| 11821 | // 3370: } // switch Inst[6] |
| 11822 | // 3370: } |
| 11823 | // 3370: } // switch Inst[31:23] |
| 11824 | // 3370: } |
| 11825 | 9, 89, // 3375: case 0x9: { |
| 11826 | OPC_SwitchField, 23, 9, // 3377: switch Inst[31:23] { |
| 11827 | 228, 3, 21, // 3380: case 0x1e4: { |
| 11828 | OPC_SwitchField, 6, 1, // 3383: switch Inst[6] { |
| 11829 | 0, 7, // 3386: case 0x0: { |
| 11830 | OPC_CheckPredicate, 35, // 3388: check predicate 35 |
| 11831 | OPC_Decode, 165, 23, 246, 1, // 3390: decode to VMLAv2i32 using decoder 246 |
| 11832 | // 3390: } |
| 11833 | 1, 0, // 3395: case 0x1: { |
| 11834 | OPC_CheckPredicate, 35, // 3397: check predicate 35 |
| 11835 | OPC_Decode, 167, 23, 247, 1, // 3399: decode to VMLAv4i32 using decoder 247 |
| 11836 | // 3399: } |
| 11837 | // 3399: } // switch Inst[6] |
| 11838 | // 3399: } |
| 11839 | 229, 3, 21, // 3404: case 0x1e5: { |
| 11840 | OPC_SwitchField, 6, 1, // 3407: switch Inst[6] { |
| 11841 | 0, 7, // 3410: case 0x0: { |
| 11842 | OPC_CheckPredicate, 35, // 3412: check predicate 35 |
| 11843 | OPC_Decode, 139, 25, 245, 1, // 3414: decode to VQDMLALv2i64 using decoder 245 |
| 11844 | // 3414: } |
| 11845 | 1, 0, // 3419: case 0x1: { |
| 11846 | OPC_CheckPredicate, 35, // 3421: check predicate 35 |
| 11847 | OPC_Decode, 148, 24, 129, 2, // 3423: decode to VMULslfd using decoder 257 |
| 11848 | // 3423: } |
| 11849 | // 3423: } // switch Inst[6] |
| 11850 | // 3423: } |
| 11851 | 230, 3, 21, // 3428: case 0x1e6: { |
| 11852 | OPC_SwitchField, 6, 1, // 3431: switch Inst[6] { |
| 11853 | 0, 7, // 3434: case 0x0: { |
| 11854 | OPC_CheckPredicate, 35, // 3436: check predicate 35 |
| 11855 | OPC_Decode, 196, 23, 246, 1, // 3438: decode to VMLSv2i32 using decoder 246 |
| 11856 | // 3438: } |
| 11857 | 1, 0, // 3443: case 0x1: { |
| 11858 | OPC_CheckPredicate, 35, // 3445: check predicate 35 |
| 11859 | OPC_Decode, 198, 23, 247, 1, // 3447: decode to VMLSv4i32 using decoder 247 |
| 11860 | // 3447: } |
| 11861 | // 3447: } // switch Inst[6] |
| 11862 | // 3447: } |
| 11863 | 231, 3, 0, // 3452: case 0x1e7: { |
| 11864 | OPC_CheckPredicate, 35, // 3455: check predicate 35 |
| 11865 | OPC_CheckField, 6, 1, 1, // 3457: check Inst[6] == 0x1 |
| 11866 | OPC_Decode, 149, 24, 130, 2, // 3461: decode to VMULslfq using decoder 258 |
| 11867 | // 3461: } |
| 11868 | // 3461: } // switch Inst[31:23] |
| 11869 | // 3461: } |
| 11870 | 10, 79, // 3466: case 0xa: { |
| 11871 | OPC_SwitchField, 23, 9, // 3468: switch Inst[31:23] { |
| 11872 | 228, 3, 11, // 3471: case 0x1e4: { |
| 11873 | OPC_CheckPredicate, 35, // 3474: check predicate 35 |
| 11874 | OPC_CheckField, 6, 1, 0, // 3476: check Inst[6] == 0x0 |
| 11875 | OPC_Decode, 230, 24, 238, 1, // 3480: decode to VPMAXs32 using decoder 238 |
| 11876 | // 3480: } |
| 11877 | 229, 3, 21, // 3485: case 0x1e5: { |
| 11878 | OPC_SwitchField, 6, 1, // 3488: switch Inst[6] { |
| 11879 | 0, 7, // 3491: case 0x0: { |
| 11880 | OPC_CheckPredicate, 35, // 3493: check predicate 35 |
| 11881 | OPC_Decode, 176, 23, 245, 1, // 3495: decode to VMLSLsv2i64 using decoder 245 |
| 11882 | // 3495: } |
| 11883 | 1, 0, // 3500: case 0x1: { |
| 11884 | OPC_CheckPredicate, 35, // 3502: check predicate 35 |
| 11885 | OPC_Decode, 131, 24, 131, 2, // 3504: decode to VMULLslsv2i32 using decoder 259 |
| 11886 | // 3504: } |
| 11887 | // 3504: } // switch Inst[6] |
| 11888 | // 3504: } |
| 11889 | 230, 3, 11, // 3509: case 0x1e6: { |
| 11890 | OPC_CheckPredicate, 35, // 3512: check predicate 35 |
| 11891 | OPC_CheckField, 6, 1, 0, // 3514: check Inst[6] == 0x0 |
| 11892 | OPC_Decode, 233, 24, 238, 1, // 3518: decode to VPMAXu32 using decoder 238 |
| 11893 | // 3518: } |
| 11894 | 231, 3, 0, // 3523: case 0x1e7: { |
| 11895 | OPC_SwitchField, 6, 1, // 3526: switch Inst[6] { |
| 11896 | 0, 7, // 3529: case 0x0: { |
| 11897 | OPC_CheckPredicate, 35, // 3531: check predicate 35 |
| 11898 | OPC_Decode, 179, 23, 245, 1, // 3533: decode to VMLSLuv2i64 using decoder 245 |
| 11899 | // 3533: } |
| 11900 | 1, 0, // 3538: case 0x1: { |
| 11901 | OPC_CheckPredicate, 35, // 3540: check predicate 35 |
| 11902 | OPC_Decode, 133, 24, 131, 2, // 3542: decode to VMULLsluv2i32 using decoder 259 |
| 11903 | // 3542: } |
| 11904 | // 3542: } // switch Inst[6] |
| 11905 | // 3542: } |
| 11906 | // 3542: } // switch Inst[31:23] |
| 11907 | // 3542: } |
| 11908 | 11, 75, // 3547: case 0xb: { |
| 11909 | OPC_SwitchField, 23, 9, // 3549: switch Inst[31:23] { |
| 11910 | 228, 3, 21, // 3552: case 0x1e4: { |
| 11911 | OPC_SwitchField, 6, 1, // 3555: switch Inst[6] { |
| 11912 | 0, 7, // 3558: case 0x0: { |
| 11913 | OPC_CheckPredicate, 35, // 3560: check predicate 35 |
| 11914 | OPC_Decode, 149, 25, 238, 1, // 3562: decode to VQDMULHv2i32 using decoder 238 |
| 11915 | // 3562: } |
| 11916 | 1, 0, // 3567: case 0x1: { |
| 11917 | OPC_CheckPredicate, 35, // 3569: check predicate 35 |
| 11918 | OPC_Decode, 151, 25, 239, 1, // 3571: decode to VQDMULHv4i32 using decoder 239 |
| 11919 | // 3571: } |
| 11920 | // 3571: } // switch Inst[6] |
| 11921 | // 3571: } |
| 11922 | 229, 3, 21, // 3576: case 0x1e5: { |
| 11923 | OPC_SwitchField, 6, 1, // 3579: switch Inst[6] { |
| 11924 | 0, 7, // 3582: case 0x0: { |
| 11925 | OPC_CheckPredicate, 35, // 3584: check predicate 35 |
| 11926 | OPC_Decode, 143, 25, 245, 1, // 3586: decode to VQDMLSLv2i64 using decoder 245 |
| 11927 | // 3586: } |
| 11928 | 1, 0, // 3591: case 0x1: { |
| 11929 | OPC_CheckPredicate, 35, // 3593: check predicate 35 |
| 11930 | OPC_Decode, 153, 25, 131, 2, // 3595: decode to VQDMULLslv2i32 using decoder 259 |
| 11931 | // 3595: } |
| 11932 | // 3595: } // switch Inst[6] |
| 11933 | // 3595: } |
| 11934 | 230, 3, 0, // 3600: case 0x1e6: { |
| 11935 | OPC_SwitchField, 6, 1, // 3603: switch Inst[6] { |
| 11936 | 0, 7, // 3606: case 0x0: { |
| 11937 | OPC_CheckPredicate, 35, // 3608: check predicate 35 |
| 11938 | OPC_Decode, 192, 25, 238, 1, // 3610: decode to VQRDMULHv2i32 using decoder 238 |
| 11939 | // 3610: } |
| 11940 | 1, 0, // 3615: case 0x1: { |
| 11941 | OPC_CheckPredicate, 35, // 3617: check predicate 35 |
| 11942 | OPC_Decode, 194, 25, 239, 1, // 3619: decode to VQRDMULHv4i32 using decoder 239 |
| 11943 | // 3619: } |
| 11944 | // 3619: } // switch Inst[6] |
| 11945 | // 3619: } |
| 11946 | // 3619: } // switch Inst[31:23] |
| 11947 | // 3619: } |
| 11948 | 12, 53, // 3624: case 0xc: { |
| 11949 | OPC_SwitchField, 6, 1, // 3626: switch Inst[6] { |
| 11950 | 0, 23, // 3629: case 0x0: { |
| 11951 | OPC_SwitchField, 23, 9, // 3631: switch Inst[31:23] { |
| 11952 | 229, 3, 7, // 3634: case 0x1e5: { |
| 11953 | OPC_CheckPredicate, 35, // 3637: check predicate 35 |
| 11954 | OPC_Decode, 135, 24, 240, 1, // 3639: decode to VMULLsv2i64 using decoder 240 |
| 11955 | // 3639: } |
| 11956 | 231, 3, 0, // 3644: case 0x1e7: { |
| 11957 | OPC_CheckPredicate, 35, // 3647: check predicate 35 |
| 11958 | OPC_Decode, 138, 24, 240, 1, // 3649: decode to VMULLuv2i64 using decoder 240 |
| 11959 | // 3649: } |
| 11960 | // 3649: } // switch Inst[31:23] |
| 11961 | // 3649: } |
| 11962 | 1, 0, // 3654: case 0x1: { |
| 11963 | OPC_SwitchField, 23, 9, // 3656: switch Inst[31:23] { |
| 11964 | 229, 3, 7, // 3659: case 0x1e5: { |
| 11965 | OPC_CheckPredicate, 35, // 3662: check predicate 35 |
| 11966 | OPC_Decode, 145, 25, 129, 2, // 3664: decode to VQDMULHslv2i32 using decoder 257 |
| 11967 | // 3664: } |
| 11968 | 231, 3, 0, // 3669: case 0x1e7: { |
| 11969 | OPC_CheckPredicate, 35, // 3672: check predicate 35 |
| 11970 | OPC_Decode, 147, 25, 130, 2, // 3674: decode to VQDMULHslv4i32 using decoder 258 |
| 11971 | // 3674: } |
| 11972 | // 3674: } // switch Inst[31:23] |
| 11973 | // 3674: } |
| 11974 | // 3674: } // switch Inst[6] |
| 11975 | // 3674: } |
| 11976 | 13, 89, // 3679: case 0xd: { |
| 11977 | OPC_SwitchField, 23, 9, // 3681: switch Inst[31:23] { |
| 11978 | 228, 3, 21, // 3684: case 0x1e4: { |
| 11979 | OPC_SwitchField, 6, 1, // 3687: switch Inst[6] { |
| 11980 | 0, 7, // 3690: case 0x0: { |
| 11981 | OPC_CheckPredicate, 35, // 3692: check predicate 35 |
| 11982 | OPC_Decode, 214, 30, 238, 1, // 3694: decode to VSUBfd using decoder 238 |
| 11983 | // 3694: } |
| 11984 | 1, 0, // 3699: case 0x1: { |
| 11985 | OPC_CheckPredicate, 35, // 3701: check predicate 35 |
| 11986 | OPC_Decode, 215, 30, 239, 1, // 3703: decode to VSUBfq using decoder 239 |
| 11987 | // 3703: } |
| 11988 | // 3703: } // switch Inst[6] |
| 11989 | // 3703: } |
| 11990 | 229, 3, 21, // 3708: case 0x1e5: { |
| 11991 | OPC_SwitchField, 6, 1, // 3711: switch Inst[6] { |
| 11992 | 0, 7, // 3714: case 0x0: { |
| 11993 | OPC_CheckPredicate, 35, // 3716: check predicate 35 |
| 11994 | OPC_Decode, 155, 25, 240, 1, // 3718: decode to VQDMULLv2i64 using decoder 240 |
| 11995 | // 3718: } |
| 11996 | 1, 0, // 3723: case 0x1: { |
| 11997 | OPC_CheckPredicate, 35, // 3725: check predicate 35 |
| 11998 | OPC_Decode, 188, 25, 129, 2, // 3727: decode to VQRDMULHslv2i32 using decoder 257 |
| 11999 | // 3727: } |
| 12000 | // 3727: } // switch Inst[6] |
| 12001 | // 3727: } |
| 12002 | 230, 3, 21, // 3732: case 0x1e6: { |
| 12003 | OPC_SwitchField, 6, 1, // 3735: switch Inst[6] { |
| 12004 | 0, 7, // 3738: case 0x0: { |
| 12005 | OPC_CheckPredicate, 35, // 3740: check predicate 35 |
| 12006 | OPC_Decode, 205, 16, 238, 1, // 3742: decode to VABDfd using decoder 238 |
| 12007 | // 3742: } |
| 12008 | 1, 0, // 3747: case 0x1: { |
| 12009 | OPC_CheckPredicate, 35, // 3749: check predicate 35 |
| 12010 | OPC_Decode, 206, 16, 239, 1, // 3751: decode to VABDfq using decoder 239 |
| 12011 | // 3751: } |
| 12012 | // 3751: } // switch Inst[6] |
| 12013 | // 3751: } |
| 12014 | 231, 3, 0, // 3756: case 0x1e7: { |
| 12015 | OPC_CheckPredicate, 35, // 3759: check predicate 35 |
| 12016 | OPC_CheckField, 6, 1, 1, // 3761: check Inst[6] == 0x1 |
| 12017 | OPC_Decode, 190, 25, 130, 2, // 3765: decode to VQRDMULHslv4i32 using decoder 258 |
| 12018 | // 3765: } |
| 12019 | // 3765: } // switch Inst[31:23] |
| 12020 | // 3765: } |
| 12021 | 14, 65, // 3770: case 0xe: { |
| 12022 | OPC_SwitchField, 23, 9, // 3772: switch Inst[31:23] { |
| 12023 | 229, 3, 21, // 3775: case 0x1e5: { |
| 12024 | OPC_SwitchField, 6, 1, // 3778: switch Inst[6] { |
| 12025 | 0, 7, // 3781: case 0x0: { |
| 12026 | OPC_CheckPredicate, 38, // 3783: check predicate 38 |
| 12027 | OPC_Decode, 129, 24, 132, 2, // 3785: decode to VMULLp64 using decoder 260 |
| 12028 | // 3785: } |
| 12029 | 1, 0, // 3790: case 0x1: { |
| 12030 | OPC_CheckPredicate, 37, // 3792: check predicate 37 |
| 12031 | OPC_Decode, 172, 25, 254, 1, // 3794: decode to VQRDMLAHslv2i32 using decoder 254 |
| 12032 | // 3794: } |
| 12033 | // 3794: } // switch Inst[6] |
| 12034 | // 3794: } |
| 12035 | 230, 3, 21, // 3799: case 0x1e6: { |
| 12036 | OPC_SwitchField, 6, 1, // 3802: switch Inst[6] { |
| 12037 | 0, 7, // 3805: case 0x0: { |
| 12038 | OPC_CheckPredicate, 35, // 3807: check predicate 35 |
| 12039 | OPC_Decode, 214, 17, 238, 1, // 3809: decode to VCGTfd using decoder 238 |
| 12040 | // 3809: } |
| 12041 | 1, 0, // 3814: case 0x1: { |
| 12042 | OPC_CheckPredicate, 35, // 3816: check predicate 35 |
| 12043 | OPC_Decode, 215, 17, 239, 1, // 3818: decode to VCGTfq using decoder 239 |
| 12044 | // 3818: } |
| 12045 | // 3818: } // switch Inst[6] |
| 12046 | // 3818: } |
| 12047 | 231, 3, 0, // 3823: case 0x1e7: { |
| 12048 | OPC_CheckPredicate, 37, // 3826: check predicate 37 |
| 12049 | OPC_CheckField, 6, 1, 1, // 3828: check Inst[6] == 0x1 |
| 12050 | OPC_Decode, 174, 25, 255, 1, // 3832: decode to VQRDMLAHslv4i32 using decoder 255 |
| 12051 | // 3832: } |
| 12052 | // 3832: } // switch Inst[31:23] |
| 12053 | // 3832: } |
| 12054 | 15, 0, // 3837: case 0xf: { |
| 12055 | OPC_SwitchField, 23, 9, // 3839: switch Inst[31:23] { |
| 12056 | 228, 3, 21, // 3842: case 0x1e4: { |
| 12057 | OPC_SwitchField, 6, 1, // 3845: switch Inst[6] { |
| 12058 | 0, 7, // 3848: case 0x0: { |
| 12059 | OPC_CheckPredicate, 35, // 3850: check predicate 35 |
| 12060 | OPC_Decode, 251, 22, 238, 1, // 3852: decode to VMINfd using decoder 238 |
| 12061 | // 3852: } |
| 12062 | 1, 0, // 3857: case 0x1: { |
| 12063 | OPC_CheckPredicate, 35, // 3859: check predicate 35 |
| 12064 | OPC_Decode, 252, 22, 239, 1, // 3861: decode to VMINfq using decoder 239 |
| 12065 | // 3861: } |
| 12066 | // 3861: } // switch Inst[6] |
| 12067 | // 3861: } |
| 12068 | 229, 3, 11, // 3866: case 0x1e5: { |
| 12069 | OPC_CheckPredicate, 37, // 3869: check predicate 37 |
| 12070 | OPC_CheckField, 6, 1, 1, // 3871: check Inst[6] == 0x1 |
| 12071 | OPC_Decode, 180, 25, 254, 1, // 3875: decode to VQRDMLSHslv2i32 using decoder 254 |
| 12072 | // 3875: } |
| 12073 | 230, 3, 11, // 3880: case 0x1e6: { |
| 12074 | OPC_CheckPredicate, 35, // 3883: check predicate 35 |
| 12075 | OPC_CheckField, 6, 1, 0, // 3885: check Inst[6] == 0x0 |
| 12076 | OPC_Decode, 235, 24, 238, 1, // 3889: decode to VPMINf using decoder 238 |
| 12077 | // 3889: } |
| 12078 | 231, 3, 0, // 3894: case 0x1e7: { |
| 12079 | OPC_CheckPredicate, 37, // 3897: check predicate 37 |
| 12080 | OPC_CheckField, 6, 1, 1, // 3899: check Inst[6] == 0x1 |
| 12081 | OPC_Decode, 182, 25, 255, 1, // 3903: decode to VQRDMLSHslv4i32 using decoder 255 |
| 12082 | // 3903: } |
| 12083 | // 3903: } // switch Inst[31:23] |
| 12084 | // 3903: } |
| 12085 | // 3903: } // switch Inst[11:8] |
| 12086 | // 3903: } |
| 12087 | 3, 0, // 3908: case 0x3: { |
| 12088 | OPC_SwitchField, 23, 9, // 3910: switch Inst[31:23] { |
| 12089 | 228, 3, 118, // 3913: case 0x1e4: { |
| 12090 | OPC_SwitchField, 8, 4, // 3916: switch Inst[11:8] { |
| 12091 | 4, 21, // 3919: case 0x4: { |
| 12092 | OPC_SwitchField, 6, 1, // 3921: switch Inst[6] { |
| 12093 | 0, 7, // 3924: case 0x0: { |
| 12094 | OPC_CheckPredicate, 35, // 3926: check predicate 35 |
| 12095 | OPC_Decode, 215, 27, 242, 1, // 3928: decode to VSHLsv1i64 using decoder 242 |
| 12096 | // 3928: } |
| 12097 | 1, 0, // 3933: case 0x1: { |
| 12098 | OPC_CheckPredicate, 35, // 3935: check predicate 35 |
| 12099 | OPC_Decode, 217, 27, 243, 1, // 3937: decode to VSHLsv2i64 using decoder 243 |
| 12100 | // 3937: } |
| 12101 | // 3937: } // switch Inst[6] |
| 12102 | // 3937: } |
| 12103 | 5, 21, // 3942: case 0x5: { |
| 12104 | OPC_SwitchField, 6, 1, // 3944: switch Inst[6] { |
| 12105 | 0, 7, // 3947: case 0x0: { |
| 12106 | OPC_CheckPredicate, 35, // 3949: check predicate 35 |
| 12107 | OPC_Decode, 241, 26, 242, 1, // 3951: decode to VRSHLsv1i64 using decoder 242 |
| 12108 | // 3951: } |
| 12109 | 1, 0, // 3956: case 0x1: { |
| 12110 | OPC_CheckPredicate, 35, // 3958: check predicate 35 |
| 12111 | OPC_Decode, 243, 26, 243, 1, // 3960: decode to VRSHLsv2i64 using decoder 243 |
| 12112 | // 3960: } |
| 12113 | // 3960: } // switch Inst[6] |
| 12114 | // 3960: } |
| 12115 | 8, 21, // 3965: case 0x8: { |
| 12116 | OPC_SwitchField, 6, 1, // 3967: switch Inst[6] { |
| 12117 | 0, 7, // 3970: case 0x0: { |
| 12118 | OPC_CheckPredicate, 35, // 3972: check predicate 35 |
| 12119 | OPC_Decode, 137, 17, 238, 1, // 3974: decode to VADDv1i64 using decoder 238 |
| 12120 | // 3974: } |
| 12121 | 1, 0, // 3979: case 0x1: { |
| 12122 | OPC_CheckPredicate, 35, // 3981: check predicate 35 |
| 12123 | OPC_Decode, 139, 17, 239, 1, // 3983: decode to VADDv2i64 using decoder 239 |
| 12124 | // 3983: } |
| 12125 | // 3983: } // switch Inst[6] |
| 12126 | // 3983: } |
| 12127 | 13, 21, // 3988: case 0xd: { |
| 12128 | OPC_SwitchField, 6, 1, // 3990: switch Inst[6] { |
| 12129 | 0, 7, // 3993: case 0x0: { |
| 12130 | OPC_CheckPredicate, 36, // 3995: check predicate 36 |
| 12131 | OPC_Decode, 216, 30, 238, 1, // 3997: decode to VSUBhd using decoder 238 |
| 12132 | // 3997: } |
| 12133 | 1, 0, // 4002: case 0x1: { |
| 12134 | OPC_CheckPredicate, 36, // 4004: check predicate 36 |
| 12135 | OPC_Decode, 217, 30, 239, 1, // 4006: decode to VSUBhq using decoder 239 |
| 12136 | // 4006: } |
| 12137 | // 4006: } // switch Inst[6] |
| 12138 | // 4006: } |
| 12139 | 15, 0, // 4011: case 0xf: { |
| 12140 | OPC_SwitchField, 6, 1, // 4013: switch Inst[6] { |
| 12141 | 0, 7, // 4016: case 0x0: { |
| 12142 | OPC_CheckPredicate, 36, // 4018: check predicate 36 |
| 12143 | OPC_Decode, 253, 22, 238, 1, // 4020: decode to VMINhd using decoder 238 |
| 12144 | // 4020: } |
| 12145 | 1, 0, // 4025: case 0x1: { |
| 12146 | OPC_CheckPredicate, 36, // 4027: check predicate 36 |
| 12147 | OPC_Decode, 254, 22, 239, 1, // 4029: decode to VMINhq using decoder 239 |
| 12148 | // 4029: } |
| 12149 | // 4029: } // switch Inst[6] |
| 12150 | // 4029: } |
| 12151 | // 4029: } // switch Inst[11:8] |
| 12152 | // 4029: } |
| 12153 | 229, 3, 90, // 4034: case 0x1e5: { |
| 12154 | OPC_SwitchField, 6, 1, // 4037: switch Inst[6] { |
| 12155 | 0, 37, // 4040: case 0x0: { |
| 12156 | OPC_CheckField, 11, 1, 0, // 4042: check Inst[11] == 0x0 |
| 12157 | OPC_Scope, 11, // 4046: try { |
| 12158 | OPC_CheckField, 8, 2, 0, // 4048: check Inst[9:8] == 0x0 |
| 12159 | OPC_CheckPredicate, 35, // 4052: check predicate 35 |
| 12160 | OPC_Decode, 156, 19, 133, 2, // 4054: decode to VEXTd32 using decoder 261 |
| 12161 | OPC_Scope, 11, // 4059: } else try { |
| 12162 | OPC_CheckField, 8, 1, 0, // 4061: check Inst[8] == 0x0 |
| 12163 | OPC_CheckPredicate, 35, // 4065: check predicate 35 |
| 12164 | OPC_Decode, 155, 19, 134, 2, // 4067: decode to VEXTd16 using decoder 262 |
| 12165 | // 4067: } else try { |
| 12166 | OPC_CheckPredicate, 35, // 4072: check predicate 35 |
| 12167 | OPC_Decode, 157, 19, 135, 2, // 4074: decode to VEXTd8 using decoder 263 |
| 12168 | // 4074: } |
| 12169 | // 4074: } |
| 12170 | 1, 0, // 4079: case 0x1: { |
| 12171 | OPC_Scope, 11, // 4081: try { |
| 12172 | OPC_CheckField, 8, 3, 0, // 4083: check Inst[10:8] == 0x0 |
| 12173 | OPC_CheckPredicate, 35, // 4087: check predicate 35 |
| 12174 | OPC_Decode, 160, 19, 136, 2, // 4089: decode to VEXTq64 using decoder 264 |
| 12175 | OPC_Scope, 11, // 4094: } else try { |
| 12176 | OPC_CheckField, 8, 2, 0, // 4096: check Inst[9:8] == 0x0 |
| 12177 | OPC_CheckPredicate, 35, // 4100: check predicate 35 |
| 12178 | OPC_Decode, 159, 19, 137, 2, // 4102: decode to VEXTq32 using decoder 265 |
| 12179 | OPC_Scope, 11, // 4107: } else try { |
| 12180 | OPC_CheckField, 8, 1, 0, // 4109: check Inst[8] == 0x0 |
| 12181 | OPC_CheckPredicate, 35, // 4113: check predicate 35 |
| 12182 | OPC_Decode, 158, 19, 138, 2, // 4115: decode to VEXTq16 using decoder 266 |
| 12183 | // 4115: } else try { |
| 12184 | OPC_CheckPredicate, 35, // 4120: check predicate 35 |
| 12185 | OPC_Decode, 161, 19, 139, 2, // 4122: decode to VEXTq8 using decoder 267 |
| 12186 | // 4122: } |
| 12187 | // 4122: } |
| 12188 | // 4122: } // switch Inst[6] |
| 12189 | // 4122: } |
| 12190 | 230, 3, 131, 1, // 4127: case 0x1e6: { |
| 12191 | OPC_SwitchField, 8, 4, // 4131: switch Inst[11:8] { |
| 12192 | 4, 21, // 4134: case 0x4: { |
| 12193 | OPC_SwitchField, 6, 1, // 4136: switch Inst[6] { |
| 12194 | 0, 7, // 4139: case 0x0: { |
| 12195 | OPC_CheckPredicate, 35, // 4141: check predicate 35 |
| 12196 | OPC_Decode, 223, 27, 242, 1, // 4143: decode to VSHLuv1i64 using decoder 242 |
| 12197 | // 4143: } |
| 12198 | 1, 0, // 4148: case 0x1: { |
| 12199 | OPC_CheckPredicate, 35, // 4150: check predicate 35 |
| 12200 | OPC_Decode, 225, 27, 243, 1, // 4152: decode to VSHLuv2i64 using decoder 243 |
| 12201 | // 4152: } |
| 12202 | // 4152: } // switch Inst[6] |
| 12203 | // 4152: } |
| 12204 | 5, 21, // 4157: case 0x5: { |
| 12205 | OPC_SwitchField, 6, 1, // 4159: switch Inst[6] { |
| 12206 | 0, 7, // 4162: case 0x0: { |
| 12207 | OPC_CheckPredicate, 35, // 4164: check predicate 35 |
| 12208 | OPC_Decode, 249, 26, 242, 1, // 4166: decode to VRSHLuv1i64 using decoder 242 |
| 12209 | // 4166: } |
| 12210 | 1, 0, // 4171: case 0x1: { |
| 12211 | OPC_CheckPredicate, 35, // 4173: check predicate 35 |
| 12212 | OPC_Decode, 251, 26, 243, 1, // 4175: decode to VRSHLuv2i64 using decoder 243 |
| 12213 | // 4175: } |
| 12214 | // 4175: } // switch Inst[6] |
| 12215 | // 4175: } |
| 12216 | 8, 21, // 4180: case 0x8: { |
| 12217 | OPC_SwitchField, 6, 1, // 4182: switch Inst[6] { |
| 12218 | 0, 7, // 4185: case 0x0: { |
| 12219 | OPC_CheckPredicate, 35, // 4187: check predicate 35 |
| 12220 | OPC_Decode, 219, 30, 238, 1, // 4189: decode to VSUBv1i64 using decoder 238 |
| 12221 | // 4189: } |
| 12222 | 1, 0, // 4194: case 0x1: { |
| 12223 | OPC_CheckPredicate, 35, // 4196: check predicate 35 |
| 12224 | OPC_Decode, 221, 30, 239, 1, // 4198: decode to VSUBv2i64 using decoder 239 |
| 12225 | // 4198: } |
| 12226 | // 4198: } // switch Inst[6] |
| 12227 | // 4198: } |
| 12228 | 13, 21, // 4203: case 0xd: { |
| 12229 | OPC_SwitchField, 6, 1, // 4205: switch Inst[6] { |
| 12230 | 0, 7, // 4208: case 0x0: { |
| 12231 | OPC_CheckPredicate, 36, // 4210: check predicate 36 |
| 12232 | OPC_Decode, 207, 16, 238, 1, // 4212: decode to VABDhd using decoder 238 |
| 12233 | // 4212: } |
| 12234 | 1, 0, // 4217: case 0x1: { |
| 12235 | OPC_CheckPredicate, 36, // 4219: check predicate 36 |
| 12236 | OPC_Decode, 208, 16, 239, 1, // 4221: decode to VABDhq using decoder 239 |
| 12237 | // 4221: } |
| 12238 | // 4221: } // switch Inst[6] |
| 12239 | // 4221: } |
| 12240 | 14, 21, // 4226: case 0xe: { |
| 12241 | OPC_SwitchField, 6, 1, // 4228: switch Inst[6] { |
| 12242 | 0, 7, // 4231: case 0x0: { |
| 12243 | OPC_CheckPredicate, 36, // 4233: check predicate 36 |
| 12244 | OPC_Decode, 216, 17, 238, 1, // 4235: decode to VCGThd using decoder 238 |
| 12245 | // 4235: } |
| 12246 | 1, 0, // 4240: case 0x1: { |
| 12247 | OPC_CheckPredicate, 36, // 4242: check predicate 36 |
| 12248 | OPC_Decode, 217, 17, 239, 1, // 4244: decode to VCGThq using decoder 239 |
| 12249 | // 4244: } |
| 12250 | // 4244: } // switch Inst[6] |
| 12251 | // 4244: } |
| 12252 | 15, 0, // 4249: case 0xf: { |
| 12253 | OPC_CheckPredicate, 36, // 4251: check predicate 36 |
| 12254 | OPC_CheckField, 6, 1, 0, // 4253: check Inst[6] == 0x0 |
| 12255 | OPC_Decode, 236, 24, 238, 1, // 4257: decode to VPMINh using decoder 238 |
| 12256 | // 4257: } |
| 12257 | // 4257: } // switch Inst[11:8] |
| 12258 | // 4257: } |
| 12259 | 231, 3, 0, // 4262: case 0x1e7: { |
| 12260 | OPC_SwitchField, 8, 4, // 4265: switch Inst[11:8] { |
| 12261 | 0, 190, 2, // 4268: case 0x0: { |
| 12262 | OPC_SwitchField, 16, 4, // 4271: switch Inst[19:16] { |
| 12263 | 0, 39, // 4274: case 0x0: { |
| 12264 | OPC_SwitchField, 6, 2, // 4276: switch Inst[7:6] { |
| 12265 | 0, 7, // 4279: case 0x0: { |
| 12266 | OPC_CheckPredicate, 35, // 4281: check predicate 35 |
| 12267 | OPC_Decode, 179, 26, 140, 2, // 4283: decode to VREV64d8 using decoder 268 |
| 12268 | // 4283: } |
| 12269 | 1, 7, // 4288: case 0x1: { |
| 12270 | OPC_CheckPredicate, 35, // 4290: check predicate 35 |
| 12271 | OPC_Decode, 182, 26, 141, 2, // 4292: decode to VREV64q8 using decoder 269 |
| 12272 | // 4292: } |
| 12273 | 2, 7, // 4297: case 0x2: { |
| 12274 | OPC_CheckPredicate, 35, // 4299: check predicate 35 |
| 12275 | OPC_Decode, 174, 26, 140, 2, // 4301: decode to VREV32d8 using decoder 268 |
| 12276 | // 4301: } |
| 12277 | 3, 0, // 4306: case 0x3: { |
| 12278 | OPC_CheckPredicate, 35, // 4308: check predicate 35 |
| 12279 | OPC_Decode, 176, 26, 141, 2, // 4310: decode to VREV32q8 using decoder 269 |
| 12280 | // 4310: } |
| 12281 | // 4310: } // switch Inst[7:6] |
| 12282 | // 4310: } |
| 12283 | 1, 39, // 4315: case 0x1: { |
| 12284 | OPC_SwitchField, 6, 2, // 4317: switch Inst[7:6] { |
| 12285 | 0, 7, // 4320: case 0x0: { |
| 12286 | OPC_CheckPredicate, 35, // 4322: check predicate 35 |
| 12287 | OPC_Decode, 239, 17, 140, 2, // 4324: decode to VCGTzv8i8 using decoder 268 |
| 12288 | // 4324: } |
| 12289 | 1, 7, // 4329: case 0x1: { |
| 12290 | OPC_CheckPredicate, 35, // 4331: check predicate 35 |
| 12291 | OPC_Decode, 230, 17, 141, 2, // 4333: decode to VCGTzv16i8 using decoder 269 |
| 12292 | // 4333: } |
| 12293 | 2, 7, // 4338: case 0x2: { |
| 12294 | OPC_CheckPredicate, 35, // 4340: check predicate 35 |
| 12295 | OPC_Decode, 213, 17, 140, 2, // 4342: decode to VCGEzv8i8 using decoder 268 |
| 12296 | // 4342: } |
| 12297 | 3, 0, // 4347: case 0x3: { |
| 12298 | OPC_CheckPredicate, 35, // 4349: check predicate 35 |
| 12299 | OPC_Decode, 204, 17, 141, 2, // 4351: decode to VCGEzv16i8 using decoder 269 |
| 12300 | // 4351: } |
| 12301 | // 4351: } // switch Inst[7:6] |
| 12302 | // 4351: } |
| 12303 | 2, 39, // 4356: case 0x2: { |
| 12304 | OPC_SwitchField, 6, 2, // 4358: switch Inst[7:6] { |
| 12305 | 0, 7, // 4361: case 0x0: { |
| 12306 | OPC_CheckPredicate, 35, // 4363: check predicate 35 |
| 12307 | OPC_Decode, 228, 30, 142, 2, // 4365: decode to VSWPd using decoder 270 |
| 12308 | // 4365: } |
| 12309 | 1, 7, // 4370: case 0x1: { |
| 12310 | OPC_CheckPredicate, 35, // 4372: check predicate 35 |
| 12311 | OPC_Decode, 229, 30, 143, 2, // 4374: decode to VSWPq using decoder 271 |
| 12312 | // 4374: } |
| 12313 | 2, 7, // 4379: case 0x2: { |
| 12314 | OPC_CheckPredicate, 35, // 4381: check predicate 35 |
| 12315 | OPC_Decode, 140, 31, 142, 2, // 4383: decode to VTRNd8 using decoder 270 |
| 12316 | // 4383: } |
| 12317 | 3, 0, // 4388: case 0x3: { |
| 12318 | OPC_CheckPredicate, 35, // 4390: check predicate 35 |
| 12319 | OPC_Decode, 143, 31, 143, 2, // 4392: decode to VTRNq8 using decoder 271 |
| 12320 | // 4392: } |
| 12321 | // 4392: } // switch Inst[7:6] |
| 12322 | // 4392: } |
| 12323 | 4, 39, // 4397: case 0x4: { |
| 12324 | OPC_SwitchField, 6, 2, // 4399: switch Inst[7:6] { |
| 12325 | 0, 7, // 4402: case 0x0: { |
| 12326 | OPC_CheckPredicate, 35, // 4404: check predicate 35 |
| 12327 | OPC_Decode, 177, 26, 140, 2, // 4406: decode to VREV64d16 using decoder 268 |
| 12328 | // 4406: } |
| 12329 | 1, 7, // 4411: case 0x1: { |
| 12330 | OPC_CheckPredicate, 35, // 4413: check predicate 35 |
| 12331 | OPC_Decode, 180, 26, 141, 2, // 4415: decode to VREV64q16 using decoder 269 |
| 12332 | // 4415: } |
| 12333 | 2, 7, // 4420: case 0x2: { |
| 12334 | OPC_CheckPredicate, 35, // 4422: check predicate 35 |
| 12335 | OPC_Decode, 173, 26, 140, 2, // 4424: decode to VREV32d16 using decoder 268 |
| 12336 | // 4424: } |
| 12337 | 3, 0, // 4429: case 0x3: { |
| 12338 | OPC_CheckPredicate, 35, // 4431: check predicate 35 |
| 12339 | OPC_Decode, 175, 26, 141, 2, // 4433: decode to VREV32q16 using decoder 269 |
| 12340 | // 4433: } |
| 12341 | // 4433: } // switch Inst[7:6] |
| 12342 | // 4433: } |
| 12343 | 5, 39, // 4438: case 0x5: { |
| 12344 | OPC_SwitchField, 6, 2, // 4440: switch Inst[7:6] { |
| 12345 | 0, 7, // 4443: case 0x0: { |
| 12346 | OPC_CheckPredicate, 35, // 4445: check predicate 35 |
| 12347 | OPC_Decode, 235, 17, 140, 2, // 4447: decode to VCGTzv4i16 using decoder 268 |
| 12348 | // 4447: } |
| 12349 | 1, 7, // 4452: case 0x1: { |
| 12350 | OPC_CheckPredicate, 35, // 4454: check predicate 35 |
| 12351 | OPC_Decode, 238, 17, 141, 2, // 4456: decode to VCGTzv8i16 using decoder 269 |
| 12352 | // 4456: } |
| 12353 | 2, 7, // 4461: case 0x2: { |
| 12354 | OPC_CheckPredicate, 35, // 4463: check predicate 35 |
| 12355 | OPC_Decode, 209, 17, 140, 2, // 4465: decode to VCGEzv4i16 using decoder 268 |
| 12356 | // 4465: } |
| 12357 | 3, 0, // 4470: case 0x3: { |
| 12358 | OPC_CheckPredicate, 35, // 4472: check predicate 35 |
| 12359 | OPC_Decode, 212, 17, 141, 2, // 4474: decode to VCGEzv8i16 using decoder 269 |
| 12360 | // 4474: } |
| 12361 | // 4474: } // switch Inst[7:6] |
| 12362 | // 4474: } |
| 12363 | 6, 21, // 4479: case 0x6: { |
| 12364 | OPC_SwitchField, 6, 2, // 4481: switch Inst[7:6] { |
| 12365 | 2, 7, // 4484: case 0x2: { |
| 12366 | OPC_CheckPredicate, 35, // 4486: check predicate 35 |
| 12367 | OPC_Decode, 138, 31, 142, 2, // 4488: decode to VTRNd16 using decoder 270 |
| 12368 | // 4488: } |
| 12369 | 3, 0, // 4493: case 0x3: { |
| 12370 | OPC_CheckPredicate, 35, // 4495: check predicate 35 |
| 12371 | OPC_Decode, 141, 31, 143, 2, // 4497: decode to VTRNq16 using decoder 271 |
| 12372 | // 4497: } |
| 12373 | // 4497: } // switch Inst[7:6] |
| 12374 | // 4497: } |
| 12375 | 8, 21, // 4502: case 0x8: { |
| 12376 | OPC_SwitchField, 6, 2, // 4504: switch Inst[7:6] { |
| 12377 | 0, 7, // 4507: case 0x0: { |
| 12378 | OPC_CheckPredicate, 35, // 4509: check predicate 35 |
| 12379 | OPC_Decode, 178, 26, 140, 2, // 4511: decode to VREV64d32 using decoder 268 |
| 12380 | // 4511: } |
| 12381 | 1, 0, // 4516: case 0x1: { |
| 12382 | OPC_CheckPredicate, 35, // 4518: check predicate 35 |
| 12383 | OPC_Decode, 181, 26, 141, 2, // 4520: decode to VREV64q32 using decoder 269 |
| 12384 | // 4520: } |
| 12385 | // 4520: } // switch Inst[7:6] |
| 12386 | // 4520: } |
| 12387 | 9, 39, // 4525: case 0x9: { |
| 12388 | OPC_SwitchField, 6, 2, // 4527: switch Inst[7:6] { |
| 12389 | 0, 7, // 4530: case 0x0: { |
| 12390 | OPC_CheckPredicate, 35, // 4532: check predicate 35 |
| 12391 | OPC_Decode, 232, 17, 140, 2, // 4534: decode to VCGTzv2i32 using decoder 268 |
| 12392 | // 4534: } |
| 12393 | 1, 7, // 4539: case 0x1: { |
| 12394 | OPC_CheckPredicate, 35, // 4541: check predicate 35 |
| 12395 | OPC_Decode, 236, 17, 141, 2, // 4543: decode to VCGTzv4i32 using decoder 269 |
| 12396 | // 4543: } |
| 12397 | 2, 7, // 4548: case 0x2: { |
| 12398 | OPC_CheckPredicate, 35, // 4550: check predicate 35 |
| 12399 | OPC_Decode, 206, 17, 140, 2, // 4552: decode to VCGEzv2i32 using decoder 268 |
| 12400 | // 4552: } |
| 12401 | 3, 0, // 4557: case 0x3: { |
| 12402 | OPC_CheckPredicate, 35, // 4559: check predicate 35 |
| 12403 | OPC_Decode, 210, 17, 141, 2, // 4561: decode to VCGEzv4i32 using decoder 269 |
| 12404 | // 4561: } |
| 12405 | // 4561: } // switch Inst[7:6] |
| 12406 | // 4561: } |
| 12407 | 10, 0, // 4566: case 0xa: { |
| 12408 | OPC_SwitchField, 6, 2, // 4568: switch Inst[7:6] { |
| 12409 | 2, 7, // 4571: case 0x2: { |
| 12410 | OPC_CheckPredicate, 35, // 4573: check predicate 35 |
| 12411 | OPC_Decode, 139, 31, 142, 2, // 4575: decode to VTRNd32 using decoder 270 |
| 12412 | // 4575: } |
| 12413 | 3, 0, // 4580: case 0x3: { |
| 12414 | OPC_CheckPredicate, 35, // 4582: check predicate 35 |
| 12415 | OPC_Decode, 142, 31, 143, 2, // 4584: decode to VTRNq32 using decoder 271 |
| 12416 | // 4584: } |
| 12417 | // 4584: } // switch Inst[7:6] |
| 12418 | // 4584: } |
| 12419 | // 4584: } // switch Inst[19:16] |
| 12420 | // 4584: } |
| 12421 | 1, 254, 1, // 4589: case 0x1: { |
| 12422 | OPC_SwitchField, 16, 4, // 4592: switch Inst[19:16] { |
| 12423 | 0, 21, // 4595: case 0x0: { |
| 12424 | OPC_SwitchField, 6, 2, // 4597: switch Inst[7:6] { |
| 12425 | 0, 7, // 4600: case 0x0: { |
| 12426 | OPC_CheckPredicate, 35, // 4602: check predicate 35 |
| 12427 | OPC_Decode, 171, 26, 140, 2, // 4604: decode to VREV16d8 using decoder 268 |
| 12428 | // 4604: } |
| 12429 | 1, 0, // 4609: case 0x1: { |
| 12430 | OPC_CheckPredicate, 35, // 4611: check predicate 35 |
| 12431 | OPC_Decode, 172, 26, 141, 2, // 4613: decode to VREV16q8 using decoder 269 |
| 12432 | // 4613: } |
| 12433 | // 4613: } // switch Inst[7:6] |
| 12434 | // 4613: } |
| 12435 | 1, 39, // 4618: case 0x1: { |
| 12436 | OPC_SwitchField, 6, 2, // 4620: switch Inst[7:6] { |
| 12437 | 0, 7, // 4623: case 0x0: { |
| 12438 | OPC_CheckPredicate, 35, // 4625: check predicate 35 |
| 12439 | OPC_Decode, 187, 17, 140, 2, // 4627: decode to VCEQzv8i8 using decoder 268 |
| 12440 | // 4627: } |
| 12441 | 1, 7, // 4632: case 0x1: { |
| 12442 | OPC_CheckPredicate, 35, // 4634: check predicate 35 |
| 12443 | OPC_Decode, 178, 17, 141, 2, // 4636: decode to VCEQzv16i8 using decoder 269 |
| 12444 | // 4636: } |
| 12445 | 2, 7, // 4641: case 0x2: { |
| 12446 | OPC_CheckPredicate, 35, // 4643: check predicate 35 |
| 12447 | OPC_Decode, 249, 17, 140, 2, // 4645: decode to VCLEzv8i8 using decoder 268 |
| 12448 | // 4645: } |
| 12449 | 3, 0, // 4650: case 0x3: { |
| 12450 | OPC_CheckPredicate, 35, // 4652: check predicate 35 |
| 12451 | OPC_Decode, 240, 17, 141, 2, // 4654: decode to VCLEzv16i8 using decoder 269 |
| 12452 | // 4654: } |
| 12453 | // 4654: } // switch Inst[7:6] |
| 12454 | // 4654: } |
| 12455 | 2, 39, // 4659: case 0x2: { |
| 12456 | OPC_SwitchField, 6, 2, // 4661: switch Inst[7:6] { |
| 12457 | 0, 7, // 4664: case 0x0: { |
| 12458 | OPC_CheckPredicate, 35, // 4666: check predicate 35 |
| 12459 | OPC_Decode, 170, 31, 142, 2, // 4668: decode to VUZPd8 using decoder 270 |
| 12460 | // 4668: } |
| 12461 | 1, 7, // 4673: case 0x1: { |
| 12462 | OPC_CheckPredicate, 35, // 4675: check predicate 35 |
| 12463 | OPC_Decode, 173, 31, 143, 2, // 4677: decode to VUZPq8 using decoder 271 |
| 12464 | // 4677: } |
| 12465 | 2, 7, // 4682: case 0x2: { |
| 12466 | OPC_CheckPredicate, 35, // 4684: check predicate 35 |
| 12467 | OPC_Decode, 175, 31, 142, 2, // 4686: decode to VZIPd8 using decoder 270 |
| 12468 | // 4686: } |
| 12469 | 3, 0, // 4691: case 0x3: { |
| 12470 | OPC_CheckPredicate, 35, // 4693: check predicate 35 |
| 12471 | OPC_Decode, 178, 31, 143, 2, // 4695: decode to VZIPq8 using decoder 271 |
| 12472 | // 4695: } |
| 12473 | // 4695: } // switch Inst[7:6] |
| 12474 | // 4695: } |
| 12475 | 5, 39, // 4700: case 0x5: { |
| 12476 | OPC_SwitchField, 6, 2, // 4702: switch Inst[7:6] { |
| 12477 | 0, 7, // 4705: case 0x0: { |
| 12478 | OPC_CheckPredicate, 35, // 4707: check predicate 35 |
| 12479 | OPC_Decode, 183, 17, 140, 2, // 4709: decode to VCEQzv4i16 using decoder 268 |
| 12480 | // 4709: } |
| 12481 | 1, 7, // 4714: case 0x1: { |
| 12482 | OPC_CheckPredicate, 35, // 4716: check predicate 35 |
| 12483 | OPC_Decode, 186, 17, 141, 2, // 4718: decode to VCEQzv8i16 using decoder 269 |
| 12484 | // 4718: } |
| 12485 | 2, 7, // 4723: case 0x2: { |
| 12486 | OPC_CheckPredicate, 35, // 4725: check predicate 35 |
| 12487 | OPC_Decode, 245, 17, 140, 2, // 4727: decode to VCLEzv4i16 using decoder 268 |
| 12488 | // 4727: } |
| 12489 | 3, 0, // 4732: case 0x3: { |
| 12490 | OPC_CheckPredicate, 35, // 4734: check predicate 35 |
| 12491 | OPC_Decode, 248, 17, 141, 2, // 4736: decode to VCLEzv8i16 using decoder 269 |
| 12492 | // 4736: } |
| 12493 | // 4736: } // switch Inst[7:6] |
| 12494 | // 4736: } |
| 12495 | 6, 39, // 4741: case 0x6: { |
| 12496 | OPC_SwitchField, 6, 2, // 4743: switch Inst[7:6] { |
| 12497 | 0, 7, // 4746: case 0x0: { |
| 12498 | OPC_CheckPredicate, 35, // 4748: check predicate 35 |
| 12499 | OPC_Decode, 169, 31, 142, 2, // 4750: decode to VUZPd16 using decoder 270 |
| 12500 | // 4750: } |
| 12501 | 1, 7, // 4755: case 0x1: { |
| 12502 | OPC_CheckPredicate, 35, // 4757: check predicate 35 |
| 12503 | OPC_Decode, 171, 31, 143, 2, // 4759: decode to VUZPq16 using decoder 271 |
| 12504 | // 4759: } |
| 12505 | 2, 7, // 4764: case 0x2: { |
| 12506 | OPC_CheckPredicate, 35, // 4766: check predicate 35 |
| 12507 | OPC_Decode, 174, 31, 142, 2, // 4768: decode to VZIPd16 using decoder 270 |
| 12508 | // 4768: } |
| 12509 | 3, 0, // 4773: case 0x3: { |
| 12510 | OPC_CheckPredicate, 35, // 4775: check predicate 35 |
| 12511 | OPC_Decode, 176, 31, 143, 2, // 4777: decode to VZIPq16 using decoder 271 |
| 12512 | // 4777: } |
| 12513 | // 4777: } // switch Inst[7:6] |
| 12514 | // 4777: } |
| 12515 | 9, 39, // 4782: case 0x9: { |
| 12516 | OPC_SwitchField, 6, 2, // 4784: switch Inst[7:6] { |
| 12517 | 0, 7, // 4787: case 0x0: { |
| 12518 | OPC_CheckPredicate, 35, // 4789: check predicate 35 |
| 12519 | OPC_Decode, 180, 17, 140, 2, // 4791: decode to VCEQzv2i32 using decoder 268 |
| 12520 | // 4791: } |
| 12521 | 1, 7, // 4796: case 0x1: { |
| 12522 | OPC_CheckPredicate, 35, // 4798: check predicate 35 |
| 12523 | OPC_Decode, 184, 17, 141, 2, // 4800: decode to VCEQzv4i32 using decoder 269 |
| 12524 | // 4800: } |
| 12525 | 2, 7, // 4805: case 0x2: { |
| 12526 | OPC_CheckPredicate, 35, // 4807: check predicate 35 |
| 12527 | OPC_Decode, 242, 17, 140, 2, // 4809: decode to VCLEzv2i32 using decoder 268 |
| 12528 | // 4809: } |
| 12529 | 3, 0, // 4814: case 0x3: { |
| 12530 | OPC_CheckPredicate, 35, // 4816: check predicate 35 |
| 12531 | OPC_Decode, 246, 17, 141, 2, // 4818: decode to VCLEzv4i32 using decoder 269 |
| 12532 | // 4818: } |
| 12533 | // 4818: } // switch Inst[7:6] |
| 12534 | // 4818: } |
| 12535 | 10, 0, // 4823: case 0xa: { |
| 12536 | OPC_SwitchField, 6, 2, // 4825: switch Inst[7:6] { |
| 12537 | 1, 7, // 4828: case 0x1: { |
| 12538 | OPC_CheckPredicate, 35, // 4830: check predicate 35 |
| 12539 | OPC_Decode, 172, 31, 143, 2, // 4832: decode to VUZPq32 using decoder 271 |
| 12540 | // 4832: } |
| 12541 | 3, 0, // 4837: case 0x3: { |
| 12542 | OPC_CheckPredicate, 35, // 4839: check predicate 35 |
| 12543 | OPC_Decode, 177, 31, 143, 2, // 4841: decode to VZIPq32 using decoder 271 |
| 12544 | // 4841: } |
| 12545 | // 4841: } // switch Inst[7:6] |
| 12546 | // 4841: } |
| 12547 | // 4841: } // switch Inst[19:16] |
| 12548 | // 4841: } |
| 12549 | 2, 190, 2, // 4846: case 0x2: { |
| 12550 | OPC_SwitchField, 16, 4, // 4849: switch Inst[19:16] { |
| 12551 | 0, 39, // 4852: case 0x0: { |
| 12552 | OPC_SwitchField, 6, 2, // 4854: switch Inst[7:6] { |
| 12553 | 0, 7, // 4857: case 0x0: { |
| 12554 | OPC_CheckPredicate, 35, // 4859: check predicate 35 |
| 12555 | OPC_Decode, 215, 24, 140, 2, // 4861: decode to VPADDLsv8i8 using decoder 268 |
| 12556 | // 4861: } |
| 12557 | 1, 7, // 4866: case 0x1: { |
| 12558 | OPC_CheckPredicate, 35, // 4868: check predicate 35 |
| 12559 | OPC_Decode, 210, 24, 141, 2, // 4870: decode to VPADDLsv16i8 using decoder 269 |
| 12560 | // 4870: } |
| 12561 | 2, 7, // 4875: case 0x2: { |
| 12562 | OPC_CheckPredicate, 35, // 4877: check predicate 35 |
| 12563 | OPC_Decode, 221, 24, 140, 2, // 4879: decode to VPADDLuv8i8 using decoder 268 |
| 12564 | // 4879: } |
| 12565 | 3, 0, // 4884: case 0x3: { |
| 12566 | OPC_CheckPredicate, 35, // 4886: check predicate 35 |
| 12567 | OPC_Decode, 216, 24, 141, 2, // 4888: decode to VPADDLuv16i8 using decoder 269 |
| 12568 | // 4888: } |
| 12569 | // 4888: } // switch Inst[7:6] |
| 12570 | // 4888: } |
| 12571 | 1, 21, // 4893: case 0x1: { |
| 12572 | OPC_SwitchField, 6, 2, // 4895: switch Inst[7:6] { |
| 12573 | 0, 7, // 4898: case 0x0: { |
| 12574 | OPC_CheckPredicate, 35, // 4900: check predicate 35 |
| 12575 | OPC_Decode, 137, 18, 140, 2, // 4902: decode to VCLTzv8i8 using decoder 268 |
| 12576 | // 4902: } |
| 12577 | 1, 0, // 4907: case 0x1: { |
| 12578 | OPC_CheckPredicate, 35, // 4909: check predicate 35 |
| 12579 | OPC_Decode, 128, 18, 141, 2, // 4911: decode to VCLTzv16i8 using decoder 269 |
| 12580 | // 4911: } |
| 12581 | // 4911: } // switch Inst[7:6] |
| 12582 | // 4911: } |
| 12583 | 2, 39, // 4916: case 0x2: { |
| 12584 | OPC_SwitchField, 6, 2, // 4918: switch Inst[7:6] { |
| 12585 | 0, 7, // 4921: case 0x0: { |
| 12586 | OPC_CheckPredicate, 35, // 4923: check predicate 35 |
| 12587 | OPC_Decode, 214, 23, 144, 2, // 4925: decode to VMOVNv8i8 using decoder 272 |
| 12588 | // 4925: } |
| 12589 | 1, 7, // 4930: case 0x1: { |
| 12590 | OPC_CheckPredicate, 35, // 4932: check predicate 35 |
| 12591 | OPC_Decode, 159, 25, 144, 2, // 4934: decode to VQMOVNsuv8i8 using decoder 272 |
| 12592 | // 4934: } |
| 12593 | 2, 7, // 4939: case 0x2: { |
| 12594 | OPC_CheckPredicate, 35, // 4941: check predicate 35 |
| 12595 | OPC_Decode, 162, 25, 144, 2, // 4943: decode to VQMOVNsv8i8 using decoder 272 |
| 12596 | // 4943: } |
| 12597 | 3, 0, // 4948: case 0x3: { |
| 12598 | OPC_CheckPredicate, 35, // 4950: check predicate 35 |
| 12599 | OPC_Decode, 165, 25, 144, 2, // 4952: decode to VQMOVNuv8i8 using decoder 272 |
| 12600 | // 4952: } |
| 12601 | // 4952: } // switch Inst[7:6] |
| 12602 | // 4952: } |
| 12603 | 4, 39, // 4957: case 0x4: { |
| 12604 | OPC_SwitchField, 6, 2, // 4959: switch Inst[7:6] { |
| 12605 | 0, 7, // 4962: case 0x0: { |
| 12606 | OPC_CheckPredicate, 35, // 4964: check predicate 35 |
| 12607 | OPC_Decode, 212, 24, 140, 2, // 4966: decode to VPADDLsv4i16 using decoder 268 |
| 12608 | // 4966: } |
| 12609 | 1, 7, // 4971: case 0x1: { |
| 12610 | OPC_CheckPredicate, 35, // 4973: check predicate 35 |
| 12611 | OPC_Decode, 214, 24, 141, 2, // 4975: decode to VPADDLsv8i16 using decoder 269 |
| 12612 | // 4975: } |
| 12613 | 2, 7, // 4980: case 0x2: { |
| 12614 | OPC_CheckPredicate, 35, // 4982: check predicate 35 |
| 12615 | OPC_Decode, 218, 24, 140, 2, // 4984: decode to VPADDLuv4i16 using decoder 268 |
| 12616 | // 4984: } |
| 12617 | 3, 0, // 4989: case 0x3: { |
| 12618 | OPC_CheckPredicate, 35, // 4991: check predicate 35 |
| 12619 | OPC_Decode, 220, 24, 141, 2, // 4993: decode to VPADDLuv8i16 using decoder 269 |
| 12620 | // 4993: } |
| 12621 | // 4993: } // switch Inst[7:6] |
| 12622 | // 4993: } |
| 12623 | 5, 21, // 4998: case 0x5: { |
| 12624 | OPC_SwitchField, 6, 2, // 5000: switch Inst[7:6] { |
| 12625 | 0, 7, // 5003: case 0x0: { |
| 12626 | OPC_CheckPredicate, 35, // 5005: check predicate 35 |
| 12627 | OPC_Decode, 133, 18, 140, 2, // 5007: decode to VCLTzv4i16 using decoder 268 |
| 12628 | // 5007: } |
| 12629 | 1, 0, // 5012: case 0x1: { |
| 12630 | OPC_CheckPredicate, 35, // 5014: check predicate 35 |
| 12631 | OPC_Decode, 136, 18, 141, 2, // 5016: decode to VCLTzv8i16 using decoder 269 |
| 12632 | // 5016: } |
| 12633 | // 5016: } // switch Inst[7:6] |
| 12634 | // 5016: } |
| 12635 | 6, 39, // 5021: case 0x6: { |
| 12636 | OPC_SwitchField, 6, 2, // 5023: switch Inst[7:6] { |
| 12637 | 0, 7, // 5026: case 0x0: { |
| 12638 | OPC_CheckPredicate, 35, // 5028: check predicate 35 |
| 12639 | OPC_Decode, 213, 23, 144, 2, // 5030: decode to VMOVNv4i16 using decoder 272 |
| 12640 | // 5030: } |
| 12641 | 1, 7, // 5035: case 0x1: { |
| 12642 | OPC_CheckPredicate, 35, // 5037: check predicate 35 |
| 12643 | OPC_Decode, 158, 25, 144, 2, // 5039: decode to VQMOVNsuv4i16 using decoder 272 |
| 12644 | // 5039: } |
| 12645 | 2, 7, // 5044: case 0x2: { |
| 12646 | OPC_CheckPredicate, 35, // 5046: check predicate 35 |
| 12647 | OPC_Decode, 161, 25, 144, 2, // 5048: decode to VQMOVNsv4i16 using decoder 272 |
| 12648 | // 5048: } |
| 12649 | 3, 0, // 5053: case 0x3: { |
| 12650 | OPC_CheckPredicate, 35, // 5055: check predicate 35 |
| 12651 | OPC_Decode, 164, 25, 144, 2, // 5057: decode to VQMOVNuv4i16 using decoder 272 |
| 12652 | // 5057: } |
| 12653 | // 5057: } // switch Inst[7:6] |
| 12654 | // 5057: } |
| 12655 | 8, 39, // 5062: case 0x8: { |
| 12656 | OPC_SwitchField, 6, 2, // 5064: switch Inst[7:6] { |
| 12657 | 0, 7, // 5067: case 0x0: { |
| 12658 | OPC_CheckPredicate, 35, // 5069: check predicate 35 |
| 12659 | OPC_Decode, 211, 24, 140, 2, // 5071: decode to VPADDLsv2i32 using decoder 268 |
| 12660 | // 5071: } |
| 12661 | 1, 7, // 5076: case 0x1: { |
| 12662 | OPC_CheckPredicate, 35, // 5078: check predicate 35 |
| 12663 | OPC_Decode, 213, 24, 141, 2, // 5080: decode to VPADDLsv4i32 using decoder 269 |
| 12664 | // 5080: } |
| 12665 | 2, 7, // 5085: case 0x2: { |
| 12666 | OPC_CheckPredicate, 35, // 5087: check predicate 35 |
| 12667 | OPC_Decode, 217, 24, 140, 2, // 5089: decode to VPADDLuv2i32 using decoder 268 |
| 12668 | // 5089: } |
| 12669 | 3, 0, // 5094: case 0x3: { |
| 12670 | OPC_CheckPredicate, 35, // 5096: check predicate 35 |
| 12671 | OPC_Decode, 219, 24, 141, 2, // 5098: decode to VPADDLuv4i32 using decoder 269 |
| 12672 | // 5098: } |
| 12673 | // 5098: } // switch Inst[7:6] |
| 12674 | // 5098: } |
| 12675 | 9, 21, // 5103: case 0x9: { |
| 12676 | OPC_SwitchField, 6, 2, // 5105: switch Inst[7:6] { |
| 12677 | 0, 7, // 5108: case 0x0: { |
| 12678 | OPC_CheckPredicate, 35, // 5110: check predicate 35 |
| 12679 | OPC_Decode, 130, 18, 140, 2, // 5112: decode to VCLTzv2i32 using decoder 268 |
| 12680 | // 5112: } |
| 12681 | 1, 0, // 5117: case 0x1: { |
| 12682 | OPC_CheckPredicate, 35, // 5119: check predicate 35 |
| 12683 | OPC_Decode, 134, 18, 141, 2, // 5121: decode to VCLTzv4i32 using decoder 269 |
| 12684 | // 5121: } |
| 12685 | // 5121: } // switch Inst[7:6] |
| 12686 | // 5121: } |
| 12687 | 10, 0, // 5126: case 0xa: { |
| 12688 | OPC_SwitchField, 6, 2, // 5128: switch Inst[7:6] { |
| 12689 | 0, 7, // 5131: case 0x0: { |
| 12690 | OPC_CheckPredicate, 35, // 5133: check predicate 35 |
| 12691 | OPC_Decode, 212, 23, 144, 2, // 5135: decode to VMOVNv2i32 using decoder 272 |
| 12692 | // 5135: } |
| 12693 | 1, 7, // 5140: case 0x1: { |
| 12694 | OPC_CheckPredicate, 35, // 5142: check predicate 35 |
| 12695 | OPC_Decode, 157, 25, 144, 2, // 5144: decode to VQMOVNsuv2i32 using decoder 272 |
| 12696 | // 5144: } |
| 12697 | 2, 7, // 5149: case 0x2: { |
| 12698 | OPC_CheckPredicate, 35, // 5151: check predicate 35 |
| 12699 | OPC_Decode, 160, 25, 144, 2, // 5153: decode to VQMOVNsv2i32 using decoder 272 |
| 12700 | // 5153: } |
| 12701 | 3, 0, // 5158: case 0x3: { |
| 12702 | OPC_CheckPredicate, 35, // 5160: check predicate 35 |
| 12703 | OPC_Decode, 163, 25, 144, 2, // 5162: decode to VQMOVNuv2i32 using decoder 272 |
| 12704 | // 5162: } |
| 12705 | // 5162: } // switch Inst[7:6] |
| 12706 | // 5162: } |
| 12707 | // 5162: } // switch Inst[19:16] |
| 12708 | // 5162: } |
| 12709 | 3, 165, 1, // 5167: case 0x3: { |
| 12710 | OPC_SwitchField, 16, 4, // 5170: switch Inst[19:16] { |
| 12711 | 1, 39, // 5173: case 0x1: { |
| 12712 | OPC_SwitchField, 6, 2, // 5175: switch Inst[7:6] { |
| 12713 | 0, 7, // 5178: case 0x0: { |
| 12714 | OPC_CheckPredicate, 35, // 5180: check predicate 35 |
| 12715 | OPC_Decode, 233, 16, 140, 2, // 5182: decode to VABSv8i8 using decoder 268 |
| 12716 | // 5182: } |
| 12717 | 1, 7, // 5187: case 0x1: { |
| 12718 | OPC_CheckPredicate, 35, // 5189: check predicate 35 |
| 12719 | OPC_Decode, 228, 16, 141, 2, // 5191: decode to VABSv16i8 using decoder 269 |
| 12720 | // 5191: } |
| 12721 | 2, 7, // 5196: case 0x2: { |
| 12722 | OPC_CheckPredicate, 35, // 5198: check predicate 35 |
| 12723 | OPC_Decode, 179, 24, 140, 2, // 5200: decode to VNEGs8d using decoder 268 |
| 12724 | // 5200: } |
| 12725 | 3, 0, // 5205: case 0x3: { |
| 12726 | OPC_CheckPredicate, 35, // 5207: check predicate 35 |
| 12727 | OPC_Decode, 180, 24, 141, 2, // 5209: decode to VNEGs8q using decoder 269 |
| 12728 | // 5209: } |
| 12729 | // 5209: } // switch Inst[7:6] |
| 12730 | // 5209: } |
| 12731 | 2, 11, // 5214: case 0x2: { |
| 12732 | OPC_CheckPredicate, 35, // 5216: check predicate 35 |
| 12733 | OPC_CheckField, 6, 2, 0, // 5218: check Inst[7:6] == 0x0 |
| 12734 | OPC_Decode, 199, 27, 145, 2, // 5222: decode to VSHLLi8 using decoder 273 |
| 12735 | // 5222: } |
| 12736 | 5, 39, // 5227: case 0x5: { |
| 12737 | OPC_SwitchField, 6, 2, // 5229: switch Inst[7:6] { |
| 12738 | 0, 7, // 5232: case 0x0: { |
| 12739 | OPC_CheckPredicate, 35, // 5234: check predicate 35 |
| 12740 | OPC_Decode, 230, 16, 140, 2, // 5236: decode to VABSv4i16 using decoder 268 |
| 12741 | // 5236: } |
| 12742 | 1, 7, // 5241: case 0x1: { |
| 12743 | OPC_CheckPredicate, 35, // 5243: check predicate 35 |
| 12744 | OPC_Decode, 232, 16, 141, 2, // 5245: decode to VABSv8i16 using decoder 269 |
| 12745 | // 5245: } |
| 12746 | 2, 7, // 5250: case 0x2: { |
| 12747 | OPC_CheckPredicate, 35, // 5252: check predicate 35 |
| 12748 | OPC_Decode, 175, 24, 140, 2, // 5254: decode to VNEGs16d using decoder 268 |
| 12749 | // 5254: } |
| 12750 | 3, 0, // 5259: case 0x3: { |
| 12751 | OPC_CheckPredicate, 35, // 5261: check predicate 35 |
| 12752 | OPC_Decode, 176, 24, 141, 2, // 5263: decode to VNEGs16q using decoder 269 |
| 12753 | // 5263: } |
| 12754 | // 5263: } // switch Inst[7:6] |
| 12755 | // 5263: } |
| 12756 | 6, 11, // 5268: case 0x6: { |
| 12757 | OPC_CheckPredicate, 35, // 5270: check predicate 35 |
| 12758 | OPC_CheckField, 6, 2, 0, // 5272: check Inst[7:6] == 0x0 |
| 12759 | OPC_Decode, 197, 27, 145, 2, // 5276: decode to VSHLLi16 using decoder 273 |
| 12760 | // 5276: } |
| 12761 | 9, 39, // 5281: case 0x9: { |
| 12762 | OPC_SwitchField, 6, 2, // 5283: switch Inst[7:6] { |
| 12763 | 0, 7, // 5286: case 0x0: { |
| 12764 | OPC_CheckPredicate, 35, // 5288: check predicate 35 |
| 12765 | OPC_Decode, 229, 16, 140, 2, // 5290: decode to VABSv2i32 using decoder 268 |
| 12766 | // 5290: } |
| 12767 | 1, 7, // 5295: case 0x1: { |
| 12768 | OPC_CheckPredicate, 35, // 5297: check predicate 35 |
| 12769 | OPC_Decode, 231, 16, 141, 2, // 5299: decode to VABSv4i32 using decoder 269 |
| 12770 | // 5299: } |
| 12771 | 2, 7, // 5304: case 0x2: { |
| 12772 | OPC_CheckPredicate, 35, // 5306: check predicate 35 |
| 12773 | OPC_Decode, 177, 24, 140, 2, // 5308: decode to VNEGs32d using decoder 268 |
| 12774 | // 5308: } |
| 12775 | 3, 0, // 5313: case 0x3: { |
| 12776 | OPC_CheckPredicate, 35, // 5315: check predicate 35 |
| 12777 | OPC_Decode, 178, 24, 141, 2, // 5317: decode to VNEGs32q using decoder 269 |
| 12778 | // 5317: } |
| 12779 | // 5317: } // switch Inst[7:6] |
| 12780 | // 5317: } |
| 12781 | 10, 0, // 5322: case 0xa: { |
| 12782 | OPC_CheckPredicate, 35, // 5324: check predicate 35 |
| 12783 | OPC_CheckField, 6, 2, 0, // 5326: check Inst[7:6] == 0x0 |
| 12784 | OPC_Decode, 198, 27, 145, 2, // 5330: decode to VSHLLi32 using decoder 273 |
| 12785 | // 5330: } |
| 12786 | // 5330: } // switch Inst[19:16] |
| 12787 | // 5330: } |
| 12788 | 4, 249, 1, // 5335: case 0x4: { |
| 12789 | OPC_SwitchField, 16, 4, // 5338: switch Inst[19:16] { |
| 12790 | 0, 39, // 5341: case 0x0: { |
| 12791 | OPC_SwitchField, 6, 2, // 5343: switch Inst[7:6] { |
| 12792 | 0, 7, // 5346: case 0x0: { |
| 12793 | OPC_CheckPredicate, 35, // 5348: check predicate 35 |
| 12794 | OPC_Decode, 255, 17, 140, 2, // 5350: decode to VCLSv8i8 using decoder 268 |
| 12795 | // 5350: } |
| 12796 | 1, 7, // 5355: case 0x1: { |
| 12797 | OPC_CheckPredicate, 35, // 5357: check predicate 35 |
| 12798 | OPC_Decode, 250, 17, 141, 2, // 5359: decode to VCLSv16i8 using decoder 269 |
| 12799 | // 5359: } |
| 12800 | 2, 7, // 5364: case 0x2: { |
| 12801 | OPC_CheckPredicate, 35, // 5366: check predicate 35 |
| 12802 | OPC_Decode, 143, 18, 140, 2, // 5368: decode to VCLZv8i8 using decoder 268 |
| 12803 | // 5368: } |
| 12804 | 3, 0, // 5373: case 0x3: { |
| 12805 | OPC_CheckPredicate, 35, // 5375: check predicate 35 |
| 12806 | OPC_Decode, 138, 18, 141, 2, // 5377: decode to VCLZv16i8 using decoder 269 |
| 12807 | // 5377: } |
| 12808 | // 5377: } // switch Inst[7:6] |
| 12809 | // 5377: } |
| 12810 | 4, 39, // 5382: case 0x4: { |
| 12811 | OPC_SwitchField, 6, 2, // 5384: switch Inst[7:6] { |
| 12812 | 0, 7, // 5387: case 0x0: { |
| 12813 | OPC_CheckPredicate, 35, // 5389: check predicate 35 |
| 12814 | OPC_Decode, 252, 17, 140, 2, // 5391: decode to VCLSv4i16 using decoder 268 |
| 12815 | // 5391: } |
| 12816 | 1, 7, // 5396: case 0x1: { |
| 12817 | OPC_CheckPredicate, 35, // 5398: check predicate 35 |
| 12818 | OPC_Decode, 254, 17, 141, 2, // 5400: decode to VCLSv8i16 using decoder 269 |
| 12819 | // 5400: } |
| 12820 | 2, 7, // 5405: case 0x2: { |
| 12821 | OPC_CheckPredicate, 35, // 5407: check predicate 35 |
| 12822 | OPC_Decode, 140, 18, 140, 2, // 5409: decode to VCLZv4i16 using decoder 268 |
| 12823 | // 5409: } |
| 12824 | 3, 0, // 5414: case 0x3: { |
| 12825 | OPC_CheckPredicate, 35, // 5416: check predicate 35 |
| 12826 | OPC_Decode, 142, 18, 141, 2, // 5418: decode to VCLZv8i16 using decoder 269 |
| 12827 | // 5418: } |
| 12828 | // 5418: } // switch Inst[7:6] |
| 12829 | // 5418: } |
| 12830 | 5, 39, // 5423: case 0x5: { |
| 12831 | OPC_SwitchField, 6, 2, // 5425: switch Inst[7:6] { |
| 12832 | 0, 7, // 5428: case 0x0: { |
| 12833 | OPC_CheckPredicate, 36, // 5430: check predicate 36 |
| 12834 | OPC_Decode, 233, 17, 140, 2, // 5432: decode to VCGTzv4f16 using decoder 268 |
| 12835 | // 5432: } |
| 12836 | 1, 7, // 5437: case 0x1: { |
| 12837 | OPC_CheckPredicate, 36, // 5439: check predicate 36 |
| 12838 | OPC_Decode, 237, 17, 141, 2, // 5441: decode to VCGTzv8f16 using decoder 269 |
| 12839 | // 5441: } |
| 12840 | 2, 7, // 5446: case 0x2: { |
| 12841 | OPC_CheckPredicate, 36, // 5448: check predicate 36 |
| 12842 | OPC_Decode, 207, 17, 140, 2, // 5450: decode to VCGEzv4f16 using decoder 268 |
| 12843 | // 5450: } |
| 12844 | 3, 0, // 5455: case 0x3: { |
| 12845 | OPC_CheckPredicate, 36, // 5457: check predicate 36 |
| 12846 | OPC_Decode, 211, 17, 141, 2, // 5459: decode to VCGEzv8f16 using decoder 269 |
| 12847 | // 5459: } |
| 12848 | // 5459: } // switch Inst[7:6] |
| 12849 | // 5459: } |
| 12850 | 8, 39, // 5464: case 0x8: { |
| 12851 | OPC_SwitchField, 6, 2, // 5466: switch Inst[7:6] { |
| 12852 | 0, 7, // 5469: case 0x0: { |
| 12853 | OPC_CheckPredicate, 35, // 5471: check predicate 35 |
| 12854 | OPC_Decode, 251, 17, 140, 2, // 5473: decode to VCLSv2i32 using decoder 268 |
| 12855 | // 5473: } |
| 12856 | 1, 7, // 5478: case 0x1: { |
| 12857 | OPC_CheckPredicate, 35, // 5480: check predicate 35 |
| 12858 | OPC_Decode, 253, 17, 141, 2, // 5482: decode to VCLSv4i32 using decoder 269 |
| 12859 | // 5482: } |
| 12860 | 2, 7, // 5487: case 0x2: { |
| 12861 | OPC_CheckPredicate, 35, // 5489: check predicate 35 |
| 12862 | OPC_Decode, 139, 18, 140, 2, // 5491: decode to VCLZv2i32 using decoder 268 |
| 12863 | // 5491: } |
| 12864 | 3, 0, // 5496: case 0x3: { |
| 12865 | OPC_CheckPredicate, 35, // 5498: check predicate 35 |
| 12866 | OPC_Decode, 141, 18, 141, 2, // 5500: decode to VCLZv4i32 using decoder 269 |
| 12867 | // 5500: } |
| 12868 | // 5500: } // switch Inst[7:6] |
| 12869 | // 5500: } |
| 12870 | 9, 39, // 5505: case 0x9: { |
| 12871 | OPC_SwitchField, 6, 2, // 5507: switch Inst[7:6] { |
| 12872 | 0, 7, // 5510: case 0x0: { |
| 12873 | OPC_CheckPredicate, 35, // 5512: check predicate 35 |
| 12874 | OPC_Decode, 231, 17, 140, 2, // 5514: decode to VCGTzv2f32 using decoder 268 |
| 12875 | // 5514: } |
| 12876 | 1, 7, // 5519: case 0x1: { |
| 12877 | OPC_CheckPredicate, 35, // 5521: check predicate 35 |
| 12878 | OPC_Decode, 234, 17, 141, 2, // 5523: decode to VCGTzv4f32 using decoder 269 |
| 12879 | // 5523: } |
| 12880 | 2, 7, // 5528: case 0x2: { |
| 12881 | OPC_CheckPredicate, 35, // 5530: check predicate 35 |
| 12882 | OPC_Decode, 205, 17, 140, 2, // 5532: decode to VCGEzv2f32 using decoder 268 |
| 12883 | // 5532: } |
| 12884 | 3, 0, // 5537: case 0x3: { |
| 12885 | OPC_CheckPredicate, 35, // 5539: check predicate 35 |
| 12886 | OPC_Decode, 208, 17, 141, 2, // 5541: decode to VCGEzv4f32 using decoder 269 |
| 12887 | // 5541: } |
| 12888 | // 5541: } // switch Inst[7:6] |
| 12889 | // 5541: } |
| 12890 | 11, 0, // 5546: case 0xb: { |
| 12891 | OPC_SwitchField, 6, 2, // 5548: switch Inst[7:6] { |
| 12892 | 0, 7, // 5551: case 0x0: { |
| 12893 | OPC_CheckPredicate, 35, // 5553: check predicate 35 |
| 12894 | OPC_Decode, 161, 26, 140, 2, // 5555: decode to VRECPEd using decoder 268 |
| 12895 | // 5555: } |
| 12896 | 1, 7, // 5560: case 0x1: { |
| 12897 | OPC_CheckPredicate, 35, // 5562: check predicate 35 |
| 12898 | OPC_Decode, 166, 26, 141, 2, // 5564: decode to VRECPEq using decoder 269 |
| 12899 | // 5564: } |
| 12900 | 2, 7, // 5569: case 0x2: { |
| 12901 | OPC_CheckPredicate, 35, // 5571: check predicate 35 |
| 12902 | OPC_Decode, 147, 27, 140, 2, // 5573: decode to VRSQRTEd using decoder 268 |
| 12903 | // 5573: } |
| 12904 | 3, 0, // 5578: case 0x3: { |
| 12905 | OPC_CheckPredicate, 35, // 5580: check predicate 35 |
| 12906 | OPC_Decode, 152, 27, 141, 2, // 5582: decode to VRSQRTEq using decoder 269 |
| 12907 | // 5582: } |
| 12908 | // 5582: } // switch Inst[7:6] |
| 12909 | // 5582: } |
| 12910 | // 5582: } // switch Inst[19:16] |
| 12911 | // 5582: } |
| 12912 | 5, 208, 1, // 5587: case 0x5: { |
| 12913 | OPC_SwitchField, 16, 4, // 5590: switch Inst[19:16] { |
| 12914 | 0, 39, // 5593: case 0x0: { |
| 12915 | OPC_SwitchField, 6, 2, // 5595: switch Inst[7:6] { |
| 12916 | 0, 7, // 5598: case 0x0: { |
| 12917 | OPC_CheckPredicate, 35, // 5600: check predicate 35 |
| 12918 | OPC_Decode, 164, 18, 140, 2, // 5602: decode to VCNTd using decoder 268 |
| 12919 | // 5602: } |
| 12920 | 1, 7, // 5607: case 0x1: { |
| 12921 | OPC_CheckPredicate, 35, // 5609: check predicate 35 |
| 12922 | OPC_Decode, 165, 18, 141, 2, // 5611: decode to VCNTq using decoder 269 |
| 12923 | // 5611: } |
| 12924 | 2, 7, // 5616: case 0x2: { |
| 12925 | OPC_CheckPredicate, 35, // 5618: check predicate 35 |
| 12926 | OPC_Decode, 162, 24, 140, 2, // 5620: decode to VMVNd using decoder 268 |
| 12927 | // 5620: } |
| 12928 | 3, 0, // 5625: case 0x3: { |
| 12929 | OPC_CheckPredicate, 35, // 5627: check predicate 35 |
| 12930 | OPC_Decode, 163, 24, 141, 2, // 5629: decode to VMVNq using decoder 269 |
| 12931 | // 5629: } |
| 12932 | // 5629: } // switch Inst[7:6] |
| 12933 | // 5629: } |
| 12934 | 5, 39, // 5634: case 0x5: { |
| 12935 | OPC_SwitchField, 6, 2, // 5636: switch Inst[7:6] { |
| 12936 | 0, 7, // 5639: case 0x0: { |
| 12937 | OPC_CheckPredicate, 36, // 5641: check predicate 36 |
| 12938 | OPC_Decode, 181, 17, 140, 2, // 5643: decode to VCEQzv4f16 using decoder 268 |
| 12939 | // 5643: } |
| 12940 | 1, 7, // 5648: case 0x1: { |
| 12941 | OPC_CheckPredicate, 36, // 5650: check predicate 36 |
| 12942 | OPC_Decode, 185, 17, 141, 2, // 5652: decode to VCEQzv8f16 using decoder 269 |
| 12943 | // 5652: } |
| 12944 | 2, 7, // 5657: case 0x2: { |
| 12945 | OPC_CheckPredicate, 36, // 5659: check predicate 36 |
| 12946 | OPC_Decode, 243, 17, 140, 2, // 5661: decode to VCLEzv4f16 using decoder 268 |
| 12947 | // 5661: } |
| 12948 | 3, 0, // 5666: case 0x3: { |
| 12949 | OPC_CheckPredicate, 36, // 5668: check predicate 36 |
| 12950 | OPC_Decode, 247, 17, 141, 2, // 5670: decode to VCLEzv8f16 using decoder 269 |
| 12951 | // 5670: } |
| 12952 | // 5670: } // switch Inst[7:6] |
| 12953 | // 5670: } |
| 12954 | 7, 39, // 5675: case 0x7: { |
| 12955 | OPC_SwitchField, 6, 2, // 5677: switch Inst[7:6] { |
| 12956 | 0, 7, // 5680: case 0x0: { |
| 12957 | OPC_CheckPredicate, 36, // 5682: check predicate 36 |
| 12958 | OPC_Decode, 164, 26, 140, 2, // 5684: decode to VRECPEhd using decoder 268 |
| 12959 | // 5684: } |
| 12960 | 1, 7, // 5689: case 0x1: { |
| 12961 | OPC_CheckPredicate, 36, // 5691: check predicate 36 |
| 12962 | OPC_Decode, 165, 26, 141, 2, // 5693: decode to VRECPEhq using decoder 269 |
| 12963 | // 5693: } |
| 12964 | 2, 7, // 5698: case 0x2: { |
| 12965 | OPC_CheckPredicate, 36, // 5700: check predicate 36 |
| 12966 | OPC_Decode, 150, 27, 140, 2, // 5702: decode to VRSQRTEhd using decoder 268 |
| 12967 | // 5702: } |
| 12968 | 3, 0, // 5707: case 0x3: { |
| 12969 | OPC_CheckPredicate, 36, // 5709: check predicate 36 |
| 12970 | OPC_Decode, 151, 27, 141, 2, // 5711: decode to VRSQRTEhq using decoder 269 |
| 12971 | // 5711: } |
| 12972 | // 5711: } // switch Inst[7:6] |
| 12973 | // 5711: } |
| 12974 | 9, 39, // 5716: case 0x9: { |
| 12975 | OPC_SwitchField, 6, 2, // 5718: switch Inst[7:6] { |
| 12976 | 0, 7, // 5721: case 0x0: { |
| 12977 | OPC_CheckPredicate, 35, // 5723: check predicate 35 |
| 12978 | OPC_Decode, 179, 17, 140, 2, // 5725: decode to VCEQzv2f32 using decoder 268 |
| 12979 | // 5725: } |
| 12980 | 1, 7, // 5730: case 0x1: { |
| 12981 | OPC_CheckPredicate, 35, // 5732: check predicate 35 |
| 12982 | OPC_Decode, 182, 17, 141, 2, // 5734: decode to VCEQzv4f32 using decoder 269 |
| 12983 | // 5734: } |
| 12984 | 2, 7, // 5739: case 0x2: { |
| 12985 | OPC_CheckPredicate, 35, // 5741: check predicate 35 |
| 12986 | OPC_Decode, 241, 17, 140, 2, // 5743: decode to VCLEzv2f32 using decoder 268 |
| 12987 | // 5743: } |
| 12988 | 3, 0, // 5748: case 0x3: { |
| 12989 | OPC_CheckPredicate, 35, // 5750: check predicate 35 |
| 12990 | OPC_Decode, 244, 17, 141, 2, // 5752: decode to VCLEzv4f32 using decoder 269 |
| 12991 | // 5752: } |
| 12992 | // 5752: } // switch Inst[7:6] |
| 12993 | // 5752: } |
| 12994 | 11, 0, // 5757: case 0xb: { |
| 12995 | OPC_SwitchField, 6, 2, // 5759: switch Inst[7:6] { |
| 12996 | 0, 7, // 5762: case 0x0: { |
| 12997 | OPC_CheckPredicate, 35, // 5764: check predicate 35 |
| 12998 | OPC_Decode, 162, 26, 140, 2, // 5766: decode to VRECPEfd using decoder 268 |
| 12999 | // 5766: } |
| 13000 | 1, 7, // 5771: case 0x1: { |
| 13001 | OPC_CheckPredicate, 35, // 5773: check predicate 35 |
| 13002 | OPC_Decode, 163, 26, 141, 2, // 5775: decode to VRECPEfq using decoder 269 |
| 13003 | // 5775: } |
| 13004 | 2, 7, // 5780: case 0x2: { |
| 13005 | OPC_CheckPredicate, 35, // 5782: check predicate 35 |
| 13006 | OPC_Decode, 148, 27, 140, 2, // 5784: decode to VRSQRTEfd using decoder 268 |
| 13007 | // 5784: } |
| 13008 | 3, 0, // 5789: case 0x3: { |
| 13009 | OPC_CheckPredicate, 35, // 5791: check predicate 35 |
| 13010 | OPC_Decode, 149, 27, 141, 2, // 5793: decode to VRSQRTEfq using decoder 269 |
| 13011 | // 5793: } |
| 13012 | // 5793: } // switch Inst[7:6] |
| 13013 | // 5793: } |
| 13014 | // 5793: } // switch Inst[19:16] |
| 13015 | // 5793: } |
| 13016 | 6, 149, 2, // 5798: case 0x6: { |
| 13017 | OPC_SwitchField, 16, 4, // 5801: switch Inst[19:16] { |
| 13018 | 0, 39, // 5804: case 0x0: { |
| 13019 | OPC_SwitchField, 6, 2, // 5806: switch Inst[7:6] { |
| 13020 | 0, 7, // 5809: case 0x0: { |
| 13021 | OPC_CheckPredicate, 35, // 5811: check predicate 35 |
| 13022 | OPC_Decode, 203, 24, 146, 2, // 5813: decode to VPADALsv8i8 using decoder 274 |
| 13023 | // 5813: } |
| 13024 | 1, 7, // 5818: case 0x1: { |
| 13025 | OPC_CheckPredicate, 35, // 5820: check predicate 35 |
| 13026 | OPC_Decode, 198, 24, 147, 2, // 5822: decode to VPADALsv16i8 using decoder 275 |
| 13027 | // 5822: } |
| 13028 | 2, 7, // 5827: case 0x2: { |
| 13029 | OPC_CheckPredicate, 35, // 5829: check predicate 35 |
| 13030 | OPC_Decode, 209, 24, 146, 2, // 5831: decode to VPADALuv8i8 using decoder 274 |
| 13031 | // 5831: } |
| 13032 | 3, 0, // 5836: case 0x3: { |
| 13033 | OPC_CheckPredicate, 35, // 5838: check predicate 35 |
| 13034 | OPC_Decode, 204, 24, 147, 2, // 5840: decode to VPADALuv16i8 using decoder 275 |
| 13035 | // 5840: } |
| 13036 | // 5840: } // switch Inst[7:6] |
| 13037 | // 5840: } |
| 13038 | 4, 39, // 5845: case 0x4: { |
| 13039 | OPC_SwitchField, 6, 2, // 5847: switch Inst[7:6] { |
| 13040 | 0, 7, // 5850: case 0x0: { |
| 13041 | OPC_CheckPredicate, 35, // 5852: check predicate 35 |
| 13042 | OPC_Decode, 200, 24, 146, 2, // 5854: decode to VPADALsv4i16 using decoder 274 |
| 13043 | // 5854: } |
| 13044 | 1, 7, // 5859: case 0x1: { |
| 13045 | OPC_CheckPredicate, 35, // 5861: check predicate 35 |
| 13046 | OPC_Decode, 202, 24, 147, 2, // 5863: decode to VPADALsv8i16 using decoder 275 |
| 13047 | // 5863: } |
| 13048 | 2, 7, // 5868: case 0x2: { |
| 13049 | OPC_CheckPredicate, 35, // 5870: check predicate 35 |
| 13050 | OPC_Decode, 206, 24, 146, 2, // 5872: decode to VPADALuv4i16 using decoder 274 |
| 13051 | // 5872: } |
| 13052 | 3, 0, // 5877: case 0x3: { |
| 13053 | OPC_CheckPredicate, 35, // 5879: check predicate 35 |
| 13054 | OPC_Decode, 208, 24, 147, 2, // 5881: decode to VPADALuv8i16 using decoder 275 |
| 13055 | // 5881: } |
| 13056 | // 5881: } // switch Inst[7:6] |
| 13057 | // 5881: } |
| 13058 | 5, 21, // 5886: case 0x5: { |
| 13059 | OPC_SwitchField, 6, 2, // 5888: switch Inst[7:6] { |
| 13060 | 0, 7, // 5891: case 0x0: { |
| 13061 | OPC_CheckPredicate, 36, // 5893: check predicate 36 |
| 13062 | OPC_Decode, 131, 18, 140, 2, // 5895: decode to VCLTzv4f16 using decoder 268 |
| 13063 | // 5895: } |
| 13064 | 1, 0, // 5900: case 0x1: { |
| 13065 | OPC_CheckPredicate, 36, // 5902: check predicate 36 |
| 13066 | OPC_Decode, 135, 18, 141, 2, // 5904: decode to VCLTzv8f16 using decoder 269 |
| 13067 | // 5904: } |
| 13068 | // 5904: } // switch Inst[7:6] |
| 13069 | // 5904: } |
| 13070 | 6, 21, // 5909: case 0x6: { |
| 13071 | OPC_SwitchField, 6, 2, // 5911: switch Inst[7:6] { |
| 13072 | 0, 7, // 5914: case 0x0: { |
| 13073 | OPC_CheckPredicate, 39, // 5916: check predicate 39 |
| 13074 | OPC_Decode, 232, 18, 144, 2, // 5918: decode to VCVTf2h using decoder 272 |
| 13075 | // 5918: } |
| 13076 | 1, 0, // 5923: case 0x1: { |
| 13077 | OPC_CheckPredicate, 40, // 5925: check predicate 40 |
| 13078 | OPC_Decode, 183, 6, 144, 2, // 5927: decode to BF16_VCVT using decoder 272 |
| 13079 | // 5927: } |
| 13080 | // 5927: } // switch Inst[7:6] |
| 13081 | // 5927: } |
| 13082 | 7, 39, // 5932: case 0x7: { |
| 13083 | OPC_SwitchField, 6, 2, // 5934: switch Inst[7:6] { |
| 13084 | 0, 7, // 5937: case 0x0: { |
| 13085 | OPC_CheckPredicate, 36, // 5939: check predicate 36 |
| 13086 | OPC_Decode, 252, 18, 140, 2, // 5941: decode to VCVTs2hd using decoder 268 |
| 13087 | // 5941: } |
| 13088 | 1, 7, // 5946: case 0x1: { |
| 13089 | OPC_CheckPredicate, 36, // 5948: check predicate 36 |
| 13090 | OPC_Decode, 253, 18, 141, 2, // 5950: decode to VCVTs2hq using decoder 269 |
| 13091 | // 5950: } |
| 13092 | 2, 7, // 5955: case 0x2: { |
| 13093 | OPC_CheckPredicate, 36, // 5957: check predicate 36 |
| 13094 | OPC_Decode, 128, 19, 140, 2, // 5959: decode to VCVTu2hd using decoder 268 |
| 13095 | // 5959: } |
| 13096 | 3, 0, // 5964: case 0x3: { |
| 13097 | OPC_CheckPredicate, 36, // 5966: check predicate 36 |
| 13098 | OPC_Decode, 129, 19, 141, 2, // 5968: decode to VCVTu2hq using decoder 269 |
| 13099 | // 5968: } |
| 13100 | // 5968: } // switch Inst[7:6] |
| 13101 | // 5968: } |
| 13102 | 8, 39, // 5973: case 0x8: { |
| 13103 | OPC_SwitchField, 6, 2, // 5975: switch Inst[7:6] { |
| 13104 | 0, 7, // 5978: case 0x0: { |
| 13105 | OPC_CheckPredicate, 35, // 5980: check predicate 35 |
| 13106 | OPC_Decode, 199, 24, 146, 2, // 5982: decode to VPADALsv2i32 using decoder 274 |
| 13107 | // 5982: } |
| 13108 | 1, 7, // 5987: case 0x1: { |
| 13109 | OPC_CheckPredicate, 35, // 5989: check predicate 35 |
| 13110 | OPC_Decode, 201, 24, 147, 2, // 5991: decode to VPADALsv4i32 using decoder 275 |
| 13111 | // 5991: } |
| 13112 | 2, 7, // 5996: case 0x2: { |
| 13113 | OPC_CheckPredicate, 35, // 5998: check predicate 35 |
| 13114 | OPC_Decode, 205, 24, 146, 2, // 6000: decode to VPADALuv2i32 using decoder 274 |
| 13115 | // 6000: } |
| 13116 | 3, 0, // 6005: case 0x3: { |
| 13117 | OPC_CheckPredicate, 35, // 6007: check predicate 35 |
| 13118 | OPC_Decode, 207, 24, 147, 2, // 6009: decode to VPADALuv4i32 using decoder 275 |
| 13119 | // 6009: } |
| 13120 | // 6009: } // switch Inst[7:6] |
| 13121 | // 6009: } |
| 13122 | 9, 21, // 6014: case 0x9: { |
| 13123 | OPC_SwitchField, 6, 2, // 6016: switch Inst[7:6] { |
| 13124 | 0, 7, // 6019: case 0x0: { |
| 13125 | OPC_CheckPredicate, 35, // 6021: check predicate 35 |
| 13126 | OPC_Decode, 129, 18, 140, 2, // 6023: decode to VCLTzv2f32 using decoder 268 |
| 13127 | // 6023: } |
| 13128 | 1, 0, // 6028: case 0x1: { |
| 13129 | OPC_CheckPredicate, 35, // 6030: check predicate 35 |
| 13130 | OPC_Decode, 132, 18, 141, 2, // 6032: decode to VCLTzv4f32 using decoder 269 |
| 13131 | // 6032: } |
| 13132 | // 6032: } // switch Inst[7:6] |
| 13133 | // 6032: } |
| 13134 | 11, 0, // 6037: case 0xb: { |
| 13135 | OPC_SwitchField, 6, 2, // 6039: switch Inst[7:6] { |
| 13136 | 0, 7, // 6042: case 0x0: { |
| 13137 | OPC_CheckPredicate, 35, // 6044: check predicate 35 |
| 13138 | OPC_Decode, 250, 18, 140, 2, // 6046: decode to VCVTs2fd using decoder 268 |
| 13139 | // 6046: } |
| 13140 | 1, 7, // 6051: case 0x1: { |
| 13141 | OPC_CheckPredicate, 35, // 6053: check predicate 35 |
| 13142 | OPC_Decode, 251, 18, 141, 2, // 6055: decode to VCVTs2fq using decoder 269 |
| 13143 | // 6055: } |
| 13144 | 2, 7, // 6060: case 0x2: { |
| 13145 | OPC_CheckPredicate, 35, // 6062: check predicate 35 |
| 13146 | OPC_Decode, 254, 18, 140, 2, // 6064: decode to VCVTu2fd using decoder 268 |
| 13147 | // 6064: } |
| 13148 | 3, 0, // 6069: case 0x3: { |
| 13149 | OPC_CheckPredicate, 35, // 6071: check predicate 35 |
| 13150 | OPC_Decode, 255, 18, 141, 2, // 6073: decode to VCVTu2fq using decoder 269 |
| 13151 | // 6073: } |
| 13152 | // 6073: } // switch Inst[7:6] |
| 13153 | // 6073: } |
| 13154 | // 6073: } // switch Inst[19:16] |
| 13155 | // 6073: } |
| 13156 | 7, 175, 2, // 6078: case 0x7: { |
| 13157 | OPC_SwitchField, 16, 4, // 6081: switch Inst[19:16] { |
| 13158 | 0, 39, // 6084: case 0x0: { |
| 13159 | OPC_SwitchField, 6, 2, // 6086: switch Inst[7:6] { |
| 13160 | 0, 7, // 6089: case 0x0: { |
| 13161 | OPC_CheckPredicate, 35, // 6091: check predicate 35 |
| 13162 | OPC_Decode, 248, 24, 140, 2, // 6093: decode to VQABSv8i8 using decoder 268 |
| 13163 | // 6093: } |
| 13164 | 1, 7, // 6098: case 0x1: { |
| 13165 | OPC_CheckPredicate, 35, // 6100: check predicate 35 |
| 13166 | OPC_Decode, 243, 24, 141, 2, // 6102: decode to VQABSv16i8 using decoder 269 |
| 13167 | // 6102: } |
| 13168 | 2, 7, // 6107: case 0x2: { |
| 13169 | OPC_CheckPredicate, 35, // 6109: check predicate 35 |
| 13170 | OPC_Decode, 171, 25, 140, 2, // 6111: decode to VQNEGv8i8 using decoder 268 |
| 13171 | // 6111: } |
| 13172 | 3, 0, // 6116: case 0x3: { |
| 13173 | OPC_CheckPredicate, 35, // 6118: check predicate 35 |
| 13174 | OPC_Decode, 166, 25, 141, 2, // 6120: decode to VQNEGv16i8 using decoder 269 |
| 13175 | // 6120: } |
| 13176 | // 6120: } // switch Inst[7:6] |
| 13177 | // 6120: } |
| 13178 | 4, 39, // 6125: case 0x4: { |
| 13179 | OPC_SwitchField, 6, 2, // 6127: switch Inst[7:6] { |
| 13180 | 0, 7, // 6130: case 0x0: { |
| 13181 | OPC_CheckPredicate, 35, // 6132: check predicate 35 |
| 13182 | OPC_Decode, 245, 24, 140, 2, // 6134: decode to VQABSv4i16 using decoder 268 |
| 13183 | // 6134: } |
| 13184 | 1, 7, // 6139: case 0x1: { |
| 13185 | OPC_CheckPredicate, 35, // 6141: check predicate 35 |
| 13186 | OPC_Decode, 247, 24, 141, 2, // 6143: decode to VQABSv8i16 using decoder 269 |
| 13187 | // 6143: } |
| 13188 | 2, 7, // 6148: case 0x2: { |
| 13189 | OPC_CheckPredicate, 35, // 6150: check predicate 35 |
| 13190 | OPC_Decode, 168, 25, 140, 2, // 6152: decode to VQNEGv4i16 using decoder 268 |
| 13191 | // 6152: } |
| 13192 | 3, 0, // 6157: case 0x3: { |
| 13193 | OPC_CheckPredicate, 35, // 6159: check predicate 35 |
| 13194 | OPC_Decode, 170, 25, 141, 2, // 6161: decode to VQNEGv8i16 using decoder 269 |
| 13195 | // 6161: } |
| 13196 | // 6161: } // switch Inst[7:6] |
| 13197 | // 6161: } |
| 13198 | 5, 39, // 6166: case 0x5: { |
| 13199 | OPC_SwitchField, 6, 2, // 6168: switch Inst[7:6] { |
| 13200 | 0, 7, // 6171: case 0x0: { |
| 13201 | OPC_CheckPredicate, 36, // 6173: check predicate 36 |
| 13202 | OPC_Decode, 226, 16, 140, 2, // 6175: decode to VABShd using decoder 268 |
| 13203 | // 6175: } |
| 13204 | 1, 7, // 6180: case 0x1: { |
| 13205 | OPC_CheckPredicate, 36, // 6182: check predicate 36 |
| 13206 | OPC_Decode, 227, 16, 141, 2, // 6184: decode to VABShq using decoder 269 |
| 13207 | // 6184: } |
| 13208 | 2, 7, // 6189: case 0x2: { |
| 13209 | OPC_CheckPredicate, 36, // 6191: check predicate 36 |
| 13210 | OPC_Decode, 173, 24, 140, 2, // 6193: decode to VNEGhd using decoder 268 |
| 13211 | // 6193: } |
| 13212 | 3, 0, // 6198: case 0x3: { |
| 13213 | OPC_CheckPredicate, 36, // 6200: check predicate 36 |
| 13214 | OPC_Decode, 174, 24, 141, 2, // 6202: decode to VNEGhq using decoder 269 |
| 13215 | // 6202: } |
| 13216 | // 6202: } // switch Inst[7:6] |
| 13217 | // 6202: } |
| 13218 | 6, 11, // 6207: case 0x6: { |
| 13219 | OPC_CheckPredicate, 39, // 6209: check predicate 39 |
| 13220 | OPC_CheckField, 6, 2, 0, // 6211: check Inst[7:6] == 0x0 |
| 13221 | OPC_Decode, 241, 18, 148, 2, // 6215: decode to VCVTh2f using decoder 276 |
| 13222 | // 6215: } |
| 13223 | 7, 39, // 6220: case 0x7: { |
| 13224 | OPC_SwitchField, 6, 2, // 6222: switch Inst[7:6] { |
| 13225 | 0, 7, // 6225: case 0x0: { |
| 13226 | OPC_CheckPredicate, 36, // 6227: check predicate 36 |
| 13227 | OPC_Decode, 242, 18, 140, 2, // 6229: decode to VCVTh2sd using decoder 268 |
| 13228 | // 6229: } |
| 13229 | 1, 7, // 6234: case 0x1: { |
| 13230 | OPC_CheckPredicate, 36, // 6236: check predicate 36 |
| 13231 | OPC_Decode, 243, 18, 141, 2, // 6238: decode to VCVTh2sq using decoder 269 |
| 13232 | // 6238: } |
| 13233 | 2, 7, // 6243: case 0x2: { |
| 13234 | OPC_CheckPredicate, 36, // 6245: check predicate 36 |
| 13235 | OPC_Decode, 244, 18, 140, 2, // 6247: decode to VCVTh2ud using decoder 268 |
| 13236 | // 6247: } |
| 13237 | 3, 0, // 6252: case 0x3: { |
| 13238 | OPC_CheckPredicate, 36, // 6254: check predicate 36 |
| 13239 | OPC_Decode, 245, 18, 141, 2, // 6256: decode to VCVTh2uq using decoder 269 |
| 13240 | // 6256: } |
| 13241 | // 6256: } // switch Inst[7:6] |
| 13242 | // 6256: } |
| 13243 | 8, 39, // 6261: case 0x8: { |
| 13244 | OPC_SwitchField, 6, 2, // 6263: switch Inst[7:6] { |
| 13245 | 0, 7, // 6266: case 0x0: { |
| 13246 | OPC_CheckPredicate, 35, // 6268: check predicate 35 |
| 13247 | OPC_Decode, 244, 24, 140, 2, // 6270: decode to VQABSv2i32 using decoder 268 |
| 13248 | // 6270: } |
| 13249 | 1, 7, // 6275: case 0x1: { |
| 13250 | OPC_CheckPredicate, 35, // 6277: check predicate 35 |
| 13251 | OPC_Decode, 246, 24, 141, 2, // 6279: decode to VQABSv4i32 using decoder 269 |
| 13252 | // 6279: } |
| 13253 | 2, 7, // 6284: case 0x2: { |
| 13254 | OPC_CheckPredicate, 35, // 6286: check predicate 35 |
| 13255 | OPC_Decode, 167, 25, 140, 2, // 6288: decode to VQNEGv2i32 using decoder 268 |
| 13256 | // 6288: } |
| 13257 | 3, 0, // 6293: case 0x3: { |
| 13258 | OPC_CheckPredicate, 35, // 6295: check predicate 35 |
| 13259 | OPC_Decode, 169, 25, 141, 2, // 6297: decode to VQNEGv4i32 using decoder 269 |
| 13260 | // 6297: } |
| 13261 | // 6297: } // switch Inst[7:6] |
| 13262 | // 6297: } |
| 13263 | 9, 39, // 6302: case 0x9: { |
| 13264 | OPC_SwitchField, 6, 2, // 6304: switch Inst[7:6] { |
| 13265 | 0, 7, // 6307: case 0x0: { |
| 13266 | OPC_CheckPredicate, 35, // 6309: check predicate 35 |
| 13267 | OPC_Decode, 224, 16, 140, 2, // 6311: decode to VABSfd using decoder 268 |
| 13268 | // 6311: } |
| 13269 | 1, 7, // 6316: case 0x1: { |
| 13270 | OPC_CheckPredicate, 35, // 6318: check predicate 35 |
| 13271 | OPC_Decode, 225, 16, 141, 2, // 6320: decode to VABSfq using decoder 269 |
| 13272 | // 6320: } |
| 13273 | 2, 7, // 6325: case 0x2: { |
| 13274 | OPC_CheckPredicate, 35, // 6327: check predicate 35 |
| 13275 | OPC_Decode, 172, 24, 140, 2, // 6329: decode to VNEGfd using decoder 268 |
| 13276 | // 6329: } |
| 13277 | 3, 0, // 6334: case 0x3: { |
| 13278 | OPC_CheckPredicate, 35, // 6336: check predicate 35 |
| 13279 | OPC_Decode, 171, 24, 141, 2, // 6338: decode to VNEGf32q using decoder 269 |
| 13280 | // 6338: } |
| 13281 | // 6338: } // switch Inst[7:6] |
| 13282 | // 6338: } |
| 13283 | 11, 0, // 6343: case 0xb: { |
| 13284 | OPC_SwitchField, 6, 2, // 6345: switch Inst[7:6] { |
| 13285 | 0, 7, // 6348: case 0x0: { |
| 13286 | OPC_CheckPredicate, 35, // 6350: check predicate 35 |
| 13287 | OPC_Decode, 233, 18, 140, 2, // 6352: decode to VCVTf2sd using decoder 268 |
| 13288 | // 6352: } |
| 13289 | 1, 7, // 6357: case 0x1: { |
| 13290 | OPC_CheckPredicate, 35, // 6359: check predicate 35 |
| 13291 | OPC_Decode, 234, 18, 141, 2, // 6361: decode to VCVTf2sq using decoder 269 |
| 13292 | // 6361: } |
| 13293 | 2, 7, // 6366: case 0x2: { |
| 13294 | OPC_CheckPredicate, 35, // 6368: check predicate 35 |
| 13295 | OPC_Decode, 235, 18, 140, 2, // 6370: decode to VCVTf2ud using decoder 268 |
| 13296 | // 6370: } |
| 13297 | 3, 0, // 6375: case 0x3: { |
| 13298 | OPC_CheckPredicate, 35, // 6377: check predicate 35 |
| 13299 | OPC_Decode, 236, 18, 141, 2, // 6379: decode to VCVTf2uq using decoder 269 |
| 13300 | // 6379: } |
| 13301 | // 6379: } // switch Inst[7:6] |
| 13302 | // 6379: } |
| 13303 | // 6379: } // switch Inst[19:16] |
| 13304 | // 6379: } |
| 13305 | 8, 21, // 6384: case 0x8: { |
| 13306 | OPC_SwitchField, 6, 1, // 6386: switch Inst[6] { |
| 13307 | 0, 7, // 6389: case 0x0: { |
| 13308 | OPC_CheckPredicate, 35, // 6391: check predicate 35 |
| 13309 | OPC_Decode, 230, 30, 149, 2, // 6393: decode to VTBL1 using decoder 277 |
| 13310 | // 6393: } |
| 13311 | 1, 0, // 6398: case 0x1: { |
| 13312 | OPC_CheckPredicate, 35, // 6400: check predicate 35 |
| 13313 | OPC_Decode, 236, 30, 149, 2, // 6402: decode to VTBX1 using decoder 277 |
| 13314 | // 6402: } |
| 13315 | // 6402: } // switch Inst[6] |
| 13316 | // 6402: } |
| 13317 | 9, 21, // 6407: case 0x9: { |
| 13318 | OPC_SwitchField, 6, 1, // 6409: switch Inst[6] { |
| 13319 | 0, 7, // 6412: case 0x0: { |
| 13320 | OPC_CheckPredicate, 35, // 6414: check predicate 35 |
| 13321 | OPC_Decode, 231, 30, 149, 2, // 6416: decode to VTBL2 using decoder 277 |
| 13322 | // 6416: } |
| 13323 | 1, 0, // 6421: case 0x1: { |
| 13324 | OPC_CheckPredicate, 35, // 6423: check predicate 35 |
| 13325 | OPC_Decode, 237, 30, 149, 2, // 6425: decode to VTBX2 using decoder 277 |
| 13326 | // 6425: } |
| 13327 | // 6425: } // switch Inst[6] |
| 13328 | // 6425: } |
| 13329 | 10, 21, // 6430: case 0xa: { |
| 13330 | OPC_SwitchField, 6, 1, // 6432: switch Inst[6] { |
| 13331 | 0, 7, // 6435: case 0x0: { |
| 13332 | OPC_CheckPredicate, 35, // 6437: check predicate 35 |
| 13333 | OPC_Decode, 232, 30, 149, 2, // 6439: decode to VTBL3 using decoder 277 |
| 13334 | // 6439: } |
| 13335 | 1, 0, // 6444: case 0x1: { |
| 13336 | OPC_CheckPredicate, 35, // 6446: check predicate 35 |
| 13337 | OPC_Decode, 238, 30, 149, 2, // 6448: decode to VTBX3 using decoder 277 |
| 13338 | // 6448: } |
| 13339 | // 6448: } // switch Inst[6] |
| 13340 | // 6448: } |
| 13341 | 11, 21, // 6453: case 0xb: { |
| 13342 | OPC_SwitchField, 6, 1, // 6455: switch Inst[6] { |
| 13343 | 0, 7, // 6458: case 0x0: { |
| 13344 | OPC_CheckPredicate, 35, // 6460: check predicate 35 |
| 13345 | OPC_Decode, 234, 30, 149, 2, // 6462: decode to VTBL4 using decoder 277 |
| 13346 | // 6462: } |
| 13347 | 1, 0, // 6467: case 0x1: { |
| 13348 | OPC_CheckPredicate, 35, // 6469: check predicate 35 |
| 13349 | OPC_Decode, 240, 30, 149, 2, // 6471: decode to VTBX4 using decoder 277 |
| 13350 | // 6471: } |
| 13351 | // 6471: } // switch Inst[6] |
| 13352 | // 6471: } |
| 13353 | 12, 0, // 6476: case 0xc: { |
| 13354 | OPC_SwitchField, 6, 2, // 6478: switch Inst[7:6] { |
| 13355 | 0, 39, // 6481: case 0x0: { |
| 13356 | OPC_SwitchField, 16, 1, // 6483: switch Inst[16] { |
| 13357 | 0, 25, // 6486: case 0x0: { |
| 13358 | OPC_SwitchField, 17, 1, // 6488: switch Inst[17] { |
| 13359 | 0, 11, // 6491: case 0x0: { |
| 13360 | OPC_CheckPredicate, 35, // 6493: check predicate 35 |
| 13361 | OPC_CheckField, 18, 1, 1, // 6495: check Inst[18] == 0x1 |
| 13362 | OPC_Decode, 149, 19, 150, 2, // 6499: decode to VDUPLN32d using decoder 278 |
| 13363 | // 6499: } |
| 13364 | 1, 0, // 6504: case 0x1: { |
| 13365 | OPC_CheckPredicate, 35, // 6506: check predicate 35 |
| 13366 | OPC_Decode, 147, 19, 151, 2, // 6508: decode to VDUPLN16d using decoder 279 |
| 13367 | // 6508: } |
| 13368 | // 6508: } // switch Inst[17] |
| 13369 | // 6508: } |
| 13370 | 1, 0, // 6513: case 0x1: { |
| 13371 | OPC_CheckPredicate, 35, // 6515: check predicate 35 |
| 13372 | OPC_Decode, 151, 19, 152, 2, // 6517: decode to VDUPLN8d using decoder 280 |
| 13373 | // 6517: } |
| 13374 | // 6517: } // switch Inst[16] |
| 13375 | // 6517: } |
| 13376 | 1, 0, // 6522: case 0x1: { |
| 13377 | OPC_SwitchField, 16, 1, // 6524: switch Inst[16] { |
| 13378 | 0, 25, // 6527: case 0x0: { |
| 13379 | OPC_SwitchField, 17, 1, // 6529: switch Inst[17] { |
| 13380 | 0, 11, // 6532: case 0x0: { |
| 13381 | OPC_CheckPredicate, 35, // 6534: check predicate 35 |
| 13382 | OPC_CheckField, 18, 1, 1, // 6536: check Inst[18] == 0x1 |
| 13383 | OPC_Decode, 150, 19, 153, 2, // 6540: decode to VDUPLN32q using decoder 281 |
| 13384 | // 6540: } |
| 13385 | 1, 0, // 6545: case 0x1: { |
| 13386 | OPC_CheckPredicate, 35, // 6547: check predicate 35 |
| 13387 | OPC_Decode, 148, 19, 154, 2, // 6549: decode to VDUPLN16q using decoder 282 |
| 13388 | // 6549: } |
| 13389 | // 6549: } // switch Inst[17] |
| 13390 | // 6549: } |
| 13391 | 1, 0, // 6554: case 0x1: { |
| 13392 | OPC_CheckPredicate, 35, // 6556: check predicate 35 |
| 13393 | OPC_Decode, 152, 19, 155, 2, // 6558: decode to VDUPLN8q using decoder 283 |
| 13394 | // 6558: } |
| 13395 | // 6558: } // switch Inst[16] |
| 13396 | // 6558: } |
| 13397 | // 6558: } // switch Inst[7:6] |
| 13398 | // 6558: } |
| 13399 | // 6558: } // switch Inst[11:8] |
| 13400 | // 6558: } |
| 13401 | // 6558: } // switch Inst[31:23] |
| 13402 | // 6558: } |
| 13403 | // 6558: } // switch Inst[21:20] |
| 13404 | // 6558: } |
| 13405 | 1, 0, // 6563: case 0x1: { |
| 13406 | OPC_SwitchField, 6, 1, // 6565: switch Inst[6] { |
| 13407 | 0, 217, 21, // 6568: case 0x0: { |
| 13408 | OPC_SwitchField, 23, 1, // 6571: switch Inst[23] { |
| 13409 | 0, 191, 10, // 6574: case 0x0: { |
| 13410 | OPC_SwitchField, 8, 4, // 6577: switch Inst[11:8] { |
| 13411 | 0, 103, // 6580: case 0x0: { |
| 13412 | OPC_SwitchField, 20, 2, // 6582: switch Inst[21:20] { |
| 13413 | 0, 23, // 6585: case 0x0: { |
| 13414 | OPC_SwitchField, 24, 8, // 6587: switch Inst[31:24] { |
| 13415 | 242, 1, 7, // 6590: case 0xf2: { |
| 13416 | OPC_CheckPredicate, 35, // 6593: check predicate 35 |
| 13417 | OPC_Decode, 128, 25, 238, 1, // 6595: decode to VQADDsv8i8 using decoder 238 |
| 13418 | // 6595: } |
| 13419 | 243, 1, 0, // 6600: case 0xf3: { |
| 13420 | OPC_CheckPredicate, 35, // 6603: check predicate 35 |
| 13421 | OPC_Decode, 136, 25, 238, 1, // 6605: decode to VQADDuv8i8 using decoder 238 |
| 13422 | // 6605: } |
| 13423 | // 6605: } // switch Inst[31:24] |
| 13424 | // 6605: } |
| 13425 | 1, 23, // 6610: case 0x1: { |
| 13426 | OPC_SwitchField, 24, 8, // 6612: switch Inst[31:24] { |
| 13427 | 242, 1, 7, // 6615: case 0xf2: { |
| 13428 | OPC_CheckPredicate, 35, // 6618: check predicate 35 |
| 13429 | OPC_Decode, 253, 24, 238, 1, // 6620: decode to VQADDsv4i16 using decoder 238 |
| 13430 | // 6620: } |
| 13431 | 243, 1, 0, // 6625: case 0xf3: { |
| 13432 | OPC_CheckPredicate, 35, // 6628: check predicate 35 |
| 13433 | OPC_Decode, 133, 25, 238, 1, // 6630: decode to VQADDuv4i16 using decoder 238 |
| 13434 | // 6630: } |
| 13435 | // 6630: } // switch Inst[31:24] |
| 13436 | // 6630: } |
| 13437 | 2, 23, // 6635: case 0x2: { |
| 13438 | OPC_SwitchField, 24, 8, // 6637: switch Inst[31:24] { |
| 13439 | 242, 1, 7, // 6640: case 0xf2: { |
| 13440 | OPC_CheckPredicate, 35, // 6643: check predicate 35 |
| 13441 | OPC_Decode, 251, 24, 238, 1, // 6645: decode to VQADDsv2i32 using decoder 238 |
| 13442 | // 6645: } |
| 13443 | 243, 1, 0, // 6650: case 0xf3: { |
| 13444 | OPC_CheckPredicate, 35, // 6653: check predicate 35 |
| 13445 | OPC_Decode, 131, 25, 238, 1, // 6655: decode to VQADDuv2i32 using decoder 238 |
| 13446 | // 6655: } |
| 13447 | // 6655: } // switch Inst[31:24] |
| 13448 | // 6655: } |
| 13449 | 3, 0, // 6660: case 0x3: { |
| 13450 | OPC_SwitchField, 24, 8, // 6662: switch Inst[31:24] { |
| 13451 | 242, 1, 7, // 6665: case 0xf2: { |
| 13452 | OPC_CheckPredicate, 35, // 6668: check predicate 35 |
| 13453 | OPC_Decode, 250, 24, 238, 1, // 6670: decode to VQADDsv1i64 using decoder 238 |
| 13454 | // 6670: } |
| 13455 | 243, 1, 0, // 6675: case 0xf3: { |
| 13456 | OPC_CheckPredicate, 35, // 6678: check predicate 35 |
| 13457 | OPC_Decode, 130, 25, 238, 1, // 6680: decode to VQADDuv1i64 using decoder 238 |
| 13458 | // 6680: } |
| 13459 | // 6680: } // switch Inst[31:24] |
| 13460 | // 6680: } |
| 13461 | // 6680: } // switch Inst[21:20] |
| 13462 | // 6680: } |
| 13463 | 1, 103, // 6685: case 0x1: { |
| 13464 | OPC_SwitchField, 20, 2, // 6687: switch Inst[21:20] { |
| 13465 | 0, 23, // 6690: case 0x0: { |
| 13466 | OPC_SwitchField, 24, 8, // 6692: switch Inst[31:24] { |
| 13467 | 242, 1, 7, // 6695: case 0xf2: { |
| 13468 | OPC_CheckPredicate, 35, // 6698: check predicate 35 |
| 13469 | OPC_Decode, 144, 17, 238, 1, // 6700: decode to VANDd using decoder 238 |
| 13470 | // 6700: } |
| 13471 | 243, 1, 0, // 6705: case 0xf3: { |
| 13472 | OPC_CheckPredicate, 35, // 6708: check predicate 35 |
| 13473 | OPC_Decode, 153, 19, 238, 1, // 6710: decode to VEORd using decoder 238 |
| 13474 | // 6710: } |
| 13475 | // 6710: } // switch Inst[31:24] |
| 13476 | // 6710: } |
| 13477 | 1, 23, // 6715: case 0x1: { |
| 13478 | OPC_SwitchField, 24, 8, // 6717: switch Inst[31:24] { |
| 13479 | 242, 1, 7, // 6720: case 0xf2: { |
| 13480 | OPC_CheckPredicate, 35, // 6723: check predicate 35 |
| 13481 | OPC_Decode, 150, 17, 238, 1, // 6725: decode to VBICd using decoder 238 |
| 13482 | // 6725: } |
| 13483 | 243, 1, 0, // 6730: case 0xf3: { |
| 13484 | OPC_CheckPredicate, 35, // 6733: check predicate 35 |
| 13485 | OPC_Decode, 160, 17, 246, 1, // 6735: decode to VBSLd using decoder 246 |
| 13486 | // 6735: } |
| 13487 | // 6735: } // switch Inst[31:24] |
| 13488 | // 6735: } |
| 13489 | 2, 23, // 6740: case 0x2: { |
| 13490 | OPC_SwitchField, 24, 8, // 6742: switch Inst[31:24] { |
| 13491 | 242, 1, 7, // 6745: case 0xf2: { |
| 13492 | OPC_CheckPredicate, 35, // 6748: check predicate 35 |
| 13493 | OPC_Decode, 192, 24, 238, 1, // 6750: decode to VORRd using decoder 238 |
| 13494 | // 6750: } |
| 13495 | 243, 1, 0, // 6755: case 0xf3: { |
| 13496 | OPC_CheckPredicate, 35, // 6758: check predicate 35 |
| 13497 | OPC_Decode, 158, 17, 246, 1, // 6760: decode to VBITd using decoder 246 |
| 13498 | // 6760: } |
| 13499 | // 6760: } // switch Inst[31:24] |
| 13500 | // 6760: } |
| 13501 | 3, 0, // 6765: case 0x3: { |
| 13502 | OPC_SwitchField, 24, 8, // 6767: switch Inst[31:24] { |
| 13503 | 242, 1, 7, // 6770: case 0xf2: { |
| 13504 | OPC_CheckPredicate, 35, // 6773: check predicate 35 |
| 13505 | OPC_Decode, 190, 24, 238, 1, // 6775: decode to VORNd using decoder 238 |
| 13506 | // 6775: } |
| 13507 | 243, 1, 0, // 6780: case 0xf3: { |
| 13508 | OPC_CheckPredicate, 35, // 6783: check predicate 35 |
| 13509 | OPC_Decode, 156, 17, 246, 1, // 6785: decode to VBIFd using decoder 246 |
| 13510 | // 6785: } |
| 13511 | // 6785: } // switch Inst[31:24] |
| 13512 | // 6785: } |
| 13513 | // 6785: } // switch Inst[21:20] |
| 13514 | // 6785: } |
| 13515 | 2, 103, // 6790: case 0x2: { |
| 13516 | OPC_SwitchField, 20, 2, // 6792: switch Inst[21:20] { |
| 13517 | 0, 23, // 6795: case 0x0: { |
| 13518 | OPC_SwitchField, 24, 8, // 6797: switch Inst[31:24] { |
| 13519 | 242, 1, 7, // 6800: case 0xf2: { |
| 13520 | OPC_CheckPredicate, 35, // 6803: check predicate 35 |
| 13521 | OPC_Decode, 149, 26, 238, 1, // 6805: decode to VQSUBsv8i8 using decoder 238 |
| 13522 | // 6805: } |
| 13523 | 243, 1, 0, // 6810: case 0xf3: { |
| 13524 | OPC_CheckPredicate, 35, // 6813: check predicate 35 |
| 13525 | OPC_Decode, 157, 26, 238, 1, // 6815: decode to VQSUBuv8i8 using decoder 238 |
| 13526 | // 6815: } |
| 13527 | // 6815: } // switch Inst[31:24] |
| 13528 | // 6815: } |
| 13529 | 1, 23, // 6820: case 0x1: { |
| 13530 | OPC_SwitchField, 24, 8, // 6822: switch Inst[31:24] { |
| 13531 | 242, 1, 7, // 6825: case 0xf2: { |
| 13532 | OPC_CheckPredicate, 35, // 6828: check predicate 35 |
| 13533 | OPC_Decode, 146, 26, 238, 1, // 6830: decode to VQSUBsv4i16 using decoder 238 |
| 13534 | // 6830: } |
| 13535 | 243, 1, 0, // 6835: case 0xf3: { |
| 13536 | OPC_CheckPredicate, 35, // 6838: check predicate 35 |
| 13537 | OPC_Decode, 154, 26, 238, 1, // 6840: decode to VQSUBuv4i16 using decoder 238 |
| 13538 | // 6840: } |
| 13539 | // 6840: } // switch Inst[31:24] |
| 13540 | // 6840: } |
| 13541 | 2, 23, // 6845: case 0x2: { |
| 13542 | OPC_SwitchField, 24, 8, // 6847: switch Inst[31:24] { |
| 13543 | 242, 1, 7, // 6850: case 0xf2: { |
| 13544 | OPC_CheckPredicate, 35, // 6853: check predicate 35 |
| 13545 | OPC_Decode, 144, 26, 238, 1, // 6855: decode to VQSUBsv2i32 using decoder 238 |
| 13546 | // 6855: } |
| 13547 | 243, 1, 0, // 6860: case 0xf3: { |
| 13548 | OPC_CheckPredicate, 35, // 6863: check predicate 35 |
| 13549 | OPC_Decode, 152, 26, 238, 1, // 6865: decode to VQSUBuv2i32 using decoder 238 |
| 13550 | // 6865: } |
| 13551 | // 6865: } // switch Inst[31:24] |
| 13552 | // 6865: } |
| 13553 | 3, 0, // 6870: case 0x3: { |
| 13554 | OPC_SwitchField, 24, 8, // 6872: switch Inst[31:24] { |
| 13555 | 242, 1, 7, // 6875: case 0xf2: { |
| 13556 | OPC_CheckPredicate, 35, // 6878: check predicate 35 |
| 13557 | OPC_Decode, 143, 26, 238, 1, // 6880: decode to VQSUBsv1i64 using decoder 238 |
| 13558 | // 6880: } |
| 13559 | 243, 1, 0, // 6885: case 0xf3: { |
| 13560 | OPC_CheckPredicate, 35, // 6888: check predicate 35 |
| 13561 | OPC_Decode, 151, 26, 238, 1, // 6890: decode to VQSUBuv1i64 using decoder 238 |
| 13562 | // 6890: } |
| 13563 | // 6890: } // switch Inst[31:24] |
| 13564 | // 6890: } |
| 13565 | // 6890: } // switch Inst[21:20] |
| 13566 | // 6890: } |
| 13567 | 3, 78, // 6895: case 0x3: { |
| 13568 | OPC_SwitchField, 20, 2, // 6897: switch Inst[21:20] { |
| 13569 | 0, 23, // 6900: case 0x0: { |
| 13570 | OPC_SwitchField, 24, 8, // 6902: switch Inst[31:24] { |
| 13571 | 242, 1, 7, // 6905: case 0xf2: { |
| 13572 | OPC_CheckPredicate, 35, // 6908: check predicate 35 |
| 13573 | OPC_Decode, 197, 17, 238, 1, // 6910: decode to VCGEsv8i8 using decoder 238 |
| 13574 | // 6910: } |
| 13575 | 243, 1, 0, // 6915: case 0xf3: { |
| 13576 | OPC_CheckPredicate, 35, // 6918: check predicate 35 |
| 13577 | OPC_Decode, 203, 17, 238, 1, // 6920: decode to VCGEuv8i8 using decoder 238 |
| 13578 | // 6920: } |
| 13579 | // 6920: } // switch Inst[31:24] |
| 13580 | // 6920: } |
| 13581 | 1, 23, // 6925: case 0x1: { |
| 13582 | OPC_SwitchField, 24, 8, // 6927: switch Inst[31:24] { |
| 13583 | 242, 1, 7, // 6930: case 0xf2: { |
| 13584 | OPC_CheckPredicate, 35, // 6933: check predicate 35 |
| 13585 | OPC_Decode, 194, 17, 238, 1, // 6935: decode to VCGEsv4i16 using decoder 238 |
| 13586 | // 6935: } |
| 13587 | 243, 1, 0, // 6940: case 0xf3: { |
| 13588 | OPC_CheckPredicate, 35, // 6943: check predicate 35 |
| 13589 | OPC_Decode, 200, 17, 238, 1, // 6945: decode to VCGEuv4i16 using decoder 238 |
| 13590 | // 6945: } |
| 13591 | // 6945: } // switch Inst[31:24] |
| 13592 | // 6945: } |
| 13593 | 2, 0, // 6950: case 0x2: { |
| 13594 | OPC_SwitchField, 24, 8, // 6952: switch Inst[31:24] { |
| 13595 | 242, 1, 7, // 6955: case 0xf2: { |
| 13596 | OPC_CheckPredicate, 35, // 6958: check predicate 35 |
| 13597 | OPC_Decode, 193, 17, 238, 1, // 6960: decode to VCGEsv2i32 using decoder 238 |
| 13598 | // 6960: } |
| 13599 | 243, 1, 0, // 6965: case 0xf3: { |
| 13600 | OPC_CheckPredicate, 35, // 6968: check predicate 35 |
| 13601 | OPC_Decode, 199, 17, 238, 1, // 6970: decode to VCGEuv2i32 using decoder 238 |
| 13602 | // 6970: } |
| 13603 | // 6970: } // switch Inst[31:24] |
| 13604 | // 6970: } |
| 13605 | // 6970: } // switch Inst[21:20] |
| 13606 | // 6970: } |
| 13607 | 4, 103, // 6975: case 0x4: { |
| 13608 | OPC_SwitchField, 20, 2, // 6977: switch Inst[21:20] { |
| 13609 | 0, 23, // 6980: case 0x0: { |
| 13610 | OPC_SwitchField, 24, 8, // 6982: switch Inst[31:24] { |
| 13611 | 242, 1, 7, // 6985: case 0xf2: { |
| 13612 | OPC_CheckPredicate, 35, // 6988: check predicate 35 |
| 13613 | OPC_Decode, 244, 25, 242, 1, // 6990: decode to VQSHLsv8i8 using decoder 242 |
| 13614 | // 6990: } |
| 13615 | 243, 1, 0, // 6995: case 0xf3: { |
| 13616 | OPC_CheckPredicate, 35, // 6998: check predicate 35 |
| 13617 | OPC_Decode, 132, 26, 242, 1, // 7000: decode to VQSHLuv8i8 using decoder 242 |
| 13618 | // 7000: } |
| 13619 | // 7000: } // switch Inst[31:24] |
| 13620 | // 7000: } |
| 13621 | 1, 23, // 7005: case 0x1: { |
| 13622 | OPC_SwitchField, 24, 8, // 7007: switch Inst[31:24] { |
| 13623 | 242, 1, 7, // 7010: case 0xf2: { |
| 13624 | OPC_CheckPredicate, 35, // 7013: check predicate 35 |
| 13625 | OPC_Decode, 241, 25, 242, 1, // 7015: decode to VQSHLsv4i16 using decoder 242 |
| 13626 | // 7015: } |
| 13627 | 243, 1, 0, // 7020: case 0xf3: { |
| 13628 | OPC_CheckPredicate, 35, // 7023: check predicate 35 |
| 13629 | OPC_Decode, 129, 26, 242, 1, // 7025: decode to VQSHLuv4i16 using decoder 242 |
| 13630 | // 7025: } |
| 13631 | // 7025: } // switch Inst[31:24] |
| 13632 | // 7025: } |
| 13633 | 2, 23, // 7030: case 0x2: { |
| 13634 | OPC_SwitchField, 24, 8, // 7032: switch Inst[31:24] { |
| 13635 | 242, 1, 7, // 7035: case 0xf2: { |
| 13636 | OPC_CheckPredicate, 35, // 7038: check predicate 35 |
| 13637 | OPC_Decode, 239, 25, 242, 1, // 7040: decode to VQSHLsv2i32 using decoder 242 |
| 13638 | // 7040: } |
| 13639 | 243, 1, 0, // 7045: case 0xf3: { |
| 13640 | OPC_CheckPredicate, 35, // 7048: check predicate 35 |
| 13641 | OPC_Decode, 255, 25, 242, 1, // 7050: decode to VQSHLuv2i32 using decoder 242 |
| 13642 | // 7050: } |
| 13643 | // 7050: } // switch Inst[31:24] |
| 13644 | // 7050: } |
| 13645 | 3, 0, // 7055: case 0x3: { |
| 13646 | OPC_SwitchField, 24, 8, // 7057: switch Inst[31:24] { |
| 13647 | 242, 1, 7, // 7060: case 0xf2: { |
| 13648 | OPC_CheckPredicate, 35, // 7063: check predicate 35 |
| 13649 | OPC_Decode, 238, 25, 242, 1, // 7065: decode to VQSHLsv1i64 using decoder 242 |
| 13650 | // 7065: } |
| 13651 | 243, 1, 0, // 7070: case 0xf3: { |
| 13652 | OPC_CheckPredicate, 35, // 7073: check predicate 35 |
| 13653 | OPC_Decode, 254, 25, 242, 1, // 7075: decode to VQSHLuv1i64 using decoder 242 |
| 13654 | // 7075: } |
| 13655 | // 7075: } // switch Inst[31:24] |
| 13656 | // 7075: } |
| 13657 | // 7075: } // switch Inst[21:20] |
| 13658 | // 7075: } |
| 13659 | 5, 103, // 7080: case 0x5: { |
| 13660 | OPC_SwitchField, 20, 2, // 7082: switch Inst[21:20] { |
| 13661 | 0, 23, // 7085: case 0x0: { |
| 13662 | OPC_SwitchField, 24, 8, // 7087: switch Inst[31:24] { |
| 13663 | 242, 1, 7, // 7090: case 0xf2: { |
| 13664 | OPC_CheckPredicate, 35, // 7093: check predicate 35 |
| 13665 | OPC_Decode, 203, 25, 242, 1, // 7095: decode to VQRSHLsv8i8 using decoder 242 |
| 13666 | // 7095: } |
| 13667 | 243, 1, 0, // 7100: case 0xf3: { |
| 13668 | OPC_CheckPredicate, 35, // 7103: check predicate 35 |
| 13669 | OPC_Decode, 211, 25, 242, 1, // 7105: decode to VQRSHLuv8i8 using decoder 242 |
| 13670 | // 7105: } |
| 13671 | // 7105: } // switch Inst[31:24] |
| 13672 | // 7105: } |
| 13673 | 1, 23, // 7110: case 0x1: { |
| 13674 | OPC_SwitchField, 24, 8, // 7112: switch Inst[31:24] { |
| 13675 | 242, 1, 7, // 7115: case 0xf2: { |
| 13676 | OPC_CheckPredicate, 35, // 7118: check predicate 35 |
| 13677 | OPC_Decode, 200, 25, 242, 1, // 7120: decode to VQRSHLsv4i16 using decoder 242 |
| 13678 | // 7120: } |
| 13679 | 243, 1, 0, // 7125: case 0xf3: { |
| 13680 | OPC_CheckPredicate, 35, // 7128: check predicate 35 |
| 13681 | OPC_Decode, 208, 25, 242, 1, // 7130: decode to VQRSHLuv4i16 using decoder 242 |
| 13682 | // 7130: } |
| 13683 | // 7130: } // switch Inst[31:24] |
| 13684 | // 7130: } |
| 13685 | 2, 23, // 7135: case 0x2: { |
| 13686 | OPC_SwitchField, 24, 8, // 7137: switch Inst[31:24] { |
| 13687 | 242, 1, 7, // 7140: case 0xf2: { |
| 13688 | OPC_CheckPredicate, 35, // 7143: check predicate 35 |
| 13689 | OPC_Decode, 198, 25, 242, 1, // 7145: decode to VQRSHLsv2i32 using decoder 242 |
| 13690 | // 7145: } |
| 13691 | 243, 1, 0, // 7150: case 0xf3: { |
| 13692 | OPC_CheckPredicate, 35, // 7153: check predicate 35 |
| 13693 | OPC_Decode, 206, 25, 242, 1, // 7155: decode to VQRSHLuv2i32 using decoder 242 |
| 13694 | // 7155: } |
| 13695 | // 7155: } // switch Inst[31:24] |
| 13696 | // 7155: } |
| 13697 | 3, 0, // 7160: case 0x3: { |
| 13698 | OPC_SwitchField, 24, 8, // 7162: switch Inst[31:24] { |
| 13699 | 242, 1, 7, // 7165: case 0xf2: { |
| 13700 | OPC_CheckPredicate, 35, // 7168: check predicate 35 |
| 13701 | OPC_Decode, 197, 25, 242, 1, // 7170: decode to VQRSHLsv1i64 using decoder 242 |
| 13702 | // 7170: } |
| 13703 | 243, 1, 0, // 7175: case 0xf3: { |
| 13704 | OPC_CheckPredicate, 35, // 7178: check predicate 35 |
| 13705 | OPC_Decode, 205, 25, 242, 1, // 7180: decode to VQRSHLuv1i64 using decoder 242 |
| 13706 | // 7180: } |
| 13707 | // 7180: } // switch Inst[31:24] |
| 13708 | // 7180: } |
| 13709 | // 7180: } // switch Inst[21:20] |
| 13710 | // 7180: } |
| 13711 | 6, 78, // 7185: case 0x6: { |
| 13712 | OPC_SwitchField, 20, 2, // 7187: switch Inst[21:20] { |
| 13713 | 0, 23, // 7190: case 0x0: { |
| 13714 | OPC_SwitchField, 24, 8, // 7192: switch Inst[31:24] { |
| 13715 | 242, 1, 7, // 7195: case 0xf2: { |
| 13716 | OPC_CheckPredicate, 35, // 7198: check predicate 35 |
| 13717 | OPC_Decode, 132, 23, 238, 1, // 7200: decode to VMINsv8i8 using decoder 238 |
| 13718 | // 7200: } |
| 13719 | 243, 1, 0, // 7205: case 0xf3: { |
| 13720 | OPC_CheckPredicate, 35, // 7208: check predicate 35 |
| 13721 | OPC_Decode, 138, 23, 238, 1, // 7210: decode to VMINuv8i8 using decoder 238 |
| 13722 | // 7210: } |
| 13723 | // 7210: } // switch Inst[31:24] |
| 13724 | // 7210: } |
| 13725 | 1, 23, // 7215: case 0x1: { |
| 13726 | OPC_SwitchField, 24, 8, // 7217: switch Inst[31:24] { |
| 13727 | 242, 1, 7, // 7220: case 0xf2: { |
| 13728 | OPC_CheckPredicate, 35, // 7223: check predicate 35 |
| 13729 | OPC_Decode, 129, 23, 238, 1, // 7225: decode to VMINsv4i16 using decoder 238 |
| 13730 | // 7225: } |
| 13731 | 243, 1, 0, // 7230: case 0xf3: { |
| 13732 | OPC_CheckPredicate, 35, // 7233: check predicate 35 |
| 13733 | OPC_Decode, 135, 23, 238, 1, // 7235: decode to VMINuv4i16 using decoder 238 |
| 13734 | // 7235: } |
| 13735 | // 7235: } // switch Inst[31:24] |
| 13736 | // 7235: } |
| 13737 | 2, 0, // 7240: case 0x2: { |
| 13738 | OPC_SwitchField, 24, 8, // 7242: switch Inst[31:24] { |
| 13739 | 242, 1, 7, // 7245: case 0xf2: { |
| 13740 | OPC_CheckPredicate, 35, // 7248: check predicate 35 |
| 13741 | OPC_Decode, 128, 23, 238, 1, // 7250: decode to VMINsv2i32 using decoder 238 |
| 13742 | // 7250: } |
| 13743 | 243, 1, 0, // 7255: case 0xf3: { |
| 13744 | OPC_CheckPredicate, 35, // 7258: check predicate 35 |
| 13745 | OPC_Decode, 134, 23, 238, 1, // 7260: decode to VMINuv2i32 using decoder 238 |
| 13746 | // 7260: } |
| 13747 | // 7260: } // switch Inst[31:24] |
| 13748 | // 7260: } |
| 13749 | // 7260: } // switch Inst[21:20] |
| 13750 | // 7260: } |
| 13751 | 7, 78, // 7265: case 0x7: { |
| 13752 | OPC_SwitchField, 20, 2, // 7267: switch Inst[21:20] { |
| 13753 | 0, 23, // 7270: case 0x0: { |
| 13754 | OPC_SwitchField, 24, 8, // 7272: switch Inst[31:24] { |
| 13755 | 242, 1, 7, // 7275: case 0xf2: { |
| 13756 | OPC_CheckPredicate, 35, // 7278: check predicate 35 |
| 13757 | OPC_Decode, 192, 16, 246, 1, // 7280: decode to VABAsv8i8 using decoder 246 |
| 13758 | // 7280: } |
| 13759 | 243, 1, 0, // 7285: case 0xf3: { |
| 13760 | OPC_CheckPredicate, 35, // 7288: check predicate 35 |
| 13761 | OPC_Decode, 198, 16, 246, 1, // 7290: decode to VABAuv8i8 using decoder 246 |
| 13762 | // 7290: } |
| 13763 | // 7290: } // switch Inst[31:24] |
| 13764 | // 7290: } |
| 13765 | 1, 23, // 7295: case 0x1: { |
| 13766 | OPC_SwitchField, 24, 8, // 7297: switch Inst[31:24] { |
| 13767 | 242, 1, 7, // 7300: case 0xf2: { |
| 13768 | OPC_CheckPredicate, 35, // 7303: check predicate 35 |
| 13769 | OPC_Decode, 189, 16, 246, 1, // 7305: decode to VABAsv4i16 using decoder 246 |
| 13770 | // 7305: } |
| 13771 | 243, 1, 0, // 7310: case 0xf3: { |
| 13772 | OPC_CheckPredicate, 35, // 7313: check predicate 35 |
| 13773 | OPC_Decode, 195, 16, 246, 1, // 7315: decode to VABAuv4i16 using decoder 246 |
| 13774 | // 7315: } |
| 13775 | // 7315: } // switch Inst[31:24] |
| 13776 | // 7315: } |
| 13777 | 2, 0, // 7320: case 0x2: { |
| 13778 | OPC_SwitchField, 24, 8, // 7322: switch Inst[31:24] { |
| 13779 | 242, 1, 7, // 7325: case 0xf2: { |
| 13780 | OPC_CheckPredicate, 35, // 7328: check predicate 35 |
| 13781 | OPC_Decode, 188, 16, 246, 1, // 7330: decode to VABAsv2i32 using decoder 246 |
| 13782 | // 7330: } |
| 13783 | 243, 1, 0, // 7335: case 0xf3: { |
| 13784 | OPC_CheckPredicate, 35, // 7338: check predicate 35 |
| 13785 | OPC_Decode, 194, 16, 246, 1, // 7340: decode to VABAuv2i32 using decoder 246 |
| 13786 | // 7340: } |
| 13787 | // 7340: } // switch Inst[31:24] |
| 13788 | // 7340: } |
| 13789 | // 7340: } // switch Inst[21:20] |
| 13790 | // 7340: } |
| 13791 | 8, 78, // 7345: case 0x8: { |
| 13792 | OPC_SwitchField, 20, 2, // 7347: switch Inst[21:20] { |
| 13793 | 0, 23, // 7350: case 0x0: { |
| 13794 | OPC_SwitchField, 24, 8, // 7352: switch Inst[31:24] { |
| 13795 | 242, 1, 7, // 7355: case 0xf2: { |
| 13796 | OPC_CheckPredicate, 35, // 7358: check predicate 35 |
| 13797 | OPC_Decode, 149, 31, 238, 1, // 7360: decode to VTSTv8i8 using decoder 238 |
| 13798 | // 7360: } |
| 13799 | 243, 1, 0, // 7365: case 0xf3: { |
| 13800 | OPC_CheckPredicate, 35, // 7368: check predicate 35 |
| 13801 | OPC_Decode, 177, 17, 238, 1, // 7370: decode to VCEQv8i8 using decoder 238 |
| 13802 | // 7370: } |
| 13803 | // 7370: } // switch Inst[31:24] |
| 13804 | // 7370: } |
| 13805 | 1, 23, // 7375: case 0x1: { |
| 13806 | OPC_SwitchField, 24, 8, // 7377: switch Inst[31:24] { |
| 13807 | 242, 1, 7, // 7380: case 0xf2: { |
| 13808 | OPC_CheckPredicate, 35, // 7383: check predicate 35 |
| 13809 | OPC_Decode, 146, 31, 238, 1, // 7385: decode to VTSTv4i16 using decoder 238 |
| 13810 | // 7385: } |
| 13811 | 243, 1, 0, // 7390: case 0xf3: { |
| 13812 | OPC_CheckPredicate, 35, // 7393: check predicate 35 |
| 13813 | OPC_Decode, 174, 17, 238, 1, // 7395: decode to VCEQv4i16 using decoder 238 |
| 13814 | // 7395: } |
| 13815 | // 7395: } // switch Inst[31:24] |
| 13816 | // 7395: } |
| 13817 | 2, 0, // 7400: case 0x2: { |
| 13818 | OPC_SwitchField, 24, 8, // 7402: switch Inst[31:24] { |
| 13819 | 242, 1, 7, // 7405: case 0xf2: { |
| 13820 | OPC_CheckPredicate, 35, // 7408: check predicate 35 |
| 13821 | OPC_Decode, 145, 31, 238, 1, // 7410: decode to VTSTv2i32 using decoder 238 |
| 13822 | // 7410: } |
| 13823 | 243, 1, 0, // 7415: case 0xf3: { |
| 13824 | OPC_CheckPredicate, 35, // 7418: check predicate 35 |
| 13825 | OPC_Decode, 173, 17, 238, 1, // 7420: decode to VCEQv2i32 using decoder 238 |
| 13826 | // 7420: } |
| 13827 | // 7420: } // switch Inst[31:24] |
| 13828 | // 7420: } |
| 13829 | // 7420: } // switch Inst[21:20] |
| 13830 | // 7420: } |
| 13831 | 9, 56, // 7425: case 0x9: { |
| 13832 | OPC_SwitchField, 20, 2, // 7427: switch Inst[21:20] { |
| 13833 | 0, 23, // 7430: case 0x0: { |
| 13834 | OPC_SwitchField, 24, 8, // 7432: switch Inst[31:24] { |
| 13835 | 242, 1, 7, // 7435: case 0xf2: { |
| 13836 | OPC_CheckPredicate, 35, // 7438: check predicate 35 |
| 13837 | OPC_Decode, 161, 24, 238, 1, // 7440: decode to VMULv8i8 using decoder 238 |
| 13838 | // 7440: } |
| 13839 | 243, 1, 0, // 7445: case 0xf3: { |
| 13840 | OPC_CheckPredicate, 35, // 7448: check predicate 35 |
| 13841 | OPC_Decode, 146, 24, 238, 1, // 7450: decode to VMULpd using decoder 238 |
| 13842 | // 7450: } |
| 13843 | // 7450: } // switch Inst[31:24] |
| 13844 | // 7450: } |
| 13845 | 1, 12, // 7455: case 0x1: { |
| 13846 | OPC_CheckPredicate, 35, // 7457: check predicate 35 |
| 13847 | OPC_CheckField, 24, 8, 242, 1, // 7459: check Inst[31:24] == 0xf2 |
| 13848 | OPC_Decode, 158, 24, 238, 1, // 7464: decode to VMULv4i16 using decoder 238 |
| 13849 | // 7464: } |
| 13850 | 2, 0, // 7469: case 0x2: { |
| 13851 | OPC_CheckPredicate, 35, // 7471: check predicate 35 |
| 13852 | OPC_CheckField, 24, 8, 242, 1, // 7473: check Inst[31:24] == 0xf2 |
| 13853 | OPC_Decode, 157, 24, 238, 1, // 7478: decode to VMULv2i32 using decoder 238 |
| 13854 | // 7478: } |
| 13855 | // 7478: } // switch Inst[21:20] |
| 13856 | // 7478: } |
| 13857 | 10, 78, // 7483: case 0xa: { |
| 13858 | OPC_SwitchField, 20, 2, // 7485: switch Inst[21:20] { |
| 13859 | 0, 23, // 7488: case 0x0: { |
| 13860 | OPC_SwitchField, 24, 8, // 7490: switch Inst[31:24] { |
| 13861 | 242, 1, 7, // 7493: case 0xf2: { |
| 13862 | OPC_CheckPredicate, 35, // 7496: check predicate 35 |
| 13863 | OPC_Decode, 239, 24, 238, 1, // 7498: decode to VPMINs8 using decoder 238 |
| 13864 | // 7498: } |
| 13865 | 243, 1, 0, // 7503: case 0xf3: { |
| 13866 | OPC_CheckPredicate, 35, // 7506: check predicate 35 |
| 13867 | OPC_Decode, 242, 24, 238, 1, // 7508: decode to VPMINu8 using decoder 238 |
| 13868 | // 7508: } |
| 13869 | // 7508: } // switch Inst[31:24] |
| 13870 | // 7508: } |
| 13871 | 1, 23, // 7513: case 0x1: { |
| 13872 | OPC_SwitchField, 24, 8, // 7515: switch Inst[31:24] { |
| 13873 | 242, 1, 7, // 7518: case 0xf2: { |
| 13874 | OPC_CheckPredicate, 35, // 7521: check predicate 35 |
| 13875 | OPC_Decode, 237, 24, 238, 1, // 7523: decode to VPMINs16 using decoder 238 |
| 13876 | // 7523: } |
| 13877 | 243, 1, 0, // 7528: case 0xf3: { |
| 13878 | OPC_CheckPredicate, 35, // 7531: check predicate 35 |
| 13879 | OPC_Decode, 240, 24, 238, 1, // 7533: decode to VPMINu16 using decoder 238 |
| 13880 | // 7533: } |
| 13881 | // 7533: } // switch Inst[31:24] |
| 13882 | // 7533: } |
| 13883 | 2, 0, // 7538: case 0x2: { |
| 13884 | OPC_SwitchField, 24, 8, // 7540: switch Inst[31:24] { |
| 13885 | 242, 1, 7, // 7543: case 0xf2: { |
| 13886 | OPC_CheckPredicate, 35, // 7546: check predicate 35 |
| 13887 | OPC_Decode, 238, 24, 238, 1, // 7548: decode to VPMINs32 using decoder 238 |
| 13888 | // 7548: } |
| 13889 | 243, 1, 0, // 7553: case 0xf3: { |
| 13890 | OPC_CheckPredicate, 35, // 7556: check predicate 35 |
| 13891 | OPC_Decode, 241, 24, 238, 1, // 7558: decode to VPMINu32 using decoder 238 |
| 13892 | // 7558: } |
| 13893 | // 7558: } // switch Inst[31:24] |
| 13894 | // 7558: } |
| 13895 | // 7558: } // switch Inst[21:20] |
| 13896 | // 7558: } |
| 13897 | 11, 67, // 7563: case 0xb: { |
| 13898 | OPC_SwitchField, 20, 2, // 7565: switch Inst[21:20] { |
| 13899 | 0, 12, // 7568: case 0x0: { |
| 13900 | OPC_CheckPredicate, 35, // 7570: check predicate 35 |
| 13901 | OPC_CheckField, 24, 8, 242, 1, // 7572: check Inst[31:24] == 0xf2 |
| 13902 | OPC_Decode, 226, 24, 238, 1, // 7577: decode to VPADDi8 using decoder 238 |
| 13903 | // 7577: } |
| 13904 | 1, 23, // 7582: case 0x1: { |
| 13905 | OPC_SwitchField, 24, 8, // 7584: switch Inst[31:24] { |
| 13906 | 242, 1, 7, // 7587: case 0xf2: { |
| 13907 | OPC_CheckPredicate, 35, // 7590: check predicate 35 |
| 13908 | OPC_Decode, 224, 24, 238, 1, // 7592: decode to VPADDi16 using decoder 238 |
| 13909 | // 7592: } |
| 13910 | 243, 1, 0, // 7597: case 0xf3: { |
| 13911 | OPC_CheckPredicate, 37, // 7600: check predicate 37 |
| 13912 | OPC_Decode, 177, 25, 246, 1, // 7602: decode to VQRDMLAHv4i16 using decoder 246 |
| 13913 | // 7602: } |
| 13914 | // 7602: } // switch Inst[31:24] |
| 13915 | // 7602: } |
| 13916 | 2, 0, // 7607: case 0x2: { |
| 13917 | OPC_SwitchField, 24, 8, // 7609: switch Inst[31:24] { |
| 13918 | 242, 1, 7, // 7612: case 0xf2: { |
| 13919 | OPC_CheckPredicate, 35, // 7615: check predicate 35 |
| 13920 | OPC_Decode, 225, 24, 238, 1, // 7617: decode to VPADDi32 using decoder 238 |
| 13921 | // 7617: } |
| 13922 | 243, 1, 0, // 7622: case 0xf3: { |
| 13923 | OPC_CheckPredicate, 37, // 7625: check predicate 37 |
| 13924 | OPC_Decode, 176, 25, 246, 1, // 7627: decode to VQRDMLAHv2i32 using decoder 246 |
| 13925 | // 7627: } |
| 13926 | // 7627: } // switch Inst[31:24] |
| 13927 | // 7627: } |
| 13928 | // 7627: } // switch Inst[21:20] |
| 13929 | // 7627: } |
| 13930 | 12, 81, // 7632: case 0xc: { |
| 13931 | OPC_SwitchField, 20, 2, // 7634: switch Inst[21:20] { |
| 13932 | 0, 12, // 7637: case 0x0: { |
| 13933 | OPC_CheckPredicate, 41, // 7639: check predicate 41 |
| 13934 | OPC_CheckField, 24, 8, 242, 1, // 7641: check Inst[31:24] == 0xf2 |
| 13935 | OPC_Decode, 169, 19, 246, 1, // 7646: decode to VFMAfd using decoder 246 |
| 13936 | // 7646: } |
| 13937 | 1, 23, // 7651: case 0x1: { |
| 13938 | OPC_SwitchField, 24, 8, // 7653: switch Inst[31:24] { |
| 13939 | 242, 1, 7, // 7656: case 0xf2: { |
| 13940 | OPC_CheckPredicate, 36, // 7659: check predicate 36 |
| 13941 | OPC_Decode, 171, 19, 246, 1, // 7661: decode to VFMAhd using decoder 246 |
| 13942 | // 7661: } |
| 13943 | 243, 1, 0, // 7666: case 0xf3: { |
| 13944 | OPC_CheckPredicate, 37, // 7669: check predicate 37 |
| 13945 | OPC_Decode, 185, 25, 246, 1, // 7671: decode to VQRDMLSHv4i16 using decoder 246 |
| 13946 | // 7671: } |
| 13947 | // 7671: } // switch Inst[31:24] |
| 13948 | // 7671: } |
| 13949 | 2, 23, // 7676: case 0x2: { |
| 13950 | OPC_SwitchField, 24, 8, // 7678: switch Inst[31:24] { |
| 13951 | 242, 1, 7, // 7681: case 0xf2: { |
| 13952 | OPC_CheckPredicate, 41, // 7684: check predicate 41 |
| 13953 | OPC_Decode, 180, 19, 246, 1, // 7686: decode to VFMSfd using decoder 246 |
| 13954 | // 7686: } |
| 13955 | 243, 1, 0, // 7691: case 0xf3: { |
| 13956 | OPC_CheckPredicate, 37, // 7694: check predicate 37 |
| 13957 | OPC_Decode, 184, 25, 246, 1, // 7696: decode to VQRDMLSHv2i32 using decoder 246 |
| 13958 | // 7696: } |
| 13959 | // 7696: } // switch Inst[31:24] |
| 13960 | // 7696: } |
| 13961 | 3, 0, // 7701: case 0x3: { |
| 13962 | OPC_CheckPredicate, 36, // 7703: check predicate 36 |
| 13963 | OPC_CheckField, 24, 8, 242, 1, // 7705: check Inst[31:24] == 0xf2 |
| 13964 | OPC_Decode, 182, 19, 246, 1, // 7710: decode to VFMShd using decoder 246 |
| 13965 | // 7710: } |
| 13966 | // 7710: } // switch Inst[21:20] |
| 13967 | // 7710: } |
| 13968 | 13, 81, // 7715: case 0xd: { |
| 13969 | OPC_SwitchField, 20, 2, // 7717: switch Inst[21:20] { |
| 13970 | 0, 23, // 7720: case 0x0: { |
| 13971 | OPC_SwitchField, 24, 8, // 7722: switch Inst[31:24] { |
| 13972 | 242, 1, 7, // 7725: case 0xf2: { |
| 13973 | OPC_CheckPredicate, 35, // 7728: check predicate 35 |
| 13974 | OPC_Decode, 152, 23, 246, 1, // 7730: decode to VMLAfd using decoder 246 |
| 13975 | // 7730: } |
| 13976 | 243, 1, 0, // 7735: case 0xf3: { |
| 13977 | OPC_CheckPredicate, 35, // 7738: check predicate 35 |
| 13978 | OPC_Decode, 142, 24, 238, 1, // 7740: decode to VMULfd using decoder 238 |
| 13979 | // 7740: } |
| 13980 | // 7740: } // switch Inst[31:24] |
| 13981 | // 7740: } |
| 13982 | 1, 23, // 7745: case 0x1: { |
| 13983 | OPC_SwitchField, 24, 8, // 7747: switch Inst[31:24] { |
| 13984 | 242, 1, 7, // 7750: case 0xf2: { |
| 13985 | OPC_CheckPredicate, 36, // 7753: check predicate 36 |
| 13986 | OPC_Decode, 154, 23, 246, 1, // 7755: decode to VMLAhd using decoder 246 |
| 13987 | // 7755: } |
| 13988 | 243, 1, 0, // 7760: case 0xf3: { |
| 13989 | OPC_CheckPredicate, 36, // 7763: check predicate 36 |
| 13990 | OPC_Decode, 144, 24, 238, 1, // 7765: decode to VMULhd using decoder 238 |
| 13991 | // 7765: } |
| 13992 | // 7765: } // switch Inst[31:24] |
| 13993 | // 7765: } |
| 13994 | 2, 12, // 7770: case 0x2: { |
| 13995 | OPC_CheckPredicate, 35, // 7772: check predicate 35 |
| 13996 | OPC_CheckField, 24, 8, 242, 1, // 7774: check Inst[31:24] == 0xf2 |
| 13997 | OPC_Decode, 183, 23, 246, 1, // 7779: decode to VMLSfd using decoder 246 |
| 13998 | // 7779: } |
| 13999 | 3, 0, // 7784: case 0x3: { |
| 14000 | OPC_CheckPredicate, 36, // 7786: check predicate 36 |
| 14001 | OPC_CheckField, 24, 8, 242, 1, // 7788: check Inst[31:24] == 0xf2 |
| 14002 | OPC_Decode, 185, 23, 246, 1, // 7793: decode to VMLShd using decoder 246 |
| 14003 | // 7793: } |
| 14004 | // 7793: } // switch Inst[21:20] |
| 14005 | // 7793: } |
| 14006 | 14, 59, // 7798: case 0xe: { |
| 14007 | OPC_SwitchField, 20, 2, // 7800: switch Inst[21:20] { |
| 14008 | 0, 12, // 7803: case 0x0: { |
| 14009 | OPC_CheckPredicate, 35, // 7805: check predicate 35 |
| 14010 | OPC_CheckField, 24, 8, 243, 1, // 7807: check Inst[31:24] == 0xf3 |
| 14011 | OPC_Decode, 234, 16, 238, 1, // 7812: decode to VACGEfd using decoder 238 |
| 14012 | // 7812: } |
| 14013 | 1, 12, // 7817: case 0x1: { |
| 14014 | OPC_CheckPredicate, 36, // 7819: check predicate 36 |
| 14015 | OPC_CheckField, 24, 8, 243, 1, // 7821: check Inst[31:24] == 0xf3 |
| 14016 | OPC_Decode, 236, 16, 238, 1, // 7826: decode to VACGEhd using decoder 238 |
| 14017 | // 7826: } |
| 14018 | 2, 12, // 7831: case 0x2: { |
| 14019 | OPC_CheckPredicate, 35, // 7833: check predicate 35 |
| 14020 | OPC_CheckField, 24, 8, 243, 1, // 7835: check Inst[31:24] == 0xf3 |
| 14021 | OPC_Decode, 238, 16, 238, 1, // 7840: decode to VACGTfd using decoder 238 |
| 14022 | // 7840: } |
| 14023 | 3, 0, // 7845: case 0x3: { |
| 14024 | OPC_CheckPredicate, 36, // 7847: check predicate 36 |
| 14025 | OPC_CheckField, 24, 8, 243, 1, // 7849: check Inst[31:24] == 0xf3 |
| 14026 | OPC_Decode, 240, 16, 238, 1, // 7854: decode to VACGThd using decoder 238 |
| 14027 | // 7854: } |
| 14028 | // 7854: } // switch Inst[21:20] |
| 14029 | // 7854: } |
| 14030 | 15, 0, // 7859: case 0xf: { |
| 14031 | OPC_SwitchField, 20, 2, // 7861: switch Inst[21:20] { |
| 14032 | 0, 12, // 7864: case 0x0: { |
| 14033 | OPC_CheckPredicate, 35, // 7866: check predicate 35 |
| 14034 | OPC_CheckField, 24, 8, 242, 1, // 7868: check Inst[31:24] == 0xf2 |
| 14035 | OPC_Decode, 167, 26, 238, 1, // 7873: decode to VRECPSfd using decoder 238 |
| 14036 | // 7873: } |
| 14037 | 1, 12, // 7878: case 0x1: { |
| 14038 | OPC_CheckPredicate, 36, // 7880: check predicate 36 |
| 14039 | OPC_CheckField, 24, 8, 242, 1, // 7882: check Inst[31:24] == 0xf2 |
| 14040 | OPC_Decode, 169, 26, 238, 1, // 7887: decode to VRECPShd using decoder 238 |
| 14041 | // 7887: } |
| 14042 | 2, 12, // 7892: case 0x2: { |
| 14043 | OPC_CheckPredicate, 35, // 7894: check predicate 35 |
| 14044 | OPC_CheckField, 24, 8, 242, 1, // 7896: check Inst[31:24] == 0xf2 |
| 14045 | OPC_Decode, 153, 27, 238, 1, // 7901: decode to VRSQRTSfd using decoder 238 |
| 14046 | // 7901: } |
| 14047 | 3, 0, // 7906: case 0x3: { |
| 14048 | OPC_CheckPredicate, 36, // 7908: check predicate 36 |
| 14049 | OPC_CheckField, 24, 8, 242, 1, // 7910: check Inst[31:24] == 0xf2 |
| 14050 | OPC_Decode, 155, 27, 238, 1, // 7915: decode to VRSQRTShd using decoder 238 |
| 14051 | // 7915: } |
| 14052 | // 7915: } // switch Inst[21:20] |
| 14053 | // 7915: } |
| 14054 | // 7915: } // switch Inst[11:8] |
| 14055 | // 7915: } |
| 14056 | 1, 0, // 7920: case 0x1: { |
| 14057 | OPC_SwitchField, 7, 1, // 7922: switch Inst[7] { |
| 14058 | 0, 213, 9, // 7925: case 0x0: { |
| 14059 | OPC_CheckField, 25, 7, 121, // 7928: check Inst[31:25] == 0x79 |
| 14060 | OPC_Scope, 215, 8, // 7932: try { |
| 14061 | OPC_SwitchField, 8, 4, // 7935: switch Inst[11:8] { |
| 14062 | 0, 85, // 7938: case 0x0: { |
| 14063 | OPC_SwitchField, 21, 1, // 7940: switch Inst[21] { |
| 14064 | 0, 57, // 7943: case 0x0: { |
| 14065 | OPC_SwitchField, 20, 1, // 7945: switch Inst[20] { |
| 14066 | 0, 29, // 7948: case 0x0: { |
| 14067 | OPC_SwitchField, 24, 1, // 7950: switch Inst[24] { |
| 14068 | 0, 11, // 7953: case 0x0: { |
| 14069 | OPC_CheckPredicate, 35, // 7955: check predicate 35 |
| 14070 | OPC_CheckField, 19, 1, 1, // 7957: check Inst[19] == 0x1 |
| 14071 | OPC_Decode, 240, 27, 156, 2, // 7961: decode to VSHRsv8i8 using decoder 284 |
| 14072 | // 7961: } |
| 14073 | 1, 0, // 7966: case 0x1: { |
| 14074 | OPC_CheckPredicate, 35, // 7968: check predicate 35 |
| 14075 | OPC_CheckField, 19, 1, 1, // 7970: check Inst[19] == 0x1 |
| 14076 | OPC_Decode, 248, 27, 156, 2, // 7974: decode to VSHRuv8i8 using decoder 284 |
| 14077 | // 7974: } |
| 14078 | // 7974: } // switch Inst[24] |
| 14079 | // 7974: } |
| 14080 | 1, 0, // 7979: case 0x1: { |
| 14081 | OPC_SwitchField, 24, 1, // 7981: switch Inst[24] { |
| 14082 | 0, 7, // 7984: case 0x0: { |
| 14083 | OPC_CheckPredicate, 35, // 7986: check predicate 35 |
| 14084 | OPC_Decode, 237, 27, 157, 2, // 7988: decode to VSHRsv4i16 using decoder 285 |
| 14085 | // 7988: } |
| 14086 | 1, 0, // 7993: case 0x1: { |
| 14087 | OPC_CheckPredicate, 35, // 7995: check predicate 35 |
| 14088 | OPC_Decode, 245, 27, 157, 2, // 7997: decode to VSHRuv4i16 using decoder 285 |
| 14089 | // 7997: } |
| 14090 | // 7997: } // switch Inst[24] |
| 14091 | // 7997: } |
| 14092 | // 7997: } // switch Inst[20] |
| 14093 | // 7997: } |
| 14094 | 1, 0, // 8002: case 0x1: { |
| 14095 | OPC_SwitchField, 24, 1, // 8004: switch Inst[24] { |
| 14096 | 0, 7, // 8007: case 0x0: { |
| 14097 | OPC_CheckPredicate, 35, // 8009: check predicate 35 |
| 14098 | OPC_Decode, 235, 27, 158, 2, // 8011: decode to VSHRsv2i32 using decoder 286 |
| 14099 | // 8011: } |
| 14100 | 1, 0, // 8016: case 0x1: { |
| 14101 | OPC_CheckPredicate, 35, // 8018: check predicate 35 |
| 14102 | OPC_Decode, 243, 27, 158, 2, // 8020: decode to VSHRuv2i32 using decoder 286 |
| 14103 | // 8020: } |
| 14104 | // 8020: } // switch Inst[24] |
| 14105 | // 8020: } |
| 14106 | // 8020: } // switch Inst[21] |
| 14107 | // 8020: } |
| 14108 | 1, 85, // 8025: case 0x1: { |
| 14109 | OPC_SwitchField, 21, 1, // 8027: switch Inst[21] { |
| 14110 | 0, 57, // 8030: case 0x0: { |
| 14111 | OPC_SwitchField, 20, 1, // 8032: switch Inst[20] { |
| 14112 | 0, 29, // 8035: case 0x0: { |
| 14113 | OPC_SwitchField, 24, 1, // 8037: switch Inst[24] { |
| 14114 | 0, 11, // 8040: case 0x0: { |
| 14115 | OPC_CheckPredicate, 35, // 8042: check predicate 35 |
| 14116 | OPC_CheckField, 19, 1, 1, // 8044: check Inst[19] == 0x1 |
| 14117 | OPC_Decode, 149, 28, 159, 2, // 8048: decode to VSRAsv8i8 using decoder 287 |
| 14118 | // 8048: } |
| 14119 | 1, 0, // 8053: case 0x1: { |
| 14120 | OPC_CheckPredicate, 35, // 8055: check predicate 35 |
| 14121 | OPC_CheckField, 19, 1, 1, // 8057: check Inst[19] == 0x1 |
| 14122 | OPC_Decode, 157, 28, 159, 2, // 8061: decode to VSRAuv8i8 using decoder 287 |
| 14123 | // 8061: } |
| 14124 | // 8061: } // switch Inst[24] |
| 14125 | // 8061: } |
| 14126 | 1, 0, // 8066: case 0x1: { |
| 14127 | OPC_SwitchField, 24, 1, // 8068: switch Inst[24] { |
| 14128 | 0, 7, // 8071: case 0x0: { |
| 14129 | OPC_CheckPredicate, 35, // 8073: check predicate 35 |
| 14130 | OPC_Decode, 146, 28, 160, 2, // 8075: decode to VSRAsv4i16 using decoder 288 |
| 14131 | // 8075: } |
| 14132 | 1, 0, // 8080: case 0x1: { |
| 14133 | OPC_CheckPredicate, 35, // 8082: check predicate 35 |
| 14134 | OPC_Decode, 154, 28, 160, 2, // 8084: decode to VSRAuv4i16 using decoder 288 |
| 14135 | // 8084: } |
| 14136 | // 8084: } // switch Inst[24] |
| 14137 | // 8084: } |
| 14138 | // 8084: } // switch Inst[20] |
| 14139 | // 8084: } |
| 14140 | 1, 0, // 8089: case 0x1: { |
| 14141 | OPC_SwitchField, 24, 1, // 8091: switch Inst[24] { |
| 14142 | 0, 7, // 8094: case 0x0: { |
| 14143 | OPC_CheckPredicate, 35, // 8096: check predicate 35 |
| 14144 | OPC_Decode, 144, 28, 161, 2, // 8098: decode to VSRAsv2i32 using decoder 289 |
| 14145 | // 8098: } |
| 14146 | 1, 0, // 8103: case 0x1: { |
| 14147 | OPC_CheckPredicate, 35, // 8105: check predicate 35 |
| 14148 | OPC_Decode, 152, 28, 161, 2, // 8107: decode to VSRAuv2i32 using decoder 289 |
| 14149 | // 8107: } |
| 14150 | // 8107: } // switch Inst[24] |
| 14151 | // 8107: } |
| 14152 | // 8107: } // switch Inst[21] |
| 14153 | // 8107: } |
| 14154 | 2, 85, // 8112: case 0x2: { |
| 14155 | OPC_SwitchField, 21, 1, // 8114: switch Inst[21] { |
| 14156 | 0, 57, // 8117: case 0x0: { |
| 14157 | OPC_SwitchField, 20, 1, // 8119: switch Inst[20] { |
| 14158 | 0, 29, // 8122: case 0x0: { |
| 14159 | OPC_SwitchField, 24, 1, // 8124: switch Inst[24] { |
| 14160 | 0, 11, // 8127: case 0x0: { |
| 14161 | OPC_CheckPredicate, 35, // 8129: check predicate 35 |
| 14162 | OPC_CheckField, 19, 1, 1, // 8131: check Inst[19] == 0x1 |
| 14163 | OPC_Decode, 138, 27, 156, 2, // 8135: decode to VRSHRsv8i8 using decoder 284 |
| 14164 | // 8135: } |
| 14165 | 1, 0, // 8140: case 0x1: { |
| 14166 | OPC_CheckPredicate, 35, // 8142: check predicate 35 |
| 14167 | OPC_CheckField, 19, 1, 1, // 8144: check Inst[19] == 0x1 |
| 14168 | OPC_Decode, 146, 27, 156, 2, // 8148: decode to VRSHRuv8i8 using decoder 284 |
| 14169 | // 8148: } |
| 14170 | // 8148: } // switch Inst[24] |
| 14171 | // 8148: } |
| 14172 | 1, 0, // 8153: case 0x1: { |
| 14173 | OPC_SwitchField, 24, 1, // 8155: switch Inst[24] { |
| 14174 | 0, 7, // 8158: case 0x0: { |
| 14175 | OPC_CheckPredicate, 35, // 8160: check predicate 35 |
| 14176 | OPC_Decode, 135, 27, 157, 2, // 8162: decode to VRSHRsv4i16 using decoder 285 |
| 14177 | // 8162: } |
| 14178 | 1, 0, // 8167: case 0x1: { |
| 14179 | OPC_CheckPredicate, 35, // 8169: check predicate 35 |
| 14180 | OPC_Decode, 143, 27, 157, 2, // 8171: decode to VRSHRuv4i16 using decoder 285 |
| 14181 | // 8171: } |
| 14182 | // 8171: } // switch Inst[24] |
| 14183 | // 8171: } |
| 14184 | // 8171: } // switch Inst[20] |
| 14185 | // 8171: } |
| 14186 | 1, 0, // 8176: case 0x1: { |
| 14187 | OPC_SwitchField, 24, 1, // 8178: switch Inst[24] { |
| 14188 | 0, 7, // 8181: case 0x0: { |
| 14189 | OPC_CheckPredicate, 35, // 8183: check predicate 35 |
| 14190 | OPC_Decode, 133, 27, 158, 2, // 8185: decode to VRSHRsv2i32 using decoder 286 |
| 14191 | // 8185: } |
| 14192 | 1, 0, // 8190: case 0x1: { |
| 14193 | OPC_CheckPredicate, 35, // 8192: check predicate 35 |
| 14194 | OPC_Decode, 141, 27, 158, 2, // 8194: decode to VRSHRuv2i32 using decoder 286 |
| 14195 | // 8194: } |
| 14196 | // 8194: } // switch Inst[24] |
| 14197 | // 8194: } |
| 14198 | // 8194: } // switch Inst[21] |
| 14199 | // 8194: } |
| 14200 | 3, 85, // 8199: case 0x3: { |
| 14201 | OPC_SwitchField, 21, 1, // 8201: switch Inst[21] { |
| 14202 | 0, 57, // 8204: case 0x0: { |
| 14203 | OPC_SwitchField, 20, 1, // 8206: switch Inst[20] { |
| 14204 | 0, 29, // 8209: case 0x0: { |
| 14205 | OPC_SwitchField, 24, 1, // 8211: switch Inst[24] { |
| 14206 | 0, 11, // 8214: case 0x0: { |
| 14207 | OPC_CheckPredicate, 35, // 8216: check predicate 35 |
| 14208 | OPC_CheckField, 19, 1, 1, // 8218: check Inst[19] == 0x1 |
| 14209 | OPC_Decode, 164, 27, 159, 2, // 8222: decode to VRSRAsv8i8 using decoder 287 |
| 14210 | // 8222: } |
| 14211 | 1, 0, // 8227: case 0x1: { |
| 14212 | OPC_CheckPredicate, 35, // 8229: check predicate 35 |
| 14213 | OPC_CheckField, 19, 1, 1, // 8231: check Inst[19] == 0x1 |
| 14214 | OPC_Decode, 172, 27, 159, 2, // 8235: decode to VRSRAuv8i8 using decoder 287 |
| 14215 | // 8235: } |
| 14216 | // 8235: } // switch Inst[24] |
| 14217 | // 8235: } |
| 14218 | 1, 0, // 8240: case 0x1: { |
| 14219 | OPC_SwitchField, 24, 1, // 8242: switch Inst[24] { |
| 14220 | 0, 7, // 8245: case 0x0: { |
| 14221 | OPC_CheckPredicate, 35, // 8247: check predicate 35 |
| 14222 | OPC_Decode, 161, 27, 160, 2, // 8249: decode to VRSRAsv4i16 using decoder 288 |
| 14223 | // 8249: } |
| 14224 | 1, 0, // 8254: case 0x1: { |
| 14225 | OPC_CheckPredicate, 35, // 8256: check predicate 35 |
| 14226 | OPC_Decode, 169, 27, 160, 2, // 8258: decode to VRSRAuv4i16 using decoder 288 |
| 14227 | // 8258: } |
| 14228 | // 8258: } // switch Inst[24] |
| 14229 | // 8258: } |
| 14230 | // 8258: } // switch Inst[20] |
| 14231 | // 8258: } |
| 14232 | 1, 0, // 8263: case 0x1: { |
| 14233 | OPC_SwitchField, 24, 1, // 8265: switch Inst[24] { |
| 14234 | 0, 7, // 8268: case 0x0: { |
| 14235 | OPC_CheckPredicate, 35, // 8270: check predicate 35 |
| 14236 | OPC_Decode, 159, 27, 161, 2, // 8272: decode to VRSRAsv2i32 using decoder 289 |
| 14237 | // 8272: } |
| 14238 | 1, 0, // 8277: case 0x1: { |
| 14239 | OPC_CheckPredicate, 35, // 8279: check predicate 35 |
| 14240 | OPC_Decode, 167, 27, 161, 2, // 8281: decode to VRSRAuv2i32 using decoder 289 |
| 14241 | // 8281: } |
| 14242 | // 8281: } // switch Inst[24] |
| 14243 | // 8281: } |
| 14244 | // 8281: } // switch Inst[21] |
| 14245 | // 8281: } |
| 14246 | 4, 51, // 8286: case 0x4: { |
| 14247 | OPC_SwitchField, 21, 1, // 8288: switch Inst[21] { |
| 14248 | 0, 33, // 8291: case 0x0: { |
| 14249 | OPC_SwitchField, 20, 1, // 8293: switch Inst[20] { |
| 14250 | 0, 15, // 8296: case 0x0: { |
| 14251 | OPC_CheckPredicate, 35, // 8298: check predicate 35 |
| 14252 | OPC_CheckField, 24, 1, 1, // 8300: check Inst[24] == 0x1 |
| 14253 | OPC_CheckField, 19, 1, 1, // 8304: check Inst[19] == 0x1 |
| 14254 | OPC_Decode, 165, 28, 159, 2, // 8308: decode to VSRIv8i8 using decoder 287 |
| 14255 | // 8308: } |
| 14256 | 1, 0, // 8313: case 0x1: { |
| 14257 | OPC_CheckPredicate, 35, // 8315: check predicate 35 |
| 14258 | OPC_CheckField, 24, 1, 1, // 8317: check Inst[24] == 0x1 |
| 14259 | OPC_Decode, 162, 28, 160, 2, // 8321: decode to VSRIv4i16 using decoder 288 |
| 14260 | // 8321: } |
| 14261 | // 8321: } // switch Inst[20] |
| 14262 | // 8321: } |
| 14263 | 1, 0, // 8326: case 0x1: { |
| 14264 | OPC_CheckPredicate, 35, // 8328: check predicate 35 |
| 14265 | OPC_CheckField, 24, 1, 1, // 8330: check Inst[24] == 0x1 |
| 14266 | OPC_Decode, 160, 28, 161, 2, // 8334: decode to VSRIv2i32 using decoder 289 |
| 14267 | // 8334: } |
| 14268 | // 8334: } // switch Inst[21] |
| 14269 | // 8334: } |
| 14270 | 5, 85, // 8339: case 0x5: { |
| 14271 | OPC_SwitchField, 21, 1, // 8341: switch Inst[21] { |
| 14272 | 0, 57, // 8344: case 0x0: { |
| 14273 | OPC_SwitchField, 20, 1, // 8346: switch Inst[20] { |
| 14274 | 0, 29, // 8349: case 0x0: { |
| 14275 | OPC_SwitchField, 24, 1, // 8351: switch Inst[24] { |
| 14276 | 0, 11, // 8354: case 0x0: { |
| 14277 | OPC_CheckPredicate, 35, // 8356: check predicate 35 |
| 14278 | OPC_CheckField, 19, 1, 1, // 8358: check Inst[19] == 0x1 |
| 14279 | OPC_Decode, 213, 27, 162, 2, // 8362: decode to VSHLiv8i8 using decoder 290 |
| 14280 | // 8362: } |
| 14281 | 1, 0, // 8367: case 0x1: { |
| 14282 | OPC_CheckPredicate, 35, // 8369: check predicate 35 |
| 14283 | OPC_CheckField, 19, 1, 1, // 8371: check Inst[19] == 0x1 |
| 14284 | OPC_Decode, 134, 28, 163, 2, // 8375: decode to VSLIv8i8 using decoder 291 |
| 14285 | // 8375: } |
| 14286 | // 8375: } // switch Inst[24] |
| 14287 | // 8375: } |
| 14288 | 1, 0, // 8380: case 0x1: { |
| 14289 | OPC_SwitchField, 24, 1, // 8382: switch Inst[24] { |
| 14290 | 0, 7, // 8385: case 0x0: { |
| 14291 | OPC_CheckPredicate, 35, // 8387: check predicate 35 |
| 14292 | OPC_Decode, 210, 27, 164, 2, // 8389: decode to VSHLiv4i16 using decoder 292 |
| 14293 | // 8389: } |
| 14294 | 1, 0, // 8394: case 0x1: { |
| 14295 | OPC_CheckPredicate, 35, // 8396: check predicate 35 |
| 14296 | OPC_Decode, 131, 28, 165, 2, // 8398: decode to VSLIv4i16 using decoder 293 |
| 14297 | // 8398: } |
| 14298 | // 8398: } // switch Inst[24] |
| 14299 | // 8398: } |
| 14300 | // 8398: } // switch Inst[20] |
| 14301 | // 8398: } |
| 14302 | 1, 0, // 8403: case 0x1: { |
| 14303 | OPC_SwitchField, 24, 1, // 8405: switch Inst[24] { |
| 14304 | 0, 7, // 8408: case 0x0: { |
| 14305 | OPC_CheckPredicate, 35, // 8410: check predicate 35 |
| 14306 | OPC_Decode, 208, 27, 166, 2, // 8412: decode to VSHLiv2i32 using decoder 294 |
| 14307 | // 8412: } |
| 14308 | 1, 0, // 8417: case 0x1: { |
| 14309 | OPC_CheckPredicate, 35, // 8419: check predicate 35 |
| 14310 | OPC_Decode, 129, 28, 167, 2, // 8421: decode to VSLIv2i32 using decoder 295 |
| 14311 | // 8421: } |
| 14312 | // 8421: } // switch Inst[24] |
| 14313 | // 8421: } |
| 14314 | // 8421: } // switch Inst[21] |
| 14315 | // 8421: } |
| 14316 | 6, 51, // 8426: case 0x6: { |
| 14317 | OPC_SwitchField, 21, 1, // 8428: switch Inst[21] { |
| 14318 | 0, 33, // 8431: case 0x0: { |
| 14319 | OPC_SwitchField, 20, 1, // 8433: switch Inst[20] { |
| 14320 | 0, 15, // 8436: case 0x0: { |
| 14321 | OPC_CheckPredicate, 35, // 8438: check predicate 35 |
| 14322 | OPC_CheckField, 24, 1, 1, // 8440: check Inst[24] == 0x1 |
| 14323 | OPC_CheckField, 19, 1, 1, // 8444: check Inst[19] == 0x1 |
| 14324 | OPC_Decode, 236, 25, 162, 2, // 8448: decode to VQSHLsuv8i8 using decoder 290 |
| 14325 | // 8448: } |
| 14326 | 1, 0, // 8453: case 0x1: { |
| 14327 | OPC_CheckPredicate, 35, // 8455: check predicate 35 |
| 14328 | OPC_CheckField, 24, 1, 1, // 8457: check Inst[24] == 0x1 |
| 14329 | OPC_Decode, 233, 25, 164, 2, // 8461: decode to VQSHLsuv4i16 using decoder 292 |
| 14330 | // 8461: } |
| 14331 | // 8461: } // switch Inst[20] |
| 14332 | // 8461: } |
| 14333 | 1, 0, // 8466: case 0x1: { |
| 14334 | OPC_CheckPredicate, 35, // 8468: check predicate 35 |
| 14335 | OPC_CheckField, 24, 1, 1, // 8470: check Inst[24] == 0x1 |
| 14336 | OPC_Decode, 231, 25, 166, 2, // 8474: decode to VQSHLsuv2i32 using decoder 294 |
| 14337 | // 8474: } |
| 14338 | // 8474: } // switch Inst[21] |
| 14339 | // 8474: } |
| 14340 | 7, 85, // 8479: case 0x7: { |
| 14341 | OPC_SwitchField, 21, 1, // 8481: switch Inst[21] { |
| 14342 | 0, 57, // 8484: case 0x0: { |
| 14343 | OPC_SwitchField, 20, 1, // 8486: switch Inst[20] { |
| 14344 | 0, 29, // 8489: case 0x0: { |
| 14345 | OPC_SwitchField, 24, 1, // 8491: switch Inst[24] { |
| 14346 | 0, 11, // 8494: case 0x0: { |
| 14347 | OPC_CheckPredicate, 35, // 8496: check predicate 35 |
| 14348 | OPC_CheckField, 19, 1, 1, // 8498: check Inst[19] == 0x1 |
| 14349 | OPC_Decode, 228, 25, 162, 2, // 8502: decode to VQSHLsiv8i8 using decoder 290 |
| 14350 | // 8502: } |
| 14351 | 1, 0, // 8507: case 0x1: { |
| 14352 | OPC_CheckPredicate, 35, // 8509: check predicate 35 |
| 14353 | OPC_CheckField, 19, 1, 1, // 8511: check Inst[19] == 0x1 |
| 14354 | OPC_Decode, 252, 25, 162, 2, // 8515: decode to VQSHLuiv8i8 using decoder 290 |
| 14355 | // 8515: } |
| 14356 | // 8515: } // switch Inst[24] |
| 14357 | // 8515: } |
| 14358 | 1, 0, // 8520: case 0x1: { |
| 14359 | OPC_SwitchField, 24, 1, // 8522: switch Inst[24] { |
| 14360 | 0, 7, // 8525: case 0x0: { |
| 14361 | OPC_CheckPredicate, 35, // 8527: check predicate 35 |
| 14362 | OPC_Decode, 225, 25, 164, 2, // 8529: decode to VQSHLsiv4i16 using decoder 292 |
| 14363 | // 8529: } |
| 14364 | 1, 0, // 8534: case 0x1: { |
| 14365 | OPC_CheckPredicate, 35, // 8536: check predicate 35 |
| 14366 | OPC_Decode, 249, 25, 164, 2, // 8538: decode to VQSHLuiv4i16 using decoder 292 |
| 14367 | // 8538: } |
| 14368 | // 8538: } // switch Inst[24] |
| 14369 | // 8538: } |
| 14370 | // 8538: } // switch Inst[20] |
| 14371 | // 8538: } |
| 14372 | 1, 0, // 8543: case 0x1: { |
| 14373 | OPC_SwitchField, 24, 1, // 8545: switch Inst[24] { |
| 14374 | 0, 7, // 8548: case 0x0: { |
| 14375 | OPC_CheckPredicate, 35, // 8550: check predicate 35 |
| 14376 | OPC_Decode, 223, 25, 166, 2, // 8552: decode to VQSHLsiv2i32 using decoder 294 |
| 14377 | // 8552: } |
| 14378 | 1, 0, // 8557: case 0x1: { |
| 14379 | OPC_CheckPredicate, 35, // 8559: check predicate 35 |
| 14380 | OPC_Decode, 247, 25, 166, 2, // 8561: decode to VQSHLuiv2i32 using decoder 294 |
| 14381 | // 8561: } |
| 14382 | // 8561: } // switch Inst[24] |
| 14383 | // 8561: } |
| 14384 | // 8561: } // switch Inst[21] |
| 14385 | // 8561: } |
| 14386 | 8, 85, // 8566: case 0x8: { |
| 14387 | OPC_SwitchField, 21, 1, // 8568: switch Inst[21] { |
| 14388 | 0, 57, // 8571: case 0x0: { |
| 14389 | OPC_SwitchField, 20, 1, // 8573: switch Inst[20] { |
| 14390 | 0, 29, // 8576: case 0x0: { |
| 14391 | OPC_SwitchField, 24, 1, // 8578: switch Inst[24] { |
| 14392 | 0, 11, // 8581: case 0x0: { |
| 14393 | OPC_CheckPredicate, 35, // 8583: check predicate 35 |
| 14394 | OPC_CheckField, 19, 1, 1, // 8585: check Inst[19] == 0x1 |
| 14395 | OPC_Decode, 232, 27, 168, 2, // 8589: decode to VSHRNv8i8 using decoder 296 |
| 14396 | // 8589: } |
| 14397 | 1, 0, // 8594: case 0x1: { |
| 14398 | OPC_CheckPredicate, 35, // 8596: check predicate 35 |
| 14399 | OPC_CheckField, 19, 1, 1, // 8598: check Inst[19] == 0x1 |
| 14400 | OPC_Decode, 141, 26, 168, 2, // 8602: decode to VQSHRUNv8i8 using decoder 296 |
| 14401 | // 8602: } |
| 14402 | // 8602: } // switch Inst[24] |
| 14403 | // 8602: } |
| 14404 | 1, 0, // 8607: case 0x1: { |
| 14405 | OPC_SwitchField, 24, 1, // 8609: switch Inst[24] { |
| 14406 | 0, 7, // 8612: case 0x0: { |
| 14407 | OPC_CheckPredicate, 35, // 8614: check predicate 35 |
| 14408 | OPC_Decode, 231, 27, 169, 2, // 8616: decode to VSHRNv4i16 using decoder 297 |
| 14409 | // 8616: } |
| 14410 | 1, 0, // 8621: case 0x1: { |
| 14411 | OPC_CheckPredicate, 35, // 8623: check predicate 35 |
| 14412 | OPC_Decode, 140, 26, 169, 2, // 8625: decode to VQSHRUNv4i16 using decoder 297 |
| 14413 | // 8625: } |
| 14414 | // 8625: } // switch Inst[24] |
| 14415 | // 8625: } |
| 14416 | // 8625: } // switch Inst[20] |
| 14417 | // 8625: } |
| 14418 | 1, 0, // 8630: case 0x1: { |
| 14419 | OPC_SwitchField, 24, 1, // 8632: switch Inst[24] { |
| 14420 | 0, 7, // 8635: case 0x0: { |
| 14421 | OPC_CheckPredicate, 35, // 8637: check predicate 35 |
| 14422 | OPC_Decode, 230, 27, 170, 2, // 8639: decode to VSHRNv2i32 using decoder 298 |
| 14423 | // 8639: } |
| 14424 | 1, 0, // 8644: case 0x1: { |
| 14425 | OPC_CheckPredicate, 35, // 8646: check predicate 35 |
| 14426 | OPC_Decode, 139, 26, 170, 2, // 8648: decode to VQSHRUNv2i32 using decoder 298 |
| 14427 | // 8648: } |
| 14428 | // 8648: } // switch Inst[24] |
| 14429 | // 8648: } |
| 14430 | // 8648: } // switch Inst[21] |
| 14431 | // 8648: } |
| 14432 | 9, 85, // 8653: case 0x9: { |
| 14433 | OPC_SwitchField, 21, 1, // 8655: switch Inst[21] { |
| 14434 | 0, 57, // 8658: case 0x0: { |
| 14435 | OPC_SwitchField, 20, 1, // 8660: switch Inst[20] { |
| 14436 | 0, 29, // 8663: case 0x0: { |
| 14437 | OPC_SwitchField, 24, 1, // 8665: switch Inst[24] { |
| 14438 | 0, 11, // 8668: case 0x0: { |
| 14439 | OPC_CheckPredicate, 35, // 8670: check predicate 35 |
| 14440 | OPC_CheckField, 19, 1, 1, // 8672: check Inst[19] == 0x1 |
| 14441 | OPC_Decode, 135, 26, 168, 2, // 8676: decode to VQSHRNsv8i8 using decoder 296 |
| 14442 | // 8676: } |
| 14443 | 1, 0, // 8681: case 0x1: { |
| 14444 | OPC_CheckPredicate, 35, // 8683: check predicate 35 |
| 14445 | OPC_CheckField, 19, 1, 1, // 8685: check Inst[19] == 0x1 |
| 14446 | OPC_Decode, 138, 26, 168, 2, // 8689: decode to VQSHRNuv8i8 using decoder 296 |
| 14447 | // 8689: } |
| 14448 | // 8689: } // switch Inst[24] |
| 14449 | // 8689: } |
| 14450 | 1, 0, // 8694: case 0x1: { |
| 14451 | OPC_SwitchField, 24, 1, // 8696: switch Inst[24] { |
| 14452 | 0, 7, // 8699: case 0x0: { |
| 14453 | OPC_CheckPredicate, 35, // 8701: check predicate 35 |
| 14454 | OPC_Decode, 134, 26, 169, 2, // 8703: decode to VQSHRNsv4i16 using decoder 297 |
| 14455 | // 8703: } |
| 14456 | 1, 0, // 8708: case 0x1: { |
| 14457 | OPC_CheckPredicate, 35, // 8710: check predicate 35 |
| 14458 | OPC_Decode, 137, 26, 169, 2, // 8712: decode to VQSHRNuv4i16 using decoder 297 |
| 14459 | // 8712: } |
| 14460 | // 8712: } // switch Inst[24] |
| 14461 | // 8712: } |
| 14462 | // 8712: } // switch Inst[20] |
| 14463 | // 8712: } |
| 14464 | 1, 0, // 8717: case 0x1: { |
| 14465 | OPC_SwitchField, 24, 1, // 8719: switch Inst[24] { |
| 14466 | 0, 7, // 8722: case 0x0: { |
| 14467 | OPC_CheckPredicate, 35, // 8724: check predicate 35 |
| 14468 | OPC_Decode, 133, 26, 170, 2, // 8726: decode to VQSHRNsv2i32 using decoder 298 |
| 14469 | // 8726: } |
| 14470 | 1, 0, // 8731: case 0x1: { |
| 14471 | OPC_CheckPredicate, 35, // 8733: check predicate 35 |
| 14472 | OPC_Decode, 136, 26, 170, 2, // 8735: decode to VQSHRNuv2i32 using decoder 298 |
| 14473 | // 8735: } |
| 14474 | // 8735: } // switch Inst[24] |
| 14475 | // 8735: } |
| 14476 | // 8735: } // switch Inst[21] |
| 14477 | // 8735: } |
| 14478 | 10, 163, 1, // 8740: case 0xa: { |
| 14479 | OPC_SwitchField, 21, 1, // 8743: switch Inst[21] { |
| 14480 | 0, 109, // 8746: case 0x0: { |
| 14481 | OPC_SwitchField, 20, 1, // 8748: switch Inst[20] { |
| 14482 | 0, 55, // 8751: case 0x0: { |
| 14483 | OPC_SwitchField, 24, 1, // 8753: switch Inst[24] { |
| 14484 | 0, 24, // 8756: case 0x0: { |
| 14485 | OPC_CheckField, 19, 1, 1, // 8758: check Inst[19] == 0x1 |
| 14486 | OPC_Scope, 11, // 8762: try { |
| 14487 | OPC_CheckField, 16, 3, 0, // 8764: check Inst[18:16] == 0x0 |
| 14488 | OPC_CheckPredicate, 35, // 8768: check predicate 35 |
| 14489 | OPC_Decode, 208, 23, 148, 2, // 8770: decode to VMOVLsv8i16 using decoder 276 |
| 14490 | // 8770: } else try { |
| 14491 | OPC_CheckPredicate, 35, // 8775: check predicate 35 |
| 14492 | OPC_Decode, 202, 27, 171, 2, // 8777: decode to VSHLLsv8i16 using decoder 299 |
| 14493 | // 8777: } |
| 14494 | // 8777: } |
| 14495 | 1, 0, // 8782: case 0x1: { |
| 14496 | OPC_CheckField, 19, 1, 1, // 8784: check Inst[19] == 0x1 |
| 14497 | OPC_Scope, 11, // 8788: try { |
| 14498 | OPC_CheckField, 16, 3, 0, // 8790: check Inst[18:16] == 0x0 |
| 14499 | OPC_CheckPredicate, 35, // 8794: check predicate 35 |
| 14500 | OPC_Decode, 211, 23, 148, 2, // 8796: decode to VMOVLuv8i16 using decoder 276 |
| 14501 | // 8796: } else try { |
| 14502 | OPC_CheckPredicate, 35, // 8801: check predicate 35 |
| 14503 | OPC_Decode, 205, 27, 171, 2, // 8803: decode to VSHLLuv8i16 using decoder 299 |
| 14504 | // 8803: } |
| 14505 | // 8803: } |
| 14506 | // 8803: } // switch Inst[24] |
| 14507 | // 8803: } |
| 14508 | 1, 0, // 8808: case 0x1: { |
| 14509 | OPC_SwitchField, 24, 1, // 8810: switch Inst[24] { |
| 14510 | 0, 20, // 8813: case 0x0: { |
| 14511 | OPC_Scope, 11, // 8815: try { |
| 14512 | OPC_CheckField, 16, 4, 0, // 8817: check Inst[19:16] == 0x0 |
| 14513 | OPC_CheckPredicate, 35, // 8821: check predicate 35 |
| 14514 | OPC_Decode, 207, 23, 148, 2, // 8823: decode to VMOVLsv4i32 using decoder 276 |
| 14515 | // 8823: } else try { |
| 14516 | OPC_CheckPredicate, 35, // 8828: check predicate 35 |
| 14517 | OPC_Decode, 201, 27, 172, 2, // 8830: decode to VSHLLsv4i32 using decoder 300 |
| 14518 | // 8830: } |
| 14519 | // 8830: } |
| 14520 | 1, 0, // 8835: case 0x1: { |
| 14521 | OPC_Scope, 11, // 8837: try { |
| 14522 | OPC_CheckField, 16, 4, 0, // 8839: check Inst[19:16] == 0x0 |
| 14523 | OPC_CheckPredicate, 35, // 8843: check predicate 35 |
| 14524 | OPC_Decode, 210, 23, 148, 2, // 8845: decode to VMOVLuv4i32 using decoder 276 |
| 14525 | // 8845: } else try { |
| 14526 | OPC_CheckPredicate, 35, // 8850: check predicate 35 |
| 14527 | OPC_Decode, 204, 27, 172, 2, // 8852: decode to VSHLLuv4i32 using decoder 300 |
| 14528 | // 8852: } |
| 14529 | // 8852: } |
| 14530 | // 8852: } // switch Inst[24] |
| 14531 | // 8852: } |
| 14532 | // 8852: } // switch Inst[20] |
| 14533 | // 8852: } |
| 14534 | 1, 0, // 8857: case 0x1: { |
| 14535 | OPC_SwitchField, 24, 1, // 8859: switch Inst[24] { |
| 14536 | 0, 20, // 8862: case 0x0: { |
| 14537 | OPC_Scope, 11, // 8864: try { |
| 14538 | OPC_CheckField, 16, 5, 0, // 8866: check Inst[20:16] == 0x0 |
| 14539 | OPC_CheckPredicate, 35, // 8870: check predicate 35 |
| 14540 | OPC_Decode, 206, 23, 148, 2, // 8872: decode to VMOVLsv2i64 using decoder 276 |
| 14541 | // 8872: } else try { |
| 14542 | OPC_CheckPredicate, 35, // 8877: check predicate 35 |
| 14543 | OPC_Decode, 200, 27, 173, 2, // 8879: decode to VSHLLsv2i64 using decoder 301 |
| 14544 | // 8879: } |
| 14545 | // 8879: } |
| 14546 | 1, 0, // 8884: case 0x1: { |
| 14547 | OPC_Scope, 11, // 8886: try { |
| 14548 | OPC_CheckField, 16, 5, 0, // 8888: check Inst[20:16] == 0x0 |
| 14549 | OPC_CheckPredicate, 35, // 8892: check predicate 35 |
| 14550 | OPC_Decode, 209, 23, 148, 2, // 8894: decode to VMOVLuv2i64 using decoder 276 |
| 14551 | // 8894: } else try { |
| 14552 | OPC_CheckPredicate, 35, // 8899: check predicate 35 |
| 14553 | OPC_Decode, 203, 27, 173, 2, // 8901: decode to VSHLLuv2i64 using decoder 301 |
| 14554 | // 8901: } |
| 14555 | // 8901: } |
| 14556 | // 8901: } // switch Inst[24] |
| 14557 | // 8901: } |
| 14558 | // 8901: } // switch Inst[21] |
| 14559 | // 8901: } |
| 14560 | 12, 21, // 8906: case 0xc: { |
| 14561 | OPC_SwitchField, 24, 1, // 8908: switch Inst[24] { |
| 14562 | 0, 7, // 8911: case 0x0: { |
| 14563 | OPC_CheckPredicate, 36, // 8913: check predicate 36 |
| 14564 | OPC_Decode, 132, 19, 174, 2, // 8915: decode to VCVTxs2hd using decoder 302 |
| 14565 | // 8915: } |
| 14566 | 1, 0, // 8920: case 0x1: { |
| 14567 | OPC_CheckPredicate, 36, // 8922: check predicate 36 |
| 14568 | OPC_Decode, 136, 19, 174, 2, // 8924: decode to VCVTxu2hd using decoder 302 |
| 14569 | // 8924: } |
| 14570 | // 8924: } // switch Inst[24] |
| 14571 | // 8924: } |
| 14572 | 13, 21, // 8929: case 0xd: { |
| 14573 | OPC_SwitchField, 24, 1, // 8931: switch Inst[24] { |
| 14574 | 0, 7, // 8934: case 0x0: { |
| 14575 | OPC_CheckPredicate, 36, // 8936: check predicate 36 |
| 14576 | OPC_Decode, 246, 18, 174, 2, // 8938: decode to VCVTh2xsd using decoder 302 |
| 14577 | // 8938: } |
| 14578 | 1, 0, // 8943: case 0x1: { |
| 14579 | OPC_CheckPredicate, 36, // 8945: check predicate 36 |
| 14580 | OPC_Decode, 248, 18, 174, 2, // 8947: decode to VCVTh2xud using decoder 302 |
| 14581 | // 8947: } |
| 14582 | // 8947: } // switch Inst[24] |
| 14583 | // 8947: } |
| 14584 | 14, 52, // 8952: case 0xe: { |
| 14585 | OPC_Scope, 29, // 8954: try { |
| 14586 | OPC_SwitchField, 5, 1, // 8956: switch Inst[5] { |
| 14587 | 0, 11, // 8959: case 0x0: { |
| 14588 | OPC_CheckPredicate, 35, // 8961: check predicate 35 |
| 14589 | OPC_CheckField, 19, 3, 0, // 8963: check Inst[21:19] == 0x0 |
| 14590 | OPC_Decode, 231, 23, 175, 2, // 8967: decode to VMOVv8i8 using decoder 303 |
| 14591 | // 8967: } |
| 14592 | 1, 0, // 8972: case 0x1: { |
| 14593 | OPC_CheckPredicate, 35, // 8974: check predicate 35 |
| 14594 | OPC_CheckField, 19, 3, 0, // 8976: check Inst[21:19] == 0x0 |
| 14595 | OPC_Decode, 223, 23, 175, 2, // 8980: decode to VMOVv1i64 using decoder 303 |
| 14596 | // 8980: } |
| 14597 | // 8980: } // switch Inst[5] |
| 14598 | // 8980: } else try { |
| 14599 | OPC_SwitchField, 24, 1, // 8985: switch Inst[24] { |
| 14600 | 0, 7, // 8988: case 0x0: { |
| 14601 | OPC_CheckPredicate, 35, // 8990: check predicate 35 |
| 14602 | OPC_Decode, 130, 19, 174, 2, // 8992: decode to VCVTxs2fd using decoder 302 |
| 14603 | // 8992: } |
| 14604 | 1, 0, // 8997: case 0x1: { |
| 14605 | OPC_CheckPredicate, 35, // 8999: check predicate 35 |
| 14606 | OPC_Decode, 134, 19, 174, 2, // 9001: decode to VCVTxu2fd using decoder 302 |
| 14607 | // 9001: } |
| 14608 | // 9001: } // switch Inst[24] |
| 14609 | // 9001: } |
| 14610 | // 9001: } |
| 14611 | 15, 0, // 9006: case 0xf: { |
| 14612 | OPC_Scope, 21, // 9008: try { |
| 14613 | OPC_SwitchField, 24, 1, // 9010: switch Inst[24] { |
| 14614 | 0, 7, // 9013: case 0x0: { |
| 14615 | OPC_CheckPredicate, 35, // 9015: check predicate 35 |
| 14616 | OPC_Decode, 237, 18, 174, 2, // 9017: decode to VCVTf2xsd using decoder 302 |
| 14617 | // 9017: } |
| 14618 | 1, 0, // 9022: case 0x1: { |
| 14619 | OPC_CheckPredicate, 35, // 9024: check predicate 35 |
| 14620 | OPC_Decode, 239, 18, 174, 2, // 9026: decode to VCVTf2xud using decoder 302 |
| 14621 | // 9026: } |
| 14622 | // 9026: } // switch Inst[24] |
| 14623 | // 9026: } else try { |
| 14624 | OPC_CheckPredicate, 35, // 9031: check predicate 35 |
| 14625 | OPC_CheckField, 19, 3, 0, // 9033: check Inst[21:19] == 0x0 |
| 14626 | OPC_CheckField, 5, 1, 0, // 9037: check Inst[5] == 0x0 |
| 14627 | OPC_Decode, 224, 23, 175, 2, // 9041: decode to VMOVv2f32 using decoder 303 |
| 14628 | // 9041: } |
| 14629 | // 9041: } |
| 14630 | // 9041: } // switch Inst[11:8] |
| 14631 | // 9041: } else try { |
| 14632 | OPC_SwitchField, 5, 1, // 9046: switch Inst[5] { |
| 14633 | 0, 56, // 9049: case 0x0: { |
| 14634 | OPC_CheckField, 19, 3, 0, // 9051: check Inst[21:19] == 0x0 |
| 14635 | OPC_Scope, 43, // 9055: try { |
| 14636 | OPC_SwitchField, 8, 1, // 9057: switch Inst[8] { |
| 14637 | 0, 11, // 9060: case 0x0: { |
| 14638 | OPC_CheckPredicate, 35, // 9062: check predicate 35 |
| 14639 | OPC_CheckField, 10, 2, 2, // 9064: check Inst[11:10] == 0x2 |
| 14640 | OPC_Decode, 228, 23, 175, 2, // 9068: decode to VMOVv4i16 using decoder 303 |
| 14641 | // 9068: } |
| 14642 | 1, 0, // 9073: case 0x1: { |
| 14643 | OPC_SwitchField, 11, 1, // 9075: switch Inst[11] { |
| 14644 | 0, 7, // 9078: case 0x0: { |
| 14645 | OPC_CheckPredicate, 35, // 9080: check predicate 35 |
| 14646 | OPC_Decode, 193, 24, 175, 2, // 9082: decode to VORRiv2i32 using decoder 303 |
| 14647 | // 9082: } |
| 14648 | 1, 0, // 9087: case 0x1: { |
| 14649 | OPC_CheckPredicate, 35, // 9089: check predicate 35 |
| 14650 | OPC_CheckField, 10, 1, 0, // 9091: check Inst[10] == 0x0 |
| 14651 | OPC_Decode, 194, 24, 175, 2, // 9095: decode to VORRiv4i16 using decoder 303 |
| 14652 | // 9095: } |
| 14653 | // 9095: } // switch Inst[11] |
| 14654 | // 9095: } |
| 14655 | // 9095: } // switch Inst[8] |
| 14656 | // 9095: } else try { |
| 14657 | OPC_CheckPredicate, 35, // 9100: check predicate 35 |
| 14658 | OPC_Decode, 225, 23, 175, 2, // 9102: decode to VMOVv2i32 using decoder 303 |
| 14659 | // 9102: } |
| 14660 | // 9102: } |
| 14661 | 1, 0, // 9107: case 0x1: { |
| 14662 | OPC_CheckField, 19, 3, 0, // 9109: check Inst[21:19] == 0x0 |
| 14663 | OPC_Scope, 43, // 9113: try { |
| 14664 | OPC_SwitchField, 8, 1, // 9115: switch Inst[8] { |
| 14665 | 0, 11, // 9118: case 0x0: { |
| 14666 | OPC_CheckPredicate, 35, // 9120: check predicate 35 |
| 14667 | OPC_CheckField, 10, 2, 2, // 9122: check Inst[11:10] == 0x2 |
| 14668 | OPC_Decode, 165, 24, 175, 2, // 9126: decode to VMVNv4i16 using decoder 303 |
| 14669 | // 9126: } |
| 14670 | 1, 0, // 9131: case 0x1: { |
| 14671 | OPC_SwitchField, 11, 1, // 9133: switch Inst[11] { |
| 14672 | 0, 7, // 9136: case 0x0: { |
| 14673 | OPC_CheckPredicate, 35, // 9138: check predicate 35 |
| 14674 | OPC_Decode, 151, 17, 175, 2, // 9140: decode to VBICiv2i32 using decoder 303 |
| 14675 | // 9140: } |
| 14676 | 1, 0, // 9145: case 0x1: { |
| 14677 | OPC_CheckPredicate, 35, // 9147: check predicate 35 |
| 14678 | OPC_CheckField, 10, 1, 0, // 9149: check Inst[10] == 0x0 |
| 14679 | OPC_Decode, 152, 17, 175, 2, // 9153: decode to VBICiv4i16 using decoder 303 |
| 14680 | // 9153: } |
| 14681 | // 9153: } // switch Inst[11] |
| 14682 | // 9153: } |
| 14683 | // 9153: } // switch Inst[8] |
| 14684 | // 9153: } else try { |
| 14685 | OPC_CheckPredicate, 35, // 9158: check predicate 35 |
| 14686 | OPC_Decode, 164, 24, 175, 2, // 9160: decode to VMVNv2i32 using decoder 303 |
| 14687 | // 9160: } |
| 14688 | // 9160: } |
| 14689 | // 9160: } // switch Inst[5] |
| 14690 | // 9160: } |
| 14691 | // 9160: } |
| 14692 | 1, 0, // 9165: case 0x1: { |
| 14693 | OPC_SwitchField, 8, 4, // 9167: switch Inst[11:8] { |
| 14694 | 0, 23, // 9170: case 0x0: { |
| 14695 | OPC_SwitchField, 24, 8, // 9172: switch Inst[31:24] { |
| 14696 | 242, 1, 7, // 9175: case 0xf2: { |
| 14697 | OPC_CheckPredicate, 35, // 9178: check predicate 35 |
| 14698 | OPC_Decode, 234, 27, 176, 2, // 9180: decode to VSHRsv1i64 using decoder 304 |
| 14699 | // 9180: } |
| 14700 | 243, 1, 0, // 9185: case 0xf3: { |
| 14701 | OPC_CheckPredicate, 35, // 9188: check predicate 35 |
| 14702 | OPC_Decode, 242, 27, 176, 2, // 9190: decode to VSHRuv1i64 using decoder 304 |
| 14703 | // 9190: } |
| 14704 | // 9190: } // switch Inst[31:24] |
| 14705 | // 9190: } |
| 14706 | 1, 23, // 9195: case 0x1: { |
| 14707 | OPC_SwitchField, 24, 8, // 9197: switch Inst[31:24] { |
| 14708 | 242, 1, 7, // 9200: case 0xf2: { |
| 14709 | OPC_CheckPredicate, 35, // 9203: check predicate 35 |
| 14710 | OPC_Decode, 143, 28, 177, 2, // 9205: decode to VSRAsv1i64 using decoder 305 |
| 14711 | // 9205: } |
| 14712 | 243, 1, 0, // 9210: case 0xf3: { |
| 14713 | OPC_CheckPredicate, 35, // 9213: check predicate 35 |
| 14714 | OPC_Decode, 151, 28, 177, 2, // 9215: decode to VSRAuv1i64 using decoder 305 |
| 14715 | // 9215: } |
| 14716 | // 9215: } // switch Inst[31:24] |
| 14717 | // 9215: } |
| 14718 | 2, 23, // 9220: case 0x2: { |
| 14719 | OPC_SwitchField, 24, 8, // 9222: switch Inst[31:24] { |
| 14720 | 242, 1, 7, // 9225: case 0xf2: { |
| 14721 | OPC_CheckPredicate, 35, // 9228: check predicate 35 |
| 14722 | OPC_Decode, 132, 27, 176, 2, // 9230: decode to VRSHRsv1i64 using decoder 304 |
| 14723 | // 9230: } |
| 14724 | 243, 1, 0, // 9235: case 0xf3: { |
| 14725 | OPC_CheckPredicate, 35, // 9238: check predicate 35 |
| 14726 | OPC_Decode, 140, 27, 176, 2, // 9240: decode to VRSHRuv1i64 using decoder 304 |
| 14727 | // 9240: } |
| 14728 | // 9240: } // switch Inst[31:24] |
| 14729 | // 9240: } |
| 14730 | 3, 23, // 9245: case 0x3: { |
| 14731 | OPC_SwitchField, 24, 8, // 9247: switch Inst[31:24] { |
| 14732 | 242, 1, 7, // 9250: case 0xf2: { |
| 14733 | OPC_CheckPredicate, 35, // 9253: check predicate 35 |
| 14734 | OPC_Decode, 158, 27, 177, 2, // 9255: decode to VRSRAsv1i64 using decoder 305 |
| 14735 | // 9255: } |
| 14736 | 243, 1, 0, // 9260: case 0xf3: { |
| 14737 | OPC_CheckPredicate, 35, // 9263: check predicate 35 |
| 14738 | OPC_Decode, 166, 27, 177, 2, // 9265: decode to VRSRAuv1i64 using decoder 305 |
| 14739 | // 9265: } |
| 14740 | // 9265: } // switch Inst[31:24] |
| 14741 | // 9265: } |
| 14742 | 4, 12, // 9270: case 0x4: { |
| 14743 | OPC_CheckPredicate, 35, // 9272: check predicate 35 |
| 14744 | OPC_CheckField, 24, 8, 243, 1, // 9274: check Inst[31:24] == 0xf3 |
| 14745 | OPC_Decode, 159, 28, 177, 2, // 9279: decode to VSRIv1i64 using decoder 305 |
| 14746 | // 9279: } |
| 14747 | 5, 23, // 9284: case 0x5: { |
| 14748 | OPC_SwitchField, 24, 8, // 9286: switch Inst[31:24] { |
| 14749 | 242, 1, 7, // 9289: case 0xf2: { |
| 14750 | OPC_CheckPredicate, 35, // 9292: check predicate 35 |
| 14751 | OPC_Decode, 207, 27, 178, 2, // 9294: decode to VSHLiv1i64 using decoder 306 |
| 14752 | // 9294: } |
| 14753 | 243, 1, 0, // 9299: case 0xf3: { |
| 14754 | OPC_CheckPredicate, 35, // 9302: check predicate 35 |
| 14755 | OPC_Decode, 128, 28, 179, 2, // 9304: decode to VSLIv1i64 using decoder 307 |
| 14756 | // 9304: } |
| 14757 | // 9304: } // switch Inst[31:24] |
| 14758 | // 9304: } |
| 14759 | 6, 12, // 9309: case 0x6: { |
| 14760 | OPC_CheckPredicate, 35, // 9311: check predicate 35 |
| 14761 | OPC_CheckField, 24, 8, 243, 1, // 9313: check Inst[31:24] == 0xf3 |
| 14762 | OPC_Decode, 230, 25, 178, 2, // 9318: decode to VQSHLsuv1i64 using decoder 306 |
| 14763 | // 9318: } |
| 14764 | 7, 0, // 9323: case 0x7: { |
| 14765 | OPC_SwitchField, 24, 8, // 9325: switch Inst[31:24] { |
| 14766 | 242, 1, 7, // 9328: case 0xf2: { |
| 14767 | OPC_CheckPredicate, 35, // 9331: check predicate 35 |
| 14768 | OPC_Decode, 222, 25, 178, 2, // 9333: decode to VQSHLsiv1i64 using decoder 306 |
| 14769 | // 9333: } |
| 14770 | 243, 1, 0, // 9338: case 0xf3: { |
| 14771 | OPC_CheckPredicate, 35, // 9341: check predicate 35 |
| 14772 | OPC_Decode, 246, 25, 178, 2, // 9343: decode to VQSHLuiv1i64 using decoder 306 |
| 14773 | // 9343: } |
| 14774 | // 9343: } // switch Inst[31:24] |
| 14775 | // 9343: } |
| 14776 | // 9343: } // switch Inst[11:8] |
| 14777 | // 9343: } |
| 14778 | // 9343: } // switch Inst[7] |
| 14779 | // 9343: } |
| 14780 | // 9343: } // switch Inst[23] |
| 14781 | // 9343: } |
| 14782 | 1, 0, // 9348: case 0x1: { |
| 14783 | OPC_SwitchField, 23, 1, // 9350: switch Inst[23] { |
| 14784 | 0, 203, 9, // 9353: case 0x0: { |
| 14785 | OPC_SwitchField, 8, 4, // 9356: switch Inst[11:8] { |
| 14786 | 0, 103, // 9359: case 0x0: { |
| 14787 | OPC_SwitchField, 20, 2, // 9361: switch Inst[21:20] { |
| 14788 | 0, 23, // 9364: case 0x0: { |
| 14789 | OPC_SwitchField, 24, 8, // 9366: switch Inst[31:24] { |
| 14790 | 242, 1, 7, // 9369: case 0xf2: { |
| 14791 | OPC_CheckPredicate, 35, // 9372: check predicate 35 |
| 14792 | OPC_Decode, 249, 24, 239, 1, // 9374: decode to VQADDsv16i8 using decoder 239 |
| 14793 | // 9374: } |
| 14794 | 243, 1, 0, // 9379: case 0xf3: { |
| 14795 | OPC_CheckPredicate, 35, // 9382: check predicate 35 |
| 14796 | OPC_Decode, 129, 25, 239, 1, // 9384: decode to VQADDuv16i8 using decoder 239 |
| 14797 | // 9384: } |
| 14798 | // 9384: } // switch Inst[31:24] |
| 14799 | // 9384: } |
| 14800 | 1, 23, // 9389: case 0x1: { |
| 14801 | OPC_SwitchField, 24, 8, // 9391: switch Inst[31:24] { |
| 14802 | 242, 1, 7, // 9394: case 0xf2: { |
| 14803 | OPC_CheckPredicate, 35, // 9397: check predicate 35 |
| 14804 | OPC_Decode, 255, 24, 239, 1, // 9399: decode to VQADDsv8i16 using decoder 239 |
| 14805 | // 9399: } |
| 14806 | 243, 1, 0, // 9404: case 0xf3: { |
| 14807 | OPC_CheckPredicate, 35, // 9407: check predicate 35 |
| 14808 | OPC_Decode, 135, 25, 239, 1, // 9409: decode to VQADDuv8i16 using decoder 239 |
| 14809 | // 9409: } |
| 14810 | // 9409: } // switch Inst[31:24] |
| 14811 | // 9409: } |
| 14812 | 2, 23, // 9414: case 0x2: { |
| 14813 | OPC_SwitchField, 24, 8, // 9416: switch Inst[31:24] { |
| 14814 | 242, 1, 7, // 9419: case 0xf2: { |
| 14815 | OPC_CheckPredicate, 35, // 9422: check predicate 35 |
| 14816 | OPC_Decode, 254, 24, 239, 1, // 9424: decode to VQADDsv4i32 using decoder 239 |
| 14817 | // 9424: } |
| 14818 | 243, 1, 0, // 9429: case 0xf3: { |
| 14819 | OPC_CheckPredicate, 35, // 9432: check predicate 35 |
| 14820 | OPC_Decode, 134, 25, 239, 1, // 9434: decode to VQADDuv4i32 using decoder 239 |
| 14821 | // 9434: } |
| 14822 | // 9434: } // switch Inst[31:24] |
| 14823 | // 9434: } |
| 14824 | 3, 0, // 9439: case 0x3: { |
| 14825 | OPC_SwitchField, 24, 8, // 9441: switch Inst[31:24] { |
| 14826 | 242, 1, 7, // 9444: case 0xf2: { |
| 14827 | OPC_CheckPredicate, 35, // 9447: check predicate 35 |
| 14828 | OPC_Decode, 252, 24, 239, 1, // 9449: decode to VQADDsv2i64 using decoder 239 |
| 14829 | // 9449: } |
| 14830 | 243, 1, 0, // 9454: case 0xf3: { |
| 14831 | OPC_CheckPredicate, 35, // 9457: check predicate 35 |
| 14832 | OPC_Decode, 132, 25, 239, 1, // 9459: decode to VQADDuv2i64 using decoder 239 |
| 14833 | // 9459: } |
| 14834 | // 9459: } // switch Inst[31:24] |
| 14835 | // 9459: } |
| 14836 | // 9459: } // switch Inst[21:20] |
| 14837 | // 9459: } |
| 14838 | 1, 103, // 9464: case 0x1: { |
| 14839 | OPC_SwitchField, 20, 2, // 9466: switch Inst[21:20] { |
| 14840 | 0, 23, // 9469: case 0x0: { |
| 14841 | OPC_SwitchField, 24, 8, // 9471: switch Inst[31:24] { |
| 14842 | 242, 1, 7, // 9474: case 0xf2: { |
| 14843 | OPC_CheckPredicate, 35, // 9477: check predicate 35 |
| 14844 | OPC_Decode, 145, 17, 239, 1, // 9479: decode to VANDq using decoder 239 |
| 14845 | // 9479: } |
| 14846 | 243, 1, 0, // 9484: case 0xf3: { |
| 14847 | OPC_CheckPredicate, 35, // 9487: check predicate 35 |
| 14848 | OPC_Decode, 154, 19, 239, 1, // 9489: decode to VEORq using decoder 239 |
| 14849 | // 9489: } |
| 14850 | // 9489: } // switch Inst[31:24] |
| 14851 | // 9489: } |
| 14852 | 1, 23, // 9494: case 0x1: { |
| 14853 | OPC_SwitchField, 24, 8, // 9496: switch Inst[31:24] { |
| 14854 | 242, 1, 7, // 9499: case 0xf2: { |
| 14855 | OPC_CheckPredicate, 35, // 9502: check predicate 35 |
| 14856 | OPC_Decode, 155, 17, 239, 1, // 9504: decode to VBICq using decoder 239 |
| 14857 | // 9504: } |
| 14858 | 243, 1, 0, // 9509: case 0xf3: { |
| 14859 | OPC_CheckPredicate, 35, // 9512: check predicate 35 |
| 14860 | OPC_Decode, 161, 17, 247, 1, // 9514: decode to VBSLq using decoder 247 |
| 14861 | // 9514: } |
| 14862 | // 9514: } // switch Inst[31:24] |
| 14863 | // 9514: } |
| 14864 | 2, 23, // 9519: case 0x2: { |
| 14865 | OPC_SwitchField, 24, 8, // 9521: switch Inst[31:24] { |
| 14866 | 242, 1, 7, // 9524: case 0xf2: { |
| 14867 | OPC_CheckPredicate, 35, // 9527: check predicate 35 |
| 14868 | OPC_Decode, 197, 24, 239, 1, // 9529: decode to VORRq using decoder 239 |
| 14869 | // 9529: } |
| 14870 | 243, 1, 0, // 9534: case 0xf3: { |
| 14871 | OPC_CheckPredicate, 35, // 9537: check predicate 35 |
| 14872 | OPC_Decode, 159, 17, 247, 1, // 9539: decode to VBITq using decoder 247 |
| 14873 | // 9539: } |
| 14874 | // 9539: } // switch Inst[31:24] |
| 14875 | // 9539: } |
| 14876 | 3, 0, // 9544: case 0x3: { |
| 14877 | OPC_SwitchField, 24, 8, // 9546: switch Inst[31:24] { |
| 14878 | 242, 1, 7, // 9549: case 0xf2: { |
| 14879 | OPC_CheckPredicate, 35, // 9552: check predicate 35 |
| 14880 | OPC_Decode, 191, 24, 239, 1, // 9554: decode to VORNq using decoder 239 |
| 14881 | // 9554: } |
| 14882 | 243, 1, 0, // 9559: case 0xf3: { |
| 14883 | OPC_CheckPredicate, 35, // 9562: check predicate 35 |
| 14884 | OPC_Decode, 157, 17, 247, 1, // 9564: decode to VBIFq using decoder 247 |
| 14885 | // 9564: } |
| 14886 | // 9564: } // switch Inst[31:24] |
| 14887 | // 9564: } |
| 14888 | // 9564: } // switch Inst[21:20] |
| 14889 | // 9564: } |
| 14890 | 2, 103, // 9569: case 0x2: { |
| 14891 | OPC_SwitchField, 20, 2, // 9571: switch Inst[21:20] { |
| 14892 | 0, 23, // 9574: case 0x0: { |
| 14893 | OPC_SwitchField, 24, 8, // 9576: switch Inst[31:24] { |
| 14894 | 242, 1, 7, // 9579: case 0xf2: { |
| 14895 | OPC_CheckPredicate, 35, // 9582: check predicate 35 |
| 14896 | OPC_Decode, 142, 26, 239, 1, // 9584: decode to VQSUBsv16i8 using decoder 239 |
| 14897 | // 9584: } |
| 14898 | 243, 1, 0, // 9589: case 0xf3: { |
| 14899 | OPC_CheckPredicate, 35, // 9592: check predicate 35 |
| 14900 | OPC_Decode, 150, 26, 239, 1, // 9594: decode to VQSUBuv16i8 using decoder 239 |
| 14901 | // 9594: } |
| 14902 | // 9594: } // switch Inst[31:24] |
| 14903 | // 9594: } |
| 14904 | 1, 23, // 9599: case 0x1: { |
| 14905 | OPC_SwitchField, 24, 8, // 9601: switch Inst[31:24] { |
| 14906 | 242, 1, 7, // 9604: case 0xf2: { |
| 14907 | OPC_CheckPredicate, 35, // 9607: check predicate 35 |
| 14908 | OPC_Decode, 148, 26, 239, 1, // 9609: decode to VQSUBsv8i16 using decoder 239 |
| 14909 | // 9609: } |
| 14910 | 243, 1, 0, // 9614: case 0xf3: { |
| 14911 | OPC_CheckPredicate, 35, // 9617: check predicate 35 |
| 14912 | OPC_Decode, 156, 26, 239, 1, // 9619: decode to VQSUBuv8i16 using decoder 239 |
| 14913 | // 9619: } |
| 14914 | // 9619: } // switch Inst[31:24] |
| 14915 | // 9619: } |
| 14916 | 2, 23, // 9624: case 0x2: { |
| 14917 | OPC_SwitchField, 24, 8, // 9626: switch Inst[31:24] { |
| 14918 | 242, 1, 7, // 9629: case 0xf2: { |
| 14919 | OPC_CheckPredicate, 35, // 9632: check predicate 35 |
| 14920 | OPC_Decode, 147, 26, 239, 1, // 9634: decode to VQSUBsv4i32 using decoder 239 |
| 14921 | // 9634: } |
| 14922 | 243, 1, 0, // 9639: case 0xf3: { |
| 14923 | OPC_CheckPredicate, 35, // 9642: check predicate 35 |
| 14924 | OPC_Decode, 155, 26, 239, 1, // 9644: decode to VQSUBuv4i32 using decoder 239 |
| 14925 | // 9644: } |
| 14926 | // 9644: } // switch Inst[31:24] |
| 14927 | // 9644: } |
| 14928 | 3, 0, // 9649: case 0x3: { |
| 14929 | OPC_SwitchField, 24, 8, // 9651: switch Inst[31:24] { |
| 14930 | 242, 1, 7, // 9654: case 0xf2: { |
| 14931 | OPC_CheckPredicate, 35, // 9657: check predicate 35 |
| 14932 | OPC_Decode, 145, 26, 239, 1, // 9659: decode to VQSUBsv2i64 using decoder 239 |
| 14933 | // 9659: } |
| 14934 | 243, 1, 0, // 9664: case 0xf3: { |
| 14935 | OPC_CheckPredicate, 35, // 9667: check predicate 35 |
| 14936 | OPC_Decode, 153, 26, 239, 1, // 9669: decode to VQSUBuv2i64 using decoder 239 |
| 14937 | // 9669: } |
| 14938 | // 9669: } // switch Inst[31:24] |
| 14939 | // 9669: } |
| 14940 | // 9669: } // switch Inst[21:20] |
| 14941 | // 9669: } |
| 14942 | 3, 78, // 9674: case 0x3: { |
| 14943 | OPC_SwitchField, 20, 2, // 9676: switch Inst[21:20] { |
| 14944 | 0, 23, // 9679: case 0x0: { |
| 14945 | OPC_SwitchField, 24, 8, // 9681: switch Inst[31:24] { |
| 14946 | 242, 1, 7, // 9684: case 0xf2: { |
| 14947 | OPC_CheckPredicate, 35, // 9687: check predicate 35 |
| 14948 | OPC_Decode, 192, 17, 239, 1, // 9689: decode to VCGEsv16i8 using decoder 239 |
| 14949 | // 9689: } |
| 14950 | 243, 1, 0, // 9694: case 0xf3: { |
| 14951 | OPC_CheckPredicate, 35, // 9697: check predicate 35 |
| 14952 | OPC_Decode, 198, 17, 239, 1, // 9699: decode to VCGEuv16i8 using decoder 239 |
| 14953 | // 9699: } |
| 14954 | // 9699: } // switch Inst[31:24] |
| 14955 | // 9699: } |
| 14956 | 1, 23, // 9704: case 0x1: { |
| 14957 | OPC_SwitchField, 24, 8, // 9706: switch Inst[31:24] { |
| 14958 | 242, 1, 7, // 9709: case 0xf2: { |
| 14959 | OPC_CheckPredicate, 35, // 9712: check predicate 35 |
| 14960 | OPC_Decode, 196, 17, 239, 1, // 9714: decode to VCGEsv8i16 using decoder 239 |
| 14961 | // 9714: } |
| 14962 | 243, 1, 0, // 9719: case 0xf3: { |
| 14963 | OPC_CheckPredicate, 35, // 9722: check predicate 35 |
| 14964 | OPC_Decode, 202, 17, 239, 1, // 9724: decode to VCGEuv8i16 using decoder 239 |
| 14965 | // 9724: } |
| 14966 | // 9724: } // switch Inst[31:24] |
| 14967 | // 9724: } |
| 14968 | 2, 0, // 9729: case 0x2: { |
| 14969 | OPC_SwitchField, 24, 8, // 9731: switch Inst[31:24] { |
| 14970 | 242, 1, 7, // 9734: case 0xf2: { |
| 14971 | OPC_CheckPredicate, 35, // 9737: check predicate 35 |
| 14972 | OPC_Decode, 195, 17, 239, 1, // 9739: decode to VCGEsv4i32 using decoder 239 |
| 14973 | // 9739: } |
| 14974 | 243, 1, 0, // 9744: case 0xf3: { |
| 14975 | OPC_CheckPredicate, 35, // 9747: check predicate 35 |
| 14976 | OPC_Decode, 201, 17, 239, 1, // 9749: decode to VCGEuv4i32 using decoder 239 |
| 14977 | // 9749: } |
| 14978 | // 9749: } // switch Inst[31:24] |
| 14979 | // 9749: } |
| 14980 | // 9749: } // switch Inst[21:20] |
| 14981 | // 9749: } |
| 14982 | 4, 103, // 9754: case 0x4: { |
| 14983 | OPC_SwitchField, 20, 2, // 9756: switch Inst[21:20] { |
| 14984 | 0, 23, // 9759: case 0x0: { |
| 14985 | OPC_SwitchField, 24, 8, // 9761: switch Inst[31:24] { |
| 14986 | 242, 1, 7, // 9764: case 0xf2: { |
| 14987 | OPC_CheckPredicate, 35, // 9767: check predicate 35 |
| 14988 | OPC_Decode, 237, 25, 243, 1, // 9769: decode to VQSHLsv16i8 using decoder 243 |
| 14989 | // 9769: } |
| 14990 | 243, 1, 0, // 9774: case 0xf3: { |
| 14991 | OPC_CheckPredicate, 35, // 9777: check predicate 35 |
| 14992 | OPC_Decode, 253, 25, 243, 1, // 9779: decode to VQSHLuv16i8 using decoder 243 |
| 14993 | // 9779: } |
| 14994 | // 9779: } // switch Inst[31:24] |
| 14995 | // 9779: } |
| 14996 | 1, 23, // 9784: case 0x1: { |
| 14997 | OPC_SwitchField, 24, 8, // 9786: switch Inst[31:24] { |
| 14998 | 242, 1, 7, // 9789: case 0xf2: { |
| 14999 | OPC_CheckPredicate, 35, // 9792: check predicate 35 |
| 15000 | OPC_Decode, 243, 25, 243, 1, // 9794: decode to VQSHLsv8i16 using decoder 243 |
| 15001 | // 9794: } |
| 15002 | 243, 1, 0, // 9799: case 0xf3: { |
| 15003 | OPC_CheckPredicate, 35, // 9802: check predicate 35 |
| 15004 | OPC_Decode, 131, 26, 243, 1, // 9804: decode to VQSHLuv8i16 using decoder 243 |
| 15005 | // 9804: } |
| 15006 | // 9804: } // switch Inst[31:24] |
| 15007 | // 9804: } |
| 15008 | 2, 23, // 9809: case 0x2: { |
| 15009 | OPC_SwitchField, 24, 8, // 9811: switch Inst[31:24] { |
| 15010 | 242, 1, 7, // 9814: case 0xf2: { |
| 15011 | OPC_CheckPredicate, 35, // 9817: check predicate 35 |
| 15012 | OPC_Decode, 242, 25, 243, 1, // 9819: decode to VQSHLsv4i32 using decoder 243 |
| 15013 | // 9819: } |
| 15014 | 243, 1, 0, // 9824: case 0xf3: { |
| 15015 | OPC_CheckPredicate, 35, // 9827: check predicate 35 |
| 15016 | OPC_Decode, 130, 26, 243, 1, // 9829: decode to VQSHLuv4i32 using decoder 243 |
| 15017 | // 9829: } |
| 15018 | // 9829: } // switch Inst[31:24] |
| 15019 | // 9829: } |
| 15020 | 3, 0, // 9834: case 0x3: { |
| 15021 | OPC_SwitchField, 24, 8, // 9836: switch Inst[31:24] { |
| 15022 | 242, 1, 7, // 9839: case 0xf2: { |
| 15023 | OPC_CheckPredicate, 35, // 9842: check predicate 35 |
| 15024 | OPC_Decode, 240, 25, 243, 1, // 9844: decode to VQSHLsv2i64 using decoder 243 |
| 15025 | // 9844: } |
| 15026 | 243, 1, 0, // 9849: case 0xf3: { |
| 15027 | OPC_CheckPredicate, 35, // 9852: check predicate 35 |
| 15028 | OPC_Decode, 128, 26, 243, 1, // 9854: decode to VQSHLuv2i64 using decoder 243 |
| 15029 | // 9854: } |
| 15030 | // 9854: } // switch Inst[31:24] |
| 15031 | // 9854: } |
| 15032 | // 9854: } // switch Inst[21:20] |
| 15033 | // 9854: } |
| 15034 | 5, 103, // 9859: case 0x5: { |
| 15035 | OPC_SwitchField, 20, 2, // 9861: switch Inst[21:20] { |
| 15036 | 0, 23, // 9864: case 0x0: { |
| 15037 | OPC_SwitchField, 24, 8, // 9866: switch Inst[31:24] { |
| 15038 | 242, 1, 7, // 9869: case 0xf2: { |
| 15039 | OPC_CheckPredicate, 35, // 9872: check predicate 35 |
| 15040 | OPC_Decode, 196, 25, 243, 1, // 9874: decode to VQRSHLsv16i8 using decoder 243 |
| 15041 | // 9874: } |
| 15042 | 243, 1, 0, // 9879: case 0xf3: { |
| 15043 | OPC_CheckPredicate, 35, // 9882: check predicate 35 |
| 15044 | OPC_Decode, 204, 25, 243, 1, // 9884: decode to VQRSHLuv16i8 using decoder 243 |
| 15045 | // 9884: } |
| 15046 | // 9884: } // switch Inst[31:24] |
| 15047 | // 9884: } |
| 15048 | 1, 23, // 9889: case 0x1: { |
| 15049 | OPC_SwitchField, 24, 8, // 9891: switch Inst[31:24] { |
| 15050 | 242, 1, 7, // 9894: case 0xf2: { |
| 15051 | OPC_CheckPredicate, 35, // 9897: check predicate 35 |
| 15052 | OPC_Decode, 202, 25, 243, 1, // 9899: decode to VQRSHLsv8i16 using decoder 243 |
| 15053 | // 9899: } |
| 15054 | 243, 1, 0, // 9904: case 0xf3: { |
| 15055 | OPC_CheckPredicate, 35, // 9907: check predicate 35 |
| 15056 | OPC_Decode, 210, 25, 243, 1, // 9909: decode to VQRSHLuv8i16 using decoder 243 |
| 15057 | // 9909: } |
| 15058 | // 9909: } // switch Inst[31:24] |
| 15059 | // 9909: } |
| 15060 | 2, 23, // 9914: case 0x2: { |
| 15061 | OPC_SwitchField, 24, 8, // 9916: switch Inst[31:24] { |
| 15062 | 242, 1, 7, // 9919: case 0xf2: { |
| 15063 | OPC_CheckPredicate, 35, // 9922: check predicate 35 |
| 15064 | OPC_Decode, 201, 25, 243, 1, // 9924: decode to VQRSHLsv4i32 using decoder 243 |
| 15065 | // 9924: } |
| 15066 | 243, 1, 0, // 9929: case 0xf3: { |
| 15067 | OPC_CheckPredicate, 35, // 9932: check predicate 35 |
| 15068 | OPC_Decode, 209, 25, 243, 1, // 9934: decode to VQRSHLuv4i32 using decoder 243 |
| 15069 | // 9934: } |
| 15070 | // 9934: } // switch Inst[31:24] |
| 15071 | // 9934: } |
| 15072 | 3, 0, // 9939: case 0x3: { |
| 15073 | OPC_SwitchField, 24, 8, // 9941: switch Inst[31:24] { |
| 15074 | 242, 1, 7, // 9944: case 0xf2: { |
| 15075 | OPC_CheckPredicate, 35, // 9947: check predicate 35 |
| 15076 | OPC_Decode, 199, 25, 243, 1, // 9949: decode to VQRSHLsv2i64 using decoder 243 |
| 15077 | // 9949: } |
| 15078 | 243, 1, 0, // 9954: case 0xf3: { |
| 15079 | OPC_CheckPredicate, 35, // 9957: check predicate 35 |
| 15080 | OPC_Decode, 207, 25, 243, 1, // 9959: decode to VQRSHLuv2i64 using decoder 243 |
| 15081 | // 9959: } |
| 15082 | // 9959: } // switch Inst[31:24] |
| 15083 | // 9959: } |
| 15084 | // 9959: } // switch Inst[21:20] |
| 15085 | // 9959: } |
| 15086 | 6, 78, // 9964: case 0x6: { |
| 15087 | OPC_SwitchField, 20, 2, // 9966: switch Inst[21:20] { |
| 15088 | 0, 23, // 9969: case 0x0: { |
| 15089 | OPC_SwitchField, 24, 8, // 9971: switch Inst[31:24] { |
| 15090 | 242, 1, 7, // 9974: case 0xf2: { |
| 15091 | OPC_CheckPredicate, 35, // 9977: check predicate 35 |
| 15092 | OPC_Decode, 255, 22, 239, 1, // 9979: decode to VMINsv16i8 using decoder 239 |
| 15093 | // 9979: } |
| 15094 | 243, 1, 0, // 9984: case 0xf3: { |
| 15095 | OPC_CheckPredicate, 35, // 9987: check predicate 35 |
| 15096 | OPC_Decode, 133, 23, 239, 1, // 9989: decode to VMINuv16i8 using decoder 239 |
| 15097 | // 9989: } |
| 15098 | // 9989: } // switch Inst[31:24] |
| 15099 | // 9989: } |
| 15100 | 1, 23, // 9994: case 0x1: { |
| 15101 | OPC_SwitchField, 24, 8, // 9996: switch Inst[31:24] { |
| 15102 | 242, 1, 7, // 9999: case 0xf2: { |
| 15103 | OPC_CheckPredicate, 35, // 10002: check predicate 35 |
| 15104 | OPC_Decode, 131, 23, 239, 1, // 10004: decode to VMINsv8i16 using decoder 239 |
| 15105 | // 10004: } |
| 15106 | 243, 1, 0, // 10009: case 0xf3: { |
| 15107 | OPC_CheckPredicate, 35, // 10012: check predicate 35 |
| 15108 | OPC_Decode, 137, 23, 239, 1, // 10014: decode to VMINuv8i16 using decoder 239 |
| 15109 | // 10014: } |
| 15110 | // 10014: } // switch Inst[31:24] |
| 15111 | // 10014: } |
| 15112 | 2, 0, // 10019: case 0x2: { |
| 15113 | OPC_SwitchField, 24, 8, // 10021: switch Inst[31:24] { |
| 15114 | 242, 1, 7, // 10024: case 0xf2: { |
| 15115 | OPC_CheckPredicate, 35, // 10027: check predicate 35 |
| 15116 | OPC_Decode, 130, 23, 239, 1, // 10029: decode to VMINsv4i32 using decoder 239 |
| 15117 | // 10029: } |
| 15118 | 243, 1, 0, // 10034: case 0xf3: { |
| 15119 | OPC_CheckPredicate, 35, // 10037: check predicate 35 |
| 15120 | OPC_Decode, 136, 23, 239, 1, // 10039: decode to VMINuv4i32 using decoder 239 |
| 15121 | // 10039: } |
| 15122 | // 10039: } // switch Inst[31:24] |
| 15123 | // 10039: } |
| 15124 | // 10039: } // switch Inst[21:20] |
| 15125 | // 10039: } |
| 15126 | 7, 78, // 10044: case 0x7: { |
| 15127 | OPC_SwitchField, 20, 2, // 10046: switch Inst[21:20] { |
| 15128 | 0, 23, // 10049: case 0x0: { |
| 15129 | OPC_SwitchField, 24, 8, // 10051: switch Inst[31:24] { |
| 15130 | 242, 1, 7, // 10054: case 0xf2: { |
| 15131 | OPC_CheckPredicate, 35, // 10057: check predicate 35 |
| 15132 | OPC_Decode, 187, 16, 247, 1, // 10059: decode to VABAsv16i8 using decoder 247 |
| 15133 | // 10059: } |
| 15134 | 243, 1, 0, // 10064: case 0xf3: { |
| 15135 | OPC_CheckPredicate, 35, // 10067: check predicate 35 |
| 15136 | OPC_Decode, 193, 16, 247, 1, // 10069: decode to VABAuv16i8 using decoder 247 |
| 15137 | // 10069: } |
| 15138 | // 10069: } // switch Inst[31:24] |
| 15139 | // 10069: } |
| 15140 | 1, 23, // 10074: case 0x1: { |
| 15141 | OPC_SwitchField, 24, 8, // 10076: switch Inst[31:24] { |
| 15142 | 242, 1, 7, // 10079: case 0xf2: { |
| 15143 | OPC_CheckPredicate, 35, // 10082: check predicate 35 |
| 15144 | OPC_Decode, 191, 16, 247, 1, // 10084: decode to VABAsv8i16 using decoder 247 |
| 15145 | // 10084: } |
| 15146 | 243, 1, 0, // 10089: case 0xf3: { |
| 15147 | OPC_CheckPredicate, 35, // 10092: check predicate 35 |
| 15148 | OPC_Decode, 197, 16, 247, 1, // 10094: decode to VABAuv8i16 using decoder 247 |
| 15149 | // 10094: } |
| 15150 | // 10094: } // switch Inst[31:24] |
| 15151 | // 10094: } |
| 15152 | 2, 0, // 10099: case 0x2: { |
| 15153 | OPC_SwitchField, 24, 8, // 10101: switch Inst[31:24] { |
| 15154 | 242, 1, 7, // 10104: case 0xf2: { |
| 15155 | OPC_CheckPredicate, 35, // 10107: check predicate 35 |
| 15156 | OPC_Decode, 190, 16, 247, 1, // 10109: decode to VABAsv4i32 using decoder 247 |
| 15157 | // 10109: } |
| 15158 | 243, 1, 0, // 10114: case 0xf3: { |
| 15159 | OPC_CheckPredicate, 35, // 10117: check predicate 35 |
| 15160 | OPC_Decode, 196, 16, 247, 1, // 10119: decode to VABAuv4i32 using decoder 247 |
| 15161 | // 10119: } |
| 15162 | // 10119: } // switch Inst[31:24] |
| 15163 | // 10119: } |
| 15164 | // 10119: } // switch Inst[21:20] |
| 15165 | // 10119: } |
| 15166 | 8, 78, // 10124: case 0x8: { |
| 15167 | OPC_SwitchField, 20, 2, // 10126: switch Inst[21:20] { |
| 15168 | 0, 23, // 10129: case 0x0: { |
| 15169 | OPC_SwitchField, 24, 8, // 10131: switch Inst[31:24] { |
| 15170 | 242, 1, 7, // 10134: case 0xf2: { |
| 15171 | OPC_CheckPredicate, 35, // 10137: check predicate 35 |
| 15172 | OPC_Decode, 144, 31, 239, 1, // 10139: decode to VTSTv16i8 using decoder 239 |
| 15173 | // 10139: } |
| 15174 | 243, 1, 0, // 10144: case 0xf3: { |
| 15175 | OPC_CheckPredicate, 35, // 10147: check predicate 35 |
| 15176 | OPC_Decode, 172, 17, 239, 1, // 10149: decode to VCEQv16i8 using decoder 239 |
| 15177 | // 10149: } |
| 15178 | // 10149: } // switch Inst[31:24] |
| 15179 | // 10149: } |
| 15180 | 1, 23, // 10154: case 0x1: { |
| 15181 | OPC_SwitchField, 24, 8, // 10156: switch Inst[31:24] { |
| 15182 | 242, 1, 7, // 10159: case 0xf2: { |
| 15183 | OPC_CheckPredicate, 35, // 10162: check predicate 35 |
| 15184 | OPC_Decode, 148, 31, 239, 1, // 10164: decode to VTSTv8i16 using decoder 239 |
| 15185 | // 10164: } |
| 15186 | 243, 1, 0, // 10169: case 0xf3: { |
| 15187 | OPC_CheckPredicate, 35, // 10172: check predicate 35 |
| 15188 | OPC_Decode, 176, 17, 239, 1, // 10174: decode to VCEQv8i16 using decoder 239 |
| 15189 | // 10174: } |
| 15190 | // 10174: } // switch Inst[31:24] |
| 15191 | // 10174: } |
| 15192 | 2, 0, // 10179: case 0x2: { |
| 15193 | OPC_SwitchField, 24, 8, // 10181: switch Inst[31:24] { |
| 15194 | 242, 1, 7, // 10184: case 0xf2: { |
| 15195 | OPC_CheckPredicate, 35, // 10187: check predicate 35 |
| 15196 | OPC_Decode, 147, 31, 239, 1, // 10189: decode to VTSTv4i32 using decoder 239 |
| 15197 | // 10189: } |
| 15198 | 243, 1, 0, // 10194: case 0xf3: { |
| 15199 | OPC_CheckPredicate, 35, // 10197: check predicate 35 |
| 15200 | OPC_Decode, 175, 17, 239, 1, // 10199: decode to VCEQv4i32 using decoder 239 |
| 15201 | // 10199: } |
| 15202 | // 10199: } // switch Inst[31:24] |
| 15203 | // 10199: } |
| 15204 | // 10199: } // switch Inst[21:20] |
| 15205 | // 10199: } |
| 15206 | 9, 56, // 10204: case 0x9: { |
| 15207 | OPC_SwitchField, 20, 2, // 10206: switch Inst[21:20] { |
| 15208 | 0, 23, // 10209: case 0x0: { |
| 15209 | OPC_SwitchField, 24, 8, // 10211: switch Inst[31:24] { |
| 15210 | 242, 1, 7, // 10214: case 0xf2: { |
| 15211 | OPC_CheckPredicate, 35, // 10217: check predicate 35 |
| 15212 | OPC_Decode, 156, 24, 239, 1, // 10219: decode to VMULv16i8 using decoder 239 |
| 15213 | // 10219: } |
| 15214 | 243, 1, 0, // 10224: case 0xf3: { |
| 15215 | OPC_CheckPredicate, 35, // 10227: check predicate 35 |
| 15216 | OPC_Decode, 147, 24, 239, 1, // 10229: decode to VMULpq using decoder 239 |
| 15217 | // 10229: } |
| 15218 | // 10229: } // switch Inst[31:24] |
| 15219 | // 10229: } |
| 15220 | 1, 12, // 10234: case 0x1: { |
| 15221 | OPC_CheckPredicate, 35, // 10236: check predicate 35 |
| 15222 | OPC_CheckField, 24, 8, 242, 1, // 10238: check Inst[31:24] == 0xf2 |
| 15223 | OPC_Decode, 160, 24, 239, 1, // 10243: decode to VMULv8i16 using decoder 239 |
| 15224 | // 10243: } |
| 15225 | 2, 0, // 10248: case 0x2: { |
| 15226 | OPC_CheckPredicate, 35, // 10250: check predicate 35 |
| 15227 | OPC_CheckField, 24, 8, 242, 1, // 10252: check Inst[31:24] == 0xf2 |
| 15228 | OPC_Decode, 159, 24, 239, 1, // 10257: decode to VMULv4i32 using decoder 239 |
| 15229 | // 10257: } |
| 15230 | // 10257: } // switch Inst[21:20] |
| 15231 | // 10257: } |
| 15232 | 11, 31, // 10262: case 0xb: { |
| 15233 | OPC_SwitchField, 20, 2, // 10264: switch Inst[21:20] { |
| 15234 | 1, 12, // 10267: case 0x1: { |
| 15235 | OPC_CheckPredicate, 37, // 10269: check predicate 37 |
| 15236 | OPC_CheckField, 24, 8, 243, 1, // 10271: check Inst[31:24] == 0xf3 |
| 15237 | OPC_Decode, 179, 25, 247, 1, // 10276: decode to VQRDMLAHv8i16 using decoder 247 |
| 15238 | // 10276: } |
| 15239 | 2, 0, // 10281: case 0x2: { |
| 15240 | OPC_CheckPredicate, 37, // 10283: check predicate 37 |
| 15241 | OPC_CheckField, 24, 8, 243, 1, // 10285: check Inst[31:24] == 0xf3 |
| 15242 | OPC_Decode, 178, 25, 247, 1, // 10290: decode to VQRDMLAHv4i32 using decoder 247 |
| 15243 | // 10290: } |
| 15244 | // 10290: } // switch Inst[21:20] |
| 15245 | // 10290: } |
| 15246 | 12, 81, // 10295: case 0xc: { |
| 15247 | OPC_SwitchField, 20, 2, // 10297: switch Inst[21:20] { |
| 15248 | 0, 12, // 10300: case 0x0: { |
| 15249 | OPC_CheckPredicate, 41, // 10302: check predicate 41 |
| 15250 | OPC_CheckField, 24, 8, 242, 1, // 10304: check Inst[31:24] == 0xf2 |
| 15251 | OPC_Decode, 170, 19, 247, 1, // 10309: decode to VFMAfq using decoder 247 |
| 15252 | // 10309: } |
| 15253 | 1, 23, // 10314: case 0x1: { |
| 15254 | OPC_SwitchField, 24, 8, // 10316: switch Inst[31:24] { |
| 15255 | 242, 1, 7, // 10319: case 0xf2: { |
| 15256 | OPC_CheckPredicate, 36, // 10322: check predicate 36 |
| 15257 | OPC_Decode, 172, 19, 247, 1, // 10324: decode to VFMAhq using decoder 247 |
| 15258 | // 10324: } |
| 15259 | 243, 1, 0, // 10329: case 0xf3: { |
| 15260 | OPC_CheckPredicate, 37, // 10332: check predicate 37 |
| 15261 | OPC_Decode, 187, 25, 247, 1, // 10334: decode to VQRDMLSHv8i16 using decoder 247 |
| 15262 | // 10334: } |
| 15263 | // 10334: } // switch Inst[31:24] |
| 15264 | // 10334: } |
| 15265 | 2, 23, // 10339: case 0x2: { |
| 15266 | OPC_SwitchField, 24, 8, // 10341: switch Inst[31:24] { |
| 15267 | 242, 1, 7, // 10344: case 0xf2: { |
| 15268 | OPC_CheckPredicate, 41, // 10347: check predicate 41 |
| 15269 | OPC_Decode, 181, 19, 247, 1, // 10349: decode to VFMSfq using decoder 247 |
| 15270 | // 10349: } |
| 15271 | 243, 1, 0, // 10354: case 0xf3: { |
| 15272 | OPC_CheckPredicate, 37, // 10357: check predicate 37 |
| 15273 | OPC_Decode, 186, 25, 247, 1, // 10359: decode to VQRDMLSHv4i32 using decoder 247 |
| 15274 | // 10359: } |
| 15275 | // 10359: } // switch Inst[31:24] |
| 15276 | // 10359: } |
| 15277 | 3, 0, // 10364: case 0x3: { |
| 15278 | OPC_CheckPredicate, 36, // 10366: check predicate 36 |
| 15279 | OPC_CheckField, 24, 8, 242, 1, // 10368: check Inst[31:24] == 0xf2 |
| 15280 | OPC_Decode, 183, 19, 247, 1, // 10373: decode to VFMShq using decoder 247 |
| 15281 | // 10373: } |
| 15282 | // 10373: } // switch Inst[21:20] |
| 15283 | // 10373: } |
| 15284 | 13, 81, // 10378: case 0xd: { |
| 15285 | OPC_SwitchField, 20, 2, // 10380: switch Inst[21:20] { |
| 15286 | 0, 23, // 10383: case 0x0: { |
| 15287 | OPC_SwitchField, 24, 8, // 10385: switch Inst[31:24] { |
| 15288 | 242, 1, 7, // 10388: case 0xf2: { |
| 15289 | OPC_CheckPredicate, 35, // 10391: check predicate 35 |
| 15290 | OPC_Decode, 153, 23, 247, 1, // 10393: decode to VMLAfq using decoder 247 |
| 15291 | // 10393: } |
| 15292 | 243, 1, 0, // 10398: case 0xf3: { |
| 15293 | OPC_CheckPredicate, 35, // 10401: check predicate 35 |
| 15294 | OPC_Decode, 143, 24, 239, 1, // 10403: decode to VMULfq using decoder 239 |
| 15295 | // 10403: } |
| 15296 | // 10403: } // switch Inst[31:24] |
| 15297 | // 10403: } |
| 15298 | 1, 23, // 10408: case 0x1: { |
| 15299 | OPC_SwitchField, 24, 8, // 10410: switch Inst[31:24] { |
| 15300 | 242, 1, 7, // 10413: case 0xf2: { |
| 15301 | OPC_CheckPredicate, 36, // 10416: check predicate 36 |
| 15302 | OPC_Decode, 155, 23, 247, 1, // 10418: decode to VMLAhq using decoder 247 |
| 15303 | // 10418: } |
| 15304 | 243, 1, 0, // 10423: case 0xf3: { |
| 15305 | OPC_CheckPredicate, 36, // 10426: check predicate 36 |
| 15306 | OPC_Decode, 145, 24, 239, 1, // 10428: decode to VMULhq using decoder 239 |
| 15307 | // 10428: } |
| 15308 | // 10428: } // switch Inst[31:24] |
| 15309 | // 10428: } |
| 15310 | 2, 12, // 10433: case 0x2: { |
| 15311 | OPC_CheckPredicate, 35, // 10435: check predicate 35 |
| 15312 | OPC_CheckField, 24, 8, 242, 1, // 10437: check Inst[31:24] == 0xf2 |
| 15313 | OPC_Decode, 184, 23, 247, 1, // 10442: decode to VMLSfq using decoder 247 |
| 15314 | // 10442: } |
| 15315 | 3, 0, // 10447: case 0x3: { |
| 15316 | OPC_CheckPredicate, 36, // 10449: check predicate 36 |
| 15317 | OPC_CheckField, 24, 8, 242, 1, // 10451: check Inst[31:24] == 0xf2 |
| 15318 | OPC_Decode, 186, 23, 247, 1, // 10456: decode to VMLShq using decoder 247 |
| 15319 | // 10456: } |
| 15320 | // 10456: } // switch Inst[21:20] |
| 15321 | // 10456: } |
| 15322 | 14, 59, // 10461: case 0xe: { |
| 15323 | OPC_SwitchField, 20, 2, // 10463: switch Inst[21:20] { |
| 15324 | 0, 12, // 10466: case 0x0: { |
| 15325 | OPC_CheckPredicate, 35, // 10468: check predicate 35 |
| 15326 | OPC_CheckField, 24, 8, 243, 1, // 10470: check Inst[31:24] == 0xf3 |
| 15327 | OPC_Decode, 235, 16, 239, 1, // 10475: decode to VACGEfq using decoder 239 |
| 15328 | // 10475: } |
| 15329 | 1, 12, // 10480: case 0x1: { |
| 15330 | OPC_CheckPredicate, 36, // 10482: check predicate 36 |
| 15331 | OPC_CheckField, 24, 8, 243, 1, // 10484: check Inst[31:24] == 0xf3 |
| 15332 | OPC_Decode, 237, 16, 239, 1, // 10489: decode to VACGEhq using decoder 239 |
| 15333 | // 10489: } |
| 15334 | 2, 12, // 10494: case 0x2: { |
| 15335 | OPC_CheckPredicate, 35, // 10496: check predicate 35 |
| 15336 | OPC_CheckField, 24, 8, 243, 1, // 10498: check Inst[31:24] == 0xf3 |
| 15337 | OPC_Decode, 239, 16, 239, 1, // 10503: decode to VACGTfq using decoder 239 |
| 15338 | // 10503: } |
| 15339 | 3, 0, // 10508: case 0x3: { |
| 15340 | OPC_CheckPredicate, 36, // 10510: check predicate 36 |
| 15341 | OPC_CheckField, 24, 8, 243, 1, // 10512: check Inst[31:24] == 0xf3 |
| 15342 | OPC_Decode, 241, 16, 239, 1, // 10517: decode to VACGThq using decoder 239 |
| 15343 | // 10517: } |
| 15344 | // 10517: } // switch Inst[21:20] |
| 15345 | // 10517: } |
| 15346 | 15, 0, // 10522: case 0xf: { |
| 15347 | OPC_SwitchField, 20, 2, // 10524: switch Inst[21:20] { |
| 15348 | 0, 12, // 10527: case 0x0: { |
| 15349 | OPC_CheckPredicate, 35, // 10529: check predicate 35 |
| 15350 | OPC_CheckField, 24, 8, 242, 1, // 10531: check Inst[31:24] == 0xf2 |
| 15351 | OPC_Decode, 168, 26, 239, 1, // 10536: decode to VRECPSfq using decoder 239 |
| 15352 | // 10536: } |
| 15353 | 1, 12, // 10541: case 0x1: { |
| 15354 | OPC_CheckPredicate, 36, // 10543: check predicate 36 |
| 15355 | OPC_CheckField, 24, 8, 242, 1, // 10545: check Inst[31:24] == 0xf2 |
| 15356 | OPC_Decode, 170, 26, 239, 1, // 10550: decode to VRECPShq using decoder 239 |
| 15357 | // 10550: } |
| 15358 | 2, 12, // 10555: case 0x2: { |
| 15359 | OPC_CheckPredicate, 35, // 10557: check predicate 35 |
| 15360 | OPC_CheckField, 24, 8, 242, 1, // 10559: check Inst[31:24] == 0xf2 |
| 15361 | OPC_Decode, 154, 27, 239, 1, // 10564: decode to VRSQRTSfq using decoder 239 |
| 15362 | // 10564: } |
| 15363 | 3, 0, // 10569: case 0x3: { |
| 15364 | OPC_CheckPredicate, 36, // 10571: check predicate 36 |
| 15365 | OPC_CheckField, 24, 8, 242, 1, // 10573: check Inst[31:24] == 0xf2 |
| 15366 | OPC_Decode, 156, 27, 239, 1, // 10578: decode to VRSQRTShq using decoder 239 |
| 15367 | // 10578: } |
| 15368 | // 10578: } // switch Inst[21:20] |
| 15369 | // 10578: } |
| 15370 | // 10578: } // switch Inst[11:8] |
| 15371 | // 10578: } |
| 15372 | 1, 0, // 10583: case 0x1: { |
| 15373 | OPC_SwitchField, 7, 1, // 10585: switch Inst[7] { |
| 15374 | 0, 175, 8, // 10588: case 0x0: { |
| 15375 | OPC_CheckField, 25, 7, 121, // 10591: check Inst[31:25] == 0x79 |
| 15376 | OPC_Scope, 177, 7, // 10595: try { |
| 15377 | OPC_SwitchField, 8, 4, // 10598: switch Inst[11:8] { |
| 15378 | 0, 85, // 10601: case 0x0: { |
| 15379 | OPC_SwitchField, 21, 1, // 10603: switch Inst[21] { |
| 15380 | 0, 57, // 10606: case 0x0: { |
| 15381 | OPC_SwitchField, 20, 1, // 10608: switch Inst[20] { |
| 15382 | 0, 29, // 10611: case 0x0: { |
| 15383 | OPC_SwitchField, 24, 1, // 10613: switch Inst[24] { |
| 15384 | 0, 11, // 10616: case 0x0: { |
| 15385 | OPC_CheckPredicate, 35, // 10618: check predicate 35 |
| 15386 | OPC_CheckField, 19, 1, 1, // 10620: check Inst[19] == 0x1 |
| 15387 | OPC_Decode, 233, 27, 180, 2, // 10624: decode to VSHRsv16i8 using decoder 308 |
| 15388 | // 10624: } |
| 15389 | 1, 0, // 10629: case 0x1: { |
| 15390 | OPC_CheckPredicate, 35, // 10631: check predicate 35 |
| 15391 | OPC_CheckField, 19, 1, 1, // 10633: check Inst[19] == 0x1 |
| 15392 | OPC_Decode, 241, 27, 180, 2, // 10637: decode to VSHRuv16i8 using decoder 308 |
| 15393 | // 10637: } |
| 15394 | // 10637: } // switch Inst[24] |
| 15395 | // 10637: } |
| 15396 | 1, 0, // 10642: case 0x1: { |
| 15397 | OPC_SwitchField, 24, 1, // 10644: switch Inst[24] { |
| 15398 | 0, 7, // 10647: case 0x0: { |
| 15399 | OPC_CheckPredicate, 35, // 10649: check predicate 35 |
| 15400 | OPC_Decode, 239, 27, 181, 2, // 10651: decode to VSHRsv8i16 using decoder 309 |
| 15401 | // 10651: } |
| 15402 | 1, 0, // 10656: case 0x1: { |
| 15403 | OPC_CheckPredicate, 35, // 10658: check predicate 35 |
| 15404 | OPC_Decode, 247, 27, 181, 2, // 10660: decode to VSHRuv8i16 using decoder 309 |
| 15405 | // 10660: } |
| 15406 | // 10660: } // switch Inst[24] |
| 15407 | // 10660: } |
| 15408 | // 10660: } // switch Inst[20] |
| 15409 | // 10660: } |
| 15410 | 1, 0, // 10665: case 0x1: { |
| 15411 | OPC_SwitchField, 24, 1, // 10667: switch Inst[24] { |
| 15412 | 0, 7, // 10670: case 0x0: { |
| 15413 | OPC_CheckPredicate, 35, // 10672: check predicate 35 |
| 15414 | OPC_Decode, 238, 27, 182, 2, // 10674: decode to VSHRsv4i32 using decoder 310 |
| 15415 | // 10674: } |
| 15416 | 1, 0, // 10679: case 0x1: { |
| 15417 | OPC_CheckPredicate, 35, // 10681: check predicate 35 |
| 15418 | OPC_Decode, 246, 27, 182, 2, // 10683: decode to VSHRuv4i32 using decoder 310 |
| 15419 | // 10683: } |
| 15420 | // 10683: } // switch Inst[24] |
| 15421 | // 10683: } |
| 15422 | // 10683: } // switch Inst[21] |
| 15423 | // 10683: } |
| 15424 | 1, 85, // 10688: case 0x1: { |
| 15425 | OPC_SwitchField, 21, 1, // 10690: switch Inst[21] { |
| 15426 | 0, 57, // 10693: case 0x0: { |
| 15427 | OPC_SwitchField, 20, 1, // 10695: switch Inst[20] { |
| 15428 | 0, 29, // 10698: case 0x0: { |
| 15429 | OPC_SwitchField, 24, 1, // 10700: switch Inst[24] { |
| 15430 | 0, 11, // 10703: case 0x0: { |
| 15431 | OPC_CheckPredicate, 35, // 10705: check predicate 35 |
| 15432 | OPC_CheckField, 19, 1, 1, // 10707: check Inst[19] == 0x1 |
| 15433 | OPC_Decode, 142, 28, 183, 2, // 10711: decode to VSRAsv16i8 using decoder 311 |
| 15434 | // 10711: } |
| 15435 | 1, 0, // 10716: case 0x1: { |
| 15436 | OPC_CheckPredicate, 35, // 10718: check predicate 35 |
| 15437 | OPC_CheckField, 19, 1, 1, // 10720: check Inst[19] == 0x1 |
| 15438 | OPC_Decode, 150, 28, 183, 2, // 10724: decode to VSRAuv16i8 using decoder 311 |
| 15439 | // 10724: } |
| 15440 | // 10724: } // switch Inst[24] |
| 15441 | // 10724: } |
| 15442 | 1, 0, // 10729: case 0x1: { |
| 15443 | OPC_SwitchField, 24, 1, // 10731: switch Inst[24] { |
| 15444 | 0, 7, // 10734: case 0x0: { |
| 15445 | OPC_CheckPredicate, 35, // 10736: check predicate 35 |
| 15446 | OPC_Decode, 148, 28, 184, 2, // 10738: decode to VSRAsv8i16 using decoder 312 |
| 15447 | // 10738: } |
| 15448 | 1, 0, // 10743: case 0x1: { |
| 15449 | OPC_CheckPredicate, 35, // 10745: check predicate 35 |
| 15450 | OPC_Decode, 156, 28, 184, 2, // 10747: decode to VSRAuv8i16 using decoder 312 |
| 15451 | // 10747: } |
| 15452 | // 10747: } // switch Inst[24] |
| 15453 | // 10747: } |
| 15454 | // 10747: } // switch Inst[20] |
| 15455 | // 10747: } |
| 15456 | 1, 0, // 10752: case 0x1: { |
| 15457 | OPC_SwitchField, 24, 1, // 10754: switch Inst[24] { |
| 15458 | 0, 7, // 10757: case 0x0: { |
| 15459 | OPC_CheckPredicate, 35, // 10759: check predicate 35 |
| 15460 | OPC_Decode, 147, 28, 185, 2, // 10761: decode to VSRAsv4i32 using decoder 313 |
| 15461 | // 10761: } |
| 15462 | 1, 0, // 10766: case 0x1: { |
| 15463 | OPC_CheckPredicate, 35, // 10768: check predicate 35 |
| 15464 | OPC_Decode, 155, 28, 185, 2, // 10770: decode to VSRAuv4i32 using decoder 313 |
| 15465 | // 10770: } |
| 15466 | // 10770: } // switch Inst[24] |
| 15467 | // 10770: } |
| 15468 | // 10770: } // switch Inst[21] |
| 15469 | // 10770: } |
| 15470 | 2, 85, // 10775: case 0x2: { |
| 15471 | OPC_SwitchField, 21, 1, // 10777: switch Inst[21] { |
| 15472 | 0, 57, // 10780: case 0x0: { |
| 15473 | OPC_SwitchField, 20, 1, // 10782: switch Inst[20] { |
| 15474 | 0, 29, // 10785: case 0x0: { |
| 15475 | OPC_SwitchField, 24, 1, // 10787: switch Inst[24] { |
| 15476 | 0, 11, // 10790: case 0x0: { |
| 15477 | OPC_CheckPredicate, 35, // 10792: check predicate 35 |
| 15478 | OPC_CheckField, 19, 1, 1, // 10794: check Inst[19] == 0x1 |
| 15479 | OPC_Decode, 131, 27, 180, 2, // 10798: decode to VRSHRsv16i8 using decoder 308 |
| 15480 | // 10798: } |
| 15481 | 1, 0, // 10803: case 0x1: { |
| 15482 | OPC_CheckPredicate, 35, // 10805: check predicate 35 |
| 15483 | OPC_CheckField, 19, 1, 1, // 10807: check Inst[19] == 0x1 |
| 15484 | OPC_Decode, 139, 27, 180, 2, // 10811: decode to VRSHRuv16i8 using decoder 308 |
| 15485 | // 10811: } |
| 15486 | // 10811: } // switch Inst[24] |
| 15487 | // 10811: } |
| 15488 | 1, 0, // 10816: case 0x1: { |
| 15489 | OPC_SwitchField, 24, 1, // 10818: switch Inst[24] { |
| 15490 | 0, 7, // 10821: case 0x0: { |
| 15491 | OPC_CheckPredicate, 35, // 10823: check predicate 35 |
| 15492 | OPC_Decode, 137, 27, 181, 2, // 10825: decode to VRSHRsv8i16 using decoder 309 |
| 15493 | // 10825: } |
| 15494 | 1, 0, // 10830: case 0x1: { |
| 15495 | OPC_CheckPredicate, 35, // 10832: check predicate 35 |
| 15496 | OPC_Decode, 145, 27, 181, 2, // 10834: decode to VRSHRuv8i16 using decoder 309 |
| 15497 | // 10834: } |
| 15498 | // 10834: } // switch Inst[24] |
| 15499 | // 10834: } |
| 15500 | // 10834: } // switch Inst[20] |
| 15501 | // 10834: } |
| 15502 | 1, 0, // 10839: case 0x1: { |
| 15503 | OPC_SwitchField, 24, 1, // 10841: switch Inst[24] { |
| 15504 | 0, 7, // 10844: case 0x0: { |
| 15505 | OPC_CheckPredicate, 35, // 10846: check predicate 35 |
| 15506 | OPC_Decode, 136, 27, 182, 2, // 10848: decode to VRSHRsv4i32 using decoder 310 |
| 15507 | // 10848: } |
| 15508 | 1, 0, // 10853: case 0x1: { |
| 15509 | OPC_CheckPredicate, 35, // 10855: check predicate 35 |
| 15510 | OPC_Decode, 144, 27, 182, 2, // 10857: decode to VRSHRuv4i32 using decoder 310 |
| 15511 | // 10857: } |
| 15512 | // 10857: } // switch Inst[24] |
| 15513 | // 10857: } |
| 15514 | // 10857: } // switch Inst[21] |
| 15515 | // 10857: } |
| 15516 | 3, 85, // 10862: case 0x3: { |
| 15517 | OPC_SwitchField, 21, 1, // 10864: switch Inst[21] { |
| 15518 | 0, 57, // 10867: case 0x0: { |
| 15519 | OPC_SwitchField, 20, 1, // 10869: switch Inst[20] { |
| 15520 | 0, 29, // 10872: case 0x0: { |
| 15521 | OPC_SwitchField, 24, 1, // 10874: switch Inst[24] { |
| 15522 | 0, 11, // 10877: case 0x0: { |
| 15523 | OPC_CheckPredicate, 35, // 10879: check predicate 35 |
| 15524 | OPC_CheckField, 19, 1, 1, // 10881: check Inst[19] == 0x1 |
| 15525 | OPC_Decode, 157, 27, 183, 2, // 10885: decode to VRSRAsv16i8 using decoder 311 |
| 15526 | // 10885: } |
| 15527 | 1, 0, // 10890: case 0x1: { |
| 15528 | OPC_CheckPredicate, 35, // 10892: check predicate 35 |
| 15529 | OPC_CheckField, 19, 1, 1, // 10894: check Inst[19] == 0x1 |
| 15530 | OPC_Decode, 165, 27, 183, 2, // 10898: decode to VRSRAuv16i8 using decoder 311 |
| 15531 | // 10898: } |
| 15532 | // 10898: } // switch Inst[24] |
| 15533 | // 10898: } |
| 15534 | 1, 0, // 10903: case 0x1: { |
| 15535 | OPC_SwitchField, 24, 1, // 10905: switch Inst[24] { |
| 15536 | 0, 7, // 10908: case 0x0: { |
| 15537 | OPC_CheckPredicate, 35, // 10910: check predicate 35 |
| 15538 | OPC_Decode, 163, 27, 184, 2, // 10912: decode to VRSRAsv8i16 using decoder 312 |
| 15539 | // 10912: } |
| 15540 | 1, 0, // 10917: case 0x1: { |
| 15541 | OPC_CheckPredicate, 35, // 10919: check predicate 35 |
| 15542 | OPC_Decode, 171, 27, 184, 2, // 10921: decode to VRSRAuv8i16 using decoder 312 |
| 15543 | // 10921: } |
| 15544 | // 10921: } // switch Inst[24] |
| 15545 | // 10921: } |
| 15546 | // 10921: } // switch Inst[20] |
| 15547 | // 10921: } |
| 15548 | 1, 0, // 10926: case 0x1: { |
| 15549 | OPC_SwitchField, 24, 1, // 10928: switch Inst[24] { |
| 15550 | 0, 7, // 10931: case 0x0: { |
| 15551 | OPC_CheckPredicate, 35, // 10933: check predicate 35 |
| 15552 | OPC_Decode, 162, 27, 185, 2, // 10935: decode to VRSRAsv4i32 using decoder 313 |
| 15553 | // 10935: } |
| 15554 | 1, 0, // 10940: case 0x1: { |
| 15555 | OPC_CheckPredicate, 35, // 10942: check predicate 35 |
| 15556 | OPC_Decode, 170, 27, 185, 2, // 10944: decode to VRSRAuv4i32 using decoder 313 |
| 15557 | // 10944: } |
| 15558 | // 10944: } // switch Inst[24] |
| 15559 | // 10944: } |
| 15560 | // 10944: } // switch Inst[21] |
| 15561 | // 10944: } |
| 15562 | 4, 51, // 10949: case 0x4: { |
| 15563 | OPC_SwitchField, 21, 1, // 10951: switch Inst[21] { |
| 15564 | 0, 33, // 10954: case 0x0: { |
| 15565 | OPC_SwitchField, 20, 1, // 10956: switch Inst[20] { |
| 15566 | 0, 15, // 10959: case 0x0: { |
| 15567 | OPC_CheckPredicate, 35, // 10961: check predicate 35 |
| 15568 | OPC_CheckField, 24, 1, 1, // 10963: check Inst[24] == 0x1 |
| 15569 | OPC_CheckField, 19, 1, 1, // 10967: check Inst[19] == 0x1 |
| 15570 | OPC_Decode, 158, 28, 183, 2, // 10971: decode to VSRIv16i8 using decoder 311 |
| 15571 | // 10971: } |
| 15572 | 1, 0, // 10976: case 0x1: { |
| 15573 | OPC_CheckPredicate, 35, // 10978: check predicate 35 |
| 15574 | OPC_CheckField, 24, 1, 1, // 10980: check Inst[24] == 0x1 |
| 15575 | OPC_Decode, 164, 28, 184, 2, // 10984: decode to VSRIv8i16 using decoder 312 |
| 15576 | // 10984: } |
| 15577 | // 10984: } // switch Inst[20] |
| 15578 | // 10984: } |
| 15579 | 1, 0, // 10989: case 0x1: { |
| 15580 | OPC_CheckPredicate, 35, // 10991: check predicate 35 |
| 15581 | OPC_CheckField, 24, 1, 1, // 10993: check Inst[24] == 0x1 |
| 15582 | OPC_Decode, 163, 28, 185, 2, // 10997: decode to VSRIv4i32 using decoder 313 |
| 15583 | // 10997: } |
| 15584 | // 10997: } // switch Inst[21] |
| 15585 | // 10997: } |
| 15586 | 5, 85, // 11002: case 0x5: { |
| 15587 | OPC_SwitchField, 21, 1, // 11004: switch Inst[21] { |
| 15588 | 0, 57, // 11007: case 0x0: { |
| 15589 | OPC_SwitchField, 20, 1, // 11009: switch Inst[20] { |
| 15590 | 0, 29, // 11012: case 0x0: { |
| 15591 | OPC_SwitchField, 24, 1, // 11014: switch Inst[24] { |
| 15592 | 0, 11, // 11017: case 0x0: { |
| 15593 | OPC_CheckPredicate, 35, // 11019: check predicate 35 |
| 15594 | OPC_CheckField, 19, 1, 1, // 11021: check Inst[19] == 0x1 |
| 15595 | OPC_Decode, 206, 27, 186, 2, // 11025: decode to VSHLiv16i8 using decoder 314 |
| 15596 | // 11025: } |
| 15597 | 1, 0, // 11030: case 0x1: { |
| 15598 | OPC_CheckPredicate, 35, // 11032: check predicate 35 |
| 15599 | OPC_CheckField, 19, 1, 1, // 11034: check Inst[19] == 0x1 |
| 15600 | OPC_Decode, 255, 27, 187, 2, // 11038: decode to VSLIv16i8 using decoder 315 |
| 15601 | // 11038: } |
| 15602 | // 11038: } // switch Inst[24] |
| 15603 | // 11038: } |
| 15604 | 1, 0, // 11043: case 0x1: { |
| 15605 | OPC_SwitchField, 24, 1, // 11045: switch Inst[24] { |
| 15606 | 0, 7, // 11048: case 0x0: { |
| 15607 | OPC_CheckPredicate, 35, // 11050: check predicate 35 |
| 15608 | OPC_Decode, 212, 27, 188, 2, // 11052: decode to VSHLiv8i16 using decoder 316 |
| 15609 | // 11052: } |
| 15610 | 1, 0, // 11057: case 0x1: { |
| 15611 | OPC_CheckPredicate, 35, // 11059: check predicate 35 |
| 15612 | OPC_Decode, 133, 28, 189, 2, // 11061: decode to VSLIv8i16 using decoder 317 |
| 15613 | // 11061: } |
| 15614 | // 11061: } // switch Inst[24] |
| 15615 | // 11061: } |
| 15616 | // 11061: } // switch Inst[20] |
| 15617 | // 11061: } |
| 15618 | 1, 0, // 11066: case 0x1: { |
| 15619 | OPC_SwitchField, 24, 1, // 11068: switch Inst[24] { |
| 15620 | 0, 7, // 11071: case 0x0: { |
| 15621 | OPC_CheckPredicate, 35, // 11073: check predicate 35 |
| 15622 | OPC_Decode, 211, 27, 190, 2, // 11075: decode to VSHLiv4i32 using decoder 318 |
| 15623 | // 11075: } |
| 15624 | 1, 0, // 11080: case 0x1: { |
| 15625 | OPC_CheckPredicate, 35, // 11082: check predicate 35 |
| 15626 | OPC_Decode, 132, 28, 191, 2, // 11084: decode to VSLIv4i32 using decoder 319 |
| 15627 | // 11084: } |
| 15628 | // 11084: } // switch Inst[24] |
| 15629 | // 11084: } |
| 15630 | // 11084: } // switch Inst[21] |
| 15631 | // 11084: } |
| 15632 | 6, 51, // 11089: case 0x6: { |
| 15633 | OPC_SwitchField, 21, 1, // 11091: switch Inst[21] { |
| 15634 | 0, 33, // 11094: case 0x0: { |
| 15635 | OPC_SwitchField, 20, 1, // 11096: switch Inst[20] { |
| 15636 | 0, 15, // 11099: case 0x0: { |
| 15637 | OPC_CheckPredicate, 35, // 11101: check predicate 35 |
| 15638 | OPC_CheckField, 24, 1, 1, // 11103: check Inst[24] == 0x1 |
| 15639 | OPC_CheckField, 19, 1, 1, // 11107: check Inst[19] == 0x1 |
| 15640 | OPC_Decode, 229, 25, 186, 2, // 11111: decode to VQSHLsuv16i8 using decoder 314 |
| 15641 | // 11111: } |
| 15642 | 1, 0, // 11116: case 0x1: { |
| 15643 | OPC_CheckPredicate, 35, // 11118: check predicate 35 |
| 15644 | OPC_CheckField, 24, 1, 1, // 11120: check Inst[24] == 0x1 |
| 15645 | OPC_Decode, 235, 25, 188, 2, // 11124: decode to VQSHLsuv8i16 using decoder 316 |
| 15646 | // 11124: } |
| 15647 | // 11124: } // switch Inst[20] |
| 15648 | // 11124: } |
| 15649 | 1, 0, // 11129: case 0x1: { |
| 15650 | OPC_CheckPredicate, 35, // 11131: check predicate 35 |
| 15651 | OPC_CheckField, 24, 1, 1, // 11133: check Inst[24] == 0x1 |
| 15652 | OPC_Decode, 234, 25, 190, 2, // 11137: decode to VQSHLsuv4i32 using decoder 318 |
| 15653 | // 11137: } |
| 15654 | // 11137: } // switch Inst[21] |
| 15655 | // 11137: } |
| 15656 | 7, 85, // 11142: case 0x7: { |
| 15657 | OPC_SwitchField, 21, 1, // 11144: switch Inst[21] { |
| 15658 | 0, 57, // 11147: case 0x0: { |
| 15659 | OPC_SwitchField, 20, 1, // 11149: switch Inst[20] { |
| 15660 | 0, 29, // 11152: case 0x0: { |
| 15661 | OPC_SwitchField, 24, 1, // 11154: switch Inst[24] { |
| 15662 | 0, 11, // 11157: case 0x0: { |
| 15663 | OPC_CheckPredicate, 35, // 11159: check predicate 35 |
| 15664 | OPC_CheckField, 19, 1, 1, // 11161: check Inst[19] == 0x1 |
| 15665 | OPC_Decode, 221, 25, 186, 2, // 11165: decode to VQSHLsiv16i8 using decoder 314 |
| 15666 | // 11165: } |
| 15667 | 1, 0, // 11170: case 0x1: { |
| 15668 | OPC_CheckPredicate, 35, // 11172: check predicate 35 |
| 15669 | OPC_CheckField, 19, 1, 1, // 11174: check Inst[19] == 0x1 |
| 15670 | OPC_Decode, 245, 25, 186, 2, // 11178: decode to VQSHLuiv16i8 using decoder 314 |
| 15671 | // 11178: } |
| 15672 | // 11178: } // switch Inst[24] |
| 15673 | // 11178: } |
| 15674 | 1, 0, // 11183: case 0x1: { |
| 15675 | OPC_SwitchField, 24, 1, // 11185: switch Inst[24] { |
| 15676 | 0, 7, // 11188: case 0x0: { |
| 15677 | OPC_CheckPredicate, 35, // 11190: check predicate 35 |
| 15678 | OPC_Decode, 227, 25, 188, 2, // 11192: decode to VQSHLsiv8i16 using decoder 316 |
| 15679 | // 11192: } |
| 15680 | 1, 0, // 11197: case 0x1: { |
| 15681 | OPC_CheckPredicate, 35, // 11199: check predicate 35 |
| 15682 | OPC_Decode, 251, 25, 188, 2, // 11201: decode to VQSHLuiv8i16 using decoder 316 |
| 15683 | // 11201: } |
| 15684 | // 11201: } // switch Inst[24] |
| 15685 | // 11201: } |
| 15686 | // 11201: } // switch Inst[20] |
| 15687 | // 11201: } |
| 15688 | 1, 0, // 11206: case 0x1: { |
| 15689 | OPC_SwitchField, 24, 1, // 11208: switch Inst[24] { |
| 15690 | 0, 7, // 11211: case 0x0: { |
| 15691 | OPC_CheckPredicate, 35, // 11213: check predicate 35 |
| 15692 | OPC_Decode, 226, 25, 190, 2, // 11215: decode to VQSHLsiv4i32 using decoder 318 |
| 15693 | // 11215: } |
| 15694 | 1, 0, // 11220: case 0x1: { |
| 15695 | OPC_CheckPredicate, 35, // 11222: check predicate 35 |
| 15696 | OPC_Decode, 250, 25, 190, 2, // 11224: decode to VQSHLuiv4i32 using decoder 318 |
| 15697 | // 11224: } |
| 15698 | // 11224: } // switch Inst[24] |
| 15699 | // 11224: } |
| 15700 | // 11224: } // switch Inst[21] |
| 15701 | // 11224: } |
| 15702 | 8, 85, // 11229: case 0x8: { |
| 15703 | OPC_SwitchField, 21, 1, // 11231: switch Inst[21] { |
| 15704 | 0, 57, // 11234: case 0x0: { |
| 15705 | OPC_SwitchField, 20, 1, // 11236: switch Inst[20] { |
| 15706 | 0, 29, // 11239: case 0x0: { |
| 15707 | OPC_SwitchField, 24, 1, // 11241: switch Inst[24] { |
| 15708 | 0, 11, // 11244: case 0x0: { |
| 15709 | OPC_CheckPredicate, 35, // 11246: check predicate 35 |
| 15710 | OPC_CheckField, 19, 1, 1, // 11248: check Inst[19] == 0x1 |
| 15711 | OPC_Decode, 130, 27, 168, 2, // 11252: decode to VRSHRNv8i8 using decoder 296 |
| 15712 | // 11252: } |
| 15713 | 1, 0, // 11257: case 0x1: { |
| 15714 | OPC_CheckPredicate, 35, // 11259: check predicate 35 |
| 15715 | OPC_CheckField, 19, 1, 1, // 11261: check Inst[19] == 0x1 |
| 15716 | OPC_Decode, 220, 25, 168, 2, // 11265: decode to VQRSHRUNv8i8 using decoder 296 |
| 15717 | // 11265: } |
| 15718 | // 11265: } // switch Inst[24] |
| 15719 | // 11265: } |
| 15720 | 1, 0, // 11270: case 0x1: { |
| 15721 | OPC_SwitchField, 24, 1, // 11272: switch Inst[24] { |
| 15722 | 0, 7, // 11275: case 0x0: { |
| 15723 | OPC_CheckPredicate, 35, // 11277: check predicate 35 |
| 15724 | OPC_Decode, 129, 27, 169, 2, // 11279: decode to VRSHRNv4i16 using decoder 297 |
| 15725 | // 11279: } |
| 15726 | 1, 0, // 11284: case 0x1: { |
| 15727 | OPC_CheckPredicate, 35, // 11286: check predicate 35 |
| 15728 | OPC_Decode, 219, 25, 169, 2, // 11288: decode to VQRSHRUNv4i16 using decoder 297 |
| 15729 | // 11288: } |
| 15730 | // 11288: } // switch Inst[24] |
| 15731 | // 11288: } |
| 15732 | // 11288: } // switch Inst[20] |
| 15733 | // 11288: } |
| 15734 | 1, 0, // 11293: case 0x1: { |
| 15735 | OPC_SwitchField, 24, 1, // 11295: switch Inst[24] { |
| 15736 | 0, 7, // 11298: case 0x0: { |
| 15737 | OPC_CheckPredicate, 35, // 11300: check predicate 35 |
| 15738 | OPC_Decode, 128, 27, 170, 2, // 11302: decode to VRSHRNv2i32 using decoder 298 |
| 15739 | // 11302: } |
| 15740 | 1, 0, // 11307: case 0x1: { |
| 15741 | OPC_CheckPredicate, 35, // 11309: check predicate 35 |
| 15742 | OPC_Decode, 218, 25, 170, 2, // 11311: decode to VQRSHRUNv2i32 using decoder 298 |
| 15743 | // 11311: } |
| 15744 | // 11311: } // switch Inst[24] |
| 15745 | // 11311: } |
| 15746 | // 11311: } // switch Inst[21] |
| 15747 | // 11311: } |
| 15748 | 9, 85, // 11316: case 0x9: { |
| 15749 | OPC_SwitchField, 21, 1, // 11318: switch Inst[21] { |
| 15750 | 0, 57, // 11321: case 0x0: { |
| 15751 | OPC_SwitchField, 20, 1, // 11323: switch Inst[20] { |
| 15752 | 0, 29, // 11326: case 0x0: { |
| 15753 | OPC_SwitchField, 24, 1, // 11328: switch Inst[24] { |
| 15754 | 0, 11, // 11331: case 0x0: { |
| 15755 | OPC_CheckPredicate, 35, // 11333: check predicate 35 |
| 15756 | OPC_CheckField, 19, 1, 1, // 11335: check Inst[19] == 0x1 |
| 15757 | OPC_Decode, 214, 25, 168, 2, // 11339: decode to VQRSHRNsv8i8 using decoder 296 |
| 15758 | // 11339: } |
| 15759 | 1, 0, // 11344: case 0x1: { |
| 15760 | OPC_CheckPredicate, 35, // 11346: check predicate 35 |
| 15761 | OPC_CheckField, 19, 1, 1, // 11348: check Inst[19] == 0x1 |
| 15762 | OPC_Decode, 217, 25, 168, 2, // 11352: decode to VQRSHRNuv8i8 using decoder 296 |
| 15763 | // 11352: } |
| 15764 | // 11352: } // switch Inst[24] |
| 15765 | // 11352: } |
| 15766 | 1, 0, // 11357: case 0x1: { |
| 15767 | OPC_SwitchField, 24, 1, // 11359: switch Inst[24] { |
| 15768 | 0, 7, // 11362: case 0x0: { |
| 15769 | OPC_CheckPredicate, 35, // 11364: check predicate 35 |
| 15770 | OPC_Decode, 213, 25, 169, 2, // 11366: decode to VQRSHRNsv4i16 using decoder 297 |
| 15771 | // 11366: } |
| 15772 | 1, 0, // 11371: case 0x1: { |
| 15773 | OPC_CheckPredicate, 35, // 11373: check predicate 35 |
| 15774 | OPC_Decode, 216, 25, 169, 2, // 11375: decode to VQRSHRNuv4i16 using decoder 297 |
| 15775 | // 11375: } |
| 15776 | // 11375: } // switch Inst[24] |
| 15777 | // 11375: } |
| 15778 | // 11375: } // switch Inst[20] |
| 15779 | // 11375: } |
| 15780 | 1, 0, // 11380: case 0x1: { |
| 15781 | OPC_SwitchField, 24, 1, // 11382: switch Inst[24] { |
| 15782 | 0, 7, // 11385: case 0x0: { |
| 15783 | OPC_CheckPredicate, 35, // 11387: check predicate 35 |
| 15784 | OPC_Decode, 212, 25, 170, 2, // 11389: decode to VQRSHRNsv2i32 using decoder 298 |
| 15785 | // 11389: } |
| 15786 | 1, 0, // 11394: case 0x1: { |
| 15787 | OPC_CheckPredicate, 35, // 11396: check predicate 35 |
| 15788 | OPC_Decode, 215, 25, 170, 2, // 11398: decode to VQRSHRNuv2i32 using decoder 298 |
| 15789 | // 11398: } |
| 15790 | // 11398: } // switch Inst[24] |
| 15791 | // 11398: } |
| 15792 | // 11398: } // switch Inst[21] |
| 15793 | // 11398: } |
| 15794 | 12, 21, // 11403: case 0xc: { |
| 15795 | OPC_SwitchField, 24, 1, // 11405: switch Inst[24] { |
| 15796 | 0, 7, // 11408: case 0x0: { |
| 15797 | OPC_CheckPredicate, 36, // 11410: check predicate 36 |
| 15798 | OPC_Decode, 133, 19, 192, 2, // 11412: decode to VCVTxs2hq using decoder 320 |
| 15799 | // 11412: } |
| 15800 | 1, 0, // 11417: case 0x1: { |
| 15801 | OPC_CheckPredicate, 36, // 11419: check predicate 36 |
| 15802 | OPC_Decode, 137, 19, 192, 2, // 11421: decode to VCVTxu2hq using decoder 320 |
| 15803 | // 11421: } |
| 15804 | // 11421: } // switch Inst[24] |
| 15805 | // 11421: } |
| 15806 | 13, 21, // 11426: case 0xd: { |
| 15807 | OPC_SwitchField, 24, 1, // 11428: switch Inst[24] { |
| 15808 | 0, 7, // 11431: case 0x0: { |
| 15809 | OPC_CheckPredicate, 36, // 11433: check predicate 36 |
| 15810 | OPC_Decode, 247, 18, 192, 2, // 11435: decode to VCVTh2xsq using decoder 320 |
| 15811 | // 11435: } |
| 15812 | 1, 0, // 11440: case 0x1: { |
| 15813 | OPC_CheckPredicate, 36, // 11442: check predicate 36 |
| 15814 | OPC_Decode, 249, 18, 192, 2, // 11444: decode to VCVTh2xuq using decoder 320 |
| 15815 | // 11444: } |
| 15816 | // 11444: } // switch Inst[24] |
| 15817 | // 11444: } |
| 15818 | 14, 52, // 11449: case 0xe: { |
| 15819 | OPC_Scope, 29, // 11451: try { |
| 15820 | OPC_SwitchField, 5, 1, // 11453: switch Inst[5] { |
| 15821 | 0, 11, // 11456: case 0x0: { |
| 15822 | OPC_CheckPredicate, 35, // 11458: check predicate 35 |
| 15823 | OPC_CheckField, 19, 3, 0, // 11460: check Inst[21:19] == 0x0 |
| 15824 | OPC_Decode, 222, 23, 175, 2, // 11464: decode to VMOVv16i8 using decoder 303 |
| 15825 | // 11464: } |
| 15826 | 1, 0, // 11469: case 0x1: { |
| 15827 | OPC_CheckPredicate, 35, // 11471: check predicate 35 |
| 15828 | OPC_CheckField, 19, 3, 0, // 11473: check Inst[21:19] == 0x0 |
| 15829 | OPC_Decode, 226, 23, 175, 2, // 11477: decode to VMOVv2i64 using decoder 303 |
| 15830 | // 11477: } |
| 15831 | // 11477: } // switch Inst[5] |
| 15832 | // 11477: } else try { |
| 15833 | OPC_SwitchField, 24, 1, // 11482: switch Inst[24] { |
| 15834 | 0, 7, // 11485: case 0x0: { |
| 15835 | OPC_CheckPredicate, 35, // 11487: check predicate 35 |
| 15836 | OPC_Decode, 131, 19, 192, 2, // 11489: decode to VCVTxs2fq using decoder 320 |
| 15837 | // 11489: } |
| 15838 | 1, 0, // 11494: case 0x1: { |
| 15839 | OPC_CheckPredicate, 35, // 11496: check predicate 35 |
| 15840 | OPC_Decode, 135, 19, 192, 2, // 11498: decode to VCVTxu2fq using decoder 320 |
| 15841 | // 11498: } |
| 15842 | // 11498: } // switch Inst[24] |
| 15843 | // 11498: } |
| 15844 | // 11498: } |
| 15845 | 15, 0, // 11503: case 0xf: { |
| 15846 | OPC_Scope, 21, // 11505: try { |
| 15847 | OPC_SwitchField, 24, 1, // 11507: switch Inst[24] { |
| 15848 | 0, 7, // 11510: case 0x0: { |
| 15849 | OPC_CheckPredicate, 35, // 11512: check predicate 35 |
| 15850 | OPC_Decode, 238, 18, 192, 2, // 11514: decode to VCVTf2xsq using decoder 320 |
| 15851 | // 11514: } |
| 15852 | 1, 0, // 11519: case 0x1: { |
| 15853 | OPC_CheckPredicate, 35, // 11521: check predicate 35 |
| 15854 | OPC_Decode, 240, 18, 192, 2, // 11523: decode to VCVTf2xuq using decoder 320 |
| 15855 | // 11523: } |
| 15856 | // 11523: } // switch Inst[24] |
| 15857 | // 11523: } else try { |
| 15858 | OPC_CheckPredicate, 35, // 11528: check predicate 35 |
| 15859 | OPC_CheckField, 19, 3, 0, // 11530: check Inst[21:19] == 0x0 |
| 15860 | OPC_CheckField, 5, 1, 0, // 11534: check Inst[5] == 0x0 |
| 15861 | OPC_Decode, 227, 23, 175, 2, // 11538: decode to VMOVv4f32 using decoder 303 |
| 15862 | // 11538: } |
| 15863 | // 11538: } |
| 15864 | // 11538: } // switch Inst[11:8] |
| 15865 | // 11538: } else try { |
| 15866 | OPC_SwitchField, 5, 1, // 11543: switch Inst[5] { |
| 15867 | 0, 56, // 11546: case 0x0: { |
| 15868 | OPC_CheckField, 19, 3, 0, // 11548: check Inst[21:19] == 0x0 |
| 15869 | OPC_Scope, 43, // 11552: try { |
| 15870 | OPC_SwitchField, 8, 1, // 11554: switch Inst[8] { |
| 15871 | 0, 11, // 11557: case 0x0: { |
| 15872 | OPC_CheckPredicate, 35, // 11559: check predicate 35 |
| 15873 | OPC_CheckField, 10, 2, 2, // 11561: check Inst[11:10] == 0x2 |
| 15874 | OPC_Decode, 230, 23, 175, 2, // 11565: decode to VMOVv8i16 using decoder 303 |
| 15875 | // 11565: } |
| 15876 | 1, 0, // 11570: case 0x1: { |
| 15877 | OPC_SwitchField, 11, 1, // 11572: switch Inst[11] { |
| 15878 | 0, 7, // 11575: case 0x0: { |
| 15879 | OPC_CheckPredicate, 35, // 11577: check predicate 35 |
| 15880 | OPC_Decode, 195, 24, 175, 2, // 11579: decode to VORRiv4i32 using decoder 303 |
| 15881 | // 11579: } |
| 15882 | 1, 0, // 11584: case 0x1: { |
| 15883 | OPC_CheckPredicate, 35, // 11586: check predicate 35 |
| 15884 | OPC_CheckField, 10, 1, 0, // 11588: check Inst[10] == 0x0 |
| 15885 | OPC_Decode, 196, 24, 175, 2, // 11592: decode to VORRiv8i16 using decoder 303 |
| 15886 | // 11592: } |
| 15887 | // 11592: } // switch Inst[11] |
| 15888 | // 11592: } |
| 15889 | // 11592: } // switch Inst[8] |
| 15890 | // 11592: } else try { |
| 15891 | OPC_CheckPredicate, 35, // 11597: check predicate 35 |
| 15892 | OPC_Decode, 229, 23, 175, 2, // 11599: decode to VMOVv4i32 using decoder 303 |
| 15893 | // 11599: } |
| 15894 | // 11599: } |
| 15895 | 1, 0, // 11604: case 0x1: { |
| 15896 | OPC_CheckField, 19, 3, 0, // 11606: check Inst[21:19] == 0x0 |
| 15897 | OPC_Scope, 43, // 11610: try { |
| 15898 | OPC_SwitchField, 8, 1, // 11612: switch Inst[8] { |
| 15899 | 0, 11, // 11615: case 0x0: { |
| 15900 | OPC_CheckPredicate, 35, // 11617: check predicate 35 |
| 15901 | OPC_CheckField, 10, 2, 2, // 11619: check Inst[11:10] == 0x2 |
| 15902 | OPC_Decode, 167, 24, 175, 2, // 11623: decode to VMVNv8i16 using decoder 303 |
| 15903 | // 11623: } |
| 15904 | 1, 0, // 11628: case 0x1: { |
| 15905 | OPC_SwitchField, 11, 1, // 11630: switch Inst[11] { |
| 15906 | 0, 7, // 11633: case 0x0: { |
| 15907 | OPC_CheckPredicate, 35, // 11635: check predicate 35 |
| 15908 | OPC_Decode, 153, 17, 175, 2, // 11637: decode to VBICiv4i32 using decoder 303 |
| 15909 | // 11637: } |
| 15910 | 1, 0, // 11642: case 0x1: { |
| 15911 | OPC_CheckPredicate, 35, // 11644: check predicate 35 |
| 15912 | OPC_CheckField, 10, 1, 0, // 11646: check Inst[10] == 0x0 |
| 15913 | OPC_Decode, 154, 17, 175, 2, // 11650: decode to VBICiv8i16 using decoder 303 |
| 15914 | // 11650: } |
| 15915 | // 11650: } // switch Inst[11] |
| 15916 | // 11650: } |
| 15917 | // 11650: } // switch Inst[8] |
| 15918 | // 11650: } else try { |
| 15919 | OPC_CheckPredicate, 35, // 11655: check predicate 35 |
| 15920 | OPC_Decode, 166, 24, 175, 2, // 11657: decode to VMVNv4i32 using decoder 303 |
| 15921 | // 11657: } |
| 15922 | // 11657: } |
| 15923 | // 11657: } // switch Inst[5] |
| 15924 | // 11657: } |
| 15925 | // 11657: } |
| 15926 | 1, 0, // 11662: case 0x1: { |
| 15927 | OPC_SwitchField, 8, 4, // 11664: switch Inst[11:8] { |
| 15928 | 0, 23, // 11667: case 0x0: { |
| 15929 | OPC_SwitchField, 24, 8, // 11669: switch Inst[31:24] { |
| 15930 | 242, 1, 7, // 11672: case 0xf2: { |
| 15931 | OPC_CheckPredicate, 35, // 11675: check predicate 35 |
| 15932 | OPC_Decode, 236, 27, 193, 2, // 11677: decode to VSHRsv2i64 using decoder 321 |
| 15933 | // 11677: } |
| 15934 | 243, 1, 0, // 11682: case 0xf3: { |
| 15935 | OPC_CheckPredicate, 35, // 11685: check predicate 35 |
| 15936 | OPC_Decode, 244, 27, 193, 2, // 11687: decode to VSHRuv2i64 using decoder 321 |
| 15937 | // 11687: } |
| 15938 | // 11687: } // switch Inst[31:24] |
| 15939 | // 11687: } |
| 15940 | 1, 23, // 11692: case 0x1: { |
| 15941 | OPC_SwitchField, 24, 8, // 11694: switch Inst[31:24] { |
| 15942 | 242, 1, 7, // 11697: case 0xf2: { |
| 15943 | OPC_CheckPredicate, 35, // 11700: check predicate 35 |
| 15944 | OPC_Decode, 145, 28, 194, 2, // 11702: decode to VSRAsv2i64 using decoder 322 |
| 15945 | // 11702: } |
| 15946 | 243, 1, 0, // 11707: case 0xf3: { |
| 15947 | OPC_CheckPredicate, 35, // 11710: check predicate 35 |
| 15948 | OPC_Decode, 153, 28, 194, 2, // 11712: decode to VSRAuv2i64 using decoder 322 |
| 15949 | // 11712: } |
| 15950 | // 11712: } // switch Inst[31:24] |
| 15951 | // 11712: } |
| 15952 | 2, 23, // 11717: case 0x2: { |
| 15953 | OPC_SwitchField, 24, 8, // 11719: switch Inst[31:24] { |
| 15954 | 242, 1, 7, // 11722: case 0xf2: { |
| 15955 | OPC_CheckPredicate, 35, // 11725: check predicate 35 |
| 15956 | OPC_Decode, 134, 27, 193, 2, // 11727: decode to VRSHRsv2i64 using decoder 321 |
| 15957 | // 11727: } |
| 15958 | 243, 1, 0, // 11732: case 0xf3: { |
| 15959 | OPC_CheckPredicate, 35, // 11735: check predicate 35 |
| 15960 | OPC_Decode, 142, 27, 193, 2, // 11737: decode to VRSHRuv2i64 using decoder 321 |
| 15961 | // 11737: } |
| 15962 | // 11737: } // switch Inst[31:24] |
| 15963 | // 11737: } |
| 15964 | 3, 23, // 11742: case 0x3: { |
| 15965 | OPC_SwitchField, 24, 8, // 11744: switch Inst[31:24] { |
| 15966 | 242, 1, 7, // 11747: case 0xf2: { |
| 15967 | OPC_CheckPredicate, 35, // 11750: check predicate 35 |
| 15968 | OPC_Decode, 160, 27, 194, 2, // 11752: decode to VRSRAsv2i64 using decoder 322 |
| 15969 | // 11752: } |
| 15970 | 243, 1, 0, // 11757: case 0xf3: { |
| 15971 | OPC_CheckPredicate, 35, // 11760: check predicate 35 |
| 15972 | OPC_Decode, 168, 27, 194, 2, // 11762: decode to VRSRAuv2i64 using decoder 322 |
| 15973 | // 11762: } |
| 15974 | // 11762: } // switch Inst[31:24] |
| 15975 | // 11762: } |
| 15976 | 4, 12, // 11767: case 0x4: { |
| 15977 | OPC_CheckPredicate, 35, // 11769: check predicate 35 |
| 15978 | OPC_CheckField, 24, 8, 243, 1, // 11771: check Inst[31:24] == 0xf3 |
| 15979 | OPC_Decode, 161, 28, 194, 2, // 11776: decode to VSRIv2i64 using decoder 322 |
| 15980 | // 11776: } |
| 15981 | 5, 23, // 11781: case 0x5: { |
| 15982 | OPC_SwitchField, 24, 8, // 11783: switch Inst[31:24] { |
| 15983 | 242, 1, 7, // 11786: case 0xf2: { |
| 15984 | OPC_CheckPredicate, 35, // 11789: check predicate 35 |
| 15985 | OPC_Decode, 209, 27, 195, 2, // 11791: decode to VSHLiv2i64 using decoder 323 |
| 15986 | // 11791: } |
| 15987 | 243, 1, 0, // 11796: case 0xf3: { |
| 15988 | OPC_CheckPredicate, 35, // 11799: check predicate 35 |
| 15989 | OPC_Decode, 130, 28, 196, 2, // 11801: decode to VSLIv2i64 using decoder 324 |
| 15990 | // 11801: } |
| 15991 | // 11801: } // switch Inst[31:24] |
| 15992 | // 11801: } |
| 15993 | 6, 12, // 11806: case 0x6: { |
| 15994 | OPC_CheckPredicate, 35, // 11808: check predicate 35 |
| 15995 | OPC_CheckField, 24, 8, 243, 1, // 11810: check Inst[31:24] == 0xf3 |
| 15996 | OPC_Decode, 232, 25, 195, 2, // 11815: decode to VQSHLsuv2i64 using decoder 323 |
| 15997 | // 11815: } |
| 15998 | 7, 0, // 11820: case 0x7: { |
| 15999 | OPC_SwitchField, 24, 8, // 11822: switch Inst[31:24] { |
| 16000 | 242, 1, 7, // 11825: case 0xf2: { |
| 16001 | OPC_CheckPredicate, 35, // 11828: check predicate 35 |
| 16002 | OPC_Decode, 224, 25, 195, 2, // 11830: decode to VQSHLsiv2i64 using decoder 323 |
| 16003 | // 11830: } |
| 16004 | 243, 1, 0, // 11835: case 0xf3: { |
| 16005 | OPC_CheckPredicate, 35, // 11838: check predicate 35 |
| 16006 | OPC_Decode, 248, 25, 195, 2, // 11840: decode to VQSHLuiv2i64 using decoder 323 |
| 16007 | // 11840: } |
| 16008 | // 11840: } // switch Inst[31:24] |
| 16009 | // 11840: } |
| 16010 | // 11840: } // switch Inst[11:8] |
| 16011 | // 11840: } |
| 16012 | // 11840: } // switch Inst[7] |
| 16013 | // 11840: } |
| 16014 | // 11840: } // switch Inst[23] |
| 16015 | // 11840: } |
| 16016 | // 11840: } // switch Inst[6] |
| 16017 | // 11840: } |
| 16018 | // 11840: } // switch Inst[4] |
| 16019 | }; |
| 16020 | static const uint8_t DecoderTableNEONDup32[279] = { |
| 16021 | OPC_SwitchField, 22, 6, // 0: switch Inst[27:22] { |
| 16022 | 56, 73, // 3: case 0x38: { |
| 16023 | OPC_SwitchField, 0, 6, // 5: switch Inst[5:0] { |
| 16024 | 16, 37, // 8: case 0x10: { |
| 16025 | OPC_SwitchField, 20, 1, // 10: switch Inst[20] { |
| 16026 | 0, 15, // 13: case 0x0: { |
| 16027 | OPC_CheckPredicate, 42, // 15: check predicate 42 |
| 16028 | OPC_CheckField, 8, 4, 11, // 17: check Inst[11:8] == 0xb |
| 16029 | OPC_CheckField, 6, 1, 0, // 21: check Inst[6] == 0x0 |
| 16030 | OPC_Decode, 195, 27, 197, 2, // 25: decode to VSETLNi32 using decoder 325 |
| 16031 | // 25: } |
| 16032 | 1, 0, // 30: case 0x1: { |
| 16033 | OPC_CheckPredicate, 43, // 32: check predicate 43 |
| 16034 | OPC_CheckField, 8, 4, 11, // 34: check Inst[11:8] == 0xb |
| 16035 | OPC_CheckField, 6, 1, 0, // 38: check Inst[6] == 0x0 |
| 16036 | OPC_Decode, 196, 19, 198, 2, // 42: decode to VGETLNi32 using decoder 326 |
| 16037 | // 42: } |
| 16038 | // 42: } // switch Inst[20] |
| 16039 | // 42: } |
| 16040 | 48, 0, // 47: case 0x30: { |
| 16041 | OPC_SwitchField, 20, 1, // 49: switch Inst[20] { |
| 16042 | 0, 11, // 52: case 0x0: { |
| 16043 | OPC_CheckPredicate, 35, // 54: check predicate 35 |
| 16044 | OPC_CheckField, 8, 4, 11, // 56: check Inst[11:8] == 0xb |
| 16045 | OPC_Decode, 194, 27, 199, 2, // 60: decode to VSETLNi16 using decoder 327 |
| 16046 | // 60: } |
| 16047 | 1, 0, // 65: case 0x1: { |
| 16048 | OPC_CheckPredicate, 35, // 67: check predicate 35 |
| 16049 | OPC_CheckField, 8, 4, 11, // 69: check Inst[11:8] == 0xb |
| 16050 | OPC_Decode, 197, 19, 200, 2, // 73: decode to VGETLNs16 using decoder 328 |
| 16051 | // 73: } |
| 16052 | // 73: } // switch Inst[20] |
| 16053 | // 73: } |
| 16054 | // 73: } // switch Inst[5:0] |
| 16055 | // 73: } |
| 16056 | 57, 37, // 78: case 0x39: { |
| 16057 | OPC_SwitchField, 20, 1, // 80: switch Inst[20] { |
| 16058 | 0, 15, // 83: case 0x0: { |
| 16059 | OPC_CheckPredicate, 35, // 85: check predicate 35 |
| 16060 | OPC_CheckField, 8, 4, 11, // 87: check Inst[11:8] == 0xb |
| 16061 | OPC_CheckField, 0, 5, 16, // 91: check Inst[4:0] == 0x10 |
| 16062 | OPC_Decode, 196, 27, 201, 2, // 95: decode to VSETLNi8 using decoder 329 |
| 16063 | // 95: } |
| 16064 | 1, 0, // 100: case 0x1: { |
| 16065 | OPC_CheckPredicate, 35, // 102: check predicate 35 |
| 16066 | OPC_CheckField, 8, 4, 11, // 104: check Inst[11:8] == 0xb |
| 16067 | OPC_CheckField, 0, 5, 16, // 108: check Inst[4:0] == 0x10 |
| 16068 | OPC_Decode, 198, 19, 202, 2, // 112: decode to VGETLNs8 using decoder 330 |
| 16069 | // 112: } |
| 16070 | // 112: } // switch Inst[20] |
| 16071 | // 112: } |
| 16072 | 58, 99, // 117: case 0x3a: { |
| 16073 | OPC_SwitchField, 0, 6, // 119: switch Inst[5:0] { |
| 16074 | 16, 37, // 122: case 0x10: { |
| 16075 | OPC_SwitchField, 20, 2, // 124: switch Inst[21:20] { |
| 16076 | 0, 15, // 127: case 0x0: { |
| 16077 | OPC_CheckPredicate, 35, // 129: check predicate 35 |
| 16078 | OPC_CheckField, 8, 4, 11, // 131: check Inst[11:8] == 0xb |
| 16079 | OPC_CheckField, 6, 1, 0, // 135: check Inst[6] == 0x0 |
| 16080 | OPC_Decode, 143, 19, 203, 2, // 139: decode to VDUP32d using decoder 331 |
| 16081 | // 139: } |
| 16082 | 2, 0, // 144: case 0x2: { |
| 16083 | OPC_CheckPredicate, 35, // 146: check predicate 35 |
| 16084 | OPC_CheckField, 8, 4, 11, // 148: check Inst[11:8] == 0xb |
| 16085 | OPC_CheckField, 6, 1, 0, // 152: check Inst[6] == 0x0 |
| 16086 | OPC_Decode, 144, 19, 204, 2, // 156: decode to VDUP32q using decoder 332 |
| 16087 | // 156: } |
| 16088 | // 156: } // switch Inst[21:20] |
| 16089 | // 156: } |
| 16090 | 48, 0, // 161: case 0x30: { |
| 16091 | OPC_SwitchField, 20, 1, // 163: switch Inst[20] { |
| 16092 | 0, 37, // 166: case 0x0: { |
| 16093 | OPC_SwitchField, 21, 1, // 168: switch Inst[21] { |
| 16094 | 0, 15, // 171: case 0x0: { |
| 16095 | OPC_CheckPredicate, 35, // 173: check predicate 35 |
| 16096 | OPC_CheckField, 8, 4, 11, // 175: check Inst[11:8] == 0xb |
| 16097 | OPC_CheckField, 6, 1, 0, // 179: check Inst[6] == 0x0 |
| 16098 | OPC_Decode, 141, 19, 203, 2, // 183: decode to VDUP16d using decoder 331 |
| 16099 | // 183: } |
| 16100 | 1, 0, // 188: case 0x1: { |
| 16101 | OPC_CheckPredicate, 35, // 190: check predicate 35 |
| 16102 | OPC_CheckField, 8, 4, 11, // 192: check Inst[11:8] == 0xb |
| 16103 | OPC_CheckField, 6, 1, 0, // 196: check Inst[6] == 0x0 |
| 16104 | OPC_Decode, 142, 19, 204, 2, // 200: decode to VDUP16q using decoder 332 |
| 16105 | // 200: } |
| 16106 | // 200: } // switch Inst[21] |
| 16107 | // 200: } |
| 16108 | 1, 0, // 205: case 0x1: { |
| 16109 | OPC_CheckPredicate, 35, // 207: check predicate 35 |
| 16110 | OPC_CheckField, 8, 4, 11, // 209: check Inst[11:8] == 0xb |
| 16111 | OPC_Decode, 199, 19, 200, 2, // 213: decode to VGETLNu16 using decoder 328 |
| 16112 | // 213: } |
| 16113 | // 213: } // switch Inst[20] |
| 16114 | // 213: } |
| 16115 | // 213: } // switch Inst[5:0] |
| 16116 | // 213: } |
| 16117 | 59, 0, // 218: case 0x3b: { |
| 16118 | OPC_SwitchField, 20, 1, // 220: switch Inst[20] { |
| 16119 | 0, 37, // 223: case 0x0: { |
| 16120 | OPC_SwitchField, 21, 1, // 225: switch Inst[21] { |
| 16121 | 0, 15, // 228: case 0x0: { |
| 16122 | OPC_CheckPredicate, 35, // 230: check predicate 35 |
| 16123 | OPC_CheckField, 8, 4, 11, // 232: check Inst[11:8] == 0xb |
| 16124 | OPC_CheckField, 0, 7, 16, // 236: check Inst[6:0] == 0x10 |
| 16125 | OPC_Decode, 145, 19, 203, 2, // 240: decode to VDUP8d using decoder 331 |
| 16126 | // 240: } |
| 16127 | 1, 0, // 245: case 0x1: { |
| 16128 | OPC_CheckPredicate, 35, // 247: check predicate 35 |
| 16129 | OPC_CheckField, 8, 4, 11, // 249: check Inst[11:8] == 0xb |
| 16130 | OPC_CheckField, 0, 7, 16, // 253: check Inst[6:0] == 0x10 |
| 16131 | OPC_Decode, 146, 19, 204, 2, // 257: decode to VDUP8q using decoder 332 |
| 16132 | // 257: } |
| 16133 | // 257: } // switch Inst[21] |
| 16134 | // 257: } |
| 16135 | 1, 0, // 262: case 0x1: { |
| 16136 | OPC_CheckPredicate, 35, // 264: check predicate 35 |
| 16137 | OPC_CheckField, 8, 4, 11, // 266: check Inst[11:8] == 0xb |
| 16138 | OPC_CheckField, 0, 5, 16, // 270: check Inst[4:0] == 0x10 |
| 16139 | OPC_Decode, 200, 19, 202, 2, // 274: decode to VGETLNu8 using decoder 330 |
| 16140 | // 274: } |
| 16141 | // 274: } // switch Inst[20] |
| 16142 | // 274: } |
| 16143 | // 274: } // switch Inst[27:22] |
| 16144 | }; |
| 16145 | static const uint8_t DecoderTableNEONLoadStore32[4440] = { |
| 16146 | OPC_SwitchField, 8, 4, // 0: switch Inst[11:8] { |
| 16147 | 0, 211, 1, // 3: case 0x0: { |
| 16148 | OPC_SwitchField, 20, 2, // 6: switch Inst[21:20] { |
| 16149 | 0, 102, // 9: case 0x0: { |
| 16150 | OPC_SwitchField, 23, 9, // 11: switch Inst[31:23] { |
| 16151 | 232, 3, 69, // 14: case 0x1e8: { |
| 16152 | OPC_SwitchField, 6, 2, // 17: switch Inst[7:6] { |
| 16153 | 0, 20, // 20: case 0x0: { |
| 16154 | OPC_Scope, 11, // 22: try { |
| 16155 | OPC_CheckField, 0, 4, 15, // 24: check Inst[3:0] == 0xf |
| 16156 | OPC_CheckPredicate, 35, // 28: check predicate 35 |
| 16157 | OPC_Decode, 149, 30, 205, 2, // 30: decode to VST4d8 using decoder 333 |
| 16158 | // 30: } else try { |
| 16159 | OPC_CheckPredicate, 35, // 35: check predicate 35 |
| 16160 | OPC_Decode, 152, 30, 205, 2, // 37: decode to VST4d8_UPD using decoder 333 |
| 16161 | // 37: } |
| 16162 | // 37: } |
| 16163 | 1, 20, // 42: case 0x1: { |
| 16164 | OPC_Scope, 11, // 44: try { |
| 16165 | OPC_CheckField, 0, 4, 15, // 46: check Inst[3:0] == 0xf |
| 16166 | OPC_CheckPredicate, 35, // 50: check predicate 35 |
| 16167 | OPC_Decode, 141, 30, 205, 2, // 52: decode to VST4d16 using decoder 333 |
| 16168 | // 52: } else try { |
| 16169 | OPC_CheckPredicate, 35, // 57: check predicate 35 |
| 16170 | OPC_Decode, 144, 30, 205, 2, // 59: decode to VST4d16_UPD using decoder 333 |
| 16171 | // 59: } |
| 16172 | // 59: } |
| 16173 | 2, 0, // 64: case 0x2: { |
| 16174 | OPC_Scope, 11, // 66: try { |
| 16175 | OPC_CheckField, 0, 4, 15, // 68: check Inst[3:0] == 0xf |
| 16176 | OPC_CheckPredicate, 35, // 72: check predicate 35 |
| 16177 | OPC_Decode, 145, 30, 205, 2, // 74: decode to VST4d32 using decoder 333 |
| 16178 | // 74: } else try { |
| 16179 | OPC_CheckPredicate, 35, // 79: check predicate 35 |
| 16180 | OPC_Decode, 148, 30, 205, 2, // 81: decode to VST4d32_UPD using decoder 333 |
| 16181 | // 81: } |
| 16182 | // 81: } |
| 16183 | // 81: } // switch Inst[7:6] |
| 16184 | // 81: } |
| 16185 | 233, 3, 0, // 86: case 0x1e9: { |
| 16186 | OPC_CheckField, 4, 1, 0, // 89: check Inst[4] == 0x0 |
| 16187 | OPC_Scope, 11, // 93: try { |
| 16188 | OPC_CheckField, 0, 4, 15, // 95: check Inst[3:0] == 0xf |
| 16189 | OPC_CheckPredicate, 35, // 99: check predicate 35 |
| 16190 | OPC_Decode, 170, 28, 206, 2, // 101: decode to VST1LNd8 using decoder 334 |
| 16191 | // 101: } else try { |
| 16192 | OPC_CheckPredicate, 35, // 106: check predicate 35 |
| 16193 | OPC_Decode, 171, 28, 206, 2, // 108: decode to VST1LNd8_UPD using decoder 334 |
| 16194 | // 108: } |
| 16195 | // 108: } |
| 16196 | // 108: } // switch Inst[31:23] |
| 16197 | // 108: } |
| 16198 | 2, 0, // 113: case 0x2: { |
| 16199 | OPC_SwitchField, 23, 9, // 115: switch Inst[31:23] { |
| 16200 | 232, 3, 69, // 118: case 0x1e8: { |
| 16201 | OPC_SwitchField, 6, 2, // 121: switch Inst[7:6] { |
| 16202 | 0, 20, // 124: case 0x0: { |
| 16203 | OPC_Scope, 11, // 126: try { |
| 16204 | OPC_CheckField, 0, 4, 15, // 128: check Inst[3:0] == 0xf |
| 16205 | OPC_CheckPredicate, 35, // 132: check predicate 35 |
| 16206 | OPC_Decode, 184, 22, 205, 2, // 134: decode to VLD4d8 using decoder 333 |
| 16207 | // 134: } else try { |
| 16208 | OPC_CheckPredicate, 35, // 139: check predicate 35 |
| 16209 | OPC_Decode, 187, 22, 205, 2, // 141: decode to VLD4d8_UPD using decoder 333 |
| 16210 | // 141: } |
| 16211 | // 141: } |
| 16212 | 1, 20, // 146: case 0x1: { |
| 16213 | OPC_Scope, 11, // 148: try { |
| 16214 | OPC_CheckField, 0, 4, 15, // 150: check Inst[3:0] == 0xf |
| 16215 | OPC_CheckPredicate, 35, // 154: check predicate 35 |
| 16216 | OPC_Decode, 176, 22, 205, 2, // 156: decode to VLD4d16 using decoder 333 |
| 16217 | // 156: } else try { |
| 16218 | OPC_CheckPredicate, 35, // 161: check predicate 35 |
| 16219 | OPC_Decode, 179, 22, 205, 2, // 163: decode to VLD4d16_UPD using decoder 333 |
| 16220 | // 163: } |
| 16221 | // 163: } |
| 16222 | 2, 0, // 168: case 0x2: { |
| 16223 | OPC_Scope, 11, // 170: try { |
| 16224 | OPC_CheckField, 0, 4, 15, // 172: check Inst[3:0] == 0xf |
| 16225 | OPC_CheckPredicate, 35, // 176: check predicate 35 |
| 16226 | OPC_Decode, 180, 22, 205, 2, // 178: decode to VLD4d32 using decoder 333 |
| 16227 | // 178: } else try { |
| 16228 | OPC_CheckPredicate, 35, // 183: check predicate 35 |
| 16229 | OPC_Decode, 183, 22, 205, 2, // 185: decode to VLD4d32_UPD using decoder 333 |
| 16230 | // 185: } |
| 16231 | // 185: } |
| 16232 | // 185: } // switch Inst[7:6] |
| 16233 | // 185: } |
| 16234 | 233, 3, 0, // 190: case 0x1e9: { |
| 16235 | OPC_CheckField, 4, 1, 0, // 193: check Inst[4] == 0x0 |
| 16236 | OPC_Scope, 11, // 197: try { |
| 16237 | OPC_CheckField, 0, 4, 15, // 199: check Inst[3:0] == 0xf |
| 16238 | OPC_CheckPredicate, 35, // 203: check predicate 35 |
| 16239 | OPC_Decode, 249, 19, 207, 2, // 205: decode to VLD1LNd8 using decoder 335 |
| 16240 | // 205: } else try { |
| 16241 | OPC_CheckPredicate, 35, // 210: check predicate 35 |
| 16242 | OPC_Decode, 250, 19, 207, 2, // 212: decode to VLD1LNd8_UPD using decoder 335 |
| 16243 | // 212: } |
| 16244 | // 212: } |
| 16245 | // 212: } // switch Inst[31:23] |
| 16246 | // 212: } |
| 16247 | // 212: } // switch Inst[21:20] |
| 16248 | // 212: } |
| 16249 | 1, 203, 1, // 217: case 0x1: { |
| 16250 | OPC_SwitchField, 20, 2, // 220: switch Inst[21:20] { |
| 16251 | 0, 98, // 223: case 0x0: { |
| 16252 | OPC_SwitchField, 23, 9, // 225: switch Inst[31:23] { |
| 16253 | 232, 3, 69, // 228: case 0x1e8: { |
| 16254 | OPC_SwitchField, 6, 2, // 231: switch Inst[7:6] { |
| 16255 | 0, 20, // 234: case 0x0: { |
| 16256 | OPC_Scope, 11, // 236: try { |
| 16257 | OPC_CheckField, 0, 4, 15, // 238: check Inst[3:0] == 0xf |
| 16258 | OPC_CheckPredicate, 35, // 242: check predicate 35 |
| 16259 | OPC_Decode, 163, 30, 205, 2, // 244: decode to VST4q8 using decoder 333 |
| 16260 | // 244: } else try { |
| 16261 | OPC_CheckPredicate, 35, // 249: check predicate 35 |
| 16262 | OPC_Decode, 165, 30, 205, 2, // 251: decode to VST4q8_UPD using decoder 333 |
| 16263 | // 251: } |
| 16264 | // 251: } |
| 16265 | 1, 20, // 256: case 0x1: { |
| 16266 | OPC_Scope, 11, // 258: try { |
| 16267 | OPC_CheckField, 0, 4, 15, // 260: check Inst[3:0] == 0xf |
| 16268 | OPC_CheckPredicate, 35, // 264: check predicate 35 |
| 16269 | OPC_Decode, 153, 30, 205, 2, // 266: decode to VST4q16 using decoder 333 |
| 16270 | // 266: } else try { |
| 16271 | OPC_CheckPredicate, 35, // 271: check predicate 35 |
| 16272 | OPC_Decode, 155, 30, 205, 2, // 273: decode to VST4q16_UPD using decoder 333 |
| 16273 | // 273: } |
| 16274 | // 273: } |
| 16275 | 2, 0, // 278: case 0x2: { |
| 16276 | OPC_Scope, 11, // 280: try { |
| 16277 | OPC_CheckField, 0, 4, 15, // 282: check Inst[3:0] == 0xf |
| 16278 | OPC_CheckPredicate, 35, // 286: check predicate 35 |
| 16279 | OPC_Decode, 158, 30, 205, 2, // 288: decode to VST4q32 using decoder 333 |
| 16280 | // 288: } else try { |
| 16281 | OPC_CheckPredicate, 35, // 293: check predicate 35 |
| 16282 | OPC_Decode, 160, 30, 205, 2, // 295: decode to VST4q32_UPD using decoder 333 |
| 16283 | // 295: } |
| 16284 | // 295: } |
| 16285 | // 295: } // switch Inst[7:6] |
| 16286 | // 295: } |
| 16287 | 233, 3, 0, // 300: case 0x1e9: { |
| 16288 | OPC_Scope, 11, // 303: try { |
| 16289 | OPC_CheckField, 0, 4, 15, // 305: check Inst[3:0] == 0xf |
| 16290 | OPC_CheckPredicate, 35, // 309: check predicate 35 |
| 16291 | OPC_Decode, 154, 29, 208, 2, // 311: decode to VST2LNd8 using decoder 336 |
| 16292 | // 311: } else try { |
| 16293 | OPC_CheckPredicate, 35, // 316: check predicate 35 |
| 16294 | OPC_Decode, 157, 29, 208, 2, // 318: decode to VST2LNd8_UPD using decoder 336 |
| 16295 | // 318: } |
| 16296 | // 318: } |
| 16297 | // 318: } // switch Inst[31:23] |
| 16298 | // 318: } |
| 16299 | 2, 0, // 323: case 0x2: { |
| 16300 | OPC_SwitchField, 23, 9, // 325: switch Inst[31:23] { |
| 16301 | 232, 3, 69, // 328: case 0x1e8: { |
| 16302 | OPC_SwitchField, 6, 2, // 331: switch Inst[7:6] { |
| 16303 | 0, 20, // 334: case 0x0: { |
| 16304 | OPC_Scope, 11, // 336: try { |
| 16305 | OPC_CheckField, 0, 4, 15, // 338: check Inst[3:0] == 0xf |
| 16306 | OPC_CheckPredicate, 35, // 342: check predicate 35 |
| 16307 | OPC_Decode, 198, 22, 205, 2, // 344: decode to VLD4q8 using decoder 333 |
| 16308 | // 344: } else try { |
| 16309 | OPC_CheckPredicate, 35, // 349: check predicate 35 |
| 16310 | OPC_Decode, 200, 22, 205, 2, // 351: decode to VLD4q8_UPD using decoder 333 |
| 16311 | // 351: } |
| 16312 | // 351: } |
| 16313 | 1, 20, // 356: case 0x1: { |
| 16314 | OPC_Scope, 11, // 358: try { |
| 16315 | OPC_CheckField, 0, 4, 15, // 360: check Inst[3:0] == 0xf |
| 16316 | OPC_CheckPredicate, 35, // 364: check predicate 35 |
| 16317 | OPC_Decode, 188, 22, 205, 2, // 366: decode to VLD4q16 using decoder 333 |
| 16318 | // 366: } else try { |
| 16319 | OPC_CheckPredicate, 35, // 371: check predicate 35 |
| 16320 | OPC_Decode, 190, 22, 205, 2, // 373: decode to VLD4q16_UPD using decoder 333 |
| 16321 | // 373: } |
| 16322 | // 373: } |
| 16323 | 2, 0, // 378: case 0x2: { |
| 16324 | OPC_Scope, 11, // 380: try { |
| 16325 | OPC_CheckField, 0, 4, 15, // 382: check Inst[3:0] == 0xf |
| 16326 | OPC_CheckPredicate, 35, // 386: check predicate 35 |
| 16327 | OPC_Decode, 193, 22, 205, 2, // 388: decode to VLD4q32 using decoder 333 |
| 16328 | // 388: } else try { |
| 16329 | OPC_CheckPredicate, 35, // 393: check predicate 35 |
| 16330 | OPC_Decode, 195, 22, 205, 2, // 395: decode to VLD4q32_UPD using decoder 333 |
| 16331 | // 395: } |
| 16332 | // 395: } |
| 16333 | // 395: } // switch Inst[7:6] |
| 16334 | // 395: } |
| 16335 | 233, 3, 0, // 400: case 0x1e9: { |
| 16336 | OPC_Scope, 11, // 403: try { |
| 16337 | OPC_CheckField, 0, 4, 15, // 405: check Inst[3:0] == 0xf |
| 16338 | OPC_CheckPredicate, 35, // 409: check predicate 35 |
| 16339 | OPC_Decode, 135, 21, 209, 2, // 411: decode to VLD2LNd8 using decoder 337 |
| 16340 | // 411: } else try { |
| 16341 | OPC_CheckPredicate, 35, // 416: check predicate 35 |
| 16342 | OPC_Decode, 138, 21, 209, 2, // 418: decode to VLD2LNd8_UPD using decoder 337 |
| 16343 | // 418: } |
| 16344 | // 418: } |
| 16345 | // 418: } // switch Inst[31:23] |
| 16346 | // 418: } |
| 16347 | // 418: } // switch Inst[21:20] |
| 16348 | // 418: } |
| 16349 | 2, 210, 2, // 423: case 0x2: { |
| 16350 | OPC_SwitchField, 20, 2, // 426: switch Inst[21:20] { |
| 16351 | 0, 165, 1, // 429: case 0x0: { |
| 16352 | OPC_SwitchField, 23, 9, // 432: switch Inst[31:23] { |
| 16353 | 232, 3, 131, 1, // 435: case 0x1e8: { |
| 16354 | OPC_SwitchField, 6, 2, // 439: switch Inst[7:6] { |
| 16355 | 0, 30, // 442: case 0x0: { |
| 16356 | OPC_Scope, 21, // 444: try { |
| 16357 | OPC_SwitchField, 0, 4, // 446: switch Inst[3:0] { |
| 16358 | 13, 7, // 449: case 0xd: { |
| 16359 | OPC_CheckPredicate, 35, // 451: check predicate 35 |
| 16360 | OPC_Decode, 228, 28, 210, 2, // 453: decode to VST1d8Qwb_fixed using decoder 338 |
| 16361 | // 453: } |
| 16362 | 15, 0, // 458: case 0xf: { |
| 16363 | OPC_CheckPredicate, 35, // 460: check predicate 35 |
| 16364 | OPC_Decode, 224, 28, 210, 2, // 462: decode to VST1d8Q using decoder 338 |
| 16365 | // 462: } |
| 16366 | // 462: } // switch Inst[3:0] |
| 16367 | // 462: } else try { |
| 16368 | OPC_CheckPredicate, 35, // 467: check predicate 35 |
| 16369 | OPC_Decode, 229, 28, 210, 2, // 469: decode to VST1d8Qwb_register using decoder 338 |
| 16370 | // 469: } |
| 16371 | // 469: } |
| 16372 | 1, 30, // 474: case 0x1: { |
| 16373 | OPC_Scope, 21, // 476: try { |
| 16374 | OPC_SwitchField, 0, 4, // 478: switch Inst[3:0] { |
| 16375 | 13, 7, // 481: case 0xd: { |
| 16376 | OPC_CheckPredicate, 35, // 483: check predicate 35 |
| 16377 | OPC_Decode, 183, 28, 210, 2, // 485: decode to VST1d16Qwb_fixed using decoder 338 |
| 16378 | // 485: } |
| 16379 | 15, 0, // 490: case 0xf: { |
| 16380 | OPC_CheckPredicate, 35, // 492: check predicate 35 |
| 16381 | OPC_Decode, 179, 28, 210, 2, // 494: decode to VST1d16Q using decoder 338 |
| 16382 | // 494: } |
| 16383 | // 494: } // switch Inst[3:0] |
| 16384 | // 494: } else try { |
| 16385 | OPC_CheckPredicate, 35, // 499: check predicate 35 |
| 16386 | OPC_Decode, 184, 28, 210, 2, // 501: decode to VST1d16Qwb_register using decoder 338 |
| 16387 | // 501: } |
| 16388 | // 501: } |
| 16389 | 2, 30, // 506: case 0x2: { |
| 16390 | OPC_Scope, 21, // 508: try { |
| 16391 | OPC_SwitchField, 0, 4, // 510: switch Inst[3:0] { |
| 16392 | 13, 7, // 513: case 0xd: { |
| 16393 | OPC_CheckPredicate, 35, // 515: check predicate 35 |
| 16394 | OPC_Decode, 198, 28, 210, 2, // 517: decode to VST1d32Qwb_fixed using decoder 338 |
| 16395 | // 517: } |
| 16396 | 15, 0, // 522: case 0xf: { |
| 16397 | OPC_CheckPredicate, 35, // 524: check predicate 35 |
| 16398 | OPC_Decode, 194, 28, 210, 2, // 526: decode to VST1d32Q using decoder 338 |
| 16399 | // 526: } |
| 16400 | // 526: } // switch Inst[3:0] |
| 16401 | // 526: } else try { |
| 16402 | OPC_CheckPredicate, 35, // 531: check predicate 35 |
| 16403 | OPC_Decode, 199, 28, 210, 2, // 533: decode to VST1d32Qwb_register using decoder 338 |
| 16404 | // 533: } |
| 16405 | // 533: } |
| 16406 | 3, 0, // 538: case 0x3: { |
| 16407 | OPC_Scope, 21, // 540: try { |
| 16408 | OPC_SwitchField, 0, 4, // 542: switch Inst[3:0] { |
| 16409 | 13, 7, // 545: case 0xd: { |
| 16410 | OPC_CheckPredicate, 35, // 547: check predicate 35 |
| 16411 | OPC_Decode, 213, 28, 210, 2, // 549: decode to VST1d64Qwb_fixed using decoder 338 |
| 16412 | // 549: } |
| 16413 | 15, 0, // 554: case 0xf: { |
| 16414 | OPC_CheckPredicate, 35, // 556: check predicate 35 |
| 16415 | OPC_Decode, 209, 28, 210, 2, // 558: decode to VST1d64Q using decoder 338 |
| 16416 | // 558: } |
| 16417 | // 558: } // switch Inst[3:0] |
| 16418 | // 558: } else try { |
| 16419 | OPC_CheckPredicate, 35, // 563: check predicate 35 |
| 16420 | OPC_Decode, 214, 28, 210, 2, // 565: decode to VST1d64Qwb_register using decoder 338 |
| 16421 | // 565: } |
| 16422 | // 565: } |
| 16423 | // 565: } // switch Inst[7:6] |
| 16424 | // 565: } |
| 16425 | 233, 3, 0, // 570: case 0x1e9: { |
| 16426 | OPC_CheckField, 4, 1, 0, // 573: check Inst[4] == 0x0 |
| 16427 | OPC_Scope, 11, // 577: try { |
| 16428 | OPC_CheckField, 0, 4, 15, // 579: check Inst[3:0] == 0xf |
| 16429 | OPC_CheckPredicate, 35, // 583: check predicate 35 |
| 16430 | OPC_Decode, 210, 29, 211, 2, // 585: decode to VST3LNd8 using decoder 339 |
| 16431 | // 585: } else try { |
| 16432 | OPC_CheckPredicate, 35, // 590: check predicate 35 |
| 16433 | OPC_Decode, 213, 29, 211, 2, // 592: decode to VST3LNd8_UPD using decoder 339 |
| 16434 | // 592: } |
| 16435 | // 592: } |
| 16436 | // 592: } // switch Inst[31:23] |
| 16437 | // 592: } |
| 16438 | 2, 0, // 597: case 0x2: { |
| 16439 | OPC_SwitchField, 23, 9, // 599: switch Inst[31:23] { |
| 16440 | 232, 3, 131, 1, // 602: case 0x1e8: { |
| 16441 | OPC_SwitchField, 6, 2, // 606: switch Inst[7:6] { |
| 16442 | 0, 30, // 609: case 0x0: { |
| 16443 | OPC_Scope, 21, // 611: try { |
| 16444 | OPC_SwitchField, 0, 4, // 613: switch Inst[3:0] { |
| 16445 | 13, 7, // 616: case 0xd: { |
| 16446 | OPC_CheckPredicate, 35, // 618: check predicate 35 |
| 16447 | OPC_Decode, 179, 20, 210, 2, // 620: decode to VLD1d8Qwb_fixed using decoder 338 |
| 16448 | // 620: } |
| 16449 | 15, 0, // 625: case 0xf: { |
| 16450 | OPC_CheckPredicate, 35, // 627: check predicate 35 |
| 16451 | OPC_Decode, 175, 20, 210, 2, // 629: decode to VLD1d8Q using decoder 338 |
| 16452 | // 629: } |
| 16453 | // 629: } // switch Inst[3:0] |
| 16454 | // 629: } else try { |
| 16455 | OPC_CheckPredicate, 35, // 634: check predicate 35 |
| 16456 | OPC_Decode, 180, 20, 210, 2, // 636: decode to VLD1d8Qwb_register using decoder 338 |
| 16457 | // 636: } |
| 16458 | // 636: } |
| 16459 | 1, 30, // 641: case 0x1: { |
| 16460 | OPC_Scope, 21, // 643: try { |
| 16461 | OPC_SwitchField, 0, 4, // 645: switch Inst[3:0] { |
| 16462 | 13, 7, // 648: case 0xd: { |
| 16463 | OPC_CheckPredicate, 35, // 650: check predicate 35 |
| 16464 | OPC_Decode, 134, 20, 210, 2, // 652: decode to VLD1d16Qwb_fixed using decoder 338 |
| 16465 | // 652: } |
| 16466 | 15, 0, // 657: case 0xf: { |
| 16467 | OPC_CheckPredicate, 35, // 659: check predicate 35 |
| 16468 | OPC_Decode, 130, 20, 210, 2, // 661: decode to VLD1d16Q using decoder 338 |
| 16469 | // 661: } |
| 16470 | // 661: } // switch Inst[3:0] |
| 16471 | // 661: } else try { |
| 16472 | OPC_CheckPredicate, 35, // 666: check predicate 35 |
| 16473 | OPC_Decode, 135, 20, 210, 2, // 668: decode to VLD1d16Qwb_register using decoder 338 |
| 16474 | // 668: } |
| 16475 | // 668: } |
| 16476 | 2, 30, // 673: case 0x2: { |
| 16477 | OPC_Scope, 21, // 675: try { |
| 16478 | OPC_SwitchField, 0, 4, // 677: switch Inst[3:0] { |
| 16479 | 13, 7, // 680: case 0xd: { |
| 16480 | OPC_CheckPredicate, 35, // 682: check predicate 35 |
| 16481 | OPC_Decode, 149, 20, 210, 2, // 684: decode to VLD1d32Qwb_fixed using decoder 338 |
| 16482 | // 684: } |
| 16483 | 15, 0, // 689: case 0xf: { |
| 16484 | OPC_CheckPredicate, 35, // 691: check predicate 35 |
| 16485 | OPC_Decode, 145, 20, 210, 2, // 693: decode to VLD1d32Q using decoder 338 |
| 16486 | // 693: } |
| 16487 | // 693: } // switch Inst[3:0] |
| 16488 | // 693: } else try { |
| 16489 | OPC_CheckPredicate, 35, // 698: check predicate 35 |
| 16490 | OPC_Decode, 150, 20, 210, 2, // 700: decode to VLD1d32Qwb_register using decoder 338 |
| 16491 | // 700: } |
| 16492 | // 700: } |
| 16493 | 3, 0, // 705: case 0x3: { |
| 16494 | OPC_Scope, 21, // 707: try { |
| 16495 | OPC_SwitchField, 0, 4, // 709: switch Inst[3:0] { |
| 16496 | 13, 7, // 712: case 0xd: { |
| 16497 | OPC_CheckPredicate, 35, // 714: check predicate 35 |
| 16498 | OPC_Decode, 164, 20, 210, 2, // 716: decode to VLD1d64Qwb_fixed using decoder 338 |
| 16499 | // 716: } |
| 16500 | 15, 0, // 721: case 0xf: { |
| 16501 | OPC_CheckPredicate, 35, // 723: check predicate 35 |
| 16502 | OPC_Decode, 160, 20, 210, 2, // 725: decode to VLD1d64Q using decoder 338 |
| 16503 | // 725: } |
| 16504 | // 725: } // switch Inst[3:0] |
| 16505 | // 725: } else try { |
| 16506 | OPC_CheckPredicate, 35, // 730: check predicate 35 |
| 16507 | OPC_Decode, 165, 20, 210, 2, // 732: decode to VLD1d64Qwb_register using decoder 338 |
| 16508 | // 732: } |
| 16509 | // 732: } |
| 16510 | // 732: } // switch Inst[7:6] |
| 16511 | // 732: } |
| 16512 | 233, 3, 0, // 737: case 0x1e9: { |
| 16513 | OPC_CheckField, 4, 1, 0, // 740: check Inst[4] == 0x0 |
| 16514 | OPC_Scope, 11, // 744: try { |
| 16515 | OPC_CheckField, 0, 4, 15, // 746: check Inst[3:0] == 0xf |
| 16516 | OPC_CheckPredicate, 35, // 750: check predicate 35 |
| 16517 | OPC_Decode, 218, 21, 212, 2, // 752: decode to VLD3LNd8 using decoder 340 |
| 16518 | // 752: } else try { |
| 16519 | OPC_CheckPredicate, 35, // 757: check predicate 35 |
| 16520 | OPC_Decode, 221, 21, 212, 2, // 759: decode to VLD3LNd8_UPD using decoder 340 |
| 16521 | // 759: } |
| 16522 | // 759: } |
| 16523 | // 759: } // switch Inst[31:23] |
| 16524 | // 759: } |
| 16525 | // 759: } // switch Inst[21:20] |
| 16526 | // 759: } |
| 16527 | 3, 136, 2, // 764: case 0x3: { |
| 16528 | OPC_SwitchField, 20, 2, // 767: switch Inst[21:20] { |
| 16529 | 0, 128, 1, // 770: case 0x0: { |
| 16530 | OPC_SwitchField, 23, 9, // 773: switch Inst[31:23] { |
| 16531 | 232, 3, 99, // 776: case 0x1e8: { |
| 16532 | OPC_SwitchField, 6, 2, // 779: switch Inst[7:6] { |
| 16533 | 0, 30, // 782: case 0x0: { |
| 16534 | OPC_Scope, 21, // 784: try { |
| 16535 | OPC_SwitchField, 0, 4, // 786: switch Inst[3:0] { |
| 16536 | 13, 7, // 789: case 0xd: { |
| 16537 | OPC_CheckPredicate, 35, // 791: check predicate 35 |
| 16538 | OPC_Decode, 200, 29, 213, 2, // 793: decode to VST2q8wb_fixed using decoder 341 |
| 16539 | // 793: } |
| 16540 | 15, 0, // 798: case 0xf: { |
| 16541 | OPC_CheckPredicate, 35, // 800: check predicate 35 |
| 16542 | OPC_Decode, 196, 29, 213, 2, // 802: decode to VST2q8 using decoder 341 |
| 16543 | // 802: } |
| 16544 | // 802: } // switch Inst[3:0] |
| 16545 | // 802: } else try { |
| 16546 | OPC_CheckPredicate, 35, // 807: check predicate 35 |
| 16547 | OPC_Decode, 201, 29, 213, 2, // 809: decode to VST2q8wb_register using decoder 341 |
| 16548 | // 809: } |
| 16549 | // 809: } |
| 16550 | 1, 30, // 814: case 0x1: { |
| 16551 | OPC_Scope, 21, // 816: try { |
| 16552 | OPC_SwitchField, 0, 4, // 818: switch Inst[3:0] { |
| 16553 | 13, 7, // 821: case 0xd: { |
| 16554 | OPC_CheckPredicate, 35, // 823: check predicate 35 |
| 16555 | OPC_Decode, 188, 29, 213, 2, // 825: decode to VST2q16wb_fixed using decoder 341 |
| 16556 | // 825: } |
| 16557 | 15, 0, // 830: case 0xf: { |
| 16558 | OPC_CheckPredicate, 35, // 832: check predicate 35 |
| 16559 | OPC_Decode, 184, 29, 213, 2, // 834: decode to VST2q16 using decoder 341 |
| 16560 | // 834: } |
| 16561 | // 834: } // switch Inst[3:0] |
| 16562 | // 834: } else try { |
| 16563 | OPC_CheckPredicate, 35, // 839: check predicate 35 |
| 16564 | OPC_Decode, 189, 29, 213, 2, // 841: decode to VST2q16wb_register using decoder 341 |
| 16565 | // 841: } |
| 16566 | // 841: } |
| 16567 | 2, 0, // 846: case 0x2: { |
| 16568 | OPC_Scope, 21, // 848: try { |
| 16569 | OPC_SwitchField, 0, 4, // 850: switch Inst[3:0] { |
| 16570 | 13, 7, // 853: case 0xd: { |
| 16571 | OPC_CheckPredicate, 35, // 855: check predicate 35 |
| 16572 | OPC_Decode, 194, 29, 213, 2, // 857: decode to VST2q32wb_fixed using decoder 341 |
| 16573 | // 857: } |
| 16574 | 15, 0, // 862: case 0xf: { |
| 16575 | OPC_CheckPredicate, 35, // 864: check predicate 35 |
| 16576 | OPC_Decode, 190, 29, 213, 2, // 866: decode to VST2q32 using decoder 341 |
| 16577 | // 866: } |
| 16578 | // 866: } // switch Inst[3:0] |
| 16579 | // 866: } else try { |
| 16580 | OPC_CheckPredicate, 35, // 871: check predicate 35 |
| 16581 | OPC_Decode, 195, 29, 213, 2, // 873: decode to VST2q32wb_register using decoder 341 |
| 16582 | // 873: } |
| 16583 | // 873: } |
| 16584 | // 873: } // switch Inst[7:6] |
| 16585 | // 873: } |
| 16586 | 233, 3, 0, // 878: case 0x1e9: { |
| 16587 | OPC_Scope, 11, // 881: try { |
| 16588 | OPC_CheckField, 0, 4, 15, // 883: check Inst[3:0] == 0xf |
| 16589 | OPC_CheckPredicate, 35, // 887: check predicate 35 |
| 16590 | OPC_Decode, 129, 30, 214, 2, // 889: decode to VST4LNd8 using decoder 342 |
| 16591 | // 889: } else try { |
| 16592 | OPC_CheckPredicate, 35, // 894: check predicate 35 |
| 16593 | OPC_Decode, 132, 30, 214, 2, // 896: decode to VST4LNd8_UPD using decoder 342 |
| 16594 | // 896: } |
| 16595 | // 896: } |
| 16596 | // 896: } // switch Inst[31:23] |
| 16597 | // 896: } |
| 16598 | 2, 0, // 901: case 0x2: { |
| 16599 | OPC_SwitchField, 23, 9, // 903: switch Inst[31:23] { |
| 16600 | 232, 3, 99, // 906: case 0x1e8: { |
| 16601 | OPC_SwitchField, 6, 2, // 909: switch Inst[7:6] { |
| 16602 | 0, 30, // 912: case 0x0: { |
| 16603 | OPC_Scope, 21, // 914: try { |
| 16604 | OPC_SwitchField, 0, 4, // 916: switch Inst[3:0] { |
| 16605 | 13, 7, // 919: case 0xd: { |
| 16606 | OPC_CheckPredicate, 35, // 921: check predicate 35 |
| 16607 | OPC_Decode, 181, 21, 213, 2, // 923: decode to VLD2q8wb_fixed using decoder 341 |
| 16608 | // 923: } |
| 16609 | 15, 0, // 928: case 0xf: { |
| 16610 | OPC_CheckPredicate, 35, // 930: check predicate 35 |
| 16611 | OPC_Decode, 177, 21, 213, 2, // 932: decode to VLD2q8 using decoder 341 |
| 16612 | // 932: } |
| 16613 | // 932: } // switch Inst[3:0] |
| 16614 | // 932: } else try { |
| 16615 | OPC_CheckPredicate, 35, // 937: check predicate 35 |
| 16616 | OPC_Decode, 182, 21, 213, 2, // 939: decode to VLD2q8wb_register using decoder 341 |
| 16617 | // 939: } |
| 16618 | // 939: } |
| 16619 | 1, 30, // 944: case 0x1: { |
| 16620 | OPC_Scope, 21, // 946: try { |
| 16621 | OPC_SwitchField, 0, 4, // 948: switch Inst[3:0] { |
| 16622 | 13, 7, // 951: case 0xd: { |
| 16623 | OPC_CheckPredicate, 35, // 953: check predicate 35 |
| 16624 | OPC_Decode, 169, 21, 213, 2, // 955: decode to VLD2q16wb_fixed using decoder 341 |
| 16625 | // 955: } |
| 16626 | 15, 0, // 960: case 0xf: { |
| 16627 | OPC_CheckPredicate, 35, // 962: check predicate 35 |
| 16628 | OPC_Decode, 165, 21, 213, 2, // 964: decode to VLD2q16 using decoder 341 |
| 16629 | // 964: } |
| 16630 | // 964: } // switch Inst[3:0] |
| 16631 | // 964: } else try { |
| 16632 | OPC_CheckPredicate, 35, // 969: check predicate 35 |
| 16633 | OPC_Decode, 170, 21, 213, 2, // 971: decode to VLD2q16wb_register using decoder 341 |
| 16634 | // 971: } |
| 16635 | // 971: } |
| 16636 | 2, 0, // 976: case 0x2: { |
| 16637 | OPC_Scope, 21, // 978: try { |
| 16638 | OPC_SwitchField, 0, 4, // 980: switch Inst[3:0] { |
| 16639 | 13, 7, // 983: case 0xd: { |
| 16640 | OPC_CheckPredicate, 35, // 985: check predicate 35 |
| 16641 | OPC_Decode, 175, 21, 213, 2, // 987: decode to VLD2q32wb_fixed using decoder 341 |
| 16642 | // 987: } |
| 16643 | 15, 0, // 992: case 0xf: { |
| 16644 | OPC_CheckPredicate, 35, // 994: check predicate 35 |
| 16645 | OPC_Decode, 171, 21, 213, 2, // 996: decode to VLD2q32 using decoder 341 |
| 16646 | // 996: } |
| 16647 | // 996: } // switch Inst[3:0] |
| 16648 | // 996: } else try { |
| 16649 | OPC_CheckPredicate, 35, // 1001: check predicate 35 |
| 16650 | OPC_Decode, 176, 21, 213, 2, // 1003: decode to VLD2q32wb_register using decoder 341 |
| 16651 | // 1003: } |
| 16652 | // 1003: } |
| 16653 | // 1003: } // switch Inst[7:6] |
| 16654 | // 1003: } |
| 16655 | 233, 3, 0, // 1008: case 0x1e9: { |
| 16656 | OPC_Scope, 11, // 1011: try { |
| 16657 | OPC_CheckField, 0, 4, 15, // 1013: check Inst[3:0] == 0xf |
| 16658 | OPC_CheckPredicate, 35, // 1017: check predicate 35 |
| 16659 | OPC_Decode, 164, 22, 215, 2, // 1019: decode to VLD4LNd8 using decoder 343 |
| 16660 | // 1019: } else try { |
| 16661 | OPC_CheckPredicate, 35, // 1024: check predicate 35 |
| 16662 | OPC_Decode, 167, 22, 215, 2, // 1026: decode to VLD4LNd8_UPD using decoder 343 |
| 16663 | // 1026: } |
| 16664 | // 1026: } |
| 16665 | // 1026: } // switch Inst[31:23] |
| 16666 | // 1026: } |
| 16667 | // 1026: } // switch Inst[21:20] |
| 16668 | // 1026: } |
| 16669 | 4, 211, 1, // 1031: case 0x4: { |
| 16670 | OPC_SwitchField, 20, 2, // 1034: switch Inst[21:20] { |
| 16671 | 0, 102, // 1037: case 0x0: { |
| 16672 | OPC_SwitchField, 23, 9, // 1039: switch Inst[31:23] { |
| 16673 | 232, 3, 69, // 1042: case 0x1e8: { |
| 16674 | OPC_SwitchField, 5, 3, // 1045: switch Inst[7:5] { |
| 16675 | 0, 20, // 1048: case 0x0: { |
| 16676 | OPC_Scope, 11, // 1050: try { |
| 16677 | OPC_CheckField, 0, 4, 15, // 1052: check Inst[3:0] == 0xf |
| 16678 | OPC_CheckPredicate, 35, // 1056: check predicate 35 |
| 16679 | OPC_Decode, 230, 29, 216, 2, // 1058: decode to VST3d8 using decoder 344 |
| 16680 | // 1058: } else try { |
| 16681 | OPC_CheckPredicate, 35, // 1063: check predicate 35 |
| 16682 | OPC_Decode, 233, 29, 216, 2, // 1065: decode to VST3d8_UPD using decoder 344 |
| 16683 | // 1065: } |
| 16684 | // 1065: } |
| 16685 | 2, 20, // 1070: case 0x2: { |
| 16686 | OPC_Scope, 11, // 1072: try { |
| 16687 | OPC_CheckField, 0, 4, 15, // 1074: check Inst[3:0] == 0xf |
| 16688 | OPC_CheckPredicate, 35, // 1078: check predicate 35 |
| 16689 | OPC_Decode, 222, 29, 216, 2, // 1080: decode to VST3d16 using decoder 344 |
| 16690 | // 1080: } else try { |
| 16691 | OPC_CheckPredicate, 35, // 1085: check predicate 35 |
| 16692 | OPC_Decode, 225, 29, 216, 2, // 1087: decode to VST3d16_UPD using decoder 344 |
| 16693 | // 1087: } |
| 16694 | // 1087: } |
| 16695 | 4, 0, // 1092: case 0x4: { |
| 16696 | OPC_Scope, 11, // 1094: try { |
| 16697 | OPC_CheckField, 0, 4, 15, // 1096: check Inst[3:0] == 0xf |
| 16698 | OPC_CheckPredicate, 35, // 1100: check predicate 35 |
| 16699 | OPC_Decode, 226, 29, 216, 2, // 1102: decode to VST3d32 using decoder 344 |
| 16700 | // 1102: } else try { |
| 16701 | OPC_CheckPredicate, 35, // 1107: check predicate 35 |
| 16702 | OPC_Decode, 229, 29, 216, 2, // 1109: decode to VST3d32_UPD using decoder 344 |
| 16703 | // 1109: } |
| 16704 | // 1109: } |
| 16705 | // 1109: } // switch Inst[7:5] |
| 16706 | // 1109: } |
| 16707 | 233, 3, 0, // 1114: case 0x1e9: { |
| 16708 | OPC_CheckField, 5, 1, 0, // 1117: check Inst[5] == 0x0 |
| 16709 | OPC_Scope, 11, // 1121: try { |
| 16710 | OPC_CheckField, 0, 4, 15, // 1123: check Inst[3:0] == 0xf |
| 16711 | OPC_CheckPredicate, 35, // 1127: check predicate 35 |
| 16712 | OPC_Decode, 166, 28, 206, 2, // 1129: decode to VST1LNd16 using decoder 334 |
| 16713 | // 1129: } else try { |
| 16714 | OPC_CheckPredicate, 35, // 1134: check predicate 35 |
| 16715 | OPC_Decode, 167, 28, 206, 2, // 1136: decode to VST1LNd16_UPD using decoder 334 |
| 16716 | // 1136: } |
| 16717 | // 1136: } |
| 16718 | // 1136: } // switch Inst[31:23] |
| 16719 | // 1136: } |
| 16720 | 2, 0, // 1141: case 0x2: { |
| 16721 | OPC_SwitchField, 23, 9, // 1143: switch Inst[31:23] { |
| 16722 | 232, 3, 69, // 1146: case 0x1e8: { |
| 16723 | OPC_SwitchField, 5, 3, // 1149: switch Inst[7:5] { |
| 16724 | 0, 20, // 1152: case 0x0: { |
| 16725 | OPC_Scope, 11, // 1154: try { |
| 16726 | OPC_CheckField, 0, 4, 15, // 1156: check Inst[3:0] == 0xf |
| 16727 | OPC_CheckPredicate, 35, // 1160: check predicate 35 |
| 16728 | OPC_Decode, 238, 21, 216, 2, // 1162: decode to VLD3d8 using decoder 344 |
| 16729 | // 1162: } else try { |
| 16730 | OPC_CheckPredicate, 35, // 1167: check predicate 35 |
| 16731 | OPC_Decode, 241, 21, 216, 2, // 1169: decode to VLD3d8_UPD using decoder 344 |
| 16732 | // 1169: } |
| 16733 | // 1169: } |
| 16734 | 2, 20, // 1174: case 0x2: { |
| 16735 | OPC_Scope, 11, // 1176: try { |
| 16736 | OPC_CheckField, 0, 4, 15, // 1178: check Inst[3:0] == 0xf |
| 16737 | OPC_CheckPredicate, 35, // 1182: check predicate 35 |
| 16738 | OPC_Decode, 230, 21, 216, 2, // 1184: decode to VLD3d16 using decoder 344 |
| 16739 | // 1184: } else try { |
| 16740 | OPC_CheckPredicate, 35, // 1189: check predicate 35 |
| 16741 | OPC_Decode, 233, 21, 216, 2, // 1191: decode to VLD3d16_UPD using decoder 344 |
| 16742 | // 1191: } |
| 16743 | // 1191: } |
| 16744 | 4, 0, // 1196: case 0x4: { |
| 16745 | OPC_Scope, 11, // 1198: try { |
| 16746 | OPC_CheckField, 0, 4, 15, // 1200: check Inst[3:0] == 0xf |
| 16747 | OPC_CheckPredicate, 35, // 1204: check predicate 35 |
| 16748 | OPC_Decode, 234, 21, 216, 2, // 1206: decode to VLD3d32 using decoder 344 |
| 16749 | // 1206: } else try { |
| 16750 | OPC_CheckPredicate, 35, // 1211: check predicate 35 |
| 16751 | OPC_Decode, 237, 21, 216, 2, // 1213: decode to VLD3d32_UPD using decoder 344 |
| 16752 | // 1213: } |
| 16753 | // 1213: } |
| 16754 | // 1213: } // switch Inst[7:5] |
| 16755 | // 1213: } |
| 16756 | 233, 3, 0, // 1218: case 0x1e9: { |
| 16757 | OPC_Scope, 11, // 1221: try { |
| 16758 | OPC_CheckField, 0, 4, 15, // 1223: check Inst[3:0] == 0xf |
| 16759 | OPC_CheckPredicate, 35, // 1227: check predicate 35 |
| 16760 | OPC_Decode, 245, 19, 207, 2, // 1229: decode to VLD1LNd16 using decoder 335 |
| 16761 | // 1229: } else try { |
| 16762 | OPC_CheckPredicate, 35, // 1234: check predicate 35 |
| 16763 | OPC_CheckField, 5, 1, 0, // 1236: check Inst[5] == 0x0 |
| 16764 | OPC_Decode, 246, 19, 207, 2, // 1240: decode to VLD1LNd16_UPD using decoder 335 |
| 16765 | // 1240: } |
| 16766 | // 1240: } |
| 16767 | // 1240: } // switch Inst[31:23] |
| 16768 | // 1240: } |
| 16769 | // 1240: } // switch Inst[21:20] |
| 16770 | // 1240: } |
| 16771 | 5, 140, 2, // 1245: case 0x5: { |
| 16772 | OPC_SwitchField, 5, 1, // 1248: switch Inst[5] { |
| 16773 | 0, 203, 1, // 1251: case 0x0: { |
| 16774 | OPC_SwitchField, 20, 2, // 1254: switch Inst[21:20] { |
| 16775 | 0, 98, // 1257: case 0x0: { |
| 16776 | OPC_SwitchField, 23, 9, // 1259: switch Inst[31:23] { |
| 16777 | 232, 3, 69, // 1262: case 0x1e8: { |
| 16778 | OPC_SwitchField, 6, 2, // 1265: switch Inst[7:6] { |
| 16779 | 0, 20, // 1268: case 0x0: { |
| 16780 | OPC_Scope, 11, // 1270: try { |
| 16781 | OPC_CheckField, 0, 4, 15, // 1272: check Inst[3:0] == 0xf |
| 16782 | OPC_CheckPredicate, 35, // 1276: check predicate 35 |
| 16783 | OPC_Decode, 244, 29, 216, 2, // 1278: decode to VST3q8 using decoder 344 |
| 16784 | // 1278: } else try { |
| 16785 | OPC_CheckPredicate, 35, // 1283: check predicate 35 |
| 16786 | OPC_Decode, 246, 29, 216, 2, // 1285: decode to VST3q8_UPD using decoder 344 |
| 16787 | // 1285: } |
| 16788 | // 1285: } |
| 16789 | 1, 20, // 1290: case 0x1: { |
| 16790 | OPC_Scope, 11, // 1292: try { |
| 16791 | OPC_CheckField, 0, 4, 15, // 1294: check Inst[3:0] == 0xf |
| 16792 | OPC_CheckPredicate, 35, // 1298: check predicate 35 |
| 16793 | OPC_Decode, 234, 29, 216, 2, // 1300: decode to VST3q16 using decoder 344 |
| 16794 | // 1300: } else try { |
| 16795 | OPC_CheckPredicate, 35, // 1305: check predicate 35 |
| 16796 | OPC_Decode, 236, 29, 216, 2, // 1307: decode to VST3q16_UPD using decoder 344 |
| 16797 | // 1307: } |
| 16798 | // 1307: } |
| 16799 | 2, 0, // 1312: case 0x2: { |
| 16800 | OPC_Scope, 11, // 1314: try { |
| 16801 | OPC_CheckField, 0, 4, 15, // 1316: check Inst[3:0] == 0xf |
| 16802 | OPC_CheckPredicate, 35, // 1320: check predicate 35 |
| 16803 | OPC_Decode, 239, 29, 216, 2, // 1322: decode to VST3q32 using decoder 344 |
| 16804 | // 1322: } else try { |
| 16805 | OPC_CheckPredicate, 35, // 1327: check predicate 35 |
| 16806 | OPC_Decode, 241, 29, 216, 2, // 1329: decode to VST3q32_UPD using decoder 344 |
| 16807 | // 1329: } |
| 16808 | // 1329: } |
| 16809 | // 1329: } // switch Inst[7:6] |
| 16810 | // 1329: } |
| 16811 | 233, 3, 0, // 1334: case 0x1e9: { |
| 16812 | OPC_Scope, 11, // 1337: try { |
| 16813 | OPC_CheckField, 0, 4, 15, // 1339: check Inst[3:0] == 0xf |
| 16814 | OPC_CheckPredicate, 35, // 1343: check predicate 35 |
| 16815 | OPC_Decode, 146, 29, 208, 2, // 1345: decode to VST2LNd16 using decoder 336 |
| 16816 | // 1345: } else try { |
| 16817 | OPC_CheckPredicate, 35, // 1350: check predicate 35 |
| 16818 | OPC_Decode, 149, 29, 208, 2, // 1352: decode to VST2LNd16_UPD using decoder 336 |
| 16819 | // 1352: } |
| 16820 | // 1352: } |
| 16821 | // 1352: } // switch Inst[31:23] |
| 16822 | // 1352: } |
| 16823 | 2, 0, // 1357: case 0x2: { |
| 16824 | OPC_SwitchField, 23, 9, // 1359: switch Inst[31:23] { |
| 16825 | 232, 3, 69, // 1362: case 0x1e8: { |
| 16826 | OPC_SwitchField, 6, 2, // 1365: switch Inst[7:6] { |
| 16827 | 0, 20, // 1368: case 0x0: { |
| 16828 | OPC_Scope, 11, // 1370: try { |
| 16829 | OPC_CheckField, 0, 4, 15, // 1372: check Inst[3:0] == 0xf |
| 16830 | OPC_CheckPredicate, 35, // 1376: check predicate 35 |
| 16831 | OPC_Decode, 252, 21, 216, 2, // 1378: decode to VLD3q8 using decoder 344 |
| 16832 | // 1378: } else try { |
| 16833 | OPC_CheckPredicate, 35, // 1383: check predicate 35 |
| 16834 | OPC_Decode, 254, 21, 216, 2, // 1385: decode to VLD3q8_UPD using decoder 344 |
| 16835 | // 1385: } |
| 16836 | // 1385: } |
| 16837 | 1, 20, // 1390: case 0x1: { |
| 16838 | OPC_Scope, 11, // 1392: try { |
| 16839 | OPC_CheckField, 0, 4, 15, // 1394: check Inst[3:0] == 0xf |
| 16840 | OPC_CheckPredicate, 35, // 1398: check predicate 35 |
| 16841 | OPC_Decode, 242, 21, 216, 2, // 1400: decode to VLD3q16 using decoder 344 |
| 16842 | // 1400: } else try { |
| 16843 | OPC_CheckPredicate, 35, // 1405: check predicate 35 |
| 16844 | OPC_Decode, 244, 21, 216, 2, // 1407: decode to VLD3q16_UPD using decoder 344 |
| 16845 | // 1407: } |
| 16846 | // 1407: } |
| 16847 | 2, 0, // 1412: case 0x2: { |
| 16848 | OPC_Scope, 11, // 1414: try { |
| 16849 | OPC_CheckField, 0, 4, 15, // 1416: check Inst[3:0] == 0xf |
| 16850 | OPC_CheckPredicate, 35, // 1420: check predicate 35 |
| 16851 | OPC_Decode, 247, 21, 216, 2, // 1422: decode to VLD3q32 using decoder 344 |
| 16852 | // 1422: } else try { |
| 16853 | OPC_CheckPredicate, 35, // 1427: check predicate 35 |
| 16854 | OPC_Decode, 249, 21, 216, 2, // 1429: decode to VLD3q32_UPD using decoder 344 |
| 16855 | // 1429: } |
| 16856 | // 1429: } |
| 16857 | // 1429: } // switch Inst[7:6] |
| 16858 | // 1429: } |
| 16859 | 233, 3, 0, // 1434: case 0x1e9: { |
| 16860 | OPC_Scope, 11, // 1437: try { |
| 16861 | OPC_CheckField, 0, 4, 15, // 1439: check Inst[3:0] == 0xf |
| 16862 | OPC_CheckPredicate, 35, // 1443: check predicate 35 |
| 16863 | OPC_Decode, 255, 20, 209, 2, // 1445: decode to VLD2LNd16 using decoder 337 |
| 16864 | // 1445: } else try { |
| 16865 | OPC_CheckPredicate, 35, // 1450: check predicate 35 |
| 16866 | OPC_Decode, 130, 21, 209, 2, // 1452: decode to VLD2LNd16_UPD using decoder 337 |
| 16867 | // 1452: } |
| 16868 | // 1452: } |
| 16869 | // 1452: } // switch Inst[31:23] |
| 16870 | // 1452: } |
| 16871 | // 1452: } // switch Inst[21:20] |
| 16872 | // 1452: } |
| 16873 | 1, 0, // 1457: case 0x1: { |
| 16874 | OPC_SwitchField, 20, 2, // 1459: switch Inst[21:20] { |
| 16875 | 0, 25, // 1462: case 0x0: { |
| 16876 | OPC_CheckField, 23, 9, 233, 3, // 1464: check Inst[31:23] == 0x1e9 |
| 16877 | OPC_Scope, 11, // 1469: try { |
| 16878 | OPC_CheckField, 0, 4, 15, // 1471: check Inst[3:0] == 0xf |
| 16879 | OPC_CheckPredicate, 35, // 1475: check predicate 35 |
| 16880 | OPC_Decode, 158, 29, 208, 2, // 1477: decode to VST2LNq16 using decoder 336 |
| 16881 | // 1477: } else try { |
| 16882 | OPC_CheckPredicate, 35, // 1482: check predicate 35 |
| 16883 | OPC_Decode, 161, 29, 208, 2, // 1484: decode to VST2LNq16_UPD using decoder 336 |
| 16884 | // 1484: } |
| 16885 | // 1484: } |
| 16886 | 2, 0, // 1489: case 0x2: { |
| 16887 | OPC_CheckField, 23, 9, 233, 3, // 1491: check Inst[31:23] == 0x1e9 |
| 16888 | OPC_Scope, 11, // 1496: try { |
| 16889 | OPC_CheckField, 0, 4, 15, // 1498: check Inst[3:0] == 0xf |
| 16890 | OPC_CheckPredicate, 35, // 1502: check predicate 35 |
| 16891 | OPC_Decode, 139, 21, 209, 2, // 1504: decode to VLD2LNq16 using decoder 337 |
| 16892 | // 1504: } else try { |
| 16893 | OPC_CheckPredicate, 35, // 1509: check predicate 35 |
| 16894 | OPC_Decode, 142, 21, 209, 2, // 1511: decode to VLD2LNq16_UPD using decoder 337 |
| 16895 | // 1511: } |
| 16896 | // 1511: } |
| 16897 | // 1511: } // switch Inst[21:20] |
| 16898 | // 1511: } |
| 16899 | // 1511: } // switch Inst[5] |
| 16900 | // 1511: } |
| 16901 | 6, 158, 3, // 1516: case 0x6: { |
| 16902 | OPC_SwitchField, 20, 2, // 1519: switch Inst[21:20] { |
| 16903 | 0, 204, 1, // 1522: case 0x0: { |
| 16904 | OPC_SwitchField, 23, 9, // 1525: switch Inst[31:23] { |
| 16905 | 232, 3, 147, 1, // 1528: case 0x1e8: { |
| 16906 | OPC_SwitchField, 6, 2, // 1532: switch Inst[7:6] { |
| 16907 | 0, 34, // 1535: case 0x0: { |
| 16908 | OPC_Scope, 25, // 1537: try { |
| 16909 | OPC_SwitchField, 0, 4, // 1539: switch Inst[3:0] { |
| 16910 | 13, 7, // 1542: case 0xd: { |
| 16911 | OPC_CheckPredicate, 35, // 1544: check predicate 35 |
| 16912 | OPC_Decode, 234, 28, 210, 2, // 1546: decode to VST1d8Twb_fixed using decoder 338 |
| 16913 | // 1546: } |
| 16914 | 15, 0, // 1551: case 0xf: { |
| 16915 | OPC_CheckPredicate, 35, // 1553: check predicate 35 |
| 16916 | OPC_CheckField, 5, 1, 0, // 1555: check Inst[5] == 0x0 |
| 16917 | OPC_Decode, 230, 28, 210, 2, // 1559: decode to VST1d8T using decoder 338 |
| 16918 | // 1559: } |
| 16919 | // 1559: } // switch Inst[3:0] |
| 16920 | // 1559: } else try { |
| 16921 | OPC_CheckPredicate, 35, // 1564: check predicate 35 |
| 16922 | OPC_Decode, 235, 28, 210, 2, // 1566: decode to VST1d8Twb_register using decoder 338 |
| 16923 | // 1566: } |
| 16924 | // 1566: } |
| 16925 | 1, 34, // 1571: case 0x1: { |
| 16926 | OPC_Scope, 25, // 1573: try { |
| 16927 | OPC_SwitchField, 0, 4, // 1575: switch Inst[3:0] { |
| 16928 | 13, 7, // 1578: case 0xd: { |
| 16929 | OPC_CheckPredicate, 35, // 1580: check predicate 35 |
| 16930 | OPC_Decode, 189, 28, 210, 2, // 1582: decode to VST1d16Twb_fixed using decoder 338 |
| 16931 | // 1582: } |
| 16932 | 15, 0, // 1587: case 0xf: { |
| 16933 | OPC_CheckPredicate, 35, // 1589: check predicate 35 |
| 16934 | OPC_CheckField, 5, 1, 0, // 1591: check Inst[5] == 0x0 |
| 16935 | OPC_Decode, 185, 28, 210, 2, // 1595: decode to VST1d16T using decoder 338 |
| 16936 | // 1595: } |
| 16937 | // 1595: } // switch Inst[3:0] |
| 16938 | // 1595: } else try { |
| 16939 | OPC_CheckPredicate, 35, // 1600: check predicate 35 |
| 16940 | OPC_Decode, 190, 28, 210, 2, // 1602: decode to VST1d16Twb_register using decoder 338 |
| 16941 | // 1602: } |
| 16942 | // 1602: } |
| 16943 | 2, 34, // 1607: case 0x2: { |
| 16944 | OPC_Scope, 25, // 1609: try { |
| 16945 | OPC_SwitchField, 0, 4, // 1611: switch Inst[3:0] { |
| 16946 | 13, 7, // 1614: case 0xd: { |
| 16947 | OPC_CheckPredicate, 35, // 1616: check predicate 35 |
| 16948 | OPC_Decode, 204, 28, 210, 2, // 1618: decode to VST1d32Twb_fixed using decoder 338 |
| 16949 | // 1618: } |
| 16950 | 15, 0, // 1623: case 0xf: { |
| 16951 | OPC_CheckPredicate, 35, // 1625: check predicate 35 |
| 16952 | OPC_CheckField, 5, 1, 0, // 1627: check Inst[5] == 0x0 |
| 16953 | OPC_Decode, 200, 28, 210, 2, // 1631: decode to VST1d32T using decoder 338 |
| 16954 | // 1631: } |
| 16955 | // 1631: } // switch Inst[3:0] |
| 16956 | // 1631: } else try { |
| 16957 | OPC_CheckPredicate, 35, // 1636: check predicate 35 |
| 16958 | OPC_Decode, 205, 28, 210, 2, // 1638: decode to VST1d32Twb_register using decoder 338 |
| 16959 | // 1638: } |
| 16960 | // 1638: } |
| 16961 | 3, 0, // 1643: case 0x3: { |
| 16962 | OPC_Scope, 25, // 1645: try { |
| 16963 | OPC_SwitchField, 0, 4, // 1647: switch Inst[3:0] { |
| 16964 | 13, 7, // 1650: case 0xd: { |
| 16965 | OPC_CheckPredicate, 35, // 1652: check predicate 35 |
| 16966 | OPC_Decode, 219, 28, 210, 2, // 1654: decode to VST1d64Twb_fixed using decoder 338 |
| 16967 | // 1654: } |
| 16968 | 15, 0, // 1659: case 0xf: { |
| 16969 | OPC_CheckPredicate, 35, // 1661: check predicate 35 |
| 16970 | OPC_CheckField, 5, 1, 0, // 1663: check Inst[5] == 0x0 |
| 16971 | OPC_Decode, 215, 28, 210, 2, // 1667: decode to VST1d64T using decoder 338 |
| 16972 | // 1667: } |
| 16973 | // 1667: } // switch Inst[3:0] |
| 16974 | // 1667: } else try { |
| 16975 | OPC_CheckPredicate, 35, // 1672: check predicate 35 |
| 16976 | OPC_Decode, 220, 28, 210, 2, // 1674: decode to VST1d64Twb_register using decoder 338 |
| 16977 | // 1674: } |
| 16978 | // 1674: } |
| 16979 | // 1674: } // switch Inst[7:6] |
| 16980 | // 1674: } |
| 16981 | 233, 3, 0, // 1679: case 0x1e9: { |
| 16982 | OPC_SwitchField, 4, 2, // 1682: switch Inst[5:4] { |
| 16983 | 0, 20, // 1685: case 0x0: { |
| 16984 | OPC_Scope, 11, // 1687: try { |
| 16985 | OPC_CheckField, 0, 4, 15, // 1689: check Inst[3:0] == 0xf |
| 16986 | OPC_CheckPredicate, 35, // 1693: check predicate 35 |
| 16987 | OPC_Decode, 202, 29, 211, 2, // 1695: decode to VST3LNd16 using decoder 339 |
| 16988 | // 1695: } else try { |
| 16989 | OPC_CheckPredicate, 35, // 1700: check predicate 35 |
| 16990 | OPC_Decode, 205, 29, 211, 2, // 1702: decode to VST3LNd16_UPD using decoder 339 |
| 16991 | // 1702: } |
| 16992 | // 1702: } |
| 16993 | 2, 0, // 1707: case 0x2: { |
| 16994 | OPC_Scope, 11, // 1709: try { |
| 16995 | OPC_CheckField, 0, 4, 15, // 1711: check Inst[3:0] == 0xf |
| 16996 | OPC_CheckPredicate, 35, // 1715: check predicate 35 |
| 16997 | OPC_Decode, 214, 29, 211, 2, // 1717: decode to VST3LNq16 using decoder 339 |
| 16998 | // 1717: } else try { |
| 16999 | OPC_CheckPredicate, 35, // 1722: check predicate 35 |
| 17000 | OPC_Decode, 217, 29, 211, 2, // 1724: decode to VST3LNq16_UPD using decoder 339 |
| 17001 | // 1724: } |
| 17002 | // 1724: } |
| 17003 | // 1724: } // switch Inst[5:4] |
| 17004 | // 1724: } |
| 17005 | // 1724: } // switch Inst[31:23] |
| 17006 | // 1724: } |
| 17007 | 2, 0, // 1729: case 0x2: { |
| 17008 | OPC_SwitchField, 5, 1, // 1731: switch Inst[5] { |
| 17009 | 0, 165, 1, // 1734: case 0x0: { |
| 17010 | OPC_SwitchField, 23, 9, // 1737: switch Inst[31:23] { |
| 17011 | 232, 3, 131, 1, // 1740: case 0x1e8: { |
| 17012 | OPC_SwitchField, 6, 2, // 1744: switch Inst[7:6] { |
| 17013 | 0, 30, // 1747: case 0x0: { |
| 17014 | OPC_Scope, 21, // 1749: try { |
| 17015 | OPC_SwitchField, 0, 4, // 1751: switch Inst[3:0] { |
| 17016 | 13, 7, // 1754: case 0xd: { |
| 17017 | OPC_CheckPredicate, 35, // 1756: check predicate 35 |
| 17018 | OPC_Decode, 185, 20, 210, 2, // 1758: decode to VLD1d8Twb_fixed using decoder 338 |
| 17019 | // 1758: } |
| 17020 | 15, 0, // 1763: case 0xf: { |
| 17021 | OPC_CheckPredicate, 35, // 1765: check predicate 35 |
| 17022 | OPC_Decode, 181, 20, 210, 2, // 1767: decode to VLD1d8T using decoder 338 |
| 17023 | // 1767: } |
| 17024 | // 1767: } // switch Inst[3:0] |
| 17025 | // 1767: } else try { |
| 17026 | OPC_CheckPredicate, 35, // 1772: check predicate 35 |
| 17027 | OPC_Decode, 186, 20, 210, 2, // 1774: decode to VLD1d8Twb_register using decoder 338 |
| 17028 | // 1774: } |
| 17029 | // 1774: } |
| 17030 | 1, 30, // 1779: case 0x1: { |
| 17031 | OPC_Scope, 21, // 1781: try { |
| 17032 | OPC_SwitchField, 0, 4, // 1783: switch Inst[3:0] { |
| 17033 | 13, 7, // 1786: case 0xd: { |
| 17034 | OPC_CheckPredicate, 35, // 1788: check predicate 35 |
| 17035 | OPC_Decode, 140, 20, 210, 2, // 1790: decode to VLD1d16Twb_fixed using decoder 338 |
| 17036 | // 1790: } |
| 17037 | 15, 0, // 1795: case 0xf: { |
| 17038 | OPC_CheckPredicate, 35, // 1797: check predicate 35 |
| 17039 | OPC_Decode, 136, 20, 210, 2, // 1799: decode to VLD1d16T using decoder 338 |
| 17040 | // 1799: } |
| 17041 | // 1799: } // switch Inst[3:0] |
| 17042 | // 1799: } else try { |
| 17043 | OPC_CheckPredicate, 35, // 1804: check predicate 35 |
| 17044 | OPC_Decode, 141, 20, 210, 2, // 1806: decode to VLD1d16Twb_register using decoder 338 |
| 17045 | // 1806: } |
| 17046 | // 1806: } |
| 17047 | 2, 30, // 1811: case 0x2: { |
| 17048 | OPC_Scope, 21, // 1813: try { |
| 17049 | OPC_SwitchField, 0, 4, // 1815: switch Inst[3:0] { |
| 17050 | 13, 7, // 1818: case 0xd: { |
| 17051 | OPC_CheckPredicate, 35, // 1820: check predicate 35 |
| 17052 | OPC_Decode, 155, 20, 210, 2, // 1822: decode to VLD1d32Twb_fixed using decoder 338 |
| 17053 | // 1822: } |
| 17054 | 15, 0, // 1827: case 0xf: { |
| 17055 | OPC_CheckPredicate, 35, // 1829: check predicate 35 |
| 17056 | OPC_Decode, 151, 20, 210, 2, // 1831: decode to VLD1d32T using decoder 338 |
| 17057 | // 1831: } |
| 17058 | // 1831: } // switch Inst[3:0] |
| 17059 | // 1831: } else try { |
| 17060 | OPC_CheckPredicate, 35, // 1836: check predicate 35 |
| 17061 | OPC_Decode, 156, 20, 210, 2, // 1838: decode to VLD1d32Twb_register using decoder 338 |
| 17062 | // 1838: } |
| 17063 | // 1838: } |
| 17064 | 3, 0, // 1843: case 0x3: { |
| 17065 | OPC_Scope, 21, // 1845: try { |
| 17066 | OPC_SwitchField, 0, 4, // 1847: switch Inst[3:0] { |
| 17067 | 13, 7, // 1850: case 0xd: { |
| 17068 | OPC_CheckPredicate, 35, // 1852: check predicate 35 |
| 17069 | OPC_Decode, 170, 20, 210, 2, // 1854: decode to VLD1d64Twb_fixed using decoder 338 |
| 17070 | // 1854: } |
| 17071 | 15, 0, // 1859: case 0xf: { |
| 17072 | OPC_CheckPredicate, 35, // 1861: check predicate 35 |
| 17073 | OPC_Decode, 166, 20, 210, 2, // 1863: decode to VLD1d64T using decoder 338 |
| 17074 | // 1863: } |
| 17075 | // 1863: } // switch Inst[3:0] |
| 17076 | // 1863: } else try { |
| 17077 | OPC_CheckPredicate, 35, // 1868: check predicate 35 |
| 17078 | OPC_Decode, 171, 20, 210, 2, // 1870: decode to VLD1d64Twb_register using decoder 338 |
| 17079 | // 1870: } |
| 17080 | // 1870: } |
| 17081 | // 1870: } // switch Inst[7:6] |
| 17082 | // 1870: } |
| 17083 | 233, 3, 0, // 1875: case 0x1e9: { |
| 17084 | OPC_CheckField, 4, 1, 0, // 1878: check Inst[4] == 0x0 |
| 17085 | OPC_Scope, 11, // 1882: try { |
| 17086 | OPC_CheckField, 0, 4, 15, // 1884: check Inst[3:0] == 0xf |
| 17087 | OPC_CheckPredicate, 35, // 1888: check predicate 35 |
| 17088 | OPC_Decode, 210, 21, 212, 2, // 1890: decode to VLD3LNd16 using decoder 340 |
| 17089 | // 1890: } else try { |
| 17090 | OPC_CheckPredicate, 35, // 1895: check predicate 35 |
| 17091 | OPC_Decode, 213, 21, 212, 2, // 1897: decode to VLD3LNd16_UPD using decoder 340 |
| 17092 | // 1897: } |
| 17093 | // 1897: } |
| 17094 | // 1897: } // switch Inst[31:23] |
| 17095 | // 1897: } |
| 17096 | 1, 0, // 1902: case 0x1: { |
| 17097 | OPC_CheckField, 4, 1, 0, // 1904: check Inst[4] == 0x0 |
| 17098 | OPC_CheckField, 23, 9, 233, 3, // 1908: check Inst[31:23] == 0x1e9 |
| 17099 | OPC_Scope, 11, // 1913: try { |
| 17100 | OPC_CheckField, 0, 4, 15, // 1915: check Inst[3:0] == 0xf |
| 17101 | OPC_CheckPredicate, 35, // 1919: check predicate 35 |
| 17102 | OPC_Decode, 222, 21, 212, 2, // 1921: decode to VLD3LNq16 using decoder 340 |
| 17103 | // 1921: } else try { |
| 17104 | OPC_CheckPredicate, 35, // 1926: check predicate 35 |
| 17105 | OPC_Decode, 225, 21, 212, 2, // 1928: decode to VLD3LNq16_UPD using decoder 340 |
| 17106 | // 1928: } |
| 17107 | // 1928: } |
| 17108 | // 1928: } // switch Inst[5] |
| 17109 | // 1928: } |
| 17110 | // 1928: } // switch Inst[21:20] |
| 17111 | // 1928: } |
| 17112 | 7, 139, 3, // 1933: case 0x7: { |
| 17113 | OPC_SwitchField, 5, 1, // 1936: switch Inst[5] { |
| 17114 | 0, 202, 2, // 1939: case 0x0: { |
| 17115 | OPC_SwitchField, 20, 2, // 1942: switch Inst[21:20] { |
| 17116 | 0, 161, 1, // 1945: case 0x0: { |
| 17117 | OPC_SwitchField, 23, 9, // 1948: switch Inst[31:23] { |
| 17118 | 232, 3, 131, 1, // 1951: case 0x1e8: { |
| 17119 | OPC_SwitchField, 6, 2, // 1955: switch Inst[7:6] { |
| 17120 | 0, 30, // 1958: case 0x0: { |
| 17121 | OPC_Scope, 21, // 1960: try { |
| 17122 | OPC_SwitchField, 0, 4, // 1962: switch Inst[3:0] { |
| 17123 | 13, 7, // 1965: case 0xd: { |
| 17124 | OPC_CheckPredicate, 35, // 1967: check predicate 35 |
| 17125 | OPC_Decode, 236, 28, 210, 2, // 1969: decode to VST1d8wb_fixed using decoder 338 |
| 17126 | // 1969: } |
| 17127 | 15, 0, // 1974: case 0xf: { |
| 17128 | OPC_CheckPredicate, 35, // 1976: check predicate 35 |
| 17129 | OPC_Decode, 223, 28, 210, 2, // 1978: decode to VST1d8 using decoder 338 |
| 17130 | // 1978: } |
| 17131 | // 1978: } // switch Inst[3:0] |
| 17132 | // 1978: } else try { |
| 17133 | OPC_CheckPredicate, 35, // 1983: check predicate 35 |
| 17134 | OPC_Decode, 237, 28, 210, 2, // 1985: decode to VST1d8wb_register using decoder 338 |
| 17135 | // 1985: } |
| 17136 | // 1985: } |
| 17137 | 1, 30, // 1990: case 0x1: { |
| 17138 | OPC_Scope, 21, // 1992: try { |
| 17139 | OPC_SwitchField, 0, 4, // 1994: switch Inst[3:0] { |
| 17140 | 13, 7, // 1997: case 0xd: { |
| 17141 | OPC_CheckPredicate, 35, // 1999: check predicate 35 |
| 17142 | OPC_Decode, 191, 28, 210, 2, // 2001: decode to VST1d16wb_fixed using decoder 338 |
| 17143 | // 2001: } |
| 17144 | 15, 0, // 2006: case 0xf: { |
| 17145 | OPC_CheckPredicate, 35, // 2008: check predicate 35 |
| 17146 | OPC_Decode, 178, 28, 210, 2, // 2010: decode to VST1d16 using decoder 338 |
| 17147 | // 2010: } |
| 17148 | // 2010: } // switch Inst[3:0] |
| 17149 | // 2010: } else try { |
| 17150 | OPC_CheckPredicate, 35, // 2015: check predicate 35 |
| 17151 | OPC_Decode, 192, 28, 210, 2, // 2017: decode to VST1d16wb_register using decoder 338 |
| 17152 | // 2017: } |
| 17153 | // 2017: } |
| 17154 | 2, 30, // 2022: case 0x2: { |
| 17155 | OPC_Scope, 21, // 2024: try { |
| 17156 | OPC_SwitchField, 0, 4, // 2026: switch Inst[3:0] { |
| 17157 | 13, 7, // 2029: case 0xd: { |
| 17158 | OPC_CheckPredicate, 35, // 2031: check predicate 35 |
| 17159 | OPC_Decode, 206, 28, 210, 2, // 2033: decode to VST1d32wb_fixed using decoder 338 |
| 17160 | // 2033: } |
| 17161 | 15, 0, // 2038: case 0xf: { |
| 17162 | OPC_CheckPredicate, 35, // 2040: check predicate 35 |
| 17163 | OPC_Decode, 193, 28, 210, 2, // 2042: decode to VST1d32 using decoder 338 |
| 17164 | // 2042: } |
| 17165 | // 2042: } // switch Inst[3:0] |
| 17166 | // 2042: } else try { |
| 17167 | OPC_CheckPredicate, 35, // 2047: check predicate 35 |
| 17168 | OPC_Decode, 207, 28, 210, 2, // 2049: decode to VST1d32wb_register using decoder 338 |
| 17169 | // 2049: } |
| 17170 | // 2049: } |
| 17171 | 3, 0, // 2054: case 0x3: { |
| 17172 | OPC_Scope, 21, // 2056: try { |
| 17173 | OPC_SwitchField, 0, 4, // 2058: switch Inst[3:0] { |
| 17174 | 13, 7, // 2061: case 0xd: { |
| 17175 | OPC_CheckPredicate, 35, // 2063: check predicate 35 |
| 17176 | OPC_Decode, 221, 28, 210, 2, // 2065: decode to VST1d64wb_fixed using decoder 338 |
| 17177 | // 2065: } |
| 17178 | 15, 0, // 2070: case 0xf: { |
| 17179 | OPC_CheckPredicate, 35, // 2072: check predicate 35 |
| 17180 | OPC_Decode, 208, 28, 210, 2, // 2074: decode to VST1d64 using decoder 338 |
| 17181 | // 2074: } |
| 17182 | // 2074: } // switch Inst[3:0] |
| 17183 | // 2074: } else try { |
| 17184 | OPC_CheckPredicate, 35, // 2079: check predicate 35 |
| 17185 | OPC_Decode, 222, 28, 210, 2, // 2081: decode to VST1d64wb_register using decoder 338 |
| 17186 | // 2081: } |
| 17187 | // 2081: } |
| 17188 | // 2081: } // switch Inst[7:6] |
| 17189 | // 2081: } |
| 17190 | 233, 3, 0, // 2086: case 0x1e9: { |
| 17191 | OPC_Scope, 11, // 2089: try { |
| 17192 | OPC_CheckField, 0, 4, 15, // 2091: check Inst[3:0] == 0xf |
| 17193 | OPC_CheckPredicate, 35, // 2095: check predicate 35 |
| 17194 | OPC_Decode, 249, 29, 214, 2, // 2097: decode to VST4LNd16 using decoder 342 |
| 17195 | // 2097: } else try { |
| 17196 | OPC_CheckPredicate, 35, // 2102: check predicate 35 |
| 17197 | OPC_Decode, 252, 29, 214, 2, // 2104: decode to VST4LNd16_UPD using decoder 342 |
| 17198 | // 2104: } |
| 17199 | // 2104: } |
| 17200 | // 2104: } // switch Inst[31:23] |
| 17201 | // 2104: } |
| 17202 | 2, 0, // 2109: case 0x2: { |
| 17203 | OPC_SwitchField, 23, 9, // 2111: switch Inst[31:23] { |
| 17204 | 232, 3, 131, 1, // 2114: case 0x1e8: { |
| 17205 | OPC_SwitchField, 6, 2, // 2118: switch Inst[7:6] { |
| 17206 | 0, 30, // 2121: case 0x0: { |
| 17207 | OPC_Scope, 21, // 2123: try { |
| 17208 | OPC_SwitchField, 0, 4, // 2125: switch Inst[3:0] { |
| 17209 | 13, 7, // 2128: case 0xd: { |
| 17210 | OPC_CheckPredicate, 35, // 2130: check predicate 35 |
| 17211 | OPC_Decode, 187, 20, 210, 2, // 2132: decode to VLD1d8wb_fixed using decoder 338 |
| 17212 | // 2132: } |
| 17213 | 15, 0, // 2137: case 0xf: { |
| 17214 | OPC_CheckPredicate, 35, // 2139: check predicate 35 |
| 17215 | OPC_Decode, 174, 20, 210, 2, // 2141: decode to VLD1d8 using decoder 338 |
| 17216 | // 2141: } |
| 17217 | // 2141: } // switch Inst[3:0] |
| 17218 | // 2141: } else try { |
| 17219 | OPC_CheckPredicate, 35, // 2146: check predicate 35 |
| 17220 | OPC_Decode, 188, 20, 210, 2, // 2148: decode to VLD1d8wb_register using decoder 338 |
| 17221 | // 2148: } |
| 17222 | // 2148: } |
| 17223 | 1, 30, // 2153: case 0x1: { |
| 17224 | OPC_Scope, 21, // 2155: try { |
| 17225 | OPC_SwitchField, 0, 4, // 2157: switch Inst[3:0] { |
| 17226 | 13, 7, // 2160: case 0xd: { |
| 17227 | OPC_CheckPredicate, 35, // 2162: check predicate 35 |
| 17228 | OPC_Decode, 142, 20, 210, 2, // 2164: decode to VLD1d16wb_fixed using decoder 338 |
| 17229 | // 2164: } |
| 17230 | 15, 0, // 2169: case 0xf: { |
| 17231 | OPC_CheckPredicate, 35, // 2171: check predicate 35 |
| 17232 | OPC_Decode, 129, 20, 210, 2, // 2173: decode to VLD1d16 using decoder 338 |
| 17233 | // 2173: } |
| 17234 | // 2173: } // switch Inst[3:0] |
| 17235 | // 2173: } else try { |
| 17236 | OPC_CheckPredicate, 35, // 2178: check predicate 35 |
| 17237 | OPC_Decode, 143, 20, 210, 2, // 2180: decode to VLD1d16wb_register using decoder 338 |
| 17238 | // 2180: } |
| 17239 | // 2180: } |
| 17240 | 2, 30, // 2185: case 0x2: { |
| 17241 | OPC_Scope, 21, // 2187: try { |
| 17242 | OPC_SwitchField, 0, 4, // 2189: switch Inst[3:0] { |
| 17243 | 13, 7, // 2192: case 0xd: { |
| 17244 | OPC_CheckPredicate, 35, // 2194: check predicate 35 |
| 17245 | OPC_Decode, 157, 20, 210, 2, // 2196: decode to VLD1d32wb_fixed using decoder 338 |
| 17246 | // 2196: } |
| 17247 | 15, 0, // 2201: case 0xf: { |
| 17248 | OPC_CheckPredicate, 35, // 2203: check predicate 35 |
| 17249 | OPC_Decode, 144, 20, 210, 2, // 2205: decode to VLD1d32 using decoder 338 |
| 17250 | // 2205: } |
| 17251 | // 2205: } // switch Inst[3:0] |
| 17252 | // 2205: } else try { |
| 17253 | OPC_CheckPredicate, 35, // 2210: check predicate 35 |
| 17254 | OPC_Decode, 158, 20, 210, 2, // 2212: decode to VLD1d32wb_register using decoder 338 |
| 17255 | // 2212: } |
| 17256 | // 2212: } |
| 17257 | 3, 0, // 2217: case 0x3: { |
| 17258 | OPC_Scope, 21, // 2219: try { |
| 17259 | OPC_SwitchField, 0, 4, // 2221: switch Inst[3:0] { |
| 17260 | 13, 7, // 2224: case 0xd: { |
| 17261 | OPC_CheckPredicate, 35, // 2226: check predicate 35 |
| 17262 | OPC_Decode, 172, 20, 210, 2, // 2228: decode to VLD1d64wb_fixed using decoder 338 |
| 17263 | // 2228: } |
| 17264 | 15, 0, // 2233: case 0xf: { |
| 17265 | OPC_CheckPredicate, 35, // 2235: check predicate 35 |
| 17266 | OPC_Decode, 159, 20, 210, 2, // 2237: decode to VLD1d64 using decoder 338 |
| 17267 | // 2237: } |
| 17268 | // 2237: } // switch Inst[3:0] |
| 17269 | // 2237: } else try { |
| 17270 | OPC_CheckPredicate, 35, // 2242: check predicate 35 |
| 17271 | OPC_Decode, 173, 20, 210, 2, // 2244: decode to VLD1d64wb_register using decoder 338 |
| 17272 | // 2244: } |
| 17273 | // 2244: } |
| 17274 | // 2244: } // switch Inst[7:6] |
| 17275 | // 2244: } |
| 17276 | 233, 3, 0, // 2249: case 0x1e9: { |
| 17277 | OPC_Scope, 11, // 2252: try { |
| 17278 | OPC_CheckField, 0, 4, 15, // 2254: check Inst[3:0] == 0xf |
| 17279 | OPC_CheckPredicate, 35, // 2258: check predicate 35 |
| 17280 | OPC_Decode, 156, 22, 215, 2, // 2260: decode to VLD4LNd16 using decoder 343 |
| 17281 | // 2260: } else try { |
| 17282 | OPC_CheckPredicate, 35, // 2265: check predicate 35 |
| 17283 | OPC_Decode, 159, 22, 215, 2, // 2267: decode to VLD4LNd16_UPD using decoder 343 |
| 17284 | // 2267: } |
| 17285 | // 2267: } |
| 17286 | // 2267: } // switch Inst[31:23] |
| 17287 | // 2267: } |
| 17288 | // 2267: } // switch Inst[21:20] |
| 17289 | // 2267: } |
| 17290 | 1, 0, // 2272: case 0x1: { |
| 17291 | OPC_SwitchField, 20, 2, // 2274: switch Inst[21:20] { |
| 17292 | 0, 25, // 2277: case 0x0: { |
| 17293 | OPC_CheckField, 23, 9, 233, 3, // 2279: check Inst[31:23] == 0x1e9 |
| 17294 | OPC_Scope, 11, // 2284: try { |
| 17295 | OPC_CheckField, 0, 4, 15, // 2286: check Inst[3:0] == 0xf |
| 17296 | OPC_CheckPredicate, 35, // 2290: check predicate 35 |
| 17297 | OPC_Decode, 133, 30, 214, 2, // 2292: decode to VST4LNq16 using decoder 342 |
| 17298 | // 2292: } else try { |
| 17299 | OPC_CheckPredicate, 35, // 2297: check predicate 35 |
| 17300 | OPC_Decode, 136, 30, 214, 2, // 2299: decode to VST4LNq16_UPD using decoder 342 |
| 17301 | // 2299: } |
| 17302 | // 2299: } |
| 17303 | 2, 0, // 2304: case 0x2: { |
| 17304 | OPC_CheckField, 23, 9, 233, 3, // 2306: check Inst[31:23] == 0x1e9 |
| 17305 | OPC_Scope, 11, // 2311: try { |
| 17306 | OPC_CheckField, 0, 4, 15, // 2313: check Inst[3:0] == 0xf |
| 17307 | OPC_CheckPredicate, 35, // 2317: check predicate 35 |
| 17308 | OPC_Decode, 168, 22, 215, 2, // 2319: decode to VLD4LNq16 using decoder 343 |
| 17309 | // 2319: } else try { |
| 17310 | OPC_CheckPredicate, 35, // 2324: check predicate 35 |
| 17311 | OPC_Decode, 171, 22, 215, 2, // 2326: decode to VLD4LNq16_UPD using decoder 343 |
| 17312 | // 2326: } |
| 17313 | // 2326: } |
| 17314 | // 2326: } // switch Inst[21:20] |
| 17315 | // 2326: } |
| 17316 | // 2326: } // switch Inst[5] |
| 17317 | // 2326: } |
| 17318 | 8, 164, 2, // 2331: case 0x8: { |
| 17319 | OPC_SwitchField, 6, 1, // 2334: switch Inst[6] { |
| 17320 | 0, 199, 1, // 2337: case 0x0: { |
| 17321 | OPC_SwitchField, 20, 2, // 2340: switch Inst[21:20] { |
| 17322 | 0, 96, // 2343: case 0x0: { |
| 17323 | OPC_SwitchField, 23, 9, // 2345: switch Inst[31:23] { |
| 17324 | 232, 3, 67, // 2348: case 0x1e8: { |
| 17325 | OPC_SwitchField, 7, 1, // 2351: switch Inst[7] { |
| 17326 | 0, 30, // 2354: case 0x0: { |
| 17327 | OPC_Scope, 21, // 2356: try { |
| 17328 | OPC_SwitchField, 0, 4, // 2358: switch Inst[3:0] { |
| 17329 | 13, 7, // 2361: case 0xd: { |
| 17330 | OPC_CheckPredicate, 35, // 2363: check predicate 35 |
| 17331 | OPC_Decode, 182, 29, 213, 2, // 2365: decode to VST2d8wb_fixed using decoder 341 |
| 17332 | // 2365: } |
| 17333 | 15, 0, // 2370: case 0xf: { |
| 17334 | OPC_CheckPredicate, 35, // 2372: check predicate 35 |
| 17335 | OPC_Decode, 181, 29, 213, 2, // 2374: decode to VST2d8 using decoder 341 |
| 17336 | // 2374: } |
| 17337 | // 2374: } // switch Inst[3:0] |
| 17338 | // 2374: } else try { |
| 17339 | OPC_CheckPredicate, 35, // 2379: check predicate 35 |
| 17340 | OPC_Decode, 183, 29, 213, 2, // 2381: decode to VST2d8wb_register using decoder 341 |
| 17341 | // 2381: } |
| 17342 | // 2381: } |
| 17343 | 1, 0, // 2386: case 0x1: { |
| 17344 | OPC_Scope, 21, // 2388: try { |
| 17345 | OPC_SwitchField, 0, 4, // 2390: switch Inst[3:0] { |
| 17346 | 13, 7, // 2393: case 0xd: { |
| 17347 | OPC_CheckPredicate, 35, // 2395: check predicate 35 |
| 17348 | OPC_Decode, 179, 29, 213, 2, // 2397: decode to VST2d32wb_fixed using decoder 341 |
| 17349 | // 2397: } |
| 17350 | 15, 0, // 2402: case 0xf: { |
| 17351 | OPC_CheckPredicate, 35, // 2404: check predicate 35 |
| 17352 | OPC_Decode, 178, 29, 213, 2, // 2406: decode to VST2d32 using decoder 341 |
| 17353 | // 2406: } |
| 17354 | // 2406: } // switch Inst[3:0] |
| 17355 | // 2406: } else try { |
| 17356 | OPC_CheckPredicate, 35, // 2411: check predicate 35 |
| 17357 | OPC_Decode, 180, 29, 213, 2, // 2413: decode to VST2d32wb_register using decoder 341 |
| 17358 | // 2413: } |
| 17359 | // 2413: } |
| 17360 | // 2413: } // switch Inst[7] |
| 17361 | // 2413: } |
| 17362 | 233, 3, 0, // 2418: case 0x1e9: { |
| 17363 | OPC_Scope, 11, // 2421: try { |
| 17364 | OPC_CheckField, 0, 4, 15, // 2423: check Inst[3:0] == 0xf |
| 17365 | OPC_CheckPredicate, 35, // 2427: check predicate 35 |
| 17366 | OPC_Decode, 168, 28, 206, 2, // 2429: decode to VST1LNd32 using decoder 334 |
| 17367 | // 2429: } else try { |
| 17368 | OPC_CheckPredicate, 35, // 2434: check predicate 35 |
| 17369 | OPC_Decode, 169, 28, 206, 2, // 2436: decode to VST1LNd32_UPD using decoder 334 |
| 17370 | // 2436: } |
| 17371 | // 2436: } |
| 17372 | // 2436: } // switch Inst[31:23] |
| 17373 | // 2436: } |
| 17374 | 2, 0, // 2441: case 0x2: { |
| 17375 | OPC_SwitchField, 23, 9, // 2443: switch Inst[31:23] { |
| 17376 | 232, 3, 67, // 2446: case 0x1e8: { |
| 17377 | OPC_SwitchField, 7, 1, // 2449: switch Inst[7] { |
| 17378 | 0, 30, // 2452: case 0x0: { |
| 17379 | OPC_Scope, 21, // 2454: try { |
| 17380 | OPC_SwitchField, 0, 4, // 2456: switch Inst[3:0] { |
| 17381 | 13, 7, // 2459: case 0xd: { |
| 17382 | OPC_CheckPredicate, 35, // 2461: check predicate 35 |
| 17383 | OPC_Decode, 163, 21, 213, 2, // 2463: decode to VLD2d8wb_fixed using decoder 341 |
| 17384 | // 2463: } |
| 17385 | 15, 0, // 2468: case 0xf: { |
| 17386 | OPC_CheckPredicate, 35, // 2470: check predicate 35 |
| 17387 | OPC_Decode, 162, 21, 213, 2, // 2472: decode to VLD2d8 using decoder 341 |
| 17388 | // 2472: } |
| 17389 | // 2472: } // switch Inst[3:0] |
| 17390 | // 2472: } else try { |
| 17391 | OPC_CheckPredicate, 35, // 2477: check predicate 35 |
| 17392 | OPC_Decode, 164, 21, 213, 2, // 2479: decode to VLD2d8wb_register using decoder 341 |
| 17393 | // 2479: } |
| 17394 | // 2479: } |
| 17395 | 1, 0, // 2484: case 0x1: { |
| 17396 | OPC_Scope, 21, // 2486: try { |
| 17397 | OPC_SwitchField, 0, 4, // 2488: switch Inst[3:0] { |
| 17398 | 13, 7, // 2491: case 0xd: { |
| 17399 | OPC_CheckPredicate, 35, // 2493: check predicate 35 |
| 17400 | OPC_Decode, 160, 21, 213, 2, // 2495: decode to VLD2d32wb_fixed using decoder 341 |
| 17401 | // 2495: } |
| 17402 | 15, 0, // 2500: case 0xf: { |
| 17403 | OPC_CheckPredicate, 35, // 2502: check predicate 35 |
| 17404 | OPC_Decode, 159, 21, 213, 2, // 2504: decode to VLD2d32 using decoder 341 |
| 17405 | // 2504: } |
| 17406 | // 2504: } // switch Inst[3:0] |
| 17407 | // 2504: } else try { |
| 17408 | OPC_CheckPredicate, 35, // 2509: check predicate 35 |
| 17409 | OPC_Decode, 161, 21, 213, 2, // 2511: decode to VLD2d32wb_register using decoder 341 |
| 17410 | // 2511: } |
| 17411 | // 2511: } |
| 17412 | // 2511: } // switch Inst[7] |
| 17413 | // 2511: } |
| 17414 | 233, 3, 0, // 2516: case 0x1e9: { |
| 17415 | OPC_Scope, 11, // 2519: try { |
| 17416 | OPC_CheckField, 0, 4, 15, // 2521: check Inst[3:0] == 0xf |
| 17417 | OPC_CheckPredicate, 35, // 2525: check predicate 35 |
| 17418 | OPC_Decode, 247, 19, 207, 2, // 2527: decode to VLD1LNd32 using decoder 335 |
| 17419 | // 2527: } else try { |
| 17420 | OPC_CheckPredicate, 35, // 2532: check predicate 35 |
| 17421 | OPC_Decode, 248, 19, 207, 2, // 2534: decode to VLD1LNd32_UPD using decoder 335 |
| 17422 | // 2534: } |
| 17423 | // 2534: } |
| 17424 | // 2534: } // switch Inst[31:23] |
| 17425 | // 2534: } |
| 17426 | // 2534: } // switch Inst[21:20] |
| 17427 | // 2534: } |
| 17428 | 1, 0, // 2539: case 0x1: { |
| 17429 | OPC_SwitchField, 20, 2, // 2541: switch Inst[21:20] { |
| 17430 | 0, 39, // 2544: case 0x0: { |
| 17431 | OPC_CheckField, 7, 1, 0, // 2546: check Inst[7] == 0x0 |
| 17432 | OPC_CheckField, 23, 9, 232, 3, // 2550: check Inst[31:23] == 0x1e8 |
| 17433 | OPC_Scope, 21, // 2555: try { |
| 17434 | OPC_SwitchField, 0, 4, // 2557: switch Inst[3:0] { |
| 17435 | 13, 7, // 2560: case 0xd: { |
| 17436 | OPC_CheckPredicate, 35, // 2562: check predicate 35 |
| 17437 | OPC_Decode, 176, 29, 213, 2, // 2564: decode to VST2d16wb_fixed using decoder 341 |
| 17438 | // 2564: } |
| 17439 | 15, 0, // 2569: case 0xf: { |
| 17440 | OPC_CheckPredicate, 35, // 2571: check predicate 35 |
| 17441 | OPC_Decode, 175, 29, 213, 2, // 2573: decode to VST2d16 using decoder 341 |
| 17442 | // 2573: } |
| 17443 | // 2573: } // switch Inst[3:0] |
| 17444 | // 2573: } else try { |
| 17445 | OPC_CheckPredicate, 35, // 2578: check predicate 35 |
| 17446 | OPC_Decode, 177, 29, 213, 2, // 2580: decode to VST2d16wb_register using decoder 341 |
| 17447 | // 2580: } |
| 17448 | // 2580: } |
| 17449 | 2, 0, // 2585: case 0x2: { |
| 17450 | OPC_CheckField, 7, 1, 0, // 2587: check Inst[7] == 0x0 |
| 17451 | OPC_CheckField, 23, 9, 232, 3, // 2591: check Inst[31:23] == 0x1e8 |
| 17452 | OPC_Scope, 21, // 2596: try { |
| 17453 | OPC_SwitchField, 0, 4, // 2598: switch Inst[3:0] { |
| 17454 | 13, 7, // 2601: case 0xd: { |
| 17455 | OPC_CheckPredicate, 35, // 2603: check predicate 35 |
| 17456 | OPC_Decode, 157, 21, 213, 2, // 2605: decode to VLD2d16wb_fixed using decoder 341 |
| 17457 | // 2605: } |
| 17458 | 15, 0, // 2610: case 0xf: { |
| 17459 | OPC_CheckPredicate, 35, // 2612: check predicate 35 |
| 17460 | OPC_Decode, 156, 21, 213, 2, // 2614: decode to VLD2d16 using decoder 341 |
| 17461 | // 2614: } |
| 17462 | // 2614: } // switch Inst[3:0] |
| 17463 | // 2614: } else try { |
| 17464 | OPC_CheckPredicate, 35, // 2619: check predicate 35 |
| 17465 | OPC_Decode, 158, 21, 213, 2, // 2621: decode to VLD2d16wb_register using decoder 341 |
| 17466 | // 2621: } |
| 17467 | // 2621: } |
| 17468 | // 2621: } // switch Inst[21:20] |
| 17469 | // 2621: } |
| 17470 | // 2621: } // switch Inst[6] |
| 17471 | // 2621: } |
| 17472 | 9, 228, 2, // 2626: case 0x9: { |
| 17473 | OPC_SwitchField, 6, 1, // 2629: switch Inst[6] { |
| 17474 | 0, 207, 1, // 2632: case 0x0: { |
| 17475 | OPC_SwitchField, 20, 2, // 2635: switch Inst[21:20] { |
| 17476 | 0, 100, // 2638: case 0x0: { |
| 17477 | OPC_SwitchField, 23, 9, // 2640: switch Inst[31:23] { |
| 17478 | 232, 3, 67, // 2643: case 0x1e8: { |
| 17479 | OPC_SwitchField, 7, 1, // 2646: switch Inst[7] { |
| 17480 | 0, 30, // 2649: case 0x0: { |
| 17481 | OPC_Scope, 21, // 2651: try { |
| 17482 | OPC_SwitchField, 0, 4, // 2653: switch Inst[3:0] { |
| 17483 | 13, 7, // 2656: case 0xd: { |
| 17484 | OPC_CheckPredicate, 35, // 2658: check predicate 35 |
| 17485 | OPC_Decode, 173, 29, 213, 2, // 2660: decode to VST2b8wb_fixed using decoder 341 |
| 17486 | // 2660: } |
| 17487 | 15, 0, // 2665: case 0xf: { |
| 17488 | OPC_CheckPredicate, 35, // 2667: check predicate 35 |
| 17489 | OPC_Decode, 172, 29, 213, 2, // 2669: decode to VST2b8 using decoder 341 |
| 17490 | // 2669: } |
| 17491 | // 2669: } // switch Inst[3:0] |
| 17492 | // 2669: } else try { |
| 17493 | OPC_CheckPredicate, 35, // 2674: check predicate 35 |
| 17494 | OPC_Decode, 174, 29, 213, 2, // 2676: decode to VST2b8wb_register using decoder 341 |
| 17495 | // 2676: } |
| 17496 | // 2676: } |
| 17497 | 1, 0, // 2681: case 0x1: { |
| 17498 | OPC_Scope, 21, // 2683: try { |
| 17499 | OPC_SwitchField, 0, 4, // 2685: switch Inst[3:0] { |
| 17500 | 13, 7, // 2688: case 0xd: { |
| 17501 | OPC_CheckPredicate, 35, // 2690: check predicate 35 |
| 17502 | OPC_Decode, 170, 29, 213, 2, // 2692: decode to VST2b32wb_fixed using decoder 341 |
| 17503 | // 2692: } |
| 17504 | 15, 0, // 2697: case 0xf: { |
| 17505 | OPC_CheckPredicate, 35, // 2699: check predicate 35 |
| 17506 | OPC_Decode, 169, 29, 213, 2, // 2701: decode to VST2b32 using decoder 341 |
| 17507 | // 2701: } |
| 17508 | // 2701: } // switch Inst[3:0] |
| 17509 | // 2701: } else try { |
| 17510 | OPC_CheckPredicate, 35, // 2706: check predicate 35 |
| 17511 | OPC_Decode, 171, 29, 213, 2, // 2708: decode to VST2b32wb_register using decoder 341 |
| 17512 | // 2708: } |
| 17513 | // 2708: } |
| 17514 | // 2708: } // switch Inst[7] |
| 17515 | // 2708: } |
| 17516 | 233, 3, 0, // 2713: case 0x1e9: { |
| 17517 | OPC_CheckField, 5, 1, 0, // 2716: check Inst[5] == 0x0 |
| 17518 | OPC_Scope, 11, // 2720: try { |
| 17519 | OPC_CheckField, 0, 4, 15, // 2722: check Inst[3:0] == 0xf |
| 17520 | OPC_CheckPredicate, 35, // 2726: check predicate 35 |
| 17521 | OPC_Decode, 150, 29, 208, 2, // 2728: decode to VST2LNd32 using decoder 336 |
| 17522 | // 2728: } else try { |
| 17523 | OPC_CheckPredicate, 35, // 2733: check predicate 35 |
| 17524 | OPC_Decode, 153, 29, 208, 2, // 2735: decode to VST2LNd32_UPD using decoder 336 |
| 17525 | // 2735: } |
| 17526 | // 2735: } |
| 17527 | // 2735: } // switch Inst[31:23] |
| 17528 | // 2735: } |
| 17529 | 2, 0, // 2740: case 0x2: { |
| 17530 | OPC_SwitchField, 23, 9, // 2742: switch Inst[31:23] { |
| 17531 | 232, 3, 67, // 2745: case 0x1e8: { |
| 17532 | OPC_SwitchField, 7, 1, // 2748: switch Inst[7] { |
| 17533 | 0, 30, // 2751: case 0x0: { |
| 17534 | OPC_Scope, 21, // 2753: try { |
| 17535 | OPC_SwitchField, 0, 4, // 2755: switch Inst[3:0] { |
| 17536 | 13, 7, // 2758: case 0xd: { |
| 17537 | OPC_CheckPredicate, 35, // 2760: check predicate 35 |
| 17538 | OPC_Decode, 154, 21, 213, 2, // 2762: decode to VLD2b8wb_fixed using decoder 341 |
| 17539 | // 2762: } |
| 17540 | 15, 0, // 2767: case 0xf: { |
| 17541 | OPC_CheckPredicate, 35, // 2769: check predicate 35 |
| 17542 | OPC_Decode, 153, 21, 213, 2, // 2771: decode to VLD2b8 using decoder 341 |
| 17543 | // 2771: } |
| 17544 | // 2771: } // switch Inst[3:0] |
| 17545 | // 2771: } else try { |
| 17546 | OPC_CheckPredicate, 35, // 2776: check predicate 35 |
| 17547 | OPC_Decode, 155, 21, 213, 2, // 2778: decode to VLD2b8wb_register using decoder 341 |
| 17548 | // 2778: } |
| 17549 | // 2778: } |
| 17550 | 1, 0, // 2783: case 0x1: { |
| 17551 | OPC_Scope, 21, // 2785: try { |
| 17552 | OPC_SwitchField, 0, 4, // 2787: switch Inst[3:0] { |
| 17553 | 13, 7, // 2790: case 0xd: { |
| 17554 | OPC_CheckPredicate, 35, // 2792: check predicate 35 |
| 17555 | OPC_Decode, 151, 21, 213, 2, // 2794: decode to VLD2b32wb_fixed using decoder 341 |
| 17556 | // 2794: } |
| 17557 | 15, 0, // 2799: case 0xf: { |
| 17558 | OPC_CheckPredicate, 35, // 2801: check predicate 35 |
| 17559 | OPC_Decode, 150, 21, 213, 2, // 2803: decode to VLD2b32 using decoder 341 |
| 17560 | // 2803: } |
| 17561 | // 2803: } // switch Inst[3:0] |
| 17562 | // 2803: } else try { |
| 17563 | OPC_CheckPredicate, 35, // 2808: check predicate 35 |
| 17564 | OPC_Decode, 152, 21, 213, 2, // 2810: decode to VLD2b32wb_register using decoder 341 |
| 17565 | // 2810: } |
| 17566 | // 2810: } |
| 17567 | // 2810: } // switch Inst[7] |
| 17568 | // 2810: } |
| 17569 | 233, 3, 0, // 2815: case 0x1e9: { |
| 17570 | OPC_CheckField, 5, 1, 0, // 2818: check Inst[5] == 0x0 |
| 17571 | OPC_Scope, 11, // 2822: try { |
| 17572 | OPC_CheckField, 0, 4, 15, // 2824: check Inst[3:0] == 0xf |
| 17573 | OPC_CheckPredicate, 35, // 2828: check predicate 35 |
| 17574 | OPC_Decode, 131, 21, 209, 2, // 2830: decode to VLD2LNd32 using decoder 337 |
| 17575 | // 2830: } else try { |
| 17576 | OPC_CheckPredicate, 35, // 2835: check predicate 35 |
| 17577 | OPC_Decode, 134, 21, 209, 2, // 2837: decode to VLD2LNd32_UPD using decoder 337 |
| 17578 | // 2837: } |
| 17579 | // 2837: } |
| 17580 | // 2837: } // switch Inst[31:23] |
| 17581 | // 2837: } |
| 17582 | // 2837: } // switch Inst[21:20] |
| 17583 | // 2837: } |
| 17584 | 1, 0, // 2842: case 0x1: { |
| 17585 | OPC_SwitchField, 20, 2, // 2844: switch Inst[21:20] { |
| 17586 | 0, 67, // 2847: case 0x0: { |
| 17587 | OPC_SwitchField, 23, 9, // 2849: switch Inst[31:23] { |
| 17588 | 232, 3, 34, // 2852: case 0x1e8: { |
| 17589 | OPC_CheckField, 7, 1, 0, // 2855: check Inst[7] == 0x0 |
| 17590 | OPC_Scope, 21, // 2859: try { |
| 17591 | OPC_SwitchField, 0, 4, // 2861: switch Inst[3:0] { |
| 17592 | 13, 7, // 2864: case 0xd: { |
| 17593 | OPC_CheckPredicate, 35, // 2866: check predicate 35 |
| 17594 | OPC_Decode, 167, 29, 213, 2, // 2868: decode to VST2b16wb_fixed using decoder 341 |
| 17595 | // 2868: } |
| 17596 | 15, 0, // 2873: case 0xf: { |
| 17597 | OPC_CheckPredicate, 35, // 2875: check predicate 35 |
| 17598 | OPC_Decode, 166, 29, 213, 2, // 2877: decode to VST2b16 using decoder 341 |
| 17599 | // 2877: } |
| 17600 | // 2877: } // switch Inst[3:0] |
| 17601 | // 2877: } else try { |
| 17602 | OPC_CheckPredicate, 35, // 2882: check predicate 35 |
| 17603 | OPC_Decode, 168, 29, 213, 2, // 2884: decode to VST2b16wb_register using decoder 341 |
| 17604 | // 2884: } |
| 17605 | // 2884: } |
| 17606 | 233, 3, 0, // 2889: case 0x1e9: { |
| 17607 | OPC_CheckField, 5, 1, 0, // 2892: check Inst[5] == 0x0 |
| 17608 | OPC_Scope, 11, // 2896: try { |
| 17609 | OPC_CheckField, 0, 4, 15, // 2898: check Inst[3:0] == 0xf |
| 17610 | OPC_CheckPredicate, 35, // 2902: check predicate 35 |
| 17611 | OPC_Decode, 162, 29, 208, 2, // 2904: decode to VST2LNq32 using decoder 336 |
| 17612 | // 2904: } else try { |
| 17613 | OPC_CheckPredicate, 35, // 2909: check predicate 35 |
| 17614 | OPC_Decode, 165, 29, 208, 2, // 2911: decode to VST2LNq32_UPD using decoder 336 |
| 17615 | // 2911: } |
| 17616 | // 2911: } |
| 17617 | // 2911: } // switch Inst[31:23] |
| 17618 | // 2911: } |
| 17619 | 2, 0, // 2916: case 0x2: { |
| 17620 | OPC_SwitchField, 23, 9, // 2918: switch Inst[31:23] { |
| 17621 | 232, 3, 34, // 2921: case 0x1e8: { |
| 17622 | OPC_CheckField, 7, 1, 0, // 2924: check Inst[7] == 0x0 |
| 17623 | OPC_Scope, 21, // 2928: try { |
| 17624 | OPC_SwitchField, 0, 4, // 2930: switch Inst[3:0] { |
| 17625 | 13, 7, // 2933: case 0xd: { |
| 17626 | OPC_CheckPredicate, 35, // 2935: check predicate 35 |
| 17627 | OPC_Decode, 148, 21, 213, 2, // 2937: decode to VLD2b16wb_fixed using decoder 341 |
| 17628 | // 2937: } |
| 17629 | 15, 0, // 2942: case 0xf: { |
| 17630 | OPC_CheckPredicate, 35, // 2944: check predicate 35 |
| 17631 | OPC_Decode, 147, 21, 213, 2, // 2946: decode to VLD2b16 using decoder 341 |
| 17632 | // 2946: } |
| 17633 | // 2946: } // switch Inst[3:0] |
| 17634 | // 2946: } else try { |
| 17635 | OPC_CheckPredicate, 35, // 2951: check predicate 35 |
| 17636 | OPC_Decode, 149, 21, 213, 2, // 2953: decode to VLD2b16wb_register using decoder 341 |
| 17637 | // 2953: } |
| 17638 | // 2953: } |
| 17639 | 233, 3, 0, // 2958: case 0x1e9: { |
| 17640 | OPC_CheckField, 5, 1, 0, // 2961: check Inst[5] == 0x0 |
| 17641 | OPC_Scope, 11, // 2965: try { |
| 17642 | OPC_CheckField, 0, 4, 15, // 2967: check Inst[3:0] == 0xf |
| 17643 | OPC_CheckPredicate, 35, // 2971: check predicate 35 |
| 17644 | OPC_Decode, 143, 21, 209, 2, // 2973: decode to VLD2LNq32 using decoder 337 |
| 17645 | // 2973: } else try { |
| 17646 | OPC_CheckPredicate, 35, // 2978: check predicate 35 |
| 17647 | OPC_Decode, 146, 21, 209, 2, // 2980: decode to VLD2LNq32_UPD using decoder 337 |
| 17648 | // 2980: } |
| 17649 | // 2980: } |
| 17650 | // 2980: } // switch Inst[31:23] |
| 17651 | // 2980: } |
| 17652 | // 2980: } // switch Inst[21:20] |
| 17653 | // 2980: } |
| 17654 | // 2980: } // switch Inst[6] |
| 17655 | // 2980: } |
| 17656 | 10, 166, 3, // 2985: case 0xa: { |
| 17657 | OPC_SwitchField, 6, 1, // 2988: switch Inst[6] { |
| 17658 | 0, 207, 1, // 2991: case 0x0: { |
| 17659 | OPC_SwitchField, 20, 2, // 2994: switch Inst[21:20] { |
| 17660 | 0, 100, // 2997: case 0x0: { |
| 17661 | OPC_SwitchField, 23, 9, // 2999: switch Inst[31:23] { |
| 17662 | 232, 3, 67, // 3002: case 0x1e8: { |
| 17663 | OPC_SwitchField, 7, 1, // 3005: switch Inst[7] { |
| 17664 | 0, 30, // 3008: case 0x0: { |
| 17665 | OPC_Scope, 21, // 3010: try { |
| 17666 | OPC_SwitchField, 0, 4, // 3012: switch Inst[3:0] { |
| 17667 | 13, 7, // 3015: case 0xd: { |
| 17668 | OPC_CheckPredicate, 35, // 3017: check predicate 35 |
| 17669 | OPC_Decode, 144, 29, 210, 2, // 3019: decode to VST1q8wb_fixed using decoder 338 |
| 17670 | // 3019: } |
| 17671 | 15, 0, // 3024: case 0xf: { |
| 17672 | OPC_CheckPredicate, 35, // 3026: check predicate 35 |
| 17673 | OPC_Decode, 137, 29, 210, 2, // 3028: decode to VST1q8 using decoder 338 |
| 17674 | // 3028: } |
| 17675 | // 3028: } // switch Inst[3:0] |
| 17676 | // 3028: } else try { |
| 17677 | OPC_CheckPredicate, 35, // 3033: check predicate 35 |
| 17678 | OPC_Decode, 145, 29, 210, 2, // 3035: decode to VST1q8wb_register using decoder 338 |
| 17679 | // 3035: } |
| 17680 | // 3035: } |
| 17681 | 1, 0, // 3040: case 0x1: { |
| 17682 | OPC_Scope, 21, // 3042: try { |
| 17683 | OPC_SwitchField, 0, 4, // 3044: switch Inst[3:0] { |
| 17684 | 13, 7, // 3047: case 0xd: { |
| 17685 | OPC_CheckPredicate, 35, // 3049: check predicate 35 |
| 17686 | OPC_Decode, 254, 28, 210, 2, // 3051: decode to VST1q32wb_fixed using decoder 338 |
| 17687 | // 3051: } |
| 17688 | 15, 0, // 3056: case 0xf: { |
| 17689 | OPC_CheckPredicate, 35, // 3058: check predicate 35 |
| 17690 | OPC_Decode, 247, 28, 210, 2, // 3060: decode to VST1q32 using decoder 338 |
| 17691 | // 3060: } |
| 17692 | // 3060: } // switch Inst[3:0] |
| 17693 | // 3060: } else try { |
| 17694 | OPC_CheckPredicate, 35, // 3065: check predicate 35 |
| 17695 | OPC_Decode, 255, 28, 210, 2, // 3067: decode to VST1q32wb_register using decoder 338 |
| 17696 | // 3067: } |
| 17697 | // 3067: } |
| 17698 | // 3067: } // switch Inst[7] |
| 17699 | // 3067: } |
| 17700 | 233, 3, 0, // 3072: case 0x1e9: { |
| 17701 | OPC_CheckField, 4, 2, 0, // 3075: check Inst[5:4] == 0x0 |
| 17702 | OPC_Scope, 11, // 3079: try { |
| 17703 | OPC_CheckField, 0, 4, 15, // 3081: check Inst[3:0] == 0xf |
| 17704 | OPC_CheckPredicate, 35, // 3085: check predicate 35 |
| 17705 | OPC_Decode, 206, 29, 211, 2, // 3087: decode to VST3LNd32 using decoder 339 |
| 17706 | // 3087: } else try { |
| 17707 | OPC_CheckPredicate, 35, // 3092: check predicate 35 |
| 17708 | OPC_Decode, 209, 29, 211, 2, // 3094: decode to VST3LNd32_UPD using decoder 339 |
| 17709 | // 3094: } |
| 17710 | // 3094: } |
| 17711 | // 3094: } // switch Inst[31:23] |
| 17712 | // 3094: } |
| 17713 | 2, 0, // 3099: case 0x2: { |
| 17714 | OPC_SwitchField, 23, 9, // 3101: switch Inst[31:23] { |
| 17715 | 232, 3, 67, // 3104: case 0x1e8: { |
| 17716 | OPC_SwitchField, 7, 1, // 3107: switch Inst[7] { |
| 17717 | 0, 30, // 3110: case 0x0: { |
| 17718 | OPC_Scope, 21, // 3112: try { |
| 17719 | OPC_SwitchField, 0, 4, // 3114: switch Inst[3:0] { |
| 17720 | 13, 7, // 3117: case 0xd: { |
| 17721 | OPC_CheckPredicate, 35, // 3119: check predicate 35 |
| 17722 | OPC_Decode, 223, 20, 210, 2, // 3121: decode to VLD1q8wb_fixed using decoder 338 |
| 17723 | // 3121: } |
| 17724 | 15, 0, // 3126: case 0xf: { |
| 17725 | OPC_CheckPredicate, 35, // 3128: check predicate 35 |
| 17726 | OPC_Decode, 216, 20, 210, 2, // 3130: decode to VLD1q8 using decoder 338 |
| 17727 | // 3130: } |
| 17728 | // 3130: } // switch Inst[3:0] |
| 17729 | // 3130: } else try { |
| 17730 | OPC_CheckPredicate, 35, // 3135: check predicate 35 |
| 17731 | OPC_Decode, 224, 20, 210, 2, // 3137: decode to VLD1q8wb_register using decoder 338 |
| 17732 | // 3137: } |
| 17733 | // 3137: } |
| 17734 | 1, 0, // 3142: case 0x1: { |
| 17735 | OPC_Scope, 21, // 3144: try { |
| 17736 | OPC_SwitchField, 0, 4, // 3146: switch Inst[3:0] { |
| 17737 | 13, 7, // 3149: case 0xd: { |
| 17738 | OPC_CheckPredicate, 35, // 3151: check predicate 35 |
| 17739 | OPC_Decode, 205, 20, 210, 2, // 3153: decode to VLD1q32wb_fixed using decoder 338 |
| 17740 | // 3153: } |
| 17741 | 15, 0, // 3158: case 0xf: { |
| 17742 | OPC_CheckPredicate, 35, // 3160: check predicate 35 |
| 17743 | OPC_Decode, 198, 20, 210, 2, // 3162: decode to VLD1q32 using decoder 338 |
| 17744 | // 3162: } |
| 17745 | // 3162: } // switch Inst[3:0] |
| 17746 | // 3162: } else try { |
| 17747 | OPC_CheckPredicate, 35, // 3167: check predicate 35 |
| 17748 | OPC_Decode, 206, 20, 210, 2, // 3169: decode to VLD1q32wb_register using decoder 338 |
| 17749 | // 3169: } |
| 17750 | // 3169: } |
| 17751 | // 3169: } // switch Inst[7] |
| 17752 | // 3169: } |
| 17753 | 233, 3, 0, // 3174: case 0x1e9: { |
| 17754 | OPC_CheckField, 4, 2, 0, // 3177: check Inst[5:4] == 0x0 |
| 17755 | OPC_Scope, 11, // 3181: try { |
| 17756 | OPC_CheckField, 0, 4, 15, // 3183: check Inst[3:0] == 0xf |
| 17757 | OPC_CheckPredicate, 35, // 3187: check predicate 35 |
| 17758 | OPC_Decode, 214, 21, 212, 2, // 3189: decode to VLD3LNd32 using decoder 340 |
| 17759 | // 3189: } else try { |
| 17760 | OPC_CheckPredicate, 35, // 3194: check predicate 35 |
| 17761 | OPC_Decode, 217, 21, 212, 2, // 3196: decode to VLD3LNd32_UPD using decoder 340 |
| 17762 | // 3196: } |
| 17763 | // 3196: } |
| 17764 | // 3196: } // switch Inst[31:23] |
| 17765 | // 3196: } |
| 17766 | // 3196: } // switch Inst[21:20] |
| 17767 | // 3196: } |
| 17768 | 1, 0, // 3201: case 0x1: { |
| 17769 | OPC_SwitchField, 20, 2, // 3203: switch Inst[21:20] { |
| 17770 | 0, 100, // 3206: case 0x0: { |
| 17771 | OPC_SwitchField, 23, 9, // 3208: switch Inst[31:23] { |
| 17772 | 232, 3, 67, // 3211: case 0x1e8: { |
| 17773 | OPC_SwitchField, 7, 1, // 3214: switch Inst[7] { |
| 17774 | 0, 30, // 3217: case 0x0: { |
| 17775 | OPC_Scope, 21, // 3219: try { |
| 17776 | OPC_SwitchField, 0, 4, // 3221: switch Inst[3:0] { |
| 17777 | 13, 7, // 3224: case 0xd: { |
| 17778 | OPC_CheckPredicate, 35, // 3226: check predicate 35 |
| 17779 | OPC_Decode, 245, 28, 210, 2, // 3228: decode to VST1q16wb_fixed using decoder 338 |
| 17780 | // 3228: } |
| 17781 | 15, 0, // 3233: case 0xf: { |
| 17782 | OPC_CheckPredicate, 35, // 3235: check predicate 35 |
| 17783 | OPC_Decode, 238, 28, 210, 2, // 3237: decode to VST1q16 using decoder 338 |
| 17784 | // 3237: } |
| 17785 | // 3237: } // switch Inst[3:0] |
| 17786 | // 3237: } else try { |
| 17787 | OPC_CheckPredicate, 35, // 3242: check predicate 35 |
| 17788 | OPC_Decode, 246, 28, 210, 2, // 3244: decode to VST1q16wb_register using decoder 338 |
| 17789 | // 3244: } |
| 17790 | // 3244: } |
| 17791 | 1, 0, // 3249: case 0x1: { |
| 17792 | OPC_Scope, 21, // 3251: try { |
| 17793 | OPC_SwitchField, 0, 4, // 3253: switch Inst[3:0] { |
| 17794 | 13, 7, // 3256: case 0xd: { |
| 17795 | OPC_CheckPredicate, 35, // 3258: check predicate 35 |
| 17796 | OPC_Decode, 135, 29, 210, 2, // 3260: decode to VST1q64wb_fixed using decoder 338 |
| 17797 | // 3260: } |
| 17798 | 15, 0, // 3265: case 0xf: { |
| 17799 | OPC_CheckPredicate, 35, // 3267: check predicate 35 |
| 17800 | OPC_Decode, 128, 29, 210, 2, // 3269: decode to VST1q64 using decoder 338 |
| 17801 | // 3269: } |
| 17802 | // 3269: } // switch Inst[3:0] |
| 17803 | // 3269: } else try { |
| 17804 | OPC_CheckPredicate, 35, // 3274: check predicate 35 |
| 17805 | OPC_Decode, 136, 29, 210, 2, // 3276: decode to VST1q64wb_register using decoder 338 |
| 17806 | // 3276: } |
| 17807 | // 3276: } |
| 17808 | // 3276: } // switch Inst[7] |
| 17809 | // 3276: } |
| 17810 | 233, 3, 0, // 3281: case 0x1e9: { |
| 17811 | OPC_CheckField, 4, 2, 0, // 3284: check Inst[5:4] == 0x0 |
| 17812 | OPC_Scope, 11, // 3288: try { |
| 17813 | OPC_CheckField, 0, 4, 15, // 3290: check Inst[3:0] == 0xf |
| 17814 | OPC_CheckPredicate, 35, // 3294: check predicate 35 |
| 17815 | OPC_Decode, 218, 29, 211, 2, // 3296: decode to VST3LNq32 using decoder 339 |
| 17816 | // 3296: } else try { |
| 17817 | OPC_CheckPredicate, 35, // 3301: check predicate 35 |
| 17818 | OPC_Decode, 221, 29, 211, 2, // 3303: decode to VST3LNq32_UPD using decoder 339 |
| 17819 | // 3303: } |
| 17820 | // 3303: } |
| 17821 | // 3303: } // switch Inst[31:23] |
| 17822 | // 3303: } |
| 17823 | 2, 0, // 3308: case 0x2: { |
| 17824 | OPC_SwitchField, 23, 9, // 3310: switch Inst[31:23] { |
| 17825 | 232, 3, 67, // 3313: case 0x1e8: { |
| 17826 | OPC_SwitchField, 7, 1, // 3316: switch Inst[7] { |
| 17827 | 0, 30, // 3319: case 0x0: { |
| 17828 | OPC_Scope, 21, // 3321: try { |
| 17829 | OPC_SwitchField, 0, 4, // 3323: switch Inst[3:0] { |
| 17830 | 13, 7, // 3326: case 0xd: { |
| 17831 | OPC_CheckPredicate, 35, // 3328: check predicate 35 |
| 17832 | OPC_Decode, 196, 20, 210, 2, // 3330: decode to VLD1q16wb_fixed using decoder 338 |
| 17833 | // 3330: } |
| 17834 | 15, 0, // 3335: case 0xf: { |
| 17835 | OPC_CheckPredicate, 35, // 3337: check predicate 35 |
| 17836 | OPC_Decode, 189, 20, 210, 2, // 3339: decode to VLD1q16 using decoder 338 |
| 17837 | // 3339: } |
| 17838 | // 3339: } // switch Inst[3:0] |
| 17839 | // 3339: } else try { |
| 17840 | OPC_CheckPredicate, 35, // 3344: check predicate 35 |
| 17841 | OPC_Decode, 197, 20, 210, 2, // 3346: decode to VLD1q16wb_register using decoder 338 |
| 17842 | // 3346: } |
| 17843 | // 3346: } |
| 17844 | 1, 0, // 3351: case 0x1: { |
| 17845 | OPC_Scope, 21, // 3353: try { |
| 17846 | OPC_SwitchField, 0, 4, // 3355: switch Inst[3:0] { |
| 17847 | 13, 7, // 3358: case 0xd: { |
| 17848 | OPC_CheckPredicate, 35, // 3360: check predicate 35 |
| 17849 | OPC_Decode, 214, 20, 210, 2, // 3362: decode to VLD1q64wb_fixed using decoder 338 |
| 17850 | // 3362: } |
| 17851 | 15, 0, // 3367: case 0xf: { |
| 17852 | OPC_CheckPredicate, 35, // 3369: check predicate 35 |
| 17853 | OPC_Decode, 207, 20, 210, 2, // 3371: decode to VLD1q64 using decoder 338 |
| 17854 | // 3371: } |
| 17855 | // 3371: } // switch Inst[3:0] |
| 17856 | // 3371: } else try { |
| 17857 | OPC_CheckPredicate, 35, // 3376: check predicate 35 |
| 17858 | OPC_Decode, 215, 20, 210, 2, // 3378: decode to VLD1q64wb_register using decoder 338 |
| 17859 | // 3378: } |
| 17860 | // 3378: } |
| 17861 | // 3378: } // switch Inst[7] |
| 17862 | // 3378: } |
| 17863 | 233, 3, 0, // 3383: case 0x1e9: { |
| 17864 | OPC_CheckField, 4, 2, 0, // 3386: check Inst[5:4] == 0x0 |
| 17865 | OPC_Scope, 11, // 3390: try { |
| 17866 | OPC_CheckField, 0, 4, 15, // 3392: check Inst[3:0] == 0xf |
| 17867 | OPC_CheckPredicate, 35, // 3396: check predicate 35 |
| 17868 | OPC_Decode, 226, 21, 212, 2, // 3398: decode to VLD3LNq32 using decoder 340 |
| 17869 | // 3398: } else try { |
| 17870 | OPC_CheckPredicate, 35, // 3403: check predicate 35 |
| 17871 | OPC_Decode, 229, 21, 212, 2, // 3405: decode to VLD3LNq32_UPD using decoder 340 |
| 17872 | // 3405: } |
| 17873 | // 3405: } |
| 17874 | // 3405: } // switch Inst[31:23] |
| 17875 | // 3405: } |
| 17876 | // 3405: } // switch Inst[21:20] |
| 17877 | // 3405: } |
| 17878 | // 3405: } // switch Inst[6] |
| 17879 | // 3405: } |
| 17880 | 11, 121, // 3410: case 0xb: { |
| 17881 | OPC_SwitchField, 6, 1, // 3412: switch Inst[6] { |
| 17882 | 0, 57, // 3415: case 0x0: { |
| 17883 | OPC_SwitchField, 20, 2, // 3417: switch Inst[21:20] { |
| 17884 | 0, 25, // 3420: case 0x0: { |
| 17885 | OPC_CheckField, 23, 9, 233, 3, // 3422: check Inst[31:23] == 0x1e9 |
| 17886 | OPC_Scope, 11, // 3427: try { |
| 17887 | OPC_CheckField, 0, 4, 15, // 3429: check Inst[3:0] == 0xf |
| 17888 | OPC_CheckPredicate, 35, // 3433: check predicate 35 |
| 17889 | OPC_Decode, 253, 29, 214, 2, // 3435: decode to VST4LNd32 using decoder 342 |
| 17890 | // 3435: } else try { |
| 17891 | OPC_CheckPredicate, 35, // 3440: check predicate 35 |
| 17892 | OPC_Decode, 128, 30, 214, 2, // 3442: decode to VST4LNd32_UPD using decoder 342 |
| 17893 | // 3442: } |
| 17894 | // 3442: } |
| 17895 | 2, 0, // 3447: case 0x2: { |
| 17896 | OPC_CheckField, 23, 9, 233, 3, // 3449: check Inst[31:23] == 0x1e9 |
| 17897 | OPC_Scope, 11, // 3454: try { |
| 17898 | OPC_CheckField, 0, 4, 15, // 3456: check Inst[3:0] == 0xf |
| 17899 | OPC_CheckPredicate, 35, // 3460: check predicate 35 |
| 17900 | OPC_Decode, 160, 22, 215, 2, // 3462: decode to VLD4LNd32 using decoder 343 |
| 17901 | // 3462: } else try { |
| 17902 | OPC_CheckPredicate, 35, // 3467: check predicate 35 |
| 17903 | OPC_Decode, 163, 22, 215, 2, // 3469: decode to VLD4LNd32_UPD using decoder 343 |
| 17904 | // 3469: } |
| 17905 | // 3469: } |
| 17906 | // 3469: } // switch Inst[21:20] |
| 17907 | // 3469: } |
| 17908 | 1, 0, // 3474: case 0x1: { |
| 17909 | OPC_SwitchField, 20, 2, // 3476: switch Inst[21:20] { |
| 17910 | 0, 25, // 3479: case 0x0: { |
| 17911 | OPC_CheckField, 23, 9, 233, 3, // 3481: check Inst[31:23] == 0x1e9 |
| 17912 | OPC_Scope, 11, // 3486: try { |
| 17913 | OPC_CheckField, 0, 4, 15, // 3488: check Inst[3:0] == 0xf |
| 17914 | OPC_CheckPredicate, 35, // 3492: check predicate 35 |
| 17915 | OPC_Decode, 137, 30, 214, 2, // 3494: decode to VST4LNq32 using decoder 342 |
| 17916 | // 3494: } else try { |
| 17917 | OPC_CheckPredicate, 35, // 3499: check predicate 35 |
| 17918 | OPC_Decode, 140, 30, 214, 2, // 3501: decode to VST4LNq32_UPD using decoder 342 |
| 17919 | // 3501: } |
| 17920 | // 3501: } |
| 17921 | 2, 0, // 3506: case 0x2: { |
| 17922 | OPC_CheckField, 23, 9, 233, 3, // 3508: check Inst[31:23] == 0x1e9 |
| 17923 | OPC_Scope, 11, // 3513: try { |
| 17924 | OPC_CheckField, 0, 4, 15, // 3515: check Inst[3:0] == 0xf |
| 17925 | OPC_CheckPredicate, 35, // 3519: check predicate 35 |
| 17926 | OPC_Decode, 172, 22, 215, 2, // 3521: decode to VLD4LNq32 using decoder 343 |
| 17927 | // 3521: } else try { |
| 17928 | OPC_CheckPredicate, 35, // 3526: check predicate 35 |
| 17929 | OPC_Decode, 175, 22, 215, 2, // 3528: decode to VLD4LNq32_UPD using decoder 343 |
| 17930 | // 3528: } |
| 17931 | // 3528: } |
| 17932 | // 3528: } // switch Inst[21:20] |
| 17933 | // 3528: } |
| 17934 | // 3528: } // switch Inst[6] |
| 17935 | // 3528: } |
| 17936 | 12, 249, 1, // 3533: case 0xc: { |
| 17937 | OPC_SwitchField, 5, 3, // 3536: switch Inst[7:5] { |
| 17938 | 0, 39, // 3539: case 0x0: { |
| 17939 | OPC_CheckField, 20, 2, 2, // 3541: check Inst[21:20] == 0x2 |
| 17940 | OPC_CheckField, 23, 9, 233, 3, // 3545: check Inst[31:23] == 0x1e9 |
| 17941 | OPC_Scope, 21, // 3550: try { |
| 17942 | OPC_SwitchField, 0, 4, // 3552: switch Inst[3:0] { |
| 17943 | 13, 7, // 3555: case 0xd: { |
| 17944 | OPC_CheckPredicate, 35, // 3557: check predicate 35 |
| 17945 | OPC_Decode, 234, 19, 217, 2, // 3559: decode to VLD1DUPd8wb_fixed using decoder 345 |
| 17946 | // 3559: } |
| 17947 | 15, 0, // 3564: case 0xf: { |
| 17948 | OPC_CheckPredicate, 35, // 3566: check predicate 35 |
| 17949 | OPC_Decode, 233, 19, 217, 2, // 3568: decode to VLD1DUPd8 using decoder 345 |
| 17950 | // 3568: } |
| 17951 | // 3568: } // switch Inst[3:0] |
| 17952 | // 3568: } else try { |
| 17953 | OPC_CheckPredicate, 35, // 3573: check predicate 35 |
| 17954 | OPC_Decode, 235, 19, 217, 2, // 3575: decode to VLD1DUPd8wb_register using decoder 345 |
| 17955 | // 3575: } |
| 17956 | // 3575: } |
| 17957 | 1, 39, // 3580: case 0x1: { |
| 17958 | OPC_CheckField, 20, 2, 2, // 3582: check Inst[21:20] == 0x2 |
| 17959 | OPC_CheckField, 23, 9, 233, 3, // 3586: check Inst[31:23] == 0x1e9 |
| 17960 | OPC_Scope, 21, // 3591: try { |
| 17961 | OPC_SwitchField, 0, 4, // 3593: switch Inst[3:0] { |
| 17962 | 13, 7, // 3596: case 0xd: { |
| 17963 | OPC_CheckPredicate, 35, // 3598: check predicate 35 |
| 17964 | OPC_Decode, 243, 19, 217, 2, // 3600: decode to VLD1DUPq8wb_fixed using decoder 345 |
| 17965 | // 3600: } |
| 17966 | 15, 0, // 3605: case 0xf: { |
| 17967 | OPC_CheckPredicate, 35, // 3607: check predicate 35 |
| 17968 | OPC_Decode, 242, 19, 217, 2, // 3609: decode to VLD1DUPq8 using decoder 345 |
| 17969 | // 3609: } |
| 17970 | // 3609: } // switch Inst[3:0] |
| 17971 | // 3609: } else try { |
| 17972 | OPC_CheckPredicate, 35, // 3614: check predicate 35 |
| 17973 | OPC_Decode, 244, 19, 217, 2, // 3616: decode to VLD1DUPq8wb_register using decoder 345 |
| 17974 | // 3616: } |
| 17975 | // 3616: } |
| 17976 | 2, 39, // 3621: case 0x2: { |
| 17977 | OPC_CheckField, 20, 2, 2, // 3623: check Inst[21:20] == 0x2 |
| 17978 | OPC_CheckField, 23, 9, 233, 3, // 3627: check Inst[31:23] == 0x1e9 |
| 17979 | OPC_Scope, 21, // 3632: try { |
| 17980 | OPC_SwitchField, 0, 4, // 3634: switch Inst[3:0] { |
| 17981 | 13, 7, // 3637: case 0xd: { |
| 17982 | OPC_CheckPredicate, 35, // 3639: check predicate 35 |
| 17983 | OPC_Decode, 228, 19, 217, 2, // 3641: decode to VLD1DUPd16wb_fixed using decoder 345 |
| 17984 | // 3641: } |
| 17985 | 15, 0, // 3646: case 0xf: { |
| 17986 | OPC_CheckPredicate, 35, // 3648: check predicate 35 |
| 17987 | OPC_Decode, 227, 19, 217, 2, // 3650: decode to VLD1DUPd16 using decoder 345 |
| 17988 | // 3650: } |
| 17989 | // 3650: } // switch Inst[3:0] |
| 17990 | // 3650: } else try { |
| 17991 | OPC_CheckPredicate, 35, // 3655: check predicate 35 |
| 17992 | OPC_Decode, 229, 19, 217, 2, // 3657: decode to VLD1DUPd16wb_register using decoder 345 |
| 17993 | // 3657: } |
| 17994 | // 3657: } |
| 17995 | 3, 39, // 3662: case 0x3: { |
| 17996 | OPC_CheckField, 20, 2, 2, // 3664: check Inst[21:20] == 0x2 |
| 17997 | OPC_CheckField, 23, 9, 233, 3, // 3668: check Inst[31:23] == 0x1e9 |
| 17998 | OPC_Scope, 21, // 3673: try { |
| 17999 | OPC_SwitchField, 0, 4, // 3675: switch Inst[3:0] { |
| 18000 | 13, 7, // 3678: case 0xd: { |
| 18001 | OPC_CheckPredicate, 35, // 3680: check predicate 35 |
| 18002 | OPC_Decode, 237, 19, 217, 2, // 3682: decode to VLD1DUPq16wb_fixed using decoder 345 |
| 18003 | // 3682: } |
| 18004 | 15, 0, // 3687: case 0xf: { |
| 18005 | OPC_CheckPredicate, 35, // 3689: check predicate 35 |
| 18006 | OPC_Decode, 236, 19, 217, 2, // 3691: decode to VLD1DUPq16 using decoder 345 |
| 18007 | // 3691: } |
| 18008 | // 3691: } // switch Inst[3:0] |
| 18009 | // 3691: } else try { |
| 18010 | OPC_CheckPredicate, 35, // 3696: check predicate 35 |
| 18011 | OPC_Decode, 238, 19, 217, 2, // 3698: decode to VLD1DUPq16wb_register using decoder 345 |
| 18012 | // 3698: } |
| 18013 | // 3698: } |
| 18014 | 4, 39, // 3703: case 0x4: { |
| 18015 | OPC_CheckField, 20, 2, 2, // 3705: check Inst[21:20] == 0x2 |
| 18016 | OPC_CheckField, 23, 9, 233, 3, // 3709: check Inst[31:23] == 0x1e9 |
| 18017 | OPC_Scope, 21, // 3714: try { |
| 18018 | OPC_SwitchField, 0, 4, // 3716: switch Inst[3:0] { |
| 18019 | 13, 7, // 3719: case 0xd: { |
| 18020 | OPC_CheckPredicate, 35, // 3721: check predicate 35 |
| 18021 | OPC_Decode, 231, 19, 217, 2, // 3723: decode to VLD1DUPd32wb_fixed using decoder 345 |
| 18022 | // 3723: } |
| 18023 | 15, 0, // 3728: case 0xf: { |
| 18024 | OPC_CheckPredicate, 35, // 3730: check predicate 35 |
| 18025 | OPC_Decode, 230, 19, 217, 2, // 3732: decode to VLD1DUPd32 using decoder 345 |
| 18026 | // 3732: } |
| 18027 | // 3732: } // switch Inst[3:0] |
| 18028 | // 3732: } else try { |
| 18029 | OPC_CheckPredicate, 35, // 3737: check predicate 35 |
| 18030 | OPC_Decode, 232, 19, 217, 2, // 3739: decode to VLD1DUPd32wb_register using decoder 345 |
| 18031 | // 3739: } |
| 18032 | // 3739: } |
| 18033 | 5, 0, // 3744: case 0x5: { |
| 18034 | OPC_CheckField, 20, 2, 2, // 3746: check Inst[21:20] == 0x2 |
| 18035 | OPC_CheckField, 23, 9, 233, 3, // 3750: check Inst[31:23] == 0x1e9 |
| 18036 | OPC_Scope, 21, // 3755: try { |
| 18037 | OPC_SwitchField, 0, 4, // 3757: switch Inst[3:0] { |
| 18038 | 13, 7, // 3760: case 0xd: { |
| 18039 | OPC_CheckPredicate, 35, // 3762: check predicate 35 |
| 18040 | OPC_Decode, 240, 19, 217, 2, // 3764: decode to VLD1DUPq32wb_fixed using decoder 345 |
| 18041 | // 3764: } |
| 18042 | 15, 0, // 3769: case 0xf: { |
| 18043 | OPC_CheckPredicate, 35, // 3771: check predicate 35 |
| 18044 | OPC_Decode, 239, 19, 217, 2, // 3773: decode to VLD1DUPq32 using decoder 345 |
| 18045 | // 3773: } |
| 18046 | // 3773: } // switch Inst[3:0] |
| 18047 | // 3773: } else try { |
| 18048 | OPC_CheckPredicate, 35, // 3778: check predicate 35 |
| 18049 | OPC_Decode, 241, 19, 217, 2, // 3780: decode to VLD1DUPq32wb_register using decoder 345 |
| 18050 | // 3780: } |
| 18051 | // 3780: } |
| 18052 | // 3780: } // switch Inst[7:5] |
| 18053 | // 3780: } |
| 18054 | 13, 249, 1, // 3785: case 0xd: { |
| 18055 | OPC_SwitchField, 5, 3, // 3788: switch Inst[7:5] { |
| 18056 | 0, 39, // 3791: case 0x0: { |
| 18057 | OPC_CheckField, 20, 2, 2, // 3793: check Inst[21:20] == 0x2 |
| 18058 | OPC_CheckField, 23, 9, 233, 3, // 3797: check Inst[31:23] == 0x1e9 |
| 18059 | OPC_Scope, 21, // 3802: try { |
| 18060 | OPC_SwitchField, 0, 4, // 3804: switch Inst[3:0] { |
| 18061 | 13, 7, // 3807: case 0xd: { |
| 18062 | OPC_CheckPredicate, 35, // 3809: check predicate 35 |
| 18063 | OPC_Decode, 238, 20, 218, 2, // 3811: decode to VLD2DUPd8wb_fixed using decoder 346 |
| 18064 | // 3811: } |
| 18065 | 15, 0, // 3816: case 0xf: { |
| 18066 | OPC_CheckPredicate, 35, // 3818: check predicate 35 |
| 18067 | OPC_Decode, 237, 20, 218, 2, // 3820: decode to VLD2DUPd8 using decoder 346 |
| 18068 | // 3820: } |
| 18069 | // 3820: } // switch Inst[3:0] |
| 18070 | // 3820: } else try { |
| 18071 | OPC_CheckPredicate, 35, // 3825: check predicate 35 |
| 18072 | OPC_Decode, 239, 20, 218, 2, // 3827: decode to VLD2DUPd8wb_register using decoder 346 |
| 18073 | // 3827: } |
| 18074 | // 3827: } |
| 18075 | 1, 39, // 3832: case 0x1: { |
| 18076 | OPC_CheckField, 20, 2, 2, // 3834: check Inst[21:20] == 0x2 |
| 18077 | OPC_CheckField, 23, 9, 233, 3, // 3838: check Inst[31:23] == 0x1e9 |
| 18078 | OPC_Scope, 21, // 3843: try { |
| 18079 | OPC_SwitchField, 0, 4, // 3845: switch Inst[3:0] { |
| 18080 | 13, 7, // 3848: case 0xd: { |
| 18081 | OPC_CheckPredicate, 35, // 3850: check predicate 35 |
| 18082 | OPC_Decode, 241, 20, 218, 2, // 3852: decode to VLD2DUPd8x2wb_fixed using decoder 346 |
| 18083 | // 3852: } |
| 18084 | 15, 0, // 3857: case 0xf: { |
| 18085 | OPC_CheckPredicate, 35, // 3859: check predicate 35 |
| 18086 | OPC_Decode, 240, 20, 218, 2, // 3861: decode to VLD2DUPd8x2 using decoder 346 |
| 18087 | // 3861: } |
| 18088 | // 3861: } // switch Inst[3:0] |
| 18089 | // 3861: } else try { |
| 18090 | OPC_CheckPredicate, 35, // 3866: check predicate 35 |
| 18091 | OPC_Decode, 242, 20, 218, 2, // 3868: decode to VLD2DUPd8x2wb_register using decoder 346 |
| 18092 | // 3868: } |
| 18093 | // 3868: } |
| 18094 | 2, 39, // 3873: case 0x2: { |
| 18095 | OPC_CheckField, 20, 2, 2, // 3875: check Inst[21:20] == 0x2 |
| 18096 | OPC_CheckField, 23, 9, 233, 3, // 3879: check Inst[31:23] == 0x1e9 |
| 18097 | OPC_Scope, 21, // 3884: try { |
| 18098 | OPC_SwitchField, 0, 4, // 3886: switch Inst[3:0] { |
| 18099 | 13, 7, // 3889: case 0xd: { |
| 18100 | OPC_CheckPredicate, 35, // 3891: check predicate 35 |
| 18101 | OPC_Decode, 226, 20, 218, 2, // 3893: decode to VLD2DUPd16wb_fixed using decoder 346 |
| 18102 | // 3893: } |
| 18103 | 15, 0, // 3898: case 0xf: { |
| 18104 | OPC_CheckPredicate, 35, // 3900: check predicate 35 |
| 18105 | OPC_Decode, 225, 20, 218, 2, // 3902: decode to VLD2DUPd16 using decoder 346 |
| 18106 | // 3902: } |
| 18107 | // 3902: } // switch Inst[3:0] |
| 18108 | // 3902: } else try { |
| 18109 | OPC_CheckPredicate, 35, // 3907: check predicate 35 |
| 18110 | OPC_Decode, 227, 20, 218, 2, // 3909: decode to VLD2DUPd16wb_register using decoder 346 |
| 18111 | // 3909: } |
| 18112 | // 3909: } |
| 18113 | 3, 39, // 3914: case 0x3: { |
| 18114 | OPC_CheckField, 20, 2, 2, // 3916: check Inst[21:20] == 0x2 |
| 18115 | OPC_CheckField, 23, 9, 233, 3, // 3920: check Inst[31:23] == 0x1e9 |
| 18116 | OPC_Scope, 21, // 3925: try { |
| 18117 | OPC_SwitchField, 0, 4, // 3927: switch Inst[3:0] { |
| 18118 | 13, 7, // 3930: case 0xd: { |
| 18119 | OPC_CheckPredicate, 35, // 3932: check predicate 35 |
| 18120 | OPC_Decode, 229, 20, 218, 2, // 3934: decode to VLD2DUPd16x2wb_fixed using decoder 346 |
| 18121 | // 3934: } |
| 18122 | 15, 0, // 3939: case 0xf: { |
| 18123 | OPC_CheckPredicate, 35, // 3941: check predicate 35 |
| 18124 | OPC_Decode, 228, 20, 218, 2, // 3943: decode to VLD2DUPd16x2 using decoder 346 |
| 18125 | // 3943: } |
| 18126 | // 3943: } // switch Inst[3:0] |
| 18127 | // 3943: } else try { |
| 18128 | OPC_CheckPredicate, 35, // 3948: check predicate 35 |
| 18129 | OPC_Decode, 230, 20, 218, 2, // 3950: decode to VLD2DUPd16x2wb_register using decoder 346 |
| 18130 | // 3950: } |
| 18131 | // 3950: } |
| 18132 | 4, 39, // 3955: case 0x4: { |
| 18133 | OPC_CheckField, 20, 2, 2, // 3957: check Inst[21:20] == 0x2 |
| 18134 | OPC_CheckField, 23, 9, 233, 3, // 3961: check Inst[31:23] == 0x1e9 |
| 18135 | OPC_Scope, 21, // 3966: try { |
| 18136 | OPC_SwitchField, 0, 4, // 3968: switch Inst[3:0] { |
| 18137 | 13, 7, // 3971: case 0xd: { |
| 18138 | OPC_CheckPredicate, 35, // 3973: check predicate 35 |
| 18139 | OPC_Decode, 232, 20, 218, 2, // 3975: decode to VLD2DUPd32wb_fixed using decoder 346 |
| 18140 | // 3975: } |
| 18141 | 15, 0, // 3980: case 0xf: { |
| 18142 | OPC_CheckPredicate, 35, // 3982: check predicate 35 |
| 18143 | OPC_Decode, 231, 20, 218, 2, // 3984: decode to VLD2DUPd32 using decoder 346 |
| 18144 | // 3984: } |
| 18145 | // 3984: } // switch Inst[3:0] |
| 18146 | // 3984: } else try { |
| 18147 | OPC_CheckPredicate, 35, // 3989: check predicate 35 |
| 18148 | OPC_Decode, 233, 20, 218, 2, // 3991: decode to VLD2DUPd32wb_register using decoder 346 |
| 18149 | // 3991: } |
| 18150 | // 3991: } |
| 18151 | 5, 0, // 3996: case 0x5: { |
| 18152 | OPC_CheckField, 20, 2, 2, // 3998: check Inst[21:20] == 0x2 |
| 18153 | OPC_CheckField, 23, 9, 233, 3, // 4002: check Inst[31:23] == 0x1e9 |
| 18154 | OPC_Scope, 21, // 4007: try { |
| 18155 | OPC_SwitchField, 0, 4, // 4009: switch Inst[3:0] { |
| 18156 | 13, 7, // 4012: case 0xd: { |
| 18157 | OPC_CheckPredicate, 35, // 4014: check predicate 35 |
| 18158 | OPC_Decode, 235, 20, 218, 2, // 4016: decode to VLD2DUPd32x2wb_fixed using decoder 346 |
| 18159 | // 4016: } |
| 18160 | 15, 0, // 4021: case 0xf: { |
| 18161 | OPC_CheckPredicate, 35, // 4023: check predicate 35 |
| 18162 | OPC_Decode, 234, 20, 218, 2, // 4025: decode to VLD2DUPd32x2 using decoder 346 |
| 18163 | // 4025: } |
| 18164 | // 4025: } // switch Inst[3:0] |
| 18165 | // 4025: } else try { |
| 18166 | OPC_CheckPredicate, 35, // 4030: check predicate 35 |
| 18167 | OPC_Decode, 236, 20, 218, 2, // 4032: decode to VLD2DUPd32x2wb_register using decoder 346 |
| 18168 | // 4032: } |
| 18169 | // 4032: } |
| 18170 | // 4032: } // switch Inst[7:5] |
| 18171 | // 4032: } |
| 18172 | 14, 189, 1, // 4037: case 0xe: { |
| 18173 | OPC_SwitchField, 4, 4, // 4040: switch Inst[7:4] { |
| 18174 | 0, 29, // 4043: case 0x0: { |
| 18175 | OPC_CheckField, 20, 2, 2, // 4045: check Inst[21:20] == 0x2 |
| 18176 | OPC_CheckField, 23, 9, 233, 3, // 4049: check Inst[31:23] == 0x1e9 |
| 18177 | OPC_Scope, 11, // 4054: try { |
| 18178 | OPC_CheckField, 0, 4, 15, // 4056: check Inst[3:0] == 0xf |
| 18179 | OPC_CheckPredicate, 35, // 4060: check predicate 35 |
| 18180 | OPC_Decode, 191, 21, 219, 2, // 4062: decode to VLD3DUPd8 using decoder 347 |
| 18181 | // 4062: } else try { |
| 18182 | OPC_CheckPredicate, 35, // 4067: check predicate 35 |
| 18183 | OPC_Decode, 194, 21, 219, 2, // 4069: decode to VLD3DUPd8_UPD using decoder 347 |
| 18184 | // 4069: } |
| 18185 | // 4069: } |
| 18186 | 2, 29, // 4074: case 0x2: { |
| 18187 | OPC_CheckField, 20, 2, 2, // 4076: check Inst[21:20] == 0x2 |
| 18188 | OPC_CheckField, 23, 9, 233, 3, // 4080: check Inst[31:23] == 0x1e9 |
| 18189 | OPC_Scope, 11, // 4085: try { |
| 18190 | OPC_CheckField, 0, 4, 15, // 4087: check Inst[3:0] == 0xf |
| 18191 | OPC_CheckPredicate, 35, // 4091: check predicate 35 |
| 18192 | OPC_Decode, 205, 21, 219, 2, // 4093: decode to VLD3DUPq8 using decoder 347 |
| 18193 | // 4093: } else try { |
| 18194 | OPC_CheckPredicate, 35, // 4098: check predicate 35 |
| 18195 | OPC_Decode, 209, 21, 219, 2, // 4100: decode to VLD3DUPq8_UPD using decoder 347 |
| 18196 | // 4100: } |
| 18197 | // 4100: } |
| 18198 | 4, 29, // 4105: case 0x4: { |
| 18199 | OPC_CheckField, 20, 2, 2, // 4107: check Inst[21:20] == 0x2 |
| 18200 | OPC_CheckField, 23, 9, 233, 3, // 4111: check Inst[31:23] == 0x1e9 |
| 18201 | OPC_Scope, 11, // 4116: try { |
| 18202 | OPC_CheckField, 0, 4, 15, // 4118: check Inst[3:0] == 0xf |
| 18203 | OPC_CheckPredicate, 35, // 4122: check predicate 35 |
| 18204 | OPC_Decode, 183, 21, 219, 2, // 4124: decode to VLD3DUPd16 using decoder 347 |
| 18205 | // 4124: } else try { |
| 18206 | OPC_CheckPredicate, 35, // 4129: check predicate 35 |
| 18207 | OPC_Decode, 186, 21, 219, 2, // 4131: decode to VLD3DUPd16_UPD using decoder 347 |
| 18208 | // 4131: } |
| 18209 | // 4131: } |
| 18210 | 6, 29, // 4136: case 0x6: { |
| 18211 | OPC_CheckField, 20, 2, 2, // 4138: check Inst[21:20] == 0x2 |
| 18212 | OPC_CheckField, 23, 9, 233, 3, // 4142: check Inst[31:23] == 0x1e9 |
| 18213 | OPC_Scope, 11, // 4147: try { |
| 18214 | OPC_CheckField, 0, 4, 15, // 4149: check Inst[3:0] == 0xf |
| 18215 | OPC_CheckPredicate, 35, // 4153: check predicate 35 |
| 18216 | OPC_Decode, 195, 21, 219, 2, // 4155: decode to VLD3DUPq16 using decoder 347 |
| 18217 | // 4155: } else try { |
| 18218 | OPC_CheckPredicate, 35, // 4160: check predicate 35 |
| 18219 | OPC_Decode, 199, 21, 219, 2, // 4162: decode to VLD3DUPq16_UPD using decoder 347 |
| 18220 | // 4162: } |
| 18221 | // 4162: } |
| 18222 | 8, 29, // 4167: case 0x8: { |
| 18223 | OPC_CheckField, 20, 2, 2, // 4169: check Inst[21:20] == 0x2 |
| 18224 | OPC_CheckField, 23, 9, 233, 3, // 4173: check Inst[31:23] == 0x1e9 |
| 18225 | OPC_Scope, 11, // 4178: try { |
| 18226 | OPC_CheckField, 0, 4, 15, // 4180: check Inst[3:0] == 0xf |
| 18227 | OPC_CheckPredicate, 35, // 4184: check predicate 35 |
| 18228 | OPC_Decode, 187, 21, 219, 2, // 4186: decode to VLD3DUPd32 using decoder 347 |
| 18229 | // 4186: } else try { |
| 18230 | OPC_CheckPredicate, 35, // 4191: check predicate 35 |
| 18231 | OPC_Decode, 190, 21, 219, 2, // 4193: decode to VLD3DUPd32_UPD using decoder 347 |
| 18232 | // 4193: } |
| 18233 | // 4193: } |
| 18234 | 10, 0, // 4198: case 0xa: { |
| 18235 | OPC_CheckField, 20, 2, 2, // 4200: check Inst[21:20] == 0x2 |
| 18236 | OPC_CheckField, 23, 9, 233, 3, // 4204: check Inst[31:23] == 0x1e9 |
| 18237 | OPC_Scope, 11, // 4209: try { |
| 18238 | OPC_CheckField, 0, 4, 15, // 4211: check Inst[3:0] == 0xf |
| 18239 | OPC_CheckPredicate, 35, // 4215: check predicate 35 |
| 18240 | OPC_Decode, 200, 21, 219, 2, // 4217: decode to VLD3DUPq32 using decoder 347 |
| 18241 | // 4217: } else try { |
| 18242 | OPC_CheckPredicate, 35, // 4222: check predicate 35 |
| 18243 | OPC_Decode, 204, 21, 219, 2, // 4224: decode to VLD3DUPq32_UPD using decoder 347 |
| 18244 | // 4224: } |
| 18245 | // 4224: } |
| 18246 | // 4224: } // switch Inst[7:4] |
| 18247 | // 4224: } |
| 18248 | 15, 0, // 4229: case 0xf: { |
| 18249 | OPC_SwitchField, 5, 1, // 4231: switch Inst[5] { |
| 18250 | 0, 101, // 4234: case 0x0: { |
| 18251 | OPC_SwitchField, 7, 1, // 4236: switch Inst[7] { |
| 18252 | 0, 65, // 4239: case 0x0: { |
| 18253 | OPC_SwitchField, 6, 1, // 4241: switch Inst[6] { |
| 18254 | 0, 29, // 4244: case 0x0: { |
| 18255 | OPC_CheckField, 20, 2, 2, // 4246: check Inst[21:20] == 0x2 |
| 18256 | OPC_CheckField, 23, 9, 233, 3, // 4250: check Inst[31:23] == 0x1e9 |
| 18257 | OPC_Scope, 11, // 4255: try { |
| 18258 | OPC_CheckField, 0, 4, 15, // 4257: check Inst[3:0] == 0xf |
| 18259 | OPC_CheckPredicate, 35, // 4261: check predicate 35 |
| 18260 | OPC_Decode, 137, 22, 220, 2, // 4263: decode to VLD4DUPd8 using decoder 348 |
| 18261 | // 4263: } else try { |
| 18262 | OPC_CheckPredicate, 35, // 4268: check predicate 35 |
| 18263 | OPC_Decode, 140, 22, 220, 2, // 4270: decode to VLD4DUPd8_UPD using decoder 348 |
| 18264 | // 4270: } |
| 18265 | // 4270: } |
| 18266 | 1, 0, // 4275: case 0x1: { |
| 18267 | OPC_CheckField, 20, 2, 2, // 4277: check Inst[21:20] == 0x2 |
| 18268 | OPC_CheckField, 23, 9, 233, 3, // 4281: check Inst[31:23] == 0x1e9 |
| 18269 | OPC_Scope, 11, // 4286: try { |
| 18270 | OPC_CheckField, 0, 4, 15, // 4288: check Inst[3:0] == 0xf |
| 18271 | OPC_CheckPredicate, 35, // 4292: check predicate 35 |
| 18272 | OPC_Decode, 129, 22, 220, 2, // 4294: decode to VLD4DUPd16 using decoder 348 |
| 18273 | // 4294: } else try { |
| 18274 | OPC_CheckPredicate, 35, // 4299: check predicate 35 |
| 18275 | OPC_Decode, 132, 22, 220, 2, // 4301: decode to VLD4DUPd16_UPD using decoder 348 |
| 18276 | // 4301: } |
| 18277 | // 4301: } |
| 18278 | // 4301: } // switch Inst[6] |
| 18279 | // 4301: } |
| 18280 | 1, 0, // 4306: case 0x1: { |
| 18281 | OPC_CheckField, 20, 2, 2, // 4308: check Inst[21:20] == 0x2 |
| 18282 | OPC_CheckField, 23, 9, 233, 3, // 4312: check Inst[31:23] == 0x1e9 |
| 18283 | OPC_Scope, 11, // 4317: try { |
| 18284 | OPC_CheckField, 0, 4, 15, // 4319: check Inst[3:0] == 0xf |
| 18285 | OPC_CheckPredicate, 35, // 4323: check predicate 35 |
| 18286 | OPC_Decode, 133, 22, 220, 2, // 4325: decode to VLD4DUPd32 using decoder 348 |
| 18287 | // 4325: } else try { |
| 18288 | OPC_CheckPredicate, 35, // 4330: check predicate 35 |
| 18289 | OPC_Decode, 136, 22, 220, 2, // 4332: decode to VLD4DUPd32_UPD using decoder 348 |
| 18290 | // 4332: } |
| 18291 | // 4332: } |
| 18292 | // 4332: } // switch Inst[7] |
| 18293 | // 4332: } |
| 18294 | 1, 0, // 4337: case 0x1: { |
| 18295 | OPC_SwitchField, 7, 1, // 4339: switch Inst[7] { |
| 18296 | 0, 65, // 4342: case 0x0: { |
| 18297 | OPC_SwitchField, 6, 1, // 4344: switch Inst[6] { |
| 18298 | 0, 29, // 4347: case 0x0: { |
| 18299 | OPC_CheckField, 20, 2, 2, // 4349: check Inst[21:20] == 0x2 |
| 18300 | OPC_CheckField, 23, 9, 233, 3, // 4353: check Inst[31:23] == 0x1e9 |
| 18301 | OPC_Scope, 11, // 4358: try { |
| 18302 | OPC_CheckField, 0, 4, 15, // 4360: check Inst[3:0] == 0xf |
| 18303 | OPC_CheckPredicate, 35, // 4364: check predicate 35 |
| 18304 | OPC_Decode, 151, 22, 220, 2, // 4366: decode to VLD4DUPq8 using decoder 348 |
| 18305 | // 4366: } else try { |
| 18306 | OPC_CheckPredicate, 35, // 4371: check predicate 35 |
| 18307 | OPC_Decode, 155, 22, 220, 2, // 4373: decode to VLD4DUPq8_UPD using decoder 348 |
| 18308 | // 4373: } |
| 18309 | // 4373: } |
| 18310 | 1, 0, // 4378: case 0x1: { |
| 18311 | OPC_CheckField, 20, 2, 2, // 4380: check Inst[21:20] == 0x2 |
| 18312 | OPC_CheckField, 23, 9, 233, 3, // 4384: check Inst[31:23] == 0x1e9 |
| 18313 | OPC_Scope, 11, // 4389: try { |
| 18314 | OPC_CheckField, 0, 4, 15, // 4391: check Inst[3:0] == 0xf |
| 18315 | OPC_CheckPredicate, 35, // 4395: check predicate 35 |
| 18316 | OPC_Decode, 141, 22, 220, 2, // 4397: decode to VLD4DUPq16 using decoder 348 |
| 18317 | // 4397: } else try { |
| 18318 | OPC_CheckPredicate, 35, // 4402: check predicate 35 |
| 18319 | OPC_Decode, 145, 22, 220, 2, // 4404: decode to VLD4DUPq16_UPD using decoder 348 |
| 18320 | // 4404: } |
| 18321 | // 4404: } |
| 18322 | // 4404: } // switch Inst[6] |
| 18323 | // 4404: } |
| 18324 | 1, 0, // 4409: case 0x1: { |
| 18325 | OPC_CheckField, 20, 2, 2, // 4411: check Inst[21:20] == 0x2 |
| 18326 | OPC_CheckField, 23, 9, 233, 3, // 4415: check Inst[31:23] == 0x1e9 |
| 18327 | OPC_Scope, 11, // 4420: try { |
| 18328 | OPC_CheckField, 0, 4, 15, // 4422: check Inst[3:0] == 0xf |
| 18329 | OPC_CheckPredicate, 35, // 4426: check predicate 35 |
| 18330 | OPC_Decode, 146, 22, 220, 2, // 4428: decode to VLD4DUPq32 using decoder 348 |
| 18331 | // 4428: } else try { |
| 18332 | OPC_CheckPredicate, 35, // 4433: check predicate 35 |
| 18333 | OPC_Decode, 150, 22, 220, 2, // 4435: decode to VLD4DUPq32_UPD using decoder 348 |
| 18334 | // 4435: } |
| 18335 | // 4435: } |
| 18336 | // 4435: } // switch Inst[7] |
| 18337 | // 4435: } |
| 18338 | // 4435: } // switch Inst[5] |
| 18339 | // 4435: } |
| 18340 | // 4435: } // switch Inst[11:8] |
| 18341 | }; |
| 18342 | static const uint8_t DecoderTableThumb32[41] = { |
| 18343 | OPC_SwitchField, 12, 1, // 0: switch Inst[12] { |
| 18344 | 0, 19, // 3: case 0x0: { |
| 18345 | OPC_CheckPredicate, 44, // 5: check predicate 44 |
| 18346 | OPC_CheckField, 27, 5, 30, // 7: check Inst[31:27] == 0x1e |
| 18347 | OPC_CheckField, 14, 2, 3, // 11: check Inst[15:14] == 0x3 |
| 18348 | OPC_CheckField, 0, 1, 0, // 15: check Inst[0] == 0x0 |
| 18349 | OPC_Decode, 226, 34, 221, 2, // 19: decode to tBLXi using decoder 349 |
| 18350 | // 19: } |
| 18351 | 1, 0, // 24: case 0x1: { |
| 18352 | OPC_CheckPredicate, 0, // 26: check predicate 0 |
| 18353 | OPC_CheckField, 27, 5, 30, // 28: check Inst[31:27] == 0x1e |
| 18354 | OPC_CheckField, 14, 2, 3, // 32: check Inst[15:14] == 0x3 |
| 18355 | OPC_Decode, 224, 34, 222, 2, // 36: decode to tBL using decoder 350 |
| 18356 | // 36: } |
| 18357 | // 36: } // switch Inst[12] |
| 18358 | }; |
| 18359 | static const uint8_t DecoderTableThumb232[5767] = { |
| 18360 | OPC_SwitchField, 27, 5, // 0: switch Inst[31:27] { |
| 18361 | 29, 229, 11, // 3: case 0x1d: { |
| 18362 | OPC_SwitchField, 21, 2, // 6: switch Inst[22:21] { |
| 18363 | 0, 227, 2, // 9: case 0x0: { |
| 18364 | OPC_SwitchField, 23, 4, // 12: switch Inst[26:23] { |
| 18365 | 0, 33, // 15: case 0x0: { |
| 18366 | OPC_SwitchField, 20, 1, // 17: switch Inst[20] { |
| 18367 | 0, 13, // 20: case 0x0: { |
| 18368 | OPC_CheckPredicate, 45, // 22: check predicate 45 |
| 18369 | OPC_CheckField, 5, 15, 128, 220, 1, // 24: check Inst[19:5] == 0x6e00 |
| 18370 | OPC_Decode, 214, 33, 223, 2, // 30: decode to t2SRSDB using decoder 351 |
| 18371 | // 30: } |
| 18372 | 1, 0, // 35: case 0x1: { |
| 18373 | OPC_CheckPredicate, 45, // 37: check predicate 45 |
| 18374 | OPC_CheckField, 0, 16, 128, 128, 3, // 39: check Inst[15:0] == 0xc000 |
| 18375 | OPC_Decode, 149, 33, 224, 2, // 45: decode to t2RFEDB using decoder 352 |
| 18376 | // 45: } |
| 18377 | // 45: } // switch Inst[20] |
| 18378 | // 45: } |
| 18379 | 1, 46, // 50: case 0x1: { |
| 18380 | OPC_SwitchField, 20, 1, // 52: switch Inst[20] { |
| 18381 | 0, 15, // 55: case 0x0: { |
| 18382 | OPC_CheckPredicate, 9, // 57: check predicate 9 |
| 18383 | OPC_CheckField, 15, 1, 0, // 59: check Inst[15] == 0x0 |
| 18384 | OPC_CheckField, 13, 1, 0, // 63: check Inst[13] == 0x0 |
| 18385 | OPC_Decode, 248, 33, 225, 2, // 67: decode to t2STMIA using decoder 353 |
| 18386 | // 67: } |
| 18387 | 1, 0, // 72: case 0x1: { |
| 18388 | OPC_Scope, 15, // 74: try { |
| 18389 | OPC_CheckField, 13, 1, 0, // 76: check Inst[13] == 0x0 |
| 18390 | OPC_CheckPredicate, 46, // 80: check predicate 46 |
| 18391 | OPC_CheckField, 16, 4, 15, // 82: check Inst[19:16] == 0xf |
| 18392 | OPC_Decode, 231, 31, 226, 2, // 86: decode to t2CLRM using decoder 354 |
| 18393 | // 86: } else try { |
| 18394 | OPC_CheckPredicate, 9, // 91: check predicate 9 |
| 18395 | OPC_Decode, 165, 32, 227, 2, // 93: decode to t2LDMIA using decoder 355 |
| 18396 | // 93: } |
| 18397 | // 93: } |
| 18398 | // 93: } // switch Inst[20] |
| 18399 | // 93: } |
| 18400 | 2, 29, // 98: case 0x2: { |
| 18401 | OPC_SwitchField, 20, 1, // 100: switch Inst[20] { |
| 18402 | 0, 15, // 103: case 0x0: { |
| 18403 | OPC_CheckPredicate, 9, // 105: check predicate 9 |
| 18404 | OPC_CheckField, 15, 1, 0, // 107: check Inst[15] == 0x0 |
| 18405 | OPC_CheckField, 13, 1, 0, // 111: check Inst[13] == 0x0 |
| 18406 | OPC_Decode, 246, 33, 225, 2, // 115: decode to t2STMDB using decoder 353 |
| 18407 | // 115: } |
| 18408 | 1, 0, // 120: case 0x1: { |
| 18409 | OPC_CheckPredicate, 9, // 122: check predicate 9 |
| 18410 | OPC_Decode, 163, 32, 227, 2, // 124: decode to t2LDMDB using decoder 355 |
| 18411 | // 124: } |
| 18412 | // 124: } // switch Inst[20] |
| 18413 | // 124: } |
| 18414 | 3, 33, // 129: case 0x3: { |
| 18415 | OPC_SwitchField, 20, 1, // 131: switch Inst[20] { |
| 18416 | 0, 13, // 134: case 0x0: { |
| 18417 | OPC_CheckPredicate, 45, // 136: check predicate 45 |
| 18418 | OPC_CheckField, 5, 15, 128, 220, 1, // 138: check Inst[19:5] == 0x6e00 |
| 18419 | OPC_Decode, 216, 33, 223, 2, // 144: decode to t2SRSIA using decoder 351 |
| 18420 | // 144: } |
| 18421 | 1, 0, // 149: case 0x1: { |
| 18422 | OPC_CheckPredicate, 45, // 151: check predicate 45 |
| 18423 | OPC_CheckField, 0, 16, 128, 128, 3, // 153: check Inst[15:0] == 0xc000 |
| 18424 | OPC_Decode, 151, 33, 224, 2, // 159: decode to t2RFEIA using decoder 352 |
| 18425 | // 159: } |
| 18426 | // 159: } // switch Inst[20] |
| 18427 | // 159: } |
| 18428 | 4, 69, // 164: case 0x4: { |
| 18429 | OPC_Scope, 16, // 166: try { |
| 18430 | OPC_CheckField, 4, 11, 240, 1, // 168: check Inst[14:4] == 0xf0 |
| 18431 | OPC_CheckPredicate, 9, // 173: check predicate 9 |
| 18432 | OPC_CheckField, 20, 1, 1, // 175: check Inst[20] == 0x1 |
| 18433 | OPC_Decode, 167, 34, 228, 2, // 179: decode to t2TSTrr using decoder 356 |
| 18434 | OPC_Scope, 15, // 184: } else try { |
| 18435 | OPC_CheckField, 20, 1, 1, // 186: check Inst[20] == 0x1 |
| 18436 | OPC_CheckPredicate, 9, // 190: check predicate 9 |
| 18437 | OPC_CheckField, 8, 4, 15, // 192: check Inst[11:8] == 0xf |
| 18438 | OPC_Decode, 168, 34, 229, 2, // 196: decode to t2TSTrs using decoder 357 |
| 18439 | OPC_Scope, 20, // 201: } else try { |
| 18440 | OPC_CheckField, 4, 4, 0, // 203: check Inst[7:4] == 0x0 |
| 18441 | OPC_CheckPredicate, 9, // 207: check predicate 9 |
| 18442 | OPC_CheckField, 12, 3, 0, // 209: check Inst[14:12] == 0x0 |
| 18443 | OPC_SoftFail, 128, 128, 2, 0, // 213: softfail pos=0x00008000 neg=0x00000000 |
| 18444 | OPC_Decode, 206, 31, 230, 2, // 218: decode to t2ANDrr using decoder 358 |
| 18445 | // 218: } else try { |
| 18446 | OPC_CheckPredicate, 9, // 223: check predicate 9 |
| 18447 | OPC_SoftFail, 128, 128, 2, 0, // 225: softfail pos=0x00008000 neg=0x00000000 |
| 18448 | OPC_Decode, 207, 31, 231, 2, // 230: decode to t2ANDrs using decoder 359 |
| 18449 | // 230: } |
| 18450 | // 230: } |
| 18451 | 5, 69, // 235: case 0x5: { |
| 18452 | OPC_Scope, 16, // 237: try { |
| 18453 | OPC_CheckField, 4, 11, 240, 1, // 239: check Inst[14:4] == 0xf0 |
| 18454 | OPC_CheckPredicate, 9, // 244: check predicate 9 |
| 18455 | OPC_CheckField, 20, 1, 1, // 246: check Inst[20] == 0x1 |
| 18456 | OPC_Decode, 163, 34, 228, 2, // 250: decode to t2TEQrr using decoder 356 |
| 18457 | OPC_Scope, 15, // 255: } else try { |
| 18458 | OPC_CheckField, 20, 1, 1, // 257: check Inst[20] == 0x1 |
| 18459 | OPC_CheckPredicate, 9, // 261: check predicate 9 |
| 18460 | OPC_CheckField, 8, 4, 15, // 263: check Inst[11:8] == 0xf |
| 18461 | OPC_Decode, 164, 34, 229, 2, // 267: decode to t2TEQrs using decoder 357 |
| 18462 | OPC_Scope, 20, // 272: } else try { |
| 18463 | OPC_CheckField, 4, 4, 0, // 274: check Inst[7:4] == 0x0 |
| 18464 | OPC_CheckPredicate, 9, // 278: check predicate 9 |
| 18465 | OPC_CheckField, 12, 3, 0, // 280: check Inst[14:12] == 0x0 |
| 18466 | OPC_SoftFail, 128, 128, 2, 0, // 284: softfail pos=0x00008000 neg=0x00000000 |
| 18467 | OPC_Decode, 132, 32, 230, 2, // 289: decode to t2EORrr using decoder 358 |
| 18468 | // 289: } else try { |
| 18469 | OPC_CheckPredicate, 9, // 294: check predicate 9 |
| 18470 | OPC_SoftFail, 128, 128, 2, 0, // 296: softfail pos=0x00008000 neg=0x00000000 |
| 18471 | OPC_Decode, 133, 32, 231, 2, // 301: decode to t2EORrs using decoder 359 |
| 18472 | // 301: } |
| 18473 | // 301: } |
| 18474 | 6, 0, // 306: case 0x6: { |
| 18475 | OPC_Scope, 16, // 308: try { |
| 18476 | OPC_CheckField, 4, 11, 240, 1, // 310: check Inst[14:4] == 0xf0 |
| 18477 | OPC_CheckPredicate, 9, // 315: check predicate 9 |
| 18478 | OPC_CheckField, 20, 1, 1, // 317: check Inst[20] == 0x1 |
| 18479 | OPC_Decode, 234, 31, 232, 2, // 321: decode to t2CMNzrr using decoder 360 |
| 18480 | OPC_Scope, 15, // 326: } else try { |
| 18481 | OPC_CheckField, 20, 1, 1, // 328: check Inst[20] == 0x1 |
| 18482 | OPC_CheckPredicate, 9, // 332: check predicate 9 |
| 18483 | OPC_CheckField, 8, 4, 15, // 334: check Inst[11:8] == 0xf |
| 18484 | OPC_Decode, 235, 31, 233, 2, // 338: decode to t2CMNzrs using decoder 361 |
| 18485 | OPC_Scope, 15, // 343: } else try { |
| 18486 | OPC_CheckField, 4, 4, 0, // 345: check Inst[7:4] == 0x0 |
| 18487 | OPC_CheckPredicate, 9, // 349: check predicate 9 |
| 18488 | OPC_CheckField, 12, 3, 0, // 351: check Inst[14:12] == 0x0 |
| 18489 | OPC_Decode, 200, 31, 234, 2, // 355: decode to t2ADDrr using decoder 362 |
| 18490 | // 355: } else try { |
| 18491 | OPC_CheckPredicate, 9, // 360: check predicate 9 |
| 18492 | OPC_Decode, 201, 31, 235, 2, // 362: decode to t2ADDrs using decoder 363 |
| 18493 | // 362: } |
| 18494 | // 362: } |
| 18495 | // 362: } // switch Inst[26:23] |
| 18496 | // 362: } |
| 18497 | 1, 232, 1, // 367: case 0x1: { |
| 18498 | OPC_SwitchField, 23, 4, // 370: switch Inst[26:23] { |
| 18499 | 0, 33, // 373: case 0x0: { |
| 18500 | OPC_SwitchField, 20, 1, // 375: switch Inst[20] { |
| 18501 | 0, 13, // 378: case 0x0: { |
| 18502 | OPC_CheckPredicate, 45, // 380: check predicate 45 |
| 18503 | OPC_CheckField, 5, 15, 128, 220, 1, // 382: check Inst[19:5] == 0x6e00 |
| 18504 | OPC_Decode, 215, 33, 223, 2, // 388: decode to t2SRSDB_UPD using decoder 351 |
| 18505 | // 388: } |
| 18506 | 1, 0, // 393: case 0x1: { |
| 18507 | OPC_CheckPredicate, 45, // 395: check predicate 45 |
| 18508 | OPC_CheckField, 0, 16, 128, 128, 3, // 397: check Inst[15:0] == 0xc000 |
| 18509 | OPC_Decode, 150, 33, 224, 2, // 403: decode to t2RFEDBW using decoder 352 |
| 18510 | // 403: } |
| 18511 | // 403: } // switch Inst[20] |
| 18512 | // 403: } |
| 18513 | 1, 29, // 408: case 0x1: { |
| 18514 | OPC_SwitchField, 20, 1, // 410: switch Inst[20] { |
| 18515 | 0, 15, // 413: case 0x0: { |
| 18516 | OPC_CheckPredicate, 9, // 415: check predicate 9 |
| 18517 | OPC_CheckField, 15, 1, 0, // 417: check Inst[15] == 0x0 |
| 18518 | OPC_CheckField, 13, 1, 0, // 421: check Inst[13] == 0x0 |
| 18519 | OPC_Decode, 249, 33, 236, 2, // 425: decode to t2STMIA_UPD using decoder 364 |
| 18520 | // 425: } |
| 18521 | 1, 0, // 430: case 0x1: { |
| 18522 | OPC_CheckPredicate, 9, // 432: check predicate 9 |
| 18523 | OPC_Decode, 166, 32, 237, 2, // 434: decode to t2LDMIA_UPD using decoder 365 |
| 18524 | // 434: } |
| 18525 | // 434: } // switch Inst[20] |
| 18526 | // 434: } |
| 18527 | 2, 29, // 439: case 0x2: { |
| 18528 | OPC_SwitchField, 20, 1, // 441: switch Inst[20] { |
| 18529 | 0, 15, // 444: case 0x0: { |
| 18530 | OPC_CheckPredicate, 9, // 446: check predicate 9 |
| 18531 | OPC_CheckField, 15, 1, 0, // 448: check Inst[15] == 0x0 |
| 18532 | OPC_CheckField, 13, 1, 0, // 452: check Inst[13] == 0x0 |
| 18533 | OPC_Decode, 247, 33, 236, 2, // 456: decode to t2STMDB_UPD using decoder 364 |
| 18534 | // 456: } |
| 18535 | 1, 0, // 461: case 0x1: { |
| 18536 | OPC_CheckPredicate, 9, // 463: check predicate 9 |
| 18537 | OPC_Decode, 164, 32, 237, 2, // 465: decode to t2LDMDB_UPD using decoder 365 |
| 18538 | // 465: } |
| 18539 | // 465: } // switch Inst[20] |
| 18540 | // 465: } |
| 18541 | 3, 33, // 470: case 0x3: { |
| 18542 | OPC_SwitchField, 20, 1, // 472: switch Inst[20] { |
| 18543 | 0, 13, // 475: case 0x0: { |
| 18544 | OPC_CheckPredicate, 45, // 477: check predicate 45 |
| 18545 | OPC_CheckField, 5, 15, 128, 220, 1, // 479: check Inst[19:5] == 0x6e00 |
| 18546 | OPC_Decode, 217, 33, 223, 2, // 485: decode to t2SRSIA_UPD using decoder 351 |
| 18547 | // 485: } |
| 18548 | 1, 0, // 490: case 0x1: { |
| 18549 | OPC_CheckPredicate, 45, // 492: check predicate 45 |
| 18550 | OPC_CheckField, 0, 16, 128, 128, 3, // 494: check Inst[15:0] == 0xc000 |
| 18551 | OPC_Decode, 152, 33, 224, 2, // 500: decode to t2RFEIAW using decoder 352 |
| 18552 | // 500: } |
| 18553 | // 500: } // switch Inst[20] |
| 18554 | // 500: } |
| 18555 | 4, 34, // 505: case 0x4: { |
| 18556 | OPC_Scope, 20, // 507: try { |
| 18557 | OPC_CheckField, 4, 4, 0, // 509: check Inst[7:4] == 0x0 |
| 18558 | OPC_CheckPredicate, 9, // 513: check predicate 9 |
| 18559 | OPC_CheckField, 12, 3, 0, // 515: check Inst[14:12] == 0x0 |
| 18560 | OPC_SoftFail, 128, 128, 2, 0, // 519: softfail pos=0x00008000 neg=0x00000000 |
| 18561 | OPC_Decode, 222, 31, 230, 2, // 524: decode to t2BICrr using decoder 358 |
| 18562 | // 524: } else try { |
| 18563 | OPC_CheckPredicate, 9, // 529: check predicate 9 |
| 18564 | OPC_SoftFail, 128, 128, 2, 0, // 531: softfail pos=0x00008000 neg=0x00000000 |
| 18565 | OPC_Decode, 223, 31, 231, 2, // 536: decode to t2BICrs using decoder 359 |
| 18566 | // 536: } |
| 18567 | // 536: } |
| 18568 | 7, 0, // 541: case 0x7: { |
| 18569 | OPC_Scope, 16, // 543: try { |
| 18570 | OPC_CheckField, 4, 11, 240, 1, // 545: check Inst[14:4] == 0xf0 |
| 18571 | OPC_CheckPredicate, 9, // 550: check predicate 9 |
| 18572 | OPC_CheckField, 20, 1, 1, // 552: check Inst[20] == 0x1 |
| 18573 | OPC_Decode, 237, 31, 232, 2, // 556: decode to t2CMPrr using decoder 360 |
| 18574 | OPC_Scope, 15, // 561: } else try { |
| 18575 | OPC_CheckField, 20, 1, 1, // 563: check Inst[20] == 0x1 |
| 18576 | OPC_CheckPredicate, 9, // 567: check predicate 9 |
| 18577 | OPC_CheckField, 8, 4, 15, // 569: check Inst[11:8] == 0xf |
| 18578 | OPC_Decode, 238, 31, 233, 2, // 573: decode to t2CMPrs using decoder 361 |
| 18579 | OPC_Scope, 15, // 578: } else try { |
| 18580 | OPC_CheckField, 4, 4, 0, // 580: check Inst[7:4] == 0x0 |
| 18581 | OPC_CheckPredicate, 9, // 584: check predicate 9 |
| 18582 | OPC_CheckField, 12, 3, 0, // 586: check Inst[14:12] == 0x0 |
| 18583 | OPC_Decode, 150, 34, 234, 2, // 590: decode to t2SUBrr using decoder 362 |
| 18584 | // 590: } else try { |
| 18585 | OPC_CheckPredicate, 9, // 595: check predicate 9 |
| 18586 | OPC_Decode, 151, 34, 235, 2, // 597: decode to t2SUBrs using decoder 363 |
| 18587 | // 597: } |
| 18588 | // 597: } |
| 18589 | // 597: } // switch Inst[26:23] |
| 18590 | // 597: } |
| 18591 | 2, 232, 5, // 602: case 0x2: { |
| 18592 | OPC_SwitchField, 24, 3, // 605: switch Inst[26:24] { |
| 18593 | 0, 183, 3, // 608: case 0x0: { |
| 18594 | OPC_SwitchField, 20, 1, // 611: switch Inst[20] { |
| 18595 | 0, 220, 1, // 614: case 0x0: { |
| 18596 | OPC_SwitchField, 23, 1, // 617: switch Inst[23] { |
| 18597 | 0, 76, // 620: case 0x0: { |
| 18598 | OPC_Scope, 67, // 622: try { |
| 18599 | OPC_SwitchField, 6, 2, // 624: switch Inst[7:6] { |
| 18600 | 0, 14, // 627: case 0x0: { |
| 18601 | OPC_CheckPredicate, 1, // 629: check predicate 1 |
| 18602 | OPC_CheckField, 12, 4, 15, // 631: check Inst[15:12] == 0xf |
| 18603 | OPC_SoftFail, 63, 0, // 635: softfail pos=0x0000003f neg=0x00000000 |
| 18604 | OPC_Decode, 169, 34, 238, 2, // 638: decode to t2TT using decoder 366 |
| 18605 | // 638: } |
| 18606 | 1, 14, // 643: case 0x1: { |
| 18607 | OPC_CheckPredicate, 1, // 645: check predicate 1 |
| 18608 | OPC_CheckField, 12, 4, 15, // 647: check Inst[15:12] == 0xf |
| 18609 | OPC_SoftFail, 63, 0, // 651: softfail pos=0x0000003f neg=0x00000000 |
| 18610 | OPC_Decode, 172, 34, 238, 2, // 654: decode to t2TTT using decoder 366 |
| 18611 | // 654: } |
| 18612 | 2, 14, // 659: case 0x2: { |
| 18613 | OPC_CheckPredicate, 1, // 661: check predicate 1 |
| 18614 | OPC_CheckField, 12, 4, 15, // 663: check Inst[15:12] == 0xf |
| 18615 | OPC_SoftFail, 63, 0, // 667: softfail pos=0x0000003f neg=0x00000000 |
| 18616 | OPC_Decode, 170, 34, 238, 2, // 670: decode to t2TTA using decoder 366 |
| 18617 | // 670: } |
| 18618 | 3, 0, // 675: case 0x3: { |
| 18619 | OPC_CheckPredicate, 1, // 677: check predicate 1 |
| 18620 | OPC_CheckField, 12, 4, 15, // 679: check Inst[15:12] == 0xf |
| 18621 | OPC_SoftFail, 63, 0, // 683: softfail pos=0x0000003f neg=0x00000000 |
| 18622 | OPC_Decode, 171, 34, 238, 2, // 686: decode to t2TTAT using decoder 366 |
| 18623 | // 686: } |
| 18624 | // 686: } // switch Inst[7:6] |
| 18625 | // 686: } else try { |
| 18626 | OPC_CheckPredicate, 4, // 691: check predicate 4 |
| 18627 | OPC_Decode, 131, 34, 239, 2, // 693: decode to t2STREX using decoder 367 |
| 18628 | // 693: } |
| 18629 | // 693: } |
| 18630 | 1, 0, // 698: case 0x1: { |
| 18631 | OPC_SwitchField, 4, 4, // 700: switch Inst[7:4] { |
| 18632 | 4, 11, // 703: case 0x4: { |
| 18633 | OPC_CheckPredicate, 4, // 705: check predicate 4 |
| 18634 | OPC_CheckField, 8, 4, 15, // 707: check Inst[11:8] == 0xf |
| 18635 | OPC_Decode, 132, 34, 240, 2, // 711: decode to t2STREXB using decoder 368 |
| 18636 | // 711: } |
| 18637 | 5, 11, // 716: case 0x5: { |
| 18638 | OPC_CheckPredicate, 4, // 718: check predicate 4 |
| 18639 | OPC_CheckField, 8, 4, 15, // 720: check Inst[11:8] == 0xf |
| 18640 | OPC_Decode, 134, 34, 240, 2, // 724: decode to t2STREXH using decoder 368 |
| 18641 | // 724: } |
| 18642 | 7, 7, // 729: case 0x7: { |
| 18643 | OPC_CheckPredicate, 45, // 731: check predicate 45 |
| 18644 | OPC_Decode, 133, 34, 241, 2, // 733: decode to t2STREXD using decoder 369 |
| 18645 | // 733: } |
| 18646 | 8, 15, // 738: case 0x8: { |
| 18647 | OPC_CheckPredicate, 47, // 740: check predicate 47 |
| 18648 | OPC_CheckField, 8, 4, 15, // 742: check Inst[11:8] == 0xf |
| 18649 | OPC_CheckField, 0, 4, 15, // 746: check Inst[3:0] == 0xf |
| 18650 | OPC_Decode, 240, 33, 242, 2, // 750: decode to t2STLB using decoder 370 |
| 18651 | // 750: } |
| 18652 | 9, 15, // 755: case 0x9: { |
| 18653 | OPC_CheckPredicate, 47, // 757: check predicate 47 |
| 18654 | OPC_CheckField, 8, 4, 15, // 759: check Inst[11:8] == 0xf |
| 18655 | OPC_CheckField, 0, 4, 15, // 763: check Inst[3:0] == 0xf |
| 18656 | OPC_Decode, 245, 33, 242, 2, // 767: decode to t2STLH using decoder 370 |
| 18657 | // 767: } |
| 18658 | 10, 15, // 772: case 0xa: { |
| 18659 | OPC_CheckPredicate, 47, // 774: check predicate 47 |
| 18660 | OPC_CheckField, 8, 4, 15, // 776: check Inst[11:8] == 0xf |
| 18661 | OPC_CheckField, 0, 4, 15, // 780: check Inst[3:0] == 0xf |
| 18662 | OPC_Decode, 239, 33, 242, 2, // 784: decode to t2STL using decoder 370 |
| 18663 | // 784: } |
| 18664 | 12, 11, // 789: case 0xc: { |
| 18665 | OPC_CheckPredicate, 48, // 791: check predicate 48 |
| 18666 | OPC_CheckField, 8, 4, 15, // 793: check Inst[11:8] == 0xf |
| 18667 | OPC_Decode, 242, 33, 240, 2, // 797: decode to t2STLEXB using decoder 368 |
| 18668 | // 797: } |
| 18669 | 13, 11, // 802: case 0xd: { |
| 18670 | OPC_CheckPredicate, 48, // 804: check predicate 48 |
| 18671 | OPC_CheckField, 8, 4, 15, // 806: check Inst[11:8] == 0xf |
| 18672 | OPC_Decode, 244, 33, 240, 2, // 810: decode to t2STLEXH using decoder 368 |
| 18673 | // 810: } |
| 18674 | 14, 11, // 815: case 0xe: { |
| 18675 | OPC_CheckPredicate, 48, // 817: check predicate 48 |
| 18676 | OPC_CheckField, 8, 4, 15, // 819: check Inst[11:8] == 0xf |
| 18677 | OPC_Decode, 241, 33, 240, 2, // 823: decode to t2STLEX using decoder 368 |
| 18678 | // 823: } |
| 18679 | 15, 0, // 828: case 0xf: { |
| 18680 | OPC_CheckPredicate, 49, // 830: check predicate 49 |
| 18681 | OPC_Decode, 243, 33, 241, 2, // 832: decode to t2STLEXD using decoder 369 |
| 18682 | // 832: } |
| 18683 | // 832: } // switch Inst[7:4] |
| 18684 | // 832: } |
| 18685 | // 832: } // switch Inst[23] |
| 18686 | // 832: } |
| 18687 | 1, 0, // 837: case 0x1: { |
| 18688 | OPC_SwitchField, 23, 1, // 839: switch Inst[23] { |
| 18689 | 0, 11, // 842: case 0x0: { |
| 18690 | OPC_CheckPredicate, 4, // 844: check predicate 4 |
| 18691 | OPC_CheckField, 8, 4, 15, // 846: check Inst[11:8] == 0xf |
| 18692 | OPC_Decode, 177, 32, 243, 2, // 850: decode to t2LDREX using decoder 371 |
| 18693 | // 850: } |
| 18694 | 1, 0, // 855: case 0x1: { |
| 18695 | OPC_SwitchField, 4, 4, // 857: switch Inst[7:4] { |
| 18696 | 0, 12, // 860: case 0x0: { |
| 18697 | OPC_CheckPredicate, 9, // 862: check predicate 9 |
| 18698 | OPC_CheckField, 8, 8, 240, 1, // 864: check Inst[15:8] == 0xf0 |
| 18699 | OPC_Decode, 160, 34, 244, 2, // 869: decode to t2TBB using decoder 372 |
| 18700 | // 869: } |
| 18701 | 1, 12, // 874: case 0x1: { |
| 18702 | OPC_CheckPredicate, 9, // 876: check predicate 9 |
| 18703 | OPC_CheckField, 8, 8, 240, 1, // 878: check Inst[15:8] == 0xf0 |
| 18704 | OPC_Decode, 161, 34, 244, 2, // 883: decode to t2TBH using decoder 372 |
| 18705 | // 883: } |
| 18706 | 4, 15, // 888: case 0x4: { |
| 18707 | OPC_CheckPredicate, 4, // 890: check predicate 4 |
| 18708 | OPC_CheckField, 8, 4, 15, // 892: check Inst[11:8] == 0xf |
| 18709 | OPC_CheckField, 0, 4, 15, // 896: check Inst[3:0] == 0xf |
| 18710 | OPC_Decode, 178, 32, 242, 2, // 900: decode to t2LDREXB using decoder 370 |
| 18711 | // 900: } |
| 18712 | 5, 15, // 905: case 0x5: { |
| 18713 | OPC_CheckPredicate, 4, // 907: check predicate 4 |
| 18714 | OPC_CheckField, 8, 4, 15, // 909: check Inst[11:8] == 0xf |
| 18715 | OPC_CheckField, 0, 4, 15, // 913: check Inst[3:0] == 0xf |
| 18716 | OPC_Decode, 180, 32, 242, 2, // 917: decode to t2LDREXH using decoder 370 |
| 18717 | // 917: } |
| 18718 | 7, 11, // 922: case 0x7: { |
| 18719 | OPC_CheckPredicate, 45, // 924: check predicate 45 |
| 18720 | OPC_CheckField, 0, 4, 15, // 926: check Inst[3:0] == 0xf |
| 18721 | OPC_Decode, 179, 32, 245, 2, // 930: decode to t2LDREXD using decoder 373 |
| 18722 | // 930: } |
| 18723 | 8, 15, // 935: case 0x8: { |
| 18724 | OPC_CheckPredicate, 47, // 937: check predicate 47 |
| 18725 | OPC_CheckField, 8, 4, 15, // 939: check Inst[11:8] == 0xf |
| 18726 | OPC_CheckField, 0, 4, 15, // 943: check Inst[3:0] == 0xf |
| 18727 | OPC_Decode, 141, 32, 242, 2, // 947: decode to t2LDAB using decoder 370 |
| 18728 | // 947: } |
| 18729 | 9, 15, // 952: case 0x9: { |
| 18730 | OPC_CheckPredicate, 47, // 954: check predicate 47 |
| 18731 | OPC_CheckField, 8, 4, 15, // 956: check Inst[11:8] == 0xf |
| 18732 | OPC_CheckField, 0, 4, 15, // 960: check Inst[3:0] == 0xf |
| 18733 | OPC_Decode, 146, 32, 242, 2, // 964: decode to t2LDAH using decoder 370 |
| 18734 | // 964: } |
| 18735 | 10, 15, // 969: case 0xa: { |
| 18736 | OPC_CheckPredicate, 47, // 971: check predicate 47 |
| 18737 | OPC_CheckField, 8, 4, 15, // 973: check Inst[11:8] == 0xf |
| 18738 | OPC_CheckField, 0, 4, 15, // 977: check Inst[3:0] == 0xf |
| 18739 | OPC_Decode, 140, 32, 242, 2, // 981: decode to t2LDA using decoder 370 |
| 18740 | // 981: } |
| 18741 | 12, 15, // 986: case 0xc: { |
| 18742 | OPC_CheckPredicate, 48, // 988: check predicate 48 |
| 18743 | OPC_CheckField, 8, 4, 15, // 990: check Inst[11:8] == 0xf |
| 18744 | OPC_CheckField, 0, 4, 15, // 994: check Inst[3:0] == 0xf |
| 18745 | OPC_Decode, 143, 32, 242, 2, // 998: decode to t2LDAEXB using decoder 370 |
| 18746 | // 998: } |
| 18747 | 13, 15, // 1003: case 0xd: { |
| 18748 | OPC_CheckPredicate, 48, // 1005: check predicate 48 |
| 18749 | OPC_CheckField, 8, 4, 15, // 1007: check Inst[11:8] == 0xf |
| 18750 | OPC_CheckField, 0, 4, 15, // 1011: check Inst[3:0] == 0xf |
| 18751 | OPC_Decode, 145, 32, 242, 2, // 1015: decode to t2LDAEXH using decoder 370 |
| 18752 | // 1015: } |
| 18753 | 14, 15, // 1020: case 0xe: { |
| 18754 | OPC_CheckPredicate, 48, // 1022: check predicate 48 |
| 18755 | OPC_CheckField, 8, 4, 15, // 1024: check Inst[11:8] == 0xf |
| 18756 | OPC_CheckField, 0, 4, 15, // 1028: check Inst[3:0] == 0xf |
| 18757 | OPC_Decode, 142, 32, 242, 2, // 1032: decode to t2LDAEX using decoder 370 |
| 18758 | // 1032: } |
| 18759 | 15, 0, // 1037: case 0xf: { |
| 18760 | OPC_CheckPredicate, 49, // 1039: check predicate 49 |
| 18761 | OPC_CheckField, 0, 4, 15, // 1041: check Inst[3:0] == 0xf |
| 18762 | OPC_Decode, 144, 32, 245, 2, // 1045: decode to t2LDAEXD using decoder 373 |
| 18763 | // 1045: } |
| 18764 | // 1045: } // switch Inst[7:4] |
| 18765 | // 1045: } |
| 18766 | // 1045: } // switch Inst[23] |
| 18767 | // 1045: } |
| 18768 | // 1045: } // switch Inst[20] |
| 18769 | // 1045: } |
| 18770 | 1, 21, // 1050: case 0x1: { |
| 18771 | OPC_SwitchField, 20, 1, // 1052: switch Inst[20] { |
| 18772 | 0, 7, // 1055: case 0x0: { |
| 18773 | OPC_CheckPredicate, 9, // 1057: check predicate 9 |
| 18774 | OPC_Decode, 130, 34, 246, 2, // 1059: decode to t2STRDi8 using decoder 374 |
| 18775 | // 1059: } |
| 18776 | 1, 0, // 1064: case 0x1: { |
| 18777 | OPC_CheckPredicate, 9, // 1066: check predicate 9 |
| 18778 | OPC_Decode, 176, 32, 246, 2, // 1068: decode to t2LDRDi8 using decoder 374 |
| 18779 | // 1068: } |
| 18780 | // 1068: } // switch Inst[20] |
| 18781 | // 1068: } |
| 18782 | 2, 216, 1, // 1073: case 0x2: { |
| 18783 | OPC_SwitchField, 23, 1, // 1076: switch Inst[23] { |
| 18784 | 0, 179, 1, // 1079: case 0x0: { |
| 18785 | OPC_Scope, 51, // 1082: try { |
| 18786 | OPC_SwitchField, 4, 4, // 1084: switch Inst[7:4] { |
| 18787 | 0, 24, // 1087: case 0x0: { |
| 18788 | OPC_CheckField, 12, 4, 0, // 1089: check Inst[15:12] == 0x0 |
| 18789 | OPC_Scope, 11, // 1093: try { |
| 18790 | OPC_CheckField, 16, 4, 15, // 1095: check Inst[19:16] == 0xf |
| 18791 | OPC_CheckPredicate, 9, // 1099: check predicate 9 |
| 18792 | OPC_Decode, 225, 32, 247, 2, // 1101: decode to t2MOVr using decoder 375 |
| 18793 | // 1101: } else try { |
| 18794 | OPC_CheckPredicate, 9, // 1106: check predicate 9 |
| 18795 | OPC_Decode, 245, 32, 230, 2, // 1108: decode to t2ORRrr using decoder 358 |
| 18796 | // 1108: } |
| 18797 | // 1108: } |
| 18798 | 3, 0, // 1113: case 0x3: { |
| 18799 | OPC_CheckPredicate, 9, // 1115: check predicate 9 |
| 18800 | OPC_CheckField, 16, 4, 15, // 1117: check Inst[19:16] == 0xf |
| 18801 | OPC_CheckField, 12, 3, 0, // 1121: check Inst[14:12] == 0x0 |
| 18802 | OPC_SoftFail, 128, 128, 2, 0, // 1125: softfail pos=0x00008000 neg=0x00000000 |
| 18803 | OPC_Decode, 155, 33, 248, 2, // 1130: decode to t2RRX using decoder 376 |
| 18804 | // 1130: } |
| 18805 | // 1130: } // switch Inst[7:4] |
| 18806 | // 1130: } else try { |
| 18807 | OPC_SwitchField, 15, 1, // 1135: switch Inst[15] { |
| 18808 | 0, 64, // 1138: case 0x0: { |
| 18809 | OPC_Scope, 55, // 1140: try { |
| 18810 | OPC_SwitchField, 4, 2, // 1142: switch Inst[5:4] { |
| 18811 | 0, 11, // 1145: case 0x0: { |
| 18812 | OPC_CheckPredicate, 9, // 1147: check predicate 9 |
| 18813 | OPC_CheckField, 16, 4, 15, // 1149: check Inst[19:16] == 0xf |
| 18814 | OPC_Decode, 211, 32, 249, 2, // 1153: decode to t2LSLri using decoder 377 |
| 18815 | // 1153: } |
| 18816 | 1, 11, // 1158: case 0x1: { |
| 18817 | OPC_CheckPredicate, 9, // 1160: check predicate 9 |
| 18818 | OPC_CheckField, 16, 4, 15, // 1162: check Inst[19:16] == 0xf |
| 18819 | OPC_Decode, 213, 32, 249, 2, // 1166: decode to t2LSRri using decoder 377 |
| 18820 | // 1166: } |
| 18821 | 2, 11, // 1171: case 0x2: { |
| 18822 | OPC_CheckPredicate, 9, // 1173: check predicate 9 |
| 18823 | OPC_CheckField, 16, 4, 15, // 1175: check Inst[19:16] == 0xf |
| 18824 | OPC_Decode, 208, 31, 249, 2, // 1179: decode to t2ASRri using decoder 377 |
| 18825 | // 1179: } |
| 18826 | 3, 0, // 1184: case 0x3: { |
| 18827 | OPC_CheckPredicate, 9, // 1186: check predicate 9 |
| 18828 | OPC_CheckField, 16, 4, 15, // 1188: check Inst[19:16] == 0xf |
| 18829 | OPC_Decode, 153, 33, 249, 2, // 1192: decode to t2RORri using decoder 377 |
| 18830 | // 1192: } |
| 18831 | // 1192: } // switch Inst[5:4] |
| 18832 | // 1192: } else try { |
| 18833 | OPC_CheckPredicate, 9, // 1197: check predicate 9 |
| 18834 | OPC_Decode, 246, 32, 231, 2, // 1199: decode to t2ORRrs using decoder 359 |
| 18835 | // 1199: } |
| 18836 | // 1199: } |
| 18837 | 1, 0, // 1204: case 0x1: { |
| 18838 | OPC_SwitchField, 12, 3, // 1206: switch Inst[14:12] { |
| 18839 | 0, 11, // 1209: case 0x0: { |
| 18840 | OPC_CheckPredicate, 46, // 1211: check predicate 46 |
| 18841 | OPC_CheckField, 20, 1, 1, // 1213: check Inst[20] == 0x1 |
| 18842 | OPC_Decode, 248, 31, 250, 2, // 1217: decode to t2CSEL using decoder 378 |
| 18843 | // 1217: } |
| 18844 | 1, 11, // 1222: case 0x1: { |
| 18845 | OPC_CheckPredicate, 46, // 1224: check predicate 46 |
| 18846 | OPC_CheckField, 20, 1, 1, // 1226: check Inst[20] == 0x1 |
| 18847 | OPC_Decode, 249, 31, 250, 2, // 1230: decode to t2CSINC using decoder 378 |
| 18848 | // 1230: } |
| 18849 | 2, 11, // 1235: case 0x2: { |
| 18850 | OPC_CheckPredicate, 46, // 1237: check predicate 46 |
| 18851 | OPC_CheckField, 20, 1, 1, // 1239: check Inst[20] == 0x1 |
| 18852 | OPC_Decode, 250, 31, 250, 2, // 1243: decode to t2CSINV using decoder 378 |
| 18853 | // 1243: } |
| 18854 | 3, 0, // 1248: case 0x3: { |
| 18855 | OPC_CheckPredicate, 46, // 1250: check predicate 46 |
| 18856 | OPC_CheckField, 20, 1, 1, // 1252: check Inst[20] == 0x1 |
| 18857 | OPC_Decode, 251, 31, 250, 2, // 1256: decode to t2CSNEG using decoder 378 |
| 18858 | // 1256: } |
| 18859 | // 1256: } // switch Inst[14:12] |
| 18860 | // 1256: } |
| 18861 | // 1256: } // switch Inst[15] |
| 18862 | // 1256: } |
| 18863 | // 1256: } |
| 18864 | 1, 0, // 1261: case 0x1: { |
| 18865 | OPC_SwitchField, 4, 2, // 1263: switch Inst[5:4] { |
| 18866 | 0, 11, // 1266: case 0x0: { |
| 18867 | OPC_CheckPredicate, 50, // 1268: check predicate 50 |
| 18868 | OPC_CheckField, 20, 1, 0, // 1270: check Inst[20] == 0x0 |
| 18869 | OPC_Decode, 250, 32, 251, 2, // 1274: decode to t2PKHBT using decoder 379 |
| 18870 | // 1274: } |
| 18871 | 2, 0, // 1279: case 0x2: { |
| 18872 | OPC_CheckPredicate, 50, // 1281: check predicate 50 |
| 18873 | OPC_CheckField, 20, 1, 0, // 1283: check Inst[20] == 0x0 |
| 18874 | OPC_Decode, 251, 32, 251, 2, // 1287: decode to t2PKHTB using decoder 379 |
| 18875 | // 1287: } |
| 18876 | // 1287: } // switch Inst[5:4] |
| 18877 | // 1287: } |
| 18878 | // 1287: } // switch Inst[23] |
| 18879 | // 1287: } |
| 18880 | 3, 0, // 1292: case 0x3: { |
| 18881 | OPC_SwitchField, 23, 1, // 1294: switch Inst[23] { |
| 18882 | 0, 24, // 1297: case 0x0: { |
| 18883 | OPC_Scope, 15, // 1299: try { |
| 18884 | OPC_CheckField, 4, 4, 0, // 1301: check Inst[7:4] == 0x0 |
| 18885 | OPC_CheckPredicate, 9, // 1305: check predicate 9 |
| 18886 | OPC_CheckField, 12, 3, 0, // 1307: check Inst[14:12] == 0x0 |
| 18887 | OPC_Decode, 196, 31, 230, 2, // 1311: decode to t2ADCrr using decoder 358 |
| 18888 | // 1311: } else try { |
| 18889 | OPC_CheckPredicate, 9, // 1316: check predicate 9 |
| 18890 | OPC_Decode, 197, 31, 231, 2, // 1318: decode to t2ADCrs using decoder 359 |
| 18891 | // 1318: } |
| 18892 | // 1318: } |
| 18893 | 1, 0, // 1323: case 0x1: { |
| 18894 | OPC_Scope, 15, // 1325: try { |
| 18895 | OPC_CheckField, 4, 4, 0, // 1327: check Inst[7:4] == 0x0 |
| 18896 | OPC_CheckPredicate, 9, // 1331: check predicate 9 |
| 18897 | OPC_CheckField, 12, 3, 0, // 1333: check Inst[14:12] == 0x0 |
| 18898 | OPC_Decode, 157, 33, 230, 2, // 1337: decode to t2RSBrr using decoder 358 |
| 18899 | // 1337: } else try { |
| 18900 | OPC_CheckPredicate, 9, // 1342: check predicate 9 |
| 18901 | OPC_Decode, 158, 33, 231, 2, // 1344: decode to t2RSBrs using decoder 359 |
| 18902 | // 1344: } |
| 18903 | // 1344: } |
| 18904 | // 1344: } // switch Inst[23] |
| 18905 | // 1344: } |
| 18906 | // 1344: } // switch Inst[26:24] |
| 18907 | // 1344: } |
| 18908 | 3, 0, // 1349: case 0x3: { |
| 18909 | OPC_SwitchField, 24, 3, // 1351: switch Inst[26:24] { |
| 18910 | 0, 21, // 1354: case 0x0: { |
| 18911 | OPC_SwitchField, 20, 1, // 1356: switch Inst[20] { |
| 18912 | 0, 7, // 1359: case 0x0: { |
| 18913 | OPC_CheckPredicate, 9, // 1361: check predicate 9 |
| 18914 | OPC_Decode, 128, 34, 252, 2, // 1363: decode to t2STRD_POST using decoder 380 |
| 18915 | // 1363: } |
| 18916 | 1, 0, // 1368: case 0x1: { |
| 18917 | OPC_CheckPredicate, 9, // 1370: check predicate 9 |
| 18918 | OPC_Decode, 174, 32, 253, 2, // 1372: decode to t2LDRD_POST using decoder 381 |
| 18919 | // 1372: } |
| 18920 | // 1372: } // switch Inst[20] |
| 18921 | // 1372: } |
| 18922 | 1, 40, // 1377: case 0x1: { |
| 18923 | OPC_SwitchField, 20, 1, // 1379: switch Inst[20] { |
| 18924 | 0, 7, // 1382: case 0x0: { |
| 18925 | OPC_CheckPredicate, 9, // 1384: check predicate 9 |
| 18926 | OPC_Decode, 129, 34, 254, 2, // 1386: decode to t2STRD_PRE using decoder 382 |
| 18927 | // 1386: } |
| 18928 | 1, 0, // 1391: case 0x1: { |
| 18929 | OPC_Scope, 17, // 1393: try { |
| 18930 | OPC_CheckField, 0, 20, 255, 210, 63, // 1395: check Inst[19:0] == 0xfe97f |
| 18931 | OPC_CheckPredicate, 51, // 1401: check predicate 51 |
| 18932 | OPC_CheckField, 23, 1, 0, // 1403: check Inst[23] == 0x0 |
| 18933 | OPC_Decode, 170, 33, 255, 2, // 1407: decode to t2SG using decoder 383 |
| 18934 | // 1407: } else try { |
| 18935 | OPC_CheckPredicate, 9, // 1412: check predicate 9 |
| 18936 | OPC_Decode, 175, 32, 128, 3, // 1414: decode to t2LDRD_PRE using decoder 384 |
| 18937 | // 1414: } |
| 18938 | // 1414: } |
| 18939 | // 1414: } // switch Inst[20] |
| 18940 | // 1414: } |
| 18941 | 2, 64, // 1419: case 0x2: { |
| 18942 | OPC_CheckField, 23, 1, 0, // 1421: check Inst[23] == 0x0 |
| 18943 | OPC_Scope, 33, // 1425: try { |
| 18944 | OPC_CheckField, 4, 4, 0, // 1427: check Inst[7:4] == 0x0 |
| 18945 | OPC_CheckField, 12, 3, 0, // 1431: check Inst[14:12] == 0x0 |
| 18946 | OPC_Scope, 11, // 1435: try { |
| 18947 | OPC_CheckField, 16, 4, 15, // 1437: check Inst[19:16] == 0xf |
| 18948 | OPC_CheckPredicate, 9, // 1441: check predicate 9 |
| 18949 | OPC_Decode, 239, 32, 248, 2, // 1443: decode to t2MVNr using decoder 376 |
| 18950 | // 1443: } else try { |
| 18951 | OPC_CheckPredicate, 9, // 1448: check predicate 9 |
| 18952 | OPC_SoftFail, 128, 128, 2, 0, // 1450: softfail pos=0x00008000 neg=0x00000000 |
| 18953 | OPC_Decode, 242, 32, 230, 2, // 1455: decode to t2ORNrr using decoder 358 |
| 18954 | // 1455: } |
| 18955 | OPC_Scope, 11, // 1460: } else try { |
| 18956 | OPC_CheckField, 16, 4, 15, // 1462: check Inst[19:16] == 0xf |
| 18957 | OPC_CheckPredicate, 9, // 1466: check predicate 9 |
| 18958 | OPC_Decode, 240, 32, 129, 3, // 1468: decode to t2MVNs using decoder 385 |
| 18959 | // 1468: } else try { |
| 18960 | OPC_CheckPredicate, 9, // 1473: check predicate 9 |
| 18961 | OPC_SoftFail, 128, 128, 2, 0, // 1475: softfail pos=0x00008000 neg=0x00000000 |
| 18962 | OPC_Decode, 243, 32, 231, 2, // 1480: decode to t2ORNrs using decoder 359 |
| 18963 | // 1480: } |
| 18964 | // 1480: } |
| 18965 | 3, 0, // 1485: case 0x3: { |
| 18966 | OPC_CheckField, 23, 1, 0, // 1487: check Inst[23] == 0x0 |
| 18967 | OPC_Scope, 15, // 1491: try { |
| 18968 | OPC_CheckField, 4, 4, 0, // 1493: check Inst[7:4] == 0x0 |
| 18969 | OPC_CheckPredicate, 9, // 1497: check predicate 9 |
| 18970 | OPC_CheckField, 12, 3, 0, // 1499: check Inst[14:12] == 0x0 |
| 18971 | OPC_Decode, 164, 33, 230, 2, // 1503: decode to t2SBCrr using decoder 358 |
| 18972 | // 1503: } else try { |
| 18973 | OPC_CheckPredicate, 9, // 1508: check predicate 9 |
| 18974 | OPC_Decode, 165, 33, 231, 2, // 1510: decode to t2SBCrs using decoder 359 |
| 18975 | // 1510: } |
| 18976 | // 1510: } |
| 18977 | // 1510: } // switch Inst[26:24] |
| 18978 | // 1510: } |
| 18979 | // 1510: } // switch Inst[22:21] |
| 18980 | // 1510: } |
| 18981 | 30, 220, 10, // 1515: case 0x1e: { |
| 18982 | OPC_SwitchField, 15, 1, // 1518: switch Inst[15] { |
| 18983 | 0, 247, 3, // 1521: case 0x0: { |
| 18984 | OPC_SwitchField, 24, 2, // 1524: switch Inst[25:24] { |
| 18985 | 0, 108, // 1527: case 0x0: { |
| 18986 | OPC_SwitchField, 21, 3, // 1529: switch Inst[23:21] { |
| 18987 | 0, 24, // 1532: case 0x0: { |
| 18988 | OPC_Scope, 15, // 1534: try { |
| 18989 | OPC_CheckField, 8, 4, 15, // 1536: check Inst[11:8] == 0xf |
| 18990 | OPC_CheckPredicate, 9, // 1540: check predicate 9 |
| 18991 | OPC_CheckField, 20, 1, 1, // 1542: check Inst[20] == 0x1 |
| 18992 | OPC_Decode, 166, 34, 130, 3, // 1546: decode to t2TSTri using decoder 386 |
| 18993 | // 1546: } else try { |
| 18994 | OPC_CheckPredicate, 9, // 1551: check predicate 9 |
| 18995 | OPC_Decode, 205, 31, 131, 3, // 1553: decode to t2ANDri using decoder 387 |
| 18996 | // 1553: } |
| 18997 | // 1553: } |
| 18998 | 1, 7, // 1558: case 0x1: { |
| 18999 | OPC_CheckPredicate, 9, // 1560: check predicate 9 |
| 19000 | OPC_Decode, 221, 31, 131, 3, // 1562: decode to t2BICri using decoder 387 |
| 19001 | // 1562: } |
| 19002 | 2, 20, // 1567: case 0x2: { |
| 19003 | OPC_Scope, 11, // 1569: try { |
| 19004 | OPC_CheckField, 16, 4, 15, // 1571: check Inst[19:16] == 0xf |
| 19005 | OPC_CheckPredicate, 9, // 1575: check predicate 9 |
| 19006 | OPC_Decode, 223, 32, 132, 3, // 1577: decode to t2MOVi using decoder 388 |
| 19007 | // 1577: } else try { |
| 19008 | OPC_CheckPredicate, 9, // 1582: check predicate 9 |
| 19009 | OPC_Decode, 244, 32, 131, 3, // 1584: decode to t2ORRri using decoder 387 |
| 19010 | // 1584: } |
| 19011 | // 1584: } |
| 19012 | 3, 20, // 1589: case 0x3: { |
| 19013 | OPC_Scope, 11, // 1591: try { |
| 19014 | OPC_CheckField, 16, 4, 15, // 1593: check Inst[19:16] == 0xf |
| 19015 | OPC_CheckPredicate, 9, // 1597: check predicate 9 |
| 19016 | OPC_Decode, 238, 32, 132, 3, // 1599: decode to t2MVNi using decoder 388 |
| 19017 | // 1599: } else try { |
| 19018 | OPC_CheckPredicate, 9, // 1604: check predicate 9 |
| 19019 | OPC_Decode, 241, 32, 131, 3, // 1606: decode to t2ORNri using decoder 387 |
| 19020 | // 1606: } |
| 19021 | // 1606: } |
| 19022 | 4, 0, // 1611: case 0x4: { |
| 19023 | OPC_Scope, 15, // 1613: try { |
| 19024 | OPC_CheckField, 8, 4, 15, // 1615: check Inst[11:8] == 0xf |
| 19025 | OPC_CheckPredicate, 9, // 1619: check predicate 9 |
| 19026 | OPC_CheckField, 20, 1, 1, // 1621: check Inst[20] == 0x1 |
| 19027 | OPC_Decode, 162, 34, 130, 3, // 1625: decode to t2TEQri using decoder 386 |
| 19028 | // 1625: } else try { |
| 19029 | OPC_CheckPredicate, 9, // 1630: check predicate 9 |
| 19030 | OPC_Decode, 131, 32, 131, 3, // 1632: decode to t2EORri using decoder 387 |
| 19031 | // 1632: } |
| 19032 | // 1632: } |
| 19033 | // 1632: } // switch Inst[23:21] |
| 19034 | // 1632: } |
| 19035 | 1, 110, // 1637: case 0x1: { |
| 19036 | OPC_SwitchField, 21, 3, // 1639: switch Inst[23:21] { |
| 19037 | 0, 38, // 1642: case 0x0: { |
| 19038 | OPC_Scope, 29, // 1644: try { |
| 19039 | OPC_SwitchField, 8, 4, // 1646: switch Inst[11:8] { |
| 19040 | 13, 11, // 1649: case 0xd: { |
| 19041 | OPC_CheckPredicate, 9, // 1651: check predicate 9 |
| 19042 | OPC_CheckField, 16, 4, 13, // 1653: check Inst[19:16] == 0xd |
| 19043 | OPC_Decode, 202, 31, 133, 3, // 1657: decode to t2ADDspImm using decoder 389 |
| 19044 | // 1657: } |
| 19045 | 15, 0, // 1662: case 0xf: { |
| 19046 | OPC_CheckPredicate, 9, // 1664: check predicate 9 |
| 19047 | OPC_CheckField, 20, 1, 1, // 1666: check Inst[20] == 0x1 |
| 19048 | OPC_Decode, 233, 31, 134, 3, // 1670: decode to t2CMNri using decoder 390 |
| 19049 | // 1670: } |
| 19050 | // 1670: } // switch Inst[11:8] |
| 19051 | // 1670: } else try { |
| 19052 | OPC_CheckPredicate, 9, // 1675: check predicate 9 |
| 19053 | OPC_Decode, 198, 31, 135, 3, // 1677: decode to t2ADDri using decoder 391 |
| 19054 | // 1677: } |
| 19055 | // 1677: } |
| 19056 | 2, 7, // 1682: case 0x2: { |
| 19057 | OPC_CheckPredicate, 9, // 1684: check predicate 9 |
| 19058 | OPC_Decode, 195, 31, 131, 3, // 1686: decode to t2ADCri using decoder 387 |
| 19059 | // 1686: } |
| 19060 | 3, 7, // 1691: case 0x3: { |
| 19061 | OPC_CheckPredicate, 9, // 1693: check predicate 9 |
| 19062 | OPC_Decode, 163, 33, 131, 3, // 1695: decode to t2SBCri using decoder 387 |
| 19063 | // 1695: } |
| 19064 | 5, 38, // 1700: case 0x5: { |
| 19065 | OPC_Scope, 29, // 1702: try { |
| 19066 | OPC_SwitchField, 8, 4, // 1704: switch Inst[11:8] { |
| 19067 | 13, 11, // 1707: case 0xd: { |
| 19068 | OPC_CheckPredicate, 9, // 1709: check predicate 9 |
| 19069 | OPC_CheckField, 16, 4, 13, // 1711: check Inst[19:16] == 0xd |
| 19070 | OPC_Decode, 152, 34, 133, 3, // 1715: decode to t2SUBspImm using decoder 389 |
| 19071 | // 1715: } |
| 19072 | 15, 0, // 1720: case 0xf: { |
| 19073 | OPC_CheckPredicate, 9, // 1722: check predicate 9 |
| 19074 | OPC_CheckField, 20, 1, 1, // 1724: check Inst[20] == 0x1 |
| 19075 | OPC_Decode, 236, 31, 134, 3, // 1728: decode to t2CMPri using decoder 390 |
| 19076 | // 1728: } |
| 19077 | // 1728: } // switch Inst[11:8] |
| 19078 | // 1728: } else try { |
| 19079 | OPC_CheckPredicate, 9, // 1733: check predicate 9 |
| 19080 | OPC_Decode, 148, 34, 135, 3, // 1735: decode to t2SUBri using decoder 391 |
| 19081 | // 1735: } |
| 19082 | // 1735: } |
| 19083 | 6, 0, // 1740: case 0x6: { |
| 19084 | OPC_CheckPredicate, 9, // 1742: check predicate 9 |
| 19085 | OPC_Decode, 156, 33, 131, 3, // 1744: decode to t2RSBri using decoder 387 |
| 19086 | // 1744: } |
| 19087 | // 1744: } // switch Inst[23:21] |
| 19088 | // 1744: } |
| 19089 | 2, 122, // 1749: case 0x2: { |
| 19090 | OPC_SwitchField, 22, 1, // 1751: switch Inst[22] { |
| 19091 | 0, 86, // 1754: case 0x0: { |
| 19092 | OPC_CheckField, 20, 1, 0, // 1756: check Inst[20] == 0x0 |
| 19093 | OPC_Scope, 51, // 1760: try { |
| 19094 | OPC_SwitchField, 16, 4, // 1762: switch Inst[19:16] { |
| 19095 | 13, 37, // 1765: case 0xd: { |
| 19096 | OPC_SwitchField, 21, 1, // 1767: switch Inst[21] { |
| 19097 | 0, 15, // 1770: case 0x0: { |
| 19098 | OPC_CheckPredicate, 9, // 1772: check predicate 9 |
| 19099 | OPC_CheckField, 23, 1, 0, // 1774: check Inst[23] == 0x0 |
| 19100 | OPC_CheckField, 8, 4, 13, // 1778: check Inst[11:8] == 0xd |
| 19101 | OPC_Decode, 203, 31, 133, 3, // 1782: decode to t2ADDspImm12 using decoder 389 |
| 19102 | // 1782: } |
| 19103 | 1, 0, // 1787: case 0x1: { |
| 19104 | OPC_CheckPredicate, 9, // 1789: check predicate 9 |
| 19105 | OPC_CheckField, 23, 1, 1, // 1791: check Inst[23] == 0x1 |
| 19106 | OPC_CheckField, 8, 4, 13, // 1795: check Inst[11:8] == 0xd |
| 19107 | OPC_Decode, 153, 34, 133, 3, // 1799: decode to t2SUBspImm12 using decoder 389 |
| 19108 | // 1799: } |
| 19109 | // 1799: } // switch Inst[21] |
| 19110 | // 1799: } |
| 19111 | 15, 0, // 1804: case 0xf: { |
| 19112 | OPC_CheckPredicate, 9, // 1806: check predicate 9 |
| 19113 | OPC_Decode, 204, 31, 136, 3, // 1808: decode to t2ADR using decoder 392 |
| 19114 | // 1808: } |
| 19115 | // 1808: } // switch Inst[19:16] |
| 19116 | // 1808: } else try { |
| 19117 | OPC_SwitchField, 21, 1, // 1813: switch Inst[21] { |
| 19118 | 0, 11, // 1816: case 0x0: { |
| 19119 | OPC_CheckPredicate, 9, // 1818: check predicate 9 |
| 19120 | OPC_CheckField, 23, 1, 0, // 1820: check Inst[23] == 0x0 |
| 19121 | OPC_Decode, 199, 31, 137, 3, // 1824: decode to t2ADDri12 using decoder 393 |
| 19122 | // 1824: } |
| 19123 | 1, 0, // 1829: case 0x1: { |
| 19124 | OPC_CheckPredicate, 9, // 1831: check predicate 9 |
| 19125 | OPC_CheckField, 23, 1, 1, // 1833: check Inst[23] == 0x1 |
| 19126 | OPC_Decode, 149, 34, 137, 3, // 1837: decode to t2SUBri12 using decoder 393 |
| 19127 | // 1837: } |
| 19128 | // 1837: } // switch Inst[21] |
| 19129 | // 1837: } |
| 19130 | // 1837: } |
| 19131 | 1, 0, // 1842: case 0x1: { |
| 19132 | OPC_SwitchField, 23, 1, // 1844: switch Inst[23] { |
| 19133 | 0, 11, // 1847: case 0x0: { |
| 19134 | OPC_CheckPredicate, 4, // 1849: check predicate 4 |
| 19135 | OPC_CheckField, 20, 2, 0, // 1851: check Inst[21:20] == 0x0 |
| 19136 | OPC_Decode, 224, 32, 138, 3, // 1855: decode to t2MOVi16 using decoder 394 |
| 19137 | // 1855: } |
| 19138 | 1, 0, // 1860: case 0x1: { |
| 19139 | OPC_CheckPredicate, 4, // 1862: check predicate 4 |
| 19140 | OPC_CheckField, 20, 2, 0, // 1864: check Inst[21:20] == 0x0 |
| 19141 | OPC_Decode, 222, 32, 138, 3, // 1868: decode to t2MOVTi16 using decoder 394 |
| 19142 | // 1868: } |
| 19143 | // 1868: } // switch Inst[23] |
| 19144 | // 1868: } |
| 19145 | // 1868: } // switch Inst[22] |
| 19146 | // 1868: } |
| 19147 | 3, 0, // 1873: case 0x3: { |
| 19148 | OPC_SwitchField, 22, 2, // 1875: switch Inst[23:22] { |
| 19149 | 0, 44, // 1878: case 0x0: { |
| 19150 | OPC_CheckField, 5, 1, 0, // 1880: check Inst[5] == 0x0 |
| 19151 | OPC_CheckField, 20, 1, 0, // 1884: check Inst[20] == 0x0 |
| 19152 | OPC_CheckField, 26, 1, 0, // 1888: check Inst[26] == 0x0 |
| 19153 | OPC_Scope, 23, // 1892: try { |
| 19154 | OPC_CheckField, 4, 1, 0, // 1894: check Inst[4] == 0x0 |
| 19155 | OPC_CheckPredicate, 52, // 1898: check predicate 52 |
| 19156 | OPC_CheckField, 21, 1, 1, // 1900: check Inst[21] == 0x1 |
| 19157 | OPC_CheckField, 12, 3, 0, // 1904: check Inst[14:12] == 0x0 |
| 19158 | OPC_CheckField, 6, 2, 0, // 1908: check Inst[7:6] == 0x0 |
| 19159 | OPC_Decode, 219, 33, 139, 3, // 1912: decode to t2SSAT16 using decoder 395 |
| 19160 | // 1912: } else try { |
| 19161 | OPC_CheckPredicate, 9, // 1917: check predicate 9 |
| 19162 | OPC_Decode, 218, 33, 140, 3, // 1919: decode to t2SSAT using decoder 396 |
| 19163 | // 1919: } |
| 19164 | // 1919: } |
| 19165 | 1, 42, // 1924: case 0x1: { |
| 19166 | OPC_SwitchField, 20, 2, // 1926: switch Inst[21:20] { |
| 19167 | 0, 7, // 1929: case 0x0: { |
| 19168 | OPC_CheckPredicate, 9, // 1931: check predicate 9 |
| 19169 | OPC_Decode, 166, 33, 141, 3, // 1933: decode to t2SBFX using decoder 397 |
| 19170 | // 1933: } |
| 19171 | 2, 0, // 1938: case 0x2: { |
| 19172 | OPC_CheckField, 5, 1, 0, // 1940: check Inst[5] == 0x0 |
| 19173 | OPC_CheckField, 26, 1, 0, // 1944: check Inst[26] == 0x0 |
| 19174 | OPC_Scope, 11, // 1948: try { |
| 19175 | OPC_CheckField, 16, 4, 15, // 1950: check Inst[19:16] == 0xf |
| 19176 | OPC_CheckPredicate, 9, // 1954: check predicate 9 |
| 19177 | OPC_Decode, 214, 31, 142, 3, // 1956: decode to t2BFC using decoder 398 |
| 19178 | // 1956: } else try { |
| 19179 | OPC_CheckPredicate, 9, // 1961: check predicate 9 |
| 19180 | OPC_Decode, 215, 31, 143, 3, // 1963: decode to t2BFI using decoder 399 |
| 19181 | // 1963: } |
| 19182 | // 1963: } |
| 19183 | // 1963: } // switch Inst[21:20] |
| 19184 | // 1963: } |
| 19185 | 2, 44, // 1968: case 0x2: { |
| 19186 | OPC_CheckField, 5, 1, 0, // 1970: check Inst[5] == 0x0 |
| 19187 | OPC_CheckField, 20, 1, 0, // 1974: check Inst[20] == 0x0 |
| 19188 | OPC_CheckField, 26, 1, 0, // 1978: check Inst[26] == 0x0 |
| 19189 | OPC_Scope, 23, // 1982: try { |
| 19190 | OPC_CheckField, 4, 1, 0, // 1984: check Inst[4] == 0x0 |
| 19191 | OPC_CheckPredicate, 52, // 1988: check predicate 52 |
| 19192 | OPC_CheckField, 21, 1, 1, // 1990: check Inst[21] == 0x1 |
| 19193 | OPC_CheckField, 12, 3, 0, // 1994: check Inst[14:12] == 0x0 |
| 19194 | OPC_CheckField, 6, 2, 0, // 1998: check Inst[7:6] == 0x0 |
| 19195 | OPC_Decode, 197, 34, 139, 3, // 2002: decode to t2USAT16 using decoder 395 |
| 19196 | // 2002: } else try { |
| 19197 | OPC_CheckPredicate, 9, // 2007: check predicate 9 |
| 19198 | OPC_Decode, 196, 34, 140, 3, // 2009: decode to t2USAT using decoder 396 |
| 19199 | // 2009: } |
| 19200 | // 2009: } |
| 19201 | 3, 0, // 2014: case 0x3: { |
| 19202 | OPC_CheckPredicate, 9, // 2016: check predicate 9 |
| 19203 | OPC_CheckField, 20, 2, 0, // 2018: check Inst[21:20] == 0x0 |
| 19204 | OPC_Decode, 176, 34, 141, 3, // 2022: decode to t2UBFX using decoder 397 |
| 19205 | // 2022: } |
| 19206 | // 2022: } // switch Inst[23:22] |
| 19207 | // 2022: } |
| 19208 | // 2022: } // switch Inst[25:24] |
| 19209 | // 2022: } |
| 19210 | 1, 0, // 2027: case 0x1: { |
| 19211 | OPC_SwitchField, 12, 1, // 2029: switch Inst[12] { |
| 19212 | 0, 202, 6, // 2032: case 0x0: { |
| 19213 | OPC_SwitchField, 14, 1, // 2035: switch Inst[14] { |
| 19214 | 0, 164, 4, // 2038: case 0x0: { |
| 19215 | OPC_Scope, 111, // 2041: try { |
| 19216 | OPC_SwitchField, 0, 12, // 2043: switch Inst[11:0] { |
| 19217 | 1, 16, // 2046: case 0x1: { |
| 19218 | OPC_CheckPredicate, 53, // 2048: check predicate 53 |
| 19219 | OPC_CheckField, 16, 11, 143, 15, // 2050: check Inst[26:16] == 0x78f |
| 19220 | OPC_CheckField, 13, 1, 0, // 2055: check Inst[13] == 0x0 |
| 19221 | OPC_Decode, 253, 31, 255, 2, // 2059: decode to t2DCPS1 using decoder 383 |
| 19222 | // 2059: } |
| 19223 | 2, 16, // 2064: case 0x2: { |
| 19224 | OPC_CheckPredicate, 53, // 2066: check predicate 53 |
| 19225 | OPC_CheckField, 16, 11, 143, 15, // 2068: check Inst[26:16] == 0x78f |
| 19226 | OPC_CheckField, 13, 1, 0, // 2073: check Inst[13] == 0x0 |
| 19227 | OPC_Decode, 254, 31, 255, 2, // 2077: decode to t2DCPS2 using decoder 383 |
| 19228 | // 2077: } |
| 19229 | 3, 16, // 2082: case 0x3: { |
| 19230 | OPC_CheckPredicate, 53, // 2084: check predicate 53 |
| 19231 | OPC_CheckField, 16, 11, 143, 15, // 2086: check Inst[26:16] == 0x78f |
| 19232 | OPC_CheckField, 13, 1, 0, // 2091: check Inst[13] == 0x0 |
| 19233 | OPC_Decode, 255, 31, 255, 2, // 2095: decode to t2DCPS3 using decoder 383 |
| 19234 | // 2095: } |
| 19235 | 18, 15, // 2100: case 0x12: { |
| 19236 | OPC_CheckPredicate, 54, // 2102: check predicate 54 |
| 19237 | OPC_CheckField, 16, 11, 175, 7, // 2104: check Inst[26:16] == 0x3af |
| 19238 | OPC_CheckField, 13, 1, 0, // 2109: check Inst[13] == 0x0 |
| 19239 | OPC_Decode, 165, 34, 89, // 2113: decode to t2TSB using decoder 89 |
| 19240 | // 2113: } |
| 19241 | 128, 30, 15, // 2117: case 0xf00: { |
| 19242 | OPC_CheckPredicate, 45, // 2120: check predicate 45 |
| 19243 | OPC_CheckField, 20, 7, 60, // 2122: check Inst[26:20] == 0x3c |
| 19244 | OPC_CheckField, 13, 1, 0, // 2126: check Inst[13] == 0x0 |
| 19245 | OPC_Decode, 226, 31, 144, 3, // 2130: decode to t2BXJ using decoder 400 |
| 19246 | // 2130: } |
| 19247 | 175, 30, 0, // 2135: case 0xf2f: { |
| 19248 | OPC_CheckPredicate, 55, // 2138: check predicate 55 |
| 19249 | OPC_CheckField, 16, 11, 191, 7, // 2140: check Inst[26:16] == 0x3bf |
| 19250 | OPC_CheckField, 13, 1, 0, // 2145: check Inst[13] == 0x0 |
| 19251 | OPC_Decode, 230, 31, 255, 2, // 2149: decode to t2CLREX using decoder 383 |
| 19252 | // 2149: } |
| 19253 | // 2149: } // switch Inst[11:0] |
| 19254 | OPC_Scope, 191, 1, // 2154: } else try { |
| 19255 | OPC_SwitchField, 16, 11, // 2157: switch Inst[26:16] { |
| 19256 | 175, 7, 84, // 2160: case 0x3af: { |
| 19257 | OPC_SwitchField, 8, 1, // 2163: switch Inst[8] { |
| 19258 | 0, 45, // 2166: case 0x0: { |
| 19259 | OPC_CheckField, 11, 1, 0, // 2168: check Inst[11] == 0x0 |
| 19260 | OPC_CheckField, 13, 1, 0, // 2172: check Inst[13] == 0x0 |
| 19261 | OPC_Scope, 24, // 2176: try { |
| 19262 | OPC_CheckField, 9, 2, 0, // 2178: check Inst[10:9] == 0x0 |
| 19263 | OPC_Scope, 11, // 2182: try { |
| 19264 | OPC_CheckField, 4, 4, 15, // 2184: check Inst[7:4] == 0xf |
| 19265 | OPC_CheckPredicate, 9, // 2188: check predicate 9 |
| 19266 | OPC_Decode, 252, 31, 145, 3, // 2190: decode to t2DBG using decoder 401 |
| 19267 | // 2190: } else try { |
| 19268 | OPC_CheckPredicate, 9, // 2195: check predicate 9 |
| 19269 | OPC_Decode, 134, 32, 146, 3, // 2197: decode to t2HINT using decoder 402 |
| 19270 | // 2197: } |
| 19271 | // 2197: } else try { |
| 19272 | OPC_CheckPredicate, 45, // 2202: check predicate 45 |
| 19273 | OPC_CheckField, 0, 5, 0, // 2204: check Inst[4:0] == 0x0 |
| 19274 | OPC_Decode, 240, 31, 147, 3, // 2208: decode to t2CPS2p using decoder 403 |
| 19275 | // 2208: } |
| 19276 | // 2208: } |
| 19277 | 1, 0, // 2213: case 0x1: { |
| 19278 | OPC_CheckField, 11, 1, 0, // 2215: check Inst[11] == 0x0 |
| 19279 | OPC_CheckField, 13, 1, 0, // 2219: check Inst[13] == 0x0 |
| 19280 | OPC_Scope, 15, // 2223: try { |
| 19281 | OPC_CheckField, 5, 3, 0, // 2225: check Inst[7:5] == 0x0 |
| 19282 | OPC_CheckPredicate, 45, // 2229: check predicate 45 |
| 19283 | OPC_CheckField, 9, 2, 0, // 2231: check Inst[10:9] == 0x0 |
| 19284 | OPC_Decode, 239, 31, 147, 3, // 2235: decode to t2CPS1p using decoder 403 |
| 19285 | // 2235: } else try { |
| 19286 | OPC_CheckPredicate, 45, // 2240: check predicate 45 |
| 19287 | OPC_Decode, 241, 31, 147, 3, // 2242: decode to t2CPS3p using decoder 403 |
| 19288 | // 2242: } |
| 19289 | // 2242: } |
| 19290 | // 2242: } // switch Inst[8] |
| 19291 | // 2242: } |
| 19292 | 191, 7, 45, // 2247: case 0x3bf: { |
| 19293 | OPC_SwitchField, 4, 8, // 2250: switch Inst[11:4] { |
| 19294 | 244, 1, 11, // 2253: case 0xf4: { |
| 19295 | OPC_CheckPredicate, 56, // 2256: check predicate 56 |
| 19296 | OPC_CheckField, 13, 1, 0, // 2258: check Inst[13] == 0x0 |
| 19297 | OPC_Decode, 130, 32, 148, 3, // 2262: decode to t2DSB using decoder 404 |
| 19298 | // 2262: } |
| 19299 | 245, 1, 11, // 2267: case 0xf5: { |
| 19300 | OPC_CheckPredicate, 56, // 2270: check predicate 56 |
| 19301 | OPC_CheckField, 13, 1, 0, // 2272: check Inst[13] == 0x0 |
| 19302 | OPC_Decode, 129, 32, 148, 3, // 2276: decode to t2DMB using decoder 404 |
| 19303 | // 2276: } |
| 19304 | 246, 1, 0, // 2281: case 0xf6: { |
| 19305 | OPC_CheckPredicate, 56, // 2284: check predicate 56 |
| 19306 | OPC_CheckField, 13, 1, 0, // 2286: check Inst[13] == 0x0 |
| 19307 | OPC_Decode, 136, 32, 149, 3, // 2290: decode to t2ISB using decoder 405 |
| 19308 | // 2290: } |
| 19309 | // 2290: } // switch Inst[11:4] |
| 19310 | // 2290: } |
| 19311 | 222, 7, 14, // 2295: case 0x3de: { |
| 19312 | OPC_CheckPredicate, 45, // 2298: check predicate 45 |
| 19313 | OPC_CheckField, 13, 1, 0, // 2300: check Inst[13] == 0x0 |
| 19314 | OPC_CheckField, 8, 4, 15, // 2304: check Inst[11:8] == 0xf |
| 19315 | OPC_Decode, 147, 34, 26, // 2308: decode to t2SUBS_PC_LR using decoder 26 |
| 19316 | // 2308: } |
| 19317 | 239, 7, 15, // 2312: case 0x3ef: { |
| 19318 | OPC_CheckPredicate, 45, // 2315: check predicate 45 |
| 19319 | OPC_CheckField, 13, 1, 0, // 2317: check Inst[13] == 0x0 |
| 19320 | OPC_CheckField, 0, 8, 0, // 2321: check Inst[7:0] == 0x0 |
| 19321 | OPC_Decode, 230, 32, 150, 3, // 2325: decode to t2MRS_AR using decoder 406 |
| 19322 | // 2325: } |
| 19323 | 255, 7, 0, // 2330: case 0x3ff: { |
| 19324 | OPC_CheckPredicate, 45, // 2333: check predicate 45 |
| 19325 | OPC_CheckField, 13, 1, 0, // 2335: check Inst[13] == 0x0 |
| 19326 | OPC_CheckField, 0, 8, 0, // 2339: check Inst[7:0] == 0x0 |
| 19327 | OPC_Decode, 233, 32, 150, 3, // 2343: decode to t2MRSsys_AR using decoder 406 |
| 19328 | // 2343: } |
| 19329 | // 2343: } // switch Inst[26:16] |
| 19330 | OPC_Scope, 79, // 2348: } else try { |
| 19331 | OPC_SwitchField, 0, 11, // 2350: switch Inst[10:0] { |
| 19332 | 13, 17, // 2353: case 0xd: { |
| 19333 | OPC_CheckPredicate, 57, // 2355: check predicate 57 |
| 19334 | OPC_CheckField, 20, 7, 58, // 2357: check Inst[26:20] == 0x3a |
| 19335 | OPC_SoftFail, 128, 80, 128, 128, 60, // 2361: softfail pos=0x00002800 neg=0x000f0000 |
| 19336 | OPC_Decode, 248, 32, 146, 3, // 2367: decode to t2PACBTI using decoder 402 |
| 19337 | // 2367: } |
| 19338 | 15, 17, // 2372: case 0xf: { |
| 19339 | OPC_CheckPredicate, 57, // 2374: check predicate 57 |
| 19340 | OPC_CheckField, 20, 7, 58, // 2376: check Inst[26:20] == 0x3a |
| 19341 | OPC_SoftFail, 128, 80, 128, 128, 60, // 2380: softfail pos=0x00002800 neg=0x000f0000 |
| 19342 | OPC_Decode, 224, 31, 146, 3, // 2386: decode to t2BTI using decoder 402 |
| 19343 | // 2386: } |
| 19344 | 29, 17, // 2391: case 0x1d: { |
| 19345 | OPC_CheckPredicate, 57, // 2393: check predicate 57 |
| 19346 | OPC_CheckField, 20, 7, 58, // 2395: check Inst[26:20] == 0x3a |
| 19347 | OPC_SoftFail, 128, 80, 128, 128, 60, // 2399: softfail pos=0x00002800 neg=0x000f0000 |
| 19348 | OPC_Decode, 247, 32, 146, 3, // 2405: decode to t2PAC using decoder 402 |
| 19349 | // 2405: } |
| 19350 | 45, 0, // 2410: case 0x2d: { |
| 19351 | OPC_CheckPredicate, 57, // 2412: check predicate 57 |
| 19352 | OPC_CheckField, 20, 7, 58, // 2414: check Inst[26:20] == 0x3a |
| 19353 | OPC_SoftFail, 128, 80, 128, 128, 60, // 2418: softfail pos=0x00002800 neg=0x000f0000 |
| 19354 | OPC_Decode, 211, 31, 146, 3, // 2424: decode to t2AUT using decoder 402 |
| 19355 | // 2424: } |
| 19356 | // 2424: } // switch Inst[10:0] |
| 19357 | OPC_Scope, 57, // 2429: } else try { |
| 19358 | OPC_SwitchField, 20, 7, // 2431: switch Inst[26:20] { |
| 19359 | 59, 16, // 2434: case 0x3b: { |
| 19360 | OPC_CheckPredicate, 58, // 2436: check predicate 58 |
| 19361 | OPC_CheckField, 4, 4, 7, // 2438: check Inst[7:4] == 0x7 |
| 19362 | OPC_SoftFail, 143, 64, 128, 158, 60, // 2442: softfail pos=0x0000200f neg=0x000f0f00 |
| 19363 | OPC_Decode, 162, 33, 25, // 2448: decode to t2SB using decoder 25 |
| 19364 | // 2448: } |
| 19365 | 126, 11, // 2452: case 0x7e: { |
| 19366 | OPC_CheckPredicate, 59, // 2454: check predicate 59 |
| 19367 | OPC_CheckField, 13, 1, 0, // 2456: check Inst[13] == 0x0 |
| 19368 | OPC_Decode, 135, 32, 151, 3, // 2460: decode to t2HVC using decoder 407 |
| 19369 | // 2460: } |
| 19370 | 127, 0, // 2465: case 0x7f: { |
| 19371 | OPC_SwitchField, 13, 1, // 2467: switch Inst[13] { |
| 19372 | 0, 7, // 2470: case 0x0: { |
| 19373 | OPC_CheckPredicate, 60, // 2472: check predicate 60 |
| 19374 | OPC_Decode, 177, 33, 152, 3, // 2474: decode to t2SMC using decoder 408 |
| 19375 | // 2474: } |
| 19376 | 1, 0, // 2479: case 0x1: { |
| 19377 | OPC_CheckPredicate, 9, // 2481: check predicate 9 |
| 19378 | OPC_Decode, 177, 34, 151, 3, // 2483: decode to t2UDF using decoder 407 |
| 19379 | // 2483: } |
| 19380 | // 2483: } // switch Inst[13] |
| 19381 | // 2483: } |
| 19382 | // 2483: } // switch Inst[26:20] |
| 19383 | OPC_Scope, 92, // 2488: } else try { |
| 19384 | OPC_SwitchField, 21, 6, // 2490: switch Inst[26:21] { |
| 19385 | 28, 50, // 2493: case 0x1c: { |
| 19386 | OPC_Scope, 15, // 2495: try { |
| 19387 | OPC_CheckField, 0, 8, 0, // 2497: check Inst[7:0] == 0x0 |
| 19388 | OPC_CheckPredicate, 45, // 2501: check predicate 45 |
| 19389 | OPC_CheckField, 13, 1, 0, // 2503: check Inst[13] == 0x0 |
| 19390 | OPC_Decode, 234, 32, 153, 3, // 2507: decode to t2MSR_AR using decoder 409 |
| 19391 | OPC_Scope, 19, // 2512: } else try { |
| 19392 | OPC_CheckField, 0, 4, 0, // 2514: check Inst[3:0] == 0x0 |
| 19393 | OPC_CheckPredicate, 61, // 2518: check predicate 61 |
| 19394 | OPC_CheckField, 13, 1, 0, // 2520: check Inst[13] == 0x0 |
| 19395 | OPC_CheckField, 5, 3, 1, // 2524: check Inst[7:5] == 0x1 |
| 19396 | OPC_Decode, 236, 32, 154, 3, // 2528: decode to t2MSRbanked using decoder 410 |
| 19397 | // 2528: } else try { |
| 19398 | OPC_CheckPredicate, 62, // 2533: check predicate 62 |
| 19399 | OPC_SoftFail, 128, 198, 64, 0, // 2535: softfail pos=0x00102300 neg=0x00000000 |
| 19400 | OPC_Decode, 235, 32, 155, 3, // 2540: decode to t2MSR_M using decoder 411 |
| 19401 | // 2540: } |
| 19402 | // 2540: } |
| 19403 | 31, 0, // 2545: case 0x1f: { |
| 19404 | OPC_Scope, 19, // 2547: try { |
| 19405 | OPC_CheckField, 0, 4, 0, // 2549: check Inst[3:0] == 0x0 |
| 19406 | OPC_CheckPredicate, 61, // 2553: check predicate 61 |
| 19407 | OPC_CheckField, 13, 1, 0, // 2555: check Inst[13] == 0x0 |
| 19408 | OPC_CheckField, 5, 3, 1, // 2559: check Inst[7:5] == 0x1 |
| 19409 | OPC_Decode, 232, 32, 156, 3, // 2563: decode to t2MRSbanked using decoder 412 |
| 19410 | // 2563: } else try { |
| 19411 | OPC_CheckPredicate, 62, // 2568: check predicate 62 |
| 19412 | OPC_SoftFail, 128, 192, 64, 128, 128, 60, // 2570: softfail pos=0x00102000 neg=0x000f0000 |
| 19413 | OPC_Decode, 231, 32, 157, 3, // 2577: decode to t2MRS_M using decoder 413 |
| 19414 | // 2577: } |
| 19415 | // 2577: } |
| 19416 | // 2577: } // switch Inst[26:21] |
| 19417 | // 2577: } else try { |
| 19418 | OPC_CheckPredicate, 9, // 2582: check predicate 9 |
| 19419 | OPC_Decode, 227, 31, 158, 3, // 2584: decode to t2Bcc using decoder 414 |
| 19420 | // 2584: } |
| 19421 | // 2584: } |
| 19422 | 1, 0, // 2589: case 0x1: { |
| 19423 | OPC_SwitchField, 13, 1, // 2591: switch Inst[13] { |
| 19424 | 0, 93, // 2594: case 0x0: { |
| 19425 | OPC_CheckField, 0, 1, 1, // 2596: check Inst[0] == 0x1 |
| 19426 | OPC_Scope, 30, // 2600: try { |
| 19427 | OPC_SwitchField, 16, 11, // 2602: switch Inst[26:16] { |
| 19428 | 15, 7, // 2605: case 0xf: { |
| 19429 | OPC_CheckPredicate, 63, // 2607: check predicate 63 |
| 19430 | OPC_Decode, 210, 32, 159, 3, // 2609: decode to t2LEUpdate using decoder 415 |
| 19431 | // 2609: } |
| 19432 | 31, 7, // 2614: case 0x1f: { |
| 19433 | OPC_CheckPredicate, 31, // 2616: check predicate 31 |
| 19434 | OPC_Decode, 250, 7, 159, 3, // 2618: decode to MVE_LETP using decoder 415 |
| 19435 | // 2618: } |
| 19436 | 47, 0, // 2623: case 0x2f: { |
| 19437 | OPC_CheckPredicate, 63, // 2625: check predicate 63 |
| 19438 | OPC_Decode, 209, 32, 159, 3, // 2627: decode to t2LE using decoder 415 |
| 19439 | // 2627: } |
| 19440 | // 2627: } // switch Inst[26:16] |
| 19441 | OPC_Scope, 48, // 2632: } else try { |
| 19442 | OPC_SwitchField, 20, 7, // 2634: switch Inst[26:20] { |
| 19443 | 0, 7, // 2637: case 0x0: { |
| 19444 | OPC_CheckPredicate, 31, // 2639: check predicate 31 |
| 19445 | OPC_Decode, 187, 14, 159, 3, // 2641: decode to MVE_WLSTP_8 using decoder 415 |
| 19446 | // 2641: } |
| 19447 | 1, 7, // 2646: case 0x1: { |
| 19448 | OPC_CheckPredicate, 31, // 2648: check predicate 31 |
| 19449 | OPC_Decode, 184, 14, 159, 3, // 2650: decode to MVE_WLSTP_16 using decoder 415 |
| 19450 | // 2650: } |
| 19451 | 2, 7, // 2655: case 0x2: { |
| 19452 | OPC_CheckPredicate, 31, // 2657: check predicate 31 |
| 19453 | OPC_Decode, 185, 14, 159, 3, // 2659: decode to MVE_WLSTP_32 using decoder 415 |
| 19454 | // 2659: } |
| 19455 | 3, 7, // 2664: case 0x3: { |
| 19456 | OPC_CheckPredicate, 31, // 2666: check predicate 31 |
| 19457 | OPC_Decode, 186, 14, 159, 3, // 2668: decode to MVE_WLSTP_64 using decoder 415 |
| 19458 | // 2668: } |
| 19459 | 4, 0, // 2673: case 0x4: { |
| 19460 | OPC_CheckPredicate, 63, // 2675: check predicate 63 |
| 19461 | OPC_Decode, 207, 34, 159, 3, // 2677: decode to t2WLS using decoder 415 |
| 19462 | // 2677: } |
| 19463 | // 2677: } // switch Inst[26:20] |
| 19464 | // 2677: } else try { |
| 19465 | OPC_CheckPredicate, 63, // 2682: check predicate 63 |
| 19466 | OPC_Decode, 216, 31, 160, 3, // 2684: decode to t2BFLi using decoder 416 |
| 19467 | // 2684: } |
| 19468 | // 2684: } |
| 19469 | 1, 0, // 2689: case 0x1: { |
| 19470 | OPC_SwitchField, 22, 1, // 2691: switch Inst[22] { |
| 19471 | 0, 111, // 2694: case 0x0: { |
| 19472 | OPC_CheckField, 0, 1, 1, // 2696: check Inst[0] == 0x1 |
| 19473 | OPC_Scope, 75, // 2700: try { |
| 19474 | OPC_CheckField, 11, 1, 0, // 2702: check Inst[11] == 0x0 |
| 19475 | OPC_SwitchField, 20, 2, // 2706: switch Inst[21:20] { |
| 19476 | 0, 15, // 2709: case 0x0: { |
| 19477 | OPC_CheckPredicate, 31, // 2711: check predicate 31 |
| 19478 | OPC_CheckField, 23, 4, 0, // 2713: check Inst[26:23] == 0x0 |
| 19479 | OPC_SoftFail, 254, 15, 0, // 2717: softfail pos=0x000007fe neg=0x00000000 |
| 19480 | OPC_Decode, 248, 7, 159, 3, // 2721: decode to MVE_DLSTP_8 using decoder 415 |
| 19481 | // 2721: } |
| 19482 | 1, 15, // 2726: case 0x1: { |
| 19483 | OPC_CheckPredicate, 31, // 2728: check predicate 31 |
| 19484 | OPC_CheckField, 23, 4, 0, // 2730: check Inst[26:23] == 0x0 |
| 19485 | OPC_SoftFail, 254, 15, 0, // 2734: softfail pos=0x000007fe neg=0x00000000 |
| 19486 | OPC_Decode, 245, 7, 159, 3, // 2738: decode to MVE_DLSTP_16 using decoder 415 |
| 19487 | // 2738: } |
| 19488 | 2, 15, // 2743: case 0x2: { |
| 19489 | OPC_CheckPredicate, 31, // 2745: check predicate 31 |
| 19490 | OPC_CheckField, 23, 4, 0, // 2747: check Inst[26:23] == 0x0 |
| 19491 | OPC_SoftFail, 254, 15, 0, // 2751: softfail pos=0x000007fe neg=0x00000000 |
| 19492 | OPC_Decode, 246, 7, 159, 3, // 2755: decode to MVE_DLSTP_32 using decoder 415 |
| 19493 | // 2755: } |
| 19494 | 3, 0, // 2760: case 0x3: { |
| 19495 | OPC_CheckPredicate, 31, // 2762: check predicate 31 |
| 19496 | OPC_CheckField, 23, 4, 0, // 2764: check Inst[26:23] == 0x0 |
| 19497 | OPC_SoftFail, 254, 15, 0, // 2768: softfail pos=0x000007fe neg=0x00000000 |
| 19498 | OPC_Decode, 247, 7, 159, 3, // 2772: decode to MVE_DLSTP_64 using decoder 415 |
| 19499 | // 2772: } |
| 19500 | // 2772: } // switch Inst[21:20] |
| 19501 | OPC_Scope, 21, // 2777: } else try { |
| 19502 | OPC_CheckField, 16, 4, 15, // 2779: check Inst[19:16] == 0xf |
| 19503 | OPC_CheckPredicate, 31, // 2783: check predicate 31 |
| 19504 | OPC_CheckField, 23, 4, 0, // 2785: check Inst[26:23] == 0x0 |
| 19505 | OPC_SoftFail, 254, 159, 192, 1, 0, // 2789: softfail pos=0x00300ffe neg=0x00000000 |
| 19506 | OPC_Decode, 249, 7, 159, 3, // 2795: decode to MVE_LCTP using decoder 415 |
| 19507 | // 2795: } else try { |
| 19508 | OPC_CheckPredicate, 63, // 2800: check predicate 63 |
| 19509 | OPC_Decode, 219, 31, 161, 3, // 2802: decode to t2BFic using decoder 417 |
| 19510 | // 2802: } |
| 19511 | // 2802: } |
| 19512 | 1, 0, // 2807: case 0x1: { |
| 19513 | OPC_SwitchField, 21, 1, // 2809: switch Inst[21] { |
| 19514 | 0, 32, // 2812: case 0x0: { |
| 19515 | OPC_CheckField, 0, 1, 1, // 2814: check Inst[0] == 0x1 |
| 19516 | OPC_Scope, 19, // 2818: try { |
| 19517 | OPC_CheckField, 1, 11, 0, // 2820: check Inst[11:1] == 0x0 |
| 19518 | OPC_CheckPredicate, 63, // 2824: check predicate 63 |
| 19519 | OPC_CheckField, 23, 4, 0, // 2826: check Inst[26:23] == 0x0 |
| 19520 | OPC_CheckField, 20, 1, 0, // 2830: check Inst[20] == 0x0 |
| 19521 | OPC_Decode, 128, 32, 159, 3, // 2834: decode to t2DLS using decoder 415 |
| 19522 | // 2834: } else try { |
| 19523 | OPC_CheckPredicate, 63, // 2839: check predicate 63 |
| 19524 | OPC_Decode, 218, 31, 162, 3, // 2841: decode to t2BFi using decoder 418 |
| 19525 | // 2841: } |
| 19526 | // 2841: } |
| 19527 | 1, 0, // 2846: case 0x1: { |
| 19528 | OPC_SwitchField, 20, 1, // 2848: switch Inst[20] { |
| 19529 | 0, 11, // 2851: case 0x0: { |
| 19530 | OPC_CheckPredicate, 63, // 2853: check predicate 63 |
| 19531 | OPC_CheckField, 0, 12, 1, // 2855: check Inst[11:0] == 0x1 |
| 19532 | OPC_Decode, 220, 31, 163, 3, // 2859: decode to t2BFr using decoder 419 |
| 19533 | // 2859: } |
| 19534 | 1, 0, // 2864: case 0x1: { |
| 19535 | OPC_CheckPredicate, 63, // 2866: check predicate 63 |
| 19536 | OPC_CheckField, 0, 12, 1, // 2868: check Inst[11:0] == 0x1 |
| 19537 | OPC_Decode, 217, 31, 163, 3, // 2872: decode to t2BFLr using decoder 419 |
| 19538 | // 2872: } |
| 19539 | // 2872: } // switch Inst[20] |
| 19540 | // 2872: } |
| 19541 | // 2872: } // switch Inst[21] |
| 19542 | // 2872: } |
| 19543 | // 2872: } // switch Inst[22] |
| 19544 | // 2872: } |
| 19545 | // 2872: } // switch Inst[13] |
| 19546 | // 2872: } |
| 19547 | // 2872: } // switch Inst[14] |
| 19548 | // 2872: } |
| 19549 | 1, 0, // 2877: case 0x1: { |
| 19550 | OPC_CheckPredicate, 4, // 2879: check predicate 4 |
| 19551 | OPC_CheckField, 14, 1, 0, // 2881: check Inst[14] == 0x0 |
| 19552 | OPC_Decode, 213, 31, 164, 3, // 2885: decode to t2B using decoder 420 |
| 19553 | // 2885: } |
| 19554 | // 2885: } // switch Inst[12] |
| 19555 | // 2885: } |
| 19556 | // 2885: } // switch Inst[15] |
| 19557 | // 2885: } |
| 19558 | 31, 0, // 2890: case 0x1f: { |
| 19559 | OPC_SwitchField, 21, 2, // 2892: switch Inst[22:21] { |
| 19560 | 0, 255, 7, // 2895: case 0x0: { |
| 19561 | OPC_SwitchField, 24, 3, // 2898: switch Inst[26:24] { |
| 19562 | 0, 231, 1, // 2901: case 0x0: { |
| 19563 | OPC_SwitchField, 20, 1, // 2904: switch Inst[20] { |
| 19564 | 0, 79, // 2907: case 0x0: { |
| 19565 | OPC_SwitchField, 23, 1, // 2909: switch Inst[23] { |
| 19566 | 0, 65, // 2912: case 0x0: { |
| 19567 | OPC_SwitchField, 10, 2, // 2914: switch Inst[11:10] { |
| 19568 | 0, 11, // 2917: case 0x0: { |
| 19569 | OPC_CheckPredicate, 9, // 2919: check predicate 9 |
| 19570 | OPC_CheckField, 6, 4, 0, // 2921: check Inst[9:6] == 0x0 |
| 19571 | OPC_Decode, 255, 33, 165, 3, // 2925: decode to t2STRBs using decoder 421 |
| 19572 | // 2925: } |
| 19573 | 2, 11, // 2930: case 0x2: { |
| 19574 | OPC_CheckPredicate, 9, // 2932: check predicate 9 |
| 19575 | OPC_CheckField, 8, 1, 1, // 2934: check Inst[8] == 0x1 |
| 19576 | OPC_Decode, 251, 33, 166, 3, // 2938: decode to t2STRB_POST using decoder 422 |
| 19577 | // 2938: } |
| 19578 | 3, 0, // 2943: case 0x3: { |
| 19579 | OPC_SwitchField, 8, 1, // 2945: switch Inst[8] { |
| 19580 | 0, 20, // 2948: case 0x0: { |
| 19581 | OPC_Scope, 11, // 2950: try { |
| 19582 | OPC_CheckField, 9, 1, 1, // 2952: check Inst[9] == 0x1 |
| 19583 | OPC_CheckPredicate, 9, // 2956: check predicate 9 |
| 19584 | OPC_Decode, 250, 33, 167, 3, // 2958: decode to t2STRBT using decoder 423 |
| 19585 | // 2958: } else try { |
| 19586 | OPC_CheckPredicate, 9, // 2963: check predicate 9 |
| 19587 | OPC_Decode, 254, 33, 168, 3, // 2965: decode to t2STRBi8 using decoder 424 |
| 19588 | // 2965: } |
| 19589 | // 2965: } |
| 19590 | 1, 0, // 2970: case 0x1: { |
| 19591 | OPC_CheckPredicate, 9, // 2972: check predicate 9 |
| 19592 | OPC_Decode, 252, 33, 166, 3, // 2974: decode to t2STRB_PRE using decoder 422 |
| 19593 | // 2974: } |
| 19594 | // 2974: } // switch Inst[8] |
| 19595 | // 2974: } |
| 19596 | // 2974: } // switch Inst[11:10] |
| 19597 | // 2974: } |
| 19598 | 1, 0, // 2979: case 0x1: { |
| 19599 | OPC_CheckPredicate, 9, // 2981: check predicate 9 |
| 19600 | OPC_Decode, 253, 33, 169, 3, // 2983: decode to t2STRBi12 using decoder 425 |
| 19601 | // 2983: } |
| 19602 | // 2983: } // switch Inst[23] |
| 19603 | // 2983: } |
| 19604 | 1, 0, // 2988: case 0x1: { |
| 19605 | OPC_Scope, 119, // 2990: try { |
| 19606 | OPC_SwitchField, 23, 1, // 2992: switch Inst[23] { |
| 19607 | 0, 92, // 2995: case 0x0: { |
| 19608 | OPC_SwitchField, 10, 2, // 2997: switch Inst[11:10] { |
| 19609 | 0, 24, // 3000: case 0x0: { |
| 19610 | OPC_CheckField, 6, 4, 0, // 3002: check Inst[9:6] == 0x0 |
| 19611 | OPC_Scope, 11, // 3006: try { |
| 19612 | OPC_CheckField, 12, 4, 15, // 3008: check Inst[15:12] == 0xf |
| 19613 | OPC_CheckPredicate, 9, // 3012: check predicate 9 |
| 19614 | OPC_Decode, 130, 33, 170, 3, // 3014: decode to t2PLDs using decoder 426 |
| 19615 | // 3014: } else try { |
| 19616 | OPC_CheckPredicate, 9, // 3019: check predicate 9 |
| 19617 | OPC_Decode, 173, 32, 170, 3, // 3021: decode to t2LDRBs using decoder 426 |
| 19618 | // 3021: } |
| 19619 | // 3021: } |
| 19620 | 2, 11, // 3026: case 0x2: { |
| 19621 | OPC_CheckPredicate, 9, // 3028: check predicate 9 |
| 19622 | OPC_CheckField, 8, 1, 1, // 3030: check Inst[8] == 0x1 |
| 19623 | OPC_Decode, 168, 32, 166, 3, // 3034: decode to t2LDRB_POST using decoder 422 |
| 19624 | // 3034: } |
| 19625 | 3, 0, // 3039: case 0x3: { |
| 19626 | OPC_SwitchField, 8, 1, // 3041: switch Inst[8] { |
| 19627 | 0, 34, // 3044: case 0x0: { |
| 19628 | OPC_Scope, 25, // 3046: try { |
| 19629 | OPC_SwitchField, 9, 1, // 3048: switch Inst[9] { |
| 19630 | 0, 11, // 3051: case 0x0: { |
| 19631 | OPC_CheckPredicate, 9, // 3053: check predicate 9 |
| 19632 | OPC_CheckField, 12, 4, 15, // 3055: check Inst[15:12] == 0xf |
| 19633 | OPC_Decode, 128, 33, 171, 3, // 3059: decode to t2PLDi8 using decoder 427 |
| 19634 | // 3059: } |
| 19635 | 1, 0, // 3064: case 0x1: { |
| 19636 | OPC_CheckPredicate, 9, // 3066: check predicate 9 |
| 19637 | OPC_Decode, 167, 32, 172, 3, // 3068: decode to t2LDRBT using decoder 428 |
| 19638 | // 3068: } |
| 19639 | // 3068: } // switch Inst[9] |
| 19640 | // 3068: } else try { |
| 19641 | OPC_CheckPredicate, 9, // 3073: check predicate 9 |
| 19642 | OPC_Decode, 171, 32, 171, 3, // 3075: decode to t2LDRBi8 using decoder 427 |
| 19643 | // 3075: } |
| 19644 | // 3075: } |
| 19645 | 1, 0, // 3080: case 0x1: { |
| 19646 | OPC_CheckPredicate, 9, // 3082: check predicate 9 |
| 19647 | OPC_Decode, 169, 32, 166, 3, // 3084: decode to t2LDRB_PRE using decoder 422 |
| 19648 | // 3084: } |
| 19649 | // 3084: } // switch Inst[8] |
| 19650 | // 3084: } |
| 19651 | // 3084: } // switch Inst[11:10] |
| 19652 | // 3084: } |
| 19653 | 1, 0, // 3089: case 0x1: { |
| 19654 | OPC_Scope, 11, // 3091: try { |
| 19655 | OPC_CheckField, 12, 4, 15, // 3093: check Inst[15:12] == 0xf |
| 19656 | OPC_CheckPredicate, 9, // 3097: check predicate 9 |
| 19657 | OPC_Decode, 255, 32, 173, 3, // 3099: decode to t2PLDi12 using decoder 429 |
| 19658 | // 3099: } else try { |
| 19659 | OPC_CheckPredicate, 9, // 3104: check predicate 9 |
| 19660 | OPC_Decode, 170, 32, 173, 3, // 3106: decode to t2LDRBi12 using decoder 429 |
| 19661 | // 3106: } |
| 19662 | // 3106: } |
| 19663 | // 3106: } // switch Inst[23] |
| 19664 | // 3106: } else try { |
| 19665 | OPC_CheckField, 16, 4, 15, // 3111: check Inst[19:16] == 0xf |
| 19666 | OPC_Scope, 11, // 3115: try { |
| 19667 | OPC_CheckField, 12, 4, 15, // 3117: check Inst[15:12] == 0xf |
| 19668 | OPC_CheckPredicate, 9, // 3121: check predicate 9 |
| 19669 | OPC_Decode, 129, 33, 174, 3, // 3123: decode to t2PLDpci using decoder 430 |
| 19670 | // 3123: } else try { |
| 19671 | OPC_CheckPredicate, 9, // 3128: check predicate 9 |
| 19672 | OPC_Decode, 172, 32, 174, 3, // 3130: decode to t2LDRBpci using decoder 430 |
| 19673 | // 3130: } |
| 19674 | // 3130: } |
| 19675 | // 3130: } |
| 19676 | // 3130: } // switch Inst[20] |
| 19677 | // 3130: } |
| 19678 | 1, 149, 1, // 3135: case 0x1: { |
| 19679 | OPC_CheckField, 20, 1, 1, // 3138: check Inst[20] == 0x1 |
| 19680 | OPC_Scope, 119, // 3142: try { |
| 19681 | OPC_SwitchField, 23, 1, // 3144: switch Inst[23] { |
| 19682 | 0, 92, // 3147: case 0x0: { |
| 19683 | OPC_SwitchField, 10, 2, // 3149: switch Inst[11:10] { |
| 19684 | 0, 24, // 3152: case 0x0: { |
| 19685 | OPC_CheckField, 6, 4, 0, // 3154: check Inst[9:6] == 0x0 |
| 19686 | OPC_Scope, 11, // 3158: try { |
| 19687 | OPC_CheckField, 12, 4, 15, // 3160: check Inst[15:12] == 0xf |
| 19688 | OPC_CheckPredicate, 64, // 3164: check predicate 64 |
| 19689 | OPC_Decode, 134, 33, 170, 3, // 3166: decode to t2PLIs using decoder 426 |
| 19690 | // 3166: } else try { |
| 19691 | OPC_CheckPredicate, 9, // 3171: check predicate 9 |
| 19692 | OPC_Decode, 194, 32, 170, 3, // 3173: decode to t2LDRSBs using decoder 426 |
| 19693 | // 3173: } |
| 19694 | // 3173: } |
| 19695 | 2, 11, // 3178: case 0x2: { |
| 19696 | OPC_CheckPredicate, 9, // 3180: check predicate 9 |
| 19697 | OPC_CheckField, 8, 1, 1, // 3182: check Inst[8] == 0x1 |
| 19698 | OPC_Decode, 189, 32, 166, 3, // 3186: decode to t2LDRSB_POST using decoder 422 |
| 19699 | // 3186: } |
| 19700 | 3, 0, // 3191: case 0x3: { |
| 19701 | OPC_SwitchField, 8, 1, // 3193: switch Inst[8] { |
| 19702 | 0, 34, // 3196: case 0x0: { |
| 19703 | OPC_Scope, 25, // 3198: try { |
| 19704 | OPC_SwitchField, 9, 1, // 3200: switch Inst[9] { |
| 19705 | 0, 11, // 3203: case 0x0: { |
| 19706 | OPC_CheckPredicate, 64, // 3205: check predicate 64 |
| 19707 | OPC_CheckField, 12, 4, 15, // 3207: check Inst[15:12] == 0xf |
| 19708 | OPC_Decode, 132, 33, 171, 3, // 3211: decode to t2PLIi8 using decoder 427 |
| 19709 | // 3211: } |
| 19710 | 1, 0, // 3216: case 0x1: { |
| 19711 | OPC_CheckPredicate, 9, // 3218: check predicate 9 |
| 19712 | OPC_Decode, 188, 32, 172, 3, // 3220: decode to t2LDRSBT using decoder 428 |
| 19713 | // 3220: } |
| 19714 | // 3220: } // switch Inst[9] |
| 19715 | // 3220: } else try { |
| 19716 | OPC_CheckPredicate, 9, // 3225: check predicate 9 |
| 19717 | OPC_Decode, 192, 32, 171, 3, // 3227: decode to t2LDRSBi8 using decoder 427 |
| 19718 | // 3227: } |
| 19719 | // 3227: } |
| 19720 | 1, 0, // 3232: case 0x1: { |
| 19721 | OPC_CheckPredicate, 9, // 3234: check predicate 9 |
| 19722 | OPC_Decode, 190, 32, 166, 3, // 3236: decode to t2LDRSB_PRE using decoder 422 |
| 19723 | // 3236: } |
| 19724 | // 3236: } // switch Inst[8] |
| 19725 | // 3236: } |
| 19726 | // 3236: } // switch Inst[11:10] |
| 19727 | // 3236: } |
| 19728 | 1, 0, // 3241: case 0x1: { |
| 19729 | OPC_Scope, 11, // 3243: try { |
| 19730 | OPC_CheckField, 12, 4, 15, // 3245: check Inst[15:12] == 0xf |
| 19731 | OPC_CheckPredicate, 64, // 3249: check predicate 64 |
| 19732 | OPC_Decode, 131, 33, 173, 3, // 3251: decode to t2PLIi12 using decoder 429 |
| 19733 | // 3251: } else try { |
| 19734 | OPC_CheckPredicate, 9, // 3256: check predicate 9 |
| 19735 | OPC_Decode, 191, 32, 173, 3, // 3258: decode to t2LDRSBi12 using decoder 429 |
| 19736 | // 3258: } |
| 19737 | // 3258: } |
| 19738 | // 3258: } // switch Inst[23] |
| 19739 | // 3258: } else try { |
| 19740 | OPC_CheckField, 16, 4, 15, // 3263: check Inst[19:16] == 0xf |
| 19741 | OPC_Scope, 11, // 3267: try { |
| 19742 | OPC_CheckField, 12, 4, 15, // 3269: check Inst[15:12] == 0xf |
| 19743 | OPC_CheckPredicate, 64, // 3273: check predicate 64 |
| 19744 | OPC_Decode, 133, 33, 174, 3, // 3275: decode to t2PLIpci using decoder 430 |
| 19745 | // 3275: } else try { |
| 19746 | OPC_CheckPredicate, 9, // 3280: check predicate 9 |
| 19747 | OPC_Decode, 193, 32, 174, 3, // 3282: decode to t2LDRSBpci using decoder 430 |
| 19748 | // 3282: } |
| 19749 | // 3282: } |
| 19750 | // 3282: } |
| 19751 | 2, 178, 3, // 3287: case 0x2: { |
| 19752 | OPC_SwitchField, 7, 1, // 3290: switch Inst[7] { |
| 19753 | 0, 247, 1, // 3293: case 0x0: { |
| 19754 | OPC_SwitchField, 4, 3, // 3296: switch Inst[6:4] { |
| 19755 | 0, 47, // 3299: case 0x0: { |
| 19756 | OPC_SwitchField, 23, 1, // 3301: switch Inst[23] { |
| 19757 | 0, 11, // 3304: case 0x0: { |
| 19758 | OPC_CheckPredicate, 9, // 3306: check predicate 9 |
| 19759 | OPC_CheckField, 12, 4, 15, // 3308: check Inst[15:12] == 0xf |
| 19760 | OPC_Decode, 212, 32, 230, 2, // 3312: decode to t2LSLrr using decoder 358 |
| 19761 | // 3312: } |
| 19762 | 1, 0, // 3317: case 0x1: { |
| 19763 | OPC_SwitchField, 20, 1, // 3319: switch Inst[20] { |
| 19764 | 0, 11, // 3322: case 0x0: { |
| 19765 | OPC_CheckPredicate, 52, // 3324: check predicate 52 |
| 19766 | OPC_CheckField, 12, 4, 15, // 3326: check Inst[15:12] == 0xf |
| 19767 | OPC_Decode, 160, 33, 175, 3, // 3330: decode to t2SADD8 using decoder 431 |
| 19768 | // 3330: } |
| 19769 | 1, 0, // 3335: case 0x1: { |
| 19770 | OPC_CheckPredicate, 52, // 3337: check predicate 52 |
| 19771 | OPC_CheckField, 12, 4, 15, // 3339: check Inst[15:12] == 0xf |
| 19772 | OPC_Decode, 159, 33, 175, 3, // 3343: decode to t2SADD16 using decoder 431 |
| 19773 | // 3343: } |
| 19774 | // 3343: } // switch Inst[20] |
| 19775 | // 3343: } |
| 19776 | // 3343: } // switch Inst[23] |
| 19777 | // 3343: } |
| 19778 | 1, 37, // 3348: case 0x1: { |
| 19779 | OPC_SwitchField, 20, 1, // 3350: switch Inst[20] { |
| 19780 | 0, 15, // 3353: case 0x0: { |
| 19781 | OPC_CheckPredicate, 52, // 3355: check predicate 52 |
| 19782 | OPC_CheckField, 23, 1, 1, // 3357: check Inst[23] == 0x1 |
| 19783 | OPC_CheckField, 12, 4, 15, // 3361: check Inst[15:12] == 0xf |
| 19784 | OPC_Decode, 137, 33, 175, 3, // 3365: decode to t2QADD8 using decoder 431 |
| 19785 | // 3365: } |
| 19786 | 1, 0, // 3370: case 0x1: { |
| 19787 | OPC_CheckPredicate, 52, // 3372: check predicate 52 |
| 19788 | OPC_CheckField, 23, 1, 1, // 3374: check Inst[23] == 0x1 |
| 19789 | OPC_CheckField, 12, 4, 15, // 3378: check Inst[15:12] == 0xf |
| 19790 | OPC_Decode, 136, 33, 175, 3, // 3382: decode to t2QADD16 using decoder 431 |
| 19791 | // 3382: } |
| 19792 | // 3382: } // switch Inst[20] |
| 19793 | // 3382: } |
| 19794 | 2, 37, // 3387: case 0x2: { |
| 19795 | OPC_SwitchField, 20, 1, // 3389: switch Inst[20] { |
| 19796 | 0, 15, // 3392: case 0x0: { |
| 19797 | OPC_CheckPredicate, 52, // 3394: check predicate 52 |
| 19798 | OPC_CheckField, 23, 1, 1, // 3396: check Inst[23] == 0x1 |
| 19799 | OPC_CheckField, 12, 4, 15, // 3400: check Inst[15:12] == 0xf |
| 19800 | OPC_Decode, 172, 33, 175, 3, // 3404: decode to t2SHADD8 using decoder 431 |
| 19801 | // 3404: } |
| 19802 | 1, 0, // 3409: case 0x1: { |
| 19803 | OPC_CheckPredicate, 52, // 3411: check predicate 52 |
| 19804 | OPC_CheckField, 23, 1, 1, // 3413: check Inst[23] == 0x1 |
| 19805 | OPC_CheckField, 12, 4, 15, // 3417: check Inst[15:12] == 0xf |
| 19806 | OPC_Decode, 171, 33, 175, 3, // 3421: decode to t2SHADD16 using decoder 431 |
| 19807 | // 3421: } |
| 19808 | // 3421: } // switch Inst[20] |
| 19809 | // 3421: } |
| 19810 | 4, 37, // 3426: case 0x4: { |
| 19811 | OPC_SwitchField, 20, 1, // 3428: switch Inst[20] { |
| 19812 | 0, 15, // 3431: case 0x0: { |
| 19813 | OPC_CheckPredicate, 52, // 3433: check predicate 52 |
| 19814 | OPC_CheckField, 23, 1, 1, // 3435: check Inst[23] == 0x1 |
| 19815 | OPC_CheckField, 12, 4, 15, // 3439: check Inst[15:12] == 0xf |
| 19816 | OPC_Decode, 174, 34, 175, 3, // 3443: decode to t2UADD8 using decoder 431 |
| 19817 | // 3443: } |
| 19818 | 1, 0, // 3448: case 0x1: { |
| 19819 | OPC_CheckPredicate, 52, // 3450: check predicate 52 |
| 19820 | OPC_CheckField, 23, 1, 1, // 3452: check Inst[23] == 0x1 |
| 19821 | OPC_CheckField, 12, 4, 15, // 3456: check Inst[15:12] == 0xf |
| 19822 | OPC_Decode, 173, 34, 175, 3, // 3460: decode to t2UADD16 using decoder 431 |
| 19823 | // 3460: } |
| 19824 | // 3460: } // switch Inst[20] |
| 19825 | // 3460: } |
| 19826 | 5, 37, // 3465: case 0x5: { |
| 19827 | OPC_SwitchField, 20, 1, // 3467: switch Inst[20] { |
| 19828 | 0, 15, // 3470: case 0x0: { |
| 19829 | OPC_CheckPredicate, 52, // 3472: check predicate 52 |
| 19830 | OPC_CheckField, 23, 1, 1, // 3474: check Inst[23] == 0x1 |
| 19831 | OPC_CheckField, 12, 4, 15, // 3478: check Inst[15:12] == 0xf |
| 19832 | OPC_Decode, 189, 34, 175, 3, // 3482: decode to t2UQADD8 using decoder 431 |
| 19833 | // 3482: } |
| 19834 | 1, 0, // 3487: case 0x1: { |
| 19835 | OPC_CheckPredicate, 52, // 3489: check predicate 52 |
| 19836 | OPC_CheckField, 23, 1, 1, // 3491: check Inst[23] == 0x1 |
| 19837 | OPC_CheckField, 12, 4, 15, // 3495: check Inst[15:12] == 0xf |
| 19838 | OPC_Decode, 188, 34, 175, 3, // 3499: decode to t2UQADD16 using decoder 431 |
| 19839 | // 3499: } |
| 19840 | // 3499: } // switch Inst[20] |
| 19841 | // 3499: } |
| 19842 | 6, 0, // 3504: case 0x6: { |
| 19843 | OPC_SwitchField, 20, 1, // 3506: switch Inst[20] { |
| 19844 | 0, 15, // 3509: case 0x0: { |
| 19845 | OPC_CheckPredicate, 52, // 3511: check predicate 52 |
| 19846 | OPC_CheckField, 23, 1, 1, // 3513: check Inst[23] == 0x1 |
| 19847 | OPC_CheckField, 12, 4, 15, // 3517: check Inst[15:12] == 0xf |
| 19848 | OPC_Decode, 180, 34, 175, 3, // 3521: decode to t2UHADD8 using decoder 431 |
| 19849 | // 3521: } |
| 19850 | 1, 0, // 3526: case 0x1: { |
| 19851 | OPC_CheckPredicate, 52, // 3528: check predicate 52 |
| 19852 | OPC_CheckField, 23, 1, 1, // 3530: check Inst[23] == 0x1 |
| 19853 | OPC_CheckField, 12, 4, 15, // 3534: check Inst[15:12] == 0xf |
| 19854 | OPC_Decode, 179, 34, 175, 3, // 3538: decode to t2UHADD16 using decoder 431 |
| 19855 | // 3538: } |
| 19856 | // 3538: } // switch Inst[20] |
| 19857 | // 3538: } |
| 19858 | // 3538: } // switch Inst[6:4] |
| 19859 | // 3538: } |
| 19860 | 1, 0, // 3543: case 0x1: { |
| 19861 | OPC_SwitchField, 20, 1, // 3545: switch Inst[20] { |
| 19862 | 0, 86, // 3548: case 0x0: { |
| 19863 | OPC_SwitchField, 23, 1, // 3550: switch Inst[23] { |
| 19864 | 0, 24, // 3553: case 0x0: { |
| 19865 | OPC_CheckField, 12, 4, 15, // 3555: check Inst[15:12] == 0xf |
| 19866 | OPC_Scope, 11, // 3559: try { |
| 19867 | OPC_CheckField, 16, 4, 15, // 3561: check Inst[19:16] == 0xf |
| 19868 | OPC_CheckPredicate, 9, // 3565: check predicate 9 |
| 19869 | OPC_Decode, 159, 34, 176, 3, // 3567: decode to t2SXTH using decoder 432 |
| 19870 | // 3567: } else try { |
| 19871 | OPC_CheckPredicate, 50, // 3572: check predicate 50 |
| 19872 | OPC_Decode, 156, 34, 177, 3, // 3574: decode to t2SXTAH using decoder 433 |
| 19873 | // 3574: } |
| 19874 | // 3574: } |
| 19875 | 1, 0, // 3579: case 0x1: { |
| 19876 | OPC_SwitchField, 4, 3, // 3581: switch Inst[6:4] { |
| 19877 | 0, 11, // 3584: case 0x0: { |
| 19878 | OPC_CheckPredicate, 52, // 3586: check predicate 52 |
| 19879 | OPC_CheckField, 12, 4, 15, // 3588: check Inst[15:12] == 0xf |
| 19880 | OPC_Decode, 135, 33, 178, 3, // 3592: decode to t2QADD using decoder 434 |
| 19881 | // 3592: } |
| 19882 | 1, 11, // 3597: case 0x1: { |
| 19883 | OPC_CheckPredicate, 52, // 3599: check predicate 52 |
| 19884 | OPC_CheckField, 12, 4, 15, // 3601: check Inst[15:12] == 0xf |
| 19885 | OPC_Decode, 139, 33, 178, 3, // 3605: decode to t2QDADD using decoder 434 |
| 19886 | // 3605: } |
| 19887 | 2, 11, // 3610: case 0x2: { |
| 19888 | OPC_CheckPredicate, 52, // 3612: check predicate 52 |
| 19889 | OPC_CheckField, 12, 4, 15, // 3614: check Inst[15:12] == 0xf |
| 19890 | OPC_Decode, 142, 33, 178, 3, // 3618: decode to t2QSUB using decoder 434 |
| 19891 | // 3618: } |
| 19892 | 3, 0, // 3623: case 0x3: { |
| 19893 | OPC_CheckPredicate, 52, // 3625: check predicate 52 |
| 19894 | OPC_CheckField, 12, 4, 15, // 3627: check Inst[15:12] == 0xf |
| 19895 | OPC_Decode, 140, 33, 178, 3, // 3631: decode to t2QDSUB using decoder 434 |
| 19896 | // 3631: } |
| 19897 | // 3631: } // switch Inst[6:4] |
| 19898 | // 3631: } |
| 19899 | // 3631: } // switch Inst[23] |
| 19900 | // 3631: } |
| 19901 | 1, 0, // 3636: case 0x1: { |
| 19902 | OPC_SwitchField, 23, 1, // 3638: switch Inst[23] { |
| 19903 | 0, 24, // 3641: case 0x0: { |
| 19904 | OPC_CheckField, 12, 4, 15, // 3643: check Inst[15:12] == 0xf |
| 19905 | OPC_Scope, 11, // 3647: try { |
| 19906 | OPC_CheckField, 16, 4, 15, // 3649: check Inst[19:16] == 0xf |
| 19907 | OPC_CheckPredicate, 9, // 3653: check predicate 9 |
| 19908 | OPC_Decode, 206, 34, 176, 3, // 3655: decode to t2UXTH using decoder 432 |
| 19909 | // 3655: } else try { |
| 19910 | OPC_CheckPredicate, 50, // 3660: check predicate 50 |
| 19911 | OPC_Decode, 203, 34, 177, 3, // 3662: decode to t2UXTAH using decoder 433 |
| 19912 | // 3662: } |
| 19913 | // 3662: } |
| 19914 | 1, 0, // 3667: case 0x1: { |
| 19915 | OPC_SwitchField, 4, 3, // 3669: switch Inst[6:4] { |
| 19916 | 0, 11, // 3672: case 0x0: { |
| 19917 | OPC_CheckPredicate, 9, // 3674: check predicate 9 |
| 19918 | OPC_CheckField, 12, 4, 15, // 3676: check Inst[15:12] == 0xf |
| 19919 | OPC_Decode, 146, 33, 179, 3, // 3680: decode to t2REV using decoder 435 |
| 19920 | // 3680: } |
| 19921 | 1, 11, // 3685: case 0x1: { |
| 19922 | OPC_CheckPredicate, 9, // 3687: check predicate 9 |
| 19923 | OPC_CheckField, 12, 4, 15, // 3689: check Inst[15:12] == 0xf |
| 19924 | OPC_Decode, 147, 33, 179, 3, // 3693: decode to t2REV16 using decoder 435 |
| 19925 | // 3693: } |
| 19926 | 2, 11, // 3698: case 0x2: { |
| 19927 | OPC_CheckPredicate, 9, // 3700: check predicate 9 |
| 19928 | OPC_CheckField, 12, 4, 15, // 3702: check Inst[15:12] == 0xf |
| 19929 | OPC_Decode, 145, 33, 179, 3, // 3706: decode to t2RBIT using decoder 435 |
| 19930 | // 3706: } |
| 19931 | 3, 0, // 3711: case 0x3: { |
| 19932 | OPC_CheckPredicate, 9, // 3713: check predicate 9 |
| 19933 | OPC_CheckField, 12, 4, 15, // 3715: check Inst[15:12] == 0xf |
| 19934 | OPC_Decode, 148, 33, 179, 3, // 3719: decode to t2REVSH using decoder 435 |
| 19935 | // 3719: } |
| 19936 | // 3719: } // switch Inst[6:4] |
| 19937 | // 3719: } |
| 19938 | // 3719: } // switch Inst[23] |
| 19939 | // 3719: } |
| 19940 | // 3719: } // switch Inst[20] |
| 19941 | // 3719: } |
| 19942 | // 3719: } // switch Inst[7] |
| 19943 | // 3719: } |
| 19944 | 3, 0, // 3724: case 0x3: { |
| 19945 | OPC_SwitchField, 4, 4, // 3726: switch Inst[7:4] { |
| 19946 | 0, 65, // 3729: case 0x0: { |
| 19947 | OPC_SwitchField, 20, 1, // 3731: switch Inst[20] { |
| 19948 | 0, 34, // 3734: case 0x0: { |
| 19949 | OPC_SwitchField, 23, 1, // 3736: switch Inst[23] { |
| 19950 | 0, 20, // 3739: case 0x0: { |
| 19951 | OPC_Scope, 11, // 3741: try { |
| 19952 | OPC_CheckField, 12, 4, 15, // 3743: check Inst[15:12] == 0xf |
| 19953 | OPC_CheckPredicate, 9, // 3747: check predicate 9 |
| 19954 | OPC_Decode, 237, 32, 175, 3, // 3749: decode to t2MUL using decoder 431 |
| 19955 | // 3749: } else try { |
| 19956 | OPC_CheckPredicate, 9, // 3754: check predicate 9 |
| 19957 | OPC_Decode, 220, 32, 180, 3, // 3756: decode to t2MLA using decoder 436 |
| 19958 | // 3756: } |
| 19959 | // 3756: } |
| 19960 | 1, 0, // 3761: case 0x1: { |
| 19961 | OPC_CheckPredicate, 9, // 3763: check predicate 9 |
| 19962 | OPC_Decode, 207, 33, 181, 3, // 3765: decode to t2SMULL using decoder 437 |
| 19963 | // 3765: } |
| 19964 | // 3765: } // switch Inst[23] |
| 19965 | // 3765: } |
| 19966 | 1, 0, // 3770: case 0x1: { |
| 19967 | OPC_CheckField, 23, 1, 0, // 3772: check Inst[23] == 0x0 |
| 19968 | OPC_Scope, 11, // 3776: try { |
| 19969 | OPC_CheckField, 12, 4, 15, // 3778: check Inst[15:12] == 0xf |
| 19970 | OPC_CheckPredicate, 52, // 3782: check predicate 52 |
| 19971 | OPC_Decode, 205, 33, 175, 3, // 3784: decode to t2SMULBB using decoder 431 |
| 19972 | // 3784: } else try { |
| 19973 | OPC_CheckPredicate, 52, // 3789: check predicate 52 |
| 19974 | OPC_Decode, 178, 33, 180, 3, // 3791: decode to t2SMLABB using decoder 436 |
| 19975 | // 3791: } |
| 19976 | // 3791: } |
| 19977 | // 3791: } // switch Inst[20] |
| 19978 | // 3791: } |
| 19979 | 1, 42, // 3796: case 0x1: { |
| 19980 | OPC_SwitchField, 20, 1, // 3798: switch Inst[20] { |
| 19981 | 0, 11, // 3801: case 0x0: { |
| 19982 | OPC_CheckPredicate, 9, // 3803: check predicate 9 |
| 19983 | OPC_CheckField, 23, 1, 0, // 3805: check Inst[23] == 0x0 |
| 19984 | OPC_Decode, 221, 32, 180, 3, // 3809: decode to t2MLS using decoder 436 |
| 19985 | // 3809: } |
| 19986 | 1, 0, // 3814: case 0x1: { |
| 19987 | OPC_CheckField, 23, 1, 0, // 3816: check Inst[23] == 0x0 |
| 19988 | OPC_Scope, 11, // 3820: try { |
| 19989 | OPC_CheckField, 12, 4, 15, // 3822: check Inst[15:12] == 0xf |
| 19990 | OPC_CheckPredicate, 52, // 3826: check predicate 52 |
| 19991 | OPC_Decode, 206, 33, 175, 3, // 3828: decode to t2SMULBT using decoder 431 |
| 19992 | // 3828: } else try { |
| 19993 | OPC_CheckPredicate, 52, // 3833: check predicate 52 |
| 19994 | OPC_Decode, 179, 33, 180, 3, // 3835: decode to t2SMLABT using decoder 436 |
| 19995 | // 3835: } |
| 19996 | // 3835: } |
| 19997 | // 3835: } // switch Inst[20] |
| 19998 | // 3835: } |
| 19999 | 2, 28, // 3840: case 0x2: { |
| 20000 | OPC_CheckField, 20, 1, 1, // 3842: check Inst[20] == 0x1 |
| 20001 | OPC_CheckField, 23, 1, 0, // 3846: check Inst[23] == 0x0 |
| 20002 | OPC_Scope, 11, // 3850: try { |
| 20003 | OPC_CheckField, 12, 4, 15, // 3852: check Inst[15:12] == 0xf |
| 20004 | OPC_CheckPredicate, 52, // 3856: check predicate 52 |
| 20005 | OPC_Decode, 208, 33, 175, 3, // 3858: decode to t2SMULTB using decoder 431 |
| 20006 | // 3858: } else try { |
| 20007 | OPC_CheckPredicate, 52, // 3863: check predicate 52 |
| 20008 | OPC_Decode, 189, 33, 180, 3, // 3865: decode to t2SMLATB using decoder 436 |
| 20009 | // 3865: } |
| 20010 | // 3865: } |
| 20011 | 3, 28, // 3870: case 0x3: { |
| 20012 | OPC_CheckField, 20, 1, 1, // 3872: check Inst[20] == 0x1 |
| 20013 | OPC_CheckField, 23, 1, 0, // 3876: check Inst[23] == 0x0 |
| 20014 | OPC_Scope, 11, // 3880: try { |
| 20015 | OPC_CheckField, 12, 4, 15, // 3882: check Inst[15:12] == 0xf |
| 20016 | OPC_CheckPredicate, 52, // 3886: check predicate 52 |
| 20017 | OPC_Decode, 209, 33, 175, 3, // 3888: decode to t2SMULTT using decoder 431 |
| 20018 | // 3888: } else try { |
| 20019 | OPC_CheckPredicate, 52, // 3893: check predicate 52 |
| 20020 | OPC_Decode, 190, 33, 180, 3, // 3895: decode to t2SMLATT using decoder 436 |
| 20021 | // 3895: } |
| 20022 | // 3895: } |
| 20023 | 15, 0, // 3900: case 0xf: { |
| 20024 | OPC_CheckPredicate, 65, // 3902: check predicate 65 |
| 20025 | OPC_CheckField, 23, 1, 1, // 3904: check Inst[23] == 0x1 |
| 20026 | OPC_CheckField, 20, 1, 1, // 3908: check Inst[20] == 0x1 |
| 20027 | OPC_CheckField, 12, 4, 15, // 3912: check Inst[15:12] == 0xf |
| 20028 | OPC_Decode, 167, 33, 175, 3, // 3916: decode to t2SDIV using decoder 431 |
| 20029 | // 3916: } |
| 20030 | // 3916: } // switch Inst[7:4] |
| 20031 | // 3916: } |
| 20032 | // 3916: } // switch Inst[26:24] |
| 20033 | // 3916: } |
| 20034 | 1, 213, 5, // 3921: case 0x1: { |
| 20035 | OPC_SwitchField, 24, 3, // 3924: switch Inst[26:24] { |
| 20036 | 0, 218, 1, // 3927: case 0x0: { |
| 20037 | OPC_SwitchField, 20, 1, // 3930: switch Inst[20] { |
| 20038 | 0, 79, // 3933: case 0x0: { |
| 20039 | OPC_SwitchField, 23, 1, // 3935: switch Inst[23] { |
| 20040 | 0, 65, // 3938: case 0x0: { |
| 20041 | OPC_SwitchField, 10, 2, // 3940: switch Inst[11:10] { |
| 20042 | 0, 11, // 3943: case 0x0: { |
| 20043 | OPC_CheckPredicate, 9, // 3945: check predicate 9 |
| 20044 | OPC_CheckField, 6, 4, 0, // 3947: check Inst[9:6] == 0x0 |
| 20045 | OPC_Decode, 140, 34, 165, 3, // 3951: decode to t2STRHs using decoder 421 |
| 20046 | // 3951: } |
| 20047 | 2, 11, // 3956: case 0x2: { |
| 20048 | OPC_CheckPredicate, 9, // 3958: check predicate 9 |
| 20049 | OPC_CheckField, 8, 1, 1, // 3960: check Inst[8] == 0x1 |
| 20050 | OPC_Decode, 136, 34, 166, 3, // 3964: decode to t2STRH_POST using decoder 422 |
| 20051 | // 3964: } |
| 20052 | 3, 0, // 3969: case 0x3: { |
| 20053 | OPC_SwitchField, 8, 1, // 3971: switch Inst[8] { |
| 20054 | 0, 20, // 3974: case 0x0: { |
| 20055 | OPC_Scope, 11, // 3976: try { |
| 20056 | OPC_CheckField, 9, 1, 1, // 3978: check Inst[9] == 0x1 |
| 20057 | OPC_CheckPredicate, 9, // 3982: check predicate 9 |
| 20058 | OPC_Decode, 135, 34, 167, 3, // 3984: decode to t2STRHT using decoder 423 |
| 20059 | // 3984: } else try { |
| 20060 | OPC_CheckPredicate, 9, // 3989: check predicate 9 |
| 20061 | OPC_Decode, 139, 34, 168, 3, // 3991: decode to t2STRHi8 using decoder 424 |
| 20062 | // 3991: } |
| 20063 | // 3991: } |
| 20064 | 1, 0, // 3996: case 0x1: { |
| 20065 | OPC_CheckPredicate, 9, // 3998: check predicate 9 |
| 20066 | OPC_Decode, 137, 34, 166, 3, // 4000: decode to t2STRH_PRE using decoder 422 |
| 20067 | // 4000: } |
| 20068 | // 4000: } // switch Inst[8] |
| 20069 | // 4000: } |
| 20070 | // 4000: } // switch Inst[11:10] |
| 20071 | // 4000: } |
| 20072 | 1, 0, // 4005: case 0x1: { |
| 20073 | OPC_CheckPredicate, 9, // 4007: check predicate 9 |
| 20074 | OPC_Decode, 138, 34, 169, 3, // 4009: decode to t2STRHi12 using decoder 425 |
| 20075 | // 4009: } |
| 20076 | // 4009: } // switch Inst[23] |
| 20077 | // 4009: } |
| 20078 | 1, 0, // 4014: case 0x1: { |
| 20079 | OPC_Scope, 119, // 4016: try { |
| 20080 | OPC_SwitchField, 23, 1, // 4018: switch Inst[23] { |
| 20081 | 0, 92, // 4021: case 0x0: { |
| 20082 | OPC_SwitchField, 10, 2, // 4023: switch Inst[11:10] { |
| 20083 | 0, 24, // 4026: case 0x0: { |
| 20084 | OPC_CheckField, 6, 4, 0, // 4028: check Inst[9:6] == 0x0 |
| 20085 | OPC_Scope, 11, // 4032: try { |
| 20086 | OPC_CheckField, 12, 4, 15, // 4034: check Inst[15:12] == 0xf |
| 20087 | OPC_CheckPredicate, 66, // 4038: check predicate 66 |
| 20088 | OPC_Decode, 254, 32, 170, 3, // 4040: decode to t2PLDWs using decoder 426 |
| 20089 | // 4040: } else try { |
| 20090 | OPC_CheckPredicate, 9, // 4045: check predicate 9 |
| 20091 | OPC_Decode, 187, 32, 170, 3, // 4047: decode to t2LDRHs using decoder 426 |
| 20092 | // 4047: } |
| 20093 | // 4047: } |
| 20094 | 2, 11, // 4052: case 0x2: { |
| 20095 | OPC_CheckPredicate, 9, // 4054: check predicate 9 |
| 20096 | OPC_CheckField, 8, 1, 1, // 4056: check Inst[8] == 0x1 |
| 20097 | OPC_Decode, 182, 32, 166, 3, // 4060: decode to t2LDRH_POST using decoder 422 |
| 20098 | // 4060: } |
| 20099 | 3, 0, // 4065: case 0x3: { |
| 20100 | OPC_SwitchField, 8, 1, // 4067: switch Inst[8] { |
| 20101 | 0, 34, // 4070: case 0x0: { |
| 20102 | OPC_Scope, 25, // 4072: try { |
| 20103 | OPC_SwitchField, 9, 1, // 4074: switch Inst[9] { |
| 20104 | 0, 11, // 4077: case 0x0: { |
| 20105 | OPC_CheckPredicate, 66, // 4079: check predicate 66 |
| 20106 | OPC_CheckField, 12, 4, 15, // 4081: check Inst[15:12] == 0xf |
| 20107 | OPC_Decode, 253, 32, 171, 3, // 4085: decode to t2PLDWi8 using decoder 427 |
| 20108 | // 4085: } |
| 20109 | 1, 0, // 4090: case 0x1: { |
| 20110 | OPC_CheckPredicate, 9, // 4092: check predicate 9 |
| 20111 | OPC_Decode, 181, 32, 172, 3, // 4094: decode to t2LDRHT using decoder 428 |
| 20112 | // 4094: } |
| 20113 | // 4094: } // switch Inst[9] |
| 20114 | // 4094: } else try { |
| 20115 | OPC_CheckPredicate, 9, // 4099: check predicate 9 |
| 20116 | OPC_Decode, 185, 32, 171, 3, // 4101: decode to t2LDRHi8 using decoder 427 |
| 20117 | // 4101: } |
| 20118 | // 4101: } |
| 20119 | 1, 0, // 4106: case 0x1: { |
| 20120 | OPC_CheckPredicate, 9, // 4108: check predicate 9 |
| 20121 | OPC_Decode, 183, 32, 166, 3, // 4110: decode to t2LDRH_PRE using decoder 422 |
| 20122 | // 4110: } |
| 20123 | // 4110: } // switch Inst[8] |
| 20124 | // 4110: } |
| 20125 | // 4110: } // switch Inst[11:10] |
| 20126 | // 4110: } |
| 20127 | 1, 0, // 4115: case 0x1: { |
| 20128 | OPC_Scope, 11, // 4117: try { |
| 20129 | OPC_CheckField, 12, 4, 15, // 4119: check Inst[15:12] == 0xf |
| 20130 | OPC_CheckPredicate, 66, // 4123: check predicate 66 |
| 20131 | OPC_Decode, 252, 32, 173, 3, // 4125: decode to t2PLDWi12 using decoder 429 |
| 20132 | // 4125: } else try { |
| 20133 | OPC_CheckPredicate, 9, // 4130: check predicate 9 |
| 20134 | OPC_Decode, 184, 32, 173, 3, // 4132: decode to t2LDRHi12 using decoder 429 |
| 20135 | // 4132: } |
| 20136 | // 4132: } |
| 20137 | // 4132: } // switch Inst[23] |
| 20138 | // 4132: } else try { |
| 20139 | OPC_CheckPredicate, 9, // 4137: check predicate 9 |
| 20140 | OPC_CheckField, 16, 4, 15, // 4139: check Inst[19:16] == 0xf |
| 20141 | OPC_Decode, 186, 32, 174, 3, // 4143: decode to t2LDRHpci using decoder 430 |
| 20142 | // 4143: } |
| 20143 | // 4143: } |
| 20144 | // 4143: } // switch Inst[20] |
| 20145 | // 4143: } |
| 20146 | 1, 96, // 4148: case 0x1: { |
| 20147 | OPC_CheckField, 20, 1, 1, // 4150: check Inst[20] == 0x1 |
| 20148 | OPC_Scope, 79, // 4154: try { |
| 20149 | OPC_SwitchField, 23, 1, // 4156: switch Inst[23] { |
| 20150 | 0, 65, // 4159: case 0x0: { |
| 20151 | OPC_SwitchField, 10, 2, // 4161: switch Inst[11:10] { |
| 20152 | 0, 11, // 4164: case 0x0: { |
| 20153 | OPC_CheckPredicate, 9, // 4166: check predicate 9 |
| 20154 | OPC_CheckField, 6, 4, 0, // 4168: check Inst[9:6] == 0x0 |
| 20155 | OPC_Decode, 201, 32, 170, 3, // 4172: decode to t2LDRSHs using decoder 426 |
| 20156 | // 4172: } |
| 20157 | 2, 11, // 4177: case 0x2: { |
| 20158 | OPC_CheckPredicate, 9, // 4179: check predicate 9 |
| 20159 | OPC_CheckField, 8, 1, 1, // 4181: check Inst[8] == 0x1 |
| 20160 | OPC_Decode, 196, 32, 166, 3, // 4185: decode to t2LDRSH_POST using decoder 422 |
| 20161 | // 4185: } |
| 20162 | 3, 0, // 4190: case 0x3: { |
| 20163 | OPC_SwitchField, 8, 1, // 4192: switch Inst[8] { |
| 20164 | 0, 20, // 4195: case 0x0: { |
| 20165 | OPC_Scope, 11, // 4197: try { |
| 20166 | OPC_CheckField, 9, 1, 1, // 4199: check Inst[9] == 0x1 |
| 20167 | OPC_CheckPredicate, 9, // 4203: check predicate 9 |
| 20168 | OPC_Decode, 195, 32, 172, 3, // 4205: decode to t2LDRSHT using decoder 428 |
| 20169 | // 4205: } else try { |
| 20170 | OPC_CheckPredicate, 9, // 4210: check predicate 9 |
| 20171 | OPC_Decode, 199, 32, 171, 3, // 4212: decode to t2LDRSHi8 using decoder 427 |
| 20172 | // 4212: } |
| 20173 | // 4212: } |
| 20174 | 1, 0, // 4217: case 0x1: { |
| 20175 | OPC_CheckPredicate, 9, // 4219: check predicate 9 |
| 20176 | OPC_Decode, 197, 32, 166, 3, // 4221: decode to t2LDRSH_PRE using decoder 422 |
| 20177 | // 4221: } |
| 20178 | // 4221: } // switch Inst[8] |
| 20179 | // 4221: } |
| 20180 | // 4221: } // switch Inst[11:10] |
| 20181 | // 4221: } |
| 20182 | 1, 0, // 4226: case 0x1: { |
| 20183 | OPC_CheckPredicate, 9, // 4228: check predicate 9 |
| 20184 | OPC_Decode, 198, 32, 173, 3, // 4230: decode to t2LDRSHi12 using decoder 429 |
| 20185 | // 4230: } |
| 20186 | // 4230: } // switch Inst[23] |
| 20187 | // 4230: } else try { |
| 20188 | OPC_CheckPredicate, 9, // 4235: check predicate 9 |
| 20189 | OPC_CheckField, 16, 4, 15, // 4237: check Inst[19:16] == 0xf |
| 20190 | OPC_Decode, 200, 32, 174, 3, // 4241: decode to t2LDRSHpci using decoder 430 |
| 20191 | // 4241: } |
| 20192 | // 4241: } |
| 20193 | 2, 250, 1, // 4246: case 0x2: { |
| 20194 | OPC_SwitchField, 7, 1, // 4249: switch Inst[7] { |
| 20195 | 0, 143, 1, // 4252: case 0x0: { |
| 20196 | OPC_SwitchField, 4, 3, // 4255: switch Inst[6:4] { |
| 20197 | 0, 33, // 4258: case 0x0: { |
| 20198 | OPC_SwitchField, 23, 1, // 4260: switch Inst[23] { |
| 20199 | 0, 11, // 4263: case 0x0: { |
| 20200 | OPC_CheckPredicate, 9, // 4265: check predicate 9 |
| 20201 | OPC_CheckField, 12, 4, 15, // 4267: check Inst[15:12] == 0xf |
| 20202 | OPC_Decode, 214, 32, 230, 2, // 4271: decode to t2LSRrr using decoder 358 |
| 20203 | // 4271: } |
| 20204 | 1, 0, // 4276: case 0x1: { |
| 20205 | OPC_CheckPredicate, 52, // 4278: check predicate 52 |
| 20206 | OPC_CheckField, 20, 1, 0, // 4280: check Inst[20] == 0x0 |
| 20207 | OPC_CheckField, 12, 4, 15, // 4284: check Inst[15:12] == 0xf |
| 20208 | OPC_Decode, 161, 33, 175, 3, // 4288: decode to t2SASX using decoder 431 |
| 20209 | // 4288: } |
| 20210 | // 4288: } // switch Inst[23] |
| 20211 | // 4288: } |
| 20212 | 1, 19, // 4293: case 0x1: { |
| 20213 | OPC_CheckPredicate, 52, // 4295: check predicate 52 |
| 20214 | OPC_CheckField, 23, 1, 1, // 4297: check Inst[23] == 0x1 |
| 20215 | OPC_CheckField, 20, 1, 0, // 4301: check Inst[20] == 0x0 |
| 20216 | OPC_CheckField, 12, 4, 15, // 4305: check Inst[15:12] == 0xf |
| 20217 | OPC_Decode, 138, 33, 175, 3, // 4309: decode to t2QASX using decoder 431 |
| 20218 | // 4309: } |
| 20219 | 2, 19, // 4314: case 0x2: { |
| 20220 | OPC_CheckPredicate, 52, // 4316: check predicate 52 |
| 20221 | OPC_CheckField, 23, 1, 1, // 4318: check Inst[23] == 0x1 |
| 20222 | OPC_CheckField, 20, 1, 0, // 4322: check Inst[20] == 0x0 |
| 20223 | OPC_CheckField, 12, 4, 15, // 4326: check Inst[15:12] == 0xf |
| 20224 | OPC_Decode, 173, 33, 175, 3, // 4330: decode to t2SHASX using decoder 431 |
| 20225 | // 4330: } |
| 20226 | 4, 19, // 4335: case 0x4: { |
| 20227 | OPC_CheckPredicate, 52, // 4337: check predicate 52 |
| 20228 | OPC_CheckField, 23, 1, 1, // 4339: check Inst[23] == 0x1 |
| 20229 | OPC_CheckField, 20, 1, 0, // 4343: check Inst[20] == 0x0 |
| 20230 | OPC_CheckField, 12, 4, 15, // 4347: check Inst[15:12] == 0xf |
| 20231 | OPC_Decode, 175, 34, 175, 3, // 4351: decode to t2UASX using decoder 431 |
| 20232 | // 4351: } |
| 20233 | 5, 19, // 4356: case 0x5: { |
| 20234 | OPC_CheckPredicate, 52, // 4358: check predicate 52 |
| 20235 | OPC_CheckField, 23, 1, 1, // 4360: check Inst[23] == 0x1 |
| 20236 | OPC_CheckField, 20, 1, 0, // 4364: check Inst[20] == 0x0 |
| 20237 | OPC_CheckField, 12, 4, 15, // 4368: check Inst[15:12] == 0xf |
| 20238 | OPC_Decode, 190, 34, 175, 3, // 4372: decode to t2UQASX using decoder 431 |
| 20239 | // 4372: } |
| 20240 | 6, 0, // 4377: case 0x6: { |
| 20241 | OPC_CheckPredicate, 52, // 4379: check predicate 52 |
| 20242 | OPC_CheckField, 23, 1, 1, // 4381: check Inst[23] == 0x1 |
| 20243 | OPC_CheckField, 20, 1, 0, // 4385: check Inst[20] == 0x0 |
| 20244 | OPC_CheckField, 12, 4, 15, // 4389: check Inst[15:12] == 0xf |
| 20245 | OPC_Decode, 181, 34, 175, 3, // 4393: decode to t2UHASX using decoder 431 |
| 20246 | // 4393: } |
| 20247 | // 4393: } // switch Inst[6:4] |
| 20248 | // 4393: } |
| 20249 | 1, 0, // 4398: case 0x1: { |
| 20250 | OPC_SwitchField, 20, 1, // 4400: switch Inst[20] { |
| 20251 | 0, 46, // 4403: case 0x0: { |
| 20252 | OPC_SwitchField, 23, 1, // 4405: switch Inst[23] { |
| 20253 | 0, 24, // 4408: case 0x0: { |
| 20254 | OPC_CheckField, 12, 4, 15, // 4410: check Inst[15:12] == 0xf |
| 20255 | OPC_Scope, 11, // 4414: try { |
| 20256 | OPC_CheckField, 16, 4, 15, // 4416: check Inst[19:16] == 0xf |
| 20257 | OPC_CheckPredicate, 50, // 4420: check predicate 50 |
| 20258 | OPC_Decode, 158, 34, 176, 3, // 4422: decode to t2SXTB16 using decoder 432 |
| 20259 | // 4422: } else try { |
| 20260 | OPC_CheckPredicate, 50, // 4427: check predicate 50 |
| 20261 | OPC_Decode, 155, 34, 177, 3, // 4429: decode to t2SXTAB16 using decoder 433 |
| 20262 | // 4429: } |
| 20263 | // 4429: } |
| 20264 | 1, 0, // 4434: case 0x1: { |
| 20265 | OPC_CheckPredicate, 52, // 4436: check predicate 52 |
| 20266 | OPC_CheckField, 12, 4, 15, // 4438: check Inst[15:12] == 0xf |
| 20267 | OPC_CheckField, 4, 3, 0, // 4442: check Inst[6:4] == 0x0 |
| 20268 | OPC_Decode, 168, 33, 182, 3, // 4446: decode to t2SEL using decoder 438 |
| 20269 | // 4446: } |
| 20270 | // 4446: } // switch Inst[23] |
| 20271 | // 4446: } |
| 20272 | 1, 0, // 4451: case 0x1: { |
| 20273 | OPC_SwitchField, 23, 1, // 4453: switch Inst[23] { |
| 20274 | 0, 24, // 4456: case 0x0: { |
| 20275 | OPC_CheckField, 12, 4, 15, // 4458: check Inst[15:12] == 0xf |
| 20276 | OPC_Scope, 11, // 4462: try { |
| 20277 | OPC_CheckField, 16, 4, 15, // 4464: check Inst[19:16] == 0xf |
| 20278 | OPC_CheckPredicate, 50, // 4468: check predicate 50 |
| 20279 | OPC_Decode, 205, 34, 176, 3, // 4470: decode to t2UXTB16 using decoder 432 |
| 20280 | // 4470: } else try { |
| 20281 | OPC_CheckPredicate, 50, // 4475: check predicate 50 |
| 20282 | OPC_Decode, 202, 34, 177, 3, // 4477: decode to t2UXTAB16 using decoder 433 |
| 20283 | // 4477: } |
| 20284 | // 4477: } |
| 20285 | 1, 0, // 4482: case 0x1: { |
| 20286 | OPC_CheckPredicate, 9, // 4484: check predicate 9 |
| 20287 | OPC_CheckField, 12, 4, 15, // 4486: check Inst[15:12] == 0xf |
| 20288 | OPC_CheckField, 4, 3, 0, // 4490: check Inst[6:4] == 0x0 |
| 20289 | OPC_Decode, 232, 31, 179, 3, // 4494: decode to t2CLZ using decoder 435 |
| 20290 | // 4494: } |
| 20291 | // 4494: } // switch Inst[23] |
| 20292 | // 4494: } |
| 20293 | // 4494: } // switch Inst[20] |
| 20294 | // 4494: } |
| 20295 | // 4494: } // switch Inst[7] |
| 20296 | // 4494: } |
| 20297 | 3, 0, // 4499: case 0x3: { |
| 20298 | OPC_SwitchField, 4, 4, // 4501: switch Inst[7:4] { |
| 20299 | 0, 65, // 4504: case 0x0: { |
| 20300 | OPC_SwitchField, 20, 1, // 4506: switch Inst[20] { |
| 20301 | 0, 34, // 4509: case 0x0: { |
| 20302 | OPC_SwitchField, 23, 1, // 4511: switch Inst[23] { |
| 20303 | 0, 20, // 4514: case 0x0: { |
| 20304 | OPC_Scope, 11, // 4516: try { |
| 20305 | OPC_CheckField, 12, 4, 15, // 4518: check Inst[15:12] == 0xf |
| 20306 | OPC_CheckPredicate, 52, // 4522: check predicate 52 |
| 20307 | OPC_Decode, 203, 33, 175, 3, // 4524: decode to t2SMUAD using decoder 431 |
| 20308 | // 4524: } else try { |
| 20309 | OPC_CheckPredicate, 52, // 4529: check predicate 52 |
| 20310 | OPC_Decode, 180, 33, 180, 3, // 4531: decode to t2SMLAD using decoder 436 |
| 20311 | // 4531: } |
| 20312 | // 4531: } |
| 20313 | 1, 0, // 4536: case 0x1: { |
| 20314 | OPC_CheckPredicate, 9, // 4538: check predicate 9 |
| 20315 | OPC_Decode, 187, 34, 181, 3, // 4540: decode to t2UMULL using decoder 437 |
| 20316 | // 4540: } |
| 20317 | // 4540: } // switch Inst[23] |
| 20318 | // 4540: } |
| 20319 | 1, 0, // 4545: case 0x1: { |
| 20320 | OPC_CheckField, 23, 1, 0, // 4547: check Inst[23] == 0x0 |
| 20321 | OPC_Scope, 11, // 4551: try { |
| 20322 | OPC_CheckField, 12, 4, 15, // 4553: check Inst[15:12] == 0xf |
| 20323 | OPC_CheckPredicate, 52, // 4557: check predicate 52 |
| 20324 | OPC_Decode, 210, 33, 175, 3, // 4559: decode to t2SMULWB using decoder 431 |
| 20325 | // 4559: } else try { |
| 20326 | OPC_CheckPredicate, 52, // 4564: check predicate 52 |
| 20327 | OPC_Decode, 191, 33, 180, 3, // 4566: decode to t2SMLAWB using decoder 436 |
| 20328 | // 4566: } |
| 20329 | // 4566: } |
| 20330 | // 4566: } // switch Inst[20] |
| 20331 | // 4566: } |
| 20332 | 1, 55, // 4571: case 0x1: { |
| 20333 | OPC_SwitchField, 20, 1, // 4573: switch Inst[20] { |
| 20334 | 0, 24, // 4576: case 0x0: { |
| 20335 | OPC_CheckField, 23, 1, 0, // 4578: check Inst[23] == 0x0 |
| 20336 | OPC_Scope, 11, // 4582: try { |
| 20337 | OPC_CheckField, 12, 4, 15, // 4584: check Inst[15:12] == 0xf |
| 20338 | OPC_CheckPredicate, 52, // 4588: check predicate 52 |
| 20339 | OPC_Decode, 204, 33, 175, 3, // 4590: decode to t2SMUADX using decoder 431 |
| 20340 | // 4590: } else try { |
| 20341 | OPC_CheckPredicate, 52, // 4595: check predicate 52 |
| 20342 | OPC_Decode, 181, 33, 180, 3, // 4597: decode to t2SMLADX using decoder 436 |
| 20343 | // 4597: } |
| 20344 | // 4597: } |
| 20345 | 1, 0, // 4602: case 0x1: { |
| 20346 | OPC_CheckField, 23, 1, 0, // 4604: check Inst[23] == 0x0 |
| 20347 | OPC_Scope, 11, // 4608: try { |
| 20348 | OPC_CheckField, 12, 4, 15, // 4610: check Inst[15:12] == 0xf |
| 20349 | OPC_CheckPredicate, 52, // 4614: check predicate 52 |
| 20350 | OPC_Decode, 211, 33, 175, 3, // 4616: decode to t2SMULWT using decoder 431 |
| 20351 | // 4616: } else try { |
| 20352 | OPC_CheckPredicate, 52, // 4621: check predicate 52 |
| 20353 | OPC_Decode, 192, 33, 180, 3, // 4623: decode to t2SMLAWT using decoder 436 |
| 20354 | // 4623: } |
| 20355 | // 4623: } |
| 20356 | // 4623: } // switch Inst[20] |
| 20357 | // 4623: } |
| 20358 | 15, 0, // 4628: case 0xf: { |
| 20359 | OPC_CheckPredicate, 65, // 4630: check predicate 65 |
| 20360 | OPC_CheckField, 23, 1, 1, // 4632: check Inst[23] == 0x1 |
| 20361 | OPC_CheckField, 20, 1, 1, // 4636: check Inst[20] == 0x1 |
| 20362 | OPC_CheckField, 12, 4, 15, // 4640: check Inst[15:12] == 0xf |
| 20363 | OPC_Decode, 178, 34, 175, 3, // 4644: decode to t2UDIV using decoder 431 |
| 20364 | // 4644: } |
| 20365 | // 4644: } // switch Inst[7:4] |
| 20366 | // 4644: } |
| 20367 | // 4644: } // switch Inst[26:24] |
| 20368 | // 4644: } |
| 20369 | 2, 240, 6, // 4649: case 0x2: { |
| 20370 | OPC_SwitchField, 24, 3, // 4652: switch Inst[26:24] { |
| 20371 | 0, 178, 1, // 4655: case 0x0: { |
| 20372 | OPC_SwitchField, 20, 1, // 4658: switch Inst[20] { |
| 20373 | 0, 79, // 4661: case 0x0: { |
| 20374 | OPC_SwitchField, 23, 1, // 4663: switch Inst[23] { |
| 20375 | 0, 65, // 4666: case 0x0: { |
| 20376 | OPC_SwitchField, 10, 2, // 4668: switch Inst[11:10] { |
| 20377 | 0, 11, // 4671: case 0x0: { |
| 20378 | OPC_CheckPredicate, 9, // 4673: check predicate 9 |
| 20379 | OPC_CheckField, 6, 4, 0, // 4675: check Inst[9:6] == 0x0 |
| 20380 | OPC_Decode, 146, 34, 183, 3, // 4679: decode to t2STRs using decoder 439 |
| 20381 | // 4679: } |
| 20382 | 2, 11, // 4684: case 0x2: { |
| 20383 | OPC_CheckPredicate, 9, // 4686: check predicate 9 |
| 20384 | OPC_CheckField, 8, 1, 1, // 4688: check Inst[8] == 0x1 |
| 20385 | OPC_Decode, 142, 34, 166, 3, // 4692: decode to t2STR_POST using decoder 422 |
| 20386 | // 4692: } |
| 20387 | 3, 0, // 4697: case 0x3: { |
| 20388 | OPC_SwitchField, 8, 1, // 4699: switch Inst[8] { |
| 20389 | 0, 20, // 4702: case 0x0: { |
| 20390 | OPC_Scope, 11, // 4704: try { |
| 20391 | OPC_CheckField, 9, 1, 1, // 4706: check Inst[9] == 0x1 |
| 20392 | OPC_CheckPredicate, 9, // 4710: check predicate 9 |
| 20393 | OPC_Decode, 141, 34, 167, 3, // 4712: decode to t2STRT using decoder 423 |
| 20394 | // 4712: } else try { |
| 20395 | OPC_CheckPredicate, 9, // 4717: check predicate 9 |
| 20396 | OPC_Decode, 145, 34, 184, 3, // 4719: decode to t2STRi8 using decoder 440 |
| 20397 | // 4719: } |
| 20398 | // 4719: } |
| 20399 | 1, 0, // 4724: case 0x1: { |
| 20400 | OPC_CheckPredicate, 9, // 4726: check predicate 9 |
| 20401 | OPC_Decode, 143, 34, 166, 3, // 4728: decode to t2STR_PRE using decoder 422 |
| 20402 | // 4728: } |
| 20403 | // 4728: } // switch Inst[8] |
| 20404 | // 4728: } |
| 20405 | // 4728: } // switch Inst[11:10] |
| 20406 | // 4728: } |
| 20407 | 1, 0, // 4733: case 0x1: { |
| 20408 | OPC_CheckPredicate, 9, // 4735: check predicate 9 |
| 20409 | OPC_Decode, 144, 34, 185, 3, // 4737: decode to t2STRi12 using decoder 441 |
| 20410 | // 4737: } |
| 20411 | // 4737: } // switch Inst[23] |
| 20412 | // 4737: } |
| 20413 | 1, 0, // 4742: case 0x1: { |
| 20414 | OPC_Scope, 79, // 4744: try { |
| 20415 | OPC_SwitchField, 23, 1, // 4746: switch Inst[23] { |
| 20416 | 0, 65, // 4749: case 0x0: { |
| 20417 | OPC_SwitchField, 10, 2, // 4751: switch Inst[11:10] { |
| 20418 | 0, 11, // 4754: case 0x0: { |
| 20419 | OPC_CheckPredicate, 9, // 4756: check predicate 9 |
| 20420 | OPC_CheckField, 6, 4, 0, // 4758: check Inst[9:6] == 0x0 |
| 20421 | OPC_Decode, 208, 32, 170, 3, // 4762: decode to t2LDRs using decoder 426 |
| 20422 | // 4762: } |
| 20423 | 2, 11, // 4767: case 0x2: { |
| 20424 | OPC_CheckPredicate, 9, // 4769: check predicate 9 |
| 20425 | OPC_CheckField, 8, 1, 1, // 4771: check Inst[8] == 0x1 |
| 20426 | OPC_Decode, 203, 32, 166, 3, // 4775: decode to t2LDR_POST using decoder 422 |
| 20427 | // 4775: } |
| 20428 | 3, 0, // 4780: case 0x3: { |
| 20429 | OPC_SwitchField, 8, 1, // 4782: switch Inst[8] { |
| 20430 | 0, 20, // 4785: case 0x0: { |
| 20431 | OPC_Scope, 11, // 4787: try { |
| 20432 | OPC_CheckField, 9, 1, 1, // 4789: check Inst[9] == 0x1 |
| 20433 | OPC_CheckPredicate, 9, // 4793: check predicate 9 |
| 20434 | OPC_Decode, 202, 32, 172, 3, // 4795: decode to t2LDRT using decoder 428 |
| 20435 | // 4795: } else try { |
| 20436 | OPC_CheckPredicate, 9, // 4800: check predicate 9 |
| 20437 | OPC_Decode, 206, 32, 171, 3, // 4802: decode to t2LDRi8 using decoder 427 |
| 20438 | // 4802: } |
| 20439 | // 4802: } |
| 20440 | 1, 0, // 4807: case 0x1: { |
| 20441 | OPC_CheckPredicate, 9, // 4809: check predicate 9 |
| 20442 | OPC_Decode, 204, 32, 166, 3, // 4811: decode to t2LDR_PRE using decoder 422 |
| 20443 | // 4811: } |
| 20444 | // 4811: } // switch Inst[8] |
| 20445 | // 4811: } |
| 20446 | // 4811: } // switch Inst[11:10] |
| 20447 | // 4811: } |
| 20448 | 1, 0, // 4816: case 0x1: { |
| 20449 | OPC_CheckPredicate, 9, // 4818: check predicate 9 |
| 20450 | OPC_Decode, 205, 32, 173, 3, // 4820: decode to t2LDRi12 using decoder 429 |
| 20451 | // 4820: } |
| 20452 | // 4820: } // switch Inst[23] |
| 20453 | // 4820: } else try { |
| 20454 | OPC_CheckPredicate, 9, // 4825: check predicate 9 |
| 20455 | OPC_CheckField, 16, 4, 15, // 4827: check Inst[19:16] == 0xf |
| 20456 | OPC_Decode, 207, 32, 174, 3, // 4831: decode to t2LDRpci using decoder 430 |
| 20457 | // 4831: } |
| 20458 | // 4831: } |
| 20459 | // 4831: } // switch Inst[20] |
| 20460 | // 4831: } |
| 20461 | 2, 152, 3, // 4836: case 0x2: { |
| 20462 | OPC_SwitchField, 7, 1, // 4839: switch Inst[7] { |
| 20463 | 0, 247, 1, // 4842: case 0x0: { |
| 20464 | OPC_SwitchField, 4, 3, // 4845: switch Inst[6:4] { |
| 20465 | 0, 47, // 4848: case 0x0: { |
| 20466 | OPC_SwitchField, 23, 1, // 4850: switch Inst[23] { |
| 20467 | 0, 11, // 4853: case 0x0: { |
| 20468 | OPC_CheckPredicate, 9, // 4855: check predicate 9 |
| 20469 | OPC_CheckField, 12, 4, 15, // 4857: check Inst[15:12] == 0xf |
| 20470 | OPC_Decode, 209, 31, 230, 2, // 4861: decode to t2ASRrr using decoder 358 |
| 20471 | // 4861: } |
| 20472 | 1, 0, // 4866: case 0x1: { |
| 20473 | OPC_SwitchField, 20, 1, // 4868: switch Inst[20] { |
| 20474 | 0, 11, // 4871: case 0x0: { |
| 20475 | OPC_CheckPredicate, 52, // 4873: check predicate 52 |
| 20476 | OPC_CheckField, 12, 4, 15, // 4875: check Inst[15:12] == 0xf |
| 20477 | OPC_Decode, 222, 33, 175, 3, // 4879: decode to t2SSUB8 using decoder 431 |
| 20478 | // 4879: } |
| 20479 | 1, 0, // 4884: case 0x1: { |
| 20480 | OPC_CheckPredicate, 52, // 4886: check predicate 52 |
| 20481 | OPC_CheckField, 12, 4, 15, // 4888: check Inst[15:12] == 0xf |
| 20482 | OPC_Decode, 221, 33, 175, 3, // 4892: decode to t2SSUB16 using decoder 431 |
| 20483 | // 4892: } |
| 20484 | // 4892: } // switch Inst[20] |
| 20485 | // 4892: } |
| 20486 | // 4892: } // switch Inst[23] |
| 20487 | // 4892: } |
| 20488 | 1, 37, // 4897: case 0x1: { |
| 20489 | OPC_SwitchField, 20, 1, // 4899: switch Inst[20] { |
| 20490 | 0, 15, // 4902: case 0x0: { |
| 20491 | OPC_CheckPredicate, 52, // 4904: check predicate 52 |
| 20492 | OPC_CheckField, 23, 1, 1, // 4906: check Inst[23] == 0x1 |
| 20493 | OPC_CheckField, 12, 4, 15, // 4910: check Inst[15:12] == 0xf |
| 20494 | OPC_Decode, 144, 33, 175, 3, // 4914: decode to t2QSUB8 using decoder 431 |
| 20495 | // 4914: } |
| 20496 | 1, 0, // 4919: case 0x1: { |
| 20497 | OPC_CheckPredicate, 52, // 4921: check predicate 52 |
| 20498 | OPC_CheckField, 23, 1, 1, // 4923: check Inst[23] == 0x1 |
| 20499 | OPC_CheckField, 12, 4, 15, // 4927: check Inst[15:12] == 0xf |
| 20500 | OPC_Decode, 143, 33, 175, 3, // 4931: decode to t2QSUB16 using decoder 431 |
| 20501 | // 4931: } |
| 20502 | // 4931: } // switch Inst[20] |
| 20503 | // 4931: } |
| 20504 | 2, 37, // 4936: case 0x2: { |
| 20505 | OPC_SwitchField, 20, 1, // 4938: switch Inst[20] { |
| 20506 | 0, 15, // 4941: case 0x0: { |
| 20507 | OPC_CheckPredicate, 52, // 4943: check predicate 52 |
| 20508 | OPC_CheckField, 23, 1, 1, // 4945: check Inst[23] == 0x1 |
| 20509 | OPC_CheckField, 12, 4, 15, // 4949: check Inst[15:12] == 0xf |
| 20510 | OPC_Decode, 176, 33, 175, 3, // 4953: decode to t2SHSUB8 using decoder 431 |
| 20511 | // 4953: } |
| 20512 | 1, 0, // 4958: case 0x1: { |
| 20513 | OPC_CheckPredicate, 52, // 4960: check predicate 52 |
| 20514 | OPC_CheckField, 23, 1, 1, // 4962: check Inst[23] == 0x1 |
| 20515 | OPC_CheckField, 12, 4, 15, // 4966: check Inst[15:12] == 0xf |
| 20516 | OPC_Decode, 175, 33, 175, 3, // 4970: decode to t2SHSUB16 using decoder 431 |
| 20517 | // 4970: } |
| 20518 | // 4970: } // switch Inst[20] |
| 20519 | // 4970: } |
| 20520 | 4, 37, // 4975: case 0x4: { |
| 20521 | OPC_SwitchField, 20, 1, // 4977: switch Inst[20] { |
| 20522 | 0, 15, // 4980: case 0x0: { |
| 20523 | OPC_CheckPredicate, 52, // 4982: check predicate 52 |
| 20524 | OPC_CheckField, 23, 1, 1, // 4984: check Inst[23] == 0x1 |
| 20525 | OPC_CheckField, 12, 4, 15, // 4988: check Inst[15:12] == 0xf |
| 20526 | OPC_Decode, 200, 34, 175, 3, // 4992: decode to t2USUB8 using decoder 431 |
| 20527 | // 4992: } |
| 20528 | 1, 0, // 4997: case 0x1: { |
| 20529 | OPC_CheckPredicate, 52, // 4999: check predicate 52 |
| 20530 | OPC_CheckField, 23, 1, 1, // 5001: check Inst[23] == 0x1 |
| 20531 | OPC_CheckField, 12, 4, 15, // 5005: check Inst[15:12] == 0xf |
| 20532 | OPC_Decode, 199, 34, 175, 3, // 5009: decode to t2USUB16 using decoder 431 |
| 20533 | // 5009: } |
| 20534 | // 5009: } // switch Inst[20] |
| 20535 | // 5009: } |
| 20536 | 5, 37, // 5014: case 0x5: { |
| 20537 | OPC_SwitchField, 20, 1, // 5016: switch Inst[20] { |
| 20538 | 0, 15, // 5019: case 0x0: { |
| 20539 | OPC_CheckPredicate, 52, // 5021: check predicate 52 |
| 20540 | OPC_CheckField, 23, 1, 1, // 5023: check Inst[23] == 0x1 |
| 20541 | OPC_CheckField, 12, 4, 15, // 5027: check Inst[15:12] == 0xf |
| 20542 | OPC_Decode, 193, 34, 175, 3, // 5031: decode to t2UQSUB8 using decoder 431 |
| 20543 | // 5031: } |
| 20544 | 1, 0, // 5036: case 0x1: { |
| 20545 | OPC_CheckPredicate, 52, // 5038: check predicate 52 |
| 20546 | OPC_CheckField, 23, 1, 1, // 5040: check Inst[23] == 0x1 |
| 20547 | OPC_CheckField, 12, 4, 15, // 5044: check Inst[15:12] == 0xf |
| 20548 | OPC_Decode, 192, 34, 175, 3, // 5048: decode to t2UQSUB16 using decoder 431 |
| 20549 | // 5048: } |
| 20550 | // 5048: } // switch Inst[20] |
| 20551 | // 5048: } |
| 20552 | 6, 0, // 5053: case 0x6: { |
| 20553 | OPC_SwitchField, 20, 1, // 5055: switch Inst[20] { |
| 20554 | 0, 15, // 5058: case 0x0: { |
| 20555 | OPC_CheckPredicate, 52, // 5060: check predicate 52 |
| 20556 | OPC_CheckField, 23, 1, 1, // 5062: check Inst[23] == 0x1 |
| 20557 | OPC_CheckField, 12, 4, 15, // 5066: check Inst[15:12] == 0xf |
| 20558 | OPC_Decode, 184, 34, 175, 3, // 5070: decode to t2UHSUB8 using decoder 431 |
| 20559 | // 5070: } |
| 20560 | 1, 0, // 5075: case 0x1: { |
| 20561 | OPC_CheckPredicate, 52, // 5077: check predicate 52 |
| 20562 | OPC_CheckField, 23, 1, 1, // 5079: check Inst[23] == 0x1 |
| 20563 | OPC_CheckField, 12, 4, 15, // 5083: check Inst[15:12] == 0xf |
| 20564 | OPC_Decode, 183, 34, 175, 3, // 5087: decode to t2UHSUB16 using decoder 431 |
| 20565 | // 5087: } |
| 20566 | // 5087: } // switch Inst[20] |
| 20567 | // 5087: } |
| 20568 | // 5087: } // switch Inst[6:4] |
| 20569 | // 5087: } |
| 20570 | 1, 0, // 5092: case 0x1: { |
| 20571 | OPC_SwitchField, 20, 1, // 5094: switch Inst[20] { |
| 20572 | 0, 73, // 5097: case 0x0: { |
| 20573 | OPC_SwitchField, 23, 1, // 5099: switch Inst[23] { |
| 20574 | 0, 24, // 5102: case 0x0: { |
| 20575 | OPC_CheckField, 12, 4, 15, // 5104: check Inst[15:12] == 0xf |
| 20576 | OPC_Scope, 11, // 5108: try { |
| 20577 | OPC_CheckField, 16, 4, 15, // 5110: check Inst[19:16] == 0xf |
| 20578 | OPC_CheckPredicate, 9, // 5114: check predicate 9 |
| 20579 | OPC_Decode, 157, 34, 176, 3, // 5116: decode to t2SXTB using decoder 432 |
| 20580 | // 5116: } else try { |
| 20581 | OPC_CheckPredicate, 50, // 5121: check predicate 50 |
| 20582 | OPC_Decode, 154, 34, 177, 3, // 5123: decode to t2SXTAB using decoder 433 |
| 20583 | // 5123: } |
| 20584 | // 5123: } |
| 20585 | 1, 0, // 5128: case 0x1: { |
| 20586 | OPC_SwitchField, 4, 3, // 5130: switch Inst[6:4] { |
| 20587 | 0, 11, // 5133: case 0x0: { |
| 20588 | OPC_CheckPredicate, 67, // 5135: check predicate 67 |
| 20589 | OPC_CheckField, 12, 4, 15, // 5137: check Inst[15:12] == 0xf |
| 20590 | OPC_Decode, 242, 31, 186, 3, // 5141: decode to t2CRC32B using decoder 442 |
| 20591 | // 5141: } |
| 20592 | 1, 11, // 5146: case 0x1: { |
| 20593 | OPC_CheckPredicate, 67, // 5148: check predicate 67 |
| 20594 | OPC_CheckField, 12, 4, 15, // 5150: check Inst[15:12] == 0xf |
| 20595 | OPC_Decode, 246, 31, 186, 3, // 5154: decode to t2CRC32H using decoder 442 |
| 20596 | // 5154: } |
| 20597 | 2, 0, // 5159: case 0x2: { |
| 20598 | OPC_CheckPredicate, 67, // 5161: check predicate 67 |
| 20599 | OPC_CheckField, 12, 4, 15, // 5163: check Inst[15:12] == 0xf |
| 20600 | OPC_Decode, 247, 31, 186, 3, // 5167: decode to t2CRC32W using decoder 442 |
| 20601 | // 5167: } |
| 20602 | // 5167: } // switch Inst[6:4] |
| 20603 | // 5167: } |
| 20604 | // 5167: } // switch Inst[23] |
| 20605 | // 5167: } |
| 20606 | 1, 0, // 5172: case 0x1: { |
| 20607 | OPC_SwitchField, 23, 1, // 5174: switch Inst[23] { |
| 20608 | 0, 24, // 5177: case 0x0: { |
| 20609 | OPC_CheckField, 12, 4, 15, // 5179: check Inst[15:12] == 0xf |
| 20610 | OPC_Scope, 11, // 5183: try { |
| 20611 | OPC_CheckField, 16, 4, 15, // 5185: check Inst[19:16] == 0xf |
| 20612 | OPC_CheckPredicate, 9, // 5189: check predicate 9 |
| 20613 | OPC_Decode, 204, 34, 176, 3, // 5191: decode to t2UXTB using decoder 432 |
| 20614 | // 5191: } else try { |
| 20615 | OPC_CheckPredicate, 50, // 5196: check predicate 50 |
| 20616 | OPC_Decode, 201, 34, 177, 3, // 5198: decode to t2UXTAB using decoder 433 |
| 20617 | // 5198: } |
| 20618 | // 5198: } |
| 20619 | 1, 0, // 5203: case 0x1: { |
| 20620 | OPC_SwitchField, 4, 3, // 5205: switch Inst[6:4] { |
| 20621 | 0, 11, // 5208: case 0x0: { |
| 20622 | OPC_CheckPredicate, 67, // 5210: check predicate 67 |
| 20623 | OPC_CheckField, 12, 4, 15, // 5212: check Inst[15:12] == 0xf |
| 20624 | OPC_Decode, 243, 31, 186, 3, // 5216: decode to t2CRC32CB using decoder 442 |
| 20625 | // 5216: } |
| 20626 | 1, 11, // 5221: case 0x1: { |
| 20627 | OPC_CheckPredicate, 67, // 5223: check predicate 67 |
| 20628 | OPC_CheckField, 12, 4, 15, // 5225: check Inst[15:12] == 0xf |
| 20629 | OPC_Decode, 244, 31, 186, 3, // 5229: decode to t2CRC32CH using decoder 442 |
| 20630 | // 5229: } |
| 20631 | 2, 0, // 5234: case 0x2: { |
| 20632 | OPC_CheckPredicate, 67, // 5236: check predicate 67 |
| 20633 | OPC_CheckField, 12, 4, 15, // 5238: check Inst[15:12] == 0xf |
| 20634 | OPC_Decode, 245, 31, 186, 3, // 5242: decode to t2CRC32CW using decoder 442 |
| 20635 | // 5242: } |
| 20636 | // 5242: } // switch Inst[6:4] |
| 20637 | // 5242: } |
| 20638 | // 5242: } // switch Inst[23] |
| 20639 | // 5242: } |
| 20640 | // 5242: } // switch Inst[20] |
| 20641 | // 5242: } |
| 20642 | // 5242: } // switch Inst[7] |
| 20643 | // 5242: } |
| 20644 | 3, 0, // 5247: case 0x3: { |
| 20645 | OPC_SwitchField, 4, 4, // 5249: switch Inst[7:4] { |
| 20646 | 0, 78, // 5252: case 0x0: { |
| 20647 | OPC_SwitchField, 20, 1, // 5254: switch Inst[20] { |
| 20648 | 0, 34, // 5257: case 0x0: { |
| 20649 | OPC_SwitchField, 23, 1, // 5259: switch Inst[23] { |
| 20650 | 0, 20, // 5262: case 0x0: { |
| 20651 | OPC_Scope, 11, // 5264: try { |
| 20652 | OPC_CheckField, 12, 4, 15, // 5266: check Inst[15:12] == 0xf |
| 20653 | OPC_CheckPredicate, 52, // 5270: check predicate 52 |
| 20654 | OPC_Decode, 212, 33, 175, 3, // 5272: decode to t2SMUSD using decoder 431 |
| 20655 | // 5272: } else try { |
| 20656 | OPC_CheckPredicate, 52, // 5277: check predicate 52 |
| 20657 | OPC_Decode, 193, 33, 180, 3, // 5279: decode to t2SMLSD using decoder 436 |
| 20658 | // 5279: } |
| 20659 | // 5279: } |
| 20660 | 1, 0, // 5284: case 0x1: { |
| 20661 | OPC_CheckPredicate, 9, // 5286: check predicate 9 |
| 20662 | OPC_Decode, 182, 33, 187, 3, // 5288: decode to t2SMLAL using decoder 443 |
| 20663 | // 5288: } |
| 20664 | // 5288: } // switch Inst[23] |
| 20665 | // 5288: } |
| 20666 | 1, 0, // 5293: case 0x1: { |
| 20667 | OPC_CheckField, 23, 1, 0, // 5295: check Inst[23] == 0x0 |
| 20668 | OPC_Scope, 11, // 5299: try { |
| 20669 | OPC_CheckField, 8, 4, 15, // 5301: check Inst[11:8] == 0xf |
| 20670 | OPC_CheckPredicate, 68, // 5305: check predicate 68 |
| 20671 | OPC_Decode, 212, 31, 188, 3, // 5307: decode to t2AUTG using decoder 444 |
| 20672 | OPC_Scope, 11, // 5312: } else try { |
| 20673 | OPC_CheckField, 12, 4, 15, // 5314: check Inst[15:12] == 0xf |
| 20674 | OPC_CheckPredicate, 52, // 5318: check predicate 52 |
| 20675 | OPC_Decode, 201, 33, 175, 3, // 5320: decode to t2SMMUL using decoder 431 |
| 20676 | // 5320: } else try { |
| 20677 | OPC_CheckPredicate, 52, // 5325: check predicate 52 |
| 20678 | OPC_Decode, 197, 33, 180, 3, // 5327: decode to t2SMMLA using decoder 436 |
| 20679 | // 5327: } |
| 20680 | // 5327: } |
| 20681 | // 5327: } // switch Inst[20] |
| 20682 | // 5327: } |
| 20683 | 1, 68, // 5332: case 0x1: { |
| 20684 | OPC_SwitchField, 20, 1, // 5334: switch Inst[20] { |
| 20685 | 0, 24, // 5337: case 0x0: { |
| 20686 | OPC_CheckField, 23, 1, 0, // 5339: check Inst[23] == 0x0 |
| 20687 | OPC_Scope, 11, // 5343: try { |
| 20688 | OPC_CheckField, 12, 4, 15, // 5345: check Inst[15:12] == 0xf |
| 20689 | OPC_CheckPredicate, 52, // 5349: check predicate 52 |
| 20690 | OPC_Decode, 213, 33, 175, 3, // 5351: decode to t2SMUSDX using decoder 431 |
| 20691 | // 5351: } else try { |
| 20692 | OPC_CheckPredicate, 52, // 5356: check predicate 52 |
| 20693 | OPC_Decode, 194, 33, 180, 3, // 5358: decode to t2SMLSDX using decoder 436 |
| 20694 | // 5358: } |
| 20695 | // 5358: } |
| 20696 | 1, 0, // 5363: case 0x1: { |
| 20697 | OPC_CheckField, 23, 1, 0, // 5365: check Inst[23] == 0x0 |
| 20698 | OPC_Scope, 11, // 5369: try { |
| 20699 | OPC_CheckField, 8, 4, 15, // 5371: check Inst[11:8] == 0xf |
| 20700 | OPC_CheckPredicate, 68, // 5375: check predicate 68 |
| 20701 | OPC_Decode, 225, 31, 189, 3, // 5377: decode to t2BXAUT using decoder 445 |
| 20702 | OPC_Scope, 11, // 5382: } else try { |
| 20703 | OPC_CheckField, 12, 4, 15, // 5384: check Inst[15:12] == 0xf |
| 20704 | OPC_CheckPredicate, 52, // 5388: check predicate 52 |
| 20705 | OPC_Decode, 202, 33, 175, 3, // 5390: decode to t2SMMULR using decoder 431 |
| 20706 | // 5390: } else try { |
| 20707 | OPC_CheckPredicate, 52, // 5395: check predicate 52 |
| 20708 | OPC_Decode, 198, 33, 180, 3, // 5397: decode to t2SMMLAR using decoder 436 |
| 20709 | // 5397: } |
| 20710 | // 5397: } |
| 20711 | // 5397: } // switch Inst[20] |
| 20712 | // 5397: } |
| 20713 | 8, 15, // 5402: case 0x8: { |
| 20714 | OPC_CheckPredicate, 52, // 5404: check predicate 52 |
| 20715 | OPC_CheckField, 23, 1, 1, // 5406: check Inst[23] == 0x1 |
| 20716 | OPC_CheckField, 20, 1, 0, // 5410: check Inst[20] == 0x0 |
| 20717 | OPC_Decode, 183, 33, 187, 3, // 5414: decode to t2SMLALBB using decoder 443 |
| 20718 | // 5414: } |
| 20719 | 9, 15, // 5419: case 0x9: { |
| 20720 | OPC_CheckPredicate, 52, // 5421: check predicate 52 |
| 20721 | OPC_CheckField, 23, 1, 1, // 5423: check Inst[23] == 0x1 |
| 20722 | OPC_CheckField, 20, 1, 0, // 5427: check Inst[20] == 0x0 |
| 20723 | OPC_Decode, 184, 33, 187, 3, // 5431: decode to t2SMLALBT using decoder 443 |
| 20724 | // 5431: } |
| 20725 | 10, 15, // 5436: case 0xa: { |
| 20726 | OPC_CheckPredicate, 52, // 5438: check predicate 52 |
| 20727 | OPC_CheckField, 23, 1, 1, // 5440: check Inst[23] == 0x1 |
| 20728 | OPC_CheckField, 20, 1, 0, // 5444: check Inst[20] == 0x0 |
| 20729 | OPC_Decode, 187, 33, 187, 3, // 5448: decode to t2SMLALTB using decoder 443 |
| 20730 | // 5448: } |
| 20731 | 11, 15, // 5453: case 0xb: { |
| 20732 | OPC_CheckPredicate, 52, // 5455: check predicate 52 |
| 20733 | OPC_CheckField, 23, 1, 1, // 5457: check Inst[23] == 0x1 |
| 20734 | OPC_CheckField, 20, 1, 0, // 5461: check Inst[20] == 0x0 |
| 20735 | OPC_Decode, 188, 33, 187, 3, // 5465: decode to t2SMLALTT using decoder 443 |
| 20736 | // 5465: } |
| 20737 | 12, 29, // 5470: case 0xc: { |
| 20738 | OPC_SwitchField, 20, 1, // 5472: switch Inst[20] { |
| 20739 | 0, 11, // 5475: case 0x0: { |
| 20740 | OPC_CheckPredicate, 52, // 5477: check predicate 52 |
| 20741 | OPC_CheckField, 23, 1, 1, // 5479: check Inst[23] == 0x1 |
| 20742 | OPC_Decode, 185, 33, 187, 3, // 5483: decode to t2SMLALD using decoder 443 |
| 20743 | // 5483: } |
| 20744 | 1, 0, // 5488: case 0x1: { |
| 20745 | OPC_CheckPredicate, 52, // 5490: check predicate 52 |
| 20746 | OPC_CheckField, 23, 1, 1, // 5492: check Inst[23] == 0x1 |
| 20747 | OPC_Decode, 195, 33, 187, 3, // 5496: decode to t2SMLSLD using decoder 443 |
| 20748 | // 5496: } |
| 20749 | // 5496: } // switch Inst[20] |
| 20750 | // 5496: } |
| 20751 | 13, 0, // 5501: case 0xd: { |
| 20752 | OPC_SwitchField, 20, 1, // 5503: switch Inst[20] { |
| 20753 | 0, 11, // 5506: case 0x0: { |
| 20754 | OPC_CheckPredicate, 52, // 5508: check predicate 52 |
| 20755 | OPC_CheckField, 23, 1, 1, // 5510: check Inst[23] == 0x1 |
| 20756 | OPC_Decode, 186, 33, 187, 3, // 5514: decode to t2SMLALDX using decoder 443 |
| 20757 | // 5514: } |
| 20758 | 1, 0, // 5519: case 0x1: { |
| 20759 | OPC_CheckPredicate, 52, // 5521: check predicate 52 |
| 20760 | OPC_CheckField, 23, 1, 1, // 5523: check Inst[23] == 0x1 |
| 20761 | OPC_Decode, 196, 33, 187, 3, // 5527: decode to t2SMLSLDX using decoder 443 |
| 20762 | // 5527: } |
| 20763 | // 5527: } // switch Inst[20] |
| 20764 | // 5527: } |
| 20765 | // 5527: } // switch Inst[7:4] |
| 20766 | // 5527: } |
| 20767 | // 5527: } // switch Inst[26:24] |
| 20768 | // 5527: } |
| 20769 | 3, 0, // 5532: case 0x3: { |
| 20770 | OPC_SwitchField, 4, 4, // 5534: switch Inst[7:4] { |
| 20771 | 0, 95, // 5537: case 0x0: { |
| 20772 | OPC_SwitchField, 23, 4, // 5539: switch Inst[26:23] { |
| 20773 | 4, 11, // 5542: case 0x4: { |
| 20774 | OPC_CheckPredicate, 9, // 5544: check predicate 9 |
| 20775 | OPC_CheckField, 12, 4, 15, // 5546: check Inst[15:12] == 0xf |
| 20776 | OPC_Decode, 154, 33, 230, 2, // 5550: decode to t2RORrr using decoder 358 |
| 20777 | // 5550: } |
| 20778 | 5, 15, // 5555: case 0x5: { |
| 20779 | OPC_CheckPredicate, 52, // 5557: check predicate 52 |
| 20780 | OPC_CheckField, 20, 1, 0, // 5559: check Inst[20] == 0x0 |
| 20781 | OPC_CheckField, 12, 4, 15, // 5563: check Inst[15:12] == 0xf |
| 20782 | OPC_Decode, 220, 33, 175, 3, // 5567: decode to t2SSAX using decoder 431 |
| 20783 | // 5567: } |
| 20784 | 6, 47, // 5572: case 0x6: { |
| 20785 | OPC_SwitchField, 20, 1, // 5574: switch Inst[20] { |
| 20786 | 0, 20, // 5577: case 0x0: { |
| 20787 | OPC_Scope, 11, // 5579: try { |
| 20788 | OPC_CheckField, 12, 4, 15, // 5581: check Inst[15:12] == 0xf |
| 20789 | OPC_CheckPredicate, 68, // 5585: check predicate 68 |
| 20790 | OPC_Decode, 249, 32, 190, 3, // 5587: decode to t2PACG using decoder 446 |
| 20791 | // 5587: } else try { |
| 20792 | OPC_CheckPredicate, 52, // 5592: check predicate 52 |
| 20793 | OPC_Decode, 199, 33, 180, 3, // 5594: decode to t2SMMLS using decoder 436 |
| 20794 | // 5594: } |
| 20795 | // 5594: } |
| 20796 | 1, 0, // 5599: case 0x1: { |
| 20797 | OPC_Scope, 11, // 5601: try { |
| 20798 | OPC_CheckField, 12, 4, 15, // 5603: check Inst[15:12] == 0xf |
| 20799 | OPC_CheckPredicate, 52, // 5607: check predicate 52 |
| 20800 | OPC_Decode, 194, 34, 175, 3, // 5609: decode to t2USAD8 using decoder 431 |
| 20801 | // 5609: } else try { |
| 20802 | OPC_CheckPredicate, 52, // 5614: check predicate 52 |
| 20803 | OPC_Decode, 195, 34, 180, 3, // 5616: decode to t2USADA8 using decoder 436 |
| 20804 | // 5616: } |
| 20805 | // 5616: } |
| 20806 | // 5616: } // switch Inst[20] |
| 20807 | // 5616: } |
| 20808 | 7, 0, // 5621: case 0x7: { |
| 20809 | OPC_CheckPredicate, 9, // 5623: check predicate 9 |
| 20810 | OPC_CheckField, 20, 1, 0, // 5625: check Inst[20] == 0x0 |
| 20811 | OPC_Decode, 186, 34, 187, 3, // 5629: decode to t2UMLAL using decoder 443 |
| 20812 | // 5629: } |
| 20813 | // 5629: } // switch Inst[26:23] |
| 20814 | // 5629: } |
| 20815 | 1, 33, // 5634: case 0x1: { |
| 20816 | OPC_SwitchField, 23, 4, // 5636: switch Inst[26:23] { |
| 20817 | 5, 15, // 5639: case 0x5: { |
| 20818 | OPC_CheckPredicate, 52, // 5641: check predicate 52 |
| 20819 | OPC_CheckField, 20, 1, 0, // 5643: check Inst[20] == 0x0 |
| 20820 | OPC_CheckField, 12, 4, 15, // 5647: check Inst[15:12] == 0xf |
| 20821 | OPC_Decode, 141, 33, 175, 3, // 5651: decode to t2QSAX using decoder 431 |
| 20822 | // 5651: } |
| 20823 | 6, 0, // 5656: case 0x6: { |
| 20824 | OPC_CheckPredicate, 52, // 5658: check predicate 52 |
| 20825 | OPC_CheckField, 20, 1, 0, // 5660: check Inst[20] == 0x0 |
| 20826 | OPC_Decode, 200, 33, 180, 3, // 5664: decode to t2SMMLSR using decoder 436 |
| 20827 | // 5664: } |
| 20828 | // 5664: } // switch Inst[26:23] |
| 20829 | // 5664: } |
| 20830 | 2, 19, // 5669: case 0x2: { |
| 20831 | OPC_CheckPredicate, 52, // 5671: check predicate 52 |
| 20832 | OPC_CheckField, 23, 4, 5, // 5673: check Inst[26:23] == 0x5 |
| 20833 | OPC_CheckField, 20, 1, 0, // 5677: check Inst[20] == 0x0 |
| 20834 | OPC_CheckField, 12, 4, 15, // 5681: check Inst[15:12] == 0xf |
| 20835 | OPC_Decode, 174, 33, 175, 3, // 5685: decode to t2SHSAX using decoder 431 |
| 20836 | // 5685: } |
| 20837 | 4, 19, // 5690: case 0x4: { |
| 20838 | OPC_CheckPredicate, 52, // 5692: check predicate 52 |
| 20839 | OPC_CheckField, 23, 4, 5, // 5694: check Inst[26:23] == 0x5 |
| 20840 | OPC_CheckField, 20, 1, 0, // 5698: check Inst[20] == 0x0 |
| 20841 | OPC_CheckField, 12, 4, 15, // 5702: check Inst[15:12] == 0xf |
| 20842 | OPC_Decode, 198, 34, 175, 3, // 5706: decode to t2USAX using decoder 431 |
| 20843 | // 5706: } |
| 20844 | 5, 19, // 5711: case 0x5: { |
| 20845 | OPC_CheckPredicate, 52, // 5713: check predicate 52 |
| 20846 | OPC_CheckField, 23, 4, 5, // 5715: check Inst[26:23] == 0x5 |
| 20847 | OPC_CheckField, 20, 1, 0, // 5719: check Inst[20] == 0x0 |
| 20848 | OPC_CheckField, 12, 4, 15, // 5723: check Inst[15:12] == 0xf |
| 20849 | OPC_Decode, 191, 34, 175, 3, // 5727: decode to t2UQSAX using decoder 431 |
| 20850 | // 5727: } |
| 20851 | 6, 0, // 5732: case 0x6: { |
| 20852 | OPC_SwitchField, 23, 4, // 5734: switch Inst[26:23] { |
| 20853 | 5, 15, // 5737: case 0x5: { |
| 20854 | OPC_CheckPredicate, 52, // 5739: check predicate 52 |
| 20855 | OPC_CheckField, 20, 1, 0, // 5741: check Inst[20] == 0x0 |
| 20856 | OPC_CheckField, 12, 4, 15, // 5745: check Inst[15:12] == 0xf |
| 20857 | OPC_Decode, 182, 34, 175, 3, // 5749: decode to t2UHSAX using decoder 431 |
| 20858 | // 5749: } |
| 20859 | 7, 0, // 5754: case 0x7: { |
| 20860 | OPC_CheckPredicate, 52, // 5756: check predicate 52 |
| 20861 | OPC_CheckField, 20, 1, 0, // 5758: check Inst[20] == 0x0 |
| 20862 | OPC_Decode, 185, 34, 187, 3, // 5762: decode to t2UMAAL using decoder 443 |
| 20863 | // 5762: } |
| 20864 | // 5762: } // switch Inst[26:23] |
| 20865 | // 5762: } |
| 20866 | // 5762: } // switch Inst[7:4] |
| 20867 | // 5762: } |
| 20868 | // 5762: } // switch Inst[22:21] |
| 20869 | // 5762: } |
| 20870 | // 5762: } // switch Inst[31:27] |
| 20871 | }; |
| 20872 | static const uint8_t DecoderTableThumb2CDE32[565] = { |
| 20873 | OPC_SwitchField, 25, 7, // 0: switch Inst[31:25] { |
| 20874 | 118, 175, 1, // 3: case 0x76: { |
| 20875 | OPC_SwitchField, 6, 1, // 6: switch Inst[6] { |
| 20876 | 0, 91, // 9: case 0x0: { |
| 20877 | OPC_SwitchField, 23, 2, // 11: switch Inst[24:23] { |
| 20878 | 0, 29, // 14: case 0x0: { |
| 20879 | OPC_SwitchField, 20, 2, // 16: switch Inst[21:20] { |
| 20880 | 2, 11, // 19: case 0x2: { |
| 20881 | OPC_CheckPredicate, 69, // 21: check predicate 69 |
| 20882 | OPC_CheckField, 11, 1, 0, // 23: check Inst[11] == 0x0 |
| 20883 | OPC_Decode, 219, 6, 191, 3, // 27: decode to CDE_VCX1_fpsp using decoder 447 |
| 20884 | // 27: } |
| 20885 | 3, 0, // 32: case 0x3: { |
| 20886 | OPC_CheckPredicate, 69, // 34: check predicate 69 |
| 20887 | OPC_CheckField, 11, 1, 0, // 36: check Inst[11] == 0x0 |
| 20888 | OPC_Decode, 225, 6, 192, 3, // 40: decode to CDE_VCX2_fpsp using decoder 448 |
| 20889 | // 40: } |
| 20890 | // 40: } // switch Inst[21:20] |
| 20891 | // 40: } |
| 20892 | 1, 11, // 45: case 0x1: { |
| 20893 | OPC_CheckPredicate, 69, // 47: check predicate 69 |
| 20894 | OPC_CheckField, 11, 1, 0, // 49: check Inst[11] == 0x0 |
| 20895 | OPC_Decode, 231, 6, 193, 3, // 53: decode to CDE_VCX3_fpsp using decoder 449 |
| 20896 | // 53: } |
| 20897 | 2, 29, // 58: case 0x2: { |
| 20898 | OPC_SwitchField, 20, 2, // 60: switch Inst[21:20] { |
| 20899 | 2, 11, // 63: case 0x2: { |
| 20900 | OPC_CheckPredicate, 69, // 65: check predicate 69 |
| 20901 | OPC_CheckField, 11, 1, 0, // 67: check Inst[11] == 0x0 |
| 20902 | OPC_Decode, 218, 6, 194, 3, // 71: decode to CDE_VCX1_fpdp using decoder 450 |
| 20903 | // 71: } |
| 20904 | 3, 0, // 76: case 0x3: { |
| 20905 | OPC_CheckPredicate, 69, // 78: check predicate 69 |
| 20906 | OPC_CheckField, 11, 1, 0, // 80: check Inst[11] == 0x0 |
| 20907 | OPC_Decode, 224, 6, 195, 3, // 84: decode to CDE_VCX2_fpdp using decoder 451 |
| 20908 | // 84: } |
| 20909 | // 84: } // switch Inst[21:20] |
| 20910 | // 84: } |
| 20911 | 3, 0, // 89: case 0x3: { |
| 20912 | OPC_CheckPredicate, 69, // 91: check predicate 69 |
| 20913 | OPC_CheckField, 11, 1, 0, // 93: check Inst[11] == 0x0 |
| 20914 | OPC_Decode, 230, 6, 196, 3, // 97: decode to CDE_VCX3_fpdp using decoder 452 |
| 20915 | // 97: } |
| 20916 | // 97: } // switch Inst[24:23] |
| 20917 | // 97: } |
| 20918 | 1, 0, // 102: case 0x1: { |
| 20919 | OPC_SwitchField, 23, 1, // 104: switch Inst[23] { |
| 20920 | 0, 45, // 107: case 0x0: { |
| 20921 | OPC_SwitchField, 20, 2, // 109: switch Inst[21:20] { |
| 20922 | 2, 17, // 112: case 0x2: { |
| 20923 | OPC_CheckPredicate, 70, // 114: check predicate 70 |
| 20924 | OPC_CheckField, 11, 2, 0, // 116: check Inst[12:11] == 0x0 |
| 20925 | OPC_SoftFail, 128, 128, 128, 2, 0, // 120: softfail pos=0x00400000 neg=0x00000000 |
| 20926 | OPC_Decode, 220, 6, 197, 3, // 126: decode to CDE_VCX1_vec using decoder 453 |
| 20927 | // 126: } |
| 20928 | 3, 0, // 131: case 0x3: { |
| 20929 | OPC_CheckPredicate, 70, // 133: check predicate 70 |
| 20930 | OPC_CheckField, 11, 2, 0, // 135: check Inst[12:11] == 0x0 |
| 20931 | OPC_CheckField, 0, 1, 0, // 139: check Inst[0] == 0x0 |
| 20932 | OPC_SoftFail, 160, 128, 128, 2, 0, // 143: softfail pos=0x00400020 neg=0x00000000 |
| 20933 | OPC_Decode, 226, 6, 198, 3, // 149: decode to CDE_VCX2_vec using decoder 454 |
| 20934 | // 149: } |
| 20935 | // 149: } // switch Inst[21:20] |
| 20936 | // 149: } |
| 20937 | 1, 0, // 154: case 0x1: { |
| 20938 | OPC_CheckPredicate, 70, // 156: check predicate 70 |
| 20939 | OPC_CheckField, 16, 1, 0, // 158: check Inst[16] == 0x0 |
| 20940 | OPC_CheckField, 11, 2, 0, // 162: check Inst[12:11] == 0x0 |
| 20941 | OPC_CheckField, 0, 1, 0, // 166: check Inst[0] == 0x0 |
| 20942 | OPC_SoftFail, 160, 129, 128, 2, 0, // 170: softfail pos=0x004000a0 neg=0x00000000 |
| 20943 | OPC_Decode, 232, 6, 199, 3, // 176: decode to CDE_VCX3_vec using decoder 455 |
| 20944 | // 176: } |
| 20945 | // 176: } // switch Inst[23] |
| 20946 | // 176: } |
| 20947 | // 176: } // switch Inst[6] |
| 20948 | // 176: } |
| 20949 | 119, 101, // 181: case 0x77: { |
| 20950 | OPC_SwitchField, 6, 1, // 183: switch Inst[6] { |
| 20951 | 0, 47, // 186: case 0x0: { |
| 20952 | OPC_SwitchField, 23, 2, // 188: switch Inst[24:23] { |
| 20953 | 0, 29, // 191: case 0x0: { |
| 20954 | OPC_SwitchField, 22, 1, // 193: switch Inst[22] { |
| 20955 | 0, 11, // 196: case 0x0: { |
| 20956 | OPC_CheckPredicate, 71, // 198: check predicate 71 |
| 20957 | OPC_CheckField, 11, 1, 0, // 200: check Inst[11] == 0x0 |
| 20958 | OPC_Decode, 203, 6, 200, 3, // 204: decode to CDE_CX1 using decoder 456 |
| 20959 | // 204: } |
| 20960 | 1, 0, // 209: case 0x1: { |
| 20961 | OPC_CheckPredicate, 71, // 211: check predicate 71 |
| 20962 | OPC_CheckField, 11, 1, 0, // 213: check Inst[11] == 0x0 |
| 20963 | OPC_Decode, 207, 6, 201, 3, // 217: decode to CDE_CX2 using decoder 457 |
| 20964 | // 217: } |
| 20965 | // 217: } // switch Inst[22] |
| 20966 | // 217: } |
| 20967 | 1, 0, // 222: case 0x1: { |
| 20968 | OPC_CheckPredicate, 71, // 224: check predicate 71 |
| 20969 | OPC_CheckField, 11, 1, 0, // 226: check Inst[11] == 0x0 |
| 20970 | OPC_Decode, 211, 6, 202, 3, // 230: decode to CDE_CX3 using decoder 458 |
| 20971 | // 230: } |
| 20972 | // 230: } // switch Inst[24:23] |
| 20973 | // 230: } |
| 20974 | 1, 0, // 235: case 0x1: { |
| 20975 | OPC_SwitchField, 23, 2, // 237: switch Inst[24:23] { |
| 20976 | 0, 29, // 240: case 0x0: { |
| 20977 | OPC_SwitchField, 22, 1, // 242: switch Inst[22] { |
| 20978 | 0, 11, // 245: case 0x0: { |
| 20979 | OPC_CheckPredicate, 71, // 247: check predicate 71 |
| 20980 | OPC_CheckField, 11, 1, 0, // 249: check Inst[11] == 0x0 |
| 20981 | OPC_Decode, 205, 6, 203, 3, // 253: decode to CDE_CX1D using decoder 459 |
| 20982 | // 253: } |
| 20983 | 1, 0, // 258: case 0x1: { |
| 20984 | OPC_CheckPredicate, 71, // 260: check predicate 71 |
| 20985 | OPC_CheckField, 11, 1, 0, // 262: check Inst[11] == 0x0 |
| 20986 | OPC_Decode, 209, 6, 204, 3, // 266: decode to CDE_CX2D using decoder 460 |
| 20987 | // 266: } |
| 20988 | // 266: } // switch Inst[22] |
| 20989 | // 266: } |
| 20990 | 1, 0, // 271: case 0x1: { |
| 20991 | OPC_CheckPredicate, 71, // 273: check predicate 71 |
| 20992 | OPC_CheckField, 11, 1, 0, // 275: check Inst[11] == 0x0 |
| 20993 | OPC_Decode, 213, 6, 205, 3, // 279: decode to CDE_CX3D using decoder 461 |
| 20994 | // 279: } |
| 20995 | // 279: } // switch Inst[24:23] |
| 20996 | // 279: } |
| 20997 | // 279: } // switch Inst[6] |
| 20998 | // 279: } |
| 20999 | 126, 175, 1, // 284: case 0x7e: { |
| 21000 | OPC_SwitchField, 6, 1, // 287: switch Inst[6] { |
| 21001 | 0, 91, // 290: case 0x0: { |
| 21002 | OPC_SwitchField, 23, 2, // 292: switch Inst[24:23] { |
| 21003 | 0, 29, // 295: case 0x0: { |
| 21004 | OPC_SwitchField, 20, 2, // 297: switch Inst[21:20] { |
| 21005 | 2, 11, // 300: case 0x2: { |
| 21006 | OPC_CheckPredicate, 69, // 302: check predicate 69 |
| 21007 | OPC_CheckField, 11, 1, 0, // 304: check Inst[11] == 0x0 |
| 21008 | OPC_Decode, 216, 6, 206, 3, // 308: decode to CDE_VCX1A_fpsp using decoder 462 |
| 21009 | // 308: } |
| 21010 | 3, 0, // 313: case 0x3: { |
| 21011 | OPC_CheckPredicate, 69, // 315: check predicate 69 |
| 21012 | OPC_CheckField, 11, 1, 0, // 317: check Inst[11] == 0x0 |
| 21013 | OPC_Decode, 222, 6, 207, 3, // 321: decode to CDE_VCX2A_fpsp using decoder 463 |
| 21014 | // 321: } |
| 21015 | // 321: } // switch Inst[21:20] |
| 21016 | // 321: } |
| 21017 | 1, 11, // 326: case 0x1: { |
| 21018 | OPC_CheckPredicate, 69, // 328: check predicate 69 |
| 21019 | OPC_CheckField, 11, 1, 0, // 330: check Inst[11] == 0x0 |
| 21020 | OPC_Decode, 228, 6, 208, 3, // 334: decode to CDE_VCX3A_fpsp using decoder 464 |
| 21021 | // 334: } |
| 21022 | 2, 29, // 339: case 0x2: { |
| 21023 | OPC_SwitchField, 20, 2, // 341: switch Inst[21:20] { |
| 21024 | 2, 11, // 344: case 0x2: { |
| 21025 | OPC_CheckPredicate, 69, // 346: check predicate 69 |
| 21026 | OPC_CheckField, 11, 1, 0, // 348: check Inst[11] == 0x0 |
| 21027 | OPC_Decode, 215, 6, 209, 3, // 352: decode to CDE_VCX1A_fpdp using decoder 465 |
| 21028 | // 352: } |
| 21029 | 3, 0, // 357: case 0x3: { |
| 21030 | OPC_CheckPredicate, 69, // 359: check predicate 69 |
| 21031 | OPC_CheckField, 11, 1, 0, // 361: check Inst[11] == 0x0 |
| 21032 | OPC_Decode, 221, 6, 210, 3, // 365: decode to CDE_VCX2A_fpdp using decoder 466 |
| 21033 | // 365: } |
| 21034 | // 365: } // switch Inst[21:20] |
| 21035 | // 365: } |
| 21036 | 3, 0, // 370: case 0x3: { |
| 21037 | OPC_CheckPredicate, 69, // 372: check predicate 69 |
| 21038 | OPC_CheckField, 11, 1, 0, // 374: check Inst[11] == 0x0 |
| 21039 | OPC_Decode, 227, 6, 211, 3, // 378: decode to CDE_VCX3A_fpdp using decoder 467 |
| 21040 | // 378: } |
| 21041 | // 378: } // switch Inst[24:23] |
| 21042 | // 378: } |
| 21043 | 1, 0, // 383: case 0x1: { |
| 21044 | OPC_SwitchField, 23, 1, // 385: switch Inst[23] { |
| 21045 | 0, 45, // 388: case 0x0: { |
| 21046 | OPC_SwitchField, 20, 2, // 390: switch Inst[21:20] { |
| 21047 | 2, 17, // 393: case 0x2: { |
| 21048 | OPC_CheckPredicate, 70, // 395: check predicate 70 |
| 21049 | OPC_CheckField, 11, 2, 0, // 397: check Inst[12:11] == 0x0 |
| 21050 | OPC_SoftFail, 128, 128, 128, 2, 0, // 401: softfail pos=0x00400000 neg=0x00000000 |
| 21051 | OPC_Decode, 217, 6, 212, 3, // 407: decode to CDE_VCX1A_vec using decoder 468 |
| 21052 | // 407: } |
| 21053 | 3, 0, // 412: case 0x3: { |
| 21054 | OPC_CheckPredicate, 70, // 414: check predicate 70 |
| 21055 | OPC_CheckField, 11, 2, 0, // 416: check Inst[12:11] == 0x0 |
| 21056 | OPC_CheckField, 0, 1, 0, // 420: check Inst[0] == 0x0 |
| 21057 | OPC_SoftFail, 160, 128, 128, 2, 0, // 424: softfail pos=0x00400020 neg=0x00000000 |
| 21058 | OPC_Decode, 223, 6, 213, 3, // 430: decode to CDE_VCX2A_vec using decoder 469 |
| 21059 | // 430: } |
| 21060 | // 430: } // switch Inst[21:20] |
| 21061 | // 430: } |
| 21062 | 1, 0, // 435: case 0x1: { |
| 21063 | OPC_CheckPredicate, 70, // 437: check predicate 70 |
| 21064 | OPC_CheckField, 16, 1, 0, // 439: check Inst[16] == 0x0 |
| 21065 | OPC_CheckField, 11, 2, 0, // 443: check Inst[12:11] == 0x0 |
| 21066 | OPC_CheckField, 0, 1, 0, // 447: check Inst[0] == 0x0 |
| 21067 | OPC_SoftFail, 160, 129, 128, 2, 0, // 451: softfail pos=0x004000a0 neg=0x00000000 |
| 21068 | OPC_Decode, 229, 6, 214, 3, // 457: decode to CDE_VCX3A_vec using decoder 470 |
| 21069 | // 457: } |
| 21070 | // 457: } // switch Inst[23] |
| 21071 | // 457: } |
| 21072 | // 457: } // switch Inst[6] |
| 21073 | // 457: } |
| 21074 | 127, 0, // 462: case 0x7f: { |
| 21075 | OPC_SwitchField, 6, 1, // 464: switch Inst[6] { |
| 21076 | 0, 47, // 467: case 0x0: { |
| 21077 | OPC_SwitchField, 23, 2, // 469: switch Inst[24:23] { |
| 21078 | 0, 29, // 472: case 0x0: { |
| 21079 | OPC_SwitchField, 22, 1, // 474: switch Inst[22] { |
| 21080 | 0, 11, // 477: case 0x0: { |
| 21081 | OPC_CheckPredicate, 71, // 479: check predicate 71 |
| 21082 | OPC_CheckField, 11, 1, 0, // 481: check Inst[11] == 0x0 |
| 21083 | OPC_Decode, 204, 6, 215, 3, // 485: decode to CDE_CX1A using decoder 471 |
| 21084 | // 485: } |
| 21085 | 1, 0, // 490: case 0x1: { |
| 21086 | OPC_CheckPredicate, 71, // 492: check predicate 71 |
| 21087 | OPC_CheckField, 11, 1, 0, // 494: check Inst[11] == 0x0 |
| 21088 | OPC_Decode, 208, 6, 216, 3, // 498: decode to CDE_CX2A using decoder 472 |
| 21089 | // 498: } |
| 21090 | // 498: } // switch Inst[22] |
| 21091 | // 498: } |
| 21092 | 1, 0, // 503: case 0x1: { |
| 21093 | OPC_CheckPredicate, 71, // 505: check predicate 71 |
| 21094 | OPC_CheckField, 11, 1, 0, // 507: check Inst[11] == 0x0 |
| 21095 | OPC_Decode, 212, 6, 217, 3, // 511: decode to CDE_CX3A using decoder 473 |
| 21096 | // 511: } |
| 21097 | // 511: } // switch Inst[24:23] |
| 21098 | // 511: } |
| 21099 | 1, 0, // 516: case 0x1: { |
| 21100 | OPC_SwitchField, 23, 2, // 518: switch Inst[24:23] { |
| 21101 | 0, 29, // 521: case 0x0: { |
| 21102 | OPC_SwitchField, 22, 1, // 523: switch Inst[22] { |
| 21103 | 0, 11, // 526: case 0x0: { |
| 21104 | OPC_CheckPredicate, 71, // 528: check predicate 71 |
| 21105 | OPC_CheckField, 11, 1, 0, // 530: check Inst[11] == 0x0 |
| 21106 | OPC_Decode, 206, 6, 218, 3, // 534: decode to CDE_CX1DA using decoder 474 |
| 21107 | // 534: } |
| 21108 | 1, 0, // 539: case 0x1: { |
| 21109 | OPC_CheckPredicate, 71, // 541: check predicate 71 |
| 21110 | OPC_CheckField, 11, 1, 0, // 543: check Inst[11] == 0x0 |
| 21111 | OPC_Decode, 210, 6, 219, 3, // 547: decode to CDE_CX2DA using decoder 475 |
| 21112 | // 547: } |
| 21113 | // 547: } // switch Inst[22] |
| 21114 | // 547: } |
| 21115 | 1, 0, // 552: case 0x1: { |
| 21116 | OPC_CheckPredicate, 71, // 554: check predicate 71 |
| 21117 | OPC_CheckField, 11, 1, 0, // 556: check Inst[11] == 0x0 |
| 21118 | OPC_Decode, 214, 6, 220, 3, // 560: decode to CDE_CX3DA using decoder 476 |
| 21119 | // 560: } |
| 21120 | // 560: } // switch Inst[24:23] |
| 21121 | // 560: } |
| 21122 | // 560: } // switch Inst[6] |
| 21123 | // 560: } |
| 21124 | // 560: } // switch Inst[31:25] |
| 21125 | }; |
| 21126 | static const uint8_t DecoderTableThumb2CoProc32[463] = { |
| 21127 | OPC_SwitchField, 24, 8, // 0: switch Inst[31:24] { |
| 21128 | 236, 1, 111, // 3: case 0xec: { |
| 21129 | OPC_SwitchField, 20, 3, // 6: switch Inst[22:20] { |
| 21130 | 0, 11, // 9: case 0x0: { |
| 21131 | OPC_CheckPredicate, 9, // 11: check predicate 9 |
| 21132 | OPC_CheckField, 23, 1, 1, // 13: check Inst[23] == 0x1 |
| 21133 | OPC_Decode, 236, 33, 128, 1, // 17: decode to t2STC_OPTION using decoder 128 |
| 21134 | // 17: } |
| 21135 | 1, 11, // 22: case 0x1: { |
| 21136 | OPC_CheckPredicate, 9, // 24: check predicate 9 |
| 21137 | OPC_CheckField, 23, 1, 1, // 26: check Inst[23] == 0x1 |
| 21138 | OPC_Decode, 160, 32, 128, 1, // 30: decode to t2LDC_OPTION using decoder 128 |
| 21139 | // 30: } |
| 21140 | 2, 7, // 35: case 0x2: { |
| 21141 | OPC_CheckPredicate, 9, // 37: check predicate 9 |
| 21142 | OPC_Decode, 237, 33, 128, 1, // 39: decode to t2STC_POST using decoder 128 |
| 21143 | // 39: } |
| 21144 | 3, 7, // 44: case 0x3: { |
| 21145 | OPC_CheckPredicate, 9, // 46: check predicate 9 |
| 21146 | OPC_Decode, 161, 32, 128, 1, // 48: decode to t2LDC_POST using decoder 128 |
| 21147 | // 48: } |
| 21148 | 4, 21, // 53: case 0x4: { |
| 21149 | OPC_SwitchField, 23, 1, // 55: switch Inst[23] { |
| 21150 | 0, 7, // 58: case 0x0: { |
| 21151 | OPC_CheckPredicate, 9, // 60: check predicate 9 |
| 21152 | OPC_Decode, 218, 32, 221, 3, // 62: decode to t2MCRR using decoder 477 |
| 21153 | // 62: } |
| 21154 | 1, 0, // 67: case 0x1: { |
| 21155 | OPC_CheckPredicate, 9, // 69: check predicate 9 |
| 21156 | OPC_Decode, 232, 33, 128, 1, // 71: decode to t2STCL_OPTION using decoder 128 |
| 21157 | // 71: } |
| 21158 | // 71: } // switch Inst[23] |
| 21159 | // 71: } |
| 21160 | 5, 21, // 76: case 0x5: { |
| 21161 | OPC_SwitchField, 23, 1, // 78: switch Inst[23] { |
| 21162 | 0, 7, // 81: case 0x0: { |
| 21163 | OPC_CheckPredicate, 9, // 83: check predicate 9 |
| 21164 | OPC_Decode, 228, 32, 222, 3, // 85: decode to t2MRRC using decoder 478 |
| 21165 | // 85: } |
| 21166 | 1, 0, // 90: case 0x1: { |
| 21167 | OPC_CheckPredicate, 9, // 92: check predicate 9 |
| 21168 | OPC_Decode, 156, 32, 128, 1, // 94: decode to t2LDCL_OPTION using decoder 128 |
| 21169 | // 94: } |
| 21170 | // 94: } // switch Inst[23] |
| 21171 | // 94: } |
| 21172 | 6, 7, // 99: case 0x6: { |
| 21173 | OPC_CheckPredicate, 9, // 101: check predicate 9 |
| 21174 | OPC_Decode, 233, 33, 128, 1, // 103: decode to t2STCL_POST using decoder 128 |
| 21175 | // 103: } |
| 21176 | 7, 0, // 108: case 0x7: { |
| 21177 | OPC_CheckPredicate, 9, // 110: check predicate 9 |
| 21178 | OPC_Decode, 157, 32, 128, 1, // 112: decode to t2LDCL_POST using decoder 128 |
| 21179 | // 112: } |
| 21180 | // 112: } // switch Inst[22:20] |
| 21181 | // 112: } |
| 21182 | 237, 1, 75, // 117: case 0xed: { |
| 21183 | OPC_SwitchField, 20, 3, // 120: switch Inst[22:20] { |
| 21184 | 0, 7, // 123: case 0x0: { |
| 21185 | OPC_CheckPredicate, 9, // 125: check predicate 9 |
| 21186 | OPC_Decode, 235, 33, 128, 1, // 127: decode to t2STC_OFFSET using decoder 128 |
| 21187 | // 127: } |
| 21188 | 1, 7, // 132: case 0x1: { |
| 21189 | OPC_CheckPredicate, 9, // 134: check predicate 9 |
| 21190 | OPC_Decode, 159, 32, 128, 1, // 136: decode to t2LDC_OFFSET using decoder 128 |
| 21191 | // 136: } |
| 21192 | 2, 7, // 141: case 0x2: { |
| 21193 | OPC_CheckPredicate, 9, // 143: check predicate 9 |
| 21194 | OPC_Decode, 238, 33, 128, 1, // 145: decode to t2STC_PRE using decoder 128 |
| 21195 | // 145: } |
| 21196 | 3, 7, // 150: case 0x3: { |
| 21197 | OPC_CheckPredicate, 9, // 152: check predicate 9 |
| 21198 | OPC_Decode, 162, 32, 128, 1, // 154: decode to t2LDC_PRE using decoder 128 |
| 21199 | // 154: } |
| 21200 | 4, 7, // 159: case 0x4: { |
| 21201 | OPC_CheckPredicate, 9, // 161: check predicate 9 |
| 21202 | OPC_Decode, 231, 33, 128, 1, // 163: decode to t2STCL_OFFSET using decoder 128 |
| 21203 | // 163: } |
| 21204 | 5, 7, // 168: case 0x5: { |
| 21205 | OPC_CheckPredicate, 9, // 170: check predicate 9 |
| 21206 | OPC_Decode, 155, 32, 128, 1, // 172: decode to t2LDCL_OFFSET using decoder 128 |
| 21207 | // 172: } |
| 21208 | 6, 7, // 177: case 0x6: { |
| 21209 | OPC_CheckPredicate, 9, // 179: check predicate 9 |
| 21210 | OPC_Decode, 234, 33, 128, 1, // 181: decode to t2STCL_PRE using decoder 128 |
| 21211 | // 181: } |
| 21212 | 7, 0, // 186: case 0x7: { |
| 21213 | OPC_CheckPredicate, 9, // 188: check predicate 9 |
| 21214 | OPC_Decode, 158, 32, 128, 1, // 190: decode to t2LDCL_PRE using decoder 128 |
| 21215 | // 190: } |
| 21216 | // 190: } // switch Inst[22:20] |
| 21217 | // 190: } |
| 21218 | 238, 1, 35, // 195: case 0xee: { |
| 21219 | OPC_SwitchField, 4, 1, // 198: switch Inst[4] { |
| 21220 | 0, 7, // 201: case 0x0: { |
| 21221 | OPC_CheckPredicate, 72, // 203: check predicate 72 |
| 21222 | OPC_Decode, 228, 31, 223, 3, // 205: decode to t2CDP using decoder 479 |
| 21223 | // 205: } |
| 21224 | 1, 0, // 210: case 0x1: { |
| 21225 | OPC_SwitchField, 20, 1, // 212: switch Inst[20] { |
| 21226 | 0, 7, // 215: case 0x0: { |
| 21227 | OPC_CheckPredicate, 9, // 217: check predicate 9 |
| 21228 | OPC_Decode, 216, 32, 224, 3, // 219: decode to t2MCR using decoder 480 |
| 21229 | // 219: } |
| 21230 | 1, 0, // 224: case 0x1: { |
| 21231 | OPC_CheckPredicate, 9, // 226: check predicate 9 |
| 21232 | OPC_Decode, 226, 32, 225, 3, // 228: decode to t2MRC using decoder 481 |
| 21233 | // 228: } |
| 21234 | // 228: } // switch Inst[20] |
| 21235 | // 228: } |
| 21236 | // 228: } // switch Inst[4] |
| 21237 | // 228: } |
| 21238 | 252, 1, 111, // 233: case 0xfc: { |
| 21239 | OPC_SwitchField, 20, 3, // 236: switch Inst[22:20] { |
| 21240 | 0, 11, // 239: case 0x0: { |
| 21241 | OPC_CheckPredicate, 73, // 241: check predicate 73 |
| 21242 | OPC_CheckField, 23, 1, 1, // 243: check Inst[23] == 0x1 |
| 21243 | OPC_Decode, 228, 33, 128, 1, // 247: decode to t2STC2_OPTION using decoder 128 |
| 21244 | // 247: } |
| 21245 | 1, 11, // 252: case 0x1: { |
| 21246 | OPC_CheckPredicate, 73, // 254: check predicate 73 |
| 21247 | OPC_CheckField, 23, 1, 1, // 256: check Inst[23] == 0x1 |
| 21248 | OPC_Decode, 152, 32, 128, 1, // 260: decode to t2LDC2_OPTION using decoder 128 |
| 21249 | // 260: } |
| 21250 | 2, 7, // 265: case 0x2: { |
| 21251 | OPC_CheckPredicate, 73, // 267: check predicate 73 |
| 21252 | OPC_Decode, 229, 33, 128, 1, // 269: decode to t2STC2_POST using decoder 128 |
| 21253 | // 269: } |
| 21254 | 3, 7, // 274: case 0x3: { |
| 21255 | OPC_CheckPredicate, 73, // 276: check predicate 73 |
| 21256 | OPC_Decode, 153, 32, 128, 1, // 278: decode to t2LDC2_POST using decoder 128 |
| 21257 | // 278: } |
| 21258 | 4, 21, // 283: case 0x4: { |
| 21259 | OPC_SwitchField, 23, 1, // 285: switch Inst[23] { |
| 21260 | 0, 7, // 288: case 0x0: { |
| 21261 | OPC_CheckPredicate, 72, // 290: check predicate 72 |
| 21262 | OPC_Decode, 219, 32, 221, 3, // 292: decode to t2MCRR2 using decoder 477 |
| 21263 | // 292: } |
| 21264 | 1, 0, // 297: case 0x1: { |
| 21265 | OPC_CheckPredicate, 73, // 299: check predicate 73 |
| 21266 | OPC_Decode, 224, 33, 128, 1, // 301: decode to t2STC2L_OPTION using decoder 128 |
| 21267 | // 301: } |
| 21268 | // 301: } // switch Inst[23] |
| 21269 | // 301: } |
| 21270 | 5, 21, // 306: case 0x5: { |
| 21271 | OPC_SwitchField, 23, 1, // 308: switch Inst[23] { |
| 21272 | 0, 7, // 311: case 0x0: { |
| 21273 | OPC_CheckPredicate, 72, // 313: check predicate 72 |
| 21274 | OPC_Decode, 229, 32, 222, 3, // 315: decode to t2MRRC2 using decoder 478 |
| 21275 | // 315: } |
| 21276 | 1, 0, // 320: case 0x1: { |
| 21277 | OPC_CheckPredicate, 73, // 322: check predicate 73 |
| 21278 | OPC_Decode, 148, 32, 128, 1, // 324: decode to t2LDC2L_OPTION using decoder 128 |
| 21279 | // 324: } |
| 21280 | // 324: } // switch Inst[23] |
| 21281 | // 324: } |
| 21282 | 6, 7, // 329: case 0x6: { |
| 21283 | OPC_CheckPredicate, 73, // 331: check predicate 73 |
| 21284 | OPC_Decode, 225, 33, 128, 1, // 333: decode to t2STC2L_POST using decoder 128 |
| 21285 | // 333: } |
| 21286 | 7, 0, // 338: case 0x7: { |
| 21287 | OPC_CheckPredicate, 73, // 340: check predicate 73 |
| 21288 | OPC_Decode, 149, 32, 128, 1, // 342: decode to t2LDC2L_POST using decoder 128 |
| 21289 | // 342: } |
| 21290 | // 342: } // switch Inst[22:20] |
| 21291 | // 342: } |
| 21292 | 253, 1, 75, // 347: case 0xfd: { |
| 21293 | OPC_SwitchField, 20, 3, // 350: switch Inst[22:20] { |
| 21294 | 0, 7, // 353: case 0x0: { |
| 21295 | OPC_CheckPredicate, 73, // 355: check predicate 73 |
| 21296 | OPC_Decode, 227, 33, 128, 1, // 357: decode to t2STC2_OFFSET using decoder 128 |
| 21297 | // 357: } |
| 21298 | 1, 7, // 362: case 0x1: { |
| 21299 | OPC_CheckPredicate, 73, // 364: check predicate 73 |
| 21300 | OPC_Decode, 151, 32, 128, 1, // 366: decode to t2LDC2_OFFSET using decoder 128 |
| 21301 | // 366: } |
| 21302 | 2, 7, // 371: case 0x2: { |
| 21303 | OPC_CheckPredicate, 73, // 373: check predicate 73 |
| 21304 | OPC_Decode, 230, 33, 128, 1, // 375: decode to t2STC2_PRE using decoder 128 |
| 21305 | // 375: } |
| 21306 | 3, 7, // 380: case 0x3: { |
| 21307 | OPC_CheckPredicate, 73, // 382: check predicate 73 |
| 21308 | OPC_Decode, 154, 32, 128, 1, // 384: decode to t2LDC2_PRE using decoder 128 |
| 21309 | // 384: } |
| 21310 | 4, 7, // 389: case 0x4: { |
| 21311 | OPC_CheckPredicate, 73, // 391: check predicate 73 |
| 21312 | OPC_Decode, 223, 33, 128, 1, // 393: decode to t2STC2L_OFFSET using decoder 128 |
| 21313 | // 393: } |
| 21314 | 5, 7, // 398: case 0x5: { |
| 21315 | OPC_CheckPredicate, 73, // 400: check predicate 73 |
| 21316 | OPC_Decode, 147, 32, 128, 1, // 402: decode to t2LDC2L_OFFSET using decoder 128 |
| 21317 | // 402: } |
| 21318 | 6, 7, // 407: case 0x6: { |
| 21319 | OPC_CheckPredicate, 73, // 409: check predicate 73 |
| 21320 | OPC_Decode, 226, 33, 128, 1, // 411: decode to t2STC2L_PRE using decoder 128 |
| 21321 | // 411: } |
| 21322 | 7, 0, // 416: case 0x7: { |
| 21323 | OPC_CheckPredicate, 73, // 418: check predicate 73 |
| 21324 | OPC_Decode, 150, 32, 128, 1, // 420: decode to t2LDC2L_PRE using decoder 128 |
| 21325 | // 420: } |
| 21326 | // 420: } // switch Inst[22:20] |
| 21327 | // 420: } |
| 21328 | 254, 1, 0, // 425: case 0xfe: { |
| 21329 | OPC_SwitchField, 4, 1, // 428: switch Inst[4] { |
| 21330 | 0, 7, // 431: case 0x0: { |
| 21331 | OPC_CheckPredicate, 72, // 433: check predicate 72 |
| 21332 | OPC_Decode, 229, 31, 223, 3, // 435: decode to t2CDP2 using decoder 479 |
| 21333 | // 435: } |
| 21334 | 1, 0, // 440: case 0x1: { |
| 21335 | OPC_SwitchField, 20, 1, // 442: switch Inst[20] { |
| 21336 | 0, 7, // 445: case 0x0: { |
| 21337 | OPC_CheckPredicate, 72, // 447: check predicate 72 |
| 21338 | OPC_Decode, 217, 32, 224, 3, // 449: decode to t2MCR2 using decoder 480 |
| 21339 | // 449: } |
| 21340 | 1, 0, // 454: case 0x1: { |
| 21341 | OPC_CheckPredicate, 72, // 456: check predicate 72 |
| 21342 | OPC_Decode, 227, 32, 225, 3, // 458: decode to t2MRC2 using decoder 481 |
| 21343 | // 458: } |
| 21344 | // 458: } // switch Inst[20] |
| 21345 | // 458: } |
| 21346 | // 458: } // switch Inst[4] |
| 21347 | // 458: } |
| 21348 | // 458: } // switch Inst[31:24] |
| 21349 | }; |
| 21350 | static const uint8_t DecoderTableVFP32[3466] = { |
| 21351 | OPC_SwitchField, 8, 4, // 0: switch Inst[11:8] { |
| 21352 | 9, 168, 5, // 3: case 0x9: { |
| 21353 | OPC_SwitchField, 20, 2, // 6: switch Inst[21:20] { |
| 21354 | 0, 79, // 9: case 0x0: { |
| 21355 | OPC_SwitchField, 24, 4, // 11: switch Inst[27:24] { |
| 21356 | 13, 7, // 14: case 0xd: { |
| 21357 | OPC_CheckPredicate, 74, // 16: check predicate 74 |
| 21358 | OPC_Decode, 176, 30, 226, 3, // 18: decode to VSTRH using decoder 482 |
| 21359 | // 18: } |
| 21360 | 14, 0, // 23: case 0xe: { |
| 21361 | OPC_SwitchField, 4, 1, // 25: switch Inst[4] { |
| 21362 | 0, 39, // 28: case 0x0: { |
| 21363 | OPC_SwitchField, 6, 1, // 30: switch Inst[6] { |
| 21364 | 0, 21, // 33: case 0x0: { |
| 21365 | OPC_SwitchField, 23, 1, // 35: switch Inst[23] { |
| 21366 | 0, 7, // 38: case 0x0: { |
| 21367 | OPC_CheckPredicate, 75, // 40: check predicate 75 |
| 21368 | OPC_Decode, 140, 23, 227, 3, // 42: decode to VMLAH using decoder 483 |
| 21369 | // 42: } |
| 21370 | 1, 0, // 47: case 0x1: { |
| 21371 | OPC_CheckPredicate, 75, // 49: check predicate 75 |
| 21372 | OPC_Decode, 139, 19, 228, 3, // 51: decode to VDIVH using decoder 484 |
| 21373 | // 51: } |
| 21374 | // 51: } // switch Inst[23] |
| 21375 | // 51: } |
| 21376 | 1, 0, // 56: case 0x1: { |
| 21377 | OPC_CheckPredicate, 75, // 58: check predicate 75 |
| 21378 | OPC_CheckField, 23, 1, 0, // 60: check Inst[23] == 0x0 |
| 21379 | OPC_Decode, 171, 23, 227, 3, // 64: decode to VMLSH using decoder 483 |
| 21380 | // 64: } |
| 21381 | // 64: } // switch Inst[6] |
| 21382 | // 64: } |
| 21383 | 1, 0, // 69: case 0x1: { |
| 21384 | OPC_CheckPredicate, 74, // 71: check predicate 74 |
| 21385 | OPC_CheckField, 22, 2, 0, // 73: check Inst[23:22] == 0x0 |
| 21386 | OPC_CheckField, 5, 2, 0, // 77: check Inst[6:5] == 0x0 |
| 21387 | OPC_CheckField, 0, 4, 0, // 81: check Inst[3:0] == 0x0 |
| 21388 | OPC_Decode, 205, 23, 229, 3, // 85: decode to VMOVHR using decoder 485 |
| 21389 | // 85: } |
| 21390 | // 85: } // switch Inst[4] |
| 21391 | // 85: } |
| 21392 | // 85: } // switch Inst[27:24] |
| 21393 | // 85: } |
| 21394 | 1, 89, // 90: case 0x1: { |
| 21395 | OPC_SwitchField, 24, 4, // 92: switch Inst[27:24] { |
| 21396 | 13, 7, // 95: case 0xd: { |
| 21397 | OPC_CheckPredicate, 74, // 97: check predicate 74 |
| 21398 | OPC_Decode, 211, 22, 226, 3, // 99: decode to VLDRH using decoder 482 |
| 21399 | // 99: } |
| 21400 | 14, 0, // 104: case 0xe: { |
| 21401 | OPC_SwitchField, 4, 1, // 106: switch Inst[4] { |
| 21402 | 0, 49, // 109: case 0x0: { |
| 21403 | OPC_SwitchField, 6, 1, // 111: switch Inst[6] { |
| 21404 | 0, 21, // 114: case 0x0: { |
| 21405 | OPC_SwitchField, 23, 1, // 116: switch Inst[23] { |
| 21406 | 0, 7, // 119: case 0x0: { |
| 21407 | OPC_CheckPredicate, 75, // 121: check predicate 75 |
| 21408 | OPC_Decode, 185, 24, 227, 3, // 123: decode to VNMLSH using decoder 483 |
| 21409 | // 123: } |
| 21410 | 1, 0, // 128: case 0x1: { |
| 21411 | OPC_CheckPredicate, 75, // 130: check predicate 75 |
| 21412 | OPC_Decode, 188, 19, 227, 3, // 132: decode to VFNMSH using decoder 483 |
| 21413 | // 132: } |
| 21414 | // 132: } // switch Inst[23] |
| 21415 | // 132: } |
| 21416 | 1, 0, // 137: case 0x1: { |
| 21417 | OPC_SwitchField, 23, 1, // 139: switch Inst[23] { |
| 21418 | 0, 7, // 142: case 0x0: { |
| 21419 | OPC_CheckPredicate, 75, // 144: check predicate 75 |
| 21420 | OPC_Decode, 182, 24, 227, 3, // 146: decode to VNMLAH using decoder 483 |
| 21421 | // 146: } |
| 21422 | 1, 0, // 151: case 0x1: { |
| 21423 | OPC_CheckPredicate, 75, // 153: check predicate 75 |
| 21424 | OPC_Decode, 185, 19, 227, 3, // 155: decode to VFNMAH using decoder 483 |
| 21425 | // 155: } |
| 21426 | // 155: } // switch Inst[23] |
| 21427 | // 155: } |
| 21428 | // 155: } // switch Inst[6] |
| 21429 | // 155: } |
| 21430 | 1, 0, // 160: case 0x1: { |
| 21431 | OPC_CheckPredicate, 74, // 162: check predicate 74 |
| 21432 | OPC_CheckField, 22, 2, 0, // 164: check Inst[23:22] == 0x0 |
| 21433 | OPC_CheckField, 5, 2, 0, // 168: check Inst[6:5] == 0x0 |
| 21434 | OPC_CheckField, 0, 4, 0, // 172: check Inst[3:0] == 0x0 |
| 21435 | OPC_Decode, 215, 23, 230, 3, // 176: decode to VMOVRH using decoder 486 |
| 21436 | // 176: } |
| 21437 | // 176: } // switch Inst[4] |
| 21438 | // 176: } |
| 21439 | // 176: } // switch Inst[27:24] |
| 21440 | // 176: } |
| 21441 | 2, 65, // 181: case 0x2: { |
| 21442 | OPC_SwitchField, 6, 1, // 183: switch Inst[6] { |
| 21443 | 0, 29, // 186: case 0x0: { |
| 21444 | OPC_SwitchField, 23, 5, // 188: switch Inst[27:23] { |
| 21445 | 28, 11, // 191: case 0x1c: { |
| 21446 | OPC_CheckPredicate, 75, // 193: check predicate 75 |
| 21447 | OPC_CheckField, 4, 1, 0, // 195: check Inst[4] == 0x0 |
| 21448 | OPC_Decode, 128, 24, 228, 3, // 199: decode to VMULH using decoder 484 |
| 21449 | // 199: } |
| 21450 | 29, 0, // 204: case 0x1d: { |
| 21451 | OPC_CheckPredicate, 75, // 206: check predicate 75 |
| 21452 | OPC_CheckField, 4, 1, 0, // 208: check Inst[4] == 0x0 |
| 21453 | OPC_Decode, 163, 19, 227, 3, // 212: decode to VFMAH using decoder 483 |
| 21454 | // 212: } |
| 21455 | // 212: } // switch Inst[27:23] |
| 21456 | // 212: } |
| 21457 | 1, 0, // 217: case 0x1: { |
| 21458 | OPC_SwitchField, 23, 5, // 219: switch Inst[27:23] { |
| 21459 | 28, 11, // 222: case 0x1c: { |
| 21460 | OPC_CheckPredicate, 75, // 224: check predicate 75 |
| 21461 | OPC_CheckField, 4, 1, 0, // 226: check Inst[4] == 0x0 |
| 21462 | OPC_Decode, 188, 24, 228, 3, // 230: decode to VNMULH using decoder 484 |
| 21463 | // 230: } |
| 21464 | 29, 0, // 235: case 0x1d: { |
| 21465 | OPC_CheckPredicate, 75, // 237: check predicate 75 |
| 21466 | OPC_CheckField, 4, 1, 0, // 239: check Inst[4] == 0x0 |
| 21467 | OPC_Decode, 174, 19, 227, 3, // 243: decode to VFMSH using decoder 483 |
| 21468 | // 243: } |
| 21469 | // 243: } // switch Inst[27:23] |
| 21470 | // 243: } |
| 21471 | // 243: } // switch Inst[6] |
| 21472 | // 243: } |
| 21473 | 3, 0, // 248: case 0x3: { |
| 21474 | OPC_SwitchField, 6, 1, // 250: switch Inst[6] { |
| 21475 | 0, 33, // 253: case 0x0: { |
| 21476 | OPC_SwitchField, 23, 5, // 255: switch Inst[27:23] { |
| 21477 | 28, 11, // 258: case 0x1c: { |
| 21478 | OPC_CheckPredicate, 75, // 260: check predicate 75 |
| 21479 | OPC_CheckField, 4, 1, 0, // 262: check Inst[4] == 0x0 |
| 21480 | OPC_Decode, 243, 16, 228, 3, // 266: decode to VADDH using decoder 484 |
| 21481 | // 266: } |
| 21482 | 29, 0, // 271: case 0x1d: { |
| 21483 | OPC_CheckPredicate, 75, // 273: check predicate 75 |
| 21484 | OPC_CheckField, 7, 1, 0, // 275: check Inst[7] == 0x0 |
| 21485 | OPC_CheckField, 4, 2, 0, // 279: check Inst[5:4] == 0x0 |
| 21486 | OPC_Decode, 135, 7, 231, 3, // 283: decode to FCONSTH using decoder 487 |
| 21487 | // 283: } |
| 21488 | // 283: } // switch Inst[27:23] |
| 21489 | // 283: } |
| 21490 | 1, 0, // 288: case 0x1: { |
| 21491 | OPC_SwitchField, 23, 5, // 290: switch Inst[27:23] { |
| 21492 | 28, 11, // 293: case 0x1c: { |
| 21493 | OPC_CheckPredicate, 75, // 295: check predicate 75 |
| 21494 | OPC_CheckField, 4, 1, 0, // 297: check Inst[4] == 0x0 |
| 21495 | OPC_Decode, 197, 30, 228, 3, // 301: decode to VSUBH using decoder 484 |
| 21496 | // 301: } |
| 21497 | 29, 0, // 306: case 0x1d: { |
| 21498 | OPC_SwitchField, 16, 4, // 308: switch Inst[19:16] { |
| 21499 | 0, 15, // 311: case 0x0: { |
| 21500 | OPC_CheckPredicate, 75, // 313: check predicate 75 |
| 21501 | OPC_CheckField, 7, 1, 1, // 315: check Inst[7] == 0x1 |
| 21502 | OPC_CheckField, 4, 1, 0, // 319: check Inst[4] == 0x0 |
| 21503 | OPC_Decode, 222, 16, 232, 3, // 323: decode to VABSH using decoder 488 |
| 21504 | // 323: } |
| 21505 | 1, 29, // 328: case 0x1: { |
| 21506 | OPC_SwitchField, 7, 1, // 330: switch Inst[7] { |
| 21507 | 0, 11, // 333: case 0x0: { |
| 21508 | OPC_CheckPredicate, 75, // 335: check predicate 75 |
| 21509 | OPC_CheckField, 4, 1, 0, // 337: check Inst[4] == 0x0 |
| 21510 | OPC_Decode, 169, 24, 232, 3, // 341: decode to VNEGH using decoder 488 |
| 21511 | // 341: } |
| 21512 | 1, 0, // 346: case 0x1: { |
| 21513 | OPC_CheckPredicate, 75, // 348: check predicate 75 |
| 21514 | OPC_CheckField, 4, 1, 0, // 350: check Inst[4] == 0x0 |
| 21515 | OPC_Decode, 140, 28, 232, 3, // 354: decode to VSQRTH using decoder 488 |
| 21516 | // 354: } |
| 21517 | // 354: } // switch Inst[7] |
| 21518 | // 354: } |
| 21519 | 4, 29, // 359: case 0x4: { |
| 21520 | OPC_SwitchField, 7, 1, // 361: switch Inst[7] { |
| 21521 | 0, 11, // 364: case 0x0: { |
| 21522 | OPC_CheckPredicate, 75, // 366: check predicate 75 |
| 21523 | OPC_CheckField, 4, 1, 0, // 368: check Inst[4] == 0x0 |
| 21524 | OPC_Decode, 159, 18, 232, 3, // 372: decode to VCMPH using decoder 488 |
| 21525 | // 372: } |
| 21526 | 1, 0, // 377: case 0x1: { |
| 21527 | OPC_CheckPredicate, 75, // 379: check predicate 75 |
| 21528 | OPC_CheckField, 4, 1, 0, // 381: check Inst[4] == 0x0 |
| 21529 | OPC_Decode, 154, 18, 232, 3, // 385: decode to VCMPEH using decoder 488 |
| 21530 | // 385: } |
| 21531 | // 385: } // switch Inst[7] |
| 21532 | // 385: } |
| 21533 | 5, 29, // 390: case 0x5: { |
| 21534 | OPC_SwitchField, 7, 1, // 392: switch Inst[7] { |
| 21535 | 0, 11, // 395: case 0x0: { |
| 21536 | OPC_CheckPredicate, 75, // 397: check predicate 75 |
| 21537 | OPC_CheckField, 0, 6, 0, // 399: check Inst[5:0] == 0x0 |
| 21538 | OPC_Decode, 162, 18, 233, 3, // 403: decode to VCMPZH using decoder 489 |
| 21539 | // 403: } |
| 21540 | 1, 0, // 408: case 0x1: { |
| 21541 | OPC_CheckPredicate, 75, // 410: check predicate 75 |
| 21542 | OPC_CheckField, 0, 6, 0, // 412: check Inst[5:0] == 0x0 |
| 21543 | OPC_Decode, 157, 18, 233, 3, // 416: decode to VCMPEZH using decoder 489 |
| 21544 | // 416: } |
| 21545 | // 416: } // switch Inst[7] |
| 21546 | // 416: } |
| 21547 | 6, 29, // 421: case 0x6: { |
| 21548 | OPC_SwitchField, 7, 1, // 423: switch Inst[7] { |
| 21549 | 0, 11, // 426: case 0x0: { |
| 21550 | OPC_CheckPredicate, 75, // 428: check predicate 75 |
| 21551 | OPC_CheckField, 4, 1, 0, // 430: check Inst[4] == 0x0 |
| 21552 | OPC_Decode, 224, 26, 232, 3, // 434: decode to VRINTRH using decoder 488 |
| 21553 | // 434: } |
| 21554 | 1, 0, // 439: case 0x1: { |
| 21555 | OPC_CheckPredicate, 75, // 441: check predicate 75 |
| 21556 | OPC_CheckField, 4, 1, 0, // 443: check Inst[4] == 0x0 |
| 21557 | OPC_Decode, 234, 26, 232, 3, // 447: decode to VRINTZH using decoder 488 |
| 21558 | // 447: } |
| 21559 | // 447: } // switch Inst[7] |
| 21560 | // 447: } |
| 21561 | 7, 15, // 452: case 0x7: { |
| 21562 | OPC_CheckPredicate, 75, // 454: check predicate 75 |
| 21563 | OPC_CheckField, 7, 1, 0, // 456: check Inst[7] == 0x0 |
| 21564 | OPC_CheckField, 4, 1, 0, // 460: check Inst[4] == 0x0 |
| 21565 | OPC_Decode, 227, 26, 232, 3, // 464: decode to VRINTXH using decoder 488 |
| 21566 | // 464: } |
| 21567 | 8, 29, // 469: case 0x8: { |
| 21568 | OPC_SwitchField, 7, 1, // 471: switch Inst[7] { |
| 21569 | 0, 11, // 474: case 0x0: { |
| 21570 | OPC_CheckPredicate, 75, // 476: check predicate 75 |
| 21571 | OPC_CheckField, 4, 1, 0, // 478: check Inst[4] == 0x0 |
| 21572 | OPC_Decode, 158, 31, 234, 3, // 482: decode to VUITOH using decoder 490 |
| 21573 | // 482: } |
| 21574 | 1, 0, // 487: case 0x1: { |
| 21575 | OPC_CheckPredicate, 75, // 489: check predicate 75 |
| 21576 | OPC_CheckField, 4, 1, 0, // 491: check Inst[4] == 0x0 |
| 21577 | OPC_Decode, 253, 27, 234, 3, // 495: decode to VSITOH using decoder 490 |
| 21578 | // 495: } |
| 21579 | // 495: } // switch Inst[7] |
| 21580 | // 495: } |
| 21581 | 10, 29, // 500: case 0xa: { |
| 21582 | OPC_SwitchField, 7, 1, // 502: switch Inst[7] { |
| 21583 | 0, 11, // 505: case 0x0: { |
| 21584 | OPC_CheckPredicate, 75, // 507: check predicate 75 |
| 21585 | OPC_CheckField, 4, 1, 0, // 509: check Inst[4] == 0x0 |
| 21586 | OPC_Decode, 250, 27, 235, 3, // 513: decode to VSHTOH using decoder 491 |
| 21587 | // 513: } |
| 21588 | 1, 0, // 518: case 0x1: { |
| 21589 | OPC_CheckPredicate, 75, // 520: check predicate 75 |
| 21590 | OPC_CheckField, 4, 1, 0, // 522: check Inst[4] == 0x0 |
| 21591 | OPC_Decode, 136, 28, 235, 3, // 526: decode to VSLTOH using decoder 491 |
| 21592 | // 526: } |
| 21593 | // 526: } // switch Inst[7] |
| 21594 | // 526: } |
| 21595 | 11, 29, // 531: case 0xb: { |
| 21596 | OPC_SwitchField, 7, 1, // 533: switch Inst[7] { |
| 21597 | 0, 11, // 536: case 0x0: { |
| 21598 | OPC_CheckPredicate, 75, // 538: check predicate 75 |
| 21599 | OPC_CheckField, 4, 1, 0, // 540: check Inst[4] == 0x0 |
| 21600 | OPC_Decode, 155, 31, 235, 3, // 544: decode to VUHTOH using decoder 491 |
| 21601 | // 544: } |
| 21602 | 1, 0, // 549: case 0x1: { |
| 21603 | OPC_CheckPredicate, 75, // 551: check predicate 75 |
| 21604 | OPC_CheckField, 4, 1, 0, // 553: check Inst[4] == 0x0 |
| 21605 | OPC_Decode, 161, 31, 235, 3, // 557: decode to VULTOH using decoder 491 |
| 21606 | // 557: } |
| 21607 | // 557: } // switch Inst[7] |
| 21608 | // 557: } |
| 21609 | 12, 29, // 562: case 0xc: { |
| 21610 | OPC_SwitchField, 7, 1, // 564: switch Inst[7] { |
| 21611 | 0, 11, // 567: case 0x0: { |
| 21612 | OPC_CheckPredicate, 75, // 569: check predicate 75 |
| 21613 | OPC_CheckField, 4, 1, 0, // 571: check Inst[4] == 0x0 |
| 21614 | OPC_Decode, 130, 31, 236, 3, // 575: decode to VTOUIRH using decoder 492 |
| 21615 | // 575: } |
| 21616 | 1, 0, // 580: case 0x1: { |
| 21617 | OPC_CheckPredicate, 75, // 582: check predicate 75 |
| 21618 | OPC_CheckField, 4, 1, 0, // 584: check Inst[4] == 0x0 |
| 21619 | OPC_Decode, 133, 31, 237, 3, // 588: decode to VTOUIZH using decoder 493 |
| 21620 | // 588: } |
| 21621 | // 588: } // switch Inst[7] |
| 21622 | // 588: } |
| 21623 | 13, 29, // 593: case 0xd: { |
| 21624 | OPC_SwitchField, 7, 1, // 595: switch Inst[7] { |
| 21625 | 0, 11, // 598: case 0x0: { |
| 21626 | OPC_CheckPredicate, 75, // 600: check predicate 75 |
| 21627 | OPC_CheckField, 4, 1, 0, // 602: check Inst[4] == 0x0 |
| 21628 | OPC_Decode, 246, 30, 236, 3, // 606: decode to VTOSIRH using decoder 492 |
| 21629 | // 606: } |
| 21630 | 1, 0, // 611: case 0x1: { |
| 21631 | OPC_CheckPredicate, 75, // 613: check predicate 75 |
| 21632 | OPC_CheckField, 4, 1, 0, // 615: check Inst[4] == 0x0 |
| 21633 | OPC_Decode, 249, 30, 237, 3, // 619: decode to VTOSIZH using decoder 493 |
| 21634 | // 619: } |
| 21635 | // 619: } // switch Inst[7] |
| 21636 | // 619: } |
| 21637 | 14, 29, // 624: case 0xe: { |
| 21638 | OPC_SwitchField, 7, 1, // 626: switch Inst[7] { |
| 21639 | 0, 11, // 629: case 0x0: { |
| 21640 | OPC_CheckPredicate, 75, // 631: check predicate 75 |
| 21641 | OPC_CheckField, 4, 1, 0, // 633: check Inst[4] == 0x0 |
| 21642 | OPC_Decode, 243, 30, 235, 3, // 637: decode to VTOSHH using decoder 491 |
| 21643 | // 637: } |
| 21644 | 1, 0, // 642: case 0x1: { |
| 21645 | OPC_CheckPredicate, 75, // 644: check predicate 75 |
| 21646 | OPC_CheckField, 4, 1, 0, // 646: check Inst[4] == 0x0 |
| 21647 | OPC_Decode, 252, 30, 235, 3, // 650: decode to VTOSLH using decoder 491 |
| 21648 | // 650: } |
| 21649 | // 650: } // switch Inst[7] |
| 21650 | // 650: } |
| 21651 | 15, 0, // 655: case 0xf: { |
| 21652 | OPC_SwitchField, 7, 1, // 657: switch Inst[7] { |
| 21653 | 0, 11, // 660: case 0x0: { |
| 21654 | OPC_CheckPredicate, 75, // 662: check predicate 75 |
| 21655 | OPC_CheckField, 4, 1, 0, // 664: check Inst[4] == 0x0 |
| 21656 | OPC_Decode, 255, 30, 235, 3, // 668: decode to VTOUHH using decoder 491 |
| 21657 | // 668: } |
| 21658 | 1, 0, // 673: case 0x1: { |
| 21659 | OPC_CheckPredicate, 75, // 675: check predicate 75 |
| 21660 | OPC_CheckField, 4, 1, 0, // 677: check Inst[4] == 0x0 |
| 21661 | OPC_Decode, 136, 31, 235, 3, // 681: decode to VTOULH using decoder 491 |
| 21662 | // 681: } |
| 21663 | // 681: } // switch Inst[7] |
| 21664 | // 681: } |
| 21665 | // 681: } // switch Inst[19:16] |
| 21666 | // 681: } |
| 21667 | // 681: } // switch Inst[27:23] |
| 21668 | // 681: } |
| 21669 | // 681: } // switch Inst[6] |
| 21670 | // 681: } |
| 21671 | // 681: } // switch Inst[21:20] |
| 21672 | // 681: } |
| 21673 | 10, 211, 9, // 686: case 0xa: { |
| 21674 | OPC_SwitchField, 20, 2, // 689: switch Inst[21:20] { |
| 21675 | 0, 114, // 692: case 0x0: { |
| 21676 | OPC_SwitchField, 24, 4, // 694: switch Inst[27:24] { |
| 21677 | 12, 33, // 697: case 0xc: { |
| 21678 | OPC_SwitchField, 23, 1, // 699: switch Inst[23] { |
| 21679 | 0, 19, // 702: case 0x0: { |
| 21680 | OPC_CheckPredicate, 43, // 704: check predicate 43 |
| 21681 | OPC_CheckField, 22, 1, 1, // 706: check Inst[22] == 0x1 |
| 21682 | OPC_CheckField, 6, 2, 0, // 710: check Inst[7:6] == 0x0 |
| 21683 | OPC_CheckField, 4, 1, 1, // 714: check Inst[4] == 0x1 |
| 21684 | OPC_Decode, 221, 23, 238, 3, // 718: decode to VMOVSRR using decoder 494 |
| 21685 | // 718: } |
| 21686 | 1, 0, // 723: case 0x1: { |
| 21687 | OPC_CheckPredicate, 43, // 725: check predicate 43 |
| 21688 | OPC_Decode, 173, 30, 239, 3, // 727: decode to VSTMSIA using decoder 495 |
| 21689 | // 727: } |
| 21690 | // 727: } // switch Inst[23] |
| 21691 | // 727: } |
| 21692 | 13, 7, // 732: case 0xd: { |
| 21693 | OPC_CheckPredicate, 43, // 734: check predicate 43 |
| 21694 | OPC_Decode, 177, 30, 240, 3, // 736: decode to VSTRS using decoder 496 |
| 21695 | // 736: } |
| 21696 | 14, 0, // 741: case 0xe: { |
| 21697 | OPC_SwitchField, 4, 1, // 743: switch Inst[4] { |
| 21698 | 0, 39, // 746: case 0x0: { |
| 21699 | OPC_SwitchField, 6, 1, // 748: switch Inst[6] { |
| 21700 | 0, 21, // 751: case 0x0: { |
| 21701 | OPC_SwitchField, 23, 1, // 753: switch Inst[23] { |
| 21702 | 0, 7, // 756: case 0x0: { |
| 21703 | OPC_CheckPredicate, 42, // 758: check predicate 42 |
| 21704 | OPC_Decode, 151, 23, 241, 3, // 760: decode to VMLAS using decoder 497 |
| 21705 | // 760: } |
| 21706 | 1, 0, // 765: case 0x1: { |
| 21707 | OPC_CheckPredicate, 42, // 767: check predicate 42 |
| 21708 | OPC_Decode, 140, 19, 242, 3, // 769: decode to VDIVS using decoder 498 |
| 21709 | // 769: } |
| 21710 | // 769: } // switch Inst[23] |
| 21711 | // 769: } |
| 21712 | 1, 0, // 774: case 0x1: { |
| 21713 | OPC_CheckPredicate, 42, // 776: check predicate 42 |
| 21714 | OPC_CheckField, 23, 1, 0, // 778: check Inst[23] == 0x0 |
| 21715 | OPC_Decode, 182, 23, 241, 3, // 782: decode to VMLSS using decoder 497 |
| 21716 | // 782: } |
| 21717 | // 782: } // switch Inst[6] |
| 21718 | // 782: } |
| 21719 | 1, 0, // 787: case 0x1: { |
| 21720 | OPC_CheckPredicate, 43, // 789: check predicate 43 |
| 21721 | OPC_CheckField, 22, 2, 0, // 791: check Inst[23:22] == 0x0 |
| 21722 | OPC_CheckField, 5, 2, 0, // 795: check Inst[6:5] == 0x0 |
| 21723 | OPC_CheckField, 0, 4, 0, // 799: check Inst[3:0] == 0x0 |
| 21724 | OPC_Decode, 220, 23, 243, 3, // 803: decode to VMOVSR using decoder 499 |
| 21725 | // 803: } |
| 21726 | // 803: } // switch Inst[4] |
| 21727 | // 803: } |
| 21728 | // 803: } // switch Inst[27:24] |
| 21729 | // 803: } |
| 21730 | 1, 141, 1, // 808: case 0x1: { |
| 21731 | OPC_SwitchField, 24, 4, // 811: switch Inst[27:24] { |
| 21732 | 12, 50, // 814: case 0xc: { |
| 21733 | OPC_SwitchField, 23, 1, // 816: switch Inst[23] { |
| 21734 | 0, 19, // 819: case 0x0: { |
| 21735 | OPC_CheckPredicate, 43, // 821: check predicate 43 |
| 21736 | OPC_CheckField, 22, 1, 1, // 823: check Inst[22] == 0x1 |
| 21737 | OPC_CheckField, 6, 2, 0, // 827: check Inst[7:6] == 0x0 |
| 21738 | OPC_CheckField, 4, 1, 1, // 831: check Inst[4] == 0x1 |
| 21739 | OPC_Decode, 217, 23, 244, 3, // 835: decode to VMOVRRS using decoder 500 |
| 21740 | // 835: } |
| 21741 | 1, 0, // 840: case 0x1: { |
| 21742 | OPC_Scope, 15, // 842: try { |
| 21743 | OPC_CheckField, 16, 4, 15, // 844: check Inst[19:16] == 0xf |
| 21744 | OPC_CheckPredicate, 76, // 848: check predicate 76 |
| 21745 | OPC_CheckField, 28, 4, 14, // 850: check Inst[31:28] == 0xe |
| 21746 | OPC_Decode, 177, 27, 245, 3, // 854: decode to VSCCLRMS using decoder 501 |
| 21747 | // 854: } else try { |
| 21748 | OPC_CheckPredicate, 43, // 859: check predicate 43 |
| 21749 | OPC_Decode, 208, 22, 239, 3, // 861: decode to VLDMSIA using decoder 495 |
| 21750 | // 861: } |
| 21751 | // 861: } |
| 21752 | // 861: } // switch Inst[23] |
| 21753 | // 861: } |
| 21754 | 13, 7, // 866: case 0xd: { |
| 21755 | OPC_CheckPredicate, 43, // 868: check predicate 43 |
| 21756 | OPC_Decode, 212, 22, 240, 3, // 870: decode to VLDRS using decoder 496 |
| 21757 | // 870: } |
| 21758 | 14, 0, // 875: case 0xe: { |
| 21759 | OPC_SwitchField, 4, 1, // 877: switch Inst[4] { |
| 21760 | 0, 49, // 880: case 0x0: { |
| 21761 | OPC_SwitchField, 6, 1, // 882: switch Inst[6] { |
| 21762 | 0, 21, // 885: case 0x0: { |
| 21763 | OPC_SwitchField, 23, 1, // 887: switch Inst[23] { |
| 21764 | 0, 7, // 890: case 0x0: { |
| 21765 | OPC_CheckPredicate, 42, // 892: check predicate 42 |
| 21766 | OPC_Decode, 186, 24, 241, 3, // 894: decode to VNMLSS using decoder 497 |
| 21767 | // 894: } |
| 21768 | 1, 0, // 899: case 0x1: { |
| 21769 | OPC_CheckPredicate, 77, // 901: check predicate 77 |
| 21770 | OPC_Decode, 189, 19, 241, 3, // 903: decode to VFNMSS using decoder 497 |
| 21771 | // 903: } |
| 21772 | // 903: } // switch Inst[23] |
| 21773 | // 903: } |
| 21774 | 1, 0, // 908: case 0x1: { |
| 21775 | OPC_SwitchField, 23, 1, // 910: switch Inst[23] { |
| 21776 | 0, 7, // 913: case 0x0: { |
| 21777 | OPC_CheckPredicate, 42, // 915: check predicate 42 |
| 21778 | OPC_Decode, 183, 24, 241, 3, // 917: decode to VNMLAS using decoder 497 |
| 21779 | // 917: } |
| 21780 | 1, 0, // 922: case 0x1: { |
| 21781 | OPC_CheckPredicate, 77, // 924: check predicate 77 |
| 21782 | OPC_Decode, 186, 19, 241, 3, // 926: decode to VFNMAS using decoder 497 |
| 21783 | // 926: } |
| 21784 | // 926: } // switch Inst[23] |
| 21785 | // 926: } |
| 21786 | // 926: } // switch Inst[6] |
| 21787 | // 926: } |
| 21788 | 1, 0, // 931: case 0x1: { |
| 21789 | OPC_CheckPredicate, 43, // 933: check predicate 43 |
| 21790 | OPC_CheckField, 22, 2, 0, // 935: check Inst[23:22] == 0x0 |
| 21791 | OPC_CheckField, 5, 2, 0, // 939: check Inst[6:5] == 0x0 |
| 21792 | OPC_CheckField, 0, 4, 0, // 943: check Inst[3:0] == 0x0 |
| 21793 | OPC_Decode, 218, 23, 246, 3, // 947: decode to VMOVRS using decoder 502 |
| 21794 | // 947: } |
| 21795 | // 947: } // switch Inst[4] |
| 21796 | // 947: } |
| 21797 | // 947: } // switch Inst[27:24] |
| 21798 | // 947: } |
| 21799 | 2, 175, 2, // 952: case 0x2: { |
| 21800 | OPC_SwitchField, 23, 5, // 955: switch Inst[27:23] { |
| 21801 | 24, 46, // 958: case 0x18: { |
| 21802 | OPC_SwitchField, 0, 8, // 960: switch Inst[7:0] { |
| 21803 | 0, 19, // 963: case 0x0: { |
| 21804 | OPC_CheckPredicate, 78, // 965: check predicate 78 |
| 21805 | OPC_CheckField, 28, 4, 14, // 967: check Inst[31:28] == 0xe |
| 21806 | OPC_CheckField, 22, 1, 0, // 971: check Inst[22] == 0x0 |
| 21807 | OPC_CheckField, 12, 4, 0, // 975: check Inst[15:12] == 0x0 |
| 21808 | OPC_Decode, 233, 22, 247, 3, // 979: decode to VLSTM using decoder 503 |
| 21809 | // 979: } |
| 21810 | 128, 1, 0, // 984: case 0x80: { |
| 21811 | OPC_CheckPredicate, 76, // 987: check predicate 76 |
| 21812 | OPC_CheckField, 28, 4, 14, // 989: check Inst[31:28] == 0xe |
| 21813 | OPC_CheckField, 22, 1, 0, // 993: check Inst[22] == 0x0 |
| 21814 | OPC_CheckField, 12, 4, 0, // 997: check Inst[15:12] == 0x0 |
| 21815 | OPC_Decode, 234, 22, 247, 3, // 1001: decode to VLSTM_T2 using decoder 503 |
| 21816 | // 1001: } |
| 21817 | // 1001: } // switch Inst[7:0] |
| 21818 | // 1001: } |
| 21819 | 25, 7, // 1006: case 0x19: { |
| 21820 | OPC_CheckPredicate, 43, // 1008: check predicate 43 |
| 21821 | OPC_Decode, 174, 30, 248, 3, // 1010: decode to VSTMSIA_UPD using decoder 504 |
| 21822 | // 1010: } |
| 21823 | 26, 7, // 1015: case 0x1a: { |
| 21824 | OPC_CheckPredicate, 43, // 1017: check predicate 43 |
| 21825 | OPC_Decode, 172, 30, 248, 3, // 1019: decode to VSTMSDB_UPD using decoder 504 |
| 21826 | // 1019: } |
| 21827 | 28, 29, // 1024: case 0x1c: { |
| 21828 | OPC_SwitchField, 6, 1, // 1026: switch Inst[6] { |
| 21829 | 0, 11, // 1029: case 0x0: { |
| 21830 | OPC_CheckPredicate, 42, // 1031: check predicate 42 |
| 21831 | OPC_CheckField, 4, 1, 0, // 1033: check Inst[4] == 0x0 |
| 21832 | OPC_Decode, 141, 24, 242, 3, // 1037: decode to VMULS using decoder 498 |
| 21833 | // 1037: } |
| 21834 | 1, 0, // 1042: case 0x1: { |
| 21835 | OPC_CheckPredicate, 42, // 1044: check predicate 42 |
| 21836 | OPC_CheckField, 4, 1, 0, // 1046: check Inst[4] == 0x0 |
| 21837 | OPC_Decode, 189, 24, 242, 3, // 1050: decode to VNMULS using decoder 498 |
| 21838 | // 1050: } |
| 21839 | // 1050: } // switch Inst[6] |
| 21840 | // 1050: } |
| 21841 | 29, 0, // 1055: case 0x1d: { |
| 21842 | OPC_SwitchField, 4, 1, // 1057: switch Inst[4] { |
| 21843 | 0, 21, // 1060: case 0x0: { |
| 21844 | OPC_SwitchField, 6, 1, // 1062: switch Inst[6] { |
| 21845 | 0, 7, // 1065: case 0x0: { |
| 21846 | OPC_CheckPredicate, 77, // 1067: check predicate 77 |
| 21847 | OPC_Decode, 168, 19, 241, 3, // 1069: decode to VFMAS using decoder 497 |
| 21848 | // 1069: } |
| 21849 | 1, 0, // 1074: case 0x1: { |
| 21850 | OPC_CheckPredicate, 77, // 1076: check predicate 77 |
| 21851 | OPC_Decode, 179, 19, 241, 3, // 1078: decode to VFMSS using decoder 497 |
| 21852 | // 1078: } |
| 21853 | // 1078: } // switch Inst[6] |
| 21854 | // 1078: } |
| 21855 | 1, 0, // 1083: case 0x1: { |
| 21856 | OPC_SwitchField, 16, 4, // 1085: switch Inst[19:16] { |
| 21857 | 0, 15, // 1088: case 0x0: { |
| 21858 | OPC_CheckPredicate, 42, // 1090: check predicate 42 |
| 21859 | OPC_CheckField, 22, 1, 1, // 1092: check Inst[22] == 0x1 |
| 21860 | OPC_SoftFail, 239, 1, 0, // 1096: softfail pos=0x000000ef neg=0x00000000 |
| 21861 | OPC_Decode, 252, 23, 249, 3, // 1100: decode to VMSR_FPSID using decoder 505 |
| 21862 | // 1100: } |
| 21863 | 1, 15, // 1105: case 0x1: { |
| 21864 | OPC_CheckPredicate, 43, // 1107: check predicate 43 |
| 21865 | OPC_CheckField, 22, 1, 1, // 1109: check Inst[22] == 0x1 |
| 21866 | OPC_SoftFail, 239, 1, 0, // 1113: softfail pos=0x000000ef neg=0x00000000 |
| 21867 | OPC_Decode, 245, 23, 249, 3, // 1117: decode to VMSR using decoder 505 |
| 21868 | // 1117: } |
| 21869 | 2, 15, // 1122: case 0x2: { |
| 21870 | OPC_CheckPredicate, 79, // 1124: check predicate 79 |
| 21871 | OPC_CheckField, 22, 1, 1, // 1126: check Inst[22] == 0x1 |
| 21872 | OPC_SoftFail, 239, 1, 0, // 1130: softfail pos=0x000000ef neg=0x00000000 |
| 21873 | OPC_Decode, 251, 23, 249, 3, // 1134: decode to VMSR_FPSCR_NZCVQC using decoder 505 |
| 21874 | // 1134: } |
| 21875 | 8, 15, // 1139: case 0x8: { |
| 21876 | OPC_CheckPredicate, 42, // 1141: check predicate 42 |
| 21877 | OPC_CheckField, 22, 1, 1, // 1143: check Inst[22] == 0x1 |
| 21878 | OPC_SoftFail, 239, 1, 0, // 1147: softfail pos=0x000000ef neg=0x00000000 |
| 21879 | OPC_Decode, 248, 23, 249, 3, // 1151: decode to VMSR_FPEXC using decoder 505 |
| 21880 | // 1151: } |
| 21881 | 9, 15, // 1156: case 0x9: { |
| 21882 | OPC_CheckPredicate, 42, // 1158: check predicate 42 |
| 21883 | OPC_CheckField, 22, 1, 1, // 1160: check Inst[22] == 0x1 |
| 21884 | OPC_SoftFail, 239, 1, 0, // 1164: softfail pos=0x000000ef neg=0x00000000 |
| 21885 | OPC_Decode, 249, 23, 249, 3, // 1168: decode to VMSR_FPINST using decoder 505 |
| 21886 | // 1168: } |
| 21887 | 10, 15, // 1173: case 0xa: { |
| 21888 | OPC_CheckPredicate, 42, // 1175: check predicate 42 |
| 21889 | OPC_CheckField, 22, 1, 1, // 1177: check Inst[22] == 0x1 |
| 21890 | OPC_SoftFail, 239, 1, 0, // 1181: softfail pos=0x000000ef neg=0x00000000 |
| 21891 | OPC_Decode, 250, 23, 249, 3, // 1185: decode to VMSR_FPINST2 using decoder 505 |
| 21892 | // 1185: } |
| 21893 | 12, 15, // 1190: case 0xc: { |
| 21894 | OPC_CheckPredicate, 32, // 1192: check predicate 32 |
| 21895 | OPC_CheckField, 22, 1, 1, // 1194: check Inst[22] == 0x1 |
| 21896 | OPC_SoftFail, 239, 1, 0, // 1198: softfail pos=0x000000ef neg=0x00000000 |
| 21897 | OPC_Decode, 254, 23, 249, 3, // 1202: decode to VMSR_VPR using decoder 505 |
| 21898 | // 1202: } |
| 21899 | 13, 15, // 1207: case 0xd: { |
| 21900 | OPC_CheckPredicate, 32, // 1209: check predicate 32 |
| 21901 | OPC_CheckField, 22, 1, 1, // 1211: check Inst[22] == 0x1 |
| 21902 | OPC_SoftFail, 239, 1, 0, // 1215: softfail pos=0x000000ef neg=0x00000000 |
| 21903 | OPC_Decode, 253, 23, 249, 3, // 1219: decode to VMSR_P0 using decoder 505 |
| 21904 | // 1219: } |
| 21905 | 14, 15, // 1224: case 0xe: { |
| 21906 | OPC_CheckPredicate, 76, // 1226: check predicate 76 |
| 21907 | OPC_CheckField, 22, 1, 1, // 1228: check Inst[22] == 0x1 |
| 21908 | OPC_SoftFail, 239, 1, 0, // 1232: softfail pos=0x000000ef neg=0x00000000 |
| 21909 | OPC_Decode, 246, 23, 249, 3, // 1236: decode to VMSR_FPCXTNS using decoder 505 |
| 21910 | // 1236: } |
| 21911 | 15, 0, // 1241: case 0xf: { |
| 21912 | OPC_CheckPredicate, 76, // 1243: check predicate 76 |
| 21913 | OPC_CheckField, 22, 1, 1, // 1245: check Inst[22] == 0x1 |
| 21914 | OPC_SoftFail, 239, 1, 0, // 1249: softfail pos=0x000000ef neg=0x00000000 |
| 21915 | OPC_Decode, 247, 23, 249, 3, // 1253: decode to VMSR_FPCXTS using decoder 505 |
| 21916 | // 1253: } |
| 21917 | // 1253: } // switch Inst[19:16] |
| 21918 | // 1253: } |
| 21919 | // 1253: } // switch Inst[4] |
| 21920 | // 1253: } |
| 21921 | // 1253: } // switch Inst[27:23] |
| 21922 | // 1253: } |
| 21923 | 3, 0, // 1258: case 0x3: { |
| 21924 | OPC_SwitchField, 23, 5, // 1260: switch Inst[27:23] { |
| 21925 | 24, 46, // 1263: case 0x18: { |
| 21926 | OPC_SwitchField, 0, 8, // 1265: switch Inst[7:0] { |
| 21927 | 0, 19, // 1268: case 0x0: { |
| 21928 | OPC_CheckPredicate, 78, // 1270: check predicate 78 |
| 21929 | OPC_CheckField, 28, 4, 14, // 1272: check Inst[31:28] == 0xe |
| 21930 | OPC_CheckField, 22, 1, 0, // 1276: check Inst[22] == 0x0 |
| 21931 | OPC_CheckField, 12, 4, 0, // 1280: check Inst[15:12] == 0x0 |
| 21932 | OPC_Decode, 231, 22, 247, 3, // 1284: decode to VLLDM using decoder 503 |
| 21933 | // 1284: } |
| 21934 | 128, 1, 0, // 1289: case 0x80: { |
| 21935 | OPC_CheckPredicate, 76, // 1292: check predicate 76 |
| 21936 | OPC_CheckField, 28, 4, 14, // 1294: check Inst[31:28] == 0xe |
| 21937 | OPC_CheckField, 22, 1, 0, // 1298: check Inst[22] == 0x0 |
| 21938 | OPC_CheckField, 12, 4, 0, // 1302: check Inst[15:12] == 0x0 |
| 21939 | OPC_Decode, 232, 22, 247, 3, // 1306: decode to VLLDM_T2 using decoder 503 |
| 21940 | // 1306: } |
| 21941 | // 1306: } // switch Inst[7:0] |
| 21942 | // 1306: } |
| 21943 | 25, 7, // 1311: case 0x19: { |
| 21944 | OPC_CheckPredicate, 43, // 1313: check predicate 43 |
| 21945 | OPC_Decode, 209, 22, 248, 3, // 1315: decode to VLDMSIA_UPD using decoder 504 |
| 21946 | // 1315: } |
| 21947 | 26, 7, // 1320: case 0x1a: { |
| 21948 | OPC_CheckPredicate, 43, // 1322: check predicate 43 |
| 21949 | OPC_Decode, 207, 22, 248, 3, // 1324: decode to VLDMSDB_UPD using decoder 504 |
| 21950 | // 1324: } |
| 21951 | 28, 29, // 1329: case 0x1c: { |
| 21952 | OPC_SwitchField, 6, 1, // 1331: switch Inst[6] { |
| 21953 | 0, 11, // 1334: case 0x0: { |
| 21954 | OPC_CheckPredicate, 42, // 1336: check predicate 42 |
| 21955 | OPC_CheckField, 4, 1, 0, // 1338: check Inst[4] == 0x0 |
| 21956 | OPC_Decode, 253, 16, 242, 3, // 1342: decode to VADDS using decoder 498 |
| 21957 | // 1342: } |
| 21958 | 1, 0, // 1347: case 0x1: { |
| 21959 | OPC_CheckPredicate, 42, // 1349: check predicate 42 |
| 21960 | OPC_CheckField, 4, 1, 0, // 1351: check Inst[4] == 0x0 |
| 21961 | OPC_Decode, 207, 30, 242, 3, // 1355: decode to VSUBS using decoder 498 |
| 21962 | // 1355: } |
| 21963 | // 1355: } // switch Inst[6] |
| 21964 | // 1355: } |
| 21965 | 29, 0, // 1360: case 0x1d: { |
| 21966 | OPC_SwitchField, 4, 1, // 1362: switch Inst[4] { |
| 21967 | 0, 185, 2, // 1365: case 0x0: { |
| 21968 | OPC_SwitchField, 6, 2, // 1368: switch Inst[7:6] { |
| 21969 | 0, 11, // 1371: case 0x0: { |
| 21970 | OPC_CheckPredicate, 80, // 1373: check predicate 80 |
| 21971 | OPC_CheckField, 5, 1, 0, // 1375: check Inst[5] == 0x0 |
| 21972 | OPC_Decode, 136, 7, 250, 3, // 1379: decode to FCONSTS using decoder 506 |
| 21973 | // 1379: } |
| 21974 | 1, 146, 1, // 1384: case 0x1: { |
| 21975 | OPC_SwitchField, 16, 4, // 1387: switch Inst[19:16] { |
| 21976 | 0, 7, // 1390: case 0x0: { |
| 21977 | OPC_CheckPredicate, 43, // 1392: check predicate 43 |
| 21978 | OPC_Decode, 219, 23, 236, 3, // 1394: decode to VMOVS using decoder 492 |
| 21979 | // 1394: } |
| 21980 | 1, 7, // 1399: case 0x1: { |
| 21981 | OPC_CheckPredicate, 42, // 1401: check predicate 42 |
| 21982 | OPC_Decode, 170, 24, 236, 3, // 1403: decode to VNEGS using decoder 492 |
| 21983 | // 1403: } |
| 21984 | 2, 7, // 1408: case 0x2: { |
| 21985 | OPC_CheckPredicate, 81, // 1410: check predicate 81 |
| 21986 | OPC_Decode, 182, 18, 236, 3, // 1412: decode to VCVTBHS using decoder 492 |
| 21987 | // 1412: } |
| 21988 | 3, 7, // 1417: case 0x3: { |
| 21989 | OPC_CheckPredicate, 81, // 1419: check predicate 81 |
| 21990 | OPC_Decode, 183, 18, 251, 3, // 1421: decode to VCVTBSH using decoder 507 |
| 21991 | // 1421: } |
| 21992 | 4, 7, // 1426: case 0x4: { |
| 21993 | OPC_CheckPredicate, 42, // 1428: check predicate 42 |
| 21994 | OPC_Decode, 160, 18, 236, 3, // 1430: decode to VCMPS using decoder 492 |
| 21995 | // 1430: } |
| 21996 | 5, 15, // 1435: case 0x5: { |
| 21997 | OPC_CheckPredicate, 42, // 1437: check predicate 42 |
| 21998 | OPC_CheckField, 5, 1, 0, // 1439: check Inst[5] == 0x0 |
| 21999 | OPC_CheckField, 0, 4, 0, // 1443: check Inst[3:0] == 0x0 |
| 22000 | OPC_Decode, 163, 18, 252, 3, // 1447: decode to VCMPZS using decoder 508 |
| 22001 | // 1447: } |
| 22002 | 6, 7, // 1452: case 0x6: { |
| 22003 | OPC_CheckPredicate, 82, // 1454: check predicate 82 |
| 22004 | OPC_Decode, 225, 26, 236, 3, // 1456: decode to VRINTRS using decoder 492 |
| 22005 | // 1456: } |
| 22006 | 7, 7, // 1461: case 0x7: { |
| 22007 | OPC_CheckPredicate, 82, // 1463: check predicate 82 |
| 22008 | OPC_Decode, 232, 26, 236, 3, // 1465: decode to VRINTXS using decoder 492 |
| 22009 | // 1465: } |
| 22010 | 8, 7, // 1470: case 0x8: { |
| 22011 | OPC_CheckPredicate, 42, // 1472: check predicate 42 |
| 22012 | OPC_Decode, 159, 31, 236, 3, // 1474: decode to VUITOS using decoder 492 |
| 22013 | // 1474: } |
| 22014 | 10, 7, // 1479: case 0xa: { |
| 22015 | OPC_CheckPredicate, 42, // 1481: check predicate 42 |
| 22016 | OPC_Decode, 251, 27, 235, 3, // 1483: decode to VSHTOS using decoder 491 |
| 22017 | // 1483: } |
| 22018 | 11, 7, // 1488: case 0xb: { |
| 22019 | OPC_CheckPredicate, 42, // 1490: check predicate 42 |
| 22020 | OPC_Decode, 156, 31, 235, 3, // 1492: decode to VUHTOS using decoder 491 |
| 22021 | // 1492: } |
| 22022 | 12, 7, // 1497: case 0xc: { |
| 22023 | OPC_CheckPredicate, 42, // 1499: check predicate 42 |
| 22024 | OPC_Decode, 131, 31, 236, 3, // 1501: decode to VTOUIRS using decoder 492 |
| 22025 | // 1501: } |
| 22026 | 13, 7, // 1506: case 0xd: { |
| 22027 | OPC_CheckPredicate, 42, // 1508: check predicate 42 |
| 22028 | OPC_Decode, 247, 30, 236, 3, // 1510: decode to VTOSIRS using decoder 492 |
| 22029 | // 1510: } |
| 22030 | 14, 7, // 1515: case 0xe: { |
| 22031 | OPC_CheckPredicate, 42, // 1517: check predicate 42 |
| 22032 | OPC_Decode, 244, 30, 235, 3, // 1519: decode to VTOSHS using decoder 491 |
| 22033 | // 1519: } |
| 22034 | 15, 0, // 1524: case 0xf: { |
| 22035 | OPC_CheckPredicate, 42, // 1526: check predicate 42 |
| 22036 | OPC_Decode, 128, 31, 235, 3, // 1528: decode to VTOUHS using decoder 491 |
| 22037 | // 1528: } |
| 22038 | // 1528: } // switch Inst[19:16] |
| 22039 | // 1528: } |
| 22040 | 3, 0, // 1533: case 0x3: { |
| 22041 | OPC_SwitchField, 16, 4, // 1535: switch Inst[19:16] { |
| 22042 | 0, 7, // 1538: case 0x0: { |
| 22043 | OPC_CheckPredicate, 42, // 1540: check predicate 42 |
| 22044 | OPC_Decode, 223, 16, 236, 3, // 1542: decode to VABSS using decoder 492 |
| 22045 | // 1542: } |
| 22046 | 1, 7, // 1547: case 0x1: { |
| 22047 | OPC_CheckPredicate, 42, // 1549: check predicate 42 |
| 22048 | OPC_Decode, 141, 28, 236, 3, // 1551: decode to VSQRTS using decoder 492 |
| 22049 | // 1551: } |
| 22050 | 2, 7, // 1556: case 0x2: { |
| 22051 | OPC_CheckPredicate, 81, // 1558: check predicate 81 |
| 22052 | OPC_Decode, 230, 18, 236, 3, // 1560: decode to VCVTTHS using decoder 492 |
| 22053 | // 1560: } |
| 22054 | 3, 7, // 1565: case 0x3: { |
| 22055 | OPC_CheckPredicate, 81, // 1567: check predicate 81 |
| 22056 | OPC_Decode, 231, 18, 251, 3, // 1569: decode to VCVTTSH using decoder 507 |
| 22057 | // 1569: } |
| 22058 | 4, 7, // 1574: case 0x4: { |
| 22059 | OPC_CheckPredicate, 42, // 1576: check predicate 42 |
| 22060 | OPC_Decode, 155, 18, 236, 3, // 1578: decode to VCMPES using decoder 492 |
| 22061 | // 1578: } |
| 22062 | 5, 15, // 1583: case 0x5: { |
| 22063 | OPC_CheckPredicate, 42, // 1585: check predicate 42 |
| 22064 | OPC_CheckField, 5, 1, 0, // 1587: check Inst[5] == 0x0 |
| 22065 | OPC_CheckField, 0, 4, 0, // 1591: check Inst[3:0] == 0x0 |
| 22066 | OPC_Decode, 158, 18, 252, 3, // 1595: decode to VCMPEZS using decoder 508 |
| 22067 | // 1595: } |
| 22068 | 6, 7, // 1600: case 0x6: { |
| 22069 | OPC_CheckPredicate, 82, // 1602: check predicate 82 |
| 22070 | OPC_Decode, 239, 26, 236, 3, // 1604: decode to VRINTZS using decoder 492 |
| 22071 | // 1604: } |
| 22072 | 7, 7, // 1609: case 0x7: { |
| 22073 | OPC_CheckPredicate, 83, // 1611: check predicate 83 |
| 22074 | OPC_Decode, 184, 18, 253, 3, // 1613: decode to VCVTDS using decoder 509 |
| 22075 | // 1613: } |
| 22076 | 8, 7, // 1618: case 0x8: { |
| 22077 | OPC_CheckPredicate, 42, // 1620: check predicate 42 |
| 22078 | OPC_Decode, 254, 27, 236, 3, // 1622: decode to VSITOS using decoder 492 |
| 22079 | // 1622: } |
| 22080 | 10, 7, // 1627: case 0xa: { |
| 22081 | OPC_CheckPredicate, 42, // 1629: check predicate 42 |
| 22082 | OPC_Decode, 137, 28, 235, 3, // 1631: decode to VSLTOS using decoder 491 |
| 22083 | // 1631: } |
| 22084 | 11, 7, // 1636: case 0xb: { |
| 22085 | OPC_CheckPredicate, 42, // 1638: check predicate 42 |
| 22086 | OPC_Decode, 162, 31, 235, 3, // 1640: decode to VULTOS using decoder 491 |
| 22087 | // 1640: } |
| 22088 | 12, 7, // 1645: case 0xc: { |
| 22089 | OPC_CheckPredicate, 42, // 1647: check predicate 42 |
| 22090 | OPC_Decode, 134, 31, 236, 3, // 1649: decode to VTOUIZS using decoder 492 |
| 22091 | // 1649: } |
| 22092 | 13, 7, // 1654: case 0xd: { |
| 22093 | OPC_CheckPredicate, 42, // 1656: check predicate 42 |
| 22094 | OPC_Decode, 250, 30, 236, 3, // 1658: decode to VTOSIZS using decoder 492 |
| 22095 | // 1658: } |
| 22096 | 14, 7, // 1663: case 0xe: { |
| 22097 | OPC_CheckPredicate, 42, // 1665: check predicate 42 |
| 22098 | OPC_Decode, 253, 30, 235, 3, // 1667: decode to VTOSLS using decoder 491 |
| 22099 | // 1667: } |
| 22100 | 15, 0, // 1672: case 0xf: { |
| 22101 | OPC_CheckPredicate, 42, // 1674: check predicate 42 |
| 22102 | OPC_Decode, 137, 31, 235, 3, // 1676: decode to VTOULS using decoder 491 |
| 22103 | // 1676: } |
| 22104 | // 1676: } // switch Inst[19:16] |
| 22105 | // 1676: } |
| 22106 | // 1676: } // switch Inst[7:6] |
| 22107 | // 1676: } |
| 22108 | 1, 0, // 1681: case 0x1: { |
| 22109 | OPC_SwitchField, 16, 4, // 1683: switch Inst[19:16] { |
| 22110 | 0, 15, // 1686: case 0x0: { |
| 22111 | OPC_CheckPredicate, 42, // 1688: check predicate 42 |
| 22112 | OPC_CheckField, 22, 1, 1, // 1690: check Inst[22] == 0x1 |
| 22113 | OPC_SoftFail, 239, 1, 0, // 1694: softfail pos=0x000000ef neg=0x00000000 |
| 22114 | OPC_Decode, 239, 23, 249, 3, // 1698: decode to VMRS_FPSID using decoder 505 |
| 22115 | // 1698: } |
| 22116 | 1, 32, // 1703: case 0x1: { |
| 22117 | OPC_CheckField, 22, 1, 1, // 1705: check Inst[22] == 0x1 |
| 22118 | OPC_Scope, 15, // 1709: try { |
| 22119 | OPC_CheckField, 12, 4, 15, // 1711: check Inst[15:12] == 0xf |
| 22120 | OPC_CheckPredicate, 43, // 1715: check predicate 43 |
| 22121 | OPC_SoftFail, 239, 1, 0, // 1717: softfail pos=0x000000ef neg=0x00000000 |
| 22122 | OPC_Decode, 140, 7, 249, 3, // 1721: decode to FMSTAT using decoder 505 |
| 22123 | // 1721: } else try { |
| 22124 | OPC_CheckPredicate, 43, // 1726: check predicate 43 |
| 22125 | OPC_SoftFail, 239, 1, 0, // 1728: softfail pos=0x000000ef neg=0x00000000 |
| 22126 | OPC_Decode, 232, 23, 249, 3, // 1732: decode to VMRS using decoder 505 |
| 22127 | // 1732: } |
| 22128 | // 1732: } |
| 22129 | 2, 15, // 1737: case 0x2: { |
| 22130 | OPC_CheckPredicate, 79, // 1739: check predicate 79 |
| 22131 | OPC_CheckField, 22, 1, 1, // 1741: check Inst[22] == 0x1 |
| 22132 | OPC_SoftFail, 239, 1, 0, // 1745: softfail pos=0x000000ef neg=0x00000000 |
| 22133 | OPC_Decode, 238, 23, 249, 3, // 1749: decode to VMRS_FPSCR_NZCVQC using decoder 505 |
| 22134 | // 1749: } |
| 22135 | 5, 15, // 1754: case 0x5: { |
| 22136 | OPC_CheckPredicate, 82, // 1756: check predicate 82 |
| 22137 | OPC_CheckField, 22, 1, 1, // 1758: check Inst[22] == 0x1 |
| 22138 | OPC_SoftFail, 239, 1, 0, // 1762: softfail pos=0x000000ef neg=0x00000000 |
| 22139 | OPC_Decode, 242, 23, 249, 3, // 1766: decode to VMRS_MVFR2 using decoder 505 |
| 22140 | // 1766: } |
| 22141 | 6, 15, // 1771: case 0x6: { |
| 22142 | OPC_CheckPredicate, 42, // 1773: check predicate 42 |
| 22143 | OPC_CheckField, 22, 1, 1, // 1775: check Inst[22] == 0x1 |
| 22144 | OPC_SoftFail, 239, 1, 0, // 1779: softfail pos=0x000000ef neg=0x00000000 |
| 22145 | OPC_Decode, 241, 23, 249, 3, // 1783: decode to VMRS_MVFR1 using decoder 505 |
| 22146 | // 1783: } |
| 22147 | 7, 15, // 1788: case 0x7: { |
| 22148 | OPC_CheckPredicate, 42, // 1790: check predicate 42 |
| 22149 | OPC_CheckField, 22, 1, 1, // 1792: check Inst[22] == 0x1 |
| 22150 | OPC_SoftFail, 239, 1, 0, // 1796: softfail pos=0x000000ef neg=0x00000000 |
| 22151 | OPC_Decode, 240, 23, 249, 3, // 1800: decode to VMRS_MVFR0 using decoder 505 |
| 22152 | // 1800: } |
| 22153 | 8, 15, // 1805: case 0x8: { |
| 22154 | OPC_CheckPredicate, 42, // 1807: check predicate 42 |
| 22155 | OPC_CheckField, 22, 1, 1, // 1809: check Inst[22] == 0x1 |
| 22156 | OPC_SoftFail, 239, 1, 0, // 1813: softfail pos=0x000000ef neg=0x00000000 |
| 22157 | OPC_Decode, 235, 23, 249, 3, // 1817: decode to VMRS_FPEXC using decoder 505 |
| 22158 | // 1817: } |
| 22159 | 9, 15, // 1822: case 0x9: { |
| 22160 | OPC_CheckPredicate, 42, // 1824: check predicate 42 |
| 22161 | OPC_CheckField, 22, 1, 1, // 1826: check Inst[22] == 0x1 |
| 22162 | OPC_SoftFail, 239, 1, 0, // 1830: softfail pos=0x000000ef neg=0x00000000 |
| 22163 | OPC_Decode, 236, 23, 249, 3, // 1834: decode to VMRS_FPINST using decoder 505 |
| 22164 | // 1834: } |
| 22165 | 10, 15, // 1839: case 0xa: { |
| 22166 | OPC_CheckPredicate, 42, // 1841: check predicate 42 |
| 22167 | OPC_CheckField, 22, 1, 1, // 1843: check Inst[22] == 0x1 |
| 22168 | OPC_SoftFail, 239, 1, 0, // 1847: softfail pos=0x000000ef neg=0x00000000 |
| 22169 | OPC_Decode, 237, 23, 249, 3, // 1851: decode to VMRS_FPINST2 using decoder 505 |
| 22170 | // 1851: } |
| 22171 | 12, 15, // 1856: case 0xc: { |
| 22172 | OPC_CheckPredicate, 32, // 1858: check predicate 32 |
| 22173 | OPC_CheckField, 22, 1, 1, // 1860: check Inst[22] == 0x1 |
| 22174 | OPC_SoftFail, 239, 1, 0, // 1864: softfail pos=0x000000ef neg=0x00000000 |
| 22175 | OPC_Decode, 244, 23, 249, 3, // 1868: decode to VMRS_VPR using decoder 505 |
| 22176 | // 1868: } |
| 22177 | 13, 15, // 1873: case 0xd: { |
| 22178 | OPC_CheckPredicate, 32, // 1875: check predicate 32 |
| 22179 | OPC_CheckField, 22, 1, 1, // 1877: check Inst[22] == 0x1 |
| 22180 | OPC_SoftFail, 239, 1, 0, // 1881: softfail pos=0x000000ef neg=0x00000000 |
| 22181 | OPC_Decode, 243, 23, 249, 3, // 1885: decode to VMRS_P0 using decoder 505 |
| 22182 | // 1885: } |
| 22183 | 14, 15, // 1890: case 0xe: { |
| 22184 | OPC_CheckPredicate, 76, // 1892: check predicate 76 |
| 22185 | OPC_CheckField, 22, 1, 1, // 1894: check Inst[22] == 0x1 |
| 22186 | OPC_SoftFail, 239, 1, 0, // 1898: softfail pos=0x000000ef neg=0x00000000 |
| 22187 | OPC_Decode, 233, 23, 249, 3, // 1902: decode to VMRS_FPCXTNS using decoder 505 |
| 22188 | // 1902: } |
| 22189 | 15, 0, // 1907: case 0xf: { |
| 22190 | OPC_CheckPredicate, 76, // 1909: check predicate 76 |
| 22191 | OPC_CheckField, 22, 1, 1, // 1911: check Inst[22] == 0x1 |
| 22192 | OPC_SoftFail, 239, 1, 0, // 1915: softfail pos=0x000000ef neg=0x00000000 |
| 22193 | OPC_Decode, 234, 23, 249, 3, // 1919: decode to VMRS_FPCXTS using decoder 505 |
| 22194 | // 1919: } |
| 22195 | // 1919: } // switch Inst[19:16] |
| 22196 | // 1919: } |
| 22197 | // 1919: } // switch Inst[4] |
| 22198 | // 1919: } |
| 22199 | // 1919: } // switch Inst[27:23] |
| 22200 | // 1919: } |
| 22201 | // 1919: } // switch Inst[21:20] |
| 22202 | // 1919: } |
| 22203 | 11, 150, 7, // 1924: case 0xb: { |
| 22204 | OPC_SwitchField, 20, 2, // 1927: switch Inst[21:20] { |
| 22205 | 0, 118, // 1930: case 0x0: { |
| 22206 | OPC_SwitchField, 24, 4, // 1932: switch Inst[27:24] { |
| 22207 | 12, 51, // 1935: case 0xc: { |
| 22208 | OPC_SwitchField, 23, 1, // 1937: switch Inst[23] { |
| 22209 | 0, 19, // 1940: case 0x0: { |
| 22210 | OPC_CheckPredicate, 43, // 1942: check predicate 43 |
| 22211 | OPC_CheckField, 22, 1, 1, // 1944: check Inst[22] == 0x1 |
| 22212 | OPC_CheckField, 6, 2, 0, // 1948: check Inst[7:6] == 0x0 |
| 22213 | OPC_CheckField, 4, 1, 1, // 1952: check Inst[4] == 0x1 |
| 22214 | OPC_Decode, 203, 23, 254, 3, // 1956: decode to VMOVDRR using decoder 510 |
| 22215 | // 1956: } |
| 22216 | 1, 0, // 1961: case 0x1: { |
| 22217 | OPC_SwitchField, 0, 1, // 1963: switch Inst[0] { |
| 22218 | 0, 7, // 1966: case 0x0: { |
| 22219 | OPC_CheckPredicate, 43, // 1968: check predicate 43 |
| 22220 | OPC_Decode, 169, 30, 255, 3, // 1970: decode to VSTMDIA using decoder 511 |
| 22221 | // 1970: } |
| 22222 | 1, 0, // 1975: case 0x1: { |
| 22223 | OPC_CheckPredicate, 43, // 1977: check predicate 43 |
| 22224 | OPC_CheckField, 22, 1, 0, // 1979: check Inst[22] == 0x0 |
| 22225 | OPC_Decode, 142, 7, 128, 4, // 1983: decode to FSTMXIA using decoder 512 |
| 22226 | // 1983: } |
| 22227 | // 1983: } // switch Inst[0] |
| 22228 | // 1983: } |
| 22229 | // 1983: } // switch Inst[23] |
| 22230 | // 1983: } |
| 22231 | 13, 7, // 1988: case 0xd: { |
| 22232 | OPC_CheckPredicate, 43, // 1990: check predicate 43 |
| 22233 | OPC_Decode, 175, 30, 129, 4, // 1992: decode to VSTRD using decoder 513 |
| 22234 | // 1992: } |
| 22235 | 14, 0, // 1997: case 0xe: { |
| 22236 | OPC_SwitchField, 6, 1, // 1999: switch Inst[6] { |
| 22237 | 0, 29, // 2002: case 0x0: { |
| 22238 | OPC_SwitchField, 23, 1, // 2004: switch Inst[23] { |
| 22239 | 0, 11, // 2007: case 0x0: { |
| 22240 | OPC_CheckPredicate, 83, // 2009: check predicate 83 |
| 22241 | OPC_CheckField, 4, 1, 0, // 2011: check Inst[4] == 0x0 |
| 22242 | OPC_Decode, 139, 23, 130, 4, // 2015: decode to VMLAD using decoder 514 |
| 22243 | // 2015: } |
| 22244 | 1, 0, // 2020: case 0x1: { |
| 22245 | OPC_CheckPredicate, 83, // 2022: check predicate 83 |
| 22246 | OPC_CheckField, 4, 1, 0, // 2024: check Inst[4] == 0x0 |
| 22247 | OPC_Decode, 138, 19, 131, 4, // 2028: decode to VDIVD using decoder 515 |
| 22248 | // 2028: } |
| 22249 | // 2028: } // switch Inst[23] |
| 22250 | // 2028: } |
| 22251 | 1, 0, // 2033: case 0x1: { |
| 22252 | OPC_CheckPredicate, 83, // 2035: check predicate 83 |
| 22253 | OPC_CheckField, 23, 1, 0, // 2037: check Inst[23] == 0x0 |
| 22254 | OPC_CheckField, 4, 1, 0, // 2041: check Inst[4] == 0x0 |
| 22255 | OPC_Decode, 170, 23, 130, 4, // 2045: decode to VMLSD using decoder 514 |
| 22256 | // 2045: } |
| 22257 | // 2045: } // switch Inst[6] |
| 22258 | // 2045: } |
| 22259 | // 2045: } // switch Inst[27:24] |
| 22260 | // 2045: } |
| 22261 | 1, 149, 1, // 2050: case 0x1: { |
| 22262 | OPC_SwitchField, 24, 4, // 2053: switch Inst[27:24] { |
| 22263 | 12, 68, // 2056: case 0xc: { |
| 22264 | OPC_SwitchField, 23, 1, // 2058: switch Inst[23] { |
| 22265 | 0, 19, // 2061: case 0x0: { |
| 22266 | OPC_CheckPredicate, 43, // 2063: check predicate 43 |
| 22267 | OPC_CheckField, 22, 1, 1, // 2065: check Inst[22] == 0x1 |
| 22268 | OPC_CheckField, 6, 2, 0, // 2069: check Inst[7:6] == 0x0 |
| 22269 | OPC_CheckField, 4, 1, 1, // 2073: check Inst[4] == 0x1 |
| 22270 | OPC_Decode, 216, 23, 132, 4, // 2077: decode to VMOVRRD using decoder 516 |
| 22271 | // 2077: } |
| 22272 | 1, 0, // 2082: case 0x1: { |
| 22273 | OPC_SwitchField, 0, 1, // 2084: switch Inst[0] { |
| 22274 | 0, 24, // 2087: case 0x0: { |
| 22275 | OPC_Scope, 15, // 2089: try { |
| 22276 | OPC_CheckField, 16, 4, 15, // 2091: check Inst[19:16] == 0xf |
| 22277 | OPC_CheckPredicate, 76, // 2095: check predicate 76 |
| 22278 | OPC_CheckField, 28, 4, 14, // 2097: check Inst[31:28] == 0xe |
| 22279 | OPC_Decode, 176, 27, 245, 3, // 2101: decode to VSCCLRMD using decoder 501 |
| 22280 | // 2101: } else try { |
| 22281 | OPC_CheckPredicate, 43, // 2106: check predicate 43 |
| 22282 | OPC_Decode, 204, 22, 255, 3, // 2108: decode to VLDMDIA using decoder 511 |
| 22283 | // 2108: } |
| 22284 | // 2108: } |
| 22285 | 1, 0, // 2113: case 0x1: { |
| 22286 | OPC_CheckPredicate, 43, // 2115: check predicate 43 |
| 22287 | OPC_CheckField, 22, 1, 0, // 2117: check Inst[22] == 0x0 |
| 22288 | OPC_Decode, 138, 7, 128, 4, // 2121: decode to FLDMXIA using decoder 512 |
| 22289 | // 2121: } |
| 22290 | // 2121: } // switch Inst[0] |
| 22291 | // 2121: } |
| 22292 | // 2121: } // switch Inst[23] |
| 22293 | // 2121: } |
| 22294 | 13, 7, // 2126: case 0xd: { |
| 22295 | OPC_CheckPredicate, 43, // 2128: check predicate 43 |
| 22296 | OPC_Decode, 210, 22, 129, 4, // 2130: decode to VLDRD using decoder 513 |
| 22297 | // 2130: } |
| 22298 | 14, 0, // 2135: case 0xe: { |
| 22299 | OPC_SwitchField, 6, 1, // 2137: switch Inst[6] { |
| 22300 | 0, 29, // 2140: case 0x0: { |
| 22301 | OPC_SwitchField, 23, 1, // 2142: switch Inst[23] { |
| 22302 | 0, 11, // 2145: case 0x0: { |
| 22303 | OPC_CheckPredicate, 83, // 2147: check predicate 83 |
| 22304 | OPC_CheckField, 4, 1, 0, // 2149: check Inst[4] == 0x0 |
| 22305 | OPC_Decode, 184, 24, 130, 4, // 2153: decode to VNMLSD using decoder 514 |
| 22306 | // 2153: } |
| 22307 | 1, 0, // 2158: case 0x1: { |
| 22308 | OPC_CheckPredicate, 84, // 2160: check predicate 84 |
| 22309 | OPC_CheckField, 4, 1, 0, // 2162: check Inst[4] == 0x0 |
| 22310 | OPC_Decode, 187, 19, 130, 4, // 2166: decode to VFNMSD using decoder 514 |
| 22311 | // 2166: } |
| 22312 | // 2166: } // switch Inst[23] |
| 22313 | // 2166: } |
| 22314 | 1, 0, // 2171: case 0x1: { |
| 22315 | OPC_SwitchField, 23, 1, // 2173: switch Inst[23] { |
| 22316 | 0, 11, // 2176: case 0x0: { |
| 22317 | OPC_CheckPredicate, 83, // 2178: check predicate 83 |
| 22318 | OPC_CheckField, 4, 1, 0, // 2180: check Inst[4] == 0x0 |
| 22319 | OPC_Decode, 181, 24, 130, 4, // 2184: decode to VNMLAD using decoder 514 |
| 22320 | // 2184: } |
| 22321 | 1, 0, // 2189: case 0x1: { |
| 22322 | OPC_CheckPredicate, 84, // 2191: check predicate 84 |
| 22323 | OPC_CheckField, 4, 1, 0, // 2193: check Inst[4] == 0x0 |
| 22324 | OPC_Decode, 184, 19, 130, 4, // 2197: decode to VFNMAD using decoder 514 |
| 22325 | // 2197: } |
| 22326 | // 2197: } // switch Inst[23] |
| 22327 | // 2197: } |
| 22328 | // 2197: } // switch Inst[6] |
| 22329 | // 2197: } |
| 22330 | // 2197: } // switch Inst[27:24] |
| 22331 | // 2197: } |
| 22332 | 2, 119, // 2202: case 0x2: { |
| 22333 | OPC_SwitchField, 23, 5, // 2204: switch Inst[27:23] { |
| 22334 | 25, 25, // 2207: case 0x19: { |
| 22335 | OPC_SwitchField, 0, 1, // 2209: switch Inst[0] { |
| 22336 | 0, 7, // 2212: case 0x0: { |
| 22337 | OPC_CheckPredicate, 43, // 2214: check predicate 43 |
| 22338 | OPC_Decode, 170, 30, 133, 4, // 2216: decode to VSTMDIA_UPD using decoder 517 |
| 22339 | // 2216: } |
| 22340 | 1, 0, // 2221: case 0x1: { |
| 22341 | OPC_CheckPredicate, 43, // 2223: check predicate 43 |
| 22342 | OPC_CheckField, 22, 1, 0, // 2225: check Inst[22] == 0x0 |
| 22343 | OPC_Decode, 143, 7, 134, 4, // 2229: decode to FSTMXIA_UPD using decoder 518 |
| 22344 | // 2229: } |
| 22345 | // 2229: } // switch Inst[0] |
| 22346 | // 2229: } |
| 22347 | 26, 25, // 2234: case 0x1a: { |
| 22348 | OPC_SwitchField, 0, 1, // 2236: switch Inst[0] { |
| 22349 | 0, 7, // 2239: case 0x0: { |
| 22350 | OPC_CheckPredicate, 43, // 2241: check predicate 43 |
| 22351 | OPC_Decode, 168, 30, 133, 4, // 2243: decode to VSTMDDB_UPD using decoder 517 |
| 22352 | // 2243: } |
| 22353 | 1, 0, // 2248: case 0x1: { |
| 22354 | OPC_CheckPredicate, 43, // 2250: check predicate 43 |
| 22355 | OPC_CheckField, 22, 1, 0, // 2252: check Inst[22] == 0x0 |
| 22356 | OPC_Decode, 141, 7, 134, 4, // 2256: decode to FSTMXDB_UPD using decoder 518 |
| 22357 | // 2256: } |
| 22358 | // 2256: } // switch Inst[0] |
| 22359 | // 2256: } |
| 22360 | 28, 29, // 2261: case 0x1c: { |
| 22361 | OPC_SwitchField, 6, 1, // 2263: switch Inst[6] { |
| 22362 | 0, 11, // 2266: case 0x0: { |
| 22363 | OPC_CheckPredicate, 83, // 2268: check predicate 83 |
| 22364 | OPC_CheckField, 4, 1, 0, // 2270: check Inst[4] == 0x0 |
| 22365 | OPC_Decode, 255, 23, 131, 4, // 2274: decode to VMULD using decoder 515 |
| 22366 | // 2274: } |
| 22367 | 1, 0, // 2279: case 0x1: { |
| 22368 | OPC_CheckPredicate, 83, // 2281: check predicate 83 |
| 22369 | OPC_CheckField, 4, 1, 0, // 2283: check Inst[4] == 0x0 |
| 22370 | OPC_Decode, 187, 24, 131, 4, // 2287: decode to VNMULD using decoder 515 |
| 22371 | // 2287: } |
| 22372 | // 2287: } // switch Inst[6] |
| 22373 | // 2287: } |
| 22374 | 29, 0, // 2292: case 0x1d: { |
| 22375 | OPC_SwitchField, 6, 1, // 2294: switch Inst[6] { |
| 22376 | 0, 11, // 2297: case 0x0: { |
| 22377 | OPC_CheckPredicate, 84, // 2299: check predicate 84 |
| 22378 | OPC_CheckField, 4, 1, 0, // 2301: check Inst[4] == 0x0 |
| 22379 | OPC_Decode, 162, 19, 130, 4, // 2305: decode to VFMAD using decoder 514 |
| 22380 | // 2305: } |
| 22381 | 1, 0, // 2310: case 0x1: { |
| 22382 | OPC_CheckPredicate, 84, // 2312: check predicate 84 |
| 22383 | OPC_CheckField, 4, 1, 0, // 2314: check Inst[4] == 0x0 |
| 22384 | OPC_Decode, 173, 19, 130, 4, // 2318: decode to VFMSD using decoder 514 |
| 22385 | // 2318: } |
| 22386 | // 2318: } // switch Inst[6] |
| 22387 | // 2318: } |
| 22388 | // 2318: } // switch Inst[27:23] |
| 22389 | // 2318: } |
| 22390 | 3, 0, // 2323: case 0x3: { |
| 22391 | OPC_SwitchField, 23, 5, // 2325: switch Inst[27:23] { |
| 22392 | 25, 25, // 2328: case 0x19: { |
| 22393 | OPC_SwitchField, 0, 1, // 2330: switch Inst[0] { |
| 22394 | 0, 7, // 2333: case 0x0: { |
| 22395 | OPC_CheckPredicate, 43, // 2335: check predicate 43 |
| 22396 | OPC_Decode, 205, 22, 133, 4, // 2337: decode to VLDMDIA_UPD using decoder 517 |
| 22397 | // 2337: } |
| 22398 | 1, 0, // 2342: case 0x1: { |
| 22399 | OPC_CheckPredicate, 43, // 2344: check predicate 43 |
| 22400 | OPC_CheckField, 22, 1, 0, // 2346: check Inst[22] == 0x0 |
| 22401 | OPC_Decode, 139, 7, 134, 4, // 2350: decode to FLDMXIA_UPD using decoder 518 |
| 22402 | // 2350: } |
| 22403 | // 2350: } // switch Inst[0] |
| 22404 | // 2350: } |
| 22405 | 26, 25, // 2355: case 0x1a: { |
| 22406 | OPC_SwitchField, 0, 1, // 2357: switch Inst[0] { |
| 22407 | 0, 7, // 2360: case 0x0: { |
| 22408 | OPC_CheckPredicate, 43, // 2362: check predicate 43 |
| 22409 | OPC_Decode, 203, 22, 133, 4, // 2364: decode to VLDMDDB_UPD using decoder 517 |
| 22410 | // 2364: } |
| 22411 | 1, 0, // 2369: case 0x1: { |
| 22412 | OPC_CheckPredicate, 43, // 2371: check predicate 43 |
| 22413 | OPC_CheckField, 22, 1, 0, // 2373: check Inst[22] == 0x0 |
| 22414 | OPC_Decode, 137, 7, 134, 4, // 2377: decode to FLDMXDB_UPD using decoder 518 |
| 22415 | // 2377: } |
| 22416 | // 2377: } // switch Inst[0] |
| 22417 | // 2377: } |
| 22418 | 28, 29, // 2382: case 0x1c: { |
| 22419 | OPC_SwitchField, 6, 1, // 2384: switch Inst[6] { |
| 22420 | 0, 11, // 2387: case 0x0: { |
| 22421 | OPC_CheckPredicate, 83, // 2389: check predicate 83 |
| 22422 | OPC_CheckField, 4, 1, 0, // 2391: check Inst[4] == 0x0 |
| 22423 | OPC_Decode, 242, 16, 131, 4, // 2395: decode to VADDD using decoder 515 |
| 22424 | // 2395: } |
| 22425 | 1, 0, // 2400: case 0x1: { |
| 22426 | OPC_CheckPredicate, 83, // 2402: check predicate 83 |
| 22427 | OPC_CheckField, 4, 1, 0, // 2404: check Inst[4] == 0x0 |
| 22428 | OPC_Decode, 196, 30, 131, 4, // 2408: decode to VSUBD using decoder 515 |
| 22429 | // 2408: } |
| 22430 | // 2408: } // switch Inst[6] |
| 22431 | // 2408: } |
| 22432 | 29, 0, // 2413: case 0x1d: { |
| 22433 | OPC_SwitchField, 6, 2, // 2415: switch Inst[7:6] { |
| 22434 | 0, 11, // 2418: case 0x0: { |
| 22435 | OPC_CheckPredicate, 85, // 2420: check predicate 85 |
| 22436 | OPC_CheckField, 4, 2, 0, // 2422: check Inst[5:4] == 0x0 |
| 22437 | OPC_Decode, 134, 7, 135, 4, // 2426: decode to FCONSTD using decoder 519 |
| 22438 | // 2426: } |
| 22439 | 1, 198, 1, // 2431: case 0x1: { |
| 22440 | OPC_SwitchField, 16, 4, // 2434: switch Inst[19:16] { |
| 22441 | 0, 11, // 2437: case 0x0: { |
| 22442 | OPC_CheckPredicate, 86, // 2439: check predicate 86 |
| 22443 | OPC_CheckField, 4, 1, 0, // 2441: check Inst[4] == 0x0 |
| 22444 | OPC_Decode, 202, 23, 136, 4, // 2445: decode to VMOVD using decoder 520 |
| 22445 | // 2445: } |
| 22446 | 1, 11, // 2450: case 0x1: { |
| 22447 | OPC_CheckPredicate, 83, // 2452: check predicate 83 |
| 22448 | OPC_CheckField, 4, 1, 0, // 2454: check Inst[4] == 0x0 |
| 22449 | OPC_Decode, 168, 24, 136, 4, // 2458: decode to VNEGD using decoder 520 |
| 22450 | // 2458: } |
| 22451 | 2, 11, // 2463: case 0x2: { |
| 22452 | OPC_CheckPredicate, 87, // 2465: check predicate 87 |
| 22453 | OPC_CheckField, 4, 1, 0, // 2467: check Inst[4] == 0x0 |
| 22454 | OPC_Decode, 181, 18, 253, 3, // 2471: decode to VCVTBHD using decoder 509 |
| 22455 | // 2471: } |
| 22456 | 3, 11, // 2476: case 0x3: { |
| 22457 | OPC_CheckPredicate, 87, // 2478: check predicate 87 |
| 22458 | OPC_CheckField, 4, 1, 0, // 2480: check Inst[4] == 0x0 |
| 22459 | OPC_Decode, 180, 18, 137, 4, // 2484: decode to VCVTBDH using decoder 521 |
| 22460 | // 2484: } |
| 22461 | 4, 11, // 2489: case 0x4: { |
| 22462 | OPC_CheckPredicate, 83, // 2491: check predicate 83 |
| 22463 | OPC_CheckField, 4, 1, 0, // 2493: check Inst[4] == 0x0 |
| 22464 | OPC_Decode, 152, 18, 136, 4, // 2497: decode to VCMPD using decoder 520 |
| 22465 | // 2497: } |
| 22466 | 5, 11, // 2502: case 0x5: { |
| 22467 | OPC_CheckPredicate, 83, // 2504: check predicate 83 |
| 22468 | OPC_CheckField, 0, 6, 0, // 2506: check Inst[5:0] == 0x0 |
| 22469 | OPC_Decode, 161, 18, 138, 4, // 2510: decode to VCMPZD using decoder 522 |
| 22470 | // 2510: } |
| 22471 | 6, 11, // 2515: case 0x6: { |
| 22472 | OPC_CheckPredicate, 87, // 2517: check predicate 87 |
| 22473 | OPC_CheckField, 4, 1, 0, // 2519: check Inst[4] == 0x0 |
| 22474 | OPC_Decode, 223, 26, 136, 4, // 2523: decode to VRINTRD using decoder 520 |
| 22475 | // 2523: } |
| 22476 | 7, 11, // 2528: case 0x7: { |
| 22477 | OPC_CheckPredicate, 87, // 2530: check predicate 87 |
| 22478 | OPC_CheckField, 4, 1, 0, // 2532: check Inst[4] == 0x0 |
| 22479 | OPC_Decode, 226, 26, 136, 4, // 2536: decode to VRINTXD using decoder 520 |
| 22480 | // 2536: } |
| 22481 | 8, 11, // 2541: case 0x8: { |
| 22482 | OPC_CheckPredicate, 83, // 2543: check predicate 83 |
| 22483 | OPC_CheckField, 4, 1, 0, // 2545: check Inst[4] == 0x0 |
| 22484 | OPC_Decode, 157, 31, 253, 3, // 2549: decode to VUITOD using decoder 509 |
| 22485 | // 2549: } |
| 22486 | 10, 11, // 2554: case 0xa: { |
| 22487 | OPC_CheckPredicate, 83, // 2556: check predicate 83 |
| 22488 | OPC_CheckField, 4, 1, 0, // 2558: check Inst[4] == 0x0 |
| 22489 | OPC_Decode, 249, 27, 139, 4, // 2562: decode to VSHTOD using decoder 523 |
| 22490 | // 2562: } |
| 22491 | 11, 11, // 2567: case 0xb: { |
| 22492 | OPC_CheckPredicate, 83, // 2569: check predicate 83 |
| 22493 | OPC_CheckField, 4, 1, 0, // 2571: check Inst[4] == 0x0 |
| 22494 | OPC_Decode, 154, 31, 139, 4, // 2575: decode to VUHTOD using decoder 523 |
| 22495 | // 2575: } |
| 22496 | 12, 11, // 2580: case 0xc: { |
| 22497 | OPC_CheckPredicate, 83, // 2582: check predicate 83 |
| 22498 | OPC_CheckField, 4, 1, 0, // 2584: check Inst[4] == 0x0 |
| 22499 | OPC_Decode, 129, 31, 140, 4, // 2588: decode to VTOUIRD using decoder 524 |
| 22500 | // 2588: } |
| 22501 | 13, 11, // 2593: case 0xd: { |
| 22502 | OPC_CheckPredicate, 83, // 2595: check predicate 83 |
| 22503 | OPC_CheckField, 4, 1, 0, // 2597: check Inst[4] == 0x0 |
| 22504 | OPC_Decode, 245, 30, 140, 4, // 2601: decode to VTOSIRD using decoder 524 |
| 22505 | // 2601: } |
| 22506 | 14, 11, // 2606: case 0xe: { |
| 22507 | OPC_CheckPredicate, 83, // 2608: check predicate 83 |
| 22508 | OPC_CheckField, 4, 1, 0, // 2610: check Inst[4] == 0x0 |
| 22509 | OPC_Decode, 242, 30, 139, 4, // 2614: decode to VTOSHD using decoder 523 |
| 22510 | // 2614: } |
| 22511 | 15, 0, // 2619: case 0xf: { |
| 22512 | OPC_CheckPredicate, 83, // 2621: check predicate 83 |
| 22513 | OPC_CheckField, 4, 1, 0, // 2623: check Inst[4] == 0x0 |
| 22514 | OPC_Decode, 254, 30, 139, 4, // 2627: decode to VTOUHD using decoder 523 |
| 22515 | // 2627: } |
| 22516 | // 2627: } // switch Inst[19:16] |
| 22517 | // 2627: } |
| 22518 | 3, 0, // 2632: case 0x3: { |
| 22519 | OPC_SwitchField, 16, 4, // 2634: switch Inst[19:16] { |
| 22520 | 0, 11, // 2637: case 0x0: { |
| 22521 | OPC_CheckPredicate, 83, // 2639: check predicate 83 |
| 22522 | OPC_CheckField, 4, 1, 0, // 2641: check Inst[4] == 0x0 |
| 22523 | OPC_Decode, 221, 16, 136, 4, // 2645: decode to VABSD using decoder 520 |
| 22524 | // 2645: } |
| 22525 | 1, 11, // 2650: case 0x1: { |
| 22526 | OPC_CheckPredicate, 83, // 2652: check predicate 83 |
| 22527 | OPC_CheckField, 4, 1, 0, // 2654: check Inst[4] == 0x0 |
| 22528 | OPC_Decode, 139, 28, 136, 4, // 2658: decode to VSQRTD using decoder 520 |
| 22529 | // 2658: } |
| 22530 | 2, 11, // 2663: case 0x2: { |
| 22531 | OPC_CheckPredicate, 87, // 2665: check predicate 87 |
| 22532 | OPC_CheckField, 4, 1, 0, // 2667: check Inst[4] == 0x0 |
| 22533 | OPC_Decode, 229, 18, 253, 3, // 2671: decode to VCVTTHD using decoder 509 |
| 22534 | // 2671: } |
| 22535 | 3, 11, // 2676: case 0x3: { |
| 22536 | OPC_CheckPredicate, 87, // 2678: check predicate 87 |
| 22537 | OPC_CheckField, 4, 1, 0, // 2680: check Inst[4] == 0x0 |
| 22538 | OPC_Decode, 228, 18, 137, 4, // 2684: decode to VCVTTDH using decoder 521 |
| 22539 | // 2684: } |
| 22540 | 4, 11, // 2689: case 0x4: { |
| 22541 | OPC_CheckPredicate, 83, // 2691: check predicate 83 |
| 22542 | OPC_CheckField, 4, 1, 0, // 2693: check Inst[4] == 0x0 |
| 22543 | OPC_Decode, 153, 18, 136, 4, // 2697: decode to VCMPED using decoder 520 |
| 22544 | // 2697: } |
| 22545 | 5, 11, // 2702: case 0x5: { |
| 22546 | OPC_CheckPredicate, 83, // 2704: check predicate 83 |
| 22547 | OPC_CheckField, 0, 6, 0, // 2706: check Inst[5:0] == 0x0 |
| 22548 | OPC_Decode, 156, 18, 138, 4, // 2710: decode to VCMPEZD using decoder 522 |
| 22549 | // 2710: } |
| 22550 | 6, 11, // 2715: case 0x6: { |
| 22551 | OPC_CheckPredicate, 87, // 2717: check predicate 87 |
| 22552 | OPC_CheckField, 4, 1, 0, // 2719: check Inst[4] == 0x0 |
| 22553 | OPC_Decode, 233, 26, 136, 4, // 2723: decode to VRINTZD using decoder 520 |
| 22554 | // 2723: } |
| 22555 | 7, 11, // 2728: case 0x7: { |
| 22556 | OPC_CheckPredicate, 83, // 2730: check predicate 83 |
| 22557 | OPC_CheckField, 4, 1, 0, // 2732: check Inst[4] == 0x0 |
| 22558 | OPC_Decode, 227, 18, 140, 4, // 2736: decode to VCVTSD using decoder 524 |
| 22559 | // 2736: } |
| 22560 | 8, 11, // 2741: case 0x8: { |
| 22561 | OPC_CheckPredicate, 83, // 2743: check predicate 83 |
| 22562 | OPC_CheckField, 4, 1, 0, // 2745: check Inst[4] == 0x0 |
| 22563 | OPC_Decode, 252, 27, 253, 3, // 2749: decode to VSITOD using decoder 509 |
| 22564 | // 2749: } |
| 22565 | 9, 11, // 2754: case 0x9: { |
| 22566 | OPC_CheckPredicate, 88, // 2756: check predicate 88 |
| 22567 | OPC_CheckField, 4, 1, 0, // 2758: check Inst[4] == 0x0 |
| 22568 | OPC_Decode, 226, 19, 140, 4, // 2762: decode to VJCVT using decoder 524 |
| 22569 | // 2762: } |
| 22570 | 10, 11, // 2767: case 0xa: { |
| 22571 | OPC_CheckPredicate, 83, // 2769: check predicate 83 |
| 22572 | OPC_CheckField, 4, 1, 0, // 2771: check Inst[4] == 0x0 |
| 22573 | OPC_Decode, 135, 28, 139, 4, // 2775: decode to VSLTOD using decoder 523 |
| 22574 | // 2775: } |
| 22575 | 11, 11, // 2780: case 0xb: { |
| 22576 | OPC_CheckPredicate, 83, // 2782: check predicate 83 |
| 22577 | OPC_CheckField, 4, 1, 0, // 2784: check Inst[4] == 0x0 |
| 22578 | OPC_Decode, 160, 31, 139, 4, // 2788: decode to VULTOD using decoder 523 |
| 22579 | // 2788: } |
| 22580 | 12, 11, // 2793: case 0xc: { |
| 22581 | OPC_CheckPredicate, 83, // 2795: check predicate 83 |
| 22582 | OPC_CheckField, 4, 1, 0, // 2797: check Inst[4] == 0x0 |
| 22583 | OPC_Decode, 132, 31, 140, 4, // 2801: decode to VTOUIZD using decoder 524 |
| 22584 | // 2801: } |
| 22585 | 13, 11, // 2806: case 0xd: { |
| 22586 | OPC_CheckPredicate, 83, // 2808: check predicate 83 |
| 22587 | OPC_CheckField, 4, 1, 0, // 2810: check Inst[4] == 0x0 |
| 22588 | OPC_Decode, 248, 30, 140, 4, // 2814: decode to VTOSIZD using decoder 524 |
| 22589 | // 2814: } |
| 22590 | 14, 11, // 2819: case 0xe: { |
| 22591 | OPC_CheckPredicate, 83, // 2821: check predicate 83 |
| 22592 | OPC_CheckField, 4, 1, 0, // 2823: check Inst[4] == 0x0 |
| 22593 | OPC_Decode, 251, 30, 139, 4, // 2827: decode to VTOSLD using decoder 523 |
| 22594 | // 2827: } |
| 22595 | 15, 0, // 2832: case 0xf: { |
| 22596 | OPC_CheckPredicate, 83, // 2834: check predicate 83 |
| 22597 | OPC_CheckField, 4, 1, 0, // 2836: check Inst[4] == 0x0 |
| 22598 | OPC_Decode, 135, 31, 139, 4, // 2840: decode to VTOULD using decoder 523 |
| 22599 | // 2840: } |
| 22600 | // 2840: } // switch Inst[19:16] |
| 22601 | // 2840: } |
| 22602 | // 2840: } // switch Inst[7:6] |
| 22603 | // 2840: } |
| 22604 | // 2840: } // switch Inst[27:23] |
| 22605 | // 2840: } |
| 22606 | // 2840: } // switch Inst[21:20] |
| 22607 | // 2840: } |
| 22608 | 15, 0, // 2845: case 0xf: { |
| 22609 | OPC_SwitchField, 20, 3, // 2847: switch Inst[22:20] { |
| 22610 | 0, 37, // 2850: case 0x0: { |
| 22611 | OPC_SwitchField, 12, 4, // 2852: switch Inst[15:12] { |
| 22612 | 2, 15, // 2855: case 0x2: { |
| 22613 | OPC_CheckPredicate, 34, // 2857: check predicate 34 |
| 22614 | OPC_CheckField, 24, 4, 13, // 2859: check Inst[27:24] == 0xd |
| 22615 | OPC_CheckField, 7, 1, 1, // 2863: check Inst[7] == 0x1 |
| 22616 | OPC_Decode, 187, 30, 141, 4, // 2867: decode to VSTR_FPSCR_off using decoder 525 |
| 22617 | // 2867: } |
| 22618 | 4, 0, // 2872: case 0x4: { |
| 22619 | OPC_CheckPredicate, 34, // 2874: check predicate 34 |
| 22620 | OPC_CheckField, 24, 4, 13, // 2876: check Inst[27:24] == 0xd |
| 22621 | OPC_CheckField, 7, 1, 1, // 2880: check Inst[7] == 0x1 |
| 22622 | OPC_Decode, 184, 30, 141, 4, // 2884: decode to VSTR_FPSCR_NZCVQC_off using decoder 525 |
| 22623 | // 2884: } |
| 22624 | // 2884: } // switch Inst[15:12] |
| 22625 | // 2884: } |
| 22626 | 1, 37, // 2889: case 0x1: { |
| 22627 | OPC_SwitchField, 12, 4, // 2891: switch Inst[15:12] { |
| 22628 | 2, 15, // 2894: case 0x2: { |
| 22629 | OPC_CheckPredicate, 34, // 2896: check predicate 34 |
| 22630 | OPC_CheckField, 24, 4, 13, // 2898: check Inst[27:24] == 0xd |
| 22631 | OPC_CheckField, 7, 1, 1, // 2902: check Inst[7] == 0x1 |
| 22632 | OPC_Decode, 222, 22, 141, 4, // 2906: decode to VLDR_FPSCR_off using decoder 525 |
| 22633 | // 2906: } |
| 22634 | 4, 0, // 2911: case 0x4: { |
| 22635 | OPC_CheckPredicate, 34, // 2913: check predicate 34 |
| 22636 | OPC_CheckField, 24, 4, 13, // 2915: check Inst[27:24] == 0xd |
| 22637 | OPC_CheckField, 7, 1, 1, // 2919: check Inst[7] == 0x1 |
| 22638 | OPC_Decode, 219, 22, 141, 4, // 2923: decode to VLDR_FPSCR_NZCVQC_off using decoder 525 |
| 22639 | // 2923: } |
| 22640 | // 2923: } // switch Inst[15:12] |
| 22641 | // 2923: } |
| 22642 | 2, 65, // 2928: case 0x2: { |
| 22643 | OPC_SwitchField, 12, 4, // 2930: switch Inst[15:12] { |
| 22644 | 2, 29, // 2933: case 0x2: { |
| 22645 | OPC_SwitchField, 24, 4, // 2935: switch Inst[27:24] { |
| 22646 | 12, 11, // 2938: case 0xc: { |
| 22647 | OPC_CheckPredicate, 34, // 2940: check predicate 34 |
| 22648 | OPC_CheckField, 7, 1, 1, // 2942: check Inst[7] == 0x1 |
| 22649 | OPC_Decode, 188, 30, 142, 4, // 2946: decode to VSTR_FPSCR_post using decoder 526 |
| 22650 | // 2946: } |
| 22651 | 13, 0, // 2951: case 0xd: { |
| 22652 | OPC_CheckPredicate, 34, // 2953: check predicate 34 |
| 22653 | OPC_CheckField, 7, 1, 1, // 2955: check Inst[7] == 0x1 |
| 22654 | OPC_Decode, 189, 30, 142, 4, // 2959: decode to VSTR_FPSCR_pre using decoder 526 |
| 22655 | // 2959: } |
| 22656 | // 2959: } // switch Inst[27:24] |
| 22657 | // 2959: } |
| 22658 | 4, 0, // 2964: case 0x4: { |
| 22659 | OPC_SwitchField, 24, 4, // 2966: switch Inst[27:24] { |
| 22660 | 12, 11, // 2969: case 0xc: { |
| 22661 | OPC_CheckPredicate, 34, // 2971: check predicate 34 |
| 22662 | OPC_CheckField, 7, 1, 1, // 2973: check Inst[7] == 0x1 |
| 22663 | OPC_Decode, 185, 30, 142, 4, // 2977: decode to VSTR_FPSCR_NZCVQC_post using decoder 526 |
| 22664 | // 2977: } |
| 22665 | 13, 0, // 2982: case 0xd: { |
| 22666 | OPC_CheckPredicate, 34, // 2984: check predicate 34 |
| 22667 | OPC_CheckField, 7, 1, 1, // 2986: check Inst[7] == 0x1 |
| 22668 | OPC_Decode, 186, 30, 142, 4, // 2990: decode to VSTR_FPSCR_NZCVQC_pre using decoder 526 |
| 22669 | // 2990: } |
| 22670 | // 2990: } // switch Inst[27:24] |
| 22671 | // 2990: } |
| 22672 | // 2990: } // switch Inst[15:12] |
| 22673 | // 2990: } |
| 22674 | 3, 65, // 2995: case 0x3: { |
| 22675 | OPC_SwitchField, 12, 4, // 2997: switch Inst[15:12] { |
| 22676 | 2, 29, // 3000: case 0x2: { |
| 22677 | OPC_SwitchField, 24, 4, // 3002: switch Inst[27:24] { |
| 22678 | 12, 11, // 3005: case 0xc: { |
| 22679 | OPC_CheckPredicate, 34, // 3007: check predicate 34 |
| 22680 | OPC_CheckField, 7, 1, 1, // 3009: check Inst[7] == 0x1 |
| 22681 | OPC_Decode, 223, 22, 142, 4, // 3013: decode to VLDR_FPSCR_post using decoder 526 |
| 22682 | // 3013: } |
| 22683 | 13, 0, // 3018: case 0xd: { |
| 22684 | OPC_CheckPredicate, 34, // 3020: check predicate 34 |
| 22685 | OPC_CheckField, 7, 1, 1, // 3022: check Inst[7] == 0x1 |
| 22686 | OPC_Decode, 224, 22, 142, 4, // 3026: decode to VLDR_FPSCR_pre using decoder 526 |
| 22687 | // 3026: } |
| 22688 | // 3026: } // switch Inst[27:24] |
| 22689 | // 3026: } |
| 22690 | 4, 0, // 3031: case 0x4: { |
| 22691 | OPC_SwitchField, 24, 4, // 3033: switch Inst[27:24] { |
| 22692 | 12, 11, // 3036: case 0xc: { |
| 22693 | OPC_CheckPredicate, 34, // 3038: check predicate 34 |
| 22694 | OPC_CheckField, 7, 1, 1, // 3040: check Inst[7] == 0x1 |
| 22695 | OPC_Decode, 220, 22, 142, 4, // 3044: decode to VLDR_FPSCR_NZCVQC_post using decoder 526 |
| 22696 | // 3044: } |
| 22697 | 13, 0, // 3049: case 0xd: { |
| 22698 | OPC_CheckPredicate, 34, // 3051: check predicate 34 |
| 22699 | OPC_CheckField, 7, 1, 1, // 3053: check Inst[7] == 0x1 |
| 22700 | OPC_Decode, 221, 22, 142, 4, // 3057: decode to VLDR_FPSCR_NZCVQC_pre using decoder 526 |
| 22701 | // 3057: } |
| 22702 | // 3057: } // switch Inst[27:24] |
| 22703 | // 3057: } |
| 22704 | // 3057: } // switch Inst[15:12] |
| 22705 | // 3057: } |
| 22706 | 4, 71, // 3062: case 0x4: { |
| 22707 | OPC_SwitchField, 12, 4, // 3064: switch Inst[15:12] { |
| 22708 | 8, 15, // 3067: case 0x8: { |
| 22709 | OPC_CheckPredicate, 32, // 3069: check predicate 32 |
| 22710 | OPC_CheckField, 24, 4, 13, // 3071: check Inst[27:24] == 0xd |
| 22711 | OPC_CheckField, 7, 1, 1, // 3075: check Inst[7] == 0x1 |
| 22712 | OPC_Decode, 193, 30, 141, 4, // 3079: decode to VSTR_VPR_off using decoder 525 |
| 22713 | // 3079: } |
| 22714 | 10, 15, // 3084: case 0xa: { |
| 22715 | OPC_CheckPredicate, 32, // 3086: check predicate 32 |
| 22716 | OPC_CheckField, 24, 4, 13, // 3088: check Inst[27:24] == 0xd |
| 22717 | OPC_CheckField, 7, 1, 1, // 3092: check Inst[7] == 0x1 |
| 22718 | OPC_Decode, 190, 30, 141, 4, // 3096: decode to VSTR_P0_off using decoder 525 |
| 22719 | // 3096: } |
| 22720 | 12, 15, // 3101: case 0xc: { |
| 22721 | OPC_CheckPredicate, 76, // 3103: check predicate 76 |
| 22722 | OPC_CheckField, 24, 4, 13, // 3105: check Inst[27:24] == 0xd |
| 22723 | OPC_CheckField, 7, 1, 1, // 3109: check Inst[7] == 0x1 |
| 22724 | OPC_Decode, 178, 30, 141, 4, // 3113: decode to VSTR_FPCXTNS_off using decoder 525 |
| 22725 | // 3113: } |
| 22726 | 14, 0, // 3118: case 0xe: { |
| 22727 | OPC_CheckPredicate, 76, // 3120: check predicate 76 |
| 22728 | OPC_CheckField, 24, 4, 13, // 3122: check Inst[27:24] == 0xd |
| 22729 | OPC_CheckField, 7, 1, 1, // 3126: check Inst[7] == 0x1 |
| 22730 | OPC_Decode, 181, 30, 141, 4, // 3130: decode to VSTR_FPCXTS_off using decoder 525 |
| 22731 | // 3130: } |
| 22732 | // 3130: } // switch Inst[15:12] |
| 22733 | // 3130: } |
| 22734 | 5, 71, // 3135: case 0x5: { |
| 22735 | OPC_SwitchField, 12, 4, // 3137: switch Inst[15:12] { |
| 22736 | 8, 15, // 3140: case 0x8: { |
| 22737 | OPC_CheckPredicate, 32, // 3142: check predicate 32 |
| 22738 | OPC_CheckField, 24, 4, 13, // 3144: check Inst[27:24] == 0xd |
| 22739 | OPC_CheckField, 7, 1, 1, // 3148: check Inst[7] == 0x1 |
| 22740 | OPC_Decode, 228, 22, 141, 4, // 3152: decode to VLDR_VPR_off using decoder 525 |
| 22741 | // 3152: } |
| 22742 | 10, 15, // 3157: case 0xa: { |
| 22743 | OPC_CheckPredicate, 32, // 3159: check predicate 32 |
| 22744 | OPC_CheckField, 24, 4, 13, // 3161: check Inst[27:24] == 0xd |
| 22745 | OPC_CheckField, 7, 1, 1, // 3165: check Inst[7] == 0x1 |
| 22746 | OPC_Decode, 225, 22, 141, 4, // 3169: decode to VLDR_P0_off using decoder 525 |
| 22747 | // 3169: } |
| 22748 | 12, 15, // 3174: case 0xc: { |
| 22749 | OPC_CheckPredicate, 76, // 3176: check predicate 76 |
| 22750 | OPC_CheckField, 24, 4, 13, // 3178: check Inst[27:24] == 0xd |
| 22751 | OPC_CheckField, 7, 1, 1, // 3182: check Inst[7] == 0x1 |
| 22752 | OPC_Decode, 213, 22, 141, 4, // 3186: decode to VLDR_FPCXTNS_off using decoder 525 |
| 22753 | // 3186: } |
| 22754 | 14, 0, // 3191: case 0xe: { |
| 22755 | OPC_CheckPredicate, 76, // 3193: check predicate 76 |
| 22756 | OPC_CheckField, 24, 4, 13, // 3195: check Inst[27:24] == 0xd |
| 22757 | OPC_CheckField, 7, 1, 1, // 3199: check Inst[7] == 0x1 |
| 22758 | OPC_Decode, 216, 22, 141, 4, // 3203: decode to VLDR_FPCXTS_off using decoder 525 |
| 22759 | // 3203: } |
| 22760 | // 3203: } // switch Inst[15:12] |
| 22761 | // 3203: } |
| 22762 | 6, 127, // 3208: case 0x6: { |
| 22763 | OPC_SwitchField, 12, 4, // 3210: switch Inst[15:12] { |
| 22764 | 8, 29, // 3213: case 0x8: { |
| 22765 | OPC_SwitchField, 24, 4, // 3215: switch Inst[27:24] { |
| 22766 | 12, 11, // 3218: case 0xc: { |
| 22767 | OPC_CheckPredicate, 32, // 3220: check predicate 32 |
| 22768 | OPC_CheckField, 7, 1, 1, // 3222: check Inst[7] == 0x1 |
| 22769 | OPC_Decode, 194, 30, 142, 4, // 3226: decode to VSTR_VPR_post using decoder 526 |
| 22770 | // 3226: } |
| 22771 | 13, 0, // 3231: case 0xd: { |
| 22772 | OPC_CheckPredicate, 32, // 3233: check predicate 32 |
| 22773 | OPC_CheckField, 7, 1, 1, // 3235: check Inst[7] == 0x1 |
| 22774 | OPC_Decode, 195, 30, 142, 4, // 3239: decode to VSTR_VPR_pre using decoder 526 |
| 22775 | // 3239: } |
| 22776 | // 3239: } // switch Inst[27:24] |
| 22777 | // 3239: } |
| 22778 | 10, 29, // 3244: case 0xa: { |
| 22779 | OPC_SwitchField, 24, 4, // 3246: switch Inst[27:24] { |
| 22780 | 12, 11, // 3249: case 0xc: { |
| 22781 | OPC_CheckPredicate, 32, // 3251: check predicate 32 |
| 22782 | OPC_CheckField, 7, 1, 1, // 3253: check Inst[7] == 0x1 |
| 22783 | OPC_Decode, 191, 30, 142, 4, // 3257: decode to VSTR_P0_post using decoder 526 |
| 22784 | // 3257: } |
| 22785 | 13, 0, // 3262: case 0xd: { |
| 22786 | OPC_CheckPredicate, 32, // 3264: check predicate 32 |
| 22787 | OPC_CheckField, 7, 1, 1, // 3266: check Inst[7] == 0x1 |
| 22788 | OPC_Decode, 192, 30, 142, 4, // 3270: decode to VSTR_P0_pre using decoder 526 |
| 22789 | // 3270: } |
| 22790 | // 3270: } // switch Inst[27:24] |
| 22791 | // 3270: } |
| 22792 | 12, 29, // 3275: case 0xc: { |
| 22793 | OPC_SwitchField, 24, 4, // 3277: switch Inst[27:24] { |
| 22794 | 12, 11, // 3280: case 0xc: { |
| 22795 | OPC_CheckPredicate, 76, // 3282: check predicate 76 |
| 22796 | OPC_CheckField, 7, 1, 1, // 3284: check Inst[7] == 0x1 |
| 22797 | OPC_Decode, 179, 30, 142, 4, // 3288: decode to VSTR_FPCXTNS_post using decoder 526 |
| 22798 | // 3288: } |
| 22799 | 13, 0, // 3293: case 0xd: { |
| 22800 | OPC_CheckPredicate, 76, // 3295: check predicate 76 |
| 22801 | OPC_CheckField, 7, 1, 1, // 3297: check Inst[7] == 0x1 |
| 22802 | OPC_Decode, 180, 30, 142, 4, // 3301: decode to VSTR_FPCXTNS_pre using decoder 526 |
| 22803 | // 3301: } |
| 22804 | // 3301: } // switch Inst[27:24] |
| 22805 | // 3301: } |
| 22806 | 14, 0, // 3306: case 0xe: { |
| 22807 | OPC_SwitchField, 24, 4, // 3308: switch Inst[27:24] { |
| 22808 | 12, 11, // 3311: case 0xc: { |
| 22809 | OPC_CheckPredicate, 76, // 3313: check predicate 76 |
| 22810 | OPC_CheckField, 7, 1, 1, // 3315: check Inst[7] == 0x1 |
| 22811 | OPC_Decode, 182, 30, 142, 4, // 3319: decode to VSTR_FPCXTS_post using decoder 526 |
| 22812 | // 3319: } |
| 22813 | 13, 0, // 3324: case 0xd: { |
| 22814 | OPC_CheckPredicate, 76, // 3326: check predicate 76 |
| 22815 | OPC_CheckField, 7, 1, 1, // 3328: check Inst[7] == 0x1 |
| 22816 | OPC_Decode, 183, 30, 142, 4, // 3332: decode to VSTR_FPCXTS_pre using decoder 526 |
| 22817 | // 3332: } |
| 22818 | // 3332: } // switch Inst[27:24] |
| 22819 | // 3332: } |
| 22820 | // 3332: } // switch Inst[15:12] |
| 22821 | // 3332: } |
| 22822 | 7, 0, // 3337: case 0x7: { |
| 22823 | OPC_SwitchField, 12, 4, // 3339: switch Inst[15:12] { |
| 22824 | 8, 29, // 3342: case 0x8: { |
| 22825 | OPC_SwitchField, 24, 4, // 3344: switch Inst[27:24] { |
| 22826 | 12, 11, // 3347: case 0xc: { |
| 22827 | OPC_CheckPredicate, 32, // 3349: check predicate 32 |
| 22828 | OPC_CheckField, 7, 1, 1, // 3351: check Inst[7] == 0x1 |
| 22829 | OPC_Decode, 229, 22, 142, 4, // 3355: decode to VLDR_VPR_post using decoder 526 |
| 22830 | // 3355: } |
| 22831 | 13, 0, // 3360: case 0xd: { |
| 22832 | OPC_CheckPredicate, 32, // 3362: check predicate 32 |
| 22833 | OPC_CheckField, 7, 1, 1, // 3364: check Inst[7] == 0x1 |
| 22834 | OPC_Decode, 230, 22, 142, 4, // 3368: decode to VLDR_VPR_pre using decoder 526 |
| 22835 | // 3368: } |
| 22836 | // 3368: } // switch Inst[27:24] |
| 22837 | // 3368: } |
| 22838 | 10, 29, // 3373: case 0xa: { |
| 22839 | OPC_SwitchField, 24, 4, // 3375: switch Inst[27:24] { |
| 22840 | 12, 11, // 3378: case 0xc: { |
| 22841 | OPC_CheckPredicate, 32, // 3380: check predicate 32 |
| 22842 | OPC_CheckField, 7, 1, 1, // 3382: check Inst[7] == 0x1 |
| 22843 | OPC_Decode, 226, 22, 142, 4, // 3386: decode to VLDR_P0_post using decoder 526 |
| 22844 | // 3386: } |
| 22845 | 13, 0, // 3391: case 0xd: { |
| 22846 | OPC_CheckPredicate, 32, // 3393: check predicate 32 |
| 22847 | OPC_CheckField, 7, 1, 1, // 3395: check Inst[7] == 0x1 |
| 22848 | OPC_Decode, 227, 22, 142, 4, // 3399: decode to VLDR_P0_pre using decoder 526 |
| 22849 | // 3399: } |
| 22850 | // 3399: } // switch Inst[27:24] |
| 22851 | // 3399: } |
| 22852 | 12, 29, // 3404: case 0xc: { |
| 22853 | OPC_SwitchField, 24, 4, // 3406: switch Inst[27:24] { |
| 22854 | 12, 11, // 3409: case 0xc: { |
| 22855 | OPC_CheckPredicate, 76, // 3411: check predicate 76 |
| 22856 | OPC_CheckField, 7, 1, 1, // 3413: check Inst[7] == 0x1 |
| 22857 | OPC_Decode, 214, 22, 142, 4, // 3417: decode to VLDR_FPCXTNS_post using decoder 526 |
| 22858 | // 3417: } |
| 22859 | 13, 0, // 3422: case 0xd: { |
| 22860 | OPC_CheckPredicate, 76, // 3424: check predicate 76 |
| 22861 | OPC_CheckField, 7, 1, 1, // 3426: check Inst[7] == 0x1 |
| 22862 | OPC_Decode, 215, 22, 142, 4, // 3430: decode to VLDR_FPCXTNS_pre using decoder 526 |
| 22863 | // 3430: } |
| 22864 | // 3430: } // switch Inst[27:24] |
| 22865 | // 3430: } |
| 22866 | 14, 0, // 3435: case 0xe: { |
| 22867 | OPC_SwitchField, 24, 4, // 3437: switch Inst[27:24] { |
| 22868 | 12, 11, // 3440: case 0xc: { |
| 22869 | OPC_CheckPredicate, 76, // 3442: check predicate 76 |
| 22870 | OPC_CheckField, 7, 1, 1, // 3444: check Inst[7] == 0x1 |
| 22871 | OPC_Decode, 217, 22, 142, 4, // 3448: decode to VLDR_FPCXTS_post using decoder 526 |
| 22872 | // 3448: } |
| 22873 | 13, 0, // 3453: case 0xd: { |
| 22874 | OPC_CheckPredicate, 76, // 3455: check predicate 76 |
| 22875 | OPC_CheckField, 7, 1, 1, // 3457: check Inst[7] == 0x1 |
| 22876 | OPC_Decode, 218, 22, 142, 4, // 3461: decode to VLDR_FPCXTS_pre using decoder 526 |
| 22877 | // 3461: } |
| 22878 | // 3461: } // switch Inst[27:24] |
| 22879 | // 3461: } |
| 22880 | // 3461: } // switch Inst[15:12] |
| 22881 | // 3461: } |
| 22882 | // 3461: } // switch Inst[22:20] |
| 22883 | // 3461: } |
| 22884 | // 3461: } // switch Inst[11:8] |
| 22885 | }; |
| 22886 | static const uint8_t DecoderTableVFPV832[1960] = { |
| 22887 | OPC_SwitchField, 8, 4, // 0: switch Inst[11:8] { |
| 22888 | 8, 216, 2, // 3: case 0x8: { |
| 22889 | OPC_SwitchField, 4, 1, // 6: switch Inst[4] { |
| 22890 | 0, 157, 1, // 9: case 0x0: { |
| 22891 | OPC_SwitchField, 6, 1, // 12: switch Inst[6] { |
| 22892 | 0, 75, // 15: case 0x0: { |
| 22893 | OPC_SwitchField, 25, 7, // 17: switch Inst[31:25] { |
| 22894 | 126, 47, // 20: case 0x7e: { |
| 22895 | OPC_SwitchField, 20, 2, // 22: switch Inst[21:20] { |
| 22896 | 0, 11, // 25: case 0x0: { |
| 22897 | OPC_CheckPredicate, 89, // 27: check predicate 89 |
| 22898 | OPC_CheckField, 23, 1, 1, // 29: check Inst[23] == 0x1 |
| 22899 | OPC_Decode, 165, 17, 143, 4, // 33: decode to VCADDv4f16 using decoder 527 |
| 22900 | // 33: } |
| 22901 | 1, 11, // 38: case 0x1: { |
| 22902 | OPC_CheckPredicate, 90, // 40: check predicate 90 |
| 22903 | OPC_CheckField, 23, 1, 1, // 42: check Inst[23] == 0x1 |
| 22904 | OPC_Decode, 164, 17, 143, 4, // 46: decode to VCADDv2f32 using decoder 527 |
| 22905 | // 46: } |
| 22906 | 2, 7, // 51: case 0x2: { |
| 22907 | OPC_CheckPredicate, 89, // 53: check predicate 89 |
| 22908 | OPC_Decode, 146, 18, 144, 4, // 55: decode to VCMLAv4f16 using decoder 528 |
| 22909 | // 55: } |
| 22910 | 3, 0, // 60: case 0x3: { |
| 22911 | OPC_CheckPredicate, 90, // 62: check predicate 90 |
| 22912 | OPC_Decode, 144, 18, 144, 4, // 64: decode to VCMLAv2f32 using decoder 528 |
| 22913 | // 64: } |
| 22914 | // 64: } // switch Inst[21:20] |
| 22915 | // 64: } |
| 22916 | 127, 0, // 69: case 0x7f: { |
| 22917 | OPC_SwitchField, 23, 2, // 71: switch Inst[24:23] { |
| 22918 | 0, 7, // 74: case 0x0: { |
| 22919 | OPC_CheckPredicate, 89, // 76: check predicate 89 |
| 22920 | OPC_Decode, 147, 18, 145, 4, // 78: decode to VCMLAv4f16_indexed using decoder 529 |
| 22921 | // 78: } |
| 22922 | 1, 0, // 83: case 0x1: { |
| 22923 | OPC_CheckPredicate, 90, // 85: check predicate 90 |
| 22924 | OPC_Decode, 145, 18, 146, 4, // 87: decode to VCMLAv2f32_indexed using decoder 530 |
| 22925 | // 87: } |
| 22926 | // 87: } // switch Inst[24:23] |
| 22927 | // 87: } |
| 22928 | // 87: } // switch Inst[31:25] |
| 22929 | // 87: } |
| 22930 | 1, 0, // 92: case 0x1: { |
| 22931 | OPC_SwitchField, 25, 7, // 94: switch Inst[31:25] { |
| 22932 | 126, 47, // 97: case 0x7e: { |
| 22933 | OPC_SwitchField, 20, 2, // 99: switch Inst[21:20] { |
| 22934 | 0, 11, // 102: case 0x0: { |
| 22935 | OPC_CheckPredicate, 89, // 104: check predicate 89 |
| 22936 | OPC_CheckField, 23, 1, 1, // 106: check Inst[23] == 0x1 |
| 22937 | OPC_Decode, 167, 17, 147, 4, // 110: decode to VCADDv8f16 using decoder 531 |
| 22938 | // 110: } |
| 22939 | 1, 11, // 115: case 0x1: { |
| 22940 | OPC_CheckPredicate, 90, // 117: check predicate 90 |
| 22941 | OPC_CheckField, 23, 1, 1, // 119: check Inst[23] == 0x1 |
| 22942 | OPC_Decode, 166, 17, 147, 4, // 123: decode to VCADDv4f32 using decoder 531 |
| 22943 | // 123: } |
| 22944 | 2, 7, // 128: case 0x2: { |
| 22945 | OPC_CheckPredicate, 89, // 130: check predicate 89 |
| 22946 | OPC_Decode, 150, 18, 148, 4, // 132: decode to VCMLAv8f16 using decoder 532 |
| 22947 | // 132: } |
| 22948 | 3, 0, // 137: case 0x3: { |
| 22949 | OPC_CheckPredicate, 90, // 139: check predicate 90 |
| 22950 | OPC_Decode, 148, 18, 148, 4, // 141: decode to VCMLAv4f32 using decoder 532 |
| 22951 | // 141: } |
| 22952 | // 141: } // switch Inst[21:20] |
| 22953 | // 141: } |
| 22954 | 127, 0, // 146: case 0x7f: { |
| 22955 | OPC_SwitchField, 23, 2, // 148: switch Inst[24:23] { |
| 22956 | 0, 7, // 151: case 0x0: { |
| 22957 | OPC_CheckPredicate, 89, // 153: check predicate 89 |
| 22958 | OPC_Decode, 151, 18, 149, 4, // 155: decode to VCMLAv8f16_indexed using decoder 533 |
| 22959 | // 155: } |
| 22960 | 1, 0, // 160: case 0x1: { |
| 22961 | OPC_CheckPredicate, 90, // 162: check predicate 90 |
| 22962 | OPC_Decode, 149, 18, 146, 4, // 164: decode to VCMLAv4f32_indexed using decoder 530 |
| 22963 | // 164: } |
| 22964 | // 164: } // switch Inst[24:23] |
| 22965 | // 164: } |
| 22966 | // 164: } // switch Inst[31:25] |
| 22967 | // 164: } |
| 22968 | // 164: } // switch Inst[6] |
| 22969 | // 164: } |
| 22970 | 1, 0, // 169: case 0x1: { |
| 22971 | OPC_SwitchField, 20, 2, // 171: switch Inst[21:20] { |
| 22972 | 0, 31, // 174: case 0x0: { |
| 22973 | OPC_SwitchField, 6, 1, // 176: switch Inst[6] { |
| 22974 | 0, 12, // 179: case 0x0: { |
| 22975 | OPC_CheckPredicate, 91, // 181: check predicate 91 |
| 22976 | OPC_CheckField, 23, 9, 252, 3, // 183: check Inst[31:23] == 0x1fc |
| 22977 | OPC_Decode, 165, 19, 150, 4, // 188: decode to VFMALDI using decoder 534 |
| 22978 | // 188: } |
| 22979 | 1, 0, // 193: case 0x1: { |
| 22980 | OPC_CheckPredicate, 91, // 195: check predicate 91 |
| 22981 | OPC_CheckField, 23, 9, 252, 3, // 197: check Inst[31:23] == 0x1fc |
| 22982 | OPC_Decode, 167, 19, 151, 4, // 202: decode to VFMALQI using decoder 535 |
| 22983 | // 202: } |
| 22984 | // 202: } // switch Inst[6] |
| 22985 | // 202: } |
| 22986 | 1, 31, // 207: case 0x1: { |
| 22987 | OPC_SwitchField, 6, 1, // 209: switch Inst[6] { |
| 22988 | 0, 12, // 212: case 0x0: { |
| 22989 | OPC_CheckPredicate, 91, // 214: check predicate 91 |
| 22990 | OPC_CheckField, 23, 9, 252, 3, // 216: check Inst[31:23] == 0x1fc |
| 22991 | OPC_Decode, 176, 19, 150, 4, // 221: decode to VFMSLDI using decoder 534 |
| 22992 | // 221: } |
| 22993 | 1, 0, // 226: case 0x1: { |
| 22994 | OPC_CheckPredicate, 91, // 228: check predicate 91 |
| 22995 | OPC_CheckField, 23, 9, 252, 3, // 230: check Inst[31:23] == 0x1fc |
| 22996 | OPC_Decode, 178, 19, 151, 4, // 235: decode to VFMSLQI using decoder 535 |
| 22997 | // 235: } |
| 22998 | // 235: } // switch Inst[6] |
| 22999 | // 235: } |
| 23000 | 2, 53, // 240: case 0x2: { |
| 23001 | OPC_SwitchField, 6, 1, // 242: switch Inst[6] { |
| 23002 | 0, 23, // 245: case 0x0: { |
| 23003 | OPC_SwitchField, 23, 9, // 247: switch Inst[31:23] { |
| 23004 | 248, 3, 7, // 250: case 0x1f8: { |
| 23005 | OPC_CheckPredicate, 91, // 253: check predicate 91 |
| 23006 | OPC_Decode, 164, 19, 152, 4, // 255: decode to VFMALD using decoder 536 |
| 23007 | // 255: } |
| 23008 | 249, 3, 0, // 260: case 0x1f9: { |
| 23009 | OPC_CheckPredicate, 91, // 263: check predicate 91 |
| 23010 | OPC_Decode, 175, 19, 152, 4, // 265: decode to VFMSLD using decoder 536 |
| 23011 | // 265: } |
| 23012 | // 265: } // switch Inst[31:23] |
| 23013 | // 265: } |
| 23014 | 1, 0, // 270: case 0x1: { |
| 23015 | OPC_SwitchField, 23, 9, // 272: switch Inst[31:23] { |
| 23016 | 248, 3, 7, // 275: case 0x1f8: { |
| 23017 | OPC_CheckPredicate, 91, // 278: check predicate 91 |
| 23018 | OPC_Decode, 166, 19, 132, 2, // 280: decode to VFMALQ using decoder 260 |
| 23019 | // 280: } |
| 23020 | 249, 3, 0, // 285: case 0x1f9: { |
| 23021 | OPC_CheckPredicate, 91, // 288: check predicate 91 |
| 23022 | OPC_Decode, 177, 19, 132, 2, // 290: decode to VFMSLQ using decoder 260 |
| 23023 | // 290: } |
| 23024 | // 290: } // switch Inst[31:23] |
| 23025 | // 290: } |
| 23026 | // 290: } // switch Inst[6] |
| 23027 | // 290: } |
| 23028 | 3, 0, // 295: case 0x3: { |
| 23029 | OPC_SwitchField, 6, 1, // 297: switch Inst[6] { |
| 23030 | 0, 23, // 300: case 0x0: { |
| 23031 | OPC_SwitchField, 23, 9, // 302: switch Inst[31:23] { |
| 23032 | 248, 3, 7, // 305: case 0x1f8: { |
| 23033 | OPC_CheckPredicate, 40, // 308: check predicate 40 |
| 23034 | OPC_Decode, 146, 17, 153, 4, // 310: decode to VBF16MALBQ using decoder 537 |
| 23035 | // 310: } |
| 23036 | 252, 3, 0, // 315: case 0x1fc: { |
| 23037 | OPC_CheckPredicate, 40, // 318: check predicate 40 |
| 23038 | OPC_Decode, 147, 17, 154, 4, // 320: decode to VBF16MALBQI using decoder 538 |
| 23039 | // 320: } |
| 23040 | // 320: } // switch Inst[31:23] |
| 23041 | // 320: } |
| 23042 | 1, 0, // 325: case 0x1: { |
| 23043 | OPC_SwitchField, 23, 9, // 327: switch Inst[31:23] { |
| 23044 | 248, 3, 7, // 330: case 0x1f8: { |
| 23045 | OPC_CheckPredicate, 40, // 333: check predicate 40 |
| 23046 | OPC_Decode, 148, 17, 153, 4, // 335: decode to VBF16MALTQ using decoder 537 |
| 23047 | // 335: } |
| 23048 | 252, 3, 0, // 340: case 0x1fc: { |
| 23049 | OPC_CheckPredicate, 40, // 343: check predicate 40 |
| 23050 | OPC_Decode, 149, 17, 154, 4, // 345: decode to VBF16MALTQI using decoder 538 |
| 23051 | // 345: } |
| 23052 | // 345: } // switch Inst[31:23] |
| 23053 | // 345: } |
| 23054 | // 345: } // switch Inst[6] |
| 23055 | // 345: } |
| 23056 | // 345: } // switch Inst[21:20] |
| 23057 | // 345: } |
| 23058 | // 345: } // switch Inst[4] |
| 23059 | // 345: } |
| 23060 | 9, 166, 3, // 350: case 0x9: { |
| 23061 | OPC_SwitchField, 20, 2, // 353: switch Inst[21:20] { |
| 23062 | 0, 54, // 356: case 0x0: { |
| 23063 | OPC_SwitchField, 6, 1, // 358: switch Inst[6] { |
| 23064 | 0, 31, // 361: case 0x0: { |
| 23065 | OPC_SwitchField, 23, 9, // 363: switch Inst[31:23] { |
| 23066 | 252, 3, 11, // 366: case 0x1fc: { |
| 23067 | OPC_CheckPredicate, 75, // 369: check predicate 75 |
| 23068 | OPC_CheckField, 4, 1, 0, // 371: check Inst[4] == 0x0 |
| 23069 | OPC_Decode, 183, 27, 155, 4, // 375: decode to VSELEQH using decoder 539 |
| 23070 | // 375: } |
| 23071 | 253, 3, 0, // 380: case 0x1fd: { |
| 23072 | OPC_CheckPredicate, 75, // 383: check predicate 75 |
| 23073 | OPC_CheckField, 4, 1, 0, // 385: check Inst[4] == 0x0 |
| 23074 | OPC_Decode, 191, 19, 155, 4, // 389: decode to VFP_VMAXNMH using decoder 539 |
| 23075 | // 389: } |
| 23076 | // 389: } // switch Inst[31:23] |
| 23077 | // 389: } |
| 23078 | 1, 0, // 394: case 0x1: { |
| 23079 | OPC_CheckPredicate, 75, // 396: check predicate 75 |
| 23080 | OPC_CheckField, 23, 9, 253, 3, // 398: check Inst[31:23] == 0x1fd |
| 23081 | OPC_CheckField, 4, 1, 0, // 403: check Inst[4] == 0x0 |
| 23082 | OPC_Decode, 194, 19, 155, 4, // 407: decode to VFP_VMINNMH using decoder 539 |
| 23083 | // 407: } |
| 23084 | // 407: } // switch Inst[6] |
| 23085 | // 407: } |
| 23086 | 1, 20, // 412: case 0x1: { |
| 23087 | OPC_CheckPredicate, 75, // 414: check predicate 75 |
| 23088 | OPC_CheckField, 23, 9, 252, 3, // 416: check Inst[31:23] == 0x1fc |
| 23089 | OPC_CheckField, 6, 1, 0, // 421: check Inst[6] == 0x0 |
| 23090 | OPC_CheckField, 4, 1, 0, // 425: check Inst[4] == 0x0 |
| 23091 | OPC_Decode, 192, 27, 155, 4, // 429: decode to VSELVSH using decoder 539 |
| 23092 | // 429: } |
| 23093 | 2, 20, // 434: case 0x2: { |
| 23094 | OPC_CheckPredicate, 75, // 436: check predicate 75 |
| 23095 | OPC_CheckField, 23, 9, 252, 3, // 438: check Inst[31:23] == 0x1fc |
| 23096 | OPC_CheckField, 6, 1, 0, // 443: check Inst[6] == 0x0 |
| 23097 | OPC_CheckField, 4, 1, 0, // 447: check Inst[4] == 0x0 |
| 23098 | OPC_Decode, 186, 27, 155, 4, // 451: decode to VSELGEH using decoder 539 |
| 23099 | // 451: } |
| 23100 | 3, 0, // 456: case 0x3: { |
| 23101 | OPC_SwitchField, 6, 1, // 458: switch Inst[6] { |
| 23102 | 0, 16, // 461: case 0x0: { |
| 23103 | OPC_CheckPredicate, 75, // 463: check predicate 75 |
| 23104 | OPC_CheckField, 23, 9, 252, 3, // 465: check Inst[31:23] == 0x1fc |
| 23105 | OPC_CheckField, 4, 1, 0, // 470: check Inst[4] == 0x0 |
| 23106 | OPC_Decode, 189, 27, 155, 4, // 474: decode to VSELGTH using decoder 539 |
| 23107 | // 474: } |
| 23108 | 1, 0, // 479: case 0x1: { |
| 23109 | OPC_SwitchField, 16, 4, // 481: switch Inst[19:16] { |
| 23110 | 3, 37, // 484: case 0x3: { |
| 23111 | OPC_SwitchField, 7, 1, // 486: switch Inst[7] { |
| 23112 | 0, 15, // 489: case 0x0: { |
| 23113 | OPC_CheckPredicate, 92, // 491: check predicate 92 |
| 23114 | OPC_CheckField, 23, 5, 29, // 493: check Inst[27:23] == 0x1d |
| 23115 | OPC_CheckField, 4, 1, 0, // 497: check Inst[4] == 0x0 |
| 23116 | OPC_Decode, 184, 6, 251, 3, // 501: decode to BF16_VCVTB using decoder 507 |
| 23117 | // 501: } |
| 23118 | 1, 0, // 506: case 0x1: { |
| 23119 | OPC_CheckPredicate, 92, // 508: check predicate 92 |
| 23120 | OPC_CheckField, 23, 5, 29, // 510: check Inst[27:23] == 0x1d |
| 23121 | OPC_CheckField, 4, 1, 0, // 514: check Inst[4] == 0x0 |
| 23122 | OPC_Decode, 185, 6, 251, 3, // 518: decode to BF16_VCVTT using decoder 507 |
| 23123 | // 518: } |
| 23124 | // 518: } // switch Inst[7] |
| 23125 | // 518: } |
| 23126 | 8, 20, // 523: case 0x8: { |
| 23127 | OPC_CheckPredicate, 75, // 525: check predicate 75 |
| 23128 | OPC_CheckField, 23, 9, 253, 3, // 527: check Inst[31:23] == 0x1fd |
| 23129 | OPC_CheckField, 7, 1, 0, // 532: check Inst[7] == 0x0 |
| 23130 | OPC_CheckField, 4, 1, 0, // 536: check Inst[4] == 0x0 |
| 23131 | OPC_Decode, 196, 26, 156, 4, // 540: decode to VRINTAH using decoder 540 |
| 23132 | // 540: } |
| 23133 | 9, 20, // 545: case 0x9: { |
| 23134 | OPC_CheckPredicate, 75, // 547: check predicate 75 |
| 23135 | OPC_CheckField, 23, 9, 253, 3, // 549: check Inst[31:23] == 0x1fd |
| 23136 | OPC_CheckField, 7, 1, 0, // 554: check Inst[7] == 0x0 |
| 23137 | OPC_CheckField, 4, 1, 0, // 558: check Inst[4] == 0x0 |
| 23138 | OPC_Decode, 210, 26, 156, 4, // 562: decode to VRINTNH using decoder 540 |
| 23139 | // 562: } |
| 23140 | 10, 20, // 567: case 0xa: { |
| 23141 | OPC_CheckPredicate, 75, // 569: check predicate 75 |
| 23142 | OPC_CheckField, 23, 9, 253, 3, // 571: check Inst[31:23] == 0x1fd |
| 23143 | OPC_CheckField, 7, 1, 0, // 576: check Inst[7] == 0x0 |
| 23144 | OPC_CheckField, 4, 1, 0, // 580: check Inst[4] == 0x0 |
| 23145 | OPC_Decode, 217, 26, 156, 4, // 584: decode to VRINTPH using decoder 540 |
| 23146 | // 584: } |
| 23147 | 11, 20, // 589: case 0xb: { |
| 23148 | OPC_CheckPredicate, 75, // 591: check predicate 75 |
| 23149 | OPC_CheckField, 23, 9, 253, 3, // 593: check Inst[31:23] == 0x1fd |
| 23150 | OPC_CheckField, 7, 1, 0, // 598: check Inst[7] == 0x0 |
| 23151 | OPC_CheckField, 4, 1, 0, // 602: check Inst[4] == 0x0 |
| 23152 | OPC_Decode, 203, 26, 156, 4, // 606: decode to VRINTMH using decoder 540 |
| 23153 | // 606: } |
| 23154 | 12, 39, // 611: case 0xc: { |
| 23155 | OPC_SwitchField, 7, 1, // 613: switch Inst[7] { |
| 23156 | 0, 16, // 616: case 0x0: { |
| 23157 | OPC_CheckPredicate, 75, // 618: check predicate 75 |
| 23158 | OPC_CheckField, 23, 9, 253, 3, // 620: check Inst[31:23] == 0x1fd |
| 23159 | OPC_CheckField, 4, 1, 0, // 625: check Inst[4] == 0x0 |
| 23160 | OPC_Decode, 178, 18, 157, 4, // 629: decode to VCVTAUH using decoder 541 |
| 23161 | // 629: } |
| 23162 | 1, 0, // 634: case 0x1: { |
| 23163 | OPC_CheckPredicate, 75, // 636: check predicate 75 |
| 23164 | OPC_CheckField, 23, 9, 253, 3, // 638: check Inst[31:23] == 0x1fd |
| 23165 | OPC_CheckField, 4, 1, 0, // 643: check Inst[4] == 0x0 |
| 23166 | OPC_Decode, 175, 18, 157, 4, // 647: decode to VCVTASH using decoder 541 |
| 23167 | // 647: } |
| 23168 | // 647: } // switch Inst[7] |
| 23169 | // 647: } |
| 23170 | 13, 39, // 652: case 0xd: { |
| 23171 | OPC_SwitchField, 7, 1, // 654: switch Inst[7] { |
| 23172 | 0, 16, // 657: case 0x0: { |
| 23173 | OPC_CheckPredicate, 75, // 659: check predicate 75 |
| 23174 | OPC_CheckField, 23, 9, 253, 3, // 661: check Inst[31:23] == 0x1fd |
| 23175 | OPC_CheckField, 4, 1, 0, // 666: check Inst[4] == 0x0 |
| 23176 | OPC_Decode, 211, 18, 157, 4, // 670: decode to VCVTNUH using decoder 541 |
| 23177 | // 670: } |
| 23178 | 1, 0, // 675: case 0x1: { |
| 23179 | OPC_CheckPredicate, 75, // 677: check predicate 75 |
| 23180 | OPC_CheckField, 23, 9, 253, 3, // 679: check Inst[31:23] == 0x1fd |
| 23181 | OPC_CheckField, 4, 1, 0, // 684: check Inst[4] == 0x0 |
| 23182 | OPC_Decode, 208, 18, 157, 4, // 688: decode to VCVTNSH using decoder 541 |
| 23183 | // 688: } |
| 23184 | // 688: } // switch Inst[7] |
| 23185 | // 688: } |
| 23186 | 14, 39, // 693: case 0xe: { |
| 23187 | OPC_SwitchField, 7, 1, // 695: switch Inst[7] { |
| 23188 | 0, 16, // 698: case 0x0: { |
| 23189 | OPC_CheckPredicate, 75, // 700: check predicate 75 |
| 23190 | OPC_CheckField, 23, 9, 253, 3, // 702: check Inst[31:23] == 0x1fd |
| 23191 | OPC_CheckField, 4, 1, 0, // 707: check Inst[4] == 0x0 |
| 23192 | OPC_Decode, 225, 18, 157, 4, // 711: decode to VCVTPUH using decoder 541 |
| 23193 | // 711: } |
| 23194 | 1, 0, // 716: case 0x1: { |
| 23195 | OPC_CheckPredicate, 75, // 718: check predicate 75 |
| 23196 | OPC_CheckField, 23, 9, 253, 3, // 720: check Inst[31:23] == 0x1fd |
| 23197 | OPC_CheckField, 4, 1, 0, // 725: check Inst[4] == 0x0 |
| 23198 | OPC_Decode, 222, 18, 157, 4, // 729: decode to VCVTPSH using decoder 541 |
| 23199 | // 729: } |
| 23200 | // 729: } // switch Inst[7] |
| 23201 | // 729: } |
| 23202 | 15, 0, // 734: case 0xf: { |
| 23203 | OPC_SwitchField, 7, 1, // 736: switch Inst[7] { |
| 23204 | 0, 16, // 739: case 0x0: { |
| 23205 | OPC_CheckPredicate, 75, // 741: check predicate 75 |
| 23206 | OPC_CheckField, 23, 9, 253, 3, // 743: check Inst[31:23] == 0x1fd |
| 23207 | OPC_CheckField, 4, 1, 0, // 748: check Inst[4] == 0x0 |
| 23208 | OPC_Decode, 197, 18, 157, 4, // 752: decode to VCVTMUH using decoder 541 |
| 23209 | // 752: } |
| 23210 | 1, 0, // 757: case 0x1: { |
| 23211 | OPC_CheckPredicate, 75, // 759: check predicate 75 |
| 23212 | OPC_CheckField, 23, 9, 253, 3, // 761: check Inst[31:23] == 0x1fd |
| 23213 | OPC_CheckField, 4, 1, 0, // 766: check Inst[4] == 0x0 |
| 23214 | OPC_Decode, 194, 18, 157, 4, // 770: decode to VCVTMSH using decoder 541 |
| 23215 | // 770: } |
| 23216 | // 770: } // switch Inst[7] |
| 23217 | // 770: } |
| 23218 | // 770: } // switch Inst[19:16] |
| 23219 | // 770: } |
| 23220 | // 770: } // switch Inst[6] |
| 23221 | // 770: } |
| 23222 | // 770: } // switch Inst[21:20] |
| 23223 | // 770: } |
| 23224 | 10, 168, 3, // 775: case 0xa: { |
| 23225 | OPC_SwitchField, 20, 2, // 778: switch Inst[21:20] { |
| 23226 | 0, 54, // 781: case 0x0: { |
| 23227 | OPC_SwitchField, 6, 1, // 783: switch Inst[6] { |
| 23228 | 0, 31, // 786: case 0x0: { |
| 23229 | OPC_SwitchField, 23, 9, // 788: switch Inst[31:23] { |
| 23230 | 252, 3, 11, // 791: case 0x1fc: { |
| 23231 | OPC_CheckPredicate, 82, // 794: check predicate 82 |
| 23232 | OPC_CheckField, 4, 1, 0, // 796: check Inst[4] == 0x0 |
| 23233 | OPC_Decode, 184, 27, 158, 4, // 800: decode to VSELEQS using decoder 542 |
| 23234 | // 800: } |
| 23235 | 253, 3, 0, // 805: case 0x1fd: { |
| 23236 | OPC_CheckPredicate, 82, // 808: check predicate 82 |
| 23237 | OPC_CheckField, 4, 1, 0, // 810: check Inst[4] == 0x0 |
| 23238 | OPC_Decode, 192, 19, 158, 4, // 814: decode to VFP_VMAXNMS using decoder 542 |
| 23239 | // 814: } |
| 23240 | // 814: } // switch Inst[31:23] |
| 23241 | // 814: } |
| 23242 | 1, 0, // 819: case 0x1: { |
| 23243 | OPC_CheckPredicate, 82, // 821: check predicate 82 |
| 23244 | OPC_CheckField, 23, 9, 253, 3, // 823: check Inst[31:23] == 0x1fd |
| 23245 | OPC_CheckField, 4, 1, 0, // 828: check Inst[4] == 0x0 |
| 23246 | OPC_Decode, 195, 19, 158, 4, // 832: decode to VFP_VMINNMS using decoder 542 |
| 23247 | // 832: } |
| 23248 | // 832: } // switch Inst[6] |
| 23249 | // 832: } |
| 23250 | 1, 20, // 837: case 0x1: { |
| 23251 | OPC_CheckPredicate, 82, // 839: check predicate 82 |
| 23252 | OPC_CheckField, 23, 9, 252, 3, // 841: check Inst[31:23] == 0x1fc |
| 23253 | OPC_CheckField, 6, 1, 0, // 846: check Inst[6] == 0x0 |
| 23254 | OPC_CheckField, 4, 1, 0, // 850: check Inst[4] == 0x0 |
| 23255 | OPC_Decode, 193, 27, 158, 4, // 854: decode to VSELVSS using decoder 542 |
| 23256 | // 854: } |
| 23257 | 2, 20, // 859: case 0x2: { |
| 23258 | OPC_CheckPredicate, 82, // 861: check predicate 82 |
| 23259 | OPC_CheckField, 23, 9, 252, 3, // 863: check Inst[31:23] == 0x1fc |
| 23260 | OPC_CheckField, 6, 1, 0, // 868: check Inst[6] == 0x0 |
| 23261 | OPC_CheckField, 4, 1, 0, // 872: check Inst[4] == 0x0 |
| 23262 | OPC_Decode, 187, 27, 158, 4, // 876: decode to VSELGES using decoder 542 |
| 23263 | // 876: } |
| 23264 | 3, 0, // 881: case 0x3: { |
| 23265 | OPC_SwitchField, 6, 1, // 883: switch Inst[6] { |
| 23266 | 0, 16, // 886: case 0x0: { |
| 23267 | OPC_CheckPredicate, 82, // 888: check predicate 82 |
| 23268 | OPC_CheckField, 23, 9, 252, 3, // 890: check Inst[31:23] == 0x1fc |
| 23269 | OPC_CheckField, 4, 1, 0, // 895: check Inst[4] == 0x0 |
| 23270 | OPC_Decode, 190, 27, 158, 4, // 899: decode to VSELGTS using decoder 542 |
| 23271 | // 899: } |
| 23272 | 1, 0, // 904: case 0x1: { |
| 23273 | OPC_SwitchField, 16, 4, // 906: switch Inst[19:16] { |
| 23274 | 0, 39, // 909: case 0x0: { |
| 23275 | OPC_SwitchField, 7, 1, // 911: switch Inst[7] { |
| 23276 | 0, 16, // 914: case 0x0: { |
| 23277 | OPC_CheckPredicate, 75, // 916: check predicate 75 |
| 23278 | OPC_CheckField, 23, 9, 253, 3, // 918: check Inst[31:23] == 0x1fd |
| 23279 | OPC_CheckField, 4, 1, 0, // 923: check Inst[4] == 0x0 |
| 23280 | OPC_Decode, 204, 23, 159, 4, // 927: decode to VMOVH using decoder 543 |
| 23281 | // 927: } |
| 23282 | 1, 0, // 932: case 0x1: { |
| 23283 | OPC_CheckPredicate, 75, // 934: check predicate 75 |
| 23284 | OPC_CheckField, 23, 9, 253, 3, // 936: check Inst[31:23] == 0x1fd |
| 23285 | OPC_CheckField, 4, 1, 0, // 941: check Inst[4] == 0x0 |
| 23286 | OPC_Decode, 225, 19, 160, 4, // 945: decode to VINSH using decoder 544 |
| 23287 | // 945: } |
| 23288 | // 945: } // switch Inst[7] |
| 23289 | // 945: } |
| 23290 | 8, 20, // 950: case 0x8: { |
| 23291 | OPC_CheckPredicate, 82, // 952: check predicate 82 |
| 23292 | OPC_CheckField, 23, 9, 253, 3, // 954: check Inst[31:23] == 0x1fd |
| 23293 | OPC_CheckField, 7, 1, 0, // 959: check Inst[7] == 0x0 |
| 23294 | OPC_CheckField, 4, 1, 0, // 963: check Inst[4] == 0x0 |
| 23295 | OPC_Decode, 201, 26, 159, 4, // 967: decode to VRINTAS using decoder 543 |
| 23296 | // 967: } |
| 23297 | 9, 20, // 972: case 0x9: { |
| 23298 | OPC_CheckPredicate, 82, // 974: check predicate 82 |
| 23299 | OPC_CheckField, 23, 9, 253, 3, // 976: check Inst[31:23] == 0x1fd |
| 23300 | OPC_CheckField, 7, 1, 0, // 981: check Inst[7] == 0x0 |
| 23301 | OPC_CheckField, 4, 1, 0, // 985: check Inst[4] == 0x0 |
| 23302 | OPC_Decode, 215, 26, 159, 4, // 989: decode to VRINTNS using decoder 543 |
| 23303 | // 989: } |
| 23304 | 10, 20, // 994: case 0xa: { |
| 23305 | OPC_CheckPredicate, 82, // 996: check predicate 82 |
| 23306 | OPC_CheckField, 23, 9, 253, 3, // 998: check Inst[31:23] == 0x1fd |
| 23307 | OPC_CheckField, 7, 1, 0, // 1003: check Inst[7] == 0x0 |
| 23308 | OPC_CheckField, 4, 1, 0, // 1007: check Inst[4] == 0x0 |
| 23309 | OPC_Decode, 222, 26, 159, 4, // 1011: decode to VRINTPS using decoder 543 |
| 23310 | // 1011: } |
| 23311 | 11, 20, // 1016: case 0xb: { |
| 23312 | OPC_CheckPredicate, 82, // 1018: check predicate 82 |
| 23313 | OPC_CheckField, 23, 9, 253, 3, // 1020: check Inst[31:23] == 0x1fd |
| 23314 | OPC_CheckField, 7, 1, 0, // 1025: check Inst[7] == 0x0 |
| 23315 | OPC_CheckField, 4, 1, 0, // 1029: check Inst[4] == 0x0 |
| 23316 | OPC_Decode, 208, 26, 159, 4, // 1033: decode to VRINTMS using decoder 543 |
| 23317 | // 1033: } |
| 23318 | 12, 39, // 1038: case 0xc: { |
| 23319 | OPC_SwitchField, 7, 1, // 1040: switch Inst[7] { |
| 23320 | 0, 16, // 1043: case 0x0: { |
| 23321 | OPC_CheckPredicate, 82, // 1045: check predicate 82 |
| 23322 | OPC_CheckField, 23, 9, 253, 3, // 1047: check Inst[31:23] == 0x1fd |
| 23323 | OPC_CheckField, 4, 1, 0, // 1052: check Inst[4] == 0x0 |
| 23324 | OPC_Decode, 179, 18, 159, 4, // 1056: decode to VCVTAUS using decoder 543 |
| 23325 | // 1056: } |
| 23326 | 1, 0, // 1061: case 0x1: { |
| 23327 | OPC_CheckPredicate, 82, // 1063: check predicate 82 |
| 23328 | OPC_CheckField, 23, 9, 253, 3, // 1065: check Inst[31:23] == 0x1fd |
| 23329 | OPC_CheckField, 4, 1, 0, // 1070: check Inst[4] == 0x0 |
| 23330 | OPC_Decode, 176, 18, 159, 4, // 1074: decode to VCVTASS using decoder 543 |
| 23331 | // 1074: } |
| 23332 | // 1074: } // switch Inst[7] |
| 23333 | // 1074: } |
| 23334 | 13, 39, // 1079: case 0xd: { |
| 23335 | OPC_SwitchField, 7, 1, // 1081: switch Inst[7] { |
| 23336 | 0, 16, // 1084: case 0x0: { |
| 23337 | OPC_CheckPredicate, 82, // 1086: check predicate 82 |
| 23338 | OPC_CheckField, 23, 9, 253, 3, // 1088: check Inst[31:23] == 0x1fd |
| 23339 | OPC_CheckField, 4, 1, 0, // 1093: check Inst[4] == 0x0 |
| 23340 | OPC_Decode, 212, 18, 159, 4, // 1097: decode to VCVTNUS using decoder 543 |
| 23341 | // 1097: } |
| 23342 | 1, 0, // 1102: case 0x1: { |
| 23343 | OPC_CheckPredicate, 82, // 1104: check predicate 82 |
| 23344 | OPC_CheckField, 23, 9, 253, 3, // 1106: check Inst[31:23] == 0x1fd |
| 23345 | OPC_CheckField, 4, 1, 0, // 1111: check Inst[4] == 0x0 |
| 23346 | OPC_Decode, 209, 18, 159, 4, // 1115: decode to VCVTNSS using decoder 543 |
| 23347 | // 1115: } |
| 23348 | // 1115: } // switch Inst[7] |
| 23349 | // 1115: } |
| 23350 | 14, 39, // 1120: case 0xe: { |
| 23351 | OPC_SwitchField, 7, 1, // 1122: switch Inst[7] { |
| 23352 | 0, 16, // 1125: case 0x0: { |
| 23353 | OPC_CheckPredicate, 82, // 1127: check predicate 82 |
| 23354 | OPC_CheckField, 23, 9, 253, 3, // 1129: check Inst[31:23] == 0x1fd |
| 23355 | OPC_CheckField, 4, 1, 0, // 1134: check Inst[4] == 0x0 |
| 23356 | OPC_Decode, 226, 18, 159, 4, // 1138: decode to VCVTPUS using decoder 543 |
| 23357 | // 1138: } |
| 23358 | 1, 0, // 1143: case 0x1: { |
| 23359 | OPC_CheckPredicate, 82, // 1145: check predicate 82 |
| 23360 | OPC_CheckField, 23, 9, 253, 3, // 1147: check Inst[31:23] == 0x1fd |
| 23361 | OPC_CheckField, 4, 1, 0, // 1152: check Inst[4] == 0x0 |
| 23362 | OPC_Decode, 223, 18, 159, 4, // 1156: decode to VCVTPSS using decoder 543 |
| 23363 | // 1156: } |
| 23364 | // 1156: } // switch Inst[7] |
| 23365 | // 1156: } |
| 23366 | 15, 0, // 1161: case 0xf: { |
| 23367 | OPC_SwitchField, 7, 1, // 1163: switch Inst[7] { |
| 23368 | 0, 16, // 1166: case 0x0: { |
| 23369 | OPC_CheckPredicate, 82, // 1168: check predicate 82 |
| 23370 | OPC_CheckField, 23, 9, 253, 3, // 1170: check Inst[31:23] == 0x1fd |
| 23371 | OPC_CheckField, 4, 1, 0, // 1175: check Inst[4] == 0x0 |
| 23372 | OPC_Decode, 198, 18, 159, 4, // 1179: decode to VCVTMUS using decoder 543 |
| 23373 | // 1179: } |
| 23374 | 1, 0, // 1184: case 0x1: { |
| 23375 | OPC_CheckPredicate, 82, // 1186: check predicate 82 |
| 23376 | OPC_CheckField, 23, 9, 253, 3, // 1188: check Inst[31:23] == 0x1fd |
| 23377 | OPC_CheckField, 4, 1, 0, // 1193: check Inst[4] == 0x0 |
| 23378 | OPC_Decode, 195, 18, 159, 4, // 1197: decode to VCVTMSS using decoder 543 |
| 23379 | // 1197: } |
| 23380 | // 1197: } // switch Inst[7] |
| 23381 | // 1197: } |
| 23382 | // 1197: } // switch Inst[19:16] |
| 23383 | // 1197: } |
| 23384 | // 1197: } // switch Inst[6] |
| 23385 | // 1197: } |
| 23386 | // 1197: } // switch Inst[21:20] |
| 23387 | // 1197: } |
| 23388 | 11, 255, 2, // 1202: case 0xb: { |
| 23389 | OPC_SwitchField, 20, 2, // 1205: switch Inst[21:20] { |
| 23390 | 0, 54, // 1208: case 0x0: { |
| 23391 | OPC_SwitchField, 6, 1, // 1210: switch Inst[6] { |
| 23392 | 0, 31, // 1213: case 0x0: { |
| 23393 | OPC_SwitchField, 23, 9, // 1215: switch Inst[31:23] { |
| 23394 | 252, 3, 11, // 1218: case 0x1fc: { |
| 23395 | OPC_CheckPredicate, 87, // 1221: check predicate 87 |
| 23396 | OPC_CheckField, 4, 1, 0, // 1223: check Inst[4] == 0x0 |
| 23397 | OPC_Decode, 182, 27, 161, 4, // 1227: decode to VSELEQD using decoder 545 |
| 23398 | // 1227: } |
| 23399 | 253, 3, 0, // 1232: case 0x1fd: { |
| 23400 | OPC_CheckPredicate, 87, // 1235: check predicate 87 |
| 23401 | OPC_CheckField, 4, 1, 0, // 1237: check Inst[4] == 0x0 |
| 23402 | OPC_Decode, 190, 19, 161, 4, // 1241: decode to VFP_VMAXNMD using decoder 545 |
| 23403 | // 1241: } |
| 23404 | // 1241: } // switch Inst[31:23] |
| 23405 | // 1241: } |
| 23406 | 1, 0, // 1246: case 0x1: { |
| 23407 | OPC_CheckPredicate, 87, // 1248: check predicate 87 |
| 23408 | OPC_CheckField, 23, 9, 253, 3, // 1250: check Inst[31:23] == 0x1fd |
| 23409 | OPC_CheckField, 4, 1, 0, // 1255: check Inst[4] == 0x0 |
| 23410 | OPC_Decode, 193, 19, 161, 4, // 1259: decode to VFP_VMINNMD using decoder 545 |
| 23411 | // 1259: } |
| 23412 | // 1259: } // switch Inst[6] |
| 23413 | // 1259: } |
| 23414 | 1, 20, // 1264: case 0x1: { |
| 23415 | OPC_CheckPredicate, 87, // 1266: check predicate 87 |
| 23416 | OPC_CheckField, 23, 9, 252, 3, // 1268: check Inst[31:23] == 0x1fc |
| 23417 | OPC_CheckField, 6, 1, 0, // 1273: check Inst[6] == 0x0 |
| 23418 | OPC_CheckField, 4, 1, 0, // 1277: check Inst[4] == 0x0 |
| 23419 | OPC_Decode, 191, 27, 161, 4, // 1281: decode to VSELVSD using decoder 545 |
| 23420 | // 1281: } |
| 23421 | 2, 20, // 1286: case 0x2: { |
| 23422 | OPC_CheckPredicate, 87, // 1288: check predicate 87 |
| 23423 | OPC_CheckField, 23, 9, 252, 3, // 1290: check Inst[31:23] == 0x1fc |
| 23424 | OPC_CheckField, 6, 1, 0, // 1295: check Inst[6] == 0x0 |
| 23425 | OPC_CheckField, 4, 1, 0, // 1299: check Inst[4] == 0x0 |
| 23426 | OPC_Decode, 185, 27, 161, 4, // 1303: decode to VSELGED using decoder 545 |
| 23427 | // 1303: } |
| 23428 | 3, 0, // 1308: case 0x3: { |
| 23429 | OPC_SwitchField, 6, 1, // 1310: switch Inst[6] { |
| 23430 | 0, 16, // 1313: case 0x0: { |
| 23431 | OPC_CheckPredicate, 87, // 1315: check predicate 87 |
| 23432 | OPC_CheckField, 23, 9, 252, 3, // 1317: check Inst[31:23] == 0x1fc |
| 23433 | OPC_CheckField, 4, 1, 0, // 1322: check Inst[4] == 0x0 |
| 23434 | OPC_Decode, 188, 27, 161, 4, // 1326: decode to VSELGTD using decoder 545 |
| 23435 | // 1326: } |
| 23436 | 1, 0, // 1331: case 0x1: { |
| 23437 | OPC_SwitchField, 16, 4, // 1333: switch Inst[19:16] { |
| 23438 | 8, 20, // 1336: case 0x8: { |
| 23439 | OPC_CheckPredicate, 87, // 1338: check predicate 87 |
| 23440 | OPC_CheckField, 23, 9, 253, 3, // 1340: check Inst[31:23] == 0x1fd |
| 23441 | OPC_CheckField, 7, 1, 0, // 1345: check Inst[7] == 0x0 |
| 23442 | OPC_CheckField, 4, 1, 0, // 1349: check Inst[4] == 0x0 |
| 23443 | OPC_Decode, 195, 26, 162, 4, // 1353: decode to VRINTAD using decoder 546 |
| 23444 | // 1353: } |
| 23445 | 9, 20, // 1358: case 0x9: { |
| 23446 | OPC_CheckPredicate, 87, // 1360: check predicate 87 |
| 23447 | OPC_CheckField, 23, 9, 253, 3, // 1362: check Inst[31:23] == 0x1fd |
| 23448 | OPC_CheckField, 7, 1, 0, // 1367: check Inst[7] == 0x0 |
| 23449 | OPC_CheckField, 4, 1, 0, // 1371: check Inst[4] == 0x0 |
| 23450 | OPC_Decode, 209, 26, 162, 4, // 1375: decode to VRINTND using decoder 546 |
| 23451 | // 1375: } |
| 23452 | 10, 20, // 1380: case 0xa: { |
| 23453 | OPC_CheckPredicate, 87, // 1382: check predicate 87 |
| 23454 | OPC_CheckField, 23, 9, 253, 3, // 1384: check Inst[31:23] == 0x1fd |
| 23455 | OPC_CheckField, 7, 1, 0, // 1389: check Inst[7] == 0x0 |
| 23456 | OPC_CheckField, 4, 1, 0, // 1393: check Inst[4] == 0x0 |
| 23457 | OPC_Decode, 216, 26, 162, 4, // 1397: decode to VRINTPD using decoder 546 |
| 23458 | // 1397: } |
| 23459 | 11, 20, // 1402: case 0xb: { |
| 23460 | OPC_CheckPredicate, 87, // 1404: check predicate 87 |
| 23461 | OPC_CheckField, 23, 9, 253, 3, // 1406: check Inst[31:23] == 0x1fd |
| 23462 | OPC_CheckField, 7, 1, 0, // 1411: check Inst[7] == 0x0 |
| 23463 | OPC_CheckField, 4, 1, 0, // 1415: check Inst[4] == 0x0 |
| 23464 | OPC_Decode, 202, 26, 162, 4, // 1419: decode to VRINTMD using decoder 546 |
| 23465 | // 1419: } |
| 23466 | 12, 39, // 1424: case 0xc: { |
| 23467 | OPC_SwitchField, 7, 1, // 1426: switch Inst[7] { |
| 23468 | 0, 16, // 1429: case 0x0: { |
| 23469 | OPC_CheckPredicate, 87, // 1431: check predicate 87 |
| 23470 | OPC_CheckField, 23, 9, 253, 3, // 1433: check Inst[31:23] == 0x1fd |
| 23471 | OPC_CheckField, 4, 1, 0, // 1438: check Inst[4] == 0x0 |
| 23472 | OPC_Decode, 177, 18, 163, 4, // 1442: decode to VCVTAUD using decoder 547 |
| 23473 | // 1442: } |
| 23474 | 1, 0, // 1447: case 0x1: { |
| 23475 | OPC_CheckPredicate, 87, // 1449: check predicate 87 |
| 23476 | OPC_CheckField, 23, 9, 253, 3, // 1451: check Inst[31:23] == 0x1fd |
| 23477 | OPC_CheckField, 4, 1, 0, // 1456: check Inst[4] == 0x0 |
| 23478 | OPC_Decode, 174, 18, 163, 4, // 1460: decode to VCVTASD using decoder 547 |
| 23479 | // 1460: } |
| 23480 | // 1460: } // switch Inst[7] |
| 23481 | // 1460: } |
| 23482 | 13, 39, // 1465: case 0xd: { |
| 23483 | OPC_SwitchField, 7, 1, // 1467: switch Inst[7] { |
| 23484 | 0, 16, // 1470: case 0x0: { |
| 23485 | OPC_CheckPredicate, 87, // 1472: check predicate 87 |
| 23486 | OPC_CheckField, 23, 9, 253, 3, // 1474: check Inst[31:23] == 0x1fd |
| 23487 | OPC_CheckField, 4, 1, 0, // 1479: check Inst[4] == 0x0 |
| 23488 | OPC_Decode, 210, 18, 163, 4, // 1483: decode to VCVTNUD using decoder 547 |
| 23489 | // 1483: } |
| 23490 | 1, 0, // 1488: case 0x1: { |
| 23491 | OPC_CheckPredicate, 87, // 1490: check predicate 87 |
| 23492 | OPC_CheckField, 23, 9, 253, 3, // 1492: check Inst[31:23] == 0x1fd |
| 23493 | OPC_CheckField, 4, 1, 0, // 1497: check Inst[4] == 0x0 |
| 23494 | OPC_Decode, 207, 18, 163, 4, // 1501: decode to VCVTNSD using decoder 547 |
| 23495 | // 1501: } |
| 23496 | // 1501: } // switch Inst[7] |
| 23497 | // 1501: } |
| 23498 | 14, 39, // 1506: case 0xe: { |
| 23499 | OPC_SwitchField, 7, 1, // 1508: switch Inst[7] { |
| 23500 | 0, 16, // 1511: case 0x0: { |
| 23501 | OPC_CheckPredicate, 87, // 1513: check predicate 87 |
| 23502 | OPC_CheckField, 23, 9, 253, 3, // 1515: check Inst[31:23] == 0x1fd |
| 23503 | OPC_CheckField, 4, 1, 0, // 1520: check Inst[4] == 0x0 |
| 23504 | OPC_Decode, 224, 18, 163, 4, // 1524: decode to VCVTPUD using decoder 547 |
| 23505 | // 1524: } |
| 23506 | 1, 0, // 1529: case 0x1: { |
| 23507 | OPC_CheckPredicate, 87, // 1531: check predicate 87 |
| 23508 | OPC_CheckField, 23, 9, 253, 3, // 1533: check Inst[31:23] == 0x1fd |
| 23509 | OPC_CheckField, 4, 1, 0, // 1538: check Inst[4] == 0x0 |
| 23510 | OPC_Decode, 221, 18, 163, 4, // 1542: decode to VCVTPSD using decoder 547 |
| 23511 | // 1542: } |
| 23512 | // 1542: } // switch Inst[7] |
| 23513 | // 1542: } |
| 23514 | 15, 0, // 1547: case 0xf: { |
| 23515 | OPC_SwitchField, 7, 1, // 1549: switch Inst[7] { |
| 23516 | 0, 16, // 1552: case 0x0: { |
| 23517 | OPC_CheckPredicate, 87, // 1554: check predicate 87 |
| 23518 | OPC_CheckField, 23, 9, 253, 3, // 1556: check Inst[31:23] == 0x1fd |
| 23519 | OPC_CheckField, 4, 1, 0, // 1561: check Inst[4] == 0x0 |
| 23520 | OPC_Decode, 196, 18, 163, 4, // 1565: decode to VCVTMUD using decoder 547 |
| 23521 | // 1565: } |
| 23522 | 1, 0, // 1570: case 0x1: { |
| 23523 | OPC_CheckPredicate, 87, // 1572: check predicate 87 |
| 23524 | OPC_CheckField, 23, 9, 253, 3, // 1574: check Inst[31:23] == 0x1fd |
| 23525 | OPC_CheckField, 4, 1, 0, // 1579: check Inst[4] == 0x0 |
| 23526 | OPC_Decode, 193, 18, 163, 4, // 1583: decode to VCVTMSD using decoder 547 |
| 23527 | // 1583: } |
| 23528 | // 1583: } // switch Inst[7] |
| 23529 | // 1583: } |
| 23530 | // 1583: } // switch Inst[19:16] |
| 23531 | // 1583: } |
| 23532 | // 1583: } // switch Inst[6] |
| 23533 | // 1583: } |
| 23534 | // 1583: } // switch Inst[21:20] |
| 23535 | // 1583: } |
| 23536 | 12, 81, // 1588: case 0xc: { |
| 23537 | OPC_SwitchField, 4, 1, // 1590: switch Inst[4] { |
| 23538 | 0, 54, // 1593: case 0x0: { |
| 23539 | OPC_SwitchField, 20, 2, // 1595: switch Inst[21:20] { |
| 23540 | 0, 16, // 1598: case 0x0: { |
| 23541 | OPC_CheckPredicate, 40, // 1600: check predicate 40 |
| 23542 | OPC_CheckField, 23, 9, 248, 3, // 1602: check Inst[31:23] == 0x1f8 |
| 23543 | OPC_CheckField, 6, 1, 1, // 1607: check Inst[6] == 0x1 |
| 23544 | OPC_Decode, 201, 23, 153, 4, // 1611: decode to VMMLA using decoder 537 |
| 23545 | // 1611: } |
| 23546 | 2, 0, // 1616: case 0x2: { |
| 23547 | OPC_SwitchField, 23, 9, // 1618: switch Inst[31:23] { |
| 23548 | 248, 3, 11, // 1621: case 0x1f8: { |
| 23549 | OPC_CheckPredicate, 93, // 1624: check predicate 93 |
| 23550 | OPC_CheckField, 6, 1, 1, // 1626: check Inst[6] == 0x1 |
| 23551 | OPC_Decode, 138, 28, 153, 4, // 1630: decode to VSMMLA using decoder 537 |
| 23552 | // 1630: } |
| 23553 | 249, 3, 0, // 1635: case 0x1f9: { |
| 23554 | OPC_CheckPredicate, 93, // 1638: check predicate 93 |
| 23555 | OPC_CheckField, 6, 1, 1, // 1640: check Inst[6] == 0x1 |
| 23556 | OPC_Decode, 168, 31, 153, 4, // 1644: decode to VUSMMLA using decoder 537 |
| 23557 | // 1644: } |
| 23558 | // 1644: } // switch Inst[31:23] |
| 23559 | // 1644: } |
| 23560 | // 1644: } // switch Inst[21:20] |
| 23561 | // 1644: } |
| 23562 | 1, 0, // 1649: case 0x1: { |
| 23563 | OPC_CheckPredicate, 93, // 1651: check predicate 93 |
| 23564 | OPC_CheckField, 23, 9, 248, 3, // 1653: check Inst[31:23] == 0x1f8 |
| 23565 | OPC_CheckField, 20, 2, 2, // 1658: check Inst[21:20] == 0x2 |
| 23566 | OPC_CheckField, 6, 1, 1, // 1662: check Inst[6] == 0x1 |
| 23567 | OPC_Decode, 163, 31, 153, 4, // 1666: decode to VUMMLA using decoder 537 |
| 23568 | // 1666: } |
| 23569 | // 1666: } // switch Inst[4] |
| 23570 | // 1666: } |
| 23571 | 13, 0, // 1671: case 0xd: { |
| 23572 | OPC_SwitchField, 23, 9, // 1673: switch Inst[31:23] { |
| 23573 | 248, 3, 85, // 1676: case 0x1f8: { |
| 23574 | OPC_SwitchField, 4, 1, // 1679: switch Inst[4] { |
| 23575 | 0, 49, // 1682: case 0x0: { |
| 23576 | OPC_SwitchField, 6, 1, // 1684: switch Inst[6] { |
| 23577 | 0, 21, // 1687: case 0x0: { |
| 23578 | OPC_SwitchField, 20, 2, // 1689: switch Inst[21:20] { |
| 23579 | 0, 7, // 1692: case 0x0: { |
| 23580 | OPC_CheckPredicate, 40, // 1694: check predicate 40 |
| 23581 | OPC_Decode, 181, 6, 164, 4, // 1696: decode to BF16VDOTS_VDOTD using decoder 548 |
| 23582 | // 1696: } |
| 23583 | 2, 0, // 1701: case 0x2: { |
| 23584 | OPC_CheckPredicate, 94, // 1703: check predicate 94 |
| 23585 | OPC_Decode, 178, 27, 164, 4, // 1705: decode to VSDOTD using decoder 548 |
| 23586 | // 1705: } |
| 23587 | // 1705: } // switch Inst[21:20] |
| 23588 | // 1705: } |
| 23589 | 1, 0, // 1710: case 0x1: { |
| 23590 | OPC_SwitchField, 20, 2, // 1712: switch Inst[21:20] { |
| 23591 | 0, 7, // 1715: case 0x0: { |
| 23592 | OPC_CheckPredicate, 40, // 1717: check predicate 40 |
| 23593 | OPC_Decode, 182, 6, 153, 4, // 1719: decode to BF16VDOTS_VDOTQ using decoder 537 |
| 23594 | // 1719: } |
| 23595 | 2, 0, // 1724: case 0x2: { |
| 23596 | OPC_CheckPredicate, 94, // 1726: check predicate 94 |
| 23597 | OPC_Decode, 180, 27, 153, 4, // 1728: decode to VSDOTQ using decoder 537 |
| 23598 | // 1728: } |
| 23599 | // 1728: } // switch Inst[21:20] |
| 23600 | // 1728: } |
| 23601 | // 1728: } // switch Inst[6] |
| 23602 | // 1728: } |
| 23603 | 1, 0, // 1733: case 0x1: { |
| 23604 | OPC_SwitchField, 6, 1, // 1735: switch Inst[6] { |
| 23605 | 0, 11, // 1738: case 0x0: { |
| 23606 | OPC_CheckPredicate, 94, // 1740: check predicate 94 |
| 23607 | OPC_CheckField, 20, 2, 2, // 1742: check Inst[21:20] == 0x2 |
| 23608 | OPC_Decode, 150, 31, 164, 4, // 1746: decode to VUDOTD using decoder 548 |
| 23609 | // 1746: } |
| 23610 | 1, 0, // 1751: case 0x1: { |
| 23611 | OPC_CheckPredicate, 94, // 1753: check predicate 94 |
| 23612 | OPC_CheckField, 20, 2, 2, // 1755: check Inst[21:20] == 0x2 |
| 23613 | OPC_Decode, 152, 31, 153, 4, // 1759: decode to VUDOTQ using decoder 537 |
| 23614 | // 1759: } |
| 23615 | // 1759: } // switch Inst[6] |
| 23616 | // 1759: } |
| 23617 | // 1759: } // switch Inst[4] |
| 23618 | // 1759: } |
| 23619 | 249, 3, 37, // 1764: case 0x1f9: { |
| 23620 | OPC_SwitchField, 6, 1, // 1767: switch Inst[6] { |
| 23621 | 0, 15, // 1770: case 0x0: { |
| 23622 | OPC_CheckPredicate, 93, // 1772: check predicate 93 |
| 23623 | OPC_CheckField, 20, 2, 2, // 1774: check Inst[21:20] == 0x2 |
| 23624 | OPC_CheckField, 4, 1, 0, // 1778: check Inst[4] == 0x0 |
| 23625 | OPC_Decode, 164, 31, 164, 4, // 1782: decode to VUSDOTD using decoder 548 |
| 23626 | // 1782: } |
| 23627 | 1, 0, // 1787: case 0x1: { |
| 23628 | OPC_CheckPredicate, 93, // 1789: check predicate 93 |
| 23629 | OPC_CheckField, 20, 2, 2, // 1791: check Inst[21:20] == 0x2 |
| 23630 | OPC_CheckField, 4, 1, 0, // 1795: check Inst[4] == 0x0 |
| 23631 | OPC_Decode, 166, 31, 153, 4, // 1799: decode to VUSDOTQ using decoder 537 |
| 23632 | // 1799: } |
| 23633 | // 1799: } // switch Inst[6] |
| 23634 | // 1799: } |
| 23635 | 252, 3, 85, // 1804: case 0x1fc: { |
| 23636 | OPC_SwitchField, 4, 1, // 1807: switch Inst[4] { |
| 23637 | 0, 49, // 1810: case 0x0: { |
| 23638 | OPC_SwitchField, 6, 1, // 1812: switch Inst[6] { |
| 23639 | 0, 21, // 1815: case 0x0: { |
| 23640 | OPC_SwitchField, 20, 2, // 1817: switch Inst[21:20] { |
| 23641 | 0, 7, // 1820: case 0x0: { |
| 23642 | OPC_CheckPredicate, 40, // 1822: check predicate 40 |
| 23643 | OPC_Decode, 179, 6, 165, 4, // 1824: decode to BF16VDOTI_VDOTD using decoder 549 |
| 23644 | // 1824: } |
| 23645 | 2, 0, // 1829: case 0x2: { |
| 23646 | OPC_CheckPredicate, 94, // 1831: check predicate 94 |
| 23647 | OPC_Decode, 179, 27, 165, 4, // 1833: decode to VSDOTDI using decoder 549 |
| 23648 | // 1833: } |
| 23649 | // 1833: } // switch Inst[21:20] |
| 23650 | // 1833: } |
| 23651 | 1, 0, // 1838: case 0x1: { |
| 23652 | OPC_SwitchField, 20, 2, // 1840: switch Inst[21:20] { |
| 23653 | 0, 7, // 1843: case 0x0: { |
| 23654 | OPC_CheckPredicate, 40, // 1845: check predicate 40 |
| 23655 | OPC_Decode, 180, 6, 166, 4, // 1847: decode to BF16VDOTI_VDOTQ using decoder 550 |
| 23656 | // 1847: } |
| 23657 | 2, 0, // 1852: case 0x2: { |
| 23658 | OPC_CheckPredicate, 94, // 1854: check predicate 94 |
| 23659 | OPC_Decode, 181, 27, 166, 4, // 1856: decode to VSDOTQI using decoder 550 |
| 23660 | // 1856: } |
| 23661 | // 1856: } // switch Inst[21:20] |
| 23662 | // 1856: } |
| 23663 | // 1856: } // switch Inst[6] |
| 23664 | // 1856: } |
| 23665 | 1, 0, // 1861: case 0x1: { |
| 23666 | OPC_SwitchField, 6, 1, // 1863: switch Inst[6] { |
| 23667 | 0, 11, // 1866: case 0x0: { |
| 23668 | OPC_CheckPredicate, 94, // 1868: check predicate 94 |
| 23669 | OPC_CheckField, 20, 2, 2, // 1870: check Inst[21:20] == 0x2 |
| 23670 | OPC_Decode, 151, 31, 165, 4, // 1874: decode to VUDOTDI using decoder 549 |
| 23671 | // 1874: } |
| 23672 | 1, 0, // 1879: case 0x1: { |
| 23673 | OPC_CheckPredicate, 94, // 1881: check predicate 94 |
| 23674 | OPC_CheckField, 20, 2, 2, // 1883: check Inst[21:20] == 0x2 |
| 23675 | OPC_Decode, 153, 31, 166, 4, // 1887: decode to VUDOTQI using decoder 550 |
| 23676 | // 1887: } |
| 23677 | // 1887: } // switch Inst[6] |
| 23678 | // 1887: } |
| 23679 | // 1887: } // switch Inst[4] |
| 23680 | // 1887: } |
| 23681 | 253, 3, 0, // 1892: case 0x1fd: { |
| 23682 | OPC_SwitchField, 4, 1, // 1895: switch Inst[4] { |
| 23683 | 0, 29, // 1898: case 0x0: { |
| 23684 | OPC_SwitchField, 6, 1, // 1900: switch Inst[6] { |
| 23685 | 0, 11, // 1903: case 0x0: { |
| 23686 | OPC_CheckPredicate, 93, // 1905: check predicate 93 |
| 23687 | OPC_CheckField, 20, 2, 0, // 1907: check Inst[21:20] == 0x0 |
| 23688 | OPC_Decode, 165, 31, 165, 4, // 1911: decode to VUSDOTDI using decoder 549 |
| 23689 | // 1911: } |
| 23690 | 1, 0, // 1916: case 0x1: { |
| 23691 | OPC_CheckPredicate, 93, // 1918: check predicate 93 |
| 23692 | OPC_CheckField, 20, 2, 0, // 1920: check Inst[21:20] == 0x0 |
| 23693 | OPC_Decode, 167, 31, 166, 4, // 1924: decode to VUSDOTQI using decoder 550 |
| 23694 | // 1924: } |
| 23695 | // 1924: } // switch Inst[6] |
| 23696 | // 1924: } |
| 23697 | 1, 0, // 1929: case 0x1: { |
| 23698 | OPC_SwitchField, 6, 1, // 1931: switch Inst[6] { |
| 23699 | 0, 11, // 1934: case 0x0: { |
| 23700 | OPC_CheckPredicate, 93, // 1936: check predicate 93 |
| 23701 | OPC_CheckField, 20, 2, 0, // 1938: check Inst[21:20] == 0x0 |
| 23702 | OPC_Decode, 226, 30, 165, 4, // 1942: decode to VSUDOTDI using decoder 549 |
| 23703 | // 1942: } |
| 23704 | 1, 0, // 1947: case 0x1: { |
| 23705 | OPC_CheckPredicate, 93, // 1949: check predicate 93 |
| 23706 | OPC_CheckField, 20, 2, 0, // 1951: check Inst[21:20] == 0x0 |
| 23707 | OPC_Decode, 227, 30, 166, 4, // 1955: decode to VSUDOTQI using decoder 550 |
| 23708 | // 1955: } |
| 23709 | // 1955: } // switch Inst[6] |
| 23710 | // 1955: } |
| 23711 | // 1955: } // switch Inst[4] |
| 23712 | // 1955: } |
| 23713 | // 1955: } // switch Inst[31:23] |
| 23714 | // 1955: } |
| 23715 | // 1955: } // switch Inst[11:8] |
| 23716 | }; |
| 23717 | static const uint8_t DecoderTablev8Crypto32[335] = { |
| 23718 | OPC_SwitchField, 20, 2, // 0: switch Inst[21:20] { |
| 23719 | 0, 47, // 3: case 0x0: { |
| 23720 | OPC_SwitchField, 23, 9, // 5: switch Inst[31:23] { |
| 23721 | 228, 3, 19, // 8: case 0x1e4: { |
| 23722 | OPC_CheckPredicate, 95, // 11: check predicate 95 |
| 23723 | OPC_CheckField, 8, 4, 12, // 13: check Inst[11:8] == 0xc |
| 23724 | OPC_CheckField, 6, 1, 1, // 17: check Inst[6] == 0x1 |
| 23725 | OPC_CheckField, 4, 1, 0, // 21: check Inst[4] == 0x0 |
| 23726 | OPC_Decode, 255, 14, 153, 4, // 25: decode to SHA1C using decoder 537 |
| 23727 | // 25: } |
| 23728 | 230, 3, 0, // 30: case 0x1e6: { |
| 23729 | OPC_CheckPredicate, 95, // 33: check predicate 95 |
| 23730 | OPC_CheckField, 8, 4, 12, // 35: check Inst[11:8] == 0xc |
| 23731 | OPC_CheckField, 6, 1, 1, // 39: check Inst[6] == 0x1 |
| 23732 | OPC_CheckField, 4, 1, 0, // 43: check Inst[4] == 0x0 |
| 23733 | OPC_Decode, 133, 15, 153, 4, // 47: decode to SHA256H using decoder 537 |
| 23734 | // 47: } |
| 23735 | // 47: } // switch Inst[31:23] |
| 23736 | // 47: } |
| 23737 | 1, 47, // 52: case 0x1: { |
| 23738 | OPC_SwitchField, 23, 9, // 54: switch Inst[31:23] { |
| 23739 | 228, 3, 19, // 57: case 0x1e4: { |
| 23740 | OPC_CheckPredicate, 95, // 60: check predicate 95 |
| 23741 | OPC_CheckField, 8, 4, 12, // 62: check Inst[11:8] == 0xc |
| 23742 | OPC_CheckField, 6, 1, 1, // 66: check Inst[6] == 0x1 |
| 23743 | OPC_CheckField, 4, 1, 0, // 70: check Inst[4] == 0x0 |
| 23744 | OPC_Decode, 130, 15, 153, 4, // 74: decode to SHA1P using decoder 537 |
| 23745 | // 74: } |
| 23746 | 230, 3, 0, // 79: case 0x1e6: { |
| 23747 | OPC_CheckPredicate, 95, // 82: check predicate 95 |
| 23748 | OPC_CheckField, 8, 4, 12, // 84: check Inst[11:8] == 0xc |
| 23749 | OPC_CheckField, 6, 1, 1, // 88: check Inst[6] == 0x1 |
| 23750 | OPC_CheckField, 4, 1, 0, // 92: check Inst[4] == 0x0 |
| 23751 | OPC_Decode, 134, 15, 153, 4, // 96: decode to SHA256H2 using decoder 537 |
| 23752 | // 96: } |
| 23753 | // 96: } // switch Inst[31:23] |
| 23754 | // 96: } |
| 23755 | 2, 47, // 101: case 0x2: { |
| 23756 | OPC_SwitchField, 23, 9, // 103: switch Inst[31:23] { |
| 23757 | 228, 3, 19, // 106: case 0x1e4: { |
| 23758 | OPC_CheckPredicate, 95, // 109: check predicate 95 |
| 23759 | OPC_CheckField, 8, 4, 12, // 111: check Inst[11:8] == 0xc |
| 23760 | OPC_CheckField, 6, 1, 1, // 115: check Inst[6] == 0x1 |
| 23761 | OPC_CheckField, 4, 1, 0, // 119: check Inst[4] == 0x0 |
| 23762 | OPC_Decode, 129, 15, 153, 4, // 123: decode to SHA1M using decoder 537 |
| 23763 | // 123: } |
| 23764 | 230, 3, 0, // 128: case 0x1e6: { |
| 23765 | OPC_CheckPredicate, 95, // 131: check predicate 95 |
| 23766 | OPC_CheckField, 8, 4, 12, // 133: check Inst[11:8] == 0xc |
| 23767 | OPC_CheckField, 6, 1, 1, // 137: check Inst[6] == 0x1 |
| 23768 | OPC_CheckField, 4, 1, 0, // 141: check Inst[4] == 0x0 |
| 23769 | OPC_Decode, 136, 15, 153, 4, // 145: decode to SHA256SU1 using decoder 537 |
| 23770 | // 145: } |
| 23771 | // 145: } // switch Inst[31:23] |
| 23772 | // 145: } |
| 23773 | 3, 0, // 150: case 0x3: { |
| 23774 | OPC_SwitchField, 8, 4, // 152: switch Inst[11:8] { |
| 23775 | 2, 24, // 155: case 0x2: { |
| 23776 | OPC_CheckPredicate, 95, // 157: check predicate 95 |
| 23777 | OPC_CheckField, 23, 9, 231, 3, // 159: check Inst[31:23] == 0x1e7 |
| 23778 | OPC_CheckField, 16, 4, 9, // 164: check Inst[19:16] == 0x9 |
| 23779 | OPC_CheckField, 6, 2, 3, // 168: check Inst[7:6] == 0x3 |
| 23780 | OPC_CheckField, 4, 1, 0, // 172: check Inst[4] == 0x0 |
| 23781 | OPC_Decode, 128, 15, 167, 4, // 176: decode to SHA1H using decoder 551 |
| 23782 | // 176: } |
| 23783 | 3, 129, 1, // 181: case 0x3: { |
| 23784 | OPC_SwitchField, 6, 2, // 184: switch Inst[7:6] { |
| 23785 | 0, 20, // 187: case 0x0: { |
| 23786 | OPC_CheckPredicate, 38, // 189: check predicate 38 |
| 23787 | OPC_CheckField, 23, 9, 231, 3, // 191: check Inst[31:23] == 0x1e7 |
| 23788 | OPC_CheckField, 16, 4, 0, // 196: check Inst[19:16] == 0x0 |
| 23789 | OPC_CheckField, 4, 1, 0, // 200: check Inst[4] == 0x0 |
| 23790 | OPC_Decode, 172, 6, 168, 4, // 204: decode to AESE using decoder 552 |
| 23791 | // 204: } |
| 23792 | 1, 20, // 209: case 0x1: { |
| 23793 | OPC_CheckPredicate, 38, // 211: check predicate 38 |
| 23794 | OPC_CheckField, 23, 9, 231, 3, // 213: check Inst[31:23] == 0x1e7 |
| 23795 | OPC_CheckField, 16, 4, 0, // 218: check Inst[19:16] == 0x0 |
| 23796 | OPC_CheckField, 4, 1, 0, // 222: check Inst[4] == 0x0 |
| 23797 | OPC_Decode, 171, 6, 168, 4, // 226: decode to AESD using decoder 552 |
| 23798 | // 226: } |
| 23799 | 2, 39, // 231: case 0x2: { |
| 23800 | OPC_SwitchField, 16, 4, // 233: switch Inst[19:16] { |
| 23801 | 0, 16, // 236: case 0x0: { |
| 23802 | OPC_CheckPredicate, 38, // 238: check predicate 38 |
| 23803 | OPC_CheckField, 23, 9, 231, 3, // 240: check Inst[31:23] == 0x1e7 |
| 23804 | OPC_CheckField, 4, 1, 0, // 245: check Inst[4] == 0x0 |
| 23805 | OPC_Decode, 174, 6, 167, 4, // 249: decode to AESMC using decoder 551 |
| 23806 | // 249: } |
| 23807 | 10, 0, // 254: case 0xa: { |
| 23808 | OPC_CheckPredicate, 95, // 256: check predicate 95 |
| 23809 | OPC_CheckField, 23, 9, 231, 3, // 258: check Inst[31:23] == 0x1e7 |
| 23810 | OPC_CheckField, 4, 1, 0, // 263: check Inst[4] == 0x0 |
| 23811 | OPC_Decode, 132, 15, 168, 4, // 267: decode to SHA1SU1 using decoder 552 |
| 23812 | // 267: } |
| 23813 | // 267: } // switch Inst[19:16] |
| 23814 | // 267: } |
| 23815 | 3, 0, // 272: case 0x3: { |
| 23816 | OPC_SwitchField, 16, 4, // 274: switch Inst[19:16] { |
| 23817 | 0, 16, // 277: case 0x0: { |
| 23818 | OPC_CheckPredicate, 38, // 279: check predicate 38 |
| 23819 | OPC_CheckField, 23, 9, 231, 3, // 281: check Inst[31:23] == 0x1e7 |
| 23820 | OPC_CheckField, 4, 1, 0, // 286: check Inst[4] == 0x0 |
| 23821 | OPC_Decode, 173, 6, 167, 4, // 290: decode to AESIMC using decoder 551 |
| 23822 | // 290: } |
| 23823 | 10, 0, // 295: case 0xa: { |
| 23824 | OPC_CheckPredicate, 95, // 297: check predicate 95 |
| 23825 | OPC_CheckField, 23, 9, 231, 3, // 299: check Inst[31:23] == 0x1e7 |
| 23826 | OPC_CheckField, 4, 1, 0, // 304: check Inst[4] == 0x0 |
| 23827 | OPC_Decode, 135, 15, 168, 4, // 308: decode to SHA256SU0 using decoder 552 |
| 23828 | // 308: } |
| 23829 | // 308: } // switch Inst[19:16] |
| 23830 | // 308: } |
| 23831 | // 308: } // switch Inst[7:6] |
| 23832 | // 308: } |
| 23833 | 12, 0, // 313: case 0xc: { |
| 23834 | OPC_CheckPredicate, 95, // 315: check predicate 95 |
| 23835 | OPC_CheckField, 23, 9, 228, 3, // 317: check Inst[31:23] == 0x1e4 |
| 23836 | OPC_CheckField, 6, 1, 1, // 322: check Inst[6] == 0x1 |
| 23837 | OPC_CheckField, 4, 1, 0, // 326: check Inst[4] == 0x0 |
| 23838 | OPC_Decode, 131, 15, 153, 4, // 330: decode to SHA1SU0 using decoder 537 |
| 23839 | // 330: } |
| 23840 | // 330: } // switch Inst[11:8] |
| 23841 | // 330: } |
| 23842 | // 330: } // switch Inst[21:20] |
| 23843 | }; |
| 23844 | static const uint8_t DecoderTablev8NEON32[1366] = { |
| 23845 | OPC_SwitchField, 8, 4, // 0: switch Inst[11:8] { |
| 23846 | 0, 167, 1, // 3: case 0x0: { |
| 23847 | OPC_SwitchField, 6, 2, // 6: switch Inst[7:6] { |
| 23848 | 0, 39, // 9: case 0x0: { |
| 23849 | OPC_SwitchField, 16, 6, // 11: switch Inst[21:16] { |
| 23850 | 55, 16, // 14: case 0x37: { |
| 23851 | OPC_CheckPredicate, 96, // 16: check predicate 96 |
| 23852 | OPC_CheckField, 23, 9, 231, 3, // 18: check Inst[31:23] == 0x1e7 |
| 23853 | OPC_CheckField, 4, 1, 0, // 23: check Inst[4] == 0x0 |
| 23854 | OPC_Decode, 167, 18, 162, 4, // 27: decode to VCVTANSDh using decoder 546 |
| 23855 | // 27: } |
| 23856 | 59, 0, // 32: case 0x3b: { |
| 23857 | OPC_CheckPredicate, 97, // 34: check predicate 97 |
| 23858 | OPC_CheckField, 23, 9, 231, 3, // 36: check Inst[31:23] == 0x1e7 |
| 23859 | OPC_CheckField, 4, 1, 0, // 41: check Inst[4] == 0x0 |
| 23860 | OPC_Decode, 166, 18, 162, 4, // 45: decode to VCVTANSDf using decoder 546 |
| 23861 | // 45: } |
| 23862 | // 45: } // switch Inst[21:16] |
| 23863 | // 45: } |
| 23864 | 1, 39, // 50: case 0x1: { |
| 23865 | OPC_SwitchField, 16, 6, // 52: switch Inst[21:16] { |
| 23866 | 55, 16, // 55: case 0x37: { |
| 23867 | OPC_CheckPredicate, 96, // 57: check predicate 96 |
| 23868 | OPC_CheckField, 23, 9, 231, 3, // 59: check Inst[31:23] == 0x1e7 |
| 23869 | OPC_CheckField, 4, 1, 0, // 64: check Inst[4] == 0x0 |
| 23870 | OPC_Decode, 169, 18, 167, 4, // 68: decode to VCVTANSQh using decoder 551 |
| 23871 | // 68: } |
| 23872 | 59, 0, // 73: case 0x3b: { |
| 23873 | OPC_CheckPredicate, 97, // 75: check predicate 97 |
| 23874 | OPC_CheckField, 23, 9, 231, 3, // 77: check Inst[31:23] == 0x1e7 |
| 23875 | OPC_CheckField, 4, 1, 0, // 82: check Inst[4] == 0x0 |
| 23876 | OPC_Decode, 168, 18, 167, 4, // 86: decode to VCVTANSQf using decoder 551 |
| 23877 | // 86: } |
| 23878 | // 86: } // switch Inst[21:16] |
| 23879 | // 86: } |
| 23880 | 2, 39, // 91: case 0x2: { |
| 23881 | OPC_SwitchField, 16, 6, // 93: switch Inst[21:16] { |
| 23882 | 55, 16, // 96: case 0x37: { |
| 23883 | OPC_CheckPredicate, 96, // 98: check predicate 96 |
| 23884 | OPC_CheckField, 23, 9, 231, 3, // 100: check Inst[31:23] == 0x1e7 |
| 23885 | OPC_CheckField, 4, 1, 0, // 105: check Inst[4] == 0x0 |
| 23886 | OPC_Decode, 171, 18, 162, 4, // 109: decode to VCVTANUDh using decoder 546 |
| 23887 | // 109: } |
| 23888 | 59, 0, // 114: case 0x3b: { |
| 23889 | OPC_CheckPredicate, 97, // 116: check predicate 97 |
| 23890 | OPC_CheckField, 23, 9, 231, 3, // 118: check Inst[31:23] == 0x1e7 |
| 23891 | OPC_CheckField, 4, 1, 0, // 123: check Inst[4] == 0x0 |
| 23892 | OPC_Decode, 170, 18, 162, 4, // 127: decode to VCVTANUDf using decoder 546 |
| 23893 | // 127: } |
| 23894 | // 127: } // switch Inst[21:16] |
| 23895 | // 127: } |
| 23896 | 3, 0, // 132: case 0x3: { |
| 23897 | OPC_SwitchField, 16, 6, // 134: switch Inst[21:16] { |
| 23898 | 55, 16, // 137: case 0x37: { |
| 23899 | OPC_CheckPredicate, 96, // 139: check predicate 96 |
| 23900 | OPC_CheckField, 23, 9, 231, 3, // 141: check Inst[31:23] == 0x1e7 |
| 23901 | OPC_CheckField, 4, 1, 0, // 146: check Inst[4] == 0x0 |
| 23902 | OPC_Decode, 173, 18, 167, 4, // 150: decode to VCVTANUQh using decoder 551 |
| 23903 | // 150: } |
| 23904 | 59, 0, // 155: case 0x3b: { |
| 23905 | OPC_CheckPredicate, 97, // 157: check predicate 97 |
| 23906 | OPC_CheckField, 23, 9, 231, 3, // 159: check Inst[31:23] == 0x1e7 |
| 23907 | OPC_CheckField, 4, 1, 0, // 164: check Inst[4] == 0x0 |
| 23908 | OPC_Decode, 172, 18, 167, 4, // 168: decode to VCVTANUQf using decoder 551 |
| 23909 | // 168: } |
| 23910 | // 168: } // switch Inst[21:16] |
| 23911 | // 168: } |
| 23912 | // 168: } // switch Inst[7:6] |
| 23913 | // 168: } |
| 23914 | 1, 167, 1, // 173: case 0x1: { |
| 23915 | OPC_SwitchField, 6, 2, // 176: switch Inst[7:6] { |
| 23916 | 0, 39, // 179: case 0x0: { |
| 23917 | OPC_SwitchField, 16, 6, // 181: switch Inst[21:16] { |
| 23918 | 55, 16, // 184: case 0x37: { |
| 23919 | OPC_CheckPredicate, 96, // 186: check predicate 96 |
| 23920 | OPC_CheckField, 23, 9, 231, 3, // 188: check Inst[31:23] == 0x1e7 |
| 23921 | OPC_CheckField, 4, 1, 0, // 193: check Inst[4] == 0x0 |
| 23922 | OPC_Decode, 200, 18, 162, 4, // 197: decode to VCVTNNSDh using decoder 546 |
| 23923 | // 197: } |
| 23924 | 59, 0, // 202: case 0x3b: { |
| 23925 | OPC_CheckPredicate, 97, // 204: check predicate 97 |
| 23926 | OPC_CheckField, 23, 9, 231, 3, // 206: check Inst[31:23] == 0x1e7 |
| 23927 | OPC_CheckField, 4, 1, 0, // 211: check Inst[4] == 0x0 |
| 23928 | OPC_Decode, 199, 18, 162, 4, // 215: decode to VCVTNNSDf using decoder 546 |
| 23929 | // 215: } |
| 23930 | // 215: } // switch Inst[21:16] |
| 23931 | // 215: } |
| 23932 | 1, 39, // 220: case 0x1: { |
| 23933 | OPC_SwitchField, 16, 6, // 222: switch Inst[21:16] { |
| 23934 | 55, 16, // 225: case 0x37: { |
| 23935 | OPC_CheckPredicate, 96, // 227: check predicate 96 |
| 23936 | OPC_CheckField, 23, 9, 231, 3, // 229: check Inst[31:23] == 0x1e7 |
| 23937 | OPC_CheckField, 4, 1, 0, // 234: check Inst[4] == 0x0 |
| 23938 | OPC_Decode, 202, 18, 167, 4, // 238: decode to VCVTNNSQh using decoder 551 |
| 23939 | // 238: } |
| 23940 | 59, 0, // 243: case 0x3b: { |
| 23941 | OPC_CheckPredicate, 97, // 245: check predicate 97 |
| 23942 | OPC_CheckField, 23, 9, 231, 3, // 247: check Inst[31:23] == 0x1e7 |
| 23943 | OPC_CheckField, 4, 1, 0, // 252: check Inst[4] == 0x0 |
| 23944 | OPC_Decode, 201, 18, 167, 4, // 256: decode to VCVTNNSQf using decoder 551 |
| 23945 | // 256: } |
| 23946 | // 256: } // switch Inst[21:16] |
| 23947 | // 256: } |
| 23948 | 2, 39, // 261: case 0x2: { |
| 23949 | OPC_SwitchField, 16, 6, // 263: switch Inst[21:16] { |
| 23950 | 55, 16, // 266: case 0x37: { |
| 23951 | OPC_CheckPredicate, 96, // 268: check predicate 96 |
| 23952 | OPC_CheckField, 23, 9, 231, 3, // 270: check Inst[31:23] == 0x1e7 |
| 23953 | OPC_CheckField, 4, 1, 0, // 275: check Inst[4] == 0x0 |
| 23954 | OPC_Decode, 204, 18, 162, 4, // 279: decode to VCVTNNUDh using decoder 546 |
| 23955 | // 279: } |
| 23956 | 59, 0, // 284: case 0x3b: { |
| 23957 | OPC_CheckPredicate, 97, // 286: check predicate 97 |
| 23958 | OPC_CheckField, 23, 9, 231, 3, // 288: check Inst[31:23] == 0x1e7 |
| 23959 | OPC_CheckField, 4, 1, 0, // 293: check Inst[4] == 0x0 |
| 23960 | OPC_Decode, 203, 18, 162, 4, // 297: decode to VCVTNNUDf using decoder 546 |
| 23961 | // 297: } |
| 23962 | // 297: } // switch Inst[21:16] |
| 23963 | // 297: } |
| 23964 | 3, 0, // 302: case 0x3: { |
| 23965 | OPC_SwitchField, 16, 6, // 304: switch Inst[21:16] { |
| 23966 | 55, 16, // 307: case 0x37: { |
| 23967 | OPC_CheckPredicate, 96, // 309: check predicate 96 |
| 23968 | OPC_CheckField, 23, 9, 231, 3, // 311: check Inst[31:23] == 0x1e7 |
| 23969 | OPC_CheckField, 4, 1, 0, // 316: check Inst[4] == 0x0 |
| 23970 | OPC_Decode, 206, 18, 167, 4, // 320: decode to VCVTNNUQh using decoder 551 |
| 23971 | // 320: } |
| 23972 | 59, 0, // 325: case 0x3b: { |
| 23973 | OPC_CheckPredicate, 97, // 327: check predicate 97 |
| 23974 | OPC_CheckField, 23, 9, 231, 3, // 329: check Inst[31:23] == 0x1e7 |
| 23975 | OPC_CheckField, 4, 1, 0, // 334: check Inst[4] == 0x0 |
| 23976 | OPC_Decode, 205, 18, 167, 4, // 338: decode to VCVTNNUQf using decoder 551 |
| 23977 | // 338: } |
| 23978 | // 338: } // switch Inst[21:16] |
| 23979 | // 338: } |
| 23980 | // 338: } // switch Inst[7:6] |
| 23981 | // 338: } |
| 23982 | 2, 167, 1, // 343: case 0x2: { |
| 23983 | OPC_SwitchField, 6, 2, // 346: switch Inst[7:6] { |
| 23984 | 0, 39, // 349: case 0x0: { |
| 23985 | OPC_SwitchField, 16, 6, // 351: switch Inst[21:16] { |
| 23986 | 55, 16, // 354: case 0x37: { |
| 23987 | OPC_CheckPredicate, 96, // 356: check predicate 96 |
| 23988 | OPC_CheckField, 23, 9, 231, 3, // 358: check Inst[31:23] == 0x1e7 |
| 23989 | OPC_CheckField, 4, 1, 0, // 363: check Inst[4] == 0x0 |
| 23990 | OPC_Decode, 214, 18, 162, 4, // 367: decode to VCVTPNSDh using decoder 546 |
| 23991 | // 367: } |
| 23992 | 59, 0, // 372: case 0x3b: { |
| 23993 | OPC_CheckPredicate, 97, // 374: check predicate 97 |
| 23994 | OPC_CheckField, 23, 9, 231, 3, // 376: check Inst[31:23] == 0x1e7 |
| 23995 | OPC_CheckField, 4, 1, 0, // 381: check Inst[4] == 0x0 |
| 23996 | OPC_Decode, 213, 18, 162, 4, // 385: decode to VCVTPNSDf using decoder 546 |
| 23997 | // 385: } |
| 23998 | // 385: } // switch Inst[21:16] |
| 23999 | // 385: } |
| 24000 | 1, 39, // 390: case 0x1: { |
| 24001 | OPC_SwitchField, 16, 6, // 392: switch Inst[21:16] { |
| 24002 | 55, 16, // 395: case 0x37: { |
| 24003 | OPC_CheckPredicate, 96, // 397: check predicate 96 |
| 24004 | OPC_CheckField, 23, 9, 231, 3, // 399: check Inst[31:23] == 0x1e7 |
| 24005 | OPC_CheckField, 4, 1, 0, // 404: check Inst[4] == 0x0 |
| 24006 | OPC_Decode, 216, 18, 167, 4, // 408: decode to VCVTPNSQh using decoder 551 |
| 24007 | // 408: } |
| 24008 | 59, 0, // 413: case 0x3b: { |
| 24009 | OPC_CheckPredicate, 97, // 415: check predicate 97 |
| 24010 | OPC_CheckField, 23, 9, 231, 3, // 417: check Inst[31:23] == 0x1e7 |
| 24011 | OPC_CheckField, 4, 1, 0, // 422: check Inst[4] == 0x0 |
| 24012 | OPC_Decode, 215, 18, 167, 4, // 426: decode to VCVTPNSQf using decoder 551 |
| 24013 | // 426: } |
| 24014 | // 426: } // switch Inst[21:16] |
| 24015 | // 426: } |
| 24016 | 2, 39, // 431: case 0x2: { |
| 24017 | OPC_SwitchField, 16, 6, // 433: switch Inst[21:16] { |
| 24018 | 55, 16, // 436: case 0x37: { |
| 24019 | OPC_CheckPredicate, 96, // 438: check predicate 96 |
| 24020 | OPC_CheckField, 23, 9, 231, 3, // 440: check Inst[31:23] == 0x1e7 |
| 24021 | OPC_CheckField, 4, 1, 0, // 445: check Inst[4] == 0x0 |
| 24022 | OPC_Decode, 218, 18, 162, 4, // 449: decode to VCVTPNUDh using decoder 546 |
| 24023 | // 449: } |
| 24024 | 59, 0, // 454: case 0x3b: { |
| 24025 | OPC_CheckPredicate, 97, // 456: check predicate 97 |
| 24026 | OPC_CheckField, 23, 9, 231, 3, // 458: check Inst[31:23] == 0x1e7 |
| 24027 | OPC_CheckField, 4, 1, 0, // 463: check Inst[4] == 0x0 |
| 24028 | OPC_Decode, 217, 18, 162, 4, // 467: decode to VCVTPNUDf using decoder 546 |
| 24029 | // 467: } |
| 24030 | // 467: } // switch Inst[21:16] |
| 24031 | // 467: } |
| 24032 | 3, 0, // 472: case 0x3: { |
| 24033 | OPC_SwitchField, 16, 6, // 474: switch Inst[21:16] { |
| 24034 | 55, 16, // 477: case 0x37: { |
| 24035 | OPC_CheckPredicate, 96, // 479: check predicate 96 |
| 24036 | OPC_CheckField, 23, 9, 231, 3, // 481: check Inst[31:23] == 0x1e7 |
| 24037 | OPC_CheckField, 4, 1, 0, // 486: check Inst[4] == 0x0 |
| 24038 | OPC_Decode, 220, 18, 167, 4, // 490: decode to VCVTPNUQh using decoder 551 |
| 24039 | // 490: } |
| 24040 | 59, 0, // 495: case 0x3b: { |
| 24041 | OPC_CheckPredicate, 97, // 497: check predicate 97 |
| 24042 | OPC_CheckField, 23, 9, 231, 3, // 499: check Inst[31:23] == 0x1e7 |
| 24043 | OPC_CheckField, 4, 1, 0, // 504: check Inst[4] == 0x0 |
| 24044 | OPC_Decode, 219, 18, 167, 4, // 508: decode to VCVTPNUQf using decoder 551 |
| 24045 | // 508: } |
| 24046 | // 508: } // switch Inst[21:16] |
| 24047 | // 508: } |
| 24048 | // 508: } // switch Inst[7:6] |
| 24049 | // 508: } |
| 24050 | 3, 167, 1, // 513: case 0x3: { |
| 24051 | OPC_SwitchField, 6, 2, // 516: switch Inst[7:6] { |
| 24052 | 0, 39, // 519: case 0x0: { |
| 24053 | OPC_SwitchField, 16, 6, // 521: switch Inst[21:16] { |
| 24054 | 55, 16, // 524: case 0x37: { |
| 24055 | OPC_CheckPredicate, 96, // 526: check predicate 96 |
| 24056 | OPC_CheckField, 23, 9, 231, 3, // 528: check Inst[31:23] == 0x1e7 |
| 24057 | OPC_CheckField, 4, 1, 0, // 533: check Inst[4] == 0x0 |
| 24058 | OPC_Decode, 186, 18, 162, 4, // 537: decode to VCVTMNSDh using decoder 546 |
| 24059 | // 537: } |
| 24060 | 59, 0, // 542: case 0x3b: { |
| 24061 | OPC_CheckPredicate, 97, // 544: check predicate 97 |
| 24062 | OPC_CheckField, 23, 9, 231, 3, // 546: check Inst[31:23] == 0x1e7 |
| 24063 | OPC_CheckField, 4, 1, 0, // 551: check Inst[4] == 0x0 |
| 24064 | OPC_Decode, 185, 18, 162, 4, // 555: decode to VCVTMNSDf using decoder 546 |
| 24065 | // 555: } |
| 24066 | // 555: } // switch Inst[21:16] |
| 24067 | // 555: } |
| 24068 | 1, 39, // 560: case 0x1: { |
| 24069 | OPC_SwitchField, 16, 6, // 562: switch Inst[21:16] { |
| 24070 | 55, 16, // 565: case 0x37: { |
| 24071 | OPC_CheckPredicate, 96, // 567: check predicate 96 |
| 24072 | OPC_CheckField, 23, 9, 231, 3, // 569: check Inst[31:23] == 0x1e7 |
| 24073 | OPC_CheckField, 4, 1, 0, // 574: check Inst[4] == 0x0 |
| 24074 | OPC_Decode, 188, 18, 167, 4, // 578: decode to VCVTMNSQh using decoder 551 |
| 24075 | // 578: } |
| 24076 | 59, 0, // 583: case 0x3b: { |
| 24077 | OPC_CheckPredicate, 97, // 585: check predicate 97 |
| 24078 | OPC_CheckField, 23, 9, 231, 3, // 587: check Inst[31:23] == 0x1e7 |
| 24079 | OPC_CheckField, 4, 1, 0, // 592: check Inst[4] == 0x0 |
| 24080 | OPC_Decode, 187, 18, 167, 4, // 596: decode to VCVTMNSQf using decoder 551 |
| 24081 | // 596: } |
| 24082 | // 596: } // switch Inst[21:16] |
| 24083 | // 596: } |
| 24084 | 2, 39, // 601: case 0x2: { |
| 24085 | OPC_SwitchField, 16, 6, // 603: switch Inst[21:16] { |
| 24086 | 55, 16, // 606: case 0x37: { |
| 24087 | OPC_CheckPredicate, 96, // 608: check predicate 96 |
| 24088 | OPC_CheckField, 23, 9, 231, 3, // 610: check Inst[31:23] == 0x1e7 |
| 24089 | OPC_CheckField, 4, 1, 0, // 615: check Inst[4] == 0x0 |
| 24090 | OPC_Decode, 190, 18, 162, 4, // 619: decode to VCVTMNUDh using decoder 546 |
| 24091 | // 619: } |
| 24092 | 59, 0, // 624: case 0x3b: { |
| 24093 | OPC_CheckPredicate, 97, // 626: check predicate 97 |
| 24094 | OPC_CheckField, 23, 9, 231, 3, // 628: check Inst[31:23] == 0x1e7 |
| 24095 | OPC_CheckField, 4, 1, 0, // 633: check Inst[4] == 0x0 |
| 24096 | OPC_Decode, 189, 18, 162, 4, // 637: decode to VCVTMNUDf using decoder 546 |
| 24097 | // 637: } |
| 24098 | // 637: } // switch Inst[21:16] |
| 24099 | // 637: } |
| 24100 | 3, 0, // 642: case 0x3: { |
| 24101 | OPC_SwitchField, 16, 6, // 644: switch Inst[21:16] { |
| 24102 | 55, 16, // 647: case 0x37: { |
| 24103 | OPC_CheckPredicate, 96, // 649: check predicate 96 |
| 24104 | OPC_CheckField, 23, 9, 231, 3, // 651: check Inst[31:23] == 0x1e7 |
| 24105 | OPC_CheckField, 4, 1, 0, // 656: check Inst[4] == 0x0 |
| 24106 | OPC_Decode, 192, 18, 167, 4, // 660: decode to VCVTMNUQh using decoder 551 |
| 24107 | // 660: } |
| 24108 | 59, 0, // 665: case 0x3b: { |
| 24109 | OPC_CheckPredicate, 97, // 667: check predicate 97 |
| 24110 | OPC_CheckField, 23, 9, 231, 3, // 669: check Inst[31:23] == 0x1e7 |
| 24111 | OPC_CheckField, 4, 1, 0, // 674: check Inst[4] == 0x0 |
| 24112 | OPC_Decode, 191, 18, 167, 4, // 678: decode to VCVTMNUQf using decoder 551 |
| 24113 | // 678: } |
| 24114 | // 678: } // switch Inst[21:16] |
| 24115 | // 678: } |
| 24116 | // 678: } // switch Inst[7:6] |
| 24117 | // 678: } |
| 24118 | 4, 167, 1, // 683: case 0x4: { |
| 24119 | OPC_SwitchField, 6, 2, // 686: switch Inst[7:6] { |
| 24120 | 0, 39, // 689: case 0x0: { |
| 24121 | OPC_SwitchField, 16, 6, // 691: switch Inst[21:16] { |
| 24122 | 54, 16, // 694: case 0x36: { |
| 24123 | OPC_CheckPredicate, 96, // 696: check predicate 96 |
| 24124 | OPC_CheckField, 23, 9, 231, 3, // 698: check Inst[31:23] == 0x1e7 |
| 24125 | OPC_CheckField, 4, 1, 0, // 703: check Inst[4] == 0x0 |
| 24126 | OPC_Decode, 212, 26, 162, 4, // 707: decode to VRINTNNDh using decoder 546 |
| 24127 | // 707: } |
| 24128 | 58, 0, // 712: case 0x3a: { |
| 24129 | OPC_CheckPredicate, 97, // 714: check predicate 97 |
| 24130 | OPC_CheckField, 23, 9, 231, 3, // 716: check Inst[31:23] == 0x1e7 |
| 24131 | OPC_CheckField, 4, 1, 0, // 721: check Inst[4] == 0x0 |
| 24132 | OPC_Decode, 211, 26, 162, 4, // 725: decode to VRINTNNDf using decoder 546 |
| 24133 | // 725: } |
| 24134 | // 725: } // switch Inst[21:16] |
| 24135 | // 725: } |
| 24136 | 1, 39, // 730: case 0x1: { |
| 24137 | OPC_SwitchField, 16, 6, // 732: switch Inst[21:16] { |
| 24138 | 54, 16, // 735: case 0x36: { |
| 24139 | OPC_CheckPredicate, 96, // 737: check predicate 96 |
| 24140 | OPC_CheckField, 23, 9, 231, 3, // 739: check Inst[31:23] == 0x1e7 |
| 24141 | OPC_CheckField, 4, 1, 0, // 744: check Inst[4] == 0x0 |
| 24142 | OPC_Decode, 214, 26, 167, 4, // 748: decode to VRINTNNQh using decoder 551 |
| 24143 | // 748: } |
| 24144 | 58, 0, // 753: case 0x3a: { |
| 24145 | OPC_CheckPredicate, 97, // 755: check predicate 97 |
| 24146 | OPC_CheckField, 23, 9, 231, 3, // 757: check Inst[31:23] == 0x1e7 |
| 24147 | OPC_CheckField, 4, 1, 0, // 762: check Inst[4] == 0x0 |
| 24148 | OPC_Decode, 213, 26, 167, 4, // 766: decode to VRINTNNQf using decoder 551 |
| 24149 | // 766: } |
| 24150 | // 766: } // switch Inst[21:16] |
| 24151 | // 766: } |
| 24152 | 2, 39, // 771: case 0x2: { |
| 24153 | OPC_SwitchField, 16, 6, // 773: switch Inst[21:16] { |
| 24154 | 54, 16, // 776: case 0x36: { |
| 24155 | OPC_CheckPredicate, 96, // 778: check predicate 96 |
| 24156 | OPC_CheckField, 23, 9, 231, 3, // 780: check Inst[31:23] == 0x1e7 |
| 24157 | OPC_CheckField, 4, 1, 0, // 785: check Inst[4] == 0x0 |
| 24158 | OPC_Decode, 229, 26, 162, 4, // 789: decode to VRINTXNDh using decoder 546 |
| 24159 | // 789: } |
| 24160 | 58, 0, // 794: case 0x3a: { |
| 24161 | OPC_CheckPredicate, 97, // 796: check predicate 97 |
| 24162 | OPC_CheckField, 23, 9, 231, 3, // 798: check Inst[31:23] == 0x1e7 |
| 24163 | OPC_CheckField, 4, 1, 0, // 803: check Inst[4] == 0x0 |
| 24164 | OPC_Decode, 228, 26, 162, 4, // 807: decode to VRINTXNDf using decoder 546 |
| 24165 | // 807: } |
| 24166 | // 807: } // switch Inst[21:16] |
| 24167 | // 807: } |
| 24168 | 3, 0, // 812: case 0x3: { |
| 24169 | OPC_SwitchField, 16, 6, // 814: switch Inst[21:16] { |
| 24170 | 54, 16, // 817: case 0x36: { |
| 24171 | OPC_CheckPredicate, 96, // 819: check predicate 96 |
| 24172 | OPC_CheckField, 23, 9, 231, 3, // 821: check Inst[31:23] == 0x1e7 |
| 24173 | OPC_CheckField, 4, 1, 0, // 826: check Inst[4] == 0x0 |
| 24174 | OPC_Decode, 231, 26, 167, 4, // 830: decode to VRINTXNQh using decoder 551 |
| 24175 | // 830: } |
| 24176 | 58, 0, // 835: case 0x3a: { |
| 24177 | OPC_CheckPredicate, 97, // 837: check predicate 97 |
| 24178 | OPC_CheckField, 23, 9, 231, 3, // 839: check Inst[31:23] == 0x1e7 |
| 24179 | OPC_CheckField, 4, 1, 0, // 844: check Inst[4] == 0x0 |
| 24180 | OPC_Decode, 230, 26, 167, 4, // 848: decode to VRINTXNQf using decoder 551 |
| 24181 | // 848: } |
| 24182 | // 848: } // switch Inst[21:16] |
| 24183 | // 848: } |
| 24184 | // 848: } // switch Inst[7:6] |
| 24185 | // 848: } |
| 24186 | 5, 167, 1, // 853: case 0x5: { |
| 24187 | OPC_SwitchField, 6, 2, // 856: switch Inst[7:6] { |
| 24188 | 0, 39, // 859: case 0x0: { |
| 24189 | OPC_SwitchField, 16, 6, // 861: switch Inst[21:16] { |
| 24190 | 54, 16, // 864: case 0x36: { |
| 24191 | OPC_CheckPredicate, 96, // 866: check predicate 96 |
| 24192 | OPC_CheckField, 23, 9, 231, 3, // 868: check Inst[31:23] == 0x1e7 |
| 24193 | OPC_CheckField, 4, 1, 0, // 873: check Inst[4] == 0x0 |
| 24194 | OPC_Decode, 198, 26, 162, 4, // 877: decode to VRINTANDh using decoder 546 |
| 24195 | // 877: } |
| 24196 | 58, 0, // 882: case 0x3a: { |
| 24197 | OPC_CheckPredicate, 97, // 884: check predicate 97 |
| 24198 | OPC_CheckField, 23, 9, 231, 3, // 886: check Inst[31:23] == 0x1e7 |
| 24199 | OPC_CheckField, 4, 1, 0, // 891: check Inst[4] == 0x0 |
| 24200 | OPC_Decode, 197, 26, 162, 4, // 895: decode to VRINTANDf using decoder 546 |
| 24201 | // 895: } |
| 24202 | // 895: } // switch Inst[21:16] |
| 24203 | // 895: } |
| 24204 | 1, 39, // 900: case 0x1: { |
| 24205 | OPC_SwitchField, 16, 6, // 902: switch Inst[21:16] { |
| 24206 | 54, 16, // 905: case 0x36: { |
| 24207 | OPC_CheckPredicate, 96, // 907: check predicate 96 |
| 24208 | OPC_CheckField, 23, 9, 231, 3, // 909: check Inst[31:23] == 0x1e7 |
| 24209 | OPC_CheckField, 4, 1, 0, // 914: check Inst[4] == 0x0 |
| 24210 | OPC_Decode, 200, 26, 167, 4, // 918: decode to VRINTANQh using decoder 551 |
| 24211 | // 918: } |
| 24212 | 58, 0, // 923: case 0x3a: { |
| 24213 | OPC_CheckPredicate, 97, // 925: check predicate 97 |
| 24214 | OPC_CheckField, 23, 9, 231, 3, // 927: check Inst[31:23] == 0x1e7 |
| 24215 | OPC_CheckField, 4, 1, 0, // 932: check Inst[4] == 0x0 |
| 24216 | OPC_Decode, 199, 26, 167, 4, // 936: decode to VRINTANQf using decoder 551 |
| 24217 | // 936: } |
| 24218 | // 936: } // switch Inst[21:16] |
| 24219 | // 936: } |
| 24220 | 2, 39, // 941: case 0x2: { |
| 24221 | OPC_SwitchField, 16, 6, // 943: switch Inst[21:16] { |
| 24222 | 54, 16, // 946: case 0x36: { |
| 24223 | OPC_CheckPredicate, 96, // 948: check predicate 96 |
| 24224 | OPC_CheckField, 23, 9, 231, 3, // 950: check Inst[31:23] == 0x1e7 |
| 24225 | OPC_CheckField, 4, 1, 0, // 955: check Inst[4] == 0x0 |
| 24226 | OPC_Decode, 236, 26, 162, 4, // 959: decode to VRINTZNDh using decoder 546 |
| 24227 | // 959: } |
| 24228 | 58, 0, // 964: case 0x3a: { |
| 24229 | OPC_CheckPredicate, 97, // 966: check predicate 97 |
| 24230 | OPC_CheckField, 23, 9, 231, 3, // 968: check Inst[31:23] == 0x1e7 |
| 24231 | OPC_CheckField, 4, 1, 0, // 973: check Inst[4] == 0x0 |
| 24232 | OPC_Decode, 235, 26, 162, 4, // 977: decode to VRINTZNDf using decoder 546 |
| 24233 | // 977: } |
| 24234 | // 977: } // switch Inst[21:16] |
| 24235 | // 977: } |
| 24236 | 3, 0, // 982: case 0x3: { |
| 24237 | OPC_SwitchField, 16, 6, // 984: switch Inst[21:16] { |
| 24238 | 54, 16, // 987: case 0x36: { |
| 24239 | OPC_CheckPredicate, 96, // 989: check predicate 96 |
| 24240 | OPC_CheckField, 23, 9, 231, 3, // 991: check Inst[31:23] == 0x1e7 |
| 24241 | OPC_CheckField, 4, 1, 0, // 996: check Inst[4] == 0x0 |
| 24242 | OPC_Decode, 238, 26, 167, 4, // 1000: decode to VRINTZNQh using decoder 551 |
| 24243 | // 1000: } |
| 24244 | 58, 0, // 1005: case 0x3a: { |
| 24245 | OPC_CheckPredicate, 97, // 1007: check predicate 97 |
| 24246 | OPC_CheckField, 23, 9, 231, 3, // 1009: check Inst[31:23] == 0x1e7 |
| 24247 | OPC_CheckField, 4, 1, 0, // 1014: check Inst[4] == 0x0 |
| 24248 | OPC_Decode, 237, 26, 167, 4, // 1018: decode to VRINTZNQf using decoder 551 |
| 24249 | // 1018: } |
| 24250 | // 1018: } // switch Inst[21:16] |
| 24251 | // 1018: } |
| 24252 | // 1018: } // switch Inst[7:6] |
| 24253 | // 1018: } |
| 24254 | 6, 85, // 1023: case 0x6: { |
| 24255 | OPC_SwitchField, 6, 2, // 1025: switch Inst[7:6] { |
| 24256 | 2, 39, // 1028: case 0x2: { |
| 24257 | OPC_SwitchField, 16, 6, // 1030: switch Inst[21:16] { |
| 24258 | 54, 16, // 1033: case 0x36: { |
| 24259 | OPC_CheckPredicate, 96, // 1035: check predicate 96 |
| 24260 | OPC_CheckField, 23, 9, 231, 3, // 1037: check Inst[31:23] == 0x1e7 |
| 24261 | OPC_CheckField, 4, 1, 0, // 1042: check Inst[4] == 0x0 |
| 24262 | OPC_Decode, 205, 26, 162, 4, // 1046: decode to VRINTMNDh using decoder 546 |
| 24263 | // 1046: } |
| 24264 | 58, 0, // 1051: case 0x3a: { |
| 24265 | OPC_CheckPredicate, 97, // 1053: check predicate 97 |
| 24266 | OPC_CheckField, 23, 9, 231, 3, // 1055: check Inst[31:23] == 0x1e7 |
| 24267 | OPC_CheckField, 4, 1, 0, // 1060: check Inst[4] == 0x0 |
| 24268 | OPC_Decode, 204, 26, 162, 4, // 1064: decode to VRINTMNDf using decoder 546 |
| 24269 | // 1064: } |
| 24270 | // 1064: } // switch Inst[21:16] |
| 24271 | // 1064: } |
| 24272 | 3, 0, // 1069: case 0x3: { |
| 24273 | OPC_SwitchField, 16, 6, // 1071: switch Inst[21:16] { |
| 24274 | 54, 16, // 1074: case 0x36: { |
| 24275 | OPC_CheckPredicate, 96, // 1076: check predicate 96 |
| 24276 | OPC_CheckField, 23, 9, 231, 3, // 1078: check Inst[31:23] == 0x1e7 |
| 24277 | OPC_CheckField, 4, 1, 0, // 1083: check Inst[4] == 0x0 |
| 24278 | OPC_Decode, 207, 26, 167, 4, // 1087: decode to VRINTMNQh using decoder 551 |
| 24279 | // 1087: } |
| 24280 | 58, 0, // 1092: case 0x3a: { |
| 24281 | OPC_CheckPredicate, 97, // 1094: check predicate 97 |
| 24282 | OPC_CheckField, 23, 9, 231, 3, // 1096: check Inst[31:23] == 0x1e7 |
| 24283 | OPC_CheckField, 4, 1, 0, // 1101: check Inst[4] == 0x0 |
| 24284 | OPC_Decode, 206, 26, 167, 4, // 1105: decode to VRINTMNQf using decoder 551 |
| 24285 | // 1105: } |
| 24286 | // 1105: } // switch Inst[21:16] |
| 24287 | // 1105: } |
| 24288 | // 1105: } // switch Inst[7:6] |
| 24289 | // 1105: } |
| 24290 | 7, 85, // 1110: case 0x7: { |
| 24291 | OPC_SwitchField, 6, 2, // 1112: switch Inst[7:6] { |
| 24292 | 2, 39, // 1115: case 0x2: { |
| 24293 | OPC_SwitchField, 16, 6, // 1117: switch Inst[21:16] { |
| 24294 | 54, 16, // 1120: case 0x36: { |
| 24295 | OPC_CheckPredicate, 96, // 1122: check predicate 96 |
| 24296 | OPC_CheckField, 23, 9, 231, 3, // 1124: check Inst[31:23] == 0x1e7 |
| 24297 | OPC_CheckField, 4, 1, 0, // 1129: check Inst[4] == 0x0 |
| 24298 | OPC_Decode, 219, 26, 162, 4, // 1133: decode to VRINTPNDh using decoder 546 |
| 24299 | // 1133: } |
| 24300 | 58, 0, // 1138: case 0x3a: { |
| 24301 | OPC_CheckPredicate, 97, // 1140: check predicate 97 |
| 24302 | OPC_CheckField, 23, 9, 231, 3, // 1142: check Inst[31:23] == 0x1e7 |
| 24303 | OPC_CheckField, 4, 1, 0, // 1147: check Inst[4] == 0x0 |
| 24304 | OPC_Decode, 218, 26, 162, 4, // 1151: decode to VRINTPNDf using decoder 546 |
| 24305 | // 1151: } |
| 24306 | // 1151: } // switch Inst[21:16] |
| 24307 | // 1151: } |
| 24308 | 3, 0, // 1156: case 0x3: { |
| 24309 | OPC_SwitchField, 16, 6, // 1158: switch Inst[21:16] { |
| 24310 | 54, 16, // 1161: case 0x36: { |
| 24311 | OPC_CheckPredicate, 96, // 1163: check predicate 96 |
| 24312 | OPC_CheckField, 23, 9, 231, 3, // 1165: check Inst[31:23] == 0x1e7 |
| 24313 | OPC_CheckField, 4, 1, 0, // 1170: check Inst[4] == 0x0 |
| 24314 | OPC_Decode, 221, 26, 167, 4, // 1174: decode to VRINTPNQh using decoder 551 |
| 24315 | // 1174: } |
| 24316 | 58, 0, // 1179: case 0x3a: { |
| 24317 | OPC_CheckPredicate, 97, // 1181: check predicate 97 |
| 24318 | OPC_CheckField, 23, 9, 231, 3, // 1183: check Inst[31:23] == 0x1e7 |
| 24319 | OPC_CheckField, 4, 1, 0, // 1188: check Inst[4] == 0x0 |
| 24320 | OPC_Decode, 220, 26, 167, 4, // 1192: decode to VRINTPNQf using decoder 551 |
| 24321 | // 1192: } |
| 24322 | // 1192: } // switch Inst[21:16] |
| 24323 | // 1192: } |
| 24324 | // 1192: } // switch Inst[7:6] |
| 24325 | // 1192: } |
| 24326 | 15, 0, // 1197: case 0xf: { |
| 24327 | OPC_SwitchField, 20, 2, // 1199: switch Inst[21:20] { |
| 24328 | 0, 39, // 1202: case 0x0: { |
| 24329 | OPC_SwitchField, 6, 1, // 1204: switch Inst[6] { |
| 24330 | 0, 16, // 1207: case 0x0: { |
| 24331 | OPC_CheckPredicate, 98, // 1209: check predicate 98 |
| 24332 | OPC_CheckField, 23, 9, 230, 3, // 1211: check Inst[31:23] == 0x1e6 |
| 24333 | OPC_CheckField, 4, 1, 1, // 1216: check Inst[4] == 0x1 |
| 24334 | OPC_Decode, 192, 14, 161, 4, // 1220: decode to NEON_VMAXNMNDf using decoder 545 |
| 24335 | // 1220: } |
| 24336 | 1, 0, // 1225: case 0x1: { |
| 24337 | OPC_CheckPredicate, 98, // 1227: check predicate 98 |
| 24338 | OPC_CheckField, 23, 9, 230, 3, // 1229: check Inst[31:23] == 0x1e6 |
| 24339 | OPC_CheckField, 4, 1, 1, // 1234: check Inst[4] == 0x1 |
| 24340 | OPC_Decode, 194, 14, 169, 4, // 1238: decode to NEON_VMAXNMNQf using decoder 553 |
| 24341 | // 1238: } |
| 24342 | // 1238: } // switch Inst[6] |
| 24343 | // 1238: } |
| 24344 | 1, 39, // 1243: case 0x1: { |
| 24345 | OPC_SwitchField, 6, 1, // 1245: switch Inst[6] { |
| 24346 | 0, 16, // 1248: case 0x0: { |
| 24347 | OPC_CheckPredicate, 99, // 1250: check predicate 99 |
| 24348 | OPC_CheckField, 23, 9, 230, 3, // 1252: check Inst[31:23] == 0x1e6 |
| 24349 | OPC_CheckField, 4, 1, 1, // 1257: check Inst[4] == 0x1 |
| 24350 | OPC_Decode, 193, 14, 161, 4, // 1261: decode to NEON_VMAXNMNDh using decoder 545 |
| 24351 | // 1261: } |
| 24352 | 1, 0, // 1266: case 0x1: { |
| 24353 | OPC_CheckPredicate, 99, // 1268: check predicate 99 |
| 24354 | OPC_CheckField, 23, 9, 230, 3, // 1270: check Inst[31:23] == 0x1e6 |
| 24355 | OPC_CheckField, 4, 1, 1, // 1275: check Inst[4] == 0x1 |
| 24356 | OPC_Decode, 195, 14, 169, 4, // 1279: decode to NEON_VMAXNMNQh using decoder 553 |
| 24357 | // 1279: } |
| 24358 | // 1279: } // switch Inst[6] |
| 24359 | // 1279: } |
| 24360 | 2, 39, // 1284: case 0x2: { |
| 24361 | OPC_SwitchField, 6, 1, // 1286: switch Inst[6] { |
| 24362 | 0, 16, // 1289: case 0x0: { |
| 24363 | OPC_CheckPredicate, 98, // 1291: check predicate 98 |
| 24364 | OPC_CheckField, 23, 9, 230, 3, // 1293: check Inst[31:23] == 0x1e6 |
| 24365 | OPC_CheckField, 4, 1, 1, // 1298: check Inst[4] == 0x1 |
| 24366 | OPC_Decode, 196, 14, 161, 4, // 1302: decode to NEON_VMINNMNDf using decoder 545 |
| 24367 | // 1302: } |
| 24368 | 1, 0, // 1307: case 0x1: { |
| 24369 | OPC_CheckPredicate, 98, // 1309: check predicate 98 |
| 24370 | OPC_CheckField, 23, 9, 230, 3, // 1311: check Inst[31:23] == 0x1e6 |
| 24371 | OPC_CheckField, 4, 1, 1, // 1316: check Inst[4] == 0x1 |
| 24372 | OPC_Decode, 198, 14, 169, 4, // 1320: decode to NEON_VMINNMNQf using decoder 553 |
| 24373 | // 1320: } |
| 24374 | // 1320: } // switch Inst[6] |
| 24375 | // 1320: } |
| 24376 | 3, 0, // 1325: case 0x3: { |
| 24377 | OPC_SwitchField, 6, 1, // 1327: switch Inst[6] { |
| 24378 | 0, 16, // 1330: case 0x0: { |
| 24379 | OPC_CheckPredicate, 99, // 1332: check predicate 99 |
| 24380 | OPC_CheckField, 23, 9, 230, 3, // 1334: check Inst[31:23] == 0x1e6 |
| 24381 | OPC_CheckField, 4, 1, 1, // 1339: check Inst[4] == 0x1 |
| 24382 | OPC_Decode, 197, 14, 161, 4, // 1343: decode to NEON_VMINNMNDh using decoder 545 |
| 24383 | // 1343: } |
| 24384 | 1, 0, // 1348: case 0x1: { |
| 24385 | OPC_CheckPredicate, 99, // 1350: check predicate 99 |
| 24386 | OPC_CheckField, 23, 9, 230, 3, // 1352: check Inst[31:23] == 0x1e6 |
| 24387 | OPC_CheckField, 4, 1, 1, // 1357: check Inst[4] == 0x1 |
| 24388 | OPC_Decode, 199, 14, 169, 4, // 1361: decode to NEON_VMINNMNQh using decoder 553 |
| 24389 | // 1361: } |
| 24390 | // 1361: } // switch Inst[6] |
| 24391 | // 1361: } |
| 24392 | // 1361: } // switch Inst[21:20] |
| 24393 | // 1361: } |
| 24394 | // 1361: } // switch Inst[11:8] |
| 24395 | }; |
| 24396 | // Handling 554 cases. |
| 24397 | template <typename InsnType> |
| 24398 | static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) { |
| 24399 | DecodeComplete = true; |
| 24400 | using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>; |
| 24401 | TmpType tmp; |
| 24402 | switch (Idx) { |
| 24403 | default: llvm_unreachable("Invalid decoder index!"); |
| 24404 | case 0: |
| 24405 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24406 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24407 | tmp = fieldFromInstruction(insn, 3, 3); |
| 24408 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24409 | return S; |
| 24410 | case 1: |
| 24411 | tmp = fieldFromInstruction(insn, 8, 3); |
| 24412 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24413 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24414 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24415 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24416 | return MCDisassembler::Fail; |
| 24417 | return S; |
| 24418 | case 2: |
| 24419 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24420 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24421 | tmp = fieldFromInstruction(insn, 3, 3); |
| 24422 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24423 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24424 | return MCDisassembler::Fail; |
| 24425 | return S; |
| 24426 | case 3: |
| 24427 | if (!Check(S, DecodeThumbAddSPReg(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24428 | return S; |
| 24429 | case 4: |
| 24430 | tmp = 0x0; |
| 24431 | tmp |= fieldFromInstruction(insn, 0, 3); |
| 24432 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 24433 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24434 | tmp = 0x0; |
| 24435 | tmp |= fieldFromInstruction(insn, 0, 3); |
| 24436 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 24437 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24438 | tmp = fieldFromInstruction(insn, 3, 4); |
| 24439 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24440 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24441 | return MCDisassembler::Fail; |
| 24442 | return S; |
| 24443 | case 5: |
| 24444 | tmp = 0x0; |
| 24445 | tmp |= fieldFromInstruction(insn, 0, 3); |
| 24446 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 24447 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24448 | tmp = fieldFromInstruction(insn, 3, 4); |
| 24449 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24450 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24451 | return MCDisassembler::Fail; |
| 24452 | return S; |
| 24453 | case 6: |
| 24454 | tmp = fieldFromInstruction(insn, 3, 4); |
| 24455 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24456 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24457 | return MCDisassembler::Fail; |
| 24458 | return S; |
| 24459 | case 7: |
| 24460 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24461 | return MCDisassembler::Fail; |
| 24462 | tmp = fieldFromInstruction(insn, 3, 4); |
| 24463 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24464 | return S; |
| 24465 | case 8: |
| 24466 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24467 | return MCDisassembler::Fail; |
| 24468 | tmp = fieldFromInstruction(insn, 3, 4); |
| 24469 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24470 | return S; |
| 24471 | case 9: |
| 24472 | tmp = fieldFromInstruction(insn, 8, 3); |
| 24473 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24474 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24475 | if (!Check(S, DecodeThumbAddrModePC(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24476 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24477 | return MCDisassembler::Fail; |
| 24478 | return S; |
| 24479 | case 10: |
| 24480 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24481 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24482 | tmp = fieldFromInstruction(insn, 3, 6); |
| 24483 | if (!Check(S, DecodeThumbAddrModeRR(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24484 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24485 | return MCDisassembler::Fail; |
| 24486 | return S; |
| 24487 | case 11: |
| 24488 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24489 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24490 | tmp = fieldFromInstruction(insn, 3, 8); |
| 24491 | if (!Check(S, DecodeThumbAddrModeIS(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24492 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24493 | return MCDisassembler::Fail; |
| 24494 | return S; |
| 24495 | case 12: |
| 24496 | tmp = fieldFromInstruction(insn, 8, 3); |
| 24497 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24498 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24499 | if (!Check(S, DecodeThumbAddrModeSP(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24500 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24501 | return MCDisassembler::Fail; |
| 24502 | return S; |
| 24503 | case 13: |
| 24504 | if (!Check(S, DecodeThumbAddSpecialReg(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24505 | return S; |
| 24506 | case 14: |
| 24507 | if (!Check(S, DecodeThumbAddSPImm(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24508 | return S; |
| 24509 | case 15: |
| 24510 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24511 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24512 | tmp = 0x0; |
| 24513 | tmp |= fieldFromInstruction(insn, 3, 5); |
| 24514 | tmp |= fieldFromInstruction(insn, 9, 1) << 5; |
| 24515 | if (!Check(S, DecodeThumbCmpBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24516 | return S; |
| 24517 | case 16: |
| 24518 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24519 | return MCDisassembler::Fail; |
| 24520 | tmp = 0x0; |
| 24521 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 24522 | tmp |= fieldFromInstruction(insn, 8, 1) << 14; |
| 24523 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24524 | return S; |
| 24525 | case 17: |
| 24526 | tmp = fieldFromInstruction(insn, 3, 1); |
| 24527 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24528 | return S; |
| 24529 | case 18: |
| 24530 | if (!Check(S, DecodeThumbCPS(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24531 | return S; |
| 24532 | case 19: |
| 24533 | tmp = fieldFromInstruction(insn, 0, 6); |
| 24534 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24535 | return S; |
| 24536 | case 20: |
| 24537 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24538 | return MCDisassembler::Fail; |
| 24539 | tmp = 0x0; |
| 24540 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 24541 | tmp |= fieldFromInstruction(insn, 8, 1) << 15; |
| 24542 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24543 | return S; |
| 24544 | case 21: |
| 24545 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24546 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24547 | return S; |
| 24548 | case 22: |
| 24549 | tmp = fieldFromInstruction(insn, 4, 4); |
| 24550 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24551 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24552 | return MCDisassembler::Fail; |
| 24553 | return S; |
| 24554 | case 23: |
| 24555 | tmp = fieldFromInstruction(insn, 8, 3); |
| 24556 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24557 | tmp = fieldFromInstruction(insn, 8, 3); |
| 24558 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24559 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24560 | return MCDisassembler::Fail; |
| 24561 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24562 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24563 | return S; |
| 24564 | case 24: |
| 24565 | tmp = fieldFromInstruction(insn, 8, 3); |
| 24566 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24567 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24568 | return MCDisassembler::Fail; |
| 24569 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24570 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24571 | return S; |
| 24572 | case 25: |
| 24573 | return S; |
| 24574 | case 26: |
| 24575 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24576 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24577 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24578 | return MCDisassembler::Fail; |
| 24579 | return S; |
| 24580 | case 27: |
| 24581 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24582 | if (!Check(S, DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24583 | tmp = fieldFromInstruction(insn, 8, 4); |
| 24584 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24585 | return S; |
| 24586 | case 28: |
| 24587 | tmp = fieldFromInstruction(insn, 0, 11); |
| 24588 | if (!Check(S, DecodeThumbBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24589 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24590 | return MCDisassembler::Fail; |
| 24591 | return S; |
| 24592 | case 29: |
| 24593 | if (!Check(S, DecodeIT(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24594 | return S; |
| 24595 | case 30: |
| 24596 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24597 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24598 | if (!Check(Out&: S, In: DecodeCCOutOperand(Inst&: MI, Decoder))) |
| 24599 | return MCDisassembler::Fail; |
| 24600 | tmp = fieldFromInstruction(insn, 3, 3); |
| 24601 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24602 | tmp = fieldFromInstruction(insn, 6, 5); |
| 24603 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24604 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24605 | return MCDisassembler::Fail; |
| 24606 | return S; |
| 24607 | case 31: |
| 24608 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24609 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24610 | if (!Check(Out&: S, In: DecodeCCOutOperand(Inst&: MI, Decoder))) |
| 24611 | return MCDisassembler::Fail; |
| 24612 | tmp = fieldFromInstruction(insn, 3, 3); |
| 24613 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24614 | tmp = fieldFromInstruction(insn, 6, 3); |
| 24615 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24616 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24617 | return MCDisassembler::Fail; |
| 24618 | return S; |
| 24619 | case 32: |
| 24620 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24621 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24622 | if (!Check(Out&: S, In: DecodeCCOutOperand(Inst&: MI, Decoder))) |
| 24623 | return MCDisassembler::Fail; |
| 24624 | tmp = fieldFromInstruction(insn, 3, 3); |
| 24625 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24626 | tmp = fieldFromInstruction(insn, 6, 3); |
| 24627 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24628 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24629 | return MCDisassembler::Fail; |
| 24630 | return S; |
| 24631 | case 33: |
| 24632 | tmp = fieldFromInstruction(insn, 8, 3); |
| 24633 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24634 | if (!Check(Out&: S, In: DecodeCCOutOperand(Inst&: MI, Decoder))) |
| 24635 | return MCDisassembler::Fail; |
| 24636 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24637 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24638 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24639 | return MCDisassembler::Fail; |
| 24640 | return S; |
| 24641 | case 34: |
| 24642 | tmp = fieldFromInstruction(insn, 8, 3); |
| 24643 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24644 | if (!Check(Out&: S, In: DecodeCCOutOperand(Inst&: MI, Decoder))) |
| 24645 | return MCDisassembler::Fail; |
| 24646 | tmp = fieldFromInstruction(insn, 8, 3); |
| 24647 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24648 | tmp = fieldFromInstruction(insn, 0, 8); |
| 24649 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24650 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24651 | return MCDisassembler::Fail; |
| 24652 | return S; |
| 24653 | case 35: |
| 24654 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24655 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24656 | if (!Check(Out&: S, In: DecodeCCOutOperand(Inst&: MI, Decoder))) |
| 24657 | return MCDisassembler::Fail; |
| 24658 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24659 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24660 | tmp = fieldFromInstruction(insn, 3, 3); |
| 24661 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24662 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24663 | return MCDisassembler::Fail; |
| 24664 | return S; |
| 24665 | case 36: |
| 24666 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24667 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24668 | if (!Check(Out&: S, In: DecodeCCOutOperand(Inst&: MI, Decoder))) |
| 24669 | return MCDisassembler::Fail; |
| 24670 | tmp = fieldFromInstruction(insn, 3, 3); |
| 24671 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24672 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24673 | return MCDisassembler::Fail; |
| 24674 | return S; |
| 24675 | case 37: |
| 24676 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24677 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24678 | if (!Check(Out&: S, In: DecodeCCOutOperand(Inst&: MI, Decoder))) |
| 24679 | return MCDisassembler::Fail; |
| 24680 | tmp = fieldFromInstruction(insn, 3, 3); |
| 24681 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24682 | tmp = fieldFromInstruction(insn, 0, 3); |
| 24683 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24684 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 24685 | return MCDisassembler::Fail; |
| 24686 | return S; |
| 24687 | case 38: |
| 24688 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24689 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24690 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24691 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24692 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24693 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24694 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24695 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24696 | tmp = fieldFromInstruction(insn, 20, 1); |
| 24697 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24698 | return S; |
| 24699 | case 39: |
| 24700 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24701 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24702 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24703 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24704 | tmp = 0x0; |
| 24705 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 24706 | tmp |= fieldFromInstruction(insn, 5, 7) << 5; |
| 24707 | if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24708 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24709 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24710 | tmp = fieldFromInstruction(insn, 20, 1); |
| 24711 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24712 | return S; |
| 24713 | case 40: |
| 24714 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24715 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24716 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24717 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24718 | tmp = 0x0; |
| 24719 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 24720 | tmp |= fieldFromInstruction(insn, 5, 2) << 5; |
| 24721 | tmp |= fieldFromInstruction(insn, 8, 4) << 8; |
| 24722 | if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24723 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24724 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24725 | tmp = fieldFromInstruction(insn, 20, 1); |
| 24726 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24727 | return S; |
| 24728 | case 41: |
| 24729 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24730 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24731 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24732 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24733 | tmp = 0x0; |
| 24734 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 24735 | tmp |= fieldFromInstruction(insn, 5, 2) << 5; |
| 24736 | tmp |= fieldFromInstruction(insn, 8, 4) << 8; |
| 24737 | if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24738 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24739 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24740 | tmp = fieldFromInstruction(insn, 20, 1); |
| 24741 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24742 | return S; |
| 24743 | case 42: |
| 24744 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24745 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24746 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24747 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24748 | tmp = fieldFromInstruction(insn, 8, 4); |
| 24749 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24750 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24751 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24752 | tmp = fieldFromInstruction(insn, 20, 1); |
| 24753 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24754 | return S; |
| 24755 | case 43: |
| 24756 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24757 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24758 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24759 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24760 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24761 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24762 | tmp = fieldFromInstruction(insn, 8, 4); |
| 24763 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24764 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24765 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24766 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24767 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24768 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24769 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24770 | return S; |
| 24771 | case 44: |
| 24772 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24773 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24774 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24775 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24776 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24777 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24778 | tmp = fieldFromInstruction(insn, 8, 4); |
| 24779 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24780 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24781 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24782 | tmp = fieldFromInstruction(insn, 20, 1); |
| 24783 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24784 | return S; |
| 24785 | case 45: |
| 24786 | if (!Check(S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24787 | return S; |
| 24788 | case 46: |
| 24789 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24790 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24791 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24792 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24793 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24794 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24795 | return S; |
| 24796 | case 47: |
| 24797 | if (!Check(S, DecodeCPSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24798 | return S; |
| 24799 | case 48: |
| 24800 | tmp = fieldFromInstruction(insn, 9, 1); |
| 24801 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24802 | return S; |
| 24803 | case 49: |
| 24804 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24805 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24806 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24807 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24808 | return S; |
| 24809 | case 50: |
| 24810 | if (!Check(S, DecodeQADDInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24811 | return S; |
| 24812 | case 51: |
| 24813 | if (!Check(S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24814 | return S; |
| 24815 | case 52: |
| 24816 | if (!Check(S, DecodeSwap(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24817 | return S; |
| 24818 | case 53: |
| 24819 | tmp = 0x0; |
| 24820 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 24821 | tmp |= fieldFromInstruction(insn, 8, 12) << 4; |
| 24822 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 24823 | return S; |
| 24824 | case 54: |
| 24825 | if (!Check(S, DecodeTSTInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24826 | return S; |
| 24827 | case 55: |
| 24828 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24829 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24830 | tmp = 0x0; |
| 24831 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 24832 | tmp |= fieldFromInstruction(insn, 5, 7) << 5; |
| 24833 | if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24834 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24835 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24836 | return S; |
| 24837 | case 56: |
| 24838 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24839 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24840 | tmp = 0x0; |
| 24841 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 24842 | tmp |= fieldFromInstruction(insn, 5, 2) << 5; |
| 24843 | tmp |= fieldFromInstruction(insn, 8, 4) << 8; |
| 24844 | if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24845 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24846 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24847 | return S; |
| 24848 | case 57: |
| 24849 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24850 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24851 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24852 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24853 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24854 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24855 | tmp = fieldFromInstruction(insn, 8, 4); |
| 24856 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24857 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24858 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24859 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24860 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24861 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24862 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24863 | return S; |
| 24864 | case 58: |
| 24865 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24866 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24867 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24868 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24869 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24870 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24871 | return S; |
| 24872 | case 59: |
| 24873 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24874 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24875 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24876 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24877 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24878 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24879 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24880 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24881 | return S; |
| 24882 | case 60: |
| 24883 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24884 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24885 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24886 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24887 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24888 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24889 | return S; |
| 24890 | case 61: |
| 24891 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24892 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24893 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24894 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24895 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24896 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24897 | return S; |
| 24898 | case 62: |
| 24899 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24900 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24901 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24902 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24903 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24904 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24905 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24906 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24907 | return S; |
| 24908 | case 63: |
| 24909 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24910 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24911 | tmp = 0x0; |
| 24912 | tmp |= fieldFromInstruction(insn, 8, 1) << 4; |
| 24913 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 24914 | tmp |= fieldFromInstruction(insn, 22, 1) << 5; |
| 24915 | if (!Check(S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24916 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24917 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24918 | return S; |
| 24919 | case 64: |
| 24920 | tmp = 0x0; |
| 24921 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 24922 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 24923 | if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24924 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24925 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24926 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24927 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24928 | return S; |
| 24929 | case 65: |
| 24930 | tmp = 0x0; |
| 24931 | tmp |= fieldFromInstruction(insn, 8, 1) << 4; |
| 24932 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 24933 | tmp |= fieldFromInstruction(insn, 22, 1) << 5; |
| 24934 | if (!Check(S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24935 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24936 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24937 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24938 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24939 | return S; |
| 24940 | case 66: |
| 24941 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24942 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24943 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24944 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24945 | return S; |
| 24946 | case 67: |
| 24947 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24948 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24949 | return S; |
| 24950 | case 68: |
| 24951 | tmp = fieldFromInstruction(insn, 16, 4); |
| 24952 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24953 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24954 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24955 | tmp = fieldFromInstruction(insn, 8, 4); |
| 24956 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24957 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24958 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24959 | return S; |
| 24960 | case 69: |
| 24961 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24962 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24963 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24964 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24965 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24966 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24967 | tmp = fieldFromInstruction(insn, 20, 1); |
| 24968 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24969 | return S; |
| 24970 | case 70: |
| 24971 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24972 | if (!Check(S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24973 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24974 | if (!Check(S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24975 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24976 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24977 | tmp = fieldFromInstruction(insn, 20, 1); |
| 24978 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24979 | return S; |
| 24980 | case 71: |
| 24981 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24982 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24983 | tmp = 0x0; |
| 24984 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 24985 | tmp |= fieldFromInstruction(insn, 5, 7) << 5; |
| 24986 | if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24987 | tmp = fieldFromInstruction(insn, 28, 4); |
| 24988 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24989 | tmp = fieldFromInstruction(insn, 20, 1); |
| 24990 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24991 | return S; |
| 24992 | case 72: |
| 24993 | tmp = fieldFromInstruction(insn, 0, 4); |
| 24994 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24995 | return S; |
| 24996 | case 73: |
| 24997 | tmp = fieldFromInstruction(insn, 12, 4); |
| 24998 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 24999 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25000 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25001 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25002 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25003 | return S; |
| 25004 | case 74: |
| 25005 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25006 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25007 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25008 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25009 | return S; |
| 25010 | case 75: |
| 25011 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25012 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25013 | tmp = 0x0; |
| 25014 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 25015 | tmp |= fieldFromInstruction(insn, 5, 2) << 5; |
| 25016 | tmp |= fieldFromInstruction(insn, 8, 4) << 8; |
| 25017 | if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25018 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25019 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25020 | tmp = fieldFromInstruction(insn, 20, 1); |
| 25021 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25022 | return S; |
| 25023 | case 76: |
| 25024 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25025 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25026 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25027 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25028 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25029 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25030 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25031 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25032 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25033 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25034 | tmp = fieldFromInstruction(insn, 20, 1); |
| 25035 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25036 | return S; |
| 25037 | case 77: |
| 25038 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25039 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25040 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25041 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25042 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25043 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25044 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25045 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25046 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25047 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25048 | return S; |
| 25049 | case 78: |
| 25050 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25051 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25052 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25053 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25054 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25055 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25056 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25057 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25058 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25059 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25060 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25061 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25062 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25063 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25064 | tmp = fieldFromInstruction(insn, 20, 1); |
| 25065 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25066 | return S; |
| 25067 | case 79: |
| 25068 | if (!Check(S, DecodeDoubleRegStore(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25069 | return S; |
| 25070 | case 80: |
| 25071 | if (!Check(S, DecodeDoubleRegLoad(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25072 | return S; |
| 25073 | case 81: |
| 25074 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25075 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25076 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25077 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25078 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25079 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25080 | tmp = 0x0; |
| 25081 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 25082 | tmp |= fieldFromInstruction(insn, 23, 1) << 4; |
| 25083 | if (!Check(S, DecodePostIdxReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25084 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25085 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25086 | return S; |
| 25087 | case 82: |
| 25088 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25089 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25090 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25091 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25092 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25093 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25094 | tmp = 0x0; |
| 25095 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 25096 | tmp |= fieldFromInstruction(insn, 8, 4) << 4; |
| 25097 | tmp |= fieldFromInstruction(insn, 23, 1) << 8; |
| 25098 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25099 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25100 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25101 | return S; |
| 25102 | case 83: |
| 25103 | if (!Check(S, DecodeLDR(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25104 | return S; |
| 25105 | case 84: |
| 25106 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25107 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25108 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25109 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25110 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25111 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25112 | tmp = 0x0; |
| 25113 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 25114 | tmp |= fieldFromInstruction(insn, 8, 4) << 4; |
| 25115 | tmp |= fieldFromInstruction(insn, 23, 1) << 8; |
| 25116 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25117 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25118 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25119 | return S; |
| 25120 | case 85: |
| 25121 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25122 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25123 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25124 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25125 | tmp = fieldFromInstruction(insn, 0, 12); |
| 25126 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25127 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25128 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25129 | tmp = fieldFromInstruction(insn, 20, 1); |
| 25130 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25131 | return S; |
| 25132 | case 86: |
| 25133 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25134 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25135 | tmp = 0x0; |
| 25136 | tmp |= fieldFromInstruction(insn, 0, 12); |
| 25137 | tmp |= fieldFromInstruction(insn, 22, 2) << 12; |
| 25138 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25139 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25140 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25141 | return S; |
| 25142 | case 87: |
| 25143 | if (!Check(S, DecodeArmMOVTWInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25144 | return S; |
| 25145 | case 88: |
| 25146 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25147 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25148 | tmp = fieldFromInstruction(insn, 0, 12); |
| 25149 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25150 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25151 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25152 | return S; |
| 25153 | case 89: |
| 25154 | if (!Check(S, DecodeTSBInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25155 | return S; |
| 25156 | case 90: |
| 25157 | if (!Check(S, DecodeHINTInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25158 | return S; |
| 25159 | case 91: |
| 25160 | tmp = 0x0; |
| 25161 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 25162 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 25163 | if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25164 | tmp = fieldFromInstruction(insn, 0, 12); |
| 25165 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25166 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25167 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25168 | return S; |
| 25169 | case 92: |
| 25170 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25171 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25172 | tmp = fieldFromInstruction(insn, 0, 12); |
| 25173 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25174 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25175 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25176 | tmp = fieldFromInstruction(insn, 20, 1); |
| 25177 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25178 | return S; |
| 25179 | case 93: |
| 25180 | if (!Check(S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25181 | return S; |
| 25182 | case 94: |
| 25183 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25184 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25185 | tmp = 0x0; |
| 25186 | tmp |= fieldFromInstruction(insn, 0, 12); |
| 25187 | tmp |= fieldFromInstruction(insn, 16, 4) << 13; |
| 25188 | tmp |= fieldFromInstruction(insn, 23, 1) << 12; |
| 25189 | if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25190 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25191 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25192 | return S; |
| 25193 | case 95: |
| 25194 | tmp = 0x0; |
| 25195 | tmp |= fieldFromInstruction(insn, 0, 12); |
| 25196 | tmp |= fieldFromInstruction(insn, 16, 4) << 13; |
| 25197 | tmp |= fieldFromInstruction(insn, 23, 1) << 12; |
| 25198 | if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25199 | return S; |
| 25200 | case 96: |
| 25201 | if (!Check(S, DecodeSTRPreImm(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25202 | return S; |
| 25203 | case 97: |
| 25204 | if (!Check(S, DecodeLDRPreImm(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25205 | return S; |
| 25206 | case 98: |
| 25207 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25208 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25209 | tmp = 0x0; |
| 25210 | tmp |= fieldFromInstruction(insn, 0, 12); |
| 25211 | tmp |= fieldFromInstruction(insn, 16, 4) << 13; |
| 25212 | tmp |= fieldFromInstruction(insn, 23, 1) << 12; |
| 25213 | if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25214 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25215 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25216 | return S; |
| 25217 | case 99: |
| 25218 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25219 | if (!Check(S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25220 | return S; |
| 25221 | case 100: |
| 25222 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25223 | if (!Check(S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25224 | return S; |
| 25225 | case 101: |
| 25226 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25227 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25228 | tmp = 0x0; |
| 25229 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 25230 | tmp |= fieldFromInstruction(insn, 5, 7) << 5; |
| 25231 | tmp |= fieldFromInstruction(insn, 16, 4) << 13; |
| 25232 | tmp |= fieldFromInstruction(insn, 23, 1) << 12; |
| 25233 | if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25234 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25235 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25236 | return S; |
| 25237 | case 102: |
| 25238 | tmp = 0x0; |
| 25239 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 25240 | tmp |= fieldFromInstruction(insn, 5, 7) << 5; |
| 25241 | tmp |= fieldFromInstruction(insn, 16, 4) << 13; |
| 25242 | tmp |= fieldFromInstruction(insn, 23, 1) << 12; |
| 25243 | if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25244 | return S; |
| 25245 | case 103: |
| 25246 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25247 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25248 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25249 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25250 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25251 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25252 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25253 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25254 | return S; |
| 25255 | case 104: |
| 25256 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25257 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25258 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25259 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25260 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25261 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25262 | tmp = fieldFromInstruction(insn, 7, 5); |
| 25263 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25264 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25265 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25266 | return S; |
| 25267 | case 105: |
| 25268 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25269 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25270 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25271 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25272 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25273 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25274 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25275 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25276 | return S; |
| 25277 | case 106: |
| 25278 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25279 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25280 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25281 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25282 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25283 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25284 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25285 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25286 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25287 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25288 | return S; |
| 25289 | case 107: |
| 25290 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25291 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25292 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25293 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25294 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25295 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25296 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25297 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25298 | return S; |
| 25299 | case 108: |
| 25300 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25301 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25302 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25303 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25304 | tmp = fieldFromInstruction(insn, 10, 2); |
| 25305 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25306 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25307 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25308 | return S; |
| 25309 | case 109: |
| 25310 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25311 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25312 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25313 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25314 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25315 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25316 | tmp = fieldFromInstruction(insn, 10, 2); |
| 25317 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25318 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25319 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25320 | return S; |
| 25321 | case 110: |
| 25322 | if (!Check(S, DecodeSTRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25323 | return S; |
| 25324 | case 111: |
| 25325 | if (!Check(S, DecodeLDRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25326 | return S; |
| 25327 | case 112: |
| 25328 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25329 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25330 | tmp = fieldFromInstruction(insn, 16, 5); |
| 25331 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25332 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25333 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25334 | tmp = 0x0; |
| 25335 | tmp |= fieldFromInstruction(insn, 6, 1) << 5; |
| 25336 | tmp |= fieldFromInstruction(insn, 7, 5); |
| 25337 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25338 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25339 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25340 | return S; |
| 25341 | case 113: |
| 25342 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25343 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25344 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25345 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25346 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25347 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25348 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25349 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25350 | return S; |
| 25351 | case 114: |
| 25352 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25353 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25354 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25355 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25356 | tmp = fieldFromInstruction(insn, 7, 5); |
| 25357 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25358 | tmp = fieldFromInstruction(insn, 16, 5); |
| 25359 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25360 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25361 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25362 | return S; |
| 25363 | case 115: |
| 25364 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25365 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25366 | tmp = 0x0; |
| 25367 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 25368 | tmp |= fieldFromInstruction(insn, 5, 7) << 5; |
| 25369 | tmp |= fieldFromInstruction(insn, 16, 4) << 13; |
| 25370 | tmp |= fieldFromInstruction(insn, 23, 1) << 12; |
| 25371 | if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25372 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25373 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25374 | return S; |
| 25375 | case 116: |
| 25376 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25377 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25378 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25379 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25380 | tmp = 0x0; |
| 25381 | tmp |= fieldFromInstruction(insn, 7, 5); |
| 25382 | tmp |= fieldFromInstruction(insn, 16, 5) << 5; |
| 25383 | if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25384 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25385 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25386 | return S; |
| 25387 | case 117: |
| 25388 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25389 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25390 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25391 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25392 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25393 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25394 | tmp = 0x0; |
| 25395 | tmp |= fieldFromInstruction(insn, 7, 5); |
| 25396 | tmp |= fieldFromInstruction(insn, 16, 5) << 5; |
| 25397 | if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25398 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25399 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25400 | return S; |
| 25401 | case 118: |
| 25402 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25403 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25404 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25405 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25406 | tmp = fieldFromInstruction(insn, 0, 16); |
| 25407 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25408 | return S; |
| 25409 | case 119: |
| 25410 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25411 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25412 | return S; |
| 25413 | case 120: |
| 25414 | if (!Check(S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25415 | return S; |
| 25416 | case 121: |
| 25417 | tmp = fieldFromInstruction(insn, 0, 5); |
| 25418 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25419 | return S; |
| 25420 | case 122: |
| 25421 | if (!Check(S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25422 | return S; |
| 25423 | case 123: |
| 25424 | tmp = 0x0; |
| 25425 | tmp |= fieldFromInstruction(insn, 0, 24) << 1; |
| 25426 | tmp |= fieldFromInstruction(insn, 24, 1); |
| 25427 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25428 | return S; |
| 25429 | case 124: |
| 25430 | if (!Check(S, DecoderForMRRC2AndMCRR2(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25431 | return S; |
| 25432 | case 125: |
| 25433 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25434 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25435 | tmp = fieldFromInstruction(insn, 4, 4); |
| 25436 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25437 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25438 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25439 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25440 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25441 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25442 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25443 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25444 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25445 | return S; |
| 25446 | case 126: |
| 25447 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25448 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25449 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25450 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25451 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25452 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25453 | tmp = fieldFromInstruction(insn, 4, 4); |
| 25454 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25455 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25456 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25457 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25458 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25459 | return S; |
| 25460 | case 127: |
| 25461 | tmp = fieldFromInstruction(insn, 0, 24); |
| 25462 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25463 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25464 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25465 | return S; |
| 25466 | case 128: |
| 25467 | if (!Check(S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25468 | return S; |
| 25469 | case 129: |
| 25470 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25471 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25472 | tmp = fieldFromInstruction(insn, 20, 4); |
| 25473 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25474 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25475 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25476 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25477 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25478 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25479 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25480 | tmp = fieldFromInstruction(insn, 5, 3); |
| 25481 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25482 | return S; |
| 25483 | case 130: |
| 25484 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25485 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25486 | tmp = fieldFromInstruction(insn, 20, 4); |
| 25487 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25488 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25489 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25490 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25491 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25492 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25493 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25494 | tmp = fieldFromInstruction(insn, 5, 3); |
| 25495 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25496 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25497 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25498 | return S; |
| 25499 | case 131: |
| 25500 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25501 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25502 | tmp = fieldFromInstruction(insn, 21, 3); |
| 25503 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25504 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25505 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25506 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25507 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25508 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25509 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25510 | tmp = fieldFromInstruction(insn, 5, 3); |
| 25511 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25512 | return S; |
| 25513 | case 132: |
| 25514 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25515 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25516 | tmp = fieldFromInstruction(insn, 21, 3); |
| 25517 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25518 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25519 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25520 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25521 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25522 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25523 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25524 | tmp = fieldFromInstruction(insn, 5, 3); |
| 25525 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25526 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25527 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25528 | return S; |
| 25529 | case 133: |
| 25530 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25531 | if (!Check(S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25532 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25533 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25534 | tmp = fieldFromInstruction(insn, 21, 3); |
| 25535 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25536 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25537 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25538 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25539 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25540 | tmp = fieldFromInstruction(insn, 5, 3); |
| 25541 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25542 | return S; |
| 25543 | case 134: |
| 25544 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25545 | if (!Check(S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25546 | tmp = fieldFromInstruction(insn, 8, 4); |
| 25547 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25548 | tmp = fieldFromInstruction(insn, 21, 3); |
| 25549 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25550 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25551 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25552 | tmp = fieldFromInstruction(insn, 0, 4); |
| 25553 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25554 | tmp = fieldFromInstruction(insn, 5, 3); |
| 25555 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25556 | tmp = fieldFromInstruction(insn, 28, 4); |
| 25557 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25558 | return S; |
| 25559 | case 135: |
| 25560 | if (!Check(S, DecodeMveVCTP(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25561 | return S; |
| 25562 | case 136: |
| 25563 | if (!Check(S, DecodeMVEOverlappingLongShift(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25564 | return S; |
| 25565 | case 137: |
| 25566 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25567 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25568 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25569 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25570 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25571 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25572 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 25573 | return MCDisassembler::Fail; |
| 25574 | return S; |
| 25575 | case 138: |
| 25576 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25577 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25578 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25579 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25580 | tmp = 0x0; |
| 25581 | tmp |= fieldFromInstruction(insn, 6, 2); |
| 25582 | tmp |= fieldFromInstruction(insn, 12, 3) << 2; |
| 25583 | if (!Check(S, DecodeLongShiftOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25584 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 25585 | return MCDisassembler::Fail; |
| 25586 | return S; |
| 25587 | case 139: |
| 25588 | tmp = fieldFromInstruction(insn, 17, 3) << 1; |
| 25589 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25590 | tmp = fieldFromInstruction(insn, 9, 3) << 1; |
| 25591 | if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25592 | tmp = fieldFromInstruction(insn, 17, 3) << 1; |
| 25593 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25594 | tmp = fieldFromInstruction(insn, 9, 3) << 1; |
| 25595 | if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25596 | tmp = 0x0; |
| 25597 | tmp |= fieldFromInstruction(insn, 6, 2); |
| 25598 | tmp |= fieldFromInstruction(insn, 12, 3) << 2; |
| 25599 | if (!Check(S, DecodeLongShiftOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25600 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 25601 | return MCDisassembler::Fail; |
| 25602 | return S; |
| 25603 | case 140: |
| 25604 | tmp = 0x0; |
| 25605 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 25606 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 25607 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25608 | tmp = 0x0; |
| 25609 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25610 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25611 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25612 | tmp = 0x0; |
| 25613 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 25614 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 25615 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25616 | tmp = fieldFromInstruction(insn, 24, 1); |
| 25617 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25618 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 25619 | return MCDisassembler::Fail; |
| 25620 | return S; |
| 25621 | case 141: |
| 25622 | tmp = 0x0; |
| 25623 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 25624 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 25625 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25626 | tmp = 0x0; |
| 25627 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 25628 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 25629 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25630 | tmp = 0x0; |
| 25631 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25632 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25633 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25634 | tmp = 0x0; |
| 25635 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 25636 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 25637 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25638 | tmp = fieldFromInstruction(insn, 23, 2); |
| 25639 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25640 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25641 | return MCDisassembler::Fail; |
| 25642 | return S; |
| 25643 | case 142: |
| 25644 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25645 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25646 | tmp = 0x0; |
| 25647 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 25648 | tmp |= fieldFromInstruction(insn, 16, 4) << 3; |
| 25649 | if (!Check(S, DecodeMveAddrModeRQ(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25650 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25651 | return MCDisassembler::Fail; |
| 25652 | return S; |
| 25653 | case 143: |
| 25654 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25655 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25656 | tmp = 0x0; |
| 25657 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25658 | tmp |= fieldFromInstruction(insn, 16, 3) << 8; |
| 25659 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25660 | if (!Check(S, DecodeTAddrModeImm7<0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25661 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25662 | return MCDisassembler::Fail; |
| 25663 | return S; |
| 25664 | case 144: |
| 25665 | tmp = fieldFromInstruction(insn, 16, 3); |
| 25666 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25667 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25668 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25669 | tmp = fieldFromInstruction(insn, 16, 3); |
| 25670 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25671 | tmp = 0x0; |
| 25672 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25673 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25674 | if (!Check(S, DecodeT2Imm7<0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25675 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25676 | return MCDisassembler::Fail; |
| 25677 | return S; |
| 25678 | case 145: |
| 25679 | if (!Check(S, DecodeMVE_MEM_1_pre<0>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25680 | return S; |
| 25681 | case 146: |
| 25682 | if (!Check(S, DecodeMVEVMOVQtoDReg(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25683 | return S; |
| 25684 | case 147: |
| 25685 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25686 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25687 | tmp = 0x0; |
| 25688 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25689 | tmp |= fieldFromInstruction(insn, 16, 3) << 8; |
| 25690 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25691 | if (!Check(S, DecodeTAddrModeImm7<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25692 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25693 | return MCDisassembler::Fail; |
| 25694 | return S; |
| 25695 | case 148: |
| 25696 | if (!Check(S, DecodeMVEVMOVDRegtoQ(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25697 | return S; |
| 25698 | case 149: |
| 25699 | tmp = fieldFromInstruction(insn, 16, 3); |
| 25700 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25701 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25702 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25703 | tmp = fieldFromInstruction(insn, 16, 3); |
| 25704 | if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25705 | tmp = 0x0; |
| 25706 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25707 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25708 | if (!Check(S, DecodeT2Imm7<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25709 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25710 | return MCDisassembler::Fail; |
| 25711 | return S; |
| 25712 | case 150: |
| 25713 | if (!Check(S, DecodeMVE_MEM_1_pre<1>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25714 | return S; |
| 25715 | case 151: |
| 25716 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25717 | if (!Check(S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25718 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25719 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25720 | return S; |
| 25721 | case 152: |
| 25722 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25723 | if (!Check(S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25724 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25725 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25726 | return S; |
| 25727 | case 153: |
| 25728 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25729 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25730 | tmp = 0x0; |
| 25731 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25732 | tmp |= fieldFromInstruction(insn, 16, 4) << 8; |
| 25733 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25734 | if (!Check(S, DecodeT2AddrModeImm7<0, 0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25735 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25736 | return MCDisassembler::Fail; |
| 25737 | return S; |
| 25738 | case 154: |
| 25739 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25740 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25741 | tmp = 0x0; |
| 25742 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25743 | tmp |= fieldFromInstruction(insn, 17, 3) << 8; |
| 25744 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25745 | if (!Check(S, DecodeMveAddrModeQ<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25746 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25747 | return MCDisassembler::Fail; |
| 25748 | return S; |
| 25749 | case 155: |
| 25750 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25751 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25752 | tmp = 0x0; |
| 25753 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25754 | tmp |= fieldFromInstruction(insn, 16, 4) << 8; |
| 25755 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25756 | if (!Check(S, DecodeT2AddrModeImm7<1, 0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25757 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25758 | return MCDisassembler::Fail; |
| 25759 | return S; |
| 25760 | case 156: |
| 25761 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25762 | if (!Check(S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25763 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25764 | if (!Check(S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25765 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25766 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25767 | return S; |
| 25768 | case 157: |
| 25769 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25770 | if (!Check(S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25771 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25772 | if (!Check(S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25773 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25774 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25775 | return S; |
| 25776 | case 158: |
| 25777 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25778 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25779 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25780 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25781 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25782 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25783 | tmp = 0x0; |
| 25784 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25785 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25786 | if (!Check(S, DecodeT2Imm7<0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25787 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25788 | return MCDisassembler::Fail; |
| 25789 | return S; |
| 25790 | case 159: |
| 25791 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25792 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25793 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25794 | if (!Check(S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25795 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25796 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25797 | return S; |
| 25798 | case 160: |
| 25799 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25800 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25801 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25802 | if (!Check(S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25803 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25804 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25805 | return S; |
| 25806 | case 161: |
| 25807 | if (!Check(S, DecodeMVE_MEM_2_pre<0>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25808 | return S; |
| 25809 | case 162: |
| 25810 | if (!Check(S, DecodeMVE_MEM_3_pre<2>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25811 | return S; |
| 25812 | case 163: |
| 25813 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25814 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25815 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25816 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25817 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25818 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25819 | tmp = 0x0; |
| 25820 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25821 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25822 | if (!Check(S, DecodeT2Imm7<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25823 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25824 | return MCDisassembler::Fail; |
| 25825 | return S; |
| 25826 | case 164: |
| 25827 | if (!Check(S, DecodeMVE_MEM_2_pre<1>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25828 | return S; |
| 25829 | case 165: |
| 25830 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25831 | if (!Check(S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25832 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25833 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25834 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25835 | if (!Check(S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25836 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25837 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25838 | return S; |
| 25839 | case 166: |
| 25840 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25841 | if (!Check(S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25842 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25843 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25844 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25845 | if (!Check(S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25846 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25847 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25848 | return S; |
| 25849 | case 167: |
| 25850 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25851 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25852 | tmp = 0x0; |
| 25853 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25854 | tmp |= fieldFromInstruction(insn, 16, 4) << 8; |
| 25855 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25856 | if (!Check(S, DecodeT2AddrModeImm7<2, 0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25857 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25858 | return MCDisassembler::Fail; |
| 25859 | return S; |
| 25860 | case 168: |
| 25861 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25862 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25863 | tmp = 0x0; |
| 25864 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25865 | tmp |= fieldFromInstruction(insn, 17, 3) << 8; |
| 25866 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25867 | if (!Check(S, DecodeMveAddrModeQ<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25868 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25869 | return MCDisassembler::Fail; |
| 25870 | return S; |
| 25871 | case 169: |
| 25872 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25873 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25874 | tmp = fieldFromInstruction(insn, 13, 3); |
| 25875 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25876 | tmp = fieldFromInstruction(insn, 16, 4); |
| 25877 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25878 | tmp = 0x0; |
| 25879 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 25880 | tmp |= fieldFromInstruction(insn, 23, 1) << 7; |
| 25881 | if (!Check(S, DecodeT2Imm7<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25882 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 25883 | return MCDisassembler::Fail; |
| 25884 | return S; |
| 25885 | case 170: |
| 25886 | if (!Check(S, DecodeMVE_MEM_2_pre<2>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25887 | return S; |
| 25888 | case 171: |
| 25889 | if (!Check(S, DecodeMVE_MEM_3_pre<3>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25890 | return S; |
| 25891 | case 172: |
| 25892 | tmp = 0x0; |
| 25893 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25894 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25895 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25896 | tmp = 0x0; |
| 25897 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25898 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25899 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25900 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25901 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25902 | tmp = 0x0; |
| 25903 | tmp |= fieldFromInstruction(insn, 16, 1) << 1; |
| 25904 | tmp |= fieldFromInstruction(insn, 21, 1); |
| 25905 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25906 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 25907 | return MCDisassembler::Fail; |
| 25908 | return S; |
| 25909 | case 173: |
| 25910 | tmp = 0x0; |
| 25911 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25912 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25913 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25914 | tmp = 0x0; |
| 25915 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25916 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25917 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25918 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25919 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25920 | tmp = 0x0; |
| 25921 | tmp |= fieldFromInstruction(insn, 6, 1); |
| 25922 | tmp |= fieldFromInstruction(insn, 16, 1) << 2; |
| 25923 | tmp |= fieldFromInstruction(insn, 21, 1) << 1; |
| 25924 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25925 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 25926 | return MCDisassembler::Fail; |
| 25927 | return S; |
| 25928 | case 174: |
| 25929 | tmp = 0x0; |
| 25930 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25931 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25932 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25933 | tmp = 0x0; |
| 25934 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25935 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25936 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25937 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25938 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25939 | tmp = 0x0; |
| 25940 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 25941 | tmp |= fieldFromInstruction(insn, 16, 1) << 3; |
| 25942 | tmp |= fieldFromInstruction(insn, 21, 1) << 2; |
| 25943 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25944 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 25945 | return MCDisassembler::Fail; |
| 25946 | return S; |
| 25947 | case 175: |
| 25948 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25949 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25950 | tmp = 0x0; |
| 25951 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25952 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25953 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25954 | tmp = 0x0; |
| 25955 | tmp |= fieldFromInstruction(insn, 16, 1) << 1; |
| 25956 | tmp |= fieldFromInstruction(insn, 21, 1); |
| 25957 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25958 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 25959 | return MCDisassembler::Fail; |
| 25960 | return S; |
| 25961 | case 176: |
| 25962 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25963 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25964 | tmp = 0x0; |
| 25965 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25966 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25967 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25968 | tmp = 0x0; |
| 25969 | tmp |= fieldFromInstruction(insn, 6, 1); |
| 25970 | tmp |= fieldFromInstruction(insn, 16, 1) << 2; |
| 25971 | tmp |= fieldFromInstruction(insn, 21, 1) << 1; |
| 25972 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25973 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 25974 | return MCDisassembler::Fail; |
| 25975 | return S; |
| 25976 | case 177: |
| 25977 | tmp = fieldFromInstruction(insn, 12, 4); |
| 25978 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25979 | tmp = 0x0; |
| 25980 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 25981 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 25982 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25983 | tmp = 0x0; |
| 25984 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 25985 | tmp |= fieldFromInstruction(insn, 16, 1) << 3; |
| 25986 | tmp |= fieldFromInstruction(insn, 21, 1) << 2; |
| 25987 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 25988 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 25989 | return MCDisassembler::Fail; |
| 25990 | return S; |
| 25991 | case 178: |
| 25992 | tmp = 0x0; |
| 25993 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 25994 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 25995 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 25996 | tmp = 0x0; |
| 25997 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 25998 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 25999 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26000 | tmp = 0x0; |
| 26001 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26002 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26003 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26004 | tmp = 0x0; |
| 26005 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26006 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26007 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26008 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26009 | return MCDisassembler::Fail; |
| 26010 | return S; |
| 26011 | case 179: |
| 26012 | tmp = 0x0; |
| 26013 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26014 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26015 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26016 | tmp = 0x0; |
| 26017 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26018 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26019 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26020 | tmp = 0x0; |
| 26021 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26022 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26023 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26024 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26025 | return MCDisassembler::Fail; |
| 26026 | return S; |
| 26027 | case 180: |
| 26028 | tmp = 0x0; |
| 26029 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26030 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26031 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26032 | tmp = 0x0; |
| 26033 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26034 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26035 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26036 | tmp = 0x0; |
| 26037 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26038 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26039 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26040 | tmp = fieldFromInstruction(insn, 0, 4); |
| 26041 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26042 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26043 | return MCDisassembler::Fail; |
| 26044 | return S; |
| 26045 | case 181: |
| 26046 | tmp = 0x0; |
| 26047 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26048 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26049 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26050 | tmp = 0x0; |
| 26051 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26052 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26053 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26054 | tmp = fieldFromInstruction(insn, 0, 4); |
| 26055 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26056 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26057 | return MCDisassembler::Fail; |
| 26058 | return S; |
| 26059 | case 182: |
| 26060 | tmp = 0x0; |
| 26061 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26062 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26063 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26064 | tmp = 0x0; |
| 26065 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26066 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26067 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26068 | tmp = 0x0; |
| 26069 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26070 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26071 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26072 | tmp = 0x0; |
| 26073 | tmp |= fieldFromInstruction(insn, 0, 1); |
| 26074 | tmp |= fieldFromInstruction(insn, 12, 1) << 1; |
| 26075 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26076 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26077 | return MCDisassembler::Fail; |
| 26078 | return S; |
| 26079 | case 183: |
| 26080 | tmp = 0x0; |
| 26081 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26082 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26083 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26084 | tmp = 0x0; |
| 26085 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26086 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26087 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26088 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26089 | return MCDisassembler::Fail; |
| 26090 | return S; |
| 26091 | case 184: |
| 26092 | tmp = 0x0; |
| 26093 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26094 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26095 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26096 | tmp = 0x0; |
| 26097 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26098 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26099 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26100 | tmp = 0x0; |
| 26101 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26102 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26103 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26104 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26105 | return MCDisassembler::Fail; |
| 26106 | return S; |
| 26107 | case 185: |
| 26108 | tmp = 0x0; |
| 26109 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26110 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26111 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26112 | tmp = 0x0; |
| 26113 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26114 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26115 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26116 | tmp = fieldFromInstruction(insn, 0, 4); |
| 26117 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26118 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26119 | return MCDisassembler::Fail; |
| 26120 | return S; |
| 26121 | case 186: |
| 26122 | tmp = 0x0; |
| 26123 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26124 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26125 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26126 | tmp = 0x0; |
| 26127 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26128 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26129 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26130 | tmp = 0x0; |
| 26131 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26132 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26133 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26134 | tmp = fieldFromInstruction(insn, 12, 1); |
| 26135 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26136 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26137 | return MCDisassembler::Fail; |
| 26138 | return S; |
| 26139 | case 187: |
| 26140 | if (!Check(S, DecodeMVEVCMP<false,DecodeRestrictedIPredicateOperand>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26141 | return S; |
| 26142 | case 188: |
| 26143 | tmp = 0x0; |
| 26144 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26145 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26146 | if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26147 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26148 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26149 | tmp = 0x0; |
| 26150 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26151 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26152 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26153 | tmp = fieldFromInstruction(insn, 7, 1); |
| 26154 | if (!Check(S, DecodeRestrictedIPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26155 | return S; |
| 26156 | case 189: |
| 26157 | if (!Check(S, DecodeMVEVCMP<false,DecodeRestrictedUPredicateOperand>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26158 | return S; |
| 26159 | case 190: |
| 26160 | tmp = 0x0; |
| 26161 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26162 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26163 | if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26164 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26165 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26166 | tmp = 0x0; |
| 26167 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26168 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26169 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26170 | tmp = fieldFromInstruction(insn, 7, 1); |
| 26171 | if (!Check(S, DecodeRestrictedUPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26172 | return S; |
| 26173 | case 191: |
| 26174 | if (!Check(S, DecodeMVEVCMP<false,DecodeRestrictedSPredicateOperand>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26175 | return S; |
| 26176 | case 192: |
| 26177 | tmp = 0x0; |
| 26178 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26179 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26180 | if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26181 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26182 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26183 | tmp = 0x0; |
| 26184 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26185 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26186 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26187 | tmp = 0x0; |
| 26188 | tmp |= fieldFromInstruction(insn, 0, 1) << 1; |
| 26189 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 26190 | if (!Check(S, DecodeRestrictedSPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26191 | return S; |
| 26192 | case 193: |
| 26193 | if (!Check(S, DecodeMVEVCMP<true,DecodeRestrictedIPredicateOperand>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26194 | return S; |
| 26195 | case 194: |
| 26196 | tmp = 0x0; |
| 26197 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26198 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26199 | if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26200 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26201 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26202 | tmp = fieldFromInstruction(insn, 0, 4); |
| 26203 | if (!Check(S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26204 | tmp = fieldFromInstruction(insn, 7, 1); |
| 26205 | if (!Check(S, DecodeRestrictedIPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26206 | return S; |
| 26207 | case 195: |
| 26208 | tmp = 0x0; |
| 26209 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26210 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26211 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26212 | tmp = fieldFromInstruction(insn, 17, 3) << 1; |
| 26213 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26214 | tmp = fieldFromInstruction(insn, 17, 3) << 1; |
| 26215 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26216 | tmp = 0x0; |
| 26217 | tmp |= fieldFromInstruction(insn, 0, 1); |
| 26218 | tmp |= fieldFromInstruction(insn, 7, 1) << 1; |
| 26219 | if (!Check(S, DecodePowerTwoOperand<0,3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26220 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26221 | return MCDisassembler::Fail; |
| 26222 | return S; |
| 26223 | case 196: |
| 26224 | tmp = 0x0; |
| 26225 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26226 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26227 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26228 | tmp = fieldFromInstruction(insn, 17, 3) << 1; |
| 26229 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26230 | tmp = fieldFromInstruction(insn, 17, 3) << 1; |
| 26231 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26232 | tmp = fieldFromInstruction(insn, 1, 3) << 1; |
| 26233 | if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26234 | tmp = 0x0; |
| 26235 | tmp |= fieldFromInstruction(insn, 0, 1); |
| 26236 | tmp |= fieldFromInstruction(insn, 7, 1) << 1; |
| 26237 | if (!Check(S, DecodePowerTwoOperand<0,3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26238 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26239 | return MCDisassembler::Fail; |
| 26240 | return S; |
| 26241 | case 197: |
| 26242 | if (!Check(S, DecodeMVEVCMP<true,DecodeRestrictedUPredicateOperand>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26243 | return S; |
| 26244 | case 198: |
| 26245 | tmp = 0x0; |
| 26246 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26247 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26248 | if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26249 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26250 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26251 | tmp = fieldFromInstruction(insn, 0, 4); |
| 26252 | if (!Check(S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26253 | tmp = fieldFromInstruction(insn, 7, 1); |
| 26254 | if (!Check(S, DecodeRestrictedUPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26255 | return S; |
| 26256 | case 199: |
| 26257 | if (!Check(S, DecodeMVEVCMP<true,DecodeRestrictedSPredicateOperand>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26258 | return S; |
| 26259 | case 200: |
| 26260 | tmp = 0x0; |
| 26261 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26262 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26263 | if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26264 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26265 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26266 | tmp = fieldFromInstruction(insn, 0, 4); |
| 26267 | if (!Check(S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26268 | tmp = 0x0; |
| 26269 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 26270 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 26271 | if (!Check(S, DecodeRestrictedSPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26272 | return S; |
| 26273 | case 201: |
| 26274 | if (!Check(S, DecodeMVEVADCInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26275 | return S; |
| 26276 | case 202: |
| 26277 | if (!Check(S, DecodeMVEVCMP<false,DecodeRestrictedFPPredicateOperand>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26278 | return S; |
| 26279 | case 203: |
| 26280 | tmp = 0x0; |
| 26281 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26282 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26283 | if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26284 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26285 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26286 | tmp = 0x0; |
| 26287 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26288 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26289 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26290 | tmp = 0x0; |
| 26291 | tmp |= fieldFromInstruction(insn, 0, 1) << 1; |
| 26292 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 26293 | tmp |= fieldFromInstruction(insn, 12, 1) << 2; |
| 26294 | if (!Check(S, DecodeRestrictedFPPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26295 | return S; |
| 26296 | case 204: |
| 26297 | tmp = 0x0; |
| 26298 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26299 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26300 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26301 | tmp = 0x0; |
| 26302 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26303 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26304 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26305 | tmp = 0x0; |
| 26306 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26307 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26308 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26309 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26310 | return MCDisassembler::Fail; |
| 26311 | return S; |
| 26312 | case 205: |
| 26313 | if (!Check(S, DecodeMVEVCMP<true,DecodeRestrictedFPPredicateOperand>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26314 | return S; |
| 26315 | case 206: |
| 26316 | tmp = 0x0; |
| 26317 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26318 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26319 | if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26320 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26321 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26322 | tmp = fieldFromInstruction(insn, 0, 4); |
| 26323 | if (!Check(S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26324 | tmp = 0x0; |
| 26325 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 26326 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 26327 | tmp |= fieldFromInstruction(insn, 12, 1) << 2; |
| 26328 | if (!Check(S, DecodeRestrictedFPPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26329 | return S; |
| 26330 | case 207: |
| 26331 | if (!Check(S, DecodeMVEVPNOT(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26332 | return S; |
| 26333 | case 208: |
| 26334 | tmp = 0x0; |
| 26335 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26336 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26337 | if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26338 | return S; |
| 26339 | case 209: |
| 26340 | tmp = 0x0; |
| 26341 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26342 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26343 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26344 | tmp = fieldFromInstruction(insn, 12, 4); |
| 26345 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26346 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26347 | return MCDisassembler::Fail; |
| 26348 | return S; |
| 26349 | case 210: |
| 26350 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26351 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26352 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26353 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26354 | tmp = fieldFromInstruction(insn, 1, 3); |
| 26355 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26356 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26357 | return MCDisassembler::Fail; |
| 26358 | return S; |
| 26359 | case 211: |
| 26360 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26361 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26362 | tmp = fieldFromInstruction(insn, 20, 3) << 1; |
| 26363 | if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26364 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26365 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26366 | tmp = fieldFromInstruction(insn, 1, 3); |
| 26367 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26368 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26369 | return MCDisassembler::Fail; |
| 26370 | return S; |
| 26371 | case 212: |
| 26372 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26373 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26374 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26375 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26376 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26377 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26378 | tmp = fieldFromInstruction(insn, 1, 3); |
| 26379 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26380 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26381 | return MCDisassembler::Fail; |
| 26382 | return S; |
| 26383 | case 213: |
| 26384 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26385 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26386 | tmp = fieldFromInstruction(insn, 20, 3) << 1; |
| 26387 | if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26388 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26389 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26390 | tmp = fieldFromInstruction(insn, 20, 3) << 1; |
| 26391 | if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26392 | tmp = fieldFromInstruction(insn, 17, 3); |
| 26393 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26394 | tmp = fieldFromInstruction(insn, 1, 3); |
| 26395 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26396 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26397 | return MCDisassembler::Fail; |
| 26398 | return S; |
| 26399 | case 214: |
| 26400 | tmp = fieldFromInstruction(insn, 12, 4); |
| 26401 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26402 | tmp = fieldFromInstruction(insn, 12, 4); |
| 26403 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26404 | tmp = fieldFromInstruction(insn, 1, 3); |
| 26405 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26406 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26407 | return MCDisassembler::Fail; |
| 26408 | return S; |
| 26409 | case 215: |
| 26410 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26411 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26412 | tmp = fieldFromInstruction(insn, 1, 3); |
| 26413 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26414 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26415 | return MCDisassembler::Fail; |
| 26416 | return S; |
| 26417 | case 216: |
| 26418 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26419 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26420 | tmp = fieldFromInstruction(insn, 20, 3) << 1; |
| 26421 | if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26422 | tmp = fieldFromInstruction(insn, 1, 3); |
| 26423 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26424 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26425 | return MCDisassembler::Fail; |
| 26426 | return S; |
| 26427 | case 217: |
| 26428 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26429 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26430 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26431 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26432 | tmp = fieldFromInstruction(insn, 1, 3); |
| 26433 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26434 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26435 | return MCDisassembler::Fail; |
| 26436 | return S; |
| 26437 | case 218: |
| 26438 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26439 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26440 | tmp = fieldFromInstruction(insn, 20, 3) << 1; |
| 26441 | if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26442 | tmp = fieldFromInstruction(insn, 13, 3) << 1; |
| 26443 | if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26444 | tmp = fieldFromInstruction(insn, 20, 3) << 1; |
| 26445 | if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26446 | tmp = fieldFromInstruction(insn, 1, 3); |
| 26447 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26448 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26449 | return MCDisassembler::Fail; |
| 26450 | return S; |
| 26451 | case 219: |
| 26452 | tmp = fieldFromInstruction(insn, 12, 4); |
| 26453 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26454 | tmp = fieldFromInstruction(insn, 12, 4); |
| 26455 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26456 | tmp = 0x0; |
| 26457 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26458 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26459 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26460 | tmp = 0x0; |
| 26461 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26462 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26463 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26464 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26465 | return MCDisassembler::Fail; |
| 26466 | return S; |
| 26467 | case 220: |
| 26468 | tmp = 0x0; |
| 26469 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26470 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26471 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26472 | tmp = 0x0; |
| 26473 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26474 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26475 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26476 | tmp = 0x0; |
| 26477 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26478 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26479 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26480 | tmp = fieldFromInstruction(insn, 16, 3); |
| 26481 | if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26482 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26483 | return MCDisassembler::Fail; |
| 26484 | return S; |
| 26485 | case 221: |
| 26486 | tmp = 0x0; |
| 26487 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26488 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26489 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26490 | tmp = 0x0; |
| 26491 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26492 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26493 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26494 | tmp = 0x0; |
| 26495 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26496 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26497 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26498 | tmp = fieldFromInstruction(insn, 16, 4); |
| 26499 | if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26500 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26501 | return MCDisassembler::Fail; |
| 26502 | return S; |
| 26503 | case 222: |
| 26504 | tmp = 0x0; |
| 26505 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26506 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26507 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26508 | tmp = 0x0; |
| 26509 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26510 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26511 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26512 | tmp = fieldFromInstruction(insn, 16, 3); |
| 26513 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26514 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26515 | return MCDisassembler::Fail; |
| 26516 | return S; |
| 26517 | case 223: |
| 26518 | tmp = 0x0; |
| 26519 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26520 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26521 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26522 | tmp = 0x0; |
| 26523 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26524 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26525 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26526 | tmp = fieldFromInstruction(insn, 16, 4); |
| 26527 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26528 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26529 | return MCDisassembler::Fail; |
| 26530 | return S; |
| 26531 | case 224: |
| 26532 | tmp = fieldFromInstruction(insn, 0, 4); |
| 26533 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26534 | tmp = 0x0; |
| 26535 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26536 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26537 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26538 | tmp = 0x0; |
| 26539 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26540 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26541 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26542 | tmp = fieldFromInstruction(insn, 0, 4); |
| 26543 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26544 | tmp = fieldFromInstruction(insn, 16, 5); |
| 26545 | if (!Check(S, DecodeLongShiftOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26546 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26547 | return MCDisassembler::Fail; |
| 26548 | return S; |
| 26549 | case 225: |
| 26550 | tmp = 0x0; |
| 26551 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26552 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26553 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26554 | tmp = 0x0; |
| 26555 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26556 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26557 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26558 | tmp = 0x0; |
| 26559 | tmp |= fieldFromInstruction(insn, 7, 1) << 3; |
| 26560 | tmp |= fieldFromInstruction(insn, 17, 3); |
| 26561 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26562 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26563 | return MCDisassembler::Fail; |
| 26564 | return S; |
| 26565 | case 226: |
| 26566 | if (!Check(S, DecodeMVEModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26567 | return S; |
| 26568 | case 227: |
| 26569 | tmp = 0x0; |
| 26570 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26571 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26572 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26573 | tmp = 0x0; |
| 26574 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26575 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26576 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26577 | tmp = 0x0; |
| 26578 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26579 | tmp |= fieldFromInstruction(insn, 9, 2) << 9; |
| 26580 | tmp |= fieldFromInstruction(insn, 16, 3) << 4; |
| 26581 | tmp |= fieldFromInstruction(insn, 28, 1) << 7; |
| 26582 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26583 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26584 | return MCDisassembler::Fail; |
| 26585 | return S; |
| 26586 | case 228: |
| 26587 | tmp = 0x0; |
| 26588 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26589 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26590 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26591 | tmp = 0x0; |
| 26592 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26593 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26594 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26595 | tmp = 0x0; |
| 26596 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26597 | tmp |= fieldFromInstruction(insn, 9, 1) << 9; |
| 26598 | tmp |= fieldFromInstruction(insn, 16, 3) << 4; |
| 26599 | tmp |= fieldFromInstruction(insn, 28, 1) << 7; |
| 26600 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26601 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26602 | return MCDisassembler::Fail; |
| 26603 | return S; |
| 26604 | case 229: |
| 26605 | tmp = 0x0; |
| 26606 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26607 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26608 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26609 | tmp = 0x0; |
| 26610 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26611 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26612 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26613 | tmp = fieldFromInstruction(insn, 16, 3); |
| 26614 | if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26615 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26616 | return MCDisassembler::Fail; |
| 26617 | return S; |
| 26618 | case 230: |
| 26619 | tmp = 0x0; |
| 26620 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26621 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26622 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26623 | tmp = 0x0; |
| 26624 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26625 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26626 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26627 | tmp = 0x0; |
| 26628 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26629 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26630 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26631 | tmp = fieldFromInstruction(insn, 16, 3); |
| 26632 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26633 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26634 | return MCDisassembler::Fail; |
| 26635 | return S; |
| 26636 | case 231: |
| 26637 | tmp = 0x0; |
| 26638 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26639 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26640 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26641 | tmp = 0x0; |
| 26642 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26643 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26644 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26645 | tmp = fieldFromInstruction(insn, 16, 4); |
| 26646 | if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26647 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26648 | return MCDisassembler::Fail; |
| 26649 | return S; |
| 26650 | case 232: |
| 26651 | tmp = 0x0; |
| 26652 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26653 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26654 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26655 | tmp = 0x0; |
| 26656 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26657 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26658 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26659 | tmp = 0x0; |
| 26660 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26661 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26662 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26663 | tmp = fieldFromInstruction(insn, 16, 4); |
| 26664 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26665 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26666 | return MCDisassembler::Fail; |
| 26667 | return S; |
| 26668 | case 233: |
| 26669 | tmp = 0x0; |
| 26670 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26671 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26672 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26673 | tmp = 0x0; |
| 26674 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26675 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26676 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26677 | tmp = fieldFromInstruction(insn, 16, 5); |
| 26678 | if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26679 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26680 | return MCDisassembler::Fail; |
| 26681 | return S; |
| 26682 | case 234: |
| 26683 | tmp = 0x0; |
| 26684 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26685 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26686 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26687 | tmp = 0x0; |
| 26688 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26689 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26690 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26691 | tmp = 0x0; |
| 26692 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26693 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26694 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26695 | tmp = fieldFromInstruction(insn, 16, 5); |
| 26696 | if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26697 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26698 | return MCDisassembler::Fail; |
| 26699 | return S; |
| 26700 | case 235: |
| 26701 | tmp = 0x0; |
| 26702 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26703 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26704 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26705 | tmp = 0x0; |
| 26706 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26707 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26708 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26709 | tmp = fieldFromInstruction(insn, 16, 5); |
| 26710 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26711 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 26712 | return MCDisassembler::Fail; |
| 26713 | return S; |
| 26714 | case 236: |
| 26715 | tmp = 0x0; |
| 26716 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26717 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26718 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26719 | tmp = 0x0; |
| 26720 | tmp |= fieldFromInstruction(insn, 13, 3); |
| 26721 | tmp |= fieldFromInstruction(insn, 22, 1) << 3; |
| 26722 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26723 | tmp = 0x0; |
| 26724 | tmp |= fieldFromInstruction(insn, 1, 3); |
| 26725 | tmp |= fieldFromInstruction(insn, 5, 1) << 3; |
| 26726 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26727 | tmp = fieldFromInstruction(insn, 16, 5); |
| 26728 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26729 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 26730 | return MCDisassembler::Fail; |
| 26731 | return S; |
| 26732 | case 237: |
| 26733 | if (!Check(S, DecodeMVEVCVTt1fp(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26734 | return S; |
| 26735 | case 238: |
| 26736 | tmp = 0x0; |
| 26737 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26738 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26739 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26740 | tmp = 0x0; |
| 26741 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26742 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26743 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26744 | tmp = 0x0; |
| 26745 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26746 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26747 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26748 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26749 | return MCDisassembler::Fail; |
| 26750 | return S; |
| 26751 | case 239: |
| 26752 | tmp = 0x0; |
| 26753 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26754 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26755 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26756 | tmp = 0x0; |
| 26757 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26758 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26759 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26760 | tmp = 0x0; |
| 26761 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26762 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26763 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26764 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26765 | return MCDisassembler::Fail; |
| 26766 | return S; |
| 26767 | case 240: |
| 26768 | tmp = 0x0; |
| 26769 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26770 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26771 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26772 | tmp = 0x0; |
| 26773 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26774 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26775 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26776 | tmp = 0x0; |
| 26777 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26778 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26779 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26780 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26781 | return MCDisassembler::Fail; |
| 26782 | return S; |
| 26783 | case 241: |
| 26784 | tmp = 0x0; |
| 26785 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26786 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26787 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26788 | tmp = 0x0; |
| 26789 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26790 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26791 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26792 | tmp = 0x0; |
| 26793 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26794 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26795 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26796 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26797 | return MCDisassembler::Fail; |
| 26798 | return S; |
| 26799 | case 242: |
| 26800 | tmp = 0x0; |
| 26801 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26802 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26803 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26804 | tmp = 0x0; |
| 26805 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26806 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26807 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26808 | tmp = 0x0; |
| 26809 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26810 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26811 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26812 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26813 | return MCDisassembler::Fail; |
| 26814 | return S; |
| 26815 | case 243: |
| 26816 | tmp = 0x0; |
| 26817 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26818 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26819 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26820 | tmp = 0x0; |
| 26821 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26822 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26823 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26824 | tmp = 0x0; |
| 26825 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26826 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26827 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26828 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26829 | return MCDisassembler::Fail; |
| 26830 | return S; |
| 26831 | case 244: |
| 26832 | tmp = 0x0; |
| 26833 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26834 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26835 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26836 | tmp = 0x0; |
| 26837 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26838 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26839 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26840 | tmp = 0x0; |
| 26841 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26842 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26843 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26844 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26845 | return MCDisassembler::Fail; |
| 26846 | return S; |
| 26847 | case 245: |
| 26848 | tmp = 0x0; |
| 26849 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26850 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26851 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26852 | tmp = 0x0; |
| 26853 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26854 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26855 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26856 | tmp = 0x0; |
| 26857 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26858 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26859 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26860 | tmp = 0x0; |
| 26861 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26862 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26863 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26864 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26865 | return MCDisassembler::Fail; |
| 26866 | return S; |
| 26867 | case 246: |
| 26868 | tmp = 0x0; |
| 26869 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26870 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26871 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26872 | tmp = 0x0; |
| 26873 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26874 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26875 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26876 | tmp = 0x0; |
| 26877 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26878 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26879 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26880 | tmp = 0x0; |
| 26881 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26882 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26883 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26884 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26885 | return MCDisassembler::Fail; |
| 26886 | return S; |
| 26887 | case 247: |
| 26888 | tmp = 0x0; |
| 26889 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26890 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26891 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26892 | tmp = 0x0; |
| 26893 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26894 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26895 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26896 | tmp = 0x0; |
| 26897 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26898 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26899 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26900 | tmp = 0x0; |
| 26901 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 26902 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 26903 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26904 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26905 | return MCDisassembler::Fail; |
| 26906 | return S; |
| 26907 | case 248: |
| 26908 | tmp = 0x0; |
| 26909 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26910 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26911 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26912 | tmp = 0x0; |
| 26913 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26914 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26915 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26916 | tmp = 0x0; |
| 26917 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26918 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26919 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26920 | tmp = fieldFromInstruction(insn, 0, 3); |
| 26921 | if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26922 | tmp = 0x0; |
| 26923 | tmp |= fieldFromInstruction(insn, 3, 1); |
| 26924 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 26925 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26926 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26927 | return MCDisassembler::Fail; |
| 26928 | return S; |
| 26929 | case 249: |
| 26930 | tmp = 0x0; |
| 26931 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26932 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26933 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26934 | tmp = 0x0; |
| 26935 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26936 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26937 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26938 | tmp = 0x0; |
| 26939 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26940 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26941 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26942 | tmp = fieldFromInstruction(insn, 0, 3); |
| 26943 | if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26944 | tmp = 0x0; |
| 26945 | tmp |= fieldFromInstruction(insn, 3, 1); |
| 26946 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 26947 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26948 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26949 | return MCDisassembler::Fail; |
| 26950 | return S; |
| 26951 | case 250: |
| 26952 | tmp = 0x0; |
| 26953 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26954 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26955 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26956 | tmp = 0x0; |
| 26957 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26958 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26959 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26960 | tmp = 0x0; |
| 26961 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26962 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26963 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26964 | tmp = fieldFromInstruction(insn, 0, 3); |
| 26965 | if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26966 | tmp = 0x0; |
| 26967 | tmp |= fieldFromInstruction(insn, 3, 1); |
| 26968 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 26969 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26970 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26971 | return MCDisassembler::Fail; |
| 26972 | return S; |
| 26973 | case 251: |
| 26974 | tmp = 0x0; |
| 26975 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26976 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26977 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26978 | tmp = 0x0; |
| 26979 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26980 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26981 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26982 | tmp = fieldFromInstruction(insn, 0, 3); |
| 26983 | if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26984 | tmp = 0x0; |
| 26985 | tmp |= fieldFromInstruction(insn, 3, 1); |
| 26986 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 26987 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 26988 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 26989 | return MCDisassembler::Fail; |
| 26990 | return S; |
| 26991 | case 252: |
| 26992 | tmp = 0x0; |
| 26993 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 26994 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 26995 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 26996 | tmp = 0x0; |
| 26997 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 26998 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 26999 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27000 | tmp = fieldFromInstruction(insn, 0, 3); |
| 27001 | if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27002 | tmp = 0x0; |
| 27003 | tmp |= fieldFromInstruction(insn, 3, 1); |
| 27004 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 27005 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27006 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27007 | return MCDisassembler::Fail; |
| 27008 | return S; |
| 27009 | case 253: |
| 27010 | tmp = 0x0; |
| 27011 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27012 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27013 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27014 | tmp = 0x0; |
| 27015 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27016 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27017 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27018 | tmp = fieldFromInstruction(insn, 0, 3); |
| 27019 | if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27020 | tmp = 0x0; |
| 27021 | tmp |= fieldFromInstruction(insn, 3, 1); |
| 27022 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 27023 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27024 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27025 | return MCDisassembler::Fail; |
| 27026 | return S; |
| 27027 | case 254: |
| 27028 | tmp = 0x0; |
| 27029 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27030 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27031 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27032 | tmp = 0x0; |
| 27033 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27034 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27035 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27036 | tmp = 0x0; |
| 27037 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27038 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27039 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27040 | tmp = fieldFromInstruction(insn, 0, 4); |
| 27041 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27042 | tmp = fieldFromInstruction(insn, 5, 1); |
| 27043 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27044 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27045 | return MCDisassembler::Fail; |
| 27046 | return S; |
| 27047 | case 255: |
| 27048 | tmp = 0x0; |
| 27049 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27050 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27051 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27052 | tmp = 0x0; |
| 27053 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27054 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27055 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27056 | tmp = 0x0; |
| 27057 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27058 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27059 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27060 | tmp = fieldFromInstruction(insn, 0, 4); |
| 27061 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27062 | tmp = fieldFromInstruction(insn, 5, 1); |
| 27063 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27064 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27065 | return MCDisassembler::Fail; |
| 27066 | return S; |
| 27067 | case 256: |
| 27068 | tmp = 0x0; |
| 27069 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27070 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27071 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27072 | tmp = 0x0; |
| 27073 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27074 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27075 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27076 | tmp = 0x0; |
| 27077 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27078 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27079 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27080 | tmp = fieldFromInstruction(insn, 0, 4); |
| 27081 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27082 | tmp = fieldFromInstruction(insn, 5, 1); |
| 27083 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27084 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27085 | return MCDisassembler::Fail; |
| 27086 | return S; |
| 27087 | case 257: |
| 27088 | tmp = 0x0; |
| 27089 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27090 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27091 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27092 | tmp = 0x0; |
| 27093 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27094 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27095 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27096 | tmp = fieldFromInstruction(insn, 0, 4); |
| 27097 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27098 | tmp = fieldFromInstruction(insn, 5, 1); |
| 27099 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27100 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27101 | return MCDisassembler::Fail; |
| 27102 | return S; |
| 27103 | case 258: |
| 27104 | tmp = 0x0; |
| 27105 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27106 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27107 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27108 | tmp = 0x0; |
| 27109 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27110 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27111 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27112 | tmp = fieldFromInstruction(insn, 0, 4); |
| 27113 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27114 | tmp = fieldFromInstruction(insn, 5, 1); |
| 27115 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27116 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27117 | return MCDisassembler::Fail; |
| 27118 | return S; |
| 27119 | case 259: |
| 27120 | tmp = 0x0; |
| 27121 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27122 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27123 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27124 | tmp = 0x0; |
| 27125 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27126 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27127 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27128 | tmp = fieldFromInstruction(insn, 0, 4); |
| 27129 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27130 | tmp = fieldFromInstruction(insn, 5, 1); |
| 27131 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27132 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27133 | return MCDisassembler::Fail; |
| 27134 | return S; |
| 27135 | case 260: |
| 27136 | tmp = 0x0; |
| 27137 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27138 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27139 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27140 | tmp = 0x0; |
| 27141 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27142 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27143 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27144 | tmp = 0x0; |
| 27145 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27146 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27147 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27148 | return S; |
| 27149 | case 261: |
| 27150 | tmp = 0x0; |
| 27151 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27152 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27153 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27154 | tmp = 0x0; |
| 27155 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27156 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27157 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27158 | tmp = 0x0; |
| 27159 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27160 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27161 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27162 | tmp = fieldFromInstruction(insn, 10, 1); |
| 27163 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27164 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27165 | return MCDisassembler::Fail; |
| 27166 | return S; |
| 27167 | case 262: |
| 27168 | tmp = 0x0; |
| 27169 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27170 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27171 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27172 | tmp = 0x0; |
| 27173 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27174 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27175 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27176 | tmp = 0x0; |
| 27177 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27178 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27179 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27180 | tmp = fieldFromInstruction(insn, 9, 2); |
| 27181 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27182 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27183 | return MCDisassembler::Fail; |
| 27184 | return S; |
| 27185 | case 263: |
| 27186 | tmp = 0x0; |
| 27187 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27188 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27189 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27190 | tmp = 0x0; |
| 27191 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27192 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27193 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27194 | tmp = 0x0; |
| 27195 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27196 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27197 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27198 | tmp = fieldFromInstruction(insn, 8, 3); |
| 27199 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27200 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27201 | return MCDisassembler::Fail; |
| 27202 | return S; |
| 27203 | case 264: |
| 27204 | tmp = 0x0; |
| 27205 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27206 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27207 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27208 | tmp = 0x0; |
| 27209 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27210 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27211 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27212 | tmp = 0x0; |
| 27213 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27214 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27215 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27216 | tmp = fieldFromInstruction(insn, 11, 1); |
| 27217 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27218 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27219 | return MCDisassembler::Fail; |
| 27220 | return S; |
| 27221 | case 265: |
| 27222 | tmp = 0x0; |
| 27223 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27224 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27225 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27226 | tmp = 0x0; |
| 27227 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27228 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27229 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27230 | tmp = 0x0; |
| 27231 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27232 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27233 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27234 | tmp = fieldFromInstruction(insn, 10, 2); |
| 27235 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27236 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27237 | return MCDisassembler::Fail; |
| 27238 | return S; |
| 27239 | case 266: |
| 27240 | tmp = 0x0; |
| 27241 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27242 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27243 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27244 | tmp = 0x0; |
| 27245 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27246 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27247 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27248 | tmp = 0x0; |
| 27249 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27250 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27251 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27252 | tmp = fieldFromInstruction(insn, 9, 3); |
| 27253 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27254 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27255 | return MCDisassembler::Fail; |
| 27256 | return S; |
| 27257 | case 267: |
| 27258 | tmp = 0x0; |
| 27259 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27260 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27261 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27262 | tmp = 0x0; |
| 27263 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 27264 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 27265 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27266 | tmp = 0x0; |
| 27267 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27268 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27269 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27270 | tmp = fieldFromInstruction(insn, 8, 4); |
| 27271 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27272 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27273 | return MCDisassembler::Fail; |
| 27274 | return S; |
| 27275 | case 268: |
| 27276 | tmp = 0x0; |
| 27277 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27278 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27279 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27280 | tmp = 0x0; |
| 27281 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27282 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27283 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27284 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27285 | return MCDisassembler::Fail; |
| 27286 | return S; |
| 27287 | case 269: |
| 27288 | tmp = 0x0; |
| 27289 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27290 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27291 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27292 | tmp = 0x0; |
| 27293 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27294 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27295 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27296 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27297 | return MCDisassembler::Fail; |
| 27298 | return S; |
| 27299 | case 270: |
| 27300 | tmp = 0x0; |
| 27301 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27302 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27303 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27304 | tmp = 0x0; |
| 27305 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27306 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27307 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27308 | tmp = 0x0; |
| 27309 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27310 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27311 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27312 | tmp = 0x0; |
| 27313 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27314 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27315 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27316 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27317 | return MCDisassembler::Fail; |
| 27318 | return S; |
| 27319 | case 271: |
| 27320 | tmp = 0x0; |
| 27321 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27322 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27323 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27324 | tmp = 0x0; |
| 27325 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27326 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27327 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27328 | tmp = 0x0; |
| 27329 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27330 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27331 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27332 | tmp = 0x0; |
| 27333 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27334 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27335 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27336 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27337 | return MCDisassembler::Fail; |
| 27338 | return S; |
| 27339 | case 272: |
| 27340 | tmp = 0x0; |
| 27341 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27342 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27343 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27344 | tmp = 0x0; |
| 27345 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27346 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27347 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27348 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27349 | return MCDisassembler::Fail; |
| 27350 | return S; |
| 27351 | case 273: |
| 27352 | if (!Check(S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27353 | return S; |
| 27354 | case 274: |
| 27355 | tmp = 0x0; |
| 27356 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27357 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27358 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27359 | tmp = 0x0; |
| 27360 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27361 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27362 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27363 | tmp = 0x0; |
| 27364 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27365 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27366 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27367 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27368 | return MCDisassembler::Fail; |
| 27369 | return S; |
| 27370 | case 275: |
| 27371 | tmp = 0x0; |
| 27372 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27373 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27374 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27375 | tmp = 0x0; |
| 27376 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27377 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27378 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27379 | tmp = 0x0; |
| 27380 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27381 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27382 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27383 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27384 | return MCDisassembler::Fail; |
| 27385 | return S; |
| 27386 | case 276: |
| 27387 | tmp = 0x0; |
| 27388 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27389 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27390 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27391 | tmp = 0x0; |
| 27392 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27393 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27394 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27395 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27396 | return MCDisassembler::Fail; |
| 27397 | return S; |
| 27398 | case 277: |
| 27399 | if (!Check(S, DecodeTBLInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27400 | return S; |
| 27401 | case 278: |
| 27402 | tmp = 0x0; |
| 27403 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27404 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27405 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27406 | tmp = 0x0; |
| 27407 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27408 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27409 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27410 | tmp = fieldFromInstruction(insn, 19, 1); |
| 27411 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27412 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27413 | return MCDisassembler::Fail; |
| 27414 | return S; |
| 27415 | case 279: |
| 27416 | tmp = 0x0; |
| 27417 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27418 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27419 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27420 | tmp = 0x0; |
| 27421 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27422 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27423 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27424 | tmp = fieldFromInstruction(insn, 18, 2); |
| 27425 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27426 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27427 | return MCDisassembler::Fail; |
| 27428 | return S; |
| 27429 | case 280: |
| 27430 | tmp = 0x0; |
| 27431 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27432 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27433 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27434 | tmp = 0x0; |
| 27435 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27436 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27437 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27438 | tmp = fieldFromInstruction(insn, 17, 3); |
| 27439 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27440 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27441 | return MCDisassembler::Fail; |
| 27442 | return S; |
| 27443 | case 281: |
| 27444 | tmp = 0x0; |
| 27445 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27446 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27447 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27448 | tmp = 0x0; |
| 27449 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27450 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27451 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27452 | tmp = fieldFromInstruction(insn, 19, 1); |
| 27453 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27454 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27455 | return MCDisassembler::Fail; |
| 27456 | return S; |
| 27457 | case 282: |
| 27458 | tmp = 0x0; |
| 27459 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27460 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27461 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27462 | tmp = 0x0; |
| 27463 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27464 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27465 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27466 | tmp = fieldFromInstruction(insn, 18, 2); |
| 27467 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27468 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27469 | return MCDisassembler::Fail; |
| 27470 | return S; |
| 27471 | case 283: |
| 27472 | tmp = 0x0; |
| 27473 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27474 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27475 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27476 | tmp = 0x0; |
| 27477 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27478 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27479 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27480 | tmp = fieldFromInstruction(insn, 17, 3); |
| 27481 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27482 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27483 | return MCDisassembler::Fail; |
| 27484 | return S; |
| 27485 | case 284: |
| 27486 | tmp = 0x0; |
| 27487 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27488 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27489 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27490 | tmp = 0x0; |
| 27491 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27492 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27493 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27494 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27495 | if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27496 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27497 | return MCDisassembler::Fail; |
| 27498 | return S; |
| 27499 | case 285: |
| 27500 | tmp = 0x0; |
| 27501 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27502 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27503 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27504 | tmp = 0x0; |
| 27505 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27506 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27507 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27508 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27509 | if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27510 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27511 | return MCDisassembler::Fail; |
| 27512 | return S; |
| 27513 | case 286: |
| 27514 | tmp = 0x0; |
| 27515 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27516 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27517 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27518 | tmp = 0x0; |
| 27519 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27520 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27521 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27522 | tmp = fieldFromInstruction(insn, 16, 5); |
| 27523 | if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27524 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27525 | return MCDisassembler::Fail; |
| 27526 | return S; |
| 27527 | case 287: |
| 27528 | tmp = 0x0; |
| 27529 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27530 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27531 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27532 | tmp = 0x0; |
| 27533 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27534 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27535 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27536 | tmp = 0x0; |
| 27537 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27538 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27539 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27540 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27541 | if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27542 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27543 | return MCDisassembler::Fail; |
| 27544 | return S; |
| 27545 | case 288: |
| 27546 | tmp = 0x0; |
| 27547 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27548 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27549 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27550 | tmp = 0x0; |
| 27551 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27552 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27553 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27554 | tmp = 0x0; |
| 27555 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27556 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27557 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27558 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27559 | if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27560 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27561 | return MCDisassembler::Fail; |
| 27562 | return S; |
| 27563 | case 289: |
| 27564 | tmp = 0x0; |
| 27565 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27566 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27567 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27568 | tmp = 0x0; |
| 27569 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27570 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27571 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27572 | tmp = 0x0; |
| 27573 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27574 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27575 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27576 | tmp = fieldFromInstruction(insn, 16, 5); |
| 27577 | if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27578 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27579 | return MCDisassembler::Fail; |
| 27580 | return S; |
| 27581 | case 290: |
| 27582 | tmp = 0x0; |
| 27583 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27584 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27585 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27586 | tmp = 0x0; |
| 27587 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27588 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27589 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27590 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27591 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27592 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27593 | return MCDisassembler::Fail; |
| 27594 | return S; |
| 27595 | case 291: |
| 27596 | tmp = 0x0; |
| 27597 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27598 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27599 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27600 | tmp = 0x0; |
| 27601 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27602 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27603 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27604 | tmp = 0x0; |
| 27605 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27606 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27607 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27608 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27609 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27610 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27611 | return MCDisassembler::Fail; |
| 27612 | return S; |
| 27613 | case 292: |
| 27614 | tmp = 0x0; |
| 27615 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27616 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27617 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27618 | tmp = 0x0; |
| 27619 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27620 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27621 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27622 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27623 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27624 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27625 | return MCDisassembler::Fail; |
| 27626 | return S; |
| 27627 | case 293: |
| 27628 | tmp = 0x0; |
| 27629 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27630 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27631 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27632 | tmp = 0x0; |
| 27633 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27634 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27635 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27636 | tmp = 0x0; |
| 27637 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27638 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27639 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27640 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27641 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27642 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27643 | return MCDisassembler::Fail; |
| 27644 | return S; |
| 27645 | case 294: |
| 27646 | tmp = 0x0; |
| 27647 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27648 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27649 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27650 | tmp = 0x0; |
| 27651 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27652 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27653 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27654 | tmp = fieldFromInstruction(insn, 16, 5); |
| 27655 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27656 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27657 | return MCDisassembler::Fail; |
| 27658 | return S; |
| 27659 | case 295: |
| 27660 | tmp = 0x0; |
| 27661 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27662 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27663 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27664 | tmp = 0x0; |
| 27665 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27666 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27667 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27668 | tmp = 0x0; |
| 27669 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27670 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27671 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27672 | tmp = fieldFromInstruction(insn, 16, 5); |
| 27673 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27674 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27675 | return MCDisassembler::Fail; |
| 27676 | return S; |
| 27677 | case 296: |
| 27678 | tmp = 0x0; |
| 27679 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27680 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27681 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27682 | tmp = 0x0; |
| 27683 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27684 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27685 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27686 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27687 | if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27688 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27689 | return MCDisassembler::Fail; |
| 27690 | return S; |
| 27691 | case 297: |
| 27692 | tmp = 0x0; |
| 27693 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27694 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27695 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27696 | tmp = 0x0; |
| 27697 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27698 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27699 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27700 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27701 | if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27702 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27703 | return MCDisassembler::Fail; |
| 27704 | return S; |
| 27705 | case 298: |
| 27706 | tmp = 0x0; |
| 27707 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27708 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27709 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27710 | tmp = 0x0; |
| 27711 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27712 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27713 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27714 | tmp = fieldFromInstruction(insn, 16, 5); |
| 27715 | if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27716 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27717 | return MCDisassembler::Fail; |
| 27718 | return S; |
| 27719 | case 299: |
| 27720 | tmp = 0x0; |
| 27721 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27722 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27723 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27724 | tmp = 0x0; |
| 27725 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27726 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27727 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27728 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27729 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27730 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27731 | return MCDisassembler::Fail; |
| 27732 | return S; |
| 27733 | case 300: |
| 27734 | tmp = 0x0; |
| 27735 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27736 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27737 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27738 | tmp = 0x0; |
| 27739 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27740 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27741 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27742 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27743 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27744 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27745 | return MCDisassembler::Fail; |
| 27746 | return S; |
| 27747 | case 301: |
| 27748 | tmp = 0x0; |
| 27749 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27750 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27751 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27752 | tmp = 0x0; |
| 27753 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27754 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27755 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27756 | tmp = fieldFromInstruction(insn, 16, 5); |
| 27757 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27758 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27759 | return MCDisassembler::Fail; |
| 27760 | return S; |
| 27761 | case 302: |
| 27762 | if (!Check(S, DecodeVCVTD(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27763 | return S; |
| 27764 | case 303: |
| 27765 | if (!Check(S, DecodeVMOVModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27766 | return S; |
| 27767 | case 304: |
| 27768 | tmp = 0x0; |
| 27769 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27770 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27771 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27772 | tmp = 0x0; |
| 27773 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27774 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27775 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27776 | tmp = fieldFromInstruction(insn, 16, 6); |
| 27777 | if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27778 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27779 | return MCDisassembler::Fail; |
| 27780 | return S; |
| 27781 | case 305: |
| 27782 | tmp = 0x0; |
| 27783 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27784 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27785 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27786 | tmp = 0x0; |
| 27787 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27788 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27789 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27790 | tmp = 0x0; |
| 27791 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27792 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27793 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27794 | tmp = fieldFromInstruction(insn, 16, 6); |
| 27795 | if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27796 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27797 | return MCDisassembler::Fail; |
| 27798 | return S; |
| 27799 | case 306: |
| 27800 | tmp = 0x0; |
| 27801 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27802 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27803 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27804 | tmp = 0x0; |
| 27805 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27806 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27807 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27808 | tmp = fieldFromInstruction(insn, 16, 6); |
| 27809 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27810 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27811 | return MCDisassembler::Fail; |
| 27812 | return S; |
| 27813 | case 307: |
| 27814 | tmp = 0x0; |
| 27815 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27816 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27817 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27818 | tmp = 0x0; |
| 27819 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27820 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27821 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27822 | tmp = 0x0; |
| 27823 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27824 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27825 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27826 | tmp = fieldFromInstruction(insn, 16, 6); |
| 27827 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27828 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27829 | return MCDisassembler::Fail; |
| 27830 | return S; |
| 27831 | case 308: |
| 27832 | tmp = 0x0; |
| 27833 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27834 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27835 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27836 | tmp = 0x0; |
| 27837 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27838 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27839 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27840 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27841 | if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27842 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27843 | return MCDisassembler::Fail; |
| 27844 | return S; |
| 27845 | case 309: |
| 27846 | tmp = 0x0; |
| 27847 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27848 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27849 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27850 | tmp = 0x0; |
| 27851 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27852 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27853 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27854 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27855 | if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27856 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27857 | return MCDisassembler::Fail; |
| 27858 | return S; |
| 27859 | case 310: |
| 27860 | tmp = 0x0; |
| 27861 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27862 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27863 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27864 | tmp = 0x0; |
| 27865 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27866 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27867 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27868 | tmp = fieldFromInstruction(insn, 16, 5); |
| 27869 | if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27870 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27871 | return MCDisassembler::Fail; |
| 27872 | return S; |
| 27873 | case 311: |
| 27874 | tmp = 0x0; |
| 27875 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27876 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27877 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27878 | tmp = 0x0; |
| 27879 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27880 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27881 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27882 | tmp = 0x0; |
| 27883 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27884 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27885 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27886 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27887 | if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27888 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27889 | return MCDisassembler::Fail; |
| 27890 | return S; |
| 27891 | case 312: |
| 27892 | tmp = 0x0; |
| 27893 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27894 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27895 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27896 | tmp = 0x0; |
| 27897 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27898 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27899 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27900 | tmp = 0x0; |
| 27901 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27902 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27903 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27904 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27905 | if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27906 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27907 | return MCDisassembler::Fail; |
| 27908 | return S; |
| 27909 | case 313: |
| 27910 | tmp = 0x0; |
| 27911 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27912 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27913 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27914 | tmp = 0x0; |
| 27915 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27916 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27917 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27918 | tmp = 0x0; |
| 27919 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27920 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27921 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27922 | tmp = fieldFromInstruction(insn, 16, 5); |
| 27923 | if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27924 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27925 | return MCDisassembler::Fail; |
| 27926 | return S; |
| 27927 | case 314: |
| 27928 | tmp = 0x0; |
| 27929 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27930 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27931 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27932 | tmp = 0x0; |
| 27933 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27934 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27935 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27936 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27937 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27938 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27939 | return MCDisassembler::Fail; |
| 27940 | return S; |
| 27941 | case 315: |
| 27942 | tmp = 0x0; |
| 27943 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27944 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27945 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27946 | tmp = 0x0; |
| 27947 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27948 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27949 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27950 | tmp = 0x0; |
| 27951 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27952 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27953 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27954 | tmp = fieldFromInstruction(insn, 16, 3); |
| 27955 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27956 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27957 | return MCDisassembler::Fail; |
| 27958 | return S; |
| 27959 | case 316: |
| 27960 | tmp = 0x0; |
| 27961 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27962 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27963 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27964 | tmp = 0x0; |
| 27965 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27966 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27967 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27968 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27969 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27970 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27971 | return MCDisassembler::Fail; |
| 27972 | return S; |
| 27973 | case 317: |
| 27974 | tmp = 0x0; |
| 27975 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27976 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27977 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27978 | tmp = 0x0; |
| 27979 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27980 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27981 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27982 | tmp = 0x0; |
| 27983 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27984 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27985 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27986 | tmp = fieldFromInstruction(insn, 16, 4); |
| 27987 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 27988 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 27989 | return MCDisassembler::Fail; |
| 27990 | return S; |
| 27991 | case 318: |
| 27992 | tmp = 0x0; |
| 27993 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 27994 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 27995 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 27996 | tmp = 0x0; |
| 27997 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 27998 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 27999 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28000 | tmp = fieldFromInstruction(insn, 16, 5); |
| 28001 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28002 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28003 | return MCDisassembler::Fail; |
| 28004 | return S; |
| 28005 | case 319: |
| 28006 | tmp = 0x0; |
| 28007 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 28008 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 28009 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28010 | tmp = 0x0; |
| 28011 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 28012 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 28013 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28014 | tmp = 0x0; |
| 28015 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28016 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 28017 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28018 | tmp = fieldFromInstruction(insn, 16, 5); |
| 28019 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28020 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28021 | return MCDisassembler::Fail; |
| 28022 | return S; |
| 28023 | case 320: |
| 28024 | if (!Check(S, DecodeVCVTQ(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28025 | return S; |
| 28026 | case 321: |
| 28027 | tmp = 0x0; |
| 28028 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 28029 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 28030 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28031 | tmp = 0x0; |
| 28032 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28033 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 28034 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28035 | tmp = fieldFromInstruction(insn, 16, 6); |
| 28036 | if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28037 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28038 | return MCDisassembler::Fail; |
| 28039 | return S; |
| 28040 | case 322: |
| 28041 | tmp = 0x0; |
| 28042 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 28043 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 28044 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28045 | tmp = 0x0; |
| 28046 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 28047 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 28048 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28049 | tmp = 0x0; |
| 28050 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28051 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 28052 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28053 | tmp = fieldFromInstruction(insn, 16, 6); |
| 28054 | if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28055 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28056 | return MCDisassembler::Fail; |
| 28057 | return S; |
| 28058 | case 323: |
| 28059 | tmp = 0x0; |
| 28060 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 28061 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 28062 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28063 | tmp = 0x0; |
| 28064 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28065 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 28066 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28067 | tmp = fieldFromInstruction(insn, 16, 6); |
| 28068 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28069 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28070 | return MCDisassembler::Fail; |
| 28071 | return S; |
| 28072 | case 324: |
| 28073 | tmp = 0x0; |
| 28074 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 28075 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 28076 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28077 | tmp = 0x0; |
| 28078 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 28079 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 28080 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28081 | tmp = 0x0; |
| 28082 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28083 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 28084 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28085 | tmp = fieldFromInstruction(insn, 16, 6); |
| 28086 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28087 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28088 | return MCDisassembler::Fail; |
| 28089 | return S; |
| 28090 | case 325: |
| 28091 | tmp = 0x0; |
| 28092 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28093 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28094 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28095 | tmp = 0x0; |
| 28096 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28097 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28098 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28099 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28100 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28101 | tmp = fieldFromInstruction(insn, 21, 1); |
| 28102 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28103 | tmp = fieldFromInstruction(insn, 28, 4); |
| 28104 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28105 | return S; |
| 28106 | case 326: |
| 28107 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28108 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28109 | tmp = 0x0; |
| 28110 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28111 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28112 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28113 | tmp = fieldFromInstruction(insn, 21, 1); |
| 28114 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28115 | tmp = fieldFromInstruction(insn, 28, 4); |
| 28116 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28117 | return S; |
| 28118 | case 327: |
| 28119 | tmp = 0x0; |
| 28120 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28121 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28122 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28123 | tmp = 0x0; |
| 28124 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28125 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28126 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28127 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28128 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28129 | tmp = 0x0; |
| 28130 | tmp |= fieldFromInstruction(insn, 6, 1); |
| 28131 | tmp |= fieldFromInstruction(insn, 21, 1) << 1; |
| 28132 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28133 | tmp = fieldFromInstruction(insn, 28, 4); |
| 28134 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28135 | return S; |
| 28136 | case 328: |
| 28137 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28138 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28139 | tmp = 0x0; |
| 28140 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28141 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28142 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28143 | tmp = 0x0; |
| 28144 | tmp |= fieldFromInstruction(insn, 6, 1); |
| 28145 | tmp |= fieldFromInstruction(insn, 21, 1) << 1; |
| 28146 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28147 | tmp = fieldFromInstruction(insn, 28, 4); |
| 28148 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28149 | return S; |
| 28150 | case 329: |
| 28151 | tmp = 0x0; |
| 28152 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28153 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28154 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28155 | tmp = 0x0; |
| 28156 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28157 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28158 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28159 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28160 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28161 | tmp = 0x0; |
| 28162 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 28163 | tmp |= fieldFromInstruction(insn, 21, 1) << 2; |
| 28164 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28165 | tmp = fieldFromInstruction(insn, 28, 4); |
| 28166 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28167 | return S; |
| 28168 | case 330: |
| 28169 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28170 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28171 | tmp = 0x0; |
| 28172 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28173 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28174 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28175 | tmp = 0x0; |
| 28176 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 28177 | tmp |= fieldFromInstruction(insn, 21, 1) << 2; |
| 28178 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28179 | tmp = fieldFromInstruction(insn, 28, 4); |
| 28180 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28181 | return S; |
| 28182 | case 331: |
| 28183 | tmp = 0x0; |
| 28184 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28185 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28186 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28187 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28188 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28189 | tmp = fieldFromInstruction(insn, 28, 4); |
| 28190 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28191 | return S; |
| 28192 | case 332: |
| 28193 | tmp = 0x0; |
| 28194 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 28195 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28196 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28197 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28198 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28199 | tmp = fieldFromInstruction(insn, 28, 4); |
| 28200 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28201 | return S; |
| 28202 | case 333: |
| 28203 | if (!Check(S, DecodeVLDST4Instruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28204 | return S; |
| 28205 | case 334: |
| 28206 | if (!Check(S, DecodeVST1LN(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28207 | return S; |
| 28208 | case 335: |
| 28209 | if (!Check(S, DecodeVLD1LN(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28210 | return S; |
| 28211 | case 336: |
| 28212 | if (!Check(S, DecodeVST2LN(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28213 | return S; |
| 28214 | case 337: |
| 28215 | if (!Check(S, DecodeVLD2LN(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28216 | return S; |
| 28217 | case 338: |
| 28218 | if (!Check(S, DecodeVLDST1Instruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28219 | return S; |
| 28220 | case 339: |
| 28221 | if (!Check(S, DecodeVST3LN(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28222 | return S; |
| 28223 | case 340: |
| 28224 | if (!Check(S, DecodeVLD3LN(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28225 | return S; |
| 28226 | case 341: |
| 28227 | if (!Check(S, DecodeVLDST2Instruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28228 | return S; |
| 28229 | case 342: |
| 28230 | if (!Check(S, DecodeVST4LN(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28231 | return S; |
| 28232 | case 343: |
| 28233 | if (!Check(S, DecodeVLD4LN(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28234 | return S; |
| 28235 | case 344: |
| 28236 | if (!Check(S, DecodeVLDST3Instruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28237 | return S; |
| 28238 | case 345: |
| 28239 | if (!Check(S, DecodeVLD1DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28240 | return S; |
| 28241 | case 346: |
| 28242 | if (!Check(S, DecodeVLD2DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28243 | return S; |
| 28244 | case 347: |
| 28245 | if (!Check(S, DecodeVLD3DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28246 | return S; |
| 28247 | case 348: |
| 28248 | if (!Check(S, DecodeVLD4DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28249 | return S; |
| 28250 | case 349: |
| 28251 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28252 | return MCDisassembler::Fail; |
| 28253 | tmp = 0x0; |
| 28254 | tmp |= fieldFromInstruction(insn, 1, 10) << 1; |
| 28255 | tmp |= fieldFromInstruction(insn, 11, 1) << 21; |
| 28256 | tmp |= fieldFromInstruction(insn, 13, 1) << 22; |
| 28257 | tmp |= fieldFromInstruction(insn, 16, 10) << 11; |
| 28258 | tmp |= fieldFromInstruction(insn, 26, 1) << 23; |
| 28259 | if (!Check(S, DecodeThumbBLXOffset(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28260 | return S; |
| 28261 | case 350: |
| 28262 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28263 | return MCDisassembler::Fail; |
| 28264 | tmp = 0x0; |
| 28265 | tmp |= fieldFromInstruction(insn, 0, 11); |
| 28266 | tmp |= fieldFromInstruction(insn, 11, 1) << 21; |
| 28267 | tmp |= fieldFromInstruction(insn, 13, 1) << 22; |
| 28268 | tmp |= fieldFromInstruction(insn, 16, 10) << 11; |
| 28269 | tmp |= fieldFromInstruction(insn, 26, 1) << 23; |
| 28270 | if (!Check(S, DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28271 | return S; |
| 28272 | case 351: |
| 28273 | tmp = fieldFromInstruction(insn, 0, 5); |
| 28274 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28275 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28276 | return MCDisassembler::Fail; |
| 28277 | return S; |
| 28278 | case 352: |
| 28279 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28280 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28281 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28282 | return MCDisassembler::Fail; |
| 28283 | return S; |
| 28284 | case 353: |
| 28285 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28286 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28287 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28288 | return MCDisassembler::Fail; |
| 28289 | tmp = 0x0; |
| 28290 | tmp |= fieldFromInstruction(insn, 0, 13); |
| 28291 | tmp |= fieldFromInstruction(insn, 14, 1) << 14; |
| 28292 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28293 | return S; |
| 28294 | case 354: |
| 28295 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28296 | return MCDisassembler::Fail; |
| 28297 | tmp = 0x0; |
| 28298 | tmp |= fieldFromInstruction(insn, 0, 13); |
| 28299 | tmp |= fieldFromInstruction(insn, 14, 2) << 14; |
| 28300 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28301 | return S; |
| 28302 | case 355: |
| 28303 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28304 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28305 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28306 | return MCDisassembler::Fail; |
| 28307 | tmp = fieldFromInstruction(insn, 0, 16); |
| 28308 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28309 | return S; |
| 28310 | case 356: |
| 28311 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28312 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28313 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28314 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28315 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28316 | return MCDisassembler::Fail; |
| 28317 | return S; |
| 28318 | case 357: |
| 28319 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28320 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28321 | tmp = 0x0; |
| 28322 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28323 | tmp |= fieldFromInstruction(insn, 4, 4) << 5; |
| 28324 | tmp |= fieldFromInstruction(insn, 12, 3) << 9; |
| 28325 | if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28326 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28327 | return MCDisassembler::Fail; |
| 28328 | return S; |
| 28329 | case 358: |
| 28330 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28331 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28332 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28333 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28334 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28335 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28336 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28337 | return MCDisassembler::Fail; |
| 28338 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28339 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28340 | return S; |
| 28341 | case 359: |
| 28342 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28343 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28344 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28345 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28346 | tmp = 0x0; |
| 28347 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28348 | tmp |= fieldFromInstruction(insn, 4, 4) << 5; |
| 28349 | tmp |= fieldFromInstruction(insn, 12, 3) << 9; |
| 28350 | if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28351 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28352 | return MCDisassembler::Fail; |
| 28353 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28354 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28355 | return S; |
| 28356 | case 360: |
| 28357 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28358 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28359 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28360 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28361 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28362 | return MCDisassembler::Fail; |
| 28363 | return S; |
| 28364 | case 361: |
| 28365 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28366 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28367 | tmp = 0x0; |
| 28368 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28369 | tmp |= fieldFromInstruction(insn, 4, 4) << 5; |
| 28370 | tmp |= fieldFromInstruction(insn, 12, 3) << 9; |
| 28371 | if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28372 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28373 | return MCDisassembler::Fail; |
| 28374 | return S; |
| 28375 | case 362: |
| 28376 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28377 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28378 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28379 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28380 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28381 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28382 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28383 | return MCDisassembler::Fail; |
| 28384 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28385 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28386 | return S; |
| 28387 | case 363: |
| 28388 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28389 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28390 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28391 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28392 | tmp = 0x0; |
| 28393 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28394 | tmp |= fieldFromInstruction(insn, 4, 4) << 5; |
| 28395 | tmp |= fieldFromInstruction(insn, 12, 3) << 9; |
| 28396 | if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28397 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28398 | return MCDisassembler::Fail; |
| 28399 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28400 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28401 | return S; |
| 28402 | case 364: |
| 28403 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28404 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28405 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28406 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28407 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28408 | return MCDisassembler::Fail; |
| 28409 | tmp = 0x0; |
| 28410 | tmp |= fieldFromInstruction(insn, 0, 13); |
| 28411 | tmp |= fieldFromInstruction(insn, 14, 1) << 14; |
| 28412 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28413 | return S; |
| 28414 | case 365: |
| 28415 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28416 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28417 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28418 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28419 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28420 | return MCDisassembler::Fail; |
| 28421 | tmp = fieldFromInstruction(insn, 0, 16); |
| 28422 | if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28423 | return S; |
| 28424 | case 366: |
| 28425 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28426 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28427 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28428 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28429 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28430 | return MCDisassembler::Fail; |
| 28431 | return S; |
| 28432 | case 367: |
| 28433 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28434 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28435 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28436 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28437 | tmp = 0x0; |
| 28438 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28439 | tmp |= fieldFromInstruction(insn, 16, 4) << 8; |
| 28440 | if (!Check(S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28441 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28442 | return MCDisassembler::Fail; |
| 28443 | return S; |
| 28444 | case 368: |
| 28445 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28446 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28447 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28448 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28449 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28450 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28451 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28452 | return MCDisassembler::Fail; |
| 28453 | return S; |
| 28454 | case 369: |
| 28455 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28456 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28457 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28458 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28459 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28460 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28461 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28462 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28463 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28464 | return MCDisassembler::Fail; |
| 28465 | return S; |
| 28466 | case 370: |
| 28467 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28468 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28469 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28470 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28471 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28472 | return MCDisassembler::Fail; |
| 28473 | return S; |
| 28474 | case 371: |
| 28475 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28476 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28477 | tmp = 0x0; |
| 28478 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28479 | tmp |= fieldFromInstruction(insn, 16, 4) << 8; |
| 28480 | if (!Check(S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28481 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28482 | return MCDisassembler::Fail; |
| 28483 | return S; |
| 28484 | case 372: |
| 28485 | if (!Check(S, DecodeThumbTableBranch(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28486 | return S; |
| 28487 | case 373: |
| 28488 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28489 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28490 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28491 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28492 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28493 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28494 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28495 | return MCDisassembler::Fail; |
| 28496 | return S; |
| 28497 | case 374: |
| 28498 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28499 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28500 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28501 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28502 | tmp = 0x0; |
| 28503 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28504 | tmp |= fieldFromInstruction(insn, 16, 4) << 9; |
| 28505 | tmp |= fieldFromInstruction(insn, 23, 1) << 8; |
| 28506 | if (!Check(S, DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28507 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28508 | return MCDisassembler::Fail; |
| 28509 | return S; |
| 28510 | case 375: |
| 28511 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28512 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28513 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28514 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28515 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28516 | return MCDisassembler::Fail; |
| 28517 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28518 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28519 | return S; |
| 28520 | case 376: |
| 28521 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28522 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28523 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28524 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28525 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28526 | return MCDisassembler::Fail; |
| 28527 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28528 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28529 | return S; |
| 28530 | case 377: |
| 28531 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28532 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28533 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28534 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28535 | tmp = 0x0; |
| 28536 | tmp |= fieldFromInstruction(insn, 6, 2); |
| 28537 | tmp |= fieldFromInstruction(insn, 12, 3) << 2; |
| 28538 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28539 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28540 | return MCDisassembler::Fail; |
| 28541 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28542 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28543 | return S; |
| 28544 | case 378: |
| 28545 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28546 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28547 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28548 | if (!Check(S, DecodeGPRwithZRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28549 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28550 | if (!Check(S, DecodeGPRwithZRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28551 | tmp = fieldFromInstruction(insn, 4, 4); |
| 28552 | if (!Check(S, DecodePredNoALOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28553 | return S; |
| 28554 | case 379: |
| 28555 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28556 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28557 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28558 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28559 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28560 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28561 | tmp = 0x0; |
| 28562 | tmp |= fieldFromInstruction(insn, 6, 2); |
| 28563 | tmp |= fieldFromInstruction(insn, 12, 3) << 2; |
| 28564 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28565 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28566 | return MCDisassembler::Fail; |
| 28567 | return S; |
| 28568 | case 380: |
| 28569 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28570 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28571 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28572 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28573 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28574 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28575 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28576 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28577 | tmp = 0x0; |
| 28578 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28579 | tmp |= fieldFromInstruction(insn, 23, 1) << 8; |
| 28580 | if (!Check(S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28581 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28582 | return MCDisassembler::Fail; |
| 28583 | return S; |
| 28584 | case 381: |
| 28585 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28586 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28587 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28588 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28589 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28590 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28591 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28592 | if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28593 | tmp = 0x0; |
| 28594 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28595 | tmp |= fieldFromInstruction(insn, 23, 1) << 8; |
| 28596 | if (!Check(S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28597 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28598 | return MCDisassembler::Fail; |
| 28599 | return S; |
| 28600 | case 382: |
| 28601 | if (!Check(S, DecodeT2STRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28602 | return S; |
| 28603 | case 383: |
| 28604 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28605 | return MCDisassembler::Fail; |
| 28606 | return S; |
| 28607 | case 384: |
| 28608 | if (!Check(S, DecodeT2LDRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28609 | return S; |
| 28610 | case 385: |
| 28611 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28612 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28613 | tmp = 0x0; |
| 28614 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 28615 | tmp |= fieldFromInstruction(insn, 4, 4) << 5; |
| 28616 | tmp |= fieldFromInstruction(insn, 12, 3) << 9; |
| 28617 | if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28618 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28619 | return MCDisassembler::Fail; |
| 28620 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28621 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28622 | return S; |
| 28623 | case 386: |
| 28624 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28625 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28626 | tmp = 0x0; |
| 28627 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28628 | tmp |= fieldFromInstruction(insn, 12, 3) << 8; |
| 28629 | tmp |= fieldFromInstruction(insn, 26, 1) << 11; |
| 28630 | if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28631 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28632 | return MCDisassembler::Fail; |
| 28633 | return S; |
| 28634 | case 387: |
| 28635 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28636 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28637 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28638 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28639 | tmp = 0x0; |
| 28640 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28641 | tmp |= fieldFromInstruction(insn, 12, 3) << 8; |
| 28642 | tmp |= fieldFromInstruction(insn, 26, 1) << 11; |
| 28643 | if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28644 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28645 | return MCDisassembler::Fail; |
| 28646 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28647 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28648 | return S; |
| 28649 | case 388: |
| 28650 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28651 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28652 | tmp = 0x0; |
| 28653 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28654 | tmp |= fieldFromInstruction(insn, 12, 3) << 8; |
| 28655 | tmp |= fieldFromInstruction(insn, 26, 1) << 11; |
| 28656 | if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28657 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28658 | return MCDisassembler::Fail; |
| 28659 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28660 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28661 | return S; |
| 28662 | case 389: |
| 28663 | if (!Check(S, DecodeT2AddSubSPImm(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28664 | return S; |
| 28665 | case 390: |
| 28666 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28667 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28668 | tmp = 0x0; |
| 28669 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28670 | tmp |= fieldFromInstruction(insn, 12, 3) << 8; |
| 28671 | tmp |= fieldFromInstruction(insn, 26, 1) << 11; |
| 28672 | if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28673 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28674 | return MCDisassembler::Fail; |
| 28675 | return S; |
| 28676 | case 391: |
| 28677 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28678 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28679 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28680 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28681 | tmp = 0x0; |
| 28682 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28683 | tmp |= fieldFromInstruction(insn, 12, 3) << 8; |
| 28684 | tmp |= fieldFromInstruction(insn, 26, 1) << 11; |
| 28685 | if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28686 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28687 | return MCDisassembler::Fail; |
| 28688 | tmp = fieldFromInstruction(insn, 20, 1); |
| 28689 | if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28690 | return S; |
| 28691 | case 392: |
| 28692 | if (!Check(S, DecodeT2Adr(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28693 | return S; |
| 28694 | case 393: |
| 28695 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28696 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28697 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28698 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28699 | tmp = 0x0; |
| 28700 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28701 | tmp |= fieldFromInstruction(insn, 12, 3) << 8; |
| 28702 | tmp |= fieldFromInstruction(insn, 26, 1) << 11; |
| 28703 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28704 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28705 | return MCDisassembler::Fail; |
| 28706 | return S; |
| 28707 | case 394: |
| 28708 | if (!Check(S, DecodeT2MOVTWInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28709 | return S; |
| 28710 | case 395: |
| 28711 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28712 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28713 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28714 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28715 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28716 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28717 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28718 | return MCDisassembler::Fail; |
| 28719 | return S; |
| 28720 | case 396: |
| 28721 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28722 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28723 | tmp = fieldFromInstruction(insn, 0, 5); |
| 28724 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28725 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28726 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28727 | tmp = 0x0; |
| 28728 | tmp |= fieldFromInstruction(insn, 6, 2); |
| 28729 | tmp |= fieldFromInstruction(insn, 12, 3) << 2; |
| 28730 | tmp |= fieldFromInstruction(insn, 21, 1) << 5; |
| 28731 | if (!Check(S, DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28732 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28733 | return MCDisassembler::Fail; |
| 28734 | return S; |
| 28735 | case 397: |
| 28736 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28737 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28738 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28739 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28740 | tmp = 0x0; |
| 28741 | tmp |= fieldFromInstruction(insn, 6, 2); |
| 28742 | tmp |= fieldFromInstruction(insn, 12, 3) << 2; |
| 28743 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28744 | tmp = fieldFromInstruction(insn, 0, 5); |
| 28745 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28746 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28747 | return MCDisassembler::Fail; |
| 28748 | return S; |
| 28749 | case 398: |
| 28750 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28751 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28752 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28753 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28754 | tmp = 0x0; |
| 28755 | tmp |= fieldFromInstruction(insn, 0, 5) << 5; |
| 28756 | tmp |= fieldFromInstruction(insn, 6, 2); |
| 28757 | tmp |= fieldFromInstruction(insn, 12, 3) << 2; |
| 28758 | if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28759 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28760 | return MCDisassembler::Fail; |
| 28761 | return S; |
| 28762 | case 399: |
| 28763 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28764 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28765 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28766 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28767 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28768 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28769 | tmp = 0x0; |
| 28770 | tmp |= fieldFromInstruction(insn, 0, 5) << 5; |
| 28771 | tmp |= fieldFromInstruction(insn, 6, 2); |
| 28772 | tmp |= fieldFromInstruction(insn, 12, 3) << 2; |
| 28773 | if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28774 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28775 | return MCDisassembler::Fail; |
| 28776 | return S; |
| 28777 | case 400: |
| 28778 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28779 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28780 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28781 | return MCDisassembler::Fail; |
| 28782 | return S; |
| 28783 | case 401: |
| 28784 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28785 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28786 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28787 | return MCDisassembler::Fail; |
| 28788 | return S; |
| 28789 | case 402: |
| 28790 | if (!Check(S, DecodeT2HintSpaceInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28791 | return S; |
| 28792 | case 403: |
| 28793 | if (!Check(S, DecodeT2CPSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28794 | return S; |
| 28795 | case 404: |
| 28796 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28797 | if (!Check(S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28798 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28799 | return MCDisassembler::Fail; |
| 28800 | return S; |
| 28801 | case 405: |
| 28802 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28803 | if (!Check(S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28804 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28805 | return MCDisassembler::Fail; |
| 28806 | return S; |
| 28807 | case 406: |
| 28808 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28809 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28810 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28811 | return MCDisassembler::Fail; |
| 28812 | return S; |
| 28813 | case 407: |
| 28814 | tmp = 0x0; |
| 28815 | tmp |= fieldFromInstruction(insn, 0, 12); |
| 28816 | tmp |= fieldFromInstruction(insn, 16, 4) << 12; |
| 28817 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28818 | return S; |
| 28819 | case 408: |
| 28820 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28821 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 28822 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28823 | return MCDisassembler::Fail; |
| 28824 | return S; |
| 28825 | case 409: |
| 28826 | tmp = 0x0; |
| 28827 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 28828 | tmp |= fieldFromInstruction(insn, 20, 1) << 4; |
| 28829 | if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28830 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28831 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28832 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28833 | return MCDisassembler::Fail; |
| 28834 | return S; |
| 28835 | case 410: |
| 28836 | tmp = 0x0; |
| 28837 | tmp |= fieldFromInstruction(insn, 4, 1) << 4; |
| 28838 | tmp |= fieldFromInstruction(insn, 8, 4); |
| 28839 | tmp |= fieldFromInstruction(insn, 20, 1) << 5; |
| 28840 | if (!Check(S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28841 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28842 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28843 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28844 | return MCDisassembler::Fail; |
| 28845 | return S; |
| 28846 | case 411: |
| 28847 | tmp = 0x0; |
| 28848 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28849 | tmp |= fieldFromInstruction(insn, 10, 2) << 10; |
| 28850 | if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28851 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28852 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28853 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28854 | return MCDisassembler::Fail; |
| 28855 | return S; |
| 28856 | case 412: |
| 28857 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28858 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28859 | tmp = 0x0; |
| 28860 | tmp |= fieldFromInstruction(insn, 4, 1) << 4; |
| 28861 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 28862 | tmp |= fieldFromInstruction(insn, 20, 1) << 5; |
| 28863 | if (!Check(S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28864 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28865 | return MCDisassembler::Fail; |
| 28866 | return S; |
| 28867 | case 413: |
| 28868 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28869 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28870 | tmp = fieldFromInstruction(insn, 0, 8); |
| 28871 | if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28872 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28873 | return MCDisassembler::Fail; |
| 28874 | return S; |
| 28875 | case 414: |
| 28876 | if (!Check(S, DecodeThumb2BCCInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28877 | return S; |
| 28878 | case 415: |
| 28879 | if (!Check(S, DecodeLOLoop(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28880 | return S; |
| 28881 | case 416: |
| 28882 | tmp = fieldFromInstruction(insn, 23, 4); |
| 28883 | if (!Check(S, DecodeBFLabelOperand<false, false, false, 4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28884 | tmp = 0x0; |
| 28885 | tmp |= fieldFromInstruction(insn, 1, 10) << 1; |
| 28886 | tmp |= fieldFromInstruction(insn, 11, 1); |
| 28887 | tmp |= fieldFromInstruction(insn, 16, 7) << 11; |
| 28888 | if (!Check(S, DecodeBFLabelOperand<true, false, true, 18>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28889 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28890 | return MCDisassembler::Fail; |
| 28891 | return S; |
| 28892 | case 417: |
| 28893 | tmp = fieldFromInstruction(insn, 23, 4); |
| 28894 | if (!Check(S, DecodeBFLabelOperand<false, false, false, 4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28895 | tmp = 0x0; |
| 28896 | tmp |= fieldFromInstruction(insn, 1, 10) << 1; |
| 28897 | tmp |= fieldFromInstruction(insn, 11, 1); |
| 28898 | tmp |= fieldFromInstruction(insn, 16, 1) << 11; |
| 28899 | if (!Check(S, DecodeBFLabelOperand<true, false, true, 12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28900 | tmp = fieldFromInstruction(insn, 17, 1); |
| 28901 | if (!Check(S, DecodeBFAfterTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28902 | tmp = fieldFromInstruction(insn, 18, 4); |
| 28903 | if (!Check(S, DecodePredNoALOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28904 | return S; |
| 28905 | case 418: |
| 28906 | tmp = fieldFromInstruction(insn, 23, 4); |
| 28907 | if (!Check(S, DecodeBFLabelOperand<false, false, false, 4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28908 | tmp = 0x0; |
| 28909 | tmp |= fieldFromInstruction(insn, 1, 10) << 1; |
| 28910 | tmp |= fieldFromInstruction(insn, 11, 1); |
| 28911 | tmp |= fieldFromInstruction(insn, 16, 5) << 11; |
| 28912 | if (!Check(S, DecodeBFLabelOperand<true, false, true, 16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28913 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28914 | return MCDisassembler::Fail; |
| 28915 | return S; |
| 28916 | case 419: |
| 28917 | tmp = fieldFromInstruction(insn, 23, 4); |
| 28918 | if (!Check(S, DecodeBFLabelOperand<false, false, false, 4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28919 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28920 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28921 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28922 | return MCDisassembler::Fail; |
| 28923 | return S; |
| 28924 | case 420: |
| 28925 | if (!Check(S, DecodeT2BInstruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28926 | return S; |
| 28927 | case 421: |
| 28928 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28929 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28930 | tmp = 0x0; |
| 28931 | tmp |= fieldFromInstruction(insn, 0, 4) << 2; |
| 28932 | tmp |= fieldFromInstruction(insn, 4, 2); |
| 28933 | tmp |= fieldFromInstruction(insn, 16, 4) << 6; |
| 28934 | if (!Check(S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28935 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28936 | return MCDisassembler::Fail; |
| 28937 | return S; |
| 28938 | case 422: |
| 28939 | if (!Check(S, DecodeT2LdStPre(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28940 | return S; |
| 28941 | case 423: |
| 28942 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28943 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28944 | tmp = 0x0; |
| 28945 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28946 | tmp |= fieldFromInstruction(insn, 16, 4) << 9; |
| 28947 | if (!Check(S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28948 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28949 | return MCDisassembler::Fail; |
| 28950 | return S; |
| 28951 | case 424: |
| 28952 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28953 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28954 | tmp = 0x0; |
| 28955 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 28956 | tmp |= fieldFromInstruction(insn, 9, 1) << 8; |
| 28957 | tmp |= fieldFromInstruction(insn, 16, 4) << 9; |
| 28958 | if (!Check(S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28959 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28960 | return MCDisassembler::Fail; |
| 28961 | return S; |
| 28962 | case 425: |
| 28963 | tmp = fieldFromInstruction(insn, 12, 4); |
| 28964 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28965 | tmp = 0x1000; |
| 28966 | tmp |= fieldFromInstruction(insn, 0, 12); |
| 28967 | tmp |= fieldFromInstruction(insn, 16, 4) << 13; |
| 28968 | if (!Check(S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28969 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28970 | return MCDisassembler::Fail; |
| 28971 | return S; |
| 28972 | case 426: |
| 28973 | if (!Check(S, DecodeT2LoadShift(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28974 | return S; |
| 28975 | case 427: |
| 28976 | if (!Check(S, DecodeT2LoadImm8(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28977 | return S; |
| 28978 | case 428: |
| 28979 | if (!Check(S, DecodeT2LoadT(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28980 | return S; |
| 28981 | case 429: |
| 28982 | if (!Check(S, DecodeT2LoadImm12(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28983 | return S; |
| 28984 | case 430: |
| 28985 | if (!Check(S, DecodeT2LoadLabel(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28986 | return S; |
| 28987 | case 431: |
| 28988 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28989 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28990 | tmp = fieldFromInstruction(insn, 16, 4); |
| 28991 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28992 | tmp = fieldFromInstruction(insn, 0, 4); |
| 28993 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 28994 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 28995 | return MCDisassembler::Fail; |
| 28996 | return S; |
| 28997 | case 432: |
| 28998 | tmp = fieldFromInstruction(insn, 8, 4); |
| 28999 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29000 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29001 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29002 | tmp = fieldFromInstruction(insn, 4, 2); |
| 29003 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29004 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29005 | return MCDisassembler::Fail; |
| 29006 | return S; |
| 29007 | case 433: |
| 29008 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29009 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29010 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29011 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29012 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29013 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29014 | tmp = fieldFromInstruction(insn, 4, 2); |
| 29015 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29016 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29017 | return MCDisassembler::Fail; |
| 29018 | return S; |
| 29019 | case 434: |
| 29020 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29021 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29022 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29023 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29024 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29025 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29026 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29027 | return MCDisassembler::Fail; |
| 29028 | return S; |
| 29029 | case 435: |
| 29030 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29031 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29032 | tmp = 0x0; |
| 29033 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 29034 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 29035 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29036 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29037 | return MCDisassembler::Fail; |
| 29038 | return S; |
| 29039 | case 436: |
| 29040 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29041 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29042 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29043 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29044 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29045 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29046 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29047 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29048 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29049 | return MCDisassembler::Fail; |
| 29050 | return S; |
| 29051 | case 437: |
| 29052 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29053 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29054 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29055 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29056 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29057 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29058 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29059 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29060 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29061 | return MCDisassembler::Fail; |
| 29062 | return S; |
| 29063 | case 438: |
| 29064 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29065 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29066 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29067 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29068 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29069 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29070 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29071 | return MCDisassembler::Fail; |
| 29072 | return S; |
| 29073 | case 439: |
| 29074 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29075 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29076 | tmp = 0x0; |
| 29077 | tmp |= fieldFromInstruction(insn, 0, 4) << 2; |
| 29078 | tmp |= fieldFromInstruction(insn, 4, 2); |
| 29079 | tmp |= fieldFromInstruction(insn, 16, 4) << 6; |
| 29080 | if (!Check(S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29081 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29082 | return MCDisassembler::Fail; |
| 29083 | return S; |
| 29084 | case 440: |
| 29085 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29086 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29087 | tmp = 0x0; |
| 29088 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 29089 | tmp |= fieldFromInstruction(insn, 9, 1) << 8; |
| 29090 | tmp |= fieldFromInstruction(insn, 16, 4) << 9; |
| 29091 | if (!Check(S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29092 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29093 | return MCDisassembler::Fail; |
| 29094 | return S; |
| 29095 | case 441: |
| 29096 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29097 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29098 | tmp = 0x1000; |
| 29099 | tmp |= fieldFromInstruction(insn, 0, 12); |
| 29100 | tmp |= fieldFromInstruction(insn, 16, 4) << 13; |
| 29101 | if (!Check(S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29102 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29103 | return MCDisassembler::Fail; |
| 29104 | return S; |
| 29105 | case 442: |
| 29106 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29107 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29108 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29109 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29110 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29111 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29112 | return S; |
| 29113 | case 443: |
| 29114 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29115 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29116 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29117 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29118 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29119 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29120 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29121 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29122 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29123 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29124 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29125 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29126 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29127 | return MCDisassembler::Fail; |
| 29128 | return S; |
| 29129 | case 444: |
| 29130 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29131 | return MCDisassembler::Fail; |
| 29132 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29133 | if (!Check(S, DecodeGPRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29134 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29135 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29136 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29137 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29138 | return S; |
| 29139 | case 445: |
| 29140 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29141 | return MCDisassembler::Fail; |
| 29142 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29143 | if (!Check(S, DecodeGPRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29144 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29145 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29146 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29147 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29148 | return S; |
| 29149 | case 446: |
| 29150 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29151 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29152 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29153 | return MCDisassembler::Fail; |
| 29154 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29155 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29156 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29157 | if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29158 | return S; |
| 29159 | case 447: |
| 29160 | tmp = 0x0; |
| 29161 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29162 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29163 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29164 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29165 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29166 | tmp = 0x0; |
| 29167 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29168 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29169 | tmp |= fieldFromInstruction(insn, 16, 4) << 7; |
| 29170 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29171 | return S; |
| 29172 | case 448: |
| 29173 | tmp = 0x0; |
| 29174 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29175 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29176 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29177 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29178 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29179 | tmp = 0x0; |
| 29180 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29181 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29182 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29183 | tmp = 0x0; |
| 29184 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29185 | tmp |= fieldFromInstruction(insn, 7, 1) << 1; |
| 29186 | tmp |= fieldFromInstruction(insn, 16, 4) << 2; |
| 29187 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29188 | return S; |
| 29189 | case 449: |
| 29190 | tmp = 0x0; |
| 29191 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29192 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29193 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29194 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29195 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29196 | tmp = 0x0; |
| 29197 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29198 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29199 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29200 | tmp = 0x0; |
| 29201 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29202 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29203 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29204 | tmp = 0x0; |
| 29205 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29206 | tmp |= fieldFromInstruction(insn, 20, 2) << 1; |
| 29207 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29208 | return S; |
| 29209 | case 450: |
| 29210 | tmp = 0x0; |
| 29211 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 29212 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 29213 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29214 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29215 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29216 | tmp = 0x0; |
| 29217 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29218 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29219 | tmp |= fieldFromInstruction(insn, 16, 4) << 7; |
| 29220 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29221 | return S; |
| 29222 | case 451: |
| 29223 | tmp = 0x0; |
| 29224 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 29225 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 29226 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29227 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29228 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29229 | tmp = 0x0; |
| 29230 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 29231 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 29232 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29233 | tmp = 0x0; |
| 29234 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29235 | tmp |= fieldFromInstruction(insn, 7, 1) << 1; |
| 29236 | tmp |= fieldFromInstruction(insn, 16, 4) << 2; |
| 29237 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29238 | return S; |
| 29239 | case 452: |
| 29240 | tmp = 0x0; |
| 29241 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 29242 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 29243 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29244 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29245 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29246 | tmp = 0x0; |
| 29247 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 29248 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 29249 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29250 | tmp = 0x0; |
| 29251 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 29252 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 29253 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29254 | tmp = 0x0; |
| 29255 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29256 | tmp |= fieldFromInstruction(insn, 20, 2) << 1; |
| 29257 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29258 | return S; |
| 29259 | case 453: |
| 29260 | tmp = fieldFromInstruction(insn, 13, 3); |
| 29261 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29262 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29263 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29264 | tmp = 0x0; |
| 29265 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29266 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29267 | tmp |= fieldFromInstruction(insn, 16, 4) << 7; |
| 29268 | tmp |= fieldFromInstruction(insn, 24, 1) << 11; |
| 29269 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29270 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 29271 | return MCDisassembler::Fail; |
| 29272 | return S; |
| 29273 | case 454: |
| 29274 | tmp = fieldFromInstruction(insn, 13, 3); |
| 29275 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29276 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29277 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29278 | tmp = fieldFromInstruction(insn, 1, 3); |
| 29279 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29280 | tmp = 0x0; |
| 29281 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29282 | tmp |= fieldFromInstruction(insn, 7, 1) << 1; |
| 29283 | tmp |= fieldFromInstruction(insn, 16, 4) << 2; |
| 29284 | tmp |= fieldFromInstruction(insn, 24, 1) << 6; |
| 29285 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29286 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 29287 | return MCDisassembler::Fail; |
| 29288 | return S; |
| 29289 | case 455: |
| 29290 | tmp = fieldFromInstruction(insn, 13, 3); |
| 29291 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29292 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29293 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29294 | tmp = fieldFromInstruction(insn, 17, 3); |
| 29295 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29296 | tmp = fieldFromInstruction(insn, 1, 3); |
| 29297 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29298 | tmp = 0x0; |
| 29299 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29300 | tmp |= fieldFromInstruction(insn, 20, 2) << 1; |
| 29301 | tmp |= fieldFromInstruction(insn, 24, 1) << 3; |
| 29302 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29303 | if (!Check(Out&: S, In: DecodeVpredROperand(Inst&: MI, Decoder))) |
| 29304 | return MCDisassembler::Fail; |
| 29305 | return S; |
| 29306 | case 456: |
| 29307 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29308 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29309 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29310 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29311 | tmp = 0x0; |
| 29312 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29313 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29314 | tmp |= fieldFromInstruction(insn, 16, 6) << 7; |
| 29315 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29316 | return S; |
| 29317 | case 457: |
| 29318 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29319 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29320 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29321 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29322 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29323 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29324 | tmp = 0x0; |
| 29325 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29326 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29327 | tmp |= fieldFromInstruction(insn, 20, 2) << 7; |
| 29328 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29329 | return S; |
| 29330 | case 458: |
| 29331 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29332 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29333 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29334 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29335 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29336 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29337 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29338 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29339 | tmp = 0x0; |
| 29340 | tmp |= fieldFromInstruction(insn, 4, 2); |
| 29341 | tmp |= fieldFromInstruction(insn, 7, 1) << 2; |
| 29342 | tmp |= fieldFromInstruction(insn, 20, 3) << 3; |
| 29343 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29344 | return S; |
| 29345 | case 459: |
| 29346 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29347 | if (!Check(S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29348 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29349 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29350 | tmp = 0x0; |
| 29351 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29352 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29353 | tmp |= fieldFromInstruction(insn, 16, 6) << 7; |
| 29354 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29355 | return S; |
| 29356 | case 460: |
| 29357 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29358 | if (!Check(S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29359 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29360 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29361 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29362 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29363 | tmp = 0x0; |
| 29364 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29365 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29366 | tmp |= fieldFromInstruction(insn, 20, 2) << 7; |
| 29367 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29368 | return S; |
| 29369 | case 461: |
| 29370 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29371 | if (!Check(S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29372 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29373 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29374 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29375 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29376 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29377 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29378 | tmp = 0x0; |
| 29379 | tmp |= fieldFromInstruction(insn, 4, 2); |
| 29380 | tmp |= fieldFromInstruction(insn, 7, 1) << 2; |
| 29381 | tmp |= fieldFromInstruction(insn, 20, 3) << 3; |
| 29382 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29383 | return S; |
| 29384 | case 462: |
| 29385 | tmp = 0x0; |
| 29386 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29387 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29388 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29389 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29390 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29391 | tmp = 0x0; |
| 29392 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29393 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29394 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29395 | tmp = 0x0; |
| 29396 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29397 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29398 | tmp |= fieldFromInstruction(insn, 16, 4) << 7; |
| 29399 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29400 | return S; |
| 29401 | case 463: |
| 29402 | tmp = 0x0; |
| 29403 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29404 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29405 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29406 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29407 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29408 | tmp = 0x0; |
| 29409 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29410 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29411 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29412 | tmp = 0x0; |
| 29413 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29414 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29415 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29416 | tmp = 0x0; |
| 29417 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29418 | tmp |= fieldFromInstruction(insn, 7, 1) << 1; |
| 29419 | tmp |= fieldFromInstruction(insn, 16, 4) << 2; |
| 29420 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29421 | return S; |
| 29422 | case 464: |
| 29423 | tmp = 0x0; |
| 29424 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29425 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29426 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29427 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29428 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29429 | tmp = 0x0; |
| 29430 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29431 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29432 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29433 | tmp = 0x0; |
| 29434 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29435 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29436 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29437 | tmp = 0x0; |
| 29438 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29439 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29440 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29441 | tmp = 0x0; |
| 29442 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29443 | tmp |= fieldFromInstruction(insn, 20, 2) << 1; |
| 29444 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29445 | return S; |
| 29446 | case 465: |
| 29447 | tmp = 0x0; |
| 29448 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 29449 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 29450 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29451 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29452 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29453 | tmp = 0x0; |
| 29454 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 29455 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 29456 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29457 | tmp = 0x0; |
| 29458 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29459 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29460 | tmp |= fieldFromInstruction(insn, 16, 4) << 7; |
| 29461 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29462 | return S; |
| 29463 | case 466: |
| 29464 | tmp = 0x0; |
| 29465 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 29466 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 29467 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29468 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29469 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29470 | tmp = 0x0; |
| 29471 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 29472 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 29473 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29474 | tmp = 0x0; |
| 29475 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 29476 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 29477 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29478 | tmp = 0x0; |
| 29479 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29480 | tmp |= fieldFromInstruction(insn, 7, 1) << 1; |
| 29481 | tmp |= fieldFromInstruction(insn, 16, 4) << 2; |
| 29482 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29483 | return S; |
| 29484 | case 467: |
| 29485 | tmp = 0x0; |
| 29486 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 29487 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 29488 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29489 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29490 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29491 | tmp = 0x0; |
| 29492 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 29493 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 29494 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29495 | tmp = 0x0; |
| 29496 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 29497 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 29498 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29499 | tmp = 0x0; |
| 29500 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 29501 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 29502 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29503 | tmp = 0x0; |
| 29504 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29505 | tmp |= fieldFromInstruction(insn, 20, 2) << 1; |
| 29506 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29507 | return S; |
| 29508 | case 468: |
| 29509 | tmp = fieldFromInstruction(insn, 13, 3); |
| 29510 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29511 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29512 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29513 | tmp = fieldFromInstruction(insn, 13, 3); |
| 29514 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29515 | tmp = 0x0; |
| 29516 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29517 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29518 | tmp |= fieldFromInstruction(insn, 16, 4) << 7; |
| 29519 | tmp |= fieldFromInstruction(insn, 24, 1) << 11; |
| 29520 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29521 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 29522 | return MCDisassembler::Fail; |
| 29523 | return S; |
| 29524 | case 469: |
| 29525 | tmp = fieldFromInstruction(insn, 13, 3); |
| 29526 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29527 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29528 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29529 | tmp = fieldFromInstruction(insn, 13, 3); |
| 29530 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29531 | tmp = fieldFromInstruction(insn, 1, 3); |
| 29532 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29533 | tmp = 0x0; |
| 29534 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29535 | tmp |= fieldFromInstruction(insn, 7, 1) << 1; |
| 29536 | tmp |= fieldFromInstruction(insn, 16, 4) << 2; |
| 29537 | tmp |= fieldFromInstruction(insn, 24, 1) << 6; |
| 29538 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29539 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 29540 | return MCDisassembler::Fail; |
| 29541 | return S; |
| 29542 | case 470: |
| 29543 | tmp = fieldFromInstruction(insn, 13, 3); |
| 29544 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29545 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29546 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29547 | tmp = fieldFromInstruction(insn, 13, 3); |
| 29548 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29549 | tmp = fieldFromInstruction(insn, 17, 3); |
| 29550 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29551 | tmp = fieldFromInstruction(insn, 1, 3); |
| 29552 | if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29553 | tmp = 0x0; |
| 29554 | tmp |= fieldFromInstruction(insn, 4, 1); |
| 29555 | tmp |= fieldFromInstruction(insn, 20, 2) << 1; |
| 29556 | tmp |= fieldFromInstruction(insn, 24, 1) << 3; |
| 29557 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29558 | if (!Check(Out&: S, In: DecodeVpredNOperand(Inst&: MI, Decoder))) |
| 29559 | return MCDisassembler::Fail; |
| 29560 | return S; |
| 29561 | case 471: |
| 29562 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29563 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29564 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29565 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29566 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29567 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29568 | tmp = 0x0; |
| 29569 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29570 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29571 | tmp |= fieldFromInstruction(insn, 16, 6) << 7; |
| 29572 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29573 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29574 | return MCDisassembler::Fail; |
| 29575 | return S; |
| 29576 | case 472: |
| 29577 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29578 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29579 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29580 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29581 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29582 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29583 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29584 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29585 | tmp = 0x0; |
| 29586 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29587 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29588 | tmp |= fieldFromInstruction(insn, 20, 2) << 7; |
| 29589 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29590 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29591 | return MCDisassembler::Fail; |
| 29592 | return S; |
| 29593 | case 473: |
| 29594 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29595 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29596 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29597 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29598 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29599 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29600 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29601 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29602 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29603 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29604 | tmp = 0x0; |
| 29605 | tmp |= fieldFromInstruction(insn, 4, 2); |
| 29606 | tmp |= fieldFromInstruction(insn, 7, 1) << 2; |
| 29607 | tmp |= fieldFromInstruction(insn, 20, 3) << 3; |
| 29608 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29609 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29610 | return MCDisassembler::Fail; |
| 29611 | return S; |
| 29612 | case 474: |
| 29613 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29614 | if (!Check(S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29615 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29616 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29617 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29618 | if (!Check(S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29619 | tmp = 0x0; |
| 29620 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29621 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29622 | tmp |= fieldFromInstruction(insn, 16, 6) << 7; |
| 29623 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29624 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29625 | return MCDisassembler::Fail; |
| 29626 | return S; |
| 29627 | case 475: |
| 29628 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29629 | if (!Check(S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29630 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29631 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29632 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29633 | if (!Check(S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29634 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29635 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29636 | tmp = 0x0; |
| 29637 | tmp |= fieldFromInstruction(insn, 0, 6); |
| 29638 | tmp |= fieldFromInstruction(insn, 7, 1) << 6; |
| 29639 | tmp |= fieldFromInstruction(insn, 20, 2) << 7; |
| 29640 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29641 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29642 | return MCDisassembler::Fail; |
| 29643 | return S; |
| 29644 | case 476: |
| 29645 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29646 | if (!Check(S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29647 | tmp = fieldFromInstruction(insn, 8, 3); |
| 29648 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29649 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29650 | if (!Check(S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29651 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29652 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29653 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29654 | if (!Check(S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29655 | tmp = 0x0; |
| 29656 | tmp |= fieldFromInstruction(insn, 4, 2); |
| 29657 | tmp |= fieldFromInstruction(insn, 7, 1) << 2; |
| 29658 | tmp |= fieldFromInstruction(insn, 20, 3) << 3; |
| 29659 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29660 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29661 | return MCDisassembler::Fail; |
| 29662 | return S; |
| 29663 | case 477: |
| 29664 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29665 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29666 | tmp = fieldFromInstruction(insn, 4, 4); |
| 29667 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29668 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29669 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29670 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29671 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29672 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29673 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29674 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29675 | return MCDisassembler::Fail; |
| 29676 | return S; |
| 29677 | case 478: |
| 29678 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29679 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29680 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29681 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29682 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29683 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29684 | tmp = fieldFromInstruction(insn, 4, 4); |
| 29685 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29686 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29687 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29688 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29689 | return MCDisassembler::Fail; |
| 29690 | return S; |
| 29691 | case 479: |
| 29692 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29693 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29694 | tmp = fieldFromInstruction(insn, 20, 4); |
| 29695 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29696 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29697 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29698 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29699 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29700 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29701 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29702 | tmp = fieldFromInstruction(insn, 5, 3); |
| 29703 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29704 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29705 | return MCDisassembler::Fail; |
| 29706 | return S; |
| 29707 | case 480: |
| 29708 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29709 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29710 | tmp = fieldFromInstruction(insn, 21, 3); |
| 29711 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29712 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29713 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29714 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29715 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29716 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29717 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29718 | tmp = fieldFromInstruction(insn, 5, 3); |
| 29719 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29720 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29721 | return MCDisassembler::Fail; |
| 29722 | return S; |
| 29723 | case 481: |
| 29724 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29725 | if (!Check(S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29726 | tmp = fieldFromInstruction(insn, 8, 4); |
| 29727 | if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29728 | tmp = fieldFromInstruction(insn, 21, 3); |
| 29729 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29730 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29731 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29732 | tmp = fieldFromInstruction(insn, 0, 4); |
| 29733 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29734 | tmp = fieldFromInstruction(insn, 5, 3); |
| 29735 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29736 | if (!Check(Out&: S, In: DecodePredicateOperand(Inst&: MI, Decoder))) |
| 29737 | return MCDisassembler::Fail; |
| 29738 | return S; |
| 29739 | case 482: |
| 29740 | tmp = 0x0; |
| 29741 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29742 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29743 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29744 | tmp = 0x0; |
| 29745 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 29746 | tmp |= fieldFromInstruction(insn, 16, 4) << 9; |
| 29747 | tmp |= fieldFromInstruction(insn, 23, 1) << 8; |
| 29748 | if (!Check(S, DecodeAddrMode5FP16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29749 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29750 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29751 | return S; |
| 29752 | case 483: |
| 29753 | tmp = 0x0; |
| 29754 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29755 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29756 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29757 | tmp = 0x0; |
| 29758 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29759 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29760 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29761 | tmp = 0x0; |
| 29762 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29763 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29764 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29765 | tmp = 0x0; |
| 29766 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29767 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29768 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29769 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29770 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29771 | return S; |
| 29772 | case 484: |
| 29773 | tmp = 0x0; |
| 29774 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29775 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29776 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29777 | tmp = 0x0; |
| 29778 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29779 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29780 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29781 | tmp = 0x0; |
| 29782 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29783 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29784 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29785 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29786 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29787 | return S; |
| 29788 | case 485: |
| 29789 | tmp = 0x0; |
| 29790 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29791 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29792 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29793 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29794 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29795 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29796 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29797 | return S; |
| 29798 | case 486: |
| 29799 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29800 | if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29801 | tmp = 0x0; |
| 29802 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29803 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29804 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29805 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29806 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29807 | return S; |
| 29808 | case 487: |
| 29809 | tmp = 0x0; |
| 29810 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29811 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29812 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29813 | tmp = 0x0; |
| 29814 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 29815 | tmp |= fieldFromInstruction(insn, 16, 4) << 4; |
| 29816 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29817 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29818 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29819 | return S; |
| 29820 | case 488: |
| 29821 | tmp = 0x0; |
| 29822 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29823 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29824 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29825 | tmp = 0x0; |
| 29826 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29827 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29828 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29829 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29830 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29831 | return S; |
| 29832 | case 489: |
| 29833 | tmp = 0x0; |
| 29834 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29835 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29836 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29837 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29838 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29839 | return S; |
| 29840 | case 490: |
| 29841 | tmp = 0x0; |
| 29842 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29843 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29844 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29845 | tmp = 0x0; |
| 29846 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29847 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29848 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29849 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29850 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29851 | return S; |
| 29852 | case 491: |
| 29853 | tmp = 0x0; |
| 29854 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29855 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29856 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29857 | tmp = 0x0; |
| 29858 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29859 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29860 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29861 | tmp = 0x0; |
| 29862 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29863 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29864 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 29865 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29866 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29867 | return S; |
| 29868 | case 492: |
| 29869 | tmp = 0x0; |
| 29870 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29871 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29872 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29873 | tmp = 0x0; |
| 29874 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29875 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29876 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29877 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29878 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29879 | return S; |
| 29880 | case 493: |
| 29881 | tmp = 0x0; |
| 29882 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29883 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29884 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29885 | tmp = 0x0; |
| 29886 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29887 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29888 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29889 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29890 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29891 | return S; |
| 29892 | case 494: |
| 29893 | if (!Check(S, DecodeVMOVSRR(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29894 | return S; |
| 29895 | case 495: |
| 29896 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29897 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29898 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29899 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29900 | tmp = 0x0; |
| 29901 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 29902 | tmp |= fieldFromInstruction(insn, 12, 4) << 9; |
| 29903 | tmp |= fieldFromInstruction(insn, 22, 1) << 8; |
| 29904 | if (!Check(S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29905 | return S; |
| 29906 | case 496: |
| 29907 | tmp = 0x0; |
| 29908 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29909 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29910 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29911 | tmp = 0x0; |
| 29912 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 29913 | tmp |= fieldFromInstruction(insn, 16, 4) << 9; |
| 29914 | tmp |= fieldFromInstruction(insn, 23, 1) << 8; |
| 29915 | if (!Check(S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29916 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29917 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29918 | return S; |
| 29919 | case 497: |
| 29920 | tmp = 0x0; |
| 29921 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29922 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29923 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29924 | tmp = 0x0; |
| 29925 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29926 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29927 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29928 | tmp = 0x0; |
| 29929 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29930 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29931 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29932 | tmp = 0x0; |
| 29933 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29934 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29935 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29936 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29937 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29938 | return S; |
| 29939 | case 498: |
| 29940 | tmp = 0x0; |
| 29941 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 29942 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 29943 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29944 | tmp = 0x0; |
| 29945 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29946 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29947 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29948 | tmp = 0x0; |
| 29949 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 29950 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 29951 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29952 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29953 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29954 | return S; |
| 29955 | case 499: |
| 29956 | tmp = 0x0; |
| 29957 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29958 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29959 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29960 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29961 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29962 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29963 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29964 | return S; |
| 29965 | case 500: |
| 29966 | if (!Check(S, DecodeVMOVRRS(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29967 | return S; |
| 29968 | case 501: |
| 29969 | if (!Check(S, DecodeVSCCLRM(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29970 | return S; |
| 29971 | case 502: |
| 29972 | tmp = fieldFromInstruction(insn, 12, 4); |
| 29973 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29974 | tmp = 0x0; |
| 29975 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 29976 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 29977 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29978 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29979 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29980 | return S; |
| 29981 | case 503: |
| 29982 | if (!Check(S, DecodeLazyLoadStoreMul(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29983 | return S; |
| 29984 | case 504: |
| 29985 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29986 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29987 | tmp = fieldFromInstruction(insn, 16, 4); |
| 29988 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29989 | tmp = fieldFromInstruction(insn, 28, 4); |
| 29990 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29991 | tmp = 0x0; |
| 29992 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 29993 | tmp |= fieldFromInstruction(insn, 12, 4) << 9; |
| 29994 | tmp |= fieldFromInstruction(insn, 22, 1) << 8; |
| 29995 | if (!Check(S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29996 | return S; |
| 29997 | case 505: |
| 29998 | if (!Check(S, DecodeForVMRSandVMSR(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 29999 | return S; |
| 30000 | case 506: |
| 30001 | tmp = 0x0; |
| 30002 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30003 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30004 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30005 | tmp = 0x0; |
| 30006 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30007 | tmp |= fieldFromInstruction(insn, 16, 4) << 4; |
| 30008 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30009 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30010 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30011 | return S; |
| 30012 | case 507: |
| 30013 | tmp = 0x0; |
| 30014 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30015 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30016 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30017 | tmp = 0x0; |
| 30018 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30019 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30020 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30021 | tmp = 0x0; |
| 30022 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30023 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30024 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30025 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30026 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30027 | return S; |
| 30028 | case 508: |
| 30029 | tmp = 0x0; |
| 30030 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30031 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30032 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30033 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30034 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30035 | return S; |
| 30036 | case 509: |
| 30037 | tmp = 0x0; |
| 30038 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30039 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30040 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30041 | tmp = 0x0; |
| 30042 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30043 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30044 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30045 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30046 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30047 | return S; |
| 30048 | case 510: |
| 30049 | tmp = 0x0; |
| 30050 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30051 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30052 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30053 | tmp = fieldFromInstruction(insn, 12, 4); |
| 30054 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30055 | tmp = fieldFromInstruction(insn, 16, 4); |
| 30056 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30057 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30058 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30059 | return S; |
| 30060 | case 511: |
| 30061 | tmp = fieldFromInstruction(insn, 16, 4); |
| 30062 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30063 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30064 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30065 | tmp = 0x0; |
| 30066 | tmp |= fieldFromInstruction(insn, 1, 7) << 1; |
| 30067 | tmp |= fieldFromInstruction(insn, 12, 4) << 8; |
| 30068 | tmp |= fieldFromInstruction(insn, 22, 1) << 12; |
| 30069 | if (!Check(S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30070 | return S; |
| 30071 | case 512: |
| 30072 | tmp = fieldFromInstruction(insn, 16, 4); |
| 30073 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30074 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30075 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30076 | tmp = 0x0; |
| 30077 | tmp |= fieldFromInstruction(insn, 1, 7) << 1; |
| 30078 | tmp |= fieldFromInstruction(insn, 12, 4) << 8; |
| 30079 | if (!Check(S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30080 | return S; |
| 30081 | case 513: |
| 30082 | tmp = 0x0; |
| 30083 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30084 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30085 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30086 | tmp = 0x0; |
| 30087 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 30088 | tmp |= fieldFromInstruction(insn, 16, 4) << 9; |
| 30089 | tmp |= fieldFromInstruction(insn, 23, 1) << 8; |
| 30090 | if (!Check(S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30091 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30092 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30093 | return S; |
| 30094 | case 514: |
| 30095 | tmp = 0x0; |
| 30096 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30097 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30098 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30099 | tmp = 0x0; |
| 30100 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30101 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30102 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30103 | tmp = 0x0; |
| 30104 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30105 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30106 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30107 | tmp = 0x0; |
| 30108 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30109 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30110 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30111 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30112 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30113 | return S; |
| 30114 | case 515: |
| 30115 | tmp = 0x0; |
| 30116 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30117 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30118 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30119 | tmp = 0x0; |
| 30120 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30121 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30122 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30123 | tmp = 0x0; |
| 30124 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30125 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30126 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30127 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30128 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30129 | return S; |
| 30130 | case 516: |
| 30131 | tmp = fieldFromInstruction(insn, 12, 4); |
| 30132 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30133 | tmp = fieldFromInstruction(insn, 16, 4); |
| 30134 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30135 | tmp = 0x0; |
| 30136 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30137 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30138 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30139 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30140 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30141 | return S; |
| 30142 | case 517: |
| 30143 | tmp = fieldFromInstruction(insn, 16, 4); |
| 30144 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30145 | tmp = fieldFromInstruction(insn, 16, 4); |
| 30146 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30147 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30148 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30149 | tmp = 0x0; |
| 30150 | tmp |= fieldFromInstruction(insn, 1, 7) << 1; |
| 30151 | tmp |= fieldFromInstruction(insn, 12, 4) << 8; |
| 30152 | tmp |= fieldFromInstruction(insn, 22, 1) << 12; |
| 30153 | if (!Check(S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30154 | return S; |
| 30155 | case 518: |
| 30156 | tmp = fieldFromInstruction(insn, 16, 4); |
| 30157 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30158 | tmp = fieldFromInstruction(insn, 16, 4); |
| 30159 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30160 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30161 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30162 | tmp = 0x0; |
| 30163 | tmp |= fieldFromInstruction(insn, 1, 7) << 1; |
| 30164 | tmp |= fieldFromInstruction(insn, 12, 4) << 8; |
| 30165 | if (!Check(S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30166 | return S; |
| 30167 | case 519: |
| 30168 | tmp = 0x0; |
| 30169 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30170 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30171 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30172 | tmp = 0x0; |
| 30173 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30174 | tmp |= fieldFromInstruction(insn, 16, 4) << 4; |
| 30175 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30176 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30177 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30178 | return S; |
| 30179 | case 520: |
| 30180 | tmp = 0x0; |
| 30181 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30182 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30183 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30184 | tmp = 0x0; |
| 30185 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30186 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30187 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30188 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30189 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30190 | return S; |
| 30191 | case 521: |
| 30192 | tmp = 0x0; |
| 30193 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30194 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30195 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30196 | tmp = 0x0; |
| 30197 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30198 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30199 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30200 | tmp = 0x0; |
| 30201 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30202 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30203 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30204 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30205 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30206 | return S; |
| 30207 | case 522: |
| 30208 | tmp = 0x0; |
| 30209 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30210 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30211 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30212 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30213 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30214 | return S; |
| 30215 | case 523: |
| 30216 | tmp = 0x0; |
| 30217 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30218 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30219 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30220 | tmp = 0x0; |
| 30221 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30222 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30223 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30224 | tmp = 0x0; |
| 30225 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30226 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30227 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30228 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30229 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30230 | return S; |
| 30231 | case 524: |
| 30232 | tmp = 0x0; |
| 30233 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30234 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30235 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30236 | tmp = 0x0; |
| 30237 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30238 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30239 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30240 | tmp = fieldFromInstruction(insn, 28, 4); |
| 30241 | if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30242 | return S; |
| 30243 | case 525: |
| 30244 | if (!Check(S, DecodeVSTRVLDR_SYSREG<false>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30245 | return S; |
| 30246 | case 526: |
| 30247 | if (!Check(S, DecodeVSTRVLDR_SYSREG<true>(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30248 | return S; |
| 30249 | case 527: |
| 30250 | tmp = 0x0; |
| 30251 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30252 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30253 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30254 | tmp = 0x0; |
| 30255 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30256 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30257 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30258 | tmp = 0x0; |
| 30259 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30260 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30261 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30262 | tmp = fieldFromInstruction(insn, 24, 1); |
| 30263 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30264 | return S; |
| 30265 | case 528: |
| 30266 | tmp = 0x0; |
| 30267 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30268 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30269 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30270 | tmp = 0x0; |
| 30271 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30272 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30273 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30274 | tmp = 0x0; |
| 30275 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30276 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30277 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30278 | tmp = 0x0; |
| 30279 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30280 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30281 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30282 | tmp = fieldFromInstruction(insn, 23, 2); |
| 30283 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30284 | return S; |
| 30285 | case 529: |
| 30286 | tmp = 0x0; |
| 30287 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30288 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30289 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30290 | tmp = 0x0; |
| 30291 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30292 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30293 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30294 | tmp = 0x0; |
| 30295 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30296 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30297 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30298 | tmp = fieldFromInstruction(insn, 0, 4); |
| 30299 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30300 | tmp = fieldFromInstruction(insn, 5, 1); |
| 30301 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30302 | tmp = fieldFromInstruction(insn, 20, 2); |
| 30303 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30304 | return S; |
| 30305 | case 530: |
| 30306 | if (!Check(S, DecodeNEONComplexLane64Instruction(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30307 | return S; |
| 30308 | case 531: |
| 30309 | tmp = 0x0; |
| 30310 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30311 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30312 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30313 | tmp = 0x0; |
| 30314 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30315 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30316 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30317 | tmp = 0x0; |
| 30318 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30319 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30320 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30321 | tmp = fieldFromInstruction(insn, 24, 1); |
| 30322 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30323 | return S; |
| 30324 | case 532: |
| 30325 | tmp = 0x0; |
| 30326 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30327 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30328 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30329 | tmp = 0x0; |
| 30330 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30331 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30332 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30333 | tmp = 0x0; |
| 30334 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30335 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30336 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30337 | tmp = 0x0; |
| 30338 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30339 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30340 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30341 | tmp = fieldFromInstruction(insn, 23, 2); |
| 30342 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30343 | return S; |
| 30344 | case 533: |
| 30345 | tmp = 0x0; |
| 30346 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30347 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30348 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30349 | tmp = 0x0; |
| 30350 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30351 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30352 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30353 | tmp = 0x0; |
| 30354 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30355 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30356 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30357 | tmp = fieldFromInstruction(insn, 0, 4); |
| 30358 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30359 | tmp = fieldFromInstruction(insn, 5, 1); |
| 30360 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30361 | tmp = fieldFromInstruction(insn, 20, 2); |
| 30362 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30363 | return S; |
| 30364 | case 534: |
| 30365 | tmp = 0x0; |
| 30366 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30367 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30368 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30369 | tmp = 0x0; |
| 30370 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 30371 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 30372 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30373 | tmp = 0x0; |
| 30374 | tmp |= fieldFromInstruction(insn, 0, 3) << 1; |
| 30375 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30376 | if (!Check(S, DecodeSPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30377 | tmp = fieldFromInstruction(insn, 3, 1); |
| 30378 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30379 | return S; |
| 30380 | case 535: |
| 30381 | tmp = 0x0; |
| 30382 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30383 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30384 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30385 | tmp = 0x0; |
| 30386 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30387 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30388 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30389 | tmp = fieldFromInstruction(insn, 0, 3); |
| 30390 | if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30391 | tmp = 0x0; |
| 30392 | tmp |= fieldFromInstruction(insn, 3, 1); |
| 30393 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 30394 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30395 | return S; |
| 30396 | case 536: |
| 30397 | tmp = 0x0; |
| 30398 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30399 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30400 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30401 | tmp = 0x0; |
| 30402 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 30403 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 30404 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30405 | tmp = 0x0; |
| 30406 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30407 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30408 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30409 | return S; |
| 30410 | case 537: |
| 30411 | tmp = 0x0; |
| 30412 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30413 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30414 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30415 | tmp = 0x0; |
| 30416 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30417 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30418 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30419 | tmp = 0x0; |
| 30420 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30421 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30422 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30423 | tmp = 0x0; |
| 30424 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30425 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30426 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30427 | return S; |
| 30428 | case 538: |
| 30429 | tmp = 0x0; |
| 30430 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30431 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30432 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30433 | tmp = 0x0; |
| 30434 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30435 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30436 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30437 | tmp = 0x0; |
| 30438 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30439 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30440 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30441 | tmp = fieldFromInstruction(insn, 0, 3); |
| 30442 | if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30443 | tmp = 0x0; |
| 30444 | tmp |= fieldFromInstruction(insn, 3, 1); |
| 30445 | tmp |= fieldFromInstruction(insn, 5, 1) << 1; |
| 30446 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30447 | return S; |
| 30448 | case 539: |
| 30449 | tmp = 0x0; |
| 30450 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30451 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30452 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30453 | tmp = 0x0; |
| 30454 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 30455 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 30456 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30457 | tmp = 0x0; |
| 30458 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30459 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30460 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30461 | return S; |
| 30462 | case 540: |
| 30463 | tmp = 0x0; |
| 30464 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30465 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30466 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30467 | tmp = 0x0; |
| 30468 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30469 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30470 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30471 | return S; |
| 30472 | case 541: |
| 30473 | tmp = 0x0; |
| 30474 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30475 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30476 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30477 | tmp = 0x0; |
| 30478 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30479 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30480 | if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30481 | return S; |
| 30482 | case 542: |
| 30483 | tmp = 0x0; |
| 30484 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30485 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30486 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30487 | tmp = 0x0; |
| 30488 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 30489 | tmp |= fieldFromInstruction(insn, 16, 4) << 1; |
| 30490 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30491 | tmp = 0x0; |
| 30492 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30493 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30494 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30495 | return S; |
| 30496 | case 543: |
| 30497 | tmp = 0x0; |
| 30498 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30499 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30500 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30501 | tmp = 0x0; |
| 30502 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30503 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30504 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30505 | return S; |
| 30506 | case 544: |
| 30507 | tmp = 0x0; |
| 30508 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30509 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30510 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30511 | tmp = 0x0; |
| 30512 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30513 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30514 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30515 | tmp = 0x0; |
| 30516 | tmp |= fieldFromInstruction(insn, 0, 4) << 1; |
| 30517 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 30518 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30519 | return S; |
| 30520 | case 545: |
| 30521 | tmp = 0x0; |
| 30522 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30523 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30524 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30525 | tmp = 0x0; |
| 30526 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30527 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30528 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30529 | tmp = 0x0; |
| 30530 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30531 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30532 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30533 | return S; |
| 30534 | case 546: |
| 30535 | tmp = 0x0; |
| 30536 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30537 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30538 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30539 | tmp = 0x0; |
| 30540 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30541 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30542 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30543 | return S; |
| 30544 | case 547: |
| 30545 | tmp = 0x0; |
| 30546 | tmp |= fieldFromInstruction(insn, 12, 4) << 1; |
| 30547 | tmp |= fieldFromInstruction(insn, 22, 1); |
| 30548 | if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30549 | tmp = 0x0; |
| 30550 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30551 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30552 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30553 | return S; |
| 30554 | case 548: |
| 30555 | tmp = 0x0; |
| 30556 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30557 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30558 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30559 | tmp = 0x0; |
| 30560 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30561 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30562 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30563 | tmp = 0x0; |
| 30564 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30565 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30566 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30567 | tmp = 0x0; |
| 30568 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30569 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30570 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30571 | return S; |
| 30572 | case 549: |
| 30573 | tmp = 0x0; |
| 30574 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30575 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30576 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30577 | tmp = 0x0; |
| 30578 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30579 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30580 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30581 | tmp = 0x0; |
| 30582 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30583 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30584 | if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30585 | tmp = fieldFromInstruction(insn, 0, 4); |
| 30586 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30587 | tmp = fieldFromInstruction(insn, 5, 1); |
| 30588 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30589 | return S; |
| 30590 | case 550: |
| 30591 | tmp = 0x0; |
| 30592 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30593 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30594 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30595 | tmp = 0x0; |
| 30596 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30597 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30598 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30599 | tmp = 0x0; |
| 30600 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30601 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30602 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30603 | tmp = fieldFromInstruction(insn, 0, 4); |
| 30604 | if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30605 | tmp = fieldFromInstruction(insn, 5, 1); |
| 30606 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 30607 | return S; |
| 30608 | case 551: |
| 30609 | tmp = 0x0; |
| 30610 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30611 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30612 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30613 | tmp = 0x0; |
| 30614 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30615 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30616 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30617 | return S; |
| 30618 | case 552: |
| 30619 | tmp = 0x0; |
| 30620 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30621 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30622 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30623 | tmp = 0x0; |
| 30624 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30625 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30626 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30627 | tmp = 0x0; |
| 30628 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30629 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30630 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30631 | return S; |
| 30632 | case 553: |
| 30633 | tmp = 0x0; |
| 30634 | tmp |= fieldFromInstruction(insn, 12, 4); |
| 30635 | tmp |= fieldFromInstruction(insn, 22, 1) << 4; |
| 30636 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30637 | tmp = 0x0; |
| 30638 | tmp |= fieldFromInstruction(insn, 7, 1) << 4; |
| 30639 | tmp |= fieldFromInstruction(insn, 16, 4); |
| 30640 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30641 | tmp = 0x0; |
| 30642 | tmp |= fieldFromInstruction(insn, 0, 4); |
| 30643 | tmp |= fieldFromInstruction(insn, 5, 1) << 4; |
| 30644 | if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 30645 | return S; |
| 30646 | } |
| 30647 | } |
| 30648 | static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset &FB) { |
| 30649 | switch (Idx) { |
| 30650 | default: llvm_unreachable("Invalid index!"); |
| 30651 | case 0: |
| 30652 | return FB[ARM::ModeThumb]; |
| 30653 | case 1: |
| 30654 | return FB[ARM::ModeThumb] && FB[ARM::Feature8MSecExt]; |
| 30655 | case 2: |
| 30656 | return FB[ARM::ModeThumb] && FB[ARM::HasV5TOps]; |
| 30657 | case 3: |
| 30658 | return FB[ARM::ModeThumb] && FB[ARM::HasV6Ops]; |
| 30659 | case 4: |
| 30660 | return FB[ARM::ModeThumb] && FB[ARM::HasV8MBaselineOps]; |
| 30661 | case 5: |
| 30662 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::HasV8Ops] && FB[ARM::HasV8_1aOps]; |
| 30663 | case 6: |
| 30664 | return FB[ARM::ModeThumb] && !FB[ARM::FeatureMClass]; |
| 30665 | case 7: |
| 30666 | return FB[ARM::ModeThumb] && FB[ARM::HasV8Ops]; |
| 30667 | case 8: |
| 30668 | return FB[ARM::ModeThumb] && FB[ARM::HasV6MOps]; |
| 30669 | case 9: |
| 30670 | return FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]; |
| 30671 | case 10: |
| 30672 | return !FB[ARM::ModeThumb]; |
| 30673 | case 11: |
| 30674 | return !FB[ARM::ModeThumb] && FB[ARM::HasV6Ops]; |
| 30675 | case 12: |
| 30676 | return !FB[ARM::ModeThumb] && FB[ARM::FeatureCRC]; |
| 30677 | case 13: |
| 30678 | return !FB[ARM::ModeThumb] && FB[ARM::HasV5TEOps]; |
| 30679 | case 14: |
| 30680 | return !FB[ARM::ModeThumb] && !FB[ARM::HasV8Ops]; |
| 30681 | case 15: |
| 30682 | return !FB[ARM::ModeThumb] && FB[ARM::HasV8Ops]; |
| 30683 | case 16: |
| 30684 | return !FB[ARM::ModeThumb] && FB[ARM::HasV8Ops] && FB[ARM::HasV8_1aOps]; |
| 30685 | case 17: |
| 30686 | return !FB[ARM::ModeThumb] && FB[ARM::FeatureVirtualization]; |
| 30687 | case 18: |
| 30688 | return !FB[ARM::ModeThumb] && FB[ARM::FeatureAcquireRelease]; |
| 30689 | case 19: |
| 30690 | return !FB[ARM::ModeThumb] && FB[ARM::FeatureAcquireRelease] && FB[ARM::FeatureV7Clrex]; |
| 30691 | case 20: |
| 30692 | return !FB[ARM::ModeThumb] && FB[ARM::HasV4TOps]; |
| 30693 | case 21: |
| 30694 | return !FB[ARM::ModeThumb] && FB[ARM::HasV5TOps]; |
| 30695 | case 22: |
| 30696 | return !FB[ARM::ModeThumb] && FB[ARM::FeatureTrustZone]; |
| 30697 | case 23: |
| 30698 | return !FB[ARM::ModeThumb] && FB[ARM::HasV6T2Ops]; |
| 30699 | case 24: |
| 30700 | return !FB[ARM::ModeThumb] && FB[ARM::HasV8_4aOps]; |
| 30701 | case 25: |
| 30702 | return !FB[ARM::ModeThumb] && FB[ARM::HasV7Ops]; |
| 30703 | case 26: |
| 30704 | return !FB[ARM::ModeThumb] && FB[ARM::HasV7Ops] && FB[ARM::FeatureMP]; |
| 30705 | case 27: |
| 30706 | return !FB[ARM::ModeThumb] && FB[ARM::HasV6KOps]; |
| 30707 | case 28: |
| 30708 | return !FB[ARM::ModeThumb] && FB[ARM::FeatureDB]; |
| 30709 | case 29: |
| 30710 | return !FB[ARM::ModeThumb] && FB[ARM::FeatureSB]; |
| 30711 | case 30: |
| 30712 | return !FB[ARM::ModeThumb] && FB[ARM::FeatureHWDivARM]; |
| 30713 | case 31: |
| 30714 | return FB[ARM::HasMVEIntegerOps]; |
| 30715 | case 32: |
| 30716 | return FB[ARM::HasV8_1MMainlineOps] && FB[ARM::HasMVEIntegerOps]; |
| 30717 | case 33: |
| 30718 | return FB[ARM::HasMVEFloatOps]; |
| 30719 | case 34: |
| 30720 | return FB[ARM::FeatureFPRegs] && FB[ARM::HasV8_1MMainlineOps]; |
| 30721 | case 35: |
| 30722 | return FB[ARM::FeatureNEON]; |
| 30723 | case 36: |
| 30724 | return FB[ARM::FeatureNEON] && FB[ARM::FeatureFullFP16]; |
| 30725 | case 37: |
| 30726 | return FB[ARM::FeatureNEON] && FB[ARM::HasV8_1aOps]; |
| 30727 | case 38: |
| 30728 | return FB[ARM::HasV8Ops] && FB[ARM::FeatureAES]; |
| 30729 | case 39: |
| 30730 | return FB[ARM::FeatureNEON] && FB[ARM::FeatureFP16]; |
| 30731 | case 40: |
| 30732 | return FB[ARM::FeatureBF16] && FB[ARM::FeatureNEON]; |
| 30733 | case 41: |
| 30734 | return FB[ARM::FeatureNEON] && FB[ARM::FeatureVFP4_D16_SP]; |
| 30735 | case 42: |
| 30736 | return FB[ARM::FeatureVFP2_SP]; |
| 30737 | case 43: |
| 30738 | return FB[ARM::FeatureFPRegs]; |
| 30739 | case 44: |
| 30740 | return FB[ARM::ModeThumb] && FB[ARM::HasV5TOps] && !FB[ARM::FeatureMClass]; |
| 30741 | case 45: |
| 30742 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && !FB[ARM::FeatureMClass]; |
| 30743 | case 46: |
| 30744 | return FB[ARM::HasV8_1MMainlineOps]; |
| 30745 | case 47: |
| 30746 | return FB[ARM::ModeThumb] && FB[ARM::FeatureAcquireRelease]; |
| 30747 | case 48: |
| 30748 | return FB[ARM::ModeThumb] && FB[ARM::FeatureAcquireRelease] && FB[ARM::FeatureV7Clrex]; |
| 30749 | case 49: |
| 30750 | return FB[ARM::ModeThumb] && FB[ARM::FeatureAcquireRelease] && FB[ARM::FeatureV7Clrex] && !FB[ARM::FeatureMClass]; |
| 30751 | case 50: |
| 30752 | return FB[ARM::FeatureDSP] && (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]); |
| 30753 | case 51: |
| 30754 | return FB[ARM::Feature8MSecExt]; |
| 30755 | case 52: |
| 30756 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::FeatureDSP]; |
| 30757 | case 53: |
| 30758 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::HasV8Ops]; |
| 30759 | case 54: |
| 30760 | return FB[ARM::ModeThumb] && FB[ARM::HasV8_4aOps]; |
| 30761 | case 55: |
| 30762 | return FB[ARM::ModeThumb] && FB[ARM::FeatureV7Clrex]; |
| 30763 | case 56: |
| 30764 | return FB[ARM::ModeThumb] && FB[ARM::FeatureDB]; |
| 30765 | case 57: |
| 30766 | return FB[ARM::HasV7Ops] && FB[ARM::FeatureMClass]; |
| 30767 | case 58: |
| 30768 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::FeatureSB]; |
| 30769 | case 59: |
| 30770 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::FeatureVirtualization]; |
| 30771 | case 60: |
| 30772 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::FeatureTrustZone]; |
| 30773 | case 61: |
| 30774 | return FB[ARM::ModeThumb] && FB[ARM::FeatureVirtualization]; |
| 30775 | case 62: |
| 30776 | return FB[ARM::ModeThumb] && FB[ARM::FeatureMClass]; |
| 30777 | case 63: |
| 30778 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::HasV8_1MMainlineOps] && FB[ARM::FeatureLOB]; |
| 30779 | case 64: |
| 30780 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::HasV7Ops]; |
| 30781 | case 65: |
| 30782 | return FB[ARM::FeatureHWDivThumb] && FB[ARM::ModeThumb] && FB[ARM::HasV8MBaselineOps]; |
| 30783 | case 66: |
| 30784 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::HasV7Ops] && FB[ARM::FeatureMP]; |
| 30785 | case 67: |
| 30786 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::FeatureCRC]; |
| 30787 | case 68: |
| 30788 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && FB[ARM::HasV8_1MMainlineOps] && FB[ARM::FeaturePACBTI]; |
| 30789 | case 69: |
| 30790 | return FB[ARM::HasCDEOps] && FB[ARM::FeatureFPRegs]; |
| 30791 | case 70: |
| 30792 | return FB[ARM::HasCDEOps] && FB[ARM::HasMVEIntegerOps]; |
| 30793 | case 71: |
| 30794 | return FB[ARM::HasCDEOps]; |
| 30795 | case 72: |
| 30796 | return (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) && !FB[ARM::HasV8Ops]; |
| 30797 | case 73: |
| 30798 | return !FB[ARM::HasV8Ops] && (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]); |
| 30799 | case 74: |
| 30800 | return FB[ARM::FeatureFPRegs16]; |
| 30801 | case 75: |
| 30802 | return FB[ARM::FeatureFullFP16]; |
| 30803 | case 76: |
| 30804 | return FB[ARM::HasV8_1MMainlineOps] && FB[ARM::Feature8MSecExt]; |
| 30805 | case 77: |
| 30806 | return FB[ARM::FeatureVFP4_D16_SP]; |
| 30807 | case 78: |
| 30808 | return FB[ARM::HasV8MMainlineOps] && FB[ARM::Feature8MSecExt]; |
| 30809 | case 79: |
| 30810 | return FB[ARM::HasV8_1MMainlineOps] && FB[ARM::FeatureFPRegs]; |
| 30811 | case 80: |
| 30812 | return FB[ARM::FeatureVFP3_D16_SP]; |
| 30813 | case 81: |
| 30814 | return FB[ARM::FeatureFP16]; |
| 30815 | case 82: |
| 30816 | return FB[ARM::FeatureFPARMv8_D16_SP]; |
| 30817 | case 83: |
| 30818 | return FB[ARM::FeatureVFP2_SP] && FB[ARM::FeatureFP64]; |
| 30819 | case 84: |
| 30820 | return FB[ARM::FeatureVFP4_D16_SP] && FB[ARM::FeatureFP64]; |
| 30821 | case 85: |
| 30822 | return FB[ARM::FeatureVFP3_D16_SP] && FB[ARM::FeatureFP64]; |
| 30823 | case 86: |
| 30824 | return FB[ARM::FeatureFPRegs64]; |
| 30825 | case 87: |
| 30826 | return FB[ARM::FeatureFPARMv8_D16_SP] && FB[ARM::FeatureFP64]; |
| 30827 | case 88: |
| 30828 | return FB[ARM::FeatureFPARMv8_D16_SP] && FB[ARM::HasV8_3aOps]; |
| 30829 | case 89: |
| 30830 | return FB[ARM::FeatureNEON] && FB[ARM::HasV8_3aOps] && FB[ARM::FeatureFullFP16]; |
| 30831 | case 90: |
| 30832 | return FB[ARM::FeatureNEON] && FB[ARM::HasV8_3aOps]; |
| 30833 | case 91: |
| 30834 | return FB[ARM::FeatureNEON] && FB[ARM::FeatureFP16FML]; |
| 30835 | case 92: |
| 30836 | return FB[ARM::FeatureBF16]; |
| 30837 | case 93: |
| 30838 | return FB[ARM::FeatureMatMulInt8]; |
| 30839 | case 94: |
| 30840 | return FB[ARM::FeatureDotProd]; |
| 30841 | case 95: |
| 30842 | return FB[ARM::HasV8Ops] && FB[ARM::FeatureSHA2]; |
| 30843 | case 96: |
| 30844 | return FB[ARM::HasV8Ops] && FB[ARM::FeatureNEON] && FB[ARM::FeatureFullFP16]; |
| 30845 | case 97: |
| 30846 | return FB[ARM::HasV8Ops] && FB[ARM::FeatureNEON]; |
| 30847 | case 98: |
| 30848 | return FB[ARM::FeatureFPARMv8_D16_SP] && FB[ARM::FeatureNEON]; |
| 30849 | case 99: |
| 30850 | return FB[ARM::FeatureFPARMv8_D16_SP] && FB[ARM::FeatureNEON] && FB[ARM::FeatureFullFP16]; |
| 30851 | } |
| 30852 | } |
| 30853 | |
| 30854 | |
| 30855 | template <typename InsnType> |
| 30856 | static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, |
| 30857 | InsnType insn, uint64_t Address, |
| 30858 | const MCDisassembler *DisAsm, |
| 30859 | const MCSubtargetInfo &STI) { |
| 30860 | const FeatureBitset &Bits = STI.getFeatureBits(); |
| 30861 | const uint8_t *Ptr = DecodeTable; |
| 30862 | |
| 30863 | SmallVector<const uint8_t *, 8> ScopeStack; |
| 30864 | DecodeStatus S = MCDisassembler::Success; |
| 30865 | while (true) { |
| 30866 | ptrdiff_t Loc = Ptr - DecodeTable; |
| 30867 | const uint8_t DecoderOp = *Ptr++; |
| 30868 | switch (DecoderOp) { |
| 30869 | default: |
| 30870 | errs() << Loc << ": Unexpected decode table opcode: " |
| 30871 | << (int)DecoderOp << '\n'; |
| 30872 | return MCDisassembler::Fail; |
| 30873 | case OPC_Scope: { |
| 30874 | unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30875 | const uint8_t *SkipTo = Ptr + NumToSkip; |
| 30876 | ScopeStack.push_back(Elt: SkipTo); |
| 30877 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope("<< SkipTo - DecodeTable |
| 30878 | << ")\n"); |
| 30879 | continue; |
| 30880 | } |
| 30881 | case OPC_SwitchField: { |
| 30882 | // Decode the start value. |
| 30883 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30884 | unsigned Len = *Ptr++; |
| 30885 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 30886 | uint64_t CaseValue; |
| 30887 | unsigned CaseSize; |
| 30888 | while (true) { |
| 30889 | CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30890 | CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30891 | if (FieldValue == CaseValue || !CaseSize) |
| 30892 | break; |
| 30893 | Ptr += CaseSize; |
| 30894 | } |
| 30895 | if (FieldValue == CaseValue) { |
| 30896 | LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField("<< Start << ", "<< Len |
| 30897 | << "): "<< FieldValue << '\n'); |
| 30898 | continue; |
| 30899 | } |
| 30900 | break; |
| 30901 | } |
| 30902 | case OPC_CheckField: { |
| 30903 | // Decode the start value. |
| 30904 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30905 | unsigned Len = *Ptr; |
| 30906 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 30907 | // Decode the field value. |
| 30908 | unsigned PtrLen = 0; |
| 30909 | uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen); |
| 30910 | Ptr += PtrLen; |
| 30911 | bool Failed = ExpectedValue != FieldValue; |
| 30912 | |
| 30913 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField("<< Start << ", "<< Len |
| 30914 | << ", "<< ExpectedValue << "): FieldValue = " |
| 30915 | << FieldValue << ", ExpectedValue = "<< ExpectedValue |
| 30916 | << ": "<< (Failed ? "FAIL, ": "PASS\n");); |
| 30917 | if (!Failed) |
| 30918 | continue; |
| 30919 | break; |
| 30920 | } |
| 30921 | case OPC_CheckPredicate: { |
| 30922 | // Decode the Predicate Index value. |
| 30923 | unsigned PIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30924 | // Check the predicate. |
| 30925 | bool Failed = !checkDecoderPredicate(Idx: PIdx, FB: Bits); |
| 30926 | |
| 30927 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate("<< PIdx << "): " |
| 30928 | << (Failed ? "FAIL, ": "PASS\n");); |
| 30929 | if (!Failed) |
| 30930 | continue; |
| 30931 | break; |
| 30932 | } |
| 30933 | case OPC_Decode: { |
| 30934 | // Decode the Opcode value. |
| 30935 | unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30936 | unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30937 | |
| 30938 | MI.clear(); |
| 30939 | MI.setOpcode(Opc); |
| 30940 | bool DecodeComplete; |
| 30941 | S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm, |
| 30942 | DecodeComplete); |
| 30943 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode "<< Opc |
| 30944 | << ", using decoder "<< DecodeIdx << ": " |
| 30945 | << (S ? "PASS, ": "FAIL, ")); |
| 30946 | |
| 30947 | if (DecodeComplete) { |
| 30948 | LLVM_DEBUG(dbgs() << "decoding complete\n"); |
| 30949 | return S; |
| 30950 | } |
| 30951 | assert(S == MCDisassembler::Fail); |
| 30952 | // Reset decode status. This also drops a SoftFail status that could be |
| 30953 | // set before the decode attempt. |
| 30954 | S = MCDisassembler::Success; |
| 30955 | break; |
| 30956 | } |
| 30957 | case OPC_SoftFail: { |
| 30958 | // Decode the mask values. |
| 30959 | uint64_t PositiveMask = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30960 | uint64_t NegativeMask = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 30961 | bool Failed = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; |
| 30962 | if (Failed) |
| 30963 | S = MCDisassembler::SoftFail; |
| 30964 | LLVM_DEBUG(dbgs() << Loc << ": OPC_SoftFail: "<< (Failed ? "FAIL\n": "PASS\n")); |
| 30965 | continue; |
| 30966 | } |
| 30967 | } |
| 30968 | if (ScopeStack.empty()) { |
| 30969 | LLVM_DEBUG(dbgs() << "returning Fail\n"); |
| 30970 | return MCDisassembler::Fail; |
| 30971 | } |
| 30972 | Ptr = ScopeStack.pop_back_val(); |
| 30973 | LLVM_DEBUG(dbgs() << "continuing at "<< Ptr - DecodeTable << '\n'); |
| 30974 | } |
| 30975 | llvm_unreachable("bogosity detected in disassembler state machine!"); |
| 30976 | } |
| 30977 | |
| 30978 | |
| 30979 | } // namespace |
| 30980 |
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