| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Target Instruction Enum Values and Descriptors *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_INSTRINFO_ENUM |
| 10 | #undef GET_INSTRINFO_ENUM |
| 11 | |
| 12 | namespace llvm::ARM { |
| 13 | |
| 14 | enum { |
| 15 | PHI = 0, // Target.td:1314 |
| 16 | INLINEASM = 1, // Target.td:1320 |
| 17 | INLINEASM_BR = 2, // Target.td:1326 |
| 18 | CFI_INSTRUCTION = 3, // Target.td:1335 |
| 19 | EH_LABEL = 4, // Target.td:1344 |
| 20 | GC_LABEL = 5, // Target.td:1353 |
| 21 | ANNOTATION_LABEL = 6, // Target.td:1362 |
| 22 | KILL = 7, // Target.td:1370 |
| 23 | EXTRACT_SUBREG = 8, // Target.td:1377 |
| 24 | INSERT_SUBREG = 9, // Target.td:1383 |
| 25 | IMPLICIT_DEF = 10, // Target.td:1390 |
| 26 | INIT_UNDEF = 11, // Target.td:1399 |
| 27 | SUBREG_TO_REG = 12, // Target.td:1406 |
| 28 | COPY_TO_REGCLASS = 13, // Target.td:1412 |
| 29 | DBG_VALUE = 14, // Target.td:1419 |
| 30 | DBG_VALUE_LIST = 15, // Target.td:1426 |
| 31 | DBG_INSTR_REF = 16, // Target.td:1433 |
| 32 | DBG_PHI = 17, // Target.td:1440 |
| 33 | DBG_LABEL = 18, // Target.td:1447 |
| 34 | REG_SEQUENCE = 19, // Target.td:1454 |
| 35 | COPY = 20, // Target.td:1461 |
| 36 | COPY_LANEMASK = 21, // Target.td:1469 |
| 37 | BUNDLE = 22, // Target.td:1476 |
| 38 | LIFETIME_START = 23, // Target.td:1482 |
| 39 | LIFETIME_END = 24, // Target.td:1489 |
| 40 | PSEUDO_PROBE = 25, // Target.td:1496 |
| 41 | ARITH_FENCE = 26, // Target.td:1503 |
| 42 | STACKMAP = 27, // Target.td:1512 |
| 43 | FENTRY_CALL = 28, // Target.td:1647 |
| 44 | PATCHPOINT = 29, // Target.td:1520 |
| 45 | LOAD_STACK_GUARD = 30, // Target.td:1538 |
| 46 | PREALLOCATED_SETUP = 31, // Target.td:1546 |
| 47 | PREALLOCATED_ARG = 32, // Target.td:1552 |
| 48 | STATEPOINT = 33, // Target.td:1529 |
| 49 | LOCAL_ESCAPE = 34, // Target.td:1558 |
| 50 | FAULTING_OP = 35, // Target.td:1567 |
| 51 | PATCHABLE_OP = 36, // Target.td:1587 |
| 52 | PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595 |
| 53 | PATCHABLE_RET = 38, // Target.td:1602 |
| 54 | PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611 |
| 55 | PATCHABLE_TAIL_CALL = 40, // Target.td:1619 |
| 56 | PATCHABLE_EVENT_CALL = 41, // Target.td:1627 |
| 57 | PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637 |
| 58 | ICALL_BRANCH_FUNNEL = 43, // Target.td:1657 |
| 59 | FAKE_USE = 44, // Target.td:1577 |
| 60 | MEMBARRIER = 45, // Target.td:1663 |
| 61 | JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671 |
| 62 | RELOC_NONE = 47, // Target.td:1679 |
| 63 | CONVERGENCECTRL_ENTRY = 48, // Target.td:1691 |
| 64 | CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687 |
| 65 | CONVERGENCECTRL_LOOP = 50, // Target.td:1695 |
| 66 | CONVERGENCECTRL_GLUE = 51, // Target.td:1699 |
| 67 | G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945 |
| 68 | G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937 |
| 69 | G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952 |
| 70 | G_ADD = 55, // GenericOpcodes.td:308 |
| 71 | G_SUB = 56, // GenericOpcodes.td:316 |
| 72 | G_MUL = 57, // GenericOpcodes.td:324 |
| 73 | G_SDIV = 58, // GenericOpcodes.td:332 |
| 74 | G_UDIV = 59, // GenericOpcodes.td:340 |
| 75 | G_SREM = 60, // GenericOpcodes.td:348 |
| 76 | G_UREM = 61, // GenericOpcodes.td:356 |
| 77 | G_SDIVREM = 62, // GenericOpcodes.td:364 |
| 78 | G_UDIVREM = 63, // GenericOpcodes.td:372 |
| 79 | G_AND = 64, // GenericOpcodes.td:380 |
| 80 | G_OR = 65, // GenericOpcodes.td:388 |
| 81 | G_XOR = 66, // GenericOpcodes.td:396 |
| 82 | G_ABDS = 67, // GenericOpcodes.td:425 |
| 83 | G_ABDU = 68, // GenericOpcodes.td:433 |
| 84 | G_UAVGFLOOR = 69, // GenericOpcodes.td:441 |
| 85 | G_UAVGCEIL = 70, // GenericOpcodes.td:448 |
| 86 | G_SAVGFLOOR = 71, // GenericOpcodes.td:455 |
| 87 | G_SAVGCEIL = 72, // GenericOpcodes.td:462 |
| 88 | G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111 |
| 89 | G_PHI = 74, // GenericOpcodes.td:118 |
| 90 | G_FRAME_INDEX = 75, // GenericOpcodes.td:125 |
| 91 | G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131 |
| 92 | G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137 |
| 93 | G_CONSTANT_POOL = 78, // GenericOpcodes.td:143 |
| 94 | G_EXTRACT = 79, // GenericOpcodes.td:1530 |
| 95 | G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543 |
| 96 | G_INSERT = 81, // GenericOpcodes.td:1552 |
| 97 | G_MERGE_VALUES = 82, // GenericOpcodes.td:1562 |
| 98 | G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582 |
| 99 | G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592 |
| 100 | G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599 |
| 101 | G_PTRTOINT = 86, // GenericOpcodes.td:155 |
| 102 | G_INTTOPTR = 87, // GenericOpcodes.td:149 |
| 103 | G_BITCAST = 88, // GenericOpcodes.td:161 |
| 104 | G_FREEZE = 89, // GenericOpcodes.td:284 |
| 105 | G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959 |
| 106 | G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288 |
| 107 | G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294 |
| 108 | G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300 |
| 109 | G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306 |
| 110 | G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312 |
| 111 | G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318 |
| 112 | G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324 |
| 113 | G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330 |
| 114 | G_LOAD = 99, // GenericOpcodes.td:1357 |
| 115 | G_SEXTLOAD = 100, // GenericOpcodes.td:1366 |
| 116 | G_ZEXTLOAD = 101, // GenericOpcodes.td:1374 |
| 117 | G_FPEXTLOAD = 102, // GenericOpcodes.td:1383 |
| 118 | G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393 |
| 119 | G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402 |
| 120 | G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410 |
| 121 | G_STORE = 106, // GenericOpcodes.td:1418 |
| 122 | G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428 |
| 123 | G_INDEXED_STORE = 108, // GenericOpcodes.td:1436 |
| 124 | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447 |
| 125 | G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458 |
| 126 | G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478 |
| 127 | G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479 |
| 128 | G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480 |
| 129 | G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481 |
| 130 | G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482 |
| 131 | G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483 |
| 132 | G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484 |
| 133 | G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485 |
| 134 | G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486 |
| 135 | G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487 |
| 136 | G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488 |
| 137 | G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499 |
| 138 | G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500 |
| 139 | G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501 |
| 140 | G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502 |
| 141 | G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503 |
| 142 | G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504 |
| 143 | G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505 |
| 144 | G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506 |
| 145 | G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489 |
| 146 | G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490 |
| 147 | G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491 |
| 148 | G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492 |
| 149 | G_FENCE = 134, // GenericOpcodes.td:1508 |
| 150 | G_PREFETCH = 135, // GenericOpcodes.td:1515 |
| 151 | G_BRCOND = 136, // GenericOpcodes.td:1655 |
| 152 | G_BRINDIRECT = 137, // GenericOpcodes.td:1664 |
| 153 | G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687 |
| 154 | G_INTRINSIC = 139, // GenericOpcodes.td:1607 |
| 155 | G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614 |
| 156 | G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623 |
| 157 | G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631 |
| 158 | G_ANYEXT = 143, // GenericOpcodes.td:44 |
| 159 | G_TRUNC = 144, // GenericOpcodes.td:83 |
| 160 | G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91 |
| 161 | G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98 |
| 162 | G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105 |
| 163 | G_CONSTANT = 148, // GenericOpcodes.td:169 |
| 164 | G_FCONSTANT = 149, // GenericOpcodes.td:177 |
| 165 | G_VASTART = 150, // GenericOpcodes.td:184 |
| 166 | G_VAARG = 151, // GenericOpcodes.td:191 |
| 167 | G_SEXT = 152, // GenericOpcodes.td:52 |
| 168 | G_SEXT_INREG = 153, // GenericOpcodes.td:66 |
| 169 | G_ZEXT = 154, // GenericOpcodes.td:74 |
| 170 | G_SHL = 155, // GenericOpcodes.td:404 |
| 171 | G_LSHR = 156, // GenericOpcodes.td:411 |
| 172 | G_ASHR = 157, // GenericOpcodes.td:418 |
| 173 | G_FSHL = 158, // GenericOpcodes.td:470 |
| 174 | G_FSHR = 159, // GenericOpcodes.td:478 |
| 175 | G_ROTR = 160, // GenericOpcodes.td:485 |
| 176 | G_ROTL = 161, // GenericOpcodes.td:492 |
| 177 | G_ICMP = 162, // GenericOpcodes.td:499 |
| 178 | G_FCMP = 163, // GenericOpcodes.td:506 |
| 179 | G_SCMP = 164, // GenericOpcodes.td:513 |
| 180 | G_UCMP = 165, // GenericOpcodes.td:520 |
| 181 | G_SELECT = 166, // GenericOpcodes.td:527 |
| 182 | G_UADDO = 167, // GenericOpcodes.td:609 |
| 183 | G_UADDE = 168, // GenericOpcodes.td:617 |
| 184 | G_USUBO = 169, // GenericOpcodes.td:639 |
| 185 | G_USUBE = 170, // GenericOpcodes.td:645 |
| 186 | G_SADDO = 171, // GenericOpcodes.td:624 |
| 187 | G_SADDE = 172, // GenericOpcodes.td:632 |
| 188 | G_SSUBO = 173, // GenericOpcodes.td:652 |
| 189 | G_SSUBE = 174, // GenericOpcodes.td:659 |
| 190 | G_UMULO = 175, // GenericOpcodes.td:666 |
| 191 | G_SMULO = 176, // GenericOpcodes.td:674 |
| 192 | G_UMULH = 177, // GenericOpcodes.td:683 |
| 193 | G_SMULH = 178, // GenericOpcodes.td:692 |
| 194 | G_UADDSAT = 179, // GenericOpcodes.td:704 |
| 195 | G_SADDSAT = 180, // GenericOpcodes.td:712 |
| 196 | G_USUBSAT = 181, // GenericOpcodes.td:720 |
| 197 | G_SSUBSAT = 182, // GenericOpcodes.td:728 |
| 198 | G_USHLSAT = 183, // GenericOpcodes.td:736 |
| 199 | G_SSHLSAT = 184, // GenericOpcodes.td:744 |
| 200 | G_SMULFIX = 185, // GenericOpcodes.td:756 |
| 201 | G_UMULFIX = 186, // GenericOpcodes.td:763 |
| 202 | G_SMULFIXSAT = 187, // GenericOpcodes.td:773 |
| 203 | G_UMULFIXSAT = 188, // GenericOpcodes.td:780 |
| 204 | G_SDIVFIX = 189, // GenericOpcodes.td:791 |
| 205 | G_UDIVFIX = 190, // GenericOpcodes.td:798 |
| 206 | G_SDIVFIXSAT = 191, // GenericOpcodes.td:808 |
| 207 | G_UDIVFIXSAT = 192, // GenericOpcodes.td:815 |
| 208 | G_FADD = 193, // GenericOpcodes.td:988 |
| 209 | G_FSUB = 194, // GenericOpcodes.td:996 |
| 210 | G_FMUL = 195, // GenericOpcodes.td:1004 |
| 211 | G_FMA = 196, // GenericOpcodes.td:1013 |
| 212 | G_FMAD = 197, // GenericOpcodes.td:1022 |
| 213 | G_FDIV = 198, // GenericOpcodes.td:1030 |
| 214 | G_FREM = 199, // GenericOpcodes.td:1037 |
| 215 | G_FMODF = 200, // GenericOpcodes.td:1044 |
| 216 | G_FPOW = 201, // GenericOpcodes.td:1051 |
| 217 | G_FPOWI = 202, // GenericOpcodes.td:1058 |
| 218 | G_FEXP = 203, // GenericOpcodes.td:1065 |
| 219 | G_FEXP2 = 204, // GenericOpcodes.td:1072 |
| 220 | G_FEXP10 = 205, // GenericOpcodes.td:1079 |
| 221 | G_FLOG = 206, // GenericOpcodes.td:1086 |
| 222 | G_FLOG2 = 207, // GenericOpcodes.td:1093 |
| 223 | G_FLOG10 = 208, // GenericOpcodes.td:1100 |
| 224 | G_FLDEXP = 209, // GenericOpcodes.td:1107 |
| 225 | G_FFREXP = 210, // GenericOpcodes.td:1114 |
| 226 | G_FNEG = 211, // GenericOpcodes.td:826 |
| 227 | G_FPEXT = 212, // GenericOpcodes.td:832 |
| 228 | G_FPTRUNC = 213, // GenericOpcodes.td:838 |
| 229 | G_FPTOSI = 214, // GenericOpcodes.td:844 |
| 230 | G_FPTOUI = 215, // GenericOpcodes.td:850 |
| 231 | G_SITOFP = 216, // GenericOpcodes.td:856 |
| 232 | G_UITOFP = 217, // GenericOpcodes.td:862 |
| 233 | G_FPTOSI_SAT = 218, // GenericOpcodes.td:868 |
| 234 | G_FPTOUI_SAT = 219, // GenericOpcodes.td:874 |
| 235 | G_FABS = 220, // GenericOpcodes.td:880 |
| 236 | G_FCOPYSIGN = 221, // GenericOpcodes.td:886 |
| 237 | G_IS_FPCLASS = 222, // GenericOpcodes.td:899 |
| 238 | G_FCANONICALIZE = 223, // GenericOpcodes.td:892 |
| 239 | G_FMINNUM = 224, // GenericOpcodes.td:912 |
| 240 | G_FMAXNUM = 225, // GenericOpcodes.td:919 |
| 241 | G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937 |
| 242 | G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944 |
| 243 | G_FMINIMUM = 228, // GenericOpcodes.td:954 |
| 244 | G_FMAXIMUM = 229, // GenericOpcodes.td:961 |
| 245 | G_FMINIMUMNUM = 230, // GenericOpcodes.td:969 |
| 246 | G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976 |
| 247 | G_GET_FPENV = 232, // GenericOpcodes.td:1244 |
| 248 | G_SET_FPENV = 233, // GenericOpcodes.td:1251 |
| 249 | G_RESET_FPENV = 234, // GenericOpcodes.td:1258 |
| 250 | G_GET_FPMODE = 235, // GenericOpcodes.td:1265 |
| 251 | G_SET_FPMODE = 236, // GenericOpcodes.td:1272 |
| 252 | G_RESET_FPMODE = 237, // GenericOpcodes.td:1279 |
| 253 | G_GET_ROUNDING = 238, // GenericOpcodes.td:1336 |
| 254 | G_SET_ROUNDING = 239, // GenericOpcodes.td:1342 |
| 255 | G_PTR_ADD = 240, // GenericOpcodes.td:534 |
| 256 | G_PTRMASK = 241, // GenericOpcodes.td:542 |
| 257 | G_SMIN = 242, // GenericOpcodes.td:549 |
| 258 | G_SMAX = 243, // GenericOpcodes.td:557 |
| 259 | G_UMIN = 244, // GenericOpcodes.td:565 |
| 260 | G_UMAX = 245, // GenericOpcodes.td:573 |
| 261 | G_ABS = 246, // GenericOpcodes.td:581 |
| 262 | G_LROUND = 247, // GenericOpcodes.td:291 |
| 263 | G_LLROUND = 248, // GenericOpcodes.td:297 |
| 264 | G_BR = 249, // GenericOpcodes.td:1645 |
| 265 | G_BRJT = 250, // GenericOpcodes.td:1675 |
| 266 | G_VSCALE = 251, // GenericOpcodes.td:1573 |
| 267 | G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719 |
| 268 | G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727 |
| 269 | G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735 |
| 270 | G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743 |
| 271 | G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754 |
| 272 | G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762 |
| 273 | G_STEP_VECTOR = 258, // GenericOpcodes.td:1770 |
| 274 | G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777 |
| 275 | G_CTTZ = 260, // GenericOpcodes.td:211 |
| 276 | G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217 |
| 277 | G_CTLZ = 262, // GenericOpcodes.td:199 |
| 278 | G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205 |
| 279 | G_CTLS = 264, // GenericOpcodes.td:223 |
| 280 | G_CTPOP = 265, // GenericOpcodes.td:229 |
| 281 | G_BSWAP = 266, // GenericOpcodes.td:235 |
| 282 | G_BITREVERSE = 267, // GenericOpcodes.td:242 |
| 283 | G_CLMUL = 268, // GenericOpcodes.td:588 |
| 284 | G_CLMULH = 269, // GenericOpcodes.td:596 |
| 285 | G_FCEIL = 270, // GenericOpcodes.td:1121 |
| 286 | G_FCOS = 271, // GenericOpcodes.td:1128 |
| 287 | G_FSIN = 272, // GenericOpcodes.td:1135 |
| 288 | G_FSINCOS = 273, // GenericOpcodes.td:1142 |
| 289 | G_FTAN = 274, // GenericOpcodes.td:1149 |
| 290 | G_FACOS = 275, // GenericOpcodes.td:1156 |
| 291 | G_FASIN = 276, // GenericOpcodes.td:1163 |
| 292 | G_FATAN = 277, // GenericOpcodes.td:1170 |
| 293 | G_FATAN2 = 278, // GenericOpcodes.td:1177 |
| 294 | G_FCOSH = 279, // GenericOpcodes.td:1184 |
| 295 | G_FSINH = 280, // GenericOpcodes.td:1191 |
| 296 | G_FTANH = 281, // GenericOpcodes.td:1198 |
| 297 | G_FSQRT = 282, // GenericOpcodes.td:1208 |
| 298 | G_FFLOOR = 283, // GenericOpcodes.td:1215 |
| 299 | G_FRINT = 284, // GenericOpcodes.td:1222 |
| 300 | G_FNEARBYINT = 285, // GenericOpcodes.td:1229 |
| 301 | G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248 |
| 302 | G_BLOCK_ADDR = 287, // GenericOpcodes.td:254 |
| 303 | G_JUMP_TABLE = 288, // GenericOpcodes.td:260 |
| 304 | G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266 |
| 305 | G_STACKSAVE = 290, // GenericOpcodes.td:272 |
| 306 | G_STACKRESTORE = 291, // GenericOpcodes.td:278 |
| 307 | G_STRICT_FADD = 292, // GenericOpcodes.td:1829 |
| 308 | G_STRICT_FSUB = 293, // GenericOpcodes.td:1830 |
| 309 | G_STRICT_FMUL = 294, // GenericOpcodes.td:1831 |
| 310 | G_STRICT_FDIV = 295, // GenericOpcodes.td:1832 |
| 311 | G_STRICT_FREM = 296, // GenericOpcodes.td:1833 |
| 312 | G_STRICT_FMA = 297, // GenericOpcodes.td:1834 |
| 313 | G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835 |
| 314 | G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836 |
| 315 | G_STRICT_FCMP = 300, // GenericOpcodes.td:1837 |
| 316 | G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838 |
| 317 | G_READ_REGISTER = 302, // GenericOpcodes.td:1694 |
| 318 | G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704 |
| 319 | G_MEMCPY = 304, // GenericOpcodes.td:1844 |
| 320 | G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852 |
| 321 | G_MEMMOVE = 306, // GenericOpcodes.td:1860 |
| 322 | G_MEMSET = 307, // GenericOpcodes.td:1868 |
| 323 | G_BZERO = 308, // GenericOpcodes.td:1875 |
| 324 | G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882 |
| 325 | G_TRAP = 310, // GenericOpcodes.td:1892 |
| 326 | G_DEBUGTRAP = 311, // GenericOpcodes.td:1899 |
| 327 | G_UBSANTRAP = 312, // GenericOpcodes.td:1905 |
| 328 | G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793 |
| 329 | G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799 |
| 330 | G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805 |
| 331 | G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806 |
| 332 | G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808 |
| 333 | G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809 |
| 334 | G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810 |
| 335 | G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811 |
| 336 | G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812 |
| 337 | G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813 |
| 338 | G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815 |
| 339 | G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816 |
| 340 | G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817 |
| 341 | G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818 |
| 342 | G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819 |
| 343 | G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820 |
| 344 | G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821 |
| 345 | G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822 |
| 346 | G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823 |
| 347 | G_SBFX = 332, // GenericOpcodes.td:1917 |
| 348 | G_UBFX = 333, // GenericOpcodes.td:1925 |
| 349 | ADDSri = 334, // ARMInstrInfo.td:1865 |
| 350 | ADDSrr = 335, // ARMInstrInfo.td:1870 |
| 351 | ADDSrsi = 336, // ARMInstrInfo.td:1876 |
| 352 | ADDSrsr = 337, // ARMInstrInfo.td:1883 |
| 353 | ADJCALLSTACKDOWN = 338, // ARMInstrInfo.td:2362 |
| 354 | ADJCALLSTACKUP = 339, // ARMInstrInfo.td:2358 |
| 355 | ASRi = 340, // ARMInstrInfo.td:6584 |
| 356 | ASRr = 341, // ARMInstrInfo.td:6600 |
| 357 | ASRs1 = 342, // ARMInstrInfo.td:3893 |
| 358 | B = 343, // ARMInstrInfo.td:2768 |
| 359 | BCCZi64 = 344, // ARMInstrInfo.td:5192 |
| 360 | BCCi64 = 345, // ARMInstrInfo.td:5186 |
| 361 | BLX_noip = 346, // ARMInstrInfo.td:2697 |
| 362 | BLX_pred_noip = 347, // ARMInstrInfo.td:2709 |
| 363 | BL_PUSHLR = 348, // ARMInstrInfo.td:2733 |
| 364 | BMOVPCB_CALL = 349, // ARMInstrInfo.td:2728 |
| 365 | BMOVPCRX_CALL = 350, // ARMInstrInfo.td:2722 |
| 366 | BR_JTadd = 351, // ARMInstrInfo.td:2789 |
| 367 | BR_JTm_i12 = 352, // ARMInstrInfo.td:2779 |
| 368 | BR_JTm_rs = 353, // ARMInstrInfo.td:2784 |
| 369 | BR_JTr = 354, // ARMInstrInfo.td:2774 |
| 370 | BX_CALL = 355, // ARMInstrInfo.td:2717 |
| 371 | CATCHRET = 356, // ARMInstrInfo.td:6771 |
| 372 | CLEANUPRET = 357, // ARMInstrInfo.td:6770 |
| 373 | CMP_SWAP_16 = 358, // ARMInstrInfo.td:6687 |
| 374 | CMP_SWAP_32 = 359, // ARMInstrInfo.td:6691 |
| 375 | CMP_SWAP_64 = 360, // ARMInstrInfo.td:6708 |
| 376 | CMP_SWAP_8 = 361, // ARMInstrInfo.td:6683 |
| 377 | CONSTPOOL_ENTRY = 362, // ARMInstrInfo.td:2324 |
| 378 | COPY_STRUCT_BYVAL_I32 = 363, // ARMInstrInfo.td:5351 |
| 379 | ITasm = 364, // ARMInstrInfo.td:6647 |
| 380 | Int_eh_sjlj_dispatchsetup = 365, // ARMInstrInfo.td:6154 |
| 381 | Int_eh_sjlj_longjmp = 366, // ARMInstrInfo.td:6139 |
| 382 | Int_eh_sjlj_setjmp = 367, // ARMInstrInfo.td:6119 |
| 383 | Int_eh_sjlj_setjmp_nofp = 368, // ARMInstrInfo.td:6129 |
| 384 | Int_eh_sjlj_setup_dispatch = 369, // ARMInstrInfo.td:6146 |
| 385 | JUMPTABLE_ADDRS = 370, // ARMInstrInfo.td:2331 |
| 386 | JUMPTABLE_INSTS = 371, // ARMInstrInfo.td:2337 |
| 387 | JUMPTABLE_TBB = 372, // ARMInstrInfo.td:2343 |
| 388 | JUMPTABLE_TBH = 373, // ARMInstrInfo.td:2349 |
| 389 | KCFI_CHECK_ARM = 374, // ARMInstrInfo.td:6722 |
| 390 | KCFI_CHECK_Thumb1 = 375, // ARMInstrInfo.td:6738 |
| 391 | KCFI_CHECK_Thumb2 = 376, // ARMInstrInfo.td:6730 |
| 392 | LDMIA_RET = 377, // ARMInstrInfo.td:3739 |
| 393 | LDRBT_POST = 378, // ARMInstrInfo.td:3290 |
| 394 | LDRConstPool = 379, // ARMInstrInfo.td:3295 |
| 395 | LDRHTii = 380, // ARMInstrInfo.td:3277 |
| 396 | LDRLIT_ga_abs = 381, // ARMInstrInfo.td:6185 |
| 397 | LDRLIT_ga_pcrel = 382, // ARMInstrInfo.td:6199 |
| 398 | LDRLIT_ga_pcrel_ldr = 383, // ARMInstrInfo.td:6206 |
| 399 | LDRSBTii = 384, // ARMInstrInfo.td:3277 |
| 400 | LDRSHTii = 385, // ARMInstrInfo.td:3277 |
| 401 | LDRT_POST = 386, // ARMInstrInfo.td:3286 |
| 402 | LEApcrel = 387, // ARMInstrInfo.td:2610 |
| 403 | LEApcrelJT = 388, // ARMInstrInfo.td:2613 |
| 404 | LOADDUAL = 389, // ARMInstrInfo.td:3031 |
| 405 | LSLi = 390, // ARMInstrInfo.td:6590 |
| 406 | LSLr = 391, // ARMInstrInfo.td:6606 |
| 407 | LSRi = 392, // ARMInstrInfo.td:6587 |
| 408 | LSRr = 393, // ARMInstrInfo.td:6603 |
| 409 | LSRs1 = 394, // ARMInstrInfo.td:3890 |
| 410 | MEMCPY = 395, // ARMInstrInfo.td:5362 |
| 411 | MLAv5 = 396, // ARMInstrInfo.td:4511 |
| 412 | MOVCCi = 397, // ARMInstrInfo.td:5227 |
| 413 | MOVCCi16 = 398, // ARMInstrInfo.td:5219 |
| 414 | MOVCCi32imm = 399, // ARMInstrInfo.td:5234 |
| 415 | MOVCCr = 400, // ARMInstrInfo.td:5203 |
| 416 | MOVCCsi = 401, // ARMInstrInfo.td:5208 |
| 417 | MOVCCsr = 402, // ARMInstrInfo.td:5212 |
| 418 | MOVPCRX = 403, // ARMInstrInfo.td:6163 |
| 419 | MOVTi16_ga_pcrel = 404, // ARMInstrInfo.td:3875 |
| 420 | MOV_ga_pcrel = 405, // ARMInstrInfo.td:6194 |
| 421 | MOV_ga_pcrel_ldr = 406, // ARMInstrInfo.td:6213 |
| 422 | MOVi16_ga_pcrel = 407, // ARMInstrInfo.td:3850 |
| 423 | MOVi32imm = 408, // ARMInstrInfo.td:6181 |
| 424 | MQPRCopy = 409, // ARMInstrMVE.td:7072 |
| 425 | MQQPRLoad = 410, // ARMInstrMVE.td:7058 |
| 426 | MQQPRStore = 411, // ARMInstrMVE.td:7052 |
| 427 | MQQQQPRLoad = 412, // ARMInstrMVE.td:7060 |
| 428 | MQQQQPRStore = 413, // ARMInstrMVE.td:7054 |
| 429 | MULv5 = 414, // ARMInstrInfo.td:4491 |
| 430 | MVE_MEMCPYLOOPINST = 415, // ARMInstrMVE.td:6986 |
| 431 | MVE_MEMSETLOOPINST = 416, // ARMInstrMVE.td:7001 |
| 432 | MVNCCi = 417, // ARMInstrInfo.td:5241 |
| 433 | PICADD = 418, // ARMInstrInfo.td:2548 |
| 434 | PICLDR = 419, // ARMInstrInfo.td:2554 |
| 435 | PICLDRB = 420, // ARMInstrInfo.td:2562 |
| 436 | PICLDRH = 421, // ARMInstrInfo.td:2558 |
| 437 | PICLDRSB = 422, // ARMInstrInfo.td:2570 |
| 438 | PICLDRSH = 423, // ARMInstrInfo.td:2566 |
| 439 | PICSTR = 424, // ARMInstrInfo.td:2575 |
| 440 | PICSTRB = 425, // ARMInstrInfo.td:2582 |
| 441 | PICSTRH = 426, // ARMInstrInfo.td:2578 |
| 442 | RORi = 427, // ARMInstrInfo.td:6593 |
| 443 | RORr = 428, // ARMInstrInfo.td:6609 |
| 444 | RRX = 429, // ARMInstrInfo.td:3885 |
| 445 | RRXi = 430, // ARMInstrInfo.td:6597 |
| 446 | RSBSri = 431, // ARMInstrInfo.td:1897 |
| 447 | RSBSrsi = 432, // ARMInstrInfo.td:1902 |
| 448 | RSBSrsr = 433, // ARMInstrInfo.td:1909 |
| 449 | SEH_EpilogEnd = 434, // ARMInstrInfo.td:6765 |
| 450 | SEH_EpilogStart = 435, // ARMInstrInfo.td:6763 |
| 451 | SEH_Nop = 436, // ARMInstrInfo.td:6759 |
| 452 | SEH_Nop_Ret = 437, // ARMInstrInfo.td:6761 |
| 453 | SEH_PrologEnd = 438, // ARMInstrInfo.td:6762 |
| 454 | SEH_SaveFRegs = 439, // ARMInstrInfo.td:6756 |
| 455 | SEH_SaveLR = 440, // ARMInstrInfo.td:6758 |
| 456 | SEH_SaveRegs = 441, // ARMInstrInfo.td:6752 |
| 457 | SEH_SaveRegs_Ret = 442, // ARMInstrInfo.td:6754 |
| 458 | SEH_SaveSP = 443, // ARMInstrInfo.td:6755 |
| 459 | SEH_StackAlloc = 444, // ARMInstrInfo.td:6751 |
| 460 | SMLALv5 = 445, // ARMInstrInfo.td:4604 |
| 461 | SMULLv5 = 446, // ARMInstrInfo.td:4554 |
| 462 | SPACE = 447, // ARMInstrInfo.td:6650 |
| 463 | STOREDUAL = 448, // ARMInstrInfo.td:3317 |
| 464 | STRBT_POST = 449, // ARMInstrInfo.td:3554 |
| 465 | STRBi_preidx = 450, // ARMInstrInfo.td:3430 |
| 466 | STRBr_preidx = 451, // ARMInstrInfo.td:3435 |
| 467 | STRH_preidx = 452, // ARMInstrInfo.td:3440 |
| 468 | STRT_POST = 453, // ARMInstrInfo.td:3594 |
| 469 | STRi_preidx = 454, // ARMInstrInfo.td:3420 |
| 470 | STRr_preidx = 455, // ARMInstrInfo.td:3425 |
| 471 | SUBS_PC_LR = 456, // ARMInstrInfo.td:2639 |
| 472 | SUBSri = 457, // ARMInstrInfo.td:1865 |
| 473 | SUBSrr = 458, // ARMInstrInfo.td:1870 |
| 474 | SUBSrsi = 459, // ARMInstrInfo.td:1876 |
| 475 | SUBSrsr = 460, // ARMInstrInfo.td:1883 |
| 476 | SpeculationBarrierISBDSBEndBB = 461, // ARMInstrInfo.td:6659 |
| 477 | SpeculationBarrierSBEndBB = 462, // ARMInstrInfo.td:6663 |
| 478 | TAILJMPd = 463, // ARMInstrInfo.td:2834 |
| 479 | TAILJMPr = 464, // ARMInstrInfo.td:2839 |
| 480 | TAILJMPr4 = 465, // ARMInstrInfo.td:6169 |
| 481 | TCRETURNdi = 466, // ARMInstrInfo.td:2825 |
| 482 | TCRETURNri = 467, // ARMInstrInfo.td:2828 |
| 483 | TCRETURNrinotr12 = 468, // ARMInstrInfo.td:2831 |
| 484 | TPsoft = 469, // ARMInstrInfo.td:6085 |
| 485 | UMLALv5 = 470, // ARMInstrInfo.td:4611 |
| 486 | UMULLv5 = 471, // ARMInstrInfo.td:4563 |
| 487 | VLD1LNdAsm_16 = 472, // ARMInstrNEON.td:8205 |
| 488 | VLD1LNdAsm_32 = 473, // ARMInstrNEON.td:8208 |
| 489 | VLD1LNdAsm_8 = 474, // ARMInstrNEON.td:8202 |
| 490 | VLD1LNdWB_fixed_Asm_16 = 475, // ARMInstrNEON.td:8216 |
| 491 | VLD1LNdWB_fixed_Asm_32 = 476, // ARMInstrNEON.td:8220 |
| 492 | VLD1LNdWB_fixed_Asm_8 = 477, // ARMInstrNEON.td:8212 |
| 493 | VLD1LNdWB_register_Asm_16 = 478, // ARMInstrNEON.td:8228 |
| 494 | VLD1LNdWB_register_Asm_32 = 479, // ARMInstrNEON.td:8232 |
| 495 | VLD1LNdWB_register_Asm_8 = 480, // ARMInstrNEON.td:8224 |
| 496 | VLD2LNdAsm_16 = 481, // ARMInstrNEON.td:8283 |
| 497 | VLD2LNdAsm_32 = 482, // ARMInstrNEON.td:8286 |
| 498 | VLD2LNdAsm_8 = 483, // ARMInstrNEON.td:8280 |
| 499 | VLD2LNdWB_fixed_Asm_16 = 484, // ARMInstrNEON.td:8299 |
| 500 | VLD2LNdWB_fixed_Asm_32 = 485, // ARMInstrNEON.td:8303 |
| 501 | VLD2LNdWB_fixed_Asm_8 = 486, // ARMInstrNEON.td:8295 |
| 502 | VLD2LNdWB_register_Asm_16 = 487, // ARMInstrNEON.td:8319 |
| 503 | VLD2LNdWB_register_Asm_32 = 488, // ARMInstrNEON.td:8323 |
| 504 | VLD2LNdWB_register_Asm_8 = 489, // ARMInstrNEON.td:8315 |
| 505 | VLD2LNqAsm_16 = 490, // ARMInstrNEON.td:8288 |
| 506 | VLD2LNqAsm_32 = 491, // ARMInstrNEON.td:8291 |
| 507 | VLD2LNqWB_fixed_Asm_16 = 492, // ARMInstrNEON.td:8307 |
| 508 | VLD2LNqWB_fixed_Asm_32 = 493, // ARMInstrNEON.td:8311 |
| 509 | VLD2LNqWB_register_Asm_16 = 494, // ARMInstrNEON.td:8327 |
| 510 | VLD2LNqWB_register_Asm_32 = 495, // ARMInstrNEON.td:8331 |
| 511 | VLD3DUPdAsm_16 = 496, // ARMInstrNEON.td:8404 |
| 512 | VLD3DUPdAsm_32 = 497, // ARMInstrNEON.td:8407 |
| 513 | VLD3DUPdAsm_8 = 498, // ARMInstrNEON.td:8401 |
| 514 | VLD3DUPdWB_fixed_Asm_16 = 499, // ARMInstrNEON.td:8424 |
| 515 | VLD3DUPdWB_fixed_Asm_32 = 500, // ARMInstrNEON.td:8428 |
| 516 | VLD3DUPdWB_fixed_Asm_8 = 501, // ARMInstrNEON.td:8420 |
| 517 | VLD3DUPdWB_register_Asm_16 = 502, // ARMInstrNEON.td:8448 |
| 518 | VLD3DUPdWB_register_Asm_32 = 503, // ARMInstrNEON.td:8452 |
| 519 | VLD3DUPdWB_register_Asm_8 = 504, // ARMInstrNEON.td:8444 |
| 520 | VLD3DUPqAsm_16 = 505, // ARMInstrNEON.td:8413 |
| 521 | VLD3DUPqAsm_32 = 506, // ARMInstrNEON.td:8416 |
| 522 | VLD3DUPqAsm_8 = 507, // ARMInstrNEON.td:8410 |
| 523 | VLD3DUPqWB_fixed_Asm_16 = 508, // ARMInstrNEON.td:8436 |
| 524 | VLD3DUPqWB_fixed_Asm_32 = 509, // ARMInstrNEON.td:8440 |
| 525 | VLD3DUPqWB_fixed_Asm_8 = 510, // ARMInstrNEON.td:8432 |
| 526 | VLD3DUPqWB_register_Asm_16 = 511, // ARMInstrNEON.td:8460 |
| 527 | VLD3DUPqWB_register_Asm_32 = 512, // ARMInstrNEON.td:8464 |
| 528 | VLD3DUPqWB_register_Asm_8 = 513, // ARMInstrNEON.td:8456 |
| 529 | VLD3LNdAsm_16 = 514, // ARMInstrNEON.td:8475 |
| 530 | VLD3LNdAsm_32 = 515, // ARMInstrNEON.td:8478 |
| 531 | VLD3LNdAsm_8 = 516, // ARMInstrNEON.td:8472 |
| 532 | VLD3LNdWB_fixed_Asm_16 = 517, // ARMInstrNEON.td:8492 |
| 533 | VLD3LNdWB_fixed_Asm_32 = 518, // ARMInstrNEON.td:8496 |
| 534 | VLD3LNdWB_fixed_Asm_8 = 519, // ARMInstrNEON.td:8488 |
| 535 | VLD3LNdWB_register_Asm_16 = 520, // ARMInstrNEON.td:8512 |
| 536 | VLD3LNdWB_register_Asm_32 = 521, // ARMInstrNEON.td:8516 |
| 537 | VLD3LNdWB_register_Asm_8 = 522, // ARMInstrNEON.td:8508 |
| 538 | VLD3LNqAsm_16 = 523, // ARMInstrNEON.td:8481 |
| 539 | VLD3LNqAsm_32 = 524, // ARMInstrNEON.td:8484 |
| 540 | VLD3LNqWB_fixed_Asm_16 = 525, // ARMInstrNEON.td:8500 |
| 541 | VLD3LNqWB_fixed_Asm_32 = 526, // ARMInstrNEON.td:8504 |
| 542 | VLD3LNqWB_register_Asm_16 = 527, // ARMInstrNEON.td:8520 |
| 543 | VLD3LNqWB_register_Asm_32 = 528, // ARMInstrNEON.td:8524 |
| 544 | VLD3dAsm_16 = 529, // ARMInstrNEON.td:8534 |
| 545 | VLD3dAsm_32 = 530, // ARMInstrNEON.td:8536 |
| 546 | VLD3dAsm_8 = 531, // ARMInstrNEON.td:8532 |
| 547 | VLD3dWB_fixed_Asm_16 = 532, // ARMInstrNEON.td:8548 |
| 548 | VLD3dWB_fixed_Asm_32 = 533, // ARMInstrNEON.td:8551 |
| 549 | VLD3dWB_fixed_Asm_8 = 534, // ARMInstrNEON.td:8545 |
| 550 | VLD3dWB_register_Asm_16 = 535, // ARMInstrNEON.td:8567 |
| 551 | VLD3dWB_register_Asm_32 = 536, // ARMInstrNEON.td:8571 |
| 552 | VLD3dWB_register_Asm_8 = 537, // ARMInstrNEON.td:8563 |
| 553 | VLD3qAsm_16 = 538, // ARMInstrNEON.td:8540 |
| 554 | VLD3qAsm_32 = 539, // ARMInstrNEON.td:8542 |
| 555 | VLD3qAsm_8 = 540, // ARMInstrNEON.td:8538 |
| 556 | VLD3qWB_fixed_Asm_16 = 541, // ARMInstrNEON.td:8557 |
| 557 | VLD3qWB_fixed_Asm_32 = 542, // ARMInstrNEON.td:8560 |
| 558 | VLD3qWB_fixed_Asm_8 = 543, // ARMInstrNEON.td:8554 |
| 559 | VLD3qWB_register_Asm_16 = 544, // ARMInstrNEON.td:8579 |
| 560 | VLD3qWB_register_Asm_32 = 545, // ARMInstrNEON.td:8583 |
| 561 | VLD3qWB_register_Asm_8 = 546, // ARMInstrNEON.td:8575 |
| 562 | VLD4DUPdAsm_16 = 547, // ARMInstrNEON.td:8716 |
| 563 | VLD4DUPdAsm_32 = 548, // ARMInstrNEON.td:8719 |
| 564 | VLD4DUPdAsm_8 = 549, // ARMInstrNEON.td:8713 |
| 565 | VLD4DUPdWB_fixed_Asm_16 = 550, // ARMInstrNEON.td:8736 |
| 566 | VLD4DUPdWB_fixed_Asm_32 = 551, // ARMInstrNEON.td:8740 |
| 567 | VLD4DUPdWB_fixed_Asm_8 = 552, // ARMInstrNEON.td:8732 |
| 568 | VLD4DUPdWB_register_Asm_16 = 553, // ARMInstrNEON.td:8760 |
| 569 | VLD4DUPdWB_register_Asm_32 = 554, // ARMInstrNEON.td:8764 |
| 570 | VLD4DUPdWB_register_Asm_8 = 555, // ARMInstrNEON.td:8756 |
| 571 | VLD4DUPqAsm_16 = 556, // ARMInstrNEON.td:8725 |
| 572 | VLD4DUPqAsm_32 = 557, // ARMInstrNEON.td:8728 |
| 573 | VLD4DUPqAsm_8 = 558, // ARMInstrNEON.td:8722 |
| 574 | VLD4DUPqWB_fixed_Asm_16 = 559, // ARMInstrNEON.td:8748 |
| 575 | VLD4DUPqWB_fixed_Asm_32 = 560, // ARMInstrNEON.td:8752 |
| 576 | VLD4DUPqWB_fixed_Asm_8 = 561, // ARMInstrNEON.td:8744 |
| 577 | VLD4DUPqWB_register_Asm_16 = 562, // ARMInstrNEON.td:8772 |
| 578 | VLD4DUPqWB_register_Asm_32 = 563, // ARMInstrNEON.td:8776 |
| 579 | VLD4DUPqWB_register_Asm_8 = 564, // ARMInstrNEON.td:8768 |
| 580 | VLD4LNdAsm_16 = 565, // ARMInstrNEON.td:8787 |
| 581 | VLD4LNdAsm_32 = 566, // ARMInstrNEON.td:8790 |
| 582 | VLD4LNdAsm_8 = 567, // ARMInstrNEON.td:8784 |
| 583 | VLD4LNdWB_fixed_Asm_16 = 568, // ARMInstrNEON.td:8804 |
| 584 | VLD4LNdWB_fixed_Asm_32 = 569, // ARMInstrNEON.td:8808 |
| 585 | VLD4LNdWB_fixed_Asm_8 = 570, // ARMInstrNEON.td:8800 |
| 586 | VLD4LNdWB_register_Asm_16 = 571, // ARMInstrNEON.td:8824 |
| 587 | VLD4LNdWB_register_Asm_32 = 572, // ARMInstrNEON.td:8828 |
| 588 | VLD4LNdWB_register_Asm_8 = 573, // ARMInstrNEON.td:8820 |
| 589 | VLD4LNqAsm_16 = 574, // ARMInstrNEON.td:8793 |
| 590 | VLD4LNqAsm_32 = 575, // ARMInstrNEON.td:8796 |
| 591 | VLD4LNqWB_fixed_Asm_16 = 576, // ARMInstrNEON.td:8812 |
| 592 | VLD4LNqWB_fixed_Asm_32 = 577, // ARMInstrNEON.td:8816 |
| 593 | VLD4LNqWB_register_Asm_16 = 578, // ARMInstrNEON.td:8832 |
| 594 | VLD4LNqWB_register_Asm_32 = 579, // ARMInstrNEON.td:8836 |
| 595 | VLD4dAsm_16 = 580, // ARMInstrNEON.td:8849 |
| 596 | VLD4dAsm_32 = 581, // ARMInstrNEON.td:8852 |
| 597 | VLD4dAsm_8 = 582, // ARMInstrNEON.td:8846 |
| 598 | VLD4dWB_fixed_Asm_16 = 583, // ARMInstrNEON.td:8869 |
| 599 | VLD4dWB_fixed_Asm_32 = 584, // ARMInstrNEON.td:8873 |
| 600 | VLD4dWB_fixed_Asm_8 = 585, // ARMInstrNEON.td:8865 |
| 601 | VLD4dWB_register_Asm_16 = 586, // ARMInstrNEON.td:8893 |
| 602 | VLD4dWB_register_Asm_32 = 587, // ARMInstrNEON.td:8897 |
| 603 | VLD4dWB_register_Asm_8 = 588, // ARMInstrNEON.td:8889 |
| 604 | VLD4qAsm_16 = 589, // ARMInstrNEON.td:8858 |
| 605 | VLD4qAsm_32 = 590, // ARMInstrNEON.td:8861 |
| 606 | VLD4qAsm_8 = 591, // ARMInstrNEON.td:8855 |
| 607 | VLD4qWB_fixed_Asm_16 = 592, // ARMInstrNEON.td:8881 |
| 608 | VLD4qWB_fixed_Asm_32 = 593, // ARMInstrNEON.td:8885 |
| 609 | VLD4qWB_fixed_Asm_8 = 594, // ARMInstrNEON.td:8877 |
| 610 | VLD4qWB_register_Asm_16 = 595, // ARMInstrNEON.td:8905 |
| 611 | VLD4qWB_register_Asm_32 = 596, // ARMInstrNEON.td:8909 |
| 612 | VLD4qWB_register_Asm_8 = 597, // ARMInstrNEON.td:8901 |
| 613 | VMOVD0 = 598, // ARMInstrNEON.td:6389 |
| 614 | VMOVDcc = 599, // ARMInstrVFP.td:2538 |
| 615 | VMOVHcc = 600, // ARMInstrVFP.td:2546 |
| 616 | VMOVQ0 = 601, // ARMInstrNEON.td:6393 |
| 617 | VMOVScc = 602, // ARMInstrVFP.td:2542 |
| 618 | VST1LNdAsm_16 = 603, // ARMInstrNEON.td:8244 |
| 619 | VST1LNdAsm_32 = 604, // ARMInstrNEON.td:8247 |
| 620 | VST1LNdAsm_8 = 605, // ARMInstrNEON.td:8241 |
| 621 | VST1LNdWB_fixed_Asm_16 = 606, // ARMInstrNEON.td:8255 |
| 622 | VST1LNdWB_fixed_Asm_32 = 607, // ARMInstrNEON.td:8259 |
| 623 | VST1LNdWB_fixed_Asm_8 = 608, // ARMInstrNEON.td:8251 |
| 624 | VST1LNdWB_register_Asm_16 = 609, // ARMInstrNEON.td:8267 |
| 625 | VST1LNdWB_register_Asm_32 = 610, // ARMInstrNEON.td:8271 |
| 626 | VST1LNdWB_register_Asm_8 = 611, // ARMInstrNEON.td:8263 |
| 627 | VST2LNdAsm_16 = 612, // ARMInstrNEON.td:8343 |
| 628 | VST2LNdAsm_32 = 613, // ARMInstrNEON.td:8346 |
| 629 | VST2LNdAsm_8 = 614, // ARMInstrNEON.td:8340 |
| 630 | VST2LNdWB_fixed_Asm_16 = 615, // ARMInstrNEON.td:8360 |
| 631 | VST2LNdWB_fixed_Asm_32 = 616, // ARMInstrNEON.td:8364 |
| 632 | VST2LNdWB_fixed_Asm_8 = 617, // ARMInstrNEON.td:8356 |
| 633 | VST2LNdWB_register_Asm_16 = 618, // ARMInstrNEON.td:8380 |
| 634 | VST2LNdWB_register_Asm_32 = 619, // ARMInstrNEON.td:8384 |
| 635 | VST2LNdWB_register_Asm_8 = 620, // ARMInstrNEON.td:8376 |
| 636 | VST2LNqAsm_16 = 621, // ARMInstrNEON.td:8349 |
| 637 | VST2LNqAsm_32 = 622, // ARMInstrNEON.td:8352 |
| 638 | VST2LNqWB_fixed_Asm_16 = 623, // ARMInstrNEON.td:8368 |
| 639 | VST2LNqWB_fixed_Asm_32 = 624, // ARMInstrNEON.td:8372 |
| 640 | VST2LNqWB_register_Asm_16 = 625, // ARMInstrNEON.td:8388 |
| 641 | VST2LNqWB_register_Asm_32 = 626, // ARMInstrNEON.td:8392 |
| 642 | VST3LNdAsm_16 = 627, // ARMInstrNEON.td:8595 |
| 643 | VST3LNdAsm_32 = 628, // ARMInstrNEON.td:8598 |
| 644 | VST3LNdAsm_8 = 629, // ARMInstrNEON.td:8592 |
| 645 | VST3LNdWB_fixed_Asm_16 = 630, // ARMInstrNEON.td:8612 |
| 646 | VST3LNdWB_fixed_Asm_32 = 631, // ARMInstrNEON.td:8616 |
| 647 | VST3LNdWB_fixed_Asm_8 = 632, // ARMInstrNEON.td:8608 |
| 648 | VST3LNdWB_register_Asm_16 = 633, // ARMInstrNEON.td:8632 |
| 649 | VST3LNdWB_register_Asm_32 = 634, // ARMInstrNEON.td:8636 |
| 650 | VST3LNdWB_register_Asm_8 = 635, // ARMInstrNEON.td:8628 |
| 651 | VST3LNqAsm_16 = 636, // ARMInstrNEON.td:8601 |
| 652 | VST3LNqAsm_32 = 637, // ARMInstrNEON.td:8604 |
| 653 | VST3LNqWB_fixed_Asm_16 = 638, // ARMInstrNEON.td:8620 |
| 654 | VST3LNqWB_fixed_Asm_32 = 639, // ARMInstrNEON.td:8624 |
| 655 | VST3LNqWB_register_Asm_16 = 640, // ARMInstrNEON.td:8640 |
| 656 | VST3LNqWB_register_Asm_32 = 641, // ARMInstrNEON.td:8644 |
| 657 | VST3dAsm_16 = 642, // ARMInstrNEON.td:8655 |
| 658 | VST3dAsm_32 = 643, // ARMInstrNEON.td:8657 |
| 659 | VST3dAsm_8 = 644, // ARMInstrNEON.td:8653 |
| 660 | VST3dWB_fixed_Asm_16 = 645, // ARMInstrNEON.td:8669 |
| 661 | VST3dWB_fixed_Asm_32 = 646, // ARMInstrNEON.td:8672 |
| 662 | VST3dWB_fixed_Asm_8 = 647, // ARMInstrNEON.td:8666 |
| 663 | VST3dWB_register_Asm_16 = 648, // ARMInstrNEON.td:8688 |
| 664 | VST3dWB_register_Asm_32 = 649, // ARMInstrNEON.td:8692 |
| 665 | VST3dWB_register_Asm_8 = 650, // ARMInstrNEON.td:8684 |
| 666 | VST3qAsm_16 = 651, // ARMInstrNEON.td:8661 |
| 667 | VST3qAsm_32 = 652, // ARMInstrNEON.td:8663 |
| 668 | VST3qAsm_8 = 653, // ARMInstrNEON.td:8659 |
| 669 | VST3qWB_fixed_Asm_16 = 654, // ARMInstrNEON.td:8678 |
| 670 | VST3qWB_fixed_Asm_32 = 655, // ARMInstrNEON.td:8681 |
| 671 | VST3qWB_fixed_Asm_8 = 656, // ARMInstrNEON.td:8675 |
| 672 | VST3qWB_register_Asm_16 = 657, // ARMInstrNEON.td:8700 |
| 673 | VST3qWB_register_Asm_32 = 658, // ARMInstrNEON.td:8704 |
| 674 | VST3qWB_register_Asm_8 = 659, // ARMInstrNEON.td:8696 |
| 675 | VST4LNdAsm_16 = 660, // ARMInstrNEON.td:8921 |
| 676 | VST4LNdAsm_32 = 661, // ARMInstrNEON.td:8924 |
| 677 | VST4LNdAsm_8 = 662, // ARMInstrNEON.td:8918 |
| 678 | VST4LNdWB_fixed_Asm_16 = 663, // ARMInstrNEON.td:8938 |
| 679 | VST4LNdWB_fixed_Asm_32 = 664, // ARMInstrNEON.td:8942 |
| 680 | VST4LNdWB_fixed_Asm_8 = 665, // ARMInstrNEON.td:8934 |
| 681 | VST4LNdWB_register_Asm_16 = 666, // ARMInstrNEON.td:8958 |
| 682 | VST4LNdWB_register_Asm_32 = 667, // ARMInstrNEON.td:8962 |
| 683 | VST4LNdWB_register_Asm_8 = 668, // ARMInstrNEON.td:8954 |
| 684 | VST4LNqAsm_16 = 669, // ARMInstrNEON.td:8927 |
| 685 | VST4LNqAsm_32 = 670, // ARMInstrNEON.td:8930 |
| 686 | VST4LNqWB_fixed_Asm_16 = 671, // ARMInstrNEON.td:8946 |
| 687 | VST4LNqWB_fixed_Asm_32 = 672, // ARMInstrNEON.td:8950 |
| 688 | VST4LNqWB_register_Asm_16 = 673, // ARMInstrNEON.td:8966 |
| 689 | VST4LNqWB_register_Asm_32 = 674, // ARMInstrNEON.td:8970 |
| 690 | VST4dAsm_16 = 675, // ARMInstrNEON.td:8982 |
| 691 | VST4dAsm_32 = 676, // ARMInstrNEON.td:8985 |
| 692 | VST4dAsm_8 = 677, // ARMInstrNEON.td:8979 |
| 693 | VST4dWB_fixed_Asm_16 = 678, // ARMInstrNEON.td:9002 |
| 694 | VST4dWB_fixed_Asm_32 = 679, // ARMInstrNEON.td:9006 |
| 695 | VST4dWB_fixed_Asm_8 = 680, // ARMInstrNEON.td:8998 |
| 696 | VST4dWB_register_Asm_16 = 681, // ARMInstrNEON.td:9026 |
| 697 | VST4dWB_register_Asm_32 = 682, // ARMInstrNEON.td:9030 |
| 698 | VST4dWB_register_Asm_8 = 683, // ARMInstrNEON.td:9022 |
| 699 | VST4qAsm_16 = 684, // ARMInstrNEON.td:8991 |
| 700 | VST4qAsm_32 = 685, // ARMInstrNEON.td:8994 |
| 701 | VST4qAsm_8 = 686, // ARMInstrNEON.td:8988 |
| 702 | VST4qWB_fixed_Asm_16 = 687, // ARMInstrNEON.td:9014 |
| 703 | VST4qWB_fixed_Asm_32 = 688, // ARMInstrNEON.td:9018 |
| 704 | VST4qWB_fixed_Asm_8 = 689, // ARMInstrNEON.td:9010 |
| 705 | VST4qWB_register_Asm_16 = 690, // ARMInstrNEON.td:9038 |
| 706 | VST4qWB_register_Asm_32 = 691, // ARMInstrNEON.td:9042 |
| 707 | VST4qWB_register_Asm_8 = 692, // ARMInstrNEON.td:9034 |
| 708 | WIN__CHKSTK = 693, // ARMInstrInfo.td:6064 |
| 709 | WIN__DBZCHK = 694, // ARMInstrInfo.td:6071 |
| 710 | t2ADDSri = 695, // ARMInstrThumb2.td:876 |
| 711 | t2ADDSrr = 696, // ARMInstrThumb2.td:883 |
| 712 | t2ADDSrs = 697, // ARMInstrThumb2.td:891 |
| 713 | t2BF_LabelPseudo = 698, // ARMInstrThumb2.td:5533 |
| 714 | t2BR_JT = 699, // ARMInstrThumb2.td:4006 |
| 715 | t2BXAUT_RET = 700, // ARMInstrThumb2.td:5902 |
| 716 | t2CALL_BTI = 701, // ARMInstrThumb2.td:5944 |
| 717 | t2DoLoopStart = 702, // ARMInstrThumb2.td:5689 |
| 718 | t2DoLoopStartTP = 703, // ARMInstrThumb2.td:5698 |
| 719 | t2LDMIA_RET = 704, // ARMInstrThumb2.td:3976 |
| 720 | t2LDRB_OFFSET_imm = 705, // ARMInstrThumb2.td:1609 |
| 721 | t2LDRB_POST_imm = 706, // ARMInstrThumb2.td:1613 |
| 722 | t2LDRB_PRE_imm = 707, // ARMInstrThumb2.td:1611 |
| 723 | t2LDRBpcrel = 708, // ARMInstrThumb2.td:5468 |
| 724 | t2LDRConstPool = 709, // ARMInstrThumb2.td:5492 |
| 725 | t2LDRH_OFFSET_imm = 710, // ARMInstrThumb2.td:1619 |
| 726 | t2LDRH_POST_imm = 711, // ARMInstrThumb2.td:1623 |
| 727 | t2LDRH_PRE_imm = 712, // ARMInstrThumb2.td:1621 |
| 728 | t2LDRHpcrel = 713, // ARMInstrThumb2.td:5470 |
| 729 | t2LDRLIT_ga_pcrel = 714, // ARMInstrThumb2.td:4398 |
| 730 | t2LDRSB_OFFSET_imm = 715, // ARMInstrThumb2.td:1629 |
| 731 | t2LDRSB_POST_imm = 716, // ARMInstrThumb2.td:1633 |
| 732 | t2LDRSB_PRE_imm = 717, // ARMInstrThumb2.td:1631 |
| 733 | t2LDRSBpcrel = 718, // ARMInstrThumb2.td:5472 |
| 734 | t2LDRSH_OFFSET_imm = 719, // ARMInstrThumb2.td:1639 |
| 735 | t2LDRSH_POST_imm = 720, // ARMInstrThumb2.td:1643 |
| 736 | t2LDRSH_PRE_imm = 721, // ARMInstrThumb2.td:1641 |
| 737 | t2LDRSHpcrel = 722, // ARMInstrThumb2.td:5474 |
| 738 | t2LDR_POST_imm = 723, // ARMInstrThumb2.td:1603 |
| 739 | t2LDR_PRE_imm = 724, // ARMInstrThumb2.td:1601 |
| 740 | t2LDRpci_pic = 725, // ARMInstrThumb2.td:4417 |
| 741 | t2LDRpcrel = 726, // ARMInstrThumb2.td:5466 |
| 742 | t2LEApcrel = 727, // ARMInstrThumb2.td:1451 |
| 743 | t2LEApcrelJT = 728, // ARMInstrThumb2.td:1454 |
| 744 | t2LoopDec = 729, // ARMInstrThumb2.td:5715 |
| 745 | t2LoopEnd = 730, // ARMInstrThumb2.td:5748 |
| 746 | t2LoopEndDec = 731, // ARMInstrThumb2.td:5757 |
| 747 | t2MOVCCasr = 732, // ARMInstrThumb2.td:3609 |
| 748 | t2MOVCCi = 733, // ARMInstrThumb2.td:3580 |
| 749 | t2MOVCCi16 = 734, // ARMInstrThumb2.td:3588 |
| 750 | t2MOVCCi32imm = 735, // ARMInstrThumb2.td:3613 |
| 751 | t2MOVCClsl = 736, // ARMInstrThumb2.td:3607 |
| 752 | t2MOVCClsr = 737, // ARMInstrThumb2.td:3608 |
| 753 | t2MOVCCr = 738, // ARMInstrThumb2.td:3574 |
| 754 | t2MOVCCror = 739, // ARMInstrThumb2.td:3610 |
| 755 | t2MOVSsi = 740, // ARMInstrThumb2.td:5442 |
| 756 | t2MOVSsr = 741, // ARMInstrThumb2.td:5447 |
| 757 | t2MOVTi16_ga_pcrel = 742, // ARMInstrThumb2.td:2328 |
| 758 | t2MOV_ga_pcrel = 743, // ARMInstrThumb2.td:4374 |
| 759 | t2MOVi16_ga_pcrel = 744, // ARMInstrThumb2.td:2297 |
| 760 | t2MOVi32imm = 745, // ARMInstrThumb2.td:4365 |
| 761 | t2MOVsi = 746, // ARMInstrThumb2.td:5440 |
| 762 | t2MOVsr = 747, // ARMInstrThumb2.td:5445 |
| 763 | t2MVNCCi = 748, // ARMInstrThumb2.td:3595 |
| 764 | t2RSBSri = 749, // ARMInstrThumb2.td:905 |
| 765 | t2RSBSrs = 750, // ARMInstrThumb2.td:912 |
| 766 | t2STRB_OFFSET_imm = 751, // ARMInstrThumb2.td:1817 |
| 767 | t2STRB_POST_imm = 752, // ARMInstrThumb2.td:1821 |
| 768 | t2STRB_PRE_imm = 753, // ARMInstrThumb2.td:1819 |
| 769 | t2STRB_preidx = 754, // ARMInstrThumb2.td:1789 |
| 770 | t2STRH_OFFSET_imm = 755, // ARMInstrThumb2.td:1827 |
| 771 | t2STRH_POST_imm = 756, // ARMInstrThumb2.td:1831 |
| 772 | t2STRH_PRE_imm = 757, // ARMInstrThumb2.td:1829 |
| 773 | t2STRH_preidx = 758, // ARMInstrThumb2.td:1795 |
| 774 | t2STR_POST_imm = 759, // ARMInstrThumb2.td:1811 |
| 775 | t2STR_PRE_imm = 760, // ARMInstrThumb2.td:1809 |
| 776 | t2STR_preidx = 761, // ARMInstrThumb2.td:1783 |
| 777 | t2SUBSri = 762, // ARMInstrThumb2.td:876 |
| 778 | t2SUBSrr = 763, // ARMInstrThumb2.td:883 |
| 779 | t2SUBSrs = 764, // ARMInstrThumb2.td:891 |
| 780 | t2SpeculationBarrierISBDSBEndBB = 765, // ARMInstrThumb2.td:5158 |
| 781 | t2SpeculationBarrierSBEndBB = 766, // ARMInstrThumb2.td:5162 |
| 782 | t2TBB_JT = 767, // ARMInstrThumb2.td:4013 |
| 783 | t2TBH_JT = 768, // ARMInstrThumb2.td:4017 |
| 784 | t2WhileLoopSetup = 769, // ARMInstrThumb2.td:5707 |
| 785 | t2WhileLoopStart = 770, // ARMInstrThumb2.td:5723 |
| 786 | t2WhileLoopStartLR = 771, // ARMInstrThumb2.td:5733 |
| 787 | t2WhileLoopStartTP = 772, // ARMInstrThumb2.td:5741 |
| 788 | tADCS = 773, // ARMInstrThumb.td:1020 |
| 789 | tADDSi3 = 774, // ARMInstrThumb.td:1027 |
| 790 | tADDSi8 = 775, // ARMInstrThumb.td:1034 |
| 791 | tADDSrr = 776, // ARMInstrThumb.td:1042 |
| 792 | tADDframe = 777, // ARMInstrThumb.td:414 |
| 793 | tADJCALLSTACKDOWN = 778, // ARMInstrThumb.td:310 |
| 794 | tADJCALLSTACKUP = 779, // ARMInstrThumb.td:305 |
| 795 | tBLXNS_CALL = 780, // ARMInstrThumb.td:583 |
| 796 | tBLXr_noip = 781, // ARMInstrThumb.td:565 |
| 797 | tBL_PUSHLR = 782, // ARMInstrThumb.td:595 |
| 798 | tBRIND = 783, // ARMInstrThumb.td:1775 |
| 799 | tBR_JTr = 784, // ARMInstrThumb.td:625 |
| 800 | tBXNS_RET = 785, // ARMInstrThumb.td:511 |
| 801 | tBX_CALL = 786, // ARMInstrThumb.td:588 |
| 802 | tBX_RET = 787, // ARMInstrThumb.td:507 |
| 803 | tBX_RET_vararg = 788, // ARMInstrThumb.td:515 |
| 804 | tBfar = 789, // ARMInstrThumb.td:620 |
| 805 | tCMP_SWAP_16 = 790, // ARMInstrThumb.td:1819 |
| 806 | tCMP_SWAP_32 = 791, // ARMInstrThumb.td:1823 |
| 807 | tCMP_SWAP_8 = 792, // ARMInstrThumb.td:1815 |
| 808 | tLDMIA_UPD = 793, // ARMInstrThumb.td:847 |
| 809 | tLDRConstPool = 794, // ARMInstrThumb.td:1802 |
| 810 | tLDRLIT_ga_abs = 795, // ARMInstrThumb.td:1612 |
| 811 | tLDRLIT_ga_pcrel = 796, // ARMInstrThumb.td:1604 |
| 812 | tLDR_postidx = 797, // ARMInstrThumb.td:1684 |
| 813 | tLDRpci_pic = 798, // ARMInstrThumb.td:1759 |
| 814 | tLEApcrel = 799, // ARMInstrThumb.td:1496 |
| 815 | tLEApcrelJT = 800, // ARMInstrThumb.td:1500 |
| 816 | tLSLSri = 801, // ARMInstrThumb.td:1402 |
| 817 | tMOVCCr_pseudo = 802, // ARMInstrThumb.td:1474 |
| 818 | tMOVi32imm = 803, // ARMInstrThumb.td:1625 |
| 819 | tPOP_RET = 804, // ARMInstrThumb.td:1769 |
| 820 | tRSBS = 805, // ARMInstrThumb.td:1396 |
| 821 | tSBCS = 806, // ARMInstrThumb.td:1368 |
| 822 | tSUBSi3 = 807, // ARMInstrThumb.td:1375 |
| 823 | tSUBSi8 = 808, // ARMInstrThumb.td:1382 |
| 824 | tSUBSrr = 809, // ARMInstrThumb.td:1389 |
| 825 | tTAILJMPd = 810, // ARMInstrThumb2.td:4082 |
| 826 | tTAILJMPdND = 811, // ARMInstrThumb.td:664 |
| 827 | tTAILJMPr = 812, // ARMInstrThumb.td:655 |
| 828 | tTBB_JT = 813, // ARMInstrThumb.td:1508 |
| 829 | tTBH_JT = 814, // ARMInstrThumb.td:1512 |
| 830 | tTPsoft = 815, // ARMInstrThumb.td:1525 |
| 831 | ADCri = 816, // ARMInstrInfo.td:2057 |
| 832 | ADCrr = 817, // ARMInstrInfo.td:2070 |
| 833 | ADCrsi = 818, // ARMInstrInfo.td:2085 |
| 834 | ADCrsr = 819, // ARMInstrInfo.td:2101 |
| 835 | ADDri = 820, // ARMInstrInfo.td:1721 |
| 836 | ADDrr = 821, // ARMInstrInfo.td:1734 |
| 837 | ADDrsi = 822, // ARMInstrInfo.td:1749 |
| 838 | ADDrsr = 823, // ARMInstrInfo.td:1765 |
| 839 | ADR = 824, // ARMInstrInfo.td:2594 |
| 840 | AESD = 825, // ARMInstrNEON.td:7394 |
| 841 | AESE = 826, // ARMInstrNEON.td:7395 |
| 842 | AESIMC = 827, // ARMInstrNEON.td:7397 |
| 843 | AESMC = 828, // ARMInstrNEON.td:7398 |
| 844 | ANDri = 829, // ARMInstrInfo.td:1721 |
| 845 | ANDrr = 830, // ARMInstrInfo.td:1734 |
| 846 | ANDrsi = 831, // ARMInstrInfo.td:1749 |
| 847 | ANDrsr = 832, // ARMInstrInfo.td:1765 |
| 848 | BF16VDOTI_VDOTD = 833, // ARMInstrNEON.td:9239 |
| 849 | BF16VDOTI_VDOTQ = 834, // ARMInstrNEON.td:9239 |
| 850 | BF16VDOTS_VDOTD = 835, // ARMInstrNEON.td:9259 |
| 851 | BF16VDOTS_VDOTQ = 836, // ARMInstrNEON.td:9260 |
| 852 | BF16_VCVT = 837, // ARMInstrNEON.td:9323 |
| 853 | BF16_VCVTB = 838, // ARMInstrVFP.td:2103 |
| 854 | BF16_VCVTT = 839, // ARMInstrVFP.td:2104 |
| 855 | BFC = 840, // ARMInstrInfo.td:4345 |
| 856 | BFI = 841, // ARMInstrInfo.td:4360 |
| 857 | BICri = 842, // ARMInstrInfo.td:1721 |
| 858 | BICrr = 843, // ARMInstrInfo.td:1734 |
| 859 | BICrsi = 844, // ARMInstrInfo.td:1749 |
| 860 | BICrsr = 845, // ARMInstrInfo.td:1765 |
| 861 | BKPT = 846, // ARMInstrInfo.td:2408 |
| 862 | BL = 847, // ARMInstrInfo.td:2671 |
| 863 | BLX = 848, // ARMInstrInfo.td:2691 |
| 864 | BLX_pred = 849, // ARMInstrInfo.td:2702 |
| 865 | BLXi = 850, // ARMInstrInfo.td:2800 |
| 866 | BL_pred = 851, // ARMInstrInfo.td:2681 |
| 867 | BX = 852, // ARMInstrInfo.td:2647 |
| 868 | BXJ = 853, // ARMInstrInfo.td:2811 |
| 869 | BX_RET = 854, // ARMInstrInfo.td:2624 |
| 870 | BX_pred = 855, // ARMInstrInfo.td:2655 |
| 871 | Bcc = 856, // ARMInstrInfo.td:2752 |
| 872 | CDE_CX1 = 857, // ARMInstrCDE.td:206 |
| 873 | CDE_CX1A = 858, // ARMInstrCDE.td:207 |
| 874 | CDE_CX1D = 859, // ARMInstrCDE.td:208 |
| 875 | CDE_CX1DA = 860, // ARMInstrCDE.td:209 |
| 876 | CDE_CX2 = 861, // ARMInstrCDE.td:211 |
| 877 | CDE_CX2A = 862, // ARMInstrCDE.td:212 |
| 878 | CDE_CX2D = 863, // ARMInstrCDE.td:213 |
| 879 | CDE_CX2DA = 864, // ARMInstrCDE.td:214 |
| 880 | CDE_CX3 = 865, // ARMInstrCDE.td:216 |
| 881 | CDE_CX3A = 866, // ARMInstrCDE.td:217 |
| 882 | CDE_CX3D = 867, // ARMInstrCDE.td:218 |
| 883 | CDE_CX3DA = 868, // ARMInstrCDE.td:219 |
| 884 | CDE_VCX1A_fpdp = 869, // ARMInstrCDE.td:532 |
| 885 | CDE_VCX1A_fpsp = 870, // ARMInstrCDE.td:530 |
| 886 | CDE_VCX1A_vec = 871, // ARMInstrCDE.td:534 |
| 887 | CDE_VCX1_fpdp = 872, // ARMInstrCDE.td:531 |
| 888 | CDE_VCX1_fpsp = 873, // ARMInstrCDE.td:529 |
| 889 | CDE_VCX1_vec = 874, // ARMInstrCDE.td:533 |
| 890 | CDE_VCX2A_fpdp = 875, // ARMInstrCDE.td:539 |
| 891 | CDE_VCX2A_fpsp = 876, // ARMInstrCDE.td:537 |
| 892 | CDE_VCX2A_vec = 877, // ARMInstrCDE.td:541 |
| 893 | CDE_VCX2_fpdp = 878, // ARMInstrCDE.td:538 |
| 894 | CDE_VCX2_fpsp = 879, // ARMInstrCDE.td:536 |
| 895 | CDE_VCX2_vec = 880, // ARMInstrCDE.td:540 |
| 896 | CDE_VCX3A_fpdp = 881, // ARMInstrCDE.td:546 |
| 897 | CDE_VCX3A_fpsp = 882, // ARMInstrCDE.td:544 |
| 898 | CDE_VCX3A_vec = 883, // ARMInstrCDE.td:548 |
| 899 | CDE_VCX3_fpdp = 884, // ARMInstrCDE.td:545 |
| 900 | CDE_VCX3_fpsp = 885, // ARMInstrCDE.td:543 |
| 901 | CDE_VCX3_vec = 886, // ARMInstrCDE.td:547 |
| 902 | CDP = 887, // ARMInstrInfo.td:5555 |
| 903 | CDP2 = 888, // ARMInstrInfo.td:5579 |
| 904 | CLREX = 889, // ARMInstrInfo.td:5495 |
| 905 | CLZ = 890, // ARMInstrInfo.td:4915 |
| 906 | CMNri = 891, // ARMInstrInfo.td:5085 |
| 907 | CMNrr = 892, // ARMInstrInfo.td:5101 |
| 908 | CMNrsi = 893, // ARMInstrInfo.td:5118 |
| 909 | CMNrsr = 894, // ARMInstrInfo.td:5136 |
| 910 | CMPri = 895, // ARMInstrInfo.td:1926 |
| 911 | CMPrr = 896, // ARMInstrInfo.td:1940 |
| 912 | CMPrsi = 897, // ARMInstrInfo.td:1957 |
| 913 | CMPrsr = 898, // ARMInstrInfo.td:1974 |
| 914 | CPS1p = 899, // ARMInstrInfo.td:2458 |
| 915 | CPS2p = 900, // ARMInstrInfo.td:2455 |
| 916 | CPS3p = 901, // ARMInstrInfo.td:2452 |
| 917 | CRC32B = 902, // ARMInstrInfo.td:5028 |
| 918 | CRC32CB = 903, // ARMInstrInfo.td:5029 |
| 919 | CRC32CH = 904, // ARMInstrInfo.td:5031 |
| 920 | CRC32CW = 905, // ARMInstrInfo.td:5033 |
| 921 | CRC32H = 906, // ARMInstrInfo.td:5030 |
| 922 | CRC32W = 907, // ARMInstrInfo.td:5032 |
| 923 | DBG = 908, // ARMInstrInfo.td:2511 |
| 924 | DMB = 909, // ARMInstrInfo.td:5308 |
| 925 | DSB = 910, // ARMInstrInfo.td:5316 |
| 926 | EORri = 911, // ARMInstrInfo.td:1721 |
| 927 | EORrr = 912, // ARMInstrInfo.td:1734 |
| 928 | EORrsi = 913, // ARMInstrInfo.td:1749 |
| 929 | EORrsr = 914, // ARMInstrInfo.td:1765 |
| 930 | ERET = 915, // ARMInstrInfo.td:2976 |
| 931 | FCONSTD = 916, // ARMInstrVFP.td:2733 |
| 932 | FCONSTH = 917, // ARMInstrVFP.td:2770 |
| 933 | FCONSTS = 918, // ARMInstrVFP.td:2752 |
| 934 | FLDMXDB_UPD = 919, // ARMInstrVFP.td:431 |
| 935 | FLDMXIA = 920, // ARMInstrVFP.td:417 |
| 936 | FLDMXIA_UPD = 921, // ARMInstrVFP.td:424 |
| 937 | FMSTAT = 922, // ARMInstrVFP.td:2598 |
| 938 | FSTMXDB_UPD = 923, // ARMInstrVFP.td:431 |
| 939 | FSTMXIA = 924, // ARMInstrVFP.td:417 |
| 940 | FSTMXIA_UPD = 925, // ARMInstrVFP.td:424 |
| 941 | HINT = 926, // ARMInstrInfo.td:2367 |
| 942 | HLT = 927, // ARMInstrInfo.td:2420 |
| 943 | HVC = 928, // ARMInstrInfo.td:2956 |
| 944 | ISB = 929, // ARMInstrInfo.td:5325 |
| 945 | LDA = 930, // ARMInstrInfo.td:3038 |
| 946 | LDAB = 931, // ARMInstrInfo.td:3040 |
| 947 | LDAEX = 932, // ARMInstrInfo.td:5446 |
| 948 | LDAEXB = 933, // ARMInstrInfo.td:5440 |
| 949 | LDAEXD = 934, // ARMInstrInfo.td:5450 |
| 950 | LDAEXH = 935, // ARMInstrInfo.td:5443 |
| 951 | LDAH = 936, // ARMInstrInfo.td:3042 |
| 952 | LDC2L_OFFSET = 937, // ARMInstrInfo.td:5694 |
| 953 | LDC2L_OPTION = 938, // ARMInstrInfo.td:5745 |
| 954 | LDC2L_POST = 939, // ARMInstrInfo.td:5727 |
| 955 | LDC2L_PRE = 940, // ARMInstrInfo.td:5711 |
| 956 | LDC2_OFFSET = 941, // ARMInstrInfo.td:5694 |
| 957 | LDC2_OPTION = 942, // ARMInstrInfo.td:5745 |
| 958 | LDC2_POST = 943, // ARMInstrInfo.td:5727 |
| 959 | LDC2_PRE = 944, // ARMInstrInfo.td:5711 |
| 960 | LDCL_OFFSET = 945, // ARMInstrInfo.td:5622 |
| 961 | LDCL_OPTION = 946, // ARMInstrInfo.td:5673 |
| 962 | LDCL_POST = 947, // ARMInstrInfo.td:5655 |
| 963 | LDCL_PRE = 948, // ARMInstrInfo.td:5639 |
| 964 | LDC_OFFSET = 949, // ARMInstrInfo.td:5622 |
| 965 | LDC_OPTION = 950, // ARMInstrInfo.td:5673 |
| 966 | LDC_POST = 951, // ARMInstrInfo.td:5655 |
| 967 | LDC_PRE = 952, // ARMInstrInfo.td:5639 |
| 968 | LDMDA = 953, // ARMInstrInfo.td:3660 |
| 969 | LDMDA_UPD = 954, // ARMInstrInfo.td:3669 |
| 970 | LDMDB = 955, // ARMInstrInfo.td:3680 |
| 971 | LDMDB_UPD = 956, // ARMInstrInfo.td:3689 |
| 972 | LDMIA = 957, // ARMInstrInfo.td:3640 |
| 973 | LDMIA_UPD = 958, // ARMInstrInfo.td:3649 |
| 974 | LDMIB = 959, // ARMInstrInfo.td:3700 |
| 975 | LDMIB_UPD = 960, // ARMInstrInfo.td:3709 |
| 976 | LDRBT_POST_IMM = 961, // ARMInstrInfo.td:3236 |
| 977 | LDRBT_POST_REG = 962, // ARMInstrInfo.td:3217 |
| 978 | LDRB_POST_IMM = 963, // ARMInstrInfo.td:3089 |
| 979 | LDRB_POST_REG = 964, // ARMInstrInfo.td:3071 |
| 980 | LDRB_PRE_IMM = 965, // ARMInstrInfo.td:3048 |
| 981 | LDRB_PRE_REG = 966, // ARMInstrInfo.td:3059 |
| 982 | LDRBi12 = 967, // ARMInstrInfo.td:2224 |
| 983 | LDRBrs = 968, // ARMInstrInfo.td:2235 |
| 984 | LDRD = 969, // ARMInstrInfo.td:3025 |
| 985 | LDRD_POST = 970, // ARMInstrInfo.td:3162 |
| 986 | LDRD_PRE = 971, // ARMInstrInfo.td:3149 |
| 987 | LDREX = 972, // ARMInstrInfo.td:5431 |
| 988 | LDREXB = 973, // ARMInstrInfo.td:5425 |
| 989 | LDREXD = 974, // ARMInstrInfo.td:5435 |
| 990 | LDREXH = 975, // ARMInstrInfo.td:5428 |
| 991 | LDRH = 976, // ARMInstrInfo.td:3010 |
| 992 | LDRHTi = 977, // ARMInstrInfo.td:3254 |
| 993 | LDRHTr = 978, // ARMInstrInfo.td:3264 |
| 994 | LDRH_POST = 979, // ARMInstrInfo.td:3128 |
| 995 | LDRH_PRE = 980, // ARMInstrInfo.td:3116 |
| 996 | LDRSB = 981, // ARMInstrInfo.td:3019 |
| 997 | LDRSBTi = 982, // ARMInstrInfo.td:3254 |
| 998 | LDRSBTr = 983, // ARMInstrInfo.td:3264 |
| 999 | LDRSB_POST = 984, // ARMInstrInfo.td:3128 |
| 1000 | LDRSB_PRE = 985, // ARMInstrInfo.td:3116 |
| 1001 | LDRSH = 986, // ARMInstrInfo.td:3015 |
| 1002 | LDRSHTi = 987, // ARMInstrInfo.td:3254 |
| 1003 | LDRSHTr = 988, // ARMInstrInfo.td:3264 |
| 1004 | LDRSH_POST = 989, // ARMInstrInfo.td:3128 |
| 1005 | LDRSH_PRE = 990, // ARMInstrInfo.td:3116 |
| 1006 | LDRT_POST_IMM = 991, // ARMInstrInfo.td:3200 |
| 1007 | LDRT_POST_REG = 992, // ARMInstrInfo.td:3181 |
| 1008 | LDR_POST_IMM = 993, // ARMInstrInfo.td:3089 |
| 1009 | LDR_POST_REG = 994, // ARMInstrInfo.td:3071 |
| 1010 | LDR_PRE_IMM = 995, // ARMInstrInfo.td:3048 |
| 1011 | LDR_PRE_REG = 996, // ARMInstrInfo.td:3059 |
| 1012 | LDRcp = 997, // ARMInstrInfo.td:2998 |
| 1013 | LDRi12 = 998, // ARMInstrInfo.td:2194 |
| 1014 | LDRrs = 999, // ARMInstrInfo.td:2204 |
| 1015 | MCR = 1000, // ARMInstrInfo.td:5810 |
| 1016 | MCR2 = 1001, // ARMInstrInfo.td:5857 |
| 1017 | MCRR = 1002, // ARMInstrInfo.td:5901 |
| 1018 | MCRR2 = 1003, // ARMInstrInfo.td:5934 |
| 1019 | MLA = 1004, // ARMInstrInfo.td:4500 |
| 1020 | MLS = 1005, // ARMInstrInfo.td:4519 |
| 1021 | MOVPCLR = 1006, // ARMInstrInfo.td:2631 |
| 1022 | MOVTi16 = 1007, // ARMInstrInfo.td:3855 |
| 1023 | MOVi = 1008, // ARMInstrInfo.td:3817 |
| 1024 | MOVi16 = 1009, // ARMInstrInfo.td:3829 |
| 1025 | MOVr = 1010, // ARMInstrInfo.td:3760 |
| 1026 | MOVr_TC = 1011, // ARMInstrInfo.td:3774 |
| 1027 | MOVsi = 1012, // ARMInstrInfo.td:3802 |
| 1028 | MOVsr = 1013, // ARMInstrInfo.td:3785 |
| 1029 | MRC = 1014, // ARMInstrInfo.td:5820 |
| 1030 | MRC2 = 1015, // ARMInstrInfo.td:5867 |
| 1031 | MRRC = 1016, // ARMInstrInfo.td:5906 |
| 1032 | MRRC2 = 1017, // ARMInstrInfo.td:5940 |
| 1033 | MRS = 1018, // ARMInstrInfo.td:5949 |
| 1034 | MRSbanked = 1019, // ARMInstrInfo.td:5980 |
| 1035 | MRSsys = 1020, // ARMInstrInfo.td:5966 |
| 1036 | MSR = 1021, // ARMInstrInfo.td:6004 |
| 1037 | MSRbanked = 1022, // ARMInstrInfo.td:6034 |
| 1038 | MSRi = 1023, // ARMInstrInfo.td:6019 |
| 1039 | MUL = 1024, // ARMInstrInfo.td:4480 |
| 1040 | MVE_ASRLi = 1025, // ARMInstrMVE.td:608 |
| 1041 | MVE_ASRLr = 1026, // ARMInstrMVE.td:605 |
| 1042 | MVE_DLSTP_16 = 1027, // ARMInstrMVE.td:7008 |
| 1043 | MVE_DLSTP_32 = 1028, // ARMInstrMVE.td:7009 |
| 1044 | MVE_DLSTP_64 = 1029, // ARMInstrMVE.td:7010 |
| 1045 | MVE_DLSTP_8 = 1030, // ARMInstrMVE.td:7007 |
| 1046 | MVE_LCTP = 1031, // ARMInstrMVE.td:7037 |
| 1047 | MVE_LETP = 1032, // ARMInstrMVE.td:7025 |
| 1048 | MVE_LSLLi = 1033, // ARMInstrMVE.td:614 |
| 1049 | MVE_LSLLr = 1034, // ARMInstrMVE.td:611 |
| 1050 | MVE_LSRL = 1035, // ARMInstrMVE.td:617 |
| 1051 | MVE_SQRSHR = 1036, // ARMInstrMVE.td:533 |
| 1052 | MVE_SQRSHRL = 1037, // ARMInstrMVE.td:621 |
| 1053 | MVE_SQSHL = 1038, // ARMInstrMVE.td:511 |
| 1054 | MVE_SQSHLL = 1039, // ARMInstrMVE.td:622 |
| 1055 | MVE_SRSHR = 1040, // ARMInstrMVE.td:512 |
| 1056 | MVE_SRSHRL = 1041, // ARMInstrMVE.td:623 |
| 1057 | MVE_UQRSHL = 1042, // ARMInstrMVE.td:534 |
| 1058 | MVE_UQRSHLL = 1043, // ARMInstrMVE.td:625 |
| 1059 | MVE_UQSHL = 1044, // ARMInstrMVE.td:513 |
| 1060 | MVE_UQSHLL = 1045, // ARMInstrMVE.td:626 |
| 1061 | MVE_URSHR = 1046, // ARMInstrMVE.td:514 |
| 1062 | MVE_URSHRL = 1047, // ARMInstrMVE.td:627 |
| 1063 | MVE_VABAVs16 = 1048, // ARMInstrMVE.td:668 |
| 1064 | MVE_VABAVs32 = 1049, // ARMInstrMVE.td:668 |
| 1065 | MVE_VABAVs8 = 1050, // ARMInstrMVE.td:668 |
| 1066 | MVE_VABAVu16 = 1051, // ARMInstrMVE.td:668 |
| 1067 | MVE_VABAVu32 = 1052, // ARMInstrMVE.td:668 |
| 1068 | MVE_VABAVu8 = 1053, // ARMInstrMVE.td:668 |
| 1069 | MVE_VABDf16 = 1054, // ARMInstrMVE.td:3888 |
| 1070 | MVE_VABDf32 = 1055, // ARMInstrMVE.td:3888 |
| 1071 | MVE_VABDs16 = 1056, // ARMInstrMVE.td:2221 |
| 1072 | MVE_VABDs32 = 1057, // ARMInstrMVE.td:2221 |
| 1073 | MVE_VABDs8 = 1058, // ARMInstrMVE.td:2221 |
| 1074 | MVE_VABDu16 = 1059, // ARMInstrMVE.td:2221 |
| 1075 | MVE_VABDu32 = 1060, // ARMInstrMVE.td:2221 |
| 1076 | MVE_VABDu8 = 1061, // ARMInstrMVE.td:2221 |
| 1077 | MVE_VABSf16 = 1062, // ARMInstrMVE.td:4144 |
| 1078 | MVE_VABSf32 = 1063, // ARMInstrMVE.td:4144 |
| 1079 | MVE_VABSs16 = 1064, // ARMInstrMVE.td:2527 |
| 1080 | MVE_VABSs32 = 1065, // ARMInstrMVE.td:2527 |
| 1081 | MVE_VABSs8 = 1066, // ARMInstrMVE.td:2527 |
| 1082 | MVE_VADC = 1067, // ARMInstrMVE.td:5160 |
| 1083 | MVE_VADCI = 1068, // ARMInstrMVE.td:5161 |
| 1084 | MVE_VADDLVs32acc = 1069, // ARMInstrMVE.td:837 |
| 1085 | MVE_VADDLVs32no_acc = 1070, // ARMInstrMVE.td:841 |
| 1086 | MVE_VADDLVu32acc = 1071, // ARMInstrMVE.td:837 |
| 1087 | MVE_VADDLVu32no_acc = 1072, // ARMInstrMVE.td:841 |
| 1088 | MVE_VADDVs16acc = 1073, // ARMInstrMVE.td:732 |
| 1089 | MVE_VADDVs16no_acc = 1074, // ARMInstrMVE.td:735 |
| 1090 | MVE_VADDVs32acc = 1075, // ARMInstrMVE.td:732 |
| 1091 | MVE_VADDVs32no_acc = 1076, // ARMInstrMVE.td:735 |
| 1092 | MVE_VADDVs8acc = 1077, // ARMInstrMVE.td:732 |
| 1093 | MVE_VADDVs8no_acc = 1078, // ARMInstrMVE.td:735 |
| 1094 | MVE_VADDVu16acc = 1079, // ARMInstrMVE.td:732 |
| 1095 | MVE_VADDVu16no_acc = 1080, // ARMInstrMVE.td:735 |
| 1096 | MVE_VADDVu32acc = 1081, // ARMInstrMVE.td:732 |
| 1097 | MVE_VADDVu32no_acc = 1082, // ARMInstrMVE.td:735 |
| 1098 | MVE_VADDVu8acc = 1083, // ARMInstrMVE.td:732 |
| 1099 | MVE_VADDVu8no_acc = 1084, // ARMInstrMVE.td:735 |
| 1100 | MVE_VADD_qr_f16 = 1085, // ARMInstrMVE.td:5451 |
| 1101 | MVE_VADD_qr_f32 = 1086, // ARMInstrMVE.td:5451 |
| 1102 | MVE_VADD_qr_i16 = 1087, // ARMInstrMVE.td:5300 |
| 1103 | MVE_VADD_qr_i32 = 1088, // ARMInstrMVE.td:5300 |
| 1104 | MVE_VADD_qr_i8 = 1089, // ARMInstrMVE.td:5300 |
| 1105 | MVE_VADDf16 = 1090, // ARMInstrMVE.td:3797 |
| 1106 | MVE_VADDf32 = 1091, // ARMInstrMVE.td:3797 |
| 1107 | MVE_VADDi16 = 1092, // ARMInstrMVE.td:2123 |
| 1108 | MVE_VADDi32 = 1093, // ARMInstrMVE.td:2123 |
| 1109 | MVE_VADDi8 = 1094, // ARMInstrMVE.td:2123 |
| 1110 | MVE_VAND = 1095, // ARMInstrMVE.td:1708 |
| 1111 | MVE_VBIC = 1096, // ARMInstrMVE.td:1590 |
| 1112 | MVE_VBICimmi16 = 1097, // ARMInstrMVE.td:1784 |
| 1113 | MVE_VBICimmi32 = 1098, // ARMInstrMVE.td:1784 |
| 1114 | MVE_VBRSR16 = 1099, // ARMInstrMVE.td:5544 |
| 1115 | MVE_VBRSR32 = 1100, // ARMInstrMVE.td:5545 |
| 1116 | MVE_VBRSR8 = 1101, // ARMInstrMVE.td:5543 |
| 1117 | MVE_VCADDf16 = 1102, // ARMInstrMVE.td:3843 |
| 1118 | MVE_VCADDf32 = 1103, // ARMInstrMVE.td:3843 |
| 1119 | MVE_VCADDi16 = 1104, // ARMInstrMVE.td:5111 |
| 1120 | MVE_VCADDi32 = 1105, // ARMInstrMVE.td:5111 |
| 1121 | MVE_VCADDi8 = 1106, // ARMInstrMVE.td:5111 |
| 1122 | MVE_VCLSs16 = 1107, // ARMInstrMVE.td:2482 |
| 1123 | MVE_VCLSs32 = 1108, // ARMInstrMVE.td:2482 |
| 1124 | MVE_VCLSs8 = 1109, // ARMInstrMVE.td:2482 |
| 1125 | MVE_VCLZs16 = 1110, // ARMInstrMVE.td:2482 |
| 1126 | MVE_VCLZs32 = 1111, // ARMInstrMVE.td:2482 |
| 1127 | MVE_VCLZs8 = 1112, // ARMInstrMVE.td:2482 |
| 1128 | MVE_VCMLAf16 = 1113, // ARMInstrMVE.td:3695 |
| 1129 | MVE_VCMLAf32 = 1114, // ARMInstrMVE.td:3695 |
| 1130 | MVE_VCMPf16 = 1115, // ARMInstrMVE.td:4285 |
| 1131 | MVE_VCMPf16r = 1116, // ARMInstrMVE.td:4350 |
| 1132 | MVE_VCMPf32 = 1117, // ARMInstrMVE.td:4284 |
| 1133 | MVE_VCMPf32r = 1118, // ARMInstrMVE.td:4349 |
| 1134 | MVE_VCMPi16 = 1119, // ARMInstrMVE.td:4288 |
| 1135 | MVE_VCMPi16r = 1120, // ARMInstrMVE.td:4353 |
| 1136 | MVE_VCMPi32 = 1121, // ARMInstrMVE.td:4289 |
| 1137 | MVE_VCMPi32r = 1122, // ARMInstrMVE.td:4354 |
| 1138 | MVE_VCMPi8 = 1123, // ARMInstrMVE.td:4287 |
| 1139 | MVE_VCMPi8r = 1124, // ARMInstrMVE.td:4352 |
| 1140 | MVE_VCMPs16 = 1125, // ARMInstrMVE.td:4296 |
| 1141 | MVE_VCMPs16r = 1126, // ARMInstrMVE.td:4361 |
| 1142 | MVE_VCMPs32 = 1127, // ARMInstrMVE.td:4297 |
| 1143 | MVE_VCMPs32r = 1128, // ARMInstrMVE.td:4362 |
| 1144 | MVE_VCMPs8 = 1129, // ARMInstrMVE.td:4295 |
| 1145 | MVE_VCMPs8r = 1130, // ARMInstrMVE.td:4360 |
| 1146 | MVE_VCMPu16 = 1131, // ARMInstrMVE.td:4292 |
| 1147 | MVE_VCMPu16r = 1132, // ARMInstrMVE.td:4357 |
| 1148 | MVE_VCMPu32 = 1133, // ARMInstrMVE.td:4293 |
| 1149 | MVE_VCMPu32r = 1134, // ARMInstrMVE.td:4358 |
| 1150 | MVE_VCMPu8 = 1135, // ARMInstrMVE.td:4291 |
| 1151 | MVE_VCMPu8r = 1136, // ARMInstrMVE.td:4356 |
| 1152 | MVE_VCMULf16 = 1137, // ARMInstrMVE.td:4652 |
| 1153 | MVE_VCMULf32 = 1138, // ARMInstrMVE.td:4652 |
| 1154 | MVE_VCTP16 = 1139, // ARMInstrMVE.td:5892 |
| 1155 | MVE_VCTP32 = 1140, // ARMInstrMVE.td:5892 |
| 1156 | MVE_VCTP64 = 1141, // ARMInstrMVE.td:5892 |
| 1157 | MVE_VCTP8 = 1142, // ARMInstrMVE.td:5892 |
| 1158 | MVE_VCVTf16f32bh = 1143, // ARMInstrMVE.td:5049 |
| 1159 | MVE_VCVTf16f32th = 1144, // ARMInstrMVE.td:5049 |
| 1160 | MVE_VCVTf16s16_fix = 1145, // ARMInstrMVE.td:3988 |
| 1161 | MVE_VCVTf16s16n = 1146, // ARMInstrMVE.td:4083 |
| 1162 | MVE_VCVTf16u16_fix = 1147, // ARMInstrMVE.td:3988 |
| 1163 | MVE_VCVTf16u16n = 1148, // ARMInstrMVE.td:4083 |
| 1164 | MVE_VCVTf32f16bh = 1149, // ARMInstrMVE.td:5069 |
| 1165 | MVE_VCVTf32f16th = 1150, // ARMInstrMVE.td:5069 |
| 1166 | MVE_VCVTf32s32_fix = 1151, // ARMInstrMVE.td:3982 |
| 1167 | MVE_VCVTf32s32n = 1152, // ARMInstrMVE.td:4083 |
| 1168 | MVE_VCVTf32u32_fix = 1153, // ARMInstrMVE.td:3982 |
| 1169 | MVE_VCVTf32u32n = 1154, // ARMInstrMVE.td:4083 |
| 1170 | MVE_VCVTs16f16_fix = 1155, // ARMInstrMVE.td:3988 |
| 1171 | MVE_VCVTs16f16a = 1156, // ARMInstrMVE.td:4023 |
| 1172 | MVE_VCVTs16f16m = 1157, // ARMInstrMVE.td:4023 |
| 1173 | MVE_VCVTs16f16n = 1158, // ARMInstrMVE.td:4023 |
| 1174 | MVE_VCVTs16f16p = 1159, // ARMInstrMVE.td:4023 |
| 1175 | MVE_VCVTs16f16z = 1160, // ARMInstrMVE.td:4083 |
| 1176 | MVE_VCVTs32f32_fix = 1161, // ARMInstrMVE.td:3982 |
| 1177 | MVE_VCVTs32f32a = 1162, // ARMInstrMVE.td:4023 |
| 1178 | MVE_VCVTs32f32m = 1163, // ARMInstrMVE.td:4023 |
| 1179 | MVE_VCVTs32f32n = 1164, // ARMInstrMVE.td:4023 |
| 1180 | MVE_VCVTs32f32p = 1165, // ARMInstrMVE.td:4023 |
| 1181 | MVE_VCVTs32f32z = 1166, // ARMInstrMVE.td:4083 |
| 1182 | MVE_VCVTu16f16_fix = 1167, // ARMInstrMVE.td:3988 |
| 1183 | MVE_VCVTu16f16a = 1168, // ARMInstrMVE.td:4023 |
| 1184 | MVE_VCVTu16f16m = 1169, // ARMInstrMVE.td:4023 |
| 1185 | MVE_VCVTu16f16n = 1170, // ARMInstrMVE.td:4023 |
| 1186 | MVE_VCVTu16f16p = 1171, // ARMInstrMVE.td:4023 |
| 1187 | MVE_VCVTu16f16z = 1172, // ARMInstrMVE.td:4083 |
| 1188 | MVE_VCVTu32f32_fix = 1173, // ARMInstrMVE.td:3982 |
| 1189 | MVE_VCVTu32f32a = 1174, // ARMInstrMVE.td:4023 |
| 1190 | MVE_VCVTu32f32m = 1175, // ARMInstrMVE.td:4023 |
| 1191 | MVE_VCVTu32f32n = 1176, // ARMInstrMVE.td:4023 |
| 1192 | MVE_VCVTu32f32p = 1177, // ARMInstrMVE.td:4023 |
| 1193 | MVE_VCVTu32f32z = 1178, // ARMInstrMVE.td:4083 |
| 1194 | MVE_VDDUPu16 = 1179, // ARMInstrMVE.td:5833 |
| 1195 | MVE_VDDUPu32 = 1180, // ARMInstrMVE.td:5834 |
| 1196 | MVE_VDDUPu8 = 1181, // ARMInstrMVE.td:5832 |
| 1197 | MVE_VDUP16 = 1182, // ARMInstrMVE.td:2405 |
| 1198 | MVE_VDUP32 = 1183, // ARMInstrMVE.td:2404 |
| 1199 | MVE_VDUP8 = 1184, // ARMInstrMVE.td:2406 |
| 1200 | MVE_VDWDUPu16 = 1185, // ARMInstrMVE.td:5869 |
| 1201 | MVE_VDWDUPu32 = 1186, // ARMInstrMVE.td:5870 |
| 1202 | MVE_VDWDUPu8 = 1187, // ARMInstrMVE.td:5868 |
| 1203 | MVE_VEOR = 1188, // ARMInstrMVE.td:1705 |
| 1204 | MVE_VFMA_qr_Sf16 = 1189, // ARMInstrMVE.td:5707 |
| 1205 | MVE_VFMA_qr_Sf32 = 1190, // ARMInstrMVE.td:5707 |
| 1206 | MVE_VFMA_qr_f16 = 1191, // ARMInstrMVE.td:5707 |
| 1207 | MVE_VFMA_qr_f32 = 1192, // ARMInstrMVE.td:5707 |
| 1208 | MVE_VFMAf16 = 1193, // ARMInstrMVE.td:3750 |
| 1209 | MVE_VFMAf32 = 1194, // ARMInstrMVE.td:3750 |
| 1210 | MVE_VFMSf16 = 1195, // ARMInstrMVE.td:3750 |
| 1211 | MVE_VFMSf32 = 1196, // ARMInstrMVE.td:3750 |
| 1212 | MVE_VHADD_qr_s16 = 1197, // ARMInstrMVE.td:5414 |
| 1213 | MVE_VHADD_qr_s32 = 1198, // ARMInstrMVE.td:5414 |
| 1214 | MVE_VHADD_qr_s8 = 1199, // ARMInstrMVE.td:5414 |
| 1215 | MVE_VHADD_qr_u16 = 1200, // ARMInstrMVE.td:5414 |
| 1216 | MVE_VHADD_qr_u32 = 1201, // ARMInstrMVE.td:5414 |
| 1217 | MVE_VHADD_qr_u8 = 1202, // ARMInstrMVE.td:5414 |
| 1218 | MVE_VHADDs16 = 1203, // ARMInstrMVE.td:2325 |
| 1219 | MVE_VHADDs32 = 1204, // ARMInstrMVE.td:2325 |
| 1220 | MVE_VHADDs8 = 1205, // ARMInstrMVE.td:2325 |
| 1221 | MVE_VHADDu16 = 1206, // ARMInstrMVE.td:2325 |
| 1222 | MVE_VHADDu32 = 1207, // ARMInstrMVE.td:2325 |
| 1223 | MVE_VHADDu8 = 1208, // ARMInstrMVE.td:2325 |
| 1224 | MVE_VHCADDs16 = 1209, // ARMInstrMVE.td:5111 |
| 1225 | MVE_VHCADDs32 = 1210, // ARMInstrMVE.td:5111 |
| 1226 | MVE_VHCADDs8 = 1211, // ARMInstrMVE.td:5111 |
| 1227 | MVE_VHSUB_qr_s16 = 1212, // ARMInstrMVE.td:5414 |
| 1228 | MVE_VHSUB_qr_s32 = 1213, // ARMInstrMVE.td:5414 |
| 1229 | MVE_VHSUB_qr_s8 = 1214, // ARMInstrMVE.td:5414 |
| 1230 | MVE_VHSUB_qr_u16 = 1215, // ARMInstrMVE.td:5414 |
| 1231 | MVE_VHSUB_qr_u32 = 1216, // ARMInstrMVE.td:5414 |
| 1232 | MVE_VHSUB_qr_u8 = 1217, // ARMInstrMVE.td:5414 |
| 1233 | MVE_VHSUBs16 = 1218, // ARMInstrMVE.td:2349 |
| 1234 | MVE_VHSUBs32 = 1219, // ARMInstrMVE.td:2349 |
| 1235 | MVE_VHSUBs8 = 1220, // ARMInstrMVE.td:2349 |
| 1236 | MVE_VHSUBu16 = 1221, // ARMInstrMVE.td:2349 |
| 1237 | MVE_VHSUBu32 = 1222, // ARMInstrMVE.td:2349 |
| 1238 | MVE_VHSUBu8 = 1223, // ARMInstrMVE.td:2349 |
| 1239 | MVE_VIDUPu16 = 1224, // ARMInstrMVE.td:5829 |
| 1240 | MVE_VIDUPu32 = 1225, // ARMInstrMVE.td:5830 |
| 1241 | MVE_VIDUPu8 = 1226, // ARMInstrMVE.td:5828 |
| 1242 | MVE_VIWDUPu16 = 1227, // ARMInstrMVE.td:5865 |
| 1243 | MVE_VIWDUPu32 = 1228, // ARMInstrMVE.td:5866 |
| 1244 | MVE_VIWDUPu8 = 1229, // ARMInstrMVE.td:5864 |
| 1245 | MVE_VLD20_16 = 1230, // ARMInstrMVE.td:6111 |
| 1246 | MVE_VLD20_16_wb = 1231, // ARMInstrMVE.td:6111 |
| 1247 | MVE_VLD20_32 = 1232, // ARMInstrMVE.td:6111 |
| 1248 | MVE_VLD20_32_wb = 1233, // ARMInstrMVE.td:6111 |
| 1249 | MVE_VLD20_8 = 1234, // ARMInstrMVE.td:6111 |
| 1250 | MVE_VLD20_8_wb = 1235, // ARMInstrMVE.td:6111 |
| 1251 | MVE_VLD21_16 = 1236, // ARMInstrMVE.td:6111 |
| 1252 | MVE_VLD21_16_wb = 1237, // ARMInstrMVE.td:6111 |
| 1253 | MVE_VLD21_32 = 1238, // ARMInstrMVE.td:6111 |
| 1254 | MVE_VLD21_32_wb = 1239, // ARMInstrMVE.td:6111 |
| 1255 | MVE_VLD21_8 = 1240, // ARMInstrMVE.td:6111 |
| 1256 | MVE_VLD21_8_wb = 1241, // ARMInstrMVE.td:6111 |
| 1257 | MVE_VLD40_16 = 1242, // ARMInstrMVE.td:6111 |
| 1258 | MVE_VLD40_16_wb = 1243, // ARMInstrMVE.td:6111 |
| 1259 | MVE_VLD40_32 = 1244, // ARMInstrMVE.td:6111 |
| 1260 | MVE_VLD40_32_wb = 1245, // ARMInstrMVE.td:6111 |
| 1261 | MVE_VLD40_8 = 1246, // ARMInstrMVE.td:6111 |
| 1262 | MVE_VLD40_8_wb = 1247, // ARMInstrMVE.td:6111 |
| 1263 | MVE_VLD41_16 = 1248, // ARMInstrMVE.td:6111 |
| 1264 | MVE_VLD41_16_wb = 1249, // ARMInstrMVE.td:6111 |
| 1265 | MVE_VLD41_32 = 1250, // ARMInstrMVE.td:6111 |
| 1266 | MVE_VLD41_32_wb = 1251, // ARMInstrMVE.td:6111 |
| 1267 | MVE_VLD41_8 = 1252, // ARMInstrMVE.td:6111 |
| 1268 | MVE_VLD41_8_wb = 1253, // ARMInstrMVE.td:6111 |
| 1269 | MVE_VLD42_16 = 1254, // ARMInstrMVE.td:6111 |
| 1270 | MVE_VLD42_16_wb = 1255, // ARMInstrMVE.td:6111 |
| 1271 | MVE_VLD42_32 = 1256, // ARMInstrMVE.td:6111 |
| 1272 | MVE_VLD42_32_wb = 1257, // ARMInstrMVE.td:6111 |
| 1273 | MVE_VLD42_8 = 1258, // ARMInstrMVE.td:6111 |
| 1274 | MVE_VLD42_8_wb = 1259, // ARMInstrMVE.td:6111 |
| 1275 | MVE_VLD43_16 = 1260, // ARMInstrMVE.td:6111 |
| 1276 | MVE_VLD43_16_wb = 1261, // ARMInstrMVE.td:6111 |
| 1277 | MVE_VLD43_32 = 1262, // ARMInstrMVE.td:6111 |
| 1278 | MVE_VLD43_32_wb = 1263, // ARMInstrMVE.td:6111 |
| 1279 | MVE_VLD43_8 = 1264, // ARMInstrMVE.td:6111 |
| 1280 | MVE_VLD43_8_wb = 1265, // ARMInstrMVE.td:6111 |
| 1281 | MVE_VLDRBS16 = 1266, // ARMInstrMVE.td:6288 |
| 1282 | MVE_VLDRBS16_post = 1267, // ARMInstrMVE.td:6301 |
| 1283 | MVE_VLDRBS16_pre = 1268, // ARMInstrMVE.td:6293 |
| 1284 | MVE_VLDRBS16_rq = 1269, // ARMInstrMVE.td:6440 |
| 1285 | MVE_VLDRBS32 = 1270, // ARMInstrMVE.td:6288 |
| 1286 | MVE_VLDRBS32_post = 1271, // ARMInstrMVE.td:6301 |
| 1287 | MVE_VLDRBS32_pre = 1272, // ARMInstrMVE.td:6293 |
| 1288 | MVE_VLDRBS32_rq = 1273, // ARMInstrMVE.td:6440 |
| 1289 | MVE_VLDRBU16 = 1274, // ARMInstrMVE.td:6288 |
| 1290 | MVE_VLDRBU16_post = 1275, // ARMInstrMVE.td:6301 |
| 1291 | MVE_VLDRBU16_pre = 1276, // ARMInstrMVE.td:6293 |
| 1292 | MVE_VLDRBU16_rq = 1277, // ARMInstrMVE.td:6440 |
| 1293 | MVE_VLDRBU32 = 1278, // ARMInstrMVE.td:6288 |
| 1294 | MVE_VLDRBU32_post = 1279, // ARMInstrMVE.td:6301 |
| 1295 | MVE_VLDRBU32_pre = 1280, // ARMInstrMVE.td:6293 |
| 1296 | MVE_VLDRBU32_rq = 1281, // ARMInstrMVE.td:6440 |
| 1297 | MVE_VLDRBU8 = 1282, // ARMInstrMVE.td:6316 |
| 1298 | MVE_VLDRBU8_post = 1283, // ARMInstrMVE.td:6329 |
| 1299 | MVE_VLDRBU8_pre = 1284, // ARMInstrMVE.td:6321 |
| 1300 | MVE_VLDRBU8_rq = 1285, // ARMInstrMVE.td:6440 |
| 1301 | MVE_VLDRDU64_qi = 1286, // ARMInstrMVE.td:6534 |
| 1302 | MVE_VLDRDU64_qi_pre = 1287, // ARMInstrMVE.td:6535 |
| 1303 | MVE_VLDRDU64_rq = 1288, // ARMInstrMVE.td:6408 |
| 1304 | MVE_VLDRDU64_rq_u = 1289, // ARMInstrMVE.td:6407 |
| 1305 | MVE_VLDRHS32 = 1290, // ARMInstrMVE.td:6288 |
| 1306 | MVE_VLDRHS32_post = 1291, // ARMInstrMVE.td:6301 |
| 1307 | MVE_VLDRHS32_pre = 1292, // ARMInstrMVE.td:6293 |
| 1308 | MVE_VLDRHS32_rq = 1293, // ARMInstrMVE.td:6408 |
| 1309 | MVE_VLDRHS32_rq_u = 1294, // ARMInstrMVE.td:6407 |
| 1310 | MVE_VLDRHU16 = 1295, // ARMInstrMVE.td:6316 |
| 1311 | MVE_VLDRHU16_post = 1296, // ARMInstrMVE.td:6329 |
| 1312 | MVE_VLDRHU16_pre = 1297, // ARMInstrMVE.td:6321 |
| 1313 | MVE_VLDRHU16_rq = 1298, // ARMInstrMVE.td:6408 |
| 1314 | MVE_VLDRHU16_rq_u = 1299, // ARMInstrMVE.td:6407 |
| 1315 | MVE_VLDRHU32 = 1300, // ARMInstrMVE.td:6288 |
| 1316 | MVE_VLDRHU32_post = 1301, // ARMInstrMVE.td:6301 |
| 1317 | MVE_VLDRHU32_pre = 1302, // ARMInstrMVE.td:6293 |
| 1318 | MVE_VLDRHU32_rq = 1303, // ARMInstrMVE.td:6408 |
| 1319 | MVE_VLDRHU32_rq_u = 1304, // ARMInstrMVE.td:6407 |
| 1320 | MVE_VLDRWU32 = 1305, // ARMInstrMVE.td:6316 |
| 1321 | MVE_VLDRWU32_post = 1306, // ARMInstrMVE.td:6329 |
| 1322 | MVE_VLDRWU32_pre = 1307, // ARMInstrMVE.td:6321 |
| 1323 | MVE_VLDRWU32_qi = 1308, // ARMInstrMVE.td:6534 |
| 1324 | MVE_VLDRWU32_qi_pre = 1309, // ARMInstrMVE.td:6535 |
| 1325 | MVE_VLDRWU32_rq = 1310, // ARMInstrMVE.td:6408 |
| 1326 | MVE_VLDRWU32_rq_u = 1311, // ARMInstrMVE.td:6407 |
| 1327 | MVE_VMAXAVs16 = 1312, // ARMInstrMVE.td:966 |
| 1328 | MVE_VMAXAVs32 = 1313, // ARMInstrMVE.td:966 |
| 1329 | MVE_VMAXAVs8 = 1314, // ARMInstrMVE.td:966 |
| 1330 | MVE_VMAXAs16 = 1315, // ARMInstrMVE.td:2705 |
| 1331 | MVE_VMAXAs32 = 1316, // ARMInstrMVE.td:2705 |
| 1332 | MVE_VMAXAs8 = 1317, // ARMInstrMVE.td:2705 |
| 1333 | MVE_VMAXNMAVf16 = 1318, // ARMInstrMVE.td:909 |
| 1334 | MVE_VMAXNMAVf32 = 1319, // ARMInstrMVE.td:909 |
| 1335 | MVE_VMAXNMAf16 = 1320, // ARMInstrMVE.td:4192 |
| 1336 | MVE_VMAXNMAf32 = 1321, // ARMInstrMVE.td:4192 |
| 1337 | MVE_VMAXNMVf16 = 1322, // ARMInstrMVE.td:909 |
| 1338 | MVE_VMAXNMVf32 = 1323, // ARMInstrMVE.td:909 |
| 1339 | MVE_VMAXNMf16 = 1324, // ARMInstrMVE.td:1518 |
| 1340 | MVE_VMAXNMf32 = 1325, // ARMInstrMVE.td:1518 |
| 1341 | MVE_VMAXVs16 = 1326, // ARMInstrMVE.td:966 |
| 1342 | MVE_VMAXVs32 = 1327, // ARMInstrMVE.td:966 |
| 1343 | MVE_VMAXVs8 = 1328, // ARMInstrMVE.td:966 |
| 1344 | MVE_VMAXVu16 = 1329, // ARMInstrMVE.td:966 |
| 1345 | MVE_VMAXVu32 = 1330, // ARMInstrMVE.td:966 |
| 1346 | MVE_VMAXVu8 = 1331, // ARMInstrMVE.td:966 |
| 1347 | MVE_VMAXs16 = 1332, // ARMInstrMVE.td:1548 |
| 1348 | MVE_VMAXs32 = 1333, // ARMInstrMVE.td:1548 |
| 1349 | MVE_VMAXs8 = 1334, // ARMInstrMVE.td:1548 |
| 1350 | MVE_VMAXu16 = 1335, // ARMInstrMVE.td:1548 |
| 1351 | MVE_VMAXu32 = 1336, // ARMInstrMVE.td:1548 |
| 1352 | MVE_VMAXu8 = 1337, // ARMInstrMVE.td:1548 |
| 1353 | MVE_VMINAVs16 = 1338, // ARMInstrMVE.td:966 |
| 1354 | MVE_VMINAVs32 = 1339, // ARMInstrMVE.td:966 |
| 1355 | MVE_VMINAVs8 = 1340, // ARMInstrMVE.td:966 |
| 1356 | MVE_VMINAs16 = 1341, // ARMInstrMVE.td:2705 |
| 1357 | MVE_VMINAs32 = 1342, // ARMInstrMVE.td:2705 |
| 1358 | MVE_VMINAs8 = 1343, // ARMInstrMVE.td:2705 |
| 1359 | MVE_VMINNMAVf16 = 1344, // ARMInstrMVE.td:909 |
| 1360 | MVE_VMINNMAVf32 = 1345, // ARMInstrMVE.td:909 |
| 1361 | MVE_VMINNMAf16 = 1346, // ARMInstrMVE.td:4192 |
| 1362 | MVE_VMINNMAf32 = 1347, // ARMInstrMVE.td:4192 |
| 1363 | MVE_VMINNMVf16 = 1348, // ARMInstrMVE.td:909 |
| 1364 | MVE_VMINNMVf32 = 1349, // ARMInstrMVE.td:909 |
| 1365 | MVE_VMINNMf16 = 1350, // ARMInstrMVE.td:1518 |
| 1366 | MVE_VMINNMf32 = 1351, // ARMInstrMVE.td:1518 |
| 1367 | MVE_VMINVs16 = 1352, // ARMInstrMVE.td:966 |
| 1368 | MVE_VMINVs32 = 1353, // ARMInstrMVE.td:966 |
| 1369 | MVE_VMINVs8 = 1354, // ARMInstrMVE.td:966 |
| 1370 | MVE_VMINVu16 = 1355, // ARMInstrMVE.td:966 |
| 1371 | MVE_VMINVu32 = 1356, // ARMInstrMVE.td:966 |
| 1372 | MVE_VMINVu8 = 1357, // ARMInstrMVE.td:966 |
| 1373 | MVE_VMINs16 = 1358, // ARMInstrMVE.td:1548 |
| 1374 | MVE_VMINs32 = 1359, // ARMInstrMVE.td:1548 |
| 1375 | MVE_VMINs8 = 1360, // ARMInstrMVE.td:1548 |
| 1376 | MVE_VMINu16 = 1361, // ARMInstrMVE.td:1548 |
| 1377 | MVE_VMINu32 = 1362, // ARMInstrMVE.td:1548 |
| 1378 | MVE_VMINu8 = 1363, // ARMInstrMVE.td:1548 |
| 1379 | MVE_VMLADAVas16 = 1364, // ARMInstrMVE.td:1109 |
| 1380 | MVE_VMLADAVas32 = 1365, // ARMInstrMVE.td:1109 |
| 1381 | MVE_VMLADAVas8 = 1366, // ARMInstrMVE.td:1109 |
| 1382 | MVE_VMLADAVau16 = 1367, // ARMInstrMVE.td:1109 |
| 1383 | MVE_VMLADAVau32 = 1368, // ARMInstrMVE.td:1109 |
| 1384 | MVE_VMLADAVau8 = 1369, // ARMInstrMVE.td:1109 |
| 1385 | MVE_VMLADAVaxs16 = 1370, // ARMInstrMVE.td:1109 |
| 1386 | MVE_VMLADAVaxs32 = 1371, // ARMInstrMVE.td:1109 |
| 1387 | MVE_VMLADAVaxs8 = 1372, // ARMInstrMVE.td:1109 |
| 1388 | MVE_VMLADAVs16 = 1373, // ARMInstrMVE.td:1106 |
| 1389 | MVE_VMLADAVs32 = 1374, // ARMInstrMVE.td:1106 |
| 1390 | MVE_VMLADAVs8 = 1375, // ARMInstrMVE.td:1106 |
| 1391 | MVE_VMLADAVu16 = 1376, // ARMInstrMVE.td:1106 |
| 1392 | MVE_VMLADAVu32 = 1377, // ARMInstrMVE.td:1106 |
| 1393 | MVE_VMLADAVu8 = 1378, // ARMInstrMVE.td:1106 |
| 1394 | MVE_VMLADAVxs16 = 1379, // ARMInstrMVE.td:1106 |
| 1395 | MVE_VMLADAVxs32 = 1380, // ARMInstrMVE.td:1106 |
| 1396 | MVE_VMLADAVxs8 = 1381, // ARMInstrMVE.td:1106 |
| 1397 | MVE_VMLALDAVas16 = 1382, // ARMInstrMVE.td:1363 |
| 1398 | MVE_VMLALDAVas32 = 1383, // ARMInstrMVE.td:1363 |
| 1399 | MVE_VMLALDAVau16 = 1384, // ARMInstrMVE.td:1363 |
| 1400 | MVE_VMLALDAVau32 = 1385, // ARMInstrMVE.td:1363 |
| 1401 | MVE_VMLALDAVaxs16 = 1386, // ARMInstrMVE.td:1363 |
| 1402 | MVE_VMLALDAVaxs32 = 1387, // ARMInstrMVE.td:1363 |
| 1403 | MVE_VMLALDAVs16 = 1388, // ARMInstrMVE.td:1360 |
| 1404 | MVE_VMLALDAVs32 = 1389, // ARMInstrMVE.td:1360 |
| 1405 | MVE_VMLALDAVu16 = 1390, // ARMInstrMVE.td:1360 |
| 1406 | MVE_VMLALDAVu32 = 1391, // ARMInstrMVE.td:1360 |
| 1407 | MVE_VMLALDAVxs16 = 1392, // ARMInstrMVE.td:1360 |
| 1408 | MVE_VMLALDAVxs32 = 1393, // ARMInstrMVE.td:1360 |
| 1409 | MVE_VMLAS_qr_i16 = 1394, // ARMInstrMVE.td:5673 |
| 1410 | MVE_VMLAS_qr_i32 = 1395, // ARMInstrMVE.td:5673 |
| 1411 | MVE_VMLAS_qr_i8 = 1396, // ARMInstrMVE.td:5673 |
| 1412 | MVE_VMLA_qr_i16 = 1397, // ARMInstrMVE.td:5673 |
| 1413 | MVE_VMLA_qr_i32 = 1398, // ARMInstrMVE.td:5673 |
| 1414 | MVE_VMLA_qr_i8 = 1399, // ARMInstrMVE.td:5673 |
| 1415 | MVE_VMLSDAVas16 = 1400, // ARMInstrMVE.td:1109 |
| 1416 | MVE_VMLSDAVas32 = 1401, // ARMInstrMVE.td:1109 |
| 1417 | MVE_VMLSDAVas8 = 1402, // ARMInstrMVE.td:1109 |
| 1418 | MVE_VMLSDAVaxs16 = 1403, // ARMInstrMVE.td:1109 |
| 1419 | MVE_VMLSDAVaxs32 = 1404, // ARMInstrMVE.td:1109 |
| 1420 | MVE_VMLSDAVaxs8 = 1405, // ARMInstrMVE.td:1109 |
| 1421 | MVE_VMLSDAVs16 = 1406, // ARMInstrMVE.td:1106 |
| 1422 | MVE_VMLSDAVs32 = 1407, // ARMInstrMVE.td:1106 |
| 1423 | MVE_VMLSDAVs8 = 1408, // ARMInstrMVE.td:1106 |
| 1424 | MVE_VMLSDAVxs16 = 1409, // ARMInstrMVE.td:1106 |
| 1425 | MVE_VMLSDAVxs32 = 1410, // ARMInstrMVE.td:1106 |
| 1426 | MVE_VMLSDAVxs8 = 1411, // ARMInstrMVE.td:1106 |
| 1427 | MVE_VMLSLDAVas16 = 1412, // ARMInstrMVE.td:1363 |
| 1428 | MVE_VMLSLDAVas32 = 1413, // ARMInstrMVE.td:1363 |
| 1429 | MVE_VMLSLDAVaxs16 = 1414, // ARMInstrMVE.td:1363 |
| 1430 | MVE_VMLSLDAVaxs32 = 1415, // ARMInstrMVE.td:1363 |
| 1431 | MVE_VMLSLDAVs16 = 1416, // ARMInstrMVE.td:1360 |
| 1432 | MVE_VMLSLDAVs32 = 1417, // ARMInstrMVE.td:1360 |
| 1433 | MVE_VMLSLDAVxs16 = 1418, // ARMInstrMVE.td:1360 |
| 1434 | MVE_VMLSLDAVxs32 = 1419, // ARMInstrMVE.td:1360 |
| 1435 | MVE_VMOVLs16bh = 1420, // ARMInstrMVE.td:2789 |
| 1436 | MVE_VMOVLs16th = 1421, // ARMInstrMVE.td:2789 |
| 1437 | MVE_VMOVLs8bh = 1422, // ARMInstrMVE.td:2789 |
| 1438 | MVE_VMOVLs8th = 1423, // ARMInstrMVE.td:2789 |
| 1439 | MVE_VMOVLu16bh = 1424, // ARMInstrMVE.td:2789 |
| 1440 | MVE_VMOVLu16th = 1425, // ARMInstrMVE.td:2789 |
| 1441 | MVE_VMOVLu8bh = 1426, // ARMInstrMVE.td:2789 |
| 1442 | MVE_VMOVLu8th = 1427, // ARMInstrMVE.td:2789 |
| 1443 | MVE_VMOVNi16bh = 1428, // ARMInstrMVE.td:4895 |
| 1444 | MVE_VMOVNi16th = 1429, // ARMInstrMVE.td:4896 |
| 1445 | MVE_VMOVNi32bh = 1430, // ARMInstrMVE.td:4895 |
| 1446 | MVE_VMOVNi32th = 1431, // ARMInstrMVE.td:4896 |
| 1447 | MVE_VMOV_from_lane_32 = 1432, // ARMInstrMVE.td:1905 |
| 1448 | MVE_VMOV_from_lane_s16 = 1433, // ARMInstrMVE.td:1906 |
| 1449 | MVE_VMOV_from_lane_s8 = 1434, // ARMInstrMVE.td:1908 |
| 1450 | MVE_VMOV_from_lane_u16 = 1435, // ARMInstrMVE.td:1907 |
| 1451 | MVE_VMOV_from_lane_u8 = 1436, // ARMInstrMVE.td:1909 |
| 1452 | MVE_VMOV_q_rr = 1437, // ARMInstrMVE.td:5963 |
| 1453 | MVE_VMOV_rr_q = 1438, // ARMInstrMVE.td:5970 |
| 1454 | MVE_VMOV_to_lane_16 = 1439, // ARMInstrMVE.td:1912 |
| 1455 | MVE_VMOV_to_lane_32 = 1440, // ARMInstrMVE.td:1911 |
| 1456 | MVE_VMOV_to_lane_8 = 1441, // ARMInstrMVE.td:1913 |
| 1457 | MVE_VMOVimmf32 = 1442, // ARMInstrMVE.td:2640 |
| 1458 | MVE_VMOVimmi16 = 1443, // ARMInstrMVE.td:2633 |
| 1459 | MVE_VMOVimmi32 = 1444, // ARMInstrMVE.td:2636 |
| 1460 | MVE_VMOVimmi64 = 1445, // ARMInstrMVE.td:2639 |
| 1461 | MVE_VMOVimmi8 = 1446, // ARMInstrMVE.td:2632 |
| 1462 | MVE_VMULHs16 = 1447, // ARMInstrMVE.td:4829 |
| 1463 | MVE_VMULHs32 = 1448, // ARMInstrMVE.td:4829 |
| 1464 | MVE_VMULHs8 = 1449, // ARMInstrMVE.td:4829 |
| 1465 | MVE_VMULHu16 = 1450, // ARMInstrMVE.td:4829 |
| 1466 | MVE_VMULHu32 = 1451, // ARMInstrMVE.td:4829 |
| 1467 | MVE_VMULHu8 = 1452, // ARMInstrMVE.td:4829 |
| 1468 | MVE_VMULLBp16 = 1453, // ARMInstrMVE.td:4699 |
| 1469 | MVE_VMULLBp8 = 1454, // ARMInstrMVE.td:4699 |
| 1470 | MVE_VMULLBs16 = 1455, // ARMInstrMVE.td:4699 |
| 1471 | MVE_VMULLBs32 = 1456, // ARMInstrMVE.td:4699 |
| 1472 | MVE_VMULLBs8 = 1457, // ARMInstrMVE.td:4699 |
| 1473 | MVE_VMULLBu16 = 1458, // ARMInstrMVE.td:4699 |
| 1474 | MVE_VMULLBu32 = 1459, // ARMInstrMVE.td:4699 |
| 1475 | MVE_VMULLBu8 = 1460, // ARMInstrMVE.td:4699 |
| 1476 | MVE_VMULLTp16 = 1461, // ARMInstrMVE.td:4699 |
| 1477 | MVE_VMULLTp8 = 1462, // ARMInstrMVE.td:4699 |
| 1478 | MVE_VMULLTs16 = 1463, // ARMInstrMVE.td:4699 |
| 1479 | MVE_VMULLTs32 = 1464, // ARMInstrMVE.td:4699 |
| 1480 | MVE_VMULLTs8 = 1465, // ARMInstrMVE.td:4699 |
| 1481 | MVE_VMULLTu16 = 1466, // ARMInstrMVE.td:4699 |
| 1482 | MVE_VMULLTu32 = 1467, // ARMInstrMVE.td:4699 |
| 1483 | MVE_VMULLTu8 = 1468, // ARMInstrMVE.td:4699 |
| 1484 | MVE_VMUL_qr_f16 = 1469, // ARMInstrMVE.td:5646 |
| 1485 | MVE_VMUL_qr_f32 = 1470, // ARMInstrMVE.td:5646 |
| 1486 | MVE_VMUL_qr_i16 = 1471, // ARMInstrMVE.td:5594 |
| 1487 | MVE_VMUL_qr_i32 = 1472, // ARMInstrMVE.td:5594 |
| 1488 | MVE_VMUL_qr_i8 = 1473, // ARMInstrMVE.td:5594 |
| 1489 | MVE_VMULf16 = 1474, // ARMInstrMVE.td:3657 |
| 1490 | MVE_VMULf32 = 1475, // ARMInstrMVE.td:3657 |
| 1491 | MVE_VMULi16 = 1476, // ARMInstrMVE.td:2048 |
| 1492 | MVE_VMULi32 = 1477, // ARMInstrMVE.td:2048 |
| 1493 | MVE_VMULi8 = 1478, // ARMInstrMVE.td:2048 |
| 1494 | MVE_VMVN = 1479, // ARMInstrMVE.td:1665 |
| 1495 | MVE_VMVNimmi16 = 1480, // ARMInstrMVE.td:2643 |
| 1496 | MVE_VMVNimmi32 = 1481, // ARMInstrMVE.td:2646 |
| 1497 | MVE_VNEGf16 = 1482, // ARMInstrMVE.td:4144 |
| 1498 | MVE_VNEGf32 = 1483, // ARMInstrMVE.td:4144 |
| 1499 | MVE_VNEGs16 = 1484, // ARMInstrMVE.td:2527 |
| 1500 | MVE_VNEGs32 = 1485, // ARMInstrMVE.td:2527 |
| 1501 | MVE_VNEGs8 = 1486, // ARMInstrMVE.td:2527 |
| 1502 | MVE_VORN = 1487, // ARMInstrMVE.td:1706 |
| 1503 | MVE_VORR = 1488, // ARMInstrMVE.td:1707 |
| 1504 | MVE_VORRimmi16 = 1489, // ARMInstrMVE.td:1784 |
| 1505 | MVE_VORRimmi32 = 1490, // ARMInstrMVE.td:1784 |
| 1506 | MVE_VPNOT = 1491, // ARMInstrMVE.td:6925 |
| 1507 | MVE_VPSEL = 1492, // ARMInstrMVE.td:6809 |
| 1508 | MVE_VPST = 1493, // ARMInstrMVE.td:6792 |
| 1509 | MVE_VPTv16i8 = 1494, // ARMInstrMVE.td:6670 |
| 1510 | MVE_VPTv16i8r = 1495, // ARMInstrMVE.td:6714 |
| 1511 | MVE_VPTv16s8 = 1496, // ARMInstrMVE.td:6691 |
| 1512 | MVE_VPTv16s8r = 1497, // ARMInstrMVE.td:6735 |
| 1513 | MVE_VPTv16u8 = 1498, // ARMInstrMVE.td:6681 |
| 1514 | MVE_VPTv16u8r = 1499, // ARMInstrMVE.td:6725 |
| 1515 | MVE_VPTv4f32 = 1500, // ARMInstrMVE.td:6775 |
| 1516 | MVE_VPTv4f32r = 1501, // ARMInstrMVE.td:6789 |
| 1517 | MVE_VPTv4i32 = 1502, // ARMInstrMVE.td:6668 |
| 1518 | MVE_VPTv4i32r = 1503, // ARMInstrMVE.td:6712 |
| 1519 | MVE_VPTv4s32 = 1504, // ARMInstrMVE.td:6689 |
| 1520 | MVE_VPTv4s32r = 1505, // ARMInstrMVE.td:6733 |
| 1521 | MVE_VPTv4u32 = 1506, // ARMInstrMVE.td:6679 |
| 1522 | MVE_VPTv4u32r = 1507, // ARMInstrMVE.td:6723 |
| 1523 | MVE_VPTv8f16 = 1508, // ARMInstrMVE.td:6776 |
| 1524 | MVE_VPTv8f16r = 1509, // ARMInstrMVE.td:6790 |
| 1525 | MVE_VPTv8i16 = 1510, // ARMInstrMVE.td:6669 |
| 1526 | MVE_VPTv8i16r = 1511, // ARMInstrMVE.td:6713 |
| 1527 | MVE_VPTv8s16 = 1512, // ARMInstrMVE.td:6690 |
| 1528 | MVE_VPTv8s16r = 1513, // ARMInstrMVE.td:6734 |
| 1529 | MVE_VPTv8u16 = 1514, // ARMInstrMVE.td:6680 |
| 1530 | MVE_VPTv8u16r = 1515, // ARMInstrMVE.td:6724 |
| 1531 | MVE_VQABSs16 = 1516, // ARMInstrMVE.td:2527 |
| 1532 | MVE_VQABSs32 = 1517, // ARMInstrMVE.td:2527 |
| 1533 | MVE_VQABSs8 = 1518, // ARMInstrMVE.td:2527 |
| 1534 | MVE_VQADD_qr_s16 = 1519, // ARMInstrMVE.td:5323 |
| 1535 | MVE_VQADD_qr_s32 = 1520, // ARMInstrMVE.td:5323 |
| 1536 | MVE_VQADD_qr_s8 = 1521, // ARMInstrMVE.td:5323 |
| 1537 | MVE_VQADD_qr_u16 = 1522, // ARMInstrMVE.td:5323 |
| 1538 | MVE_VQADD_qr_u32 = 1523, // ARMInstrMVE.td:5323 |
| 1539 | MVE_VQADD_qr_u8 = 1524, // ARMInstrMVE.td:5323 |
| 1540 | MVE_VQADDs16 = 1525, // ARMInstrMVE.td:2166 |
| 1541 | MVE_VQADDs32 = 1526, // ARMInstrMVE.td:2166 |
| 1542 | MVE_VQADDs8 = 1527, // ARMInstrMVE.td:2166 |
| 1543 | MVE_VQADDu16 = 1528, // ARMInstrMVE.td:2166 |
| 1544 | MVE_VQADDu32 = 1529, // ARMInstrMVE.td:2166 |
| 1545 | MVE_VQADDu8 = 1530, // ARMInstrMVE.td:2166 |
| 1546 | MVE_VQDMLADHXs16 = 1531, // ARMInstrMVE.td:4595 |
| 1547 | MVE_VQDMLADHXs32 = 1532, // ARMInstrMVE.td:4595 |
| 1548 | MVE_VQDMLADHXs8 = 1533, // ARMInstrMVE.td:4595 |
| 1549 | MVE_VQDMLADHs16 = 1534, // ARMInstrMVE.td:4595 |
| 1550 | MVE_VQDMLADHs32 = 1535, // ARMInstrMVE.td:4595 |
| 1551 | MVE_VQDMLADHs8 = 1536, // ARMInstrMVE.td:4595 |
| 1552 | MVE_VQDMLAH_qrs16 = 1537, // ARMInstrMVE.td:5772 |
| 1553 | MVE_VQDMLAH_qrs32 = 1538, // ARMInstrMVE.td:5772 |
| 1554 | MVE_VQDMLAH_qrs8 = 1539, // ARMInstrMVE.td:5772 |
| 1555 | MVE_VQDMLASH_qrs16 = 1540, // ARMInstrMVE.td:5772 |
| 1556 | MVE_VQDMLASH_qrs32 = 1541, // ARMInstrMVE.td:5772 |
| 1557 | MVE_VQDMLASH_qrs8 = 1542, // ARMInstrMVE.td:5772 |
| 1558 | MVE_VQDMLSDHXs16 = 1543, // ARMInstrMVE.td:4595 |
| 1559 | MVE_VQDMLSDHXs32 = 1544, // ARMInstrMVE.td:4595 |
| 1560 | MVE_VQDMLSDHXs8 = 1545, // ARMInstrMVE.td:4595 |
| 1561 | MVE_VQDMLSDHs16 = 1546, // ARMInstrMVE.td:4595 |
| 1562 | MVE_VQDMLSDHs32 = 1547, // ARMInstrMVE.td:4595 |
| 1563 | MVE_VQDMLSDHs8 = 1548, // ARMInstrMVE.td:4595 |
| 1564 | MVE_VQDMULH_qr_s16 = 1549, // ARMInstrMVE.td:5620 |
| 1565 | MVE_VQDMULH_qr_s32 = 1550, // ARMInstrMVE.td:5620 |
| 1566 | MVE_VQDMULH_qr_s8 = 1551, // ARMInstrMVE.td:5620 |
| 1567 | MVE_VQDMULHi16 = 1552, // ARMInstrMVE.td:2079 |
| 1568 | MVE_VQDMULHi32 = 1553, // ARMInstrMVE.td:2079 |
| 1569 | MVE_VQDMULHi8 = 1554, // ARMInstrMVE.td:2079 |
| 1570 | MVE_VQDMULL_qr_s16bh = 1555, // ARMInstrMVE.td:5368 |
| 1571 | MVE_VQDMULL_qr_s16th = 1556, // ARMInstrMVE.td:5368 |
| 1572 | MVE_VQDMULL_qr_s32bh = 1557, // ARMInstrMVE.td:5368 |
| 1573 | MVE_VQDMULL_qr_s32th = 1558, // ARMInstrMVE.td:5368 |
| 1574 | MVE_VQDMULLs16bh = 1559, // ARMInstrMVE.td:5187 |
| 1575 | MVE_VQDMULLs16th = 1560, // ARMInstrMVE.td:5187 |
| 1576 | MVE_VQDMULLs32bh = 1561, // ARMInstrMVE.td:5187 |
| 1577 | MVE_VQDMULLs32th = 1562, // ARMInstrMVE.td:5187 |
| 1578 | MVE_VQMOVNs16bh = 1563, // ARMInstrMVE.td:4895 |
| 1579 | MVE_VQMOVNs16th = 1564, // ARMInstrMVE.td:4896 |
| 1580 | MVE_VQMOVNs32bh = 1565, // ARMInstrMVE.td:4895 |
| 1581 | MVE_VQMOVNs32th = 1566, // ARMInstrMVE.td:4896 |
| 1582 | MVE_VQMOVNu16bh = 1567, // ARMInstrMVE.td:4895 |
| 1583 | MVE_VQMOVNu16th = 1568, // ARMInstrMVE.td:4896 |
| 1584 | MVE_VQMOVNu32bh = 1569, // ARMInstrMVE.td:4895 |
| 1585 | MVE_VQMOVNu32th = 1570, // ARMInstrMVE.td:4896 |
| 1586 | MVE_VQMOVUNs16bh = 1571, // ARMInstrMVE.td:4895 |
| 1587 | MVE_VQMOVUNs16th = 1572, // ARMInstrMVE.td:4896 |
| 1588 | MVE_VQMOVUNs32bh = 1573, // ARMInstrMVE.td:4895 |
| 1589 | MVE_VQMOVUNs32th = 1574, // ARMInstrMVE.td:4896 |
| 1590 | MVE_VQNEGs16 = 1575, // ARMInstrMVE.td:2527 |
| 1591 | MVE_VQNEGs32 = 1576, // ARMInstrMVE.td:2527 |
| 1592 | MVE_VQNEGs8 = 1577, // ARMInstrMVE.td:2527 |
| 1593 | MVE_VQRDMLADHXs16 = 1578, // ARMInstrMVE.td:4595 |
| 1594 | MVE_VQRDMLADHXs32 = 1579, // ARMInstrMVE.td:4595 |
| 1595 | MVE_VQRDMLADHXs8 = 1580, // ARMInstrMVE.td:4595 |
| 1596 | MVE_VQRDMLADHs16 = 1581, // ARMInstrMVE.td:4595 |
| 1597 | MVE_VQRDMLADHs32 = 1582, // ARMInstrMVE.td:4595 |
| 1598 | MVE_VQRDMLADHs8 = 1583, // ARMInstrMVE.td:4595 |
| 1599 | MVE_VQRDMLAH_qrs16 = 1584, // ARMInstrMVE.td:5772 |
| 1600 | MVE_VQRDMLAH_qrs32 = 1585, // ARMInstrMVE.td:5772 |
| 1601 | MVE_VQRDMLAH_qrs8 = 1586, // ARMInstrMVE.td:5772 |
| 1602 | MVE_VQRDMLASH_qrs16 = 1587, // ARMInstrMVE.td:5772 |
| 1603 | MVE_VQRDMLASH_qrs32 = 1588, // ARMInstrMVE.td:5772 |
| 1604 | MVE_VQRDMLASH_qrs8 = 1589, // ARMInstrMVE.td:5772 |
| 1605 | MVE_VQRDMLSDHXs16 = 1590, // ARMInstrMVE.td:4595 |
| 1606 | MVE_VQRDMLSDHXs32 = 1591, // ARMInstrMVE.td:4595 |
| 1607 | MVE_VQRDMLSDHXs8 = 1592, // ARMInstrMVE.td:4595 |
| 1608 | MVE_VQRDMLSDHs16 = 1593, // ARMInstrMVE.td:4595 |
| 1609 | MVE_VQRDMLSDHs32 = 1594, // ARMInstrMVE.td:4595 |
| 1610 | MVE_VQRDMLSDHs8 = 1595, // ARMInstrMVE.td:4595 |
| 1611 | MVE_VQRDMULH_qr_s16 = 1596, // ARMInstrMVE.td:5620 |
| 1612 | MVE_VQRDMULH_qr_s32 = 1597, // ARMInstrMVE.td:5620 |
| 1613 | MVE_VQRDMULH_qr_s8 = 1598, // ARMInstrMVE.td:5620 |
| 1614 | MVE_VQRDMULHi16 = 1599, // ARMInstrMVE.td:2079 |
| 1615 | MVE_VQRDMULHi32 = 1600, // ARMInstrMVE.td:2079 |
| 1616 | MVE_VQRDMULHi8 = 1601, // ARMInstrMVE.td:2079 |
| 1617 | MVE_VQRSHL_by_vecs16 = 1602, // ARMInstrMVE.td:3181 |
| 1618 | MVE_VQRSHL_by_vecs32 = 1603, // ARMInstrMVE.td:3181 |
| 1619 | MVE_VQRSHL_by_vecs8 = 1604, // ARMInstrMVE.td:3181 |
| 1620 | MVE_VQRSHL_by_vecu16 = 1605, // ARMInstrMVE.td:3181 |
| 1621 | MVE_VQRSHL_by_vecu32 = 1606, // ARMInstrMVE.td:3181 |
| 1622 | MVE_VQRSHL_by_vecu8 = 1607, // ARMInstrMVE.td:3181 |
| 1623 | MVE_VQRSHL_qrs16 = 1608, // ARMInstrMVE.td:5485 |
| 1624 | MVE_VQRSHL_qrs32 = 1609, // ARMInstrMVE.td:5485 |
| 1625 | MVE_VQRSHL_qrs8 = 1610, // ARMInstrMVE.td:5485 |
| 1626 | MVE_VQRSHL_qru16 = 1611, // ARMInstrMVE.td:5485 |
| 1627 | MVE_VQRSHL_qru32 = 1612, // ARMInstrMVE.td:5485 |
| 1628 | MVE_VQRSHL_qru8 = 1613, // ARMInstrMVE.td:5485 |
| 1629 | MVE_VQRSHRNbhs16 = 1614, // ARMInstrMVE.td:3068 |
| 1630 | MVE_VQRSHRNbhs32 = 1615, // ARMInstrMVE.td:3076 |
| 1631 | MVE_VQRSHRNbhu16 = 1616, // ARMInstrMVE.td:3072 |
| 1632 | MVE_VQRSHRNbhu32 = 1617, // ARMInstrMVE.td:3080 |
| 1633 | MVE_VQRSHRNths16 = 1618, // ARMInstrMVE.td:3068 |
| 1634 | MVE_VQRSHRNths32 = 1619, // ARMInstrMVE.td:3076 |
| 1635 | MVE_VQRSHRNthu16 = 1620, // ARMInstrMVE.td:3072 |
| 1636 | MVE_VQRSHRNthu32 = 1621, // ARMInstrMVE.td:3080 |
| 1637 | MVE_VQRSHRUNs16bh = 1622, // ARMInstrMVE.td:3017 |
| 1638 | MVE_VQRSHRUNs16th = 1623, // ARMInstrMVE.td:3021 |
| 1639 | MVE_VQRSHRUNs32bh = 1624, // ARMInstrMVE.td:3025 |
| 1640 | MVE_VQRSHRUNs32th = 1625, // ARMInstrMVE.td:3029 |
| 1641 | MVE_VQSHLU_imms16 = 1626, // ARMInstrMVE.td:3375 |
| 1642 | MVE_VQSHLU_imms32 = 1627, // ARMInstrMVE.td:3379 |
| 1643 | MVE_VQSHLU_imms8 = 1628, // ARMInstrMVE.td:3371 |
| 1644 | MVE_VQSHL_by_vecs16 = 1629, // ARMInstrMVE.td:3181 |
| 1645 | MVE_VQSHL_by_vecs32 = 1630, // ARMInstrMVE.td:3181 |
| 1646 | MVE_VQSHL_by_vecs8 = 1631, // ARMInstrMVE.td:3181 |
| 1647 | MVE_VQSHL_by_vecu16 = 1632, // ARMInstrMVE.td:3181 |
| 1648 | MVE_VQSHL_by_vecu32 = 1633, // ARMInstrMVE.td:3181 |
| 1649 | MVE_VQSHL_by_vecu8 = 1634, // ARMInstrMVE.td:3181 |
| 1650 | MVE_VQSHL_qrs16 = 1635, // ARMInstrMVE.td:5485 |
| 1651 | MVE_VQSHL_qrs32 = 1636, // ARMInstrMVE.td:5485 |
| 1652 | MVE_VQSHL_qrs8 = 1637, // ARMInstrMVE.td:5485 |
| 1653 | MVE_VQSHL_qru16 = 1638, // ARMInstrMVE.td:5485 |
| 1654 | MVE_VQSHL_qru32 = 1639, // ARMInstrMVE.td:5485 |
| 1655 | MVE_VQSHL_qru8 = 1640, // ARMInstrMVE.td:5485 |
| 1656 | MVE_VQSHLimms16 = 1641, // ARMInstrMVE.td:3339 |
| 1657 | MVE_VQSHLimms32 = 1642, // ARMInstrMVE.td:3346 |
| 1658 | MVE_VQSHLimms8 = 1643, // ARMInstrMVE.td:3332 |
| 1659 | MVE_VQSHLimmu16 = 1644, // ARMInstrMVE.td:3342 |
| 1660 | MVE_VQSHLimmu32 = 1645, // ARMInstrMVE.td:3349 |
| 1661 | MVE_VQSHLimmu8 = 1646, // ARMInstrMVE.td:3335 |
| 1662 | MVE_VQSHRNbhs16 = 1647, // ARMInstrMVE.td:3068 |
| 1663 | MVE_VQSHRNbhs32 = 1648, // ARMInstrMVE.td:3076 |
| 1664 | MVE_VQSHRNbhu16 = 1649, // ARMInstrMVE.td:3072 |
| 1665 | MVE_VQSHRNbhu32 = 1650, // ARMInstrMVE.td:3080 |
| 1666 | MVE_VQSHRNths16 = 1651, // ARMInstrMVE.td:3068 |
| 1667 | MVE_VQSHRNths32 = 1652, // ARMInstrMVE.td:3076 |
| 1668 | MVE_VQSHRNthu16 = 1653, // ARMInstrMVE.td:3072 |
| 1669 | MVE_VQSHRNthu32 = 1654, // ARMInstrMVE.td:3080 |
| 1670 | MVE_VQSHRUNs16bh = 1655, // ARMInstrMVE.td:3034 |
| 1671 | MVE_VQSHRUNs16th = 1656, // ARMInstrMVE.td:3038 |
| 1672 | MVE_VQSHRUNs32bh = 1657, // ARMInstrMVE.td:3042 |
| 1673 | MVE_VQSHRUNs32th = 1658, // ARMInstrMVE.td:3046 |
| 1674 | MVE_VQSUB_qr_s16 = 1659, // ARMInstrMVE.td:5323 |
| 1675 | MVE_VQSUB_qr_s32 = 1660, // ARMInstrMVE.td:5323 |
| 1676 | MVE_VQSUB_qr_s8 = 1661, // ARMInstrMVE.td:5323 |
| 1677 | MVE_VQSUB_qr_u16 = 1662, // ARMInstrMVE.td:5323 |
| 1678 | MVE_VQSUB_qr_u32 = 1663, // ARMInstrMVE.td:5323 |
| 1679 | MVE_VQSUB_qr_u8 = 1664, // ARMInstrMVE.td:5323 |
| 1680 | MVE_VQSUBs16 = 1665, // ARMInstrMVE.td:2187 |
| 1681 | MVE_VQSUBs32 = 1666, // ARMInstrMVE.td:2187 |
| 1682 | MVE_VQSUBs8 = 1667, // ARMInstrMVE.td:2187 |
| 1683 | MVE_VQSUBu16 = 1668, // ARMInstrMVE.td:2187 |
| 1684 | MVE_VQSUBu32 = 1669, // ARMInstrMVE.td:2187 |
| 1685 | MVE_VQSUBu8 = 1670, // ARMInstrMVE.td:2187 |
| 1686 | MVE_VREV16_8 = 1671, // ARMInstrMVE.td:1631 |
| 1687 | MVE_VREV32_16 = 1672, // ARMInstrMVE.td:1629 |
| 1688 | MVE_VREV32_8 = 1673, // ARMInstrMVE.td:1628 |
| 1689 | MVE_VREV64_16 = 1674, // ARMInstrMVE.td:1625 |
| 1690 | MVE_VREV64_32 = 1675, // ARMInstrMVE.td:1626 |
| 1691 | MVE_VREV64_8 = 1676, // ARMInstrMVE.td:1624 |
| 1692 | MVE_VRHADDs16 = 1677, // ARMInstrMVE.td:2279 |
| 1693 | MVE_VRHADDs32 = 1678, // ARMInstrMVE.td:2279 |
| 1694 | MVE_VRHADDs8 = 1679, // ARMInstrMVE.td:2279 |
| 1695 | MVE_VRHADDu16 = 1680, // ARMInstrMVE.td:2279 |
| 1696 | MVE_VRHADDu32 = 1681, // ARMInstrMVE.td:2279 |
| 1697 | MVE_VRHADDu8 = 1682, // ARMInstrMVE.td:2279 |
| 1698 | MVE_VRINTf16A = 1683, // ARMInstrMVE.td:3599 |
| 1699 | MVE_VRINTf16M = 1684, // ARMInstrMVE.td:3599 |
| 1700 | MVE_VRINTf16N = 1685, // ARMInstrMVE.td:3599 |
| 1701 | MVE_VRINTf16P = 1686, // ARMInstrMVE.td:3599 |
| 1702 | MVE_VRINTf16X = 1687, // ARMInstrMVE.td:3599 |
| 1703 | MVE_VRINTf16Z = 1688, // ARMInstrMVE.td:3599 |
| 1704 | MVE_VRINTf32A = 1689, // ARMInstrMVE.td:3599 |
| 1705 | MVE_VRINTf32M = 1690, // ARMInstrMVE.td:3599 |
| 1706 | MVE_VRINTf32N = 1691, // ARMInstrMVE.td:3599 |
| 1707 | MVE_VRINTf32P = 1692, // ARMInstrMVE.td:3599 |
| 1708 | MVE_VRINTf32X = 1693, // ARMInstrMVE.td:3599 |
| 1709 | MVE_VRINTf32Z = 1694, // ARMInstrMVE.td:3599 |
| 1710 | MVE_VRMLALDAVHas32 = 1695, // ARMInstrMVE.td:1363 |
| 1711 | MVE_VRMLALDAVHau32 = 1696, // ARMInstrMVE.td:1363 |
| 1712 | MVE_VRMLALDAVHaxs32 = 1697, // ARMInstrMVE.td:1363 |
| 1713 | MVE_VRMLALDAVHs32 = 1698, // ARMInstrMVE.td:1360 |
| 1714 | MVE_VRMLALDAVHu32 = 1699, // ARMInstrMVE.td:1360 |
| 1715 | MVE_VRMLALDAVHxs32 = 1700, // ARMInstrMVE.td:1360 |
| 1716 | MVE_VRMLSLDAVHas32 = 1701, // ARMInstrMVE.td:1363 |
| 1717 | MVE_VRMLSLDAVHaxs32 = 1702, // ARMInstrMVE.td:1363 |
| 1718 | MVE_VRMLSLDAVHs32 = 1703, // ARMInstrMVE.td:1360 |
| 1719 | MVE_VRMLSLDAVHxs32 = 1704, // ARMInstrMVE.td:1360 |
| 1720 | MVE_VRMULHs16 = 1705, // ARMInstrMVE.td:4829 |
| 1721 | MVE_VRMULHs32 = 1706, // ARMInstrMVE.td:4829 |
| 1722 | MVE_VRMULHs8 = 1707, // ARMInstrMVE.td:4829 |
| 1723 | MVE_VRMULHu16 = 1708, // ARMInstrMVE.td:4829 |
| 1724 | MVE_VRMULHu32 = 1709, // ARMInstrMVE.td:4829 |
| 1725 | MVE_VRMULHu8 = 1710, // ARMInstrMVE.td:4829 |
| 1726 | MVE_VRSHL_by_vecs16 = 1711, // ARMInstrMVE.td:3181 |
| 1727 | MVE_VRSHL_by_vecs32 = 1712, // ARMInstrMVE.td:3181 |
| 1728 | MVE_VRSHL_by_vecs8 = 1713, // ARMInstrMVE.td:3181 |
| 1729 | MVE_VRSHL_by_vecu16 = 1714, // ARMInstrMVE.td:3181 |
| 1730 | MVE_VRSHL_by_vecu32 = 1715, // ARMInstrMVE.td:3181 |
| 1731 | MVE_VRSHL_by_vecu8 = 1716, // ARMInstrMVE.td:3181 |
| 1732 | MVE_VRSHL_qrs16 = 1717, // ARMInstrMVE.td:5485 |
| 1733 | MVE_VRSHL_qrs32 = 1718, // ARMInstrMVE.td:5485 |
| 1734 | MVE_VRSHL_qrs8 = 1719, // ARMInstrMVE.td:5485 |
| 1735 | MVE_VRSHL_qru16 = 1720, // ARMInstrMVE.td:5485 |
| 1736 | MVE_VRSHL_qru32 = 1721, // ARMInstrMVE.td:5485 |
| 1737 | MVE_VRSHL_qru8 = 1722, // ARMInstrMVE.td:5485 |
| 1738 | MVE_VRSHRNi16bh = 1723, // ARMInstrMVE.td:2974 |
| 1739 | MVE_VRSHRNi16th = 1724, // ARMInstrMVE.td:2977 |
| 1740 | MVE_VRSHRNi32bh = 1725, // ARMInstrMVE.td:2980 |
| 1741 | MVE_VRSHRNi32th = 1726, // ARMInstrMVE.td:2983 |
| 1742 | MVE_VRSHR_imms16 = 1727, // ARMInstrMVE.td:3410 |
| 1743 | MVE_VRSHR_imms32 = 1728, // ARMInstrMVE.td:3418 |
| 1744 | MVE_VRSHR_imms8 = 1729, // ARMInstrMVE.td:3402 |
| 1745 | MVE_VRSHR_immu16 = 1730, // ARMInstrMVE.td:3414 |
| 1746 | MVE_VRSHR_immu32 = 1731, // ARMInstrMVE.td:3422 |
| 1747 | MVE_VRSHR_immu8 = 1732, // ARMInstrMVE.td:3406 |
| 1748 | MVE_VSBC = 1733, // ARMInstrMVE.td:5163 |
| 1749 | MVE_VSBCI = 1734, // ARMInstrMVE.td:5164 |
| 1750 | MVE_VSHLC = 1735, // ARMInstrMVE.td:2739 |
| 1751 | MVE_VSHLL_imms16bh = 1736, // ARMInstrMVE.td:2881 |
| 1752 | MVE_VSHLL_imms16th = 1737, // ARMInstrMVE.td:2882 |
| 1753 | MVE_VSHLL_imms8bh = 1738, // ARMInstrMVE.td:2877 |
| 1754 | MVE_VSHLL_imms8th = 1739, // ARMInstrMVE.td:2878 |
| 1755 | MVE_VSHLL_immu16bh = 1740, // ARMInstrMVE.td:2883 |
| 1756 | MVE_VSHLL_immu16th = 1741, // ARMInstrMVE.td:2884 |
| 1757 | MVE_VSHLL_immu8bh = 1742, // ARMInstrMVE.td:2879 |
| 1758 | MVE_VSHLL_immu8th = 1743, // ARMInstrMVE.td:2880 |
| 1759 | MVE_VSHLL_lws16bh = 1744, // ARMInstrMVE.td:2903 |
| 1760 | MVE_VSHLL_lws16th = 1745, // ARMInstrMVE.td:2906 |
| 1761 | MVE_VSHLL_lws8bh = 1746, // ARMInstrMVE.td:2903 |
| 1762 | MVE_VSHLL_lws8th = 1747, // ARMInstrMVE.td:2906 |
| 1763 | MVE_VSHLL_lwu16bh = 1748, // ARMInstrMVE.td:2903 |
| 1764 | MVE_VSHLL_lwu16th = 1749, // ARMInstrMVE.td:2906 |
| 1765 | MVE_VSHLL_lwu8bh = 1750, // ARMInstrMVE.td:2903 |
| 1766 | MVE_VSHLL_lwu8th = 1751, // ARMInstrMVE.td:2906 |
| 1767 | MVE_VSHL_by_vecs16 = 1752, // ARMInstrMVE.td:3181 |
| 1768 | MVE_VSHL_by_vecs32 = 1753, // ARMInstrMVE.td:3181 |
| 1769 | MVE_VSHL_by_vecs8 = 1754, // ARMInstrMVE.td:3181 |
| 1770 | MVE_VSHL_by_vecu16 = 1755, // ARMInstrMVE.td:3181 |
| 1771 | MVE_VSHL_by_vecu32 = 1756, // ARMInstrMVE.td:3181 |
| 1772 | MVE_VSHL_by_vecu8 = 1757, // ARMInstrMVE.td:3181 |
| 1773 | MVE_VSHL_immi16 = 1758, // ARMInstrMVE.td:3518 |
| 1774 | MVE_VSHL_immi32 = 1759, // ARMInstrMVE.td:3522 |
| 1775 | MVE_VSHL_immi8 = 1760, // ARMInstrMVE.td:3514 |
| 1776 | MVE_VSHL_qrs16 = 1761, // ARMInstrMVE.td:5485 |
| 1777 | MVE_VSHL_qrs32 = 1762, // ARMInstrMVE.td:5485 |
| 1778 | MVE_VSHL_qrs8 = 1763, // ARMInstrMVE.td:5485 |
| 1779 | MVE_VSHL_qru16 = 1764, // ARMInstrMVE.td:5485 |
| 1780 | MVE_VSHL_qru32 = 1765, // ARMInstrMVE.td:5485 |
| 1781 | MVE_VSHL_qru8 = 1766, // ARMInstrMVE.td:5485 |
| 1782 | MVE_VSHRNi16bh = 1767, // ARMInstrMVE.td:2987 |
| 1783 | MVE_VSHRNi16th = 1768, // ARMInstrMVE.td:2990 |
| 1784 | MVE_VSHRNi32bh = 1769, // ARMInstrMVE.td:2993 |
| 1785 | MVE_VSHRNi32th = 1770, // ARMInstrMVE.td:2996 |
| 1786 | MVE_VSHR_imms16 = 1771, // ARMInstrMVE.td:3482 |
| 1787 | MVE_VSHR_imms32 = 1772, // ARMInstrMVE.td:3492 |
| 1788 | MVE_VSHR_imms8 = 1773, // ARMInstrMVE.td:3472 |
| 1789 | MVE_VSHR_immu16 = 1774, // ARMInstrMVE.td:3487 |
| 1790 | MVE_VSHR_immu32 = 1775, // ARMInstrMVE.td:3497 |
| 1791 | MVE_VSHR_immu8 = 1776, // ARMInstrMVE.td:3477 |
| 1792 | MVE_VSLIimm16 = 1777, // ARMInstrMVE.td:3284 |
| 1793 | MVE_VSLIimm32 = 1778, // ARMInstrMVE.td:3288 |
| 1794 | MVE_VSLIimm8 = 1779, // ARMInstrMVE.td:3280 |
| 1795 | MVE_VSRIimm16 = 1780, // ARMInstrMVE.td:3272 |
| 1796 | MVE_VSRIimm32 = 1781, // ARMInstrMVE.td:3276 |
| 1797 | MVE_VSRIimm8 = 1782, // ARMInstrMVE.td:3268 |
| 1798 | MVE_VST20_16 = 1783, // ARMInstrMVE.td:6115 |
| 1799 | MVE_VST20_16_wb = 1784, // ARMInstrMVE.td:6115 |
| 1800 | MVE_VST20_32 = 1785, // ARMInstrMVE.td:6115 |
| 1801 | MVE_VST20_32_wb = 1786, // ARMInstrMVE.td:6115 |
| 1802 | MVE_VST20_8 = 1787, // ARMInstrMVE.td:6115 |
| 1803 | MVE_VST20_8_wb = 1788, // ARMInstrMVE.td:6115 |
| 1804 | MVE_VST21_16 = 1789, // ARMInstrMVE.td:6115 |
| 1805 | MVE_VST21_16_wb = 1790, // ARMInstrMVE.td:6115 |
| 1806 | MVE_VST21_32 = 1791, // ARMInstrMVE.td:6115 |
| 1807 | MVE_VST21_32_wb = 1792, // ARMInstrMVE.td:6115 |
| 1808 | MVE_VST21_8 = 1793, // ARMInstrMVE.td:6115 |
| 1809 | MVE_VST21_8_wb = 1794, // ARMInstrMVE.td:6115 |
| 1810 | MVE_VST40_16 = 1795, // ARMInstrMVE.td:6115 |
| 1811 | MVE_VST40_16_wb = 1796, // ARMInstrMVE.td:6115 |
| 1812 | MVE_VST40_32 = 1797, // ARMInstrMVE.td:6115 |
| 1813 | MVE_VST40_32_wb = 1798, // ARMInstrMVE.td:6115 |
| 1814 | MVE_VST40_8 = 1799, // ARMInstrMVE.td:6115 |
| 1815 | MVE_VST40_8_wb = 1800, // ARMInstrMVE.td:6115 |
| 1816 | MVE_VST41_16 = 1801, // ARMInstrMVE.td:6115 |
| 1817 | MVE_VST41_16_wb = 1802, // ARMInstrMVE.td:6115 |
| 1818 | MVE_VST41_32 = 1803, // ARMInstrMVE.td:6115 |
| 1819 | MVE_VST41_32_wb = 1804, // ARMInstrMVE.td:6115 |
| 1820 | MVE_VST41_8 = 1805, // ARMInstrMVE.td:6115 |
| 1821 | MVE_VST41_8_wb = 1806, // ARMInstrMVE.td:6115 |
| 1822 | MVE_VST42_16 = 1807, // ARMInstrMVE.td:6115 |
| 1823 | MVE_VST42_16_wb = 1808, // ARMInstrMVE.td:6115 |
| 1824 | MVE_VST42_32 = 1809, // ARMInstrMVE.td:6115 |
| 1825 | MVE_VST42_32_wb = 1810, // ARMInstrMVE.td:6115 |
| 1826 | MVE_VST42_8 = 1811, // ARMInstrMVE.td:6115 |
| 1827 | MVE_VST42_8_wb = 1812, // ARMInstrMVE.td:6115 |
| 1828 | MVE_VST43_16 = 1813, // ARMInstrMVE.td:6115 |
| 1829 | MVE_VST43_16_wb = 1814, // ARMInstrMVE.td:6115 |
| 1830 | MVE_VST43_32 = 1815, // ARMInstrMVE.td:6115 |
| 1831 | MVE_VST43_32_wb = 1816, // ARMInstrMVE.td:6115 |
| 1832 | MVE_VST43_8 = 1817, // ARMInstrMVE.td:6115 |
| 1833 | MVE_VST43_8_wb = 1818, // ARMInstrMVE.td:6115 |
| 1834 | MVE_VSTRB16 = 1819, // ARMInstrMVE.td:6288 |
| 1835 | MVE_VSTRB16_post = 1820, // ARMInstrMVE.td:6301 |
| 1836 | MVE_VSTRB16_pre = 1821, // ARMInstrMVE.td:6293 |
| 1837 | MVE_VSTRB16_rq = 1822, // ARMInstrMVE.td:6469 |
| 1838 | MVE_VSTRB32 = 1823, // ARMInstrMVE.td:6288 |
| 1839 | MVE_VSTRB32_post = 1824, // ARMInstrMVE.td:6301 |
| 1840 | MVE_VSTRB32_pre = 1825, // ARMInstrMVE.td:6293 |
| 1841 | MVE_VSTRB32_rq = 1826, // ARMInstrMVE.td:6469 |
| 1842 | MVE_VSTRB8_rq = 1827, // ARMInstrMVE.td:6469 |
| 1843 | MVE_VSTRBU8 = 1828, // ARMInstrMVE.td:6316 |
| 1844 | MVE_VSTRBU8_post = 1829, // ARMInstrMVE.td:6329 |
| 1845 | MVE_VSTRBU8_pre = 1830, // ARMInstrMVE.td:6321 |
| 1846 | MVE_VSTRD64_qi = 1831, // ARMInstrMVE.td:6534 |
| 1847 | MVE_VSTRD64_qi_pre = 1832, // ARMInstrMVE.td:6535 |
| 1848 | MVE_VSTRD64_rq = 1833, // ARMInstrMVE.td:6408 |
| 1849 | MVE_VSTRD64_rq_u = 1834, // ARMInstrMVE.td:6407 |
| 1850 | MVE_VSTRH16_rq = 1835, // ARMInstrMVE.td:6408 |
| 1851 | MVE_VSTRH16_rq_u = 1836, // ARMInstrMVE.td:6407 |
| 1852 | MVE_VSTRH32 = 1837, // ARMInstrMVE.td:6288 |
| 1853 | MVE_VSTRH32_post = 1838, // ARMInstrMVE.td:6301 |
| 1854 | MVE_VSTRH32_pre = 1839, // ARMInstrMVE.td:6293 |
| 1855 | MVE_VSTRH32_rq = 1840, // ARMInstrMVE.td:6408 |
| 1856 | MVE_VSTRH32_rq_u = 1841, // ARMInstrMVE.td:6407 |
| 1857 | MVE_VSTRHU16 = 1842, // ARMInstrMVE.td:6316 |
| 1858 | MVE_VSTRHU16_post = 1843, // ARMInstrMVE.td:6329 |
| 1859 | MVE_VSTRHU16_pre = 1844, // ARMInstrMVE.td:6321 |
| 1860 | MVE_VSTRW32_qi = 1845, // ARMInstrMVE.td:6534 |
| 1861 | MVE_VSTRW32_qi_pre = 1846, // ARMInstrMVE.td:6535 |
| 1862 | MVE_VSTRW32_rq = 1847, // ARMInstrMVE.td:6408 |
| 1863 | MVE_VSTRW32_rq_u = 1848, // ARMInstrMVE.td:6407 |
| 1864 | MVE_VSTRWU32 = 1849, // ARMInstrMVE.td:6316 |
| 1865 | MVE_VSTRWU32_post = 1850, // ARMInstrMVE.td:6329 |
| 1866 | MVE_VSTRWU32_pre = 1851, // ARMInstrMVE.td:6321 |
| 1867 | MVE_VSUB_qr_f16 = 1852, // ARMInstrMVE.td:5451 |
| 1868 | MVE_VSUB_qr_f32 = 1853, // ARMInstrMVE.td:5451 |
| 1869 | MVE_VSUB_qr_i16 = 1854, // ARMInstrMVE.td:5300 |
| 1870 | MVE_VSUB_qr_i32 = 1855, // ARMInstrMVE.td:5300 |
| 1871 | MVE_VSUB_qr_i8 = 1856, // ARMInstrMVE.td:5300 |
| 1872 | MVE_VSUBf16 = 1857, // ARMInstrMVE.td:3797 |
| 1873 | MVE_VSUBf32 = 1858, // ARMInstrMVE.td:3797 |
| 1874 | MVE_VSUBi16 = 1859, // ARMInstrMVE.td:2123 |
| 1875 | MVE_VSUBi32 = 1860, // ARMInstrMVE.td:2123 |
| 1876 | MVE_VSUBi8 = 1861, // ARMInstrMVE.td:2123 |
| 1877 | MVE_WLSTP_16 = 1862, // ARMInstrMVE.td:7013 |
| 1878 | MVE_WLSTP_32 = 1863, // ARMInstrMVE.td:7014 |
| 1879 | MVE_WLSTP_64 = 1864, // ARMInstrMVE.td:7015 |
| 1880 | MVE_WLSTP_8 = 1865, // ARMInstrMVE.td:7012 |
| 1881 | MVNi = 1866, // ARMInstrInfo.td:4423 |
| 1882 | MVNr = 1867, // ARMInstrInfo.td:4377 |
| 1883 | MVNsi = 1868, // ARMInstrInfo.td:4390 |
| 1884 | MVNsr = 1869, // ARMInstrInfo.td:4405 |
| 1885 | NEON_VMAXNMNDf = 1870, // ARMInstrNEON.td:5753 |
| 1886 | NEON_VMAXNMNDh = 1871, // ARMInstrNEON.td:5761 |
| 1887 | NEON_VMAXNMNQf = 1872, // ARMInstrNEON.td:5757 |
| 1888 | NEON_VMAXNMNQh = 1873, // ARMInstrNEON.td:5765 |
| 1889 | NEON_VMINNMNDf = 1874, // ARMInstrNEON.td:5795 |
| 1890 | NEON_VMINNMNDh = 1875, // ARMInstrNEON.td:5803 |
| 1891 | NEON_VMINNMNQf = 1876, // ARMInstrNEON.td:5799 |
| 1892 | NEON_VMINNMNQh = 1877, // ARMInstrNEON.td:5807 |
| 1893 | ORRri = 1878, // ARMInstrInfo.td:1721 |
| 1894 | ORRrr = 1879, // ARMInstrInfo.td:1734 |
| 1895 | ORRrsi = 1880, // ARMInstrInfo.td:1749 |
| 1896 | ORRrsr = 1881, // ARMInstrInfo.td:1765 |
| 1897 | PKHBT = 1882, // ARMInstrInfo.td:4956 |
| 1898 | PKHTB = 1883, // ARMInstrInfo.td:4973 |
| 1899 | PLDWi12 = 1884, // ARMInstrInfo.td:2464 |
| 1900 | PLDWrs = 1885, // ARMInstrInfo.td:2481 |
| 1901 | PLDi12 = 1886, // ARMInstrInfo.td:2464 |
| 1902 | PLDrs = 1887, // ARMInstrInfo.td:2481 |
| 1903 | PLIi12 = 1888, // ARMInstrInfo.td:2464 |
| 1904 | PLIrs = 1889, // ARMInstrInfo.td:2481 |
| 1905 | QADD = 1890, // ARMInstrInfo.td:4129 |
| 1906 | QADD16 = 1891, // ARMInstrInfo.td:4116 |
| 1907 | QADD8 = 1892, // ARMInstrInfo.td:4115 |
| 1908 | QASX = 1893, // ARMInstrInfo.td:4155 |
| 1909 | QDADD = 1894, // ARMInstrInfo.td:4120 |
| 1910 | QDSUB = 1895, // ARMInstrInfo.td:4123 |
| 1911 | QSAX = 1896, // ARMInstrInfo.td:4156 |
| 1912 | QSUB = 1897, // ARMInstrInfo.td:4126 |
| 1913 | QSUB16 = 1898, // ARMInstrInfo.td:4117 |
| 1914 | QSUB8 = 1899, // ARMInstrInfo.td:4118 |
| 1915 | RBIT = 1900, // ARMInstrInfo.td:4920 |
| 1916 | REV = 1901, // ARMInstrInfo.td:4926 |
| 1917 | REV16 = 1902, // ARMInstrInfo.td:4932 |
| 1918 | REVSH = 1903, // ARMInstrInfo.td:4946 |
| 1919 | RFEDA = 1904, // ARMInstrInfo.td:2929 |
| 1920 | RFEDA_UPD = 1905, // ARMInstrInfo.td:2932 |
| 1921 | RFEDB = 1906, // ARMInstrInfo.td:2935 |
| 1922 | RFEDB_UPD = 1907, // ARMInstrInfo.td:2938 |
| 1923 | RFEIA = 1908, // ARMInstrInfo.td:2941 |
| 1924 | RFEIA_UPD = 1909, // ARMInstrInfo.td:2944 |
| 1925 | RFEIB = 1910, // ARMInstrInfo.td:2947 |
| 1926 | RFEIB_UPD = 1911, // ARMInstrInfo.td:2950 |
| 1927 | RSBri = 1912, // ARMInstrInfo.td:1794 |
| 1928 | RSBrr = 1913, // ARMInstrInfo.td:1807 |
| 1929 | RSBrsi = 1914, // ARMInstrInfo.td:1822 |
| 1930 | RSBrsr = 1915, // ARMInstrInfo.td:1838 |
| 1931 | RSCri = 1916, // ARMInstrInfo.td:2127 |
| 1932 | RSCrr = 1917, // ARMInstrInfo.td:2140 |
| 1933 | RSCrsi = 1918, // ARMInstrInfo.td:2153 |
| 1934 | RSCrsr = 1919, // ARMInstrInfo.td:2168 |
| 1935 | SADD16 = 1920, // ARMInstrInfo.td:4173 |
| 1936 | SADD8 = 1921, // ARMInstrInfo.td:4174 |
| 1937 | SASX = 1922, // ARMInstrInfo.td:4172 |
| 1938 | SB = 1923, // ARMInstrInfo.td:5343 |
| 1939 | SBCri = 1924, // ARMInstrInfo.td:2057 |
| 1940 | SBCrr = 1925, // ARMInstrInfo.td:2070 |
| 1941 | SBCrsi = 1926, // ARMInstrInfo.td:2085 |
| 1942 | SBCrsr = 1927, // ARMInstrInfo.td:2101 |
| 1943 | SBFX = 1928, // ARMInstrInfo.td:3974 |
| 1944 | SDIV = 1929, // ARMInstrInfo.td:4898 |
| 1945 | SEL = 1930, // ARMInstrInfo.td:2390 |
| 1946 | SETEND = 1931, // ARMInstrInfo.td:2503 |
| 1947 | SETPAN = 1932, // ARMInstrInfo.td:5040 |
| 1948 | SHA1C = 1933, // ARMInstrNEON.td:7405 |
| 1949 | SHA1H = 1934, // ARMInstrNEON.td:7402 |
| 1950 | SHA1M = 1935, // ARMInstrNEON.td:7406 |
| 1951 | SHA1P = 1936, // ARMInstrNEON.td:7407 |
| 1952 | SHA1SU0 = 1937, // ARMInstrNEON.td:7408 |
| 1953 | SHA1SU1 = 1938, // ARMInstrNEON.td:7403 |
| 1954 | SHA256H = 1939, // ARMInstrNEON.td:7409 |
| 1955 | SHA256H2 = 1940, // ARMInstrNEON.td:7410 |
| 1956 | SHA256SU0 = 1941, // ARMInstrNEON.td:7404 |
| 1957 | SHA256SU1 = 1942, // ARMInstrNEON.td:7411 |
| 1958 | SHADD16 = 1943, // ARMInstrInfo.td:4188 |
| 1959 | SHADD8 = 1944, // ARMInstrInfo.td:4189 |
| 1960 | SHASX = 1945, // ARMInstrInfo.td:4187 |
| 1961 | SHSAX = 1946, // ARMInstrInfo.td:4190 |
| 1962 | SHSUB16 = 1947, // ARMInstrInfo.td:4191 |
| 1963 | SHSUB8 = 1948, // ARMInstrInfo.td:4192 |
| 1964 | SMC = 1949, // ARMInstrInfo.td:2846 |
| 1965 | SMLABB = 1950, // ARMInstrInfo.td:4707 |
| 1966 | SMLABT = 1951, // ARMInstrInfo.td:4715 |
| 1967 | SMLAD = 1952, // ARMInstrInfo.td:4827 |
| 1968 | SMLADX = 1953, // ARMInstrInfo.td:4832 |
| 1969 | SMLAL = 1954, // ARMInstrInfo.td:4575 |
| 1970 | SMLALBB = 1955, // ARMInstrInfo.td:4770 |
| 1971 | SMLALBT = 1956, // ARMInstrInfo.td:4771 |
| 1972 | SMLALD = 1957, // ARMInstrInfo.td:4837 |
| 1973 | SMLALDX = 1958, // ARMInstrInfo.td:4844 |
| 1974 | SMLALTB = 1959, // ARMInstrInfo.td:4772 |
| 1975 | SMLALTT = 1960, // ARMInstrInfo.td:4773 |
| 1976 | SMLATB = 1961, // ARMInstrInfo.td:4723 |
| 1977 | SMLATT = 1962, // ARMInstrInfo.td:4731 |
| 1978 | SMLAWB = 1963, // ARMInstrInfo.td:4739 |
| 1979 | SMLAWT = 1964, // ARMInstrInfo.td:4747 |
| 1980 | SMLSD = 1965, // ARMInstrInfo.td:4827 |
| 1981 | SMLSDX = 1966, // ARMInstrInfo.td:4832 |
| 1982 | SMLSLD = 1967, // ARMInstrInfo.td:4837 |
| 1983 | SMLSLDX = 1968, // ARMInstrInfo.td:4844 |
| 1984 | SMMLA = 1969, // ARMInstrInfo.td:4639 |
| 1985 | SMMLAR = 1970, // ARMInstrInfo.td:4646 |
| 1986 | SMMLS = 1971, // ARMInstrInfo.td:4653 |
| 1987 | SMMLSR = 1972, // ARMInstrInfo.td:4659 |
| 1988 | SMMUL = 1973, // ARMInstrInfo.td:4623 |
| 1989 | SMMULR = 1974, // ARMInstrInfo.td:4631 |
| 1990 | SMUAD = 1975, // ARMInstrInfo.td:4874 |
| 1991 | SMUADX = 1976, // ARMInstrInfo.td:4877 |
| 1992 | SMULBB = 1977, // ARMInstrInfo.td:4667 |
| 1993 | SMULBT = 1978, // ARMInstrInfo.td:4673 |
| 1994 | SMULL = 1979, // ARMInstrInfo.td:4537 |
| 1995 | SMULTB = 1980, // ARMInstrInfo.td:4679 |
| 1996 | SMULTT = 1981, // ARMInstrInfo.td:4685 |
| 1997 | SMULWB = 1982, // ARMInstrInfo.td:4691 |
| 1998 | SMULWT = 1983, // ARMInstrInfo.td:4697 |
| 1999 | SMUSD = 1984, // ARMInstrInfo.td:4874 |
| 2000 | SMUSDX = 1985, // ARMInstrInfo.td:4877 |
| 2001 | SRSDA = 1986, // ARMInstrInfo.td:2878 |
| 2002 | SRSDA_UPD = 1987, // ARMInstrInfo.td:2881 |
| 2003 | SRSDB = 1988, // ARMInstrInfo.td:2884 |
| 2004 | SRSDB_UPD = 1989, // ARMInstrInfo.td:2887 |
| 2005 | SRSIA = 1990, // ARMInstrInfo.td:2890 |
| 2006 | SRSIA_UPD = 1991, // ARMInstrInfo.td:2893 |
| 2007 | SRSIB = 1992, // ARMInstrInfo.td:2896 |
| 2008 | SRSIB_UPD = 1993, // ARMInstrInfo.td:2899 |
| 2009 | SSAT = 1994, // ARMInstrInfo.td:4235 |
| 2010 | SSAT16 = 1995, // ARMInstrInfo.td:4252 |
| 2011 | SSAX = 1996, // ARMInstrInfo.td:4175 |
| 2012 | SSUB16 = 1997, // ARMInstrInfo.td:4176 |
| 2013 | SSUB8 = 1998, // ARMInstrInfo.td:4177 |
| 2014 | STC2L_OFFSET = 1999, // ARMInstrInfo.td:5694 |
| 2015 | STC2L_OPTION = 2000, // ARMInstrInfo.td:5745 |
| 2016 | STC2L_POST = 2001, // ARMInstrInfo.td:5727 |
| 2017 | STC2L_PRE = 2002, // ARMInstrInfo.td:5711 |
| 2018 | STC2_OFFSET = 2003, // ARMInstrInfo.td:5694 |
| 2019 | STC2_OPTION = 2004, // ARMInstrInfo.td:5745 |
| 2020 | STC2_POST = 2005, // ARMInstrInfo.td:5727 |
| 2021 | STC2_PRE = 2006, // ARMInstrInfo.td:5711 |
| 2022 | STCL_OFFSET = 2007, // ARMInstrInfo.td:5622 |
| 2023 | STCL_OPTION = 2008, // ARMInstrInfo.td:5673 |
| 2024 | STCL_POST = 2009, // ARMInstrInfo.td:5655 |
| 2025 | STCL_PRE = 2010, // ARMInstrInfo.td:5639 |
| 2026 | STC_OFFSET = 2011, // ARMInstrInfo.td:5622 |
| 2027 | STC_OPTION = 2012, // ARMInstrInfo.td:5673 |
| 2028 | STC_POST = 2013, // ARMInstrInfo.td:5655 |
| 2029 | STC_PRE = 2014, // ARMInstrInfo.td:5639 |
| 2030 | STL = 2015, // ARMInstrInfo.td:3623 |
| 2031 | STLB = 2016, // ARMInstrInfo.td:3625 |
| 2032 | STLEX = 2017, // ARMInstrInfo.td:5483 |
| 2033 | STLEXB = 2018, // ARMInstrInfo.td:5475 |
| 2034 | STLEXD = 2019, // ARMInstrInfo.td:5488 |
| 2035 | STLEXH = 2020, // ARMInstrInfo.td:5479 |
| 2036 | STLH = 2021, // ARMInstrInfo.td:3627 |
| 2037 | STMDA = 2022, // ARMInstrInfo.td:3660 |
| 2038 | STMDA_UPD = 2023, // ARMInstrInfo.td:3669 |
| 2039 | STMDB = 2024, // ARMInstrInfo.td:3680 |
| 2040 | STMDB_UPD = 2025, // ARMInstrInfo.td:3689 |
| 2041 | STMIA = 2026, // ARMInstrInfo.td:3640 |
| 2042 | STMIA_UPD = 2027, // ARMInstrInfo.td:3649 |
| 2043 | STMIB = 2028, // ARMInstrInfo.td:3700 |
| 2044 | STMIB_UPD = 2029, // ARMInstrInfo.td:3709 |
| 2045 | STRBT_POST_IMM = 2030, // ARMInstrInfo.td:3537 |
| 2046 | STRBT_POST_REG = 2031, // ARMInstrInfo.td:3518 |
| 2047 | STRB_POST_IMM = 2032, // ARMInstrInfo.td:3371 |
| 2048 | STRB_POST_REG = 2033, // ARMInstrInfo.td:3353 |
| 2049 | STRB_PRE_IMM = 2034, // ARMInstrInfo.td:3327 |
| 2050 | STRB_PRE_REG = 2035, // ARMInstrInfo.td:3340 |
| 2051 | STRBi12 = 2036, // ARMInstrInfo.td:2285 |
| 2052 | STRBrs = 2037, // ARMInstrInfo.td:2296 |
| 2053 | STRD = 2038, // ARMInstrInfo.td:3309 |
| 2054 | STRD_POST = 2039, // ARMInstrInfo.td:3497 |
| 2055 | STRD_PRE = 2040, // ARMInstrInfo.td:3483 |
| 2056 | STREX = 2041, // ARMInstrInfo.td:5465 |
| 2057 | STREXB = 2042, // ARMInstrInfo.td:5457 |
| 2058 | STREXD = 2043, // ARMInstrInfo.td:5470 |
| 2059 | STREXH = 2044, // ARMInstrInfo.td:5461 |
| 2060 | STRH = 2045, // ARMInstrInfo.td:3303 |
| 2061 | STRHTi = 2046, // ARMInstrInfo.td:3599 |
| 2062 | STRHTr = 2047, // ARMInstrInfo.td:3609 |
| 2063 | STRH_POST = 2048, // ARMInstrInfo.td:3463 |
| 2064 | STRH_PRE = 2049, // ARMInstrInfo.td:3449 |
| 2065 | STRT_POST_IMM = 2050, // ARMInstrInfo.td:3577 |
| 2066 | STRT_POST_REG = 2051, // ARMInstrInfo.td:3558 |
| 2067 | STR_POST_IMM = 2052, // ARMInstrInfo.td:3371 |
| 2068 | STR_POST_REG = 2053, // ARMInstrInfo.td:3353 |
| 2069 | STR_PRE_IMM = 2054, // ARMInstrInfo.td:3327 |
| 2070 | STR_PRE_REG = 2055, // ARMInstrInfo.td:3340 |
| 2071 | STRi12 = 2056, // ARMInstrInfo.td:2256 |
| 2072 | STRrs = 2057, // ARMInstrInfo.td:2267 |
| 2073 | SUBri = 2058, // ARMInstrInfo.td:1721 |
| 2074 | SUBrr = 2059, // ARMInstrInfo.td:1734 |
| 2075 | SUBrsi = 2060, // ARMInstrInfo.td:1749 |
| 2076 | SUBrsr = 2061, // ARMInstrInfo.td:1765 |
| 2077 | SVC = 2062, // ARMInstrInfo.td:2856 |
| 2078 | SWP = 2063, // ARMInstrInfo.td:5543 |
| 2079 | SWPB = 2064, // ARMInstrInfo.td:5546 |
| 2080 | SXTAB = 2065, // ARMInstrInfo.td:3909 |
| 2081 | SXTAB16 = 2066, // ARMInstrInfo.td:3926 |
| 2082 | SXTAH = 2067, // ARMInstrInfo.td:3911 |
| 2083 | SXTB = 2068, // ARMInstrInfo.td:3904 |
| 2084 | SXTB16 = 2069, // ARMInstrInfo.td:3920 |
| 2085 | SXTH = 2070, // ARMInstrInfo.td:3906 |
| 2086 | TEQri = 2071, // ARMInstrInfo.td:1926 |
| 2087 | TEQrr = 2072, // ARMInstrInfo.td:1940 |
| 2088 | TEQrsi = 2073, // ARMInstrInfo.td:1957 |
| 2089 | TEQrsr = 2074, // ARMInstrInfo.td:1974 |
| 2090 | TRAP = 2075, // ARMInstrInfo.td:2537 |
| 2091 | TSB = 2076, // ARMInstrInfo.td:5334 |
| 2092 | TSTri = 2077, // ARMInstrInfo.td:1926 |
| 2093 | TSTrr = 2078, // ARMInstrInfo.td:1940 |
| 2094 | TSTrsi = 2079, // ARMInstrInfo.td:1957 |
| 2095 | TSTrsr = 2080, // ARMInstrInfo.td:1974 |
| 2096 | UADD16 = 2081, // ARMInstrInfo.td:4179 |
| 2097 | UADD8 = 2082, // ARMInstrInfo.td:4180 |
| 2098 | UASX = 2083, // ARMInstrInfo.td:4178 |
| 2099 | UBFX = 2084, // ARMInstrInfo.td:3992 |
| 2100 | UDF = 2085, // ARMInstrInfo.td:2519 |
| 2101 | UDIV = 2086, // ARMInstrInfo.td:4904 |
| 2102 | UHADD16 = 2087, // ARMInstrInfo.td:4194 |
| 2103 | UHADD8 = 2088, // ARMInstrInfo.td:4195 |
| 2104 | UHASX = 2089, // ARMInstrInfo.td:4193 |
| 2105 | UHSAX = 2090, // ARMInstrInfo.td:4196 |
| 2106 | UHSUB16 = 2091, // ARMInstrInfo.td:4197 |
| 2107 | UHSUB8 = 2092, // ARMInstrInfo.td:4198 |
| 2108 | UMAAL = 2093, // ARMInstrInfo.td:4586 |
| 2109 | UMLAL = 2094, // ARMInstrInfo.td:4580 |
| 2110 | UMULL = 2095, // ARMInstrInfo.td:4545 |
| 2111 | UQADD16 = 2096, // ARMInstrInfo.td:4151 |
| 2112 | UQADD8 = 2097, // ARMInstrInfo.td:4152 |
| 2113 | UQASX = 2098, // ARMInstrInfo.td:4157 |
| 2114 | UQSAX = 2099, // ARMInstrInfo.td:4158 |
| 2115 | UQSUB16 = 2100, // ARMInstrInfo.td:4153 |
| 2116 | UQSUB8 = 2101, // ARMInstrInfo.td:4154 |
| 2117 | USAD8 = 2102, // ARMInstrInfo.td:4202 |
| 2118 | USADA8 = 2103, // ARMInstrInfo.td:4217 |
| 2119 | USAT = 2104, // ARMInstrInfo.td:4266 |
| 2120 | USAT16 = 2105, // ARMInstrInfo.td:4283 |
| 2121 | USAX = 2106, // ARMInstrInfo.td:4181 |
| 2122 | USUB16 = 2107, // ARMInstrInfo.td:4182 |
| 2123 | USUB8 = 2108, // ARMInstrInfo.td:4183 |
| 2124 | UXTAB = 2109, // ARMInstrInfo.td:3955 |
| 2125 | UXTAB16 = 2110, // ARMInstrInfo.td:3967 |
| 2126 | UXTAH = 2111, // ARMInstrInfo.td:3957 |
| 2127 | UXTB = 2112, // ARMInstrInfo.td:3935 |
| 2128 | UXTB16 = 2113, // ARMInstrInfo.td:3939 |
| 2129 | UXTH = 2114, // ARMInstrInfo.td:3937 |
| 2130 | VABALsv2i64 = 2115, // ARMInstrNEON.td:3995 |
| 2131 | VABALsv4i32 = 2116, // ARMInstrNEON.td:3992 |
| 2132 | VABALsv8i16 = 2117, // ARMInstrNEON.td:3989 |
| 2133 | VABALuv2i64 = 2118, // ARMInstrNEON.td:3995 |
| 2134 | VABALuv4i32 = 2119, // ARMInstrNEON.td:3992 |
| 2135 | VABALuv8i16 = 2120, // ARMInstrNEON.td:3989 |
| 2136 | VABAsv16i8 = 2121, // ARMInstrNEON.td:3891 |
| 2137 | VABAsv2i32 = 2122, // ARMInstrNEON.td:3887 |
| 2138 | VABAsv4i16 = 2123, // ARMInstrNEON.td:3885 |
| 2139 | VABAsv4i32 = 2124, // ARMInstrNEON.td:3895 |
| 2140 | VABAsv8i16 = 2125, // ARMInstrNEON.td:3893 |
| 2141 | VABAsv8i8 = 2126, // ARMInstrNEON.td:3883 |
| 2142 | VABAuv16i8 = 2127, // ARMInstrNEON.td:3891 |
| 2143 | VABAuv2i32 = 2128, // ARMInstrNEON.td:3887 |
| 2144 | VABAuv4i16 = 2129, // ARMInstrNEON.td:3885 |
| 2145 | VABAuv4i32 = 2130, // ARMInstrNEON.td:3895 |
| 2146 | VABAuv8i16 = 2131, // ARMInstrNEON.td:3893 |
| 2147 | VABAuv8i8 = 2132, // ARMInstrNEON.td:3883 |
| 2148 | VABDLsv2i64 = 2133, // ARMInstrNEON.td:3814 |
| 2149 | VABDLsv4i32 = 2134, // ARMInstrNEON.td:3811 |
| 2150 | VABDLsv8i16 = 2135, // ARMInstrNEON.td:3808 |
| 2151 | VABDLuv2i64 = 2136, // ARMInstrNEON.td:3814 |
| 2152 | VABDLuv4i32 = 2137, // ARMInstrNEON.td:3811 |
| 2153 | VABDLuv8i16 = 2138, // ARMInstrNEON.td:3808 |
| 2154 | VABDfd = 2139, // ARMInstrNEON.td:5689 |
| 2155 | VABDfq = 2140, // ARMInstrNEON.td:5691 |
| 2156 | VABDhd = 2141, // ARMInstrNEON.td:5693 |
| 2157 | VABDhq = 2142, // ARMInstrNEON.td:5696 |
| 2158 | VABDsv16i8 = 2143, // ARMInstrNEON.td:3660 |
| 2159 | VABDsv2i32 = 2144, // ARMInstrNEON.td:3601 |
| 2160 | VABDsv4i16 = 2145, // ARMInstrNEON.td:3598 |
| 2161 | VABDsv4i32 = 2146, // ARMInstrNEON.td:3609 |
| 2162 | VABDsv8i16 = 2147, // ARMInstrNEON.td:3606 |
| 2163 | VABDsv8i8 = 2148, // ARMInstrNEON.td:3657 |
| 2164 | VABDuv16i8 = 2149, // ARMInstrNEON.td:3660 |
| 2165 | VABDuv2i32 = 2150, // ARMInstrNEON.td:3601 |
| 2166 | VABDuv4i16 = 2151, // ARMInstrNEON.td:3598 |
| 2167 | VABDuv4i32 = 2152, // ARMInstrNEON.td:3609 |
| 2168 | VABDuv8i16 = 2153, // ARMInstrNEON.td:3606 |
| 2169 | VABDuv8i8 = 2154, // ARMInstrNEON.td:3657 |
| 2170 | VABSD = 2155, // ARMInstrVFP.td:685 |
| 2171 | VABSH = 2156, // ARMInstrVFP.td:699 |
| 2172 | VABSS = 2157, // ARMInstrVFP.td:690 |
| 2173 | VABSfd = 2158, // ARMInstrNEON.td:6151 |
| 2174 | VABSfq = 2159, // ARMInstrNEON.td:6154 |
| 2175 | VABShd = 2160, // ARMInstrNEON.td:6157 |
| 2176 | VABShq = 2161, // ARMInstrNEON.td:6161 |
| 2177 | VABSv16i8 = 2162, // ARMInstrNEON.td:3477 |
| 2178 | VABSv2i32 = 2163, // ARMInstrNEON.td:3473 |
| 2179 | VABSv4i16 = 2164, // ARMInstrNEON.td:3471 |
| 2180 | VABSv4i32 = 2165, // ARMInstrNEON.td:3481 |
| 2181 | VABSv8i16 = 2166, // ARMInstrNEON.td:3479 |
| 2182 | VABSv8i8 = 2167, // ARMInstrNEON.td:3469 |
| 2183 | VACGEfd = 2168, // ARMInstrNEON.td:5241 |
| 2184 | VACGEfq = 2169, // ARMInstrNEON.td:5243 |
| 2185 | VACGEhd = 2170, // ARMInstrNEON.td:5245 |
| 2186 | VACGEhq = 2171, // ARMInstrNEON.td:5248 |
| 2187 | VACGTfd = 2172, // ARMInstrNEON.td:5252 |
| 2188 | VACGTfq = 2173, // ARMInstrNEON.td:5254 |
| 2189 | VACGThd = 2174, // ARMInstrNEON.td:5256 |
| 2190 | VACGThq = 2175, // ARMInstrNEON.td:5259 |
| 2191 | VADDD = 2176, // ARMInstrVFP.td:455 |
| 2192 | VADDH = 2177, // ARMInstrVFP.td:473 |
| 2193 | VADDHNv2i32 = 2178, // ARMInstrNEON.td:3721 |
| 2194 | VADDHNv4i16 = 2179, // ARMInstrNEON.td:3718 |
| 2195 | VADDHNv8i8 = 2180, // ARMInstrNEON.td:3715 |
| 2196 | VADDLsv2i64 = 2181, // ARMInstrNEON.td:3763 |
| 2197 | VADDLsv4i32 = 2182, // ARMInstrNEON.td:3760 |
| 2198 | VADDLsv8i16 = 2183, // ARMInstrNEON.td:3757 |
| 2199 | VADDLuv2i64 = 2184, // ARMInstrNEON.td:3763 |
| 2200 | VADDLuv4i32 = 2185, // ARMInstrNEON.td:3760 |
| 2201 | VADDLuv8i16 = 2186, // ARMInstrNEON.td:3757 |
| 2202 | VADDS = 2187, // ARMInstrVFP.td:462 |
| 2203 | VADDWsv2i64 = 2188, // ARMInstrNEON.td:3831 |
| 2204 | VADDWsv4i32 = 2189, // ARMInstrNEON.td:3828 |
| 2205 | VADDWsv8i16 = 2190, // ARMInstrNEON.td:3825 |
| 2206 | VADDWuv2i64 = 2191, // ARMInstrNEON.td:3831 |
| 2207 | VADDWuv4i32 = 2192, // ARMInstrNEON.td:3828 |
| 2208 | VADDWuv8i16 = 2193, // ARMInstrNEON.td:3825 |
| 2209 | VADDfd = 2194, // ARMInstrNEON.td:4290 |
| 2210 | VADDfq = 2195, // ARMInstrNEON.td:4292 |
| 2211 | VADDhd = 2196, // ARMInstrNEON.td:4294 |
| 2212 | VADDhq = 2197, // ARMInstrNEON.td:4297 |
| 2213 | VADDv16i8 = 2198, // ARMInstrNEON.td:3554 |
| 2214 | VADDv1i64 = 2199, // ARMInstrNEON.td:3580 |
| 2215 | VADDv2i32 = 2200, // ARMInstrNEON.td:3549 |
| 2216 | VADDv2i64 = 2201, // ARMInstrNEON.td:3583 |
| 2217 | VADDv4i16 = 2202, // ARMInstrNEON.td:3546 |
| 2218 | VADDv4i32 = 2203, // ARMInstrNEON.td:3560 |
| 2219 | VADDv8i16 = 2204, // ARMInstrNEON.td:3557 |
| 2220 | VADDv8i8 = 2205, // ARMInstrNEON.td:3543 |
| 2221 | VANDd = 2206, // ARMInstrNEON.td:5361 |
| 2222 | VANDq = 2207, // ARMInstrNEON.td:5363 |
| 2223 | VBF16MALBQ = 2208, // ARMInstrNEON.td:9293 |
| 2224 | VBF16MALBQI = 2209, // ARMInstrNEON.td:9296 |
| 2225 | VBF16MALTQ = 2210, // ARMInstrNEON.td:9292 |
| 2226 | VBF16MALTQI = 2211, // ARMInstrNEON.td:9296 |
| 2227 | VBICd = 2212, // ARMInstrNEON.td:5440 |
| 2228 | VBICiv2i32 = 2213, // ARMInstrNEON.td:5466 |
| 2229 | VBICiv4i16 = 2214, // ARMInstrNEON.td:5457 |
| 2230 | VBICiv4i32 = 2215, // ARMInstrNEON.td:5484 |
| 2231 | VBICiv8i16 = 2216, // ARMInstrNEON.td:5475 |
| 2232 | VBICq = 2217, // ARMInstrNEON.td:5445 |
| 2233 | VBIFd = 2218, // ARMInstrNEON.td:5654 |
| 2234 | VBIFq = 2219, // ARMInstrNEON.td:5659 |
| 2235 | VBITd = 2220, // ARMInstrNEON.td:5667 |
| 2236 | VBITq = 2221, // ARMInstrNEON.td:5672 |
| 2237 | VBSLd = 2222, // ARMInstrNEON.td:5640 |
| 2238 | VBSLq = 2223, // ARMInstrNEON.td:5646 |
| 2239 | VBSPd = 2224, // ARMInstrNEON.td:5571 |
| 2240 | VBSPq = 2225, // ARMInstrNEON.td:5604 |
| 2241 | VCADDv2f32 = 2226, // ARMInstrNEON.td:5055 |
| 2242 | VCADDv4f16 = 2227, // ARMInstrNEON.td:5045 |
| 2243 | VCADDv4f32 = 2228, // ARMInstrNEON.td:5059 |
| 2244 | VCADDv8f16 = 2229, // ARMInstrNEON.td:5049 |
| 2245 | VCEQfd = 2230, // ARMInstrNEON.td:5179 |
| 2246 | VCEQfq = 2231, // ARMInstrNEON.td:5181 |
| 2247 | VCEQhd = 2232, // ARMInstrNEON.td:5183 |
| 2248 | VCEQhq = 2233, // ARMInstrNEON.td:5186 |
| 2249 | VCEQv16i8 = 2234, // ARMInstrNEON.td:3450 |
| 2250 | VCEQv2i32 = 2235, // ARMInstrNEON.td:3445 |
| 2251 | VCEQv4i16 = 2236, // ARMInstrNEON.td:3442 |
| 2252 | VCEQv4i32 = 2237, // ARMInstrNEON.td:3456 |
| 2253 | VCEQv8i16 = 2238, // ARMInstrNEON.td:3453 |
| 2254 | VCEQv8i8 = 2239, // ARMInstrNEON.td:3439 |
| 2255 | VCEQzv16i8 = 2240, // ARMInstrNEON.td:3381 |
| 2256 | VCEQzv2f32 = 2241, // ARMInstrNEON.td:3366 |
| 2257 | VCEQzv2i32 = 2242, // ARMInstrNEON.td:3362 |
| 2258 | VCEQzv4f16 = 2243, // ARMInstrNEON.td:3372 |
| 2259 | VCEQzv4f32 = 2244, // ARMInstrNEON.td:3393 |
| 2260 | VCEQzv4i16 = 2245, // ARMInstrNEON.td:3358 |
| 2261 | VCEQzv4i32 = 2246, // ARMInstrNEON.td:3389 |
| 2262 | VCEQzv8f16 = 2247, // ARMInstrNEON.td:3399 |
| 2263 | VCEQzv8i16 = 2248, // ARMInstrNEON.td:3385 |
| 2264 | VCEQzv8i8 = 2249, // ARMInstrNEON.td:3354 |
| 2265 | VCGEfd = 2250, // ARMInstrNEON.td:5199 |
| 2266 | VCGEfq = 2251, // ARMInstrNEON.td:5201 |
| 2267 | VCGEhd = 2252, // ARMInstrNEON.td:5203 |
| 2268 | VCGEhq = 2253, // ARMInstrNEON.td:5206 |
| 2269 | VCGEsv16i8 = 2254, // ARMInstrNEON.td:3450 |
| 2270 | VCGEsv2i32 = 2255, // ARMInstrNEON.td:3445 |
| 2271 | VCGEsv4i16 = 2256, // ARMInstrNEON.td:3442 |
| 2272 | VCGEsv4i32 = 2257, // ARMInstrNEON.td:3456 |
| 2273 | VCGEsv8i16 = 2258, // ARMInstrNEON.td:3453 |
| 2274 | VCGEsv8i8 = 2259, // ARMInstrNEON.td:3439 |
| 2275 | VCGEuv16i8 = 2260, // ARMInstrNEON.td:3450 |
| 2276 | VCGEuv2i32 = 2261, // ARMInstrNEON.td:3445 |
| 2277 | VCGEuv4i16 = 2262, // ARMInstrNEON.td:3442 |
| 2278 | VCGEuv4i32 = 2263, // ARMInstrNEON.td:3456 |
| 2279 | VCGEuv8i16 = 2264, // ARMInstrNEON.td:3453 |
| 2280 | VCGEuv8i8 = 2265, // ARMInstrNEON.td:3439 |
| 2281 | VCGEzv16i8 = 2266, // ARMInstrNEON.td:3381 |
| 2282 | VCGEzv2f32 = 2267, // ARMInstrNEON.td:3366 |
| 2283 | VCGEzv2i32 = 2268, // ARMInstrNEON.td:3362 |
| 2284 | VCGEzv4f16 = 2269, // ARMInstrNEON.td:3372 |
| 2285 | VCGEzv4f32 = 2270, // ARMInstrNEON.td:3393 |
| 2286 | VCGEzv4i16 = 2271, // ARMInstrNEON.td:3358 |
| 2287 | VCGEzv4i32 = 2272, // ARMInstrNEON.td:3389 |
| 2288 | VCGEzv8f16 = 2273, // ARMInstrNEON.td:3399 |
| 2289 | VCGEzv8i16 = 2274, // ARMInstrNEON.td:3385 |
| 2290 | VCGEzv8i8 = 2275, // ARMInstrNEON.td:3354 |
| 2291 | VCGTfd = 2276, // ARMInstrNEON.td:5222 |
| 2292 | VCGTfq = 2277, // ARMInstrNEON.td:5224 |
| 2293 | VCGThd = 2278, // ARMInstrNEON.td:5226 |
| 2294 | VCGThq = 2279, // ARMInstrNEON.td:5229 |
| 2295 | VCGTsv16i8 = 2280, // ARMInstrNEON.td:3450 |
| 2296 | VCGTsv2i32 = 2281, // ARMInstrNEON.td:3445 |
| 2297 | VCGTsv4i16 = 2282, // ARMInstrNEON.td:3442 |
| 2298 | VCGTsv4i32 = 2283, // ARMInstrNEON.td:3456 |
| 2299 | VCGTsv8i16 = 2284, // ARMInstrNEON.td:3453 |
| 2300 | VCGTsv8i8 = 2285, // ARMInstrNEON.td:3439 |
| 2301 | VCGTuv16i8 = 2286, // ARMInstrNEON.td:3450 |
| 2302 | VCGTuv2i32 = 2287, // ARMInstrNEON.td:3445 |
| 2303 | VCGTuv4i16 = 2288, // ARMInstrNEON.td:3442 |
| 2304 | VCGTuv4i32 = 2289, // ARMInstrNEON.td:3456 |
| 2305 | VCGTuv8i16 = 2290, // ARMInstrNEON.td:3453 |
| 2306 | VCGTuv8i8 = 2291, // ARMInstrNEON.td:3439 |
| 2307 | VCGTzv16i8 = 2292, // ARMInstrNEON.td:3381 |
| 2308 | VCGTzv2f32 = 2293, // ARMInstrNEON.td:3366 |
| 2309 | VCGTzv2i32 = 2294, // ARMInstrNEON.td:3362 |
| 2310 | VCGTzv4f16 = 2295, // ARMInstrNEON.td:3372 |
| 2311 | VCGTzv4f32 = 2296, // ARMInstrNEON.td:3393 |
| 2312 | VCGTzv4i16 = 2297, // ARMInstrNEON.td:3358 |
| 2313 | VCGTzv4i32 = 2298, // ARMInstrNEON.td:3389 |
| 2314 | VCGTzv8f16 = 2299, // ARMInstrNEON.td:3399 |
| 2315 | VCGTzv8i16 = 2300, // ARMInstrNEON.td:3385 |
| 2316 | VCGTzv8i8 = 2301, // ARMInstrNEON.td:3354 |
| 2317 | VCLEzv16i8 = 2302, // ARMInstrNEON.td:3381 |
| 2318 | VCLEzv2f32 = 2303, // ARMInstrNEON.td:3366 |
| 2319 | VCLEzv2i32 = 2304, // ARMInstrNEON.td:3362 |
| 2320 | VCLEzv4f16 = 2305, // ARMInstrNEON.td:3372 |
| 2321 | VCLEzv4f32 = 2306, // ARMInstrNEON.td:3393 |
| 2322 | VCLEzv4i16 = 2307, // ARMInstrNEON.td:3358 |
| 2323 | VCLEzv4i32 = 2308, // ARMInstrNEON.td:3389 |
| 2324 | VCLEzv8f16 = 2309, // ARMInstrNEON.td:3399 |
| 2325 | VCLEzv8i16 = 2310, // ARMInstrNEON.td:3385 |
| 2326 | VCLEzv8i8 = 2311, // ARMInstrNEON.td:3354 |
| 2327 | VCLSv16i8 = 2312, // ARMInstrNEON.td:3477 |
| 2328 | VCLSv2i32 = 2313, // ARMInstrNEON.td:3473 |
| 2329 | VCLSv4i16 = 2314, // ARMInstrNEON.td:3471 |
| 2330 | VCLSv4i32 = 2315, // ARMInstrNEON.td:3481 |
| 2331 | VCLSv8i16 = 2316, // ARMInstrNEON.td:3479 |
| 2332 | VCLSv8i8 = 2317, // ARMInstrNEON.td:3469 |
| 2333 | VCLTzv16i8 = 2318, // ARMInstrNEON.td:3381 |
| 2334 | VCLTzv2f32 = 2319, // ARMInstrNEON.td:3366 |
| 2335 | VCLTzv2i32 = 2320, // ARMInstrNEON.td:3362 |
| 2336 | VCLTzv4f16 = 2321, // ARMInstrNEON.td:3372 |
| 2337 | VCLTzv4f32 = 2322, // ARMInstrNEON.td:3393 |
| 2338 | VCLTzv4i16 = 2323, // ARMInstrNEON.td:3358 |
| 2339 | VCLTzv4i32 = 2324, // ARMInstrNEON.td:3389 |
| 2340 | VCLTzv8f16 = 2325, // ARMInstrNEON.td:3399 |
| 2341 | VCLTzv8i16 = 2326, // ARMInstrNEON.td:3385 |
| 2342 | VCLTzv8i8 = 2327, // ARMInstrNEON.td:3354 |
| 2343 | VCLZv16i8 = 2328, // ARMInstrNEON.td:3477 |
| 2344 | VCLZv2i32 = 2329, // ARMInstrNEON.td:3473 |
| 2345 | VCLZv4i16 = 2330, // ARMInstrNEON.td:3471 |
| 2346 | VCLZv4i32 = 2331, // ARMInstrNEON.td:3481 |
| 2347 | VCLZv8i16 = 2332, // ARMInstrNEON.td:3479 |
| 2348 | VCLZv8i8 = 2333, // ARMInstrNEON.td:3469 |
| 2349 | VCMLAv2f32 = 2334, // ARMInstrNEON.td:5033 |
| 2350 | VCMLAv2f32_indexed = 2335, // ARMInstrNEON.td:5082 |
| 2351 | VCMLAv4f16 = 2336, // ARMInstrNEON.td:5025 |
| 2352 | VCMLAv4f16_indexed = 2337, // ARMInstrNEON.td:5070 |
| 2353 | VCMLAv4f32 = 2338, // ARMInstrNEON.td:5036 |
| 2354 | VCMLAv4f32_indexed = 2339, // ARMInstrNEON.td:5087 |
| 2355 | VCMLAv8f16 = 2340, // ARMInstrNEON.td:5028 |
| 2356 | VCMLAv8f16_indexed = 2341, // ARMInstrNEON.td:5075 |
| 2357 | VCMPD = 2342, // ARMInstrVFP.td:661 |
| 2358 | VCMPED = 2343, // ARMInstrVFP.td:642 |
| 2359 | VCMPEH = 2344, // ARMInstrVFP.td:656 |
| 2360 | VCMPES = 2345, // ARMInstrVFP.td:647 |
| 2361 | VCMPEZD = 2346, // ARMInstrVFP.td:705 |
| 2362 | VCMPEZH = 2347, // ARMInstrVFP.td:725 |
| 2363 | VCMPEZS = 2348, // ARMInstrVFP.td:713 |
| 2364 | VCMPH = 2349, // ARMInstrVFP.td:675 |
| 2365 | VCMPS = 2350, // ARMInstrVFP.td:666 |
| 2366 | VCMPZD = 2351, // ARMInstrVFP.td:733 |
| 2367 | VCMPZH = 2352, // ARMInstrVFP.td:753 |
| 2368 | VCMPZS = 2353, // ARMInstrVFP.td:741 |
| 2369 | VCNTd = 2354, // ARMInstrNEON.td:6240 |
| 2370 | VCNTq = 2355, // ARMInstrNEON.td:6243 |
| 2371 | VCVTANSDf = 2356, // ARMInstrNEON.td:6881 |
| 2372 | VCVTANSDh = 2357, // ARMInstrNEON.td:6889 |
| 2373 | VCVTANSQf = 2358, // ARMInstrNEON.td:6883 |
| 2374 | VCVTANSQh = 2359, // ARMInstrNEON.td:6892 |
| 2375 | VCVTANUDf = 2360, // ARMInstrNEON.td:6885 |
| 2376 | VCVTANUDh = 2361, // ARMInstrNEON.td:6895 |
| 2377 | VCVTANUQf = 2362, // ARMInstrNEON.td:6887 |
| 2378 | VCVTANUQh = 2363, // ARMInstrNEON.td:6898 |
| 2379 | VCVTASD = 2364, // ARMInstrVFP.td:994 |
| 2380 | VCVTASH = 2365, // ARMInstrVFP.td:962 |
| 2381 | VCVTASS = 2366, // ARMInstrVFP.td:978 |
| 2382 | VCVTAUD = 2367, // ARMInstrVFP.td:1009 |
| 2383 | VCVTAUH = 2368, // ARMInstrVFP.td:970 |
| 2384 | VCVTAUS = 2369, // ARMInstrVFP.td:986 |
| 2385 | VCVTBDH = 2370, // ARMInstrVFP.td:900 |
| 2386 | VCVTBHD = 2371, // ARMInstrVFP.td:876 |
| 2387 | VCVTBHS = 2372, // ARMInstrVFP.td:810 |
| 2388 | VCVTBSH = 2373, // ARMInstrVFP.td:822 |
| 2389 | VCVTDS = 2374, // ARMInstrVFP.td:763 |
| 2390 | VCVTMNSDf = 2375, // ARMInstrNEON.td:6881 |
| 2391 | VCVTMNSDh = 2376, // ARMInstrNEON.td:6889 |
| 2392 | VCVTMNSQf = 2377, // ARMInstrNEON.td:6883 |
| 2393 | VCVTMNSQh = 2378, // ARMInstrNEON.td:6892 |
| 2394 | VCVTMNUDf = 2379, // ARMInstrNEON.td:6885 |
| 2395 | VCVTMNUDh = 2380, // ARMInstrNEON.td:6895 |
| 2396 | VCVTMNUQf = 2381, // ARMInstrNEON.td:6887 |
| 2397 | VCVTMNUQh = 2382, // ARMInstrNEON.td:6898 |
| 2398 | VCVTMSD = 2383, // ARMInstrVFP.td:994 |
| 2399 | VCVTMSH = 2384, // ARMInstrVFP.td:962 |
| 2400 | VCVTMSS = 2385, // ARMInstrVFP.td:978 |
| 2401 | VCVTMUD = 2386, // ARMInstrVFP.td:1009 |
| 2402 | VCVTMUH = 2387, // ARMInstrVFP.td:970 |
| 2403 | VCVTMUS = 2388, // ARMInstrVFP.td:986 |
| 2404 | VCVTNNSDf = 2389, // ARMInstrNEON.td:6881 |
| 2405 | VCVTNNSDh = 2390, // ARMInstrNEON.td:6889 |
| 2406 | VCVTNNSQf = 2391, // ARMInstrNEON.td:6883 |
| 2407 | VCVTNNSQh = 2392, // ARMInstrNEON.td:6892 |
| 2408 | VCVTNNUDf = 2393, // ARMInstrNEON.td:6885 |
| 2409 | VCVTNNUDh = 2394, // ARMInstrNEON.td:6895 |
| 2410 | VCVTNNUQf = 2395, // ARMInstrNEON.td:6887 |
| 2411 | VCVTNNUQh = 2396, // ARMInstrNEON.td:6898 |
| 2412 | VCVTNSD = 2397, // ARMInstrVFP.td:994 |
| 2413 | VCVTNSH = 2398, // ARMInstrVFP.td:962 |
| 2414 | VCVTNSS = 2399, // ARMInstrVFP.td:978 |
| 2415 | VCVTNUD = 2400, // ARMInstrVFP.td:1009 |
| 2416 | VCVTNUH = 2401, // ARMInstrVFP.td:970 |
| 2417 | VCVTNUS = 2402, // ARMInstrVFP.td:986 |
| 2418 | VCVTPNSDf = 2403, // ARMInstrNEON.td:6881 |
| 2419 | VCVTPNSDh = 2404, // ARMInstrNEON.td:6889 |
| 2420 | VCVTPNSQf = 2405, // ARMInstrNEON.td:6883 |
| 2421 | VCVTPNSQh = 2406, // ARMInstrNEON.td:6892 |
| 2422 | VCVTPNUDf = 2407, // ARMInstrNEON.td:6885 |
| 2423 | VCVTPNUDh = 2408, // ARMInstrNEON.td:6895 |
| 2424 | VCVTPNUQf = 2409, // ARMInstrNEON.td:6887 |
| 2425 | VCVTPNUQh = 2410, // ARMInstrNEON.td:6898 |
| 2426 | VCVTPSD = 2411, // ARMInstrVFP.td:994 |
| 2427 | VCVTPSH = 2412, // ARMInstrVFP.td:962 |
| 2428 | VCVTPSS = 2413, // ARMInstrVFP.td:978 |
| 2429 | VCVTPUD = 2414, // ARMInstrVFP.td:1009 |
| 2430 | VCVTPUH = 2415, // ARMInstrVFP.td:970 |
| 2431 | VCVTPUS = 2416, // ARMInstrVFP.td:986 |
| 2432 | VCVTSD = 2417, // ARMInstrVFP.td:784 |
| 2433 | VCVTTDH = 2418, // ARMInstrVFP.td:941 |
| 2434 | VCVTTHD = 2419, // ARMInstrVFP.td:926 |
| 2435 | VCVTTHS = 2420, // ARMInstrVFP.td:844 |
| 2436 | VCVTTSH = 2421, // ARMInstrVFP.td:858 |
| 2437 | VCVTf2h = 2422, // ARMInstrNEON.td:6990 |
| 2438 | VCVTf2sd = 2423, // ARMInstrNEON.td:6833 |
| 2439 | VCVTf2sq = 2424, // ARMInstrNEON.td:6842 |
| 2440 | VCVTf2ud = 2425, // ARMInstrNEON.td:6835 |
| 2441 | VCVTf2uq = 2426, // ARMInstrNEON.td:6844 |
| 2442 | VCVTf2xsd = 2427, // ARMInstrNEON.td:6911 |
| 2443 | VCVTf2xsq = 2428, // ARMInstrNEON.td:6932 |
| 2444 | VCVTf2xud = 2429, // ARMInstrNEON.td:6913 |
| 2445 | VCVTf2xuq = 2430, // ARMInstrNEON.td:6934 |
| 2446 | VCVTh2f = 2431, // ARMInstrNEON.td:6994 |
| 2447 | VCVTh2sd = 2432, // ARMInstrNEON.td:6851 |
| 2448 | VCVTh2sq = 2433, // ARMInstrNEON.td:6864 |
| 2449 | VCVTh2ud = 2434, // ARMInstrNEON.td:6854 |
| 2450 | VCVTh2uq = 2435, // ARMInstrNEON.td:6867 |
| 2451 | VCVTh2xsd = 2436, // ARMInstrNEON.td:6920 |
| 2452 | VCVTh2xsq = 2437, // ARMInstrNEON.td:6941 |
| 2453 | VCVTh2xud = 2438, // ARMInstrNEON.td:6922 |
| 2454 | VCVTh2xuq = 2439, // ARMInstrNEON.td:6943 |
| 2455 | VCVTs2fd = 2440, // ARMInstrNEON.td:6837 |
| 2456 | VCVTs2fq = 2441, // ARMInstrNEON.td:6846 |
| 2457 | VCVTs2hd = 2442, // ARMInstrNEON.td:6857 |
| 2458 | VCVTs2hq = 2443, // ARMInstrNEON.td:6870 |
| 2459 | VCVTu2fd = 2444, // ARMInstrNEON.td:6839 |
| 2460 | VCVTu2fq = 2445, // ARMInstrNEON.td:6848 |
| 2461 | VCVTu2hd = 2446, // ARMInstrNEON.td:6860 |
| 2462 | VCVTu2hq = 2447, // ARMInstrNEON.td:6873 |
| 2463 | VCVTxs2fd = 2448, // ARMInstrNEON.td:6915 |
| 2464 | VCVTxs2fq = 2449, // ARMInstrNEON.td:6936 |
| 2465 | VCVTxs2hd = 2450, // ARMInstrNEON.td:6924 |
| 2466 | VCVTxs2hq = 2451, // ARMInstrNEON.td:6945 |
| 2467 | VCVTxu2fd = 2452, // ARMInstrNEON.td:6917 |
| 2468 | VCVTxu2fq = 2453, // ARMInstrNEON.td:6938 |
| 2469 | VCVTxu2hd = 2454, // ARMInstrNEON.td:6926 |
| 2470 | VCVTxu2hq = 2455, // ARMInstrNEON.td:6947 |
| 2471 | VDIVD = 2456, // ARMInstrVFP.td:505 |
| 2472 | VDIVH = 2457, // ARMInstrVFP.td:519 |
| 2473 | VDIVS = 2458, // ARMInstrVFP.td:512 |
| 2474 | VDUP16d = 2459, // ARMInstrNEON.td:6687 |
| 2475 | VDUP16q = 2460, // ARMInstrNEON.td:6691 |
| 2476 | VDUP32d = 2461, // ARMInstrNEON.td:6688 |
| 2477 | VDUP32q = 2462, // ARMInstrNEON.td:6692 |
| 2478 | VDUP8d = 2463, // ARMInstrNEON.td:6686 |
| 2479 | VDUP8q = 2464, // ARMInstrNEON.td:6690 |
| 2480 | VDUPLN16d = 2465, // ARMInstrNEON.td:6727 |
| 2481 | VDUPLN16q = 2466, // ARMInstrNEON.td:6739 |
| 2482 | VDUPLN32d = 2467, // ARMInstrNEON.td:6731 |
| 2483 | VDUPLN32q = 2468, // ARMInstrNEON.td:6743 |
| 2484 | VDUPLN8d = 2469, // ARMInstrNEON.td:6723 |
| 2485 | VDUPLN8q = 2470, // ARMInstrNEON.td:6735 |
| 2486 | VEORd = 2471, // ARMInstrNEON.td:5367 |
| 2487 | VEORq = 2472, // ARMInstrNEON.td:5369 |
| 2488 | VEXTd16 = 2473, // ARMInstrNEON.td:7134 |
| 2489 | VEXTd32 = 2474, // ARMInstrNEON.td:7145 |
| 2490 | VEXTd8 = 2475, // ARMInstrNEON.td:7131 |
| 2491 | VEXTq16 = 2476, // ARMInstrNEON.td:7157 |
| 2492 | VEXTq32 = 2477, // ARMInstrNEON.td:7168 |
| 2493 | VEXTq64 = 2478, // ARMInstrNEON.td:7172 |
| 2494 | VEXTq8 = 2479, // ARMInstrNEON.td:7154 |
| 2495 | VFMAD = 2480, // ARMInstrVFP.td:2301 |
| 2496 | VFMAH = 2481, // ARMInstrVFP.td:2324 |
| 2497 | VFMALD = 2482, // ARMInstrNEON.td:5322 |
| 2498 | VFMALDI = 2483, // ARMInstrNEON.td:5326 |
| 2499 | VFMALQ = 2484, // ARMInstrNEON.td:5324 |
| 2500 | VFMALQI = 2485, // ARMInstrNEON.td:5328 |
| 2501 | VFMAS = 2486, // ARMInstrVFP.td:2311 |
| 2502 | VFMAfd = 2487, // ARMInstrNEON.td:4787 |
| 2503 | VFMAfq = 2488, // ARMInstrNEON.td:4791 |
| 2504 | VFMAhd = 2489, // ARMInstrNEON.td:4794 |
| 2505 | VFMAhq = 2490, // ARMInstrNEON.td:4798 |
| 2506 | VFMSD = 2491, // ARMInstrVFP.td:2356 |
| 2507 | VFMSH = 2492, // ARMInstrVFP.td:2379 |
| 2508 | VFMSLD = 2493, // ARMInstrNEON.td:5323 |
| 2509 | VFMSLDI = 2494, // ARMInstrNEON.td:5327 |
| 2510 | VFMSLQ = 2495, // ARMInstrNEON.td:5325 |
| 2511 | VFMSLQI = 2496, // ARMInstrNEON.td:5329 |
| 2512 | VFMSS = 2497, // ARMInstrVFP.td:2366 |
| 2513 | VFMSfd = 2498, // ARMInstrNEON.td:4803 |
| 2514 | VFMSfq = 2499, // ARMInstrNEON.td:4806 |
| 2515 | VFMShd = 2500, // ARMInstrNEON.td:4809 |
| 2516 | VFMShq = 2501, // ARMInstrNEON.td:4812 |
| 2517 | VFNMAD = 2502, // ARMInstrVFP.td:2411 |
| 2518 | VFNMAH = 2503, // ARMInstrVFP.td:2434 |
| 2519 | VFNMAS = 2504, // ARMInstrVFP.td:2421 |
| 2520 | VFNMSD = 2505, // ARMInstrVFP.td:2473 |
| 2521 | VFNMSH = 2506, // ARMInstrVFP.td:2495 |
| 2522 | VFNMSS = 2507, // ARMInstrVFP.td:2483 |
| 2523 | VFP_VMAXNMD = 2508, // ARMInstrVFP.td:621 |
| 2524 | VFP_VMAXNMH = 2509, // ARMInstrVFP.td:609 |
| 2525 | VFP_VMAXNMS = 2510, // ARMInstrVFP.td:615 |
| 2526 | VFP_VMINNMD = 2511, // ARMInstrVFP.td:621 |
| 2527 | VFP_VMINNMH = 2512, // ARMInstrVFP.td:609 |
| 2528 | VFP_VMINNMS = 2513, // ARMInstrVFP.td:615 |
| 2529 | VGETLNi32 = 2514, // ARMInstrNEON.td:6433 |
| 2530 | VGETLNs16 = 2515, // ARMInstrNEON.td:6409 |
| 2531 | VGETLNs8 = 2516, // ARMInstrNEON.td:6401 |
| 2532 | VGETLNu16 = 2517, // ARMInstrNEON.td:6425 |
| 2533 | VGETLNu8 = 2518, // ARMInstrNEON.td:6417 |
| 2534 | VHADDsv16i8 = 2519, // ARMInstrNEON.td:3660 |
| 2535 | VHADDsv2i32 = 2520, // ARMInstrNEON.td:3601 |
| 2536 | VHADDsv4i16 = 2521, // ARMInstrNEON.td:3598 |
| 2537 | VHADDsv4i32 = 2522, // ARMInstrNEON.td:3609 |
| 2538 | VHADDsv8i16 = 2523, // ARMInstrNEON.td:3606 |
| 2539 | VHADDsv8i8 = 2524, // ARMInstrNEON.td:3657 |
| 2540 | VHADDuv16i8 = 2525, // ARMInstrNEON.td:3660 |
| 2541 | VHADDuv2i32 = 2526, // ARMInstrNEON.td:3601 |
| 2542 | VHADDuv4i16 = 2527, // ARMInstrNEON.td:3598 |
| 2543 | VHADDuv4i32 = 2528, // ARMInstrNEON.td:3609 |
| 2544 | VHADDuv8i16 = 2529, // ARMInstrNEON.td:3606 |
| 2545 | VHADDuv8i8 = 2530, // ARMInstrNEON.td:3657 |
| 2546 | VHSUBsv16i8 = 2531, // ARMInstrNEON.td:3660 |
| 2547 | VHSUBsv2i32 = 2532, // ARMInstrNEON.td:3601 |
| 2548 | VHSUBsv4i16 = 2533, // ARMInstrNEON.td:3598 |
| 2549 | VHSUBsv4i32 = 2534, // ARMInstrNEON.td:3609 |
| 2550 | VHSUBsv8i16 = 2535, // ARMInstrNEON.td:3606 |
| 2551 | VHSUBsv8i8 = 2536, // ARMInstrNEON.td:3657 |
| 2552 | VHSUBuv16i8 = 2537, // ARMInstrNEON.td:3660 |
| 2553 | VHSUBuv2i32 = 2538, // ARMInstrNEON.td:3601 |
| 2554 | VHSUBuv4i16 = 2539, // ARMInstrNEON.td:3598 |
| 2555 | VHSUBuv4i32 = 2540, // ARMInstrNEON.td:3609 |
| 2556 | VHSUBuv8i16 = 2541, // ARMInstrNEON.td:3606 |
| 2557 | VHSUBuv8i8 = 2542, // ARMInstrNEON.td:3657 |
| 2558 | VINSH = 2543, // ARMInstrVFP.td:1210 |
| 2559 | VJCVT = 2544, // ARMInstrVFP.td:1856 |
| 2560 | VLD1DUPd16 = 2545, // ARMInstrNEON.td:1404 |
| 2561 | VLD1DUPd16wb_fixed = 2546, // ARMInstrNEON.td:1441 |
| 2562 | VLD1DUPd16wb_register = 2547, // ARMInstrNEON.td:1450 |
| 2563 | VLD1DUPd32 = 2548, // ARMInstrNEON.td:1406 |
| 2564 | VLD1DUPd32wb_fixed = 2549, // ARMInstrNEON.td:1441 |
| 2565 | VLD1DUPd32wb_register = 2550, // ARMInstrNEON.td:1450 |
| 2566 | VLD1DUPd8 = 2551, // ARMInstrNEON.td:1402 |
| 2567 | VLD1DUPd8wb_fixed = 2552, // ARMInstrNEON.td:1441 |
| 2568 | VLD1DUPd8wb_register = 2553, // ARMInstrNEON.td:1450 |
| 2569 | VLD1DUPq16 = 2554, // ARMInstrNEON.td:1428 |
| 2570 | VLD1DUPq16wb_fixed = 2555, // ARMInstrNEON.td:1460 |
| 2571 | VLD1DUPq16wb_register = 2556, // ARMInstrNEON.td:1469 |
| 2572 | VLD1DUPq32 = 2557, // ARMInstrNEON.td:1430 |
| 2573 | VLD1DUPq32wb_fixed = 2558, // ARMInstrNEON.td:1460 |
| 2574 | VLD1DUPq32wb_register = 2559, // ARMInstrNEON.td:1469 |
| 2575 | VLD1DUPq8 = 2560, // ARMInstrNEON.td:1426 |
| 2576 | VLD1DUPq8wb_fixed = 2561, // ARMInstrNEON.td:1460 |
| 2577 | VLD1DUPq8wb_register = 2562, // ARMInstrNEON.td:1469 |
| 2578 | VLD1LNd16 = 2563, // ARMInstrNEON.td:1083 |
| 2579 | VLD1LNd16_UPD = 2564, // ARMInstrNEON.td:1148 |
| 2580 | VLD1LNd32 = 2565, // ARMInstrNEON.td:1087 |
| 2581 | VLD1LNd32_UPD = 2566, // ARMInstrNEON.td:1152 |
| 2582 | VLD1LNd8 = 2567, // ARMInstrNEON.td:1080 |
| 2583 | VLD1LNd8_UPD = 2568, // ARMInstrNEON.td:1145 |
| 2584 | VLD1LNq16Pseudo = 2569, // ARMInstrNEON.td:1093 |
| 2585 | VLD1LNq16Pseudo_UPD = 2570, // ARMInstrNEON.td:1159 |
| 2586 | VLD1LNq32Pseudo = 2571, // ARMInstrNEON.td:1094 |
| 2587 | VLD1LNq32Pseudo_UPD = 2572, // ARMInstrNEON.td:1160 |
| 2588 | VLD1LNq8Pseudo = 2573, // ARMInstrNEON.td:1092 |
| 2589 | VLD1LNq8Pseudo_UPD = 2574, // ARMInstrNEON.td:1158 |
| 2590 | VLD1d16 = 2575, // ARMInstrNEON.td:637 |
| 2591 | VLD1d16Q = 2576, // ARMInstrNEON.td:782 |
| 2592 | VLD1d16QPseudo = 2577, // ARMInstrNEON.td:794 |
| 2593 | VLD1d16QPseudoWB_fixed = 2578, // ARMInstrNEON.td:795 |
| 2594 | VLD1d16QPseudoWB_register = 2579, // ARMInstrNEON.td:796 |
| 2595 | VLD1d16Qwb_fixed = 2580, // ARMInstrNEON.td:764 |
| 2596 | VLD1d16Qwb_register = 2581, // ARMInstrNEON.td:772 |
| 2597 | VLD1d16T = 2582, // ARMInstrNEON.td:719 |
| 2598 | VLD1d16TPseudo = 2583, // ARMInstrNEON.td:731 |
| 2599 | VLD1d16TPseudoWB_fixed = 2584, // ARMInstrNEON.td:732 |
| 2600 | VLD1d16TPseudoWB_register = 2585, // ARMInstrNEON.td:733 |
| 2601 | VLD1d16Twb_fixed = 2586, // ARMInstrNEON.td:701 |
| 2602 | VLD1d16Twb_register = 2587, // ARMInstrNEON.td:709 |
| 2603 | VLD1d16wb_fixed = 2588, // ARMInstrNEON.td:648 |
| 2604 | VLD1d16wb_register = 2589, // ARMInstrNEON.td:656 |
| 2605 | VLD1d32 = 2590, // ARMInstrNEON.td:638 |
| 2606 | VLD1d32Q = 2591, // ARMInstrNEON.td:783 |
| 2607 | VLD1d32QPseudo = 2592, // ARMInstrNEON.td:797 |
| 2608 | VLD1d32QPseudoWB_fixed = 2593, // ARMInstrNEON.td:798 |
| 2609 | VLD1d32QPseudoWB_register = 2594, // ARMInstrNEON.td:799 |
| 2610 | VLD1d32Qwb_fixed = 2595, // ARMInstrNEON.td:764 |
| 2611 | VLD1d32Qwb_register = 2596, // ARMInstrNEON.td:772 |
| 2612 | VLD1d32T = 2597, // ARMInstrNEON.td:720 |
| 2613 | VLD1d32TPseudo = 2598, // ARMInstrNEON.td:734 |
| 2614 | VLD1d32TPseudoWB_fixed = 2599, // ARMInstrNEON.td:735 |
| 2615 | VLD1d32TPseudoWB_register = 2600, // ARMInstrNEON.td:736 |
| 2616 | VLD1d32Twb_fixed = 2601, // ARMInstrNEON.td:701 |
| 2617 | VLD1d32Twb_register = 2602, // ARMInstrNEON.td:709 |
| 2618 | VLD1d32wb_fixed = 2603, // ARMInstrNEON.td:648 |
| 2619 | VLD1d32wb_register = 2604, // ARMInstrNEON.td:656 |
| 2620 | VLD1d64 = 2605, // ARMInstrNEON.td:639 |
| 2621 | VLD1d64Q = 2606, // ARMInstrNEON.td:784 |
| 2622 | VLD1d64QPseudo = 2607, // ARMInstrNEON.td:800 |
| 2623 | VLD1d64QPseudoWB_fixed = 2608, // ARMInstrNEON.td:801 |
| 2624 | VLD1d64QPseudoWB_register = 2609, // ARMInstrNEON.td:802 |
| 2625 | VLD1d64Qwb_fixed = 2610, // ARMInstrNEON.td:764 |
| 2626 | VLD1d64Qwb_register = 2611, // ARMInstrNEON.td:772 |
| 2627 | VLD1d64T = 2612, // ARMInstrNEON.td:721 |
| 2628 | VLD1d64TPseudo = 2613, // ARMInstrNEON.td:737 |
| 2629 | VLD1d64TPseudoWB_fixed = 2614, // ARMInstrNEON.td:738 |
| 2630 | VLD1d64TPseudoWB_register = 2615, // ARMInstrNEON.td:739 |
| 2631 | VLD1d64Twb_fixed = 2616, // ARMInstrNEON.td:701 |
| 2632 | VLD1d64Twb_register = 2617, // ARMInstrNEON.td:709 |
| 2633 | VLD1d64wb_fixed = 2618, // ARMInstrNEON.td:648 |
| 2634 | VLD1d64wb_register = 2619, // ARMInstrNEON.td:656 |
| 2635 | VLD1d8 = 2620, // ARMInstrNEON.td:636 |
| 2636 | VLD1d8Q = 2621, // ARMInstrNEON.td:781 |
| 2637 | VLD1d8QPseudo = 2622, // ARMInstrNEON.td:791 |
| 2638 | VLD1d8QPseudoWB_fixed = 2623, // ARMInstrNEON.td:792 |
| 2639 | VLD1d8QPseudoWB_register = 2624, // ARMInstrNEON.td:793 |
| 2640 | VLD1d8Qwb_fixed = 2625, // ARMInstrNEON.td:764 |
| 2641 | VLD1d8Qwb_register = 2626, // ARMInstrNEON.td:772 |
| 2642 | VLD1d8T = 2627, // ARMInstrNEON.td:718 |
| 2643 | VLD1d8TPseudo = 2628, // ARMInstrNEON.td:728 |
| 2644 | VLD1d8TPseudoWB_fixed = 2629, // ARMInstrNEON.td:729 |
| 2645 | VLD1d8TPseudoWB_register = 2630, // ARMInstrNEON.td:730 |
| 2646 | VLD1d8Twb_fixed = 2631, // ARMInstrNEON.td:701 |
| 2647 | VLD1d8Twb_register = 2632, // ARMInstrNEON.td:709 |
| 2648 | VLD1d8wb_fixed = 2633, // ARMInstrNEON.td:648 |
| 2649 | VLD1d8wb_register = 2634, // ARMInstrNEON.td:656 |
| 2650 | VLD1q16 = 2635, // ARMInstrNEON.td:642 |
| 2651 | VLD1q16HighQPseudo = 2636, // ARMInstrNEON.td:808 |
| 2652 | VLD1q16HighQPseudo_UPD = 2637, // ARMInstrNEON.td:809 |
| 2653 | VLD1q16HighTPseudo = 2638, // ARMInstrNEON.td:744 |
| 2654 | VLD1q16HighTPseudo_UPD = 2639, // ARMInstrNEON.td:745 |
| 2655 | VLD1q16LowQPseudo_UPD = 2640, // ARMInstrNEON.td:807 |
| 2656 | VLD1q16LowTPseudo_UPD = 2641, // ARMInstrNEON.td:746 |
| 2657 | VLD1q16wb_fixed = 2642, // ARMInstrNEON.td:665 |
| 2658 | VLD1q16wb_register = 2643, // ARMInstrNEON.td:673 |
| 2659 | VLD1q32 = 2644, // ARMInstrNEON.td:643 |
| 2660 | VLD1q32HighQPseudo = 2645, // ARMInstrNEON.td:811 |
| 2661 | VLD1q32HighQPseudo_UPD = 2646, // ARMInstrNEON.td:812 |
| 2662 | VLD1q32HighTPseudo = 2647, // ARMInstrNEON.td:747 |
| 2663 | VLD1q32HighTPseudo_UPD = 2648, // ARMInstrNEON.td:748 |
| 2664 | VLD1q32LowQPseudo_UPD = 2649, // ARMInstrNEON.td:810 |
| 2665 | VLD1q32LowTPseudo_UPD = 2650, // ARMInstrNEON.td:749 |
| 2666 | VLD1q32wb_fixed = 2651, // ARMInstrNEON.td:665 |
| 2667 | VLD1q32wb_register = 2652, // ARMInstrNEON.td:673 |
| 2668 | VLD1q64 = 2653, // ARMInstrNEON.td:644 |
| 2669 | VLD1q64HighQPseudo = 2654, // ARMInstrNEON.td:814 |
| 2670 | VLD1q64HighQPseudo_UPD = 2655, // ARMInstrNEON.td:815 |
| 2671 | VLD1q64HighTPseudo = 2656, // ARMInstrNEON.td:750 |
| 2672 | VLD1q64HighTPseudo_UPD = 2657, // ARMInstrNEON.td:751 |
| 2673 | VLD1q64LowQPseudo_UPD = 2658, // ARMInstrNEON.td:813 |
| 2674 | VLD1q64LowTPseudo_UPD = 2659, // ARMInstrNEON.td:752 |
| 2675 | VLD1q64wb_fixed = 2660, // ARMInstrNEON.td:665 |
| 2676 | VLD1q64wb_register = 2661, // ARMInstrNEON.td:673 |
| 2677 | VLD1q8 = 2662, // ARMInstrNEON.td:641 |
| 2678 | VLD1q8HighQPseudo = 2663, // ARMInstrNEON.td:805 |
| 2679 | VLD1q8HighQPseudo_UPD = 2664, // ARMInstrNEON.td:806 |
| 2680 | VLD1q8HighTPseudo = 2665, // ARMInstrNEON.td:741 |
| 2681 | VLD1q8HighTPseudo_UPD = 2666, // ARMInstrNEON.td:742 |
| 2682 | VLD1q8LowQPseudo_UPD = 2667, // ARMInstrNEON.td:804 |
| 2683 | VLD1q8LowTPseudo_UPD = 2668, // ARMInstrNEON.td:743 |
| 2684 | VLD1q8wb_fixed = 2669, // ARMInstrNEON.td:665 |
| 2685 | VLD1q8wb_register = 2670, // ARMInstrNEON.td:673 |
| 2686 | VLD2DUPd16 = 2671, // ARMInstrNEON.td:1499 |
| 2687 | VLD2DUPd16wb_fixed = 2672, // ARMInstrNEON.td:1538 |
| 2688 | VLD2DUPd16wb_register = 2673, // ARMInstrNEON.td:1547 |
| 2689 | VLD2DUPd16x2 = 2674, // ARMInstrNEON.td:1509 |
| 2690 | VLD2DUPd16x2wb_fixed = 2675, // ARMInstrNEON.td:1538 |
| 2691 | VLD2DUPd16x2wb_register = 2676, // ARMInstrNEON.td:1547 |
| 2692 | VLD2DUPd32 = 2677, // ARMInstrNEON.td:1501 |
| 2693 | VLD2DUPd32wb_fixed = 2678, // ARMInstrNEON.td:1538 |
| 2694 | VLD2DUPd32wb_register = 2679, // ARMInstrNEON.td:1547 |
| 2695 | VLD2DUPd32x2 = 2680, // ARMInstrNEON.td:1511 |
| 2696 | VLD2DUPd32x2wb_fixed = 2681, // ARMInstrNEON.td:1538 |
| 2697 | VLD2DUPd32x2wb_register = 2682, // ARMInstrNEON.td:1547 |
| 2698 | VLD2DUPd8 = 2683, // ARMInstrNEON.td:1497 |
| 2699 | VLD2DUPd8wb_fixed = 2684, // ARMInstrNEON.td:1538 |
| 2700 | VLD2DUPd8wb_register = 2685, // ARMInstrNEON.td:1547 |
| 2701 | VLD2DUPd8x2 = 2686, // ARMInstrNEON.td:1507 |
| 2702 | VLD2DUPd8x2wb_fixed = 2687, // ARMInstrNEON.td:1538 |
| 2703 | VLD2DUPd8x2wb_register = 2688, // ARMInstrNEON.td:1547 |
| 2704 | VLD2DUPq16EvenPseudo = 2689, // ARMInstrNEON.td:1530 |
| 2705 | VLD2DUPq16OddPseudo = 2690, // ARMInstrNEON.td:1531 |
| 2706 | VLD2DUPq16OddPseudoWB_fixed = 2691, // ARMInstrNEON.td:1572 |
| 2707 | VLD2DUPq16OddPseudoWB_register = 2692, // ARMInstrNEON.td:1575 |
| 2708 | VLD2DUPq32EvenPseudo = 2693, // ARMInstrNEON.td:1532 |
| 2709 | VLD2DUPq32OddPseudo = 2694, // ARMInstrNEON.td:1533 |
| 2710 | VLD2DUPq32OddPseudoWB_fixed = 2695, // ARMInstrNEON.td:1573 |
| 2711 | VLD2DUPq32OddPseudoWB_register = 2696, // ARMInstrNEON.td:1576 |
| 2712 | VLD2DUPq8EvenPseudo = 2697, // ARMInstrNEON.td:1528 |
| 2713 | VLD2DUPq8OddPseudo = 2698, // ARMInstrNEON.td:1529 |
| 2714 | VLD2DUPq8OddPseudoWB_fixed = 2699, // ARMInstrNEON.td:1571 |
| 2715 | VLD2DUPq8OddPseudoWB_register = 2700, // ARMInstrNEON.td:1574 |
| 2716 | VLD2LNd16 = 2701, // ARMInstrNEON.td:1176 |
| 2717 | VLD2LNd16Pseudo = 2702, // ARMInstrNEON.td:1184 |
| 2718 | VLD2LNd16Pseudo_UPD = 2703, // ARMInstrNEON.td:1220 |
| 2719 | VLD2LNd16_UPD = 2704, // ARMInstrNEON.td:1212 |
| 2720 | VLD2LNd32 = 2705, // ARMInstrNEON.td:1179 |
| 2721 | VLD2LNd32Pseudo = 2706, // ARMInstrNEON.td:1185 |
| 2722 | VLD2LNd32Pseudo_UPD = 2707, // ARMInstrNEON.td:1221 |
| 2723 | VLD2LNd32_UPD = 2708, // ARMInstrNEON.td:1215 |
| 2724 | VLD2LNd8 = 2709, // ARMInstrNEON.td:1173 |
| 2725 | VLD2LNd8Pseudo = 2710, // ARMInstrNEON.td:1183 |
| 2726 | VLD2LNd8Pseudo_UPD = 2711, // ARMInstrNEON.td:1219 |
| 2727 | VLD2LNd8_UPD = 2712, // ARMInstrNEON.td:1209 |
| 2728 | VLD2LNq16 = 2713, // ARMInstrNEON.td:1188 |
| 2729 | VLD2LNq16Pseudo = 2714, // ARMInstrNEON.td:1195 |
| 2730 | VLD2LNq16Pseudo_UPD = 2715, // ARMInstrNEON.td:1230 |
| 2731 | VLD2LNq16_UPD = 2716, // ARMInstrNEON.td:1223 |
| 2732 | VLD2LNq32 = 2717, // ARMInstrNEON.td:1191 |
| 2733 | VLD2LNq32Pseudo = 2718, // ARMInstrNEON.td:1196 |
| 2734 | VLD2LNq32Pseudo_UPD = 2719, // ARMInstrNEON.td:1231 |
| 2735 | VLD2LNq32_UPD = 2720, // ARMInstrNEON.td:1226 |
| 2736 | VLD2b16 = 2721, // ARMInstrNEON.td:890 |
| 2737 | VLD2b16wb_fixed = 2722, // ARMInstrNEON.td:849 |
| 2738 | VLD2b16wb_register = 2723, // ARMInstrNEON.td:857 |
| 2739 | VLD2b32 = 2724, // ARMInstrNEON.td:892 |
| 2740 | VLD2b32wb_fixed = 2725, // ARMInstrNEON.td:849 |
| 2741 | VLD2b32wb_register = 2726, // ARMInstrNEON.td:857 |
| 2742 | VLD2b8 = 2727, // ARMInstrNEON.td:888 |
| 2743 | VLD2b8wb_fixed = 2728, // ARMInstrNEON.td:849 |
| 2744 | VLD2b8wb_register = 2729, // ARMInstrNEON.td:857 |
| 2745 | VLD2d16 = 2730, // ARMInstrNEON.td:830 |
| 2746 | VLD2d16wb_fixed = 2731, // ARMInstrNEON.td:849 |
| 2747 | VLD2d16wb_register = 2732, // ARMInstrNEON.td:857 |
| 2748 | VLD2d32 = 2733, // ARMInstrNEON.td:832 |
| 2749 | VLD2d32wb_fixed = 2734, // ARMInstrNEON.td:849 |
| 2750 | VLD2d32wb_register = 2735, // ARMInstrNEON.td:857 |
| 2751 | VLD2d8 = 2736, // ARMInstrNEON.td:828 |
| 2752 | VLD2d8wb_fixed = 2737, // ARMInstrNEON.td:849 |
| 2753 | VLD2d8wb_register = 2738, // ARMInstrNEON.td:857 |
| 2754 | VLD2q16 = 2739, // ARMInstrNEON.td:837 |
| 2755 | VLD2q16Pseudo = 2740, // ARMInstrNEON.td:843 |
| 2756 | VLD2q16PseudoWB_fixed = 2741, // ARMInstrNEON.td:881 |
| 2757 | VLD2q16PseudoWB_register = 2742, // ARMInstrNEON.td:884 |
| 2758 | VLD2q16wb_fixed = 2743, // ARMInstrNEON.td:849 |
| 2759 | VLD2q16wb_register = 2744, // ARMInstrNEON.td:857 |
| 2760 | VLD2q32 = 2745, // ARMInstrNEON.td:839 |
| 2761 | VLD2q32Pseudo = 2746, // ARMInstrNEON.td:844 |
| 2762 | VLD2q32PseudoWB_fixed = 2747, // ARMInstrNEON.td:882 |
| 2763 | VLD2q32PseudoWB_register = 2748, // ARMInstrNEON.td:885 |
| 2764 | VLD2q32wb_fixed = 2749, // ARMInstrNEON.td:849 |
| 2765 | VLD2q32wb_register = 2750, // ARMInstrNEON.td:857 |
| 2766 | VLD2q8 = 2751, // ARMInstrNEON.td:835 |
| 2767 | VLD2q8Pseudo = 2752, // ARMInstrNEON.td:842 |
| 2768 | VLD2q8PseudoWB_fixed = 2753, // ARMInstrNEON.td:880 |
| 2769 | VLD2q8PseudoWB_register = 2754, // ARMInstrNEON.td:883 |
| 2770 | VLD2q8wb_fixed = 2755, // ARMInstrNEON.td:849 |
| 2771 | VLD2q8wb_register = 2756, // ARMInstrNEON.td:857 |
| 2772 | VLD3DUPd16 = 2757, // ARMInstrNEON.td:1590 |
| 2773 | VLD3DUPd16Pseudo = 2758, // ARMInstrNEON.td:1594 |
| 2774 | VLD3DUPd16Pseudo_UPD = 2759, // ARMInstrNEON.td:1628 |
| 2775 | VLD3DUPd16_UPD = 2760, // ARMInstrNEON.td:1620 |
| 2776 | VLD3DUPd32 = 2761, // ARMInstrNEON.td:1591 |
| 2777 | VLD3DUPd32Pseudo = 2762, // ARMInstrNEON.td:1595 |
| 2778 | VLD3DUPd32Pseudo_UPD = 2763, // ARMInstrNEON.td:1629 |
| 2779 | VLD3DUPd32_UPD = 2764, // ARMInstrNEON.td:1621 |
| 2780 | VLD3DUPd8 = 2765, // ARMInstrNEON.td:1589 |
| 2781 | VLD3DUPd8Pseudo = 2766, // ARMInstrNEON.td:1593 |
| 2782 | VLD3DUPd8Pseudo_UPD = 2767, // ARMInstrNEON.td:1627 |
| 2783 | VLD3DUPd8_UPD = 2768, // ARMInstrNEON.td:1619 |
| 2784 | VLD3DUPq16 = 2769, // ARMInstrNEON.td:1599 |
| 2785 | VLD3DUPq16EvenPseudo = 2770, // ARMInstrNEON.td:1604 |
| 2786 | VLD3DUPq16OddPseudo = 2771, // ARMInstrNEON.td:1605 |
| 2787 | VLD3DUPq16OddPseudo_UPD = 2772, // ARMInstrNEON.td:1632 |
| 2788 | VLD3DUPq16_UPD = 2773, // ARMInstrNEON.td:1624 |
| 2789 | VLD3DUPq32 = 2774, // ARMInstrNEON.td:1600 |
| 2790 | VLD3DUPq32EvenPseudo = 2775, // ARMInstrNEON.td:1606 |
| 2791 | VLD3DUPq32OddPseudo = 2776, // ARMInstrNEON.td:1607 |
| 2792 | VLD3DUPq32OddPseudo_UPD = 2777, // ARMInstrNEON.td:1633 |
| 2793 | VLD3DUPq32_UPD = 2778, // ARMInstrNEON.td:1625 |
| 2794 | VLD3DUPq8 = 2779, // ARMInstrNEON.td:1598 |
| 2795 | VLD3DUPq8EvenPseudo = 2780, // ARMInstrNEON.td:1602 |
| 2796 | VLD3DUPq8OddPseudo = 2781, // ARMInstrNEON.td:1603 |
| 2797 | VLD3DUPq8OddPseudo_UPD = 2782, // ARMInstrNEON.td:1631 |
| 2798 | VLD3DUPq8_UPD = 2783, // ARMInstrNEON.td:1623 |
| 2799 | VLD3LNd16 = 2784, // ARMInstrNEON.td:1247 |
| 2800 | VLD3LNd16Pseudo = 2785, // ARMInstrNEON.td:1255 |
| 2801 | VLD3LNd16Pseudo_UPD = 2786, // ARMInstrNEON.td:1293 |
| 2802 | VLD3LNd16_UPD = 2787, // ARMInstrNEON.td:1285 |
| 2803 | VLD3LNd32 = 2788, // ARMInstrNEON.td:1250 |
| 2804 | VLD3LNd32Pseudo = 2789, // ARMInstrNEON.td:1256 |
| 2805 | VLD3LNd32Pseudo_UPD = 2790, // ARMInstrNEON.td:1294 |
| 2806 | VLD3LNd32_UPD = 2791, // ARMInstrNEON.td:1288 |
| 2807 | VLD3LNd8 = 2792, // ARMInstrNEON.td:1244 |
| 2808 | VLD3LNd8Pseudo = 2793, // ARMInstrNEON.td:1254 |
| 2809 | VLD3LNd8Pseudo_UPD = 2794, // ARMInstrNEON.td:1292 |
| 2810 | VLD3LNd8_UPD = 2795, // ARMInstrNEON.td:1282 |
| 2811 | VLD3LNq16 = 2796, // ARMInstrNEON.td:1259 |
| 2812 | VLD3LNq16Pseudo = 2797, // ARMInstrNEON.td:1266 |
| 2813 | VLD3LNq16Pseudo_UPD = 2798, // ARMInstrNEON.td:1303 |
| 2814 | VLD3LNq16_UPD = 2799, // ARMInstrNEON.td:1296 |
| 2815 | VLD3LNq32 = 2800, // ARMInstrNEON.td:1262 |
| 2816 | VLD3LNq32Pseudo = 2801, // ARMInstrNEON.td:1267 |
| 2817 | VLD3LNq32Pseudo_UPD = 2802, // ARMInstrNEON.td:1304 |
| 2818 | VLD3LNq32_UPD = 2803, // ARMInstrNEON.td:1299 |
| 2819 | VLD3d16 = 2804, // ARMInstrNEON.td:912 |
| 2820 | VLD3d16Pseudo = 2805, // ARMInstrNEON.td:916 |
| 2821 | VLD3d16Pseudo_UPD = 2806, // ARMInstrNEON.td:935 |
| 2822 | VLD3d16_UPD = 2807, // ARMInstrNEON.td:931 |
| 2823 | VLD3d32 = 2808, // ARMInstrNEON.td:913 |
| 2824 | VLD3d32Pseudo = 2809, // ARMInstrNEON.td:917 |
| 2825 | VLD3d32Pseudo_UPD = 2810, // ARMInstrNEON.td:936 |
| 2826 | VLD3d32_UPD = 2811, // ARMInstrNEON.td:932 |
| 2827 | VLD3d8 = 2812, // ARMInstrNEON.td:911 |
| 2828 | VLD3d8Pseudo = 2813, // ARMInstrNEON.td:915 |
| 2829 | VLD3d8Pseudo_UPD = 2814, // ARMInstrNEON.td:934 |
| 2830 | VLD3d8_UPD = 2815, // ARMInstrNEON.td:930 |
| 2831 | VLD3q16 = 2816, // ARMInstrNEON.td:940 |
| 2832 | VLD3q16Pseudo_UPD = 2817, // ARMInstrNEON.td:947 |
| 2833 | VLD3q16_UPD = 2818, // ARMInstrNEON.td:943 |
| 2834 | VLD3q16oddPseudo = 2819, // ARMInstrNEON.td:952 |
| 2835 | VLD3q16oddPseudo_UPD = 2820, // ARMInstrNEON.td:956 |
| 2836 | VLD3q32 = 2821, // ARMInstrNEON.td:941 |
| 2837 | VLD3q32Pseudo_UPD = 2822, // ARMInstrNEON.td:948 |
| 2838 | VLD3q32_UPD = 2823, // ARMInstrNEON.td:944 |
| 2839 | VLD3q32oddPseudo = 2824, // ARMInstrNEON.td:953 |
| 2840 | VLD3q32oddPseudo_UPD = 2825, // ARMInstrNEON.td:957 |
| 2841 | VLD3q8 = 2826, // ARMInstrNEON.td:939 |
| 2842 | VLD3q8Pseudo_UPD = 2827, // ARMInstrNEON.td:946 |
| 2843 | VLD3q8_UPD = 2828, // ARMInstrNEON.td:942 |
| 2844 | VLD3q8oddPseudo = 2829, // ARMInstrNEON.td:951 |
| 2845 | VLD3q8oddPseudo_UPD = 2830, // ARMInstrNEON.td:955 |
| 2846 | VLD4DUPd16 = 2831, // ARMInstrNEON.td:1647 |
| 2847 | VLD4DUPd16Pseudo = 2832, // ARMInstrNEON.td:1651 |
| 2848 | VLD4DUPd16Pseudo_UPD = 2833, // ARMInstrNEON.td:1686 |
| 2849 | VLD4DUPd16_UPD = 2834, // ARMInstrNEON.td:1678 |
| 2850 | VLD4DUPd32 = 2835, // ARMInstrNEON.td:1648 |
| 2851 | VLD4DUPd32Pseudo = 2836, // ARMInstrNEON.td:1652 |
| 2852 | VLD4DUPd32Pseudo_UPD = 2837, // ARMInstrNEON.td:1687 |
| 2853 | VLD4DUPd32_UPD = 2838, // ARMInstrNEON.td:1679 |
| 2854 | VLD4DUPd8 = 2839, // ARMInstrNEON.td:1646 |
| 2855 | VLD4DUPd8Pseudo = 2840, // ARMInstrNEON.td:1650 |
| 2856 | VLD4DUPd8Pseudo_UPD = 2841, // ARMInstrNEON.td:1685 |
| 2857 | VLD4DUPd8_UPD = 2842, // ARMInstrNEON.td:1677 |
| 2858 | VLD4DUPq16 = 2843, // ARMInstrNEON.td:1656 |
| 2859 | VLD4DUPq16EvenPseudo = 2844, // ARMInstrNEON.td:1661 |
| 2860 | VLD4DUPq16OddPseudo = 2845, // ARMInstrNEON.td:1662 |
| 2861 | VLD4DUPq16OddPseudo_UPD = 2846, // ARMInstrNEON.td:1690 |
| 2862 | VLD4DUPq16_UPD = 2847, // ARMInstrNEON.td:1682 |
| 2863 | VLD4DUPq32 = 2848, // ARMInstrNEON.td:1657 |
| 2864 | VLD4DUPq32EvenPseudo = 2849, // ARMInstrNEON.td:1663 |
| 2865 | VLD4DUPq32OddPseudo = 2850, // ARMInstrNEON.td:1664 |
| 2866 | VLD4DUPq32OddPseudo_UPD = 2851, // ARMInstrNEON.td:1691 |
| 2867 | VLD4DUPq32_UPD = 2852, // ARMInstrNEON.td:1683 |
| 2868 | VLD4DUPq8 = 2853, // ARMInstrNEON.td:1655 |
| 2869 | VLD4DUPq8EvenPseudo = 2854, // ARMInstrNEON.td:1659 |
| 2870 | VLD4DUPq8OddPseudo = 2855, // ARMInstrNEON.td:1660 |
| 2871 | VLD4DUPq8OddPseudo_UPD = 2856, // ARMInstrNEON.td:1689 |
| 2872 | VLD4DUPq8_UPD = 2857, // ARMInstrNEON.td:1681 |
| 2873 | VLD4LNd16 = 2858, // ARMInstrNEON.td:1323 |
| 2874 | VLD4LNd16Pseudo = 2859, // ARMInstrNEON.td:1332 |
| 2875 | VLD4LNd16Pseudo_UPD = 2860, // ARMInstrNEON.td:1373 |
| 2876 | VLD4LNd16_UPD = 2861, // ARMInstrNEON.td:1364 |
| 2877 | VLD4LNd32 = 2862, // ARMInstrNEON.td:1326 |
| 2878 | VLD4LNd32Pseudo = 2863, // ARMInstrNEON.td:1333 |
| 2879 | VLD4LNd32Pseudo_UPD = 2864, // ARMInstrNEON.td:1374 |
| 2880 | VLD4LNd32_UPD = 2865, // ARMInstrNEON.td:1367 |
| 2881 | VLD4LNd8 = 2866, // ARMInstrNEON.td:1320 |
| 2882 | VLD4LNd8Pseudo = 2867, // ARMInstrNEON.td:1331 |
| 2883 | VLD4LNd8Pseudo_UPD = 2868, // ARMInstrNEON.td:1372 |
| 2884 | VLD4LNd8_UPD = 2869, // ARMInstrNEON.td:1361 |
| 2885 | VLD4LNq16 = 2870, // ARMInstrNEON.td:1336 |
| 2886 | VLD4LNq16Pseudo = 2871, // ARMInstrNEON.td:1344 |
| 2887 | VLD4LNq16Pseudo_UPD = 2872, // ARMInstrNEON.td:1384 |
| 2888 | VLD4LNq16_UPD = 2873, // ARMInstrNEON.td:1376 |
| 2889 | VLD4LNq32 = 2874, // ARMInstrNEON.td:1339 |
| 2890 | VLD4LNq32Pseudo = 2875, // ARMInstrNEON.td:1345 |
| 2891 | VLD4LNq32Pseudo_UPD = 2876, // ARMInstrNEON.td:1385 |
| 2892 | VLD4LNq32_UPD = 2877, // ARMInstrNEON.td:1379 |
| 2893 | VLD4d16 = 2878, // ARMInstrNEON.td:972 |
| 2894 | VLD4d16Pseudo = 2879, // ARMInstrNEON.td:976 |
| 2895 | VLD4d16Pseudo_UPD = 2880, // ARMInstrNEON.td:995 |
| 2896 | VLD4d16_UPD = 2881, // ARMInstrNEON.td:991 |
| 2897 | VLD4d32 = 2882, // ARMInstrNEON.td:973 |
| 2898 | VLD4d32Pseudo = 2883, // ARMInstrNEON.td:977 |
| 2899 | VLD4d32Pseudo_UPD = 2884, // ARMInstrNEON.td:996 |
| 2900 | VLD4d32_UPD = 2885, // ARMInstrNEON.td:992 |
| 2901 | VLD4d8 = 2886, // ARMInstrNEON.td:971 |
| 2902 | VLD4d8Pseudo = 2887, // ARMInstrNEON.td:975 |
| 2903 | VLD4d8Pseudo_UPD = 2888, // ARMInstrNEON.td:994 |
| 2904 | VLD4d8_UPD = 2889, // ARMInstrNEON.td:990 |
| 2905 | VLD4q16 = 2890, // ARMInstrNEON.td:1000 |
| 2906 | VLD4q16Pseudo_UPD = 2891, // ARMInstrNEON.td:1007 |
| 2907 | VLD4q16_UPD = 2892, // ARMInstrNEON.td:1003 |
| 2908 | VLD4q16oddPseudo = 2893, // ARMInstrNEON.td:1012 |
| 2909 | VLD4q16oddPseudo_UPD = 2894, // ARMInstrNEON.td:1016 |
| 2910 | VLD4q32 = 2895, // ARMInstrNEON.td:1001 |
| 2911 | VLD4q32Pseudo_UPD = 2896, // ARMInstrNEON.td:1008 |
| 2912 | VLD4q32_UPD = 2897, // ARMInstrNEON.td:1004 |
| 2913 | VLD4q32oddPseudo = 2898, // ARMInstrNEON.td:1013 |
| 2914 | VLD4q32oddPseudo_UPD = 2899, // ARMInstrNEON.td:1017 |
| 2915 | VLD4q8 = 2900, // ARMInstrNEON.td:999 |
| 2916 | VLD4q8Pseudo_UPD = 2901, // ARMInstrNEON.td:1006 |
| 2917 | VLD4q8_UPD = 2902, // ARMInstrNEON.td:1002 |
| 2918 | VLD4q8oddPseudo = 2903, // ARMInstrNEON.td:1011 |
| 2919 | VLD4q8oddPseudo_UPD = 2904, // ARMInstrNEON.td:1015 |
| 2920 | VLDMDDB_UPD = 2905, // ARMInstrVFP.td:276 |
| 2921 | VLDMDIA = 2906, // ARMInstrVFP.td:259 |
| 2922 | VLDMDIA_UPD = 2907, // ARMInstrVFP.td:267 |
| 2923 | VLDMQIA = 2908, // ARMInstrNEON.td:563 |
| 2924 | VLDMSDB_UPD = 2909, // ARMInstrVFP.td:312 |
| 2925 | VLDMSIA = 2910, // ARMInstrVFP.td:287 |
| 2926 | VLDMSIA_UPD = 2911, // ARMInstrVFP.td:299 |
| 2927 | VLDRD = 2912, // ARMInstrVFP.td:183 |
| 2928 | VLDRH = 2913, // ARMInstrVFP.td:198 |
| 2929 | VLDRS = 2914, // ARMInstrVFP.td:188 |
| 2930 | VLDR_FPCXTNS_off = 2915, // ARMInstrVFP.td:2975 |
| 2931 | VLDR_FPCXTNS_post = 2916, // ARMInstrVFP.td:2990 |
| 2932 | VLDR_FPCXTNS_pre = 2917, // ARMInstrVFP.td:2982 |
| 2933 | VLDR_FPCXTS_off = 2918, // ARMInstrVFP.td:2975 |
| 2934 | VLDR_FPCXTS_post = 2919, // ARMInstrVFP.td:2990 |
| 2935 | VLDR_FPCXTS_pre = 2920, // ARMInstrVFP.td:2982 |
| 2936 | VLDR_FPSCR_NZCVQC_off = 2921, // ARMInstrVFP.td:2975 |
| 2937 | VLDR_FPSCR_NZCVQC_post = 2922, // ARMInstrVFP.td:2990 |
| 2938 | VLDR_FPSCR_NZCVQC_pre = 2923, // ARMInstrVFP.td:2982 |
| 2939 | VLDR_FPSCR_off = 2924, // ARMInstrVFP.td:2975 |
| 2940 | VLDR_FPSCR_post = 2925, // ARMInstrVFP.td:2990 |
| 2941 | VLDR_FPSCR_pre = 2926, // ARMInstrVFP.td:2982 |
| 2942 | VLDR_P0_off = 2927, // ARMInstrVFP.td:2975 |
| 2943 | VLDR_P0_post = 2928, // ARMInstrVFP.td:2990 |
| 2944 | VLDR_P0_pre = 2929, // ARMInstrVFP.td:2982 |
| 2945 | VLDR_VPR_off = 2930, // ARMInstrVFP.td:2975 |
| 2946 | VLDR_VPR_post = 2931, // ARMInstrVFP.td:2990 |
| 2947 | VLDR_VPR_pre = 2932, // ARMInstrVFP.td:2982 |
| 2948 | VLLDM = 2933, // ARMInstrVFP.td:355 |
| 2949 | VLLDM_T2 = 2934, // ARMInstrVFP.td:365 |
| 2950 | VLSTM = 2935, // ARMInstrVFP.td:373 |
| 2951 | VLSTM_T2 = 2936, // ARMInstrVFP.td:384 |
| 2952 | VMAXfd = 2937, // ARMInstrNEON.td:5736 |
| 2953 | VMAXfq = 2938, // ARMInstrNEON.td:5739 |
| 2954 | VMAXhd = 2939, // ARMInstrNEON.td:5742 |
| 2955 | VMAXhq = 2940, // ARMInstrNEON.td:5746 |
| 2956 | VMAXsv16i8 = 2941, // ARMInstrNEON.td:3660 |
| 2957 | VMAXsv2i32 = 2942, // ARMInstrNEON.td:3601 |
| 2958 | VMAXsv4i16 = 2943, // ARMInstrNEON.td:3598 |
| 2959 | VMAXsv4i32 = 2944, // ARMInstrNEON.td:3609 |
| 2960 | VMAXsv8i16 = 2945, // ARMInstrNEON.td:3606 |
| 2961 | VMAXsv8i8 = 2946, // ARMInstrNEON.td:3657 |
| 2962 | VMAXuv16i8 = 2947, // ARMInstrNEON.td:3660 |
| 2963 | VMAXuv2i32 = 2948, // ARMInstrNEON.td:3601 |
| 2964 | VMAXuv4i16 = 2949, // ARMInstrNEON.td:3598 |
| 2965 | VMAXuv4i32 = 2950, // ARMInstrNEON.td:3609 |
| 2966 | VMAXuv8i16 = 2951, // ARMInstrNEON.td:3606 |
| 2967 | VMAXuv8i8 = 2952, // ARMInstrNEON.td:3657 |
| 2968 | VMINfd = 2953, // ARMInstrNEON.td:5778 |
| 2969 | VMINfq = 2954, // ARMInstrNEON.td:5781 |
| 2970 | VMINhd = 2955, // ARMInstrNEON.td:5784 |
| 2971 | VMINhq = 2956, // ARMInstrNEON.td:5788 |
| 2972 | VMINsv16i8 = 2957, // ARMInstrNEON.td:3660 |
| 2973 | VMINsv2i32 = 2958, // ARMInstrNEON.td:3601 |
| 2974 | VMINsv4i16 = 2959, // ARMInstrNEON.td:3598 |
| 2975 | VMINsv4i32 = 2960, // ARMInstrNEON.td:3609 |
| 2976 | VMINsv8i16 = 2961, // ARMInstrNEON.td:3606 |
| 2977 | VMINsv8i8 = 2962, // ARMInstrNEON.td:3657 |
| 2978 | VMINuv16i8 = 2963, // ARMInstrNEON.td:3660 |
| 2979 | VMINuv2i32 = 2964, // ARMInstrNEON.td:3601 |
| 2980 | VMINuv4i16 = 2965, // ARMInstrNEON.td:3598 |
| 2981 | VMINuv4i32 = 2966, // ARMInstrNEON.td:3609 |
| 2982 | VMINuv8i16 = 2967, // ARMInstrNEON.td:3606 |
| 2983 | VMINuv8i8 = 2968, // ARMInstrNEON.td:3657 |
| 2984 | VMLAD = 2969, // ARMInstrVFP.td:2115 |
| 2985 | VMLAH = 2970, // ARMInstrVFP.td:2139 |
| 2986 | VMLALslsv2i32 = 2971, // ARMInstrNEON.td:3951 |
| 2987 | VMLALslsv4i16 = 2972, // ARMInstrNEON.td:3949 |
| 2988 | VMLALsluv2i32 = 2973, // ARMInstrNEON.td:3951 |
| 2989 | VMLALsluv4i16 = 2974, // ARMInstrNEON.td:3949 |
| 2990 | VMLALsv2i64 = 2975, // ARMInstrNEON.td:3943 |
| 2991 | VMLALsv4i32 = 2976, // ARMInstrNEON.td:3941 |
| 2992 | VMLALsv8i16 = 2977, // ARMInstrNEON.td:3939 |
| 2993 | VMLALuv2i64 = 2978, // ARMInstrNEON.td:3943 |
| 2994 | VMLALuv4i32 = 2979, // ARMInstrNEON.td:3941 |
| 2995 | VMLALuv8i16 = 2980, // ARMInstrNEON.td:3939 |
| 2996 | VMLAS = 2981, // ARMInstrVFP.td:2125 |
| 2997 | VMLAfd = 2982, // ARMInstrNEON.td:4494 |
| 2998 | VMLAfq = 2983, // ARMInstrNEON.td:4497 |
| 2999 | VMLAhd = 2984, // ARMInstrNEON.td:4500 |
| 3000 | VMLAhq = 2985, // ARMInstrNEON.td:4503 |
| 3001 | VMLAslfd = 2986, // ARMInstrNEON.td:4508 |
| 3002 | VMLAslfq = 2987, // ARMInstrNEON.td:4511 |
| 3003 | VMLAslhd = 2988, // ARMInstrNEON.td:4514 |
| 3004 | VMLAslhq = 2989, // ARMInstrNEON.td:4517 |
| 3005 | VMLAslv2i32 = 2990, // ARMInstrNEON.td:3866 |
| 3006 | VMLAslv4i16 = 2991, // ARMInstrNEON.td:3864 |
| 3007 | VMLAslv4i32 = 2992, // ARMInstrNEON.td:3871 |
| 3008 | VMLAslv8i16 = 2993, // ARMInstrNEON.td:3868 |
| 3009 | VMLAv16i8 = 2994, // ARMInstrNEON.td:3852 |
| 3010 | VMLAv2i32 = 2995, // ARMInstrNEON.td:3848 |
| 3011 | VMLAv4i16 = 2996, // ARMInstrNEON.td:3846 |
| 3012 | VMLAv4i32 = 2997, // ARMInstrNEON.td:3856 |
| 3013 | VMLAv8i16 = 2998, // ARMInstrNEON.td:3854 |
| 3014 | VMLAv8i8 = 2999, // ARMInstrNEON.td:3844 |
| 3015 | VMLSD = 3000, // ARMInstrVFP.td:2159 |
| 3016 | VMLSH = 3001, // ARMInstrVFP.td:2183 |
| 3017 | VMLSLslsv2i32 = 3002, // ARMInstrNEON.td:3951 |
| 3018 | VMLSLslsv4i16 = 3003, // ARMInstrNEON.td:3949 |
| 3019 | VMLSLsluv2i32 = 3004, // ARMInstrNEON.td:3951 |
| 3020 | VMLSLsluv4i16 = 3005, // ARMInstrNEON.td:3949 |
| 3021 | VMLSLsv2i64 = 3006, // ARMInstrNEON.td:3943 |
| 3022 | VMLSLsv4i32 = 3007, // ARMInstrNEON.td:3941 |
| 3023 | VMLSLsv8i16 = 3008, // ARMInstrNEON.td:3939 |
| 3024 | VMLSLuv2i64 = 3009, // ARMInstrNEON.td:3943 |
| 3025 | VMLSLuv4i32 = 3010, // ARMInstrNEON.td:3941 |
| 3026 | VMLSLuv8i16 = 3011, // ARMInstrNEON.td:3939 |
| 3027 | VMLSS = 3012, // ARMInstrVFP.td:2169 |
| 3028 | VMLSfd = 3013, // ARMInstrNEON.td:4696 |
| 3029 | VMLSfq = 3014, // ARMInstrNEON.td:4699 |
| 3030 | VMLShd = 3015, // ARMInstrNEON.td:4702 |
| 3031 | VMLShq = 3016, // ARMInstrNEON.td:4705 |
| 3032 | VMLSslfd = 3017, // ARMInstrNEON.td:4710 |
| 3033 | VMLSslfq = 3018, // ARMInstrNEON.td:4713 |
| 3034 | VMLSslhd = 3019, // ARMInstrNEON.td:4716 |
| 3035 | VMLSslhq = 3020, // ARMInstrNEON.td:4719 |
| 3036 | VMLSslv2i32 = 3021, // ARMInstrNEON.td:3866 |
| 3037 | VMLSslv4i16 = 3022, // ARMInstrNEON.td:3864 |
| 3038 | VMLSslv4i32 = 3023, // ARMInstrNEON.td:3871 |
| 3039 | VMLSslv8i16 = 3024, // ARMInstrNEON.td:3868 |
| 3040 | VMLSv16i8 = 3025, // ARMInstrNEON.td:3852 |
| 3041 | VMLSv2i32 = 3026, // ARMInstrNEON.td:3848 |
| 3042 | VMLSv4i16 = 3027, // ARMInstrNEON.td:3846 |
| 3043 | VMLSv4i32 = 3028, // ARMInstrNEON.td:3856 |
| 3044 | VMLSv8i16 = 3029, // ARMInstrNEON.td:3854 |
| 3045 | VMLSv8i8 = 3030, // ARMInstrNEON.td:3844 |
| 3046 | VMMLA = 3031, // ARMInstrNEON.td:9278 |
| 3047 | VMOVD = 3032, // ARMInstrVFP.td:1193 |
| 3048 | VMOVDRR = 3033, // ARMInstrVFP.td:1332 |
| 3049 | VMOVH = 3034, // ARMInstrVFP.td:1205 |
| 3050 | VMOVHR = 3035, // ARMInstrVFP.td:1426 |
| 3051 | VMOVLsv2i64 = 3036, // ARMInstrNEON.td:3529 |
| 3052 | VMOVLsv4i32 = 3037, // ARMInstrNEON.td:3527 |
| 3053 | VMOVLsv8i16 = 3038, // ARMInstrNEON.td:3525 |
| 3054 | VMOVLuv2i64 = 3039, // ARMInstrNEON.td:3529 |
| 3055 | VMOVLuv4i32 = 3040, // ARMInstrNEON.td:3527 |
| 3056 | VMOVLuv8i16 = 3041, // ARMInstrNEON.td:3525 |
| 3057 | VMOVNv2i32 = 3042, // ARMInstrNEON.td:3498 |
| 3058 | VMOVNv4i16 = 3043, // ARMInstrNEON.td:3495 |
| 3059 | VMOVNv8i8 = 3044, // ARMInstrNEON.td:3492 |
| 3060 | VMOVRH = 3045, // ARMInstrVFP.td:1404 |
| 3061 | VMOVRRD = 3046, // ARMInstrVFP.td:1275 |
| 3062 | VMOVRRS = 3047, // ARMInstrVFP.td:1304 |
| 3063 | VMOVRS = 3048, // ARMInstrVFP.td:1225 |
| 3064 | VMOVS = 3049, // ARMInstrVFP.td:1198 |
| 3065 | VMOVSR = 3050, // ARMInstrVFP.td:1249 |
| 3066 | VMOVSRR = 3051, // ARMInstrVFP.td:1377 |
| 3067 | VMOVv16i8 = 3052, // ARMInstrNEON.td:6275 |
| 3068 | VMOVv1i64 = 3053, // ARMInstrNEON.td:6308 |
| 3069 | VMOVv2f32 = 3054, // ARMInstrNEON.td:6317 |
| 3070 | VMOVv2i32 = 3055, // ARMInstrNEON.td:6294 |
| 3071 | VMOVv2i64 = 3056, // ARMInstrNEON.td:6312 |
| 3072 | VMOVv4f32 = 3057, // ARMInstrNEON.td:6321 |
| 3073 | VMOVv4i16 = 3058, // ARMInstrNEON.td:6280 |
| 3074 | VMOVv4i32 = 3059, // ARMInstrNEON.td:6301 |
| 3075 | VMOVv8i16 = 3060, // ARMInstrNEON.td:6287 |
| 3076 | VMOVv8i8 = 3061, // ARMInstrNEON.td:6271 |
| 3077 | VMRS = 3062, // ARMInstrVFP.td:2604 |
| 3078 | VMRS_FPCXTNS = 3063, // ARMInstrVFP.td:2636 |
| 3079 | VMRS_FPCXTS = 3064, // ARMInstrVFP.td:2641 |
| 3080 | VMRS_FPEXC = 3065, // ARMInstrVFP.td:2610 |
| 3081 | VMRS_FPINST = 3066, // ARMInstrVFP.td:2622 |
| 3082 | VMRS_FPINST2 = 3067, // ARMInstrVFP.td:2624 |
| 3083 | VMRS_FPSCR_NZCVQC = 3068, // ARMInstrVFP.td:2628 |
| 3084 | VMRS_FPSID = 3069, // ARMInstrVFP.td:2612 |
| 3085 | VMRS_MVFR0 = 3070, // ARMInstrVFP.td:2614 |
| 3086 | VMRS_MVFR1 = 3071, // ARMInstrVFP.td:2616 |
| 3087 | VMRS_MVFR2 = 3072, // ARMInstrVFP.td:2619 |
| 3088 | VMRS_P0 = 3073, // ARMInstrVFP.td:2651 |
| 3089 | VMRS_VPR = 3074, // ARMInstrVFP.td:2648 |
| 3090 | VMSR = 3075, // ARMInstrVFP.td:2684 |
| 3091 | VMSR_FPCXTNS = 3076, // ARMInstrVFP.td:2700 |
| 3092 | VMSR_FPCXTS = 3077, // ARMInstrVFP.td:2705 |
| 3093 | VMSR_FPEXC = 3078, // ARMInstrVFP.td:2688 |
| 3094 | VMSR_FPINST = 3079, // ARMInstrVFP.td:2693 |
| 3095 | VMSR_FPINST2 = 3080, // ARMInstrVFP.td:2695 |
| 3096 | VMSR_FPSCR_NZCVQC = 3081, // ARMInstrVFP.td:2710 |
| 3097 | VMSR_FPSID = 3082, // ARMInstrVFP.td:2691 |
| 3098 | VMSR_P0 = 3083, // ARMInstrVFP.td:2722 |
| 3099 | VMSR_VPR = 3084, // ARMInstrVFP.td:2719 |
| 3100 | VMULD = 3085, // ARMInstrVFP.td:526 |
| 3101 | VMULH = 3086, // ARMInstrVFP.td:544 |
| 3102 | VMULLp64 = 3087, // ARMInstrNEON.td:4476 |
| 3103 | VMULLp8 = 3088, // ARMInstrNEON.td:4474 |
| 3104 | VMULLslsv2i32 = 3089, // ARMInstrNEON.td:3749 |
| 3105 | VMULLslsv4i16 = 3090, // ARMInstrNEON.td:3747 |
| 3106 | VMULLsluv2i32 = 3091, // ARMInstrNEON.td:3749 |
| 3107 | VMULLsluv4i16 = 3092, // ARMInstrNEON.td:3747 |
| 3108 | VMULLsv2i64 = 3093, // ARMInstrNEON.td:3739 |
| 3109 | VMULLsv4i32 = 3094, // ARMInstrNEON.td:3736 |
| 3110 | VMULLsv8i16 = 3095, // ARMInstrNEON.td:3733 |
| 3111 | VMULLuv2i64 = 3096, // ARMInstrNEON.td:3739 |
| 3112 | VMULLuv4i32 = 3097, // ARMInstrNEON.td:3736 |
| 3113 | VMULLuv8i16 = 3098, // ARMInstrNEON.td:3733 |
| 3114 | VMULS = 3099, // ARMInstrVFP.td:533 |
| 3115 | VMULfd = 3100, // ARMInstrNEON.td:4353 |
| 3116 | VMULfq = 3101, // ARMInstrNEON.td:4355 |
| 3117 | VMULhd = 3102, // ARMInstrNEON.td:4357 |
| 3118 | VMULhq = 3103, // ARMInstrNEON.td:4360 |
| 3119 | VMULpd = 3104, // ARMInstrNEON.td:4349 |
| 3120 | VMULpq = 3105, // ARMInstrNEON.td:4351 |
| 3121 | VMULslfd = 3106, // ARMInstrNEON.td:4364 |
| 3122 | VMULslfq = 3107, // ARMInstrNEON.td:4365 |
| 3123 | VMULslhd = 3108, // ARMInstrNEON.td:4367 |
| 3124 | VMULslhq = 3109, // ARMInstrNEON.td:4369 |
| 3125 | VMULslv2i32 = 3110, // ARMInstrNEON.td:3567 |
| 3126 | VMULslv4i16 = 3111, // ARMInstrNEON.td:3566 |
| 3127 | VMULslv4i32 = 3112, // ARMInstrNEON.td:3569 |
| 3128 | VMULslv8i16 = 3113, // ARMInstrNEON.td:3568 |
| 3129 | VMULv16i8 = 3114, // ARMInstrNEON.td:3554 |
| 3130 | VMULv2i32 = 3115, // ARMInstrNEON.td:3549 |
| 3131 | VMULv4i16 = 3116, // ARMInstrNEON.td:3546 |
| 3132 | VMULv4i32 = 3117, // ARMInstrNEON.td:3560 |
| 3133 | VMULv8i16 = 3118, // ARMInstrNEON.td:3557 |
| 3134 | VMULv8i8 = 3119, // ARMInstrNEON.td:3543 |
| 3135 | VMVNd = 3120, // ARMInstrNEON.td:5544 |
| 3136 | VMVNq = 3121, // ARMInstrNEON.td:5548 |
| 3137 | VMVNv2i32 = 3122, // ARMInstrNEON.td:5528 |
| 3138 | VMVNv4i16 = 3123, // ARMInstrNEON.td:5514 |
| 3139 | VMVNv4i32 = 3124, // ARMInstrNEON.td:5535 |
| 3140 | VMVNv8i16 = 3125, // ARMInstrNEON.td:5521 |
| 3141 | VNEGD = 3126, // ARMInstrVFP.td:1063 |
| 3142 | VNEGH = 3127, // ARMInstrVFP.td:1077 |
| 3143 | VNEGS = 3128, // ARMInstrVFP.td:1068 |
| 3144 | VNEGf32q = 3129, // ARMInstrNEON.td:6200 |
| 3145 | VNEGfd = 3130, // ARMInstrNEON.td:6196 |
| 3146 | VNEGhd = 3131, // ARMInstrNEON.td:6204 |
| 3147 | VNEGhq = 3132, // ARMInstrNEON.td:6209 |
| 3148 | VNEGs16d = 3133, // ARMInstrNEON.td:6189 |
| 3149 | VNEGs16q = 3134, // ARMInstrNEON.td:6192 |
| 3150 | VNEGs32d = 3135, // ARMInstrNEON.td:6190 |
| 3151 | VNEGs32q = 3136, // ARMInstrNEON.td:6193 |
| 3152 | VNEGs8d = 3137, // ARMInstrNEON.td:6188 |
| 3153 | VNEGs8q = 3138, // ARMInstrNEON.td:6191 |
| 3154 | VNMLAD = 3139, // ARMInstrVFP.td:2202 |
| 3155 | VNMLAH = 3140, // ARMInstrVFP.td:2226 |
| 3156 | VNMLAS = 3141, // ARMInstrVFP.td:2212 |
| 3157 | VNMLSD = 3142, // ARMInstrVFP.td:2257 |
| 3158 | VNMLSH = 3143, // ARMInstrVFP.td:2280 |
| 3159 | VNMLSS = 3144, // ARMInstrVFP.td:2267 |
| 3160 | VNMULD = 3145, // ARMInstrVFP.td:551 |
| 3161 | VNMULH = 3146, // ARMInstrVFP.td:569 |
| 3162 | VNMULS = 3147, // ARMInstrVFP.td:558 |
| 3163 | VORNd = 3148, // ARMInstrNEON.td:5494 |
| 3164 | VORNq = 3149, // ARMInstrNEON.td:5499 |
| 3165 | VORRd = 3150, // ARMInstrNEON.td:5373 |
| 3166 | VORRiv2i32 = 3151, // ARMInstrNEON.td:5410 |
| 3167 | VORRiv4i16 = 3152, // ARMInstrNEON.td:5401 |
| 3168 | VORRiv4i32 = 3153, // ARMInstrNEON.td:5428 |
| 3169 | VORRiv8i16 = 3154, // ARMInstrNEON.td:5419 |
| 3170 | VORRq = 3155, // ARMInstrNEON.td:5375 |
| 3171 | VPADALsv16i8 = 3156, // ARMInstrNEON.td:4038 |
| 3172 | VPADALsv2i32 = 3157, // ARMInstrNEON.td:4034 |
| 3173 | VPADALsv4i16 = 3158, // ARMInstrNEON.td:4032 |
| 3174 | VPADALsv4i32 = 3159, // ARMInstrNEON.td:4042 |
| 3175 | VPADALsv8i16 = 3160, // ARMInstrNEON.td:4040 |
| 3176 | VPADALsv8i8 = 3161, // ARMInstrNEON.td:4030 |
| 3177 | VPADALuv16i8 = 3162, // ARMInstrNEON.td:4038 |
| 3178 | VPADALuv2i32 = 3163, // ARMInstrNEON.td:4034 |
| 3179 | VPADALuv4i16 = 3164, // ARMInstrNEON.td:4032 |
| 3180 | VPADALuv4i32 = 3165, // ARMInstrNEON.td:4042 |
| 3181 | VPADALuv8i16 = 3166, // ARMInstrNEON.td:4040 |
| 3182 | VPADALuv8i8 = 3167, // ARMInstrNEON.td:4030 |
| 3183 | VPADDLsv16i8 = 3168, // ARMInstrNEON.td:4015 |
| 3184 | VPADDLsv2i32 = 3169, // ARMInstrNEON.td:4011 |
| 3185 | VPADDLsv4i16 = 3170, // ARMInstrNEON.td:4009 |
| 3186 | VPADDLsv4i32 = 3171, // ARMInstrNEON.td:4019 |
| 3187 | VPADDLsv8i16 = 3172, // ARMInstrNEON.td:4017 |
| 3188 | VPADDLsv8i8 = 3173, // ARMInstrNEON.td:4007 |
| 3189 | VPADDLuv16i8 = 3174, // ARMInstrNEON.td:4015 |
| 3190 | VPADDLuv2i32 = 3175, // ARMInstrNEON.td:4011 |
| 3191 | VPADDLuv4i16 = 3176, // ARMInstrNEON.td:4009 |
| 3192 | VPADDLuv4i32 = 3177, // ARMInstrNEON.td:4019 |
| 3193 | VPADDLuv8i16 = 3178, // ARMInstrNEON.td:4017 |
| 3194 | VPADDLuv8i8 = 3179, // ARMInstrNEON.td:4007 |
| 3195 | VPADDf = 3180, // ARMInstrNEON.td:5825 |
| 3196 | VPADDh = 3181, // ARMInstrNEON.td:5828 |
| 3197 | VPADDi16 = 3182, // ARMInstrNEON.td:5819 |
| 3198 | VPADDi32 = 3183, // ARMInstrNEON.td:5822 |
| 3199 | VPADDi8 = 3184, // ARMInstrNEON.td:5816 |
| 3200 | VPMAXf = 3185, // ARMInstrNEON.td:5858 |
| 3201 | VPMAXh = 3186, // ARMInstrNEON.td:5860 |
| 3202 | VPMAXs16 = 3187, // ARMInstrNEON.td:5848 |
| 3203 | VPMAXs32 = 3188, // ARMInstrNEON.td:5850 |
| 3204 | VPMAXs8 = 3189, // ARMInstrNEON.td:5846 |
| 3205 | VPMAXu16 = 3190, // ARMInstrNEON.td:5854 |
| 3206 | VPMAXu32 = 3191, // ARMInstrNEON.td:5856 |
| 3207 | VPMAXu8 = 3192, // ARMInstrNEON.td:5852 |
| 3208 | VPMINf = 3193, // ARMInstrNEON.td:5877 |
| 3209 | VPMINh = 3194, // ARMInstrNEON.td:5879 |
| 3210 | VPMINs16 = 3195, // ARMInstrNEON.td:5867 |
| 3211 | VPMINs32 = 3196, // ARMInstrNEON.td:5869 |
| 3212 | VPMINs8 = 3197, // ARMInstrNEON.td:5865 |
| 3213 | VPMINu16 = 3198, // ARMInstrNEON.td:5873 |
| 3214 | VPMINu32 = 3199, // ARMInstrNEON.td:5875 |
| 3215 | VPMINu8 = 3200, // ARMInstrNEON.td:5871 |
| 3216 | VQABSv16i8 = 3201, // ARMInstrNEON.td:3477 |
| 3217 | VQABSv2i32 = 3202, // ARMInstrNEON.td:3473 |
| 3218 | VQABSv4i16 = 3203, // ARMInstrNEON.td:3471 |
| 3219 | VQABSv4i32 = 3204, // ARMInstrNEON.td:3481 |
| 3220 | VQABSv8i16 = 3205, // ARMInstrNEON.td:3479 |
| 3221 | VQABSv8i8 = 3206, // ARMInstrNEON.td:3469 |
| 3222 | VQADDsv16i8 = 3207, // ARMInstrNEON.td:3660 |
| 3223 | VQADDsv1i64 = 3208, // ARMInstrNEON.td:3688 |
| 3224 | VQADDsv2i32 = 3209, // ARMInstrNEON.td:3601 |
| 3225 | VQADDsv2i64 = 3210, // ARMInstrNEON.td:3691 |
| 3226 | VQADDsv4i16 = 3211, // ARMInstrNEON.td:3598 |
| 3227 | VQADDsv4i32 = 3212, // ARMInstrNEON.td:3609 |
| 3228 | VQADDsv8i16 = 3213, // ARMInstrNEON.td:3606 |
| 3229 | VQADDsv8i8 = 3214, // ARMInstrNEON.td:3657 |
| 3230 | VQADDuv16i8 = 3215, // ARMInstrNEON.td:3660 |
| 3231 | VQADDuv1i64 = 3216, // ARMInstrNEON.td:3688 |
| 3232 | VQADDuv2i32 = 3217, // ARMInstrNEON.td:3601 |
| 3233 | VQADDuv2i64 = 3218, // ARMInstrNEON.td:3691 |
| 3234 | VQADDuv4i16 = 3219, // ARMInstrNEON.td:3598 |
| 3235 | VQADDuv4i32 = 3220, // ARMInstrNEON.td:3609 |
| 3236 | VQADDuv8i16 = 3221, // ARMInstrNEON.td:3606 |
| 3237 | VQADDuv8i8 = 3222, // ARMInstrNEON.td:3657 |
| 3238 | VQDMLALslv2i32 = 3223, // ARMInstrNEON.td:3972 |
| 3239 | VQDMLALslv4i16 = 3224, // ARMInstrNEON.td:3970 |
| 3240 | VQDMLALv2i64 = 3225, // ARMInstrNEON.td:3964 |
| 3241 | VQDMLALv4i32 = 3226, // ARMInstrNEON.td:3962 |
| 3242 | VQDMLSLslv2i32 = 3227, // ARMInstrNEON.td:3972 |
| 3243 | VQDMLSLslv4i16 = 3228, // ARMInstrNEON.td:3970 |
| 3244 | VQDMLSLv2i64 = 3229, // ARMInstrNEON.td:3964 |
| 3245 | VQDMLSLv4i32 = 3230, // ARMInstrNEON.td:3962 |
| 3246 | VQDMULHslv2i32 = 3231, // ARMInstrNEON.td:3641 |
| 3247 | VQDMULHslv4i16 = 3232, // ARMInstrNEON.td:3639 |
| 3248 | VQDMULHslv4i32 = 3233, // ARMInstrNEON.td:3645 |
| 3249 | VQDMULHslv8i16 = 3234, // ARMInstrNEON.td:3643 |
| 3250 | VQDMULHv2i32 = 3235, // ARMInstrNEON.td:3601 |
| 3251 | VQDMULHv4i16 = 3236, // ARMInstrNEON.td:3598 |
| 3252 | VQDMULHv4i32 = 3237, // ARMInstrNEON.td:3609 |
| 3253 | VQDMULHv8i16 = 3238, // ARMInstrNEON.td:3606 |
| 3254 | VQDMULLslv2i32 = 3239, // ARMInstrNEON.td:3788 |
| 3255 | VQDMULLslv4i16 = 3240, // ARMInstrNEON.td:3786 |
| 3256 | VQDMULLv2i64 = 3241, // ARMInstrNEON.td:3778 |
| 3257 | VQDMULLv4i32 = 3242, // ARMInstrNEON.td:3775 |
| 3258 | VQMOVNsuv2i32 = 3243, // ARMInstrNEON.td:3515 |
| 3259 | VQMOVNsuv4i16 = 3244, // ARMInstrNEON.td:3512 |
| 3260 | VQMOVNsuv8i8 = 3245, // ARMInstrNEON.td:3509 |
| 3261 | VQMOVNsv2i32 = 3246, // ARMInstrNEON.td:3515 |
| 3262 | VQMOVNsv4i16 = 3247, // ARMInstrNEON.td:3512 |
| 3263 | VQMOVNsv8i8 = 3248, // ARMInstrNEON.td:3509 |
| 3264 | VQMOVNuv2i32 = 3249, // ARMInstrNEON.td:3515 |
| 3265 | VQMOVNuv4i16 = 3250, // ARMInstrNEON.td:3512 |
| 3266 | VQMOVNuv8i8 = 3251, // ARMInstrNEON.td:3509 |
| 3267 | VQNEGv16i8 = 3252, // ARMInstrNEON.td:3477 |
| 3268 | VQNEGv2i32 = 3253, // ARMInstrNEON.td:3473 |
| 3269 | VQNEGv4i16 = 3254, // ARMInstrNEON.td:3471 |
| 3270 | VQNEGv4i32 = 3255, // ARMInstrNEON.td:3481 |
| 3271 | VQNEGv8i16 = 3256, // ARMInstrNEON.td:3479 |
| 3272 | VQNEGv8i8 = 3257, // ARMInstrNEON.td:3469 |
| 3273 | VQRDMLAHslv2i32 = 3258, // ARMInstrNEON.td:3866 |
| 3274 | VQRDMLAHslv4i16 = 3259, // ARMInstrNEON.td:3864 |
| 3275 | VQRDMLAHslv4i32 = 3260, // ARMInstrNEON.td:3871 |
| 3276 | VQRDMLAHslv8i16 = 3261, // ARMInstrNEON.td:3868 |
| 3277 | VQRDMLAHv2i32 = 3262, // ARMInstrNEON.td:3908 |
| 3278 | VQRDMLAHv4i16 = 3263, // ARMInstrNEON.td:3906 |
| 3279 | VQRDMLAHv4i32 = 3264, // ARMInstrNEON.td:3914 |
| 3280 | VQRDMLAHv8i16 = 3265, // ARMInstrNEON.td:3912 |
| 3281 | VQRDMLSHslv2i32 = 3266, // ARMInstrNEON.td:3866 |
| 3282 | VQRDMLSHslv4i16 = 3267, // ARMInstrNEON.td:3864 |
| 3283 | VQRDMLSHslv4i32 = 3268, // ARMInstrNEON.td:3871 |
| 3284 | VQRDMLSHslv8i16 = 3269, // ARMInstrNEON.td:3868 |
| 3285 | VQRDMLSHv2i32 = 3270, // ARMInstrNEON.td:3908 |
| 3286 | VQRDMLSHv4i16 = 3271, // ARMInstrNEON.td:3906 |
| 3287 | VQRDMLSHv4i32 = 3272, // ARMInstrNEON.td:3914 |
| 3288 | VQRDMLSHv8i16 = 3273, // ARMInstrNEON.td:3912 |
| 3289 | VQRDMULHslv2i32 = 3274, // ARMInstrNEON.td:3641 |
| 3290 | VQRDMULHslv4i16 = 3275, // ARMInstrNEON.td:3639 |
| 3291 | VQRDMULHslv4i32 = 3276, // ARMInstrNEON.td:3645 |
| 3292 | VQRDMULHslv8i16 = 3277, // ARMInstrNEON.td:3643 |
| 3293 | VQRDMULHv2i32 = 3278, // ARMInstrNEON.td:3601 |
| 3294 | VQRDMULHv4i16 = 3279, // ARMInstrNEON.td:3598 |
| 3295 | VQRDMULHv4i32 = 3280, // ARMInstrNEON.td:3609 |
| 3296 | VQRDMULHv8i16 = 3281, // ARMInstrNEON.td:3606 |
| 3297 | VQRSHLsv16i8 = 3282, // ARMInstrNEON.td:3674 |
| 3298 | VQRSHLsv1i64 = 3283, // ARMInstrNEON.td:3702 |
| 3299 | VQRSHLsv2i32 = 3284, // ARMInstrNEON.td:3622 |
| 3300 | VQRSHLsv2i64 = 3285, // ARMInstrNEON.td:3705 |
| 3301 | VQRSHLsv4i16 = 3286, // ARMInstrNEON.td:3619 |
| 3302 | VQRSHLsv4i32 = 3287, // ARMInstrNEON.td:3630 |
| 3303 | VQRSHLsv8i16 = 3288, // ARMInstrNEON.td:3627 |
| 3304 | VQRSHLsv8i8 = 3289, // ARMInstrNEON.td:3671 |
| 3305 | VQRSHLuv16i8 = 3290, // ARMInstrNEON.td:3674 |
| 3306 | VQRSHLuv1i64 = 3291, // ARMInstrNEON.td:3702 |
| 3307 | VQRSHLuv2i32 = 3292, // ARMInstrNEON.td:3622 |
| 3308 | VQRSHLuv2i64 = 3293, // ARMInstrNEON.td:3705 |
| 3309 | VQRSHLuv4i16 = 3294, // ARMInstrNEON.td:3619 |
| 3310 | VQRSHLuv4i32 = 3295, // ARMInstrNEON.td:3630 |
| 3311 | VQRSHLuv8i16 = 3296, // ARMInstrNEON.td:3627 |
| 3312 | VQRSHLuv8i8 = 3297, // ARMInstrNEON.td:3671 |
| 3313 | VQRSHRNsv2i32 = 3298, // ARMInstrNEON.td:4274 |
| 3314 | VQRSHRNsv4i16 = 3299, // ARMInstrNEON.td:4269 |
| 3315 | VQRSHRNsv8i8 = 3300, // ARMInstrNEON.td:4264 |
| 3316 | VQRSHRNuv2i32 = 3301, // ARMInstrNEON.td:4274 |
| 3317 | VQRSHRNuv4i16 = 3302, // ARMInstrNEON.td:4269 |
| 3318 | VQRSHRNuv8i8 = 3303, // ARMInstrNEON.td:4264 |
| 3319 | VQRSHRUNv2i32 = 3304, // ARMInstrNEON.td:4274 |
| 3320 | VQRSHRUNv4i16 = 3305, // ARMInstrNEON.td:4269 |
| 3321 | VQRSHRUNv8i8 = 3306, // ARMInstrNEON.td:4264 |
| 3322 | VQSHLsiv16i8 = 3307, // ARMInstrNEON.td:4071 |
| 3323 | VQSHLsiv1i64 = 3308, // ARMInstrNEON.td:4066 |
| 3324 | VQSHLsiv2i32 = 3309, // ARMInstrNEON.td:4062 |
| 3325 | VQSHLsiv2i64 = 3310, // ARMInstrNEON.td:4083 |
| 3326 | VQSHLsiv4i16 = 3311, // ARMInstrNEON.td:4058 |
| 3327 | VQSHLsiv4i32 = 3312, // ARMInstrNEON.td:4079 |
| 3328 | VQSHLsiv8i16 = 3313, // ARMInstrNEON.td:4075 |
| 3329 | VQSHLsiv8i8 = 3314, // ARMInstrNEON.td:4054 |
| 3330 | VQSHLsuv16i8 = 3315, // ARMInstrNEON.td:4071 |
| 3331 | VQSHLsuv1i64 = 3316, // ARMInstrNEON.td:4066 |
| 3332 | VQSHLsuv2i32 = 3317, // ARMInstrNEON.td:4062 |
| 3333 | VQSHLsuv2i64 = 3318, // ARMInstrNEON.td:4083 |
| 3334 | VQSHLsuv4i16 = 3319, // ARMInstrNEON.td:4058 |
| 3335 | VQSHLsuv4i32 = 3320, // ARMInstrNEON.td:4079 |
| 3336 | VQSHLsuv8i16 = 3321, // ARMInstrNEON.td:4075 |
| 3337 | VQSHLsuv8i8 = 3322, // ARMInstrNEON.td:4054 |
| 3338 | VQSHLsv16i8 = 3323, // ARMInstrNEON.td:3674 |
| 3339 | VQSHLsv1i64 = 3324, // ARMInstrNEON.td:3702 |
| 3340 | VQSHLsv2i32 = 3325, // ARMInstrNEON.td:3622 |
| 3341 | VQSHLsv2i64 = 3326, // ARMInstrNEON.td:3705 |
| 3342 | VQSHLsv4i16 = 3327, // ARMInstrNEON.td:3619 |
| 3343 | VQSHLsv4i32 = 3328, // ARMInstrNEON.td:3630 |
| 3344 | VQSHLsv8i16 = 3329, // ARMInstrNEON.td:3627 |
| 3345 | VQSHLsv8i8 = 3330, // ARMInstrNEON.td:3671 |
| 3346 | VQSHLuiv16i8 = 3331, // ARMInstrNEON.td:4071 |
| 3347 | VQSHLuiv1i64 = 3332, // ARMInstrNEON.td:4066 |
| 3348 | VQSHLuiv2i32 = 3333, // ARMInstrNEON.td:4062 |
| 3349 | VQSHLuiv2i64 = 3334, // ARMInstrNEON.td:4083 |
| 3350 | VQSHLuiv4i16 = 3335, // ARMInstrNEON.td:4058 |
| 3351 | VQSHLuiv4i32 = 3336, // ARMInstrNEON.td:4079 |
| 3352 | VQSHLuiv8i16 = 3337, // ARMInstrNEON.td:4075 |
| 3353 | VQSHLuiv8i8 = 3338, // ARMInstrNEON.td:4054 |
| 3354 | VQSHLuv16i8 = 3339, // ARMInstrNEON.td:3674 |
| 3355 | VQSHLuv1i64 = 3340, // ARMInstrNEON.td:3702 |
| 3356 | VQSHLuv2i32 = 3341, // ARMInstrNEON.td:3622 |
| 3357 | VQSHLuv2i64 = 3342, // ARMInstrNEON.td:3705 |
| 3358 | VQSHLuv4i16 = 3343, // ARMInstrNEON.td:3619 |
| 3359 | VQSHLuv4i32 = 3344, // ARMInstrNEON.td:3630 |
| 3360 | VQSHLuv8i16 = 3345, // ARMInstrNEON.td:3627 |
| 3361 | VQSHLuv8i8 = 3346, // ARMInstrNEON.td:3671 |
| 3362 | VQSHRNsv2i32 = 3347, // ARMInstrNEON.td:4274 |
| 3363 | VQSHRNsv4i16 = 3348, // ARMInstrNEON.td:4269 |
| 3364 | VQSHRNsv8i8 = 3349, // ARMInstrNEON.td:4264 |
| 3365 | VQSHRNuv2i32 = 3350, // ARMInstrNEON.td:4274 |
| 3366 | VQSHRNuv4i16 = 3351, // ARMInstrNEON.td:4269 |
| 3367 | VQSHRNuv8i8 = 3352, // ARMInstrNEON.td:4264 |
| 3368 | VQSHRUNv2i32 = 3353, // ARMInstrNEON.td:4274 |
| 3369 | VQSHRUNv4i16 = 3354, // ARMInstrNEON.td:4269 |
| 3370 | VQSHRUNv8i8 = 3355, // ARMInstrNEON.td:4264 |
| 3371 | VQSUBsv16i8 = 3356, // ARMInstrNEON.td:3660 |
| 3372 | VQSUBsv1i64 = 3357, // ARMInstrNEON.td:3688 |
| 3373 | VQSUBsv2i32 = 3358, // ARMInstrNEON.td:3601 |
| 3374 | VQSUBsv2i64 = 3359, // ARMInstrNEON.td:3691 |
| 3375 | VQSUBsv4i16 = 3360, // ARMInstrNEON.td:3598 |
| 3376 | VQSUBsv4i32 = 3361, // ARMInstrNEON.td:3609 |
| 3377 | VQSUBsv8i16 = 3362, // ARMInstrNEON.td:3606 |
| 3378 | VQSUBsv8i8 = 3363, // ARMInstrNEON.td:3657 |
| 3379 | VQSUBuv16i8 = 3364, // ARMInstrNEON.td:3660 |
| 3380 | VQSUBuv1i64 = 3365, // ARMInstrNEON.td:3688 |
| 3381 | VQSUBuv2i32 = 3366, // ARMInstrNEON.td:3601 |
| 3382 | VQSUBuv2i64 = 3367, // ARMInstrNEON.td:3691 |
| 3383 | VQSUBuv4i16 = 3368, // ARMInstrNEON.td:3598 |
| 3384 | VQSUBuv4i32 = 3369, // ARMInstrNEON.td:3609 |
| 3385 | VQSUBuv8i16 = 3370, // ARMInstrNEON.td:3606 |
| 3386 | VQSUBuv8i8 = 3371, // ARMInstrNEON.td:3657 |
| 3387 | VRADDHNv2i32 = 3372, // ARMInstrNEON.td:3721 |
| 3388 | VRADDHNv4i16 = 3373, // ARMInstrNEON.td:3718 |
| 3389 | VRADDHNv8i8 = 3374, // ARMInstrNEON.td:3715 |
| 3390 | VRECPEd = 3375, // ARMInstrNEON.td:5886 |
| 3391 | VRECPEfd = 3376, // ARMInstrNEON.td:5892 |
| 3392 | VRECPEfq = 3377, // ARMInstrNEON.td:5895 |
| 3393 | VRECPEhd = 3378, // ARMInstrNEON.td:5898 |
| 3394 | VRECPEhq = 3379, // ARMInstrNEON.td:5902 |
| 3395 | VRECPEq = 3380, // ARMInstrNEON.td:5889 |
| 3396 | VRECPSfd = 3381, // ARMInstrNEON.td:5908 |
| 3397 | VRECPSfq = 3382, // ARMInstrNEON.td:5911 |
| 3398 | VRECPShd = 3383, // ARMInstrNEON.td:5914 |
| 3399 | VRECPShq = 3384, // ARMInstrNEON.td:5918 |
| 3400 | VREV16d8 = 3385, // ARMInstrNEON.td:7084 |
| 3401 | VREV16q8 = 3386, // ARMInstrNEON.td:7085 |
| 3402 | VREV32d16 = 3387, // ARMInstrNEON.td:7055 |
| 3403 | VREV32d8 = 3388, // ARMInstrNEON.td:7054 |
| 3404 | VREV32q16 = 3389, // ARMInstrNEON.td:7058 |
| 3405 | VREV32q8 = 3390, // ARMInstrNEON.td:7057 |
| 3406 | VREV64d16 = 3391, // ARMInstrNEON.td:7018 |
| 3407 | VREV64d32 = 3392, // ARMInstrNEON.td:7019 |
| 3408 | VREV64d8 = 3393, // ARMInstrNEON.td:7017 |
| 3409 | VREV64q16 = 3394, // ARMInstrNEON.td:7025 |
| 3410 | VREV64q32 = 3395, // ARMInstrNEON.td:7026 |
| 3411 | VREV64q8 = 3396, // ARMInstrNEON.td:7024 |
| 3412 | VRHADDsv16i8 = 3397, // ARMInstrNEON.td:3660 |
| 3413 | VRHADDsv2i32 = 3398, // ARMInstrNEON.td:3601 |
| 3414 | VRHADDsv4i16 = 3399, // ARMInstrNEON.td:3598 |
| 3415 | VRHADDsv4i32 = 3400, // ARMInstrNEON.td:3609 |
| 3416 | VRHADDsv8i16 = 3401, // ARMInstrNEON.td:3606 |
| 3417 | VRHADDsv8i8 = 3402, // ARMInstrNEON.td:3657 |
| 3418 | VRHADDuv16i8 = 3403, // ARMInstrNEON.td:3660 |
| 3419 | VRHADDuv2i32 = 3404, // ARMInstrNEON.td:3601 |
| 3420 | VRHADDuv4i16 = 3405, // ARMInstrNEON.td:3598 |
| 3421 | VRHADDuv4i32 = 3406, // ARMInstrNEON.td:3609 |
| 3422 | VRHADDuv8i16 = 3407, // ARMInstrNEON.td:3606 |
| 3423 | VRHADDuv8i8 = 3408, // ARMInstrNEON.td:3657 |
| 3424 | VRINTAD = 3409, // ARMInstrVFP.td:1145 |
| 3425 | VRINTAH = 3410, // ARMInstrVFP.td:1131 |
| 3426 | VRINTANDf = 3411, // ARMInstrNEON.td:7327 |
| 3427 | VRINTANDh = 3412, // ARMInstrNEON.td:7337 |
| 3428 | VRINTANQf = 3413, // ARMInstrNEON.td:7332 |
| 3429 | VRINTANQh = 3414, // ARMInstrNEON.td:7343 |
| 3430 | VRINTAS = 3415, // ARMInstrVFP.td:1138 |
| 3431 | VRINTMD = 3416, // ARMInstrVFP.td:1145 |
| 3432 | VRINTMH = 3417, // ARMInstrVFP.td:1131 |
| 3433 | VRINTMNDf = 3418, // ARMInstrNEON.td:7327 |
| 3434 | VRINTMNDh = 3419, // ARMInstrNEON.td:7337 |
| 3435 | VRINTMNQf = 3420, // ARMInstrNEON.td:7332 |
| 3436 | VRINTMNQh = 3421, // ARMInstrNEON.td:7343 |
| 3437 | VRINTMS = 3422, // ARMInstrVFP.td:1138 |
| 3438 | VRINTND = 3423, // ARMInstrVFP.td:1145 |
| 3439 | VRINTNH = 3424, // ARMInstrVFP.td:1131 |
| 3440 | VRINTNNDf = 3425, // ARMInstrNEON.td:7327 |
| 3441 | VRINTNNDh = 3426, // ARMInstrNEON.td:7337 |
| 3442 | VRINTNNQf = 3427, // ARMInstrNEON.td:7332 |
| 3443 | VRINTNNQh = 3428, // ARMInstrNEON.td:7343 |
| 3444 | VRINTNS = 3429, // ARMInstrVFP.td:1138 |
| 3445 | VRINTPD = 3430, // ARMInstrVFP.td:1145 |
| 3446 | VRINTPH = 3431, // ARMInstrVFP.td:1131 |
| 3447 | VRINTPNDf = 3432, // ARMInstrNEON.td:7327 |
| 3448 | VRINTPNDh = 3433, // ARMInstrNEON.td:7337 |
| 3449 | VRINTPNQf = 3434, // ARMInstrNEON.td:7332 |
| 3450 | VRINTPNQh = 3435, // ARMInstrNEON.td:7343 |
| 3451 | VRINTPS = 3436, // ARMInstrVFP.td:1138 |
| 3452 | VRINTRD = 3437, // ARMInstrVFP.td:1102 |
| 3453 | VRINTRH = 3438, // ARMInstrVFP.td:1085 |
| 3454 | VRINTRS = 3439, // ARMInstrVFP.td:1094 |
| 3455 | VRINTXD = 3440, // ARMInstrVFP.td:1102 |
| 3456 | VRINTXH = 3441, // ARMInstrVFP.td:1085 |
| 3457 | VRINTXNDf = 3442, // ARMInstrNEON.td:7327 |
| 3458 | VRINTXNDh = 3443, // ARMInstrNEON.td:7337 |
| 3459 | VRINTXNQf = 3444, // ARMInstrNEON.td:7332 |
| 3460 | VRINTXNQh = 3445, // ARMInstrNEON.td:7343 |
| 3461 | VRINTXS = 3446, // ARMInstrVFP.td:1094 |
| 3462 | VRINTZD = 3447, // ARMInstrVFP.td:1102 |
| 3463 | VRINTZH = 3448, // ARMInstrVFP.td:1085 |
| 3464 | VRINTZNDf = 3449, // ARMInstrNEON.td:7327 |
| 3465 | VRINTZNDh = 3450, // ARMInstrNEON.td:7337 |
| 3466 | VRINTZNQf = 3451, // ARMInstrNEON.td:7332 |
| 3467 | VRINTZNQh = 3452, // ARMInstrNEON.td:7343 |
| 3468 | VRINTZS = 3453, // ARMInstrVFP.td:1094 |
| 3469 | VRSHLsv16i8 = 3454, // ARMInstrNEON.td:3674 |
| 3470 | VRSHLsv1i64 = 3455, // ARMInstrNEON.td:3702 |
| 3471 | VRSHLsv2i32 = 3456, // ARMInstrNEON.td:3622 |
| 3472 | VRSHLsv2i64 = 3457, // ARMInstrNEON.td:3705 |
| 3473 | VRSHLsv4i16 = 3458, // ARMInstrNEON.td:3619 |
| 3474 | VRSHLsv4i32 = 3459, // ARMInstrNEON.td:3630 |
| 3475 | VRSHLsv8i16 = 3460, // ARMInstrNEON.td:3627 |
| 3476 | VRSHLsv8i8 = 3461, // ARMInstrNEON.td:3671 |
| 3477 | VRSHLuv16i8 = 3462, // ARMInstrNEON.td:3674 |
| 3478 | VRSHLuv1i64 = 3463, // ARMInstrNEON.td:3702 |
| 3479 | VRSHLuv2i32 = 3464, // ARMInstrNEON.td:3622 |
| 3480 | VRSHLuv2i64 = 3465, // ARMInstrNEON.td:3705 |
| 3481 | VRSHLuv4i16 = 3466, // ARMInstrNEON.td:3619 |
| 3482 | VRSHLuv4i32 = 3467, // ARMInstrNEON.td:3630 |
| 3483 | VRSHLuv8i16 = 3468, // ARMInstrNEON.td:3627 |
| 3484 | VRSHLuv8i8 = 3469, // ARMInstrNEON.td:3671 |
| 3485 | VRSHRNv2i32 = 3470, // ARMInstrNEON.td:4274 |
| 3486 | VRSHRNv4i16 = 3471, // ARMInstrNEON.td:4269 |
| 3487 | VRSHRNv8i8 = 3472, // ARMInstrNEON.td:4264 |
| 3488 | VRSHRsv16i8 = 3473, // ARMInstrNEON.td:4108 |
| 3489 | VRSHRsv1i64 = 3474, // ARMInstrNEON.td:4103 |
| 3490 | VRSHRsv2i32 = 3475, // ARMInstrNEON.td:4099 |
| 3491 | VRSHRsv2i64 = 3476, // ARMInstrNEON.td:4120 |
| 3492 | VRSHRsv4i16 = 3477, // ARMInstrNEON.td:4095 |
| 3493 | VRSHRsv4i32 = 3478, // ARMInstrNEON.td:4116 |
| 3494 | VRSHRsv8i16 = 3479, // ARMInstrNEON.td:4112 |
| 3495 | VRSHRsv8i8 = 3480, // ARMInstrNEON.td:4091 |
| 3496 | VRSHRuv16i8 = 3481, // ARMInstrNEON.td:4108 |
| 3497 | VRSHRuv1i64 = 3482, // ARMInstrNEON.td:4103 |
| 3498 | VRSHRuv2i32 = 3483, // ARMInstrNEON.td:4099 |
| 3499 | VRSHRuv2i64 = 3484, // ARMInstrNEON.td:4120 |
| 3500 | VRSHRuv4i16 = 3485, // ARMInstrNEON.td:4095 |
| 3501 | VRSHRuv4i32 = 3486, // ARMInstrNEON.td:4116 |
| 3502 | VRSHRuv8i16 = 3487, // ARMInstrNEON.td:4112 |
| 3503 | VRSHRuv8i8 = 3488, // ARMInstrNEON.td:4091 |
| 3504 | VRSQRTEd = 3489, // ARMInstrNEON.td:5924 |
| 3505 | VRSQRTEfd = 3490, // ARMInstrNEON.td:5930 |
| 3506 | VRSQRTEfq = 3491, // ARMInstrNEON.td:5933 |
| 3507 | VRSQRTEhd = 3492, // ARMInstrNEON.td:5936 |
| 3508 | VRSQRTEhq = 3493, // ARMInstrNEON.td:5940 |
| 3509 | VRSQRTEq = 3494, // ARMInstrNEON.td:5927 |
| 3510 | VRSQRTSfd = 3495, // ARMInstrNEON.td:5946 |
| 3511 | VRSQRTSfq = 3496, // ARMInstrNEON.td:5949 |
| 3512 | VRSQRTShd = 3497, // ARMInstrNEON.td:5952 |
| 3513 | VRSQRTShq = 3498, // ARMInstrNEON.td:5956 |
| 3514 | VRSRAsv16i8 = 3499, // ARMInstrNEON.td:4147 |
| 3515 | VRSRAsv1i64 = 3500, // ARMInstrNEON.td:4142 |
| 3516 | VRSRAsv2i32 = 3501, // ARMInstrNEON.td:4138 |
| 3517 | VRSRAsv2i64 = 3502, // ARMInstrNEON.td:4159 |
| 3518 | VRSRAsv4i16 = 3503, // ARMInstrNEON.td:4134 |
| 3519 | VRSRAsv4i32 = 3504, // ARMInstrNEON.td:4155 |
| 3520 | VRSRAsv8i16 = 3505, // ARMInstrNEON.td:4151 |
| 3521 | VRSRAsv8i8 = 3506, // ARMInstrNEON.td:4130 |
| 3522 | VRSRAuv16i8 = 3507, // ARMInstrNEON.td:4147 |
| 3523 | VRSRAuv1i64 = 3508, // ARMInstrNEON.td:4142 |
| 3524 | VRSRAuv2i32 = 3509, // ARMInstrNEON.td:4138 |
| 3525 | VRSRAuv2i64 = 3510, // ARMInstrNEON.td:4159 |
| 3526 | VRSRAuv4i16 = 3511, // ARMInstrNEON.td:4134 |
| 3527 | VRSRAuv4i32 = 3512, // ARMInstrNEON.td:4155 |
| 3528 | VRSRAuv8i16 = 3513, // ARMInstrNEON.td:4151 |
| 3529 | VRSRAuv8i8 = 3514, // ARMInstrNEON.td:4130 |
| 3530 | VRSUBHNv2i32 = 3515, // ARMInstrNEON.td:3721 |
| 3531 | VRSUBHNv4i16 = 3516, // ARMInstrNEON.td:3718 |
| 3532 | VRSUBHNv8i8 = 3517, // ARMInstrNEON.td:3715 |
| 3533 | VSCCLRMD = 3518, // ARMInstrVFP.td:2914 |
| 3534 | VSCCLRMS = 3519, // ARMInstrVFP.td:2931 |
| 3535 | VSDOTD = 3520, // ARMInstrNEON.td:4857 |
| 3536 | VSDOTDI = 3521, // ARMInstrNEON.td:4865 |
| 3537 | VSDOTQ = 3522, // ARMInstrNEON.td:4859 |
| 3538 | VSDOTQI = 3523, // ARMInstrNEON.td:4865 |
| 3539 | VSELEQD = 3524, // ARMInstrVFP.td:591 |
| 3540 | VSELEQH = 3525, // ARMInstrVFP.td:578 |
| 3541 | VSELEQS = 3526, // ARMInstrVFP.td:585 |
| 3542 | VSELGED = 3527, // ARMInstrVFP.td:591 |
| 3543 | VSELGEH = 3528, // ARMInstrVFP.td:578 |
| 3544 | VSELGES = 3529, // ARMInstrVFP.td:585 |
| 3545 | VSELGTD = 3530, // ARMInstrVFP.td:591 |
| 3546 | VSELGTH = 3531, // ARMInstrVFP.td:578 |
| 3547 | VSELGTS = 3532, // ARMInstrVFP.td:585 |
| 3548 | VSELVSD = 3533, // ARMInstrVFP.td:591 |
| 3549 | VSELVSH = 3534, // ARMInstrVFP.td:578 |
| 3550 | VSELVSS = 3535, // ARMInstrVFP.td:585 |
| 3551 | VSETLNi16 = 3536, // ARMInstrNEON.td:6567 |
| 3552 | VSETLNi32 = 3537, // ARMInstrNEON.td:6575 |
| 3553 | VSETLNi8 = 3538, // ARMInstrNEON.td:6559 |
| 3554 | VSHLLi16 = 3539, // ARMInstrNEON.td:6034 |
| 3555 | VSHLLi32 = 3540, // ARMInstrNEON.td:6036 |
| 3556 | VSHLLi8 = 3541, // ARMInstrNEON.td:6032 |
| 3557 | VSHLLsv2i64 = 3542, // ARMInstrNEON.td:4253 |
| 3558 | VSHLLsv4i32 = 3543, // ARMInstrNEON.td:4249 |
| 3559 | VSHLLsv8i16 = 3544, // ARMInstrNEON.td:4245 |
| 3560 | VSHLLuv2i64 = 3545, // ARMInstrNEON.td:4253 |
| 3561 | VSHLLuv4i32 = 3546, // ARMInstrNEON.td:4249 |
| 3562 | VSHLLuv8i16 = 3547, // ARMInstrNEON.td:4245 |
| 3563 | VSHLiv16i8 = 3548, // ARMInstrNEON.td:4071 |
| 3564 | VSHLiv1i64 = 3549, // ARMInstrNEON.td:4066 |
| 3565 | VSHLiv2i32 = 3550, // ARMInstrNEON.td:4062 |
| 3566 | VSHLiv2i64 = 3551, // ARMInstrNEON.td:4083 |
| 3567 | VSHLiv4i16 = 3552, // ARMInstrNEON.td:4058 |
| 3568 | VSHLiv4i32 = 3553, // ARMInstrNEON.td:4079 |
| 3569 | VSHLiv8i16 = 3554, // ARMInstrNEON.td:4075 |
| 3570 | VSHLiv8i8 = 3555, // ARMInstrNEON.td:4054 |
| 3571 | VSHLsv16i8 = 3556, // ARMInstrNEON.td:3674 |
| 3572 | VSHLsv1i64 = 3557, // ARMInstrNEON.td:3702 |
| 3573 | VSHLsv2i32 = 3558, // ARMInstrNEON.td:3622 |
| 3574 | VSHLsv2i64 = 3559, // ARMInstrNEON.td:3705 |
| 3575 | VSHLsv4i16 = 3560, // ARMInstrNEON.td:3619 |
| 3576 | VSHLsv4i32 = 3561, // ARMInstrNEON.td:3630 |
| 3577 | VSHLsv8i16 = 3562, // ARMInstrNEON.td:3627 |
| 3578 | VSHLsv8i8 = 3563, // ARMInstrNEON.td:3671 |
| 3579 | VSHLuv16i8 = 3564, // ARMInstrNEON.td:3674 |
| 3580 | VSHLuv1i64 = 3565, // ARMInstrNEON.td:3702 |
| 3581 | VSHLuv2i32 = 3566, // ARMInstrNEON.td:3622 |
| 3582 | VSHLuv2i64 = 3567, // ARMInstrNEON.td:3705 |
| 3583 | VSHLuv4i16 = 3568, // ARMInstrNEON.td:3619 |
| 3584 | VSHLuv4i32 = 3569, // ARMInstrNEON.td:3630 |
| 3585 | VSHLuv8i16 = 3570, // ARMInstrNEON.td:3627 |
| 3586 | VSHLuv8i8 = 3571, // ARMInstrNEON.td:3671 |
| 3587 | VSHRNv2i32 = 3572, // ARMInstrNEON.td:4274 |
| 3588 | VSHRNv4i16 = 3573, // ARMInstrNEON.td:4269 |
| 3589 | VSHRNv8i8 = 3574, // ARMInstrNEON.td:4264 |
| 3590 | VSHRsv16i8 = 3575, // ARMInstrNEON.td:4108 |
| 3591 | VSHRsv1i64 = 3576, // ARMInstrNEON.td:4103 |
| 3592 | VSHRsv2i32 = 3577, // ARMInstrNEON.td:4099 |
| 3593 | VSHRsv2i64 = 3578, // ARMInstrNEON.td:4120 |
| 3594 | VSHRsv4i16 = 3579, // ARMInstrNEON.td:4095 |
| 3595 | VSHRsv4i32 = 3580, // ARMInstrNEON.td:4116 |
| 3596 | VSHRsv8i16 = 3581, // ARMInstrNEON.td:4112 |
| 3597 | VSHRsv8i8 = 3582, // ARMInstrNEON.td:4091 |
| 3598 | VSHRuv16i8 = 3583, // ARMInstrNEON.td:4108 |
| 3599 | VSHRuv1i64 = 3584, // ARMInstrNEON.td:4103 |
| 3600 | VSHRuv2i32 = 3585, // ARMInstrNEON.td:4099 |
| 3601 | VSHRuv2i64 = 3586, // ARMInstrNEON.td:4120 |
| 3602 | VSHRuv4i16 = 3587, // ARMInstrNEON.td:4095 |
| 3603 | VSHRuv4i32 = 3588, // ARMInstrNEON.td:4116 |
| 3604 | VSHRuv8i16 = 3589, // ARMInstrNEON.td:4112 |
| 3605 | VSHRuv8i8 = 3590, // ARMInstrNEON.td:4091 |
| 3606 | VSHTOD = 3591, // ARMInstrVFP.td:2052 |
| 3607 | VSHTOH = 3592, // ARMInstrVFP.td:1990 |
| 3608 | VSHTOS = 3593, // ARMInstrVFP.td:2016 |
| 3609 | VSITOD = 3594, // ARMInstrVFP.td:1521 |
| 3610 | VSITOH = 3595, // ARMInstrVFP.td:1557 |
| 3611 | VSITOS = 3596, // ARMInstrVFP.td:1538 |
| 3612 | VSLIv16i8 = 3597, // ARMInstrNEON.td:4187 |
| 3613 | VSLIv1i64 = 3598, // ARMInstrNEON.td:4182 |
| 3614 | VSLIv2i32 = 3599, // ARMInstrNEON.td:4178 |
| 3615 | VSLIv2i64 = 3600, // ARMInstrNEON.td:4199 |
| 3616 | VSLIv4i16 = 3601, // ARMInstrNEON.td:4174 |
| 3617 | VSLIv4i32 = 3602, // ARMInstrNEON.td:4195 |
| 3618 | VSLIv8i16 = 3603, // ARMInstrNEON.td:4191 |
| 3619 | VSLIv8i8 = 3604, // ARMInstrNEON.td:4170 |
| 3620 | VSLTOD = 3605, // ARMInstrVFP.td:2062 |
| 3621 | VSLTOH = 3606, // ARMInstrVFP.td:2002 |
| 3622 | VSLTOS = 3607, // ARMInstrVFP.td:2034 |
| 3623 | VSMMLA = 3608, // ARMInstrNEON.td:4961 |
| 3624 | VSQRTD = 3609, // ARMInstrVFP.td:1172 |
| 3625 | VSQRTH = 3610, // ARMInstrVFP.td:1186 |
| 3626 | VSQRTS = 3611, // ARMInstrVFP.td:1179 |
| 3627 | VSRAsv16i8 = 3612, // ARMInstrNEON.td:4147 |
| 3628 | VSRAsv1i64 = 3613, // ARMInstrNEON.td:4142 |
| 3629 | VSRAsv2i32 = 3614, // ARMInstrNEON.td:4138 |
| 3630 | VSRAsv2i64 = 3615, // ARMInstrNEON.td:4159 |
| 3631 | VSRAsv4i16 = 3616, // ARMInstrNEON.td:4134 |
| 3632 | VSRAsv4i32 = 3617, // ARMInstrNEON.td:4155 |
| 3633 | VSRAsv8i16 = 3618, // ARMInstrNEON.td:4151 |
| 3634 | VSRAsv8i8 = 3619, // ARMInstrNEON.td:4130 |
| 3635 | VSRAuv16i8 = 3620, // ARMInstrNEON.td:4147 |
| 3636 | VSRAuv1i64 = 3621, // ARMInstrNEON.td:4142 |
| 3637 | VSRAuv2i32 = 3622, // ARMInstrNEON.td:4138 |
| 3638 | VSRAuv2i64 = 3623, // ARMInstrNEON.td:4159 |
| 3639 | VSRAuv4i16 = 3624, // ARMInstrNEON.td:4134 |
| 3640 | VSRAuv4i32 = 3625, // ARMInstrNEON.td:4155 |
| 3641 | VSRAuv8i16 = 3626, // ARMInstrNEON.td:4151 |
| 3642 | VSRAuv8i8 = 3627, // ARMInstrNEON.td:4130 |
| 3643 | VSRIv16i8 = 3628, // ARMInstrNEON.td:4223 |
| 3644 | VSRIv1i64 = 3629, // ARMInstrNEON.td:4218 |
| 3645 | VSRIv2i32 = 3630, // ARMInstrNEON.td:4214 |
| 3646 | VSRIv2i64 = 3631, // ARMInstrNEON.td:4235 |
| 3647 | VSRIv4i16 = 3632, // ARMInstrNEON.td:4210 |
| 3648 | VSRIv4i32 = 3633, // ARMInstrNEON.td:4231 |
| 3649 | VSRIv8i16 = 3634, // ARMInstrNEON.td:4227 |
| 3650 | VSRIv8i8 = 3635, // ARMInstrNEON.td:4206 |
| 3651 | VST1LNd16 = 3636, // ARMInstrNEON.td:2204 |
| 3652 | VST1LNd16_UPD = 3637, // ARMInstrNEON.td:2255 |
| 3653 | VST1LNd32 = 3638, // ARMInstrNEON.td:2210 |
| 3654 | VST1LNd32_UPD = 3639, // ARMInstrNEON.td:2260 |
| 3655 | VST1LNd8 = 3640, // ARMInstrNEON.td:2200 |
| 3656 | VST1LNd8_UPD = 3641, // ARMInstrNEON.td:2251 |
| 3657 | VST1LNq16Pseudo = 3642, // ARMInstrNEON.td:2217 |
| 3658 | VST1LNq16Pseudo_UPD = 3643, // ARMInstrNEON.td:2267 |
| 3659 | VST1LNq32Pseudo = 3644, // ARMInstrNEON.td:2218 |
| 3660 | VST1LNq32Pseudo_UPD = 3645, // ARMInstrNEON.td:2268 |
| 3661 | VST1LNq8Pseudo = 3646, // ARMInstrNEON.td:2216 |
| 3662 | VST1LNq8Pseudo_UPD = 3647, // ARMInstrNEON.td:2266 |
| 3663 | VST1d16 = 3648, // ARMInstrNEON.td:1752 |
| 3664 | VST1d16Q = 3649, // ARMInstrNEON.td:1905 |
| 3665 | VST1d16QPseudo = 3650, // ARMInstrNEON.td:1917 |
| 3666 | VST1d16QPseudoWB_fixed = 3651, // ARMInstrNEON.td:1918 |
| 3667 | VST1d16QPseudoWB_register = 3652, // ARMInstrNEON.td:1919 |
| 3668 | VST1d16Qwb_fixed = 3653, // ARMInstrNEON.td:1886 |
| 3669 | VST1d16Qwb_register = 3654, // ARMInstrNEON.td:1894 |
| 3670 | VST1d16T = 3655, // ARMInstrNEON.td:1838 |
| 3671 | VST1d16TPseudo = 3656, // ARMInstrNEON.td:1850 |
| 3672 | VST1d16TPseudoWB_fixed = 3657, // ARMInstrNEON.td:1851 |
| 3673 | VST1d16TPseudoWB_register = 3658, // ARMInstrNEON.td:1852 |
| 3674 | VST1d16Twb_fixed = 3659, // ARMInstrNEON.td:1819 |
| 3675 | VST1d16Twb_register = 3660, // ARMInstrNEON.td:1827 |
| 3676 | VST1d16wb_fixed = 3661, // ARMInstrNEON.td:1763 |
| 3677 | VST1d16wb_register = 3662, // ARMInstrNEON.td:1771 |
| 3678 | VST1d32 = 3663, // ARMInstrNEON.td:1753 |
| 3679 | VST1d32Q = 3664, // ARMInstrNEON.td:1906 |
| 3680 | VST1d32QPseudo = 3665, // ARMInstrNEON.td:1920 |
| 3681 | VST1d32QPseudoWB_fixed = 3666, // ARMInstrNEON.td:1921 |
| 3682 | VST1d32QPseudoWB_register = 3667, // ARMInstrNEON.td:1922 |
| 3683 | VST1d32Qwb_fixed = 3668, // ARMInstrNEON.td:1886 |
| 3684 | VST1d32Qwb_register = 3669, // ARMInstrNEON.td:1894 |
| 3685 | VST1d32T = 3670, // ARMInstrNEON.td:1839 |
| 3686 | VST1d32TPseudo = 3671, // ARMInstrNEON.td:1853 |
| 3687 | VST1d32TPseudoWB_fixed = 3672, // ARMInstrNEON.td:1854 |
| 3688 | VST1d32TPseudoWB_register = 3673, // ARMInstrNEON.td:1855 |
| 3689 | VST1d32Twb_fixed = 3674, // ARMInstrNEON.td:1819 |
| 3690 | VST1d32Twb_register = 3675, // ARMInstrNEON.td:1827 |
| 3691 | VST1d32wb_fixed = 3676, // ARMInstrNEON.td:1763 |
| 3692 | VST1d32wb_register = 3677, // ARMInstrNEON.td:1771 |
| 3693 | VST1d64 = 3678, // ARMInstrNEON.td:1754 |
| 3694 | VST1d64Q = 3679, // ARMInstrNEON.td:1907 |
| 3695 | VST1d64QPseudo = 3680, // ARMInstrNEON.td:1923 |
| 3696 | VST1d64QPseudoWB_fixed = 3681, // ARMInstrNEON.td:1924 |
| 3697 | VST1d64QPseudoWB_register = 3682, // ARMInstrNEON.td:1925 |
| 3698 | VST1d64Qwb_fixed = 3683, // ARMInstrNEON.td:1886 |
| 3699 | VST1d64Qwb_register = 3684, // ARMInstrNEON.td:1894 |
| 3700 | VST1d64T = 3685, // ARMInstrNEON.td:1840 |
| 3701 | VST1d64TPseudo = 3686, // ARMInstrNEON.td:1856 |
| 3702 | VST1d64TPseudoWB_fixed = 3687, // ARMInstrNEON.td:1857 |
| 3703 | VST1d64TPseudoWB_register = 3688, // ARMInstrNEON.td:1858 |
| 3704 | VST1d64Twb_fixed = 3689, // ARMInstrNEON.td:1819 |
| 3705 | VST1d64Twb_register = 3690, // ARMInstrNEON.td:1827 |
| 3706 | VST1d64wb_fixed = 3691, // ARMInstrNEON.td:1763 |
| 3707 | VST1d64wb_register = 3692, // ARMInstrNEON.td:1771 |
| 3708 | VST1d8 = 3693, // ARMInstrNEON.td:1751 |
| 3709 | VST1d8Q = 3694, // ARMInstrNEON.td:1904 |
| 3710 | VST1d8QPseudo = 3695, // ARMInstrNEON.td:1914 |
| 3711 | VST1d8QPseudoWB_fixed = 3696, // ARMInstrNEON.td:1915 |
| 3712 | VST1d8QPseudoWB_register = 3697, // ARMInstrNEON.td:1916 |
| 3713 | VST1d8Qwb_fixed = 3698, // ARMInstrNEON.td:1886 |
| 3714 | VST1d8Qwb_register = 3699, // ARMInstrNEON.td:1894 |
| 3715 | VST1d8T = 3700, // ARMInstrNEON.td:1837 |
| 3716 | VST1d8TPseudo = 3701, // ARMInstrNEON.td:1847 |
| 3717 | VST1d8TPseudoWB_fixed = 3702, // ARMInstrNEON.td:1848 |
| 3718 | VST1d8TPseudoWB_register = 3703, // ARMInstrNEON.td:1849 |
| 3719 | VST1d8Twb_fixed = 3704, // ARMInstrNEON.td:1819 |
| 3720 | VST1d8Twb_register = 3705, // ARMInstrNEON.td:1827 |
| 3721 | VST1d8wb_fixed = 3706, // ARMInstrNEON.td:1763 |
| 3722 | VST1d8wb_register = 3707, // ARMInstrNEON.td:1771 |
| 3723 | VST1q16 = 3708, // ARMInstrNEON.td:1757 |
| 3724 | VST1q16HighQPseudo = 3709, // ARMInstrNEON.td:1928 |
| 3725 | VST1q16HighQPseudo_UPD = 3710, // ARMInstrNEON.td:1933 |
| 3726 | VST1q16HighTPseudo = 3711, // ARMInstrNEON.td:1861 |
| 3727 | VST1q16HighTPseudo_UPD = 3712, // ARMInstrNEON.td:1866 |
| 3728 | VST1q16LowQPseudo_UPD = 3713, // ARMInstrNEON.td:1938 |
| 3729 | VST1q16LowTPseudo_UPD = 3714, // ARMInstrNEON.td:1871 |
| 3730 | VST1q16wb_fixed = 3715, // ARMInstrNEON.td:1781 |
| 3731 | VST1q16wb_register = 3716, // ARMInstrNEON.td:1789 |
| 3732 | VST1q32 = 3717, // ARMInstrNEON.td:1758 |
| 3733 | VST1q32HighQPseudo = 3718, // ARMInstrNEON.td:1929 |
| 3734 | VST1q32HighQPseudo_UPD = 3719, // ARMInstrNEON.td:1934 |
| 3735 | VST1q32HighTPseudo = 3720, // ARMInstrNEON.td:1862 |
| 3736 | VST1q32HighTPseudo_UPD = 3721, // ARMInstrNEON.td:1867 |
| 3737 | VST1q32LowQPseudo_UPD = 3722, // ARMInstrNEON.td:1939 |
| 3738 | VST1q32LowTPseudo_UPD = 3723, // ARMInstrNEON.td:1872 |
| 3739 | VST1q32wb_fixed = 3724, // ARMInstrNEON.td:1781 |
| 3740 | VST1q32wb_register = 3725, // ARMInstrNEON.td:1789 |
| 3741 | VST1q64 = 3726, // ARMInstrNEON.td:1759 |
| 3742 | VST1q64HighQPseudo = 3727, // ARMInstrNEON.td:1930 |
| 3743 | VST1q64HighQPseudo_UPD = 3728, // ARMInstrNEON.td:1935 |
| 3744 | VST1q64HighTPseudo = 3729, // ARMInstrNEON.td:1863 |
| 3745 | VST1q64HighTPseudo_UPD = 3730, // ARMInstrNEON.td:1868 |
| 3746 | VST1q64LowQPseudo_UPD = 3731, // ARMInstrNEON.td:1940 |
| 3747 | VST1q64LowTPseudo_UPD = 3732, // ARMInstrNEON.td:1873 |
| 3748 | VST1q64wb_fixed = 3733, // ARMInstrNEON.td:1781 |
| 3749 | VST1q64wb_register = 3734, // ARMInstrNEON.td:1789 |
| 3750 | VST1q8 = 3735, // ARMInstrNEON.td:1756 |
| 3751 | VST1q8HighQPseudo = 3736, // ARMInstrNEON.td:1927 |
| 3752 | VST1q8HighQPseudo_UPD = 3737, // ARMInstrNEON.td:1932 |
| 3753 | VST1q8HighTPseudo = 3738, // ARMInstrNEON.td:1860 |
| 3754 | VST1q8HighTPseudo_UPD = 3739, // ARMInstrNEON.td:1865 |
| 3755 | VST1q8LowQPseudo_UPD = 3740, // ARMInstrNEON.td:1937 |
| 3756 | VST1q8LowTPseudo_UPD = 3741, // ARMInstrNEON.td:1870 |
| 3757 | VST1q8wb_fixed = 3742, // ARMInstrNEON.td:1781 |
| 3758 | VST1q8wb_register = 3743, // ARMInstrNEON.td:1789 |
| 3759 | VST2LNd16 = 3744, // ARMInstrNEON.td:2286 |
| 3760 | VST2LNd16Pseudo = 3745, // ARMInstrNEON.td:2294 |
| 3761 | VST2LNd16Pseudo_UPD = 3746, // ARMInstrNEON.td:2332 |
| 3762 | VST2LNd16_UPD = 3747, // ARMInstrNEON.td:2324 |
| 3763 | VST2LNd32 = 3748, // ARMInstrNEON.td:2289 |
| 3764 | VST2LNd32Pseudo = 3749, // ARMInstrNEON.td:2295 |
| 3765 | VST2LNd32Pseudo_UPD = 3750, // ARMInstrNEON.td:2333 |
| 3766 | VST2LNd32_UPD = 3751, // ARMInstrNEON.td:2327 |
| 3767 | VST2LNd8 = 3752, // ARMInstrNEON.td:2283 |
| 3768 | VST2LNd8Pseudo = 3753, // ARMInstrNEON.td:2293 |
| 3769 | VST2LNd8Pseudo_UPD = 3754, // ARMInstrNEON.td:2331 |
| 3770 | VST2LNd8_UPD = 3755, // ARMInstrNEON.td:2321 |
| 3771 | VST2LNq16 = 3756, // ARMInstrNEON.td:2298 |
| 3772 | VST2LNq16Pseudo = 3757, // ARMInstrNEON.td:2307 |
| 3773 | VST2LNq16Pseudo_UPD = 3758, // ARMInstrNEON.td:2342 |
| 3774 | VST2LNq16_UPD = 3759, // ARMInstrNEON.td:2335 |
| 3775 | VST2LNq32 = 3760, // ARMInstrNEON.td:2302 |
| 3776 | VST2LNq32Pseudo = 3761, // ARMInstrNEON.td:2308 |
| 3777 | VST2LNq32Pseudo_UPD = 3762, // ARMInstrNEON.td:2343 |
| 3778 | VST2LNq32_UPD = 3763, // ARMInstrNEON.td:2338 |
| 3779 | VST2b16 = 3764, // ARMInstrNEON.td:2029 |
| 3780 | VST2b16wb_fixed = 3765, // ARMInstrNEON.td:1973 |
| 3781 | VST2b16wb_register = 3766, // ARMInstrNEON.td:1981 |
| 3782 | VST2b32 = 3767, // ARMInstrNEON.td:2031 |
| 3783 | VST2b32wb_fixed = 3768, // ARMInstrNEON.td:1973 |
| 3784 | VST2b32wb_register = 3769, // ARMInstrNEON.td:1981 |
| 3785 | VST2b8 = 3770, // ARMInstrNEON.td:2027 |
| 3786 | VST2b8wb_fixed = 3771, // ARMInstrNEON.td:1973 |
| 3787 | VST2b8wb_register = 3772, // ARMInstrNEON.td:1981 |
| 3788 | VST2d16 = 3773, // ARMInstrNEON.td:1954 |
| 3789 | VST2d16wb_fixed = 3774, // ARMInstrNEON.td:1973 |
| 3790 | VST2d16wb_register = 3775, // ARMInstrNEON.td:1981 |
| 3791 | VST2d32 = 3776, // ARMInstrNEON.td:1956 |
| 3792 | VST2d32wb_fixed = 3777, // ARMInstrNEON.td:1973 |
| 3793 | VST2d32wb_register = 3778, // ARMInstrNEON.td:1981 |
| 3794 | VST2d8 = 3779, // ARMInstrNEON.td:1952 |
| 3795 | VST2d8wb_fixed = 3780, // ARMInstrNEON.td:1973 |
| 3796 | VST2d8wb_register = 3781, // ARMInstrNEON.td:1981 |
| 3797 | VST2q16 = 3782, // ARMInstrNEON.td:1961 |
| 3798 | VST2q16Pseudo = 3783, // ARMInstrNEON.td:1967 |
| 3799 | VST2q16PseudoWB_fixed = 3784, // ARMInstrNEON.td:2020 |
| 3800 | VST2q16PseudoWB_register = 3785, // ARMInstrNEON.td:2023 |
| 3801 | VST2q16wb_fixed = 3786, // ARMInstrNEON.td:1990 |
| 3802 | VST2q16wb_register = 3787, // ARMInstrNEON.td:1998 |
| 3803 | VST2q32 = 3788, // ARMInstrNEON.td:1963 |
| 3804 | VST2q32Pseudo = 3789, // ARMInstrNEON.td:1968 |
| 3805 | VST2q32PseudoWB_fixed = 3790, // ARMInstrNEON.td:2021 |
| 3806 | VST2q32PseudoWB_register = 3791, // ARMInstrNEON.td:2024 |
| 3807 | VST2q32wb_fixed = 3792, // ARMInstrNEON.td:1990 |
| 3808 | VST2q32wb_register = 3793, // ARMInstrNEON.td:1998 |
| 3809 | VST2q8 = 3794, // ARMInstrNEON.td:1959 |
| 3810 | VST2q8Pseudo = 3795, // ARMInstrNEON.td:1966 |
| 3811 | VST2q8PseudoWB_fixed = 3796, // ARMInstrNEON.td:2019 |
| 3812 | VST2q8PseudoWB_register = 3797, // ARMInstrNEON.td:2022 |
| 3813 | VST2q8wb_fixed = 3798, // ARMInstrNEON.td:1990 |
| 3814 | VST2q8wb_register = 3799, // ARMInstrNEON.td:1998 |
| 3815 | VST3LNd16 = 3800, // ARMInstrNEON.td:2359 |
| 3816 | VST3LNd16Pseudo = 3801, // ARMInstrNEON.td:2367 |
| 3817 | VST3LNd16Pseudo_UPD = 3802, // ARMInstrNEON.td:2403 |
| 3818 | VST3LNd16_UPD = 3803, // ARMInstrNEON.td:2395 |
| 3819 | VST3LNd32 = 3804, // ARMInstrNEON.td:2362 |
| 3820 | VST3LNd32Pseudo = 3805, // ARMInstrNEON.td:2368 |
| 3821 | VST3LNd32Pseudo_UPD = 3806, // ARMInstrNEON.td:2404 |
| 3822 | VST3LNd32_UPD = 3807, // ARMInstrNEON.td:2398 |
| 3823 | VST3LNd8 = 3808, // ARMInstrNEON.td:2356 |
| 3824 | VST3LNd8Pseudo = 3809, // ARMInstrNEON.td:2366 |
| 3825 | VST3LNd8Pseudo_UPD = 3810, // ARMInstrNEON.td:2402 |
| 3826 | VST3LNd8_UPD = 3811, // ARMInstrNEON.td:2392 |
| 3827 | VST3LNq16 = 3812, // ARMInstrNEON.td:2371 |
| 3828 | VST3LNq16Pseudo = 3813, // ARMInstrNEON.td:2378 |
| 3829 | VST3LNq16Pseudo_UPD = 3814, // ARMInstrNEON.td:2413 |
| 3830 | VST3LNq16_UPD = 3815, // ARMInstrNEON.td:2406 |
| 3831 | VST3LNq32 = 3816, // ARMInstrNEON.td:2374 |
| 3832 | VST3LNq32Pseudo = 3817, // ARMInstrNEON.td:2379 |
| 3833 | VST3LNq32Pseudo_UPD = 3818, // ARMInstrNEON.td:2414 |
| 3834 | VST3LNq32_UPD = 3819, // ARMInstrNEON.td:2409 |
| 3835 | VST3d16 = 3820, // ARMInstrNEON.td:2051 |
| 3836 | VST3d16Pseudo = 3821, // ARMInstrNEON.td:2055 |
| 3837 | VST3d16Pseudo_UPD = 3822, // ARMInstrNEON.td:2074 |
| 3838 | VST3d16_UPD = 3823, // ARMInstrNEON.td:2070 |
| 3839 | VST3d32 = 3824, // ARMInstrNEON.td:2052 |
| 3840 | VST3d32Pseudo = 3825, // ARMInstrNEON.td:2056 |
| 3841 | VST3d32Pseudo_UPD = 3826, // ARMInstrNEON.td:2075 |
| 3842 | VST3d32_UPD = 3827, // ARMInstrNEON.td:2071 |
| 3843 | VST3d8 = 3828, // ARMInstrNEON.td:2050 |
| 3844 | VST3d8Pseudo = 3829, // ARMInstrNEON.td:2054 |
| 3845 | VST3d8Pseudo_UPD = 3830, // ARMInstrNEON.td:2073 |
| 3846 | VST3d8_UPD = 3831, // ARMInstrNEON.td:2069 |
| 3847 | VST3q16 = 3832, // ARMInstrNEON.td:2079 |
| 3848 | VST3q16Pseudo_UPD = 3833, // ARMInstrNEON.td:2086 |
| 3849 | VST3q16_UPD = 3834, // ARMInstrNEON.td:2082 |
| 3850 | VST3q16oddPseudo = 3835, // ARMInstrNEON.td:2091 |
| 3851 | VST3q16oddPseudo_UPD = 3836, // ARMInstrNEON.td:2095 |
| 3852 | VST3q32 = 3837, // ARMInstrNEON.td:2080 |
| 3853 | VST3q32Pseudo_UPD = 3838, // ARMInstrNEON.td:2087 |
| 3854 | VST3q32_UPD = 3839, // ARMInstrNEON.td:2083 |
| 3855 | VST3q32oddPseudo = 3840, // ARMInstrNEON.td:2092 |
| 3856 | VST3q32oddPseudo_UPD = 3841, // ARMInstrNEON.td:2096 |
| 3857 | VST3q8 = 3842, // ARMInstrNEON.td:2078 |
| 3858 | VST3q8Pseudo_UPD = 3843, // ARMInstrNEON.td:2085 |
| 3859 | VST3q8_UPD = 3844, // ARMInstrNEON.td:2081 |
| 3860 | VST3q8oddPseudo = 3845, // ARMInstrNEON.td:2090 |
| 3861 | VST3q8oddPseudo_UPD = 3846, // ARMInstrNEON.td:2094 |
| 3862 | VST4LNd16 = 3847, // ARMInstrNEON.td:2431 |
| 3863 | VST4LNd16Pseudo = 3848, // ARMInstrNEON.td:2440 |
| 3864 | VST4LNd16Pseudo_UPD = 3849, // ARMInstrNEON.td:2479 |
| 3865 | VST4LNd16_UPD = 3850, // ARMInstrNEON.td:2470 |
| 3866 | VST4LNd32 = 3851, // ARMInstrNEON.td:2434 |
| 3867 | VST4LNd32Pseudo = 3852, // ARMInstrNEON.td:2441 |
| 3868 | VST4LNd32Pseudo_UPD = 3853, // ARMInstrNEON.td:2480 |
| 3869 | VST4LNd32_UPD = 3854, // ARMInstrNEON.td:2473 |
| 3870 | VST4LNd8 = 3855, // ARMInstrNEON.td:2428 |
| 3871 | VST4LNd8Pseudo = 3856, // ARMInstrNEON.td:2439 |
| 3872 | VST4LNd8Pseudo_UPD = 3857, // ARMInstrNEON.td:2478 |
| 3873 | VST4LNd8_UPD = 3858, // ARMInstrNEON.td:2467 |
| 3874 | VST4LNq16 = 3859, // ARMInstrNEON.td:2444 |
| 3875 | VST4LNq16Pseudo = 3860, // ARMInstrNEON.td:2452 |
| 3876 | VST4LNq16Pseudo_UPD = 3861, // ARMInstrNEON.td:2490 |
| 3877 | VST4LNq16_UPD = 3862, // ARMInstrNEON.td:2482 |
| 3878 | VST4LNq32 = 3863, // ARMInstrNEON.td:2447 |
| 3879 | VST4LNq32Pseudo = 3864, // ARMInstrNEON.td:2453 |
| 3880 | VST4LNq32Pseudo_UPD = 3865, // ARMInstrNEON.td:2491 |
| 3881 | VST4LNq32_UPD = 3866, // ARMInstrNEON.td:2485 |
| 3882 | VST4d16 = 3867, // ARMInstrNEON.td:2110 |
| 3883 | VST4d16Pseudo = 3868, // ARMInstrNEON.td:2114 |
| 3884 | VST4d16Pseudo_UPD = 3869, // ARMInstrNEON.td:2133 |
| 3885 | VST4d16_UPD = 3870, // ARMInstrNEON.td:2129 |
| 3886 | VST4d32 = 3871, // ARMInstrNEON.td:2111 |
| 3887 | VST4d32Pseudo = 3872, // ARMInstrNEON.td:2115 |
| 3888 | VST4d32Pseudo_UPD = 3873, // ARMInstrNEON.td:2134 |
| 3889 | VST4d32_UPD = 3874, // ARMInstrNEON.td:2130 |
| 3890 | VST4d8 = 3875, // ARMInstrNEON.td:2109 |
| 3891 | VST4d8Pseudo = 3876, // ARMInstrNEON.td:2113 |
| 3892 | VST4d8Pseudo_UPD = 3877, // ARMInstrNEON.td:2132 |
| 3893 | VST4d8_UPD = 3878, // ARMInstrNEON.td:2128 |
| 3894 | VST4q16 = 3879, // ARMInstrNEON.td:2138 |
| 3895 | VST4q16Pseudo_UPD = 3880, // ARMInstrNEON.td:2145 |
| 3896 | VST4q16_UPD = 3881, // ARMInstrNEON.td:2141 |
| 3897 | VST4q16oddPseudo = 3882, // ARMInstrNEON.td:2150 |
| 3898 | VST4q16oddPseudo_UPD = 3883, // ARMInstrNEON.td:2154 |
| 3899 | VST4q32 = 3884, // ARMInstrNEON.td:2139 |
| 3900 | VST4q32Pseudo_UPD = 3885, // ARMInstrNEON.td:2146 |
| 3901 | VST4q32_UPD = 3886, // ARMInstrNEON.td:2142 |
| 3902 | VST4q32oddPseudo = 3887, // ARMInstrNEON.td:2151 |
| 3903 | VST4q32oddPseudo_UPD = 3888, // ARMInstrNEON.td:2155 |
| 3904 | VST4q8 = 3889, // ARMInstrNEON.td:2137 |
| 3905 | VST4q8Pseudo_UPD = 3890, // ARMInstrNEON.td:2144 |
| 3906 | VST4q8_UPD = 3891, // ARMInstrNEON.td:2140 |
| 3907 | VST4q8oddPseudo = 3892, // ARMInstrNEON.td:2149 |
| 3908 | VST4q8oddPseudo_UPD = 3893, // ARMInstrNEON.td:2153 |
| 3909 | VSTMDDB_UPD = 3894, // ARMInstrVFP.td:276 |
| 3910 | VSTMDIA = 3895, // ARMInstrVFP.td:259 |
| 3911 | VSTMDIA_UPD = 3896, // ARMInstrVFP.td:267 |
| 3912 | VSTMQIA = 3897, // ARMInstrNEON.td:570 |
| 3913 | VSTMSDB_UPD = 3898, // ARMInstrVFP.td:312 |
| 3914 | VSTMSIA = 3899, // ARMInstrVFP.td:287 |
| 3915 | VSTMSIA_UPD = 3900, // ARMInstrVFP.td:299 |
| 3916 | VSTRD = 3901, // ARMInstrVFP.td:218 |
| 3917 | VSTRH = 3902, // ARMInstrVFP.td:233 |
| 3918 | VSTRS = 3903, // ARMInstrVFP.td:223 |
| 3919 | VSTR_FPCXTNS_off = 3904, // ARMInstrVFP.td:2975 |
| 3920 | VSTR_FPCXTNS_post = 3905, // ARMInstrVFP.td:2990 |
| 3921 | VSTR_FPCXTNS_pre = 3906, // ARMInstrVFP.td:2982 |
| 3922 | VSTR_FPCXTS_off = 3907, // ARMInstrVFP.td:2975 |
| 3923 | VSTR_FPCXTS_post = 3908, // ARMInstrVFP.td:2990 |
| 3924 | VSTR_FPCXTS_pre = 3909, // ARMInstrVFP.td:2982 |
| 3925 | VSTR_FPSCR_NZCVQC_off = 3910, // ARMInstrVFP.td:2975 |
| 3926 | VSTR_FPSCR_NZCVQC_post = 3911, // ARMInstrVFP.td:2990 |
| 3927 | VSTR_FPSCR_NZCVQC_pre = 3912, // ARMInstrVFP.td:2982 |
| 3928 | VSTR_FPSCR_off = 3913, // ARMInstrVFP.td:2975 |
| 3929 | VSTR_FPSCR_post = 3914, // ARMInstrVFP.td:2990 |
| 3930 | VSTR_FPSCR_pre = 3915, // ARMInstrVFP.td:2982 |
| 3931 | VSTR_P0_off = 3916, // ARMInstrVFP.td:2975 |
| 3932 | VSTR_P0_post = 3917, // ARMInstrVFP.td:2990 |
| 3933 | VSTR_P0_pre = 3918, // ARMInstrVFP.td:2982 |
| 3934 | VSTR_VPR_off = 3919, // ARMInstrVFP.td:2975 |
| 3935 | VSTR_VPR_post = 3920, // ARMInstrVFP.td:2990 |
| 3936 | VSTR_VPR_pre = 3921, // ARMInstrVFP.td:2982 |
| 3937 | VSUBD = 3922, // ARMInstrVFP.td:480 |
| 3938 | VSUBH = 3923, // ARMInstrVFP.td:498 |
| 3939 | VSUBHNv2i32 = 3924, // ARMInstrNEON.td:3721 |
| 3940 | VSUBHNv4i16 = 3925, // ARMInstrNEON.td:3718 |
| 3941 | VSUBHNv8i8 = 3926, // ARMInstrNEON.td:3715 |
| 3942 | VSUBLsv2i64 = 3927, // ARMInstrNEON.td:3763 |
| 3943 | VSUBLsv4i32 = 3928, // ARMInstrNEON.td:3760 |
| 3944 | VSUBLsv8i16 = 3929, // ARMInstrNEON.td:3757 |
| 3945 | VSUBLuv2i64 = 3930, // ARMInstrNEON.td:3763 |
| 3946 | VSUBLuv4i32 = 3931, // ARMInstrNEON.td:3760 |
| 3947 | VSUBLuv8i16 = 3932, // ARMInstrNEON.td:3757 |
| 3948 | VSUBS = 3933, // ARMInstrVFP.td:487 |
| 3949 | VSUBWsv2i64 = 3934, // ARMInstrNEON.td:3831 |
| 3950 | VSUBWsv4i32 = 3935, // ARMInstrNEON.td:3828 |
| 3951 | VSUBWsv8i16 = 3936, // ARMInstrNEON.td:3825 |
| 3952 | VSUBWuv2i64 = 3937, // ARMInstrNEON.td:3831 |
| 3953 | VSUBWuv4i32 = 3938, // ARMInstrNEON.td:3828 |
| 3954 | VSUBWuv8i16 = 3939, // ARMInstrNEON.td:3825 |
| 3955 | VSUBfd = 3940, // ARMInstrNEON.td:5127 |
| 3956 | VSUBfq = 3941, // ARMInstrNEON.td:5129 |
| 3957 | VSUBhd = 3942, // ARMInstrNEON.td:5131 |
| 3958 | VSUBhq = 3943, // ARMInstrNEON.td:5134 |
| 3959 | VSUBv16i8 = 3944, // ARMInstrNEON.td:3554 |
| 3960 | VSUBv1i64 = 3945, // ARMInstrNEON.td:3580 |
| 3961 | VSUBv2i32 = 3946, // ARMInstrNEON.td:3549 |
| 3962 | VSUBv2i64 = 3947, // ARMInstrNEON.td:3583 |
| 3963 | VSUBv4i16 = 3948, // ARMInstrNEON.td:3546 |
| 3964 | VSUBv4i32 = 3949, // ARMInstrNEON.td:3560 |
| 3965 | VSUBv8i16 = 3950, // ARMInstrNEON.td:3557 |
| 3966 | VSUBv8i8 = 3951, // ARMInstrNEON.td:3543 |
| 3967 | VSUDOTDI = 3952, // ARMInstrNEON.td:4930 |
| 3968 | VSUDOTQI = 3953, // ARMInstrNEON.td:4930 |
| 3969 | VSWPd = 3954, // ARMInstrNEON.td:6248 |
| 3970 | VSWPq = 3955, // ARMInstrNEON.td:6252 |
| 3971 | VTBL1 = 3956, // ARMInstrNEON.td:7219 |
| 3972 | VTBL2 = 3957, // ARMInstrNEON.td:7226 |
| 3973 | VTBL3 = 3958, // ARMInstrNEON.td:7230 |
| 3974 | VTBL3Pseudo = 3959, // ARMInstrNEON.td:7241 |
| 3975 | VTBL4 = 3960, // ARMInstrNEON.td:7234 |
| 3976 | VTBL4Pseudo = 3961, // ARMInstrNEON.td:7243 |
| 3977 | VTBX1 = 3962, // ARMInstrNEON.td:7247 |
| 3978 | VTBX2 = 3963, // ARMInstrNEON.td:7254 |
| 3979 | VTBX3 = 3964, // ARMInstrNEON.td:7258 |
| 3980 | VTBX3Pseudo = 3965, // ARMInstrNEON.td:7271 |
| 3981 | VTBX4 = 3966, // ARMInstrNEON.td:7264 |
| 3982 | VTBX4Pseudo = 3967, // ARMInstrNEON.td:7274 |
| 3983 | VTOSHD = 3968, // ARMInstrVFP.td:1966 |
| 3984 | VTOSHH = 3969, // ARMInstrVFP.td:1904 |
| 3985 | VTOSHS = 3970, // ARMInstrVFP.td:1930 |
| 3986 | VTOSIRD = 3971, // ARMInstrVFP.td:1804 |
| 3987 | VTOSIRH = 3972, // ARMInstrVFP.td:1820 |
| 3988 | VTOSIRS = 3973, // ARMInstrVFP.td:1812 |
| 3989 | VTOSIZD = 3974, // ARMInstrVFP.td:1681 |
| 3990 | VTOSIZH = 3975, // ARMInstrVFP.td:1727 |
| 3991 | VTOSIZS = 3976, // ARMInstrVFP.td:1702 |
| 3992 | VTOSLD = 3977, // ARMInstrVFP.td:1976 |
| 3993 | VTOSLH = 3978, // ARMInstrVFP.td:1916 |
| 3994 | VTOSLS = 3979, // ARMInstrVFP.td:1948 |
| 3995 | VTOUHD = 3980, // ARMInstrVFP.td:1971 |
| 3996 | VTOUHH = 3981, // ARMInstrVFP.td:1910 |
| 3997 | VTOUHS = 3982, // ARMInstrVFP.td:1939 |
| 3998 | VTOUIRD = 3983, // ARMInstrVFP.td:1829 |
| 3999 | VTOUIRH = 3984, // ARMInstrVFP.td:1845 |
| 4000 | VTOUIRS = 3985, // ARMInstrVFP.td:1837 |
| 4001 | VTOUIZD = 3986, // ARMInstrVFP.td:1742 |
| 4002 | VTOUIZH = 3987, // ARMInstrVFP.td:1788 |
| 4003 | VTOUIZS = 3988, // ARMInstrVFP.td:1763 |
| 4004 | VTOULD = 3989, // ARMInstrVFP.td:1981 |
| 4005 | VTOULH = 3990, // ARMInstrVFP.td:1922 |
| 4006 | VTOULS = 3991, // ARMInstrVFP.td:1957 |
| 4007 | VTRNd16 = 3992, // ARMInstrNEON.td:7184 |
| 4008 | VTRNd32 = 3993, // ARMInstrNEON.td:7185 |
| 4009 | VTRNd8 = 3994, // ARMInstrNEON.td:7183 |
| 4010 | VTRNq16 = 3995, // ARMInstrNEON.td:7188 |
| 4011 | VTRNq32 = 3996, // ARMInstrNEON.td:7189 |
| 4012 | VTRNq8 = 3997, // ARMInstrNEON.td:7187 |
| 4013 | VTSTv16i8 = 3998, // ARMInstrNEON.td:3554 |
| 4014 | VTSTv2i32 = 3999, // ARMInstrNEON.td:3549 |
| 4015 | VTSTv4i16 = 4000, // ARMInstrNEON.td:3546 |
| 4016 | VTSTv4i32 = 4001, // ARMInstrNEON.td:3560 |
| 4017 | VTSTv8i16 = 4002, // ARMInstrNEON.td:3557 |
| 4018 | VTSTv8i8 = 4003, // ARMInstrNEON.td:3543 |
| 4019 | VUDOTD = 4004, // ARMInstrNEON.td:4856 |
| 4020 | VUDOTDI = 4005, // ARMInstrNEON.td:4865 |
| 4021 | VUDOTQ = 4006, // ARMInstrNEON.td:4858 |
| 4022 | VUDOTQI = 4007, // ARMInstrNEON.td:4865 |
| 4023 | VUHTOD = 4008, // ARMInstrVFP.td:2057 |
| 4024 | VUHTOH = 4009, // ARMInstrVFP.td:1996 |
| 4025 | VUHTOS = 4010, // ARMInstrVFP.td:2025 |
| 4026 | VUITOD = 4011, // ARMInstrVFP.td:1570 |
| 4027 | VUITOH = 4012, // ARMInstrVFP.td:1606 |
| 4028 | VUITOS = 4013, // ARMInstrVFP.td:1587 |
| 4029 | VULTOD = 4014, // ARMInstrVFP.td:2067 |
| 4030 | VULTOH = 4015, // ARMInstrVFP.td:2008 |
| 4031 | VULTOS = 4016, // ARMInstrVFP.td:2043 |
| 4032 | VUMMLA = 4017, // ARMInstrNEON.td:4962 |
| 4033 | VUSDOTD = 4018, // ARMInstrNEON.td:4964 |
| 4034 | VUSDOTDI = 4019, // ARMInstrNEON.td:4930 |
| 4035 | VUSDOTQ = 4020, // ARMInstrNEON.td:4965 |
| 4036 | VUSDOTQI = 4021, // ARMInstrNEON.td:4930 |
| 4037 | VUSMMLA = 4022, // ARMInstrNEON.td:4963 |
| 4038 | VUZPd16 = 4023, // ARMInstrNEON.td:7194 |
| 4039 | VUZPd8 = 4024, // ARMInstrNEON.td:7193 |
| 4040 | VUZPq16 = 4025, // ARMInstrNEON.td:7200 |
| 4041 | VUZPq32 = 4026, // ARMInstrNEON.td:7201 |
| 4042 | VUZPq8 = 4027, // ARMInstrNEON.td:7199 |
| 4043 | VZIPd16 = 4028, // ARMInstrNEON.td:7206 |
| 4044 | VZIPd8 = 4029, // ARMInstrNEON.td:7205 |
| 4045 | VZIPq16 = 4030, // ARMInstrNEON.td:7212 |
| 4046 | VZIPq32 = 4031, // ARMInstrNEON.td:7213 |
| 4047 | VZIPq8 = 4032, // ARMInstrNEON.td:7211 |
| 4048 | sysLDMDA = 4033, // ARMInstrInfo.td:3660 |
| 4049 | sysLDMDA_UPD = 4034, // ARMInstrInfo.td:3669 |
| 4050 | sysLDMDB = 4035, // ARMInstrInfo.td:3680 |
| 4051 | sysLDMDB_UPD = 4036, // ARMInstrInfo.td:3689 |
| 4052 | sysLDMIA = 4037, // ARMInstrInfo.td:3640 |
| 4053 | sysLDMIA_UPD = 4038, // ARMInstrInfo.td:3649 |
| 4054 | sysLDMIB = 4039, // ARMInstrInfo.td:3700 |
| 4055 | sysLDMIB_UPD = 4040, // ARMInstrInfo.td:3709 |
| 4056 | sysSTMDA = 4041, // ARMInstrInfo.td:3660 |
| 4057 | sysSTMDA_UPD = 4042, // ARMInstrInfo.td:3669 |
| 4058 | sysSTMDB = 4043, // ARMInstrInfo.td:3680 |
| 4059 | sysSTMDB_UPD = 4044, // ARMInstrInfo.td:3689 |
| 4060 | sysSTMIA = 4045, // ARMInstrInfo.td:3640 |
| 4061 | sysSTMIA_UPD = 4046, // ARMInstrInfo.td:3649 |
| 4062 | sysSTMIB = 4047, // ARMInstrInfo.td:3700 |
| 4063 | sysSTMIB_UPD = 4048, // ARMInstrInfo.td:3709 |
| 4064 | t2ADCri = 4049, // ARMInstrThumb2.td:1033 |
| 4065 | t2ADCrr = 4050, // ARMInstrThumb2.td:1043 |
| 4066 | t2ADCrs = 4051, // ARMInstrThumb2.td:1056 |
| 4067 | t2ADDri = 4052, // ARMInstrThumb2.td:946 |
| 4068 | t2ADDri12 = 4053, // ARMInstrThumb2.td:959 |
| 4069 | t2ADDrr = 4054, // ARMInstrThumb2.td:1000 |
| 4070 | t2ADDrs = 4055, // ARMInstrThumb2.td:1014 |
| 4071 | t2ADDspImm = 4056, // ARMInstrThumb2.td:929 |
| 4072 | t2ADDspImm12 = 4057, // ARMInstrThumb2.td:978 |
| 4073 | t2ADR = 4058, // ARMInstrThumb2.td:1425 |
| 4074 | t2ANDri = 4059, // ARMInstrThumb2.td:733 |
| 4075 | t2ANDrr = 4060, // ARMInstrThumb2.td:744 |
| 4076 | t2ANDrs = 4061, // ARMInstrThumb2.td:768 |
| 4077 | t2ASRri = 4062, // ARMInstrThumb2.td:1091 |
| 4078 | t2ASRrr = 4063, // ARMInstrThumb2.td:1103 |
| 4079 | t2ASRs1 = 4064, // ARMInstrThumb2.td:2840 |
| 4080 | t2AUT = 4065, // ARMInstrThumb2.td:5935 |
| 4081 | t2AUTG = 4066, // ARMInstrThumb2.td:5892 |
| 4082 | t2B = 4067, // ARMInstrThumb2.td:3984 |
| 4083 | t2BFC = 4068, // ARMInstrThumb2.td:2893 |
| 4084 | t2BFI = 4069, // ARMInstrThumb2.td:2946 |
| 4085 | t2BFLi = 4070, // ARMInstrThumb2.td:5584 |
| 4086 | t2BFLr = 4071, // ARMInstrThumb2.td:5597 |
| 4087 | t2BFi = 4072, // ARMInstrThumb2.td:5540 |
| 4088 | t2BFic = 4073, // ARMInstrThumb2.td:5554 |
| 4089 | t2BFr = 4074, // ARMInstrThumb2.td:5572 |
| 4090 | t2BICri = 4075, // ARMInstrThumb2.td:733 |
| 4091 | t2BICrr = 4076, // ARMInstrThumb2.td:744 |
| 4092 | t2BICrs = 4077, // ARMInstrThumb2.td:768 |
| 4093 | t2BTI = 4078, // ARMInstrThumb2.td:5934 |
| 4094 | t2BXAUT = 4079, // ARMInstrThumb2.td:5896 |
| 4095 | t2BXJ = 4080, // ARMInstrThumb2.td:4109 |
| 4096 | t2Bcc = 4081, // ARMInstrThumb2.td:4053 |
| 4097 | t2CDP = 4082, // ARMInstrThumb2.td:4773 |
| 4098 | t2CDP2 = 4083, // ARMInstrThumb2.td:4799 |
| 4099 | t2CLREX = 4084, // ARMInstrThumb2.td:3894 |
| 4100 | t2CLRM = 4085, // ARMInstrThumb2.td:5510 |
| 4101 | t2CLZ = 4086, // ARMInstrThumb2.td:3364 |
| 4102 | t2CMNri = 4087, // ARMInstrThumb2.td:3500 |
| 4103 | t2CMNrr = 4088, // ARMInstrThumb2.td:3513 |
| 4104 | t2CMNrs = 4089, // ARMInstrThumb2.td:3528 |
| 4105 | t2CMPri = 4090, // ARMInstrThumb2.td:1148 |
| 4106 | t2CMPrr = 4091, // ARMInstrThumb2.td:1161 |
| 4107 | t2CMPrs = 4092, // ARMInstrThumb2.td:1176 |
| 4108 | t2CPS1p = 4093, // ARMInstrThumb2.td:4176 |
| 4109 | t2CPS2p = 4094, // ARMInstrThumb2.td:4173 |
| 4110 | t2CPS3p = 4095, // ARMInstrThumb2.td:4170 |
| 4111 | t2CRC32B = 4096, // ARMInstrThumb2.td:3478 |
| 4112 | t2CRC32CB = 4097, // ARMInstrThumb2.td:3479 |
| 4113 | t2CRC32CH = 4098, // ARMInstrThumb2.td:3481 |
| 4114 | t2CRC32CW = 4099, // ARMInstrThumb2.td:3483 |
| 4115 | t2CRC32H = 4100, // ARMInstrThumb2.td:3480 |
| 4116 | t2CRC32W = 4101, // ARMInstrThumb2.td:3482 |
| 4117 | t2CSEL = 4102, // ARMInstrThumb2.td:5786 |
| 4118 | t2CSINC = 4103, // ARMInstrThumb2.td:5787 |
| 4119 | t2CSINV = 4104, // ARMInstrThumb2.td:5788 |
| 4120 | t2CSNEG = 4105, // ARMInstrThumb2.td:5789 |
| 4121 | t2DBG = 4106, // ARMInstrThumb2.td:4220 |
| 4122 | t2DCPS1 = 4107, // ARMInstrThumb2.td:4254 |
| 4123 | t2DCPS2 = 4108, // ARMInstrThumb2.td:4255 |
| 4124 | t2DCPS3 = 4109, // ARMInstrThumb2.td:4256 |
| 4125 | t2DLS = 4110, // ARMInstrThumb2.td:5653 |
| 4126 | t2DMB = 4111, // ARMInstrThumb2.td:3659 |
| 4127 | t2DSB = 4112, // ARMInstrThumb2.td:3667 |
| 4128 | t2EORri = 4113, // ARMInstrThumb2.td:733 |
| 4129 | t2EORrr = 4114, // ARMInstrThumb2.td:744 |
| 4130 | t2EORrs = 4115, // ARMInstrThumb2.td:768 |
| 4131 | t2HINT = 4116, // ARMInstrThumb2.td:4184 |
| 4132 | t2HVC = 4117, // ARMInstrThumb2.td:4342 |
| 4133 | t2ISB = 4118, // ARMInstrThumb2.td:3675 |
| 4134 | t2IT = 4119, // ARMInstrThumb2.td:4091 |
| 4135 | t2Int_eh_sjlj_setjmp = 4120, // ARMInstrThumb2.td:3950 |
| 4136 | t2Int_eh_sjlj_setjmp_nofp = 4121, // ARMInstrThumb2.td:3961 |
| 4137 | t2LDA = 4122, // ARMInstrThumb2.td:1693 |
| 4138 | t2LDAB = 4123, // ARMInstrThumb2.td:1696 |
| 4139 | t2LDAEX = 4124, // ARMInstrThumb2.td:3775 |
| 4140 | t2LDAEXB = 4125, // ARMInstrThumb2.td:3765 |
| 4141 | t2LDAEXD = 4126, // ARMInstrThumb2.td:3790 |
| 4142 | t2LDAEXH = 4127, // ARMInstrThumb2.td:3770 |
| 4143 | t2LDAH = 4128, // ARMInstrThumb2.td:1699 |
| 4144 | t2LDC2L_OFFSET = 4129, // ARMInstrThumb2.td:4434 |
| 4145 | t2LDC2L_OPTION = 4130, // ARMInstrThumb2.td:4487 |
| 4146 | t2LDC2L_POST = 4131, // ARMInstrThumb2.td:4468 |
| 4147 | t2LDC2L_PRE = 4132, // ARMInstrThumb2.td:4451 |
| 4148 | t2LDC2_OFFSET = 4133, // ARMInstrThumb2.td:4434 |
| 4149 | t2LDC2_OPTION = 4134, // ARMInstrThumb2.td:4487 |
| 4150 | t2LDC2_POST = 4135, // ARMInstrThumb2.td:4468 |
| 4151 | t2LDC2_PRE = 4136, // ARMInstrThumb2.td:4451 |
| 4152 | t2LDCL_OFFSET = 4137, // ARMInstrThumb2.td:4434 |
| 4153 | t2LDCL_OPTION = 4138, // ARMInstrThumb2.td:4487 |
| 4154 | t2LDCL_POST = 4139, // ARMInstrThumb2.td:4468 |
| 4155 | t2LDCL_PRE = 4140, // ARMInstrThumb2.td:4451 |
| 4156 | t2LDC_OFFSET = 4141, // ARMInstrThumb2.td:4434 |
| 4157 | t2LDC_OPTION = 4142, // ARMInstrThumb2.td:4487 |
| 4158 | t2LDC_POST = 4143, // ARMInstrThumb2.td:4468 |
| 4159 | t2LDC_PRE = 4144, // ARMInstrThumb2.td:4451 |
| 4160 | t2LDMDB = 4145, // ARMInstrThumb2.td:2096 |
| 4161 | t2LDMDB_UPD = 4146, // ARMInstrThumb2.td:2112 |
| 4162 | t2LDMIA = 4147, // ARMInstrThumb2.td:2064 |
| 4163 | t2LDMIA_UPD = 4148, // ARMInstrThumb2.td:2080 |
| 4164 | t2LDRBT = 4149, // ARMInstrThumb2.td:1669 |
| 4165 | t2LDRB_POST = 4150, // ARMInstrThumb2.td:1555 |
| 4166 | t2LDRB_PRE = 4151, // ARMInstrThumb2.td:1549 |
| 4167 | t2LDRBi12 = 4152, // ARMInstrThumb2.td:1202 |
| 4168 | t2LDRBi8 = 4153, // ARMInstrThumb2.td:1219 |
| 4169 | t2LDRBpci = 4154, // ARMInstrThumb2.td:1267 |
| 4170 | t2LDRBs = 4155, // ARMInstrThumb2.td:1242 |
| 4171 | t2LDRD_POST = 4156, // ARMInstrThumb2.td:1873 |
| 4172 | t2LDRD_PRE = 4157, // ARMInstrThumb2.td:1865 |
| 4173 | t2LDRDi8 = 4158, // ARMInstrThumb2.td:1482 |
| 4174 | t2LDREX = 4159, // ARMInstrThumb2.td:3741 |
| 4175 | t2LDREXB = 4160, // ARMInstrThumb2.td:3731 |
| 4176 | t2LDREXD = 4161, // ARMInstrThumb2.td:3756 |
| 4177 | t2LDREXH = 4162, // ARMInstrThumb2.td:3736 |
| 4178 | t2LDRHT = 4163, // ARMInstrThumb2.td:1670 |
| 4179 | t2LDRH_POST = 4164, // ARMInstrThumb2.td:1567 |
| 4180 | t2LDRH_PRE = 4165, // ARMInstrThumb2.td:1561 |
| 4181 | t2LDRHi12 = 4166, // ARMInstrThumb2.td:1202 |
| 4182 | t2LDRHi8 = 4167, // ARMInstrThumb2.td:1219 |
| 4183 | t2LDRHpci = 4168, // ARMInstrThumb2.td:1267 |
| 4184 | t2LDRHs = 4169, // ARMInstrThumb2.td:1242 |
| 4185 | t2LDRSBT = 4170, // ARMInstrThumb2.td:1671 |
| 4186 | t2LDRSB_POST = 4171, // ARMInstrThumb2.td:1579 |
| 4187 | t2LDRSB_PRE = 4172, // ARMInstrThumb2.td:1573 |
| 4188 | t2LDRSBi12 = 4173, // ARMInstrThumb2.td:1202 |
| 4189 | t2LDRSBi8 = 4174, // ARMInstrThumb2.td:1219 |
| 4190 | t2LDRSBpci = 4175, // ARMInstrThumb2.td:1267 |
| 4191 | t2LDRSBs = 4176, // ARMInstrThumb2.td:1242 |
| 4192 | t2LDRSHT = 4177, // ARMInstrThumb2.td:1672 |
| 4193 | t2LDRSH_POST = 4178, // ARMInstrThumb2.td:1591 |
| 4194 | t2LDRSH_PRE = 4179, // ARMInstrThumb2.td:1585 |
| 4195 | t2LDRSHi12 = 4180, // ARMInstrThumb2.td:1202 |
| 4196 | t2LDRSHi8 = 4181, // ARMInstrThumb2.td:1219 |
| 4197 | t2LDRSHpci = 4182, // ARMInstrThumb2.td:1267 |
| 4198 | t2LDRSHs = 4183, // ARMInstrThumb2.td:1242 |
| 4199 | t2LDRT = 4184, // ARMInstrThumb2.td:1668 |
| 4200 | t2LDR_POST = 4185, // ARMInstrThumb2.td:1543 |
| 4201 | t2LDR_PRE = 4186, // ARMInstrThumb2.td:1537 |
| 4202 | t2LDRi12 = 4187, // ARMInstrThumb2.td:1202 |
| 4203 | t2LDRi8 = 4188, // ARMInstrThumb2.td:1219 |
| 4204 | t2LDRpci = 4189, // ARMInstrThumb2.td:1267 |
| 4205 | t2LDRs = 4190, // ARMInstrThumb2.td:1242 |
| 4206 | t2LE = 4191, // ARMInstrThumb2.td:5675 |
| 4207 | t2LEUpdate = 4192, // ARMInstrThumb2.td:5662 |
| 4208 | t2LSLri = 4193, // ARMInstrThumb2.td:1091 |
| 4209 | t2LSLrr = 4194, // ARMInstrThumb2.td:1103 |
| 4210 | t2LSRri = 4195, // ARMInstrThumb2.td:1091 |
| 4211 | t2LSRrr = 4196, // ARMInstrThumb2.td:1103 |
| 4212 | t2LSRs1 = 4197, // ARMInstrThumb2.td:2826 |
| 4213 | t2MCR = 4198, // ARMInstrThumb2.td:4701 |
| 4214 | t2MCR2 = 4199, // ARMInstrThumb2.td:4711 |
| 4215 | t2MCRR = 4200, // ARMInstrThumb2.td:4747 |
| 4216 | t2MCRR2 = 4201, // ARMInstrThumb2.td:4752 |
| 4217 | t2MLA = 4202, // ARMInstrThumb2.td:3079 |
| 4218 | t2MLS = 4203, // ARMInstrThumb2.td:3082 |
| 4219 | t2MOVTi16 = 4204, // ARMInstrThumb2.td:2302 |
| 4220 | t2MOVi = 4205, // ARMInstrThumb2.td:2247 |
| 4221 | t2MOVi16 = 4206, // ARMInstrThumb2.td:2270 |
| 4222 | t2MOVr = 4207, // ARMInstrThumb2.td:2227 |
| 4223 | t2MRC = 4208, // ARMInstrThumb2.td:4723 |
| 4224 | t2MRC2 = 4209, // ARMInstrThumb2.td:4730 |
| 4225 | t2MRRC = 4210, // ARMInstrThumb2.td:4761 |
| 4226 | t2MRRC2 = 4211, // ARMInstrThumb2.td:4764 |
| 4227 | t2MRS_AR = 4212, // ARMInstrThumb2.td:4532 |
| 4228 | t2MRS_M = 4213, // ARMInstrThumb2.td:4571 |
| 4229 | t2MRSbanked = 4214, // ARMInstrThumb2.td:4550 |
| 4230 | t2MRSsys_AR = 4215, // ARMInstrThumb2.td:4542 |
| 4231 | t2MSR_AR = 4216, // ARMInstrThumb2.td:4594 |
| 4232 | t2MSR_M = 4217, // ARMInstrThumb2.td:4630 |
| 4233 | t2MSRbanked = 4218, // ARMInstrThumb2.td:4609 |
| 4234 | t2MUL = 4219, // ARMInstrThumb2.td:3057 |
| 4235 | t2MVNi = 4220, // ARMInstrThumb2.td:2982 |
| 4236 | t2MVNr = 4221, // ARMInstrThumb2.td:2995 |
| 4237 | t2MVNs = 4222, // ARMInstrThumb2.td:3007 |
| 4238 | t2ORNri = 4223, // ARMInstrThumb2.td:733 |
| 4239 | t2ORNrr = 4224, // ARMInstrThumb2.td:744 |
| 4240 | t2ORNrs = 4225, // ARMInstrThumb2.td:768 |
| 4241 | t2ORRri = 4226, // ARMInstrThumb2.td:733 |
| 4242 | t2ORRrr = 4227, // ARMInstrThumb2.td:744 |
| 4243 | t2ORRrs = 4228, // ARMInstrThumb2.td:768 |
| 4244 | t2PAC = 4229, // ARMInstrThumb2.td:5932 |
| 4245 | t2PACBTI = 4230, // ARMInstrThumb2.td:5933 |
| 4246 | t2PACG = 4231, // ARMInstrThumb2.td:5860 |
| 4247 | t2PKHBT = 4232, // ARMInstrThumb2.td:3394 |
| 4248 | t2PKHTB = 4233, // ARMInstrThumb2.td:3423 |
| 4249 | t2PLDWi12 = 4234, // ARMInstrThumb2.td:1925 |
| 4250 | t2PLDWi8 = 4235, // ARMInstrThumb2.td:1944 |
| 4251 | t2PLDWs = 4236, // ARMInstrThumb2.td:1964 |
| 4252 | t2PLDi12 = 4237, // ARMInstrThumb2.td:1925 |
| 4253 | t2PLDi8 = 4238, // ARMInstrThumb2.td:1944 |
| 4254 | t2PLDpci = 4239, // ARMInstrThumb2.td:2037 |
| 4255 | t2PLDs = 4240, // ARMInstrThumb2.td:1964 |
| 4256 | t2PLIi12 = 4241, // ARMInstrThumb2.td:1925 |
| 4257 | t2PLIi8 = 4242, // ARMInstrThumb2.td:1944 |
| 4258 | t2PLIpci = 4243, // ARMInstrThumb2.td:2038 |
| 4259 | t2PLIs = 4244, // ARMInstrThumb2.td:1964 |
| 4260 | t2QADD = 4245, // ARMInstrThumb2.td:2600 |
| 4261 | t2QADD16 = 4246, // ARMInstrThumb2.td:2588 |
| 4262 | t2QADD8 = 4247, // ARMInstrThumb2.td:2589 |
| 4263 | t2QASX = 4248, // ARMInstrThumb2.td:2590 |
| 4264 | t2QDADD = 4249, // ARMInstrThumb2.td:2602 |
| 4265 | t2QDSUB = 4250, // ARMInstrThumb2.td:2603 |
| 4266 | t2QSAX = 4251, // ARMInstrThumb2.td:2592 |
| 4267 | t2QSUB = 4252, // ARMInstrThumb2.td:2601 |
| 4268 | t2QSUB16 = 4253, // ARMInstrThumb2.td:2593 |
| 4269 | t2QSUB8 = 4254, // ARMInstrThumb2.td:2594 |
| 4270 | t2RBIT = 4255, // ARMInstrThumb2.td:3368 |
| 4271 | t2REV = 4256, // ARMInstrThumb2.td:3373 |
| 4272 | t2REV16 = 4257, // ARMInstrThumb2.td:3377 |
| 4273 | t2REVSH = 4258, // ARMInstrThumb2.td:3385 |
| 4274 | t2RFEDB = 4259, // ARMInstrThumb2.td:4305 |
| 4275 | t2RFEDBW = 4260, // ARMInstrThumb2.td:4302 |
| 4276 | t2RFEIA = 4261, // ARMInstrThumb2.td:4311 |
| 4277 | t2RFEIAW = 4262, // ARMInstrThumb2.td:4308 |
| 4278 | t2RORri = 4263, // ARMInstrThumb2.td:1091 |
| 4279 | t2RORrr = 4264, // ARMInstrThumb2.td:1103 |
| 4280 | t2RRX = 4265, // ARMInstrThumb2.td:2808 |
| 4281 | t2RSBri = 4266, // ARMInstrThumb2.td:830 |
| 4282 | t2RSBrr = 4267, // ARMInstrThumb2.td:841 |
| 4283 | t2RSBrs = 4268, // ARMInstrThumb2.td:855 |
| 4284 | t2SADD16 = 4269, // ARMInstrThumb2.td:2644 |
| 4285 | t2SADD8 = 4270, // ARMInstrThumb2.td:2645 |
| 4286 | t2SASX = 4271, // ARMInstrThumb2.td:2643 |
| 4287 | t2SB = 4272, // ARMInstrThumb2.td:3691 |
| 4288 | t2SBCri = 4273, // ARMInstrThumb2.td:1033 |
| 4289 | t2SBCrr = 4274, // ARMInstrThumb2.td:1043 |
| 4290 | t2SBCrs = 4275, // ARMInstrThumb2.td:1056 |
| 4291 | t2SBFX = 4276, // ARMInstrThumb2.td:2909 |
| 4292 | t2SDIV = 4277, // ARMInstrThumb2.td:3323 |
| 4293 | t2SEL = 4278, // ARMInstrThumb2.td:2543 |
| 4294 | t2SETPAN = 4279, // ARMInstrThumb2.td:4839 |
| 4295 | t2SG = 4280, // ARMInstrThumb2.td:4856 |
| 4296 | t2SHADD16 = 4281, // ARMInstrThumb2.td:2659 |
| 4297 | t2SHADD8 = 4282, // ARMInstrThumb2.td:2660 |
| 4298 | t2SHASX = 4283, // ARMInstrThumb2.td:2658 |
| 4299 | t2SHSAX = 4284, // ARMInstrThumb2.td:2661 |
| 4300 | t2SHSUB16 = 4285, // ARMInstrThumb2.td:2662 |
| 4301 | t2SHSUB8 = 4286, // ARMInstrThumb2.td:2663 |
| 4302 | t2SMC = 4287, // ARMInstrThumb2.td:4234 |
| 4303 | t2SMLABB = 4288, // ARMInstrThumb2.td:3206 |
| 4304 | t2SMLABT = 4289, // ARMInstrThumb2.td:3208 |
| 4305 | t2SMLAD = 4290, // ARMInstrThumb2.td:3290 |
| 4306 | t2SMLADX = 4291, // ARMInstrThumb2.td:3291 |
| 4307 | t2SMLAL = 4292, // ARMInstrThumb2.td:3098 |
| 4308 | t2SMLALBB = 4293, // ARMInstrThumb2.td:3245 |
| 4309 | t2SMLALBT = 4294, // ARMInstrThumb2.td:3247 |
| 4310 | t2SMLALD = 4295, // ARMInstrThumb2.td:3304 |
| 4311 | t2SMLALDX = 4296, // ARMInstrThumb2.td:3305 |
| 4312 | t2SMLALTB = 4297, // ARMInstrThumb2.td:3249 |
| 4313 | t2SMLALTT = 4298, // ARMInstrThumb2.td:3251 |
| 4314 | t2SMLATB = 4299, // ARMInstrThumb2.td:3210 |
| 4315 | t2SMLATT = 4300, // ARMInstrThumb2.td:3212 |
| 4316 | t2SMLAWB = 4301, // ARMInstrThumb2.td:3214 |
| 4317 | t2SMLAWT = 4302, // ARMInstrThumb2.td:3216 |
| 4318 | t2SMLSD = 4303, // ARMInstrThumb2.td:3292 |
| 4319 | t2SMLSDX = 4304, // ARMInstrThumb2.td:3293 |
| 4320 | t2SMLSLD = 4305, // ARMInstrThumb2.td:3306 |
| 4321 | t2SMLSLDX = 4306, // ARMInstrThumb2.td:3307 |
| 4322 | t2SMMLA = 4307, // ARMInstrThumb2.td:3138 |
| 4323 | t2SMMLAR = 4308, // ARMInstrThumb2.td:3140 |
| 4324 | t2SMMLS = 4309, // ARMInstrThumb2.td:3142 |
| 4325 | t2SMMLSR = 4310, // ARMInstrThumb2.td:3143 |
| 4326 | t2SMMUL = 4311, // ARMInstrThumb2.td:3118 |
| 4327 | t2SMMULR = 4312, // ARMInstrThumb2.td:3120 |
| 4328 | t2SMUAD = 4313, // ARMInstrThumb2.td:3276 |
| 4329 | t2SMUADX = 4314, // ARMInstrThumb2.td:3277 |
| 4330 | t2SMULBB = 4315, // ARMInstrThumb2.td:3160 |
| 4331 | t2SMULBT = 4316, // ARMInstrThumb2.td:3162 |
| 4332 | t2SMULL = 4317, // ARMInstrThumb2.td:3089 |
| 4333 | t2SMULTB = 4318, // ARMInstrThumb2.td:3164 |
| 4334 | t2SMULTT = 4319, // ARMInstrThumb2.td:3166 |
| 4335 | t2SMULWB = 4320, // ARMInstrThumb2.td:3168 |
| 4336 | t2SMULWT = 4321, // ARMInstrThumb2.td:3170 |
| 4337 | t2SMUSD = 4322, // ARMInstrThumb2.td:3278 |
| 4338 | t2SMUSDX = 4323, // ARMInstrThumb2.td:3279 |
| 4339 | t2SRSDB = 4324, // ARMInstrThumb2.td:4275 |
| 4340 | t2SRSDB_UPD = 4325, // ARMInstrThumb2.td:4273 |
| 4341 | t2SRSIA = 4326, // ARMInstrThumb2.td:4279 |
| 4342 | t2SRSIA_UPD = 4327, // ARMInstrThumb2.td:4277 |
| 4343 | t2SSAT = 4328, // ARMInstrThumb2.td:2728 |
| 4344 | t2SSAT16 = 4329, // ARMInstrThumb2.td:2735 |
| 4345 | t2SSAX = 4330, // ARMInstrThumb2.td:2646 |
| 4346 | t2SSUB16 = 4331, // ARMInstrThumb2.td:2647 |
| 4347 | t2SSUB8 = 4332, // ARMInstrThumb2.td:2648 |
| 4348 | t2STC2L_OFFSET = 4333, // ARMInstrThumb2.td:4434 |
| 4349 | t2STC2L_OPTION = 4334, // ARMInstrThumb2.td:4487 |
| 4350 | t2STC2L_POST = 4335, // ARMInstrThumb2.td:4468 |
| 4351 | t2STC2L_PRE = 4336, // ARMInstrThumb2.td:4451 |
| 4352 | t2STC2_OFFSET = 4337, // ARMInstrThumb2.td:4434 |
| 4353 | t2STC2_OPTION = 4338, // ARMInstrThumb2.td:4487 |
| 4354 | t2STC2_POST = 4339, // ARMInstrThumb2.td:4468 |
| 4355 | t2STC2_PRE = 4340, // ARMInstrThumb2.td:4451 |
| 4356 | t2STCL_OFFSET = 4341, // ARMInstrThumb2.td:4434 |
| 4357 | t2STCL_OPTION = 4342, // ARMInstrThumb2.td:4487 |
| 4358 | t2STCL_POST = 4343, // ARMInstrThumb2.td:4468 |
| 4359 | t2STCL_PRE = 4344, // ARMInstrThumb2.td:4451 |
| 4360 | t2STC_OFFSET = 4345, // ARMInstrThumb2.td:4434 |
| 4361 | t2STC_OPTION = 4346, // ARMInstrThumb2.td:4487 |
| 4362 | t2STC_POST = 4347, // ARMInstrThumb2.td:4468 |
| 4363 | t2STC_PRE = 4348, // ARMInstrThumb2.td:4451 |
| 4364 | t2STL = 4349, // ARMInstrThumb2.td:1912 |
| 4365 | t2STLB = 4350, // ARMInstrThumb2.td:1914 |
| 4366 | t2STLEX = 4351, // ARMInstrThumb2.td:3864 |
| 4367 | t2STLEXB = 4352, // ARMInstrThumb2.td:3846 |
| 4368 | t2STLEXD = 4353, // ARMInstrThumb2.td:3883 |
| 4369 | t2STLEXH = 4354, // ARMInstrThumb2.td:3855 |
| 4370 | t2STLH = 4355, // ARMInstrThumb2.td:1916 |
| 4371 | t2STMDB = 4356, // ARMInstrThumb2.td:2175 |
| 4372 | t2STMDB_UPD = 4357, // ARMInstrThumb2.td:2194 |
| 4373 | t2STMIA = 4358, // ARMInstrThumb2.td:2137 |
| 4374 | t2STMIA_UPD = 4359, // ARMInstrThumb2.td:2156 |
| 4375 | t2STRBT = 4360, // ARMInstrThumb2.td:1857 |
| 4376 | t2STRB_POST = 4361, // ARMInstrThumb2.td:1765 |
| 4377 | t2STRB_PRE = 4362, // ARMInstrThumb2.td:1735 |
| 4378 | t2STRBi12 = 4363, // ARMInstrThumb2.td:1294 |
| 4379 | t2STRBi8 = 4364, // ARMInstrThumb2.td:1312 |
| 4380 | t2STRBs = 4365, // ARMInstrThumb2.td:1333 |
| 4381 | t2STRD_POST = 4366, // ARMInstrThumb2.td:1887 |
| 4382 | t2STRD_PRE = 4367, // ARMInstrThumb2.td:1879 |
| 4383 | t2STRDi8 = 4368, // ARMInstrThumb2.td:1712 |
| 4384 | t2STREX = 4369, // ARMInstrThumb2.td:3819 |
| 4385 | t2STREXB = 4370, // ARMInstrThumb2.td:3804 |
| 4386 | t2STREXD = 4371, // ARMInstrThumb2.td:3837 |
| 4387 | t2STREXH = 4372, // ARMInstrThumb2.td:3811 |
| 4388 | t2STRHT = 4373, // ARMInstrThumb2.td:1858 |
| 4389 | t2STRH_POST = 4374, // ARMInstrThumb2.td:1754 |
| 4390 | t2STRH_PRE = 4375, // ARMInstrThumb2.td:1728 |
| 4391 | t2STRHi12 = 4376, // ARMInstrThumb2.td:1294 |
| 4392 | t2STRHi8 = 4377, // ARMInstrThumb2.td:1312 |
| 4393 | t2STRHs = 4378, // ARMInstrThumb2.td:1333 |
| 4394 | t2STRT = 4379, // ARMInstrThumb2.td:1856 |
| 4395 | t2STR_POST = 4380, // ARMInstrThumb2.td:1743 |
| 4396 | t2STR_PRE = 4381, // ARMInstrThumb2.td:1721 |
| 4397 | t2STRi12 = 4382, // ARMInstrThumb2.td:1294 |
| 4398 | t2STRi8 = 4383, // ARMInstrThumb2.td:1312 |
| 4399 | t2STRs = 4384, // ARMInstrThumb2.td:1333 |
| 4400 | t2SUBS_PC_LR = 4385, // ARMInstrThumb2.td:4318 |
| 4401 | t2SUBri = 4386, // ARMInstrThumb2.td:946 |
| 4402 | t2SUBri12 = 4387, // ARMInstrThumb2.td:959 |
| 4403 | t2SUBrr = 4388, // ARMInstrThumb2.td:1000 |
| 4404 | t2SUBrs = 4389, // ARMInstrThumb2.td:1014 |
| 4405 | t2SUBspImm = 4390, // ARMInstrThumb2.td:929 |
| 4406 | t2SUBspImm12 = 4391, // ARMInstrThumb2.td:978 |
| 4407 | t2SXTAB = 4392, // ARMInstrThumb2.td:2345 |
| 4408 | t2SXTAB16 = 4393, // ARMInstrThumb2.td:2347 |
| 4409 | t2SXTAH = 4394, // ARMInstrThumb2.td:2346 |
| 4410 | t2SXTB = 4395, // ARMInstrThumb2.td:2341 |
| 4411 | t2SXTB16 = 4396, // ARMInstrThumb2.td:2343 |
| 4412 | t2SXTH = 4397, // ARMInstrThumb2.td:2342 |
| 4413 | t2TBB = 4398, // ARMInstrThumb2.td:4021 |
| 4414 | t2TBH = 4399, // ARMInstrThumb2.td:4034 |
| 4415 | t2TEQri = 4400, // ARMInstrThumb2.td:1148 |
| 4416 | t2TEQrr = 4401, // ARMInstrThumb2.td:1161 |
| 4417 | t2TEQrs = 4402, // ARMInstrThumb2.td:1176 |
| 4418 | t2TSB = 4403, // ARMInstrThumb2.td:3684 |
| 4419 | t2TSTri = 4404, // ARMInstrThumb2.td:1148 |
| 4420 | t2TSTrr = 4405, // ARMInstrThumb2.td:1161 |
| 4421 | t2TSTrs = 4406, // ARMInstrThumb2.td:1176 |
| 4422 | t2TT = 4407, // ARMInstrThumb2.td:4877 |
| 4423 | t2TTA = 4408, // ARMInstrThumb2.td:4883 |
| 4424 | t2TTAT = 4409, // ARMInstrThumb2.td:4886 |
| 4425 | t2TTT = 4410, // ARMInstrThumb2.td:4880 |
| 4426 | t2UADD16 = 4411, // ARMInstrThumb2.td:2650 |
| 4427 | t2UADD8 = 4412, // ARMInstrThumb2.td:2651 |
| 4428 | t2UASX = 4413, // ARMInstrThumb2.td:2649 |
| 4429 | t2UBFX = 4414, // ARMInstrThumb2.td:2920 |
| 4430 | t2UDF = 4415, // ARMInstrThumb2.td:2932 |
| 4431 | t2UDIV = 4416, // ARMInstrThumb2.td:3335 |
| 4432 | t2UHADD16 = 4417, // ARMInstrThumb2.td:2665 |
| 4433 | t2UHADD8 = 4418, // ARMInstrThumb2.td:2666 |
| 4434 | t2UHASX = 4419, // ARMInstrThumb2.td:2664 |
| 4435 | t2UHSAX = 4420, // ARMInstrThumb2.td:2667 |
| 4436 | t2UHSUB16 = 4421, // ARMInstrThumb2.td:2668 |
| 4437 | t2UHSUB8 = 4422, // ARMInstrThumb2.td:2669 |
| 4438 | t2UMAAL = 4423, // ARMInstrThumb2.td:3100 |
| 4439 | t2UMLAL = 4424, // ARMInstrThumb2.td:3099 |
| 4440 | t2UMULL = 4425, // ARMInstrThumb2.td:3092 |
| 4441 | t2UQADD16 = 4426, // ARMInstrThumb2.td:2595 |
| 4442 | t2UQADD8 = 4427, // ARMInstrThumb2.td:2596 |
| 4443 | t2UQASX = 4428, // ARMInstrThumb2.td:2597 |
| 4444 | t2UQSAX = 4429, // ARMInstrThumb2.td:2598 |
| 4445 | t2UQSUB16 = 4430, // ARMInstrThumb2.td:2599 |
| 4446 | t2UQSUB8 = 4431, // ARMInstrThumb2.td:2591 |
| 4447 | t2USAD8 = 4432, // ARMInstrThumb2.td:2695 |
| 4448 | t2USADA8 = 4433, // ARMInstrThumb2.td:2702 |
| 4449 | t2USAT = 4434, // ARMInstrThumb2.td:2743 |
| 4450 | t2USAT16 = 4435, // ARMInstrThumb2.td:2749 |
| 4451 | t2USAX = 4436, // ARMInstrThumb2.td:2652 |
| 4452 | t2USUB16 = 4437, // ARMInstrThumb2.td:2653 |
| 4453 | t2USUB8 = 4438, // ARMInstrThumb2.td:2654 |
| 4454 | t2UXTAB = 4439, // ARMInstrThumb2.td:2416 |
| 4455 | t2UXTAB16 = 4440, // ARMInstrThumb2.td:2418 |
| 4456 | t2UXTAH = 4441, // ARMInstrThumb2.td:2417 |
| 4457 | t2UXTB = 4442, // ARMInstrThumb2.td:2389 |
| 4458 | t2UXTB16 = 4443, // ARMInstrThumb2.td:2391 |
| 4459 | t2UXTH = 4444, // ARMInstrThumb2.td:2390 |
| 4460 | t2WLS = 4445, // ARMInstrThumb2.td:5638 |
| 4461 | tADC = 4446, // ARMInstrThumb.td:981 |
| 4462 | tADDhirr = 4447, // ARMInstrThumb.td:1051 |
| 4463 | tADDi3 = 4448, // ARMInstrThumb.td:987 |
| 4464 | tADDi8 = 4449, // ARMInstrThumb.td:997 |
| 4465 | tADDrSP = 4450, // ARMInstrThumb.td:455 |
| 4466 | tADDrSPi = 4451, // ARMInstrThumb.td:400 |
| 4467 | tADDrr = 4452, // ARMInstrThumb.td:1006 |
| 4468 | tADDspi = 4453, // ARMInstrThumb.td:421 |
| 4469 | tADDspr = 4454, // ARMInstrThumb.td:468 |
| 4470 | tADR = 4455, // ARMInstrThumb.td:1484 |
| 4471 | tAND = 4456, // ARMInstrThumb.td:1083 |
| 4472 | tASRri = 4457, // ARMInstrThumb.td:1090 |
| 4473 | tASRrr = 4458, // ARMInstrThumb.td:1101 |
| 4474 | tB = 4459, // ARMInstrThumb.td:608 |
| 4475 | tBIC = 4460, // ARMInstrThumb.td:1109 |
| 4476 | tBKPT = 4461, // ARMInstrThumb.td:346 |
| 4477 | tBL = 4462, // ARMInstrThumb.td:526 |
| 4478 | tBLXNSr = 4463, // ARMInstrThumb.td:572 |
| 4479 | tBLXi = 4464, // ARMInstrThumb.td:541 |
| 4480 | tBLXr = 4465, // ARMInstrThumb.td:556 |
| 4481 | tBX = 4466, // ARMInstrThumb.td:486 |
| 4482 | tBXNS = 4467, // ARMInstrThumb.td:495 |
| 4483 | tBcc = 4468, // ARMInstrThumb.td:639 |
| 4484 | tCBNZ = 4469, // ARMInstrThumb2.td:4135 |
| 4485 | tCBZ = 4470, // ARMInstrThumb2.td:4123 |
| 4486 | tCMN = 4471, // ARMInstrThumb.td:1118 |
| 4487 | tCMPhir = 4472, // ARMInstrThumb.td:1146 |
| 4488 | tCMPi8 = 4473, // ARMInstrThumb.td:1128 |
| 4489 | tCMPr = 4474, // ARMInstrThumb.td:1140 |
| 4490 | tCPS = 4475, // ARMInstrThumb.td:375 |
| 4491 | tEOR = 4476, // ARMInstrThumb.td:1161 |
| 4492 | tHINT = 4477, // ARMInstrThumb.td:322 |
| 4493 | tHLT = 4478, // ARMInstrThumb.td:357 |
| 4494 | tInt_WIN_eh_sjlj_longjmp = 4479, // ARMInstrThumb.td:1566 |
| 4495 | tInt_eh_sjlj_longjmp = 4480, // ARMInstrThumb.td:1556 |
| 4496 | tInt_eh_sjlj_setjmp = 4481, // ARMInstrThumb.td:1548 |
| 4497 | tLDMIA = 4482, // ARMInstrThumb.td:834 |
| 4498 | tLDRBi = 4483, // ARMInstrThumb.td:734 |
| 4499 | tLDRBr = 4484, // ARMInstrThumb.td:740 |
| 4500 | tLDRHi = 4485, // ARMInstrThumb.td:734 |
| 4501 | tLDRHr = 4486, // ARMInstrThumb.td:740 |
| 4502 | tLDRSB = 4487, // ARMInstrThumb.td:783 |
| 4503 | tLDRSH = 4488, // ARMInstrThumb.td:790 |
| 4504 | tLDRi = 4489, // ARMInstrThumb.td:734 |
| 4505 | tLDRpci = 4490, // ARMInstrThumb.td:700 |
| 4506 | tLDRr = 4491, // ARMInstrThumb.td:740 |
| 4507 | tLDRspi = 4492, // ARMInstrThumb.td:714 |
| 4508 | tLSLri = 4493, // ARMInstrThumb.td:1168 |
| 4509 | tLSLrr = 4494, // ARMInstrThumb.td:1179 |
| 4510 | tLSRri = 4495, // ARMInstrThumb.td:1186 |
| 4511 | tLSRrr = 4496, // ARMInstrThumb.td:1197 |
| 4512 | tMOVSr = 4497, // ARMInstrThumb.td:1236 |
| 4513 | tMOVi8 = 4498, // ARMInstrThumb.td:1205 |
| 4514 | tMOVr = 4499, // ARMInstrThumb.td:1224 |
| 4515 | tMUL = 4500, // ARMInstrThumb.td:1249 |
| 4516 | tMVN = 4501, // ARMInstrThumb.td:1265 |
| 4517 | tORR = 4502, // ARMInstrThumb.td:1272 |
| 4518 | tPICADD = 4503, // ARMInstrThumb.td:390 |
| 4519 | tPOP = 4504, // ARMInstrThumb.td:882 |
| 4520 | tPUSH = 4505, // ARMInstrThumb.td:893 |
| 4521 | tREV = 4506, // ARMInstrThumb.td:1279 |
| 4522 | tREV16 = 4507, // ARMInstrThumb.td:1286 |
| 4523 | tREVSH = 4508, // ARMInstrThumb.td:1293 |
| 4524 | tROR = 4509, // ARMInstrThumb.td:1301 |
| 4525 | tRSB = 4510, // ARMInstrThumb.td:1309 |
| 4526 | tSBC = 4511, // ARMInstrThumb.td:1317 |
| 4527 | tSETEND = 4512, // ARMInstrThumb.td:364 |
| 4528 | tSTMIA_UPD = 4513, // ARMInstrThumb.td:862 |
| 4529 | tSTRBi = 4514, // ARMInstrThumb.td:752 |
| 4530 | tSTRBr = 4515, // ARMInstrThumb.td:757 |
| 4531 | tSTRHi = 4516, // ARMInstrThumb.td:752 |
| 4532 | tSTRHr = 4517, // ARMInstrThumb.td:757 |
| 4533 | tSTRi = 4518, // ARMInstrThumb.td:752 |
| 4534 | tSTRr = 4519, // ARMInstrThumb.td:757 |
| 4535 | tSTRspi = 4520, // ARMInstrThumb.td:797 |
| 4536 | tSUBi3 = 4521, // ARMInstrThumb.td:1325 |
| 4537 | tSUBi8 = 4522, // ARMInstrThumb.td:1335 |
| 4538 | tSUBrr = 4523, // ARMInstrThumb.td:1351 |
| 4539 | tSUBspi = 4524, // ARMInstrThumb.td:433 |
| 4540 | tSVC = 4525, // ARMInstrThumb.td:677 |
| 4541 | tSXTB = 4526, // ARMInstrThumb.td:1410 |
| 4542 | tSXTH = 4527, // ARMInstrThumb.td:1419 |
| 4543 | tTRAP = 4528, // ARMInstrThumb.td:687 |
| 4544 | tTST = 4529, // ARMInstrThumb.td:1429 |
| 4545 | tUDF = 4530, // ARMInstrThumb.td:1436 |
| 4546 | tUXTB = 4531, // ARMInstrThumb.td:1455 |
| 4547 | tUXTH = 4532, // ARMInstrThumb.td:1464 |
| 4548 | t__brkdiv0 = 4533, // ARMInstrThumb.td:1447 |
| 4549 | INSTRUCTION_LIST_END = 4534 |
| 4550 | }; |
| 4551 | enum RegClassByHwModeUses : uint16_t { |
| 4552 | arm_ptr_rc, |
| 4553 | }; |
| 4554 | |
| 4555 | } // namespace llvm::ARM |
| 4556 | |
| 4557 | #endif // GET_INSTRINFO_ENUM |
| 4558 | |
| 4559 | #ifdef GET_INSTRINFO_SCHED_ENUM |
| 4560 | #undef GET_INSTRINFO_SCHED_ENUM |
| 4561 | |
| 4562 | namespace llvm::ARM::Sched { |
| 4563 | |
| 4564 | enum { |
| 4565 | NoInstrModel = 0, |
| 4566 | IIC_iALUi_WriteALU_ReadALU = 1, |
| 4567 | IIC_iALUr_WriteALU_ReadALU_ReadALU = 2, |
| 4568 | IIC_iALUsr_WriteALUsi_ReadALU = 3, |
| 4569 | IIC_iALUsr_WriteALUSsr_ReadALUsr = 4, |
| 4570 | IIC_iMOVsi_WriteALU = 5, |
| 4571 | IIC_Br_WriteBr = 6, |
| 4572 | IIC_Br_WriteBrL = 7, |
| 4573 | IIC_Br_WriteBrTbl = 8, |
| 4574 | IIC_iLoad_mBr = 9, |
| 4575 | IIC_iLoad_i = 10, |
| 4576 | IIC_iLoadiALU = 11, |
| 4577 | IIC_iLoad_d_r = 12, |
| 4578 | IIC_iMAC32_WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 13, |
| 4579 | IIC_iCMOVi_WriteALU = 14, |
| 4580 | IIC_iMOVi_WriteALU = 15, |
| 4581 | IIC_iCMOVix2 = 16, |
| 4582 | IIC_iCMOVr_WriteALU = 17, |
| 4583 | IIC_iCMOVsr_WriteALU = 18, |
| 4584 | IIC_iMOVix2addpc = 19, |
| 4585 | IIC_iMOVix2ld = 20, |
| 4586 | IIC_iMOVix2 = 21, |
| 4587 | IIC_iMUL32_WriteMUL32_ReadMUL_ReadMUL = 22, |
| 4588 | IIC_iALUr_WriteALU_ReadALU = 23, |
| 4589 | IIC_iLoad_r = 24, |
| 4590 | IIC_iLoad_bh_r = 25, |
| 4591 | IIC_iStore_r = 26, |
| 4592 | IIC_iStore_bh_r = 27, |
| 4593 | IIC_iMAC64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 28, |
| 4594 | IIC_iMUL64_WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 29, |
| 4595 | IIC_iStore_d_r = 30, |
| 4596 | IIC_iStore_ru = 31, |
| 4597 | IIC_Br = 32, |
| 4598 | IIC_VMOVImm = 33, |
| 4599 | IIC_fpUNA64 = 34, |
| 4600 | IIC_fpUNA16 = 35, |
| 4601 | IIC_fpUNA32 = 36, |
| 4602 | IIC_iALUsi_WriteALUsi_ReadALUsr = 37, |
| 4603 | IIC_iCMOVsi_WriteALU = 38, |
| 4604 | IIC_iALUsi_WriteALUsi_ReadALU = 39, |
| 4605 | IIC_iStore_ru_WriteST = 40, |
| 4606 | IIC_iALUr_WriteALU = 41, |
| 4607 | IIC_iALUi_WriteALU = 42, |
| 4608 | IIC_iLoad_mu = 43, |
| 4609 | IIC_iPop_Br_WriteBrL = 44, |
| 4610 | IIC_iALUsr_WriteALUsr_ReadALUsr = 45, |
| 4611 | IIC_iBITi_WriteALU_ReadALU = 46, |
| 4612 | IIC_iBITr_WriteALU_ReadALU_ReadALU = 47, |
| 4613 | IIC_iBITsr_WriteALUsi_ReadALU = 48, |
| 4614 | IIC_iBITsr_WriteALUsr_ReadALUsr = 49, |
| 4615 | IIC_VDOTPROD = 50, |
| 4616 | IIC_iUNAsi = 51, |
| 4617 | WriteBrL = 52, |
| 4618 | WriteBr = 53, |
| 4619 | IIC_iUNAr_WriteALU = 54, |
| 4620 | IIC_iCMPi_WriteCMP_ReadALU = 55, |
| 4621 | IIC_iCMPr_WriteCMP_ReadALU_ReadALU = 56, |
| 4622 | IIC_iCMPsr_WriteCMPsi_ReadALU = 57, |
| 4623 | IIC_iCMPsr_WriteCMPsr_ReadALU = 58, |
| 4624 | IIC_fpSTAT = 59, |
| 4625 | IIC_iLoad_m = 60, |
| 4626 | IIC_iLoad_bh_ru = 61, |
| 4627 | IIC_iLoad_bh_iu = 62, |
| 4628 | IIC_iLoad_bh_si = 63, |
| 4629 | IIC_iLoad_d_ru = 64, |
| 4630 | IIC_iLoad_ru = 65, |
| 4631 | IIC_iLoad_iu = 66, |
| 4632 | IIC_iLoad_si = 67, |
| 4633 | IIC_iMOVr_WriteALU = 68, |
| 4634 | IIC_iMOVsr_WriteALU = 69, |
| 4635 | IIC_iMVNi_WriteALU = 70, |
| 4636 | IIC_iMVNr_WriteALU = 71, |
| 4637 | IIC_iMVNsr_WriteALU = 72, |
| 4638 | IIC_iBITsi_WriteALUsi_ReadALU = 73, |
| 4639 | IIC_Preload_WritePreLd = 74, |
| 4640 | IIC_iDIV_WriteDIV = 75, |
| 4641 | IIC_iMAC16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 76, |
| 4642 | WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 77, |
| 4643 | WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 78, |
| 4644 | WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 79, |
| 4645 | WriteMUL32_ReadMUL_ReadMUL = 80, |
| 4646 | IIC_iMUL16_WriteMUL16_ReadMUL_ReadMUL = 81, |
| 4647 | IIC_iStore_m = 82, |
| 4648 | IIC_iStore_mu = 83, |
| 4649 | IIC_iStore_bh_ru = 84, |
| 4650 | IIC_iStore_bh_iu = 85, |
| 4651 | IIC_iStore_bh_si = 86, |
| 4652 | IIC_iStore_d_ru = 87, |
| 4653 | IIC_iStore_iu = 88, |
| 4654 | IIC_iStore_si = 89, |
| 4655 | IIC_iEXTAr_WriteALUsr = 90, |
| 4656 | IIC_iEXTr_WriteALUsi = 91, |
| 4657 | IIC_iTSTi_WriteCMP_ReadALU = 92, |
| 4658 | IIC_iTSTr_WriteCMP_ReadALU_ReadALU = 93, |
| 4659 | IIC_iTSTsr_WriteCMPsi_ReadALU = 94, |
| 4660 | IIC_iTSTsr_WriteCMPsr_ReadALU = 95, |
| 4661 | IIC_iMUL64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL = 96, |
| 4662 | WriteALU_ReadALU_ReadALU = 97, |
| 4663 | IIC_VABAD = 98, |
| 4664 | IIC_VABAQ = 99, |
| 4665 | IIC_VSUBi4Q = 100, |
| 4666 | IIC_VBIND = 101, |
| 4667 | IIC_VBINQ = 102, |
| 4668 | IIC_VSUBi4D = 103, |
| 4669 | IIC_VUNAD = 104, |
| 4670 | IIC_VUNAQ = 105, |
| 4671 | IIC_VUNAiQ = 106, |
| 4672 | IIC_VUNAiD = 107, |
| 4673 | IIC_fpALU64_WriteFPALU64 = 108, |
| 4674 | IIC_fpALU16_WriteFPALU32 = 109, |
| 4675 | IIC_VBINi4D = 110, |
| 4676 | IIC_VSHLiD = 111, |
| 4677 | IIC_fpALU32_WriteFPALU32 = 112, |
| 4678 | IIC_VSUBiD = 113, |
| 4679 | IIC_VBINiQ = 114, |
| 4680 | IIC_VBINiD = 115, |
| 4681 | IIC_VMACD = 116, |
| 4682 | IIC_VMACQ = 117, |
| 4683 | IIC_VCNTiQ = 118, |
| 4684 | IIC_VCNTiD = 119, |
| 4685 | IIC_fpCMP64 = 120, |
| 4686 | IIC_fpCMP16 = 121, |
| 4687 | IIC_fpCMP32 = 122, |
| 4688 | WriteFPCVT = 123, |
| 4689 | IIC_fpCVTSH_WriteFPCVT = 124, |
| 4690 | IIC_fpCVTHS_WriteFPCVT = 125, |
| 4691 | IIC_fpCVTDS_WriteFPCVT = 126, |
| 4692 | IIC_fpCVTSD_WriteFPCVT = 127, |
| 4693 | IIC_fpDIV64_WriteFPDIV64 = 128, |
| 4694 | IIC_fpDIV16_WriteFPDIV32 = 129, |
| 4695 | IIC_fpDIV32_WriteFPDIV32 = 130, |
| 4696 | IIC_VMOVIS = 131, |
| 4697 | IIC_VMOVD = 132, |
| 4698 | IIC_VMOVQ = 133, |
| 4699 | IIC_VEXTD = 134, |
| 4700 | IIC_VEXTQ = 135, |
| 4701 | IIC_fpFMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 136, |
| 4702 | IIC_fpFMAC16_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 137, |
| 4703 | IIC_fpFMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 138, |
| 4704 | IIC_VFMACD = 139, |
| 4705 | IIC_VFMACQ = 140, |
| 4706 | IIC_VMOVSI = 141, |
| 4707 | IIC_VBINi4Q = 142, |
| 4708 | IIC_fpCVTDI = 143, |
| 4709 | IIC_VLD1dup_WriteVLD2 = 144, |
| 4710 | IIC_VLD1dupu = 145, |
| 4711 | IIC_VLD1dup = 146, |
| 4712 | IIC_VLD1dupu_WriteVLD1 = 147, |
| 4713 | IIC_VLD1ln = 148, |
| 4714 | IIC_VLD1lnu_WriteVLD1 = 149, |
| 4715 | IIC_VLD1ln_WriteVLD1 = 150, |
| 4716 | IIC_VLD1_WriteVLD1 = 151, |
| 4717 | IIC_VLD1x4_WriteVLD4 = 152, |
| 4718 | IIC_VLD1x2u_WriteVLD4 = 153, |
| 4719 | IIC_VLD1x3_WriteVLD3 = 154, |
| 4720 | IIC_VLD1x2u_WriteVLD3 = 155, |
| 4721 | IIC_VLD1u_WriteVLD1 = 156, |
| 4722 | IIC_VLD1x2_WriteVLD2 = 157, |
| 4723 | IIC_VLD1x2u_WriteVLD2 = 158, |
| 4724 | IIC_VLD2dup = 159, |
| 4725 | IIC_VLD2dupu_WriteVLD1 = 160, |
| 4726 | IIC_VLD2dup_WriteVLD2 = 161, |
| 4727 | IIC_VLD2ln_WriteVLD1 = 162, |
| 4728 | IIC_VLD2lnu_WriteVLD1 = 163, |
| 4729 | IIC_VLD2lnu = 164, |
| 4730 | IIC_VLD2_WriteVLD2 = 165, |
| 4731 | IIC_VLD2u_WriteVLD2 = 166, |
| 4732 | IIC_VLD2x2_WriteVLD4 = 167, |
| 4733 | IIC_VLD2x2u_WriteVLD4 = 168, |
| 4734 | IIC_VLD3dup_WriteVLD2 = 169, |
| 4735 | IIC_VLD3dupu_WriteVLD2 = 170, |
| 4736 | IIC_VLD3ln_WriteVLD2 = 171, |
| 4737 | IIC_VLD3lnu_WriteVLD2 = 172, |
| 4738 | IIC_VLD3_WriteVLD3 = 173, |
| 4739 | IIC_VLD3u_WriteVLD3 = 174, |
| 4740 | IIC_VLD4dup = 175, |
| 4741 | IIC_VLD4dup_WriteVLD2 = 176, |
| 4742 | IIC_VLD4dupu_WriteVLD2 = 177, |
| 4743 | IIC_VLD4ln_WriteVLD2 = 178, |
| 4744 | IIC_VLD4lnu_WriteVLD2 = 179, |
| 4745 | IIC_VLD4lnu = 180, |
| 4746 | IIC_VLD4_WriteVLD4 = 181, |
| 4747 | IIC_VLD4u_WriteVLD4 = 182, |
| 4748 | IIC_fpLoad_mu = 183, |
| 4749 | IIC_fpLoad_m = 184, |
| 4750 | IIC_fpLoad64 = 185, |
| 4751 | IIC_fpLoad16 = 186, |
| 4752 | IIC_fpLoad32 = 187, |
| 4753 | IIC_fpMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 188, |
| 4754 | IIC_fpMAC16 = 189, |
| 4755 | IIC_VMACi32D = 190, |
| 4756 | IIC_VMACi16D = 191, |
| 4757 | IIC_fpMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 192, |
| 4758 | IIC_VMACi32Q = 193, |
| 4759 | IIC_VMACi16Q = 194, |
| 4760 | IIC_fpMOVID_WriteFPMOV = 195, |
| 4761 | IIC_fpMOVIS_WriteFPMOV = 196, |
| 4762 | IIC_VQUNAiD = 197, |
| 4763 | IIC_VMOVN = 198, |
| 4764 | IIC_fpMOVSI_WriteFPMOV = 199, |
| 4765 | IIC_fpMOVDI_WriteFPMOV = 200, |
| 4766 | IIC_fpMUL64_WriteFPMUL64_ReadFPMUL_ReadFPMUL = 201, |
| 4767 | IIC_fpMUL16_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 202, |
| 4768 | IIC_VMULi16D = 203, |
| 4769 | IIC_VMULi32D = 204, |
| 4770 | IIC_fpMUL32_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 205, |
| 4771 | IIC_VFMULD = 206, |
| 4772 | IIC_VFMULQ = 207, |
| 4773 | IIC_VMULi16Q = 208, |
| 4774 | IIC_VMULi32Q = 209, |
| 4775 | IIC_VSHLiQ = 210, |
| 4776 | IIC_VPALiQ = 211, |
| 4777 | IIC_VPALiD = 212, |
| 4778 | IIC_VPBIND = 213, |
| 4779 | IIC_VQUNAiQ = 214, |
| 4780 | IIC_VSHLi4Q = 215, |
| 4781 | IIC_VSHLi4D = 216, |
| 4782 | IIC_VRECSD = 217, |
| 4783 | IIC_VRECSQ = 218, |
| 4784 | IIC_VMOVISL = 219, |
| 4785 | IIC_fpCVTID_WriteFPCVT = 220, |
| 4786 | IIC_fpCVTIH_WriteFPCVT = 221, |
| 4787 | IIC_fpCVTIS_WriteFPCVT = 222, |
| 4788 | IIC_fpSQRT64_WriteFPSQRT64 = 223, |
| 4789 | IIC_fpSQRT16 = 224, |
| 4790 | IIC_fpSQRT32_WriteFPSQRT32 = 225, |
| 4791 | IIC_VST1ln_WriteVST1 = 226, |
| 4792 | IIC_VST1lnu_WriteVST1 = 227, |
| 4793 | IIC_VST1_WriteVST1 = 228, |
| 4794 | IIC_VST1x4_WriteVST4 = 229, |
| 4795 | IIC_VST1x4u_WriteVST4 = 230, |
| 4796 | IIC_VLD1x4u_WriteVST4 = 231, |
| 4797 | IIC_VST1x3_WriteVST3 = 232, |
| 4798 | IIC_VST1x3u_WriteVST3 = 233, |
| 4799 | IIC_VLD1x3u_WriteVST3 = 234, |
| 4800 | IIC_VLD1u_WriteVST1 = 235, |
| 4801 | IIC_VST1x2_WriteVST2 = 236, |
| 4802 | IIC_VLD1x2u_WriteVST2 = 237, |
| 4803 | IIC_VST2ln_WriteVST1 = 238, |
| 4804 | IIC_VST2lnu_WriteVST1 = 239, |
| 4805 | IIC_VST2lnu = 240, |
| 4806 | IIC_VST2 = 241, |
| 4807 | IIC_VLD1u_WriteVST2 = 242, |
| 4808 | IIC_VST2_WriteVST2 = 243, |
| 4809 | IIC_VST2x2_WriteVST4 = 244, |
| 4810 | IIC_VST2x2u_WriteVST4 = 245, |
| 4811 | IIC_VLD1u_WriteVST4 = 246, |
| 4812 | IIC_VST3ln_WriteVST2 = 247, |
| 4813 | IIC_VST3lnu_WriteVST2 = 248, |
| 4814 | IIC_VST3lnu = 249, |
| 4815 | IIC_VST3ln = 250, |
| 4816 | IIC_VST3_WriteVST3 = 251, |
| 4817 | IIC_VST3u_WriteVST3 = 252, |
| 4818 | IIC_VST4ln_WriteVST2 = 253, |
| 4819 | IIC_VST4lnu_WriteVST2 = 254, |
| 4820 | IIC_VST4lnu = 255, |
| 4821 | IIC_VST4_WriteVST4 = 256, |
| 4822 | IIC_VST4u_WriteVST4 = 257, |
| 4823 | IIC_fpStore_mu = 258, |
| 4824 | IIC_fpStore_m = 259, |
| 4825 | IIC_fpStore64 = 260, |
| 4826 | IIC_fpStore16 = 261, |
| 4827 | IIC_fpStore32 = 262, |
| 4828 | IIC_VSUBiQ = 263, |
| 4829 | IIC_VTB1 = 264, |
| 4830 | IIC_VTB2 = 265, |
| 4831 | IIC_VTB3 = 266, |
| 4832 | IIC_VTB4 = 267, |
| 4833 | IIC_VTBX1 = 268, |
| 4834 | IIC_VTBX2 = 269, |
| 4835 | IIC_VTBX3 = 270, |
| 4836 | IIC_VTBX4 = 271, |
| 4837 | IIC_fpCVTDI_WriteFPCVT = 272, |
| 4838 | IIC_fpCVTHI_WriteFPCVT = 273, |
| 4839 | IIC_fpCVTSI_WriteFPCVT = 274, |
| 4840 | IIC_VPERMD = 275, |
| 4841 | IIC_VPERMQ = 276, |
| 4842 | IIC_VPERMQ3 = 277, |
| 4843 | IIC_iUNAsi_WriteALU = 278, |
| 4844 | IIC_iBITi_WriteALU = 279, |
| 4845 | IIC_iCMPsi_WriteCMPsi_ReadALU_ReadALU = 280, |
| 4846 | IIC_iCMPi_WriteCMP = 281, |
| 4847 | IIC_iCMPr_WriteCMP = 282, |
| 4848 | IIC_iCMPsi_WriteCMPsi = 283, |
| 4849 | IIC_iALUx = 284, |
| 4850 | WriteLd = 285, |
| 4851 | IIC_iLoad_bh_i_WriteLd = 286, |
| 4852 | IIC_iLoad_bh_iu_WriteLd = 287, |
| 4853 | IIC_iLoad_bh_si_WriteLd = 288, |
| 4854 | IIC_iLoad_d_ru_WriteLd = 289, |
| 4855 | IIC_iLoad_d_i_WriteLd = 290, |
| 4856 | IIC_iLoad_i_WriteLd = 291, |
| 4857 | IIC_iLoad_iu_WriteLd = 292, |
| 4858 | IIC_iLoad_si_WriteLd = 293, |
| 4859 | IIC_iMVNsi_WriteALU = 294, |
| 4860 | IIC_iALUsir_WriteALUsi_ReadALU = 295, |
| 4861 | IIC_iMUL16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 296, |
| 4862 | IIC_iMAC32 = 297, |
| 4863 | WriteALU = 298, |
| 4864 | WriteST = 299, |
| 4865 | IIC_iStore_bh_i_WriteST = 300, |
| 4866 | IIC_iStore_bh_iu_WriteST = 301, |
| 4867 | IIC_iStore_bh_si_WriteST = 302, |
| 4868 | IIC_iStore_d_ru_WriteST = 303, |
| 4869 | IIC_iStore_d_r_WriteST = 304, |
| 4870 | IIC_iStore_iu_WriteST = 305, |
| 4871 | IIC_iStore_i_WriteST = 306, |
| 4872 | IIC_iStore_si_WriteST = 307, |
| 4873 | IIC_iEXTAsr_WriteALU_ReadALU = 308, |
| 4874 | IIC_iEXTr_WriteALU_ReadALU = 309, |
| 4875 | IIC_iTSTi_WriteCMP = 310, |
| 4876 | IIC_iTSTr_WriteCMP = 311, |
| 4877 | IIC_iTSTsi_WriteCMPsi = 312, |
| 4878 | IIC_iBITr_WriteALU = 313, |
| 4879 | IIC_iLoad_bh_r_WriteLd = 314, |
| 4880 | IIC_iLoad_r_WriteLd = 315, |
| 4881 | IIC_iPop_WriteLd = 316, |
| 4882 | IIC_iStore_m_WriteST = 317, |
| 4883 | IIC_iStore_bh_r_WriteST = 318, |
| 4884 | IIC_iStore_r_WriteST = 319, |
| 4885 | IIC_iTSTr_WriteALU = 320, |
| 4886 | ANDri_ORRri_EORri_BICri = 321, |
| 4887 | ANDrr_ORRrr_EORrr_BICrr = 322, |
| 4888 | ANDrsi_ORRrsi_EORrsi_BICrsi = 323, |
| 4889 | ANDrsr_ORRrsr_EORrsr_BICrsr = 324, |
| 4890 | MOVsr_MOVsi = 325, |
| 4891 | MVNsr = 326, |
| 4892 | MOVCCsi_MOVCCsr = 327, |
| 4893 | MVNr = 328, |
| 4894 | MOVCCi32imm = 329, |
| 4895 | MOVi32imm = 330, |
| 4896 | MOV_ga_pcrel = 331, |
| 4897 | MOV_ga_pcrel_ldr = 332, |
| 4898 | SEL = 333, |
| 4899 | BFC_BFI_UBFX_SBFX = 334, |
| 4900 | MULv5_MUL_SMMUL_SMMULR = 335, |
| 4901 | MLAv5_MLA_MLS_SMMLA_SMMLAR_SMMLS_SMMLSR = 336, |
| 4902 | SMULLv5_SMULL_UMULLv5 = 337, |
| 4903 | UMULL = 338, |
| 4904 | SMLAL_UMLALv5_UMLAL_UMAAL_SMLALv5_SMLALBB_SMLALBT_SMLALTB_SMLALTT = 339, |
| 4905 | SMLAD_SMLADX_SMLSD_SMLSDX = 340, |
| 4906 | SMLALD_SMLSLD = 341, |
| 4907 | SMLALDX_SMLSLDX = 342, |
| 4908 | SMUAD_SMUADX_SMUSD_SMUSDX = 343, |
| 4909 | SMULBB_SMULBT_SMULTB_SMULTT_SMULWB_SMULWT = 344, |
| 4910 | SMLABB_SMLABT_SMLATB_SMLATT_SMLAWB_SMLAWT = 345, |
| 4911 | LDRi12_PICLDR = 346, |
| 4912 | LDRrs = 347, |
| 4913 | LDRBi12_PICLDRH_PICLDRB_PICLDRSH_PICLDRSB_LDRH_LDRSH_LDRSB = 348, |
| 4914 | LDRHTii_LDRSHTii_LDRSBTii = 349, |
| 4915 | LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE_LDRSHTi_LDRSHTr_LDRSH_POST_LDRSH_PRE_LDRSBTi_LDRSBTr_LDRSB_POST_LDRSB_PRE = 350, |
| 4916 | SXTB_SXTB16_SXTH_UXTB_UXTB16_UXTH = 351, |
| 4917 | t2SXTB_t2SXTB16_t2SXTH_t2UXTB_t2UXTB16_t2UXTH = 352, |
| 4918 | t2MOVCCi32imm = 353, |
| 4919 | t2MOVi32imm = 354, |
| 4920 | t2MOV_ga_pcrel = 355, |
| 4921 | t2MOVi16_ga_pcrel = 356, |
| 4922 | t2SEL = 357, |
| 4923 | t2BFC_t2UBFX_t2SBFX = 358, |
| 4924 | t2BFI = 359, |
| 4925 | QADD_QADD16_QADD8_QSUB_QSUB16_QSUB8_QDADD_QDSUB_QASX_QSAX_UQADD8_UQADD16_UQSUB8_UQSUB16_UQASX_UQSAX = 360, |
| 4926 | SSAT_SSAT16_USAT_USAT16_t2QADD_t2QADD16_t2QADD8_t2QSUB_t2QSUB16_t2QSUB8_t2QDADD_t2QDSUB_t2QASX_t2QSAX_t2UQADD8_t2UQADD16_t2UQSUB8_t2UQSUB16_t2UQASX_t2UQSAX = 361, |
| 4927 | t2SSAT_t2SSAT16_t2USAT_t2USAT16 = 362, |
| 4928 | SADD8_SADD16_SSUB8_SSUB16_SASX_SSAX_UADD8_UADD16_USUB8_USUB16_UASX_USAX = 363, |
| 4929 | t2SADD8_t2SADD16_t2SSUB8_t2SSUB16_t2SASX_t2SSAX_t2UADD8_t2UADD16_t2USUB8_t2USUB16_t2UASX_t2USAX = 364, |
| 4930 | SHADD8_SHADD16_SHSUB8_SHSUB16_SHASX_SHSAX_UHADD8_UHADD16_UHSUB8_UHSUB16_UHASX_UHSAX = 365, |
| 4931 | SXTAB_SXTAB16_SXTAH_UXTAB_UXTAB16_UXTAH = 366, |
| 4932 | t2SHADD8_t2SHADD16_t2SHSUB8_t2SHSUB16_t2SHASX_t2SHSAX_t2UHADD8_t2UHADD16_t2UHSUB8_t2UHSUB16_t2UHASX_t2UHSAX = 367, |
| 4933 | t2SXTAB_t2SXTAB16_t2SXTAH_t2UXTAB_t2UXTAB16_t2UXTAH = 368, |
| 4934 | USAD8 = 369, |
| 4935 | USADA8 = 370, |
| 4936 | SMUSD_SMUSDX = 371, |
| 4937 | t2MUL_t2SMMUL_t2SMMULR = 372, |
| 4938 | t2SMULBB_t2SMULBT_t2SMULTB_t2SMULTT_t2SMULWB_t2SMULWT = 373, |
| 4939 | t2SMUSD_t2SMUSDX = 374, |
| 4940 | t2MLA_t2MLS_t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 375, |
| 4941 | t2SMUAD_t2SMUADX = 376, |
| 4942 | SMLSD_SMLSDX = 377, |
| 4943 | t2SMLABB_t2SMLABT_t2SMLATB_t2SMLATT_t2SMLAWB_t2SMLAWT = 378, |
| 4944 | t2SMLSD_t2SMLSDX = 379, |
| 4945 | t2SMLAD_t2SMLADX = 380, |
| 4946 | SMULL = 381, |
| 4947 | t2SMULL_t2UMULL = 382, |
| 4948 | t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2UMLAL_t2SMLSLD_t2SMLSLDX_t2UMAAL = 383, |
| 4949 | SDIV_UDIV_t2SDIV_t2UDIV = 384, |
| 4950 | LDRi12 = 385, |
| 4951 | LDRBi12 = 386, |
| 4952 | LDRBrs = 387, |
| 4953 | t2LDRpci_pic = 388, |
| 4954 | t2LDRi12_t2LDRi8_t2LDRpci_tLDRi_tLDRpci_tLDRspi = 389, |
| 4955 | t2LDRs = 390, |
| 4956 | t2LDRBi12_t2LDRBi8_t2LDRBpci_t2LDRHi12_t2LDRHi8_t2LDRHpci_tLDRBi_tLDRHi = 391, |
| 4957 | t2LDRBs_t2LDRHs = 392, |
| 4958 | LDREX_LDREXB_LDREXD_LDREXH_tLDRpci_pic = 393, |
| 4959 | tLDRBr_tLDRHr = 394, |
| 4960 | tLDRr = 395, |
| 4961 | LDRH_PICLDRB_PICLDRH = 396, |
| 4962 | LDRcp = 397, |
| 4963 | t2LDRSBpcrel_t2LDRSHpcrel = 398, |
| 4964 | t2LDRSBi12_t2LDRSBi8_t2LDRSBpci_t2LDRSHi12_t2LDRSHi8_t2LDRSHpci = 399, |
| 4965 | t2LDRSBs_t2LDRSHs = 400, |
| 4966 | tLDRSB_tLDRSH = 401, |
| 4967 | LDRBT_POST_IMM_LDRBT_POST_REG_LDRB_POST_REG_LDRB_PRE_REG = 402, |
| 4968 | LDRB_POST_IMM_LDRB_PRE_IMM = 403, |
| 4969 | LDRT_POST_IMM_LDRT_POST_REG_LDR_POST_REG_LDR_PRE_REG = 404, |
| 4970 | LDR_POST_IMM_LDR_PRE_IMM = 405, |
| 4971 | LDRH_POST_LDRH_PRE_LDRHTi_LDRHTr = 406, |
| 4972 | LDRHTii = 407, |
| 4973 | t2LDRB_POST_imm_t2LDRB_PRE_imm_t2LDRH_POST_imm_t2LDRH_PRE_imm_t2LDR_POST_imm_t2LDR_PRE_imm = 408, |
| 4974 | t2LDRB_POST_t2LDRB_PRE_t2LDRH_POST_t2LDRH_PRE = 409, |
| 4975 | t2LDR_POST_t2LDR_PRE = 410, |
| 4976 | t2LDRBT_t2LDRHT = 411, |
| 4977 | t2LDRT = 412, |
| 4978 | t2LDRSB_POST_imm_t2LDRSB_PRE_imm_t2LDRSH_POST_imm_t2LDRSH_PRE_imm = 413, |
| 4979 | t2LDRSB_POST_t2LDRSB_PRE_t2LDRSH_POST_t2LDRSH_PRE = 414, |
| 4980 | t2LDRSBT_t2LDRSHT = 415, |
| 4981 | t2LDRDi8 = 416, |
| 4982 | LDRD = 417, |
| 4983 | LDRD_POST_LDRD_PRE = 418, |
| 4984 | t2LDRD_POST_t2LDRD_PRE = 419, |
| 4985 | LDMDA_LDMDB_LDMIA_LDMIB_t2LDMDB_t2LDMIA_sysLDMDA_sysLDMDB_sysLDMIA_sysLDMIB_tLDMIA = 420, |
| 4986 | LDMDA_UPD_LDMDB_UPD_LDMIA_UPD_LDMIB_UPD_tLDMIA_UPD_sysLDMDA_UPD_sysLDMDB_UPD_sysLDMIA_UPD_sysLDMIB_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 421, |
| 4987 | LDMIA_RET_t2LDMIA_RET = 422, |
| 4988 | tPOP_RET = 423, |
| 4989 | tPOP = 424, |
| 4990 | PICSTR_STRi12 = 425, |
| 4991 | PICSTRB_PICSTRH_STRBi12_STRH = 426, |
| 4992 | STRrs = 427, |
| 4993 | STRBrs = 428, |
| 4994 | STREX_STREXB_STREXD_STREXH = 429, |
| 4995 | t2STRi12_t2STRi8_tSTRi_tSTRspi = 430, |
| 4996 | t2STRs = 431, |
| 4997 | t2STRBi12_t2STRBi8_t2STRHi12_t2STRHi8_tSTRBi_tSTRHi = 432, |
| 4998 | t2STRBs_t2STRHs = 433, |
| 4999 | tSTRBr_tSTRHr = 434, |
| 5000 | tSTRr = 435, |
| 5001 | STRBT_POST_IMM_STRBT_POST_REG_STRB_POST_REG_STRB_PRE_REG_STRH_POST_STRH_PRE_STRHTi_STRHTr = 436, |
| 5002 | STRB_POST_IMM_STRB_PRE_IMM = 437, |
| 5003 | STRT_POST_IMM_STRT_POST_REG_STR_POST_REG_STR_PRE_REG_STRi_preidx_STRr_preidx_STRBi_preidx_STRBr_preidx_STRH_preidx = 438, |
| 5004 | STR_POST_IMM_STR_PRE_IMM = 439, |
| 5005 | STRBT_POST_STRT_POST_t2STR_POST_imm_t2STR_PRE_imm_t2STRB_POST_imm_t2STRB_PRE_imm_t2STRH_POST_imm_t2STRH_PRE_imm = 440, |
| 5006 | t2STR_POST_t2STR_PRE_t2STRH_PRE = 441, |
| 5007 | t2STRB_POST_t2STRB_PRE_t2STRH_POST = 442, |
| 5008 | t2STR_preidx_t2STRB_preidx_t2STRH_preidx = 443, |
| 5009 | t2STRBT_t2STRHT = 444, |
| 5010 | t2STRT = 445, |
| 5011 | STRD = 446, |
| 5012 | t2STRDi8 = 447, |
| 5013 | t2STRD_POST_t2STRD_PRE = 448, |
| 5014 | STRD_POST_STRD_PRE = 449, |
| 5015 | STMDA_STMDB_STMIA_STMIB_sysSTMDA_sysSTMDB_sysSTMIA_sysSTMIB_t2STMDB_t2STMIA = 450, |
| 5016 | STMDA_UPD_STMDB_UPD_STMIA_UPD_STMIB_UPD_sysSTMDA_UPD_sysSTMDB_UPD_sysSTMIA_UPD_sysSTMIB_UPD_t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 451, |
| 5017 | tPUSH = 452, |
| 5018 | LDRLIT_ga_abs_tLDRLIT_ga_abs = 453, |
| 5019 | LDRLIT_ga_pcrel_tLDRLIT_ga_pcrel = 454, |
| 5020 | LDRLIT_ga_pcrel_ldr = 455, |
| 5021 | t2IT = 456, |
| 5022 | ITasm = 457, |
| 5023 | VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16_VANDq_VBICq_VEORq_VORNq_VORRq_VBIFq_VBITq_VBSLq_VBSPq = 458, |
| 5024 | VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8_VANDd_VBICd_VEORd_VORNd_VORRd_VBIFd_VBITd_VBSLd_VBSPd = 459, |
| 5025 | VSUBv16i8_VSUBv2i64_VSUBv4i32_VSUBv8i16 = 460, |
| 5026 | VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8_VADDWsv2i64_VADDWsv4i32_VADDWsv8i16_VADDWuv2i64_VADDWuv4i32_VADDWuv8i16_VSUBWsv2i64_VSUBWsv4i32_VSUBWsv8i16_VSUBWuv2i64_VSUBWuv4i32_VSUBWuv8i16 = 461, |
| 5027 | VNEGf32q = 462, |
| 5028 | VNEGfd = 463, |
| 5029 | VNEGs16d_VNEGs32d_VNEGs8d_VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16_VPADDi16_VPADDi32_VPADDi8_VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLsv1i64_VSHLsv2i32_VSHLsv4i16_VSHLsv8i8_VSHLuv1i64_VSHLuv2i32_VSHLuv4i16_VSHLuv8i8_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8_VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 464, |
| 5030 | VNEGs16q_VNEGs32q_VNEGs8q_VSHLsv16i8_VSHLsv2i64_VSHLsv4i32_VSHLsv8i16_VSHLuv16i8_VSHLuv2i64_VSHLuv4i32_VSHLuv8i16_VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 465, |
| 5031 | VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16_VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16_VTSTv16i8_VTSTv4i32_VTSTv8i16 = 466, |
| 5032 | VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8_VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8_VTSTv2i32_VTSTv4i16_VTSTv8i8 = 467, |
| 5033 | VHSUBsv16i8_VHSUBsv4i32_VHSUBsv8i16_VHSUBuv16i8_VHSUBuv4i32_VHSUBuv8i16 = 468, |
| 5034 | VHSUBsv2i32_VHSUBsv4i16_VHSUBsv8i8_VHSUBuv2i32_VHSUBuv4i16_VHSUBuv8i8 = 469, |
| 5035 | VBICiv2i32_VBICiv4i16_VBICiv4i32_VBICiv8i16_VORRiv2i32_VORRiv4i16_VORRiv4i32_VORRiv8i16 = 470, |
| 5036 | VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLsv1i64_VQSHLsv2i32_VQSHLsv4i16_VQSHLsv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8_VQSHLuv1i64_VQSHLuv2i32_VQSHLuv4i16_VQSHLuv8i8 = 471, |
| 5037 | VQSHLsv16i8_VQSHLsv2i64_VQSHLsv4i32_VQSHLsv8i16_VQSHLuv16i8_VQSHLuv2i64_VQSHLuv4i32_VQSHLuv8i16 = 472, |
| 5038 | VCLSv16i8_VCLSv4i32_VCLSv8i16_VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 473, |
| 5039 | VCLSv2i32_VCLSv4i16_VCLSv8i8_VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 474, |
| 5040 | VEXTd16_VEXTd32_VEXTd8 = 475, |
| 5041 | VEXTq16_VEXTq32_VEXTq64_VEXTq8 = 476, |
| 5042 | VREV16d8_VREV32d16_VREV32d8_VREV64d16_VREV64d32_VREV64d8 = 477, |
| 5043 | VREV16q8_VREV32q16_VREV32q8_VREV64q16_VREV64q32_VREV64q8 = 478, |
| 5044 | VABALsv2i64_VABALsv4i32_VABALsv8i16_VABALuv2i64_VABALuv4i32_VABALuv8i16_VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 479, |
| 5045 | VABAsv16i8_VABAsv4i32_VABAsv8i16_VABAuv16i8_VABAuv4i32_VABAuv8i16 = 480, |
| 5046 | VPADALsv16i8_VPADALsv4i32_VPADALsv8i16_VPADALuv16i8_VPADALuv4i32_VPADALuv8i16 = 481, |
| 5047 | VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8_VRSRAsv16i8_VRSRAsv1i64_VRSRAsv2i32_VRSRAsv2i64_VRSRAsv4i16_VRSRAsv4i32_VRSRAsv8i16_VRSRAsv8i8_VRSRAuv16i8_VRSRAuv1i64_VRSRAuv2i32_VRSRAuv2i64_VRSRAuv4i16_VRSRAuv4i32_VRSRAuv8i16_VRSRAuv8i8_VSRAsv16i8_VSRAsv1i64_VSRAsv2i32_VSRAsv2i64_VSRAsv4i16_VSRAsv4i32_VSRAsv8i16_VSRAsv8i8_VSRAuv16i8_VSRAuv1i64_VSRAuv2i32_VSRAuv2i64_VSRAuv4i16_VSRAuv4i32_VSRAuv8i16_VSRAuv8i8 = 482, |
| 5048 | VACGEfd_VACGEhd_VACGTfd_VACGThd_VCEQfd_VCEQhd_VCGEfd_VCGEhd_VCGTfd_VCGThd = 483, |
| 5049 | VACGEfq_VACGEhq_VACGTfq_VACGThq_VCEQfq_VCEQhq_VCGEfq_VCGEhq_VCGTfq_VCGThq = 484, |
| 5050 | VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16_VQSUBsv16i8_VQSUBsv2i64_VQSUBsv4i32_VQSUBsv8i16_VQSUBuv16i8_VQSUBuv2i64_VQSUBuv4i32_VQSUBuv8i16 = 485, |
| 5051 | VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8_VQSUBsv1i64_VQSUBsv2i32_VQSUBsv4i16_VQSUBsv8i8_VQSUBuv1i64_VQSUBuv2i32_VQSUBuv4i16_VQSUBuv8i8 = 486, |
| 5052 | VCEQzv16i8_VCEQzv2f32_VCEQzv2i32_VCEQzv4f16_VCEQzv4f32_VCEQzv4i16_VCEQzv4i32_VCEQzv8f16_VCEQzv8i16_VCEQzv8i8_VCGEzv16i8_VCGEzv2f32_VCGEzv2i32_VCGEzv4f16_VCGEzv4f32_VCGEzv4i16_VCGEzv4i32_VCGEzv8f16_VCGEzv8i16_VCGEzv8i8_VCGTzv16i8_VCGTzv2f32_VCGTzv2i32_VCGTzv4f16_VCGTzv4f32_VCGTzv4i16_VCGTzv4i32_VCGTzv8f16_VCGTzv8i16_VCGTzv8i8_VCLEzv16i8_VCLEzv2f32_VCLEzv2i32_VCLEzv4f16_VCLEzv4f32_VCLEzv4i16_VCLEzv4i32_VCLEzv8f16_VCLEzv8i16_VCLEzv8i8_VCLTzv16i8_VCLTzv2f32_VCLTzv2i32_VCLTzv4f16_VCLTzv4f32_VCLTzv4i16_VCLTzv4i32_VCLTzv8f16_VCLTzv8i16_VCLTzv8i8 = 487, |
| 5053 | VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16_VQRSHLsv16i8_VQRSHLsv2i64_VQRSHLsv4i32_VQRSHLsv8i16_VQRSHLuv16i8_VQRSHLuv2i64_VQRSHLuv4i32_VQRSHLuv8i16 = 488, |
| 5054 | VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VQRSHLsv1i64_VQRSHLsv2i32_VQRSHLsv4i16_VQRSHLsv8i8_VQRSHLuv1i64_VQRSHLuv2i32_VQRSHLuv4i16_VQRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 489, |
| 5055 | VABSfd = 490, |
| 5056 | VABSfq = 491, |
| 5057 | VABSv16i8_VABSv4i32_VABSv8i16 = 492, |
| 5058 | VABSv2i32_VABSv4i16_VABSv8i8 = 493, |
| 5059 | VQABSv16i8_VQABSv4i32_VQABSv8i16_VQNEGv16i8_VQNEGv4i32_VQNEGv8i16 = 494, |
| 5060 | VQABSv2i32_VQABSv4i16_VQABSv8i8_VQNEGv2i32_VQNEGv4i16_VQNEGv8i8 = 495, |
| 5061 | VQADDsv16i8_VQADDsv2i64_VQADDsv4i32_VQADDsv8i16_VQADDuv16i8_VQADDuv2i64_VQADDuv4i32_VQADDuv8i16 = 496, |
| 5062 | VQADDsv1i64_VQADDsv2i32_VQADDsv4i16_VQADDsv8i8_VQADDuv1i64_VQADDuv2i32_VQADDuv4i16_VQADDuv8i8 = 497, |
| 5063 | VRECPEd_VRECPEfd_VRECPEhd_VRSQRTEd_VRSQRTEfd_VRSQRTEhd = 498, |
| 5064 | VRECPEfq_VRECPEhq_VRECPEq_VRSQRTEfq_VRSQRTEhq_VRSQRTEq = 499, |
| 5065 | VADDHNv2i32_VADDHNv4i16_VADDHNv8i8_VSUBHNv2i32_VSUBHNv4i16_VSUBHNv8i8 = 500, |
| 5066 | VSHRNv2i32_VSHRNv4i16_VSHRNv8i8 = 501, |
| 5067 | VRADDHNv2i32_VRADDHNv4i16_VRADDHNv8i8_VRSUBHNv2i32_VRSUBHNv4i16_VRSUBHNv8i8 = 502, |
| 5068 | VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8_VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8_VQSHRUNv2i32_VQSHRUNv4i16_VQSHRUNv8i8_VQRSHRNsv2i32_VQRSHRNsv4i16_VQRSHRNsv8i8_VQRSHRNuv2i32_VQRSHRNuv4i16_VQRSHRNuv8i8_VQRSHRUNv2i32_VQRSHRUNv4i16_VQRSHRUNv8i8 = 503, |
| 5069 | VTBL1 = 504, |
| 5070 | VTBX1 = 505, |
| 5071 | VTBL2 = 506, |
| 5072 | VTBX2 = 507, |
| 5073 | VTBL3_VTBL3Pseudo = 508, |
| 5074 | VTBX3_VTBX3Pseudo = 509, |
| 5075 | VTBL4_VTBL4Pseudo = 510, |
| 5076 | VTBX4_VTBX4Pseudo = 511, |
| 5077 | VSWPd_VSWPq = 512, |
| 5078 | VTRNd16_VTRNd32_VTRNd8_VUZPd16_VUZPd8_VZIPd16_VZIPd8 = 513, |
| 5079 | VTRNq16_VTRNq32_VTRNq8 = 514, |
| 5080 | VUZPq16_VUZPq32_VUZPq8_VZIPq16_VZIPq32_VZIPq8 = 515, |
| 5081 | VABSD_VNEGD = 516, |
| 5082 | VABSS_VNEGS = 517, |
| 5083 | VCMPD_VCMPZD_VCMPED_VCMPEZD = 518, |
| 5084 | VCMPS_VCMPZS_VCMPES_VCMPEZS = 519, |
| 5085 | VADDS_VSUBS = 520, |
| 5086 | VADDfd_VSUBfd_VABDfd_VABDhd_VMAXfd_VMAXhd_VMINfd_VMINhd = 521, |
| 5087 | VADDfq_VSUBfq_VABDfq_VABDhq_VMAXfq_VMAXhq_VMINfq_VMINhq = 522, |
| 5088 | VABDLsv2i64_VABDLsv4i32_VABDLsv8i16_VABDLuv2i64_VABDLuv4i32_VABDLuv8i16_VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16_VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 523, |
| 5089 | VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8_VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8_VPMAXs16_VPMAXs32_VPMAXs8_VPMAXu16_VPMAXu32_VPMAXu8_VPMINs16_VPMINs32_VPMINs8_VPMINu16_VPMINu32_VPMINu8 = 524, |
| 5090 | VPADDf_VPMAXf_VPMAXh_VPMINf_VPMINh = 525, |
| 5091 | VADDD_VSUBD = 526, |
| 5092 | VRECPSfd_VRECPShd_VRSQRTSfd_VRSQRTShd = 527, |
| 5093 | VRECPSfq_VRECPShq_VRSQRTSfq_VRSQRTShq = 528, |
| 5094 | VMULS_VNMULS = 529, |
| 5095 | VMULfd = 530, |
| 5096 | VMULfq = 531, |
| 5097 | VMULpd_VMULslhd_VMULslv4i16_VMULv4i16_VMULv8i8_VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16_VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32 = 532, |
| 5098 | VMULpq_VMULslhq_VMULslv8i16_VMULv16i8_VMULv8i16_VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 533, |
| 5099 | VMULslfd = 534, |
| 5100 | VMULslfq = 535, |
| 5101 | VMULslv2i32_VMULv2i32_VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32_VMULLsv2i64_VMULLuv2i64_VQDMULLv2i64 = 536, |
| 5102 | VMULslv4i32_VMULv4i32_VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 537, |
| 5103 | VMULLp64 = 538, |
| 5104 | VMLAD_VMLSD_VNMLAD_VNMLSD = 539, |
| 5105 | VMLAH_VMLSH_VNMLAH_VNMLSH = 540, |
| 5106 | VMLALslsv2i32_VMLALsluv2i32_VMLALsv2i64_VMLALuv2i64_VMLAslv2i32_VMLAv2i32_VMLSLslsv2i32_VMLSLsluv2i32_VMLSLsv2i64_VMLSLuv2i64_VMLSslv2i32_VMLSv2i32_VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 541, |
| 5107 | VMLALslsv4i16_VMLALsluv4i16_VMLALsv4i32_VMLALsv8i16_VMLALuv4i32_VMLALuv8i16_VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSLslsv4i16_VMLSLsluv4i16_VMLSLsv4i32_VMLSLsv8i16_VMLSLuv4i32_VMLSLuv8i16_VMLSslv4i16_VMLSv4i16_VMLSv8i8_VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 542, |
| 5108 | VMLAS_VMLSS_VNMLAS_VNMLSS = 543, |
| 5109 | VMLAfd_VMLAhd_VMLAslfd_VMLAslhd_VMLSfd_VMLShd_VMLSslfd_VMLSslhd = 544, |
| 5110 | VMLAfq_VMLAhq_VMLAslfq_VMLAslhq_VMLSfq_VMLShq_VMLSslfq_VMLSslhq = 545, |
| 5111 | VMLAslv4i32_VMLAv4i32_VMLSslv4i32_VMLSv4i32 = 546, |
| 5112 | VMLAslv8i16_VMLAv16i8_VMLAv8i16_VMLSslv8i16_VMLSv16i8_VMLSv8i16 = 547, |
| 5113 | VFMAD_VFMSD_VFNMAD_VFNMSD = 548, |
| 5114 | VFMAS_VFMSS_VFNMAS_VFNMSS = 549, |
| 5115 | VFNMAH_VFNMSH = 550, |
| 5116 | VFMAfd_VFMSfd = 551, |
| 5117 | VFMAfq_VFMSfq = 552, |
| 5118 | VCVTANSDf_VCVTANSDh_VCVTANSQf_VCVTANSQh_VCVTANUDf_VCVTANUDh_VCVTANUQf_VCVTANUQh_VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTBDH_VCVTMNSDf_VCVTMNSDh_VCVTMNSQf_VCVTMNSQh_VCVTMNUDf_VCVTMNUDh_VCVTMNUQf_VCVTMNUQh_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNNSDf_VCVTNNSDh_VCVTNNSQf_VCVTNNSQh_VCVTNNUDf_VCVTNNUDh_VCVTNNUQf_VCVTNNUQh_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPNSDf_VCVTPNSDh_VCVTPNSQf_VCVTPNSQh_VCVTPNUDf_VCVTPNUDh_VCVTPNUQf_VCVTPNUQh_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTTDH_VCVTTHD = 553, |
| 5119 | VCVTBHD = 554, |
| 5120 | VCVTBHS_VCVTTHS = 555, |
| 5121 | VCVTBSH_VCVTTSH = 556, |
| 5122 | VCVTDS = 557, |
| 5123 | VCVTSD = 558, |
| 5124 | VCVTf2h_VCVTf2sq_VCVTf2uq_VCVTf2xsq_VCVTf2xuq_VCVTh2f_VCVTh2sq_VCVTh2uq_VCVTh2xsq_VCVTh2xuq_VCVTs2fq_VCVTs2hq_VCVTu2fq_VCVTu2hq_VCVTxs2fq_VCVTxs2hq_VCVTxu2fq_VCVTxu2hq = 559, |
| 5125 | VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTh2sd_VCVTh2ud_VCVTh2xsd_VCVTh2xud_VCVTs2fd_VCVTs2hd_VCVTu2fd_VCVTu2hd_VCVTxs2fd_VCVTxs2hd_VCVTxu2fd_VCVTxu2hd = 560, |
| 5126 | VSITOD_VUITOD = 561, |
| 5127 | VSITOH_VUITOH = 562, |
| 5128 | VSITOS_VUITOS = 563, |
| 5129 | VTOSHD_VTOSIRD_VTOSIZD_VTOSLD_VTOUHD_VTOUIRD_VTOUIZD_VTOULD = 564, |
| 5130 | VTOSHH_VTOSIRH_VTOSIZH_VTOSLH_VTOUHH_VTOUIRH_VTOUIZH_VTOULH = 565, |
| 5131 | VTOSHS_VTOSIRS_VTOSIZS_VTOSLS_VTOUHS_VTOUIRS_VTOUIZS_VTOULS = 566, |
| 5132 | VMOVv16i8_VMOVv1i64_VMOVv2f32_VMOVv2i32_VMOVv2i64_VMOVv4f32_VMOVv4i16_VMOVv4i32_VMOVv8i16_VMOVv8i8_VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 567, |
| 5133 | VMOVD_VMOVDcc_FCONSTD = 568, |
| 5134 | VMOVS_VMOVScc_FCONSTS = 569, |
| 5135 | VMVNd_VMVNq = 570, |
| 5136 | VMOVNv2i32_VMOVNv4i16_VMOVNv8i8 = 571, |
| 5137 | VMOVLsv2i64_VMOVLsv4i32_VMOVLsv8i16_VMOVLuv2i64_VMOVLuv4i32_VMOVLuv8i16 = 572, |
| 5138 | VQMOVNsuv2i32_VQMOVNsuv4i16_VQMOVNsuv8i8_VQMOVNsv2i32_VQMOVNsv4i16_VQMOVNsv8i8_VQMOVNuv2i32_VQMOVNuv4i16_VQMOVNuv8i8 = 573, |
| 5139 | VDUPLN16d_VDUPLN32d_VDUPLN8d = 574, |
| 5140 | VDUPLN16q_VDUPLN32q_VDUPLN8q = 575, |
| 5141 | VDUP16d_VDUP16q_VDUP32d_VDUP32q_VDUP8d_VDUP8q = 576, |
| 5142 | VMOVRS = 577, |
| 5143 | VMOVSR = 578, |
| 5144 | VSETLNi16_VSETLNi32_VSETLNi8 = 579, |
| 5145 | VMOVRRD_VMOVRRS = 580, |
| 5146 | VMOVDRR = 581, |
| 5147 | VMOVSRR = 582, |
| 5148 | VGETLNi32_VGETLNu16_VGETLNu8 = 583, |
| 5149 | VGETLNs16_VGETLNs8 = 584, |
| 5150 | VMRS_VMRS_FPCXTNS_VMRS_FPCXTS_VMRS_FPEXC_VMRS_FPINST_VMRS_FPINST2_VMRS_FPSCR_NZCVQC_VMRS_FPSID_VMRS_MVFR0_VMRS_MVFR1_VMRS_MVFR2_VMRS_P0_VMRS_VPR = 585, |
| 5151 | VMSR_VMSR_FPCXTNS_VMSR_FPCXTS_VMSR_FPEXC_VMSR_FPINST_VMSR_FPINST2_VMSR_FPSCR_NZCVQC_VMSR_FPSID_VMSR_P0_VMSR_VPR = 586, |
| 5152 | FMSTAT = 587, |
| 5153 | VLDRD = 588, |
| 5154 | VLDRS = 589, |
| 5155 | VSTRD = 590, |
| 5156 | VSTRS = 591, |
| 5157 | VLDMQIA = 592, |
| 5158 | VSTMQIA = 593, |
| 5159 | VLDMDIA_VLDMSIA = 594, |
| 5160 | VLDMDDB_UPD_VLDMDIA_UPD_VLDMSDB_UPD_VLDMSIA_UPD = 595, |
| 5161 | VSTMDIA_VSTMSIA = 596, |
| 5162 | VSTMDDB_UPD_VSTMDIA_UPD_VSTMSDB_UPD_VSTMSIA_UPD = 597, |
| 5163 | VLD1d16_VLD1d32_VLD1d64_VLD1d8 = 598, |
| 5164 | VLD1q16_VLD1q32_VLD1q64_VLD1q8 = 599, |
| 5165 | VLD1d16wb_fixed_VLD1d16wb_register_VLD1d32wb_fixed_VLD1d32wb_register_VLD1d64wb_fixed_VLD1d64wb_register_VLD1d8wb_fixed_VLD1d8wb_register = 600, |
| 5166 | VLD1q16wb_fixed_VLD1q16wb_register_VLD1q32wb_fixed_VLD1q32wb_register_VLD1q64wb_fixed_VLD1q64wb_register_VLD1q8wb_fixed_VLD1q8wb_register = 601, |
| 5167 | VLD1d16T_VLD1d32T_VLD1d64T_VLD1d8T_VLD1d64TPseudo_VLD1d64TPseudoWB_fixed_VLD1d64TPseudoWB_register = 602, |
| 5168 | VLD1d16Twb_fixed_VLD1d16Twb_register_VLD1d32Twb_fixed_VLD1d32Twb_register_VLD1d64Twb_fixed_VLD1d64Twb_register_VLD1d8Twb_fixed_VLD1d8Twb_register = 603, |
| 5169 | VLD1d16Q_VLD1d32Q_VLD1d64Q_VLD1d8Q_VLD1d64QPseudo_VLD1d64QPseudoWB_fixed_VLD1d64QPseudoWB_register = 604, |
| 5170 | VLD1d16Qwb_fixed_VLD1d16Qwb_register_VLD1d32Qwb_fixed_VLD1d32Qwb_register_VLD1d64Qwb_fixed_VLD1d64Qwb_register_VLD1d8Qwb_fixed_VLD1d8Qwb_register = 605, |
| 5171 | VLD2b16_VLD2b32_VLD2b8_VLD2d16_VLD2d32_VLD2d8 = 606, |
| 5172 | VLD2q16_VLD2q32_VLD2q8_VLD2q16Pseudo_VLD2q32Pseudo_VLD2q8Pseudo = 607, |
| 5173 | VLD2b16wb_fixed_VLD2b16wb_register_VLD2b32wb_fixed_VLD2b32wb_register_VLD2b8wb_fixed_VLD2b8wb_register_VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 608, |
| 5174 | VLD2q16wb_fixed_VLD2q16wb_register_VLD2q32wb_fixed_VLD2q32wb_register_VLD2q8wb_fixed_VLD2q8wb_register_VLD2q16PseudoWB_fixed_VLD2q16PseudoWB_register_VLD2q32PseudoWB_fixed_VLD2q32PseudoWB_register_VLD2q8PseudoWB_fixed_VLD2q8PseudoWB_register = 609, |
| 5175 | VLD3d16_VLD3d32_VLD3d8_VLD3q16_VLD3q32_VLD3q8 = 610, |
| 5176 | VLD3d16Pseudo_VLD3d32Pseudo_VLD3d8Pseudo_VLD3q16oddPseudo_VLD3q32oddPseudo_VLD3q8oddPseudo = 611, |
| 5177 | VLD3d16_UPD_VLD3d32_UPD_VLD3d8_UPD_VLD3q16_UPD_VLD3q32_UPD_VLD3q8_UPD = 612, |
| 5178 | VLD3d16Pseudo_UPD_VLD3d32Pseudo_UPD_VLD3d8Pseudo_UPD_VLD3q16Pseudo_UPD_VLD3q16oddPseudo_UPD_VLD3q32Pseudo_UPD_VLD3q32oddPseudo_UPD_VLD3q8Pseudo_UPD_VLD3q8oddPseudo_UPD = 613, |
| 5179 | VLD4d16_VLD4d32_VLD4d8_VLD4q16_VLD4q32_VLD4q8 = 614, |
| 5180 | VLD4d16Pseudo_VLD4d32Pseudo_VLD4d8Pseudo_VLD4q16oddPseudo_VLD4q32oddPseudo_VLD4q8oddPseudo = 615, |
| 5181 | VLD4d16_UPD_VLD4d32_UPD_VLD4d8_UPD_VLD4q16_UPD_VLD4q32_UPD_VLD4q8_UPD = 616, |
| 5182 | VLD4d16Pseudo_UPD_VLD4d32Pseudo_UPD_VLD4d8Pseudo_UPD_VLD4q16Pseudo_UPD_VLD4q16oddPseudo_UPD_VLD4q32Pseudo_UPD_VLD4q32oddPseudo_UPD_VLD4q8Pseudo_UPD_VLD4q8oddPseudo_UPD = 617, |
| 5183 | VLD1DUPd16_VLD1DUPd32_VLD1DUPd8 = 618, |
| 5184 | VLD1DUPq16_VLD1DUPq32_VLD1DUPq8 = 619, |
| 5185 | VLD1LNd16_VLD1LNd8 = 620, |
| 5186 | VLD1LNd32_VLD1LNq16Pseudo_VLD1LNq32Pseudo_VLD1LNq8Pseudo = 621, |
| 5187 | VLD1DUPd16wb_fixed_VLD1DUPd16wb_register_VLD1DUPd32wb_fixed_VLD1DUPd32wb_register_VLD1DUPd8wb_fixed_VLD1DUPd8wb_register_VLD1DUPq16wb_register_VLD1DUPq32wb_register_VLD1DUPq8wb_register = 622, |
| 5188 | VLD1DUPq16wb_fixed_VLD1DUPq32wb_fixed_VLD1DUPq8wb_fixed = 623, |
| 5189 | VLD1LNd16_UPD_VLD1LNd32_UPD_VLD1LNd8_UPD_VLD1LNq16Pseudo_UPD_VLD1LNq32Pseudo_UPD_VLD1LNq8Pseudo_UPD = 624, |
| 5190 | VLD2DUPd16_VLD2DUPd16x2_VLD2DUPd32_VLD2DUPd32x2_VLD2DUPd8_VLD2DUPd8x2 = 625, |
| 5191 | VLD2LNd16_VLD2LNd32_VLD2LNd8_VLD2LNq16_VLD2LNq32_VLD2LNd16Pseudo_VLD2LNd32Pseudo_VLD2LNd8Pseudo_VLD2LNq16Pseudo_VLD2LNq32Pseudo = 626, |
| 5192 | VLD2LNd16_UPD_VLD2LNd32_UPD_VLD2LNd8_UPD_VLD2LNq16_UPD_VLD2LNq32_UPD = 627, |
| 5193 | VLD2DUPd16wb_fixed_VLD2DUPd16wb_register_VLD2DUPd16x2wb_fixed_VLD2DUPd16x2wb_register_VLD2DUPd32wb_fixed_VLD2DUPd32wb_register_VLD2DUPd32x2wb_fixed_VLD2DUPd32x2wb_register_VLD2DUPd8wb_fixed_VLD2DUPd8wb_register_VLD2DUPd8x2wb_fixed_VLD2DUPd8x2wb_register = 628, |
| 5194 | VLD2LNd16Pseudo_UPD_VLD2LNd32Pseudo_UPD_VLD2LNd8Pseudo_UPD_VLD2LNq16Pseudo_UPD_VLD2LNq32Pseudo_UPD = 629, |
| 5195 | VLD3DUPd16_VLD3DUPd32_VLD3DUPd8_VLD3DUPq16_VLD3DUPq32_VLD3DUPq8_VLD3DUPd16Pseudo_VLD3DUPd32Pseudo_VLD3DUPd8Pseudo = 630, |
| 5196 | VLD3LNd16_VLD3LNd32_VLD3LNd8_VLD3LNq16_VLD3LNq32_VLD3LNd16Pseudo_VLD3LNd32Pseudo_VLD3LNd8Pseudo_VLD3LNq16Pseudo_VLD3LNq32Pseudo = 631, |
| 5197 | VLD3DUPd16_UPD_VLD3DUPd32_UPD_VLD3DUPd8_UPD_VLD3DUPq16_UPD_VLD3DUPq32_UPD_VLD3DUPq8_UPD = 632, |
| 5198 | VLD3LNd16_UPD_VLD3LNd32_UPD_VLD3LNd8_UPD_VLD3LNq16_UPD_VLD3LNq32_UPD = 633, |
| 5199 | VLD3DUPd16Pseudo_UPD_VLD3DUPd32Pseudo_UPD_VLD3DUPd8Pseudo_UPD = 634, |
| 5200 | VLD3LNd16Pseudo_UPD_VLD3LNd32Pseudo_UPD_VLD3LNd8Pseudo_UPD_VLD3LNq16Pseudo_UPD_VLD3LNq32Pseudo_UPD = 635, |
| 5201 | VLD4DUPd16_VLD4DUPd32_VLD4DUPd8_VLD4DUPq16_VLD4DUPq32_VLD4DUPq8 = 636, |
| 5202 | VLD4LNd16_VLD4LNd32_VLD4LNd8_VLD4LNq16_VLD4LNq32_VLD4LNd16Pseudo_VLD4LNd32Pseudo_VLD4LNd8Pseudo_VLD4LNq16Pseudo_VLD4LNq32Pseudo = 637, |
| 5203 | VLD4DUPd16Pseudo_VLD4DUPd32Pseudo_VLD4DUPd8Pseudo = 638, |
| 5204 | VLD4DUPd16_UPD_VLD4DUPd32_UPD_VLD4DUPd8_UPD_VLD4DUPq16_UPD_VLD4DUPq32_UPD_VLD4DUPq8_UPD = 639, |
| 5205 | VLD4LNd16_UPD_VLD4LNd32_UPD_VLD4LNd8_UPD_VLD4LNq16_UPD_VLD4LNq32_UPD = 640, |
| 5206 | VLD4DUPd16Pseudo_UPD_VLD4DUPd32Pseudo_UPD_VLD4DUPd8Pseudo_UPD = 641, |
| 5207 | VLD4LNd16Pseudo_UPD_VLD4LNd32Pseudo_UPD_VLD4LNd8Pseudo_UPD_VLD4LNq16Pseudo_UPD_VLD4LNq32Pseudo_UPD = 642, |
| 5208 | VST1d16_VST1d32_VST1d64_VST1d8 = 643, |
| 5209 | VST1q16_VST1q32_VST1q64_VST1q8 = 644, |
| 5210 | VST1d16wb_fixed_VST1d16wb_register_VST1d32wb_fixed_VST1d32wb_register_VST1d64wb_fixed_VST1d64wb_register_VST1d8wb_fixed_VST1d8wb_register = 645, |
| 5211 | VST1q16wb_fixed_VST1q16wb_register_VST1q32wb_fixed_VST1q32wb_register_VST1q64wb_fixed_VST1q64wb_register_VST1q8wb_fixed_VST1q8wb_register = 646, |
| 5212 | VST1d16T_VST1d32T_VST1d64T_VST1d8T_VST1d64TPseudo = 647, |
| 5213 | VST1d16Twb_fixed_VST1d16Twb_register_VST1d32Twb_fixed_VST1d32Twb_register_VST1d64Twb_fixed_VST1d64Twb_register_VST1d8Twb_fixed_VST1d8Twb_register = 648, |
| 5214 | VST1d64TPseudoWB_fixed_VST1d64TPseudoWB_register = 649, |
| 5215 | VST1d16Q_VST1d16QPseudo_VST1d32Q_VST1d32QPseudo_VST1d64Q_VST1d64QPseudo_VST1d8Q_VST1d8QPseudo = 650, |
| 5216 | VST1d16QPseudoWB_fixed_VST1d16QPseudoWB_register_VST1d32QPseudoWB_fixed_VST1d32QPseudoWB_register_VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register_VST1d8QPseudoWB_fixed_VST1d8QPseudoWB_register = 651, |
| 5217 | VST1d16Qwb_fixed_VST1d16Qwb_register_VST1d32Qwb_fixed_VST1d32Qwb_register_VST1d64Qwb_fixed_VST1d64Qwb_register_VST1d8Qwb_fixed_VST1d8Qwb_register = 652, |
| 5218 | VST2b16_VST2b32_VST2b8 = 653, |
| 5219 | VST2d16_VST2d32_VST2d8 = 654, |
| 5220 | VST2b16wb_fixed_VST2b16wb_register_VST2b32wb_fixed_VST2b32wb_register_VST2b8wb_fixed_VST2b8wb_register_VST2d16wb_fixed_VST2d16wb_register_VST2d32wb_fixed_VST2d32wb_register_VST2d8wb_fixed_VST2d8wb_register = 655, |
| 5221 | VST2q16_VST2q32_VST2q8_VST2q16Pseudo_VST2q32Pseudo_VST2q8Pseudo = 656, |
| 5222 | VST2q16wb_fixed_VST2q16wb_register_VST2q32wb_fixed_VST2q32wb_register_VST2q8wb_fixed_VST2q8wb_register = 657, |
| 5223 | VST2q16PseudoWB_fixed_VST2q16PseudoWB_register_VST2q32PseudoWB_fixed_VST2q32PseudoWB_register_VST2q8PseudoWB_fixed_VST2q8PseudoWB_register = 658, |
| 5224 | VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8_VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo_VST3q16oddPseudo_VST3q32oddPseudo_VST3q8oddPseudo = 659, |
| 5225 | VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD_VST3d16Pseudo_UPD_VST3d32Pseudo_UPD_VST3d8Pseudo_UPD_VST3q16Pseudo_UPD_VST3q16oddPseudo_UPD_VST3q32Pseudo_UPD_VST3q32oddPseudo_UPD_VST3q8Pseudo_UPD_VST3q8oddPseudo_UPD = 660, |
| 5226 | VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8_VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo_VST4q16oddPseudo_VST4q32oddPseudo_VST4q8oddPseudo = 661, |
| 5227 | VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD_VST4d16Pseudo_UPD_VST4d32Pseudo_UPD_VST4d8Pseudo_UPD_VST4q16Pseudo_UPD_VST4q16oddPseudo_UPD_VST4q32Pseudo_UPD_VST4q32oddPseudo_UPD_VST4q8Pseudo_UPD_VST4q8oddPseudo_UPD = 662, |
| 5228 | VST1LNd16_VST1LNd32_VST1LNd8_VST1LNq16Pseudo_VST1LNq32Pseudo_VST1LNq8Pseudo = 663, |
| 5229 | VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD_VST1LNq16Pseudo_UPD_VST1LNq32Pseudo_UPD_VST1LNq8Pseudo_UPD = 664, |
| 5230 | VST2LNd16_VST2LNd32_VST2LNd8_VST2LNq16_VST2LNq32_VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo_VST2LNq16Pseudo_VST2LNq32Pseudo = 665, |
| 5231 | VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD_VST2LNq16_UPD_VST2LNq32_UPD = 666, |
| 5232 | VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD_VST2LNq16Pseudo_UPD_VST2LNq32Pseudo_UPD = 667, |
| 5233 | VST3LNd16_VST3LNd32_VST3LNd8_VST3LNq16_VST3LNq32_VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 668, |
| 5234 | VST3LNq16Pseudo_VST3LNq32Pseudo = 669, |
| 5235 | VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD_VST3LNq16_UPD_VST3LNq32_UPD = 670, |
| 5236 | VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD_VST3LNq16Pseudo_UPD_VST3LNq32Pseudo_UPD = 671, |
| 5237 | VST4LNd16_VST4LNd32_VST4LNd8_VST4LNq16_VST4LNq32_VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo_VST4LNq16Pseudo_VST4LNq32Pseudo = 672, |
| 5238 | VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD_VST4LNq16_UPD_VST4LNq32_UPD = 673, |
| 5239 | VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD_VST4LNq16Pseudo_UPD_VST4LNq32Pseudo_UPD = 674, |
| 5240 | VDIVS = 675, |
| 5241 | VSQRTS = 676, |
| 5242 | VDIVD = 677, |
| 5243 | VSQRTD = 678, |
| 5244 | COPY = 679, |
| 5245 | t2MOVCCi_t2MOVCCi16 = 680, |
| 5246 | t2MOVi_t2MOVi16 = 681, |
| 5247 | t2USAD8_t2USADA8 = 682, |
| 5248 | t2SDIV_t2UDIV = 683, |
| 5249 | t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH_t2LDA_t2LDAB_t2LDAEX_t2LDAEXB_t2LDAEXD_t2LDAEXH_t2LDAH = 684, |
| 5250 | LDA_LDAB_LDAEX_LDAEXB_LDAEXD_LDAEXH_LDAH = 685, |
| 5251 | LDRBT_POST = 686, |
| 5252 | MOVsr = 687, |
| 5253 | t2MOVSsr_t2MOVsr = 688, |
| 5254 | MOVTi16_ga_pcrel_MOVTi16_t2MOVTi16_ga_pcrel_t2MOVTi16 = 689, |
| 5255 | ADDSri_ADCri_ADDri_RSBSri_RSBri_RSCri_SBCri_t2ADDSri_t2ADCri_t2ADDri_t2ADDri12_t2RSBSri_t2RSBri_t2SBCri = 690, |
| 5256 | CLZ_t2CLZ = 691, |
| 5257 | t2ANDri_t2BICri_t2EORri_t2ORRri = 692, |
| 5258 | t2MVNCCi = 693, |
| 5259 | t2MVNi = 694, |
| 5260 | t2MVNr = 695, |
| 5261 | t2MVNs = 696, |
| 5262 | ADDSrr_ADCrr_ADDrr_RSBrr_RSCrr_SBCrr_t2ADDSrr_t2ADCrr_t2ADDrr_t2SBCrr = 697, |
| 5263 | CRC32B_CRC32CB_CRC32CH_CRC32CW_CRC32H_CRC32W_t2CRC32B_t2CRC32CB_t2CRC32CH_t2CRC32CW_t2CRC32H_t2CRC32W = 698, |
| 5264 | t2ANDrr_t2BICrr_t2EORrr = 699, |
| 5265 | ADDSrsi_ADCrsi_ADDrsi_RSBrsi_RSCrsi_SBCrsi = 700, |
| 5266 | t2ADDSrs = 701, |
| 5267 | t2ADCrs_t2ADDrs_t2SBCrs = 702, |
| 5268 | t2ANDrs_t2BICrs_t2EORrs_t2ORRrs = 703, |
| 5269 | t2RSBrs = 704, |
| 5270 | ADDSrsr = 705, |
| 5271 | ADCrsr_ADDrsr_RSBrsr_RSCrsr_SBCrsr = 706, |
| 5272 | ADR = 707, |
| 5273 | MVNi = 708, |
| 5274 | MVNsi = 709, |
| 5275 | t2MOVSsi_t2MOVsi = 710, |
| 5276 | ASRi_RORi = 711, |
| 5277 | ASRr_RORr_LSRi_LSRr_LSLi_LSLr = 712, |
| 5278 | LSRs1 = 713, |
| 5279 | CMPri_CMNri = 714, |
| 5280 | CMPrr_CMNrr = 715, |
| 5281 | CMPrsi_CMNrsi = 716, |
| 5282 | CMPrsr_CMNrsr = 717, |
| 5283 | t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE_RRXi = 718, |
| 5284 | RBIT_REV_REV16_REVSH = 719, |
| 5285 | RRX = 720, |
| 5286 | TSTri = 721, |
| 5287 | TSTrr = 722, |
| 5288 | TSTrsi = 723, |
| 5289 | TSTrsr = 724, |
| 5290 | MRS_MRSbanked_MRSsys = 725, |
| 5291 | MSR_MSRbanked_MSRi = 726, |
| 5292 | SRSDA_SRSDA_UPD_SRSDB_SRSDB_UPD_SRSIA_SRSIA_UPD_SRSIB_SRSIB_UPD_t2SRSDB_t2SRSDB_UPD_t2SRSIA_t2SRSIA_UPD_RFEDA_RFEDA_UPD_RFEDB_RFEDB_UPD_RFEIA_RFEIA_UPD_RFEIB_RFEIB_UPD_t2RFEDB_t2RFEDBW_t2RFEIA_t2RFEIAW = 727, |
| 5293 | t2STREX_t2STREXB_t2STREXD_t2STREXH = 728, |
| 5294 | STL_STLB_STLEX_STLEXB_STLEXD_STLEXH_STLH = 729, |
| 5295 | t2STL_t2STLB_t2STLEX_t2STLEXB_t2STLEXD_t2STLEXH_t2STLH = 730, |
| 5296 | VABDfd_VABDhd = 731, |
| 5297 | VABDfq_VABDhq = 732, |
| 5298 | VABSD = 733, |
| 5299 | VABSH = 734, |
| 5300 | VABSS = 735, |
| 5301 | VABShd = 736, |
| 5302 | VABShq = 737, |
| 5303 | VACGEfd_VACGEhd_VACGTfd_VACGThd = 738, |
| 5304 | VACGEfq_VACGEhq_VACGTfq_VACGThq = 739, |
| 5305 | VADDH_VSUBH = 740, |
| 5306 | VADDfd_VSUBfd = 741, |
| 5307 | VADDhd_VSUBhd = 742, |
| 5308 | VADDfq_VSUBfq = 743, |
| 5309 | VADDhq_VSUBhq = 744, |
| 5310 | VLDRH = 745, |
| 5311 | VLDR_FPCXTNS_off_VLDR_FPCXTNS_post_VLDR_FPCXTNS_pre_VLDR_FPCXTS_off_VLDR_FPCXTS_post_VLDR_FPCXTS_pre_VLDR_FPSCR_NZCVQC_off_VLDR_FPSCR_NZCVQC_post_VLDR_FPSCR_NZCVQC_pre_VLDR_FPSCR_off_VLDR_FPSCR_post_VLDR_FPSCR_pre_VLDR_P0_off_VLDR_P0_post_VLDR_P0_pre_VLDR_VPR_off_VLDR_VPR_post_VLDR_VPR_pre = 746, |
| 5312 | VSTRH = 747, |
| 5313 | VSTR_FPCXTNS_off_VSTR_FPCXTNS_post_VSTR_FPCXTNS_pre_VSTR_FPCXTS_off_VSTR_FPCXTS_post_VSTR_FPCXTS_pre_VSTR_FPSCR_NZCVQC_off_VSTR_FPSCR_NZCVQC_post_VSTR_FPSCR_NZCVQC_pre_VSTR_FPSCR_off_VSTR_FPSCR_post_VSTR_FPSCR_pre_VSTR_P0_off_VSTR_P0_post_VSTR_P0_pre_VSTR_VPR_off_VSTR_VPR_post_VSTR_VPR_pre = 748, |
| 5314 | VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 749, |
| 5315 | VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8 = 750, |
| 5316 | VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16 = 751, |
| 5317 | VABDLsv4i32_VABDLsv8i16_VABDLuv4i32_VABDLuv8i16 = 752, |
| 5318 | VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8 = 753, |
| 5319 | VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8 = 754, |
| 5320 | VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16 = 755, |
| 5321 | VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16 = 756, |
| 5322 | VANDd_VBICd_VEORd = 757, |
| 5323 | VANDq_VBICq_VEORq = 758, |
| 5324 | VBICiv2i32_VBICiv4i16 = 759, |
| 5325 | VBICiv4i32_VBICiv8i16 = 760, |
| 5326 | VBIFd_VBITd_VBSLd_VBSPd = 761, |
| 5327 | VBIFq_VBITq_VBSLq_VBSPq = 762, |
| 5328 | VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16 = 763, |
| 5329 | VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8 = 764, |
| 5330 | VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 765, |
| 5331 | VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 766, |
| 5332 | VCMPEH_VCMPEZH_VCMPH_VCMPZH = 767, |
| 5333 | VDUP16d_VDUP32d_VDUP8d = 768, |
| 5334 | VSELEQD_VSELEQH_VSELEQS_VSELGED_VSELGEH_VSELGES_VSELGTD_VSELGTH_VSELGTS_VSELVSD_VSELVSH_VSELVSS = 769, |
| 5335 | VFMAhd_VFMShd = 770, |
| 5336 | VFMAhq_VFMShq = 771, |
| 5337 | VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8 = 772, |
| 5338 | VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16 = 773, |
| 5339 | VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 774, |
| 5340 | VPMAXf_VPMAXh_VPMINf_VPMINh = 775, |
| 5341 | VNEGH = 776, |
| 5342 | VNEGhd = 777, |
| 5343 | VNEGhq = 778, |
| 5344 | VNEGs16d_VNEGs32d_VNEGs8d = 779, |
| 5345 | VNEGs16q_VNEGs32q_VNEGs8q = 780, |
| 5346 | VPADDi16_VPADDi32_VPADDi8 = 781, |
| 5347 | VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8 = 782, |
| 5348 | VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8 = 783, |
| 5349 | VQABSv2i32_VQABSv4i16_VQABSv8i8 = 784, |
| 5350 | VQABSv16i8_VQABSv4i32_VQABSv8i16 = 785, |
| 5351 | VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 786, |
| 5352 | VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 787, |
| 5353 | VQDMULHslv2i32_VQDMULHv2i32_VQDMULLv2i64_VQRDMULHslv2i32_VQRDMULHv2i32 = 788, |
| 5354 | VQDMULHslv4i16_VQDMULHv4i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32_VQRDMULHslv4i16_VQRDMULHv4i16 = 789, |
| 5355 | VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 790, |
| 5356 | VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 791, |
| 5357 | VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8 = 792, |
| 5358 | VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16 = 793, |
| 5359 | VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 794, |
| 5360 | VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8 = 795, |
| 5361 | VST1d16T_VST1d32T_VST1d64T_VST1d8T = 796, |
| 5362 | VST1d16Q_VST1d32Q_VST1d64Q_VST1d8Q = 797, |
| 5363 | VST1d64QPseudo = 798, |
| 5364 | VST1LNd16_VST1LNd32_VST1LNd8 = 799, |
| 5365 | VST1LNdAsm_16_VST1LNdAsm_32_VST1LNdAsm_8 = 800, |
| 5366 | VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register = 801, |
| 5367 | VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD = 802, |
| 5368 | VST1LNdWB_fixed_Asm_16_VST1LNdWB_fixed_Asm_32_VST1LNdWB_fixed_Asm_8_VST1LNdWB_register_Asm_16_VST1LNdWB_register_Asm_32_VST1LNdWB_register_Asm_8 = 803, |
| 5369 | VST2q16_VST2q32_VST2q8 = 804, |
| 5370 | VST2LNd16_VST2LNd32_VST2LNd8 = 805, |
| 5371 | VST2LNdAsm_16_VST2LNdAsm_32_VST2LNdAsm_8 = 806, |
| 5372 | VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo = 807, |
| 5373 | VST2LNq16_VST2LNq32 = 808, |
| 5374 | VST2LNqAsm_16_VST2LNqAsm_32 = 809, |
| 5375 | VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD = 810, |
| 5376 | VST2LNdWB_fixed_Asm_16_VST2LNdWB_fixed_Asm_32_VST2LNdWB_fixed_Asm_8_VST2LNdWB_register_Asm_16_VST2LNdWB_register_Asm_32_VST2LNdWB_register_Asm_8 = 811, |
| 5377 | VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD = 812, |
| 5378 | VST2LNqWB_fixed_Asm_16_VST2LNqWB_fixed_Asm_32_VST2LNqWB_register_Asm_16_VST2LNqWB_register_Asm_32 = 813, |
| 5379 | VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8 = 814, |
| 5380 | VST3dAsm_16_VST3dAsm_32_VST3dAsm_8_VST3qAsm_16_VST3qAsm_32_VST3qAsm_8 = 815, |
| 5381 | VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo = 816, |
| 5382 | VST3LNd16_VST3LNd32_VST3LNd8 = 817, |
| 5383 | VST3LNdAsm_16_VST3LNdAsm_32_VST3LNdAsm_8 = 818, |
| 5384 | VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 819, |
| 5385 | VST3LNqAsm_16_VST3LNqAsm_32 = 820, |
| 5386 | VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD = 821, |
| 5387 | VST3dWB_fixed_Asm_16_VST3dWB_fixed_Asm_32_VST3dWB_fixed_Asm_8_VST3dWB_register_Asm_16_VST3dWB_register_Asm_32_VST3dWB_register_Asm_8_VST3qWB_fixed_Asm_16_VST3qWB_fixed_Asm_32_VST3qWB_fixed_Asm_8_VST3qWB_register_Asm_16_VST3qWB_register_Asm_32_VST3qWB_register_Asm_8 = 822, |
| 5388 | VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD = 823, |
| 5389 | VST3LNdWB_fixed_Asm_16_VST3LNdWB_fixed_Asm_32_VST3LNdWB_fixed_Asm_8_VST3LNdWB_register_Asm_16_VST3LNdWB_register_Asm_32_VST3LNdWB_register_Asm_8 = 824, |
| 5390 | VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD = 825, |
| 5391 | VST3LNqWB_fixed_Asm_16_VST3LNqWB_fixed_Asm_32_VST3LNqWB_register_Asm_16_VST3LNqWB_register_Asm_32 = 826, |
| 5392 | VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8 = 827, |
| 5393 | VST4dAsm_16_VST4dAsm_32_VST4dAsm_8_VST4qAsm_16_VST4qAsm_32_VST4qAsm_8 = 828, |
| 5394 | VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo = 829, |
| 5395 | VST4LNd16_VST4LNd32_VST4LNd8 = 830, |
| 5396 | VST4LNdAsm_16_VST4LNdAsm_32_VST4LNdAsm_8 = 831, |
| 5397 | VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo = 832, |
| 5398 | VST4LNq16_VST4LNq32 = 833, |
| 5399 | VST4LNqAsm_16_VST4LNqAsm_32 = 834, |
| 5400 | VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD = 835, |
| 5401 | VST4dWB_fixed_Asm_16_VST4dWB_fixed_Asm_32_VST4dWB_fixed_Asm_8_VST4dWB_register_Asm_16_VST4dWB_register_Asm_32_VST4dWB_register_Asm_8_VST4qWB_fixed_Asm_16_VST4qWB_fixed_Asm_32_VST4qWB_fixed_Asm_8_VST4qWB_register_Asm_16_VST4qWB_register_Asm_32_VST4qWB_register_Asm_8 = 836, |
| 5402 | VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD = 837, |
| 5403 | VST4LNdWB_fixed_Asm_16_VST4LNdWB_fixed_Asm_32_VST4LNdWB_fixed_Asm_8_VST4LNdWB_register_Asm_16_VST4LNdWB_register_Asm_32_VST4LNdWB_register_Asm_8 = 838, |
| 5404 | VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD = 839, |
| 5405 | VST4LNqWB_fixed_Asm_16_VST4LNqWB_fixed_Asm_32_VST4LNqWB_register_Asm_16_VST4LNqWB_register_Asm_32 = 840, |
| 5406 | BKPT_tBKPT_CDP_CDP2_t2CDP_t2CDP2_CLREX_t2CLREX_CONSTPOOL_ENTRY_COPY_STRUCT_BYVAL_I32_CPS1p_CPS2p_CPS3p_t2CPS1p_t2CPS2p_t2CPS3p_DBG_t2DBG_DMB_t2DMB_DSB_t2DSB_ERET_HINT_t2HINT_tHINT_HLT_tHLT_HVC_ISB_t2ISB_SETEND_tSETEND_SETPAN_t2SETPAN_SMC_t2SMC_SPACE_SWP_SWPB_TRAP_UDF_t2DCPS1_t2DCPS2_t2DCPS3_t2SG_t2TT_t2TTA_t2TTAT_t2TTT_tCPS_CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 841, |
| 5407 | t2HVC_tTRAP_SVC_tSVC = 842, |
| 5408 | t2UDF_tUDF_t__brkdiv0 = 843, |
| 5409 | LDC2L_OFFSET_LDC2L_OPTION_LDC2L_POST_LDC2L_PRE_LDC2_OFFSET_LDC2_OPTION_LDC2_POST_LDC2_PRE_LDCL_OFFSET_LDCL_OPTION_LDCL_POST_LDCL_PRE_LDC_OFFSET_LDC_OPTION_LDC_POST_LDC_PRE_STC2L_OFFSET_STC2L_OPTION_STC2L_POST_STC2L_PRE_STC2_OFFSET_STC2_OPTION_STC2_POST_STC2_PRE_STCL_OFFSET_STCL_OPTION_STCL_POST_STCL_PRE_STC_OFFSET_STC_OPTION_STC_POST_STC_PRE_t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE_MEMCPY = 844, |
| 5410 | t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE = 845, |
| 5411 | LDREX_LDREXB_LDREXD_LDREXH = 846, |
| 5412 | MCR_MCR2_MCRR_MCRR2_t2MCR_t2MCR2_t2MCRR_t2MCRR2_MRC_MRC2_t2MRC_t2MRC2_MRRC_MRRC2_t2MRRC_t2MRRC2_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR_t2MSR_AR_t2MSR_M_t2MSRbanked = 847, |
| 5413 | FLDMXDB_UPD_FLDMXIA_FLDMXIA_UPD_FSTMXDB_UPD_FSTMXIA_FSTMXIA_UPD = 848, |
| 5414 | ADJCALLSTACKDOWN_tADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKUP_Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_t2SUBS_PC_LR_JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH_tInt_WIN_eh_sjlj_longjmp_VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8_WIN__CHKSTK_WIN__DBZCHK = 849, |
| 5415 | SUBS_PC_LR = 850, |
| 5416 | B_t2B_tB_BX_CALL_tBXNS_RET_tBX_CALL_tBX_RET_tBX_RET_vararg_BX_BX_RET_BX_pred_tBX_tBXNS_Bcc_t2Bcc_tBcc_TAILJMPd_TAILJMPr_TAILJMPr4_tTAILJMPd_tTAILJMPdND_tTAILJMPr_TCRETURNdi_TCRETURNri_TCRETURNrinotr12_tCBNZ_tCBZ = 851, |
| 5417 | BXJ = 852, |
| 5418 | tBfar = 853, |
| 5419 | BL_tBL_BL_pred_tBLXi = 854, |
| 5420 | BLXi = 855, |
| 5421 | TPsoft_tTPsoft = 856, |
| 5422 | BLX_noip_BLX_pred_noip_BLX_BLX_pred_tBLXr_noip_tBLXNSr_tBLXr = 857, |
| 5423 | BCCi64_BCCZi64 = 858, |
| 5424 | BR_JTadd_tBR_JTr_t2TBB_t2TBH = 859, |
| 5425 | BR_JTr_t2BR_JT_t2TBB_JT_t2TBH_JT_tBRIND = 860, |
| 5426 | t2BXJ = 861, |
| 5427 | BR_JTm_i12_BR_JTm_rs = 862, |
| 5428 | tADDframe = 863, |
| 5429 | MOVi16_ga_pcrel_MOVi_MOVi16_MOVCCi16_tMOVi8 = 864, |
| 5430 | MOVr_MOVr_TC_tMOVSr_tMOVr = 865, |
| 5431 | MVNCCi_MOVCCi = 866, |
| 5432 | BMOVPCB_CALL_BMOVPCRX_CALL = 867, |
| 5433 | MOVCCr = 868, |
| 5434 | tMOVCCr_pseudo_tMOVi32imm = 869, |
| 5435 | tMVN = 870, |
| 5436 | MOVCCsi = 871, |
| 5437 | t2ASRri_tASRri_t2LSRri_tLSRri_t2LSLri_tLSLri_t2RORri_t2RRX = 872, |
| 5438 | LSRi_LSLi = 873, |
| 5439 | t2MOVCCasr_t2MOVCClsl_t2MOVCClsr_t2MOVCCror = 874, |
| 5440 | t2MOVCCr = 875, |
| 5441 | t2MOVTi16_ga_pcrel_t2MOVTi16 = 876, |
| 5442 | t2MOVr = 877, |
| 5443 | tROR = 878, |
| 5444 | t2ASRrr_tASRrr_t2LSRrr_tLSRrr_t2LSLrr_tLSLrr_t2RORrr = 879, |
| 5445 | MOVPCRX_MOVPCLR = 880, |
| 5446 | tMUL = 881, |
| 5447 | SADD16_SADD8_SSUB16_SSUB8_UADD16_UADD8_USUB16_USUB8 = 882, |
| 5448 | t2SADD16_t2SADD8_t2SSUB16_t2SSUB8_t2UADD16_t2UADD8_t2USUB16_t2USUB8 = 883, |
| 5449 | SHADD16_SHADD8_SHSUB16_SHSUB8_UHADD16_UHADD8_UHSUB16_UHSUB8 = 884, |
| 5450 | t2SHADD16_t2SHADD8_t2SHSUB16_t2SHSUB8_t2UHADD16_t2UHADD8_t2UHSUB16_t2UHSUB8 = 885, |
| 5451 | QADD16_QADD8_QSUB16_QSUB8_UQADD16_UQADD8_UQSUB16_UQSUB8 = 886, |
| 5452 | t2QADD_t2QADD16_t2QADD8_t2UQADD16_t2UQADD8_t2QSUB_t2QSUB16_t2QSUB8_t2UQSUB16_t2UQSUB8 = 887, |
| 5453 | QASX_QSAX_UQASX_UQSAX = 888, |
| 5454 | t2QASX_t2QSAX_t2UQASX_t2UQSAX = 889, |
| 5455 | SSAT_SSAT16_USAT_USAT16 = 890, |
| 5456 | QADD_QSUB = 891, |
| 5457 | SBFX_UBFX = 892, |
| 5458 | t2SBFX_t2UBFX = 893, |
| 5459 | SXTB_SXTH_UXTB_UXTH = 894, |
| 5460 | t2SXTB_t2SXTH_t2UXTB_t2UXTH = 895, |
| 5461 | tSXTB_tSXTH_tUXTB_tUXTH = 896, |
| 5462 | SXTAB_SXTAH_UXTAB_UXTAH = 897, |
| 5463 | t2SXTAB_t2SXTAH_t2UXTAB_t2UXTAH = 898, |
| 5464 | LDRConstPool_t2LDRConstPool_tLDRConstPool = 899, |
| 5465 | PICLDRB_PICLDRH = 900, |
| 5466 | PICLDRSB_PICLDRSH = 901, |
| 5467 | tLDR_postidx = 902, |
| 5468 | tLDRBi_tLDRHi = 903, |
| 5469 | tLDRi_tLDRpci_tLDRspi = 904, |
| 5470 | t2LDRBpcrel_t2LDRHpcrel_t2LDRpcrel = 905, |
| 5471 | LDR_PRE_IMM = 906, |
| 5472 | LDRB_PRE_IMM = 907, |
| 5473 | t2LDRB_PRE_imm = 908, |
| 5474 | t2LDRB_PRE = 909, |
| 5475 | LDR_PRE_REG = 910, |
| 5476 | LDRB_PRE_REG = 911, |
| 5477 | LDRH_PRE = 912, |
| 5478 | LDRSB_PRE_LDRSH_PRE = 913, |
| 5479 | t2LDRH_PRE_imm_t2LDR_PRE_imm = 914, |
| 5480 | t2LDRSB_PRE_imm_t2LDRSH_PRE_imm = 915, |
| 5481 | t2LDRH_PRE = 916, |
| 5482 | t2LDRSB_PRE_t2LDRSH_PRE = 917, |
| 5483 | t2LDR_PRE = 918, |
| 5484 | LDRD_PRE = 919, |
| 5485 | t2LDRD_PRE = 920, |
| 5486 | LDRT_POST_IMM = 921, |
| 5487 | LDRBT_POST_IMM = 922, |
| 5488 | LDRHTi = 923, |
| 5489 | LDRSBTi_LDRSHTi = 924, |
| 5490 | t2LDRB_POST_imm = 925, |
| 5491 | t2LDRB_POST = 926, |
| 5492 | LDRH_POST = 927, |
| 5493 | LDRSB_POST_LDRSH_POST = 928, |
| 5494 | LDR_POST_REG = 929, |
| 5495 | LDRB_POST_REG = 930, |
| 5496 | LDRT_POST = 931, |
| 5497 | PLDi12_t2PLDi12_PLDWi12_t2PLDWi12_t2PLDWi8_t2PLDWs_t2PLDi8_t2PLDpci_t2PLDs_PLIi12_PLIrs_t2PLIi12_t2PLIi8_t2PLIpci_t2PLIs = 932, |
| 5498 | PLDrs_PLDWrs = 933, |
| 5499 | VLLDM_VLLDM_T2 = 934, |
| 5500 | STRBi12_PICSTRB_PICSTRH = 935, |
| 5501 | t2STRBT = 936, |
| 5502 | STR_PRE_IMM = 937, |
| 5503 | STRB_PRE_IMM = 938, |
| 5504 | STRBi_preidx_STRBr_preidx_STRi_preidx_STRr_preidx_STRH_preidx = 939, |
| 5505 | t2STRH_PRE_imm_t2STRB_PRE_imm_t2STR_PRE_imm = 940, |
| 5506 | STRH_PRE = 941, |
| 5507 | t2STRH_PRE_t2STR_PRE = 942, |
| 5508 | t2STRB_PRE = 943, |
| 5509 | t2STRD_PRE = 944, |
| 5510 | STR_PRE_REG = 945, |
| 5511 | STRB_PRE_REG = 946, |
| 5512 | STRD_PRE = 947, |
| 5513 | STRT_POST_IMM = 948, |
| 5514 | STRBT_POST_IMM = 949, |
| 5515 | t2STRB_POST_imm_t2STR_POST_imm = 950, |
| 5516 | t2STRB_POST = 951, |
| 5517 | STRBT_POST_REG_STRB_POST_REG = 952, |
| 5518 | STRBT_POST_STRT_POST = 953, |
| 5519 | VLSTM_VLSTM_T2 = 954, |
| 5520 | VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTBDH_VCVTTDH_VCVTTHD = 955, |
| 5521 | VTOSLS_VTOUHS_VTOULS = 956, |
| 5522 | VJCVT = 957, |
| 5523 | VRINTAD_VRINTAH_VRINTAS_VRINTMD_VRINTMH_VRINTMS_VRINTND_VRINTNH_VRINTNS_VRINTPD_VRINTPH_VRINTPS_VRINTRD_VRINTRH_VRINTRS_VRINTXD_VRINTXH_VRINTXS_VRINTZD_VRINTZH_VRINTZS = 958, |
| 5524 | VSQRTH = 959, |
| 5525 | VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8 = 960, |
| 5526 | VUDOTD_VUDOTDI_VSDOTD_VSDOTDI_VUDOTQ_VUDOTQI_VSDOTQ_VSDOTQI = 961, |
| 5527 | FCONSTD = 962, |
| 5528 | FCONSTH = 963, |
| 5529 | FCONSTS = 964, |
| 5530 | VMOVHcc_VMOVH = 965, |
| 5531 | VINSH = 966, |
| 5532 | VSTMSIA = 967, |
| 5533 | VSTMSDB_UPD_VSTMSIA_UPD = 968, |
| 5534 | VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16 = 969, |
| 5535 | VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8 = 970, |
| 5536 | VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 971, |
| 5537 | VMULpd_VMULv4i16_VMULv8i8_VMULslv4i16 = 972, |
| 5538 | VMULv2i32_VMULslv2i32 = 973, |
| 5539 | VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32 = 974, |
| 5540 | VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16 = 975, |
| 5541 | VMULpq_VMULv16i8_VMULv8i16_VMULslv8i16 = 976, |
| 5542 | VMLAslv2i32_VMLAv2i32_VMLSslv2i32_VMLSv2i32 = 977, |
| 5543 | VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSslv4i16_VMLSv4i16_VMLSv8i8 = 978, |
| 5544 | VQRDMLAHslv2i32_VQRDMLAHv2i32_VQRDMLSHslv2i32_VQRDMLSHv2i32 = 979, |
| 5545 | VQRDMLAHslv4i16_VQRDMLAHv4i16_VQRDMLSHslv4i16_VQRDMLSHv4i16 = 980, |
| 5546 | VQRDMLAHslv4i32_VQRDMLAHv4i32_VQRDMLSHslv4i32_VQRDMLSHv4i32 = 981, |
| 5547 | VQRDMLAHslv8i16_VQRDMLAHv8i16_VQRDMLSHslv8i16_VQRDMLSHv8i16 = 982, |
| 5548 | VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16 = 983, |
| 5549 | VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8 = 984, |
| 5550 | VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8 = 985, |
| 5551 | VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 986, |
| 5552 | VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 987, |
| 5553 | VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 988, |
| 5554 | VPADDh = 989, |
| 5555 | VCADDv2f32_VCADDv4f16_VCMLAv2f32_VCMLAv2f32_indexed_VCMLAv4f16_VCMLAv4f16_indexed = 990, |
| 5556 | VCADDv4f32_VCADDv8f16_VCMLAv4f32_VCMLAv4f32_indexed_VCMLAv8f16_VCMLAv8f16_indexed = 991, |
| 5557 | VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTs2fd_VCVTu2fd_VCVTxs2fd_VCVTxu2fd = 992, |
| 5558 | VCVTf2sq_VCVTf2uq_VCVTs2fq_VCVTu2fq_VCVTf2xsq_VCVTf2xuq_VCVTxs2fq_VCVTxu2fq = 993, |
| 5559 | NEON_VMAXNMNDf_NEON_VMAXNMNDh_NEON_VMAXNMNQf_NEON_VMAXNMNQh_VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_NEON_VMINNMNDf_NEON_VMINNMNDh_NEON_VMINNMNQf_NEON_VMINNMNQh_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 994, |
| 5560 | VMULhd = 995, |
| 5561 | VMULhq = 996, |
| 5562 | VRINTANDf_VRINTANDh_VRINTANQf_VRINTANQh_VRINTMNDf_VRINTMNDh_VRINTMNQf_VRINTMNQh_VRINTNNDf_VRINTNNDh_VRINTNNQf_VRINTNNQh_VRINTPNDf_VRINTPNDh_VRINTPNQf_VRINTPNQh_VRINTXNDf_VRINTXNDh_VRINTXNQf_VRINTXNQh_VRINTZNDf_VRINTZNDh_VRINTZNQf_VRINTZNQh = 997, |
| 5563 | VMOVD0_VMOVQ0 = 998, |
| 5564 | VTRNd16_VTRNd32_VTRNd8 = 999, |
| 5565 | VLD2d16_VLD2d32_VLD2d8 = 1000, |
| 5566 | VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 1001, |
| 5567 | VLD3LNd32_VLD3LNq32_VLD3LNd32Pseudo_VLD3LNq32Pseudo = 1002, |
| 5568 | VLD3LNd32_UPD_VLD3LNq32_UPD = 1003, |
| 5569 | VLD3LNd32Pseudo_UPD_VLD3LNq32Pseudo_UPD = 1004, |
| 5570 | VLD4LNd32_VLD4LNq32_VLD4LNd32Pseudo_VLD4LNq32Pseudo = 1005, |
| 5571 | VLD4LNd32_UPD_VLD4LNq32_UPD = 1006, |
| 5572 | VLD4LNd32Pseudo_UPD_VLD4LNq32Pseudo_UPD = 1007, |
| 5573 | AESD_AESE_AESIMC_AESMC = 1008, |
| 5574 | SHA1SU0 = 1009, |
| 5575 | SHA1H_SHA1SU1 = 1010, |
| 5576 | SHA1C_SHA1M_SHA1P = 1011, |
| 5577 | SHA256SU0 = 1012, |
| 5578 | SHA256H_SHA256H2_SHA256SU1 = 1013, |
| 5579 | t2LDMIA_RET = 1014, |
| 5580 | tLDMIA_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 1015, |
| 5581 | t2LDMDB_t2LDMIA_tLDMIA = 1016, |
| 5582 | t2LDRB_OFFSET_imm_t2LDRH_OFFSET_imm_t2LDRSB_OFFSET_imm_t2LDRSH_OFFSET_imm = 1017, |
| 5583 | t2LDRConstPool_tLDRConstPool = 1018, |
| 5584 | t2LDRLIT_ga_pcrel = 1019, |
| 5585 | tLDRLIT_ga_abs = 1020, |
| 5586 | tLDRLIT_ga_pcrel = 1021, |
| 5587 | t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH = 1022, |
| 5588 | t2STMDB_t2STMIA = 1023, |
| 5589 | t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 1024, |
| 5590 | tMOVSr_tMOVr = 1025, |
| 5591 | tMOVi8 = 1026, |
| 5592 | t2MSR_AR_t2MSR_M_t2MSRbanked_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR = 1027, |
| 5593 | t2CLREX = 1028, |
| 5594 | t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2SMLSLD_t2SMLSLDX = 1029, |
| 5595 | t2REV_t2REV16_t2REVSH_tREV_tREV16_tREVSH = 1030, |
| 5596 | t2CDP_t2CDP2 = 1031, |
| 5597 | t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2_t2MRRC_t2MRRC2 = 1032, |
| 5598 | t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE = 1033, |
| 5599 | tCPS_t2ISB_t2DSB_t2DMB_t2HINT_tHINT = 1034, |
| 5600 | t2UDF_tUDF = 1035, |
| 5601 | tBKPT_t2DBG = 1036, |
| 5602 | Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_ADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKDOWN_tADJCALLSTACKUP = 1037, |
| 5603 | CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 1038, |
| 5604 | JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH = 1039, |
| 5605 | MEMCPY = 1040, |
| 5606 | VSETLNi32 = 1041, |
| 5607 | VGETLNi32 = 1042, |
| 5608 | VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8 = 1043, |
| 5609 | VLD1d16QPseudo_VLD1d16QPseudoWB_fixed_VLD1d16QPseudoWB_register_VLD1d32QPseudo_VLD1d32QPseudoWB_fixed_VLD1d32QPseudoWB_register_VLD1d8QPseudo_VLD1d8QPseudoWB_fixed_VLD1d8QPseudoWB_register_VLD1q16HighQPseudo_VLD1q16HighQPseudo_UPD_VLD1q16LowQPseudo_UPD_VLD1q32HighQPseudo_VLD1q32HighQPseudo_UPD_VLD1q32LowQPseudo_UPD_VLD1q64HighQPseudo_VLD1q64HighQPseudo_UPD_VLD1q64LowQPseudo_UPD_VLD1q8HighQPseudo_VLD1q8HighQPseudo_UPD_VLD1q8LowQPseudo_UPD = 1044, |
| 5610 | VLD1d16TPseudo_VLD1d16TPseudoWB_fixed_VLD1d16TPseudoWB_register_VLD1d32TPseudo_VLD1d32TPseudoWB_fixed_VLD1d32TPseudoWB_register_VLD1d8TPseudo_VLD1d8TPseudoWB_fixed_VLD1d8TPseudoWB_register_VLD1q16HighTPseudo_VLD1q16HighTPseudo_UPD_VLD1q16LowTPseudo_UPD_VLD1q32HighTPseudo_VLD1q32HighTPseudo_UPD_VLD1q32LowTPseudo_UPD_VLD1q64HighTPseudo_VLD1q64HighTPseudo_UPD_VLD1q64LowTPseudo_UPD_VLD1q8HighTPseudo_VLD1q8HighTPseudo_UPD_VLD1q8LowTPseudo_UPD = 1045, |
| 5611 | VLD2DUPq16EvenPseudo_VLD2DUPq16OddPseudo_VLD2DUPq16OddPseudoWB_fixed_VLD2DUPq16OddPseudoWB_register_VLD2DUPq32EvenPseudo_VLD2DUPq32OddPseudo_VLD2DUPq32OddPseudoWB_fixed_VLD2DUPq32OddPseudoWB_register_VLD2DUPq8EvenPseudo_VLD2DUPq8OddPseudo_VLD2DUPq8OddPseudoWB_fixed_VLD2DUPq8OddPseudoWB_register = 1046, |
| 5612 | VLD3DUPq16EvenPseudo_VLD3DUPq16OddPseudo_VLD3DUPq32EvenPseudo_VLD3DUPq32OddPseudo_VLD3DUPq8EvenPseudo_VLD3DUPq8OddPseudo = 1047, |
| 5613 | VLD3DUPq16OddPseudo_UPD_VLD3DUPq32OddPseudo_UPD_VLD3DUPq8OddPseudo_UPD = 1048, |
| 5614 | VLD4DUPq16EvenPseudo_VLD4DUPq16OddPseudo_VLD4DUPq32EvenPseudo_VLD4DUPq32OddPseudo_VLD4DUPq8EvenPseudo_VLD4DUPq8OddPseudo = 1049, |
| 5615 | VLD4DUPq16OddPseudo_UPD_VLD4DUPq32OddPseudo_UPD_VLD4DUPq8OddPseudo_UPD = 1050, |
| 5616 | VST1d16TPseudo_VST1d32TPseudo_VST1d8TPseudo_VST1q16HighTPseudo_VST1q16HighTPseudo_UPD_VST1q16LowTPseudo_UPD_VST1q32HighTPseudo_VST1q32HighTPseudo_UPD_VST1q32LowTPseudo_UPD_VST1q64HighTPseudo_VST1q64HighTPseudo_UPD_VST1q64LowTPseudo_UPD_VST1q8HighTPseudo_VST1q8HighTPseudo_UPD_VST1q8LowTPseudo_UPD = 1051, |
| 5617 | VST1d16TPseudoWB_fixed_VST1d16TPseudoWB_register_VST1d32TPseudoWB_fixed_VST1d32TPseudoWB_register_VST1d8TPseudoWB_fixed_VST1d8TPseudoWB_register = 1052, |
| 5618 | VST1q16HighQPseudo_VST1q16HighQPseudo_UPD_VST1q16LowQPseudo_UPD_VST1q32HighQPseudo_VST1q32HighQPseudo_UPD_VST1q32LowQPseudo_UPD_VST1q64HighQPseudo_VST1q64HighQPseudo_UPD_VST1q64LowQPseudo_UPD_VST1q8HighQPseudo_VST1q8HighQPseudo_UPD_VST1q8LowQPseudo_UPD = 1053, |
| 5619 | VMOVD0 = 1054, |
| 5620 | t2CPS1p_t2CPS2p_t2CPS3p_t2SG_t2TT_t2TTA_t2TTAT_t2TTT = 1055, |
| 5621 | t2DBG = 1056, |
| 5622 | t2SUBS_PC_LR = 1057, |
| 5623 | COPY_TO_REGCLASS_COPY_LANEMASK = 1058, |
| 5624 | COPY_STRUCT_BYVAL_I32 = 1059, |
| 5625 | t2CSEL_t2CSINC_t2CSINV_t2CSNEG = 1060, |
| 5626 | t2ADDrr_t2ADDSrr_t2SBCrr = 1061, |
| 5627 | t2ASRri_t2LSLri_t2LSRri = 1062, |
| 5628 | t2ASRrr_t2LSLrr_t2LSRrr_t2RORrr = 1063, |
| 5629 | t2CMNrr = 1064, |
| 5630 | t2CMPri = 1065, |
| 5631 | t2CMPrr = 1066, |
| 5632 | t2ORRrr = 1067, |
| 5633 | t2REV_t2REV16_t2REVSH = 1068, |
| 5634 | t2RSBri_t2RSBSri = 1069, |
| 5635 | t2RSBrr_t2SUBSrr_t2SUBrr = 1070, |
| 5636 | t2TEQrr_t2TSTrr = 1071, |
| 5637 | t2STRi12 = 1072, |
| 5638 | t2STRBi12_t2STRHi12 = 1073, |
| 5639 | t2STMIA_UPD_t2STMDB_UPD = 1074, |
| 5640 | t2SETPAN_tHLT_tSETEND = 1075, |
| 5641 | tADC_tADDhirr_tADDrSP_tADDrr_tADDspr_tPICADD_tSBC_tSUBrr = 1076, |
| 5642 | tADDrSPi_tADDspi_tADR_tRSB_tSUBspi = 1077, |
| 5643 | tAND_tBIC_tEOR_tORR = 1078, |
| 5644 | tASRri_tLSLri_tLSRri = 1079, |
| 5645 | tCBNZ_tCBZ = 1080, |
| 5646 | tCMN_tCMPhir_tCMPr = 1081, |
| 5647 | tCMPi8 = 1082, |
| 5648 | tCPS_tHINT = 1083, |
| 5649 | tMOVSr = 1084, |
| 5650 | tSTRBi_tSTRHi = 1085, |
| 5651 | tSTRi_tSTRspi = 1086, |
| 5652 | tSVC_tTRAP = 1087, |
| 5653 | tTST = 1088, |
| 5654 | tUDF = 1089, |
| 5655 | tB_tBX_tBXNS_tBcc = 1090, |
| 5656 | tBLXNSr_tBLXr = 1091, |
| 5657 | t2DMB_t2DSB_t2ISB = 1092, |
| 5658 | t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2 = 1093, |
| 5659 | t2MOVSsi = 1094, |
| 5660 | t2MOVSsr = 1095, |
| 5661 | t2MUL = 1096, |
| 5662 | t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 1097, |
| 5663 | t2UXTAB_t2UXTAH = 1098, |
| 5664 | t2UXTAB16 = 1099, |
| 5665 | MVE_SQRSHR_MVE_SQSHL_MVE_SRSHR_MVE_UQRSHL_MVE_UQSHL_MVE_URSHR = 1100, |
| 5666 | MVE_ASRLi_MVE_ASRLr_MVE_LSLLi_MVE_LSLLr_MVE_LSRL_MVE_SQRSHRL_MVE_SQSHLL_MVE_SRSHRL_MVE_UQRSHLL_MVE_UQSHLL_MVE_URSHRL = 1101, |
| 5667 | t2CLRM = 1102, |
| 5668 | t2LDRBi12_t2LDRHi12 = 1103, |
| 5669 | t2LDRi12 = 1104, |
| 5670 | t2LDMDB_t2LDMIA = 1105, |
| 5671 | t2LDMDB_UPD_t2LDMIA_UPD = 1106, |
| 5672 | tADDi3_tADDi8_tSUBi3_tSUBi8 = 1107, |
| 5673 | t2ADDSri_t2ADDri = 1108, |
| 5674 | t2SUBSri_t2SUBri = 1109, |
| 5675 | t2LoopDec = 1110, |
| 5676 | MVE_VLDRBS16_MVE_VLDRBS32_MVE_VLDRBU16_MVE_VLDRBU32_MVE_VLDRBU8_MVE_VLDRHS32_MVE_VLDRHU16_MVE_VLDRHU32_MVE_VLDRWU32 = 1111, |
| 5677 | MVE_VLDRBS16_post_MVE_VLDRBS16_pre_MVE_VLDRBS32_post_MVE_VLDRBS32_pre_MVE_VLDRBU16_post_MVE_VLDRBU16_pre_MVE_VLDRBU32_post_MVE_VLDRBU32_pre_MVE_VLDRBU8_post_MVE_VLDRBU8_pre_MVE_VLDRHS32_post_MVE_VLDRHS32_pre_MVE_VLDRHU16_post_MVE_VLDRHU16_pre_MVE_VLDRHU32_post_MVE_VLDRHU32_pre_MVE_VLDRWU32_post_MVE_VLDRWU32_pre = 1112, |
| 5678 | MVE_VLDRBS16_rq_MVE_VLDRBS32_rq_MVE_VLDRBU16_rq_MVE_VLDRBU32_rq_MVE_VLDRBU8_rq_MVE_VLDRDU64_rq_MVE_VLDRDU64_rq_u_MVE_VLDRHS32_rq_MVE_VLDRHS32_rq_u_MVE_VLDRHU16_rq_MVE_VLDRHU16_rq_u_MVE_VLDRHU32_rq_MVE_VLDRHU32_rq_u_MVE_VLDRWU32_rq_MVE_VLDRWU32_rq_u = 1113, |
| 5679 | MVE_VLDRDU64_qi_MVE_VLDRWU32_qi = 1114, |
| 5680 | MVE_VLDRDU64_qi_pre_MVE_VLDRWU32_qi_pre = 1115, |
| 5681 | MVE_VLD20_16_MVE_VLD20_32_MVE_VLD20_8_MVE_VLD21_16_MVE_VLD21_32_MVE_VLD21_8_MVE_VLD40_16_MVE_VLD40_32_MVE_VLD40_8_MVE_VLD41_16_MVE_VLD41_32_MVE_VLD41_8_MVE_VLD42_16_MVE_VLD42_32_MVE_VLD42_8_MVE_VLD43_16_MVE_VLD43_32_MVE_VLD43_8 = 1116, |
| 5682 | MVE_VLD20_16_wb_MVE_VLD20_32_wb_MVE_VLD20_8_wb_MVE_VLD21_16_wb_MVE_VLD21_32_wb_MVE_VLD21_8_wb_MVE_VLD40_16_wb_MVE_VLD40_32_wb_MVE_VLD40_8_wb_MVE_VLD41_16_wb_MVE_VLD41_32_wb_MVE_VLD41_8_wb_MVE_VLD42_16_wb_MVE_VLD42_32_wb_MVE_VLD42_8_wb_MVE_VLD43_16_wb_MVE_VLD43_32_wb_MVE_VLD43_8_wb = 1117, |
| 5683 | MVE_VSTRB16_MVE_VSTRB32_MVE_VSTRBU8_MVE_VSTRH32_MVE_VSTRHU16_MVE_VSTRWU32 = 1118, |
| 5684 | MVE_VSTRB16_post_MVE_VSTRB16_pre_MVE_VSTRB32_post_MVE_VSTRB32_pre_MVE_VSTRBU8_post_MVE_VSTRBU8_pre_MVE_VSTRH32_post_MVE_VSTRH32_pre_MVE_VSTRHU16_post_MVE_VSTRHU16_pre_MVE_VSTRWU32_post_MVE_VSTRWU32_pre = 1119, |
| 5685 | MVE_VSTRB16_rq_MVE_VSTRB32_rq_MVE_VSTRB8_rq_MVE_VSTRD64_rq_MVE_VSTRD64_rq_u_MVE_VSTRH16_rq_MVE_VSTRH16_rq_u_MVE_VSTRH32_rq_MVE_VSTRH32_rq_u_MVE_VSTRW32_rq_MVE_VSTRW32_rq_u = 1120, |
| 5686 | MVE_VSTRD64_qi_MVE_VSTRD64_qi_pre_MVE_VSTRW32_qi_MVE_VSTRW32_qi_pre = 1121, |
| 5687 | MVE_VST20_16_MVE_VST20_16_wb_MVE_VST20_32_MVE_VST20_32_wb_MVE_VST20_8_MVE_VST20_8_wb_MVE_VST21_16_MVE_VST21_16_wb_MVE_VST21_32_MVE_VST21_32_wb_MVE_VST21_8_MVE_VST21_8_wb_MVE_VST40_16_MVE_VST40_16_wb_MVE_VST40_32_MVE_VST40_32_wb_MVE_VST40_8_MVE_VST40_8_wb_MVE_VST41_16_MVE_VST41_16_wb_MVE_VST41_32_MVE_VST41_32_wb_MVE_VST41_8_MVE_VST41_8_wb_MVE_VST42_16_MVE_VST42_16_wb_MVE_VST42_32_MVE_VST42_32_wb_MVE_VST42_8_MVE_VST42_8_wb_MVE_VST43_16_MVE_VST43_16_wb_MVE_VST43_32_MVE_VST43_32_wb_MVE_VST43_8_MVE_VST43_8_wb = 1122, |
| 5688 | MVE_VABAVs16_MVE_VABAVs32_MVE_VABAVs8_MVE_VABAVu16_MVE_VABAVu32_MVE_VABAVu8 = 1123, |
| 5689 | MVE_VABDs16_MVE_VABDs32_MVE_VABDs8_MVE_VABDu16_MVE_VABDu32_MVE_VABDu8 = 1124, |
| 5690 | MVE_VABSs16_MVE_VABSs32_MVE_VABSs8 = 1125, |
| 5691 | MVE_VADC_MVE_VADCI = 1126, |
| 5692 | MVE_VADD_qr_i16_MVE_VADD_qr_i32_MVE_VADD_qr_i8_MVE_VADDi16_MVE_VADDi32_MVE_VADDi8 = 1127, |
| 5693 | MVE_VAND = 1128, |
| 5694 | MVE_VBIC_MVE_VBICimmi16_MVE_VBICimmi32 = 1129, |
| 5695 | MVE_VBRSR16_MVE_VBRSR32_MVE_VBRSR8 = 1130, |
| 5696 | MVE_VCADDi16_MVE_VCADDi32_MVE_VCADDi8 = 1131, |
| 5697 | MVE_VCLSs16_MVE_VCLSs32_MVE_VCLSs8 = 1132, |
| 5698 | MVE_VCLZs16_MVE_VCLZs32_MVE_VCLZs8 = 1133, |
| 5699 | MVE_VDDUPu16_MVE_VDDUPu32_MVE_VDDUPu8_MVE_VDUP16_MVE_VDUP32_MVE_VDUP8_MVE_VDWDUPu16_MVE_VDWDUPu32_MVE_VDWDUPu8_MVE_VIDUPu16_MVE_VIDUPu32_MVE_VIDUPu8_MVE_VIWDUPu16_MVE_VIWDUPu32_MVE_VIWDUPu8 = 1134, |
| 5700 | MVE_VEOR = 1135, |
| 5701 | MVE_VHADD_qr_s16_MVE_VHADD_qr_s32_MVE_VHADD_qr_s8_MVE_VHADD_qr_u16_MVE_VHADD_qr_u32_MVE_VHADD_qr_u8_MVE_VHADDs16_MVE_VHADDs32_MVE_VHADDs8_MVE_VHADDu16_MVE_VHADDu32_MVE_VHADDu8 = 1136, |
| 5702 | MVE_VHCADDs16_MVE_VHCADDs32_MVE_VHCADDs8 = 1137, |
| 5703 | MVE_VHSUB_qr_s16_MVE_VHSUB_qr_s32_MVE_VHSUB_qr_s8_MVE_VHSUB_qr_u16_MVE_VHSUB_qr_u32_MVE_VHSUB_qr_u8_MVE_VHSUBs16_MVE_VHSUBs32_MVE_VHSUBs8_MVE_VHSUBu16_MVE_VHSUBu32_MVE_VHSUBu8 = 1138, |
| 5704 | MVE_VMAXAs16_MVE_VMAXAs32_MVE_VMAXAs8_MVE_VMAXs16_MVE_VMAXs32_MVE_VMAXs8_MVE_VMAXu16_MVE_VMAXu32_MVE_VMAXu8_MVE_VMINAs16_MVE_VMINAs32_MVE_VMINAs8_MVE_VMINs16_MVE_VMINs32_MVE_VMINs8_MVE_VMINu16_MVE_VMINu32_MVE_VMINu8 = 1139, |
| 5705 | MVE_VMAXAVs8_MVE_VMAXVs8_MVE_VMAXVu8_MVE_VMINAVs8_MVE_VMINVs8_MVE_VMINVu8 = 1140, |
| 5706 | MVE_VMAXAVs16_MVE_VMAXVs16_MVE_VMAXVu16_MVE_VMINAVs16_MVE_VMINVs16_MVE_VMINVu16 = 1141, |
| 5707 | MVE_VMAXAVs32_MVE_VMAXVs32_MVE_VMAXVu32_MVE_VMINAVs32_MVE_VMINVs32_MVE_VMINVu32 = 1142, |
| 5708 | MVE_VMOVNi16bh_MVE_VMOVNi16th_MVE_VMOVNi32bh_MVE_VMOVNi32th = 1143, |
| 5709 | MVE_VMOVLs16bh_MVE_VMOVLs16th_MVE_VMOVLs8bh_MVE_VMOVLs8th_MVE_VMOVLu16bh_MVE_VMOVLu16th_MVE_VMOVLu8bh_MVE_VMOVLu8th = 1144, |
| 5710 | MVE_VMULLBp16_MVE_VMULLBp8_MVE_VMULLTp16_MVE_VMULLTp8 = 1145, |
| 5711 | MVE_VMVN_MVE_VMVNimmi16_MVE_VMVNimmi32 = 1146, |
| 5712 | MVE_VNEGs16_MVE_VNEGs32_MVE_VNEGs8 = 1147, |
| 5713 | MVE_VORN = 1148, |
| 5714 | MVE_VORR_MVE_VORRimmi16_MVE_VORRimmi32 = 1149, |
| 5715 | MVE_VPSEL = 1150, |
| 5716 | MQPRCopy = 1151, |
| 5717 | MVE_VQABSs16_MVE_VQABSs32_MVE_VQABSs8 = 1152, |
| 5718 | MVE_VQADD_qr_s16_MVE_VQADD_qr_s32_MVE_VQADD_qr_s8_MVE_VQADD_qr_u16_MVE_VQADD_qr_u32_MVE_VQADD_qr_u8_MVE_VQADDs16_MVE_VQADDs32_MVE_VQADDs8_MVE_VQADDu16_MVE_VQADDu32_MVE_VQADDu8 = 1153, |
| 5719 | MVE_VQMOVNs16bh_MVE_VQMOVNs16th_MVE_VQMOVNs32bh_MVE_VQMOVNs32th_MVE_VQMOVNu16bh_MVE_VQMOVNu16th_MVE_VQMOVNu32bh_MVE_VQMOVNu32th_MVE_VQMOVUNs16bh_MVE_VQMOVUNs16th_MVE_VQMOVUNs32bh_MVE_VQMOVUNs32th = 1154, |
| 5720 | MVE_VQNEGs16_MVE_VQNEGs32_MVE_VQNEGs8 = 1155, |
| 5721 | MVE_VSHLC_MVE_VSHLL_imms16bh_MVE_VSHLL_imms16th_MVE_VSHLL_imms8bh_MVE_VSHLL_imms8th_MVE_VSHLL_immu16bh_MVE_VSHLL_immu16th_MVE_VSHLL_immu8bh_MVE_VSHLL_immu8th_MVE_VSHLL_lws16bh_MVE_VSHLL_lws16th_MVE_VSHLL_lws8bh_MVE_VSHLL_lws8th_MVE_VSHLL_lwu16bh_MVE_VSHLL_lwu16th_MVE_VSHLL_lwu8bh_MVE_VSHLL_lwu8th_MVE_VSHL_by_vecs16_MVE_VSHL_by_vecs32_MVE_VSHL_by_vecs8_MVE_VSHL_by_vecu16_MVE_VSHL_by_vecu32_MVE_VSHL_by_vecu8_MVE_VSHL_immi16_MVE_VSHL_immi32_MVE_VSHL_immi8_MVE_VSHL_qrs16_MVE_VSHL_qrs32_MVE_VSHL_qrs8_MVE_VSHL_qru16_MVE_VSHL_qru32_MVE_VSHL_qru8 = 1156, |
| 5722 | MVE_VQSHLU_imms16_MVE_VQSHLU_imms32_MVE_VQSHLU_imms8_MVE_VQSHL_by_vecs16_MVE_VQSHL_by_vecs32_MVE_VQSHL_by_vecs8_MVE_VQSHL_by_vecu16_MVE_VQSHL_by_vecu32_MVE_VQSHL_by_vecu8_MVE_VQSHL_qrs16_MVE_VQSHL_qrs32_MVE_VQSHL_qrs8_MVE_VQSHL_qru16_MVE_VQSHL_qru32_MVE_VQSHL_qru8_MVE_VQSHLimms16_MVE_VQSHLimms32_MVE_VQSHLimms8_MVE_VQSHLimmu16_MVE_VQSHLimmu32_MVE_VQSHLimmu8_MVE_VRSHL_by_vecs16_MVE_VRSHL_by_vecs32_MVE_VRSHL_by_vecs8_MVE_VRSHL_by_vecu16_MVE_VRSHL_by_vecu32_MVE_VRSHL_by_vecu8_MVE_VRSHL_qrs16_MVE_VRSHL_qrs32_MVE_VRSHL_qrs8_MVE_VRSHL_qru16_MVE_VRSHL_qru32_MVE_VRSHL_qru8 = 1157, |
| 5723 | MVE_VQRSHL_by_vecs16_MVE_VQRSHL_by_vecs32_MVE_VQRSHL_by_vecs8_MVE_VQRSHL_by_vecu16_MVE_VQRSHL_by_vecu32_MVE_VQRSHL_by_vecu8_MVE_VQRSHL_qrs16_MVE_VQRSHL_qrs32_MVE_VQRSHL_qrs8_MVE_VQRSHL_qru16_MVE_VQRSHL_qru32_MVE_VQRSHL_qru8 = 1158, |
| 5724 | MVE_VQRSHRNbhs16_MVE_VQRSHRNbhs32_MVE_VQRSHRNbhu16_MVE_VQRSHRNbhu32_MVE_VQRSHRNths16_MVE_VQRSHRNths32_MVE_VQRSHRNthu16_MVE_VQRSHRNthu32_MVE_VQRSHRUNs16bh_MVE_VQRSHRUNs16th_MVE_VQRSHRUNs32bh_MVE_VQRSHRUNs32th_MVE_VQSHRNbhs16_MVE_VQSHRNbhs32_MVE_VQSHRNbhu16_MVE_VQSHRNbhu32_MVE_VQSHRNths16_MVE_VQSHRNths32_MVE_VQSHRNthu16_MVE_VQSHRNthu32_MVE_VQSHRUNs16bh_MVE_VQSHRUNs16th_MVE_VQSHRUNs32bh_MVE_VQSHRUNs32th_MVE_VRSHRNi16bh_MVE_VRSHRNi16th_MVE_VRSHRNi32bh_MVE_VRSHRNi32th_MVE_VSHRNi16bh_MVE_VSHRNi16th_MVE_VSHRNi32bh_MVE_VSHRNi32th = 1159, |
| 5725 | MVE_VSHR_imms16_MVE_VSHR_imms32_MVE_VSHR_imms8_MVE_VSHR_immu16_MVE_VSHR_immu32_MVE_VSHR_immu8 = 1160, |
| 5726 | MVE_VRSHR_imms16_MVE_VRSHR_imms32_MVE_VRSHR_imms8_MVE_VRSHR_immu16_MVE_VRSHR_immu32_MVE_VRSHR_immu8 = 1161, |
| 5727 | MVE_VQSUB_qr_s16_MVE_VQSUB_qr_s32_MVE_VQSUB_qr_s8_MVE_VQSUB_qr_u16_MVE_VQSUB_qr_u32_MVE_VQSUB_qr_u8_MVE_VQSUBs16_MVE_VQSUBs32_MVE_VQSUBs8_MVE_VQSUBu16_MVE_VQSUBu32_MVE_VQSUBu8 = 1162, |
| 5728 | MVE_VREV16_8_MVE_VREV32_16_MVE_VREV32_8_MVE_VREV64_16_MVE_VREV64_32_MVE_VREV64_8 = 1163, |
| 5729 | MVE_VRHADDs16_MVE_VRHADDs32_MVE_VRHADDs8_MVE_VRHADDu16_MVE_VRHADDu32_MVE_VRHADDu8 = 1164, |
| 5730 | MVE_VSBC_MVE_VSBCI = 1165, |
| 5731 | MVE_VSLIimm16_MVE_VSLIimm32_MVE_VSLIimm8 = 1166, |
| 5732 | MVE_VSRIimm16_MVE_VSRIimm32_MVE_VSRIimm8 = 1167, |
| 5733 | MVE_VSUB_qr_i16_MVE_VSUB_qr_i32_MVE_VSUB_qr_i8_MVE_VSUBi16_MVE_VSUBi32_MVE_VSUBi8 = 1168, |
| 5734 | MVE_VABDf16_MVE_VABDf32 = 1169, |
| 5735 | MVE_VABSf16_MVE_VABSf32 = 1170, |
| 5736 | MVE_VADDf16_MVE_VADDf32 = 1171, |
| 5737 | MVE_VADD_qr_f16_MVE_VADD_qr_f32 = 1172, |
| 5738 | MVE_VADDLVs32acc_MVE_VADDLVs32no_acc_MVE_VADDLVu32acc_MVE_VADDLVu32no_acc = 1173, |
| 5739 | MVE_VADDVs16acc_MVE_VADDVs16no_acc_MVE_VADDVs32acc_MVE_VADDVs32no_acc_MVE_VADDVs8acc_MVE_VADDVs8no_acc_MVE_VADDVu16acc_MVE_VADDVu16no_acc_MVE_VADDVu32acc_MVE_VADDVu32no_acc_MVE_VADDVu8acc_MVE_VADDVu8no_acc = 1174, |
| 5740 | MVE_VCADDf16_MVE_VCADDf32 = 1175, |
| 5741 | MVE_VCMLAf16_MVE_VCMLAf32 = 1176, |
| 5742 | MVE_VCMULf16_MVE_VCMULf32 = 1177, |
| 5743 | MVE_VCMPi16_MVE_VCMPi16r_MVE_VCMPi32_MVE_VCMPi32r_MVE_VCMPi8_MVE_VCMPi8r_MVE_VCMPs16_MVE_VCMPs16r_MVE_VCMPs32_MVE_VCMPs32r_MVE_VCMPs8_MVE_VCMPs8r_MVE_VCMPu16_MVE_VCMPu16r_MVE_VCMPu32_MVE_VCMPu32r_MVE_VCMPu8_MVE_VCMPu8r_MVE_VPTv16i8_MVE_VPTv16i8r_MVE_VPTv16s8_MVE_VPTv16s8r_MVE_VPTv16u8_MVE_VPTv16u8r_MVE_VPTv4i32_MVE_VPTv4i32r_MVE_VPTv4s32_MVE_VPTv4s32r_MVE_VPTv4u32_MVE_VPTv4u32r_MVE_VPTv8i16_MVE_VPTv8i16r_MVE_VPTv8s16_MVE_VPTv8s16r_MVE_VPTv8u16_MVE_VPTv8u16r = 1178, |
| 5744 | MVE_VCMPf16_MVE_VCMPf16r_MVE_VCMPf32_MVE_VCMPf32r_MVE_VPTv4f32_MVE_VPTv4f32r_MVE_VPTv8f16_MVE_VPTv8f16r = 1179, |
| 5745 | MVE_VCVTf16s16_fix_MVE_VCVTf16s16n_MVE_VCVTf16u16_fix_MVE_VCVTf16u16n = 1180, |
| 5746 | MVE_VCVTf32s32_fix_MVE_VCVTf32s32n_MVE_VCVTf32u32_fix_MVE_VCVTf32u32n = 1181, |
| 5747 | MVE_VCVTs16f16_fix_MVE_VCVTs16f16a_MVE_VCVTs16f16m_MVE_VCVTs16f16n_MVE_VCVTs16f16p_MVE_VCVTs16f16z_MVE_VCVTu16f16_fix_MVE_VCVTu16f16a_MVE_VCVTu16f16m_MVE_VCVTu16f16n_MVE_VCVTu16f16p_MVE_VCVTu16f16z = 1182, |
| 5748 | MVE_VCVTs32f32_fix_MVE_VCVTs32f32a_MVE_VCVTs32f32m_MVE_VCVTs32f32n_MVE_VCVTs32f32p_MVE_VCVTs32f32z_MVE_VCVTu32f32_fix_MVE_VCVTu32f32a_MVE_VCVTu32f32m_MVE_VCVTu32f32n_MVE_VCVTu32f32p_MVE_VCVTu32f32z = 1183, |
| 5749 | MVE_VCVTf16f32bh_MVE_VCVTf16f32th = 1184, |
| 5750 | MVE_VCVTf32f16bh_MVE_VCVTf32f16th = 1185, |
| 5751 | MVE_VFMA_qr_Sf16_MVE_VFMA_qr_Sf32_MVE_VFMA_qr_f16_MVE_VFMA_qr_f32_MVE_VFMAf16_MVE_VFMAf32_MVE_VFMSf16_MVE_VFMSf32 = 1186, |
| 5752 | MVE_VMAXNMAVf16_MVE_VMAXNMAVf32_MVE_VMAXNMAf16_MVE_VMAXNMAf32_MVE_VMAXNMVf16_MVE_VMAXNMVf32_MVE_VMAXNMf16_MVE_VMAXNMf32_MVE_VMINNMAVf16_MVE_VMINNMAVf32_MVE_VMINNMAf16_MVE_VMINNMAf32_MVE_VMINNMVf16_MVE_VMINNMVf32_MVE_VMINNMf16_MVE_VMINNMf32 = 1187, |
| 5753 | MVE_VMOV_from_lane_32_MVE_VMOV_from_lane_s16_MVE_VMOV_from_lane_s8_MVE_VMOV_from_lane_u16_MVE_VMOV_from_lane_u8 = 1188, |
| 5754 | MVE_VMOV_rr_q = 1189, |
| 5755 | MVE_VMOVimmf32_MVE_VMOVimmi16_MVE_VMOVimmi32_MVE_VMOVimmi64_MVE_VMOVimmi8 = 1190, |
| 5756 | MVE_VMUL_qr_f16_MVE_VMUL_qr_f32_MVE_VMUL_qr_i16_MVE_VMUL_qr_i32_MVE_VMUL_qr_i8_MVE_VMULf16_MVE_VMULf32_MVE_VMULi16_MVE_VMULi32_MVE_VMULi8 = 1191, |
| 5757 | MVE_VMULHs16_MVE_VMULHs32_MVE_VMULHs8_MVE_VMULHu16_MVE_VMULHu32_MVE_VMULHu8_MVE_VQDMULH_qr_s16_MVE_VQDMULH_qr_s32_MVE_VQDMULH_qr_s8_MVE_VQDMULHi16_MVE_VQDMULHi32_MVE_VQDMULHi8_MVE_VQRDMULH_qr_s16_MVE_VQRDMULH_qr_s32_MVE_VQRDMULH_qr_s8_MVE_VQRDMULHi16_MVE_VQRDMULHi32_MVE_VQRDMULHi8_MVE_VRMULHs16_MVE_VRMULHs32_MVE_VRMULHs8_MVE_VRMULHu16_MVE_VRMULHu32_MVE_VRMULHu8 = 1192, |
| 5758 | MVE_VMULLBs16_MVE_VMULLBs32_MVE_VMULLBs8_MVE_VMULLBu16_MVE_VMULLBu32_MVE_VMULLBu8_MVE_VMULLTs16_MVE_VMULLTs32_MVE_VMULLTs8_MVE_VMULLTu16_MVE_VMULLTu32_MVE_VMULLTu8_MVE_VQDMULLs16bh_MVE_VQDMULLs16th_MVE_VQDMULLs32bh_MVE_VQDMULLs32th = 1193, |
| 5759 | MVE_VQDMULL_qr_s16bh_MVE_VQDMULL_qr_s16th_MVE_VQDMULL_qr_s32bh_MVE_VQDMULL_qr_s32th = 1194, |
| 5760 | MVE_VMLADAVas16_MVE_VMLADAVas32_MVE_VMLADAVas8_MVE_VMLADAVau16_MVE_VMLADAVau32_MVE_VMLADAVau8_MVE_VMLADAVaxs16_MVE_VMLADAVaxs32_MVE_VMLADAVaxs8_MVE_VMLADAVs16_MVE_VMLADAVs32_MVE_VMLADAVs8_MVE_VMLADAVu16_MVE_VMLADAVu32_MVE_VMLADAVu8_MVE_VMLADAVxs16_MVE_VMLADAVxs32_MVE_VMLADAVxs8_MVE_VMLAS_qr_i16_MVE_VMLAS_qr_i32_MVE_VMLAS_qr_i8_MVE_VMLA_qr_i16_MVE_VMLA_qr_i32_MVE_VMLA_qr_i8_MVE_VMLSDAVas16_MVE_VMLSDAVas32_MVE_VMLSDAVas8_MVE_VMLSDAVaxs16_MVE_VMLSDAVaxs32_MVE_VMLSDAVaxs8_MVE_VMLSDAVs16_MVE_VMLSDAVs32_MVE_VMLSDAVs8_MVE_VMLSDAVxs16_MVE_VMLSDAVxs32_MVE_VMLSDAVxs8_MVE_VQDMLADHXs16_MVE_VQDMLADHXs32_MVE_VQDMLADHXs8_MVE_VQDMLADHs16_MVE_VQDMLADHs32_MVE_VQDMLADHs8_MVE_VQDMLAH_qrs16_MVE_VQDMLAH_qrs32_MVE_VQDMLAH_qrs8_MVE_VQDMLASH_qrs16_MVE_VQDMLASH_qrs32_MVE_VQDMLASH_qrs8_MVE_VQDMLSDHXs16_MVE_VQDMLSDHXs32_MVE_VQDMLSDHXs8_MVE_VQDMLSDHs16_MVE_VQDMLSDHs32_MVE_VQDMLSDHs8_MVE_VQRDMLADHXs16_MVE_VQRDMLADHXs32_MVE_VQRDMLADHXs8_MVE_VQRDMLADHs16_MVE_VQRDMLADHs32_MVE_VQRDMLADHs8_MVE_VQRDMLAH_qrs16_MVE_VQRDMLAH_qrs32_MVE_VQRDMLAH_qrs8_MVE_VQRDMLASH_qrs16_MVE_VQRDMLASH_qrs32_MVE_VQRDMLASH_qrs8_MVE_VQRDMLSDHXs16_MVE_VQRDMLSDHXs32_MVE_VQRDMLSDHXs8_MVE_VQRDMLSDHs16_MVE_VQRDMLSDHs32_MVE_VQRDMLSDHs8 = 1195, |
| 5761 | MVE_VMLALDAVas16_MVE_VMLALDAVas32_MVE_VMLALDAVau16_MVE_VMLALDAVau32_MVE_VMLALDAVaxs16_MVE_VMLALDAVaxs32_MVE_VMLALDAVs16_MVE_VMLALDAVs32_MVE_VMLALDAVu16_MVE_VMLALDAVu32_MVE_VMLALDAVxs16_MVE_VMLALDAVxs32_MVE_VMLSLDAVas16_MVE_VMLSLDAVas32_MVE_VMLSLDAVaxs16_MVE_VMLSLDAVaxs32_MVE_VMLSLDAVs16_MVE_VMLSLDAVs32_MVE_VMLSLDAVxs16_MVE_VMLSLDAVxs32_MVE_VRMLALDAVHas32_MVE_VRMLALDAVHau32_MVE_VRMLALDAVHaxs32_MVE_VRMLALDAVHs32_MVE_VRMLALDAVHu32_MVE_VRMLALDAVHxs32_MVE_VRMLSLDAVHas32_MVE_VRMLSLDAVHaxs32_MVE_VRMLSLDAVHs32_MVE_VRMLSLDAVHxs32 = 1196, |
| 5762 | MVE_VNEGf16_MVE_VNEGf32 = 1197, |
| 5763 | MVE_VRINTf16A_MVE_VRINTf16M_MVE_VRINTf16N_MVE_VRINTf16P_MVE_VRINTf16X_MVE_VRINTf16Z_MVE_VRINTf32A_MVE_VRINTf32M_MVE_VRINTf32N_MVE_VRINTf32P_MVE_VRINTf32X_MVE_VRINTf32Z = 1198, |
| 5764 | MVE_VSUBf16_MVE_VSUBf32 = 1199, |
| 5765 | MVE_VSUB_qr_f16_MVE_VSUB_qr_f32 = 1200, |
| 5766 | MVE_VMOV_to_lane_16_MVE_VMOV_to_lane_32_MVE_VMOV_to_lane_8_MVE_VMOV_q_rr = 1201, |
| 5767 | MVE_VCTP16_MVE_VCTP32_MVE_VCTP64_MVE_VCTP8 = 1202, |
| 5768 | MVE_VPNOT = 1203, |
| 5769 | MVE_VPST = 1204, |
| 5770 | VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS = 1205, |
| 5771 | VDIVH = 1206, |
| 5772 | VFMAH_VFMSH = 1207, |
| 5773 | VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 1208, |
| 5774 | VMOVH = 1209, |
| 5775 | VMOVHR = 1210, |
| 5776 | VMOVD = 1211, |
| 5777 | VMOVS = 1212, |
| 5778 | VMOVRH = 1213, |
| 5779 | tSVC = 1214, |
| 5780 | t2HVC = 1215, |
| 5781 | t2SMC_ERET = 1216, |
| 5782 | tHINT = 1217, |
| 5783 | BUNDLE = 1218, |
| 5784 | t2LDRBpcrel_t2LDRHpcrel = 1219, |
| 5785 | t2LDRBpci_t2LDRHpci = 1220, |
| 5786 | t2LDRSBpci_t2LDRSHpci = 1221, |
| 5787 | t2LDRH_POST_imm = 1222, |
| 5788 | t2LDRH_PRE_imm = 1223, |
| 5789 | t2LDREX = 1224, |
| 5790 | t2LDREXB_t2LDREXH = 1225, |
| 5791 | t2STREX_t2STREXB_t2STREXH = 1226, |
| 5792 | t2LDRpci = 1227, |
| 5793 | t2PLDpci_t2PLIpci = 1228, |
| 5794 | tLDRpci = 1229, |
| 5795 | t2PLDWi12_t2PLDWi8_t2PLDi12_t2PLDi8_t2PLIi12_t2PLIi8 = 1230, |
| 5796 | t2PLDs_t2PLIs = 1231, |
| 5797 | t2TBB_JT_t2TBH_JT = 1232, |
| 5798 | t2TBB_t2TBH = 1233, |
| 5799 | t2RSBSrs_t2SUBrs = 1234, |
| 5800 | t2SUBSrs = 1235, |
| 5801 | t2BICrs_t2EORrs_t2ORRrs = 1236, |
| 5802 | t2ORNrs = 1237, |
| 5803 | t2CMNrs = 1238, |
| 5804 | t2CMPrs = 1239, |
| 5805 | t2TEQrs_t2TSTrs = 1240, |
| 5806 | t2ASRs1_t2LSRs1 = 1241, |
| 5807 | t2RRX = 1242, |
| 5808 | t2CLZ = 1243, |
| 5809 | t2USAD8 = 1244, |
| 5810 | t2RBIT = 1245, |
| 5811 | t2PKHBT_t2PKHTB = 1246, |
| 5812 | VCVTASS_VCVTAUS_VCVTMSS_VCVTMUS_VCVTNSS_VCVTNUS_VCVTPSS_VCVTPUS = 1247, |
| 5813 | VFP_VMAXNMS_VFP_VMINNMS = 1248, |
| 5814 | VRINTAS_VRINTMS_VRINTNS_VRINTPS_VRINTRS_VRINTXS_VRINTZS = 1249, |
| 5815 | VCVTASD_VCVTAUD_VCVTMSD_VCVTMUD_VCVTNSD_VCVTNUD_VCVTPSD_VCVTPUD = 1250, |
| 5816 | VCVTTHD = 1251, |
| 5817 | VFP_VMAXNMD_VFP_VMINNMD = 1252, |
| 5818 | VRINTAD_VRINTMD_VRINTND_VRINTPD_VRINTRD_VRINTXD_VRINTZD = 1253, |
| 5819 | VCMPS = 1254, |
| 5820 | VCMPD = 1255, |
| 5821 | VSELEQS_VSELGES_VSELGTS_VSELVSS = 1256, |
| 5822 | VSELEQD_VSELGED_VSELGTD_VSELVSD = 1257, |
| 5823 | VMULD_VNMULD = 1258, |
| 5824 | tLDRspi = 1259, |
| 5825 | t2LDA_t2LDAEX = 1260, |
| 5826 | t2LDAEXD = 1261, |
| 5827 | t2STL_t2STLB_t2STLEX_t2STLEXB_t2STLEXH_t2STLH = 1262, |
| 5828 | MVE_VST20_16_MVE_VST20_32_MVE_VST20_8_MVE_VST21_16_MVE_VST21_32_MVE_VST21_8_MVE_VST40_16_MVE_VST40_32_MVE_VST40_8_MVE_VST41_16_MVE_VST41_32_MVE_VST41_8_MVE_VST42_16_MVE_VST42_32_MVE_VST42_8_MVE_VST43_16_MVE_VST43_32_MVE_VST43_8 = 1263, |
| 5829 | MVE_VSTRD64_qi_MVE_VSTRW32_qi = 1264, |
| 5830 | t2RSBSrs = 1265, |
| 5831 | t2ADCrs_t2SBCrs = 1266, |
| 5832 | t2ADDSrr_t2SBCrr = 1267, |
| 5833 | t2SUBSrr_t2RSBrr = 1268, |
| 5834 | t2ADCrr = 1269, |
| 5835 | t2BICrr_t2EORrr = 1270, |
| 5836 | t2ORNrr = 1271, |
| 5837 | tLSLSri = 1272, |
| 5838 | tADDspi_tSUBspi = 1273, |
| 5839 | t2ADDri = 1274, |
| 5840 | t2ADDri12 = 1275, |
| 5841 | t2SUBri = 1276, |
| 5842 | t2SUBri12 = 1277, |
| 5843 | tADDrSP_tADDspr_tADDhirr = 1278, |
| 5844 | tADDrSPi = 1279, |
| 5845 | MVE_ASRLi_MVE_LSLLi_MVE_LSRL_MVE_SQSHLL_MVE_SRSHRL_MVE_UQSHLL_MVE_URSHRL = 1280, |
| 5846 | MVE_SQRSHR_MVE_UQRSHL = 1281, |
| 5847 | t2BF_LabelPseudo_t2BFLi_t2BFLr_t2BFi_t2BFic_t2BFr = 1282, |
| 5848 | MVE_LCTP = 1283, |
| 5849 | t2DLS_t2WLS_MVE_DLSTP_16_MVE_DLSTP_32_MVE_DLSTP_64_MVE_DLSTP_8_MVE_WLSTP_16_MVE_WLSTP_32_MVE_WLSTP_64_MVE_WLSTP_8 = 1284, |
| 5850 | t2LE = 1285, |
| 5851 | t2LEUpdate_MVE_LETP = 1286, |
| 5852 | VSHTOD_VSLTOD_VUHTOD_VULTOD = 1287, |
| 5853 | VMSR_VMSR_FPSCR_NZCVQC_VMSR_P0_VMSR_VPR = 1288, |
| 5854 | VMRS_P0_VMRS_VPR = 1289, |
| 5855 | VMRS_FPSCR_NZCVQC = 1290, |
| 5856 | VMRS = 1291, |
| 5857 | MVE_VMOV_q_rr = 1292, |
| 5858 | MVE_VADC = 1293, |
| 5859 | MVE_VADD_qr_i16_MVE_VADD_qr_i32_MVE_VADD_qr_i8 = 1294, |
| 5860 | MVE_VHADD_qr_s16_MVE_VHADD_qr_s32_MVE_VHADD_qr_s8_MVE_VHADD_qr_u16_MVE_VHADD_qr_u32_MVE_VHADD_qr_u8 = 1295, |
| 5861 | MVE_VHSUB_qr_s16_MVE_VHSUB_qr_s32_MVE_VHSUB_qr_s8_MVE_VHSUB_qr_u16_MVE_VHSUB_qr_u32_MVE_VHSUB_qr_u8 = 1296, |
| 5862 | MVE_VQADD_qr_s16_MVE_VQADD_qr_s32_MVE_VQADD_qr_s8_MVE_VQADD_qr_u16_MVE_VQADD_qr_u32_MVE_VQADD_qr_u8 = 1297, |
| 5863 | MVE_VQSUB_qr_s16_MVE_VQSUB_qr_s32_MVE_VQSUB_qr_s8_MVE_VQSUB_qr_u16_MVE_VQSUB_qr_u32_MVE_VQSUB_qr_u8 = 1298, |
| 5864 | MVE_VSHL_qrs16_MVE_VSHL_qrs32_MVE_VSHL_qrs8_MVE_VSHL_qru16_MVE_VSHL_qru32_MVE_VSHL_qru8 = 1299, |
| 5865 | MVE_VSUB_qr_i16_MVE_VSUB_qr_i32_MVE_VSUB_qr_i8 = 1300, |
| 5866 | MVE_VSHL_by_vecs16_MVE_VSHL_by_vecs32_MVE_VSHL_by_vecs8_MVE_VSHL_by_vecu16_MVE_VSHL_by_vecu32_MVE_VSHL_by_vecu8_MVE_VSHL_immi16_MVE_VSHL_immi32_MVE_VSHL_immi8_MVE_VSHLL_imms16bh_MVE_VSHLL_imms16th_MVE_VSHLL_imms8bh_MVE_VSHLL_imms8th_MVE_VSHLL_immu16bh_MVE_VSHLL_immu16th_MVE_VSHLL_immu8bh_MVE_VSHLL_immu8th_MVE_VSHLL_lws16bh_MVE_VSHLL_lws16th_MVE_VSHLL_lws8bh_MVE_VSHLL_lws8th_MVE_VSHLL_lwu16bh_MVE_VSHLL_lwu16th_MVE_VSHLL_lwu8bh_MVE_VSHLL_lwu8th = 1301, |
| 5867 | MVE_VSHRNi16bh_MVE_VSHRNi16th_MVE_VSHRNi32bh_MVE_VSHRNi32th = 1302, |
| 5868 | MVE_VDWDUPu16_MVE_VDWDUPu32_MVE_VDWDUPu8_MVE_VIWDUPu16_MVE_VIWDUPu32_MVE_VIWDUPu8 = 1303, |
| 5869 | MVE_VDDUPu16_MVE_VDDUPu32_MVE_VDDUPu8_MVE_VIDUPu16_MVE_VIDUPu32_MVE_VIDUPu8 = 1304, |
| 5870 | MVE_VQRSHL_qrs16_MVE_VQRSHL_qrs32_MVE_VQRSHL_qrs8_MVE_VQRSHL_qru16_MVE_VQRSHL_qru32_MVE_VQRSHL_qru8 = 1305, |
| 5871 | MVE_VQSHL_qrs16_MVE_VQSHL_qrs32_MVE_VQSHL_qrs8_MVE_VQSHL_qru16_MVE_VQSHL_qru32_MVE_VQSHL_qru8_MVE_VRSHL_qrs16_MVE_VRSHL_qrs32_MVE_VRSHL_qrs8_MVE_VRSHL_qru16_MVE_VRSHL_qru32_MVE_VRSHL_qru8 = 1306, |
| 5872 | MVE_VMAXNMAf16_MVE_VMAXNMAf32_MVE_VMAXNMf16_MVE_VMAXNMf32_MVE_VMINNMAf16_MVE_VMINNMAf32_MVE_VMINNMf16_MVE_VMINNMf32 = 1307, |
| 5873 | MVE_VADDLVs32acc_MVE_VADDLVu32acc = 1308, |
| 5874 | MVE_VADDVs16acc_MVE_VADDVs32acc_MVE_VADDVs8acc_MVE_VADDVu16acc_MVE_VADDVu32acc_MVE_VADDVu8acc = 1309, |
| 5875 | MVE_VMUL_qr_i16_MVE_VMUL_qr_i32_MVE_VMUL_qr_i8 = 1310, |
| 5876 | MVE_VQDMULH_qr_s16_MVE_VQDMULH_qr_s32_MVE_VQDMULH_qr_s8_MVE_VQRDMULH_qr_s16_MVE_VQRDMULH_qr_s32_MVE_VQRDMULH_qr_s8 = 1311, |
| 5877 | MVE_VMLAS_qr_i16_MVE_VMLAS_qr_i32_MVE_VMLAS_qr_i8_MVE_VMLA_qr_i16_MVE_VMLA_qr_i32_MVE_VMLA_qr_i8 = 1312, |
| 5878 | MVE_VQDMLAH_qrs16_MVE_VQDMLAH_qrs32_MVE_VQDMLAH_qrs8_MVE_VQDMLASH_qrs16_MVE_VQDMLASH_qrs32_MVE_VQDMLASH_qrs8_MVE_VQRDMLAH_qrs16_MVE_VQRDMLAH_qrs32_MVE_VQRDMLAH_qrs8_MVE_VQRDMLASH_qrs16_MVE_VQRDMLASH_qrs32_MVE_VQRDMLASH_qrs8 = 1313, |
| 5879 | MVE_VQDMLADHXs16_MVE_VQDMLADHXs32_MVE_VQDMLADHXs8_MVE_VQDMLADHs16_MVE_VQDMLADHs32_MVE_VQDMLADHs8_MVE_VQDMLSDHXs16_MVE_VQDMLSDHXs32_MVE_VQDMLSDHXs8_MVE_VQDMLSDHs16_MVE_VQDMLSDHs32_MVE_VQDMLSDHs8_MVE_VQRDMLADHXs16_MVE_VQRDMLADHXs32_MVE_VQRDMLADHXs8_MVE_VQRDMLADHs16_MVE_VQRDMLADHs32_MVE_VQRDMLADHs8_MVE_VQRDMLSDHXs16_MVE_VQRDMLSDHXs32_MVE_VQRDMLSDHXs8_MVE_VQRDMLSDHs16_MVE_VQRDMLSDHs32_MVE_VQRDMLSDHs8 = 1314, |
| 5880 | MVE_VMLALDAVas16_MVE_VMLALDAVas32_MVE_VMLALDAVau16_MVE_VMLALDAVau32_MVE_VMLALDAVaxs16_MVE_VMLALDAVaxs32_MVE_VMLSLDAVas16_MVE_VMLSLDAVas32_MVE_VMLSLDAVaxs16_MVE_VMLSLDAVaxs32_MVE_VRMLALDAVHas32_MVE_VRMLALDAVHau32_MVE_VRMLALDAVHaxs32_MVE_VRMLSLDAVHas32_MVE_VRMLSLDAVHaxs32 = 1315, |
| 5881 | MVE_VMLADAVas16_MVE_VMLADAVas32_MVE_VMLADAVas8_MVE_VMLADAVau16_MVE_VMLADAVau32_MVE_VMLADAVau8_MVE_VMLADAVaxs16_MVE_VMLADAVaxs32_MVE_VMLADAVaxs8_MVE_VMLSDAVas16_MVE_VMLSDAVas32_MVE_VMLSDAVas8_MVE_VMLSDAVaxs16_MVE_VMLSDAVaxs32_MVE_VMLSDAVaxs8 = 1316, |
| 5882 | MVE_VMULi16_MVE_VMULi32_MVE_VMULi8 = 1317, |
| 5883 | MVE_VMUL_qr_f16_MVE_VMUL_qr_f32 = 1318, |
| 5884 | MVE_VFMA_qr_Sf16_MVE_VFMA_qr_Sf32_MVE_VFMA_qr_f16_MVE_VFMA_qr_f32 = 1319, |
| 5885 | MVE_VPTv4f32r_MVE_VPTv8f16r = 1320, |
| 5886 | MVE_VPTv16i8r_MVE_VPTv16s8r_MVE_VPTv16u8r_MVE_VPTv4i32r_MVE_VPTv4s32r_MVE_VPTv4u32r_MVE_VPTv8i16r_MVE_VPTv8s16r_MVE_VPTv8u16r = 1321, |
| 5887 | MVE_VCMPi16r_MVE_VCMPi32r_MVE_VCMPi8r_MVE_VCMPs16r_MVE_VCMPs32r_MVE_VCMPs8r_MVE_VCMPu16r_MVE_VCMPu32r_MVE_VCMPu8r = 1322, |
| 5888 | MVE_VCMPf16r_MVE_VCMPf32r = 1323, |
| 5889 | SCHED_LIST_END = 1324 |
| 5890 | }; |
| 5891 | |
| 5892 | } // namespace llvm::ARM::Sched |
| 5893 | |
| 5894 | #endif // GET_INSTRINFO_SCHED_ENUM |
| 5895 | |
| 5896 | #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 5897 | |
| 5898 | namespace llvm { |
| 5899 | |
| 5900 | struct ARMInstrTable { |
| 5901 | MCInstrDesc Insts[4534]; |
| 5902 | static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps"); |
| 5903 | MCPhysReg ImplicitOps[238]; |
| 5904 | char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)]; |
| 5905 | static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); |
| 5906 | MCOperandInfo OperandInfo[3095]; |
| 5907 | }; |
| 5908 | } // namespace llvm |
| 5909 | |
| 5910 | #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 5911 | |
| 5912 | #ifdef GET_INSTRINFO_MC_DESC |
| 5913 | #undef GET_INSTRINFO_MC_DESC |
| 5914 | |
| 5915 | namespace llvm { |
| 5916 | |
| 5917 | static_assert((sizeof ARMInstrTable::ImplicitOps + sizeof ARMInstrTable::Padding) % sizeof(MCOperandInfo) == 0); |
| 5918 | static constexpr unsigned ARMOpInfoBase = (sizeof ARMInstrTable::ImplicitOps + sizeof ARMInstrTable::Padding) / sizeof(MCOperandInfo); |
| 5919 | |
| 5920 | extern const ARMInstrTable ARMDescs = { |
| 5921 | { |
| 5922 | { 4533, 0, 0, 2, 843, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t__brkdiv0 |
| 5923 | { 4532, 4, 1, 2, 896, 0, 0, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tUXTH |
| 5924 | { 4531, 4, 1, 2, 896, 0, 0, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tUXTB |
| 5925 | { 4530, 1, 0, 2, 1089, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tUDF |
| 5926 | { 4529, 4, 0, 2, 1088, 0, 1, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // tTST |
| 5927 | { 4528, 0, 0, 2, 1087, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tTRAP |
| 5928 | { 4527, 4, 1, 2, 896, 0, 0, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tSXTH |
| 5929 | { 4526, 4, 1, 2, 896, 0, 0, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tSXTB |
| 5930 | { 4525, 3, 0, 2, 1214, 1, 0, ARMOpInfoBase + 854, 54, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tSVC |
| 5931 | { 4524, 5, 1, 2, 1273, 0, 0, ARMOpInfoBase + 3027, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tSUBspi |
| 5932 | { 4523, 6, 2, 2, 1076, 0, 0, ARMOpInfoBase + 3021, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tSUBrr |
| 5933 | { 4522, 6, 2, 2, 1107, 0, 0, ARMOpInfoBase + 3005, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tSUBi8 |
| 5934 | { 4521, 6, 2, 2, 1107, 0, 0, ARMOpInfoBase + 2999, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tSUBi3 |
| 5935 | { 4520, 5, 0, 2, 1086, 0, 0, ARMOpInfoBase + 3071, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8aULL }, // tSTRspi |
| 5936 | { 4519, 5, 0, 2, 435, 0, 0, ARMOpInfoBase + 3062, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL }, // tSTRr |
| 5937 | { 4518, 5, 0, 2, 1086, 0, 0, ARMOpInfoBase + 3057, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL }, // tSTRi |
| 5938 | { 4517, 5, 0, 2, 434, 0, 0, ARMOpInfoBase + 3062, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL }, // tSTRHr |
| 5939 | { 4516, 5, 0, 2, 1085, 0, 0, ARMOpInfoBase + 3057, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL }, // tSTRHi |
| 5940 | { 4515, 5, 0, 2, 434, 0, 0, ARMOpInfoBase + 3062, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL }, // tSTRBr |
| 5941 | { 4514, 5, 0, 2, 1085, 0, 0, ARMOpInfoBase + 3057, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL }, // tSTRBi |
| 5942 | { 4513, 5, 1, 2, 1024, 0, 0, ARMOpInfoBase + 557, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // tSTMIA_UPD |
| 5943 | { 4512, 1, 0, 2, 1075, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tSETEND |
| 5944 | { 4511, 6, 2, 2, 1076, 1, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tSBC |
| 5945 | { 4510, 5, 2, 2, 1077, 0, 0, ARMOpInfoBase + 3087, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tRSB |
| 5946 | { 4509, 6, 2, 2, 878, 0, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tROR |
| 5947 | { 4508, 4, 1, 2, 1030, 0, 0, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tREVSH |
| 5948 | { 4507, 4, 1, 2, 1030, 0, 0, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tREV16 |
| 5949 | { 4506, 4, 1, 2, 1030, 0, 0, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tREV |
| 5950 | { 4505, 3, 0, 2, 452, 1, 1, ARMOpInfoBase + 583, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // tPUSH |
| 5951 | { 4504, 3, 0, 2, 424, 1, 1, ARMOpInfoBase + 583, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // tPOP |
| 5952 | { 4503, 3, 1, 2, 1076, 0, 0, ARMOpInfoBase + 3092, 0, 0|(1ULL<<MCID::NotDuplicable), 0xc80ULL }, // tPICADD |
| 5953 | { 4502, 6, 2, 2, 1078, 0, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tORR |
| 5954 | { 4501, 5, 2, 2, 870, 0, 0, ARMOpInfoBase + 3087, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tMVN |
| 5955 | { 4500, 6, 2, 2, 881, 0, 0, ARMOpInfoBase + 3081, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tMUL |
| 5956 | { 4499, 4, 1, 2, 1025, 0, 0, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0xc80ULL }, // tMOVr |
| 5957 | { 4498, 5, 2, 2, 1026, 0, 0, ARMOpInfoBase + 3076, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tMOVi8 |
| 5958 | { 4497, 2, 1, 2, 1084, 0, 1, ARMOpInfoBase + 586, 0, 0|(1ULL<<MCID::MoveReg), 0xc80ULL }, // tMOVSr |
| 5959 | { 4496, 6, 2, 2, 879, 0, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tLSRrr |
| 5960 | { 4495, 6, 2, 2, 1079, 0, 0, ARMOpInfoBase + 2999, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tLSRri |
| 5961 | { 4494, 6, 2, 2, 879, 0, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tLSLrr |
| 5962 | { 4493, 6, 2, 2, 1079, 0, 0, ARMOpInfoBase + 2999, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tLSLri |
| 5963 | { 4492, 5, 1, 2, 1259, 0, 0, ARMOpInfoBase + 3071, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8aULL }, // tLDRspi |
| 5964 | { 4491, 5, 1, 2, 395, 0, 0, ARMOpInfoBase + 3062, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL }, // tLDRr |
| 5965 | { 4490, 4, 1, 2, 1229, 0, 0, ARMOpInfoBase + 3067, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8aULL }, // tLDRpci |
| 5966 | { 4489, 5, 1, 2, 904, 0, 0, ARMOpInfoBase + 3057, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL }, // tLDRi |
| 5967 | { 4488, 5, 1, 2, 401, 0, 0, ARMOpInfoBase + 3062, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc88ULL }, // tLDRSH |
| 5968 | { 4487, 5, 1, 2, 401, 0, 0, ARMOpInfoBase + 3062, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc87ULL }, // tLDRSB |
| 5969 | { 4486, 5, 1, 2, 394, 0, 0, ARMOpInfoBase + 3062, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL }, // tLDRHr |
| 5970 | { 4485, 5, 1, 2, 903, 0, 0, ARMOpInfoBase + 3057, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL }, // tLDRHi |
| 5971 | { 4484, 5, 1, 2, 394, 0, 0, ARMOpInfoBase + 3062, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL }, // tLDRBr |
| 5972 | { 4483, 5, 1, 2, 903, 0, 0, ARMOpInfoBase + 3057, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL }, // tLDRBi |
| 5973 | { 4482, 4, 0, 2, 1016, 0, 0, ARMOpInfoBase + 3053, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // tLDMIA |
| 5974 | { 4481, 2, 0, 12, 1037, 0, 10, ARMOpInfoBase + 586, 228, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tInt_eh_sjlj_setjmp |
| 5975 | { 4480, 2, 0, 0, 1037, 0, 3, ARMOpInfoBase + 586, 5, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tInt_eh_sjlj_longjmp |
| 5976 | { 4479, 2, 0, 12, 849, 0, 3, ARMOpInfoBase + 190, 225, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tInt_WIN_eh_sjlj_longjmp |
| 5977 | { 4478, 1, 0, 2, 1075, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tHLT |
| 5978 | { 4477, 3, 0, 2, 1217, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tHINT |
| 5979 | { 4476, 6, 2, 2, 1078, 0, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tEOR |
| 5980 | { 4475, 2, 0, 2, 1083, 0, 0, ARMOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tCPS |
| 5981 | { 4474, 4, 0, 2, 1081, 0, 1, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // tCMPr |
| 5982 | { 4473, 4, 0, 2, 1082, 0, 1, ARMOpInfoBase + 562, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // tCMPi8 |
| 5983 | { 4472, 4, 0, 2, 1081, 0, 1, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // tCMPhir |
| 5984 | { 4471, 4, 0, 2, 1081, 0, 1, ARMOpInfoBase + 3049, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // tCMN |
| 5985 | { 4470, 2, 0, 2, 1080, 0, 0, ARMOpInfoBase + 3047, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0xc80ULL }, // tCBZ |
| 5986 | { 4469, 2, 0, 2, 1080, 0, 0, ARMOpInfoBase + 3047, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0xc80ULL }, // tCBNZ |
| 5987 | { 4468, 3, 0, 2, 1090, 0, 0, ARMOpInfoBase + 544, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // tBcc |
| 5988 | { 4467, 3, 0, 2, 1090, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // tBXNS |
| 5989 | { 4466, 3, 0, 2, 1090, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // tBX |
| 5990 | { 4465, 3, 0, 2, 1091, 1, 1, ARMOpInfoBase + 3044, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL }, // tBLXr |
| 5991 | { 4464, 3, 0, 4, 854, 1, 1, ARMOpInfoBase + 432, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tBLXi |
| 5992 | { 4463, 3, 0, 2, 1091, 1, 1, ARMOpInfoBase + 3041, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tBLXNSr |
| 5993 | { 4462, 3, 0, 4, 854, 1, 1, ARMOpInfoBase + 432, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL }, // tBL |
| 5994 | { 4461, 1, 0, 2, 1036, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // tBKPT |
| 5995 | { 4460, 6, 2, 2, 1078, 0, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tBIC |
| 5996 | { 4459, 3, 0, 2, 1090, 0, 0, ARMOpInfoBase + 544, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // tB |
| 5997 | { 4458, 6, 2, 2, 879, 0, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tASRrr |
| 5998 | { 4457, 6, 2, 2, 1079, 0, 0, ARMOpInfoBase + 2999, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tASRri |
| 5999 | { 4456, 6, 2, 2, 1078, 0, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tAND |
| 6000 | { 4455, 4, 1, 2, 1077, 0, 0, ARMOpInfoBase + 3037, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tADR |
| 6001 | { 4454, 5, 1, 2, 1278, 0, 0, ARMOpInfoBase + 3032, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tADDspr |
| 6002 | { 4453, 5, 1, 2, 1273, 0, 0, ARMOpInfoBase + 3027, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tADDspi |
| 6003 | { 4452, 6, 2, 2, 1076, 0, 0, ARMOpInfoBase + 3021, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tADDrr |
| 6004 | { 4451, 5, 1, 2, 1279, 0, 0, ARMOpInfoBase + 3016, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tADDrSPi |
| 6005 | { 4450, 5, 1, 2, 1278, 0, 0, ARMOpInfoBase + 3011, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // tADDrSP |
| 6006 | { 4449, 6, 2, 2, 1107, 0, 0, ARMOpInfoBase + 3005, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tADDi8 |
| 6007 | { 4448, 6, 2, 2, 1107, 0, 0, ARMOpInfoBase + 2999, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tADDi3 |
| 6008 | { 4447, 5, 1, 2, 1278, 0, 0, ARMOpInfoBase + 278, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL }, // tADDhirr |
| 6009 | { 4446, 6, 2, 2, 1076, 1, 0, ARMOpInfoBase + 2993, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL }, // tADC |
| 6010 | { 4445, 3, 1, 4, 1284, 0, 0, ARMOpInfoBase + 512, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2WLS |
| 6011 | { 4444, 5, 1, 4, 895, 0, 0, ARMOpInfoBase + 495, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UXTH |
| 6012 | { 4443, 5, 1, 4, 352, 0, 0, ARMOpInfoBase + 495, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UXTB16 |
| 6013 | { 4442, 5, 1, 4, 895, 0, 0, ARMOpInfoBase + 495, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UXTB |
| 6014 | { 4441, 6, 1, 4, 1098, 0, 0, ARMOpInfoBase + 2900, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UXTAH |
| 6015 | { 4440, 6, 1, 4, 1099, 0, 0, ARMOpInfoBase + 2900, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UXTAB16 |
| 6016 | { 4439, 6, 1, 4, 1098, 0, 0, ARMOpInfoBase + 2900, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UXTAB |
| 6017 | { 4438, 5, 1, 4, 883, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2USUB8 |
| 6018 | { 4437, 5, 1, 4, 883, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2USUB16 |
| 6019 | { 4436, 5, 1, 4, 364, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2USAX |
| 6020 | { 4435, 5, 1, 4, 362, 0, 0, ARMOpInfoBase + 2938, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2USAT16 |
| 6021 | { 4434, 6, 1, 4, 362, 0, 0, ARMOpInfoBase + 2932, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2USAT |
| 6022 | { 4433, 6, 1, 4, 682, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2USADA8 |
| 6023 | { 4432, 5, 1, 4, 1244, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2USAD8 |
| 6024 | { 4431, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UQSUB8 |
| 6025 | { 4430, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UQSUB16 |
| 6026 | { 4429, 5, 1, 4, 889, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UQSAX |
| 6027 | { 4428, 5, 1, 4, 889, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UQASX |
| 6028 | { 4427, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UQADD8 |
| 6029 | { 4426, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UQADD16 |
| 6030 | { 4425, 6, 2, 4, 382, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // t2UMULL |
| 6031 | { 4424, 8, 2, 4, 383, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UMLAL |
| 6032 | { 4423, 8, 2, 4, 383, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UMAAL |
| 6033 | { 4422, 5, 1, 4, 885, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UHSUB8 |
| 6034 | { 4421, 5, 1, 4, 885, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UHSUB16 |
| 6035 | { 4420, 5, 1, 4, 367, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UHSAX |
| 6036 | { 4419, 5, 1, 4, 367, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UHASX |
| 6037 | { 4418, 5, 1, 4, 885, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UHADD8 |
| 6038 | { 4417, 5, 1, 4, 885, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UHADD16 |
| 6039 | { 4416, 5, 1, 4, 683, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UDIV |
| 6040 | { 4415, 1, 0, 4, 1035, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2UDF |
| 6041 | { 4414, 6, 1, 4, 893, 0, 0, ARMOpInfoBase + 2918, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2UBFX |
| 6042 | { 4413, 5, 1, 4, 364, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2UASX |
| 6043 | { 4412, 5, 1, 4, 883, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2UADD8 |
| 6044 | { 4411, 5, 1, 4, 883, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2UADD16 |
| 6045 | { 4410, 4, 1, 4, 1055, 0, 0, ARMOpInfoBase + 2989, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TTT |
| 6046 | { 4409, 4, 1, 4, 1055, 0, 0, ARMOpInfoBase + 2989, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TTAT |
| 6047 | { 4408, 4, 1, 4, 1055, 0, 0, ARMOpInfoBase + 2989, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TTA |
| 6048 | { 4407, 4, 1, 4, 1055, 0, 0, ARMOpInfoBase + 2989, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TT |
| 6049 | { 4406, 5, 0, 4, 1240, 0, 1, ARMOpInfoBase + 480, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TSTrs |
| 6050 | { 4405, 4, 0, 4, 1071, 0, 1, ARMOpInfoBase + 2748, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TSTrr |
| 6051 | { 4404, 4, 0, 4, 310, 0, 1, ARMOpInfoBase + 2744, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TSTri |
| 6052 | { 4403, 3, 0, 4, 0, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2TSB |
| 6053 | { 4402, 5, 0, 4, 1240, 0, 1, ARMOpInfoBase + 480, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TEQrs |
| 6054 | { 4401, 4, 0, 4, 1071, 0, 1, ARMOpInfoBase + 2748, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TEQrr |
| 6055 | { 4400, 4, 0, 4, 310, 0, 1, ARMOpInfoBase + 2744, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2TEQri |
| 6056 | { 4399, 4, 0, 4, 1233, 0, 0, ARMOpInfoBase + 2985, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2TBH |
| 6057 | { 4398, 4, 0, 4, 1233, 0, 0, ARMOpInfoBase + 2985, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2TBB |
| 6058 | { 4397, 5, 1, 4, 895, 0, 0, ARMOpInfoBase + 495, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SXTH |
| 6059 | { 4396, 5, 1, 4, 352, 0, 0, ARMOpInfoBase + 495, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SXTB16 |
| 6060 | { 4395, 5, 1, 4, 895, 0, 0, ARMOpInfoBase + 495, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SXTB |
| 6061 | { 4394, 6, 1, 4, 898, 0, 0, ARMOpInfoBase + 2900, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SXTAH |
| 6062 | { 4393, 6, 1, 4, 368, 0, 0, ARMOpInfoBase + 2900, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SXTAB16 |
| 6063 | { 4392, 6, 1, 4, 898, 0, 0, ARMOpInfoBase + 2900, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SXTAB |
| 6064 | { 4391, 5, 1, 4, 1, 0, 0, ARMOpInfoBase + 2739, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SUBspImm12 |
| 6065 | { 4390, 6, 1, 4, 1, 0, 0, ARMOpInfoBase + 2733, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2SUBspImm |
| 6066 | { 4389, 7, 1, 4, 1234, 0, 0, ARMOpInfoBase + 2726, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2SUBrs |
| 6067 | { 4388, 6, 1, 4, 1070, 0, 0, ARMOpInfoBase + 2720, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2SUBrr |
| 6068 | { 4387, 5, 1, 4, 1277, 0, 0, ARMOpInfoBase + 2715, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SUBri12 |
| 6069 | { 4386, 6, 1, 4, 1276, 0, 0, ARMOpInfoBase + 2709, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2SUBri |
| 6070 | { 4385, 3, 0, 4, 1057, 0, 1, ARMOpInfoBase + 854, 70, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // t2SUBS_PC_LR |
| 6071 | { 4384, 6, 0, 4, 431, 0, 0, ARMOpInfoBase + 2839, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2STRs |
| 6072 | { 4383, 5, 0, 4, 430, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2STRi8 |
| 6073 | { 4382, 5, 0, 4, 1072, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2STRi12 |
| 6074 | { 4381, 6, 1, 4, 942, 0, 0, ARMOpInfoBase + 2979, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // t2STR_PRE |
| 6075 | { 4380, 6, 1, 4, 441, 0, 0, ARMOpInfoBase + 2979, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // t2STR_POST |
| 6076 | { 4379, 5, 0, 4, 445, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL }, // t2STRT |
| 6077 | { 4378, 6, 0, 4, 433, 0, 0, ARMOpInfoBase + 2960, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2STRHs |
| 6078 | { 4377, 5, 0, 4, 432, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2STRHi8 |
| 6079 | { 4376, 5, 0, 4, 1073, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2STRHi12 |
| 6080 | { 4375, 6, 1, 4, 942, 0, 0, ARMOpInfoBase + 2954, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // t2STRH_PRE |
| 6081 | { 4374, 6, 1, 4, 442, 0, 0, ARMOpInfoBase + 2954, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // t2STRH_POST |
| 6082 | { 4373, 5, 0, 4, 444, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL }, // t2STRHT |
| 6083 | { 4372, 5, 1, 4, 1226, 0, 0, ARMOpInfoBase + 2943, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STREXH |
| 6084 | { 4371, 6, 1, 4, 728, 0, 0, ARMOpInfoBase + 2948, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // t2STREXD |
| 6085 | { 4370, 5, 1, 4, 1226, 0, 0, ARMOpInfoBase + 2943, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STREXB |
| 6086 | { 4369, 6, 1, 4, 1226, 0, 0, ARMOpInfoBase + 2973, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL }, // t2STREX |
| 6087 | { 4368, 6, 0, 4, 447, 0, 0, ARMOpInfoBase + 2824, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc91ULL }, // t2STRDi8 |
| 6088 | { 4367, 7, 1, 4, 944, 0, 0, ARMOpInfoBase + 2966, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL }, // t2STRD_PRE |
| 6089 | { 4366, 7, 1, 4, 448, 0, 0, ARMOpInfoBase + 2966, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL }, // t2STRD_POST |
| 6090 | { 4365, 6, 0, 4, 433, 0, 0, ARMOpInfoBase + 2960, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2STRBs |
| 6091 | { 4364, 5, 0, 4, 432, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2STRBi8 |
| 6092 | { 4363, 5, 0, 4, 1073, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2STRBi12 |
| 6093 | { 4362, 6, 1, 4, 943, 0, 0, ARMOpInfoBase + 2954, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL }, // t2STRB_PRE |
| 6094 | { 4361, 6, 1, 4, 951, 0, 0, ARMOpInfoBase + 2954, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL }, // t2STRB_POST |
| 6095 | { 4360, 5, 0, 4, 936, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL }, // t2STRBT |
| 6096 | { 4359, 5, 1, 4, 1074, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // t2STMIA_UPD |
| 6097 | { 4358, 4, 0, 4, 1023, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // t2STMIA |
| 6098 | { 4357, 5, 1, 4, 1074, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // t2STMDB_UPD |
| 6099 | { 4356, 4, 0, 4, 1023, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // t2STMDB |
| 6100 | { 4355, 4, 0, 4, 1262, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2STLH |
| 6101 | { 4354, 5, 1, 4, 1262, 0, 0, ARMOpInfoBase + 2943, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STLEXH |
| 6102 | { 4353, 6, 1, 4, 730, 0, 0, ARMOpInfoBase + 2948, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL }, // t2STLEXD |
| 6103 | { 4352, 5, 1, 4, 1262, 0, 0, ARMOpInfoBase + 2943, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STLEXB |
| 6104 | { 4351, 5, 1, 4, 1262, 0, 0, ARMOpInfoBase + 2943, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STLEX |
| 6105 | { 4350, 4, 0, 4, 1262, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2STLB |
| 6106 | { 4349, 4, 0, 4, 1262, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2STL |
| 6107 | { 4348, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STC_PRE |
| 6108 | { 4347, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STC_POST |
| 6109 | { 4346, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STC_OPTION |
| 6110 | { 4345, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // t2STC_OFFSET |
| 6111 | { 4344, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STCL_PRE |
| 6112 | { 4343, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STCL_POST |
| 6113 | { 4342, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STCL_OPTION |
| 6114 | { 4341, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // t2STCL_OFFSET |
| 6115 | { 4340, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STC2_PRE |
| 6116 | { 4339, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STC2_POST |
| 6117 | { 4338, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STC2_OPTION |
| 6118 | { 4337, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // t2STC2_OFFSET |
| 6119 | { 4336, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STC2L_PRE |
| 6120 | { 4335, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STC2L_POST |
| 6121 | { 4334, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2STC2L_OPTION |
| 6122 | { 4333, 6, 0, 4, 1033, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // t2STC2L_OFFSET |
| 6123 | { 4332, 5, 1, 4, 883, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SSUB8 |
| 6124 | { 4331, 5, 1, 4, 883, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SSUB16 |
| 6125 | { 4330, 5, 1, 4, 364, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SSAX |
| 6126 | { 4329, 5, 1, 4, 362, 0, 0, ARMOpInfoBase + 2938, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SSAT16 |
| 6127 | { 4328, 6, 1, 4, 362, 0, 0, ARMOpInfoBase + 2932, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SSAT |
| 6128 | { 4327, 3, 0, 4, 727, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SRSIA_UPD |
| 6129 | { 4326, 3, 0, 4, 727, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SRSIA |
| 6130 | { 4325, 3, 0, 4, 727, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SRSDB_UPD |
| 6131 | { 4324, 3, 0, 4, 727, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SRSDB |
| 6132 | { 4323, 5, 1, 4, 374, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMUSDX |
| 6133 | { 4322, 5, 1, 4, 374, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMUSD |
| 6134 | { 4321, 5, 1, 4, 373, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMULWT |
| 6135 | { 4320, 5, 1, 4, 373, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMULWB |
| 6136 | { 4319, 5, 1, 4, 373, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMULTT |
| 6137 | { 4318, 5, 1, 4, 373, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMULTB |
| 6138 | { 4317, 6, 2, 4, 382, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // t2SMULL |
| 6139 | { 4316, 5, 1, 4, 373, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMULBT |
| 6140 | { 4315, 5, 1, 4, 373, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMULBB |
| 6141 | { 4314, 5, 1, 4, 376, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMUADX |
| 6142 | { 4313, 5, 1, 4, 376, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMUAD |
| 6143 | { 4312, 5, 1, 4, 372, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMMULR |
| 6144 | { 4311, 5, 1, 4, 372, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMMUL |
| 6145 | { 4310, 6, 1, 4, 1097, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMMLSR |
| 6146 | { 4309, 6, 1, 4, 1097, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMMLS |
| 6147 | { 4308, 6, 1, 4, 1097, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMMLAR |
| 6148 | { 4307, 6, 1, 4, 1097, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMMLA |
| 6149 | { 4306, 8, 2, 4, 1029, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLSLDX |
| 6150 | { 4305, 8, 2, 4, 1029, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLSLD |
| 6151 | { 4304, 6, 1, 4, 379, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLSDX |
| 6152 | { 4303, 6, 1, 4, 379, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLSD |
| 6153 | { 4302, 6, 1, 4, 378, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLAWT |
| 6154 | { 4301, 6, 1, 4, 378, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLAWB |
| 6155 | { 4300, 6, 1, 4, 378, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLATT |
| 6156 | { 4299, 6, 1, 4, 378, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLATB |
| 6157 | { 4298, 8, 2, 4, 1029, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLALTT |
| 6158 | { 4297, 8, 2, 4, 1029, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLALTB |
| 6159 | { 4296, 8, 2, 4, 1029, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLALDX |
| 6160 | { 4295, 8, 2, 4, 1029, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLALD |
| 6161 | { 4294, 8, 2, 4, 1029, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLALBT |
| 6162 | { 4293, 8, 2, 4, 1029, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLALBB |
| 6163 | { 4292, 8, 2, 4, 1029, 0, 0, ARMOpInfoBase + 2924, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLAL |
| 6164 | { 4291, 6, 1, 4, 380, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLADX |
| 6165 | { 4290, 6, 1, 4, 380, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLAD |
| 6166 | { 4289, 6, 1, 4, 378, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLABT |
| 6167 | { 4288, 6, 1, 4, 378, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SMLABB |
| 6168 | { 4287, 3, 0, 4, 1216, 1, 0, ARMOpInfoBase + 854, 54, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SMC |
| 6169 | { 4286, 5, 1, 4, 885, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SHSUB8 |
| 6170 | { 4285, 5, 1, 4, 885, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SHSUB16 |
| 6171 | { 4284, 5, 1, 4, 367, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SHSAX |
| 6172 | { 4283, 5, 1, 4, 367, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SHASX |
| 6173 | { 4282, 5, 1, 4, 885, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SHADD8 |
| 6174 | { 4281, 5, 1, 4, 885, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SHADD16 |
| 6175 | { 4280, 2, 0, 4, 1055, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SG |
| 6176 | { 4279, 1, 0, 2, 1075, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SETPAN |
| 6177 | { 4278, 5, 1, 4, 357, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SEL |
| 6178 | { 4277, 5, 1, 4, 683, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SDIV |
| 6179 | { 4276, 6, 1, 4, 893, 0, 0, ARMOpInfoBase + 2918, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2SBFX |
| 6180 | { 4275, 7, 1, 4, 1266, 1, 1, ARMOpInfoBase + 2702, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // t2SBCrs |
| 6181 | { 4274, 6, 1, 4, 1267, 1, 1, ARMOpInfoBase + 2696, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // t2SBCrr |
| 6182 | { 4273, 6, 1, 4, 690, 1, 1, ARMOpInfoBase + 2690, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // t2SBCri |
| 6183 | { 4272, 0, 0, 4, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SB |
| 6184 | { 4271, 5, 1, 4, 364, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SASX |
| 6185 | { 4270, 5, 1, 4, 883, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SADD8 |
| 6186 | { 4269, 5, 1, 4, 883, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2SADD16 |
| 6187 | { 4268, 7, 1, 4, 704, 0, 0, ARMOpInfoBase + 2702, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2RSBrs |
| 6188 | { 4267, 6, 1, 4, 1268, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2RSBrr |
| 6189 | { 4266, 6, 1, 4, 1069, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2RSBri |
| 6190 | { 4265, 5, 1, 4, 1242, 1, 0, ARMOpInfoBase + 2884, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2RRX |
| 6191 | { 4264, 6, 1, 4, 1063, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2RORrr |
| 6192 | { 4263, 6, 1, 4, 872, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2RORri |
| 6193 | { 4262, 3, 0, 4, 727, 0, 1, ARMOpInfoBase + 536, 70, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2RFEIAW |
| 6194 | { 4261, 3, 0, 4, 727, 0, 1, ARMOpInfoBase + 536, 70, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2RFEIA |
| 6195 | { 4260, 3, 0, 4, 727, 0, 1, ARMOpInfoBase + 536, 70, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2RFEDBW |
| 6196 | { 4259, 3, 0, 4, 727, 0, 1, ARMOpInfoBase + 536, 70, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2RFEDB |
| 6197 | { 4258, 4, 1, 4, 1068, 0, 0, ARMOpInfoBase + 2748, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2REVSH |
| 6198 | { 4257, 4, 1, 4, 1068, 0, 0, ARMOpInfoBase + 2748, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2REV16 |
| 6199 | { 4256, 4, 1, 4, 1068, 0, 0, ARMOpInfoBase + 2748, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2REV |
| 6200 | { 4255, 4, 1, 4, 1245, 0, 0, ARMOpInfoBase + 2748, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2RBIT |
| 6201 | { 4254, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QSUB8 |
| 6202 | { 4253, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QSUB16 |
| 6203 | { 4252, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QSUB |
| 6204 | { 4251, 5, 1, 4, 889, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QSAX |
| 6205 | { 4250, 5, 1, 4, 361, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QDSUB |
| 6206 | { 4249, 5, 1, 4, 361, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QDADD |
| 6207 | { 4248, 5, 1, 4, 889, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QASX |
| 6208 | { 4247, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QADD8 |
| 6209 | { 4246, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QADD16 |
| 6210 | { 4245, 5, 1, 4, 887, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2QADD |
| 6211 | { 4244, 5, 0, 4, 1231, 0, 0, ARMOpInfoBase + 2910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2PLIs |
| 6212 | { 4243, 3, 0, 4, 1228, 0, 0, ARMOpInfoBase + 2915, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL }, // t2PLIpci |
| 6213 | { 4242, 4, 0, 4, 1230, 0, 0, ARMOpInfoBase + 2906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2PLIi8 |
| 6214 | { 4241, 4, 0, 4, 1230, 0, 0, ARMOpInfoBase + 2906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2PLIi12 |
| 6215 | { 4240, 5, 0, 4, 1231, 0, 0, ARMOpInfoBase + 2910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2PLDs |
| 6216 | { 4239, 3, 0, 4, 1228, 0, 0, ARMOpInfoBase + 2915, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL }, // t2PLDpci |
| 6217 | { 4238, 4, 0, 4, 1230, 0, 0, ARMOpInfoBase + 2906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2PLDi8 |
| 6218 | { 4237, 4, 0, 4, 1230, 0, 0, ARMOpInfoBase + 2906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2PLDi12 |
| 6219 | { 4236, 5, 0, 4, 932, 0, 0, ARMOpInfoBase + 2910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2PLDWs |
| 6220 | { 4235, 4, 0, 4, 1230, 0, 0, ARMOpInfoBase + 2906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2PLDWi8 |
| 6221 | { 4234, 4, 0, 4, 1230, 0, 0, ARMOpInfoBase + 2906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2PLDWi12 |
| 6222 | { 4233, 6, 1, 4, 1246, 0, 0, ARMOpInfoBase + 2900, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2PKHTB |
| 6223 | { 4232, 6, 1, 4, 1246, 0, 0, ARMOpInfoBase + 2900, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2PKHBT |
| 6224 | { 4231, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 2895, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2PACG |
| 6225 | { 4230, 0, 0, 4, 0, 2, 1, ARMOpInfoBase + 1, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2PACBTI |
| 6226 | { 4229, 0, 0, 4, 0, 2, 1, ARMOpInfoBase + 1, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2PAC |
| 6227 | { 4228, 7, 1, 4, 1236, 0, 0, ARMOpInfoBase + 2702, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ORRrs |
| 6228 | { 4227, 6, 1, 4, 1067, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ORRrr |
| 6229 | { 4226, 6, 1, 4, 692, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ORRri |
| 6230 | { 4225, 7, 1, 4, 1237, 0, 0, ARMOpInfoBase + 2702, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ORNrs |
| 6231 | { 4224, 6, 1, 4, 1271, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ORNrr |
| 6232 | { 4223, 6, 1, 4, 46, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ORNri |
| 6233 | { 4222, 6, 1, 4, 696, 0, 0, ARMOpInfoBase + 2889, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2MVNs |
| 6234 | { 4221, 5, 1, 4, 695, 0, 0, ARMOpInfoBase + 2884, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2MVNr |
| 6235 | { 4220, 5, 1, 4, 694, 0, 0, ARMOpInfoBase + 2858, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // t2MVNi |
| 6236 | { 4219, 5, 1, 4, 1096, 0, 0, ARMOpInfoBase + 2879, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL }, // t2MUL |
| 6237 | { 4218, 4, 0, 4, 1027, 0, 0, ARMOpInfoBase + 2875, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MSRbanked |
| 6238 | { 4217, 4, 0, 4, 1027, 0, 1, ARMOpInfoBase + 2875, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MSR_M |
| 6239 | { 4216, 4, 0, 4, 1027, 0, 1, ARMOpInfoBase + 2875, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MSR_AR |
| 6240 | { 4215, 3, 1, 4, 1027, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MRSsys_AR |
| 6241 | { 4214, 4, 1, 4, 1027, 0, 0, ARMOpInfoBase + 2744, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MRSbanked |
| 6242 | { 4213, 4, 1, 4, 1027, 0, 0, ARMOpInfoBase + 2744, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MRS_M |
| 6243 | { 4212, 3, 1, 4, 1027, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MRS_AR |
| 6244 | { 4211, 7, 2, 4, 1032, 0, 0, ARMOpInfoBase + 2868, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MRRC2 |
| 6245 | { 4210, 7, 2, 4, 1032, 0, 0, ARMOpInfoBase + 2868, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MRRC |
| 6246 | { 4209, 8, 1, 4, 1093, 0, 0, ARMOpInfoBase + 1029, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MRC2 |
| 6247 | { 4208, 8, 1, 4, 1093, 0, 0, ARMOpInfoBase + 1029, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MRC |
| 6248 | { 4207, 5, 1, 4, 877, 0, 0, ARMOpInfoBase + 2863, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2MOVr |
| 6249 | { 4206, 4, 1, 4, 681, 0, 0, ARMOpInfoBase + 2744, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // t2MOVi16 |
| 6250 | { 4205, 5, 1, 4, 681, 0, 0, ARMOpInfoBase + 2858, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL }, // t2MOVi |
| 6251 | { 4204, 5, 1, 4, 876, 0, 0, ARMOpInfoBase + 465, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2MOVTi16 |
| 6252 | { 4203, 6, 1, 4, 375, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2MLS |
| 6253 | { 4202, 6, 1, 4, 375, 0, 0, ARMOpInfoBase + 2852, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2MLA |
| 6254 | { 4201, 7, 0, 4, 1093, 0, 0, ARMOpInfoBase + 2845, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MCRR2 |
| 6255 | { 4200, 7, 0, 4, 1093, 0, 0, ARMOpInfoBase + 2845, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MCRR |
| 6256 | { 4199, 8, 0, 4, 1093, 0, 0, ARMOpInfoBase + 962, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MCR2 |
| 6257 | { 4198, 8, 0, 4, 1093, 0, 0, ARMOpInfoBase + 962, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2MCR |
| 6258 | { 4197, 4, 1, 4, 1241, 0, 1, ARMOpInfoBase + 2748, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2LSRs1 |
| 6259 | { 4196, 6, 1, 4, 1063, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2LSRrr |
| 6260 | { 4195, 6, 1, 4, 1062, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2LSRri |
| 6261 | { 4194, 6, 1, 4, 1063, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2LSLrr |
| 6262 | { 4193, 6, 1, 4, 1062, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2LSLri |
| 6263 | { 4192, 3, 1, 4, 1286, 0, 0, ARMOpInfoBase + 456, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LEUpdate |
| 6264 | { 4191, 1, 0, 4, 1285, 0, 0, ARMOpInfoBase + 192, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LE |
| 6265 | { 4190, 6, 1, 4, 390, 0, 0, ARMOpInfoBase + 2839, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8fULL }, // t2LDRs |
| 6266 | { 4189, 4, 1, 4, 1227, 0, 0, ARMOpInfoBase + 2835, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // t2LDRpci |
| 6267 | { 4188, 5, 1, 4, 389, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL }, // t2LDRi8 |
| 6268 | { 4187, 5, 1, 4, 1104, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8bULL }, // t2LDRi12 |
| 6269 | { 4186, 6, 2, 4, 918, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // t2LDR_PRE |
| 6270 | { 4185, 6, 2, 4, 410, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // t2LDR_POST |
| 6271 | { 4184, 5, 1, 4, 412, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // t2LDRT |
| 6272 | { 4183, 6, 1, 4, 400, 0, 0, ARMOpInfoBase + 2811, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2LDRSHs |
| 6273 | { 4182, 4, 1, 4, 1221, 0, 0, ARMOpInfoBase + 2807, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // t2LDRSHpci |
| 6274 | { 4181, 5, 1, 4, 399, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2LDRSHi8 |
| 6275 | { 4180, 5, 1, 4, 399, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2LDRSHi12 |
| 6276 | { 4179, 6, 2, 4, 917, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // t2LDRSH_PRE |
| 6277 | { 4178, 6, 2, 4, 414, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // t2LDRSH_POST |
| 6278 | { 4177, 5, 1, 4, 415, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // t2LDRSHT |
| 6279 | { 4176, 6, 1, 4, 400, 0, 0, ARMOpInfoBase + 2811, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2LDRSBs |
| 6280 | { 4175, 4, 1, 4, 1221, 0, 0, ARMOpInfoBase + 2807, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // t2LDRSBpci |
| 6281 | { 4174, 5, 1, 4, 399, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2LDRSBi8 |
| 6282 | { 4173, 5, 1, 4, 399, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2LDRSBi12 |
| 6283 | { 4172, 6, 2, 4, 917, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // t2LDRSB_PRE |
| 6284 | { 4171, 6, 2, 4, 414, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // t2LDRSB_POST |
| 6285 | { 4170, 5, 1, 4, 415, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // t2LDRSBT |
| 6286 | { 4169, 6, 1, 4, 392, 0, 0, ARMOpInfoBase + 2811, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2LDRHs |
| 6287 | { 4168, 4, 1, 4, 1220, 0, 0, ARMOpInfoBase + 2807, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // t2LDRHpci |
| 6288 | { 4167, 5, 1, 4, 391, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2LDRHi8 |
| 6289 | { 4166, 5, 1, 4, 1103, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2LDRHi12 |
| 6290 | { 4165, 6, 2, 4, 916, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // t2LDRH_PRE |
| 6291 | { 4164, 6, 2, 4, 409, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // t2LDRH_POST |
| 6292 | { 4163, 5, 1, 4, 411, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // t2LDRHT |
| 6293 | { 4162, 4, 1, 4, 1225, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDREXH |
| 6294 | { 4161, 5, 2, 4, 1022, 0, 0, ARMOpInfoBase + 2797, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL }, // t2LDREXD |
| 6295 | { 4160, 4, 1, 4, 1225, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDREXB |
| 6296 | { 4159, 5, 1, 4, 1224, 0, 0, ARMOpInfoBase + 2830, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL }, // t2LDREX |
| 6297 | { 4158, 6, 2, 4, 416, 0, 0, ARMOpInfoBase + 2824, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc91ULL }, // t2LDRDi8 |
| 6298 | { 4157, 7, 3, 4, 920, 0, 0, ARMOpInfoBase + 2817, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL }, // t2LDRD_PRE |
| 6299 | { 4156, 7, 3, 4, 419, 0, 0, ARMOpInfoBase + 2817, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL }, // t2LDRD_POST |
| 6300 | { 4155, 6, 1, 4, 392, 0, 0, ARMOpInfoBase + 2811, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL }, // t2LDRBs |
| 6301 | { 4154, 4, 1, 4, 1220, 0, 0, ARMOpInfoBase + 2807, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL }, // t2LDRBpci |
| 6302 | { 4153, 5, 1, 4, 391, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL }, // t2LDRBi8 |
| 6303 | { 4152, 5, 1, 4, 1103, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL }, // t2LDRBi12 |
| 6304 | { 4151, 6, 2, 4, 909, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL }, // t2LDRB_PRE |
| 6305 | { 4150, 6, 2, 4, 926, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL }, // t2LDRB_POST |
| 6306 | { 4149, 5, 1, 4, 411, 0, 0, ARMOpInfoBase + 2802, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL }, // t2LDRBT |
| 6307 | { 4148, 5, 1, 4, 1106, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // t2LDMIA_UPD |
| 6308 | { 4147, 4, 0, 4, 1105, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // t2LDMIA |
| 6309 | { 4146, 5, 1, 4, 1106, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // t2LDMDB_UPD |
| 6310 | { 4145, 4, 0, 4, 1105, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL }, // t2LDMDB |
| 6311 | { 4144, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDC_PRE |
| 6312 | { 4143, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDC_POST |
| 6313 | { 4142, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDC_OPTION |
| 6314 | { 4141, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // t2LDC_OFFSET |
| 6315 | { 4140, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDCL_PRE |
| 6316 | { 4139, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDCL_POST |
| 6317 | { 4138, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDCL_OPTION |
| 6318 | { 4137, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // t2LDCL_OFFSET |
| 6319 | { 4136, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDC2_PRE |
| 6320 | { 4135, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDC2_POST |
| 6321 | { 4134, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDC2_OPTION |
| 6322 | { 4133, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // t2LDC2_OFFSET |
| 6323 | { 4132, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDC2L_PRE |
| 6324 | { 4131, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDC2L_POST |
| 6325 | { 4130, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDC2L_OPTION |
| 6326 | { 4129, 6, 0, 4, 845, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL }, // t2LDC2L_OFFSET |
| 6327 | { 4128, 4, 1, 4, 684, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2LDAH |
| 6328 | { 4127, 4, 1, 4, 684, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDAEXH |
| 6329 | { 4126, 5, 2, 4, 1261, 0, 0, ARMOpInfoBase + 2797, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL }, // t2LDAEXD |
| 6330 | { 4125, 4, 1, 4, 684, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDAEXB |
| 6331 | { 4124, 4, 1, 4, 1260, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2LDAEX |
| 6332 | { 4123, 4, 1, 4, 684, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2LDAB |
| 6333 | { 4122, 4, 1, 4, 1260, 0, 0, ARMOpInfoBase + 2793, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2LDA |
| 6334 | { 4121, 2, 0, 12, 1037, 0, 15, ARMOpInfoBase + 586, 39, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2Int_eh_sjlj_setjmp_nofp |
| 6335 | { 4120, 2, 0, 12, 1037, 0, 27, ARMOpInfoBase + 586, 195, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2Int_eh_sjlj_setjmp |
| 6336 | { 4119, 2, 0, 2, 456, 0, 1, ARMOpInfoBase + 9, 194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2IT |
| 6337 | { 4118, 3, 0, 4, 1092, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2ISB |
| 6338 | { 4117, 1, 0, 4, 1215, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2HVC |
| 6339 | { 4116, 3, 0, 4, 1034, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2HINT |
| 6340 | { 4115, 7, 1, 4, 1236, 0, 0, ARMOpInfoBase + 2702, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2EORrs |
| 6341 | { 4114, 6, 1, 4, 1270, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2EORrr |
| 6342 | { 4113, 6, 1, 4, 692, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2EORri |
| 6343 | { 4112, 3, 0, 4, 1092, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2DSB |
| 6344 | { 4111, 3, 0, 4, 1092, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2DMB |
| 6345 | { 4110, 2, 1, 4, 1284, 0, 0, ARMOpInfoBase + 435, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2DLS |
| 6346 | { 4109, 2, 0, 4, 841, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2DCPS3 |
| 6347 | { 4108, 2, 0, 4, 841, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2DCPS2 |
| 6348 | { 4107, 2, 0, 4, 841, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2DCPS1 |
| 6349 | { 4106, 3, 0, 4, 1056, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2DBG |
| 6350 | { 4105, 4, 1, 4, 1060, 1, 0, ARMOpInfoBase + 2789, 0, 0, 0xc80ULL }, // t2CSNEG |
| 6351 | { 4104, 4, 1, 4, 1060, 1, 0, ARMOpInfoBase + 2789, 0, 0, 0xc80ULL }, // t2CSINV |
| 6352 | { 4103, 4, 1, 4, 1060, 1, 0, ARMOpInfoBase + 2789, 0, 0, 0xc80ULL }, // t2CSINC |
| 6353 | { 4102, 4, 1, 4, 1060, 1, 0, ARMOpInfoBase + 2789, 0, 0, 0xc80ULL }, // t2CSEL |
| 6354 | { 4101, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 316, 0, 0, 0xc80ULL }, // t2CRC32W |
| 6355 | { 4100, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 316, 0, 0, 0xc80ULL }, // t2CRC32H |
| 6356 | { 4099, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 316, 0, 0, 0xc80ULL }, // t2CRC32CW |
| 6357 | { 4098, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 316, 0, 0, 0xc80ULL }, // t2CRC32CH |
| 6358 | { 4097, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 316, 0, 0, 0xc80ULL }, // t2CRC32CB |
| 6359 | { 4096, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 316, 0, 0, 0xc80ULL }, // t2CRC32B |
| 6360 | { 4095, 3, 0, 4, 1055, 0, 0, ARMOpInfoBase + 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2CPS3p |
| 6361 | { 4094, 2, 0, 4, 1055, 0, 0, ARMOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2CPS2p |
| 6362 | { 4093, 1, 0, 4, 1055, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2CPS1p |
| 6363 | { 4092, 5, 0, 4, 1239, 0, 1, ARMOpInfoBase + 2784, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2CMPrs |
| 6364 | { 4091, 4, 0, 4, 1066, 0, 1, ARMOpInfoBase + 2780, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2CMPrr |
| 6365 | { 4090, 4, 0, 4, 1065, 0, 1, ARMOpInfoBase + 440, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2CMPri |
| 6366 | { 4089, 5, 0, 4, 1238, 0, 1, ARMOpInfoBase + 2784, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2CMNrs |
| 6367 | { 4088, 4, 0, 4, 1064, 0, 1, ARMOpInfoBase + 2780, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2CMNrr |
| 6368 | { 4087, 4, 0, 4, 55, 0, 1, ARMOpInfoBase + 440, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2CMNri |
| 6369 | { 4086, 4, 1, 4, 1243, 0, 0, ARMOpInfoBase + 2748, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2CLZ |
| 6370 | { 4085, 3, 0, 4, 1102, 0, 0, ARMOpInfoBase + 583, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2CLRM |
| 6371 | { 4084, 2, 0, 4, 1028, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2CLREX |
| 6372 | { 4083, 8, 0, 4, 1031, 0, 0, ARMOpInfoBase + 822, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2CDP2 |
| 6373 | { 4082, 8, 0, 4, 1031, 0, 0, ARMOpInfoBase + 822, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2CDP |
| 6374 | { 4081, 3, 0, 4, 851, 0, 0, ARMOpInfoBase + 544, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // t2Bcc |
| 6375 | { 4080, 3, 0, 4, 861, 0, 0, ARMOpInfoBase + 1055, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2BXJ |
| 6376 | { 4079, 5, 0, 4, 0, 0, 0, ARMOpInfoBase + 2775, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2BXAUT |
| 6377 | { 4078, 0, 0, 4, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2BTI |
| 6378 | { 4077, 7, 1, 4, 1236, 0, 0, ARMOpInfoBase + 2702, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2BICrs |
| 6379 | { 4076, 6, 1, 4, 1270, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2BICrr |
| 6380 | { 4075, 6, 1, 4, 692, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2BICri |
| 6381 | { 4074, 4, 0, 4, 1282, 0, 0, ARMOpInfoBase + 2767, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2BFr |
| 6382 | { 4073, 4, 0, 4, 1282, 0, 0, ARMOpInfoBase + 2771, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2BFic |
| 6383 | { 4072, 4, 0, 4, 1282, 0, 0, ARMOpInfoBase + 2763, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2BFi |
| 6384 | { 4071, 4, 0, 4, 1282, 0, 0, ARMOpInfoBase + 2767, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2BFLr |
| 6385 | { 4070, 4, 0, 4, 1282, 0, 0, ARMOpInfoBase + 2763, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2BFLi |
| 6386 | { 4069, 6, 1, 4, 359, 0, 0, ARMOpInfoBase + 2757, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2BFI |
| 6387 | { 4068, 5, 1, 4, 358, 0, 0, ARMOpInfoBase + 465, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2BFC |
| 6388 | { 4067, 3, 0, 4, 851, 0, 0, ARMOpInfoBase + 544, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL }, // t2B |
| 6389 | { 4066, 5, 0, 4, 0, 0, 0, ARMOpInfoBase + 2752, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2AUTG |
| 6390 | { 4065, 0, 0, 4, 0, 3, 0, ARMOpInfoBase + 1, 191, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // t2AUT |
| 6391 | { 4064, 4, 1, 4, 1241, 0, 1, ARMOpInfoBase + 2748, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2ASRs1 |
| 6392 | { 4063, 6, 1, 4, 1063, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ASRrr |
| 6393 | { 4062, 6, 1, 4, 1062, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ASRri |
| 6394 | { 4061, 7, 1, 4, 703, 0, 0, ARMOpInfoBase + 2702, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ANDrs |
| 6395 | { 4060, 6, 1, 4, 699, 0, 0, ARMOpInfoBase + 2696, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ANDrr |
| 6396 | { 4059, 6, 1, 4, 692, 0, 0, ARMOpInfoBase + 2690, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ANDri |
| 6397 | { 4058, 4, 1, 4, 1, 0, 0, ARMOpInfoBase + 2744, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2ADR |
| 6398 | { 4057, 5, 1, 4, 1, 0, 0, ARMOpInfoBase + 2739, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2ADDspImm12 |
| 6399 | { 4056, 6, 1, 4, 1, 0, 0, ARMOpInfoBase + 2733, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ADDspImm |
| 6400 | { 4055, 7, 1, 4, 702, 0, 0, ARMOpInfoBase + 2726, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ADDrs |
| 6401 | { 4054, 6, 1, 4, 1061, 0, 0, ARMOpInfoBase + 2720, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ADDrr |
| 6402 | { 4053, 5, 1, 4, 1275, 0, 0, ARMOpInfoBase + 2715, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL }, // t2ADDri12 |
| 6403 | { 4052, 6, 1, 4, 1274, 0, 0, ARMOpInfoBase + 2709, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL }, // t2ADDri |
| 6404 | { 4051, 7, 1, 4, 1266, 1, 1, ARMOpInfoBase + 2702, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // t2ADCrs |
| 6405 | { 4050, 6, 1, 4, 1269, 1, 1, ARMOpInfoBase + 2696, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // t2ADCrr |
| 6406 | { 4049, 6, 1, 4, 690, 1, 1, ARMOpInfoBase + 2690, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL }, // t2ADCri |
| 6407 | { 4048, 5, 1, 4, 451, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // sysSTMIB_UPD |
| 6408 | { 4047, 4, 0, 4, 450, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // sysSTMIB |
| 6409 | { 4046, 5, 1, 4, 451, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // sysSTMIA_UPD |
| 6410 | { 4045, 4, 0, 4, 450, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // sysSTMIA |
| 6411 | { 4044, 5, 1, 4, 451, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // sysSTMDB_UPD |
| 6412 | { 4043, 4, 0, 4, 450, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // sysSTMDB |
| 6413 | { 4042, 5, 1, 4, 451, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // sysSTMDA_UPD |
| 6414 | { 4041, 4, 0, 4, 450, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // sysSTMDA |
| 6415 | { 4040, 5, 1, 4, 421, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // sysLDMIB_UPD |
| 6416 | { 4039, 4, 0, 4, 420, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // sysLDMIB |
| 6417 | { 4038, 5, 1, 4, 421, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // sysLDMIA_UPD |
| 6418 | { 4037, 4, 0, 4, 420, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // sysLDMIA |
| 6419 | { 4036, 5, 1, 4, 421, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // sysLDMDB_UPD |
| 6420 | { 4035, 4, 0, 4, 420, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // sysLDMDB |
| 6421 | { 4034, 5, 1, 4, 421, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL }, // sysLDMDA_UPD |
| 6422 | { 4033, 4, 0, 4, 420, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL }, // sysLDMDA |
| 6423 | { 4032, 6, 2, 4, 515, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VZIPq8 |
| 6424 | { 4031, 6, 2, 4, 515, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VZIPq32 |
| 6425 | { 4030, 6, 2, 4, 515, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VZIPq16 |
| 6426 | { 4029, 6, 2, 4, 513, 0, 0, ARMOpInfoBase + 2652, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VZIPd8 |
| 6427 | { 4028, 6, 2, 4, 513, 0, 0, ARMOpInfoBase + 2652, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VZIPd16 |
| 6428 | { 4027, 6, 2, 4, 515, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VUZPq8 |
| 6429 | { 4026, 6, 2, 4, 515, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VUZPq32 |
| 6430 | { 4025, 6, 2, 4, 515, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VUZPq16 |
| 6431 | { 4024, 6, 2, 4, 513, 0, 0, ARMOpInfoBase + 2652, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VUZPd8 |
| 6432 | { 4023, 6, 2, 4, 513, 0, 0, ARMOpInfoBase + 2652, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VUZPd16 |
| 6433 | { 4022, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // VUSMMLA |
| 6434 | { 4021, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 631, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // VUSDOTQI |
| 6435 | { 4020, 4, 1, 4, 50, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // VUSDOTQ |
| 6436 | { 4019, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 626, 0, 0, 0x11280ULL }, // VUSDOTDI |
| 6437 | { 4018, 4, 1, 4, 50, 0, 0, ARMOpInfoBase + 636, 0, 0, 0x11280ULL }, // VUSDOTD |
| 6438 | { 4017, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // VUMMLA |
| 6439 | { 4016, 5, 1, 4, 222, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VULTOS |
| 6440 | { 4015, 5, 1, 4, 221, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VULTOH |
| 6441 | { 4014, 5, 1, 4, 1287, 0, 0, ARMOpInfoBase + 2397, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VULTOD |
| 6442 | { 4013, 4, 1, 4, 563, 0, 0, ARMOpInfoBase + 1687, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VUITOS |
| 6443 | { 4012, 4, 1, 4, 562, 0, 0, ARMOpInfoBase + 2407, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VUITOH |
| 6444 | { 4011, 4, 1, 4, 561, 0, 0, ARMOpInfoBase + 1806, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VUITOD |
| 6445 | { 4010, 5, 1, 4, 222, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VUHTOS |
| 6446 | { 4009, 5, 1, 4, 221, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VUHTOH |
| 6447 | { 4008, 5, 1, 4, 1287, 0, 0, ARMOpInfoBase + 2397, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VUHTOD |
| 6448 | { 4007, 5, 1, 4, 961, 0, 0, ARMOpInfoBase + 631, 0, 0, 0x11280ULL }, // VUDOTQI |
| 6449 | { 4006, 4, 1, 4, 961, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // VUDOTQ |
| 6450 | { 4005, 5, 1, 4, 961, 0, 0, ARMOpInfoBase + 626, 0, 0, 0x11280ULL }, // VUDOTDI |
| 6451 | { 4004, 4, 1, 4, 961, 0, 0, ARMOpInfoBase + 636, 0, 0, 0x11280ULL }, // VUDOTD |
| 6452 | { 4003, 5, 1, 4, 467, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VTSTv8i8 |
| 6453 | { 4002, 5, 1, 4, 466, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VTSTv8i16 |
| 6454 | { 4001, 5, 1, 4, 466, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VTSTv4i32 |
| 6455 | { 4000, 5, 1, 4, 467, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VTSTv4i16 |
| 6456 | { 3999, 5, 1, 4, 467, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VTSTv2i32 |
| 6457 | { 3998, 5, 1, 4, 466, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VTSTv16i8 |
| 6458 | { 3997, 6, 2, 4, 514, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VTRNq8 |
| 6459 | { 3996, 6, 2, 4, 514, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VTRNq32 |
| 6460 | { 3995, 6, 2, 4, 514, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VTRNq16 |
| 6461 | { 3994, 6, 2, 4, 999, 0, 0, ARMOpInfoBase + 2652, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VTRNd8 |
| 6462 | { 3993, 6, 2, 4, 999, 0, 0, ARMOpInfoBase + 2652, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VTRNd32 |
| 6463 | { 3992, 6, 2, 4, 999, 0, 0, ARMOpInfoBase + 2652, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VTRNd16 |
| 6464 | { 3991, 5, 1, 4, 956, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VTOULS |
| 6465 | { 3990, 5, 1, 4, 565, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VTOULH |
| 6466 | { 3989, 5, 1, 4, 564, 0, 0, ARMOpInfoBase + 2397, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOULD |
| 6467 | { 3988, 4, 1, 4, 566, 0, 0, ARMOpInfoBase + 1687, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VTOUIZS |
| 6468 | { 3987, 4, 1, 4, 565, 0, 0, ARMOpInfoBase + 2686, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VTOUIZH |
| 6469 | { 3986, 4, 1, 4, 564, 0, 0, ARMOpInfoBase + 1810, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOUIZD |
| 6470 | { 3985, 4, 1, 4, 566, 1, 0, ARMOpInfoBase + 1687, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOUIRS |
| 6471 | { 3984, 4, 1, 4, 565, 1, 0, ARMOpInfoBase + 1687, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VTOUIRH |
| 6472 | { 3983, 4, 1, 4, 564, 1, 0, ARMOpInfoBase + 1810, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOUIRD |
| 6473 | { 3982, 5, 1, 4, 956, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VTOUHS |
| 6474 | { 3981, 5, 1, 4, 565, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VTOUHH |
| 6475 | { 3980, 5, 1, 4, 564, 0, 0, ARMOpInfoBase + 2397, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOUHD |
| 6476 | { 3979, 5, 1, 4, 956, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VTOSLS |
| 6477 | { 3978, 5, 1, 4, 565, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VTOSLH |
| 6478 | { 3977, 5, 1, 4, 564, 0, 0, ARMOpInfoBase + 2397, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOSLD |
| 6479 | { 3976, 4, 1, 4, 566, 0, 0, ARMOpInfoBase + 1687, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VTOSIZS |
| 6480 | { 3975, 4, 1, 4, 565, 0, 0, ARMOpInfoBase + 2686, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VTOSIZH |
| 6481 | { 3974, 4, 1, 4, 564, 0, 0, ARMOpInfoBase + 1810, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOSIZD |
| 6482 | { 3973, 4, 1, 4, 566, 1, 0, ARMOpInfoBase + 1687, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOSIRS |
| 6483 | { 3972, 4, 1, 4, 565, 1, 0, ARMOpInfoBase + 1687, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VTOSIRH |
| 6484 | { 3971, 4, 1, 4, 564, 1, 0, ARMOpInfoBase + 1810, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOSIRD |
| 6485 | { 3970, 5, 1, 4, 566, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VTOSHS |
| 6486 | { 3969, 5, 1, 4, 565, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VTOSHH |
| 6487 | { 3968, 5, 1, 4, 564, 0, 0, ARMOpInfoBase + 2397, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VTOSHD |
| 6488 | { 3967, 6, 1, 4, 511, 0, 0, ARMOpInfoBase + 2680, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // VTBX4Pseudo |
| 6489 | { 3966, 6, 1, 4, 511, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // VTBX4 |
| 6490 | { 3965, 6, 1, 4, 509, 0, 0, ARMOpInfoBase + 2680, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // VTBX3Pseudo |
| 6491 | { 3964, 6, 1, 4, 509, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // VTBX3 |
| 6492 | { 3963, 6, 1, 4, 507, 0, 0, ARMOpInfoBase + 2674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // VTBX2 |
| 6493 | { 3962, 6, 1, 4, 505, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11480ULL }, // VTBX1 |
| 6494 | { 3961, 5, 1, 4, 510, 0, 0, ARMOpInfoBase + 2669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // VTBL4Pseudo |
| 6495 | { 3960, 5, 1, 4, 510, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // VTBL4 |
| 6496 | { 3959, 5, 1, 4, 508, 0, 0, ARMOpInfoBase + 2669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL }, // VTBL3Pseudo |
| 6497 | { 3958, 5, 1, 4, 508, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // VTBL3 |
| 6498 | { 3957, 5, 1, 4, 506, 0, 0, ARMOpInfoBase + 2664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL }, // VTBL2 |
| 6499 | { 3956, 5, 1, 4, 504, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11480ULL }, // VTBL1 |
| 6500 | { 3955, 6, 2, 4, 512, 0, 0, ARMOpInfoBase + 2658, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // VSWPq |
| 6501 | { 3954, 6, 2, 4, 512, 0, 0, ARMOpInfoBase + 2652, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL }, // VSWPd |
| 6502 | { 3953, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 631, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL }, // VSUDOTQI |
| 6503 | { 3952, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 626, 0, 0, 0x11280ULL }, // VSUDOTDI |
| 6504 | { 3951, 5, 1, 4, 754, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBv8i8 |
| 6505 | { 3950, 5, 1, 4, 460, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBv8i16 |
| 6506 | { 3949, 5, 1, 4, 460, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBv4i32 |
| 6507 | { 3948, 5, 1, 4, 754, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBv4i16 |
| 6508 | { 3947, 5, 1, 4, 460, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBv2i64 |
| 6509 | { 3946, 5, 1, 4, 754, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBv2i32 |
| 6510 | { 3945, 5, 1, 4, 754, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBv1i64 |
| 6511 | { 3944, 5, 1, 4, 460, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBv16i8 |
| 6512 | { 3943, 5, 1, 4, 744, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBhq |
| 6513 | { 3942, 5, 1, 4, 742, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBhd |
| 6514 | { 3941, 5, 1, 4, 743, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBfq |
| 6515 | { 3940, 5, 1, 4, 741, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBfd |
| 6516 | { 3939, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBWuv8i16 |
| 6517 | { 3938, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBWuv4i32 |
| 6518 | { 3937, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBWuv2i64 |
| 6519 | { 3936, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBWsv8i16 |
| 6520 | { 3935, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBWsv4i32 |
| 6521 | { 3934, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBWsv2i64 |
| 6522 | { 3933, 5, 1, 4, 520, 1, 0, ARMOpInfoBase + 1705, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28800ULL }, // VSUBS |
| 6523 | { 3932, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBLuv8i16 |
| 6524 | { 3931, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBLuv4i32 |
| 6525 | { 3930, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBLuv2i64 |
| 6526 | { 3929, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBLsv8i16 |
| 6527 | { 3928, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBLsv4i32 |
| 6528 | { 3927, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBLsv2i64 |
| 6529 | { 3926, 5, 1, 4, 500, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBHNv8i8 |
| 6530 | { 3925, 5, 1, 4, 500, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBHNv4i16 |
| 6531 | { 3924, 5, 1, 4, 500, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VSUBHNv2i32 |
| 6532 | { 3923, 5, 1, 4, 740, 1, 0, ARMOpInfoBase + 1695, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VSUBH |
| 6533 | { 3922, 5, 1, 4, 526, 1, 0, ARMOpInfoBase + 1669, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VSUBD |
| 6534 | { 3921, 5, 1, 4, 748, 1, 0, ARMOpInfoBase + 2190, 73, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VSTR_VPR_pre |
| 6535 | { 3920, 5, 1, 4, 748, 1, 0, ARMOpInfoBase + 2190, 73, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_VPR_post |
| 6536 | { 3919, 4, 0, 4, 748, 1, 0, ARMOpInfoBase + 2186, 73, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_VPR_off |
| 6537 | { 3918, 6, 1, 4, 748, 0, 0, ARMOpInfoBase + 2646, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VSTR_P0_pre |
| 6538 | { 3917, 6, 1, 4, 748, 0, 0, ARMOpInfoBase + 2646, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_P0_post |
| 6539 | { 3916, 5, 0, 4, 748, 0, 0, ARMOpInfoBase + 2206, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_P0_off |
| 6540 | { 3915, 5, 1, 4, 748, 1, 0, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VSTR_FPSCR_pre |
| 6541 | { 3914, 5, 1, 4, 748, 1, 0, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_FPSCR_post |
| 6542 | { 3913, 4, 0, 4, 748, 1, 0, ARMOpInfoBase + 2186, 76, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_FPSCR_off |
| 6543 | { 3912, 6, 1, 4, 748, 0, 0, ARMOpInfoBase + 2640, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VSTR_FPSCR_NZCVQC_pre |
| 6544 | { 3911, 6, 1, 4, 748, 0, 0, ARMOpInfoBase + 2640, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_FPSCR_NZCVQC_post |
| 6545 | { 3910, 5, 0, 4, 748, 0, 0, ARMOpInfoBase + 2195, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_FPSCR_NZCVQC_off |
| 6546 | { 3909, 5, 1, 4, 748, 1, 0, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VSTR_FPCXTS_pre |
| 6547 | { 3908, 5, 1, 4, 748, 1, 0, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_FPCXTS_post |
| 6548 | { 3907, 4, 0, 4, 748, 1, 0, ARMOpInfoBase + 2186, 76, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_FPCXTS_off |
| 6549 | { 3906, 5, 1, 4, 748, 1, 0, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VSTR_FPCXTNS_pre |
| 6550 | { 3905, 5, 1, 4, 748, 1, 0, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_FPCXTNS_post |
| 6551 | { 3904, 4, 0, 4, 748, 1, 0, ARMOpInfoBase + 2186, 76, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VSTR_FPCXTNS_off |
| 6552 | { 3903, 5, 0, 4, 591, 0, 0, ARMOpInfoBase + 2181, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL }, // VSTRS |
| 6553 | { 3902, 5, 0, 4, 747, 0, 0, ARMOpInfoBase + 2176, 0, 0|(1ULL<<MCID::MayStore), 0x18b13ULL }, // VSTRH |
| 6554 | { 3901, 5, 0, 4, 590, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL }, // VSTRD |
| 6555 | { 3900, 5, 1, 4, 968, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL }, // VSTMSIA_UPD |
| 6556 | { 3899, 4, 0, 4, 967, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18b84ULL }, // VSTMSIA |
| 6557 | { 3898, 5, 1, 4, 968, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL }, // VSTMSDB_UPD |
| 6558 | { 3897, 4, 0, 4, 593, 0, 0, ARMOpInfoBase + 2172, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18004ULL }, // VSTMQIA |
| 6559 | { 3896, 5, 1, 4, 597, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL }, // VSTMDIA_UPD |
| 6560 | { 3895, 4, 0, 4, 596, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8b84ULL }, // VSTMDIA |
| 6561 | { 3894, 5, 1, 4, 597, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL }, // VSTMDDB_UPD |
| 6562 | { 3893, 7, 1, 4, 662, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4q8oddPseudo_UPD |
| 6563 | { 3892, 5, 0, 4, 661, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4q8oddPseudo |
| 6564 | { 3891, 10, 1, 4, 835, 0, 0, ARMOpInfoBase + 2630, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4q8_UPD |
| 6565 | { 3890, 7, 1, 4, 662, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4q8Pseudo_UPD |
| 6566 | { 3889, 8, 0, 4, 827, 0, 0, ARMOpInfoBase + 2622, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4q8 |
| 6567 | { 3888, 7, 1, 4, 662, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4q32oddPseudo_UPD |
| 6568 | { 3887, 5, 0, 4, 661, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4q32oddPseudo |
| 6569 | { 3886, 10, 1, 4, 835, 0, 0, ARMOpInfoBase + 2630, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4q32_UPD |
| 6570 | { 3885, 7, 1, 4, 662, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4q32Pseudo_UPD |
| 6571 | { 3884, 8, 0, 4, 827, 0, 0, ARMOpInfoBase + 2622, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4q32 |
| 6572 | { 3883, 7, 1, 4, 662, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4q16oddPseudo_UPD |
| 6573 | { 3882, 5, 0, 4, 661, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4q16oddPseudo |
| 6574 | { 3881, 10, 1, 4, 835, 0, 0, ARMOpInfoBase + 2630, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4q16_UPD |
| 6575 | { 3880, 7, 1, 4, 662, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4q16Pseudo_UPD |
| 6576 | { 3879, 8, 0, 4, 827, 0, 0, ARMOpInfoBase + 2622, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4q16 |
| 6577 | { 3878, 10, 1, 4, 835, 0, 0, ARMOpInfoBase + 2630, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4d8_UPD |
| 6578 | { 3877, 7, 1, 4, 662, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4d8Pseudo_UPD |
| 6579 | { 3876, 5, 0, 4, 829, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4d8Pseudo |
| 6580 | { 3875, 8, 0, 4, 827, 0, 0, ARMOpInfoBase + 2622, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4d8 |
| 6581 | { 3874, 10, 1, 4, 835, 0, 0, ARMOpInfoBase + 2630, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4d32_UPD |
| 6582 | { 3873, 7, 1, 4, 662, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4d32Pseudo_UPD |
| 6583 | { 3872, 5, 0, 4, 829, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4d32Pseudo |
| 6584 | { 3871, 8, 0, 4, 827, 0, 0, ARMOpInfoBase + 2622, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4d32 |
| 6585 | { 3870, 10, 1, 4, 835, 0, 0, ARMOpInfoBase + 2630, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4d16_UPD |
| 6586 | { 3869, 7, 1, 4, 662, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4d16Pseudo_UPD |
| 6587 | { 3868, 5, 0, 4, 829, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4d16Pseudo |
| 6588 | { 3867, 8, 0, 4, 827, 0, 0, ARMOpInfoBase + 2622, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4d16 |
| 6589 | { 3866, 11, 1, 4, 673, 0, 0, ARMOpInfoBase + 2611, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNq32_UPD |
| 6590 | { 3865, 8, 1, 4, 674, 0, 0, ARMOpInfoBase + 2578, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNq32Pseudo_UPD |
| 6591 | { 3864, 6, 0, 4, 672, 0, 0, ARMOpInfoBase + 2572, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNq32Pseudo |
| 6592 | { 3863, 9, 0, 4, 833, 0, 0, ARMOpInfoBase + 2602, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNq32 |
| 6593 | { 3862, 11, 1, 4, 673, 0, 0, ARMOpInfoBase + 2611, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNq16_UPD |
| 6594 | { 3861, 8, 1, 4, 674, 0, 0, ARMOpInfoBase + 2578, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNq16Pseudo_UPD |
| 6595 | { 3860, 6, 0, 4, 672, 0, 0, ARMOpInfoBase + 2572, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNq16Pseudo |
| 6596 | { 3859, 9, 0, 4, 833, 0, 0, ARMOpInfoBase + 2602, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNq16 |
| 6597 | { 3858, 11, 1, 4, 837, 0, 0, ARMOpInfoBase + 2611, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNd8_UPD |
| 6598 | { 3857, 8, 1, 4, 839, 0, 0, ARMOpInfoBase + 2539, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNd8Pseudo_UPD |
| 6599 | { 3856, 6, 0, 4, 832, 0, 0, ARMOpInfoBase + 2533, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNd8Pseudo |
| 6600 | { 3855, 9, 0, 4, 830, 0, 0, ARMOpInfoBase + 2602, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNd8 |
| 6601 | { 3854, 11, 1, 4, 837, 0, 0, ARMOpInfoBase + 2611, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNd32_UPD |
| 6602 | { 3853, 8, 1, 4, 839, 0, 0, ARMOpInfoBase + 2539, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNd32Pseudo_UPD |
| 6603 | { 3852, 6, 0, 4, 832, 0, 0, ARMOpInfoBase + 2533, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNd32Pseudo |
| 6604 | { 3851, 9, 0, 4, 830, 0, 0, ARMOpInfoBase + 2602, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNd32 |
| 6605 | { 3850, 11, 1, 4, 837, 0, 0, ARMOpInfoBase + 2611, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNd16_UPD |
| 6606 | { 3849, 8, 1, 4, 839, 0, 0, ARMOpInfoBase + 2539, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNd16Pseudo_UPD |
| 6607 | { 3848, 6, 0, 4, 832, 0, 0, ARMOpInfoBase + 2533, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST4LNd16Pseudo |
| 6608 | { 3847, 9, 0, 4, 830, 0, 0, ARMOpInfoBase + 2602, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST4LNd16 |
| 6609 | { 3846, 7, 1, 4, 660, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3q8oddPseudo_UPD |
| 6610 | { 3845, 5, 0, 4, 659, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3q8oddPseudo |
| 6611 | { 3844, 9, 1, 4, 821, 0, 0, ARMOpInfoBase + 2593, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3q8_UPD |
| 6612 | { 3843, 7, 1, 4, 660, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3q8Pseudo_UPD |
| 6613 | { 3842, 7, 0, 4, 814, 0, 0, ARMOpInfoBase + 2586, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3q8 |
| 6614 | { 3841, 7, 1, 4, 660, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3q32oddPseudo_UPD |
| 6615 | { 3840, 5, 0, 4, 659, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3q32oddPseudo |
| 6616 | { 3839, 9, 1, 4, 821, 0, 0, ARMOpInfoBase + 2593, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3q32_UPD |
| 6617 | { 3838, 7, 1, 4, 660, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3q32Pseudo_UPD |
| 6618 | { 3837, 7, 0, 4, 814, 0, 0, ARMOpInfoBase + 2586, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3q32 |
| 6619 | { 3836, 7, 1, 4, 660, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3q16oddPseudo_UPD |
| 6620 | { 3835, 5, 0, 4, 659, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3q16oddPseudo |
| 6621 | { 3834, 9, 1, 4, 821, 0, 0, ARMOpInfoBase + 2593, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3q16_UPD |
| 6622 | { 3833, 7, 1, 4, 660, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3q16Pseudo_UPD |
| 6623 | { 3832, 7, 0, 4, 814, 0, 0, ARMOpInfoBase + 2586, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3q16 |
| 6624 | { 3831, 9, 1, 4, 821, 0, 0, ARMOpInfoBase + 2593, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3d8_UPD |
| 6625 | { 3830, 7, 1, 4, 660, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3d8Pseudo_UPD |
| 6626 | { 3829, 5, 0, 4, 816, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3d8Pseudo |
| 6627 | { 3828, 7, 0, 4, 814, 0, 0, ARMOpInfoBase + 2586, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3d8 |
| 6628 | { 3827, 9, 1, 4, 821, 0, 0, ARMOpInfoBase + 2593, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3d32_UPD |
| 6629 | { 3826, 7, 1, 4, 660, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3d32Pseudo_UPD |
| 6630 | { 3825, 5, 0, 4, 816, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3d32Pseudo |
| 6631 | { 3824, 7, 0, 4, 814, 0, 0, ARMOpInfoBase + 2586, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3d32 |
| 6632 | { 3823, 9, 1, 4, 821, 0, 0, ARMOpInfoBase + 2593, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3d16_UPD |
| 6633 | { 3822, 7, 1, 4, 660, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3d16Pseudo_UPD |
| 6634 | { 3821, 5, 0, 4, 816, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3d16Pseudo |
| 6635 | { 3820, 7, 0, 4, 814, 0, 0, ARMOpInfoBase + 2586, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3d16 |
| 6636 | { 3819, 10, 1, 4, 670, 0, 0, ARMOpInfoBase + 2562, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNq32_UPD |
| 6637 | { 3818, 8, 1, 4, 671, 0, 0, ARMOpInfoBase + 2578, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNq32Pseudo_UPD |
| 6638 | { 3817, 6, 0, 4, 669, 0, 0, ARMOpInfoBase + 2572, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNq32Pseudo |
| 6639 | { 3816, 8, 0, 4, 668, 0, 0, ARMOpInfoBase + 2554, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNq32 |
| 6640 | { 3815, 10, 1, 4, 670, 0, 0, ARMOpInfoBase + 2562, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNq16_UPD |
| 6641 | { 3814, 8, 1, 4, 671, 0, 0, ARMOpInfoBase + 2578, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNq16Pseudo_UPD |
| 6642 | { 3813, 6, 0, 4, 669, 0, 0, ARMOpInfoBase + 2572, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNq16Pseudo |
| 6643 | { 3812, 8, 0, 4, 668, 0, 0, ARMOpInfoBase + 2554, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNq16 |
| 6644 | { 3811, 10, 1, 4, 823, 0, 0, ARMOpInfoBase + 2562, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNd8_UPD |
| 6645 | { 3810, 8, 1, 4, 825, 0, 0, ARMOpInfoBase + 2539, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNd8Pseudo_UPD |
| 6646 | { 3809, 6, 0, 4, 819, 0, 0, ARMOpInfoBase + 2533, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNd8Pseudo |
| 6647 | { 3808, 8, 0, 4, 817, 0, 0, ARMOpInfoBase + 2554, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNd8 |
| 6648 | { 3807, 10, 1, 4, 823, 0, 0, ARMOpInfoBase + 2562, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNd32_UPD |
| 6649 | { 3806, 8, 1, 4, 825, 0, 0, ARMOpInfoBase + 2539, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNd32Pseudo_UPD |
| 6650 | { 3805, 6, 0, 4, 819, 0, 0, ARMOpInfoBase + 2533, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNd32Pseudo |
| 6651 | { 3804, 8, 0, 4, 817, 0, 0, ARMOpInfoBase + 2554, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNd32 |
| 6652 | { 3803, 10, 1, 4, 823, 0, 0, ARMOpInfoBase + 2562, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNd16_UPD |
| 6653 | { 3802, 8, 1, 4, 825, 0, 0, ARMOpInfoBase + 2539, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNd16Pseudo_UPD |
| 6654 | { 3801, 6, 0, 4, 819, 0, 0, ARMOpInfoBase + 2533, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST3LNd16Pseudo |
| 6655 | { 3800, 8, 0, 4, 817, 0, 0, ARMOpInfoBase + 2554, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST3LNd16 |
| 6656 | { 3799, 7, 1, 4, 657, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2q8wb_register |
| 6657 | { 3798, 6, 1, 4, 657, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2q8wb_fixed |
| 6658 | { 3797, 7, 1, 4, 658, 0, 0, ARMOpInfoBase + 2547, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2q8PseudoWB_register |
| 6659 | { 3796, 6, 1, 4, 658, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2q8PseudoWB_fixed |
| 6660 | { 3795, 5, 0, 4, 656, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2q8Pseudo |
| 6661 | { 3794, 5, 0, 4, 804, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2q8 |
| 6662 | { 3793, 7, 1, 4, 657, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2q32wb_register |
| 6663 | { 3792, 6, 1, 4, 657, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2q32wb_fixed |
| 6664 | { 3791, 7, 1, 4, 658, 0, 0, ARMOpInfoBase + 2547, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2q32PseudoWB_register |
| 6665 | { 3790, 6, 1, 4, 658, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2q32PseudoWB_fixed |
| 6666 | { 3789, 5, 0, 4, 656, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2q32Pseudo |
| 6667 | { 3788, 5, 0, 4, 804, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2q32 |
| 6668 | { 3787, 7, 1, 4, 657, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2q16wb_register |
| 6669 | { 3786, 6, 1, 4, 657, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2q16wb_fixed |
| 6670 | { 3785, 7, 1, 4, 658, 0, 0, ARMOpInfoBase + 2547, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2q16PseudoWB_register |
| 6671 | { 3784, 6, 1, 4, 658, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2q16PseudoWB_fixed |
| 6672 | { 3783, 5, 0, 4, 656, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2q16Pseudo |
| 6673 | { 3782, 5, 0, 4, 804, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2q16 |
| 6674 | { 3781, 7, 1, 4, 655, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2d8wb_register |
| 6675 | { 3780, 6, 1, 4, 655, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2d8wb_fixed |
| 6676 | { 3779, 5, 0, 4, 654, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2d8 |
| 6677 | { 3778, 7, 1, 4, 655, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2d32wb_register |
| 6678 | { 3777, 6, 1, 4, 655, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2d32wb_fixed |
| 6679 | { 3776, 5, 0, 4, 654, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2d32 |
| 6680 | { 3775, 7, 1, 4, 655, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2d16wb_register |
| 6681 | { 3774, 6, 1, 4, 655, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2d16wb_fixed |
| 6682 | { 3773, 5, 0, 4, 654, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2d16 |
| 6683 | { 3772, 7, 1, 4, 655, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2b8wb_register |
| 6684 | { 3771, 6, 1, 4, 655, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2b8wb_fixed |
| 6685 | { 3770, 5, 0, 4, 653, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2b8 |
| 6686 | { 3769, 7, 1, 4, 655, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2b32wb_register |
| 6687 | { 3768, 6, 1, 4, 655, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2b32wb_fixed |
| 6688 | { 3767, 5, 0, 4, 653, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2b32 |
| 6689 | { 3766, 7, 1, 4, 655, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2b16wb_register |
| 6690 | { 3765, 6, 1, 4, 655, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2b16wb_fixed |
| 6691 | { 3764, 5, 0, 4, 653, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2b16 |
| 6692 | { 3763, 9, 1, 4, 666, 0, 0, ARMOpInfoBase + 2524, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNq32_UPD |
| 6693 | { 3762, 8, 1, 4, 667, 0, 0, ARMOpInfoBase + 2539, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNq32Pseudo_UPD |
| 6694 | { 3761, 6, 0, 4, 665, 0, 0, ARMOpInfoBase + 2533, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNq32Pseudo |
| 6695 | { 3760, 7, 0, 4, 808, 0, 0, ARMOpInfoBase + 2517, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNq32 |
| 6696 | { 3759, 9, 1, 4, 666, 0, 0, ARMOpInfoBase + 2524, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNq16_UPD |
| 6697 | { 3758, 8, 1, 4, 667, 0, 0, ARMOpInfoBase + 2539, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNq16Pseudo_UPD |
| 6698 | { 3757, 6, 0, 4, 665, 0, 0, ARMOpInfoBase + 2533, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNq16Pseudo |
| 6699 | { 3756, 7, 0, 4, 808, 0, 0, ARMOpInfoBase + 2517, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNq16 |
| 6700 | { 3755, 9, 1, 4, 810, 0, 0, ARMOpInfoBase + 2524, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNd8_UPD |
| 6701 | { 3754, 8, 1, 4, 812, 0, 0, ARMOpInfoBase + 2443, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNd8Pseudo_UPD |
| 6702 | { 3753, 6, 0, 4, 807, 0, 0, ARMOpInfoBase + 2437, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNd8Pseudo |
| 6703 | { 3752, 7, 0, 4, 805, 0, 0, ARMOpInfoBase + 2517, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNd8 |
| 6704 | { 3751, 9, 1, 4, 810, 0, 0, ARMOpInfoBase + 2524, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNd32_UPD |
| 6705 | { 3750, 8, 1, 4, 812, 0, 0, ARMOpInfoBase + 2443, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNd32Pseudo_UPD |
| 6706 | { 3749, 6, 0, 4, 807, 0, 0, ARMOpInfoBase + 2437, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNd32Pseudo |
| 6707 | { 3748, 7, 0, 4, 805, 0, 0, ARMOpInfoBase + 2517, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNd32 |
| 6708 | { 3747, 9, 1, 4, 810, 0, 0, ARMOpInfoBase + 2524, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNd16_UPD |
| 6709 | { 3746, 8, 1, 4, 812, 0, 0, ARMOpInfoBase + 2443, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNd16Pseudo_UPD |
| 6710 | { 3745, 6, 0, 4, 807, 0, 0, ARMOpInfoBase + 2437, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST2LNd16Pseudo |
| 6711 | { 3744, 7, 0, 4, 805, 0, 0, ARMOpInfoBase + 2517, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST2LNd16 |
| 6712 | { 3743, 7, 1, 4, 646, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q8wb_register |
| 6713 | { 3742, 6, 1, 4, 646, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q8wb_fixed |
| 6714 | { 3741, 7, 1, 4, 1051, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q8LowTPseudo_UPD |
| 6715 | { 3740, 7, 1, 4, 1053, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q8LowQPseudo_UPD |
| 6716 | { 3739, 7, 1, 4, 1051, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q8HighTPseudo_UPD |
| 6717 | { 3738, 5, 0, 4, 1051, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q8HighTPseudo |
| 6718 | { 3737, 7, 1, 4, 1053, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q8HighQPseudo_UPD |
| 6719 | { 3736, 5, 0, 4, 1053, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q8HighQPseudo |
| 6720 | { 3735, 5, 0, 4, 644, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q8 |
| 6721 | { 3734, 7, 1, 4, 646, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q64wb_register |
| 6722 | { 3733, 6, 1, 4, 646, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q64wb_fixed |
| 6723 | { 3732, 7, 1, 4, 1051, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q64LowTPseudo_UPD |
| 6724 | { 3731, 7, 1, 4, 1053, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q64LowQPseudo_UPD |
| 6725 | { 3730, 7, 1, 4, 1051, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q64HighTPseudo_UPD |
| 6726 | { 3729, 5, 0, 4, 1051, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q64HighTPseudo |
| 6727 | { 3728, 7, 1, 4, 1053, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q64HighQPseudo_UPD |
| 6728 | { 3727, 5, 0, 4, 1053, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q64HighQPseudo |
| 6729 | { 3726, 5, 0, 4, 644, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q64 |
| 6730 | { 3725, 7, 1, 4, 646, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q32wb_register |
| 6731 | { 3724, 6, 1, 4, 646, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q32wb_fixed |
| 6732 | { 3723, 7, 1, 4, 1051, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q32LowTPseudo_UPD |
| 6733 | { 3722, 7, 1, 4, 1053, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q32LowQPseudo_UPD |
| 6734 | { 3721, 7, 1, 4, 1051, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q32HighTPseudo_UPD |
| 6735 | { 3720, 5, 0, 4, 1051, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q32HighTPseudo |
| 6736 | { 3719, 7, 1, 4, 1053, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q32HighQPseudo_UPD |
| 6737 | { 3718, 5, 0, 4, 1053, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q32HighQPseudo |
| 6738 | { 3717, 5, 0, 4, 644, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q32 |
| 6739 | { 3716, 7, 1, 4, 646, 0, 0, ARMOpInfoBase + 2510, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q16wb_register |
| 6740 | { 3715, 6, 1, 4, 646, 0, 0, ARMOpInfoBase + 2504, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q16wb_fixed |
| 6741 | { 3714, 7, 1, 4, 1051, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q16LowTPseudo_UPD |
| 6742 | { 3713, 7, 1, 4, 1053, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q16LowQPseudo_UPD |
| 6743 | { 3712, 7, 1, 4, 1051, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q16HighTPseudo_UPD |
| 6744 | { 3711, 5, 0, 4, 1051, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q16HighTPseudo |
| 6745 | { 3710, 7, 1, 4, 1053, 0, 0, ARMOpInfoBase + 2497, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q16HighQPseudo_UPD |
| 6746 | { 3709, 5, 0, 4, 1053, 0, 0, ARMOpInfoBase + 2492, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1q16HighQPseudo |
| 6747 | { 3708, 5, 0, 4, 644, 0, 0, ARMOpInfoBase + 2487, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1q16 |
| 6748 | { 3707, 7, 1, 4, 645, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d8wb_register |
| 6749 | { 3706, 6, 1, 4, 645, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d8wb_fixed |
| 6750 | { 3705, 7, 1, 4, 648, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d8Twb_register |
| 6751 | { 3704, 6, 1, 4, 648, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d8Twb_fixed |
| 6752 | { 3703, 7, 1, 4, 1052, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d8TPseudoWB_register |
| 6753 | { 3702, 6, 1, 4, 1052, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d8TPseudoWB_fixed |
| 6754 | { 3701, 5, 0, 4, 1051, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d8TPseudo |
| 6755 | { 3700, 5, 0, 4, 796, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d8T |
| 6756 | { 3699, 7, 1, 4, 652, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d8Qwb_register |
| 6757 | { 3698, 6, 1, 4, 652, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d8Qwb_fixed |
| 6758 | { 3697, 7, 1, 4, 651, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d8QPseudoWB_register |
| 6759 | { 3696, 6, 1, 4, 651, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d8QPseudoWB_fixed |
| 6760 | { 3695, 5, 0, 4, 650, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d8QPseudo |
| 6761 | { 3694, 5, 0, 4, 797, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d8Q |
| 6762 | { 3693, 5, 0, 4, 643, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d8 |
| 6763 | { 3692, 7, 1, 4, 645, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d64wb_register |
| 6764 | { 3691, 6, 1, 4, 645, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d64wb_fixed |
| 6765 | { 3690, 7, 1, 4, 648, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d64Twb_register |
| 6766 | { 3689, 6, 1, 4, 648, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d64Twb_fixed |
| 6767 | { 3688, 7, 1, 4, 649, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d64TPseudoWB_register |
| 6768 | { 3687, 6, 1, 4, 649, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d64TPseudoWB_fixed |
| 6769 | { 3686, 5, 0, 4, 647, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d64TPseudo |
| 6770 | { 3685, 5, 0, 4, 796, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d64T |
| 6771 | { 3684, 7, 1, 4, 652, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d64Qwb_register |
| 6772 | { 3683, 6, 1, 4, 652, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d64Qwb_fixed |
| 6773 | { 3682, 7, 1, 4, 801, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d64QPseudoWB_register |
| 6774 | { 3681, 6, 1, 4, 801, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d64QPseudoWB_fixed |
| 6775 | { 3680, 5, 0, 4, 798, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d64QPseudo |
| 6776 | { 3679, 5, 0, 4, 797, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d64Q |
| 6777 | { 3678, 5, 0, 4, 643, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d64 |
| 6778 | { 3677, 7, 1, 4, 645, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d32wb_register |
| 6779 | { 3676, 6, 1, 4, 645, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d32wb_fixed |
| 6780 | { 3675, 7, 1, 4, 648, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d32Twb_register |
| 6781 | { 3674, 6, 1, 4, 648, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d32Twb_fixed |
| 6782 | { 3673, 7, 1, 4, 1052, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d32TPseudoWB_register |
| 6783 | { 3672, 6, 1, 4, 1052, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d32TPseudoWB_fixed |
| 6784 | { 3671, 5, 0, 4, 1051, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d32TPseudo |
| 6785 | { 3670, 5, 0, 4, 796, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d32T |
| 6786 | { 3669, 7, 1, 4, 652, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d32Qwb_register |
| 6787 | { 3668, 6, 1, 4, 652, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d32Qwb_fixed |
| 6788 | { 3667, 7, 1, 4, 651, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d32QPseudoWB_register |
| 6789 | { 3666, 6, 1, 4, 651, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d32QPseudoWB_fixed |
| 6790 | { 3665, 5, 0, 4, 650, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d32QPseudo |
| 6791 | { 3664, 5, 0, 4, 797, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d32Q |
| 6792 | { 3663, 5, 0, 4, 643, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d32 |
| 6793 | { 3662, 7, 1, 4, 645, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d16wb_register |
| 6794 | { 3661, 6, 1, 4, 645, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d16wb_fixed |
| 6795 | { 3660, 7, 1, 4, 648, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d16Twb_register |
| 6796 | { 3659, 6, 1, 4, 648, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d16Twb_fixed |
| 6797 | { 3658, 7, 1, 4, 1052, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d16TPseudoWB_register |
| 6798 | { 3657, 6, 1, 4, 1052, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d16TPseudoWB_fixed |
| 6799 | { 3656, 5, 0, 4, 1051, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d16TPseudo |
| 6800 | { 3655, 5, 0, 4, 796, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d16T |
| 6801 | { 3654, 7, 1, 4, 652, 0, 0, ARMOpInfoBase + 2480, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d16Qwb_register |
| 6802 | { 3653, 6, 1, 4, 652, 0, 0, ARMOpInfoBase + 2474, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d16Qwb_fixed |
| 6803 | { 3652, 7, 1, 4, 651, 0, 0, ARMOpInfoBase + 2467, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d16QPseudoWB_register |
| 6804 | { 3651, 6, 1, 4, 651, 0, 0, ARMOpInfoBase + 2461, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d16QPseudoWB_fixed |
| 6805 | { 3650, 5, 0, 4, 650, 0, 0, ARMOpInfoBase + 2456, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL }, // VST1d16QPseudo |
| 6806 | { 3649, 5, 0, 4, 797, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d16Q |
| 6807 | { 3648, 5, 0, 4, 643, 0, 0, ARMOpInfoBase + 2451, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL }, // VST1d16 |
| 6808 | { 3647, 8, 1, 4, 664, 0, 0, ARMOpInfoBase + 2443, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // VST1LNq8Pseudo_UPD |
| 6809 | { 3646, 6, 0, 4, 663, 0, 0, ARMOpInfoBase + 2437, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // VST1LNq8Pseudo |
| 6810 | { 3645, 8, 1, 4, 664, 0, 0, ARMOpInfoBase + 2443, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // VST1LNq32Pseudo_UPD |
| 6811 | { 3644, 6, 0, 4, 663, 0, 0, ARMOpInfoBase + 2437, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // VST1LNq32Pseudo |
| 6812 | { 3643, 8, 1, 4, 664, 0, 0, ARMOpInfoBase + 2443, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // VST1LNq16Pseudo_UPD |
| 6813 | { 3642, 6, 0, 4, 663, 0, 0, ARMOpInfoBase + 2437, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL }, // VST1LNq16Pseudo |
| 6814 | { 3641, 8, 1, 4, 802, 0, 0, ARMOpInfoBase + 2429, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VST1LNd8_UPD |
| 6815 | { 3640, 6, 0, 4, 799, 0, 0, ARMOpInfoBase + 2423, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VST1LNd8 |
| 6816 | { 3639, 8, 1, 4, 802, 0, 0, ARMOpInfoBase + 2429, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VST1LNd32_UPD |
| 6817 | { 3638, 6, 0, 4, 799, 0, 0, ARMOpInfoBase + 2423, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VST1LNd32 |
| 6818 | { 3637, 8, 1, 4, 802, 0, 0, ARMOpInfoBase + 2429, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VST1LNd16_UPD |
| 6819 | { 3636, 6, 0, 4, 799, 0, 0, ARMOpInfoBase + 2423, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VST1LNd16 |
| 6820 | { 3635, 6, 1, 4, 987, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRIv8i8 |
| 6821 | { 3634, 6, 1, 4, 988, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRIv8i16 |
| 6822 | { 3633, 6, 1, 4, 988, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRIv4i32 |
| 6823 | { 3632, 6, 1, 4, 987, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRIv4i16 |
| 6824 | { 3631, 6, 1, 4, 988, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRIv2i64 |
| 6825 | { 3630, 6, 1, 4, 987, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRIv2i32 |
| 6826 | { 3629, 6, 1, 4, 987, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRIv1i64 |
| 6827 | { 3628, 6, 1, 4, 988, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRIv16i8 |
| 6828 | { 3627, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAuv8i8 |
| 6829 | { 3626, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAuv8i16 |
| 6830 | { 3625, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAuv4i32 |
| 6831 | { 3624, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAuv4i16 |
| 6832 | { 3623, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAuv2i64 |
| 6833 | { 3622, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAuv2i32 |
| 6834 | { 3621, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAuv1i64 |
| 6835 | { 3620, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAuv16i8 |
| 6836 | { 3619, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAsv8i8 |
| 6837 | { 3618, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAsv8i16 |
| 6838 | { 3617, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAsv4i32 |
| 6839 | { 3616, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAsv4i16 |
| 6840 | { 3615, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAsv2i64 |
| 6841 | { 3614, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAsv2i32 |
| 6842 | { 3613, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAsv1i64 |
| 6843 | { 3612, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSRAsv16i8 |
| 6844 | { 3611, 4, 1, 4, 676, 1, 0, ARMOpInfoBase + 1687, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VSQRTS |
| 6845 | { 3610, 4, 1, 4, 959, 1, 0, ARMOpInfoBase + 1683, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VSQRTH |
| 6846 | { 3609, 4, 1, 4, 678, 1, 0, ARMOpInfoBase + 1679, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VSQRTD |
| 6847 | { 3608, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // VSMMLA |
| 6848 | { 3607, 5, 1, 4, 222, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VSLTOS |
| 6849 | { 3606, 5, 1, 4, 221, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VSLTOH |
| 6850 | { 3605, 5, 1, 4, 1287, 0, 0, ARMOpInfoBase + 2397, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VSLTOD |
| 6851 | { 3604, 6, 1, 4, 987, 0, 0, ARMOpInfoBase + 2417, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSLIv8i8 |
| 6852 | { 3603, 6, 1, 4, 988, 0, 0, ARMOpInfoBase + 2411, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSLIv8i16 |
| 6853 | { 3602, 6, 1, 4, 988, 0, 0, ARMOpInfoBase + 2411, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSLIv4i32 |
| 6854 | { 3601, 6, 1, 4, 987, 0, 0, ARMOpInfoBase + 2417, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSLIv4i16 |
| 6855 | { 3600, 6, 1, 4, 988, 0, 0, ARMOpInfoBase + 2411, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSLIv2i64 |
| 6856 | { 3599, 6, 1, 4, 987, 0, 0, ARMOpInfoBase + 2417, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSLIv2i32 |
| 6857 | { 3598, 6, 1, 4, 987, 0, 0, ARMOpInfoBase + 2417, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSLIv1i64 |
| 6858 | { 3597, 6, 1, 4, 988, 0, 0, ARMOpInfoBase + 2411, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSLIv16i8 |
| 6859 | { 3596, 4, 1, 4, 563, 0, 0, ARMOpInfoBase + 1687, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VSITOS |
| 6860 | { 3595, 4, 1, 4, 562, 0, 0, ARMOpInfoBase + 2407, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VSITOH |
| 6861 | { 3594, 4, 1, 4, 561, 0, 0, ARMOpInfoBase + 1806, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VSITOD |
| 6862 | { 3593, 5, 1, 4, 222, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28880ULL }, // VSHTOS |
| 6863 | { 3592, 5, 1, 4, 221, 0, 0, ARMOpInfoBase + 2402, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8880ULL }, // VSHTOH |
| 6864 | { 3591, 5, 1, 4, 1287, 0, 0, ARMOpInfoBase + 2397, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8880ULL }, // VSHTOD |
| 6865 | { 3590, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRuv8i8 |
| 6866 | { 3589, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRuv8i16 |
| 6867 | { 3588, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRuv4i32 |
| 6868 | { 3587, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRuv4i16 |
| 6869 | { 3586, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRuv2i64 |
| 6870 | { 3585, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRuv2i32 |
| 6871 | { 3584, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRuv1i64 |
| 6872 | { 3583, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRuv16i8 |
| 6873 | { 3582, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRsv8i8 |
| 6874 | { 3581, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRsv8i16 |
| 6875 | { 3580, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRsv4i32 |
| 6876 | { 3579, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRsv4i16 |
| 6877 | { 3578, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRsv2i64 |
| 6878 | { 3577, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRsv2i32 |
| 6879 | { 3576, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRsv1i64 |
| 6880 | { 3575, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRsv16i8 |
| 6881 | { 3574, 5, 1, 4, 501, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRNv8i8 |
| 6882 | { 3573, 5, 1, 4, 501, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRNv4i16 |
| 6883 | { 3572, 5, 1, 4, 501, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VSHRNv2i32 |
| 6884 | { 3571, 5, 1, 4, 464, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLuv8i8 |
| 6885 | { 3570, 5, 1, 4, 465, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLuv8i16 |
| 6886 | { 3569, 5, 1, 4, 465, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLuv4i32 |
| 6887 | { 3568, 5, 1, 4, 464, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLuv4i16 |
| 6888 | { 3567, 5, 1, 4, 465, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLuv2i64 |
| 6889 | { 3566, 5, 1, 4, 464, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLuv2i32 |
| 6890 | { 3565, 5, 1, 4, 464, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLuv1i64 |
| 6891 | { 3564, 5, 1, 4, 465, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLuv16i8 |
| 6892 | { 3563, 5, 1, 4, 464, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLsv8i8 |
| 6893 | { 3562, 5, 1, 4, 465, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLsv8i16 |
| 6894 | { 3561, 5, 1, 4, 465, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLsv4i32 |
| 6895 | { 3560, 5, 1, 4, 464, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLsv4i16 |
| 6896 | { 3559, 5, 1, 4, 465, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLsv2i64 |
| 6897 | { 3558, 5, 1, 4, 464, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLsv2i32 |
| 6898 | { 3557, 5, 1, 4, 464, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLsv1i64 |
| 6899 | { 3556, 5, 1, 4, 465, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VSHLsv16i8 |
| 6900 | { 3555, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLiv8i8 |
| 6901 | { 3554, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLiv8i16 |
| 6902 | { 3553, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLiv4i32 |
| 6903 | { 3552, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLiv4i16 |
| 6904 | { 3551, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLiv2i64 |
| 6905 | { 3550, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLiv2i32 |
| 6906 | { 3549, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLiv1i64 |
| 6907 | { 3548, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLiv16i8 |
| 6908 | { 3547, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLLuv8i16 |
| 6909 | { 3546, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLLuv4i32 |
| 6910 | { 3545, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLLuv2i64 |
| 6911 | { 3544, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLLsv8i16 |
| 6912 | { 3543, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLLsv4i32 |
| 6913 | { 3542, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLLsv2i64 |
| 6914 | { 3541, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLLi8 |
| 6915 | { 3540, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLLi32 |
| 6916 | { 3539, 5, 1, 4, 984, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VSHLLi16 |
| 6917 | { 3538, 6, 1, 4, 579, 0, 0, ARMOpInfoBase + 2391, 0, 0|(1ULL<<MCID::Predicable), 0x10e00ULL }, // VSETLNi8 |
| 6918 | { 3537, 6, 1, 4, 1041, 0, 0, ARMOpInfoBase + 2391, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::InsertSubreg), 0x10e00ULL }, // VSETLNi32 |
| 6919 | { 3536, 6, 1, 4, 579, 0, 0, ARMOpInfoBase + 2391, 0, 0|(1ULL<<MCID::Predicable), 0x10e00ULL }, // VSETLNi16 |
| 6920 | { 3535, 3, 1, 4, 1256, 1, 0, ARMOpInfoBase + 1882, 0, 0, 0x8800ULL }, // VSELVSS |
| 6921 | { 3534, 3, 1, 4, 769, 1, 0, ARMOpInfoBase + 1879, 0, 0, 0x8800ULL }, // VSELVSH |
| 6922 | { 3533, 3, 1, 4, 1257, 1, 0, ARMOpInfoBase + 1502, 0, 0, 0x8800ULL }, // VSELVSD |
| 6923 | { 3532, 3, 1, 4, 1256, 1, 0, ARMOpInfoBase + 1882, 0, 0, 0x8800ULL }, // VSELGTS |
| 6924 | { 3531, 3, 1, 4, 769, 1, 0, ARMOpInfoBase + 1879, 0, 0, 0x8800ULL }, // VSELGTH |
| 6925 | { 3530, 3, 1, 4, 1257, 1, 0, ARMOpInfoBase + 1502, 0, 0, 0x8800ULL }, // VSELGTD |
| 6926 | { 3529, 3, 1, 4, 1256, 1, 0, ARMOpInfoBase + 1882, 0, 0, 0x8800ULL }, // VSELGES |
| 6927 | { 3528, 3, 1, 4, 769, 1, 0, ARMOpInfoBase + 1879, 0, 0, 0x8800ULL }, // VSELGEH |
| 6928 | { 3527, 3, 1, 4, 1257, 1, 0, ARMOpInfoBase + 1502, 0, 0, 0x8800ULL }, // VSELGED |
| 6929 | { 3526, 3, 1, 4, 1256, 1, 0, ARMOpInfoBase + 1882, 0, 0, 0x8800ULL }, // VSELEQS |
| 6930 | { 3525, 3, 1, 4, 769, 1, 0, ARMOpInfoBase + 1879, 0, 0, 0x8800ULL }, // VSELEQH |
| 6931 | { 3524, 3, 1, 4, 1257, 1, 0, ARMOpInfoBase + 1502, 0, 0, 0x8800ULL }, // VSELEQD |
| 6932 | { 3523, 5, 1, 4, 961, 0, 0, ARMOpInfoBase + 631, 0, 0, 0x11280ULL }, // VSDOTQI |
| 6933 | { 3522, 4, 1, 4, 961, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // VSDOTQ |
| 6934 | { 3521, 5, 1, 4, 961, 0, 0, ARMOpInfoBase + 626, 0, 0, 0x11280ULL }, // VSDOTDI |
| 6935 | { 3520, 4, 1, 4, 961, 0, 0, ARMOpInfoBase + 636, 0, 0, 0x11280ULL }, // VSDOTD |
| 6936 | { 3519, 3, 0, 4, 0, 0, 0, ARMOpInfoBase + 583, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VSCCLRMS |
| 6937 | { 3518, 3, 0, 4, 0, 0, 0, ARMOpInfoBase + 583, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VSCCLRMD |
| 6938 | { 3517, 5, 1, 4, 502, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VRSUBHNv8i8 |
| 6939 | { 3516, 5, 1, 4, 502, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VRSUBHNv4i16 |
| 6940 | { 3515, 5, 1, 4, 502, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VRSUBHNv2i32 |
| 6941 | { 3514, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAuv8i8 |
| 6942 | { 3513, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAuv8i16 |
| 6943 | { 3512, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAuv4i32 |
| 6944 | { 3511, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAuv4i16 |
| 6945 | { 3510, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAuv2i64 |
| 6946 | { 3509, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAuv2i32 |
| 6947 | { 3508, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAuv1i64 |
| 6948 | { 3507, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAuv16i8 |
| 6949 | { 3506, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAsv8i8 |
| 6950 | { 3505, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAsv8i16 |
| 6951 | { 3504, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAsv4i32 |
| 6952 | { 3503, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAsv4i16 |
| 6953 | { 3502, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAsv2i64 |
| 6954 | { 3501, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAsv2i32 |
| 6955 | { 3500, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2385, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAsv1i64 |
| 6956 | { 3499, 6, 1, 4, 482, 0, 0, ARMOpInfoBase + 2379, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSRAsv16i8 |
| 6957 | { 3498, 5, 1, 4, 528, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRSQRTShq |
| 6958 | { 3497, 5, 1, 4, 527, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRSQRTShd |
| 6959 | { 3496, 5, 1, 4, 528, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRSQRTSfq |
| 6960 | { 3495, 5, 1, 4, 527, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRSQRTSfd |
| 6961 | { 3494, 4, 1, 4, 499, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRSQRTEq |
| 6962 | { 3493, 4, 1, 4, 499, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRSQRTEhq |
| 6963 | { 3492, 4, 1, 4, 498, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRSQRTEhd |
| 6964 | { 3491, 4, 1, 4, 499, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRSQRTEfq |
| 6965 | { 3490, 4, 1, 4, 498, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRSQRTEfd |
| 6966 | { 3489, 4, 1, 4, 498, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRSQRTEd |
| 6967 | { 3488, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRuv8i8 |
| 6968 | { 3487, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRuv8i16 |
| 6969 | { 3486, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRuv4i32 |
| 6970 | { 3485, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRuv4i16 |
| 6971 | { 3484, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRuv2i64 |
| 6972 | { 3483, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRuv2i32 |
| 6973 | { 3482, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRuv1i64 |
| 6974 | { 3481, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRuv16i8 |
| 6975 | { 3480, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRsv8i8 |
| 6976 | { 3479, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRsv8i16 |
| 6977 | { 3478, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRsv4i32 |
| 6978 | { 3477, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRsv4i16 |
| 6979 | { 3476, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRsv2i64 |
| 6980 | { 3475, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRsv2i32 |
| 6981 | { 3474, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRsv1i64 |
| 6982 | { 3473, 5, 1, 4, 986, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRsv16i8 |
| 6983 | { 3472, 5, 1, 4, 795, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRNv8i8 |
| 6984 | { 3471, 5, 1, 4, 795, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRNv4i16 |
| 6985 | { 3470, 5, 1, 4, 795, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VRSHRNv2i32 |
| 6986 | { 3469, 5, 1, 4, 794, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLuv8i8 |
| 6987 | { 3468, 5, 1, 4, 793, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLuv8i16 |
| 6988 | { 3467, 5, 1, 4, 793, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLuv4i32 |
| 6989 | { 3466, 5, 1, 4, 794, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLuv4i16 |
| 6990 | { 3465, 5, 1, 4, 793, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLuv2i64 |
| 6991 | { 3464, 5, 1, 4, 794, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLuv2i32 |
| 6992 | { 3463, 5, 1, 4, 794, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLuv1i64 |
| 6993 | { 3462, 5, 1, 4, 793, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLuv16i8 |
| 6994 | { 3461, 5, 1, 4, 794, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLsv8i8 |
| 6995 | { 3460, 5, 1, 4, 793, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLsv8i16 |
| 6996 | { 3459, 5, 1, 4, 793, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLsv4i32 |
| 6997 | { 3458, 5, 1, 4, 794, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLsv4i16 |
| 6998 | { 3457, 5, 1, 4, 793, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLsv2i64 |
| 6999 | { 3456, 5, 1, 4, 794, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLsv2i32 |
| 7000 | { 3455, 5, 1, 4, 794, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLsv1i64 |
| 7001 | { 3454, 5, 1, 4, 793, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VRSHLsv16i8 |
| 7002 | { 3453, 4, 1, 4, 1249, 0, 0, ARMOpInfoBase + 1687, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // VRINTZS |
| 7003 | { 3452, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTZNQh |
| 7004 | { 3451, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTZNQf |
| 7005 | { 3450, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTZNDh |
| 7006 | { 3449, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTZNDf |
| 7007 | { 3448, 4, 1, 4, 958, 0, 0, ARMOpInfoBase + 1683, 0, 0, 0x8780ULL }, // VRINTZH |
| 7008 | { 3447, 4, 1, 4, 1253, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // VRINTZD |
| 7009 | { 3446, 4, 1, 4, 1249, 1, 0, ARMOpInfoBase + 1687, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VRINTXS |
| 7010 | { 3445, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTXNQh |
| 7011 | { 3444, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTXNQf |
| 7012 | { 3443, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTXNDh |
| 7013 | { 3442, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTXNDf |
| 7014 | { 3441, 4, 1, 4, 958, 1, 0, ARMOpInfoBase + 1683, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VRINTXH |
| 7015 | { 3440, 4, 1, 4, 1253, 1, 0, ARMOpInfoBase + 1679, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VRINTXD |
| 7016 | { 3439, 4, 1, 4, 1249, 1, 0, ARMOpInfoBase + 1687, 69, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // VRINTRS |
| 7017 | { 3438, 4, 1, 4, 958, 1, 0, ARMOpInfoBase + 1683, 69, 0, 0x8780ULL }, // VRINTRH |
| 7018 | { 3437, 4, 1, 4, 1253, 1, 0, ARMOpInfoBase + 1679, 69, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // VRINTRD |
| 7019 | { 3436, 2, 1, 4, 1249, 0, 0, ARMOpInfoBase + 1799, 0, 0, 0x8780ULL }, // VRINTPS |
| 7020 | { 3435, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTPNQh |
| 7021 | { 3434, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTPNQf |
| 7022 | { 3433, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTPNDh |
| 7023 | { 3432, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTPNDf |
| 7024 | { 3431, 2, 1, 4, 958, 0, 0, ARMOpInfoBase + 2377, 0, 0, 0x8780ULL }, // VRINTPH |
| 7025 | { 3430, 2, 1, 4, 1253, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x8780ULL }, // VRINTPD |
| 7026 | { 3429, 2, 1, 4, 1249, 0, 0, ARMOpInfoBase + 1799, 0, 0, 0x8780ULL }, // VRINTNS |
| 7027 | { 3428, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTNNQh |
| 7028 | { 3427, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTNNQf |
| 7029 | { 3426, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTNNDh |
| 7030 | { 3425, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTNNDf |
| 7031 | { 3424, 2, 1, 4, 958, 0, 0, ARMOpInfoBase + 2377, 0, 0, 0x8780ULL }, // VRINTNH |
| 7032 | { 3423, 2, 1, 4, 1253, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x8780ULL }, // VRINTND |
| 7033 | { 3422, 2, 1, 4, 1249, 0, 0, ARMOpInfoBase + 1799, 0, 0, 0x8780ULL }, // VRINTMS |
| 7034 | { 3421, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTMNQh |
| 7035 | { 3420, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTMNQf |
| 7036 | { 3419, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTMNDh |
| 7037 | { 3418, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTMNDf |
| 7038 | { 3417, 2, 1, 4, 958, 0, 0, ARMOpInfoBase + 2377, 0, 0, 0x8780ULL }, // VRINTMH |
| 7039 | { 3416, 2, 1, 4, 1253, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x8780ULL }, // VRINTMD |
| 7040 | { 3415, 2, 1, 4, 1249, 0, 0, ARMOpInfoBase + 1799, 0, 0, 0x8780ULL }, // VRINTAS |
| 7041 | { 3414, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTANQh |
| 7042 | { 3413, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VRINTANQf |
| 7043 | { 3412, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTANDh |
| 7044 | { 3411, 2, 1, 4, 997, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VRINTANDf |
| 7045 | { 3410, 2, 1, 4, 958, 0, 0, ARMOpInfoBase + 2377, 0, 0, 0x8780ULL }, // VRINTAH |
| 7046 | { 3409, 2, 1, 4, 1253, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x8780ULL }, // VRINTAD |
| 7047 | { 3408, 5, 1, 4, 970, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDuv8i8 |
| 7048 | { 3407, 5, 1, 4, 969, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDuv8i16 |
| 7049 | { 3406, 5, 1, 4, 969, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDuv4i32 |
| 7050 | { 3405, 5, 1, 4, 970, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDuv4i16 |
| 7051 | { 3404, 5, 1, 4, 970, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDuv2i32 |
| 7052 | { 3403, 5, 1, 4, 969, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDuv16i8 |
| 7053 | { 3402, 5, 1, 4, 970, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDsv8i8 |
| 7054 | { 3401, 5, 1, 4, 969, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDsv8i16 |
| 7055 | { 3400, 5, 1, 4, 969, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDsv4i32 |
| 7056 | { 3399, 5, 1, 4, 970, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDsv4i16 |
| 7057 | { 3398, 5, 1, 4, 970, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDsv2i32 |
| 7058 | { 3397, 5, 1, 4, 969, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRHADDsv16i8 |
| 7059 | { 3396, 4, 1, 4, 478, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV64q8 |
| 7060 | { 3395, 4, 1, 4, 478, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV64q32 |
| 7061 | { 3394, 4, 1, 4, 478, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV64q16 |
| 7062 | { 3393, 4, 1, 4, 477, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV64d8 |
| 7063 | { 3392, 4, 1, 4, 477, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV64d32 |
| 7064 | { 3391, 4, 1, 4, 477, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV64d16 |
| 7065 | { 3390, 4, 1, 4, 478, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV32q8 |
| 7066 | { 3389, 4, 1, 4, 478, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV32q16 |
| 7067 | { 3388, 4, 1, 4, 477, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV32d8 |
| 7068 | { 3387, 4, 1, 4, 477, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV32d16 |
| 7069 | { 3386, 4, 1, 4, 478, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV16q8 |
| 7070 | { 3385, 4, 1, 4, 477, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VREV16d8 |
| 7071 | { 3384, 5, 1, 4, 528, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRECPShq |
| 7072 | { 3383, 5, 1, 4, 527, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRECPShd |
| 7073 | { 3382, 5, 1, 4, 528, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRECPSfq |
| 7074 | { 3381, 5, 1, 4, 527, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRECPSfd |
| 7075 | { 3380, 4, 1, 4, 499, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRECPEq |
| 7076 | { 3379, 4, 1, 4, 499, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRECPEhq |
| 7077 | { 3378, 4, 1, 4, 498, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRECPEhd |
| 7078 | { 3377, 4, 1, 4, 499, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRECPEfq |
| 7079 | { 3376, 4, 1, 4, 498, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRECPEfd |
| 7080 | { 3375, 4, 1, 4, 498, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VRECPEd |
| 7081 | { 3374, 5, 1, 4, 502, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRADDHNv8i8 |
| 7082 | { 3373, 5, 1, 4, 502, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRADDHNv4i16 |
| 7083 | { 3372, 5, 1, 4, 502, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VRADDHNv2i32 |
| 7084 | { 3371, 5, 1, 4, 486, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBuv8i8 |
| 7085 | { 3370, 5, 1, 4, 485, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBuv8i16 |
| 7086 | { 3369, 5, 1, 4, 485, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBuv4i32 |
| 7087 | { 3368, 5, 1, 4, 486, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBuv4i16 |
| 7088 | { 3367, 5, 1, 4, 485, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBuv2i64 |
| 7089 | { 3366, 5, 1, 4, 486, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBuv2i32 |
| 7090 | { 3365, 5, 1, 4, 486, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBuv1i64 |
| 7091 | { 3364, 5, 1, 4, 485, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBuv16i8 |
| 7092 | { 3363, 5, 1, 4, 486, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBsv8i8 |
| 7093 | { 3362, 5, 1, 4, 485, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBsv8i16 |
| 7094 | { 3361, 5, 1, 4, 485, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBsv4i32 |
| 7095 | { 3360, 5, 1, 4, 486, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBsv4i16 |
| 7096 | { 3359, 5, 1, 4, 485, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBsv2i64 |
| 7097 | { 3358, 5, 1, 4, 486, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBsv2i32 |
| 7098 | { 3357, 5, 1, 4, 486, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBsv1i64 |
| 7099 | { 3356, 5, 1, 4, 485, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQSUBsv16i8 |
| 7100 | { 3355, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQSHRUNv8i8 |
| 7101 | { 3354, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQSHRUNv4i16 |
| 7102 | { 3353, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQSHRUNv2i32 |
| 7103 | { 3352, 5, 1, 4, 792, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQSHRNuv8i8 |
| 7104 | { 3351, 5, 1, 4, 792, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQSHRNuv4i16 |
| 7105 | { 3350, 5, 1, 4, 792, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQSHRNuv2i32 |
| 7106 | { 3349, 5, 1, 4, 792, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQSHRNsv8i8 |
| 7107 | { 3348, 5, 1, 4, 792, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQSHRNsv4i16 |
| 7108 | { 3347, 5, 1, 4, 792, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQSHRNsv2i32 |
| 7109 | { 3346, 5, 1, 4, 471, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLuv8i8 |
| 7110 | { 3345, 5, 1, 4, 472, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLuv8i16 |
| 7111 | { 3344, 5, 1, 4, 472, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLuv4i32 |
| 7112 | { 3343, 5, 1, 4, 471, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLuv4i16 |
| 7113 | { 3342, 5, 1, 4, 472, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLuv2i64 |
| 7114 | { 3341, 5, 1, 4, 471, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLuv2i32 |
| 7115 | { 3340, 5, 1, 4, 471, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLuv1i64 |
| 7116 | { 3339, 5, 1, 4, 472, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLuv16i8 |
| 7117 | { 3338, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLuiv8i8 |
| 7118 | { 3337, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLuiv8i16 |
| 7119 | { 3336, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLuiv4i32 |
| 7120 | { 3335, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLuiv4i16 |
| 7121 | { 3334, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLuiv2i64 |
| 7122 | { 3333, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLuiv2i32 |
| 7123 | { 3332, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLuiv1i64 |
| 7124 | { 3331, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLuiv16i8 |
| 7125 | { 3330, 5, 1, 4, 471, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLsv8i8 |
| 7126 | { 3329, 5, 1, 4, 472, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLsv8i16 |
| 7127 | { 3328, 5, 1, 4, 472, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLsv4i32 |
| 7128 | { 3327, 5, 1, 4, 471, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLsv4i16 |
| 7129 | { 3326, 5, 1, 4, 472, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLsv2i64 |
| 7130 | { 3325, 5, 1, 4, 471, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLsv2i32 |
| 7131 | { 3324, 5, 1, 4, 471, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLsv1i64 |
| 7132 | { 3323, 5, 1, 4, 472, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQSHLsv16i8 |
| 7133 | { 3322, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsuv8i8 |
| 7134 | { 3321, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsuv8i16 |
| 7135 | { 3320, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsuv4i32 |
| 7136 | { 3319, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsuv4i16 |
| 7137 | { 3318, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsuv2i64 |
| 7138 | { 3317, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsuv2i32 |
| 7139 | { 3316, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsuv1i64 |
| 7140 | { 3315, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsuv16i8 |
| 7141 | { 3314, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsiv8i8 |
| 7142 | { 3313, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsiv8i16 |
| 7143 | { 3312, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsiv4i32 |
| 7144 | { 3311, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsiv4i16 |
| 7145 | { 3310, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsiv2i64 |
| 7146 | { 3309, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsiv2i32 |
| 7147 | { 3308, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2372, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsiv1i64 |
| 7148 | { 3307, 5, 1, 4, 985, 0, 0, ARMOpInfoBase + 2367, 0, 0|(1ULL<<MCID::Predicable), 0x11180ULL }, // VQSHLsiv16i8 |
| 7149 | { 3306, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQRSHRUNv8i8 |
| 7150 | { 3305, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQRSHRUNv4i16 |
| 7151 | { 3304, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQRSHRUNv2i32 |
| 7152 | { 3303, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQRSHRNuv8i8 |
| 7153 | { 3302, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQRSHRNuv4i16 |
| 7154 | { 3301, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQRSHRNuv2i32 |
| 7155 | { 3300, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQRSHRNsv8i8 |
| 7156 | { 3299, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQRSHRNsv4i16 |
| 7157 | { 3298, 5, 1, 4, 503, 0, 0, ARMOpInfoBase + 2362, 0, 0|(1ULL<<MCID::Predicable), 0x11200ULL }, // VQRSHRNsv2i32 |
| 7158 | { 3297, 5, 1, 4, 489, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLuv8i8 |
| 7159 | { 3296, 5, 1, 4, 488, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLuv8i16 |
| 7160 | { 3295, 5, 1, 4, 488, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLuv4i32 |
| 7161 | { 3294, 5, 1, 4, 489, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLuv4i16 |
| 7162 | { 3293, 5, 1, 4, 488, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLuv2i64 |
| 7163 | { 3292, 5, 1, 4, 489, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLuv2i32 |
| 7164 | { 3291, 5, 1, 4, 489, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLuv1i64 |
| 7165 | { 3290, 5, 1, 4, 488, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLuv16i8 |
| 7166 | { 3289, 5, 1, 4, 489, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLsv8i8 |
| 7167 | { 3288, 5, 1, 4, 488, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLsv8i16 |
| 7168 | { 3287, 5, 1, 4, 488, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLsv4i32 |
| 7169 | { 3286, 5, 1, 4, 489, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLsv4i16 |
| 7170 | { 3285, 5, 1, 4, 488, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLsv2i64 |
| 7171 | { 3284, 5, 1, 4, 489, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLsv2i32 |
| 7172 | { 3283, 5, 1, 4, 489, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLsv1i64 |
| 7173 | { 3282, 5, 1, 4, 488, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11300ULL }, // VQRSHLsv16i8 |
| 7174 | { 3281, 5, 1, 4, 791, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQRDMULHv8i16 |
| 7175 | { 3280, 5, 1, 4, 790, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQRDMULHv4i32 |
| 7176 | { 3279, 5, 1, 4, 975, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQRDMULHv4i16 |
| 7177 | { 3278, 5, 1, 4, 974, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQRDMULHv2i32 |
| 7178 | { 3277, 6, 1, 4, 791, 0, 0, ARMOpInfoBase + 2351, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQRDMULHslv8i16 |
| 7179 | { 3276, 6, 1, 4, 790, 0, 0, ARMOpInfoBase + 2339, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQRDMULHslv4i32 |
| 7180 | { 3275, 6, 1, 4, 975, 0, 0, ARMOpInfoBase + 2345, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQRDMULHslv4i16 |
| 7181 | { 3274, 6, 1, 4, 974, 0, 0, ARMOpInfoBase + 2333, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQRDMULHslv2i32 |
| 7182 | { 3273, 6, 1, 4, 982, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQRDMLSHv8i16 |
| 7183 | { 3272, 6, 1, 4, 981, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQRDMLSHv4i32 |
| 7184 | { 3271, 6, 1, 4, 980, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQRDMLSHv4i16 |
| 7185 | { 3270, 6, 1, 4, 979, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQRDMLSHv2i32 |
| 7186 | { 3269, 7, 1, 4, 982, 0, 0, ARMOpInfoBase + 2256, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // VQRDMLSHslv8i16 |
| 7187 | { 3268, 7, 1, 4, 981, 0, 0, ARMOpInfoBase + 2242, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // VQRDMLSHslv4i32 |
| 7188 | { 3267, 7, 1, 4, 980, 0, 0, ARMOpInfoBase + 2249, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQRDMLSHslv4i16 |
| 7189 | { 3266, 7, 1, 4, 979, 0, 0, ARMOpInfoBase + 2235, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQRDMLSHslv2i32 |
| 7190 | { 3265, 6, 1, 4, 982, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQRDMLAHv8i16 |
| 7191 | { 3264, 6, 1, 4, 981, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQRDMLAHv4i32 |
| 7192 | { 3263, 6, 1, 4, 980, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQRDMLAHv4i16 |
| 7193 | { 3262, 6, 1, 4, 979, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQRDMLAHv2i32 |
| 7194 | { 3261, 7, 1, 4, 982, 0, 0, ARMOpInfoBase + 2256, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // VQRDMLAHslv8i16 |
| 7195 | { 3260, 7, 1, 4, 981, 0, 0, ARMOpInfoBase + 2242, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL }, // VQRDMLAHslv4i32 |
| 7196 | { 3259, 7, 1, 4, 980, 0, 0, ARMOpInfoBase + 2249, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQRDMLAHslv4i16 |
| 7197 | { 3258, 7, 1, 4, 979, 0, 0, ARMOpInfoBase + 2235, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQRDMLAHslv2i32 |
| 7198 | { 3257, 4, 1, 4, 495, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQNEGv8i8 |
| 7199 | { 3256, 4, 1, 4, 494, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQNEGv8i16 |
| 7200 | { 3255, 4, 1, 4, 494, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQNEGv4i32 |
| 7201 | { 3254, 4, 1, 4, 495, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQNEGv4i16 |
| 7202 | { 3253, 4, 1, 4, 495, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQNEGv2i32 |
| 7203 | { 3252, 4, 1, 4, 494, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQNEGv16i8 |
| 7204 | { 3251, 4, 1, 4, 573, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQMOVNuv8i8 |
| 7205 | { 3250, 4, 1, 4, 573, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQMOVNuv4i16 |
| 7206 | { 3249, 4, 1, 4, 573, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQMOVNuv2i32 |
| 7207 | { 3248, 4, 1, 4, 573, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQMOVNsv8i8 |
| 7208 | { 3247, 4, 1, 4, 573, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQMOVNsv4i16 |
| 7209 | { 3246, 4, 1, 4, 573, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQMOVNsv2i32 |
| 7210 | { 3245, 4, 1, 4, 573, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQMOVNsuv8i8 |
| 7211 | { 3244, 4, 1, 4, 573, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQMOVNsuv4i16 |
| 7212 | { 3243, 4, 1, 4, 573, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQMOVNsuv2i32 |
| 7213 | { 3242, 5, 1, 4, 789, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQDMULLv4i32 |
| 7214 | { 3241, 5, 1, 4, 788, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQDMULLv2i64 |
| 7215 | { 3240, 6, 1, 4, 789, 0, 0, ARMOpInfoBase + 2327, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMULLslv4i16 |
| 7216 | { 3239, 6, 1, 4, 789, 0, 0, ARMOpInfoBase + 2321, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMULLslv2i32 |
| 7217 | { 3238, 5, 1, 4, 791, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQDMULHv8i16 |
| 7218 | { 3237, 5, 1, 4, 790, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQDMULHv4i32 |
| 7219 | { 3236, 5, 1, 4, 975, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQDMULHv4i16 |
| 7220 | { 3235, 5, 1, 4, 974, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQDMULHv2i32 |
| 7221 | { 3234, 6, 1, 4, 791, 0, 0, ARMOpInfoBase + 2351, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMULHslv8i16 |
| 7222 | { 3233, 6, 1, 4, 790, 0, 0, ARMOpInfoBase + 2339, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMULHslv4i32 |
| 7223 | { 3232, 6, 1, 4, 975, 0, 0, ARMOpInfoBase + 2345, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMULHslv4i16 |
| 7224 | { 3231, 6, 1, 4, 974, 0, 0, ARMOpInfoBase + 2333, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMULHslv2i32 |
| 7225 | { 3230, 6, 1, 4, 787, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQDMLSLv4i32 |
| 7226 | { 3229, 6, 1, 4, 786, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQDMLSLv2i64 |
| 7227 | { 3228, 7, 1, 4, 787, 0, 0, ARMOpInfoBase + 2228, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMLSLslv4i16 |
| 7228 | { 3227, 7, 1, 4, 786, 0, 0, ARMOpInfoBase + 2221, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMLSLslv2i32 |
| 7229 | { 3226, 6, 1, 4, 787, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQDMLALv4i32 |
| 7230 | { 3225, 6, 1, 4, 786, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VQDMLALv2i64 |
| 7231 | { 3224, 7, 1, 4, 787, 0, 0, ARMOpInfoBase + 2228, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMLALslv4i16 |
| 7232 | { 3223, 7, 1, 4, 786, 0, 0, ARMOpInfoBase + 2221, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VQDMLALslv2i32 |
| 7233 | { 3222, 5, 1, 4, 497, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDuv8i8 |
| 7234 | { 3221, 5, 1, 4, 496, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDuv8i16 |
| 7235 | { 3220, 5, 1, 4, 496, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDuv4i32 |
| 7236 | { 3219, 5, 1, 4, 497, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDuv4i16 |
| 7237 | { 3218, 5, 1, 4, 496, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDuv2i64 |
| 7238 | { 3217, 5, 1, 4, 497, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDuv2i32 |
| 7239 | { 3216, 5, 1, 4, 497, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDuv1i64 |
| 7240 | { 3215, 5, 1, 4, 496, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDuv16i8 |
| 7241 | { 3214, 5, 1, 4, 497, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDsv8i8 |
| 7242 | { 3213, 5, 1, 4, 496, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDsv8i16 |
| 7243 | { 3212, 5, 1, 4, 496, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDsv4i32 |
| 7244 | { 3211, 5, 1, 4, 497, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDsv4i16 |
| 7245 | { 3210, 5, 1, 4, 496, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDsv2i64 |
| 7246 | { 3209, 5, 1, 4, 497, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDsv2i32 |
| 7247 | { 3208, 5, 1, 4, 497, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDsv1i64 |
| 7248 | { 3207, 5, 1, 4, 496, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VQADDsv16i8 |
| 7249 | { 3206, 4, 1, 4, 784, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQABSv8i8 |
| 7250 | { 3205, 4, 1, 4, 785, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQABSv8i16 |
| 7251 | { 3204, 4, 1, 4, 785, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQABSv4i32 |
| 7252 | { 3203, 4, 1, 4, 784, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQABSv4i16 |
| 7253 | { 3202, 4, 1, 4, 784, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQABSv2i32 |
| 7254 | { 3201, 4, 1, 4, 785, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VQABSv16i8 |
| 7255 | { 3200, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMINu8 |
| 7256 | { 3199, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMINu32 |
| 7257 | { 3198, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMINu16 |
| 7258 | { 3197, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMINs8 |
| 7259 | { 3196, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMINs32 |
| 7260 | { 3195, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMINs16 |
| 7261 | { 3194, 5, 1, 4, 775, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMINh |
| 7262 | { 3193, 5, 1, 4, 775, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMINf |
| 7263 | { 3192, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMAXu8 |
| 7264 | { 3191, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMAXu32 |
| 7265 | { 3190, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMAXu16 |
| 7266 | { 3189, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMAXs8 |
| 7267 | { 3188, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMAXs32 |
| 7268 | { 3187, 5, 1, 4, 524, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMAXs16 |
| 7269 | { 3186, 5, 1, 4, 775, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMAXh |
| 7270 | { 3185, 5, 1, 4, 775, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPMAXf |
| 7271 | { 3184, 5, 1, 4, 781, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPADDi8 |
| 7272 | { 3183, 5, 1, 4, 781, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPADDi32 |
| 7273 | { 3182, 5, 1, 4, 781, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPADDi16 |
| 7274 | { 3181, 5, 1, 4, 989, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPADDh |
| 7275 | { 3180, 5, 1, 4, 525, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VPADDf |
| 7276 | { 3179, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLuv8i8 |
| 7277 | { 3178, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLuv8i16 |
| 7278 | { 3177, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLuv4i32 |
| 7279 | { 3176, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLuv4i16 |
| 7280 | { 3175, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLuv2i32 |
| 7281 | { 3174, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLuv16i8 |
| 7282 | { 3173, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLsv8i8 |
| 7283 | { 3172, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLsv8i16 |
| 7284 | { 3171, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLsv4i32 |
| 7285 | { 3170, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLsv4i16 |
| 7286 | { 3169, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLsv2i32 |
| 7287 | { 3168, 4, 1, 4, 783, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADDLsv16i8 |
| 7288 | { 3167, 5, 1, 4, 782, 0, 0, ARMOpInfoBase + 398, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALuv8i8 |
| 7289 | { 3166, 5, 1, 4, 481, 0, 0, ARMOpInfoBase + 2357, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALuv8i16 |
| 7290 | { 3165, 5, 1, 4, 481, 0, 0, ARMOpInfoBase + 2357, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALuv4i32 |
| 7291 | { 3164, 5, 1, 4, 782, 0, 0, ARMOpInfoBase + 398, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALuv4i16 |
| 7292 | { 3163, 5, 1, 4, 782, 0, 0, ARMOpInfoBase + 398, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALuv2i32 |
| 7293 | { 3162, 5, 1, 4, 481, 0, 0, ARMOpInfoBase + 2357, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALuv16i8 |
| 7294 | { 3161, 5, 1, 4, 782, 0, 0, ARMOpInfoBase + 398, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALsv8i8 |
| 7295 | { 3160, 5, 1, 4, 481, 0, 0, ARMOpInfoBase + 2357, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALsv8i16 |
| 7296 | { 3159, 5, 1, 4, 481, 0, 0, ARMOpInfoBase + 2357, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALsv4i32 |
| 7297 | { 3158, 5, 1, 4, 782, 0, 0, ARMOpInfoBase + 398, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALsv4i16 |
| 7298 | { 3157, 5, 1, 4, 782, 0, 0, ARMOpInfoBase + 398, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALsv2i32 |
| 7299 | { 3156, 5, 1, 4, 481, 0, 0, ARMOpInfoBase + 2357, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VPADALsv16i8 |
| 7300 | { 3155, 5, 1, 4, 458, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VORRq |
| 7301 | { 3154, 5, 1, 4, 470, 0, 0, ARMOpInfoBase + 1725, 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // VORRiv8i16 |
| 7302 | { 3153, 5, 1, 4, 470, 0, 0, ARMOpInfoBase + 1725, 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // VORRiv4i32 |
| 7303 | { 3152, 5, 1, 4, 470, 0, 0, ARMOpInfoBase + 1720, 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // VORRiv4i16 |
| 7304 | { 3151, 5, 1, 4, 470, 0, 0, ARMOpInfoBase + 1720, 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // VORRiv2i32 |
| 7305 | { 3150, 5, 1, 4, 459, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VORRd |
| 7306 | { 3149, 5, 1, 4, 458, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VORNq |
| 7307 | { 3148, 5, 1, 4, 459, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VORNd |
| 7308 | { 3147, 5, 1, 4, 529, 1, 0, ARMOpInfoBase + 1705, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28800ULL }, // VNMULS |
| 7309 | { 3146, 5, 1, 4, 202, 1, 0, ARMOpInfoBase + 1695, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VNMULH |
| 7310 | { 3145, 5, 1, 4, 1258, 1, 0, ARMOpInfoBase + 1669, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VNMULD |
| 7311 | { 3144, 6, 1, 4, 543, 1, 0, ARMOpInfoBase + 1873, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28800ULL }, // VNMLSS |
| 7312 | { 3143, 6, 1, 4, 540, 1, 0, ARMOpInfoBase + 1853, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VNMLSH |
| 7313 | { 3142, 6, 1, 4, 539, 1, 0, ARMOpInfoBase + 1658, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VNMLSD |
| 7314 | { 3141, 6, 1, 4, 543, 1, 0, ARMOpInfoBase + 1873, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28800ULL }, // VNMLAS |
| 7315 | { 3140, 6, 1, 4, 540, 1, 0, ARMOpInfoBase + 1853, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VNMLAH |
| 7316 | { 3139, 6, 1, 4, 539, 1, 0, ARMOpInfoBase + 1658, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VNMLAD |
| 7317 | { 3138, 4, 1, 4, 780, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGs8q |
| 7318 | { 3137, 4, 1, 4, 779, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGs8d |
| 7319 | { 3136, 4, 1, 4, 780, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGs32q |
| 7320 | { 3135, 4, 1, 4, 779, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGs32d |
| 7321 | { 3134, 4, 1, 4, 780, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGs16q |
| 7322 | { 3133, 4, 1, 4, 779, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGs16d |
| 7323 | { 3132, 4, 1, 4, 778, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGhq |
| 7324 | { 3131, 4, 1, 4, 777, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGhd |
| 7325 | { 3130, 4, 1, 4, 463, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGfd |
| 7326 | { 3129, 4, 1, 4, 462, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VNEGf32q |
| 7327 | { 3128, 4, 1, 4, 517, 0, 0, ARMOpInfoBase + 1687, 0, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // VNEGS |
| 7328 | { 3127, 4, 1, 4, 776, 0, 0, ARMOpInfoBase + 1683, 0, 0, 0x8780ULL }, // VNEGH |
| 7329 | { 3126, 4, 1, 4, 516, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // VNEGD |
| 7330 | { 3125, 4, 1, 4, 971, 0, 0, ARMOpInfoBase + 2301, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // VMVNv8i16 |
| 7331 | { 3124, 4, 1, 4, 971, 0, 0, ARMOpInfoBase + 2301, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // VMVNv4i32 |
| 7332 | { 3123, 4, 1, 4, 971, 0, 0, ARMOpInfoBase + 857, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // VMVNv4i16 |
| 7333 | { 3122, 4, 1, 4, 971, 0, 0, ARMOpInfoBase + 857, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL }, // VMVNv2i32 |
| 7334 | { 3121, 4, 1, 4, 570, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMVNq |
| 7335 | { 3120, 4, 1, 4, 570, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMVNd |
| 7336 | { 3119, 5, 1, 4, 972, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULv8i8 |
| 7337 | { 3118, 5, 1, 4, 976, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULv8i16 |
| 7338 | { 3117, 5, 1, 4, 537, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULv4i32 |
| 7339 | { 3116, 5, 1, 4, 972, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULv4i16 |
| 7340 | { 3115, 5, 1, 4, 973, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULv2i32 |
| 7341 | { 3114, 5, 1, 4, 976, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULv16i8 |
| 7342 | { 3113, 6, 1, 4, 976, 0, 0, ARMOpInfoBase + 2351, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULslv8i16 |
| 7343 | { 3112, 6, 1, 4, 537, 0, 0, ARMOpInfoBase + 2339, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULslv4i32 |
| 7344 | { 3111, 6, 1, 4, 972, 0, 0, ARMOpInfoBase + 2345, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULslv4i16 |
| 7345 | { 3110, 6, 1, 4, 973, 0, 0, ARMOpInfoBase + 2333, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULslv2i32 |
| 7346 | { 3109, 6, 1, 4, 533, 0, 0, ARMOpInfoBase + 2351, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULslhq |
| 7347 | { 3108, 6, 1, 4, 532, 0, 0, ARMOpInfoBase + 2345, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULslhd |
| 7348 | { 3107, 6, 1, 4, 535, 0, 0, ARMOpInfoBase + 2339, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULslfq |
| 7349 | { 3106, 6, 1, 4, 534, 0, 0, ARMOpInfoBase + 2333, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULslfd |
| 7350 | { 3105, 5, 1, 4, 976, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULpq |
| 7351 | { 3104, 5, 1, 4, 972, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULpd |
| 7352 | { 3103, 5, 1, 4, 996, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULhq |
| 7353 | { 3102, 5, 1, 4, 995, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULhd |
| 7354 | { 3101, 5, 1, 4, 531, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULfq |
| 7355 | { 3100, 5, 1, 4, 530, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULfd |
| 7356 | { 3099, 5, 1, 4, 529, 1, 0, ARMOpInfoBase + 1705, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28800ULL }, // VMULS |
| 7357 | { 3098, 5, 1, 4, 983, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULLuv8i16 |
| 7358 | { 3097, 5, 1, 4, 983, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULLuv4i32 |
| 7359 | { 3096, 5, 1, 4, 536, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULLuv2i64 |
| 7360 | { 3095, 5, 1, 4, 983, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULLsv8i16 |
| 7361 | { 3094, 5, 1, 4, 983, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULLsv4i32 |
| 7362 | { 3093, 5, 1, 4, 536, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULLsv2i64 |
| 7363 | { 3092, 6, 1, 4, 983, 0, 0, ARMOpInfoBase + 2327, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULLsluv4i16 |
| 7364 | { 3091, 6, 1, 4, 983, 0, 0, ARMOpInfoBase + 2321, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULLsluv2i32 |
| 7365 | { 3090, 6, 1, 4, 983, 0, 0, ARMOpInfoBase + 2327, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULLslsv4i16 |
| 7366 | { 3089, 6, 1, 4, 983, 0, 0, ARMOpInfoBase + 2321, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMULLslsv2i32 |
| 7367 | { 3088, 5, 1, 4, 983, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULLp8 |
| 7368 | { 3087, 3, 1, 4, 538, 0, 0, ARMOpInfoBase + 1866, 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMULLp64 |
| 7369 | { 3086, 5, 1, 4, 202, 1, 0, ARMOpInfoBase + 1695, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VMULH |
| 7370 | { 3085, 5, 1, 4, 1258, 1, 0, ARMOpInfoBase + 1669, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VMULD |
| 7371 | { 3084, 3, 0, 4, 1288, 0, 1, ARMOpInfoBase + 536, 73, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR_VPR |
| 7372 | { 3083, 4, 1, 4, 1288, 0, 0, ARMOpInfoBase + 2317, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR_P0 |
| 7373 | { 3082, 3, 0, 4, 586, 0, 1, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR_FPSID |
| 7374 | { 3081, 4, 1, 4, 1288, 0, 0, ARMOpInfoBase + 2313, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR_FPSCR_NZCVQC |
| 7375 | { 3080, 3, 0, 4, 586, 0, 1, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR_FPINST2 |
| 7376 | { 3079, 3, 0, 4, 586, 0, 1, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR_FPINST |
| 7377 | { 3078, 3, 0, 4, 586, 0, 1, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR_FPEXC |
| 7378 | { 3077, 3, 0, 4, 586, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR_FPCXTS |
| 7379 | { 3076, 3, 0, 4, 586, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR_FPCXTNS |
| 7380 | { 3075, 3, 0, 4, 1288, 0, 1, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMSR |
| 7381 | { 3074, 3, 1, 4, 1289, 1, 0, ARMOpInfoBase + 536, 73, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_VPR |
| 7382 | { 3073, 4, 1, 4, 1289, 0, 0, ARMOpInfoBase + 2309, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_P0 |
| 7383 | { 3072, 3, 1, 4, 585, 1, 0, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_MVFR2 |
| 7384 | { 3071, 3, 1, 4, 585, 1, 0, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_MVFR1 |
| 7385 | { 3070, 3, 1, 4, 585, 1, 0, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_MVFR0 |
| 7386 | { 3069, 3, 1, 4, 585, 1, 0, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_FPSID |
| 7387 | { 3068, 4, 1, 4, 1290, 1, 0, ARMOpInfoBase + 2305, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_FPSCR_NZCVQC |
| 7388 | { 3067, 3, 1, 4, 585, 1, 0, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_FPINST2 |
| 7389 | { 3066, 3, 1, 4, 585, 1, 0, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_FPINST |
| 7390 | { 3065, 3, 1, 4, 585, 1, 0, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_FPEXC |
| 7391 | { 3064, 3, 1, 4, 585, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_FPCXTS |
| 7392 | { 3063, 3, 1, 4, 585, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS_FPCXTNS |
| 7393 | { 3062, 3, 1, 4, 1291, 1, 0, ARMOpInfoBase + 1055, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL }, // VMRS |
| 7394 | { 3061, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 857, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv8i8 |
| 7395 | { 3060, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 2301, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv8i16 |
| 7396 | { 3059, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 2301, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv4i32 |
| 7397 | { 3058, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 857, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv4i16 |
| 7398 | { 3057, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 2301, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv4f32 |
| 7399 | { 3056, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 2301, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv2i64 |
| 7400 | { 3055, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 857, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv2i32 |
| 7401 | { 3054, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 857, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv2f32 |
| 7402 | { 3053, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 857, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv1i64 |
| 7403 | { 3052, 4, 1, 4, 567, 0, 0, ARMOpInfoBase + 2301, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL }, // VMOVv16i8 |
| 7404 | { 3051, 6, 2, 4, 582, 0, 0, ARMOpInfoBase + 2295, 0, 0|(1ULL<<MCID::Predicable), 0x18a80ULL }, // VMOVSRR |
| 7405 | { 3050, 4, 1, 4, 578, 0, 0, ARMOpInfoBase + 2291, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18a00ULL }, // VMOVSR |
| 7406 | { 3049, 4, 1, 4, 1212, 0, 0, ARMOpInfoBase + 1687, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VMOVS |
| 7407 | { 3048, 4, 1, 4, 577, 0, 0, ARMOpInfoBase + 2287, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18900ULL }, // VMOVRS |
| 7408 | { 3047, 6, 2, 4, 580, 0, 0, ARMOpInfoBase + 2281, 0, 0|(1ULL<<MCID::Predicable), 0x18980ULL }, // VMOVRRS |
| 7409 | { 3046, 5, 2, 4, 580, 0, 0, ARMOpInfoBase + 2276, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtractSubreg), 0x18980ULL }, // VMOVRRD |
| 7410 | { 3045, 4, 1, 4, 1213, 0, 0, ARMOpInfoBase + 2272, 0, 0, 0x8900ULL }, // VMOVRH |
| 7411 | { 3044, 4, 1, 4, 571, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMOVNv8i8 |
| 7412 | { 3043, 4, 1, 4, 571, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMOVNv4i16 |
| 7413 | { 3042, 4, 1, 4, 571, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMOVNv2i32 |
| 7414 | { 3041, 4, 1, 4, 572, 0, 0, ARMOpInfoBase + 1824, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMOVLuv8i16 |
| 7415 | { 3040, 4, 1, 4, 572, 0, 0, ARMOpInfoBase + 1824, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMOVLuv4i32 |
| 7416 | { 3039, 4, 1, 4, 572, 0, 0, ARMOpInfoBase + 1824, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMOVLuv2i64 |
| 7417 | { 3038, 4, 1, 4, 572, 0, 0, ARMOpInfoBase + 1824, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMOVLsv8i16 |
| 7418 | { 3037, 4, 1, 4, 572, 0, 0, ARMOpInfoBase + 1824, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMOVLsv4i32 |
| 7419 | { 3036, 4, 1, 4, 572, 0, 0, ARMOpInfoBase + 1824, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VMOVLsv2i64 |
| 7420 | { 3035, 4, 1, 4, 1210, 0, 0, ARMOpInfoBase + 2268, 0, 0, 0x8a00ULL }, // VMOVHR |
| 7421 | { 3034, 2, 1, 4, 1209, 0, 0, ARMOpInfoBase + 1799, 0, 0, 0x8780ULL }, // VMOVH |
| 7422 | { 3033, 5, 1, 4, 581, 0, 0, ARMOpInfoBase + 2263, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::RegSequence), 0x18a80ULL }, // VMOVDRR |
| 7423 | { 3032, 4, 1, 4, 1211, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VMOVD |
| 7424 | { 3031, 4, 1, 4, 50, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // VMMLA |
| 7425 | { 3030, 6, 1, 4, 978, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSv8i8 |
| 7426 | { 3029, 6, 1, 4, 547, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSv8i16 |
| 7427 | { 3028, 6, 1, 4, 546, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSv4i32 |
| 7428 | { 3027, 6, 1, 4, 978, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSv4i16 |
| 7429 | { 3026, 6, 1, 4, 977, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSv2i32 |
| 7430 | { 3025, 6, 1, 4, 547, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSv16i8 |
| 7431 | { 3024, 7, 1, 4, 547, 0, 0, ARMOpInfoBase + 2256, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSslv8i16 |
| 7432 | { 3023, 7, 1, 4, 546, 0, 0, ARMOpInfoBase + 2242, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSslv4i32 |
| 7433 | { 3022, 7, 1, 4, 978, 0, 0, ARMOpInfoBase + 2249, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSslv4i16 |
| 7434 | { 3021, 7, 1, 4, 977, 0, 0, ARMOpInfoBase + 2235, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSslv2i32 |
| 7435 | { 3020, 7, 1, 4, 545, 0, 0, ARMOpInfoBase + 2256, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSslhq |
| 7436 | { 3019, 7, 1, 4, 544, 0, 0, ARMOpInfoBase + 2249, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSslhd |
| 7437 | { 3018, 7, 1, 4, 545, 0, 0, ARMOpInfoBase + 2242, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSslfq |
| 7438 | { 3017, 7, 1, 4, 544, 0, 0, ARMOpInfoBase + 2235, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSslfd |
| 7439 | { 3016, 6, 1, 4, 545, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLShq |
| 7440 | { 3015, 6, 1, 4, 544, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLShd |
| 7441 | { 3014, 6, 1, 4, 545, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSfq |
| 7442 | { 3013, 6, 1, 4, 544, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSfd |
| 7443 | { 3012, 6, 1, 4, 543, 1, 0, ARMOpInfoBase + 1873, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28800ULL }, // VMLSS |
| 7444 | { 3011, 6, 1, 4, 542, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSLuv8i16 |
| 7445 | { 3010, 6, 1, 4, 542, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSLuv4i32 |
| 7446 | { 3009, 6, 1, 4, 541, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSLuv2i64 |
| 7447 | { 3008, 6, 1, 4, 542, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSLsv8i16 |
| 7448 | { 3007, 6, 1, 4, 542, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSLsv4i32 |
| 7449 | { 3006, 6, 1, 4, 541, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLSLsv2i64 |
| 7450 | { 3005, 7, 1, 4, 542, 0, 0, ARMOpInfoBase + 2228, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSLsluv4i16 |
| 7451 | { 3004, 7, 1, 4, 541, 0, 0, ARMOpInfoBase + 2221, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSLsluv2i32 |
| 7452 | { 3003, 7, 1, 4, 542, 0, 0, ARMOpInfoBase + 2228, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSLslsv4i16 |
| 7453 | { 3002, 7, 1, 4, 541, 0, 0, ARMOpInfoBase + 2221, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLSLslsv2i32 |
| 7454 | { 3001, 6, 1, 4, 540, 1, 0, ARMOpInfoBase + 1853, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VMLSH |
| 7455 | { 3000, 6, 1, 4, 539, 1, 0, ARMOpInfoBase + 1658, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VMLSD |
| 7456 | { 2999, 6, 1, 4, 978, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAv8i8 |
| 7457 | { 2998, 6, 1, 4, 547, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAv8i16 |
| 7458 | { 2997, 6, 1, 4, 546, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAv4i32 |
| 7459 | { 2996, 6, 1, 4, 978, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAv4i16 |
| 7460 | { 2995, 6, 1, 4, 977, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAv2i32 |
| 7461 | { 2994, 6, 1, 4, 547, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAv16i8 |
| 7462 | { 2993, 7, 1, 4, 547, 0, 0, ARMOpInfoBase + 2256, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLAslv8i16 |
| 7463 | { 2992, 7, 1, 4, 546, 0, 0, ARMOpInfoBase + 2242, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLAslv4i32 |
| 7464 | { 2991, 7, 1, 4, 978, 0, 0, ARMOpInfoBase + 2249, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLAslv4i16 |
| 7465 | { 2990, 7, 1, 4, 977, 0, 0, ARMOpInfoBase + 2235, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLAslv2i32 |
| 7466 | { 2989, 7, 1, 4, 545, 0, 0, ARMOpInfoBase + 2256, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLAslhq |
| 7467 | { 2988, 7, 1, 4, 544, 0, 0, ARMOpInfoBase + 2249, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLAslhd |
| 7468 | { 2987, 7, 1, 4, 545, 0, 0, ARMOpInfoBase + 2242, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLAslfq |
| 7469 | { 2986, 7, 1, 4, 544, 0, 0, ARMOpInfoBase + 2235, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLAslfd |
| 7470 | { 2985, 6, 1, 4, 545, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAhq |
| 7471 | { 2984, 6, 1, 4, 544, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAhd |
| 7472 | { 2983, 6, 1, 4, 545, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAfq |
| 7473 | { 2982, 6, 1, 4, 544, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLAfd |
| 7474 | { 2981, 6, 1, 4, 543, 1, 0, ARMOpInfoBase + 1873, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28800ULL }, // VMLAS |
| 7475 | { 2980, 6, 1, 4, 542, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLALuv8i16 |
| 7476 | { 2979, 6, 1, 4, 542, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLALuv4i32 |
| 7477 | { 2978, 6, 1, 4, 541, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLALuv2i64 |
| 7478 | { 2977, 6, 1, 4, 542, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLALsv8i16 |
| 7479 | { 2976, 6, 1, 4, 542, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLALsv4i32 |
| 7480 | { 2975, 6, 1, 4, 541, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VMLALsv2i64 |
| 7481 | { 2974, 7, 1, 4, 542, 0, 0, ARMOpInfoBase + 2228, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLALsluv4i16 |
| 7482 | { 2973, 7, 1, 4, 541, 0, 0, ARMOpInfoBase + 2221, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLALsluv2i32 |
| 7483 | { 2972, 7, 1, 4, 542, 0, 0, ARMOpInfoBase + 2228, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLALslsv4i16 |
| 7484 | { 2971, 7, 1, 4, 541, 0, 0, ARMOpInfoBase + 2221, 0, 0|(1ULL<<MCID::Predicable), 0x11400ULL }, // VMLALslsv2i32 |
| 7485 | { 2970, 6, 1, 4, 540, 1, 0, ARMOpInfoBase + 1853, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VMLAH |
| 7486 | { 2969, 6, 1, 4, 539, 1, 0, ARMOpInfoBase + 1658, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VMLAD |
| 7487 | { 2968, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINuv8i8 |
| 7488 | { 2967, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINuv8i16 |
| 7489 | { 2966, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINuv4i32 |
| 7490 | { 2965, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINuv4i16 |
| 7491 | { 2964, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINuv2i32 |
| 7492 | { 2963, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINuv16i8 |
| 7493 | { 2962, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINsv8i8 |
| 7494 | { 2961, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINsv8i16 |
| 7495 | { 2960, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINsv4i32 |
| 7496 | { 2959, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINsv4i16 |
| 7497 | { 2958, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINsv2i32 |
| 7498 | { 2957, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINsv16i8 |
| 7499 | { 2956, 5, 1, 4, 522, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINhq |
| 7500 | { 2955, 5, 1, 4, 521, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINhd |
| 7501 | { 2954, 5, 1, 4, 522, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINfq |
| 7502 | { 2953, 5, 1, 4, 521, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMINfd |
| 7503 | { 2952, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXuv8i8 |
| 7504 | { 2951, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXuv8i16 |
| 7505 | { 2950, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXuv4i32 |
| 7506 | { 2949, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXuv4i16 |
| 7507 | { 2948, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXuv2i32 |
| 7508 | { 2947, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXuv16i8 |
| 7509 | { 2946, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXsv8i8 |
| 7510 | { 2945, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXsv8i16 |
| 7511 | { 2944, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXsv4i32 |
| 7512 | { 2943, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXsv4i16 |
| 7513 | { 2942, 5, 1, 4, 960, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXsv2i32 |
| 7514 | { 2941, 5, 1, 4, 774, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXsv16i8 |
| 7515 | { 2940, 5, 1, 4, 522, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXhq |
| 7516 | { 2939, 5, 1, 4, 521, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXhd |
| 7517 | { 2938, 5, 1, 4, 522, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXfq |
| 7518 | { 2937, 5, 1, 4, 521, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VMAXfd |
| 7519 | { 2936, 4, 0, 4, 954, 35, 3, ARMOpInfoBase + 2217, 153, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // VLSTM_T2 |
| 7520 | { 2935, 4, 0, 4, 954, 19, 3, ARMOpInfoBase + 2217, 131, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // VLSTM |
| 7521 | { 2934, 4, 0, 4, 934, 0, 35, ARMOpInfoBase + 2217, 96, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // VLLDM_T2 |
| 7522 | { 2933, 4, 0, 4, 934, 0, 19, ARMOpInfoBase + 2217, 77, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL }, // VLLDM |
| 7523 | { 2932, 5, 1, 4, 746, 0, 1, ARMOpInfoBase + 2190, 73, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VLDR_VPR_pre |
| 7524 | { 2931, 5, 1, 4, 746, 0, 1, ARMOpInfoBase + 2190, 73, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_VPR_post |
| 7525 | { 2930, 4, 0, 4, 746, 0, 1, ARMOpInfoBase + 2186, 73, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_VPR_off |
| 7526 | { 2929, 6, 2, 4, 746, 0, 0, ARMOpInfoBase + 2211, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VLDR_P0_pre |
| 7527 | { 2928, 6, 2, 4, 746, 0, 0, ARMOpInfoBase + 2211, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_P0_post |
| 7528 | { 2927, 5, 1, 4, 746, 0, 0, ARMOpInfoBase + 2206, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_P0_off |
| 7529 | { 2926, 5, 1, 4, 746, 0, 1, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VLDR_FPSCR_pre |
| 7530 | { 2925, 5, 1, 4, 746, 0, 1, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_FPSCR_post |
| 7531 | { 2924, 4, 0, 4, 746, 0, 1, ARMOpInfoBase + 2186, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_FPSCR_off |
| 7532 | { 2923, 6, 2, 4, 746, 0, 0, ARMOpInfoBase + 2200, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VLDR_FPSCR_NZCVQC_pre |
| 7533 | { 2922, 6, 2, 4, 746, 0, 0, ARMOpInfoBase + 2200, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_FPSCR_NZCVQC_post |
| 7534 | { 2921, 5, 1, 4, 746, 0, 0, ARMOpInfoBase + 2195, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_FPSCR_NZCVQC_off |
| 7535 | { 2920, 5, 1, 4, 746, 0, 1, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VLDR_FPCXTS_pre |
| 7536 | { 2919, 5, 1, 4, 746, 0, 1, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_FPCXTS_post |
| 7537 | { 2918, 4, 0, 4, 746, 0, 1, ARMOpInfoBase + 2186, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_FPCXTS_off |
| 7538 | { 2917, 5, 1, 4, 746, 0, 1, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL }, // VLDR_FPCXTNS_pre |
| 7539 | { 2916, 5, 1, 4, 746, 0, 1, ARMOpInfoBase + 2190, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_FPCXTNS_post |
| 7540 | { 2915, 4, 0, 4, 746, 0, 1, ARMOpInfoBase + 2186, 76, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL }, // VLDR_FPCXTNS_off |
| 7541 | { 2914, 5, 1, 4, 589, 0, 0, ARMOpInfoBase + 2181, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL }, // VLDRS |
| 7542 | { 2913, 5, 1, 4, 745, 0, 0, ARMOpInfoBase + 2176, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x18b13ULL }, // VLDRH |
| 7543 | { 2912, 5, 1, 4, 588, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL }, // VLDRD |
| 7544 | { 2911, 5, 1, 4, 595, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL }, // VLDMSIA_UPD |
| 7545 | { 2910, 4, 0, 4, 594, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18b84ULL }, // VLDMSIA |
| 7546 | { 2909, 5, 1, 4, 595, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL }, // VLDMSDB_UPD |
| 7547 | { 2908, 4, 1, 4, 592, 0, 0, ARMOpInfoBase + 2172, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18004ULL }, // VLDMQIA |
| 7548 | { 2907, 5, 1, 4, 595, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL }, // VLDMDIA_UPD |
| 7549 | { 2906, 4, 0, 4, 594, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8b84ULL }, // VLDMDIA |
| 7550 | { 2905, 5, 1, 4, 595, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL }, // VLDMDDB_UPD |
| 7551 | { 2904, 8, 2, 4, 617, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4q8oddPseudo_UPD |
| 7552 | { 2903, 6, 1, 4, 615, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4q8oddPseudo |
| 7553 | { 2902, 10, 5, 4, 616, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4q8_UPD |
| 7554 | { 2901, 8, 2, 4, 617, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4q8Pseudo_UPD |
| 7555 | { 2900, 8, 4, 4, 614, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4q8 |
| 7556 | { 2899, 8, 2, 4, 617, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4q32oddPseudo_UPD |
| 7557 | { 2898, 6, 1, 4, 615, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4q32oddPseudo |
| 7558 | { 2897, 10, 5, 4, 616, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4q32_UPD |
| 7559 | { 2896, 8, 2, 4, 617, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4q32Pseudo_UPD |
| 7560 | { 2895, 8, 4, 4, 614, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4q32 |
| 7561 | { 2894, 8, 2, 4, 617, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4q16oddPseudo_UPD |
| 7562 | { 2893, 6, 1, 4, 615, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4q16oddPseudo |
| 7563 | { 2892, 10, 5, 4, 616, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4q16_UPD |
| 7564 | { 2891, 8, 2, 4, 617, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4q16Pseudo_UPD |
| 7565 | { 2890, 8, 4, 4, 614, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4q16 |
| 7566 | { 2889, 10, 5, 4, 616, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4d8_UPD |
| 7567 | { 2888, 7, 2, 4, 617, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4d8Pseudo_UPD |
| 7568 | { 2887, 5, 1, 4, 615, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4d8Pseudo |
| 7569 | { 2886, 8, 4, 4, 614, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4d8 |
| 7570 | { 2885, 10, 5, 4, 616, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4d32_UPD |
| 7571 | { 2884, 7, 2, 4, 617, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4d32Pseudo_UPD |
| 7572 | { 2883, 5, 1, 4, 615, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4d32Pseudo |
| 7573 | { 2882, 8, 4, 4, 614, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4d32 |
| 7574 | { 2881, 10, 5, 4, 616, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4d16_UPD |
| 7575 | { 2880, 7, 2, 4, 617, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4d16Pseudo_UPD |
| 7576 | { 2879, 5, 1, 4, 615, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4d16Pseudo |
| 7577 | { 2878, 8, 4, 4, 614, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4d16 |
| 7578 | { 2877, 15, 5, 4, 1006, 0, 0, ARMOpInfoBase + 2157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNq32_UPD |
| 7579 | { 2876, 9, 2, 4, 1007, 0, 0, ARMOpInfoBase + 2117, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNq32Pseudo_UPD |
| 7580 | { 2875, 7, 1, 4, 1005, 0, 0, ARMOpInfoBase + 2110, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNq32Pseudo |
| 7581 | { 2874, 13, 4, 4, 1005, 0, 0, ARMOpInfoBase + 2144, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNq32 |
| 7582 | { 2873, 15, 5, 4, 640, 0, 0, ARMOpInfoBase + 2157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNq16_UPD |
| 7583 | { 2872, 9, 2, 4, 642, 0, 0, ARMOpInfoBase + 2117, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNq16Pseudo_UPD |
| 7584 | { 2871, 7, 1, 4, 637, 0, 0, ARMOpInfoBase + 2110, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNq16Pseudo |
| 7585 | { 2870, 13, 4, 4, 637, 0, 0, ARMOpInfoBase + 2144, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNq16 |
| 7586 | { 2869, 15, 5, 4, 640, 0, 0, ARMOpInfoBase + 2157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNd8_UPD |
| 7587 | { 2868, 9, 2, 4, 642, 0, 0, ARMOpInfoBase + 2054, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNd8Pseudo_UPD |
| 7588 | { 2867, 7, 1, 4, 637, 0, 0, ARMOpInfoBase + 2047, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNd8Pseudo |
| 7589 | { 2866, 13, 4, 4, 637, 0, 0, ARMOpInfoBase + 2144, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNd8 |
| 7590 | { 2865, 15, 5, 4, 1006, 0, 0, ARMOpInfoBase + 2157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNd32_UPD |
| 7591 | { 2864, 9, 2, 4, 1007, 0, 0, ARMOpInfoBase + 2054, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNd32Pseudo_UPD |
| 7592 | { 2863, 7, 1, 4, 1005, 0, 0, ARMOpInfoBase + 2047, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNd32Pseudo |
| 7593 | { 2862, 13, 4, 4, 1005, 0, 0, ARMOpInfoBase + 2144, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNd32 |
| 7594 | { 2861, 15, 5, 4, 640, 0, 0, ARMOpInfoBase + 2157, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNd16_UPD |
| 7595 | { 2860, 9, 2, 4, 642, 0, 0, ARMOpInfoBase + 2054, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNd16Pseudo_UPD |
| 7596 | { 2859, 7, 1, 4, 637, 0, 0, ARMOpInfoBase + 2047, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4LNd16Pseudo |
| 7597 | { 2858, 13, 4, 4, 637, 0, 0, ARMOpInfoBase + 2144, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4LNd16 |
| 7598 | { 2857, 10, 5, 4, 639, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPq8_UPD |
| 7599 | { 2856, 8, 2, 4, 1050, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPq8OddPseudo_UPD |
| 7600 | { 2855, 6, 1, 4, 1049, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPq8OddPseudo |
| 7601 | { 2854, 6, 1, 4, 1049, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPq8EvenPseudo |
| 7602 | { 2853, 8, 4, 4, 636, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPq8 |
| 7603 | { 2852, 10, 5, 4, 639, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPq32_UPD |
| 7604 | { 2851, 8, 2, 4, 1050, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPq32OddPseudo_UPD |
| 7605 | { 2850, 6, 1, 4, 1049, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPq32OddPseudo |
| 7606 | { 2849, 6, 1, 4, 1049, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPq32EvenPseudo |
| 7607 | { 2848, 8, 4, 4, 636, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPq32 |
| 7608 | { 2847, 10, 5, 4, 639, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPq16_UPD |
| 7609 | { 2846, 8, 2, 4, 1050, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPq16OddPseudo_UPD |
| 7610 | { 2845, 6, 1, 4, 1049, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPq16OddPseudo |
| 7611 | { 2844, 6, 1, 4, 1049, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPq16EvenPseudo |
| 7612 | { 2843, 8, 4, 4, 636, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPq16 |
| 7613 | { 2842, 10, 5, 4, 639, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPd8_UPD |
| 7614 | { 2841, 7, 2, 4, 641, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPd8Pseudo_UPD |
| 7615 | { 2840, 5, 1, 4, 638, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPd8Pseudo |
| 7616 | { 2839, 8, 4, 4, 636, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPd8 |
| 7617 | { 2838, 10, 5, 4, 639, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPd32_UPD |
| 7618 | { 2837, 7, 2, 4, 641, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPd32Pseudo_UPD |
| 7619 | { 2836, 5, 1, 4, 638, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPd32Pseudo |
| 7620 | { 2835, 8, 4, 4, 636, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPd32 |
| 7621 | { 2834, 10, 5, 4, 639, 0, 0, ARMOpInfoBase + 2134, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPd16_UPD |
| 7622 | { 2833, 7, 2, 4, 641, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPd16Pseudo_UPD |
| 7623 | { 2832, 5, 1, 4, 638, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD4DUPd16Pseudo |
| 7624 | { 2831, 8, 4, 4, 636, 0, 0, ARMOpInfoBase + 2126, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD4DUPd16 |
| 7625 | { 2830, 8, 2, 4, 613, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3q8oddPseudo_UPD |
| 7626 | { 2829, 6, 1, 4, 611, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3q8oddPseudo |
| 7627 | { 2828, 9, 4, 4, 612, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3q8_UPD |
| 7628 | { 2827, 8, 2, 4, 613, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3q8Pseudo_UPD |
| 7629 | { 2826, 7, 3, 4, 610, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3q8 |
| 7630 | { 2825, 8, 2, 4, 613, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3q32oddPseudo_UPD |
| 7631 | { 2824, 6, 1, 4, 611, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3q32oddPseudo |
| 7632 | { 2823, 9, 4, 4, 612, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3q32_UPD |
| 7633 | { 2822, 8, 2, 4, 613, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3q32Pseudo_UPD |
| 7634 | { 2821, 7, 3, 4, 610, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3q32 |
| 7635 | { 2820, 8, 2, 4, 613, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3q16oddPseudo_UPD |
| 7636 | { 2819, 6, 1, 4, 611, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3q16oddPseudo |
| 7637 | { 2818, 9, 4, 4, 612, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3q16_UPD |
| 7638 | { 2817, 8, 2, 4, 613, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3q16Pseudo_UPD |
| 7639 | { 2816, 7, 3, 4, 610, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3q16 |
| 7640 | { 2815, 9, 4, 4, 612, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3d8_UPD |
| 7641 | { 2814, 7, 2, 4, 613, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3d8Pseudo_UPD |
| 7642 | { 2813, 5, 1, 4, 611, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3d8Pseudo |
| 7643 | { 2812, 7, 3, 4, 610, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3d8 |
| 7644 | { 2811, 9, 4, 4, 612, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3d32_UPD |
| 7645 | { 2810, 7, 2, 4, 613, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3d32Pseudo_UPD |
| 7646 | { 2809, 5, 1, 4, 611, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3d32Pseudo |
| 7647 | { 2808, 7, 3, 4, 610, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3d32 |
| 7648 | { 2807, 9, 4, 4, 612, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3d16_UPD |
| 7649 | { 2806, 7, 2, 4, 613, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3d16Pseudo_UPD |
| 7650 | { 2805, 5, 1, 4, 611, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3d16Pseudo |
| 7651 | { 2804, 7, 3, 4, 610, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3d16 |
| 7652 | { 2803, 13, 4, 4, 1003, 0, 0, ARMOpInfoBase + 2097, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNq32_UPD |
| 7653 | { 2802, 9, 2, 4, 1004, 0, 0, ARMOpInfoBase + 2117, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNq32Pseudo_UPD |
| 7654 | { 2801, 7, 1, 4, 1002, 0, 0, ARMOpInfoBase + 2110, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNq32Pseudo |
| 7655 | { 2800, 11, 3, 4, 1002, 0, 0, ARMOpInfoBase + 2086, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNq32 |
| 7656 | { 2799, 13, 4, 4, 633, 0, 0, ARMOpInfoBase + 2097, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNq16_UPD |
| 7657 | { 2798, 9, 2, 4, 635, 0, 0, ARMOpInfoBase + 2117, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNq16Pseudo_UPD |
| 7658 | { 2797, 7, 1, 4, 631, 0, 0, ARMOpInfoBase + 2110, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNq16Pseudo |
| 7659 | { 2796, 11, 3, 4, 631, 0, 0, ARMOpInfoBase + 2086, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNq16 |
| 7660 | { 2795, 13, 4, 4, 633, 0, 0, ARMOpInfoBase + 2097, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNd8_UPD |
| 7661 | { 2794, 9, 2, 4, 635, 0, 0, ARMOpInfoBase + 2054, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNd8Pseudo_UPD |
| 7662 | { 2793, 7, 1, 4, 631, 0, 0, ARMOpInfoBase + 2047, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNd8Pseudo |
| 7663 | { 2792, 11, 3, 4, 631, 0, 0, ARMOpInfoBase + 2086, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNd8 |
| 7664 | { 2791, 13, 4, 4, 1003, 0, 0, ARMOpInfoBase + 2097, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNd32_UPD |
| 7665 | { 2790, 9, 2, 4, 1004, 0, 0, ARMOpInfoBase + 2054, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNd32Pseudo_UPD |
| 7666 | { 2789, 7, 1, 4, 1002, 0, 0, ARMOpInfoBase + 2047, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNd32Pseudo |
| 7667 | { 2788, 11, 3, 4, 1002, 0, 0, ARMOpInfoBase + 2086, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNd32 |
| 7668 | { 2787, 13, 4, 4, 633, 0, 0, ARMOpInfoBase + 2097, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNd16_UPD |
| 7669 | { 2786, 9, 2, 4, 635, 0, 0, ARMOpInfoBase + 2054, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNd16Pseudo_UPD |
| 7670 | { 2785, 7, 1, 4, 631, 0, 0, ARMOpInfoBase + 2047, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3LNd16Pseudo |
| 7671 | { 2784, 11, 3, 4, 631, 0, 0, ARMOpInfoBase + 2086, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3LNd16 |
| 7672 | { 2783, 9, 4, 4, 632, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPq8_UPD |
| 7673 | { 2782, 8, 2, 4, 1048, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPq8OddPseudo_UPD |
| 7674 | { 2781, 6, 1, 4, 1047, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPq8OddPseudo |
| 7675 | { 2780, 6, 1, 4, 1047, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPq8EvenPseudo |
| 7676 | { 2779, 7, 3, 4, 630, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPq8 |
| 7677 | { 2778, 9, 4, 4, 632, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPq32_UPD |
| 7678 | { 2777, 8, 2, 4, 1048, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPq32OddPseudo_UPD |
| 7679 | { 2776, 6, 1, 4, 1047, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPq32OddPseudo |
| 7680 | { 2775, 6, 1, 4, 1047, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPq32EvenPseudo |
| 7681 | { 2774, 7, 3, 4, 630, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPq32 |
| 7682 | { 2773, 9, 4, 4, 632, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPq16_UPD |
| 7683 | { 2772, 8, 2, 4, 1048, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPq16OddPseudo_UPD |
| 7684 | { 2771, 6, 1, 4, 1047, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPq16OddPseudo |
| 7685 | { 2770, 6, 1, 4, 1047, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPq16EvenPseudo |
| 7686 | { 2769, 7, 3, 4, 630, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPq16 |
| 7687 | { 2768, 9, 4, 4, 632, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPd8_UPD |
| 7688 | { 2767, 7, 2, 4, 634, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPd8Pseudo_UPD |
| 7689 | { 2766, 5, 1, 4, 630, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPd8Pseudo |
| 7690 | { 2765, 7, 3, 4, 630, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPd8 |
| 7691 | { 2764, 9, 4, 4, 632, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPd32_UPD |
| 7692 | { 2763, 7, 2, 4, 634, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPd32Pseudo_UPD |
| 7693 | { 2762, 5, 1, 4, 630, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPd32Pseudo |
| 7694 | { 2761, 7, 3, 4, 630, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPd32 |
| 7695 | { 2760, 9, 4, 4, 632, 0, 0, ARMOpInfoBase + 2077, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPd16_UPD |
| 7696 | { 2759, 7, 2, 4, 634, 0, 0, ARMOpInfoBase + 2070, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPd16Pseudo_UPD |
| 7697 | { 2758, 5, 1, 4, 630, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD3DUPd16Pseudo |
| 7698 | { 2757, 7, 3, 4, 630, 0, 0, ARMOpInfoBase + 2063, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD3DUPd16 |
| 7699 | { 2756, 7, 2, 4, 609, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2q8wb_register |
| 7700 | { 2755, 6, 2, 4, 609, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2q8wb_fixed |
| 7701 | { 2754, 7, 2, 4, 609, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2q8PseudoWB_register |
| 7702 | { 2753, 6, 2, 4, 609, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2q8PseudoWB_fixed |
| 7703 | { 2752, 5, 1, 4, 607, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2q8Pseudo |
| 7704 | { 2751, 5, 1, 4, 607, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2q8 |
| 7705 | { 2750, 7, 2, 4, 609, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2q32wb_register |
| 7706 | { 2749, 6, 2, 4, 609, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2q32wb_fixed |
| 7707 | { 2748, 7, 2, 4, 609, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2q32PseudoWB_register |
| 7708 | { 2747, 6, 2, 4, 609, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2q32PseudoWB_fixed |
| 7709 | { 2746, 5, 1, 4, 607, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2q32Pseudo |
| 7710 | { 2745, 5, 1, 4, 607, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2q32 |
| 7711 | { 2744, 7, 2, 4, 609, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2q16wb_register |
| 7712 | { 2743, 6, 2, 4, 609, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2q16wb_fixed |
| 7713 | { 2742, 7, 2, 4, 609, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2q16PseudoWB_register |
| 7714 | { 2741, 6, 2, 4, 609, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2q16PseudoWB_fixed |
| 7715 | { 2740, 5, 1, 4, 607, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2q16Pseudo |
| 7716 | { 2739, 5, 1, 4, 607, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2q16 |
| 7717 | { 2738, 7, 2, 4, 1001, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2d8wb_register |
| 7718 | { 2737, 6, 2, 4, 1001, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2d8wb_fixed |
| 7719 | { 2736, 5, 1, 4, 1000, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2d8 |
| 7720 | { 2735, 7, 2, 4, 1001, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2d32wb_register |
| 7721 | { 2734, 6, 2, 4, 1001, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2d32wb_fixed |
| 7722 | { 2733, 5, 1, 4, 1000, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2d32 |
| 7723 | { 2732, 7, 2, 4, 1001, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2d16wb_register |
| 7724 | { 2731, 6, 2, 4, 1001, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2d16wb_fixed |
| 7725 | { 2730, 5, 1, 4, 1000, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2d16 |
| 7726 | { 2729, 7, 2, 4, 608, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2b8wb_register |
| 7727 | { 2728, 6, 2, 4, 608, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2b8wb_fixed |
| 7728 | { 2727, 5, 1, 4, 606, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2b8 |
| 7729 | { 2726, 7, 2, 4, 608, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2b32wb_register |
| 7730 | { 2725, 6, 2, 4, 608, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2b32wb_fixed |
| 7731 | { 2724, 5, 1, 4, 606, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2b32 |
| 7732 | { 2723, 7, 2, 4, 608, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2b16wb_register |
| 7733 | { 2722, 6, 2, 4, 608, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2b16wb_fixed |
| 7734 | { 2721, 5, 1, 4, 606, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2b16 |
| 7735 | { 2720, 11, 3, 4, 627, 0, 0, ARMOpInfoBase + 2036, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNq32_UPD |
| 7736 | { 2719, 9, 2, 4, 629, 0, 0, ARMOpInfoBase + 2054, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNq32Pseudo_UPD |
| 7737 | { 2718, 7, 1, 4, 626, 0, 0, ARMOpInfoBase + 2047, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNq32Pseudo |
| 7738 | { 2717, 9, 2, 4, 626, 0, 0, ARMOpInfoBase + 2027, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNq32 |
| 7739 | { 2716, 11, 3, 4, 627, 0, 0, ARMOpInfoBase + 2036, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNq16_UPD |
| 7740 | { 2715, 9, 2, 4, 629, 0, 0, ARMOpInfoBase + 2054, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNq16Pseudo_UPD |
| 7741 | { 2714, 7, 1, 4, 626, 0, 0, ARMOpInfoBase + 2047, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNq16Pseudo |
| 7742 | { 2713, 9, 2, 4, 626, 0, 0, ARMOpInfoBase + 2027, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNq16 |
| 7743 | { 2712, 11, 3, 4, 627, 0, 0, ARMOpInfoBase + 2036, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNd8_UPD |
| 7744 | { 2711, 9, 2, 4, 629, 0, 0, ARMOpInfoBase + 1947, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNd8Pseudo_UPD |
| 7745 | { 2710, 7, 1, 4, 626, 0, 0, ARMOpInfoBase + 1940, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNd8Pseudo |
| 7746 | { 2709, 9, 2, 4, 626, 0, 0, ARMOpInfoBase + 2027, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNd8 |
| 7747 | { 2708, 11, 3, 4, 627, 0, 0, ARMOpInfoBase + 2036, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNd32_UPD |
| 7748 | { 2707, 9, 2, 4, 629, 0, 0, ARMOpInfoBase + 1947, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNd32Pseudo_UPD |
| 7749 | { 2706, 7, 1, 4, 626, 0, 0, ARMOpInfoBase + 1940, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNd32Pseudo |
| 7750 | { 2705, 9, 2, 4, 626, 0, 0, ARMOpInfoBase + 2027, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNd32 |
| 7751 | { 2704, 11, 3, 4, 627, 0, 0, ARMOpInfoBase + 2036, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNd16_UPD |
| 7752 | { 2703, 9, 2, 4, 629, 0, 0, ARMOpInfoBase + 1947, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNd16Pseudo_UPD |
| 7753 | { 2702, 7, 1, 4, 626, 0, 0, ARMOpInfoBase + 1940, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2LNd16Pseudo |
| 7754 | { 2701, 9, 2, 4, 626, 0, 0, ARMOpInfoBase + 2027, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2LNd16 |
| 7755 | { 2700, 8, 2, 4, 1046, 0, 0, ARMOpInfoBase + 2019, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq8OddPseudoWB_register |
| 7756 | { 2699, 7, 2, 4, 1046, 0, 0, ARMOpInfoBase + 2012, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq8OddPseudoWB_fixed |
| 7757 | { 2698, 6, 1, 4, 1046, 0, 0, ARMOpInfoBase + 2006, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq8OddPseudo |
| 7758 | { 2697, 6, 1, 4, 1046, 0, 0, ARMOpInfoBase + 2006, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq8EvenPseudo |
| 7759 | { 2696, 8, 2, 4, 1046, 0, 0, ARMOpInfoBase + 2019, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq32OddPseudoWB_register |
| 7760 | { 2695, 7, 2, 4, 1046, 0, 0, ARMOpInfoBase + 2012, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq32OddPseudoWB_fixed |
| 7761 | { 2694, 6, 1, 4, 1046, 0, 0, ARMOpInfoBase + 2006, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq32OddPseudo |
| 7762 | { 2693, 6, 1, 4, 1046, 0, 0, ARMOpInfoBase + 2006, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq32EvenPseudo |
| 7763 | { 2692, 8, 2, 4, 1046, 0, 0, ARMOpInfoBase + 2019, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq16OddPseudoWB_register |
| 7764 | { 2691, 7, 2, 4, 1046, 0, 0, ARMOpInfoBase + 2012, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq16OddPseudoWB_fixed |
| 7765 | { 2690, 6, 1, 4, 1046, 0, 0, ARMOpInfoBase + 2006, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq16OddPseudo |
| 7766 | { 2689, 6, 1, 4, 1046, 0, 0, ARMOpInfoBase + 2006, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD2DUPq16EvenPseudo |
| 7767 | { 2688, 7, 2, 4, 628, 0, 0, ARMOpInfoBase + 1999, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd8x2wb_register |
| 7768 | { 2687, 6, 2, 4, 628, 0, 0, ARMOpInfoBase + 1993, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd8x2wb_fixed |
| 7769 | { 2686, 5, 1, 4, 625, 0, 0, ARMOpInfoBase + 1988, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd8x2 |
| 7770 | { 2685, 7, 2, 4, 628, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd8wb_register |
| 7771 | { 2684, 6, 2, 4, 628, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd8wb_fixed |
| 7772 | { 2683, 5, 1, 4, 625, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd8 |
| 7773 | { 2682, 7, 2, 4, 628, 0, 0, ARMOpInfoBase + 1999, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd32x2wb_register |
| 7774 | { 2681, 6, 2, 4, 628, 0, 0, ARMOpInfoBase + 1993, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd32x2wb_fixed |
| 7775 | { 2680, 5, 1, 4, 625, 0, 0, ARMOpInfoBase + 1988, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd32x2 |
| 7776 | { 2679, 7, 2, 4, 628, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd32wb_register |
| 7777 | { 2678, 6, 2, 4, 628, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd32wb_fixed |
| 7778 | { 2677, 5, 1, 4, 625, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd32 |
| 7779 | { 2676, 7, 2, 4, 628, 0, 0, ARMOpInfoBase + 1999, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd16x2wb_register |
| 7780 | { 2675, 6, 2, 4, 628, 0, 0, ARMOpInfoBase + 1993, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd16x2wb_fixed |
| 7781 | { 2674, 5, 1, 4, 625, 0, 0, ARMOpInfoBase + 1988, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd16x2 |
| 7782 | { 2673, 7, 2, 4, 628, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd16wb_register |
| 7783 | { 2672, 6, 2, 4, 628, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd16wb_fixed |
| 7784 | { 2671, 5, 1, 4, 625, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD2DUPd16 |
| 7785 | { 2670, 7, 2, 4, 601, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q8wb_register |
| 7786 | { 2669, 6, 2, 4, 601, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q8wb_fixed |
| 7787 | { 2668, 8, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q8LowTPseudo_UPD |
| 7788 | { 2667, 8, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q8LowQPseudo_UPD |
| 7789 | { 2666, 8, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q8HighTPseudo_UPD |
| 7790 | { 2665, 6, 1, 4, 1045, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q8HighTPseudo |
| 7791 | { 2664, 8, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q8HighQPseudo_UPD |
| 7792 | { 2663, 6, 1, 4, 1044, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q8HighQPseudo |
| 7793 | { 2662, 5, 1, 4, 599, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q8 |
| 7794 | { 2661, 7, 2, 4, 601, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q64wb_register |
| 7795 | { 2660, 6, 2, 4, 601, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q64wb_fixed |
| 7796 | { 2659, 8, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q64LowTPseudo_UPD |
| 7797 | { 2658, 8, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q64LowQPseudo_UPD |
| 7798 | { 2657, 8, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q64HighTPseudo_UPD |
| 7799 | { 2656, 6, 1, 4, 1045, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q64HighTPseudo |
| 7800 | { 2655, 8, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q64HighQPseudo_UPD |
| 7801 | { 2654, 6, 1, 4, 1044, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q64HighQPseudo |
| 7802 | { 2653, 5, 1, 4, 599, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q64 |
| 7803 | { 2652, 7, 2, 4, 601, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q32wb_register |
| 7804 | { 2651, 6, 2, 4, 601, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q32wb_fixed |
| 7805 | { 2650, 8, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q32LowTPseudo_UPD |
| 7806 | { 2649, 8, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q32LowQPseudo_UPD |
| 7807 | { 2648, 8, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q32HighTPseudo_UPD |
| 7808 | { 2647, 6, 1, 4, 1045, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q32HighTPseudo |
| 7809 | { 2646, 8, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q32HighQPseudo_UPD |
| 7810 | { 2645, 6, 1, 4, 1044, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q32HighQPseudo |
| 7811 | { 2644, 5, 1, 4, 599, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q32 |
| 7812 | { 2643, 7, 2, 4, 601, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q16wb_register |
| 7813 | { 2642, 6, 2, 4, 601, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q16wb_fixed |
| 7814 | { 2641, 8, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q16LowTPseudo_UPD |
| 7815 | { 2640, 8, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q16LowQPseudo_UPD |
| 7816 | { 2639, 8, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q16HighTPseudo_UPD |
| 7817 | { 2638, 6, 1, 4, 1045, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q16HighTPseudo |
| 7818 | { 2637, 8, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1980, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q16HighQPseudo_UPD |
| 7819 | { 2636, 6, 1, 4, 1044, 0, 0, ARMOpInfoBase + 1974, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1q16HighQPseudo |
| 7820 | { 2635, 5, 1, 4, 599, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1q16 |
| 7821 | { 2634, 7, 2, 4, 600, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d8wb_register |
| 7822 | { 2633, 6, 2, 4, 600, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d8wb_fixed |
| 7823 | { 2632, 7, 2, 4, 603, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d8Twb_register |
| 7824 | { 2631, 6, 2, 4, 603, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d8Twb_fixed |
| 7825 | { 2630, 7, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d8TPseudoWB_register |
| 7826 | { 2629, 6, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d8TPseudoWB_fixed |
| 7827 | { 2628, 5, 1, 4, 1045, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d8TPseudo |
| 7828 | { 2627, 5, 1, 4, 602, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d8T |
| 7829 | { 2626, 7, 2, 4, 605, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d8Qwb_register |
| 7830 | { 2625, 6, 2, 4, 605, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d8Qwb_fixed |
| 7831 | { 2624, 7, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d8QPseudoWB_register |
| 7832 | { 2623, 6, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d8QPseudoWB_fixed |
| 7833 | { 2622, 5, 1, 4, 1044, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d8QPseudo |
| 7834 | { 2621, 5, 1, 4, 604, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d8Q |
| 7835 | { 2620, 5, 1, 4, 598, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d8 |
| 7836 | { 2619, 7, 2, 4, 600, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d64wb_register |
| 7837 | { 2618, 6, 2, 4, 600, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d64wb_fixed |
| 7838 | { 2617, 7, 2, 4, 603, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d64Twb_register |
| 7839 | { 2616, 6, 2, 4, 603, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d64Twb_fixed |
| 7840 | { 2615, 7, 2, 4, 602, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d64TPseudoWB_register |
| 7841 | { 2614, 6, 2, 4, 602, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d64TPseudoWB_fixed |
| 7842 | { 2613, 5, 1, 4, 602, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d64TPseudo |
| 7843 | { 2612, 5, 1, 4, 602, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d64T |
| 7844 | { 2611, 7, 2, 4, 605, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d64Qwb_register |
| 7845 | { 2610, 6, 2, 4, 605, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d64Qwb_fixed |
| 7846 | { 2609, 7, 2, 4, 604, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d64QPseudoWB_register |
| 7847 | { 2608, 6, 2, 4, 604, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d64QPseudoWB_fixed |
| 7848 | { 2607, 5, 1, 4, 604, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d64QPseudo |
| 7849 | { 2606, 5, 1, 4, 604, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d64Q |
| 7850 | { 2605, 5, 1, 4, 598, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d64 |
| 7851 | { 2604, 7, 2, 4, 600, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d32wb_register |
| 7852 | { 2603, 6, 2, 4, 600, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d32wb_fixed |
| 7853 | { 2602, 7, 2, 4, 603, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d32Twb_register |
| 7854 | { 2601, 6, 2, 4, 603, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d32Twb_fixed |
| 7855 | { 2600, 7, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d32TPseudoWB_register |
| 7856 | { 2599, 6, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d32TPseudoWB_fixed |
| 7857 | { 2598, 5, 1, 4, 1045, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d32TPseudo |
| 7858 | { 2597, 5, 1, 4, 602, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d32T |
| 7859 | { 2596, 7, 2, 4, 605, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d32Qwb_register |
| 7860 | { 2595, 6, 2, 4, 605, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d32Qwb_fixed |
| 7861 | { 2594, 7, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d32QPseudoWB_register |
| 7862 | { 2593, 6, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d32QPseudoWB_fixed |
| 7863 | { 2592, 5, 1, 4, 1044, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d32QPseudo |
| 7864 | { 2591, 5, 1, 4, 604, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d32Q |
| 7865 | { 2590, 5, 1, 4, 598, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d32 |
| 7866 | { 2589, 7, 2, 4, 600, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d16wb_register |
| 7867 | { 2588, 6, 2, 4, 600, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d16wb_fixed |
| 7868 | { 2587, 7, 2, 4, 603, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d16Twb_register |
| 7869 | { 2586, 6, 2, 4, 603, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d16Twb_fixed |
| 7870 | { 2585, 7, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d16TPseudoWB_register |
| 7871 | { 2584, 6, 2, 4, 1045, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d16TPseudoWB_fixed |
| 7872 | { 2583, 5, 1, 4, 1045, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d16TPseudo |
| 7873 | { 2582, 5, 1, 4, 602, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d16T |
| 7874 | { 2581, 7, 2, 4, 605, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d16Qwb_register |
| 7875 | { 2580, 6, 2, 4, 605, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d16Qwb_fixed |
| 7876 | { 2579, 7, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1967, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d16QPseudoWB_register |
| 7877 | { 2578, 6, 2, 4, 1044, 0, 0, ARMOpInfoBase + 1961, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d16QPseudoWB_fixed |
| 7878 | { 2577, 5, 1, 4, 1044, 0, 0, ARMOpInfoBase + 1956, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1d16QPseudo |
| 7879 | { 2576, 5, 1, 4, 604, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d16Q |
| 7880 | { 2575, 5, 1, 4, 598, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1d16 |
| 7881 | { 2574, 9, 2, 4, 624, 0, 0, ARMOpInfoBase + 1947, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1LNq8Pseudo_UPD |
| 7882 | { 2573, 7, 1, 4, 621, 0, 0, ARMOpInfoBase + 1940, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL }, // VLD1LNq8Pseudo |
| 7883 | { 2572, 9, 2, 4, 624, 0, 0, ARMOpInfoBase + 1947, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1LNq32Pseudo_UPD |
| 7884 | { 2571, 7, 1, 4, 621, 0, 0, ARMOpInfoBase + 1940, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL }, // VLD1LNq32Pseudo |
| 7885 | { 2570, 9, 2, 4, 624, 0, 0, ARMOpInfoBase + 1947, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL }, // VLD1LNq16Pseudo_UPD |
| 7886 | { 2569, 7, 1, 4, 621, 0, 0, ARMOpInfoBase + 1940, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL }, // VLD1LNq16Pseudo |
| 7887 | { 2568, 9, 2, 4, 624, 0, 0, ARMOpInfoBase + 1931, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1LNd8_UPD |
| 7888 | { 2567, 7, 1, 4, 620, 0, 0, ARMOpInfoBase + 1924, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VLD1LNd8 |
| 7889 | { 2566, 9, 2, 4, 624, 0, 0, ARMOpInfoBase + 1931, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1LNd32_UPD |
| 7890 | { 2565, 7, 1, 4, 621, 0, 0, ARMOpInfoBase + 1924, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VLD1LNd32 |
| 7891 | { 2564, 9, 2, 4, 624, 0, 0, ARMOpInfoBase + 1931, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1LNd16_UPD |
| 7892 | { 2563, 7, 1, 4, 620, 0, 0, ARMOpInfoBase + 1924, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VLD1LNd16 |
| 7893 | { 2562, 7, 2, 4, 622, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPq8wb_register |
| 7894 | { 2561, 6, 2, 4, 623, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPq8wb_fixed |
| 7895 | { 2560, 5, 1, 4, 619, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VLD1DUPq8 |
| 7896 | { 2559, 7, 2, 4, 622, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPq32wb_register |
| 7897 | { 2558, 6, 2, 4, 623, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPq32wb_fixed |
| 7898 | { 2557, 5, 1, 4, 619, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VLD1DUPq32 |
| 7899 | { 2556, 7, 2, 4, 622, 0, 0, ARMOpInfoBase + 1917, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPq16wb_register |
| 7900 | { 2555, 6, 2, 4, 623, 0, 0, ARMOpInfoBase + 1911, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPq16wb_fixed |
| 7901 | { 2554, 5, 1, 4, 619, 0, 0, ARMOpInfoBase + 1906, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VLD1DUPq16 |
| 7902 | { 2553, 7, 2, 4, 622, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPd8wb_register |
| 7903 | { 2552, 6, 2, 4, 622, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPd8wb_fixed |
| 7904 | { 2551, 5, 1, 4, 618, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VLD1DUPd8 |
| 7905 | { 2550, 7, 2, 4, 622, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPd32wb_register |
| 7906 | { 2549, 6, 2, 4, 622, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPd32wb_fixed |
| 7907 | { 2548, 5, 1, 4, 618, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VLD1DUPd32 |
| 7908 | { 2547, 7, 2, 4, 622, 0, 0, ARMOpInfoBase + 1899, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPd16wb_register |
| 7909 | { 2546, 6, 2, 4, 622, 0, 0, ARMOpInfoBase + 1893, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL }, // VLD1DUPd16wb_fixed |
| 7910 | { 2545, 5, 1, 4, 618, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL }, // VLD1DUPd16 |
| 7911 | { 2544, 4, 1, 4, 957, 0, 0, ARMOpInfoBase + 1810, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL }, // VJCVT |
| 7912 | { 2543, 3, 1, 4, 966, 0, 0, ARMOpInfoBase + 1890, 0, 0, 0x8780ULL }, // VINSH |
| 7913 | { 2542, 5, 1, 4, 469, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBuv8i8 |
| 7914 | { 2541, 5, 1, 4, 468, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBuv8i16 |
| 7915 | { 2540, 5, 1, 4, 468, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBuv4i32 |
| 7916 | { 2539, 5, 1, 4, 469, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBuv4i16 |
| 7917 | { 2538, 5, 1, 4, 469, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBuv2i32 |
| 7918 | { 2537, 5, 1, 4, 468, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBuv16i8 |
| 7919 | { 2536, 5, 1, 4, 469, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBsv8i8 |
| 7920 | { 2535, 5, 1, 4, 468, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBsv8i16 |
| 7921 | { 2534, 5, 1, 4, 468, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBsv4i32 |
| 7922 | { 2533, 5, 1, 4, 469, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBsv4i16 |
| 7923 | { 2532, 5, 1, 4, 469, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBsv2i32 |
| 7924 | { 2531, 5, 1, 4, 468, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VHSUBsv16i8 |
| 7925 | { 2530, 5, 1, 4, 772, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDuv8i8 |
| 7926 | { 2529, 5, 1, 4, 773, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDuv8i16 |
| 7927 | { 2528, 5, 1, 4, 773, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDuv4i32 |
| 7928 | { 2527, 5, 1, 4, 772, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDuv4i16 |
| 7929 | { 2526, 5, 1, 4, 772, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDuv2i32 |
| 7930 | { 2525, 5, 1, 4, 773, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDuv16i8 |
| 7931 | { 2524, 5, 1, 4, 772, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDsv8i8 |
| 7932 | { 2523, 5, 1, 4, 773, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDsv8i16 |
| 7933 | { 2522, 5, 1, 4, 773, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDsv4i32 |
| 7934 | { 2521, 5, 1, 4, 772, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDsv4i16 |
| 7935 | { 2520, 5, 1, 4, 772, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDsv2i32 |
| 7936 | { 2519, 5, 1, 4, 773, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VHADDsv16i8 |
| 7937 | { 2518, 5, 1, 4, 583, 0, 0, ARMOpInfoBase + 1885, 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // VGETLNu8 |
| 7938 | { 2517, 5, 1, 4, 583, 0, 0, ARMOpInfoBase + 1885, 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // VGETLNu16 |
| 7939 | { 2516, 5, 1, 4, 584, 0, 0, ARMOpInfoBase + 1885, 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // VGETLNs8 |
| 7940 | { 2515, 5, 1, 4, 584, 0, 0, ARMOpInfoBase + 1885, 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // VGETLNs16 |
| 7941 | { 2514, 5, 1, 4, 1042, 0, 0, ARMOpInfoBase + 1885, 0, 0|(1ULL<<MCID::Predicable), 0x10d80ULL }, // VGETLNi32 |
| 7942 | { 2513, 3, 1, 4, 1248, 0, 0, ARMOpInfoBase + 1882, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFP_VMINNMS |
| 7943 | { 2512, 3, 1, 4, 1208, 0, 0, ARMOpInfoBase + 1879, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFP_VMINNMH |
| 7944 | { 2511, 3, 1, 4, 1252, 0, 0, ARMOpInfoBase + 1502, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFP_VMINNMD |
| 7945 | { 2510, 3, 1, 4, 1248, 0, 0, ARMOpInfoBase + 1882, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFP_VMAXNMS |
| 7946 | { 2509, 3, 1, 4, 1208, 0, 0, ARMOpInfoBase + 1879, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFP_VMAXNMH |
| 7947 | { 2508, 3, 1, 4, 1252, 0, 0, ARMOpInfoBase + 1502, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFP_VMAXNMD |
| 7948 | { 2507, 6, 1, 4, 549, 1, 0, ARMOpInfoBase + 1873, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VFNMSS |
| 7949 | { 2506, 6, 1, 4, 550, 1, 0, ARMOpInfoBase + 1853, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFNMSH |
| 7950 | { 2505, 6, 1, 4, 548, 1, 0, ARMOpInfoBase + 1658, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VFNMSD |
| 7951 | { 2504, 6, 1, 4, 549, 1, 0, ARMOpInfoBase + 1873, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VFNMAS |
| 7952 | { 2503, 6, 1, 4, 550, 1, 0, ARMOpInfoBase + 1853, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFNMAH |
| 7953 | { 2502, 6, 1, 4, 548, 1, 0, ARMOpInfoBase + 1658, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VFNMAD |
| 7954 | { 2501, 6, 1, 4, 771, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VFMShq |
| 7955 | { 2500, 6, 1, 4, 770, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VFMShd |
| 7956 | { 2499, 6, 1, 4, 552, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VFMSfq |
| 7957 | { 2498, 6, 1, 4, 551, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VFMSfd |
| 7958 | { 2497, 6, 1, 4, 549, 1, 0, ARMOpInfoBase + 1873, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VFMSS |
| 7959 | { 2496, 4, 1, 4, 116, 0, 0, ARMOpInfoBase + 1869, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // VFMSLQI |
| 7960 | { 2495, 3, 1, 4, 0, 0, 0, ARMOpInfoBase + 1866, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // VFMSLQ |
| 7961 | { 2494, 4, 1, 4, 116, 0, 0, ARMOpInfoBase + 1862, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // VFMSLDI |
| 7962 | { 2493, 3, 1, 4, 0, 0, 0, ARMOpInfoBase + 1859, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // VFMSLD |
| 7963 | { 2492, 6, 1, 4, 1207, 1, 0, ARMOpInfoBase + 1853, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFMSH |
| 7964 | { 2491, 6, 1, 4, 548, 1, 0, ARMOpInfoBase + 1658, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VFMSD |
| 7965 | { 2490, 6, 1, 4, 771, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VFMAhq |
| 7966 | { 2489, 6, 1, 4, 770, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VFMAhd |
| 7967 | { 2488, 6, 1, 4, 552, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VFMAfq |
| 7968 | { 2487, 6, 1, 4, 551, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VFMAfd |
| 7969 | { 2486, 6, 1, 4, 549, 1, 0, ARMOpInfoBase + 1873, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VFMAS |
| 7970 | { 2485, 4, 1, 4, 116, 0, 0, ARMOpInfoBase + 1869, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // VFMALQI |
| 7971 | { 2484, 3, 1, 4, 0, 0, 0, ARMOpInfoBase + 1866, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // VFMALQ |
| 7972 | { 2483, 4, 1, 4, 116, 0, 0, ARMOpInfoBase + 1862, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // VFMALDI |
| 7973 | { 2482, 3, 1, 4, 0, 0, 0, ARMOpInfoBase + 1859, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11580ULL }, // VFMALD |
| 7974 | { 2481, 6, 1, 4, 1207, 1, 0, ARMOpInfoBase + 1853, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VFMAH |
| 7975 | { 2480, 6, 1, 4, 548, 1, 0, ARMOpInfoBase + 1658, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VFMAD |
| 7976 | { 2479, 6, 1, 4, 476, 0, 0, ARMOpInfoBase + 1847, 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // VEXTq8 |
| 7977 | { 2478, 6, 1, 4, 476, 0, 0, ARMOpInfoBase + 1847, 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // VEXTq64 |
| 7978 | { 2477, 6, 1, 4, 476, 0, 0, ARMOpInfoBase + 1847, 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // VEXTq32 |
| 7979 | { 2476, 6, 1, 4, 476, 0, 0, ARMOpInfoBase + 1847, 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // VEXTq16 |
| 7980 | { 2475, 6, 1, 4, 475, 0, 0, ARMOpInfoBase + 1841, 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // VEXTd8 |
| 7981 | { 2474, 6, 1, 4, 475, 0, 0, ARMOpInfoBase + 1841, 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // VEXTd32 |
| 7982 | { 2473, 6, 1, 4, 475, 0, 0, ARMOpInfoBase + 1841, 0, 0|(1ULL<<MCID::Predicable), 0x11380ULL }, // VEXTd16 |
| 7983 | { 2472, 5, 1, 4, 758, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VEORq |
| 7984 | { 2471, 5, 1, 4, 757, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VEORd |
| 7985 | { 2470, 5, 1, 4, 575, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // VDUPLN8q |
| 7986 | { 2469, 5, 1, 4, 574, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // VDUPLN8d |
| 7987 | { 2468, 5, 1, 4, 575, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // VDUPLN32q |
| 7988 | { 2467, 5, 1, 4, 574, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // VDUPLN32d |
| 7989 | { 2466, 5, 1, 4, 575, 0, 0, ARMOpInfoBase + 1836, 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // VDUPLN16q |
| 7990 | { 2465, 5, 1, 4, 574, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11100ULL }, // VDUPLN16d |
| 7991 | { 2464, 4, 1, 4, 576, 0, 0, ARMOpInfoBase + 1832, 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // VDUP8q |
| 7992 | { 2463, 4, 1, 4, 768, 0, 0, ARMOpInfoBase + 1828, 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // VDUP8d |
| 7993 | { 2462, 4, 1, 4, 576, 0, 0, ARMOpInfoBase + 1832, 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // VDUP32q |
| 7994 | { 2461, 4, 1, 4, 768, 0, 0, ARMOpInfoBase + 1828, 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // VDUP32d |
| 7995 | { 2460, 4, 1, 4, 576, 0, 0, ARMOpInfoBase + 1832, 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // VDUP16q |
| 7996 | { 2459, 4, 1, 4, 768, 0, 0, ARMOpInfoBase + 1828, 0, 0|(1ULL<<MCID::Predicable), 0x10e80ULL }, // VDUP16d |
| 7997 | { 2458, 5, 1, 4, 675, 1, 0, ARMOpInfoBase + 1705, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VDIVS |
| 7998 | { 2457, 5, 1, 4, 1206, 1, 0, ARMOpInfoBase + 1695, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VDIVH |
| 7999 | { 2456, 5, 1, 4, 677, 1, 0, ARMOpInfoBase + 1669, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VDIVD |
| 8000 | { 2455, 5, 1, 4, 559, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTxu2hq |
| 8001 | { 2454, 5, 1, 4, 560, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTxu2hd |
| 8002 | { 2453, 5, 1, 4, 993, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTxu2fq |
| 8003 | { 2452, 5, 1, 4, 992, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTxu2fd |
| 8004 | { 2451, 5, 1, 4, 559, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTxs2hq |
| 8005 | { 2450, 5, 1, 4, 560, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTxs2hd |
| 8006 | { 2449, 5, 1, 4, 993, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTxs2fq |
| 8007 | { 2448, 5, 1, 4, 992, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTxs2fd |
| 8008 | { 2447, 4, 1, 4, 559, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTu2hq |
| 8009 | { 2446, 4, 1, 4, 560, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTu2hd |
| 8010 | { 2445, 4, 1, 4, 993, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTu2fq |
| 8011 | { 2444, 4, 1, 4, 992, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTu2fd |
| 8012 | { 2443, 4, 1, 4, 559, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTs2hq |
| 8013 | { 2442, 4, 1, 4, 560, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTs2hd |
| 8014 | { 2441, 4, 1, 4, 993, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTs2fq |
| 8015 | { 2440, 4, 1, 4, 992, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTs2fd |
| 8016 | { 2439, 5, 1, 4, 559, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTh2xuq |
| 8017 | { 2438, 5, 1, 4, 560, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTh2xud |
| 8018 | { 2437, 5, 1, 4, 559, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTh2xsq |
| 8019 | { 2436, 5, 1, 4, 560, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTh2xsd |
| 8020 | { 2435, 4, 1, 4, 559, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTh2uq |
| 8021 | { 2434, 4, 1, 4, 560, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTh2ud |
| 8022 | { 2433, 4, 1, 4, 559, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTh2sq |
| 8023 | { 2432, 4, 1, 4, 560, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTh2sd |
| 8024 | { 2431, 4, 1, 4, 559, 0, 0, ARMOpInfoBase + 1824, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTh2f |
| 8025 | { 2430, 5, 1, 4, 993, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTf2xuq |
| 8026 | { 2429, 5, 1, 4, 992, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTf2xud |
| 8027 | { 2428, 5, 1, 4, 993, 0, 0, ARMOpInfoBase + 1819, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTf2xsq |
| 8028 | { 2427, 5, 1, 4, 992, 0, 0, ARMOpInfoBase + 1814, 0, 0|(1ULL<<MCID::Predicable), 0x11080ULL }, // VCVTf2xsd |
| 8029 | { 2426, 4, 1, 4, 993, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTf2uq |
| 8030 | { 2425, 4, 1, 4, 992, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTf2ud |
| 8031 | { 2424, 4, 1, 4, 993, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTf2sq |
| 8032 | { 2423, 4, 1, 4, 992, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTf2sd |
| 8033 | { 2422, 4, 1, 4, 559, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCVTf2h |
| 8034 | { 2421, 5, 1, 4, 556, 1, 0, ARMOpInfoBase + 409, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTTSH |
| 8035 | { 2420, 4, 1, 4, 555, 1, 0, ARMOpInfoBase + 1687, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTTHS |
| 8036 | { 2419, 4, 1, 4, 1251, 1, 0, ARMOpInfoBase + 1806, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTTHD |
| 8037 | { 2418, 5, 1, 4, 955, 1, 0, ARMOpInfoBase + 1801, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTTDH |
| 8038 | { 2417, 4, 1, 4, 558, 1, 0, ARMOpInfoBase + 1810, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTSD |
| 8039 | { 2416, 2, 1, 4, 1247, 0, 0, ARMOpInfoBase + 1799, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTPUS |
| 8040 | { 2415, 2, 1, 4, 1205, 0, 0, ARMOpInfoBase + 1797, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTPUH |
| 8041 | { 2414, 2, 1, 4, 1250, 0, 0, ARMOpInfoBase + 1795, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTPUD |
| 8042 | { 2413, 2, 1, 4, 1247, 0, 0, ARMOpInfoBase + 1799, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTPSS |
| 8043 | { 2412, 2, 1, 4, 1205, 0, 0, ARMOpInfoBase + 1797, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTPSH |
| 8044 | { 2411, 2, 1, 4, 1250, 0, 0, ARMOpInfoBase + 1795, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTPSD |
| 8045 | { 2410, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTPNUQh |
| 8046 | { 2409, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTPNUQf |
| 8047 | { 2408, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTPNUDh |
| 8048 | { 2407, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTPNUDf |
| 8049 | { 2406, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTPNSQh |
| 8050 | { 2405, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTPNSQf |
| 8051 | { 2404, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTPNSDh |
| 8052 | { 2403, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTPNSDf |
| 8053 | { 2402, 2, 1, 4, 1247, 0, 0, ARMOpInfoBase + 1799, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTNUS |
| 8054 | { 2401, 2, 1, 4, 1205, 0, 0, ARMOpInfoBase + 1797, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTNUH |
| 8055 | { 2400, 2, 1, 4, 1250, 0, 0, ARMOpInfoBase + 1795, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTNUD |
| 8056 | { 2399, 2, 1, 4, 1247, 0, 0, ARMOpInfoBase + 1799, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTNSS |
| 8057 | { 2398, 2, 1, 4, 1205, 0, 0, ARMOpInfoBase + 1797, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTNSH |
| 8058 | { 2397, 2, 1, 4, 1250, 0, 0, ARMOpInfoBase + 1795, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTNSD |
| 8059 | { 2396, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTNNUQh |
| 8060 | { 2395, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTNNUQf |
| 8061 | { 2394, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTNNUDh |
| 8062 | { 2393, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTNNUDf |
| 8063 | { 2392, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTNNSQh |
| 8064 | { 2391, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTNNSQf |
| 8065 | { 2390, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTNNSDh |
| 8066 | { 2389, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTNNSDf |
| 8067 | { 2388, 2, 1, 4, 1247, 0, 0, ARMOpInfoBase + 1799, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTMUS |
| 8068 | { 2387, 2, 1, 4, 1205, 0, 0, ARMOpInfoBase + 1797, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTMUH |
| 8069 | { 2386, 2, 1, 4, 1250, 0, 0, ARMOpInfoBase + 1795, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTMUD |
| 8070 | { 2385, 2, 1, 4, 1247, 0, 0, ARMOpInfoBase + 1799, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTMSS |
| 8071 | { 2384, 2, 1, 4, 1205, 0, 0, ARMOpInfoBase + 1797, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTMSH |
| 8072 | { 2383, 2, 1, 4, 1250, 0, 0, ARMOpInfoBase + 1795, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTMSD |
| 8073 | { 2382, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTMNUQh |
| 8074 | { 2381, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTMNUQf |
| 8075 | { 2380, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTMNUDh |
| 8076 | { 2379, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTMNUDf |
| 8077 | { 2378, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTMNSQh |
| 8078 | { 2377, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTMNSQf |
| 8079 | { 2376, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTMNSDh |
| 8080 | { 2375, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTMNSDf |
| 8081 | { 2374, 4, 1, 4, 557, 1, 0, ARMOpInfoBase + 1806, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTDS |
| 8082 | { 2373, 5, 1, 4, 556, 1, 0, ARMOpInfoBase + 409, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTBSH |
| 8083 | { 2372, 4, 1, 4, 555, 1, 0, ARMOpInfoBase + 1687, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTBHS |
| 8084 | { 2371, 4, 1, 4, 554, 1, 0, ARMOpInfoBase + 1806, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTBHD |
| 8085 | { 2370, 5, 1, 4, 955, 1, 0, ARMOpInfoBase + 1801, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCVTBDH |
| 8086 | { 2369, 2, 1, 4, 1247, 0, 0, ARMOpInfoBase + 1799, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTAUS |
| 8087 | { 2368, 2, 1, 4, 1205, 0, 0, ARMOpInfoBase + 1797, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTAUH |
| 8088 | { 2367, 2, 1, 4, 1250, 0, 0, ARMOpInfoBase + 1795, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTAUD |
| 8089 | { 2366, 2, 1, 4, 1247, 0, 0, ARMOpInfoBase + 1799, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTASS |
| 8090 | { 2365, 2, 1, 4, 1205, 0, 0, ARMOpInfoBase + 1797, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTASH |
| 8091 | { 2364, 2, 1, 4, 1250, 0, 0, ARMOpInfoBase + 1795, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCVTASD |
| 8092 | { 2363, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTANUQh |
| 8093 | { 2362, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTANUQf |
| 8094 | { 2361, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTANUDh |
| 8095 | { 2360, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTANUDf |
| 8096 | { 2359, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTANSQh |
| 8097 | { 2358, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // VCVTANSQf |
| 8098 | { 2357, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTANSDh |
| 8099 | { 2356, 2, 1, 4, 553, 0, 0, ARMOpInfoBase + 1793, 0, 0, 0x11000ULL }, // VCVTANSDf |
| 8100 | { 2355, 4, 1, 4, 765, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCNTq |
| 8101 | { 2354, 4, 1, 4, 766, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCNTd |
| 8102 | { 2353, 3, 0, 4, 519, 1, 1, ARMOpInfoBase + 1790, 74, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28780ULL }, // VCMPZS |
| 8103 | { 2352, 3, 0, 4, 767, 1, 1, ARMOpInfoBase + 1787, 74, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCMPZH |
| 8104 | { 2351, 3, 0, 4, 518, 1, 1, ARMOpInfoBase + 1784, 74, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCMPZD |
| 8105 | { 2350, 4, 0, 4, 1254, 1, 1, ARMOpInfoBase + 1687, 74, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28780ULL }, // VCMPS |
| 8106 | { 2349, 4, 0, 4, 767, 1, 1, ARMOpInfoBase + 1683, 74, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCMPH |
| 8107 | { 2348, 3, 0, 4, 519, 1, 1, ARMOpInfoBase + 1790, 74, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28780ULL }, // VCMPEZS |
| 8108 | { 2347, 3, 0, 4, 767, 1, 1, ARMOpInfoBase + 1787, 74, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCMPEZH |
| 8109 | { 2346, 3, 0, 4, 518, 1, 1, ARMOpInfoBase + 1784, 74, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCMPEZD |
| 8110 | { 2345, 4, 0, 4, 519, 1, 1, ARMOpInfoBase + 1687, 74, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28780ULL }, // VCMPES |
| 8111 | { 2344, 4, 0, 4, 767, 1, 1, ARMOpInfoBase + 1683, 74, 0|(1ULL<<MCID::MayRaiseFPException), 0x8780ULL }, // VCMPEH |
| 8112 | { 2343, 4, 0, 4, 518, 1, 1, ARMOpInfoBase + 1679, 74, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCMPED |
| 8113 | { 2342, 4, 0, 4, 1255, 1, 1, ARMOpInfoBase + 1679, 74, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // VCMPD |
| 8114 | { 2341, 6, 1, 4, 991, 0, 0, ARMOpInfoBase + 1778, 0, 0, 0x11580ULL }, // VCMLAv8f16_indexed |
| 8115 | { 2340, 5, 1, 4, 991, 0, 0, ARMOpInfoBase + 1767, 0, 0, 0x11580ULL }, // VCMLAv8f16 |
| 8116 | { 2339, 6, 1, 4, 991, 0, 0, ARMOpInfoBase + 1772, 0, 0, 0x11580ULL }, // VCMLAv4f32_indexed |
| 8117 | { 2338, 5, 1, 4, 991, 0, 0, ARMOpInfoBase + 1767, 0, 0, 0x11580ULL }, // VCMLAv4f32 |
| 8118 | { 2337, 6, 1, 4, 990, 0, 0, ARMOpInfoBase + 1761, 0, 0, 0x11580ULL }, // VCMLAv4f16_indexed |
| 8119 | { 2336, 5, 1, 4, 990, 0, 0, ARMOpInfoBase + 1750, 0, 0, 0x11580ULL }, // VCMLAv4f16 |
| 8120 | { 2335, 6, 1, 4, 990, 0, 0, ARMOpInfoBase + 1755, 0, 0, 0x11580ULL }, // VCMLAv2f32_indexed |
| 8121 | { 2334, 5, 1, 4, 990, 0, 0, ARMOpInfoBase + 1750, 0, 0, 0x11580ULL }, // VCMLAv2f32 |
| 8122 | { 2333, 4, 1, 4, 766, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLZv8i8 |
| 8123 | { 2332, 4, 1, 4, 765, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLZv8i16 |
| 8124 | { 2331, 4, 1, 4, 765, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLZv4i32 |
| 8125 | { 2330, 4, 1, 4, 766, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLZv4i16 |
| 8126 | { 2329, 4, 1, 4, 766, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLZv2i32 |
| 8127 | { 2328, 4, 1, 4, 765, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLZv16i8 |
| 8128 | { 2327, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv8i8 |
| 8129 | { 2326, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv8i16 |
| 8130 | { 2325, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv8f16 |
| 8131 | { 2324, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv4i32 |
| 8132 | { 2323, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv4i16 |
| 8133 | { 2322, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv4f32 |
| 8134 | { 2321, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv4f16 |
| 8135 | { 2320, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv2i32 |
| 8136 | { 2319, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv2f32 |
| 8137 | { 2318, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLTzv16i8 |
| 8138 | { 2317, 4, 1, 4, 474, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLSv8i8 |
| 8139 | { 2316, 4, 1, 4, 473, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLSv8i16 |
| 8140 | { 2315, 4, 1, 4, 473, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLSv4i32 |
| 8141 | { 2314, 4, 1, 4, 474, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLSv4i16 |
| 8142 | { 2313, 4, 1, 4, 474, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLSv2i32 |
| 8143 | { 2312, 4, 1, 4, 473, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLSv16i8 |
| 8144 | { 2311, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv8i8 |
| 8145 | { 2310, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv8i16 |
| 8146 | { 2309, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv8f16 |
| 8147 | { 2308, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv4i32 |
| 8148 | { 2307, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv4i16 |
| 8149 | { 2306, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv4f32 |
| 8150 | { 2305, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv4f16 |
| 8151 | { 2304, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv2i32 |
| 8152 | { 2303, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv2f32 |
| 8153 | { 2302, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCLEzv16i8 |
| 8154 | { 2301, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv8i8 |
| 8155 | { 2300, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv8i16 |
| 8156 | { 2299, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv8f16 |
| 8157 | { 2298, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv4i32 |
| 8158 | { 2297, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv4i16 |
| 8159 | { 2296, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv4f32 |
| 8160 | { 2295, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv4f16 |
| 8161 | { 2294, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv2i32 |
| 8162 | { 2293, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv2f32 |
| 8163 | { 2292, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGTzv16i8 |
| 8164 | { 2291, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTuv8i8 |
| 8165 | { 2290, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTuv8i16 |
| 8166 | { 2289, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTuv4i32 |
| 8167 | { 2288, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTuv4i16 |
| 8168 | { 2287, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTuv2i32 |
| 8169 | { 2286, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTuv16i8 |
| 8170 | { 2285, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTsv8i8 |
| 8171 | { 2284, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTsv8i16 |
| 8172 | { 2283, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTsv4i32 |
| 8173 | { 2282, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTsv4i16 |
| 8174 | { 2281, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTsv2i32 |
| 8175 | { 2280, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTsv16i8 |
| 8176 | { 2279, 5, 1, 4, 484, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGThq |
| 8177 | { 2278, 5, 1, 4, 483, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGThd |
| 8178 | { 2277, 5, 1, 4, 484, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTfq |
| 8179 | { 2276, 5, 1, 4, 483, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGTfd |
| 8180 | { 2275, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv8i8 |
| 8181 | { 2274, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv8i16 |
| 8182 | { 2273, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv8f16 |
| 8183 | { 2272, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv4i32 |
| 8184 | { 2271, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv4i16 |
| 8185 | { 2270, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv4f32 |
| 8186 | { 2269, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv4f16 |
| 8187 | { 2268, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv2i32 |
| 8188 | { 2267, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv2f32 |
| 8189 | { 2266, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCGEzv16i8 |
| 8190 | { 2265, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEuv8i8 |
| 8191 | { 2264, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEuv8i16 |
| 8192 | { 2263, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEuv4i32 |
| 8193 | { 2262, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEuv4i16 |
| 8194 | { 2261, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEuv2i32 |
| 8195 | { 2260, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEuv16i8 |
| 8196 | { 2259, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEsv8i8 |
| 8197 | { 2258, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEsv8i16 |
| 8198 | { 2257, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEsv4i32 |
| 8199 | { 2256, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEsv4i16 |
| 8200 | { 2255, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEsv2i32 |
| 8201 | { 2254, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEsv16i8 |
| 8202 | { 2253, 5, 1, 4, 484, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEhq |
| 8203 | { 2252, 5, 1, 4, 483, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEhd |
| 8204 | { 2251, 5, 1, 4, 484, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEfq |
| 8205 | { 2250, 5, 1, 4, 483, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VCGEfd |
| 8206 | { 2249, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv8i8 |
| 8207 | { 2248, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv8i16 |
| 8208 | { 2247, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv8f16 |
| 8209 | { 2246, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv4i32 |
| 8210 | { 2245, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv4i16 |
| 8211 | { 2244, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv4f32 |
| 8212 | { 2243, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv4f16 |
| 8213 | { 2242, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv2i32 |
| 8214 | { 2241, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv2f32 |
| 8215 | { 2240, 4, 1, 4, 487, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VCEQzv16i8 |
| 8216 | { 2239, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQv8i8 |
| 8217 | { 2238, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQv8i16 |
| 8218 | { 2237, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQv4i32 |
| 8219 | { 2236, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQv4i16 |
| 8220 | { 2235, 5, 1, 4, 764, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQv2i32 |
| 8221 | { 2234, 5, 1, 4, 763, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQv16i8 |
| 8222 | { 2233, 5, 1, 4, 484, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQhq |
| 8223 | { 2232, 5, 1, 4, 483, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQhd |
| 8224 | { 2231, 5, 1, 4, 484, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQfq |
| 8225 | { 2230, 5, 1, 4, 483, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VCEQfd |
| 8226 | { 2229, 4, 1, 4, 991, 0, 0, ARMOpInfoBase + 1746, 0, 0, 0x11580ULL }, // VCADDv8f16 |
| 8227 | { 2228, 4, 1, 4, 991, 0, 0, ARMOpInfoBase + 1746, 0, 0, 0x11580ULL }, // VCADDv4f32 |
| 8228 | { 2227, 4, 1, 4, 990, 0, 0, ARMOpInfoBase + 1742, 0, 0, 0x11580ULL }, // VCADDv4f16 |
| 8229 | { 2226, 4, 1, 4, 990, 0, 0, ARMOpInfoBase + 1742, 0, 0, 0x11580ULL }, // VCADDv2f32 |
| 8230 | { 2225, 6, 1, 4, 762, 0, 0, ARMOpInfoBase + 1736, 0, 0|(1ULL<<MCID::Predicable), 0x10000ULL }, // VBSPq |
| 8231 | { 2224, 6, 1, 4, 761, 0, 0, ARMOpInfoBase + 1730, 0, 0|(1ULL<<MCID::Predicable), 0x10000ULL }, // VBSPd |
| 8232 | { 2223, 6, 1, 4, 762, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VBSLq |
| 8233 | { 2222, 6, 1, 4, 761, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VBSLd |
| 8234 | { 2221, 6, 1, 4, 762, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VBITq |
| 8235 | { 2220, 6, 1, 4, 761, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VBITd |
| 8236 | { 2219, 6, 1, 4, 762, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VBIFq |
| 8237 | { 2218, 6, 1, 4, 761, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VBIFd |
| 8238 | { 2217, 5, 1, 4, 758, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VBICq |
| 8239 | { 2216, 5, 1, 4, 760, 0, 0, ARMOpInfoBase + 1725, 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // VBICiv8i16 |
| 8240 | { 2215, 5, 1, 4, 760, 0, 0, ARMOpInfoBase + 1725, 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // VBICiv4i32 |
| 8241 | { 2214, 5, 1, 4, 759, 0, 0, ARMOpInfoBase + 1720, 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // VBICiv4i16 |
| 8242 | { 2213, 5, 1, 4, 759, 0, 0, ARMOpInfoBase + 1720, 0, 0|(1ULL<<MCID::Predicable), 0x10f80ULL }, // VBICiv2i32 |
| 8243 | { 2212, 5, 1, 4, 757, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VBICd |
| 8244 | { 2211, 5, 1, 4, 116, 0, 0, ARMOpInfoBase + 1715, 0, 0, 0x11580ULL }, // VBF16MALTQI |
| 8245 | { 2210, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11580ULL }, // VBF16MALTQ |
| 8246 | { 2209, 5, 1, 4, 116, 0, 0, ARMOpInfoBase + 1715, 0, 0, 0x11580ULL }, // VBF16MALBQI |
| 8247 | { 2208, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11580ULL }, // VBF16MALBQ |
| 8248 | { 2207, 5, 1, 4, 758, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VANDq |
| 8249 | { 2206, 5, 1, 4, 757, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VANDd |
| 8250 | { 2205, 5, 1, 4, 753, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDv8i8 |
| 8251 | { 2204, 5, 1, 4, 755, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDv8i16 |
| 8252 | { 2203, 5, 1, 4, 755, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDv4i32 |
| 8253 | { 2202, 5, 1, 4, 753, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDv4i16 |
| 8254 | { 2201, 5, 1, 4, 755, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDv2i64 |
| 8255 | { 2200, 5, 1, 4, 753, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDv2i32 |
| 8256 | { 2199, 5, 1, 4, 753, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDv1i64 |
| 8257 | { 2198, 5, 1, 4, 755, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDv16i8 |
| 8258 | { 2197, 5, 1, 4, 744, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDhq |
| 8259 | { 2196, 5, 1, 4, 742, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDhd |
| 8260 | { 2195, 5, 1, 4, 743, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDfq |
| 8261 | { 2194, 5, 1, 4, 741, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDfd |
| 8262 | { 2193, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VADDWuv8i16 |
| 8263 | { 2192, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VADDWuv4i32 |
| 8264 | { 2191, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VADDWuv2i64 |
| 8265 | { 2190, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VADDWsv8i16 |
| 8266 | { 2189, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VADDWsv4i32 |
| 8267 | { 2188, 5, 1, 4, 461, 0, 0, ARMOpInfoBase + 1710, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VADDWsv2i64 |
| 8268 | { 2187, 5, 1, 4, 520, 1, 0, ARMOpInfoBase + 1705, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x28800ULL }, // VADDS |
| 8269 | { 2186, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDLuv8i16 |
| 8270 | { 2185, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDLuv4i32 |
| 8271 | { 2184, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDLuv2i64 |
| 8272 | { 2183, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDLsv8i16 |
| 8273 | { 2182, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDLsv4i32 |
| 8274 | { 2181, 5, 1, 4, 756, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDLsv2i64 |
| 8275 | { 2180, 5, 1, 4, 500, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDHNv8i8 |
| 8276 | { 2179, 5, 1, 4, 500, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDHNv4i16 |
| 8277 | { 2178, 5, 1, 4, 500, 0, 0, ARMOpInfoBase + 1700, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VADDHNv2i32 |
| 8278 | { 2177, 5, 1, 4, 740, 1, 0, ARMOpInfoBase + 1695, 69, 0|(1ULL<<MCID::MayRaiseFPException), 0x8800ULL }, // VADDH |
| 8279 | { 2176, 5, 1, 4, 526, 1, 0, ARMOpInfoBase + 1669, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8800ULL }, // VADDD |
| 8280 | { 2175, 5, 1, 4, 739, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VACGThq |
| 8281 | { 2174, 5, 1, 4, 738, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VACGThd |
| 8282 | { 2173, 5, 1, 4, 739, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VACGTfq |
| 8283 | { 2172, 5, 1, 4, 738, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VACGTfd |
| 8284 | { 2171, 5, 1, 4, 739, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VACGEhq |
| 8285 | { 2170, 5, 1, 4, 738, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VACGEhd |
| 8286 | { 2169, 5, 1, 4, 739, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VACGEfq |
| 8287 | { 2168, 5, 1, 4, 738, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VACGEfd |
| 8288 | { 2167, 4, 1, 4, 493, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABSv8i8 |
| 8289 | { 2166, 4, 1, 4, 492, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABSv8i16 |
| 8290 | { 2165, 4, 1, 4, 492, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABSv4i32 |
| 8291 | { 2164, 4, 1, 4, 493, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABSv4i16 |
| 8292 | { 2163, 4, 1, 4, 493, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABSv2i32 |
| 8293 | { 2162, 4, 1, 4, 492, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABSv16i8 |
| 8294 | { 2161, 4, 1, 4, 737, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABShq |
| 8295 | { 2160, 4, 1, 4, 736, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABShd |
| 8296 | { 2159, 4, 1, 4, 491, 0, 0, ARMOpInfoBase + 1691, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABSfq |
| 8297 | { 2158, 4, 1, 4, 490, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // VABSfd |
| 8298 | { 2157, 4, 1, 4, 735, 0, 0, ARMOpInfoBase + 1687, 0, 0|(1ULL<<MCID::Predicable), 0x28780ULL }, // VABSS |
| 8299 | { 2156, 4, 1, 4, 734, 0, 0, ARMOpInfoBase + 1683, 0, 0, 0x8780ULL }, // VABSH |
| 8300 | { 2155, 4, 1, 4, 733, 0, 0, ARMOpInfoBase + 1679, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL }, // VABSD |
| 8301 | { 2154, 5, 1, 4, 750, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDuv8i8 |
| 8302 | { 2153, 5, 1, 4, 751, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDuv8i16 |
| 8303 | { 2152, 5, 1, 4, 751, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDuv4i32 |
| 8304 | { 2151, 5, 1, 4, 750, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDuv4i16 |
| 8305 | { 2150, 5, 1, 4, 750, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDuv2i32 |
| 8306 | { 2149, 5, 1, 4, 751, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDuv16i8 |
| 8307 | { 2148, 5, 1, 4, 750, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDsv8i8 |
| 8308 | { 2147, 5, 1, 4, 751, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDsv8i16 |
| 8309 | { 2146, 5, 1, 4, 751, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDsv4i32 |
| 8310 | { 2145, 5, 1, 4, 750, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDsv4i16 |
| 8311 | { 2144, 5, 1, 4, 750, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDsv2i32 |
| 8312 | { 2143, 5, 1, 4, 751, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDsv16i8 |
| 8313 | { 2142, 5, 1, 4, 732, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDhq |
| 8314 | { 2141, 5, 1, 4, 731, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDhd |
| 8315 | { 2140, 5, 1, 4, 732, 0, 0, ARMOpInfoBase + 1674, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDfq |
| 8316 | { 2139, 5, 1, 4, 731, 0, 0, ARMOpInfoBase + 1669, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDfd |
| 8317 | { 2138, 5, 1, 4, 752, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDLuv8i16 |
| 8318 | { 2137, 5, 1, 4, 752, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDLuv4i32 |
| 8319 | { 2136, 5, 1, 4, 523, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDLuv2i64 |
| 8320 | { 2135, 5, 1, 4, 752, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDLsv8i16 |
| 8321 | { 2134, 5, 1, 4, 752, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDLsv4i32 |
| 8322 | { 2133, 5, 1, 4, 523, 0, 0, ARMOpInfoBase + 1664, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL }, // VABDLsv2i64 |
| 8323 | { 2132, 6, 1, 4, 749, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAuv8i8 |
| 8324 | { 2131, 6, 1, 4, 480, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAuv8i16 |
| 8325 | { 2130, 6, 1, 4, 480, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAuv4i32 |
| 8326 | { 2129, 6, 1, 4, 749, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAuv4i16 |
| 8327 | { 2128, 6, 1, 4, 749, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAuv2i32 |
| 8328 | { 2127, 6, 1, 4, 480, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAuv16i8 |
| 8329 | { 2126, 6, 1, 4, 749, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAsv8i8 |
| 8330 | { 2125, 6, 1, 4, 480, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAsv8i16 |
| 8331 | { 2124, 6, 1, 4, 480, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAsv4i32 |
| 8332 | { 2123, 6, 1, 4, 749, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAsv4i16 |
| 8333 | { 2122, 6, 1, 4, 749, 0, 0, ARMOpInfoBase + 1658, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAsv2i32 |
| 8334 | { 2121, 6, 1, 4, 480, 0, 0, ARMOpInfoBase + 1652, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABAsv16i8 |
| 8335 | { 2120, 6, 1, 4, 479, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABALuv8i16 |
| 8336 | { 2119, 6, 1, 4, 479, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABALuv4i32 |
| 8337 | { 2118, 6, 1, 4, 479, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABALuv2i64 |
| 8338 | { 2117, 6, 1, 4, 479, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABALsv8i16 |
| 8339 | { 2116, 6, 1, 4, 479, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABALsv4i32 |
| 8340 | { 2115, 6, 1, 4, 479, 0, 0, ARMOpInfoBase + 1646, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL }, // VABALsv2i64 |
| 8341 | { 2114, 5, 1, 4, 894, 0, 0, ARMOpInfoBase + 1633, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // UXTH |
| 8342 | { 2113, 5, 1, 4, 351, 0, 0, ARMOpInfoBase + 1633, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // UXTB16 |
| 8343 | { 2112, 5, 1, 4, 894, 0, 0, ARMOpInfoBase + 1633, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // UXTB |
| 8344 | { 2111, 6, 1, 4, 897, 0, 0, ARMOpInfoBase + 1627, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // UXTAH |
| 8345 | { 2110, 6, 1, 4, 366, 0, 0, ARMOpInfoBase + 1627, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // UXTAB16 |
| 8346 | { 2109, 6, 1, 4, 897, 0, 0, ARMOpInfoBase + 1627, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // UXTAB |
| 8347 | { 2108, 5, 1, 4, 882, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // USUB8 |
| 8348 | { 2107, 5, 1, 4, 882, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // USUB16 |
| 8349 | { 2106, 5, 1, 4, 363, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // USAX |
| 8350 | { 2105, 5, 1, 4, 890, 0, 0, ARMOpInfoBase + 1566, 0, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // USAT16 |
| 8351 | { 2104, 6, 1, 4, 890, 0, 0, ARMOpInfoBase + 1560, 0, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // USAT |
| 8352 | { 2103, 6, 1, 4, 370, 0, 0, ARMOpInfoBase + 995, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // USADA8 |
| 8353 | { 2102, 5, 1, 4, 369, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // USAD8 |
| 8354 | { 2101, 5, 1, 4, 886, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UQSUB8 |
| 8355 | { 2100, 5, 1, 4, 886, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UQSUB16 |
| 8356 | { 2099, 5, 1, 4, 888, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UQSAX |
| 8357 | { 2098, 5, 1, 4, 888, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UQASX |
| 8358 | { 2097, 5, 1, 4, 886, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UQADD8 |
| 8359 | { 2096, 5, 1, 4, 886, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UQADD16 |
| 8360 | { 2095, 7, 2, 4, 338, 0, 0, ARMOpInfoBase + 1553, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // UMULL |
| 8361 | { 2094, 9, 2, 4, 339, 0, 0, ARMOpInfoBase + 1536, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // UMLAL |
| 8362 | { 2093, 8, 2, 4, 339, 0, 0, ARMOpInfoBase + 1638, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // UMAAL |
| 8363 | { 2092, 5, 1, 4, 884, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UHSUB8 |
| 8364 | { 2091, 5, 1, 4, 884, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UHSUB16 |
| 8365 | { 2090, 5, 1, 4, 365, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UHSAX |
| 8366 | { 2089, 5, 1, 4, 365, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UHASX |
| 8367 | { 2088, 5, 1, 4, 884, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UHADD8 |
| 8368 | { 2087, 5, 1, 4, 884, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // UHADD16 |
| 8369 | { 2086, 5, 1, 4, 384, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // UDIV |
| 8370 | { 2085, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // UDF |
| 8371 | { 2084, 6, 1, 4, 892, 0, 0, ARMOpInfoBase + 1524, 0, 0|(1ULL<<MCID::Predicable), 0x201ULL }, // UBFX |
| 8372 | { 2083, 5, 1, 4, 363, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // UASX |
| 8373 | { 2082, 5, 1, 4, 882, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // UADD8 |
| 8374 | { 2081, 5, 1, 4, 882, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // UADD16 |
| 8375 | { 2080, 6, 0, 4, 724, 0, 1, ARMOpInfoBase + 845, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // TSTrsr |
| 8376 | { 2079, 5, 0, 4, 723, 0, 1, ARMOpInfoBase + 840, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // TSTrsi |
| 8377 | { 2078, 4, 0, 4, 722, 0, 1, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL }, // TSTrr |
| 8378 | { 2077, 4, 0, 4, 721, 0, 1, ARMOpInfoBase + 244, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // TSTri |
| 8379 | { 2076, 1, 0, 4, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // TSB |
| 8380 | { 2075, 0, 0, 4, 841, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // TRAP |
| 8381 | { 2074, 6, 0, 4, 95, 0, 1, ARMOpInfoBase + 845, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // TEQrsr |
| 8382 | { 2073, 5, 0, 4, 94, 0, 1, ARMOpInfoBase + 840, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // TEQrsi |
| 8383 | { 2072, 4, 0, 4, 93, 0, 1, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL }, // TEQrr |
| 8384 | { 2071, 4, 0, 4, 92, 0, 1, ARMOpInfoBase + 244, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // TEQri |
| 8385 | { 2070, 5, 1, 4, 894, 0, 0, ARMOpInfoBase + 1633, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // SXTH |
| 8386 | { 2069, 5, 1, 4, 351, 0, 0, ARMOpInfoBase + 1633, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // SXTB16 |
| 8387 | { 2068, 5, 1, 4, 894, 0, 0, ARMOpInfoBase + 1633, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // SXTB |
| 8388 | { 2067, 6, 1, 4, 897, 0, 0, ARMOpInfoBase + 1627, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // SXTAH |
| 8389 | { 2066, 6, 1, 4, 366, 0, 0, ARMOpInfoBase + 1627, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // SXTAB16 |
| 8390 | { 2065, 6, 1, 4, 897, 0, 0, ARMOpInfoBase + 1627, 0, 0|(1ULL<<MCID::Predicable), 0x700ULL }, // SXTAB |
| 8391 | { 2064, 5, 1, 4, 841, 0, 0, ARMOpInfoBase + 1622, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // SWPB |
| 8392 | { 2063, 5, 1, 4, 841, 0, 0, ARMOpInfoBase + 1622, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // SWP |
| 8393 | { 2062, 3, 0, 4, 842, 1, 0, ARMOpInfoBase + 854, 54, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SVC |
| 8394 | { 2061, 8, 1, 4, 45, 0, 0, ARMOpInfoBase + 613, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // SUBrsr |
| 8395 | { 2060, 7, 1, 4, 3, 0, 0, ARMOpInfoBase + 598, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // SUBrsi |
| 8396 | { 2059, 6, 1, 4, 2, 0, 0, ARMOpInfoBase + 592, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // SUBrr |
| 8397 | { 2058, 6, 1, 4, 1, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // SUBri |
| 8398 | { 2057, 6, 0, 4, 427, 0, 0, ARMOpInfoBase + 956, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL }, // STRrs |
| 8399 | { 2056, 5, 0, 4, 425, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x392ULL }, // STRi12 |
| 8400 | { 2055, 7, 1, 4, 945, 0, 0, ARMOpInfoBase + 1588, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // STR_PRE_REG |
| 8401 | { 2054, 6, 1, 4, 937, 0, 0, ARMOpInfoBase + 1595, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // STR_PRE_IMM |
| 8402 | { 2053, 7, 1, 4, 438, 0, 0, ARMOpInfoBase + 1588, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // STR_POST_REG |
| 8403 | { 2052, 7, 1, 4, 439, 0, 0, ARMOpInfoBase + 1588, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // STR_POST_IMM |
| 8404 | { 2051, 7, 1, 4, 438, 0, 0, ARMOpInfoBase + 1581, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // STRT_POST_REG |
| 8405 | { 2050, 7, 1, 4, 948, 0, 0, ARMOpInfoBase + 1581, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // STRT_POST_IMM |
| 8406 | { 2049, 7, 1, 4, 941, 0, 0, ARMOpInfoBase + 1615, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4a3ULL }, // STRH_PRE |
| 8407 | { 2048, 7, 1, 4, 436, 0, 0, ARMOpInfoBase + 1615, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4c3ULL }, // STRH_POST |
| 8408 | { 2047, 7, 1, 4, 436, 0, 0, ARMOpInfoBase + 1581, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4c3ULL }, // STRHTr |
| 8409 | { 2046, 6, 1, 4, 436, 0, 0, ARMOpInfoBase + 1609, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4c3ULL }, // STRHTi |
| 8410 | { 2045, 6, 0, 4, 426, 0, 0, ARMOpInfoBase + 936, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x483ULL }, // STRH |
| 8411 | { 2044, 5, 1, 4, 429, 0, 0, ARMOpInfoBase + 1571, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // STREXH |
| 8412 | { 2043, 5, 1, 4, 429, 0, 0, ARMOpInfoBase + 1576, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL }, // STREXD |
| 8413 | { 2042, 5, 1, 4, 429, 0, 0, ARMOpInfoBase + 1571, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // STREXB |
| 8414 | { 2041, 5, 1, 4, 429, 0, 0, ARMOpInfoBase + 1571, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // STREX |
| 8415 | { 2040, 8, 1, 4, 947, 0, 0, ARMOpInfoBase + 1601, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4a3ULL }, // STRD_PRE |
| 8416 | { 2039, 8, 1, 4, 449, 0, 0, ARMOpInfoBase + 1601, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4c3ULL }, // STRD_POST |
| 8417 | { 2038, 7, 0, 4, 446, 0, 0, ARMOpInfoBase + 921, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x483ULL }, // STRD |
| 8418 | { 2037, 6, 0, 4, 428, 0, 0, ARMOpInfoBase + 915, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL }, // STRBrs |
| 8419 | { 2036, 5, 0, 4, 935, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x392ULL }, // STRBi12 |
| 8420 | { 2035, 7, 1, 4, 946, 0, 0, ARMOpInfoBase + 1588, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // STRB_PRE_REG |
| 8421 | { 2034, 6, 1, 4, 938, 0, 0, ARMOpInfoBase + 1595, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL }, // STRB_PRE_IMM |
| 8422 | { 2033, 7, 1, 4, 952, 0, 0, ARMOpInfoBase + 1588, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // STRB_POST_REG |
| 8423 | { 2032, 7, 1, 4, 437, 0, 0, ARMOpInfoBase + 1588, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // STRB_POST_IMM |
| 8424 | { 2031, 7, 1, 4, 952, 0, 0, ARMOpInfoBase + 1581, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // STRBT_POST_REG |
| 8425 | { 2030, 7, 1, 4, 949, 0, 0, ARMOpInfoBase + 1581, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL }, // STRBT_POST_IMM |
| 8426 | { 2029, 5, 1, 4, 451, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // STMIB_UPD |
| 8427 | { 2028, 4, 0, 4, 450, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // STMIB |
| 8428 | { 2027, 5, 1, 4, 451, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // STMIA_UPD |
| 8429 | { 2026, 4, 0, 4, 450, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // STMIA |
| 8430 | { 2025, 5, 1, 4, 451, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // STMDB_UPD |
| 8431 | { 2024, 4, 0, 4, 450, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // STMDB |
| 8432 | { 2023, 5, 1, 4, 451, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL }, // STMDA_UPD |
| 8433 | { 2022, 4, 0, 4, 450, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL }, // STMDA |
| 8434 | { 2021, 4, 0, 4, 729, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL }, // STLH |
| 8435 | { 2020, 5, 1, 4, 729, 0, 0, ARMOpInfoBase + 1571, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // STLEXH |
| 8436 | { 2019, 5, 1, 4, 729, 0, 0, ARMOpInfoBase + 1576, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL }, // STLEXD |
| 8437 | { 2018, 5, 1, 4, 729, 0, 0, ARMOpInfoBase + 1571, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // STLEXB |
| 8438 | { 2017, 5, 1, 4, 729, 0, 0, ARMOpInfoBase + 1571, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // STLEX |
| 8439 | { 2016, 4, 0, 4, 729, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL }, // STLB |
| 8440 | { 2015, 4, 0, 4, 729, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL }, // STL |
| 8441 | { 2014, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // STC_PRE |
| 8442 | { 2013, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // STC_POST |
| 8443 | { 2012, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // STC_OPTION |
| 8444 | { 2011, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // STC_OFFSET |
| 8445 | { 2010, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // STCL_PRE |
| 8446 | { 2009, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // STCL_POST |
| 8447 | { 2008, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // STCL_OPTION |
| 8448 | { 2007, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // STCL_OFFSET |
| 8449 | { 2006, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // STC2_PRE |
| 8450 | { 2005, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // STC2_POST |
| 8451 | { 2004, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 881, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // STC2_OPTION |
| 8452 | { 2003, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // STC2_OFFSET |
| 8453 | { 2002, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // STC2L_PRE |
| 8454 | { 2001, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // STC2L_POST |
| 8455 | { 2000, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 881, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // STC2L_OPTION |
| 8456 | { 1999, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // STC2L_OFFSET |
| 8457 | { 1998, 5, 1, 4, 882, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // SSUB8 |
| 8458 | { 1997, 5, 1, 4, 882, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // SSUB16 |
| 8459 | { 1996, 5, 1, 4, 363, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // SSAX |
| 8460 | { 1995, 5, 1, 4, 890, 0, 0, ARMOpInfoBase + 1566, 0, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // SSAT16 |
| 8461 | { 1994, 6, 1, 4, 890, 0, 0, ARMOpInfoBase + 1560, 0, 0|(1ULL<<MCID::Predicable), 0x680ULL }, // SSAT |
| 8462 | { 1993, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SRSIB_UPD |
| 8463 | { 1992, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SRSIB |
| 8464 | { 1991, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SRSIA_UPD |
| 8465 | { 1990, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SRSIA |
| 8466 | { 1989, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SRSDB_UPD |
| 8467 | { 1988, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SRSDB |
| 8468 | { 1987, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SRSDA_UPD |
| 8469 | { 1986, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SRSDA |
| 8470 | { 1985, 5, 1, 4, 371, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMUSDX |
| 8471 | { 1984, 5, 1, 4, 371, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMUSD |
| 8472 | { 1983, 5, 1, 4, 344, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMULWT |
| 8473 | { 1982, 5, 1, 4, 344, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMULWB |
| 8474 | { 1981, 5, 1, 4, 344, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMULTT |
| 8475 | { 1980, 5, 1, 4, 344, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMULTB |
| 8476 | { 1979, 7, 2, 4, 381, 0, 0, ARMOpInfoBase + 1553, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // SMULL |
| 8477 | { 1978, 5, 1, 4, 344, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMULBT |
| 8478 | { 1977, 5, 1, 4, 344, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMULBB |
| 8479 | { 1976, 5, 1, 4, 343, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMUADX |
| 8480 | { 1975, 5, 1, 4, 343, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMUAD |
| 8481 | { 1974, 5, 1, 4, 335, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMMULR |
| 8482 | { 1973, 5, 1, 4, 335, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMMUL |
| 8483 | { 1972, 6, 1, 4, 336, 0, 0, ARMOpInfoBase + 995, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMMLSR |
| 8484 | { 1971, 6, 1, 4, 336, 0, 0, ARMOpInfoBase + 995, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMMLS |
| 8485 | { 1970, 6, 1, 4, 336, 0, 0, ARMOpInfoBase + 995, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMMLAR |
| 8486 | { 1969, 6, 1, 4, 336, 0, 0, ARMOpInfoBase + 995, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMMLA |
| 8487 | { 1968, 8, 2, 4, 342, 0, 0, ARMOpInfoBase + 1545, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLSLDX |
| 8488 | { 1967, 8, 2, 4, 341, 0, 0, ARMOpInfoBase + 1545, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLSLD |
| 8489 | { 1966, 6, 1, 4, 377, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLSDX |
| 8490 | { 1965, 6, 1, 4, 377, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLSD |
| 8491 | { 1964, 6, 1, 4, 345, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLAWT |
| 8492 | { 1963, 6, 1, 4, 345, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLAWB |
| 8493 | { 1962, 6, 1, 4, 345, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLATT |
| 8494 | { 1961, 6, 1, 4, 345, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLATB |
| 8495 | { 1960, 8, 2, 4, 339, 0, 0, ARMOpInfoBase + 1545, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLALTT |
| 8496 | { 1959, 8, 2, 4, 339, 0, 0, ARMOpInfoBase + 1545, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLALTB |
| 8497 | { 1958, 8, 2, 4, 342, 0, 0, ARMOpInfoBase + 1545, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLALDX |
| 8498 | { 1957, 8, 2, 4, 341, 0, 0, ARMOpInfoBase + 1545, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLALD |
| 8499 | { 1956, 8, 2, 4, 339, 0, 0, ARMOpInfoBase + 1545, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLALBT |
| 8500 | { 1955, 8, 2, 4, 339, 0, 0, ARMOpInfoBase + 1545, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLALBB |
| 8501 | { 1954, 9, 2, 4, 339, 0, 0, ARMOpInfoBase + 1536, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // SMLAL |
| 8502 | { 1953, 6, 1, 4, 340, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLADX |
| 8503 | { 1952, 6, 1, 4, 340, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLAD |
| 8504 | { 1951, 6, 1, 4, 345, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLABT |
| 8505 | { 1950, 6, 1, 4, 345, 0, 0, ARMOpInfoBase + 1530, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // SMLABB |
| 8506 | { 1949, 3, 0, 4, 841, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // SMC |
| 8507 | { 1948, 5, 1, 4, 884, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // SHSUB8 |
| 8508 | { 1947, 5, 1, 4, 884, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // SHSUB16 |
| 8509 | { 1946, 5, 1, 4, 365, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // SHSAX |
| 8510 | { 1945, 5, 1, 4, 365, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // SHASX |
| 8511 | { 1944, 5, 1, 4, 884, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // SHADD8 |
| 8512 | { 1943, 5, 1, 4, 884, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // SHADD16 |
| 8513 | { 1942, 4, 1, 4, 1013, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // SHA256SU1 |
| 8514 | { 1941, 3, 1, 4, 1012, 0, 0, ARMOpInfoBase + 621, 0, 0, 0x11000ULL }, // SHA256SU0 |
| 8515 | { 1940, 4, 1, 4, 1013, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // SHA256H2 |
| 8516 | { 1939, 4, 1, 4, 1013, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // SHA256H |
| 8517 | { 1938, 3, 1, 4, 1010, 0, 0, ARMOpInfoBase + 621, 0, 0, 0x11000ULL }, // SHA1SU1 |
| 8518 | { 1937, 4, 1, 4, 1009, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // SHA1SU0 |
| 8519 | { 1936, 4, 1, 4, 1011, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // SHA1P |
| 8520 | { 1935, 4, 1, 4, 1011, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // SHA1M |
| 8521 | { 1934, 2, 1, 4, 1010, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // SHA1H |
| 8522 | { 1933, 4, 1, 4, 1011, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // SHA1C |
| 8523 | { 1932, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // SETPAN |
| 8524 | { 1931, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // SETEND |
| 8525 | { 1930, 5, 1, 4, 333, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x200ULL }, // SEL |
| 8526 | { 1929, 5, 1, 4, 384, 0, 0, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // SDIV |
| 8527 | { 1928, 6, 1, 4, 892, 0, 0, ARMOpInfoBase + 1524, 0, 0|(1ULL<<MCID::Predicable), 0x201ULL }, // SBFX |
| 8528 | { 1927, 8, 1, 4, 706, 1, 1, ARMOpInfoBase + 605, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL }, // SBCrsr |
| 8529 | { 1926, 7, 1, 4, 700, 1, 1, ARMOpInfoBase + 598, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL }, // SBCrsi |
| 8530 | { 1925, 6, 1, 4, 697, 1, 1, ARMOpInfoBase + 592, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // SBCrr |
| 8531 | { 1924, 6, 1, 4, 690, 1, 1, ARMOpInfoBase + 178, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // SBCri |
| 8532 | { 1923, 0, 0, 4, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // SB |
| 8533 | { 1922, 5, 1, 4, 363, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // SASX |
| 8534 | { 1921, 5, 1, 4, 882, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // SADD8 |
| 8535 | { 1920, 5, 1, 4, 882, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // SADD16 |
| 8536 | { 1919, 8, 1, 4, 706, 1, 1, ARMOpInfoBase + 613, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL }, // RSCrsr |
| 8537 | { 1918, 7, 1, 4, 700, 1, 1, ARMOpInfoBase + 598, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL }, // RSCrsi |
| 8538 | { 1917, 6, 1, 4, 697, 1, 1, ARMOpInfoBase + 592, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL }, // RSCrr |
| 8539 | { 1916, 6, 1, 4, 690, 1, 1, ARMOpInfoBase + 178, 66, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // RSCri |
| 8540 | { 1915, 8, 1, 4, 706, 0, 0, ARMOpInfoBase + 613, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // RSBrsr |
| 8541 | { 1914, 7, 1, 4, 700, 0, 0, ARMOpInfoBase + 598, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // RSBrsi |
| 8542 | { 1913, 6, 1, 4, 697, 0, 0, ARMOpInfoBase + 592, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // RSBrr |
| 8543 | { 1912, 6, 1, 4, 690, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // RSBri |
| 8544 | { 1911, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // RFEIB_UPD |
| 8545 | { 1910, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // RFEIB |
| 8546 | { 1909, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // RFEIA_UPD |
| 8547 | { 1908, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // RFEIA |
| 8548 | { 1907, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // RFEDB_UPD |
| 8549 | { 1906, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // RFEDB |
| 8550 | { 1905, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // RFEDA_UPD |
| 8551 | { 1904, 1, 0, 4, 727, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // RFEDA |
| 8552 | { 1903, 4, 1, 4, 719, 0, 0, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // REVSH |
| 8553 | { 1902, 4, 1, 4, 719, 0, 0, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // REV16 |
| 8554 | { 1901, 4, 1, 4, 719, 0, 0, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // REV |
| 8555 | { 1900, 4, 1, 4, 719, 0, 0, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // RBIT |
| 8556 | { 1899, 5, 1, 4, 886, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // QSUB8 |
| 8557 | { 1898, 5, 1, 4, 886, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // QSUB16 |
| 8558 | { 1897, 5, 1, 4, 891, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // QSUB |
| 8559 | { 1896, 5, 1, 4, 888, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // QSAX |
| 8560 | { 1895, 5, 1, 4, 360, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // QDSUB |
| 8561 | { 1894, 5, 1, 4, 360, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // QDADD |
| 8562 | { 1893, 5, 1, 4, 888, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable), 0x200ULL }, // QASX |
| 8563 | { 1892, 5, 1, 4, 886, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // QADD8 |
| 8564 | { 1891, 5, 1, 4, 886, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // QADD16 |
| 8565 | { 1890, 5, 1, 4, 891, 0, 0, ARMOpInfoBase + 1519, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL }, // QADD |
| 8566 | { 1889, 3, 0, 4, 932, 0, 0, ARMOpInfoBase + 1516, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL }, // PLIrs |
| 8567 | { 1888, 2, 0, 4, 932, 0, 0, ARMOpInfoBase + 1514, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd12ULL }, // PLIi12 |
| 8568 | { 1887, 3, 0, 4, 933, 0, 0, ARMOpInfoBase + 1516, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL }, // PLDrs |
| 8569 | { 1886, 2, 0, 4, 932, 0, 0, ARMOpInfoBase + 1514, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd12ULL }, // PLDi12 |
| 8570 | { 1885, 3, 0, 4, 933, 0, 0, ARMOpInfoBase + 1516, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL }, // PLDWrs |
| 8571 | { 1884, 2, 0, 4, 932, 0, 0, ARMOpInfoBase + 1514, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd12ULL }, // PLDWi12 |
| 8572 | { 1883, 6, 1, 4, 73, 0, 0, ARMOpInfoBase + 1508, 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // PKHTB |
| 8573 | { 1882, 6, 1, 4, 39, 0, 0, ARMOpInfoBase + 1508, 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // PKHBT |
| 8574 | { 1881, 8, 1, 4, 324, 0, 0, ARMOpInfoBase + 613, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // ORRrsr |
| 8575 | { 1880, 7, 1, 4, 323, 0, 0, ARMOpInfoBase + 598, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // ORRrsi |
| 8576 | { 1879, 6, 1, 4, 322, 0, 0, ARMOpInfoBase + 592, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // ORRrr |
| 8577 | { 1878, 6, 1, 4, 321, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // ORRri |
| 8578 | { 1877, 3, 1, 4, 994, 0, 0, ARMOpInfoBase + 1505, 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // NEON_VMINNMNQh |
| 8579 | { 1876, 3, 1, 4, 994, 0, 0, ARMOpInfoBase + 1505, 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // NEON_VMINNMNQf |
| 8580 | { 1875, 3, 1, 4, 994, 0, 0, ARMOpInfoBase + 1502, 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // NEON_VMINNMNDh |
| 8581 | { 1874, 3, 1, 4, 994, 0, 0, ARMOpInfoBase + 1502, 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // NEON_VMINNMNDf |
| 8582 | { 1873, 3, 1, 4, 994, 0, 0, ARMOpInfoBase + 1505, 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // NEON_VMAXNMNQh |
| 8583 | { 1872, 3, 1, 4, 994, 0, 0, ARMOpInfoBase + 1505, 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // NEON_VMAXNMNQf |
| 8584 | { 1871, 3, 1, 4, 994, 0, 0, ARMOpInfoBase + 1502, 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // NEON_VMAXNMNDh |
| 8585 | { 1870, 3, 1, 4, 994, 0, 0, ARMOpInfoBase + 1502, 0, 0|(1ULL<<MCID::Commutable), 0x11280ULL }, // NEON_VMAXNMNDf |
| 8586 | { 1869, 7, 1, 4, 326, 0, 0, ARMOpInfoBase + 1495, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL }, // MVNsr |
| 8587 | { 1868, 6, 1, 4, 709, 0, 0, ARMOpInfoBase + 1016, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL }, // MVNsi |
| 8588 | { 1867, 5, 1, 4, 328, 0, 0, ARMOpInfoBase + 327, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL }, // MVNr |
| 8589 | { 1866, 5, 1, 4, 708, 0, 0, ARMOpInfoBase + 1006, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL }, // MVNi |
| 8590 | { 1865, 3, 1, 4, 1284, 0, 0, ARMOpInfoBase + 512, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_WLSTP_8 |
| 8591 | { 1864, 3, 1, 4, 1284, 0, 0, ARMOpInfoBase + 512, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_WLSTP_64 |
| 8592 | { 1863, 3, 1, 4, 1284, 0, 0, ARMOpInfoBase + 512, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_WLSTP_32 |
| 8593 | { 1862, 3, 1, 4, 1284, 0, 0, ARMOpInfoBase + 512, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_WLSTP_16 |
| 8594 | { 1861, 7, 1, 4, 1168, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VSUBi8 |
| 8595 | { 1860, 7, 1, 4, 1168, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VSUBi32 |
| 8596 | { 1859, 7, 1, 4, 1168, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VSUBi16 |
| 8597 | { 1858, 7, 1, 4, 1199, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VSUBf32 |
| 8598 | { 1857, 7, 1, 4, 1199, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VSUBf16 |
| 8599 | { 1856, 7, 1, 4, 1300, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VSUB_qr_i8 |
| 8600 | { 1855, 7, 1, 4, 1300, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VSUB_qr_i32 |
| 8601 | { 1854, 7, 1, 4, 1300, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VSUB_qr_i16 |
| 8602 | { 1853, 7, 1, 4, 1200, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VSUB_qr_f32 |
| 8603 | { 1852, 7, 1, 4, 1200, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VSUB_qr_f16 |
| 8604 | { 1851, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayStore), 0x2140cb5ULL }, // MVE_VSTRWU32_pre |
| 8605 | { 1850, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayStore), 0x2140cd5ULL }, // MVE_VSTRWU32_post |
| 8606 | { 1849, 6, 0, 4, 1118, 0, 0, ARMOpInfoBase + 1306, 0, 0|(1ULL<<MCID::MayStore), 0x2140c95ULL }, // MVE_VSTRWU32 |
| 8607 | { 1848, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // MVE_VSTRW32_rq_u |
| 8608 | { 1847, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // MVE_VSTRW32_rq |
| 8609 | { 1846, 7, 1, 4, 1121, 0, 0, ARMOpInfoBase + 1488, 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // MVE_VSTRW32_qi_pre |
| 8610 | { 1845, 6, 0, 4, 1264, 0, 0, ARMOpInfoBase + 1482, 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // MVE_VSTRW32_qi |
| 8611 | { 1844, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayStore), 0x1140cb6ULL }, // MVE_VSTRHU16_pre |
| 8612 | { 1843, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayStore), 0x1140cd6ULL }, // MVE_VSTRHU16_post |
| 8613 | { 1842, 6, 0, 4, 1118, 0, 0, ARMOpInfoBase + 1306, 0, 0|(1ULL<<MCID::MayStore), 0x1140c96ULL }, // MVE_VSTRHU16 |
| 8614 | { 1841, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // MVE_VSTRH32_rq_u |
| 8615 | { 1840, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // MVE_VSTRH32_rq |
| 8616 | { 1839, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayStore), 0x2140cb6ULL }, // MVE_VSTRH32_pre |
| 8617 | { 1838, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayStore), 0x2140cd6ULL }, // MVE_VSTRH32_post |
| 8618 | { 1837, 6, 0, 4, 1118, 0, 0, ARMOpInfoBase + 1287, 0, 0|(1ULL<<MCID::MayStore), 0x2140c96ULL }, // MVE_VSTRH32 |
| 8619 | { 1836, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x1140c80ULL }, // MVE_VSTRH16_rq_u |
| 8620 | { 1835, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x1140c80ULL }, // MVE_VSTRH16_rq |
| 8621 | { 1834, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // MVE_VSTRD64_rq_u |
| 8622 | { 1833, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // MVE_VSTRD64_rq |
| 8623 | { 1832, 7, 1, 4, 1121, 0, 0, ARMOpInfoBase + 1488, 0, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // MVE_VSTRD64_qi_pre |
| 8624 | { 1831, 6, 0, 4, 1264, 0, 0, ARMOpInfoBase + 1482, 0, 0|(1ULL<<MCID::MayStore), 0x3140c80ULL }, // MVE_VSTRD64_qi |
| 8625 | { 1830, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayStore), 0x140cb7ULL }, // MVE_VSTRBU8_pre |
| 8626 | { 1829, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayStore), 0x140cd7ULL }, // MVE_VSTRBU8_post |
| 8627 | { 1828, 6, 0, 4, 1118, 0, 0, ARMOpInfoBase + 1306, 0, 0|(1ULL<<MCID::MayStore), 0x140c97ULL }, // MVE_VSTRBU8 |
| 8628 | { 1827, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x140c80ULL }, // MVE_VSTRB8_rq |
| 8629 | { 1826, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x2140c80ULL }, // MVE_VSTRB32_rq |
| 8630 | { 1825, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayStore), 0x2140cb7ULL }, // MVE_VSTRB32_pre |
| 8631 | { 1824, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayStore), 0x2140cd7ULL }, // MVE_VSTRB32_post |
| 8632 | { 1823, 6, 0, 4, 1118, 0, 0, ARMOpInfoBase + 1287, 0, 0|(1ULL<<MCID::MayStore), 0x2140c97ULL }, // MVE_VSTRB32 |
| 8633 | { 1822, 6, 0, 4, 1120, 0, 0, ARMOpInfoBase + 1476, 0, 0|(1ULL<<MCID::MayStore), 0x1140c80ULL }, // MVE_VSTRB16_rq |
| 8634 | { 1821, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayStore), 0x1140cb7ULL }, // MVE_VSTRB16_pre |
| 8635 | { 1820, 7, 1, 4, 1119, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayStore), 0x1140cd7ULL }, // MVE_VSTRB16_post |
| 8636 | { 1819, 6, 0, 4, 1118, 0, 0, ARMOpInfoBase + 1287, 0, 0|(1ULL<<MCID::MayStore), 0x1140c97ULL }, // MVE_VSTRB16 |
| 8637 | { 1818, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST43_8_wb |
| 8638 | { 1817, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST43_8 |
| 8639 | { 1816, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST43_32_wb |
| 8640 | { 1815, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST43_32 |
| 8641 | { 1814, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST43_16_wb |
| 8642 | { 1813, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST43_16 |
| 8643 | { 1812, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST42_8_wb |
| 8644 | { 1811, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST42_8 |
| 8645 | { 1810, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST42_32_wb |
| 8646 | { 1809, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST42_32 |
| 8647 | { 1808, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST42_16_wb |
| 8648 | { 1807, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST42_16 |
| 8649 | { 1806, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST41_8_wb |
| 8650 | { 1805, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST41_8 |
| 8651 | { 1804, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST41_32_wb |
| 8652 | { 1803, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST41_32 |
| 8653 | { 1802, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST41_16_wb |
| 8654 | { 1801, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST41_16 |
| 8655 | { 1800, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST40_8_wb |
| 8656 | { 1799, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST40_8 |
| 8657 | { 1798, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST40_32_wb |
| 8658 | { 1797, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST40_32 |
| 8659 | { 1796, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1473, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST40_16_wb |
| 8660 | { 1795, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1471, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST40_16 |
| 8661 | { 1794, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1468, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST21_8_wb |
| 8662 | { 1793, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1466, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST21_8 |
| 8663 | { 1792, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1468, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST21_32_wb |
| 8664 | { 1791, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1466, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST21_32 |
| 8665 | { 1790, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1468, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST21_16_wb |
| 8666 | { 1789, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1466, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST21_16 |
| 8667 | { 1788, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1468, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST20_8_wb |
| 8668 | { 1787, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1466, 0, 0|(1ULL<<MCID::MayStore), 0x40c80ULL }, // MVE_VST20_8 |
| 8669 | { 1786, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1468, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST20_32_wb |
| 8670 | { 1785, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1466, 0, 0|(1ULL<<MCID::MayStore), 0x2040c80ULL }, // MVE_VST20_32 |
| 8671 | { 1784, 3, 1, 4, 1122, 0, 0, ARMOpInfoBase + 1468, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST20_16_wb |
| 8672 | { 1783, 2, 0, 4, 1263, 0, 0, ARMOpInfoBase + 1466, 0, 0|(1ULL<<MCID::MayStore), 0x1040c80ULL }, // MVE_VST20_16 |
| 8673 | { 1782, 7, 1, 4, 1167, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x140c80ULL }, // MVE_VSRIimm8 |
| 8674 | { 1781, 7, 1, 4, 1167, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2140c80ULL }, // MVE_VSRIimm32 |
| 8675 | { 1780, 7, 1, 4, 1167, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1140c80ULL }, // MVE_VSRIimm16 |
| 8676 | { 1779, 7, 1, 4, 1166, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x140c80ULL }, // MVE_VSLIimm8 |
| 8677 | { 1778, 7, 1, 4, 1166, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2140c80ULL }, // MVE_VSLIimm32 |
| 8678 | { 1777, 7, 1, 4, 1166, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1140c80ULL }, // MVE_VSLIimm16 |
| 8679 | { 1776, 7, 1, 4, 1160, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x140c80ULL }, // MVE_VSHR_immu8 |
| 8680 | { 1775, 7, 1, 4, 1160, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VSHR_immu32 |
| 8681 | { 1774, 7, 1, 4, 1160, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VSHR_immu16 |
| 8682 | { 1773, 7, 1, 4, 1160, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x140c80ULL }, // MVE_VSHR_imms8 |
| 8683 | { 1772, 7, 1, 4, 1160, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VSHR_imms32 |
| 8684 | { 1771, 7, 1, 4, 1160, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VSHR_imms16 |
| 8685 | { 1770, 7, 1, 4, 1302, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VSHRNi32th |
| 8686 | { 1769, 7, 1, 4, 1302, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VSHRNi32bh |
| 8687 | { 1768, 7, 1, 4, 1302, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VSHRNi16th |
| 8688 | { 1767, 7, 1, 4, 1302, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VSHRNi16bh |
| 8689 | { 1766, 6, 1, 4, 1299, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x140c80ULL }, // MVE_VSHL_qru8 |
| 8690 | { 1765, 6, 1, 4, 1299, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x2140c80ULL }, // MVE_VSHL_qru32 |
| 8691 | { 1764, 6, 1, 4, 1299, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x1140c80ULL }, // MVE_VSHL_qru16 |
| 8692 | { 1763, 6, 1, 4, 1299, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x140c80ULL }, // MVE_VSHL_qrs8 |
| 8693 | { 1762, 6, 1, 4, 1299, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x2140c80ULL }, // MVE_VSHL_qrs32 |
| 8694 | { 1761, 6, 1, 4, 1299, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x1140c80ULL }, // MVE_VSHL_qrs16 |
| 8695 | { 1760, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x140c80ULL }, // MVE_VSHL_immi8 |
| 8696 | { 1759, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VSHL_immi32 |
| 8697 | { 1758, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VSHL_immi16 |
| 8698 | { 1757, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VSHL_by_vecu8 |
| 8699 | { 1756, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VSHL_by_vecu32 |
| 8700 | { 1755, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VSHL_by_vecu16 |
| 8701 | { 1754, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VSHL_by_vecs8 |
| 8702 | { 1753, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VSHL_by_vecs32 |
| 8703 | { 1752, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VSHL_by_vecs16 |
| 8704 | { 1751, 6, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1840c80ULL }, // MVE_VSHLL_lwu8th |
| 8705 | { 1750, 6, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1840c80ULL }, // MVE_VSHLL_lwu8bh |
| 8706 | { 1749, 6, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2840c80ULL }, // MVE_VSHLL_lwu16th |
| 8707 | { 1748, 6, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2840c80ULL }, // MVE_VSHLL_lwu16bh |
| 8708 | { 1747, 6, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1840c80ULL }, // MVE_VSHLL_lws8th |
| 8709 | { 1746, 6, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1840c80ULL }, // MVE_VSHLL_lws8bh |
| 8710 | { 1745, 6, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2840c80ULL }, // MVE_VSHLL_lws16th |
| 8711 | { 1744, 6, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2840c80ULL }, // MVE_VSHLL_lws16bh |
| 8712 | { 1743, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1840c80ULL }, // MVE_VSHLL_immu8th |
| 8713 | { 1742, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1840c80ULL }, // MVE_VSHLL_immu8bh |
| 8714 | { 1741, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2840c80ULL }, // MVE_VSHLL_immu16th |
| 8715 | { 1740, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2840c80ULL }, // MVE_VSHLL_immu16bh |
| 8716 | { 1739, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1840c80ULL }, // MVE_VSHLL_imms8th |
| 8717 | { 1738, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1840c80ULL }, // MVE_VSHLL_imms8bh |
| 8718 | { 1737, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2840c80ULL }, // MVE_VSHLL_imms16th |
| 8719 | { 1736, 7, 1, 4, 1301, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2840c80ULL }, // MVE_VSHLL_imms16bh |
| 8720 | { 1735, 8, 2, 4, 1156, 0, 0, ARMOpInfoBase + 1458, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // MVE_VSHLC |
| 8721 | { 1734, 8, 2, 4, 1165, 0, 0, ARMOpInfoBase + 1126, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // MVE_VSBCI |
| 8722 | { 1733, 9, 2, 4, 1165, 0, 0, ARMOpInfoBase + 1117, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // MVE_VSBC |
| 8723 | { 1732, 7, 1, 4, 1161, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x140c80ULL }, // MVE_VRSHR_immu8 |
| 8724 | { 1731, 7, 1, 4, 1161, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VRSHR_immu32 |
| 8725 | { 1730, 7, 1, 4, 1161, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VRSHR_immu16 |
| 8726 | { 1729, 7, 1, 4, 1161, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x140c80ULL }, // MVE_VRSHR_imms8 |
| 8727 | { 1728, 7, 1, 4, 1161, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VRSHR_imms32 |
| 8728 | { 1727, 7, 1, 4, 1161, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VRSHR_imms16 |
| 8729 | { 1726, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VRSHRNi32th |
| 8730 | { 1725, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VRSHRNi32bh |
| 8731 | { 1724, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VRSHRNi16th |
| 8732 | { 1723, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VRSHRNi16bh |
| 8733 | { 1722, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x140c80ULL }, // MVE_VRSHL_qru8 |
| 8734 | { 1721, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x2140c80ULL }, // MVE_VRSHL_qru32 |
| 8735 | { 1720, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x1140c80ULL }, // MVE_VRSHL_qru16 |
| 8736 | { 1719, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x140c80ULL }, // MVE_VRSHL_qrs8 |
| 8737 | { 1718, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x2140c80ULL }, // MVE_VRSHL_qrs32 |
| 8738 | { 1717, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x1140c80ULL }, // MVE_VRSHL_qrs16 |
| 8739 | { 1716, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VRSHL_by_vecu8 |
| 8740 | { 1715, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VRSHL_by_vecu32 |
| 8741 | { 1714, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VRSHL_by_vecu16 |
| 8742 | { 1713, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VRSHL_by_vecs8 |
| 8743 | { 1712, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VRSHL_by_vecs32 |
| 8744 | { 1711, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VRSHL_by_vecs16 |
| 8745 | { 1710, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VRMULHu8 |
| 8746 | { 1709, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VRMULHu32 |
| 8747 | { 1708, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VRMULHu16 |
| 8748 | { 1707, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VRMULHs8 |
| 8749 | { 1706, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VRMULHs32 |
| 8750 | { 1705, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VRMULHs16 |
| 8751 | { 1704, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2440c80ULL }, // MVE_VRMLSLDAVHxs32 |
| 8752 | { 1703, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2540c80ULL }, // MVE_VRMLSLDAVHs32 |
| 8753 | { 1702, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2440c80ULL }, // MVE_VRMLSLDAVHaxs32 |
| 8754 | { 1701, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2540c80ULL }, // MVE_VRMLSLDAVHas32 |
| 8755 | { 1700, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2440c80ULL }, // MVE_VRMLALDAVHxs32 |
| 8756 | { 1699, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2540c80ULL }, // MVE_VRMLALDAVHu32 |
| 8757 | { 1698, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2540c80ULL }, // MVE_VRMLALDAVHs32 |
| 8758 | { 1697, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2440c80ULL }, // MVE_VRMLALDAVHaxs32 |
| 8759 | { 1696, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2540c80ULL }, // MVE_VRMLALDAVHau32 |
| 8760 | { 1695, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2540c80ULL }, // MVE_VRMLALDAVHas32 |
| 8761 | { 1694, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VRINTf32Z |
| 8762 | { 1693, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VRINTf32X |
| 8763 | { 1692, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VRINTf32P |
| 8764 | { 1691, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VRINTf32N |
| 8765 | { 1690, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VRINTf32M |
| 8766 | { 1689, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VRINTf32A |
| 8767 | { 1688, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VRINTf16Z |
| 8768 | { 1687, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VRINTf16X |
| 8769 | { 1686, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VRINTf16P |
| 8770 | { 1685, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VRINTf16N |
| 8771 | { 1684, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VRINTf16M |
| 8772 | { 1683, 6, 1, 4, 1198, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VRINTf16A |
| 8773 | { 1682, 7, 1, 4, 1164, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VRHADDu8 |
| 8774 | { 1681, 7, 1, 4, 1164, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VRHADDu32 |
| 8775 | { 1680, 7, 1, 4, 1164, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VRHADDu16 |
| 8776 | { 1679, 7, 1, 4, 1164, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VRHADDs8 |
| 8777 | { 1678, 7, 1, 4, 1164, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VRHADDs32 |
| 8778 | { 1677, 7, 1, 4, 1164, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VRHADDs16 |
| 8779 | { 1676, 6, 1, 4, 1163, 0, 0, ARMOpInfoBase + 1452, 0, 0, 0x3040c80ULL }, // MVE_VREV64_8 |
| 8780 | { 1675, 6, 1, 4, 1163, 0, 0, ARMOpInfoBase + 1452, 0, 0, 0x3040c80ULL }, // MVE_VREV64_32 |
| 8781 | { 1674, 6, 1, 4, 1163, 0, 0, ARMOpInfoBase + 1452, 0, 0, 0x3040c80ULL }, // MVE_VREV64_16 |
| 8782 | { 1673, 6, 1, 4, 1163, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2040c80ULL }, // MVE_VREV32_8 |
| 8783 | { 1672, 6, 1, 4, 1163, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2040c80ULL }, // MVE_VREV32_16 |
| 8784 | { 1671, 6, 1, 4, 1163, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1040c80ULL }, // MVE_VREV16_8 |
| 8785 | { 1670, 7, 1, 4, 1162, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQSUBu8 |
| 8786 | { 1669, 7, 1, 4, 1162, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQSUBu32 |
| 8787 | { 1668, 7, 1, 4, 1162, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQSUBu16 |
| 8788 | { 1667, 7, 1, 4, 1162, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQSUBs8 |
| 8789 | { 1666, 7, 1, 4, 1162, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQSUBs32 |
| 8790 | { 1665, 7, 1, 4, 1162, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQSUBs16 |
| 8791 | { 1664, 7, 1, 4, 1298, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VQSUB_qr_u8 |
| 8792 | { 1663, 7, 1, 4, 1298, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VQSUB_qr_u32 |
| 8793 | { 1662, 7, 1, 4, 1298, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VQSUB_qr_u16 |
| 8794 | { 1661, 7, 1, 4, 1298, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VQSUB_qr_s8 |
| 8795 | { 1660, 7, 1, 4, 1298, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VQSUB_qr_s32 |
| 8796 | { 1659, 7, 1, 4, 1298, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VQSUB_qr_s16 |
| 8797 | { 1658, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQSHRUNs32th |
| 8798 | { 1657, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQSHRUNs32bh |
| 8799 | { 1656, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQSHRUNs16th |
| 8800 | { 1655, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQSHRUNs16bh |
| 8801 | { 1654, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQSHRNthu32 |
| 8802 | { 1653, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQSHRNthu16 |
| 8803 | { 1652, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQSHRNths32 |
| 8804 | { 1651, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQSHRNths16 |
| 8805 | { 1650, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQSHRNbhu32 |
| 8806 | { 1649, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQSHRNbhu16 |
| 8807 | { 1648, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQSHRNbhs32 |
| 8808 | { 1647, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQSHRNbhs16 |
| 8809 | { 1646, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x140c80ULL }, // MVE_VQSHLimmu8 |
| 8810 | { 1645, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VQSHLimmu32 |
| 8811 | { 1644, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VQSHLimmu16 |
| 8812 | { 1643, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x140c80ULL }, // MVE_VQSHLimms8 |
| 8813 | { 1642, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VQSHLimms32 |
| 8814 | { 1641, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VQSHLimms16 |
| 8815 | { 1640, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x140c80ULL }, // MVE_VQSHL_qru8 |
| 8816 | { 1639, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x2140c80ULL }, // MVE_VQSHL_qru32 |
| 8817 | { 1638, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x1140c80ULL }, // MVE_VQSHL_qru16 |
| 8818 | { 1637, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x140c80ULL }, // MVE_VQSHL_qrs8 |
| 8819 | { 1636, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x2140c80ULL }, // MVE_VQSHL_qrs32 |
| 8820 | { 1635, 6, 1, 4, 1306, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x1140c80ULL }, // MVE_VQSHL_qrs16 |
| 8821 | { 1634, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQSHL_by_vecu8 |
| 8822 | { 1633, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQSHL_by_vecu32 |
| 8823 | { 1632, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQSHL_by_vecu16 |
| 8824 | { 1631, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQSHL_by_vecs8 |
| 8825 | { 1630, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQSHL_by_vecs32 |
| 8826 | { 1629, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQSHL_by_vecs16 |
| 8827 | { 1628, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x140c80ULL }, // MVE_VQSHLU_imms8 |
| 8828 | { 1627, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VQSHLU_imms32 |
| 8829 | { 1626, 7, 1, 4, 1157, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VQSHLU_imms16 |
| 8830 | { 1625, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQRSHRUNs32th |
| 8831 | { 1624, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQRSHRUNs32bh |
| 8832 | { 1623, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQRSHRUNs16th |
| 8833 | { 1622, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQRSHRUNs16bh |
| 8834 | { 1621, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQRSHRNthu32 |
| 8835 | { 1620, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQRSHRNthu16 |
| 8836 | { 1619, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQRSHRNths32 |
| 8837 | { 1618, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQRSHRNths16 |
| 8838 | { 1617, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQRSHRNbhu32 |
| 8839 | { 1616, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQRSHRNbhu16 |
| 8840 | { 1615, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x2340c80ULL }, // MVE_VQRSHRNbhs32 |
| 8841 | { 1614, 7, 1, 4, 1159, 0, 0, ARMOpInfoBase + 1445, 0, 0, 0x1340c80ULL }, // MVE_VQRSHRNbhs16 |
| 8842 | { 1613, 6, 1, 4, 1305, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x140c80ULL }, // MVE_VQRSHL_qru8 |
| 8843 | { 1612, 6, 1, 4, 1305, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x2140c80ULL }, // MVE_VQRSHL_qru32 |
| 8844 | { 1611, 6, 1, 4, 1305, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x1140c80ULL }, // MVE_VQRSHL_qru16 |
| 8845 | { 1610, 6, 1, 4, 1305, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x140c80ULL }, // MVE_VQRSHL_qrs8 |
| 8846 | { 1609, 6, 1, 4, 1305, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x2140c80ULL }, // MVE_VQRSHL_qrs32 |
| 8847 | { 1608, 6, 1, 4, 1305, 0, 0, ARMOpInfoBase + 1439, 0, 0, 0x1140c80ULL }, // MVE_VQRSHL_qrs16 |
| 8848 | { 1607, 7, 1, 4, 1158, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQRSHL_by_vecu8 |
| 8849 | { 1606, 7, 1, 4, 1158, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQRSHL_by_vecu32 |
| 8850 | { 1605, 7, 1, 4, 1158, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQRSHL_by_vecu16 |
| 8851 | { 1604, 7, 1, 4, 1158, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQRSHL_by_vecs8 |
| 8852 | { 1603, 7, 1, 4, 1158, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQRSHL_by_vecs32 |
| 8853 | { 1602, 7, 1, 4, 1158, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQRSHL_by_vecs16 |
| 8854 | { 1601, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQRDMULHi8 |
| 8855 | { 1600, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQRDMULHi32 |
| 8856 | { 1599, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQRDMULHi16 |
| 8857 | { 1598, 7, 1, 4, 1311, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VQRDMULH_qr_s8 |
| 8858 | { 1597, 7, 1, 4, 1311, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VQRDMULH_qr_s32 |
| 8859 | { 1596, 7, 1, 4, 1311, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VQRDMULH_qr_s16 |
| 8860 | { 1595, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x40c80ULL }, // MVE_VQRDMLSDHs8 |
| 8861 | { 1594, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1425, 0, 0, 0x2040c80ULL }, // MVE_VQRDMLSDHs32 |
| 8862 | { 1593, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1040c80ULL }, // MVE_VQRDMLSDHs16 |
| 8863 | { 1592, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x40c80ULL }, // MVE_VQRDMLSDHXs8 |
| 8864 | { 1591, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1425, 0, 0, 0x2040c80ULL }, // MVE_VQRDMLSDHXs32 |
| 8865 | { 1590, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1040c80ULL }, // MVE_VQRDMLSDHXs16 |
| 8866 | { 1589, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x40c80ULL }, // MVE_VQRDMLASH_qrs8 |
| 8867 | { 1588, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x2040c80ULL }, // MVE_VQRDMLASH_qrs32 |
| 8868 | { 1587, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x1040c80ULL }, // MVE_VQRDMLASH_qrs16 |
| 8869 | { 1586, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x40c80ULL }, // MVE_VQRDMLAH_qrs8 |
| 8870 | { 1585, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x2040c80ULL }, // MVE_VQRDMLAH_qrs32 |
| 8871 | { 1584, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x1040c80ULL }, // MVE_VQRDMLAH_qrs16 |
| 8872 | { 1583, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x40c80ULL }, // MVE_VQRDMLADHs8 |
| 8873 | { 1582, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1425, 0, 0, 0x2040c80ULL }, // MVE_VQRDMLADHs32 |
| 8874 | { 1581, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1040c80ULL }, // MVE_VQRDMLADHs16 |
| 8875 | { 1580, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x40c80ULL }, // MVE_VQRDMLADHXs8 |
| 8876 | { 1579, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1425, 0, 0, 0x2040c80ULL }, // MVE_VQRDMLADHXs32 |
| 8877 | { 1578, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1040c80ULL }, // MVE_VQRDMLADHXs16 |
| 8878 | { 1577, 6, 1, 4, 1155, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x140c80ULL }, // MVE_VQNEGs8 |
| 8879 | { 1576, 6, 1, 4, 1155, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VQNEGs32 |
| 8880 | { 1575, 6, 1, 4, 1155, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VQNEGs16 |
| 8881 | { 1574, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2340c80ULL }, // MVE_VQMOVUNs32th |
| 8882 | { 1573, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2340c80ULL }, // MVE_VQMOVUNs32bh |
| 8883 | { 1572, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1340c80ULL }, // MVE_VQMOVUNs16th |
| 8884 | { 1571, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1340c80ULL }, // MVE_VQMOVUNs16bh |
| 8885 | { 1570, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2340c80ULL }, // MVE_VQMOVNu32th |
| 8886 | { 1569, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2340c80ULL }, // MVE_VQMOVNu32bh |
| 8887 | { 1568, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1340c80ULL }, // MVE_VQMOVNu16th |
| 8888 | { 1567, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1340c80ULL }, // MVE_VQMOVNu16bh |
| 8889 | { 1566, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2340c80ULL }, // MVE_VQMOVNs32th |
| 8890 | { 1565, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2340c80ULL }, // MVE_VQMOVNs32bh |
| 8891 | { 1564, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1340c80ULL }, // MVE_VQMOVNs16th |
| 8892 | { 1563, 6, 1, 4, 1154, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1340c80ULL }, // MVE_VQMOVNs16bh |
| 8893 | { 1562, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1399, 0, 0, 0x2940c80ULL }, // MVE_VQDMULLs32th |
| 8894 | { 1561, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1399, 0, 0, 0x2940c80ULL }, // MVE_VQDMULLs32bh |
| 8895 | { 1560, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1940c80ULL }, // MVE_VQDMULLs16th |
| 8896 | { 1559, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1940c80ULL }, // MVE_VQDMULLs16bh |
| 8897 | { 1558, 7, 1, 4, 1194, 0, 0, ARMOpInfoBase + 1432, 0, 0, 0x2940c80ULL }, // MVE_VQDMULL_qr_s32th |
| 8898 | { 1557, 7, 1, 4, 1194, 0, 0, ARMOpInfoBase + 1432, 0, 0, 0x2940c80ULL }, // MVE_VQDMULL_qr_s32bh |
| 8899 | { 1556, 7, 1, 4, 1194, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1940c80ULL }, // MVE_VQDMULL_qr_s16th |
| 8900 | { 1555, 7, 1, 4, 1194, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1940c80ULL }, // MVE_VQDMULL_qr_s16bh |
| 8901 | { 1554, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQDMULHi8 |
| 8902 | { 1553, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQDMULHi32 |
| 8903 | { 1552, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQDMULHi16 |
| 8904 | { 1551, 7, 1, 4, 1311, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VQDMULH_qr_s8 |
| 8905 | { 1550, 7, 1, 4, 1311, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VQDMULH_qr_s32 |
| 8906 | { 1549, 7, 1, 4, 1311, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VQDMULH_qr_s16 |
| 8907 | { 1548, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x40c80ULL }, // MVE_VQDMLSDHs8 |
| 8908 | { 1547, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1425, 0, 0, 0x2040c80ULL }, // MVE_VQDMLSDHs32 |
| 8909 | { 1546, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1040c80ULL }, // MVE_VQDMLSDHs16 |
| 8910 | { 1545, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x40c80ULL }, // MVE_VQDMLSDHXs8 |
| 8911 | { 1544, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1425, 0, 0, 0x2040c80ULL }, // MVE_VQDMLSDHXs32 |
| 8912 | { 1543, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1040c80ULL }, // MVE_VQDMLSDHXs16 |
| 8913 | { 1542, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x40c80ULL }, // MVE_VQDMLASH_qrs8 |
| 8914 | { 1541, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x2040c80ULL }, // MVE_VQDMLASH_qrs32 |
| 8915 | { 1540, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x1040c80ULL }, // MVE_VQDMLASH_qrs16 |
| 8916 | { 1539, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x40c80ULL }, // MVE_VQDMLAH_qrs8 |
| 8917 | { 1538, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x2040c80ULL }, // MVE_VQDMLAH_qrs32 |
| 8918 | { 1537, 7, 1, 4, 1313, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x1040c80ULL }, // MVE_VQDMLAH_qrs16 |
| 8919 | { 1536, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x40c80ULL }, // MVE_VQDMLADHs8 |
| 8920 | { 1535, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1425, 0, 0, 0x2040c80ULL }, // MVE_VQDMLADHs32 |
| 8921 | { 1534, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1040c80ULL }, // MVE_VQDMLADHs16 |
| 8922 | { 1533, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x40c80ULL }, // MVE_VQDMLADHXs8 |
| 8923 | { 1532, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1425, 0, 0, 0x2040c80ULL }, // MVE_VQDMLADHXs32 |
| 8924 | { 1531, 7, 1, 4, 1314, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1040c80ULL }, // MVE_VQDMLADHXs16 |
| 8925 | { 1530, 7, 1, 4, 1153, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQADDu8 |
| 8926 | { 1529, 7, 1, 4, 1153, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQADDu32 |
| 8927 | { 1528, 7, 1, 4, 1153, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQADDu16 |
| 8928 | { 1527, 7, 1, 4, 1153, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VQADDs8 |
| 8929 | { 1526, 7, 1, 4, 1153, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VQADDs32 |
| 8930 | { 1525, 7, 1, 4, 1153, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VQADDs16 |
| 8931 | { 1524, 7, 1, 4, 1297, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VQADD_qr_u8 |
| 8932 | { 1523, 7, 1, 4, 1297, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VQADD_qr_u32 |
| 8933 | { 1522, 7, 1, 4, 1297, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VQADD_qr_u16 |
| 8934 | { 1521, 7, 1, 4, 1297, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VQADD_qr_s8 |
| 8935 | { 1520, 7, 1, 4, 1297, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VQADD_qr_s32 |
| 8936 | { 1519, 7, 1, 4, 1297, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VQADD_qr_s16 |
| 8937 | { 1518, 6, 1, 4, 1152, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x140c80ULL }, // MVE_VQABSs8 |
| 8938 | { 1517, 6, 1, 4, 1152, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VQABSs32 |
| 8939 | { 1516, 6, 1, 4, 1152, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VQABSs16 |
| 8940 | { 1515, 4, 0, 4, 1321, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // MVE_VPTv8u16r |
| 8941 | { 1514, 4, 0, 4, 1178, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // MVE_VPTv8u16 |
| 8942 | { 1513, 4, 0, 4, 1321, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // MVE_VPTv8s16r |
| 8943 | { 1512, 4, 0, 4, 1178, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // MVE_VPTv8s16 |
| 8944 | { 1511, 4, 0, 4, 1321, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // MVE_VPTv8i16r |
| 8945 | { 1510, 4, 0, 4, 1178, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // MVE_VPTv8i16 |
| 8946 | { 1509, 4, 0, 4, 1320, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // MVE_VPTv8f16r |
| 8947 | { 1508, 4, 0, 4, 1179, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1140c80ULL }, // MVE_VPTv8f16 |
| 8948 | { 1507, 4, 0, 4, 1321, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // MVE_VPTv4u32r |
| 8949 | { 1506, 4, 0, 4, 1178, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // MVE_VPTv4u32 |
| 8950 | { 1505, 4, 0, 4, 1321, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // MVE_VPTv4s32r |
| 8951 | { 1504, 4, 0, 4, 1178, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // MVE_VPTv4s32 |
| 8952 | { 1503, 4, 0, 4, 1321, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // MVE_VPTv4i32r |
| 8953 | { 1502, 4, 0, 4, 1178, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // MVE_VPTv4i32 |
| 8954 | { 1501, 4, 0, 4, 1320, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // MVE_VPTv4f32r |
| 8955 | { 1500, 4, 0, 4, 1179, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2140c80ULL }, // MVE_VPTv4f32 |
| 8956 | { 1499, 4, 0, 4, 1321, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // MVE_VPTv16u8r |
| 8957 | { 1498, 4, 0, 4, 1178, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // MVE_VPTv16u8 |
| 8958 | { 1497, 4, 0, 4, 1321, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // MVE_VPTv16s8r |
| 8959 | { 1496, 4, 0, 4, 1178, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // MVE_VPTv16s8 |
| 8960 | { 1495, 4, 0, 4, 1321, 0, 1, ARMOpInfoBase + 1421, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // MVE_VPTv16i8r |
| 8961 | { 1494, 4, 0, 4, 1178, 0, 1, ARMOpInfoBase + 1417, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // MVE_VPTv16i8 |
| 8962 | { 1493, 1, 0, 4, 1204, 1, 0, ARMOpInfoBase + 0, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL }, // MVE_VPST |
| 8963 | { 1492, 6, 1, 4, 1150, 0, 0, ARMOpInfoBase + 1411, 0, 0, 0x40c80ULL }, // MVE_VPSEL |
| 8964 | { 1491, 5, 1, 4, 1203, 0, 0, ARMOpInfoBase + 1406, 0, 0, 0x40c80ULL }, // MVE_VPNOT |
| 8965 | { 1490, 6, 1, 4, 1149, 0, 0, ARMOpInfoBase + 1166, 0, 0, 0x2140c80ULL }, // MVE_VORRimmi32 |
| 8966 | { 1489, 6, 1, 4, 1149, 0, 0, ARMOpInfoBase + 1166, 0, 0, 0x1140c80ULL }, // MVE_VORRimmi16 |
| 8967 | { 1488, 7, 1, 4, 1149, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VORR |
| 8968 | { 1487, 7, 1, 4, 1148, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VORN |
| 8969 | { 1486, 6, 1, 4, 1147, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x140c80ULL }, // MVE_VNEGs8 |
| 8970 | { 1485, 6, 1, 4, 1147, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VNEGs32 |
| 8971 | { 1484, 6, 1, 4, 1147, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VNEGs16 |
| 8972 | { 1483, 6, 1, 4, 1197, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VNEGf32 |
| 8973 | { 1482, 6, 1, 4, 1197, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VNEGf16 |
| 8974 | { 1481, 6, 1, 4, 1146, 0, 0, ARMOpInfoBase + 1393, 0, 0|(1ULL<<MCID::Rematerializable), 0x2140c80ULL }, // MVE_VMVNimmi32 |
| 8975 | { 1480, 6, 1, 4, 1146, 0, 0, ARMOpInfoBase + 1393, 0, 0|(1ULL<<MCID::Rematerializable), 0x1140c80ULL }, // MVE_VMVNimmi16 |
| 8976 | { 1479, 6, 1, 4, 1146, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x140c80ULL }, // MVE_VMVN |
| 8977 | { 1478, 7, 1, 4, 1317, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VMULi8 |
| 8978 | { 1477, 7, 1, 4, 1317, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMULi32 |
| 8979 | { 1476, 7, 1, 4, 1317, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMULi16 |
| 8980 | { 1475, 7, 1, 4, 1191, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMULf32 |
| 8981 | { 1474, 7, 1, 4, 1191, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMULf16 |
| 8982 | { 1473, 7, 1, 4, 1310, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VMUL_qr_i8 |
| 8983 | { 1472, 7, 1, 4, 1310, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VMUL_qr_i32 |
| 8984 | { 1471, 7, 1, 4, 1310, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VMUL_qr_i16 |
| 8985 | { 1470, 7, 1, 4, 1318, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VMUL_qr_f32 |
| 8986 | { 1469, 7, 1, 4, 1318, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VMUL_qr_f16 |
| 8987 | { 1468, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1940c80ULL }, // MVE_VMULLTu8 |
| 8988 | { 1467, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1399, 0, 0, 0x3940c80ULL }, // MVE_VMULLTu32 |
| 8989 | { 1466, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2940c80ULL }, // MVE_VMULLTu16 |
| 8990 | { 1465, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1940c80ULL }, // MVE_VMULLTs8 |
| 8991 | { 1464, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1399, 0, 0, 0x3940c80ULL }, // MVE_VMULLTs32 |
| 8992 | { 1463, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2940c80ULL }, // MVE_VMULLTs16 |
| 8993 | { 1462, 7, 1, 4, 1145, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1940c80ULL }, // MVE_VMULLTp8 |
| 8994 | { 1461, 7, 1, 4, 1145, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2940c80ULL }, // MVE_VMULLTp16 |
| 8995 | { 1460, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1940c80ULL }, // MVE_VMULLBu8 |
| 8996 | { 1459, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1399, 0, 0, 0x3940c80ULL }, // MVE_VMULLBu32 |
| 8997 | { 1458, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2940c80ULL }, // MVE_VMULLBu16 |
| 8998 | { 1457, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1940c80ULL }, // MVE_VMULLBs8 |
| 8999 | { 1456, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1399, 0, 0, 0x3940c80ULL }, // MVE_VMULLBs32 |
| 9000 | { 1455, 7, 1, 4, 1193, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2940c80ULL }, // MVE_VMULLBs16 |
| 9001 | { 1454, 7, 1, 4, 1145, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1940c80ULL }, // MVE_VMULLBp8 |
| 9002 | { 1453, 7, 1, 4, 1145, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2940c80ULL }, // MVE_VMULLBp16 |
| 9003 | { 1452, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VMULHu8 |
| 9004 | { 1451, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMULHu32 |
| 9005 | { 1450, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMULHu16 |
| 9006 | { 1449, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VMULHs8 |
| 9007 | { 1448, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMULHs32 |
| 9008 | { 1447, 7, 1, 4, 1192, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMULHs16 |
| 9009 | { 1446, 6, 1, 4, 1190, 0, 0, ARMOpInfoBase + 1393, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x140c80ULL }, // MVE_VMOVimmi8 |
| 9010 | { 1445, 6, 1, 4, 1190, 0, 0, ARMOpInfoBase + 1393, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3140c80ULL }, // MVE_VMOVimmi64 |
| 9011 | { 1444, 6, 1, 4, 1190, 0, 0, ARMOpInfoBase + 1393, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2140c80ULL }, // MVE_VMOVimmi32 |
| 9012 | { 1443, 6, 1, 4, 1190, 0, 0, ARMOpInfoBase + 1393, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x1140c80ULL }, // MVE_VMOVimmi16 |
| 9013 | { 1442, 6, 1, 4, 1190, 0, 0, ARMOpInfoBase + 1393, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2140c80ULL }, // MVE_VMOVimmf32 |
| 9014 | { 1441, 6, 1, 4, 1201, 0, 0, ARMOpInfoBase + 1387, 0, 0|(1ULL<<MCID::Predicable), 0x40c80ULL }, // MVE_VMOV_to_lane_8 |
| 9015 | { 1440, 6, 1, 4, 1201, 0, 0, ARMOpInfoBase + 1387, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::InsertSubreg), 0x2040c80ULL }, // MVE_VMOV_to_lane_32 |
| 9016 | { 1439, 6, 1, 4, 1201, 0, 0, ARMOpInfoBase + 1387, 0, 0|(1ULL<<MCID::Predicable), 0x1040c80ULL }, // MVE_VMOV_to_lane_16 |
| 9017 | { 1438, 7, 2, 4, 1189, 0, 0, ARMOpInfoBase + 1380, 0, 0|(1ULL<<MCID::Predicable), 0x2040c80ULL }, // MVE_VMOV_rr_q |
| 9018 | { 1437, 8, 1, 4, 1292, 0, 0, ARMOpInfoBase + 1372, 0, 0|(1ULL<<MCID::Predicable), 0x2040c80ULL }, // MVE_VMOV_q_rr |
| 9019 | { 1436, 5, 1, 4, 1188, 0, 0, ARMOpInfoBase + 1367, 0, 0|(1ULL<<MCID::Predicable), 0x40c80ULL }, // MVE_VMOV_from_lane_u8 |
| 9020 | { 1435, 5, 1, 4, 1188, 0, 0, ARMOpInfoBase + 1367, 0, 0|(1ULL<<MCID::Predicable), 0x1040c80ULL }, // MVE_VMOV_from_lane_u16 |
| 9021 | { 1434, 5, 1, 4, 1188, 0, 0, ARMOpInfoBase + 1367, 0, 0|(1ULL<<MCID::Predicable), 0x40c80ULL }, // MVE_VMOV_from_lane_s8 |
| 9022 | { 1433, 5, 1, 4, 1188, 0, 0, ARMOpInfoBase + 1367, 0, 0|(1ULL<<MCID::Predicable), 0x1040c80ULL }, // MVE_VMOV_from_lane_s16 |
| 9023 | { 1432, 5, 1, 4, 1188, 0, 0, ARMOpInfoBase + 1367, 0, 0|(1ULL<<MCID::Predicable), 0x2040c80ULL }, // MVE_VMOV_from_lane_32 |
| 9024 | { 1431, 6, 1, 4, 1143, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2340c80ULL }, // MVE_VMOVNi32th |
| 9025 | { 1430, 6, 1, 4, 1143, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2340c80ULL }, // MVE_VMOVNi32bh |
| 9026 | { 1429, 6, 1, 4, 1143, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1340c80ULL }, // MVE_VMOVNi16th |
| 9027 | { 1428, 6, 1, 4, 1143, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1340c80ULL }, // MVE_VMOVNi16bh |
| 9028 | { 1427, 6, 1, 4, 1144, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1840c80ULL }, // MVE_VMOVLu8th |
| 9029 | { 1426, 6, 1, 4, 1144, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1840c80ULL }, // MVE_VMOVLu8bh |
| 9030 | { 1425, 6, 1, 4, 1144, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2840c80ULL }, // MVE_VMOVLu16th |
| 9031 | { 1424, 6, 1, 4, 1144, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2840c80ULL }, // MVE_VMOVLu16bh |
| 9032 | { 1423, 6, 1, 4, 1144, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1840c80ULL }, // MVE_VMOVLs8th |
| 9033 | { 1422, 6, 1, 4, 1144, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1840c80ULL }, // MVE_VMOVLs8bh |
| 9034 | { 1421, 6, 1, 4, 1144, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2840c80ULL }, // MVE_VMOVLs16th |
| 9035 | { 1420, 6, 1, 4, 1144, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2840c80ULL }, // MVE_VMOVLs16bh |
| 9036 | { 1419, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2440c80ULL }, // MVE_VMLSLDAVxs32 |
| 9037 | { 1418, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x1440c80ULL }, // MVE_VMLSLDAVxs16 |
| 9038 | { 1417, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2540c80ULL }, // MVE_VMLSLDAVs32 |
| 9039 | { 1416, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x1540c80ULL }, // MVE_VMLSLDAVs16 |
| 9040 | { 1415, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2440c80ULL }, // MVE_VMLSLDAVaxs32 |
| 9041 | { 1414, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x1440c80ULL }, // MVE_VMLSLDAVaxs16 |
| 9042 | { 1413, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2540c80ULL }, // MVE_VMLSLDAVas32 |
| 9043 | { 1412, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x1540c80ULL }, // MVE_VMLSLDAVas16 |
| 9044 | { 1411, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x440c80ULL }, // MVE_VMLSDAVxs8 |
| 9045 | { 1410, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x2440c80ULL }, // MVE_VMLSDAVxs32 |
| 9046 | { 1409, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x1440c80ULL }, // MVE_VMLSDAVxs16 |
| 9047 | { 1408, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x540c80ULL }, // MVE_VMLSDAVs8 |
| 9048 | { 1407, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x2540c80ULL }, // MVE_VMLSDAVs32 |
| 9049 | { 1406, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x1540c80ULL }, // MVE_VMLSDAVs16 |
| 9050 | { 1405, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x440c80ULL }, // MVE_VMLSDAVaxs8 |
| 9051 | { 1404, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x2440c80ULL }, // MVE_VMLSDAVaxs32 |
| 9052 | { 1403, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x1440c80ULL }, // MVE_VMLSDAVaxs16 |
| 9053 | { 1402, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x540c80ULL }, // MVE_VMLSDAVas8 |
| 9054 | { 1401, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x2540c80ULL }, // MVE_VMLSDAVas32 |
| 9055 | { 1400, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x1540c80ULL }, // MVE_VMLSDAVas16 |
| 9056 | { 1399, 7, 1, 4, 1312, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x140c80ULL }, // MVE_VMLA_qr_i8 |
| 9057 | { 1398, 7, 1, 4, 1312, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x2140c80ULL }, // MVE_VMLA_qr_i32 |
| 9058 | { 1397, 7, 1, 4, 1312, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x1140c80ULL }, // MVE_VMLA_qr_i16 |
| 9059 | { 1396, 7, 1, 4, 1312, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x140c80ULL }, // MVE_VMLAS_qr_i8 |
| 9060 | { 1395, 7, 1, 4, 1312, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x2140c80ULL }, // MVE_VMLAS_qr_i32 |
| 9061 | { 1394, 7, 1, 4, 1312, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x1140c80ULL }, // MVE_VMLAS_qr_i16 |
| 9062 | { 1393, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2440c80ULL }, // MVE_VMLALDAVxs32 |
| 9063 | { 1392, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x1440c80ULL }, // MVE_VMLALDAVxs16 |
| 9064 | { 1391, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2540c80ULL }, // MVE_VMLALDAVu32 |
| 9065 | { 1390, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x1540c80ULL }, // MVE_VMLALDAVu16 |
| 9066 | { 1389, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x2540c80ULL }, // MVE_VMLALDAVs32 |
| 9067 | { 1388, 7, 2, 4, 1196, 0, 0, ARMOpInfoBase + 1360, 0, 0, 0x1540c80ULL }, // MVE_VMLALDAVs16 |
| 9068 | { 1387, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2440c80ULL }, // MVE_VMLALDAVaxs32 |
| 9069 | { 1386, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x1440c80ULL }, // MVE_VMLALDAVaxs16 |
| 9070 | { 1385, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2540c80ULL }, // MVE_VMLALDAVau32 |
| 9071 | { 1384, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x1540c80ULL }, // MVE_VMLALDAVau16 |
| 9072 | { 1383, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x2540c80ULL }, // MVE_VMLALDAVas32 |
| 9073 | { 1382, 9, 2, 4, 1315, 0, 0, ARMOpInfoBase + 1351, 0, 0, 0x1540c80ULL }, // MVE_VMLALDAVas16 |
| 9074 | { 1381, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x440c80ULL }, // MVE_VMLADAVxs8 |
| 9075 | { 1380, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x2440c80ULL }, // MVE_VMLADAVxs32 |
| 9076 | { 1379, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x1440c80ULL }, // MVE_VMLADAVxs16 |
| 9077 | { 1378, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x540c80ULL }, // MVE_VMLADAVu8 |
| 9078 | { 1377, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x2540c80ULL }, // MVE_VMLADAVu32 |
| 9079 | { 1376, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x1540c80ULL }, // MVE_VMLADAVu16 |
| 9080 | { 1375, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x540c80ULL }, // MVE_VMLADAVs8 |
| 9081 | { 1374, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x2540c80ULL }, // MVE_VMLADAVs32 |
| 9082 | { 1373, 6, 1, 4, 1195, 0, 0, ARMOpInfoBase + 1345, 0, 0, 0x1540c80ULL }, // MVE_VMLADAVs16 |
| 9083 | { 1372, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x440c80ULL }, // MVE_VMLADAVaxs8 |
| 9084 | { 1371, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x2440c80ULL }, // MVE_VMLADAVaxs32 |
| 9085 | { 1370, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x1440c80ULL }, // MVE_VMLADAVaxs16 |
| 9086 | { 1369, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x540c80ULL }, // MVE_VMLADAVau8 |
| 9087 | { 1368, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x2540c80ULL }, // MVE_VMLADAVau32 |
| 9088 | { 1367, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x1540c80ULL }, // MVE_VMLADAVau16 |
| 9089 | { 1366, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x540c80ULL }, // MVE_VMLADAVas8 |
| 9090 | { 1365, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x2540c80ULL }, // MVE_VMLADAVas32 |
| 9091 | { 1364, 7, 1, 4, 1316, 0, 0, ARMOpInfoBase + 1338, 0, 0, 0x1540c80ULL }, // MVE_VMLADAVas16 |
| 9092 | { 1363, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VMINu8 |
| 9093 | { 1362, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMINu32 |
| 9094 | { 1361, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMINu16 |
| 9095 | { 1360, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VMINs8 |
| 9096 | { 1359, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMINs32 |
| 9097 | { 1358, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMINs16 |
| 9098 | { 1357, 6, 1, 4, 1140, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x440c80ULL }, // MVE_VMINVu8 |
| 9099 | { 1356, 6, 1, 4, 1142, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMINVu32 |
| 9100 | { 1355, 6, 1, 4, 1141, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMINVu16 |
| 9101 | { 1354, 6, 1, 4, 1140, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x440c80ULL }, // MVE_VMINVs8 |
| 9102 | { 1353, 6, 1, 4, 1142, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMINVs32 |
| 9103 | { 1352, 6, 1, 4, 1141, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMINVs16 |
| 9104 | { 1351, 7, 1, 4, 1307, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMINNMf32 |
| 9105 | { 1350, 7, 1, 4, 1307, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMINNMf16 |
| 9106 | { 1349, 6, 1, 4, 1187, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMINNMVf32 |
| 9107 | { 1348, 6, 1, 4, 1187, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMINNMVf16 |
| 9108 | { 1347, 6, 1, 4, 1307, 0, 0, ARMOpInfoBase + 1223, 0, 0|(1ULL<<MCID::Commutable), 0x2140c80ULL }, // MVE_VMINNMAf32 |
| 9109 | { 1346, 6, 1, 4, 1307, 0, 0, ARMOpInfoBase + 1223, 0, 0|(1ULL<<MCID::Commutable), 0x1140c80ULL }, // MVE_VMINNMAf16 |
| 9110 | { 1345, 6, 1, 4, 1187, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMINNMAVf32 |
| 9111 | { 1344, 6, 1, 4, 1187, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMINNMAVf16 |
| 9112 | { 1343, 6, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x140c80ULL }, // MVE_VMINAs8 |
| 9113 | { 1342, 6, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2140c80ULL }, // MVE_VMINAs32 |
| 9114 | { 1341, 6, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1140c80ULL }, // MVE_VMINAs16 |
| 9115 | { 1340, 6, 1, 4, 1140, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x440c80ULL }, // MVE_VMINAVs8 |
| 9116 | { 1339, 6, 1, 4, 1142, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMINAVs32 |
| 9117 | { 1338, 6, 1, 4, 1141, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMINAVs16 |
| 9118 | { 1337, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VMAXu8 |
| 9119 | { 1336, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMAXu32 |
| 9120 | { 1335, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMAXu16 |
| 9121 | { 1334, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VMAXs8 |
| 9122 | { 1333, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMAXs32 |
| 9123 | { 1332, 7, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMAXs16 |
| 9124 | { 1331, 6, 1, 4, 1140, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x440c80ULL }, // MVE_VMAXVu8 |
| 9125 | { 1330, 6, 1, 4, 1142, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMAXVu32 |
| 9126 | { 1329, 6, 1, 4, 1141, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMAXVu16 |
| 9127 | { 1328, 6, 1, 4, 1140, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x440c80ULL }, // MVE_VMAXVs8 |
| 9128 | { 1327, 6, 1, 4, 1142, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMAXVs32 |
| 9129 | { 1326, 6, 1, 4, 1141, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMAXVs16 |
| 9130 | { 1325, 7, 1, 4, 1307, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VMAXNMf32 |
| 9131 | { 1324, 7, 1, 4, 1307, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VMAXNMf16 |
| 9132 | { 1323, 6, 1, 4, 1187, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMAXNMVf32 |
| 9133 | { 1322, 6, 1, 4, 1187, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMAXNMVf16 |
| 9134 | { 1321, 6, 1, 4, 1307, 0, 0, ARMOpInfoBase + 1223, 0, 0|(1ULL<<MCID::Commutable), 0x2140c80ULL }, // MVE_VMAXNMAf32 |
| 9135 | { 1320, 6, 1, 4, 1307, 0, 0, ARMOpInfoBase + 1223, 0, 0|(1ULL<<MCID::Commutable), 0x1140c80ULL }, // MVE_VMAXNMAf16 |
| 9136 | { 1319, 6, 1, 4, 1187, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMAXNMAVf32 |
| 9137 | { 1318, 6, 1, 4, 1187, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMAXNMAVf16 |
| 9138 | { 1317, 6, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x140c80ULL }, // MVE_VMAXAs8 |
| 9139 | { 1316, 6, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2140c80ULL }, // MVE_VMAXAs32 |
| 9140 | { 1315, 6, 1, 4, 1139, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x1140c80ULL }, // MVE_VMAXAs16 |
| 9141 | { 1314, 6, 1, 4, 1140, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x440c80ULL }, // MVE_VMAXAVs8 |
| 9142 | { 1313, 6, 1, 4, 1142, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x2440c80ULL }, // MVE_VMAXAVs32 |
| 9143 | { 1312, 6, 1, 4, 1141, 0, 0, ARMOpInfoBase + 1332, 0, 0, 0x1440c80ULL }, // MVE_VMAXAVs16 |
| 9144 | { 1311, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRWU32_rq_u |
| 9145 | { 1310, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRWU32_rq |
| 9146 | { 1309, 7, 2, 4, 1115, 0, 0, ARMOpInfoBase + 1325, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRWU32_qi_pre |
| 9147 | { 1308, 6, 1, 4, 1114, 0, 0, ARMOpInfoBase + 1319, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRWU32_qi |
| 9148 | { 1307, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb5ULL }, // MVE_VLDRWU32_pre |
| 9149 | { 1306, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd5ULL }, // MVE_VLDRWU32_post |
| 9150 | { 1305, 6, 1, 4, 1111, 0, 0, ARMOpInfoBase + 1306, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c95ULL }, // MVE_VLDRWU32 |
| 9151 | { 1304, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRHU32_rq_u |
| 9152 | { 1303, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRHU32_rq |
| 9153 | { 1302, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb6ULL }, // MVE_VLDRHU32_pre |
| 9154 | { 1301, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd6ULL }, // MVE_VLDRHU32_post |
| 9155 | { 1300, 6, 1, 4, 1111, 0, 0, ARMOpInfoBase + 1287, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c96ULL }, // MVE_VLDRHU32 |
| 9156 | { 1299, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLDRHU16_rq_u |
| 9157 | { 1298, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLDRHU16_rq |
| 9158 | { 1297, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayLoad), 0x1140cb6ULL }, // MVE_VLDRHU16_pre |
| 9159 | { 1296, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayLoad), 0x1140cd6ULL }, // MVE_VLDRHU16_post |
| 9160 | { 1295, 6, 1, 4, 1111, 0, 0, ARMOpInfoBase + 1306, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c96ULL }, // MVE_VLDRHU16 |
| 9161 | { 1294, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRHS32_rq_u |
| 9162 | { 1293, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRHS32_rq |
| 9163 | { 1292, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb6ULL }, // MVE_VLDRHS32_pre |
| 9164 | { 1291, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd6ULL }, // MVE_VLDRHS32_post |
| 9165 | { 1290, 6, 1, 4, 1111, 0, 0, ARMOpInfoBase + 1287, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c96ULL }, // MVE_VLDRHS32 |
| 9166 | { 1289, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // MVE_VLDRDU64_rq_u |
| 9167 | { 1288, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // MVE_VLDRDU64_rq |
| 9168 | { 1287, 7, 2, 4, 1115, 0, 0, ARMOpInfoBase + 1325, 0, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // MVE_VLDRDU64_qi_pre |
| 9169 | { 1286, 6, 1, 4, 1114, 0, 0, ARMOpInfoBase + 1319, 0, 0|(1ULL<<MCID::MayLoad), 0x3140c80ULL }, // MVE_VLDRDU64_qi |
| 9170 | { 1285, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLDRBU8_rq |
| 9171 | { 1284, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayLoad), 0x140cb7ULL }, // MVE_VLDRBU8_pre |
| 9172 | { 1283, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1312, 0, 0|(1ULL<<MCID::MayLoad), 0x140cd7ULL }, // MVE_VLDRBU8_post |
| 9173 | { 1282, 6, 1, 4, 1111, 0, 0, ARMOpInfoBase + 1306, 0, 0|(1ULL<<MCID::MayLoad), 0x140c97ULL }, // MVE_VLDRBU8 |
| 9174 | { 1281, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRBU32_rq |
| 9175 | { 1280, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb7ULL }, // MVE_VLDRBU32_pre |
| 9176 | { 1279, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd7ULL }, // MVE_VLDRBU32_post |
| 9177 | { 1278, 6, 1, 4, 1111, 0, 0, ARMOpInfoBase + 1287, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c97ULL }, // MVE_VLDRBU32 |
| 9178 | { 1277, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLDRBU16_rq |
| 9179 | { 1276, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x1140cb7ULL }, // MVE_VLDRBU16_pre |
| 9180 | { 1275, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x1140cd7ULL }, // MVE_VLDRBU16_post |
| 9181 | { 1274, 6, 1, 4, 1111, 0, 0, ARMOpInfoBase + 1287, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c97ULL }, // MVE_VLDRBU16 |
| 9182 | { 1273, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLDRBS32_rq |
| 9183 | { 1272, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cb7ULL }, // MVE_VLDRBS32_pre |
| 9184 | { 1271, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x2140cd7ULL }, // MVE_VLDRBS32_post |
| 9185 | { 1270, 6, 1, 4, 1111, 0, 0, ARMOpInfoBase + 1287, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c97ULL }, // MVE_VLDRBS32 |
| 9186 | { 1269, 6, 1, 4, 1113, 0, 0, ARMOpInfoBase + 1300, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLDRBS16_rq |
| 9187 | { 1268, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x1140cb7ULL }, // MVE_VLDRBS16_pre |
| 9188 | { 1267, 7, 2, 4, 1112, 0, 0, ARMOpInfoBase + 1293, 0, 0|(1ULL<<MCID::MayLoad), 0x1140cd7ULL }, // MVE_VLDRBS16_post |
| 9189 | { 1266, 6, 1, 4, 1111, 0, 0, ARMOpInfoBase + 1287, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c97ULL }, // MVE_VLDRBS16 |
| 9190 | { 1265, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD43_8_wb |
| 9191 | { 1264, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD43_8 |
| 9192 | { 1263, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD43_32_wb |
| 9193 | { 1262, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD43_32 |
| 9194 | { 1261, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD43_16_wb |
| 9195 | { 1260, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD43_16 |
| 9196 | { 1259, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD42_8_wb |
| 9197 | { 1258, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD42_8 |
| 9198 | { 1257, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD42_32_wb |
| 9199 | { 1256, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD42_32 |
| 9200 | { 1255, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD42_16_wb |
| 9201 | { 1254, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD42_16 |
| 9202 | { 1253, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD41_8_wb |
| 9203 | { 1252, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD41_8 |
| 9204 | { 1251, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD41_32_wb |
| 9205 | { 1250, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD41_32 |
| 9206 | { 1249, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD41_16_wb |
| 9207 | { 1248, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD41_16 |
| 9208 | { 1247, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD40_8_wb |
| 9209 | { 1246, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD40_8 |
| 9210 | { 1245, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD40_32_wb |
| 9211 | { 1244, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD40_32 |
| 9212 | { 1243, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1283, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD40_16_wb |
| 9213 | { 1242, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1280, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD40_16 |
| 9214 | { 1241, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1276, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD21_8_wb |
| 9215 | { 1240, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1273, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD21_8 |
| 9216 | { 1239, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1276, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD21_32_wb |
| 9217 | { 1238, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1273, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD21_32 |
| 9218 | { 1237, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1276, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD21_16_wb |
| 9219 | { 1236, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1273, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD21_16 |
| 9220 | { 1235, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1276, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD20_8_wb |
| 9221 | { 1234, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1273, 0, 0|(1ULL<<MCID::MayLoad), 0x140c80ULL }, // MVE_VLD20_8 |
| 9222 | { 1233, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1276, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD20_32_wb |
| 9223 | { 1232, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1273, 0, 0|(1ULL<<MCID::MayLoad), 0x2140c80ULL }, // MVE_VLD20_32 |
| 9224 | { 1231, 4, 2, 4, 1117, 0, 0, ARMOpInfoBase + 1276, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD20_16_wb |
| 9225 | { 1230, 3, 1, 4, 1116, 0, 0, ARMOpInfoBase + 1273, 0, 0|(1ULL<<MCID::MayLoad), 0x1140c80ULL }, // MVE_VLD20_16 |
| 9226 | { 1229, 9, 2, 4, 1303, 0, 0, ARMOpInfoBase + 1250, 0, 0, 0x140c80ULL }, // MVE_VIWDUPu8 |
| 9227 | { 1228, 9, 2, 4, 1303, 0, 0, ARMOpInfoBase + 1250, 0, 0, 0x2140c80ULL }, // MVE_VIWDUPu32 |
| 9228 | { 1227, 9, 2, 4, 1303, 0, 0, ARMOpInfoBase + 1250, 0, 0, 0x1140c80ULL }, // MVE_VIWDUPu16 |
| 9229 | { 1226, 8, 2, 4, 1304, 0, 0, ARMOpInfoBase + 1236, 0, 0, 0x140c80ULL }, // MVE_VIDUPu8 |
| 9230 | { 1225, 8, 2, 4, 1304, 0, 0, ARMOpInfoBase + 1236, 0, 0, 0x2140c80ULL }, // MVE_VIDUPu32 |
| 9231 | { 1224, 8, 2, 4, 1304, 0, 0, ARMOpInfoBase + 1236, 0, 0, 0x1140c80ULL }, // MVE_VIDUPu16 |
| 9232 | { 1223, 7, 1, 4, 1138, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VHSUBu8 |
| 9233 | { 1222, 7, 1, 4, 1138, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VHSUBu32 |
| 9234 | { 1221, 7, 1, 4, 1138, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VHSUBu16 |
| 9235 | { 1220, 7, 1, 4, 1138, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VHSUBs8 |
| 9236 | { 1219, 7, 1, 4, 1138, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VHSUBs32 |
| 9237 | { 1218, 7, 1, 4, 1138, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VHSUBs16 |
| 9238 | { 1217, 7, 1, 4, 1296, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VHSUB_qr_u8 |
| 9239 | { 1216, 7, 1, 4, 1296, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VHSUB_qr_u32 |
| 9240 | { 1215, 7, 1, 4, 1296, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VHSUB_qr_u16 |
| 9241 | { 1214, 7, 1, 4, 1296, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VHSUB_qr_s8 |
| 9242 | { 1213, 7, 1, 4, 1296, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VHSUB_qr_s32 |
| 9243 | { 1212, 7, 1, 4, 1296, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VHSUB_qr_s16 |
| 9244 | { 1211, 8, 1, 4, 1137, 0, 0, ARMOpInfoBase + 1172, 0, 0, 0x40c80ULL }, // MVE_VHCADDs8 |
| 9245 | { 1210, 8, 1, 4, 1137, 0, 0, ARMOpInfoBase + 1180, 0, 0, 0x2040c80ULL }, // MVE_VHCADDs32 |
| 9246 | { 1209, 8, 1, 4, 1137, 0, 0, ARMOpInfoBase + 1172, 0, 0, 0x1040c80ULL }, // MVE_VHCADDs16 |
| 9247 | { 1208, 7, 1, 4, 1136, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VHADDu8 |
| 9248 | { 1207, 7, 1, 4, 1136, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VHADDu32 |
| 9249 | { 1206, 7, 1, 4, 1136, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VHADDu16 |
| 9250 | { 1205, 7, 1, 4, 1136, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VHADDs8 |
| 9251 | { 1204, 7, 1, 4, 1136, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VHADDs32 |
| 9252 | { 1203, 7, 1, 4, 1136, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VHADDs16 |
| 9253 | { 1202, 7, 1, 4, 1295, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VHADD_qr_u8 |
| 9254 | { 1201, 7, 1, 4, 1295, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VHADD_qr_u32 |
| 9255 | { 1200, 7, 1, 4, 1295, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VHADD_qr_u16 |
| 9256 | { 1199, 7, 1, 4, 1295, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VHADD_qr_s8 |
| 9257 | { 1198, 7, 1, 4, 1295, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VHADD_qr_s32 |
| 9258 | { 1197, 7, 1, 4, 1295, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VHADD_qr_s16 |
| 9259 | { 1196, 7, 1, 4, 1186, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x2140c80ULL }, // MVE_VFMSf32 |
| 9260 | { 1195, 7, 1, 4, 1186, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1140c80ULL }, // MVE_VFMSf16 |
| 9261 | { 1194, 7, 1, 4, 1186, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x2140c80ULL }, // MVE_VFMAf32 |
| 9262 | { 1193, 7, 1, 4, 1186, 0, 0, ARMOpInfoBase + 1266, 0, 0, 0x1140c80ULL }, // MVE_VFMAf16 |
| 9263 | { 1192, 7, 1, 4, 1319, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x2140c80ULL }, // MVE_VFMA_qr_f32 |
| 9264 | { 1191, 7, 1, 4, 1319, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x1140c80ULL }, // MVE_VFMA_qr_f16 |
| 9265 | { 1190, 7, 1, 4, 1319, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x2140c80ULL }, // MVE_VFMA_qr_Sf32 |
| 9266 | { 1189, 7, 1, 4, 1319, 0, 0, ARMOpInfoBase + 1259, 0, 0, 0x1140c80ULL }, // MVE_VFMA_qr_Sf16 |
| 9267 | { 1188, 7, 1, 4, 1135, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VEOR |
| 9268 | { 1187, 9, 2, 4, 1303, 0, 0, ARMOpInfoBase + 1250, 0, 0, 0x140c80ULL }, // MVE_VDWDUPu8 |
| 9269 | { 1186, 9, 2, 4, 1303, 0, 0, ARMOpInfoBase + 1250, 0, 0, 0x2140c80ULL }, // MVE_VDWDUPu32 |
| 9270 | { 1185, 9, 2, 4, 1303, 0, 0, ARMOpInfoBase + 1250, 0, 0, 0x1140c80ULL }, // MVE_VDWDUPu16 |
| 9271 | { 1184, 6, 1, 4, 1134, 0, 0, ARMOpInfoBase + 1244, 0, 0, 0x140c80ULL }, // MVE_VDUP8 |
| 9272 | { 1183, 6, 1, 4, 1134, 0, 0, ARMOpInfoBase + 1244, 0, 0, 0x2140c80ULL }, // MVE_VDUP32 |
| 9273 | { 1182, 6, 1, 4, 1134, 0, 0, ARMOpInfoBase + 1244, 0, 0, 0x1140c80ULL }, // MVE_VDUP16 |
| 9274 | { 1181, 8, 2, 4, 1304, 0, 0, ARMOpInfoBase + 1236, 0, 0, 0x140c80ULL }, // MVE_VDDUPu8 |
| 9275 | { 1180, 8, 2, 4, 1304, 0, 0, ARMOpInfoBase + 1236, 0, 0, 0x2140c80ULL }, // MVE_VDDUPu32 |
| 9276 | { 1179, 8, 2, 4, 1304, 0, 0, ARMOpInfoBase + 1236, 0, 0, 0x1140c80ULL }, // MVE_VDDUPu16 |
| 9277 | { 1178, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTu32f32z |
| 9278 | { 1177, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTu32f32p |
| 9279 | { 1176, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTu32f32n |
| 9280 | { 1175, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTu32f32m |
| 9281 | { 1174, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTu32f32a |
| 9282 | { 1173, 7, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VCVTu32f32_fix |
| 9283 | { 1172, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTu16f16z |
| 9284 | { 1171, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTu16f16p |
| 9285 | { 1170, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTu16f16n |
| 9286 | { 1169, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTu16f16m |
| 9287 | { 1168, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTu16f16a |
| 9288 | { 1167, 7, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VCVTu16f16_fix |
| 9289 | { 1166, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTs32f32z |
| 9290 | { 1165, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTs32f32p |
| 9291 | { 1164, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTs32f32n |
| 9292 | { 1163, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTs32f32m |
| 9293 | { 1162, 6, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTs32f32a |
| 9294 | { 1161, 7, 1, 4, 1183, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VCVTs32f32_fix |
| 9295 | { 1160, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTs16f16z |
| 9296 | { 1159, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTs16f16p |
| 9297 | { 1158, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTs16f16n |
| 9298 | { 1157, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTs16f16m |
| 9299 | { 1156, 6, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTs16f16a |
| 9300 | { 1155, 7, 1, 4, 1182, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VCVTs16f16_fix |
| 9301 | { 1154, 6, 1, 4, 1181, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTf32u32n |
| 9302 | { 1153, 7, 1, 4, 1181, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VCVTf32u32_fix |
| 9303 | { 1152, 6, 1, 4, 1181, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCVTf32s32n |
| 9304 | { 1151, 7, 1, 4, 1181, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x2140c80ULL }, // MVE_VCVTf32s32_fix |
| 9305 | { 1150, 6, 1, 4, 1185, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2240c80ULL }, // MVE_VCVTf32f16th |
| 9306 | { 1149, 6, 1, 4, 1185, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2240c80ULL }, // MVE_VCVTf32f16bh |
| 9307 | { 1148, 6, 1, 4, 1180, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTf16u16n |
| 9308 | { 1147, 7, 1, 4, 1180, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VCVTf16u16_fix |
| 9309 | { 1146, 6, 1, 4, 1180, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCVTf16s16n |
| 9310 | { 1145, 7, 1, 4, 1180, 0, 0, ARMOpInfoBase + 1229, 0, 0, 0x1140c80ULL }, // MVE_VCVTf16s16_fix |
| 9311 | { 1144, 6, 1, 4, 1184, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2240c80ULL }, // MVE_VCVTf16f32th |
| 9312 | { 1143, 6, 1, 4, 1184, 0, 0, ARMOpInfoBase + 1223, 0, 0, 0x2240c80ULL }, // MVE_VCVTf16f32bh |
| 9313 | { 1142, 5, 1, 4, 1202, 0, 0, ARMOpInfoBase + 1218, 0, 0|(1ULL<<MCID::Rematerializable), 0x140c80ULL }, // MVE_VCTP8 |
| 9314 | { 1141, 5, 1, 4, 1202, 0, 0, ARMOpInfoBase + 1218, 0, 0|(1ULL<<MCID::Rematerializable), 0x3140c80ULL }, // MVE_VCTP64 |
| 9315 | { 1140, 5, 1, 4, 1202, 0, 0, ARMOpInfoBase + 1218, 0, 0|(1ULL<<MCID::Rematerializable), 0x2140c80ULL }, // MVE_VCTP32 |
| 9316 | { 1139, 5, 1, 4, 1202, 0, 0, ARMOpInfoBase + 1218, 0, 0|(1ULL<<MCID::Rematerializable), 0x1140c80ULL }, // MVE_VCTP16 |
| 9317 | { 1138, 8, 1, 4, 1177, 0, 0, ARMOpInfoBase + 1180, 0, 0, 0x2040c80ULL }, // MVE_VCMULf32 |
| 9318 | { 1137, 8, 1, 4, 1177, 0, 0, ARMOpInfoBase + 1172, 0, 0, 0x1040c80ULL }, // MVE_VCMULf16 |
| 9319 | { 1136, 7, 1, 4, 1322, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x140c80ULL }, // MVE_VCMPu8r |
| 9320 | { 1135, 7, 1, 4, 1178, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x140c80ULL }, // MVE_VCMPu8 |
| 9321 | { 1134, 7, 1, 4, 1322, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x2140c80ULL }, // MVE_VCMPu32r |
| 9322 | { 1133, 7, 1, 4, 1178, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x2140c80ULL }, // MVE_VCMPu32 |
| 9323 | { 1132, 7, 1, 4, 1322, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x1140c80ULL }, // MVE_VCMPu16r |
| 9324 | { 1131, 7, 1, 4, 1178, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x1140c80ULL }, // MVE_VCMPu16 |
| 9325 | { 1130, 7, 1, 4, 1322, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x140c80ULL }, // MVE_VCMPs8r |
| 9326 | { 1129, 7, 1, 4, 1178, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x140c80ULL }, // MVE_VCMPs8 |
| 9327 | { 1128, 7, 1, 4, 1322, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x2140c80ULL }, // MVE_VCMPs32r |
| 9328 | { 1127, 7, 1, 4, 1178, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x2140c80ULL }, // MVE_VCMPs32 |
| 9329 | { 1126, 7, 1, 4, 1322, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x1140c80ULL }, // MVE_VCMPs16r |
| 9330 | { 1125, 7, 1, 4, 1178, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x1140c80ULL }, // MVE_VCMPs16 |
| 9331 | { 1124, 7, 1, 4, 1322, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x140c80ULL }, // MVE_VCMPi8r |
| 9332 | { 1123, 7, 1, 4, 1178, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x140c80ULL }, // MVE_VCMPi8 |
| 9333 | { 1122, 7, 1, 4, 1322, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x2140c80ULL }, // MVE_VCMPi32r |
| 9334 | { 1121, 7, 1, 4, 1178, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x2140c80ULL }, // MVE_VCMPi32 |
| 9335 | { 1120, 7, 1, 4, 1322, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x1140c80ULL }, // MVE_VCMPi16r |
| 9336 | { 1119, 7, 1, 4, 1178, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x1140c80ULL }, // MVE_VCMPi16 |
| 9337 | { 1118, 7, 1, 4, 1323, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x2140c80ULL }, // MVE_VCMPf32r |
| 9338 | { 1117, 7, 1, 4, 1179, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x2140c80ULL }, // MVE_VCMPf32 |
| 9339 | { 1116, 7, 1, 4, 1323, 0, 0, ARMOpInfoBase + 1211, 0, 0, 0x1140c80ULL }, // MVE_VCMPf16r |
| 9340 | { 1115, 7, 1, 4, 1179, 0, 0, ARMOpInfoBase + 1204, 0, 0, 0x1140c80ULL }, // MVE_VCMPf16 |
| 9341 | { 1114, 8, 1, 4, 1176, 0, 0, ARMOpInfoBase + 1196, 0, 0, 0x2040c80ULL }, // MVE_VCMLAf32 |
| 9342 | { 1113, 8, 1, 4, 1176, 0, 0, ARMOpInfoBase + 1188, 0, 0, 0x1040c80ULL }, // MVE_VCMLAf16 |
| 9343 | { 1112, 6, 1, 4, 1133, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x140c80ULL }, // MVE_VCLZs8 |
| 9344 | { 1111, 6, 1, 4, 1133, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCLZs32 |
| 9345 | { 1110, 6, 1, 4, 1133, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCLZs16 |
| 9346 | { 1109, 6, 1, 4, 1132, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x140c80ULL }, // MVE_VCLSs8 |
| 9347 | { 1108, 6, 1, 4, 1132, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VCLSs32 |
| 9348 | { 1107, 6, 1, 4, 1132, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VCLSs16 |
| 9349 | { 1106, 8, 1, 4, 1131, 0, 0, ARMOpInfoBase + 1172, 0, 0, 0x40c80ULL }, // MVE_VCADDi8 |
| 9350 | { 1105, 8, 1, 4, 1131, 0, 0, ARMOpInfoBase + 1180, 0, 0, 0x2040c80ULL }, // MVE_VCADDi32 |
| 9351 | { 1104, 8, 1, 4, 1131, 0, 0, ARMOpInfoBase + 1172, 0, 0, 0x1040c80ULL }, // MVE_VCADDi16 |
| 9352 | { 1103, 8, 1, 4, 1175, 0, 0, ARMOpInfoBase + 1180, 0, 0, 0x2040c80ULL }, // MVE_VCADDf32 |
| 9353 | { 1102, 8, 1, 4, 1175, 0, 0, ARMOpInfoBase + 1172, 0, 0, 0x1040c80ULL }, // MVE_VCADDf16 |
| 9354 | { 1101, 7, 1, 4, 1130, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VBRSR8 |
| 9355 | { 1100, 7, 1, 4, 1130, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VBRSR32 |
| 9356 | { 1099, 7, 1, 4, 1130, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VBRSR16 |
| 9357 | { 1098, 6, 1, 4, 1129, 0, 0, ARMOpInfoBase + 1166, 0, 0, 0x2140c80ULL }, // MVE_VBICimmi32 |
| 9358 | { 1097, 6, 1, 4, 1129, 0, 0, ARMOpInfoBase + 1166, 0, 0, 0x1140c80ULL }, // MVE_VBICimmi16 |
| 9359 | { 1096, 7, 1, 4, 1129, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VBIC |
| 9360 | { 1095, 7, 1, 4, 1128, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VAND |
| 9361 | { 1094, 7, 1, 4, 1127, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VADDi8 |
| 9362 | { 1093, 7, 1, 4, 1127, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VADDi32 |
| 9363 | { 1092, 7, 1, 4, 1127, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VADDi16 |
| 9364 | { 1091, 7, 1, 4, 1171, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VADDf32 |
| 9365 | { 1090, 7, 1, 4, 1171, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VADDf16 |
| 9366 | { 1089, 7, 1, 4, 1294, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x140c80ULL }, // MVE_VADD_qr_i8 |
| 9367 | { 1088, 7, 1, 4, 1294, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VADD_qr_i32 |
| 9368 | { 1087, 7, 1, 4, 1294, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VADD_qr_i16 |
| 9369 | { 1086, 7, 1, 4, 1172, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x2140c80ULL }, // MVE_VADD_qr_f32 |
| 9370 | { 1085, 7, 1, 4, 1172, 0, 0, ARMOpInfoBase + 1159, 0, 0, 0x1140c80ULL }, // MVE_VADD_qr_f16 |
| 9371 | { 1084, 5, 1, 4, 1174, 0, 0, ARMOpInfoBase + 1154, 0, 0, 0x540c80ULL }, // MVE_VADDVu8no_acc |
| 9372 | { 1083, 6, 1, 4, 1309, 0, 0, ARMOpInfoBase + 1148, 0, 0, 0x540c80ULL }, // MVE_VADDVu8acc |
| 9373 | { 1082, 5, 1, 4, 1174, 0, 0, ARMOpInfoBase + 1154, 0, 0, 0x2540c80ULL }, // MVE_VADDVu32no_acc |
| 9374 | { 1081, 6, 1, 4, 1309, 0, 0, ARMOpInfoBase + 1148, 0, 0, 0x2540c80ULL }, // MVE_VADDVu32acc |
| 9375 | { 1080, 5, 1, 4, 1174, 0, 0, ARMOpInfoBase + 1154, 0, 0, 0x1540c80ULL }, // MVE_VADDVu16no_acc |
| 9376 | { 1079, 6, 1, 4, 1309, 0, 0, ARMOpInfoBase + 1148, 0, 0, 0x1540c80ULL }, // MVE_VADDVu16acc |
| 9377 | { 1078, 5, 1, 4, 1174, 0, 0, ARMOpInfoBase + 1154, 0, 0, 0x540c80ULL }, // MVE_VADDVs8no_acc |
| 9378 | { 1077, 6, 1, 4, 1309, 0, 0, ARMOpInfoBase + 1148, 0, 0, 0x540c80ULL }, // MVE_VADDVs8acc |
| 9379 | { 1076, 5, 1, 4, 1174, 0, 0, ARMOpInfoBase + 1154, 0, 0, 0x2540c80ULL }, // MVE_VADDVs32no_acc |
| 9380 | { 1075, 6, 1, 4, 1309, 0, 0, ARMOpInfoBase + 1148, 0, 0, 0x2540c80ULL }, // MVE_VADDVs32acc |
| 9381 | { 1074, 5, 1, 4, 1174, 0, 0, ARMOpInfoBase + 1154, 0, 0, 0x1540c80ULL }, // MVE_VADDVs16no_acc |
| 9382 | { 1073, 6, 1, 4, 1309, 0, 0, ARMOpInfoBase + 1148, 0, 0, 0x1540c80ULL }, // MVE_VADDVs16acc |
| 9383 | { 1072, 6, 2, 4, 1173, 0, 0, ARMOpInfoBase + 1142, 0, 0, 0x2440c80ULL }, // MVE_VADDLVu32no_acc |
| 9384 | { 1071, 8, 2, 4, 1308, 0, 0, ARMOpInfoBase + 1134, 0, 0, 0x2440c80ULL }, // MVE_VADDLVu32acc |
| 9385 | { 1070, 6, 2, 4, 1173, 0, 0, ARMOpInfoBase + 1142, 0, 0, 0x2440c80ULL }, // MVE_VADDLVs32no_acc |
| 9386 | { 1069, 8, 2, 4, 1308, 0, 0, ARMOpInfoBase + 1134, 0, 0, 0x2440c80ULL }, // MVE_VADDLVs32acc |
| 9387 | { 1068, 8, 2, 4, 1126, 0, 0, ARMOpInfoBase + 1126, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // MVE_VADCI |
| 9388 | { 1067, 9, 2, 4, 1293, 0, 0, ARMOpInfoBase + 1117, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040c80ULL }, // MVE_VADC |
| 9389 | { 1066, 6, 1, 4, 1125, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x140c80ULL }, // MVE_VABSs8 |
| 9390 | { 1065, 6, 1, 4, 1125, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VABSs32 |
| 9391 | { 1064, 6, 1, 4, 1125, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VABSs16 |
| 9392 | { 1063, 6, 1, 4, 1170, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x2140c80ULL }, // MVE_VABSf32 |
| 9393 | { 1062, 6, 1, 4, 1170, 0, 0, ARMOpInfoBase + 1111, 0, 0, 0x1140c80ULL }, // MVE_VABSf16 |
| 9394 | { 1061, 7, 1, 4, 1124, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VABDu8 |
| 9395 | { 1060, 7, 1, 4, 1124, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VABDu32 |
| 9396 | { 1059, 7, 1, 4, 1124, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VABDu16 |
| 9397 | { 1058, 7, 1, 4, 1124, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x140c80ULL }, // MVE_VABDs8 |
| 9398 | { 1057, 7, 1, 4, 1124, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VABDs32 |
| 9399 | { 1056, 7, 1, 4, 1124, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VABDs16 |
| 9400 | { 1055, 7, 1, 4, 1169, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x2140c80ULL }, // MVE_VABDf32 |
| 9401 | { 1054, 7, 1, 4, 1169, 0, 0, ARMOpInfoBase + 1104, 0, 0, 0x1140c80ULL }, // MVE_VABDf16 |
| 9402 | { 1053, 7, 1, 4, 1123, 0, 0, ARMOpInfoBase + 1097, 0, 0, 0x440c80ULL }, // MVE_VABAVu8 |
| 9403 | { 1052, 7, 1, 4, 1123, 0, 0, ARMOpInfoBase + 1097, 0, 0, 0x2440c80ULL }, // MVE_VABAVu32 |
| 9404 | { 1051, 7, 1, 4, 1123, 0, 0, ARMOpInfoBase + 1097, 0, 0, 0x1440c80ULL }, // MVE_VABAVu16 |
| 9405 | { 1050, 7, 1, 4, 1123, 0, 0, ARMOpInfoBase + 1097, 0, 0, 0x440c80ULL }, // MVE_VABAVs8 |
| 9406 | { 1049, 7, 1, 4, 1123, 0, 0, ARMOpInfoBase + 1097, 0, 0, 0x2440c80ULL }, // MVE_VABAVs32 |
| 9407 | { 1048, 7, 1, 4, 1123, 0, 0, ARMOpInfoBase + 1097, 0, 0, 0x1440c80ULL }, // MVE_VABAVs16 |
| 9408 | { 1047, 7, 2, 4, 1280, 0, 0, ARMOpInfoBase + 1070, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_URSHRL |
| 9409 | { 1046, 5, 1, 4, 1100, 0, 0, ARMOpInfoBase + 465, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_URSHR |
| 9410 | { 1045, 7, 2, 4, 1280, 0, 0, ARMOpInfoBase + 1070, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_UQSHLL |
| 9411 | { 1044, 5, 1, 4, 1100, 0, 0, ARMOpInfoBase + 465, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_UQSHL |
| 9412 | { 1043, 8, 2, 4, 1101, 0, 0, ARMOpInfoBase + 1089, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_UQRSHLL |
| 9413 | { 1042, 5, 1, 4, 1281, 0, 0, ARMOpInfoBase + 1084, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_UQRSHL |
| 9414 | { 1041, 7, 2, 4, 1280, 0, 0, ARMOpInfoBase + 1070, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_SRSHRL |
| 9415 | { 1040, 5, 1, 4, 1100, 0, 0, ARMOpInfoBase + 465, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_SRSHR |
| 9416 | { 1039, 7, 2, 4, 1280, 0, 0, ARMOpInfoBase + 1070, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_SQSHLL |
| 9417 | { 1038, 5, 1, 4, 1100, 0, 0, ARMOpInfoBase + 465, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_SQSHL |
| 9418 | { 1037, 8, 2, 4, 1101, 0, 0, ARMOpInfoBase + 1089, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_SQRSHRL |
| 9419 | { 1036, 5, 1, 4, 1281, 0, 0, ARMOpInfoBase + 1084, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_SQRSHR |
| 9420 | { 1035, 7, 2, 4, 1280, 0, 0, ARMOpInfoBase + 1070, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_LSRL |
| 9421 | { 1034, 7, 2, 4, 1101, 0, 0, ARMOpInfoBase + 1077, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_LSLLr |
| 9422 | { 1033, 7, 2, 4, 1280, 0, 0, ARMOpInfoBase + 1070, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_LSLLi |
| 9423 | { 1032, 3, 1, 4, 1286, 0, 0, ARMOpInfoBase + 456, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_LETP |
| 9424 | { 1031, 2, 0, 4, 1283, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_LCTP |
| 9425 | { 1030, 2, 1, 4, 1284, 0, 0, ARMOpInfoBase + 435, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_DLSTP_8 |
| 9426 | { 1029, 2, 1, 4, 1284, 0, 0, ARMOpInfoBase + 435, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_DLSTP_64 |
| 9427 | { 1028, 2, 1, 4, 1284, 0, 0, ARMOpInfoBase + 435, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_DLSTP_32 |
| 9428 | { 1027, 2, 1, 4, 1284, 0, 0, ARMOpInfoBase + 435, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // MVE_DLSTP_16 |
| 9429 | { 1026, 7, 2, 4, 1101, 0, 0, ARMOpInfoBase + 1077, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_ASRLr |
| 9430 | { 1025, 7, 2, 4, 1280, 0, 0, ARMOpInfoBase + 1070, 0, 0|(1ULL<<MCID::Predicable), 0x140c80ULL }, // MVE_ASRLi |
| 9431 | { 1024, 6, 1, 4, 335, 0, 0, ARMOpInfoBase + 184, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // MUL |
| 9432 | { 1023, 4, 0, 4, 726, 0, 1, ARMOpInfoBase + 1066, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MSRi |
| 9433 | { 1022, 4, 0, 4, 726, 0, 0, ARMOpInfoBase + 1062, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MSRbanked |
| 9434 | { 1021, 4, 0, 4, 726, 0, 1, ARMOpInfoBase + 1058, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MSR |
| 9435 | { 1020, 3, 1, 4, 725, 0, 0, ARMOpInfoBase + 1055, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MRSsys |
| 9436 | { 1019, 4, 1, 4, 725, 0, 0, ARMOpInfoBase + 440, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MRSbanked |
| 9437 | { 1018, 3, 1, 4, 725, 0, 0, ARMOpInfoBase + 1055, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MRS |
| 9438 | { 1017, 5, 2, 4, 847, 0, 0, ARMOpInfoBase + 1050, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MRRC2 |
| 9439 | { 1016, 7, 2, 4, 847, 0, 0, ARMOpInfoBase + 1043, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MRRC |
| 9440 | { 1015, 6, 1, 4, 847, 0, 0, ARMOpInfoBase + 1037, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MRC2 |
| 9441 | { 1014, 8, 1, 4, 847, 0, 0, ARMOpInfoBase + 1029, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MRC |
| 9442 | { 1013, 7, 1, 4, 687, 0, 0, ARMOpInfoBase + 1022, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL }, // MOVsr |
| 9443 | { 1012, 6, 1, 4, 325, 0, 0, ARMOpInfoBase + 1016, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL }, // MOVsi |
| 9444 | { 1011, 5, 1, 4, 865, 0, 0, ARMOpInfoBase + 1011, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL }, // MOVr_TC |
| 9445 | { 1010, 5, 1, 4, 865, 0, 0, ARMOpInfoBase + 327, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL }, // MOVr |
| 9446 | { 1009, 4, 1, 4, 864, 0, 0, ARMOpInfoBase + 244, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL }, // MOVi16 |
| 9447 | { 1008, 5, 1, 4, 864, 0, 0, ARMOpInfoBase + 1006, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL }, // MOVi |
| 9448 | { 1007, 5, 1, 4, 689, 0, 0, ARMOpInfoBase + 1001, 0, 0|(1ULL<<MCID::Predicable), 0x2201ULL }, // MOVTi16 |
| 9449 | { 1006, 2, 0, 4, 880, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL }, // MOVPCLR |
| 9450 | { 1005, 6, 1, 4, 336, 0, 0, ARMOpInfoBase + 995, 0, 0|(1ULL<<MCID::Predicable), 0x80ULL }, // MLS |
| 9451 | { 1004, 7, 1, 4, 336, 0, 0, ARMOpInfoBase + 988, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL }, // MLA |
| 9452 | { 1003, 5, 0, 4, 847, 0, 0, ARMOpInfoBase + 983, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MCRR2 |
| 9453 | { 1002, 7, 0, 4, 847, 0, 0, ARMOpInfoBase + 976, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MCRR |
| 9454 | { 1001, 6, 0, 4, 847, 0, 0, ARMOpInfoBase + 970, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MCR2 |
| 9455 | { 1000, 8, 0, 4, 847, 0, 0, ARMOpInfoBase + 962, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // MCR |
| 9456 | { 999, 6, 1, 4, 347, 0, 0, ARMOpInfoBase + 956, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL }, // LDRrs |
| 9457 | { 998, 5, 1, 4, 385, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x312ULL }, // LDRi12 |
| 9458 | { 997, 5, 1, 4, 397, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x312ULL }, // LDRcp |
| 9459 | { 996, 7, 2, 4, 910, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // LDR_PRE_REG |
| 9460 | { 995, 6, 2, 4, 906, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // LDR_PRE_IMM |
| 9461 | { 994, 7, 2, 4, 929, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // LDR_POST_REG |
| 9462 | { 993, 7, 2, 4, 405, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // LDR_POST_IMM |
| 9463 | { 992, 7, 2, 4, 404, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // LDRT_POST_REG |
| 9464 | { 991, 7, 2, 4, 921, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // LDRT_POST_IMM |
| 9465 | { 990, 7, 2, 4, 913, 0, 0, ARMOpInfoBase + 949, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL }, // LDRSH_PRE |
| 9466 | { 989, 7, 2, 4, 928, 0, 0, ARMOpInfoBase + 949, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // LDRSH_POST |
| 9467 | { 988, 7, 2, 4, 350, 0, 0, ARMOpInfoBase + 942, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // LDRSHTr |
| 9468 | { 987, 6, 2, 4, 924, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // LDRSHTi |
| 9469 | { 986, 6, 1, 4, 348, 0, 0, ARMOpInfoBase + 936, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL }, // LDRSH |
| 9470 | { 985, 7, 2, 4, 913, 0, 0, ARMOpInfoBase + 949, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL }, // LDRSB_PRE |
| 9471 | { 984, 7, 2, 4, 928, 0, 0, ARMOpInfoBase + 949, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // LDRSB_POST |
| 9472 | { 983, 7, 2, 4, 350, 0, 0, ARMOpInfoBase + 942, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // LDRSBTr |
| 9473 | { 982, 6, 2, 4, 924, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // LDRSBTi |
| 9474 | { 981, 6, 1, 4, 348, 0, 0, ARMOpInfoBase + 936, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL }, // LDRSB |
| 9475 | { 980, 7, 2, 4, 912, 0, 0, ARMOpInfoBase + 949, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL }, // LDRH_PRE |
| 9476 | { 979, 7, 2, 4, 927, 0, 0, ARMOpInfoBase + 949, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // LDRH_POST |
| 9477 | { 978, 7, 2, 4, 406, 0, 0, ARMOpInfoBase + 942, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // LDRHTr |
| 9478 | { 977, 6, 2, 4, 923, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL }, // LDRHTi |
| 9479 | { 976, 6, 1, 4, 396, 0, 0, ARMOpInfoBase + 936, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL }, // LDRH |
| 9480 | { 975, 4, 1, 4, 846, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // LDREXH |
| 9481 | { 974, 4, 1, 4, 846, 0, 0, ARMOpInfoBase + 873, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL }, // LDREXD |
| 9482 | { 973, 4, 1, 4, 846, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // LDREXB |
| 9483 | { 972, 4, 1, 4, 846, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // LDREX |
| 9484 | { 971, 8, 3, 4, 919, 0, 0, ARMOpInfoBase + 928, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x423ULL }, // LDRD_PRE |
| 9485 | { 970, 8, 3, 4, 418, 0, 0, ARMOpInfoBase + 928, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x443ULL }, // LDRD_POST |
| 9486 | { 969, 7, 2, 4, 417, 0, 0, ARMOpInfoBase + 921, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x403ULL }, // LDRD |
| 9487 | { 968, 6, 1, 4, 387, 0, 0, ARMOpInfoBase + 915, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL }, // LDRBrs |
| 9488 | { 967, 5, 1, 4, 386, 0, 0, ARMOpInfoBase + 910, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x312ULL }, // LDRBi12 |
| 9489 | { 966, 7, 2, 4, 911, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // LDRB_PRE_REG |
| 9490 | { 965, 6, 2, 4, 907, 0, 0, ARMOpInfoBase + 904, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL }, // LDRB_PRE_IMM |
| 9491 | { 964, 7, 2, 4, 930, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // LDRB_POST_REG |
| 9492 | { 963, 7, 2, 4, 403, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // LDRB_POST_IMM |
| 9493 | { 962, 7, 2, 4, 402, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // LDRBT_POST_REG |
| 9494 | { 961, 7, 2, 4, 922, 0, 0, ARMOpInfoBase + 897, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL }, // LDRBT_POST_IMM |
| 9495 | { 960, 5, 1, 4, 421, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // LDMIB_UPD |
| 9496 | { 959, 4, 0, 4, 420, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // LDMIB |
| 9497 | { 958, 5, 1, 4, 421, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // LDMIA_UPD |
| 9498 | { 957, 4, 0, 4, 420, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // LDMIA |
| 9499 | { 956, 5, 1, 4, 421, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // LDMDB_UPD |
| 9500 | { 955, 4, 0, 4, 420, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // LDMDB |
| 9501 | { 954, 5, 1, 4, 421, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL }, // LDMDA_UPD |
| 9502 | { 953, 4, 0, 4, 420, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL }, // LDMDA |
| 9503 | { 952, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // LDC_PRE |
| 9504 | { 951, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // LDC_POST |
| 9505 | { 950, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // LDC_OPTION |
| 9506 | { 949, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // LDC_OFFSET |
| 9507 | { 948, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // LDCL_PRE |
| 9508 | { 947, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // LDCL_POST |
| 9509 | { 946, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 891, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // LDCL_OPTION |
| 9510 | { 945, 6, 0, 4, 844, 0, 0, ARMOpInfoBase + 885, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // LDCL_OFFSET |
| 9511 | { 944, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // LDC2_PRE |
| 9512 | { 943, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // LDC2_POST |
| 9513 | { 942, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 881, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // LDC2_OPTION |
| 9514 | { 941, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // LDC2_OFFSET |
| 9515 | { 940, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL }, // LDC2L_PRE |
| 9516 | { 939, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL }, // LDC2L_POST |
| 9517 | { 938, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 881, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // LDC2L_OPTION |
| 9518 | { 937, 4, 0, 4, 844, 0, 0, ARMOpInfoBase + 877, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x105ULL }, // LDC2L_OFFSET |
| 9519 | { 936, 4, 1, 4, 685, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL }, // LDAH |
| 9520 | { 935, 4, 1, 4, 685, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // LDAEXH |
| 9521 | { 934, 4, 1, 4, 685, 0, 0, ARMOpInfoBase + 873, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL }, // LDAEXD |
| 9522 | { 933, 4, 1, 4, 685, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // LDAEXB |
| 9523 | { 932, 4, 1, 4, 685, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL }, // LDAEX |
| 9524 | { 931, 4, 1, 4, 685, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL }, // LDAB |
| 9525 | { 930, 4, 1, 4, 685, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL }, // LDA |
| 9526 | { 929, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // ISB |
| 9527 | { 928, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // HVC |
| 9528 | { 927, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // HLT |
| 9529 | { 926, 3, 0, 4, 841, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // HINT |
| 9530 | { 925, 5, 1, 4, 848, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // FSTMXIA_UPD |
| 9531 | { 924, 4, 0, 4, 848, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL }, // FSTMXIA |
| 9532 | { 923, 5, 1, 4, 848, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // FSTMXDB_UPD |
| 9533 | { 922, 2, 0, 4, 587, 1, 1, ARMOpInfoBase + 430, 71, 0|(1ULL<<MCID::Predicable), 0x8c00ULL }, // FMSTAT |
| 9534 | { 921, 5, 1, 4, 848, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // FLDMXIA_UPD |
| 9535 | { 920, 4, 0, 4, 848, 0, 0, ARMOpInfoBase + 869, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL }, // FLDMXIA |
| 9536 | { 919, 5, 1, 4, 848, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL }, // FLDMXDB_UPD |
| 9537 | { 918, 4, 1, 4, 964, 0, 0, ARMOpInfoBase + 865, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL }, // FCONSTS |
| 9538 | { 917, 4, 1, 4, 963, 0, 0, ARMOpInfoBase + 861, 0, 0|(1ULL<<MCID::Rematerializable), 0x8c00ULL }, // FCONSTH |
| 9539 | { 916, 4, 1, 4, 962, 0, 0, ARMOpInfoBase + 857, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL }, // FCONSTD |
| 9540 | { 915, 2, 0, 4, 1216, 0, 1, ARMOpInfoBase + 430, 70, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // ERET |
| 9541 | { 914, 8, 1, 4, 324, 0, 0, ARMOpInfoBase + 613, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // EORrsr |
| 9542 | { 913, 7, 1, 4, 323, 0, 0, ARMOpInfoBase + 598, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // EORrsi |
| 9543 | { 912, 6, 1, 4, 322, 0, 0, ARMOpInfoBase + 592, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // EORrr |
| 9544 | { 911, 6, 1, 4, 321, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // EORri |
| 9545 | { 910, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // DSB |
| 9546 | { 909, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // DMB |
| 9547 | { 908, 3, 0, 4, 841, 0, 0, ARMOpInfoBase + 854, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // DBG |
| 9548 | { 907, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 851, 0, 0, 0xd00ULL }, // CRC32W |
| 9549 | { 906, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 851, 0, 0, 0xd00ULL }, // CRC32H |
| 9550 | { 905, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 851, 0, 0, 0xd00ULL }, // CRC32CW |
| 9551 | { 904, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 851, 0, 0, 0xd00ULL }, // CRC32CH |
| 9552 | { 903, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 851, 0, 0, 0xd00ULL }, // CRC32CB |
| 9553 | { 902, 3, 1, 4, 698, 0, 0, ARMOpInfoBase + 851, 0, 0, 0xd00ULL }, // CRC32B |
| 9554 | { 901, 3, 0, 4, 841, 0, 0, ARMOpInfoBase + 11, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // CPS3p |
| 9555 | { 900, 2, 0, 4, 841, 0, 0, ARMOpInfoBase + 9, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // CPS2p |
| 9556 | { 899, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // CPS1p |
| 9557 | { 898, 6, 0, 4, 717, 0, 1, ARMOpInfoBase + 845, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // CMPrsr |
| 9558 | { 897, 5, 0, 4, 716, 0, 1, ARMOpInfoBase + 840, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // CMPrsi |
| 9559 | { 896, 4, 0, 4, 715, 0, 1, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // CMPrr |
| 9560 | { 895, 4, 0, 4, 714, 0, 1, ARMOpInfoBase + 244, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // CMPri |
| 9561 | { 894, 6, 0, 4, 717, 0, 1, ARMOpInfoBase + 845, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL }, // CMNrsr |
| 9562 | { 893, 5, 0, 4, 716, 0, 1, ARMOpInfoBase + 840, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL }, // CMNrsi |
| 9563 | { 892, 4, 0, 4, 715, 0, 1, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL }, // CMNrr |
| 9564 | { 891, 4, 0, 4, 714, 0, 1, ARMOpInfoBase + 244, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL }, // CMNri |
| 9565 | { 890, 4, 1, 4, 691, 0, 0, ARMOpInfoBase + 836, 0, 0|(1ULL<<MCID::Predicable), 0x600ULL }, // CLZ |
| 9566 | { 889, 0, 0, 4, 841, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // CLREX |
| 9567 | { 888, 6, 0, 4, 841, 0, 0, ARMOpInfoBase + 830, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // CDP2 |
| 9568 | { 887, 8, 0, 4, 841, 0, 0, ARMOpInfoBase + 822, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // CDP |
| 9569 | { 886, 9, 1, 4, 0, 0, 0, ARMOpInfoBase + 813, 0, 0, 0xc80ULL }, // CDE_VCX3_vec |
| 9570 | { 885, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 808, 0, 0, 0xc80ULL }, // CDE_VCX3_fpsp |
| 9571 | { 884, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 803, 0, 0, 0xc80ULL }, // CDE_VCX3_fpdp |
| 9572 | { 883, 9, 1, 4, 0, 0, 0, ARMOpInfoBase + 794, 0, 0, 0xc80ULL }, // CDE_VCX3A_vec |
| 9573 | { 882, 6, 1, 4, 0, 0, 0, ARMOpInfoBase + 788, 0, 0, 0xc80ULL }, // CDE_VCX3A_fpsp |
| 9574 | { 881, 6, 1, 4, 0, 0, 0, ARMOpInfoBase + 782, 0, 0, 0xc80ULL }, // CDE_VCX3A_fpdp |
| 9575 | { 880, 8, 1, 4, 0, 0, 0, ARMOpInfoBase + 774, 0, 0, 0xc80ULL }, // CDE_VCX2_vec |
| 9576 | { 879, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 770, 0, 0, 0xc80ULL }, // CDE_VCX2_fpsp |
| 9577 | { 878, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 766, 0, 0, 0xc80ULL }, // CDE_VCX2_fpdp |
| 9578 | { 877, 8, 1, 4, 0, 0, 0, ARMOpInfoBase + 758, 0, 0, 0xc80ULL }, // CDE_VCX2A_vec |
| 9579 | { 876, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 753, 0, 0, 0xc80ULL }, // CDE_VCX2A_fpsp |
| 9580 | { 875, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 748, 0, 0, 0xc80ULL }, // CDE_VCX2A_fpdp |
| 9581 | { 874, 7, 1, 4, 0, 0, 0, ARMOpInfoBase + 741, 0, 0, 0xc80ULL }, // CDE_VCX1_vec |
| 9582 | { 873, 3, 1, 4, 0, 0, 0, ARMOpInfoBase + 738, 0, 0, 0xc80ULL }, // CDE_VCX1_fpsp |
| 9583 | { 872, 3, 1, 4, 0, 0, 0, ARMOpInfoBase + 735, 0, 0, 0xc80ULL }, // CDE_VCX1_fpdp |
| 9584 | { 871, 7, 1, 4, 0, 0, 0, ARMOpInfoBase + 728, 0, 0, 0xc80ULL }, // CDE_VCX1A_vec |
| 9585 | { 870, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 724, 0, 0, 0xc80ULL }, // CDE_VCX1A_fpsp |
| 9586 | { 869, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 720, 0, 0, 0xc80ULL }, // CDE_VCX1A_fpdp |
| 9587 | { 868, 8, 1, 4, 0, 0, 0, ARMOpInfoBase + 712, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // CDE_CX3DA |
| 9588 | { 867, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 707, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // CDE_CX3D |
| 9589 | { 866, 8, 1, 4, 0, 0, 0, ARMOpInfoBase + 699, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // CDE_CX3A |
| 9590 | { 865, 5, 1, 4, 0, 0, 0, ARMOpInfoBase + 694, 0, 0, 0xc80ULL }, // CDE_CX3 |
| 9591 | { 864, 7, 1, 4, 0, 0, 0, ARMOpInfoBase + 687, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // CDE_CX2DA |
| 9592 | { 863, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 683, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // CDE_CX2D |
| 9593 | { 862, 7, 1, 4, 0, 0, 0, ARMOpInfoBase + 676, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // CDE_CX2A |
| 9594 | { 861, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 672, 0, 0, 0xc80ULL }, // CDE_CX2 |
| 9595 | { 860, 6, 1, 4, 0, 0, 0, ARMOpInfoBase + 666, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // CDE_CX1DA |
| 9596 | { 859, 3, 1, 4, 0, 0, 0, ARMOpInfoBase + 663, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL }, // CDE_CX1D |
| 9597 | { 858, 6, 1, 4, 0, 0, 0, ARMOpInfoBase + 657, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL }, // CDE_CX1A |
| 9598 | { 857, 3, 1, 4, 0, 0, 0, ARMOpInfoBase + 654, 0, 0, 0xc80ULL }, // CDE_CX1 |
| 9599 | { 856, 3, 0, 4, 851, 0, 0, ARMOpInfoBase + 544, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x100ULL }, // Bcc |
| 9600 | { 855, 3, 0, 4, 851, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // BX_pred |
| 9601 | { 854, 2, 0, 4, 851, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL }, // BX_RET |
| 9602 | { 853, 3, 0, 4, 852, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL }, // BXJ |
| 9603 | { 852, 1, 0, 4, 851, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x180ULL }, // BX |
| 9604 | { 851, 3, 0, 4, 854, 1, 1, ARMOpInfoBase + 544, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x100ULL }, // BL_pred |
| 9605 | { 850, 1, 0, 4, 855, 0, 0, ARMOpInfoBase + 192, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL }, // BLXi |
| 9606 | { 849, 3, 0, 4, 857, 1, 1, ARMOpInfoBase + 536, 3, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x180ULL }, // BLX_pred |
| 9607 | { 848, 1, 0, 4, 857, 1, 1, ARMOpInfoBase + 296, 3, 0|(1ULL<<MCID::Call), 0x180ULL }, // BLX |
| 9608 | { 847, 1, 0, 4, 854, 1, 1, ARMOpInfoBase + 192, 3, 0|(1ULL<<MCID::Call), 0x100ULL }, // BL |
| 9609 | { 846, 1, 0, 4, 841, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL }, // BKPT |
| 9610 | { 845, 8, 1, 4, 324, 0, 0, ARMOpInfoBase + 613, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // BICrsr |
| 9611 | { 844, 7, 1, 4, 323, 0, 0, ARMOpInfoBase + 598, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // BICrsi |
| 9612 | { 843, 6, 1, 4, 322, 0, 0, ARMOpInfoBase + 592, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // BICrr |
| 9613 | { 842, 6, 1, 4, 321, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // BICri |
| 9614 | { 841, 6, 1, 4, 334, 0, 0, ARMOpInfoBase + 648, 0, 0|(1ULL<<MCID::Predicable), 0x201ULL }, // BFI |
| 9615 | { 840, 5, 1, 4, 334, 0, 0, ARMOpInfoBase + 268, 0, 0|(1ULL<<MCID::Predicable), 0x201ULL }, // BFC |
| 9616 | { 839, 5, 1, 4, 0, 1, 0, ARMOpInfoBase + 409, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // BF16_VCVTT |
| 9617 | { 838, 5, 1, 4, 0, 1, 0, ARMOpInfoBase + 409, 69, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Predicable), 0x8780ULL }, // BF16_VCVTB |
| 9618 | { 837, 4, 1, 4, 0, 0, 0, ARMOpInfoBase + 644, 0, 0|(1ULL<<MCID::Predicable), 0x11000ULL }, // BF16_VCVT |
| 9619 | { 836, 4, 1, 4, 50, 0, 0, ARMOpInfoBase + 640, 0, 0, 0x11280ULL }, // BF16VDOTS_VDOTQ |
| 9620 | { 835, 4, 1, 4, 50, 0, 0, ARMOpInfoBase + 636, 0, 0, 0x11280ULL }, // BF16VDOTS_VDOTD |
| 9621 | { 834, 5, 1, 4, 50, 0, 0, ARMOpInfoBase + 631, 0, 0, 0x11280ULL }, // BF16VDOTI_VDOTQ |
| 9622 | { 833, 5, 1, 4, 50, 0, 0, ARMOpInfoBase + 626, 0, 0, 0x11280ULL }, // BF16VDOTI_VDOTD |
| 9623 | { 832, 8, 1, 4, 324, 0, 0, ARMOpInfoBase + 613, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // ANDrsr |
| 9624 | { 831, 7, 1, 4, 323, 0, 0, ARMOpInfoBase + 598, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // ANDrsi |
| 9625 | { 830, 6, 1, 4, 322, 0, 0, ARMOpInfoBase + 592, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // ANDrr |
| 9626 | { 829, 6, 1, 4, 321, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // ANDri |
| 9627 | { 828, 2, 1, 4, 1008, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // AESMC |
| 9628 | { 827, 2, 1, 4, 1008, 0, 0, ARMOpInfoBase + 624, 0, 0, 0x11000ULL }, // AESIMC |
| 9629 | { 826, 3, 1, 4, 1008, 0, 0, ARMOpInfoBase + 621, 0, 0|(1ULL<<MCID::Commutable), 0x11000ULL }, // AESE |
| 9630 | { 825, 3, 1, 4, 1008, 0, 0, ARMOpInfoBase + 621, 0, 0|(1ULL<<MCID::Commutable), 0x11000ULL }, // AESD |
| 9631 | { 824, 4, 1, 4, 707, 0, 0, ARMOpInfoBase + 244, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xd01ULL }, // ADR |
| 9632 | { 823, 8, 1, 4, 706, 0, 0, ARMOpInfoBase + 613, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL }, // ADDrsr |
| 9633 | { 822, 7, 1, 4, 700, 0, 0, ARMOpInfoBase + 598, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL }, // ADDrsi |
| 9634 | { 821, 6, 1, 4, 697, 0, 0, ARMOpInfoBase + 592, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // ADDrr |
| 9635 | { 820, 6, 1, 4, 690, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL }, // ADDri |
| 9636 | { 819, 8, 1, 4, 706, 1, 1, ARMOpInfoBase + 605, 66, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL }, // ADCrsr |
| 9637 | { 818, 7, 1, 4, 700, 1, 1, ARMOpInfoBase + 598, 66, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL }, // ADCrsi |
| 9638 | { 817, 6, 1, 4, 697, 1, 1, ARMOpInfoBase + 592, 66, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // ADCrr |
| 9639 | { 816, 6, 1, 4, 690, 1, 1, ARMOpInfoBase + 178, 66, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL }, // ADCri |
| 9640 | { 815, 0, 0, 4, 856, 1, 4, ARMOpInfoBase + 1, 55, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // tTPsoft |
| 9641 | { 814, 4, 0, 2, 6, 0, 0, ARMOpInfoBase + 588, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tTBH_JT |
| 9642 | { 813, 4, 0, 2, 6, 0, 0, ARMOpInfoBase + 588, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tTBB_JT |
| 9643 | { 812, 1, 0, 4, 851, 1, 0, ARMOpInfoBase + 296, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tTAILJMPr |
| 9644 | { 811, 3, 0, 4, 851, 1, 0, ARMOpInfoBase + 544, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tTAILJMPdND |
| 9645 | { 810, 3, 0, 4, 851, 1, 0, ARMOpInfoBase + 544, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tTAILJMPd |
| 9646 | { 809, 3, 1, 2, 41, 0, 1, ARMOpInfoBase + 519, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tSUBSrr |
| 9647 | { 808, 3, 1, 2, 42, 0, 1, ARMOpInfoBase + 522, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tSUBSi8 |
| 9648 | { 807, 3, 1, 2, 42, 0, 1, ARMOpInfoBase + 522, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tSUBSi3 |
| 9649 | { 806, 3, 1, 2, 41, 1, 1, ARMOpInfoBase + 519, 66, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tSBCS |
| 9650 | { 805, 2, 1, 2, 41, 0, 1, ARMOpInfoBase + 586, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tRSBS |
| 9651 | { 804, 3, 0, 2, 423, 0, 0, ARMOpInfoBase + 583, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // tPOP_RET |
| 9652 | { 803, 2, 1, 16, 869, 0, 1, ARMOpInfoBase + 444, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // tMOVi32imm |
| 9653 | { 802, 5, 1, 0, 869, 0, 0, ARMOpInfoBase + 578, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // tMOVCCr_pseudo |
| 9654 | { 801, 3, 1, 2, 1272, 0, 1, ARMOpInfoBase + 522, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tLSLSri |
| 9655 | { 800, 4, 1, 2, 42, 0, 0, ARMOpInfoBase + 574, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tLEApcrelJT |
| 9656 | { 799, 4, 1, 2, 42, 0, 0, ARMOpInfoBase + 574, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // tLEApcrel |
| 9657 | { 798, 3, 1, 0, 393, 0, 0, ARMOpInfoBase + 571, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // tLDRpci_pic |
| 9658 | { 797, 5, 2, 4, 902, 0, 0, ARMOpInfoBase + 566, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // tLDR_postidx |
| 9659 | { 796, 2, 1, 8, 1021, 0, 0, ARMOpInfoBase + 539, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // tLDRLIT_ga_pcrel |
| 9660 | { 795, 2, 1, 6, 1020, 0, 0, ARMOpInfoBase + 539, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // tLDRLIT_ga_abs |
| 9661 | { 794, 4, 0, 4, 1018, 0, 0, ARMOpInfoBase + 562, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // tLDRConstPool |
| 9662 | { 793, 5, 1, 2, 1015, 0, 0, ARMOpInfoBase + 557, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // tLDMIA_UPD |
| 9663 | { 792, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 547, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tCMP_SWAP_8 |
| 9664 | { 791, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 552, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tCMP_SWAP_32 |
| 9665 | { 790, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 547, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tCMP_SWAP_16 |
| 9666 | { 789, 3, 0, 4, 853, 0, 1, ARMOpInfoBase + 544, 68, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tBfar |
| 9667 | { 788, 3, 0, 2, 851, 0, 0, ARMOpInfoBase + 541, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tBX_RET_vararg |
| 9668 | { 787, 2, 0, 2, 851, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // tBX_RET |
| 9669 | { 786, 1, 0, 4, 851, 1, 1, ARMOpInfoBase + 206, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // tBX_CALL |
| 9670 | { 785, 0, 0, 2, 851, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // tBXNS_RET |
| 9671 | { 784, 2, 0, 2, 859, 0, 0, ARMOpInfoBase + 539, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // tBR_JTr |
| 9672 | { 783, 3, 0, 2, 860, 0, 0, ARMOpInfoBase + 536, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // tBRIND |
| 9673 | { 782, 4, 0, 4, 6, 1, 1, ARMOpInfoBase + 532, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tBL_PUSHLR |
| 9674 | { 781, 3, 0, 2, 857, 1, 1, ARMOpInfoBase + 529, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x0ULL }, // tBLXr_noip |
| 9675 | { 780, 1, 0, 0, 6, 1, 1, ARMOpInfoBase + 528, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // tBLXNS_CALL |
| 9676 | { 779, 2, 0, 0, 1037, 1, 1, ARMOpInfoBase + 20, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tADJCALLSTACKUP |
| 9677 | { 778, 2, 0, 0, 1037, 1, 1, ARMOpInfoBase + 20, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tADJCALLSTACKDOWN |
| 9678 | { 777, 3, 1, 0, 863, 0, 1, ARMOpInfoBase + 525, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // tADDframe |
| 9679 | { 776, 3, 1, 2, 41, 0, 1, ARMOpInfoBase + 519, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tADDSrr |
| 9680 | { 775, 3, 1, 2, 42, 0, 1, ARMOpInfoBase + 522, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tADDSi8 |
| 9681 | { 774, 3, 1, 2, 42, 0, 1, ARMOpInfoBase + 522, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tADDSi3 |
| 9682 | { 773, 3, 1, 2, 41, 1, 1, ARMOpInfoBase + 519, 66, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // tADCS |
| 9683 | { 772, 4, 1, 8, 6, 0, 1, ARMOpInfoBase + 515, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2WhileLoopStartTP |
| 9684 | { 771, 3, 1, 8, 6, 0, 1, ARMOpInfoBase + 512, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2WhileLoopStartLR |
| 9685 | { 770, 2, 0, 4, 6, 0, 1, ARMOpInfoBase + 204, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2WhileLoopStart |
| 9686 | { 769, 2, 1, 4, 32, 0, 0, ARMOpInfoBase + 435, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2WhileLoopSetup |
| 9687 | { 768, 4, 0, 4, 1232, 0, 0, ARMOpInfoBase + 231, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2TBH_JT |
| 9688 | { 767, 4, 0, 4, 1232, 0, 0, ARMOpInfoBase + 231, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2TBB_JT |
| 9689 | { 766, 0, 0, 4, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2SpeculationBarrierSBEndBB |
| 9690 | { 765, 0, 0, 8, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2SpeculationBarrierISBDSBEndBB |
| 9691 | { 764, 6, 1, 4, 1235, 0, 1, ARMOpInfoBase + 424, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // t2SUBSrs |
| 9692 | { 763, 5, 1, 4, 1268, 0, 1, ARMOpInfoBase + 419, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // t2SUBSrr |
| 9693 | { 762, 5, 1, 4, 1109, 0, 1, ARMOpInfoBase + 414, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // t2SUBSri |
| 9694 | { 761, 6, 1, 4, 443, 0, 0, ARMOpInfoBase + 506, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // t2STR_preidx |
| 9695 | { 760, 5, 0, 4, 940, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2STR_PRE_imm |
| 9696 | { 759, 5, 0, 4, 950, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2STR_POST_imm |
| 9697 | { 758, 6, 1, 4, 443, 0, 0, ARMOpInfoBase + 506, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // t2STRH_preidx |
| 9698 | { 757, 5, 0, 4, 940, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2STRH_PRE_imm |
| 9699 | { 756, 5, 0, 4, 440, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2STRH_POST_imm |
| 9700 | { 755, 5, 0, 4, 0, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2STRH_OFFSET_imm |
| 9701 | { 754, 6, 1, 4, 443, 0, 0, ARMOpInfoBase + 506, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // t2STRB_preidx |
| 9702 | { 753, 5, 0, 4, 940, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2STRB_PRE_imm |
| 9703 | { 752, 5, 0, 4, 950, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2STRB_POST_imm |
| 9704 | { 751, 5, 0, 4, 0, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2STRB_OFFSET_imm |
| 9705 | { 750, 6, 1, 4, 1265, 0, 1, ARMOpInfoBase + 500, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // t2RSBSrs |
| 9706 | { 749, 5, 1, 4, 1069, 0, 1, ARMOpInfoBase + 495, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // t2RSBSri |
| 9707 | { 748, 5, 1, 4, 693, 0, 0, ARMOpInfoBase + 465, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MVNCCi |
| 9708 | { 747, 6, 0, 4, 688, 0, 0, ARMOpInfoBase + 485, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVsr |
| 9709 | { 746, 5, 0, 4, 710, 0, 0, ARMOpInfoBase + 480, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVsi |
| 9710 | { 745, 2, 1, 8, 354, 0, 0, ARMOpInfoBase + 444, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // t2MOVi32imm |
| 9711 | { 744, 3, 1, 4, 356, 0, 0, ARMOpInfoBase + 446, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2MOVi16_ga_pcrel |
| 9712 | { 743, 2, 1, 0, 355, 0, 0, ARMOpInfoBase + 444, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // t2MOV_ga_pcrel |
| 9713 | { 742, 4, 1, 4, 876, 0, 0, ARMOpInfoBase + 491, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2MOVTi16_ga_pcrel |
| 9714 | { 741, 6, 0, 4, 1095, 0, 0, ARMOpInfoBase + 485, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVSsr |
| 9715 | { 740, 5, 0, 4, 1094, 0, 0, ARMOpInfoBase + 480, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVSsi |
| 9716 | { 739, 6, 1, 4, 874, 0, 0, ARMOpInfoBase + 459, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVCCror |
| 9717 | { 738, 5, 1, 4, 875, 0, 0, ARMOpInfoBase + 475, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL }, // t2MOVCCr |
| 9718 | { 737, 6, 1, 4, 874, 0, 0, ARMOpInfoBase + 459, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVCClsr |
| 9719 | { 736, 6, 1, 4, 874, 0, 0, ARMOpInfoBase + 459, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVCClsl |
| 9720 | { 735, 5, 1, 8, 353, 0, 0, ARMOpInfoBase + 470, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVCCi32imm |
| 9721 | { 734, 5, 1, 4, 680, 0, 0, ARMOpInfoBase + 465, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVCCi16 |
| 9722 | { 733, 5, 1, 4, 680, 0, 0, ARMOpInfoBase + 465, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVCCi |
| 9723 | { 732, 6, 1, 4, 874, 0, 0, ARMOpInfoBase + 459, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2MOVCCasr |
| 9724 | { 731, 3, 1, 8, 6, 0, 1, ARMOpInfoBase + 456, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LoopEndDec |
| 9725 | { 730, 2, 0, 8, 6, 0, 1, ARMOpInfoBase + 204, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LoopEnd |
| 9726 | { 729, 3, 1, 4, 1110, 0, 0, ARMOpInfoBase + 453, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // t2LoopDec |
| 9727 | { 728, 4, 1, 4, 1, 0, 0, ARMOpInfoBase + 449, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LEApcrelJT |
| 9728 | { 727, 4, 1, 4, 1, 0, 0, ARMOpInfoBase + 449, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // t2LEApcrel |
| 9729 | { 726, 4, 0, 4, 905, 0, 0, ARMOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRpcrel |
| 9730 | { 725, 3, 1, 0, 388, 0, 0, ARMOpInfoBase + 446, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // t2LDRpci_pic |
| 9731 | { 724, 5, 0, 4, 914, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDR_PRE_imm |
| 9732 | { 723, 5, 0, 4, 408, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDR_POST_imm |
| 9733 | { 722, 4, 0, 4, 398, 0, 0, ARMOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRSHpcrel |
| 9734 | { 721, 5, 0, 4, 915, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRSH_PRE_imm |
| 9735 | { 720, 5, 0, 4, 413, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRSH_POST_imm |
| 9736 | { 719, 5, 0, 4, 1017, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRSH_OFFSET_imm |
| 9737 | { 718, 4, 0, 4, 398, 0, 0, ARMOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRSBpcrel |
| 9738 | { 717, 5, 0, 4, 915, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRSB_PRE_imm |
| 9739 | { 716, 5, 0, 4, 413, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRSB_POST_imm |
| 9740 | { 715, 5, 0, 4, 1017, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRSB_OFFSET_imm |
| 9741 | { 714, 2, 1, 0, 1019, 0, 0, ARMOpInfoBase + 444, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // t2LDRLIT_ga_pcrel |
| 9742 | { 713, 4, 0, 4, 1219, 0, 0, ARMOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRHpcrel |
| 9743 | { 712, 5, 0, 4, 1223, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRH_PRE_imm |
| 9744 | { 711, 5, 0, 4, 1222, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRH_POST_imm |
| 9745 | { 710, 5, 0, 4, 1017, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRH_OFFSET_imm |
| 9746 | { 709, 4, 0, 4, 1018, 0, 0, ARMOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRConstPool |
| 9747 | { 708, 4, 0, 4, 1219, 0, 0, ARMOpInfoBase + 440, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRBpcrel |
| 9748 | { 707, 5, 0, 4, 908, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRB_PRE_imm |
| 9749 | { 706, 5, 0, 4, 925, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRB_POST_imm |
| 9750 | { 705, 5, 0, 4, 1017, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2LDRB_OFFSET_imm |
| 9751 | { 704, 5, 1, 4, 1014, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // t2LDMIA_RET |
| 9752 | { 703, 3, 1, 4, 32, 0, 0, ARMOpInfoBase + 437, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2DoLoopStartTP |
| 9753 | { 702, 2, 1, 4, 32, 0, 0, ARMOpInfoBase + 435, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2DoLoopStart |
| 9754 | { 701, 3, 0, 0, 7, 1, 1, ARMOpInfoBase + 432, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // t2CALL_BTI |
| 9755 | { 700, 2, 0, 4, 6, 0, 0, ARMOpInfoBase + 430, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // t2BXAUT_RET |
| 9756 | { 699, 3, 0, 4, 860, 0, 0, ARMOpInfoBase + 207, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // t2BR_JT |
| 9757 | { 698, 1, 0, 0, 1282, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // t2BF_LabelPseudo |
| 9758 | { 697, 6, 1, 4, 701, 0, 1, ARMOpInfoBase + 424, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // t2ADDSrs |
| 9759 | { 696, 5, 1, 4, 1267, 0, 1, ARMOpInfoBase + 419, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // t2ADDSrr |
| 9760 | { 695, 5, 1, 4, 1108, 0, 1, ARMOpInfoBase + 414, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // t2ADDSri |
| 9761 | { 694, 1, 0, 0, 849, 0, 1, ARMOpInfoBase + 206, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WIN__DBZCHK |
| 9762 | { 693, 0, 0, 0, 849, 1, 5, ARMOpInfoBase + 1, 60, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // WIN__CHKSTK |
| 9763 | { 692, 6, 0, 4, 836, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4qWB_register_Asm_8 |
| 9764 | { 691, 6, 0, 4, 836, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4qWB_register_Asm_32 |
| 9765 | { 690, 6, 0, 4, 836, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4qWB_register_Asm_16 |
| 9766 | { 689, 5, 0, 4, 836, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4qWB_fixed_Asm_8 |
| 9767 | { 688, 5, 0, 4, 836, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4qWB_fixed_Asm_32 |
| 9768 | { 687, 5, 0, 4, 836, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4qWB_fixed_Asm_16 |
| 9769 | { 686, 5, 0, 4, 828, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4qAsm_8 |
| 9770 | { 685, 5, 0, 4, 828, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4qAsm_32 |
| 9771 | { 684, 5, 0, 4, 828, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4qAsm_16 |
| 9772 | { 683, 6, 0, 4, 836, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4dWB_register_Asm_8 |
| 9773 | { 682, 6, 0, 4, 836, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4dWB_register_Asm_32 |
| 9774 | { 681, 6, 0, 4, 836, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4dWB_register_Asm_16 |
| 9775 | { 680, 5, 0, 4, 836, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4dWB_fixed_Asm_8 |
| 9776 | { 679, 5, 0, 4, 836, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4dWB_fixed_Asm_32 |
| 9777 | { 678, 5, 0, 4, 836, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4dWB_fixed_Asm_16 |
| 9778 | { 677, 5, 0, 4, 828, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4dAsm_8 |
| 9779 | { 676, 5, 0, 4, 828, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4dAsm_32 |
| 9780 | { 675, 5, 0, 4, 828, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4dAsm_16 |
| 9781 | { 674, 7, 0, 4, 840, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNqWB_register_Asm_32 |
| 9782 | { 673, 7, 0, 4, 840, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNqWB_register_Asm_16 |
| 9783 | { 672, 6, 0, 4, 840, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNqWB_fixed_Asm_32 |
| 9784 | { 671, 6, 0, 4, 840, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNqWB_fixed_Asm_16 |
| 9785 | { 670, 6, 0, 4, 834, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNqAsm_32 |
| 9786 | { 669, 6, 0, 4, 834, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNqAsm_16 |
| 9787 | { 668, 7, 0, 4, 838, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNdWB_register_Asm_8 |
| 9788 | { 667, 7, 0, 4, 838, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNdWB_register_Asm_32 |
| 9789 | { 666, 7, 0, 4, 838, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNdWB_register_Asm_16 |
| 9790 | { 665, 6, 0, 4, 838, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNdWB_fixed_Asm_8 |
| 9791 | { 664, 6, 0, 4, 838, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNdWB_fixed_Asm_32 |
| 9792 | { 663, 6, 0, 4, 838, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNdWB_fixed_Asm_16 |
| 9793 | { 662, 6, 0, 4, 831, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNdAsm_8 |
| 9794 | { 661, 6, 0, 4, 831, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNdAsm_32 |
| 9795 | { 660, 6, 0, 4, 831, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST4LNdAsm_16 |
| 9796 | { 659, 6, 0, 4, 822, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3qWB_register_Asm_8 |
| 9797 | { 658, 6, 0, 4, 822, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3qWB_register_Asm_32 |
| 9798 | { 657, 6, 0, 4, 822, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3qWB_register_Asm_16 |
| 9799 | { 656, 5, 0, 4, 822, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3qWB_fixed_Asm_8 |
| 9800 | { 655, 5, 0, 4, 822, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3qWB_fixed_Asm_32 |
| 9801 | { 654, 5, 0, 4, 822, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3qWB_fixed_Asm_16 |
| 9802 | { 653, 5, 0, 4, 815, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3qAsm_8 |
| 9803 | { 652, 5, 0, 4, 815, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3qAsm_32 |
| 9804 | { 651, 5, 0, 4, 815, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3qAsm_16 |
| 9805 | { 650, 6, 0, 4, 822, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3dWB_register_Asm_8 |
| 9806 | { 649, 6, 0, 4, 822, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3dWB_register_Asm_32 |
| 9807 | { 648, 6, 0, 4, 822, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3dWB_register_Asm_16 |
| 9808 | { 647, 5, 0, 4, 822, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3dWB_fixed_Asm_8 |
| 9809 | { 646, 5, 0, 4, 822, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3dWB_fixed_Asm_32 |
| 9810 | { 645, 5, 0, 4, 822, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3dWB_fixed_Asm_16 |
| 9811 | { 644, 5, 0, 4, 815, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3dAsm_8 |
| 9812 | { 643, 5, 0, 4, 815, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3dAsm_32 |
| 9813 | { 642, 5, 0, 4, 815, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3dAsm_16 |
| 9814 | { 641, 7, 0, 4, 826, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNqWB_register_Asm_32 |
| 9815 | { 640, 7, 0, 4, 826, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNqWB_register_Asm_16 |
| 9816 | { 639, 6, 0, 4, 826, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNqWB_fixed_Asm_32 |
| 9817 | { 638, 6, 0, 4, 826, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNqWB_fixed_Asm_16 |
| 9818 | { 637, 6, 0, 4, 820, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNqAsm_32 |
| 9819 | { 636, 6, 0, 4, 820, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNqAsm_16 |
| 9820 | { 635, 7, 0, 4, 824, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNdWB_register_Asm_8 |
| 9821 | { 634, 7, 0, 4, 824, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNdWB_register_Asm_32 |
| 9822 | { 633, 7, 0, 4, 824, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNdWB_register_Asm_16 |
| 9823 | { 632, 6, 0, 4, 824, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNdWB_fixed_Asm_8 |
| 9824 | { 631, 6, 0, 4, 824, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNdWB_fixed_Asm_32 |
| 9825 | { 630, 6, 0, 4, 824, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNdWB_fixed_Asm_16 |
| 9826 | { 629, 6, 0, 4, 818, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNdAsm_8 |
| 9827 | { 628, 6, 0, 4, 818, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNdAsm_32 |
| 9828 | { 627, 6, 0, 4, 818, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST3LNdAsm_16 |
| 9829 | { 626, 7, 0, 4, 813, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNqWB_register_Asm_32 |
| 9830 | { 625, 7, 0, 4, 813, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNqWB_register_Asm_16 |
| 9831 | { 624, 6, 0, 4, 813, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNqWB_fixed_Asm_32 |
| 9832 | { 623, 6, 0, 4, 813, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNqWB_fixed_Asm_16 |
| 9833 | { 622, 6, 0, 4, 809, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNqAsm_32 |
| 9834 | { 621, 6, 0, 4, 809, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNqAsm_16 |
| 9835 | { 620, 7, 0, 4, 811, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNdWB_register_Asm_8 |
| 9836 | { 619, 7, 0, 4, 811, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNdWB_register_Asm_32 |
| 9837 | { 618, 7, 0, 4, 811, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNdWB_register_Asm_16 |
| 9838 | { 617, 6, 0, 4, 811, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNdWB_fixed_Asm_8 |
| 9839 | { 616, 6, 0, 4, 811, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNdWB_fixed_Asm_32 |
| 9840 | { 615, 6, 0, 4, 811, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNdWB_fixed_Asm_16 |
| 9841 | { 614, 6, 0, 4, 806, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNdAsm_8 |
| 9842 | { 613, 6, 0, 4, 806, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNdAsm_32 |
| 9843 | { 612, 6, 0, 4, 806, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST2LNdAsm_16 |
| 9844 | { 611, 7, 0, 4, 803, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST1LNdWB_register_Asm_8 |
| 9845 | { 610, 7, 0, 4, 803, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST1LNdWB_register_Asm_32 |
| 9846 | { 609, 7, 0, 4, 803, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST1LNdWB_register_Asm_16 |
| 9847 | { 608, 6, 0, 4, 803, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST1LNdWB_fixed_Asm_8 |
| 9848 | { 607, 6, 0, 4, 803, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST1LNdWB_fixed_Asm_32 |
| 9849 | { 606, 6, 0, 4, 803, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST1LNdWB_fixed_Asm_16 |
| 9850 | { 605, 6, 0, 4, 800, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST1LNdAsm_8 |
| 9851 | { 604, 6, 0, 4, 800, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST1LNdAsm_32 |
| 9852 | { 603, 6, 0, 4, 800, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VST1LNdAsm_16 |
| 9853 | { 602, 5, 1, 0, 569, 0, 0, ARMOpInfoBase + 409, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // VMOVScc |
| 9854 | { 601, 1, 1, 4, 998, 0, 0, ARMOpInfoBase + 408, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // VMOVQ0 |
| 9855 | { 600, 5, 1, 0, 965, 0, 0, ARMOpInfoBase + 403, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // VMOVHcc |
| 9856 | { 599, 5, 1, 0, 568, 0, 0, ARMOpInfoBase + 398, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // VMOVDcc |
| 9857 | { 598, 1, 1, 4, 1054, 0, 0, ARMOpInfoBase + 397, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // VMOVD0 |
| 9858 | { 597, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4qWB_register_Asm_8 |
| 9859 | { 596, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4qWB_register_Asm_32 |
| 9860 | { 595, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4qWB_register_Asm_16 |
| 9861 | { 594, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4qWB_fixed_Asm_8 |
| 9862 | { 593, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4qWB_fixed_Asm_32 |
| 9863 | { 592, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4qWB_fixed_Asm_16 |
| 9864 | { 591, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4qAsm_8 |
| 9865 | { 590, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4qAsm_32 |
| 9866 | { 589, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4qAsm_16 |
| 9867 | { 588, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4dWB_register_Asm_8 |
| 9868 | { 587, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4dWB_register_Asm_32 |
| 9869 | { 586, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4dWB_register_Asm_16 |
| 9870 | { 585, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4dWB_fixed_Asm_8 |
| 9871 | { 584, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4dWB_fixed_Asm_32 |
| 9872 | { 583, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4dWB_fixed_Asm_16 |
| 9873 | { 582, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4dAsm_8 |
| 9874 | { 581, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4dAsm_32 |
| 9875 | { 580, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4dAsm_16 |
| 9876 | { 579, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNqWB_register_Asm_32 |
| 9877 | { 578, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNqWB_register_Asm_16 |
| 9878 | { 577, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNqWB_fixed_Asm_32 |
| 9879 | { 576, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNqWB_fixed_Asm_16 |
| 9880 | { 575, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNqAsm_32 |
| 9881 | { 574, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNqAsm_16 |
| 9882 | { 573, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNdWB_register_Asm_8 |
| 9883 | { 572, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNdWB_register_Asm_32 |
| 9884 | { 571, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNdWB_register_Asm_16 |
| 9885 | { 570, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNdWB_fixed_Asm_8 |
| 9886 | { 569, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNdWB_fixed_Asm_32 |
| 9887 | { 568, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNdWB_fixed_Asm_16 |
| 9888 | { 567, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNdAsm_8 |
| 9889 | { 566, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNdAsm_32 |
| 9890 | { 565, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4LNdAsm_16 |
| 9891 | { 564, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPqWB_register_Asm_8 |
| 9892 | { 563, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPqWB_register_Asm_32 |
| 9893 | { 562, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPqWB_register_Asm_16 |
| 9894 | { 561, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPqWB_fixed_Asm_8 |
| 9895 | { 560, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPqWB_fixed_Asm_32 |
| 9896 | { 559, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPqWB_fixed_Asm_16 |
| 9897 | { 558, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPqAsm_8 |
| 9898 | { 557, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPqAsm_32 |
| 9899 | { 556, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPqAsm_16 |
| 9900 | { 555, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPdWB_register_Asm_8 |
| 9901 | { 554, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPdWB_register_Asm_32 |
| 9902 | { 553, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPdWB_register_Asm_16 |
| 9903 | { 552, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPdWB_fixed_Asm_8 |
| 9904 | { 551, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPdWB_fixed_Asm_32 |
| 9905 | { 550, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPdWB_fixed_Asm_16 |
| 9906 | { 549, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPdAsm_8 |
| 9907 | { 548, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPdAsm_32 |
| 9908 | { 547, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD4DUPdAsm_16 |
| 9909 | { 546, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3qWB_register_Asm_8 |
| 9910 | { 545, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3qWB_register_Asm_32 |
| 9911 | { 544, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3qWB_register_Asm_16 |
| 9912 | { 543, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3qWB_fixed_Asm_8 |
| 9913 | { 542, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3qWB_fixed_Asm_32 |
| 9914 | { 541, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3qWB_fixed_Asm_16 |
| 9915 | { 540, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3qAsm_8 |
| 9916 | { 539, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3qAsm_32 |
| 9917 | { 538, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3qAsm_16 |
| 9918 | { 537, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3dWB_register_Asm_8 |
| 9919 | { 536, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3dWB_register_Asm_32 |
| 9920 | { 535, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3dWB_register_Asm_16 |
| 9921 | { 534, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3dWB_fixed_Asm_8 |
| 9922 | { 533, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3dWB_fixed_Asm_32 |
| 9923 | { 532, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3dWB_fixed_Asm_16 |
| 9924 | { 531, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3dAsm_8 |
| 9925 | { 530, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3dAsm_32 |
| 9926 | { 529, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3dAsm_16 |
| 9927 | { 528, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNqWB_register_Asm_32 |
| 9928 | { 527, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNqWB_register_Asm_16 |
| 9929 | { 526, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNqWB_fixed_Asm_32 |
| 9930 | { 525, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNqWB_fixed_Asm_16 |
| 9931 | { 524, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNqAsm_32 |
| 9932 | { 523, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNqAsm_16 |
| 9933 | { 522, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNdWB_register_Asm_8 |
| 9934 | { 521, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNdWB_register_Asm_32 |
| 9935 | { 520, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNdWB_register_Asm_16 |
| 9936 | { 519, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNdWB_fixed_Asm_8 |
| 9937 | { 518, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNdWB_fixed_Asm_32 |
| 9938 | { 517, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNdWB_fixed_Asm_16 |
| 9939 | { 516, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNdAsm_8 |
| 9940 | { 515, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNdAsm_32 |
| 9941 | { 514, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3LNdAsm_16 |
| 9942 | { 513, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPqWB_register_Asm_8 |
| 9943 | { 512, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPqWB_register_Asm_32 |
| 9944 | { 511, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPqWB_register_Asm_16 |
| 9945 | { 510, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPqWB_fixed_Asm_8 |
| 9946 | { 509, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPqWB_fixed_Asm_32 |
| 9947 | { 508, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPqWB_fixed_Asm_16 |
| 9948 | { 507, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPqAsm_8 |
| 9949 | { 506, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPqAsm_32 |
| 9950 | { 505, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPqAsm_16 |
| 9951 | { 504, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPdWB_register_Asm_8 |
| 9952 | { 503, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPdWB_register_Asm_32 |
| 9953 | { 502, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 391, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPdWB_register_Asm_16 |
| 9954 | { 501, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPdWB_fixed_Asm_8 |
| 9955 | { 500, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPdWB_fixed_Asm_32 |
| 9956 | { 499, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPdWB_fixed_Asm_16 |
| 9957 | { 498, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPdAsm_8 |
| 9958 | { 497, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPdAsm_32 |
| 9959 | { 496, 5, 0, 4, 1043, 0, 0, ARMOpInfoBase + 386, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD3DUPdAsm_16 |
| 9960 | { 495, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNqWB_register_Asm_32 |
| 9961 | { 494, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNqWB_register_Asm_16 |
| 9962 | { 493, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNqWB_fixed_Asm_32 |
| 9963 | { 492, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNqWB_fixed_Asm_16 |
| 9964 | { 491, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNqAsm_32 |
| 9965 | { 490, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNqAsm_16 |
| 9966 | { 489, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNdWB_register_Asm_8 |
| 9967 | { 488, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNdWB_register_Asm_32 |
| 9968 | { 487, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNdWB_register_Asm_16 |
| 9969 | { 486, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNdWB_fixed_Asm_8 |
| 9970 | { 485, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNdWB_fixed_Asm_32 |
| 9971 | { 484, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNdWB_fixed_Asm_16 |
| 9972 | { 483, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNdAsm_8 |
| 9973 | { 482, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNdAsm_32 |
| 9974 | { 481, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD2LNdAsm_16 |
| 9975 | { 480, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD1LNdWB_register_Asm_8 |
| 9976 | { 479, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD1LNdWB_register_Asm_32 |
| 9977 | { 478, 7, 0, 4, 1043, 0, 0, ARMOpInfoBase + 379, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD1LNdWB_register_Asm_16 |
| 9978 | { 477, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD1LNdWB_fixed_Asm_8 |
| 9979 | { 476, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD1LNdWB_fixed_Asm_32 |
| 9980 | { 475, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD1LNdWB_fixed_Asm_16 |
| 9981 | { 474, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD1LNdAsm_8 |
| 9982 | { 473, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD1LNdAsm_32 |
| 9983 | { 472, 6, 0, 4, 1043, 0, 0, ARMOpInfoBase + 373, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // VLD1LNdAsm_16 |
| 9984 | { 471, 7, 2, 4, 337, 0, 0, ARMOpInfoBase + 341, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // UMULLv5 |
| 9985 | { 470, 9, 2, 4, 339, 0, 0, ARMOpInfoBase + 332, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // UMLALv5 |
| 9986 | { 469, 0, 0, 4, 856, 1, 4, ARMOpInfoBase + 1, 55, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // TPsoft |
| 9987 | { 468, 2, 0, 0, 851, 1, 0, ARMOpInfoBase + 371, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // TCRETURNrinotr12 |
| 9988 | { 467, 2, 0, 0, 851, 1, 0, ARMOpInfoBase + 369, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // TCRETURNri |
| 9989 | { 466, 2, 0, 0, 851, 1, 0, ARMOpInfoBase + 20, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // TCRETURNdi |
| 9990 | { 465, 1, 0, 4, 851, 1, 0, ARMOpInfoBase + 296, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TAILJMPr4 |
| 9991 | { 464, 1, 0, 4, 851, 1, 0, ARMOpInfoBase + 368, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TAILJMPr |
| 9992 | { 463, 1, 0, 4, 851, 1, 0, ARMOpInfoBase + 192, 54, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // TAILJMPd |
| 9993 | { 462, 0, 0, 4, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SpeculationBarrierSBEndBB |
| 9994 | { 461, 0, 0, 8, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SpeculationBarrierISBDSBEndBB |
| 9995 | { 460, 7, 1, 4, 4, 0, 1, ARMOpInfoBase + 167, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBSrsr |
| 9996 | { 459, 6, 1, 4, 3, 0, 1, ARMOpInfoBase + 161, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBSrsi |
| 9997 | { 458, 5, 1, 4, 2, 0, 1, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBSrr |
| 9998 | { 457, 5, 1, 4, 1, 0, 1, ARMOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // SUBSri |
| 9999 | { 456, 3, 0, 4, 850, 0, 0, ARMOpInfoBase + 365, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // SUBS_PC_LR |
| 10000 | { 455, 7, 1, 4, 939, 0, 0, ARMOpInfoBase + 351, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // STRr_preidx |
| 10001 | { 454, 7, 1, 4, 939, 0, 0, ARMOpInfoBase + 351, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // STRi_preidx |
| 10002 | { 453, 4, 0, 4, 953, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // STRT_POST |
| 10003 | { 452, 7, 1, 4, 939, 0, 0, ARMOpInfoBase + 358, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // STRH_preidx |
| 10004 | { 451, 7, 1, 4, 939, 0, 0, ARMOpInfoBase + 351, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // STRBr_preidx |
| 10005 | { 450, 7, 1, 4, 939, 0, 0, ARMOpInfoBase + 351, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // STRBi_preidx |
| 10006 | { 449, 4, 0, 4, 953, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x0ULL }, // STRBT_POST |
| 10007 | { 448, 4, 0, 64, 30, 0, 0, ARMOpInfoBase + 252, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x3ULL }, // STOREDUAL |
| 10008 | { 447, 3, 1, 0, 841, 0, 0, ARMOpInfoBase + 348, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SPACE |
| 10009 | { 446, 7, 2, 4, 337, 0, 0, ARMOpInfoBase + 341, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // SMULLv5 |
| 10010 | { 445, 9, 2, 4, 339, 0, 0, ARMOpInfoBase + 332, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // SMLALv5 |
| 10011 | { 444, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_StackAlloc |
| 10012 | { 443, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_SaveSP |
| 10013 | { 442, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_SaveRegs_Ret |
| 10014 | { 441, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_SaveRegs |
| 10015 | { 440, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_SaveLR |
| 10016 | { 439, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_SaveFRegs |
| 10017 | { 438, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_PrologEnd |
| 10018 | { 437, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_Nop_Ret |
| 10019 | { 436, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_Nop |
| 10020 | { 435, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_EpilogStart |
| 10021 | { 434, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // SEH_EpilogEnd |
| 10022 | { 433, 7, 1, 4, 4, 0, 1, ARMOpInfoBase + 167, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // RSBSrsr |
| 10023 | { 432, 6, 1, 4, 3, 0, 1, ARMOpInfoBase + 161, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // RSBSrsi |
| 10024 | { 431, 5, 1, 4, 690, 0, 1, ARMOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // RSBSri |
| 10025 | { 430, 5, 0, 4, 718, 0, 0, ARMOpInfoBase + 327, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RRXi |
| 10026 | { 429, 2, 1, 0, 720, 1, 0, ARMOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo), 0x2000ULL }, // RRX |
| 10027 | { 428, 6, 0, 4, 712, 0, 0, ARMOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RORr |
| 10028 | { 427, 6, 0, 4, 711, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RORi |
| 10029 | { 426, 5, 0, 4, 935, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // PICSTRH |
| 10030 | { 425, 5, 0, 4, 935, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // PICSTRB |
| 10031 | { 424, 5, 0, 4, 425, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // PICSTR |
| 10032 | { 423, 5, 1, 4, 901, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // PICLDRSH |
| 10033 | { 422, 5, 1, 4, 901, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // PICLDRSB |
| 10034 | { 421, 5, 1, 4, 900, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // PICLDRH |
| 10035 | { 420, 5, 1, 4, 900, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // PICLDRB |
| 10036 | { 419, 5, 1, 4, 346, 0, 0, ARMOpInfoBase + 322, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // PICLDR |
| 10037 | { 418, 5, 1, 4, 23, 0, 0, ARMOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // PICADD |
| 10038 | { 417, 5, 1, 4, 866, 0, 0, ARMOpInfoBase + 268, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // MVNCCi |
| 10039 | { 416, 3, 0, 0, 0, 0, 1, ARMOpInfoBase + 319, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MVE_MEMSETLOOPINST |
| 10040 | { 415, 3, 0, 0, 0, 0, 1, ARMOpInfoBase + 316, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // MVE_MEMCPYLOOPINST |
| 10041 | { 414, 6, 1, 4, 335, 0, 0, ARMOpInfoBase + 310, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // MULv5 |
| 10042 | { 413, 2, 0, 4, 0, 0, 0, ARMOpInfoBase + 308, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4ULL }, // MQQQQPRStore |
| 10043 | { 412, 2, 1, 4, 0, 0, 0, ARMOpInfoBase + 308, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4ULL }, // MQQQQPRLoad |
| 10044 | { 411, 2, 0, 4, 0, 0, 0, ARMOpInfoBase + 306, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x4ULL }, // MQQPRStore |
| 10045 | { 410, 2, 1, 4, 0, 0, 0, ARMOpInfoBase + 306, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4ULL }, // MQQPRLoad |
| 10046 | { 409, 2, 1, 8, 1151, 0, 0, ARMOpInfoBase + 304, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveReg), 0x40000ULL }, // MQPRCopy |
| 10047 | { 408, 2, 1, 8, 330, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // MOVi32imm |
| 10048 | { 407, 3, 1, 4, 864, 0, 0, ARMOpInfoBase + 301, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVi16_ga_pcrel |
| 10049 | { 406, 2, 1, 0, 332, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // MOV_ga_pcrel_ldr |
| 10050 | { 405, 2, 1, 0, 331, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // MOV_ga_pcrel |
| 10051 | { 404, 4, 1, 4, 689, 0, 0, ARMOpInfoBase + 297, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MOVTi16_ga_pcrel |
| 10052 | { 403, 1, 0, 4, 880, 0, 0, ARMOpInfoBase + 296, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // MOVPCRX |
| 10053 | { 402, 7, 1, 4, 327, 0, 0, ARMOpInfoBase + 289, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // MOVCCsr |
| 10054 | { 401, 6, 1, 4, 871, 0, 0, ARMOpInfoBase + 283, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL }, // MOVCCsi |
| 10055 | { 400, 5, 1, 4, 868, 0, 0, ARMOpInfoBase + 278, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL }, // MOVCCr |
| 10056 | { 399, 5, 1, 8, 329, 0, 0, ARMOpInfoBase + 273, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // MOVCCi32imm |
| 10057 | { 398, 5, 1, 4, 864, 0, 0, ARMOpInfoBase + 268, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // MOVCCi16 |
| 10058 | { 397, 5, 1, 4, 866, 0, 0, ARMOpInfoBase + 268, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL }, // MOVCCi |
| 10059 | { 396, 7, 1, 4, 336, 0, 0, ARMOpInfoBase + 261, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL }, // MLAv5 |
| 10060 | { 395, 5, 2, 0, 1040, 0, 0, ARMOpInfoBase + 256, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::Variadic), 0x0ULL }, // MEMCPY |
| 10061 | { 394, 2, 1, 0, 713, 0, 1, ARMOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo), 0x2000ULL }, // LSRs1 |
| 10062 | { 393, 6, 0, 4, 712, 0, 0, ARMOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LSRr |
| 10063 | { 392, 6, 0, 4, 873, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LSRi |
| 10064 | { 391, 6, 0, 4, 712, 0, 0, ARMOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LSLr |
| 10065 | { 390, 6, 0, 4, 873, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LSLi |
| 10066 | { 389, 4, 1, 64, 12, 0, 0, ARMOpInfoBase + 252, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x3ULL }, // LOADDUAL |
| 10067 | { 388, 4, 1, 4, 1, 0, 0, ARMOpInfoBase + 248, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LEApcrelJT |
| 10068 | { 387, 4, 1, 4, 1, 0, 0, ARMOpInfoBase + 248, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LEApcrel |
| 10069 | { 386, 4, 1, 4, 931, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDRT_POST |
| 10070 | { 385, 4, 1, 4, 349, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x0ULL }, // LDRSHTii |
| 10071 | { 384, 4, 1, 4, 349, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x0ULL }, // LDRSBTii |
| 10072 | { 383, 2, 1, 0, 455, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // LDRLIT_ga_pcrel_ldr |
| 10073 | { 382, 2, 1, 0, 454, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // LDRLIT_ga_pcrel |
| 10074 | { 381, 2, 1, 0, 453, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LDRLIT_ga_abs |
| 10075 | { 380, 4, 1, 4, 407, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x0ULL }, // LDRHTii |
| 10076 | { 379, 4, 1, 4, 899, 0, 0, ARMOpInfoBase + 244, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDRConstPool |
| 10077 | { 378, 4, 1, 4, 686, 0, 0, ARMOpInfoBase + 240, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // LDRBT_POST |
| 10078 | { 377, 5, 1, 4, 422, 0, 0, ARMOpInfoBase + 235, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDMIA_RET |
| 10079 | { 376, 2, 0, 34, 0, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // KCFI_CHECK_Thumb2 |
| 10080 | { 375, 2, 0, 38, 0, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // KCFI_CHECK_Thumb1 |
| 10081 | { 374, 2, 0, 40, 0, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // KCFI_CHECK_ARM |
| 10082 | { 373, 3, 0, 0, 1039, 0, 0, ARMOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMPTABLE_TBH |
| 10083 | { 372, 3, 0, 0, 1039, 0, 0, ARMOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMPTABLE_TBB |
| 10084 | { 371, 3, 0, 0, 1039, 0, 0, ARMOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMPTABLE_INSTS |
| 10085 | { 370, 3, 0, 0, 1039, 0, 0, ARMOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // JUMPTABLE_ADDRS |
| 10086 | { 369, 0, 0, 0, 1037, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Int_eh_sjlj_setup_dispatch |
| 10087 | { 368, 2, 0, 20, 1037, 0, 15, ARMOpInfoBase + 190, 39, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Int_eh_sjlj_setjmp_nofp |
| 10088 | { 367, 2, 0, 20, 1037, 0, 31, ARMOpInfoBase + 190, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Int_eh_sjlj_setjmp |
| 10089 | { 366, 2, 0, 0, 1037, 0, 3, ARMOpInfoBase + 190, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Int_eh_sjlj_longjmp |
| 10090 | { 365, 0, 0, 0, 1037, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Int_eh_sjlj_dispatchsetup |
| 10091 | { 364, 2, 0, 4, 457, 0, 0, ARMOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ITasm |
| 10092 | { 363, 4, 0, 0, 1059, 0, 1, ARMOpInfoBase + 231, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // COPY_STRUCT_BYVAL_I32 |
| 10093 | { 362, 3, 0, 0, 841, 0, 0, ARMOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CONSTPOOL_ENTRY |
| 10094 | { 361, 5, 2, 0, 1038, 0, 0, ARMOpInfoBase + 221, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMP_SWAP_8 |
| 10095 | { 360, 5, 2, 0, 1038, 0, 0, ARMOpInfoBase + 226, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMP_SWAP_64 |
| 10096 | { 359, 5, 2, 0, 1038, 0, 0, ARMOpInfoBase + 221, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMP_SWAP_32 |
| 10097 | { 358, 5, 2, 0, 1038, 0, 0, ARMOpInfoBase + 221, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CMP_SWAP_16 |
| 10098 | { 357, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // CLEANUPRET |
| 10099 | { 356, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 219, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // CATCHRET |
| 10100 | { 355, 1, 0, 8, 851, 1, 1, ARMOpInfoBase + 206, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // BX_CALL |
| 10101 | { 354, 2, 0, 4, 860, 0, 0, ARMOpInfoBase + 217, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // BR_JTr |
| 10102 | { 353, 4, 0, 4, 862, 0, 0, ARMOpInfoBase + 213, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // BR_JTm_rs |
| 10103 | { 352, 3, 0, 4, 862, 0, 0, ARMOpInfoBase + 210, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // BR_JTm_i12 |
| 10104 | { 351, 3, 0, 4, 859, 0, 0, ARMOpInfoBase + 207, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // BR_JTadd |
| 10105 | { 350, 1, 0, 8, 867, 1, 1, ARMOpInfoBase + 206, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // BMOVPCRX_CALL |
| 10106 | { 349, 1, 0, 8, 867, 1, 1, ARMOpInfoBase + 192, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // BMOVPCB_CALL |
| 10107 | { 348, 2, 0, 4, 6, 1, 1, ARMOpInfoBase + 204, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // BL_PUSHLR |
| 10108 | { 347, 1, 0, 4, 857, 1, 1, ARMOpInfoBase + 203, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // BLX_pred_noip |
| 10109 | { 346, 1, 0, 4, 857, 1, 1, ARMOpInfoBase + 203, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // BLX_noip |
| 10110 | { 345, 6, 0, 0, 858, 0, 1, ARMOpInfoBase + 197, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BCCi64 |
| 10111 | { 344, 4, 0, 0, 858, 0, 1, ARMOpInfoBase + 193, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // BCCZi64 |
| 10112 | { 343, 1, 0, 4, 851, 0, 0, ARMOpInfoBase + 192, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL }, // B |
| 10113 | { 342, 2, 1, 0, 5, 0, 1, ARMOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo), 0x2000ULL }, // ASRs1 |
| 10114 | { 341, 6, 0, 4, 712, 0, 0, ARMOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ASRr |
| 10115 | { 340, 6, 0, 4, 711, 0, 0, ARMOpInfoBase + 178, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ASRi |
| 10116 | { 339, 4, 0, 0, 1037, 1, 1, ARMOpInfoBase + 174, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADJCALLSTACKUP |
| 10117 | { 338, 4, 0, 0, 1037, 1, 1, ARMOpInfoBase + 174, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ADJCALLSTACKDOWN |
| 10118 | { 337, 7, 1, 4, 705, 0, 1, ARMOpInfoBase + 167, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // ADDSrsr |
| 10119 | { 336, 6, 1, 4, 700, 0, 1, ARMOpInfoBase + 161, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // ADDSrsi |
| 10120 | { 335, 5, 1, 4, 697, 0, 1, ARMOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // ADDSrr |
| 10121 | { 334, 5, 1, 4, 690, 0, 1, ARMOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // ADDSri |
| 10122 | { 333, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UBFX |
| 10123 | { 332, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SBFX |
| 10124 | { 331, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMIN |
| 10125 | { 330, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_UMAX |
| 10126 | { 329, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMIN |
| 10127 | { 328, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SMAX |
| 10128 | { 327, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_XOR |
| 10129 | { 326, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_OR |
| 10130 | { 325, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_AND |
| 10131 | { 324, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_MUL |
| 10132 | { 323, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_ADD |
| 10133 | { 322, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM |
| 10134 | { 321, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM |
| 10135 | { 320, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMINIMUM |
| 10136 | { 319, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAXIMUM |
| 10137 | { 318, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMIN |
| 10138 | { 317, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMAX |
| 10139 | { 316, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FMUL |
| 10140 | { 315, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_FADD |
| 10141 | { 314, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL |
| 10142 | { 313, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECREDUCE_SEQ_FADD |
| 10143 | { 312, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_UBSANTRAP |
| 10144 | { 311, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DEBUGTRAP |
| 10145 | { 310, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_TRAP |
| 10146 | { 309, 3, 0, 0, 0, 0, 0, ARMOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET_INLINE |
| 10147 | { 308, 3, 0, 0, 0, 0, 0, ARMOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_BZERO |
| 10148 | { 307, 4, 0, 0, 0, 0, 0, ARMOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMSET |
| 10149 | { 306, 4, 0, 0, 0, 0, 0, ARMOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMMOVE |
| 10150 | { 305, 3, 0, 0, 0, 0, 0, ARMOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY_INLINE |
| 10151 | { 304, 4, 0, 0, 0, 0, 0, ARMOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_MEMCPY |
| 10152 | { 303, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER |
| 10153 | { 302, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER |
| 10154 | { 301, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMPS |
| 10155 | { 300, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FCMP |
| 10156 | { 299, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FLDEXP |
| 10157 | { 298, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSQRT |
| 10158 | { 297, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMA |
| 10159 | { 296, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FREM |
| 10160 | { 295, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FDIV |
| 10161 | { 294, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FMUL |
| 10162 | { 293, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FSUB |
| 10163 | { 292, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STRICT_FADD |
| 10164 | { 291, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKRESTORE |
| 10165 | { 290, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_STACKSAVE |
| 10166 | { 289, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_DYN_STACKALLOC |
| 10167 | { 288, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_JUMP_TABLE |
| 10168 | { 287, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BLOCK_ADDR |
| 10169 | { 286, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ADDRSPACE_CAST |
| 10170 | { 285, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEARBYINT |
| 10171 | { 284, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRINT |
| 10172 | { 283, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFLOOR |
| 10173 | { 282, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSQRT |
| 10174 | { 281, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTANH |
| 10175 | { 280, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINH |
| 10176 | { 279, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOSH |
| 10177 | { 278, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN2 |
| 10178 | { 277, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FATAN |
| 10179 | { 276, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FASIN |
| 10180 | { 275, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FACOS |
| 10181 | { 274, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FTAN |
| 10182 | { 273, 3, 2, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSINCOS |
| 10183 | { 272, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSIN |
| 10184 | { 271, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOS |
| 10185 | { 270, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCEIL |
| 10186 | { 269, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMULH |
| 10187 | { 268, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_CLMUL |
| 10188 | { 267, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITREVERSE |
| 10189 | { 266, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BSWAP |
| 10190 | { 265, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTPOP |
| 10191 | { 264, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLS |
| 10192 | { 263, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ_ZERO_POISON |
| 10193 | { 262, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTLZ |
| 10194 | { 261, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ_ZERO_POISON |
| 10195 | { 260, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CTTZ |
| 10196 | { 259, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VECTOR_COMPRESS |
| 10197 | { 258, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_STEP_VECTOR |
| 10198 | { 257, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SPLAT_VECTOR |
| 10199 | { 256, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHUFFLE_VECTOR |
| 10200 | { 255, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_VECTOR_ELT |
| 10201 | { 254, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_VECTOR_ELT |
| 10202 | { 253, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT_SUBVECTOR |
| 10203 | { 252, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT_SUBVECTOR |
| 10204 | { 251, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_VSCALE |
| 10205 | { 250, 3, 0, 0, 0, 0, 0, ARMOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRJT |
| 10206 | { 249, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BR |
| 10207 | { 248, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LLROUND |
| 10208 | { 247, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LROUND |
| 10209 | { 246, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ABS |
| 10210 | { 245, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMAX |
| 10211 | { 244, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMIN |
| 10212 | { 243, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMAX |
| 10213 | { 242, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMIN |
| 10214 | { 241, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRMASK |
| 10215 | { 240, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTR_ADD |
| 10216 | { 239, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_ROUNDING |
| 10217 | { 238, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_ROUNDING |
| 10218 | { 237, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPMODE |
| 10219 | { 236, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPMODE |
| 10220 | { 235, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPMODE |
| 10221 | { 234, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_RESET_FPENV |
| 10222 | { 233, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_SET_FPENV |
| 10223 | { 232, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_GET_FPENV |
| 10224 | { 231, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUMNUM |
| 10225 | { 230, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUMNUM |
| 10226 | { 229, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXIMUM |
| 10227 | { 228, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINIMUM |
| 10228 | { 227, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM_IEEE |
| 10229 | { 226, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM_IEEE |
| 10230 | { 225, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMAXNUM |
| 10231 | { 224, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMINNUM |
| 10232 | { 223, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCANONICALIZE |
| 10233 | { 222, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IS_FPCLASS |
| 10234 | { 221, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCOPYSIGN |
| 10235 | { 220, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FABS |
| 10236 | { 219, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI_SAT |
| 10237 | { 218, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI_SAT |
| 10238 | { 217, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UITOFP |
| 10239 | { 216, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SITOFP |
| 10240 | { 215, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOUI |
| 10241 | { 214, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTOSI |
| 10242 | { 213, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPTRUNC |
| 10243 | { 212, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPEXT |
| 10244 | { 211, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FNEG |
| 10245 | { 210, 3, 2, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FFREXP |
| 10246 | { 209, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLDEXP |
| 10247 | { 208, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG10 |
| 10248 | { 207, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG2 |
| 10249 | { 206, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FLOG |
| 10250 | { 205, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP10 |
| 10251 | { 204, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP2 |
| 10252 | { 203, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FEXP |
| 10253 | { 202, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOWI |
| 10254 | { 201, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FPOW |
| 10255 | { 200, 3, 2, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMODF |
| 10256 | { 199, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREM |
| 10257 | { 198, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FDIV |
| 10258 | { 197, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMAD |
| 10259 | { 196, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FMA |
| 10260 | { 195, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FMUL |
| 10261 | { 194, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSUB |
| 10262 | { 193, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_FADD |
| 10263 | { 192, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIXSAT |
| 10264 | { 191, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIXSAT |
| 10265 | { 190, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVFIX |
| 10266 | { 189, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVFIX |
| 10267 | { 188, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIXSAT |
| 10268 | { 187, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIXSAT |
| 10269 | { 186, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULFIX |
| 10270 | { 185, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULFIX |
| 10271 | { 184, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSHLSAT |
| 10272 | { 183, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USHLSAT |
| 10273 | { 182, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBSAT |
| 10274 | { 181, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBSAT |
| 10275 | { 180, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDSAT |
| 10276 | { 179, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDSAT |
| 10277 | { 178, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULH |
| 10278 | { 177, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULH |
| 10279 | { 176, 4, 2, 0, 0, 0, 0, ARMOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SMULO |
| 10280 | { 175, 4, 2, 0, 0, 0, 0, ARMOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UMULO |
| 10281 | { 174, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBE |
| 10282 | { 173, 4, 2, 0, 0, 0, 0, ARMOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SSUBO |
| 10283 | { 172, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SADDE |
| 10284 | { 171, 4, 2, 0, 0, 0, 0, ARMOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_SADDO |
| 10285 | { 170, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBE |
| 10286 | { 169, 4, 2, 0, 0, 0, 0, ARMOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_USUBO |
| 10287 | { 168, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UADDE |
| 10288 | { 167, 4, 2, 0, 0, 0, 0, ARMOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_UADDO |
| 10289 | { 166, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SELECT |
| 10290 | { 165, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UCMP |
| 10291 | { 164, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SCMP |
| 10292 | { 163, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCMP |
| 10293 | { 162, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ICMP |
| 10294 | { 161, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTL |
| 10295 | { 160, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ROTR |
| 10296 | { 159, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHR |
| 10297 | { 158, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FSHL |
| 10298 | { 157, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASHR |
| 10299 | { 156, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_LSHR |
| 10300 | { 155, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SHL |
| 10301 | { 154, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ZEXT |
| 10302 | { 153, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT_INREG |
| 10303 | { 152, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SEXT |
| 10304 | { 151, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VAARG |
| 10305 | { 150, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_VASTART |
| 10306 | { 149, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FCONSTANT |
| 10307 | { 148, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT |
| 10308 | { 147, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_USAT_U |
| 10309 | { 146, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_U |
| 10310 | { 145, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC_SSAT_S |
| 10311 | { 144, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_TRUNC |
| 10312 | { 143, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ANYEXT |
| 10313 | { 142, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 10314 | { 141, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT |
| 10315 | { 140, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS |
| 10316 | { 139, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_INTRINSIC |
| 10317 | { 138, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_INVOKE_REGION_START |
| 10318 | { 137, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRINDIRECT |
| 10319 | { 136, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // G_BRCOND |
| 10320 | { 135, 4, 0, 0, 0, 0, 0, ARMOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_PREFETCH |
| 10321 | { 134, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_FENCE |
| 10322 | { 133, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_SAT |
| 10323 | { 132, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_USUB_COND |
| 10324 | { 131, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP |
| 10325 | { 130, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP |
| 10326 | { 129, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM |
| 10327 | { 128, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM |
| 10328 | { 127, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMINIMUM |
| 10329 | { 126, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM |
| 10330 | { 125, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMIN |
| 10331 | { 124, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FMAX |
| 10332 | { 123, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FSUB |
| 10333 | { 122, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_FADD |
| 10334 | { 121, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMIN |
| 10335 | { 120, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_UMAX |
| 10336 | { 119, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MIN |
| 10337 | { 118, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_MAX |
| 10338 | { 117, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XOR |
| 10339 | { 116, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_OR |
| 10340 | { 115, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_NAND |
| 10341 | { 114, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_AND |
| 10342 | { 113, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_SUB |
| 10343 | { 112, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_ADD |
| 10344 | { 111, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMICRMW_XCHG |
| 10345 | { 110, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG |
| 10346 | { 109, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 10347 | { 108, 5, 1, 0, 0, 0, 0, ARMOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_INDEXED_STORE |
| 10348 | { 107, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_FPTRUNCSTORE |
| 10349 | { 106, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // G_STORE |
| 10350 | { 105, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_ZEXTLOAD |
| 10351 | { 104, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_SEXTLOAD |
| 10352 | { 103, 5, 2, 0, 0, 0, 0, ARMOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_INDEXED_LOAD |
| 10353 | { 102, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_FPEXTLOAD |
| 10354 | { 101, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_ZEXTLOAD |
| 10355 | { 100, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_SEXTLOAD |
| 10356 | { 99, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // G_LOAD |
| 10357 | { 98, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READSTEADYCOUNTER |
| 10358 | { 97, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // G_READCYCLECOUNTER |
| 10359 | { 96, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN |
| 10360 | { 95, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LLRINT |
| 10361 | { 94, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_LRINT |
| 10362 | { 93, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_ROUND |
| 10363 | { 92, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_TRUNC |
| 10364 | { 91, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND |
| 10365 | { 90, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER |
| 10366 | { 89, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FREEZE |
| 10367 | { 88, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_BITCAST |
| 10368 | { 87, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INTTOPTR |
| 10369 | { 86, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRTOINT |
| 10370 | { 85, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_CONCAT_VECTORS |
| 10371 | { 84, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR_TRUNC |
| 10372 | { 83, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_BUILD_VECTOR |
| 10373 | { 82, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_MERGE_VALUES |
| 10374 | { 81, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_INSERT |
| 10375 | { 80, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_UNMERGE_VALUES |
| 10376 | { 79, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_EXTRACT |
| 10377 | { 78, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_CONSTANT_POOL |
| 10378 | { 77, 5, 1, 0, 0, 0, 0, ARMOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE |
| 10379 | { 76, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_GLOBAL_VALUE |
| 10380 | { 75, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_FRAME_INDEX |
| 10381 | { 74, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // G_PHI |
| 10382 | { 73, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_IMPLICIT_DEF |
| 10383 | { 72, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGCEIL |
| 10384 | { 71, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SAVGFLOOR |
| 10385 | { 70, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGCEIL |
| 10386 | { 69, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UAVGFLOOR |
| 10387 | { 68, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDU |
| 10388 | { 67, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ABDS |
| 10389 | { 66, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_XOR |
| 10390 | { 65, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_OR |
| 10391 | { 64, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_AND |
| 10392 | { 63, 4, 2, 0, 0, 0, 0, ARMOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIVREM |
| 10393 | { 62, 4, 2, 0, 0, 0, 0, ARMOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIVREM |
| 10394 | { 61, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UREM |
| 10395 | { 60, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SREM |
| 10396 | { 59, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_UDIV |
| 10397 | { 58, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SDIV |
| 10398 | { 57, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_MUL |
| 10399 | { 56, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_SUB |
| 10400 | { 55, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // G_ADD |
| 10401 | { 54, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ALIGN |
| 10402 | { 53, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_ZEXT |
| 10403 | { 52, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // G_ASSERT_SEXT |
| 10404 | { 51, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE |
| 10405 | { 50, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP |
| 10406 | { 49, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR |
| 10407 | { 48, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY |
| 10408 | { 47, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // RELOC_NONE |
| 10409 | { 46, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO |
| 10410 | { 45, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // MEMBARRIER |
| 10411 | { 44, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // FAKE_USE |
| 10412 | { 43, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // ICALL_BRANCH_FUNNEL |
| 10413 | { 42, 3, 0, 0, 0, 0, 0, ARMOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_19977 |
| 10414 | { 41, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_19976 |
| 10415 | { 40, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_TAIL_CALL |
| 10416 | { 39, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT |
| 10417 | { 38, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_RET |
| 10418 | { 37, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER |
| 10419 | { 36, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHABLE_OP |
| 10420 | { 35, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FAULTING_OP |
| 10421 | { 34, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // LOCAL_ESCAPE |
| 10422 | { 33, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STATEPOINT |
| 10423 | { 32, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // anonymous_19975 |
| 10424 | { 31, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PREALLOCATED_SETUP |
| 10425 | { 30, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // anonymous_14348 |
| 10426 | { 29, 6, 1, 0, 0, 0, 0, ARMOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PATCHPOINT |
| 10427 | { 28, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // FENTRY_CALL |
| 10428 | { 27, 2, 0, 0, 0, 0, 0, ARMOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // STACKMAP |
| 10429 | { 26, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // ARITH_FENCE |
| 10430 | { 25, 4, 0, 0, 0, 0, 0, ARMOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // PSEUDO_PROBE |
| 10431 | { 24, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_END |
| 10432 | { 23, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // LIFETIME_START |
| 10433 | { 22, 0, 0, 0, 1218, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // BUNDLE |
| 10434 | { 21, 3, 1, 0, 1058, 0, 0, ARMOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_LANEMASK |
| 10435 | { 20, 2, 1, 0, 679, 0, 0, ARMOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY |
| 10436 | { 19, 2, 1, 0, 0, 0, 0, ARMOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // REG_SEQUENCE |
| 10437 | { 18, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // DBG_LABEL |
| 10438 | { 17, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_PHI |
| 10439 | { 16, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_INSTR_REF |
| 10440 | { 15, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE_LIST |
| 10441 | { 14, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // DBG_VALUE |
| 10442 | { 13, 3, 1, 0, 1058, 0, 0, ARMOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // COPY_TO_REGCLASS |
| 10443 | { 12, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // SUBREG_TO_REG |
| 10444 | { 11, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INIT_UNDEF |
| 10445 | { 10, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // IMPLICIT_DEF |
| 10446 | { 9, 4, 1, 0, 0, 0, 0, ARMOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // INSERT_SUBREG |
| 10447 | { 8, 3, 1, 0, 0, 0, 0, ARMOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // EXTRACT_SUBREG |
| 10448 | { 7, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // KILL |
| 10449 | { 6, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // ANNOTATION_LABEL |
| 10450 | { 5, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // GC_LABEL |
| 10451 | { 4, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // EH_LABEL |
| 10452 | { 3, 1, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // CFI_INSTRUCTION |
| 10453 | { 2, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // INLINEASM_BR |
| 10454 | { 1, 0, 0, 0, 0, 0, 0, ARMOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // INLINEASM |
| 10455 | { 0, 1, 1, 0, 0, 0, 0, ARMOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // PHI |
| 10456 | }, { |
| 10457 | /* 0 */ |
| 10458 | /* 0 */ ARM::CPSR, |
| 10459 | /* 1 */ ARM::SP, ARM::SP, |
| 10460 | /* 3 */ ARM::SP, ARM::LR, |
| 10461 | /* 5 */ ARM::R7, ARM::LR, ARM::SP, |
| 10462 | /* 8 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, |
| 10463 | /* 39 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, |
| 10464 | /* 54 */ ARM::SP, |
| 10465 | /* 55 */ ARM::SP, ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, |
| 10466 | /* 60 */ ARM::R4, ARM::R4, ARM::R12, ARM::LR, ARM::SP, ARM::CPSR, |
| 10467 | /* 66 */ ARM::CPSR, ARM::CPSR, |
| 10468 | /* 68 */ ARM::LR, |
| 10469 | /* 69 */ ARM::FPSCR_RM, |
| 10470 | /* 70 */ ARM::PC, |
| 10471 | /* 71 */ ARM::FPSCR_NZCV, ARM::CPSR, |
| 10472 | /* 73 */ ARM::VPR, |
| 10473 | /* 74 */ ARM::FPSCR_RM, ARM::FPSCR_NZCV, |
| 10474 | /* 76 */ ARM::FPSCR, |
| 10475 | /* 77 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, |
| 10476 | /* 96 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, |
| 10477 | /* 131 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, |
| 10478 | /* 153 */ ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, |
| 10479 | /* 191 */ ARM::R12, ARM::LR, ARM::SP, |
| 10480 | /* 194 */ ARM::ITSTATE, |
| 10481 | /* 195 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, |
| 10482 | /* 222 */ ARM::LR, ARM::SP, ARM::R12, |
| 10483 | /* 225 */ ARM::R11, ARM::LR, ARM::SP, |
| 10484 | /* 228 */ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, |
| 10485 | }, { |
| 10486 | 0 |
| 10487 | }, { |
| 10488 | /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10489 | /* 1 */ |
| 10490 | /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10491 | /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10492 | /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10493 | /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10494 | /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10495 | /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10496 | /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, |
| 10497 | /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10498 | /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10499 | /* 28 */ { ARM::arm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, |
| 10500 | /* 29 */ { ARM::arm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10501 | /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10502 | /* 34 */ { ARM::arm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10503 | /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::arm_ptr_rc, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10504 | /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10505 | /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10506 | /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10507 | /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10508 | /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10509 | /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10510 | /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10511 | /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10512 | /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10513 | /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10514 | /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10515 | /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10516 | /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10517 | /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10518 | /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10519 | /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10520 | /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 }, |
| 10521 | /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10522 | /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10523 | /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10524 | /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10525 | /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10526 | /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10527 | /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10528 | /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10529 | /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 10530 | /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 10531 | /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10532 | /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10533 | /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 10534 | /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 10535 | /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 10536 | /* 151 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10537 | /* 156 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10538 | /* 161 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10539 | /* 167 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10540 | /* 174 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10541 | /* 178 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10542 | /* 184 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10543 | /* 190 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10544 | /* 192 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10545 | /* 193 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10546 | /* 197 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10547 | /* 203 */ { ARM::GPRnoipRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10548 | /* 204 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10549 | /* 206 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10550 | /* 207 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10551 | /* 210 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10552 | /* 213 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10553 | /* 217 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10554 | /* 219 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10555 | /* 221 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10556 | /* 226 */ { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10557 | /* 231 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10558 | /* 235 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10559 | /* 240 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10560 | /* 244 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10561 | /* 248 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10562 | /* 252 */ { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10563 | /* 256 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10564 | /* 261 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10565 | /* 268 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10566 | /* 273 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10567 | /* 278 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10568 | /* 283 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10569 | /* 289 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10570 | /* 296 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10571 | /* 297 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10572 | /* 301 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10573 | /* 304 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10574 | /* 306 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10575 | /* 308 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10576 | /* 310 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10577 | /* 316 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10578 | /* 319 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10579 | /* 322 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10580 | /* 327 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10581 | /* 332 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10582 | /* 341 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10583 | /* 348 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10584 | /* 351 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10585 | /* 358 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10586 | /* 365 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10587 | /* 368 */ { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10588 | /* 369 */ { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10589 | /* 371 */ { ARM::tcGPRnotr12RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10590 | /* 373 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10591 | /* 379 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10592 | /* 386 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10593 | /* 391 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10594 | /* 397 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10595 | /* 398 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10596 | /* 403 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10597 | /* 408 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10598 | /* 409 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10599 | /* 414 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10600 | /* 419 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10601 | /* 424 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10602 | /* 430 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10603 | /* 432 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10604 | /* 435 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10605 | /* 437 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10606 | /* 440 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10607 | /* 444 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10608 | /* 446 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10609 | /* 449 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10610 | /* 453 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10611 | /* 456 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10612 | /* 459 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10613 | /* 465 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10614 | /* 470 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10615 | /* 475 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10616 | /* 480 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10617 | /* 485 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10618 | /* 491 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10619 | /* 495 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10620 | /* 500 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10621 | /* 506 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10622 | /* 512 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10623 | /* 515 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10624 | /* 519 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10625 | /* 522 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10626 | /* 525 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10627 | /* 528 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10628 | /* 529 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnoipRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10629 | /* 532 */ { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 10630 | /* 536 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10631 | /* 539 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10632 | /* 541 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10633 | /* 544 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10634 | /* 547 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10635 | /* 552 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10636 | /* 557 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10637 | /* 562 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10638 | /* 566 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10639 | /* 571 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10640 | /* 574 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10641 | /* 578 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10642 | /* 583 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10643 | /* 586 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10644 | /* 588 */ { ARM::tGPRwithpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 10645 | /* 592 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10646 | /* 598 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10647 | /* 605 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10648 | /* 613 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10649 | /* 621 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10650 | /* 624 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10651 | /* 626 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10652 | /* 631 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10653 | /* 636 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10654 | /* 640 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10655 | /* 644 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10656 | /* 648 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10657 | /* 654 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10658 | /* 657 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10659 | /* 663 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10660 | /* 666 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10661 | /* 672 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10662 | /* 676 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10663 | /* 683 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10664 | /* 687 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10665 | /* 694 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10666 | /* 699 */ { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10667 | /* 707 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10668 | /* 712 */ { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10669 | /* 720 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10670 | /* 724 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10671 | /* 728 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10672 | /* 735 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10673 | /* 738 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10674 | /* 741 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10675 | /* 748 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10676 | /* 753 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10677 | /* 758 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10678 | /* 766 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10679 | /* 770 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10680 | /* 774 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10681 | /* 782 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10682 | /* 788 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10683 | /* 794 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10684 | /* 803 */ { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10685 | /* 808 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10686 | /* 813 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10687 | /* 822 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10688 | /* 830 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10689 | /* 836 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10690 | /* 840 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10691 | /* 845 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10692 | /* 851 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10693 | /* 854 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10694 | /* 857 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10695 | /* 861 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10696 | /* 865 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10697 | /* 869 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10698 | /* 873 */ { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10699 | /* 877 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10700 | /* 881 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10701 | /* 885 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10702 | /* 891 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10703 | /* 897 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10704 | /* 904 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10705 | /* 910 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10706 | /* 915 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10707 | /* 921 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10708 | /* 928 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10709 | /* 936 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10710 | /* 942 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10711 | /* 949 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10712 | /* 956 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10713 | /* 962 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10714 | /* 970 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10715 | /* 976 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10716 | /* 983 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10717 | /* 988 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10718 | /* 995 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10719 | /* 1001 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10720 | /* 1006 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10721 | /* 1011 */ { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10722 | /* 1016 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10723 | /* 1022 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10724 | /* 1029 */ { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10725 | /* 1037 */ { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10726 | /* 1043 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10727 | /* 1050 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10728 | /* 1055 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10729 | /* 1058 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10730 | /* 1062 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10731 | /* 1066 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10732 | /* 1070 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10733 | /* 1077 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10734 | /* 1084 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10735 | /* 1089 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10736 | /* 1097 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10737 | /* 1104 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10738 | /* 1111 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10739 | /* 1117 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10740 | /* 1126 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10741 | /* 1134 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10742 | /* 1142 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10743 | /* 1148 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10744 | /* 1154 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10745 | /* 1159 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10746 | /* 1166 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10747 | /* 1172 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10748 | /* 1180 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10749 | /* 1188 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10750 | /* 1196 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10751 | /* 1204 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10752 | /* 1211 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10753 | /* 1218 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10754 | /* 1223 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10755 | /* 1229 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10756 | /* 1236 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10757 | /* 1244 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10758 | /* 1250 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10759 | /* 1259 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10760 | /* 1266 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10761 | /* 1273 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10762 | /* 1276 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, |
| 10763 | /* 1280 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10764 | /* 1283 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, |
| 10765 | /* 1287 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10766 | /* 1293 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10767 | /* 1300 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10768 | /* 1306 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10769 | /* 1312 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10770 | /* 1319 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10771 | /* 1325 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10772 | /* 1332 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10773 | /* 1338 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10774 | /* 1345 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10775 | /* 1351 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10776 | /* 1360 */ { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10777 | /* 1367 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10778 | /* 1372 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10779 | /* 1380 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10780 | /* 1387 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10781 | /* 1393 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10782 | /* 1399 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10783 | /* 1406 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10784 | /* 1411 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10785 | /* 1417 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10786 | /* 1421 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10787 | /* 1425 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10788 | /* 1432 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10789 | /* 1439 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10790 | /* 1445 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10791 | /* 1452 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, |
| 10792 | /* 1458 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10793 | /* 1466 */ { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10794 | /* 1468 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, |
| 10795 | /* 1471 */ { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10796 | /* 1473 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, |
| 10797 | /* 1476 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10798 | /* 1482 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10799 | /* 1488 */ { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, |
| 10800 | /* 1495 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10801 | /* 1502 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10802 | /* 1505 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10803 | /* 1508 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10804 | /* 1514 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10805 | /* 1516 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
| 10806 | /* 1519 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10807 | /* 1524 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10808 | /* 1530 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10809 | /* 1536 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10810 | /* 1545 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10811 | /* 1553 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10812 | /* 1560 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10813 | /* 1566 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10814 | /* 1571 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10815 | /* 1576 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10816 | /* 1581 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10817 | /* 1588 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10818 | /* 1595 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10819 | /* 1601 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10820 | /* 1609 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10821 | /* 1615 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10822 | /* 1622 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10823 | /* 1627 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10824 | /* 1633 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10825 | /* 1638 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10826 | /* 1646 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10827 | /* 1652 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10828 | /* 1658 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10829 | /* 1664 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10830 | /* 1669 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10831 | /* 1674 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10832 | /* 1679 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10833 | /* 1683 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10834 | /* 1687 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10835 | /* 1691 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10836 | /* 1695 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10837 | /* 1700 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10838 | /* 1705 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10839 | /* 1710 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10840 | /* 1715 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10841 | /* 1720 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10842 | /* 1725 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10843 | /* 1730 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10844 | /* 1736 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10845 | /* 1742 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10846 | /* 1746 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10847 | /* 1750 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10848 | /* 1755 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10849 | /* 1761 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10850 | /* 1767 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10851 | /* 1772 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10852 | /* 1778 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10853 | /* 1784 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10854 | /* 1787 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10855 | /* 1790 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10856 | /* 1793 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10857 | /* 1795 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10858 | /* 1797 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10859 | /* 1799 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10860 | /* 1801 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10861 | /* 1806 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10862 | /* 1810 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10863 | /* 1814 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10864 | /* 1819 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10865 | /* 1824 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10866 | /* 1828 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10867 | /* 1832 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10868 | /* 1836 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10869 | /* 1841 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10870 | /* 1847 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10871 | /* 1853 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10872 | /* 1859 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10873 | /* 1862 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10874 | /* 1866 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10875 | /* 1869 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10876 | /* 1873 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10877 | /* 1879 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10878 | /* 1882 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10879 | /* 1885 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10880 | /* 1890 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10881 | /* 1893 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10882 | /* 1899 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10883 | /* 1906 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10884 | /* 1911 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10885 | /* 1917 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10886 | /* 1924 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10887 | /* 1931 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10888 | /* 1940 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10889 | /* 1947 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10890 | /* 1956 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10891 | /* 1961 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10892 | /* 1967 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10893 | /* 1974 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10894 | /* 1980 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10895 | /* 1988 */ { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10896 | /* 1993 */ { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10897 | /* 1999 */ { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10898 | /* 2006 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10899 | /* 2012 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10900 | /* 2019 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10901 | /* 2027 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10902 | /* 2036 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10903 | /* 2047 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10904 | /* 2054 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10905 | /* 2063 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10906 | /* 2070 */ { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10907 | /* 2077 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10908 | /* 2086 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10909 | /* 2097 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10910 | /* 2110 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10911 | /* 2117 */ { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10912 | /* 2126 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10913 | /* 2134 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(4) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10914 | /* 2144 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10915 | /* 2157 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(4) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10916 | /* 2172 */ { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10917 | /* 2176 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10918 | /* 2181 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10919 | /* 2186 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10920 | /* 2190 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10921 | /* 2195 */ { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10922 | /* 2200 */ { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10923 | /* 2206 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10924 | /* 2211 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10925 | /* 2217 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 10926 | /* 2221 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10927 | /* 2228 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10928 | /* 2235 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10929 | /* 2242 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10930 | /* 2249 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10931 | /* 2256 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10932 | /* 2263 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10933 | /* 2268 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10934 | /* 2272 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10935 | /* 2276 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10936 | /* 2281 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10937 | /* 2287 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10938 | /* 2291 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10939 | /* 2295 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10940 | /* 2301 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10941 | /* 2305 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10942 | /* 2309 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10943 | /* 2313 */ { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10944 | /* 2317 */ { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10945 | /* 2321 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10946 | /* 2327 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10947 | /* 2333 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10948 | /* 2339 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10949 | /* 2345 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10950 | /* 2351 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10951 | /* 2357 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10952 | /* 2362 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10953 | /* 2367 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10954 | /* 2372 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10955 | /* 2377 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 10956 | /* 2379 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10957 | /* 2385 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10958 | /* 2391 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10959 | /* 2397 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10960 | /* 2402 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10961 | /* 2407 */ { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10962 | /* 2411 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10963 | /* 2417 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10964 | /* 2423 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10965 | /* 2429 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10966 | /* 2437 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10967 | /* 2443 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10968 | /* 2451 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10969 | /* 2456 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10970 | /* 2461 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10971 | /* 2467 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10972 | /* 2474 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10973 | /* 2480 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10974 | /* 2487 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10975 | /* 2492 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10976 | /* 2497 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10977 | /* 2504 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10978 | /* 2510 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10979 | /* 2517 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10980 | /* 2524 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10981 | /* 2533 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10982 | /* 2539 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10983 | /* 2547 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10984 | /* 2554 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10985 | /* 2562 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10986 | /* 2572 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10987 | /* 2578 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10988 | /* 2586 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10989 | /* 2593 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10990 | /* 2602 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10991 | /* 2611 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10992 | /* 2622 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10993 | /* 2630 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10994 | /* 2640 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10995 | /* 2646 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10996 | /* 2652 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10997 | /* 2658 */ { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10998 | /* 2664 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 10999 | /* 2669 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11000 | /* 2674 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11001 | /* 2680 */ { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11002 | /* 2686 */ { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11003 | /* 2690 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11004 | /* 2696 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11005 | /* 2702 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11006 | /* 2709 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11007 | /* 2715 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11008 | /* 2720 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11009 | /* 2726 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11010 | /* 2733 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11011 | /* 2739 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11012 | /* 2744 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11013 | /* 2748 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11014 | /* 2752 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 11015 | /* 2757 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11016 | /* 2763 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11017 | /* 2767 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11018 | /* 2771 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 11019 | /* 2775 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 11020 | /* 2780 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11021 | /* 2784 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11022 | /* 2789 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 11023 | /* 2793 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11024 | /* 2797 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11025 | /* 2802 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11026 | /* 2807 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11027 | /* 2811 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11028 | /* 2817 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11029 | /* 2824 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11030 | /* 2830 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11031 | /* 2835 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11032 | /* 2839 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11033 | /* 2845 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11034 | /* 2852 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11035 | /* 2858 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11036 | /* 2863 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11037 | /* 2868 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11038 | /* 2875 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11039 | /* 2879 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11040 | /* 2884 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11041 | /* 2889 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11042 | /* 2895 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 11043 | /* 2900 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11044 | /* 2906 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11045 | /* 2910 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11046 | /* 2915 */ { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11047 | /* 2918 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11048 | /* 2924 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11049 | /* 2932 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11050 | /* 2938 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11051 | /* 2943 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11052 | /* 2948 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11053 | /* 2954 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11054 | /* 2960 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11055 | /* 2966 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11056 | /* 2973 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11057 | /* 2979 */ { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11058 | /* 2985 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11059 | /* 2989 */ { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11060 | /* 2993 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11061 | /* 2999 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11062 | /* 3005 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11063 | /* 3011 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11064 | /* 3016 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11065 | /* 3021 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11066 | /* 3027 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11067 | /* 3032 */ { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11068 | /* 3037 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11069 | /* 3041 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 11070 | /* 3044 */ { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 11071 | /* 3047 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
| 11072 | /* 3049 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11073 | /* 3053 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 11074 | /* 3057 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11075 | /* 3062 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11076 | /* 3067 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11077 | /* 3071 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11078 | /* 3076 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11079 | /* 3081 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11080 | /* 3087 */ { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, |
| 11081 | /* 3092 */ { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 11082 | } |
| 11083 | }; |
| 11084 | |
| 11085 | |
| 11086 | #ifdef __GNUC__ |
| 11087 | #pragma GCC diagnostic push |
| 11088 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 11089 | #endif |
| 11090 | extern const char ARMInstrNameData[] = { |
| 11091 | /* 0 */ "G_FLOG10\000" |
| 11092 | /* 9 */ "G_FEXP10\000" |
| 11093 | /* 18 */ "VMOVD0\000" |
| 11094 | /* 25 */ "VMSR_P0\000" |
| 11095 | /* 33 */ "VMRS_P0\000" |
| 11096 | /* 41 */ "VMOVQ0\000" |
| 11097 | /* 48 */ "VMRS_MVFR0\000" |
| 11098 | /* 59 */ "SHA1SU0\000" |
| 11099 | /* 67 */ "SHA256SU0\000" |
| 11100 | /* 77 */ "t__brkdiv0\000" |
| 11101 | /* 88 */ "VTBL1\000" |
| 11102 | /* 94 */ "VMRS_MVFR1\000" |
| 11103 | /* 105 */ "t2DCPS1\000" |
| 11104 | /* 113 */ "SHA1SU1\000" |
| 11105 | /* 121 */ "SHA256SU1\000" |
| 11106 | /* 131 */ "VTBX1\000" |
| 11107 | /* 137 */ "CDE_CX1\000" |
| 11108 | /* 145 */ "KCFI_CHECK_Thumb1\000" |
| 11109 | /* 163 */ "t2ASRs1\000" |
| 11110 | /* 171 */ "t2LSRs1\000" |
| 11111 | /* 179 */ "t2LDRBi12\000" |
| 11112 | /* 189 */ "t2STRBi12\000" |
| 11113 | /* 199 */ "t2LDRSBi12\000" |
| 11114 | /* 210 */ "t2PLDi12\000" |
| 11115 | /* 219 */ "t2LDRHi12\000" |
| 11116 | /* 229 */ "t2STRHi12\000" |
| 11117 | /* 239 */ "t2LDRSHi12\000" |
| 11118 | /* 250 */ "t2PLIi12\000" |
| 11119 | /* 259 */ "t2LDRi12\000" |
| 11120 | /* 268 */ "t2STRi12\000" |
| 11121 | /* 277 */ "t2PLDWi12\000" |
| 11122 | /* 287 */ "BR_JTm_i12\000" |
| 11123 | /* 298 */ "t2SUBri12\000" |
| 11124 | /* 308 */ "t2ADDri12\000" |
| 11125 | /* 318 */ "t2SUBspImm12\000" |
| 11126 | /* 331 */ "t2ADDspImm12\000" |
| 11127 | /* 344 */ "TCRETURNrinotr12\000" |
| 11128 | /* 361 */ "MVE_VSTRB32\000" |
| 11129 | /* 373 */ "MVE_VSTRH32\000" |
| 11130 | /* 385 */ "COPY_STRUCT_BYVAL_I32\000" |
| 11131 | /* 407 */ "MVE_VCTP32\000" |
| 11132 | /* 418 */ "MVE_VDUP32\000" |
| 11133 | /* 429 */ "MVE_VBRSR32\000" |
| 11134 | /* 441 */ "MVE_VLDRBS32\000" |
| 11135 | /* 454 */ "MVE_VLDRHS32\000" |
| 11136 | /* 467 */ "MVE_VLDRBU32\000" |
| 11137 | /* 480 */ "MVE_VLDRHU32\000" |
| 11138 | /* 493 */ "MVE_VLDRWU32\000" |
| 11139 | /* 506 */ "MVE_VSTRWU32\000" |
| 11140 | /* 519 */ "MVE_VLD20_32\000" |
| 11141 | /* 532 */ "MVE_VST20_32\000" |
| 11142 | /* 545 */ "MVE_VLD40_32\000" |
| 11143 | /* 558 */ "MVE_VST40_32\000" |
| 11144 | /* 571 */ "MVE_VLD21_32\000" |
| 11145 | /* 584 */ "MVE_VST21_32\000" |
| 11146 | /* 597 */ "MVE_VLD41_32\000" |
| 11147 | /* 610 */ "MVE_VST41_32\000" |
| 11148 | /* 623 */ "MVE_VLD42_32\000" |
| 11149 | /* 636 */ "MVE_VST42_32\000" |
| 11150 | /* 649 */ "MVE_VLD43_32\000" |
| 11151 | /* 662 */ "MVE_VST43_32\000" |
| 11152 | /* 675 */ "MVE_VREV64_32\000" |
| 11153 | /* 689 */ "tCMP_SWAP_32\000" |
| 11154 | /* 702 */ "MVE_DLSTP_32\000" |
| 11155 | /* 715 */ "MVE_WLSTP_32\000" |
| 11156 | /* 728 */ "MVE_VMOV_from_lane_32\000" |
| 11157 | /* 750 */ "MVE_VMOV_to_lane_32\000" |
| 11158 | /* 770 */ "VLD3dWB_fixed_Asm_32\000" |
| 11159 | /* 791 */ "VST3dWB_fixed_Asm_32\000" |
| 11160 | /* 812 */ "VLD4dWB_fixed_Asm_32\000" |
| 11161 | /* 833 */ "VST4dWB_fixed_Asm_32\000" |
| 11162 | /* 854 */ "VLD1LNdWB_fixed_Asm_32\000" |
| 11163 | /* 877 */ "VST1LNdWB_fixed_Asm_32\000" |
| 11164 | /* 900 */ "VLD2LNdWB_fixed_Asm_32\000" |
| 11165 | /* 923 */ "VST2LNdWB_fixed_Asm_32\000" |
| 11166 | /* 946 */ "VLD3LNdWB_fixed_Asm_32\000" |
| 11167 | /* 969 */ "VST3LNdWB_fixed_Asm_32\000" |
| 11168 | /* 992 */ "VLD4LNdWB_fixed_Asm_32\000" |
| 11169 | /* 1015 */ "VST4LNdWB_fixed_Asm_32\000" |
| 11170 | /* 1038 */ "VLD3DUPdWB_fixed_Asm_32\000" |
| 11171 | /* 1062 */ "VLD4DUPdWB_fixed_Asm_32\000" |
| 11172 | /* 1086 */ "VLD3qWB_fixed_Asm_32\000" |
| 11173 | /* 1107 */ "VST3qWB_fixed_Asm_32\000" |
| 11174 | /* 1128 */ "VLD4qWB_fixed_Asm_32\000" |
| 11175 | /* 1149 */ "VST4qWB_fixed_Asm_32\000" |
| 11176 | /* 1170 */ "VLD2LNqWB_fixed_Asm_32\000" |
| 11177 | /* 1193 */ "VST2LNqWB_fixed_Asm_32\000" |
| 11178 | /* 1216 */ "VLD3LNqWB_fixed_Asm_32\000" |
| 11179 | /* 1239 */ "VST3LNqWB_fixed_Asm_32\000" |
| 11180 | /* 1262 */ "VLD4LNqWB_fixed_Asm_32\000" |
| 11181 | /* 1285 */ "VST4LNqWB_fixed_Asm_32\000" |
| 11182 | /* 1308 */ "VLD3DUPqWB_fixed_Asm_32\000" |
| 11183 | /* 1332 */ "VLD4DUPqWB_fixed_Asm_32\000" |
| 11184 | /* 1356 */ "VLD3dWB_register_Asm_32\000" |
| 11185 | /* 1380 */ "VST3dWB_register_Asm_32\000" |
| 11186 | /* 1404 */ "VLD4dWB_register_Asm_32\000" |
| 11187 | /* 1428 */ "VST4dWB_register_Asm_32\000" |
| 11188 | /* 1452 */ "VLD1LNdWB_register_Asm_32\000" |
| 11189 | /* 1478 */ "VST1LNdWB_register_Asm_32\000" |
| 11190 | /* 1504 */ "VLD2LNdWB_register_Asm_32\000" |
| 11191 | /* 1530 */ "VST2LNdWB_register_Asm_32\000" |
| 11192 | /* 1556 */ "VLD3LNdWB_register_Asm_32\000" |
| 11193 | /* 1582 */ "VST3LNdWB_register_Asm_32\000" |
| 11194 | /* 1608 */ "VLD4LNdWB_register_Asm_32\000" |
| 11195 | /* 1634 */ "VST4LNdWB_register_Asm_32\000" |
| 11196 | /* 1660 */ "VLD3DUPdWB_register_Asm_32\000" |
| 11197 | /* 1687 */ "VLD4DUPdWB_register_Asm_32\000" |
| 11198 | /* 1714 */ "VLD3qWB_register_Asm_32\000" |
| 11199 | /* 1738 */ "VST3qWB_register_Asm_32\000" |
| 11200 | /* 1762 */ "VLD4qWB_register_Asm_32\000" |
| 11201 | /* 1786 */ "VST4qWB_register_Asm_32\000" |
| 11202 | /* 1810 */ "VLD2LNqWB_register_Asm_32\000" |
| 11203 | /* 1836 */ "VST2LNqWB_register_Asm_32\000" |
| 11204 | /* 1862 */ "VLD3LNqWB_register_Asm_32\000" |
| 11205 | /* 1888 */ "VST3LNqWB_register_Asm_32\000" |
| 11206 | /* 1914 */ "VLD4LNqWB_register_Asm_32\000" |
| 11207 | /* 1940 */ "VST4LNqWB_register_Asm_32\000" |
| 11208 | /* 1966 */ "VLD3DUPqWB_register_Asm_32\000" |
| 11209 | /* 1993 */ "VLD4DUPqWB_register_Asm_32\000" |
| 11210 | /* 2020 */ "VLD3dAsm_32\000" |
| 11211 | /* 2032 */ "VST3dAsm_32\000" |
| 11212 | /* 2044 */ "VLD4dAsm_32\000" |
| 11213 | /* 2056 */ "VST4dAsm_32\000" |
| 11214 | /* 2068 */ "VLD1LNdAsm_32\000" |
| 11215 | /* 2082 */ "VST1LNdAsm_32\000" |
| 11216 | /* 2096 */ "VLD2LNdAsm_32\000" |
| 11217 | /* 2110 */ "VST2LNdAsm_32\000" |
| 11218 | /* 2124 */ "VLD3LNdAsm_32\000" |
| 11219 | /* 2138 */ "VST3LNdAsm_32\000" |
| 11220 | /* 2152 */ "VLD4LNdAsm_32\000" |
| 11221 | /* 2166 */ "VST4LNdAsm_32\000" |
| 11222 | /* 2180 */ "VLD3DUPdAsm_32\000" |
| 11223 | /* 2195 */ "VLD4DUPdAsm_32\000" |
| 11224 | /* 2210 */ "VLD3qAsm_32\000" |
| 11225 | /* 2222 */ "VST3qAsm_32\000" |
| 11226 | /* 2234 */ "VLD4qAsm_32\000" |
| 11227 | /* 2246 */ "VST4qAsm_32\000" |
| 11228 | /* 2258 */ "VLD2LNqAsm_32\000" |
| 11229 | /* 2272 */ "VST2LNqAsm_32\000" |
| 11230 | /* 2286 */ "VLD3LNqAsm_32\000" |
| 11231 | /* 2300 */ "VST3LNqAsm_32\000" |
| 11232 | /* 2314 */ "VLD4LNqAsm_32\000" |
| 11233 | /* 2328 */ "VST4LNqAsm_32\000" |
| 11234 | /* 2342 */ "VLD3DUPqAsm_32\000" |
| 11235 | /* 2357 */ "VLD4DUPqAsm_32\000" |
| 11236 | /* 2372 */ "VLD2b32\000" |
| 11237 | /* 2380 */ "VST2b32\000" |
| 11238 | /* 2388 */ "VLD1d32\000" |
| 11239 | /* 2396 */ "VST1d32\000" |
| 11240 | /* 2404 */ "VLD2d32\000" |
| 11241 | /* 2412 */ "VST2d32\000" |
| 11242 | /* 2420 */ "VLD3d32\000" |
| 11243 | /* 2428 */ "VST3d32\000" |
| 11244 | /* 2436 */ "VREV64d32\000" |
| 11245 | /* 2446 */ "VLD4d32\000" |
| 11246 | /* 2454 */ "VST4d32\000" |
| 11247 | /* 2462 */ "VLD1LNd32\000" |
| 11248 | /* 2472 */ "VST1LNd32\000" |
| 11249 | /* 2482 */ "VLD2LNd32\000" |
| 11250 | /* 2492 */ "VST2LNd32\000" |
| 11251 | /* 2502 */ "VLD3LNd32\000" |
| 11252 | /* 2512 */ "VST3LNd32\000" |
| 11253 | /* 2522 */ "VLD4LNd32\000" |
| 11254 | /* 2532 */ "VST4LNd32\000" |
| 11255 | /* 2542 */ "VTRNd32\000" |
| 11256 | /* 2550 */ "VLD1DUPd32\000" |
| 11257 | /* 2561 */ "VLD2DUPd32\000" |
| 11258 | /* 2572 */ "VLD3DUPd32\000" |
| 11259 | /* 2583 */ "VLD4DUPd32\000" |
| 11260 | /* 2594 */ "VEXTd32\000" |
| 11261 | /* 2602 */ "VCMLAv2f32\000" |
| 11262 | /* 2613 */ "VCADDv2f32\000" |
| 11263 | /* 2624 */ "VMOVv2f32\000" |
| 11264 | /* 2634 */ "VCGEzv2f32\000" |
| 11265 | /* 2645 */ "VCLEzv2f32\000" |
| 11266 | /* 2656 */ "VCEQzv2f32\000" |
| 11267 | /* 2667 */ "VCGTzv2f32\000" |
| 11268 | /* 2678 */ "VCLTzv2f32\000" |
| 11269 | /* 2689 */ "VCMLAv4f32\000" |
| 11270 | /* 2700 */ "VCADDv4f32\000" |
| 11271 | /* 2711 */ "MVE_VPTv4f32\000" |
| 11272 | /* 2724 */ "VMOVv4f32\000" |
| 11273 | /* 2734 */ "VCGEzv4f32\000" |
| 11274 | /* 2745 */ "VCLEzv4f32\000" |
| 11275 | /* 2756 */ "VCEQzv4f32\000" |
| 11276 | /* 2767 */ "VCGTzv4f32\000" |
| 11277 | /* 2778 */ "VCLTzv4f32\000" |
| 11278 | /* 2789 */ "MVE_VCMLAf32\000" |
| 11279 | /* 2802 */ "MVE_VFMAf32\000" |
| 11280 | /* 2814 */ "MVE_VMINNMAf32\000" |
| 11281 | /* 2829 */ "MVE_VMAXNMAf32\000" |
| 11282 | /* 2844 */ "MVE_VSUBf32\000" |
| 11283 | /* 2856 */ "MVE_VABDf32\000" |
| 11284 | /* 2868 */ "MVE_VCADDf32\000" |
| 11285 | /* 2881 */ "MVE_VADDf32\000" |
| 11286 | /* 2893 */ "MVE_VNEGf32\000" |
| 11287 | /* 2905 */ "MVE_VCMULf32\000" |
| 11288 | /* 2918 */ "MVE_VMULf32\000" |
| 11289 | /* 2930 */ "MVE_VMINNMf32\000" |
| 11290 | /* 2944 */ "MVE_VMAXNMf32\000" |
| 11291 | /* 2958 */ "MVE_VCMPf32\000" |
| 11292 | /* 2970 */ "MVE_VABSf32\000" |
| 11293 | /* 2982 */ "MVE_VFMSf32\000" |
| 11294 | /* 2994 */ "MVE_VFMA_qr_Sf32\000" |
| 11295 | /* 3011 */ "MVE_VMINNMAVf32\000" |
| 11296 | /* 3027 */ "MVE_VMAXNMAVf32\000" |
| 11297 | /* 3043 */ "MVE_VMINNMVf32\000" |
| 11298 | /* 3058 */ "MVE_VMAXNMVf32\000" |
| 11299 | /* 3073 */ "MVE_VFMA_qr_f32\000" |
| 11300 | /* 3089 */ "MVE_VSUB_qr_f32\000" |
| 11301 | /* 3105 */ "MVE_VADD_qr_f32\000" |
| 11302 | /* 3121 */ "MVE_VMUL_qr_f32\000" |
| 11303 | /* 3137 */ "MVE_VMOVimmf32\000" |
| 11304 | /* 3152 */ "VMLAv2i32\000" |
| 11305 | /* 3162 */ "VSUBv2i32\000" |
| 11306 | /* 3172 */ "VADDv2i32\000" |
| 11307 | /* 3182 */ "VQNEGv2i32\000" |
| 11308 | /* 3193 */ "VQRDMLAHv2i32\000" |
| 11309 | /* 3207 */ "VQDMULHv2i32\000" |
| 11310 | /* 3220 */ "VQRDMULHv2i32\000" |
| 11311 | /* 3234 */ "VQRDMLSHv2i32\000" |
| 11312 | /* 3248 */ "VSLIv2i32\000" |
| 11313 | /* 3258 */ "VSRIv2i32\000" |
| 11314 | /* 3268 */ "VMULv2i32\000" |
| 11315 | /* 3278 */ "VRSUBHNv2i32\000" |
| 11316 | /* 3291 */ "VSUBHNv2i32\000" |
| 11317 | /* 3303 */ "VRADDHNv2i32\000" |
| 11318 | /* 3316 */ "VADDHNv2i32\000" |
| 11319 | /* 3328 */ "VRSHRNv2i32\000" |
| 11320 | /* 3340 */ "VSHRNv2i32\000" |
| 11321 | /* 3351 */ "VQSHRUNv2i32\000" |
| 11322 | /* 3364 */ "VQRSHRUNv2i32\000" |
| 11323 | /* 3378 */ "VMVNv2i32\000" |
| 11324 | /* 3388 */ "VMOVNv2i32\000" |
| 11325 | /* 3399 */ "VCEQv2i32\000" |
| 11326 | /* 3409 */ "VQABSv2i32\000" |
| 11327 | /* 3420 */ "VABSv2i32\000" |
| 11328 | /* 3430 */ "VCLSv2i32\000" |
| 11329 | /* 3440 */ "VMLSv2i32\000" |
| 11330 | /* 3450 */ "VTSTv2i32\000" |
| 11331 | /* 3460 */ "VMOVv2i32\000" |
| 11332 | /* 3470 */ "VCLZv2i32\000" |
| 11333 | /* 3480 */ "VBICiv2i32\000" |
| 11334 | /* 3491 */ "VSHLiv2i32\000" |
| 11335 | /* 3502 */ "VORRiv2i32\000" |
| 11336 | /* 3513 */ "VQSHLsiv2i32\000" |
| 11337 | /* 3526 */ "VQSHLuiv2i32\000" |
| 11338 | /* 3539 */ "VMLAslv2i32\000" |
| 11339 | /* 3551 */ "VQRDMLAHslv2i32\000" |
| 11340 | /* 3567 */ "VQDMULHslv2i32\000" |
| 11341 | /* 3582 */ "VQRDMULHslv2i32\000" |
| 11342 | /* 3598 */ "VQRDMLSHslv2i32\000" |
| 11343 | /* 3614 */ "VQDMLALslv2i32\000" |
| 11344 | /* 3629 */ "VQDMULLslv2i32\000" |
| 11345 | /* 3644 */ "VQDMLSLslv2i32\000" |
| 11346 | /* 3659 */ "VMULslv2i32\000" |
| 11347 | /* 3671 */ "VMLSslv2i32\000" |
| 11348 | /* 3683 */ "VABAsv2i32\000" |
| 11349 | /* 3694 */ "VRSRAsv2i32\000" |
| 11350 | /* 3706 */ "VSRAsv2i32\000" |
| 11351 | /* 3717 */ "VHSUBsv2i32\000" |
| 11352 | /* 3729 */ "VQSUBsv2i32\000" |
| 11353 | /* 3741 */ "VABDsv2i32\000" |
| 11354 | /* 3752 */ "VRHADDsv2i32\000" |
| 11355 | /* 3765 */ "VHADDsv2i32\000" |
| 11356 | /* 3777 */ "VQADDsv2i32\000" |
| 11357 | /* 3789 */ "VCGEsv2i32\000" |
| 11358 | /* 3800 */ "VPADALsv2i32\000" |
| 11359 | /* 3813 */ "VPADDLsv2i32\000" |
| 11360 | /* 3826 */ "VQSHLsv2i32\000" |
| 11361 | /* 3838 */ "VQRSHLsv2i32\000" |
| 11362 | /* 3851 */ "VRSHLsv2i32\000" |
| 11363 | /* 3863 */ "VSHLsv2i32\000" |
| 11364 | /* 3874 */ "VMINsv2i32\000" |
| 11365 | /* 3885 */ "VQSHRNsv2i32\000" |
| 11366 | /* 3898 */ "VQRSHRNsv2i32\000" |
| 11367 | /* 3912 */ "VQMOVNsv2i32\000" |
| 11368 | /* 3925 */ "VRSHRsv2i32\000" |
| 11369 | /* 3937 */ "VSHRsv2i32\000" |
| 11370 | /* 3948 */ "VCGTsv2i32\000" |
| 11371 | /* 3959 */ "VMAXsv2i32\000" |
| 11372 | /* 3970 */ "VMLALslsv2i32\000" |
| 11373 | /* 3984 */ "VMULLslsv2i32\000" |
| 11374 | /* 3998 */ "VMLSLslsv2i32\000" |
| 11375 | /* 4012 */ "VABAuv2i32\000" |
| 11376 | /* 4023 */ "VRSRAuv2i32\000" |
| 11377 | /* 4035 */ "VSRAuv2i32\000" |
| 11378 | /* 4046 */ "VHSUBuv2i32\000" |
| 11379 | /* 4058 */ "VQSUBuv2i32\000" |
| 11380 | /* 4070 */ "VABDuv2i32\000" |
| 11381 | /* 4081 */ "VRHADDuv2i32\000" |
| 11382 | /* 4094 */ "VHADDuv2i32\000" |
| 11383 | /* 4106 */ "VQADDuv2i32\000" |
| 11384 | /* 4118 */ "VCGEuv2i32\000" |
| 11385 | /* 4129 */ "VPADALuv2i32\000" |
| 11386 | /* 4142 */ "VPADDLuv2i32\000" |
| 11387 | /* 4155 */ "VQSHLuv2i32\000" |
| 11388 | /* 4167 */ "VQRSHLuv2i32\000" |
| 11389 | /* 4180 */ "VRSHLuv2i32\000" |
| 11390 | /* 4192 */ "VSHLuv2i32\000" |
| 11391 | /* 4203 */ "VMINuv2i32\000" |
| 11392 | /* 4214 */ "VQSHRNuv2i32\000" |
| 11393 | /* 4227 */ "VQRSHRNuv2i32\000" |
| 11394 | /* 4241 */ "VQMOVNuv2i32\000" |
| 11395 | /* 4254 */ "VRSHRuv2i32\000" |
| 11396 | /* 4266 */ "VSHRuv2i32\000" |
| 11397 | /* 4277 */ "VCGTuv2i32\000" |
| 11398 | /* 4288 */ "VMAXuv2i32\000" |
| 11399 | /* 4299 */ "VMLALsluv2i32\000" |
| 11400 | /* 4313 */ "VMULLsluv2i32\000" |
| 11401 | /* 4327 */ "VMLSLsluv2i32\000" |
| 11402 | /* 4341 */ "VQSHLsuv2i32\000" |
| 11403 | /* 4354 */ "VQMOVNsuv2i32\000" |
| 11404 | /* 4368 */ "VCGEzv2i32\000" |
| 11405 | /* 4379 */ "VCLEzv2i32\000" |
| 11406 | /* 4390 */ "VCEQzv2i32\000" |
| 11407 | /* 4401 */ "VCGTzv2i32\000" |
| 11408 | /* 4412 */ "VCLTzv2i32\000" |
| 11409 | /* 4423 */ "VMLAv4i32\000" |
| 11410 | /* 4433 */ "VSUBv4i32\000" |
| 11411 | /* 4443 */ "VADDv4i32\000" |
| 11412 | /* 4453 */ "VQNEGv4i32\000" |
| 11413 | /* 4464 */ "VQRDMLAHv4i32\000" |
| 11414 | /* 4478 */ "VQDMULHv4i32\000" |
| 11415 | /* 4491 */ "VQRDMULHv4i32\000" |
| 11416 | /* 4505 */ "VQRDMLSHv4i32\000" |
| 11417 | /* 4519 */ "VSLIv4i32\000" |
| 11418 | /* 4529 */ "VSRIv4i32\000" |
| 11419 | /* 4539 */ "VQDMLALv4i32\000" |
| 11420 | /* 4552 */ "VQDMULLv4i32\000" |
| 11421 | /* 4565 */ "VQDMLSLv4i32\000" |
| 11422 | /* 4578 */ "VMULv4i32\000" |
| 11423 | /* 4588 */ "VMVNv4i32\000" |
| 11424 | /* 4598 */ "VCEQv4i32\000" |
| 11425 | /* 4608 */ "VQABSv4i32\000" |
| 11426 | /* 4619 */ "VABSv4i32\000" |
| 11427 | /* 4629 */ "VCLSv4i32\000" |
| 11428 | /* 4639 */ "VMLSv4i32\000" |
| 11429 | /* 4649 */ "MVE_VPTv4i32\000" |
| 11430 | /* 4662 */ "VTSTv4i32\000" |
| 11431 | /* 4672 */ "VMOVv4i32\000" |
| 11432 | /* 4682 */ "VCLZv4i32\000" |
| 11433 | /* 4692 */ "VBICiv4i32\000" |
| 11434 | /* 4703 */ "VSHLiv4i32\000" |
| 11435 | /* 4714 */ "VORRiv4i32\000" |
| 11436 | /* 4725 */ "VQSHLsiv4i32\000" |
| 11437 | /* 4738 */ "VQSHLuiv4i32\000" |
| 11438 | /* 4751 */ "VMLAslv4i32\000" |
| 11439 | /* 4763 */ "VQRDMLAHslv4i32\000" |
| 11440 | /* 4779 */ "VQDMULHslv4i32\000" |
| 11441 | /* 4794 */ "VQRDMULHslv4i32\000" |
| 11442 | /* 4810 */ "VQRDMLSHslv4i32\000" |
| 11443 | /* 4826 */ "VMULslv4i32\000" |
| 11444 | /* 4838 */ "VMLSslv4i32\000" |
| 11445 | /* 4850 */ "VABAsv4i32\000" |
| 11446 | /* 4861 */ "VRSRAsv4i32\000" |
| 11447 | /* 4873 */ "VSRAsv4i32\000" |
| 11448 | /* 4884 */ "VHSUBsv4i32\000" |
| 11449 | /* 4896 */ "VQSUBsv4i32\000" |
| 11450 | /* 4908 */ "VABDsv4i32\000" |
| 11451 | /* 4919 */ "VRHADDsv4i32\000" |
| 11452 | /* 4932 */ "VHADDsv4i32\000" |
| 11453 | /* 4944 */ "VQADDsv4i32\000" |
| 11454 | /* 4956 */ "VCGEsv4i32\000" |
| 11455 | /* 4967 */ "VABALsv4i32\000" |
| 11456 | /* 4979 */ "VPADALsv4i32\000" |
| 11457 | /* 4992 */ "VMLALsv4i32\000" |
| 11458 | /* 5004 */ "VSUBLsv4i32\000" |
| 11459 | /* 5016 */ "VABDLsv4i32\000" |
| 11460 | /* 5028 */ "VPADDLsv4i32\000" |
| 11461 | /* 5041 */ "VADDLsv4i32\000" |
| 11462 | /* 5053 */ "VQSHLsv4i32\000" |
| 11463 | /* 5065 */ "VQRSHLsv4i32\000" |
| 11464 | /* 5078 */ "VRSHLsv4i32\000" |
| 11465 | /* 5090 */ "VSHLsv4i32\000" |
| 11466 | /* 5101 */ "VSHLLsv4i32\000" |
| 11467 | /* 5113 */ "VMULLsv4i32\000" |
| 11468 | /* 5125 */ "VMLSLsv4i32\000" |
| 11469 | /* 5137 */ "VMOVLsv4i32\000" |
| 11470 | /* 5149 */ "VMINsv4i32\000" |
| 11471 | /* 5160 */ "VRSHRsv4i32\000" |
| 11472 | /* 5172 */ "VSHRsv4i32\000" |
| 11473 | /* 5183 */ "VCGTsv4i32\000" |
| 11474 | /* 5194 */ "VSUBWsv4i32\000" |
| 11475 | /* 5206 */ "VADDWsv4i32\000" |
| 11476 | /* 5218 */ "VMAXsv4i32\000" |
| 11477 | /* 5229 */ "VABAuv4i32\000" |
| 11478 | /* 5240 */ "VRSRAuv4i32\000" |
| 11479 | /* 5252 */ "VSRAuv4i32\000" |
| 11480 | /* 5263 */ "VHSUBuv4i32\000" |
| 11481 | /* 5275 */ "VQSUBuv4i32\000" |
| 11482 | /* 5287 */ "VABDuv4i32\000" |
| 11483 | /* 5298 */ "VRHADDuv4i32\000" |
| 11484 | /* 5311 */ "VHADDuv4i32\000" |
| 11485 | /* 5323 */ "VQADDuv4i32\000" |
| 11486 | /* 5335 */ "VCGEuv4i32\000" |
| 11487 | /* 5346 */ "VABALuv4i32\000" |
| 11488 | /* 5358 */ "VPADALuv4i32\000" |
| 11489 | /* 5371 */ "VMLALuv4i32\000" |
| 11490 | /* 5383 */ "VSUBLuv4i32\000" |
| 11491 | /* 5395 */ "VABDLuv4i32\000" |
| 11492 | /* 5407 */ "VPADDLuv4i32\000" |
| 11493 | /* 5420 */ "VADDLuv4i32\000" |
| 11494 | /* 5432 */ "VQSHLuv4i32\000" |
| 11495 | /* 5444 */ "VQRSHLuv4i32\000" |
| 11496 | /* 5457 */ "VRSHLuv4i32\000" |
| 11497 | /* 5469 */ "VSHLuv4i32\000" |
| 11498 | /* 5480 */ "VSHLLuv4i32\000" |
| 11499 | /* 5492 */ "VMULLuv4i32\000" |
| 11500 | /* 5504 */ "VMLSLuv4i32\000" |
| 11501 | /* 5516 */ "VMOVLuv4i32\000" |
| 11502 | /* 5528 */ "VMINuv4i32\000" |
| 11503 | /* 5539 */ "VRSHRuv4i32\000" |
| 11504 | /* 5551 */ "VSHRuv4i32\000" |
| 11505 | /* 5562 */ "VCGTuv4i32\000" |
| 11506 | /* 5573 */ "VSUBWuv4i32\000" |
| 11507 | /* 5585 */ "VADDWuv4i32\000" |
| 11508 | /* 5597 */ "VMAXuv4i32\000" |
| 11509 | /* 5608 */ "VQSHLsuv4i32\000" |
| 11510 | /* 5621 */ "VCGEzv4i32\000" |
| 11511 | /* 5632 */ "VCLEzv4i32\000" |
| 11512 | /* 5643 */ "VCEQzv4i32\000" |
| 11513 | /* 5654 */ "VCGTzv4i32\000" |
| 11514 | /* 5665 */ "VCLTzv4i32\000" |
| 11515 | /* 5676 */ "MVE_VSUBi32\000" |
| 11516 | /* 5688 */ "MVE_VCADDi32\000" |
| 11517 | /* 5701 */ "VPADDi32\000" |
| 11518 | /* 5710 */ "MVE_VADDi32\000" |
| 11519 | /* 5722 */ "MVE_VQDMULHi32\000" |
| 11520 | /* 5737 */ "MVE_VQRDMULHi32\000" |
| 11521 | /* 5753 */ "VSHLLi32\000" |
| 11522 | /* 5762 */ "MVE_VMULi32\000" |
| 11523 | /* 5774 */ "VGETLNi32\000" |
| 11524 | /* 5784 */ "VSETLNi32\000" |
| 11525 | /* 5794 */ "MVE_VCMPi32\000" |
| 11526 | /* 5806 */ "MVE_VMLA_qr_i32\000" |
| 11527 | /* 5822 */ "MVE_VSUB_qr_i32\000" |
| 11528 | /* 5838 */ "MVE_VADD_qr_i32\000" |
| 11529 | /* 5854 */ "MVE_VMUL_qr_i32\000" |
| 11530 | /* 5870 */ "MVE_VMLAS_qr_i32\000" |
| 11531 | /* 5887 */ "MVE_VBICimmi32\000" |
| 11532 | /* 5902 */ "MVE_VMVNimmi32\000" |
| 11533 | /* 5917 */ "MVE_VORRimmi32\000" |
| 11534 | /* 5932 */ "MVE_VMOVimmi32\000" |
| 11535 | /* 5947 */ "MVE_VSHL_immi32\000" |
| 11536 | /* 5963 */ "MVE_VSLIimm32\000" |
| 11537 | /* 5977 */ "MVE_VSRIimm32\000" |
| 11538 | /* 5991 */ "VLD1q32\000" |
| 11539 | /* 5999 */ "VST1q32\000" |
| 11540 | /* 6007 */ "VLD2q32\000" |
| 11541 | /* 6015 */ "VST2q32\000" |
| 11542 | /* 6023 */ "VLD3q32\000" |
| 11543 | /* 6031 */ "VST3q32\000" |
| 11544 | /* 6039 */ "VREV64q32\000" |
| 11545 | /* 6049 */ "VLD4q32\000" |
| 11546 | /* 6057 */ "VST4q32\000" |
| 11547 | /* 6065 */ "VLD2LNq32\000" |
| 11548 | /* 6075 */ "VST2LNq32\000" |
| 11549 | /* 6085 */ "VLD3LNq32\000" |
| 11550 | /* 6095 */ "VST3LNq32\000" |
| 11551 | /* 6105 */ "VLD4LNq32\000" |
| 11552 | /* 6115 */ "VST4LNq32\000" |
| 11553 | /* 6125 */ "VTRNq32\000" |
| 11554 | /* 6133 */ "VZIPq32\000" |
| 11555 | /* 6141 */ "VLD1DUPq32\000" |
| 11556 | /* 6152 */ "VLD3DUPq32\000" |
| 11557 | /* 6163 */ "VLD4DUPq32\000" |
| 11558 | /* 6174 */ "VUZPq32\000" |
| 11559 | /* 6182 */ "VEXTq32\000" |
| 11560 | /* 6190 */ "MVE_VPTv4s32\000" |
| 11561 | /* 6203 */ "MVE_VMINAs32\000" |
| 11562 | /* 6216 */ "MVE_VMAXAs32\000" |
| 11563 | /* 6229 */ "MVE_VMULLBs32\000" |
| 11564 | /* 6243 */ "MVE_VHSUBs32\000" |
| 11565 | /* 6256 */ "MVE_VQSUBs32\000" |
| 11566 | /* 6269 */ "MVE_VABDs32\000" |
| 11567 | /* 6281 */ "MVE_VHCADDs32\000" |
| 11568 | /* 6295 */ "MVE_VRHADDs32\000" |
| 11569 | /* 6309 */ "MVE_VHADDs32\000" |
| 11570 | /* 6322 */ "MVE_VQADDs32\000" |
| 11571 | /* 6335 */ "MVE_VQNEGs32\000" |
| 11572 | /* 6348 */ "MVE_VNEGs32\000" |
| 11573 | /* 6360 */ "MVE_VQDMLADHs32\000" |
| 11574 | /* 6376 */ "MVE_VQRDMLADHs32\000" |
| 11575 | /* 6393 */ "MVE_VQDMLSDHs32\000" |
| 11576 | /* 6409 */ "MVE_VQRDMLSDHs32\000" |
| 11577 | /* 6426 */ "MVE_VRMULHs32\000" |
| 11578 | /* 6440 */ "MVE_VMULHs32\000" |
| 11579 | /* 6453 */ "MVE_VRMLALDAVHs32\000" |
| 11580 | /* 6471 */ "MVE_VRMLSLDAVHs32\000" |
| 11581 | /* 6489 */ "VPMINs32\000" |
| 11582 | /* 6498 */ "MVE_VMINs32\000" |
| 11583 | /* 6510 */ "MVE_VCMPs32\000" |
| 11584 | /* 6522 */ "MVE_VQABSs32\000" |
| 11585 | /* 6535 */ "MVE_VABSs32\000" |
| 11586 | /* 6547 */ "MVE_VCLSs32\000" |
| 11587 | /* 6559 */ "MVE_VMULLTs32\000" |
| 11588 | /* 6573 */ "MVE_VABAVs32\000" |
| 11589 | /* 6586 */ "MVE_VMLADAVs32\000" |
| 11590 | /* 6601 */ "MVE_VMLALDAVs32\000" |
| 11591 | /* 6617 */ "MVE_VMLSLDAVs32\000" |
| 11592 | /* 6633 */ "MVE_VMLSDAVs32\000" |
| 11593 | /* 6648 */ "MVE_VMINAVs32\000" |
| 11594 | /* 6662 */ "MVE_VMAXAVs32\000" |
| 11595 | /* 6676 */ "MVE_VMINVs32\000" |
| 11596 | /* 6689 */ "MVE_VMAXVs32\000" |
| 11597 | /* 6702 */ "VPMAXs32\000" |
| 11598 | /* 6711 */ "MVE_VMAXs32\000" |
| 11599 | /* 6723 */ "MVE_VQDMLADHXs32\000" |
| 11600 | /* 6740 */ "MVE_VQRDMLADHXs32\000" |
| 11601 | /* 6758 */ "MVE_VQDMLSDHXs32\000" |
| 11602 | /* 6775 */ "MVE_VQRDMLSDHXs32\000" |
| 11603 | /* 6793 */ "MVE_VCLZs32\000" |
| 11604 | /* 6805 */ "MVE_VHSUB_qr_s32\000" |
| 11605 | /* 6822 */ "MVE_VQSUB_qr_s32\000" |
| 11606 | /* 6839 */ "MVE_VHADD_qr_s32\000" |
| 11607 | /* 6856 */ "MVE_VQADD_qr_s32\000" |
| 11608 | /* 6873 */ "MVE_VQDMULH_qr_s32\000" |
| 11609 | /* 6892 */ "MVE_VQRDMULH_qr_s32\000" |
| 11610 | /* 6912 */ "MVE_VRMLALDAVHas32\000" |
| 11611 | /* 6931 */ "MVE_VRMLSLDAVHas32\000" |
| 11612 | /* 6950 */ "MVE_VMLADAVas32\000" |
| 11613 | /* 6966 */ "MVE_VMLALDAVas32\000" |
| 11614 | /* 6983 */ "MVE_VMLSLDAVas32\000" |
| 11615 | /* 7000 */ "MVE_VMLSDAVas32\000" |
| 11616 | /* 7016 */ "MVE_VQSHL_by_vecs32\000" |
| 11617 | /* 7036 */ "MVE_VQRSHL_by_vecs32\000" |
| 11618 | /* 7057 */ "MVE_VRSHL_by_vecs32\000" |
| 11619 | /* 7077 */ "MVE_VSHL_by_vecs32\000" |
| 11620 | /* 7096 */ "MVE_VQSHRNbhs32\000" |
| 11621 | /* 7112 */ "MVE_VQRSHRNbhs32\000" |
| 11622 | /* 7129 */ "MVE_VQSHRNths32\000" |
| 11623 | /* 7145 */ "MVE_VQRSHRNths32\000" |
| 11624 | /* 7162 */ "MVE_VQSHLimms32\000" |
| 11625 | /* 7178 */ "MVE_VRSHR_imms32\000" |
| 11626 | /* 7195 */ "MVE_VSHR_imms32\000" |
| 11627 | /* 7211 */ "MVE_VQSHLU_imms32\000" |
| 11628 | /* 7229 */ "MVE_VQDMLAH_qrs32\000" |
| 11629 | /* 7247 */ "MVE_VQRDMLAH_qrs32\000" |
| 11630 | /* 7266 */ "MVE_VQDMLASH_qrs32\000" |
| 11631 | /* 7285 */ "MVE_VQRDMLASH_qrs32\000" |
| 11632 | /* 7305 */ "MVE_VQSHL_qrs32\000" |
| 11633 | /* 7321 */ "MVE_VQRSHL_qrs32\000" |
| 11634 | /* 7338 */ "MVE_VRSHL_qrs32\000" |
| 11635 | /* 7354 */ "MVE_VSHL_qrs32\000" |
| 11636 | /* 7369 */ "MVE_VRMLALDAVHxs32\000" |
| 11637 | /* 7388 */ "MVE_VRMLSLDAVHxs32\000" |
| 11638 | /* 7407 */ "MVE_VMLADAVxs32\000" |
| 11639 | /* 7423 */ "MVE_VMLALDAVxs32\000" |
| 11640 | /* 7440 */ "MVE_VMLSLDAVxs32\000" |
| 11641 | /* 7457 */ "MVE_VMLSDAVxs32\000" |
| 11642 | /* 7473 */ "MVE_VRMLALDAVHaxs32\000" |
| 11643 | /* 7493 */ "MVE_VRMLSLDAVHaxs32\000" |
| 11644 | /* 7513 */ "MVE_VMLADAVaxs32\000" |
| 11645 | /* 7530 */ "MVE_VMLALDAVaxs32\000" |
| 11646 | /* 7548 */ "MVE_VMLSLDAVaxs32\000" |
| 11647 | /* 7566 */ "MVE_VMLSDAVaxs32\000" |
| 11648 | /* 7583 */ "MVE_VPTv4u32\000" |
| 11649 | /* 7596 */ "MVE_VMULLBu32\000" |
| 11650 | /* 7610 */ "MVE_VHSUBu32\000" |
| 11651 | /* 7623 */ "MVE_VQSUBu32\000" |
| 11652 | /* 7636 */ "MVE_VABDu32\000" |
| 11653 | /* 7648 */ "MVE_VRHADDu32\000" |
| 11654 | /* 7662 */ "MVE_VHADDu32\000" |
| 11655 | /* 7675 */ "MVE_VQADDu32\000" |
| 11656 | /* 7688 */ "MVE_VRMULHu32\000" |
| 11657 | /* 7702 */ "MVE_VMULHu32\000" |
| 11658 | /* 7715 */ "MVE_VRMLALDAVHu32\000" |
| 11659 | /* 7733 */ "VPMINu32\000" |
| 11660 | /* 7742 */ "MVE_VMINu32\000" |
| 11661 | /* 7754 */ "MVE_VCMPu32\000" |
| 11662 | /* 7766 */ "MVE_VDDUPu32\000" |
| 11663 | /* 7779 */ "MVE_VIDUPu32\000" |
| 11664 | /* 7792 */ "MVE_VDWDUPu32\000" |
| 11665 | /* 7806 */ "MVE_VIWDUPu32\000" |
| 11666 | /* 7820 */ "MVE_VMULLTu32\000" |
| 11667 | /* 7834 */ "MVE_VABAVu32\000" |
| 11668 | /* 7847 */ "MVE_VMLADAVu32\000" |
| 11669 | /* 7862 */ "MVE_VMLALDAVu32\000" |
| 11670 | /* 7878 */ "MVE_VMINVu32\000" |
| 11671 | /* 7891 */ "MVE_VMAXVu32\000" |
| 11672 | /* 7904 */ "VPMAXu32\000" |
| 11673 | /* 7913 */ "MVE_VMAXu32\000" |
| 11674 | /* 7925 */ "MVE_VHSUB_qr_u32\000" |
| 11675 | /* 7942 */ "MVE_VQSUB_qr_u32\000" |
| 11676 | /* 7959 */ "MVE_VHADD_qr_u32\000" |
| 11677 | /* 7976 */ "MVE_VQADD_qr_u32\000" |
| 11678 | /* 7993 */ "MVE_VRMLALDAVHau32\000" |
| 11679 | /* 8012 */ "MVE_VMLADAVau32\000" |
| 11680 | /* 8028 */ "MVE_VMLALDAVau32\000" |
| 11681 | /* 8045 */ "MVE_VQSHL_by_vecu32\000" |
| 11682 | /* 8065 */ "MVE_VQRSHL_by_vecu32\000" |
| 11683 | /* 8086 */ "MVE_VRSHL_by_vecu32\000" |
| 11684 | /* 8106 */ "MVE_VSHL_by_vecu32\000" |
| 11685 | /* 8125 */ "MVE_VQSHRNbhu32\000" |
| 11686 | /* 8141 */ "MVE_VQRSHRNbhu32\000" |
| 11687 | /* 8158 */ "MVE_VQSHRNthu32\000" |
| 11688 | /* 8174 */ "MVE_VQRSHRNthu32\000" |
| 11689 | /* 8191 */ "MVE_VQSHLimmu32\000" |
| 11690 | /* 8207 */ "MVE_VRSHR_immu32\000" |
| 11691 | /* 8224 */ "MVE_VSHR_immu32\000" |
| 11692 | /* 8240 */ "MVE_VQSHL_qru32\000" |
| 11693 | /* 8256 */ "MVE_VQRSHL_qru32\000" |
| 11694 | /* 8273 */ "MVE_VRSHL_qru32\000" |
| 11695 | /* 8289 */ "MVE_VSHL_qru32\000" |
| 11696 | /* 8304 */ "t2MRC2\000" |
| 11697 | /* 8311 */ "t2MRRC2\000" |
| 11698 | /* 8319 */ "G_FLOG2\000" |
| 11699 | /* 8327 */ "SHA256H2\000" |
| 11700 | /* 8336 */ "VTBL2\000" |
| 11701 | /* 8342 */ "G_FATAN2\000" |
| 11702 | /* 8351 */ "t2CDP2\000" |
| 11703 | /* 8358 */ "G_FEXP2\000" |
| 11704 | /* 8366 */ "t2MCR2\000" |
| 11705 | /* 8373 */ "VMRS_MVFR2\000" |
| 11706 | /* 8384 */ "t2MCRR2\000" |
| 11707 | /* 8392 */ "t2DCPS2\000" |
| 11708 | /* 8400 */ "VMSR_FPINST2\000" |
| 11709 | /* 8413 */ "VMRS_FPINST2\000" |
| 11710 | /* 8426 */ "VLLDM_T2\000" |
| 11711 | /* 8435 */ "VLSTM_T2\000" |
| 11712 | /* 8444 */ "VTBX2\000" |
| 11713 | /* 8450 */ "CDE_CX2\000" |
| 11714 | /* 8458 */ "KCFI_CHECK_Thumb2\000" |
| 11715 | /* 8476 */ "VLD2DUPd32x2\000" |
| 11716 | /* 8489 */ "VLD2DUPd16x2\000" |
| 11717 | /* 8502 */ "VLD2DUPd8x2\000" |
| 11718 | /* 8514 */ "VTBL3\000" |
| 11719 | /* 8520 */ "t2DCPS3\000" |
| 11720 | /* 8528 */ "VTBX3\000" |
| 11721 | /* 8534 */ "CDE_CX3\000" |
| 11722 | /* 8542 */ "tSUBi3\000" |
| 11723 | /* 8549 */ "tADDi3\000" |
| 11724 | /* 8556 */ "tSUBSi3\000" |
| 11725 | /* 8564 */ "tADDSi3\000" |
| 11726 | /* 8572 */ "MVE_VCTP64\000" |
| 11727 | /* 8583 */ "CMP_SWAP_64\000" |
| 11728 | /* 8595 */ "MVE_DLSTP_64\000" |
| 11729 | /* 8608 */ "MVE_WLSTP_64\000" |
| 11730 | /* 8621 */ "VLD1d64\000" |
| 11731 | /* 8629 */ "VST1d64\000" |
| 11732 | /* 8637 */ "VSUBv1i64\000" |
| 11733 | /* 8647 */ "VADDv1i64\000" |
| 11734 | /* 8657 */ "VSLIv1i64\000" |
| 11735 | /* 8667 */ "VSRIv1i64\000" |
| 11736 | /* 8677 */ "VMOVv1i64\000" |
| 11737 | /* 8687 */ "VSHLiv1i64\000" |
| 11738 | /* 8698 */ "VQSHLsiv1i64\000" |
| 11739 | /* 8711 */ "VQSHLuiv1i64\000" |
| 11740 | /* 8724 */ "VRSRAsv1i64\000" |
| 11741 | /* 8736 */ "VSRAsv1i64\000" |
| 11742 | /* 8747 */ "VQSUBsv1i64\000" |
| 11743 | /* 8759 */ "VQADDsv1i64\000" |
| 11744 | /* 8771 */ "VQSHLsv1i64\000" |
| 11745 | /* 8783 */ "VQRSHLsv1i64\000" |
| 11746 | /* 8796 */ "VRSHLsv1i64\000" |
| 11747 | /* 8808 */ "VSHLsv1i64\000" |
| 11748 | /* 8819 */ "VRSHRsv1i64\000" |
| 11749 | /* 8831 */ "VSHRsv1i64\000" |
| 11750 | /* 8842 */ "VRSRAuv1i64\000" |
| 11751 | /* 8854 */ "VSRAuv1i64\000" |
| 11752 | /* 8865 */ "VQSUBuv1i64\000" |
| 11753 | /* 8877 */ "VQADDuv1i64\000" |
| 11754 | /* 8889 */ "VQSHLuv1i64\000" |
| 11755 | /* 8901 */ "VQRSHLuv1i64\000" |
| 11756 | /* 8914 */ "VRSHLuv1i64\000" |
| 11757 | /* 8926 */ "VSHLuv1i64\000" |
| 11758 | /* 8937 */ "VRSHRuv1i64\000" |
| 11759 | /* 8949 */ "VSHRuv1i64\000" |
| 11760 | /* 8960 */ "VQSHLsuv1i64\000" |
| 11761 | /* 8973 */ "VSUBv2i64\000" |
| 11762 | /* 8983 */ "VADDv2i64\000" |
| 11763 | /* 8993 */ "VSLIv2i64\000" |
| 11764 | /* 9003 */ "VSRIv2i64\000" |
| 11765 | /* 9013 */ "VQDMLALv2i64\000" |
| 11766 | /* 9026 */ "VQDMULLv2i64\000" |
| 11767 | /* 9039 */ "VQDMLSLv2i64\000" |
| 11768 | /* 9052 */ "VMOVv2i64\000" |
| 11769 | /* 9062 */ "VSHLiv2i64\000" |
| 11770 | /* 9073 */ "VQSHLsiv2i64\000" |
| 11771 | /* 9086 */ "VQSHLuiv2i64\000" |
| 11772 | /* 9099 */ "VRSRAsv2i64\000" |
| 11773 | /* 9111 */ "VSRAsv2i64\000" |
| 11774 | /* 9122 */ "VQSUBsv2i64\000" |
| 11775 | /* 9134 */ "VQADDsv2i64\000" |
| 11776 | /* 9146 */ "VABALsv2i64\000" |
| 11777 | /* 9158 */ "VMLALsv2i64\000" |
| 11778 | /* 9170 */ "VSUBLsv2i64\000" |
| 11779 | /* 9182 */ "VABDLsv2i64\000" |
| 11780 | /* 9194 */ "VADDLsv2i64\000" |
| 11781 | /* 9206 */ "VQSHLsv2i64\000" |
| 11782 | /* 9218 */ "VQRSHLsv2i64\000" |
| 11783 | /* 9231 */ "VRSHLsv2i64\000" |
| 11784 | /* 9243 */ "VSHLsv2i64\000" |
| 11785 | /* 9254 */ "VSHLLsv2i64\000" |
| 11786 | /* 9266 */ "VMULLsv2i64\000" |
| 11787 | /* 9278 */ "VMLSLsv2i64\000" |
| 11788 | /* 9290 */ "VMOVLsv2i64\000" |
| 11789 | /* 9302 */ "VRSHRsv2i64\000" |
| 11790 | /* 9314 */ "VSHRsv2i64\000" |
| 11791 | /* 9325 */ "VSUBWsv2i64\000" |
| 11792 | /* 9337 */ "VADDWsv2i64\000" |
| 11793 | /* 9349 */ "VRSRAuv2i64\000" |
| 11794 | /* 9361 */ "VSRAuv2i64\000" |
| 11795 | /* 9372 */ "VQSUBuv2i64\000" |
| 11796 | /* 9384 */ "VQADDuv2i64\000" |
| 11797 | /* 9396 */ "VABALuv2i64\000" |
| 11798 | /* 9408 */ "VMLALuv2i64\000" |
| 11799 | /* 9420 */ "VSUBLuv2i64\000" |
| 11800 | /* 9432 */ "VABDLuv2i64\000" |
| 11801 | /* 9444 */ "VADDLuv2i64\000" |
| 11802 | /* 9456 */ "VQSHLuv2i64\000" |
| 11803 | /* 9468 */ "VQRSHLuv2i64\000" |
| 11804 | /* 9481 */ "VRSHLuv2i64\000" |
| 11805 | /* 9493 */ "VSHLuv2i64\000" |
| 11806 | /* 9504 */ "VSHLLuv2i64\000" |
| 11807 | /* 9516 */ "VMULLuv2i64\000" |
| 11808 | /* 9528 */ "VMLSLuv2i64\000" |
| 11809 | /* 9540 */ "VMOVLuv2i64\000" |
| 11810 | /* 9552 */ "VRSHRuv2i64\000" |
| 11811 | /* 9564 */ "VSHRuv2i64\000" |
| 11812 | /* 9575 */ "VSUBWuv2i64\000" |
| 11813 | /* 9587 */ "VADDWuv2i64\000" |
| 11814 | /* 9599 */ "VQSHLsuv2i64\000" |
| 11815 | /* 9612 */ "BCCi64\000" |
| 11816 | /* 9619 */ "BCCZi64\000" |
| 11817 | /* 9627 */ "MVE_VMOVimmi64\000" |
| 11818 | /* 9642 */ "VMULLp64\000" |
| 11819 | /* 9651 */ "VLD1q64\000" |
| 11820 | /* 9659 */ "VST1q64\000" |
| 11821 | /* 9667 */ "VEXTq64\000" |
| 11822 | /* 9675 */ "VTBL4\000" |
| 11823 | /* 9681 */ "VTBX4\000" |
| 11824 | /* 9687 */ "TAILJMPr4\000" |
| 11825 | /* 9697 */ "MLAv5\000" |
| 11826 | /* 9703 */ "SMLALv5\000" |
| 11827 | /* 9711 */ "UMLALv5\000" |
| 11828 | /* 9719 */ "SMULLv5\000" |
| 11829 | /* 9727 */ "UMULLv5\000" |
| 11830 | /* 9735 */ "MULv5\000" |
| 11831 | /* 9741 */ "t2SXTAB16\000" |
| 11832 | /* 9751 */ "t2UXTAB16\000" |
| 11833 | /* 9761 */ "MVE_VSTRB16\000" |
| 11834 | /* 9773 */ "t2SXTB16\000" |
| 11835 | /* 9782 */ "t2UXTB16\000" |
| 11836 | /* 9791 */ "t2SHSUB16\000" |
| 11837 | /* 9801 */ "t2UHSUB16\000" |
| 11838 | /* 9811 */ "t2QSUB16\000" |
| 11839 | /* 9820 */ "t2UQSUB16\000" |
| 11840 | /* 9830 */ "t2SSUB16\000" |
| 11841 | /* 9839 */ "t2USUB16\000" |
| 11842 | /* 9848 */ "t2SHADD16\000" |
| 11843 | /* 9858 */ "t2UHADD16\000" |
| 11844 | /* 9868 */ "t2QADD16\000" |
| 11845 | /* 9877 */ "t2UQADD16\000" |
| 11846 | /* 9887 */ "t2SADD16\000" |
| 11847 | /* 9896 */ "t2UADD16\000" |
| 11848 | /* 9905 */ "MVE_VCTP16\000" |
| 11849 | /* 9916 */ "MVE_VDUP16\000" |
| 11850 | /* 9927 */ "MVE_VBRSR16\000" |
| 11851 | /* 9939 */ "MVE_VLDRBS16\000" |
| 11852 | /* 9952 */ "t2SSAT16\000" |
| 11853 | /* 9961 */ "t2USAT16\000" |
| 11854 | /* 9970 */ "MVE_VLDRBU16\000" |
| 11855 | /* 9983 */ "MVE_VLDRHU16\000" |
| 11856 | /* 9996 */ "MVE_VSTRHU16\000" |
| 11857 | /* 10009 */ "t2REV16\000" |
| 11858 | /* 10017 */ "tREV16\000" |
| 11859 | /* 10024 */ "MVE_VLD20_16\000" |
| 11860 | /* 10037 */ "MVE_VST20_16\000" |
| 11861 | /* 10050 */ "MVE_VLD40_16\000" |
| 11862 | /* 10063 */ "MVE_VST40_16\000" |
| 11863 | /* 10076 */ "MVE_VLD21_16\000" |
| 11864 | /* 10089 */ "MVE_VST21_16\000" |
| 11865 | /* 10102 */ "MVE_VLD41_16\000" |
| 11866 | /* 10115 */ "MVE_VST41_16\000" |
| 11867 | /* 10128 */ "MVE_VREV32_16\000" |
| 11868 | /* 10142 */ "MVE_VLD42_16\000" |
| 11869 | /* 10155 */ "MVE_VST42_16\000" |
| 11870 | /* 10168 */ "MVE_VLD43_16\000" |
| 11871 | /* 10181 */ "MVE_VST43_16\000" |
| 11872 | /* 10194 */ "MVE_VREV64_16\000" |
| 11873 | /* 10208 */ "tCMP_SWAP_16\000" |
| 11874 | /* 10221 */ "MVE_DLSTP_16\000" |
| 11875 | /* 10234 */ "MVE_WLSTP_16\000" |
| 11876 | /* 10247 */ "MVE_VMOV_to_lane_16\000" |
| 11877 | /* 10267 */ "VLD3dWB_fixed_Asm_16\000" |
| 11878 | /* 10288 */ "VST3dWB_fixed_Asm_16\000" |
| 11879 | /* 10309 */ "VLD4dWB_fixed_Asm_16\000" |
| 11880 | /* 10330 */ "VST4dWB_fixed_Asm_16\000" |
| 11881 | /* 10351 */ "VLD1LNdWB_fixed_Asm_16\000" |
| 11882 | /* 10374 */ "VST1LNdWB_fixed_Asm_16\000" |
| 11883 | /* 10397 */ "VLD2LNdWB_fixed_Asm_16\000" |
| 11884 | /* 10420 */ "VST2LNdWB_fixed_Asm_16\000" |
| 11885 | /* 10443 */ "VLD3LNdWB_fixed_Asm_16\000" |
| 11886 | /* 10466 */ "VST3LNdWB_fixed_Asm_16\000" |
| 11887 | /* 10489 */ "VLD4LNdWB_fixed_Asm_16\000" |
| 11888 | /* 10512 */ "VST4LNdWB_fixed_Asm_16\000" |
| 11889 | /* 10535 */ "VLD3DUPdWB_fixed_Asm_16\000" |
| 11890 | /* 10559 */ "VLD4DUPdWB_fixed_Asm_16\000" |
| 11891 | /* 10583 */ "VLD3qWB_fixed_Asm_16\000" |
| 11892 | /* 10604 */ "VST3qWB_fixed_Asm_16\000" |
| 11893 | /* 10625 */ "VLD4qWB_fixed_Asm_16\000" |
| 11894 | /* 10646 */ "VST4qWB_fixed_Asm_16\000" |
| 11895 | /* 10667 */ "VLD2LNqWB_fixed_Asm_16\000" |
| 11896 | /* 10690 */ "VST2LNqWB_fixed_Asm_16\000" |
| 11897 | /* 10713 */ "VLD3LNqWB_fixed_Asm_16\000" |
| 11898 | /* 10736 */ "VST3LNqWB_fixed_Asm_16\000" |
| 11899 | /* 10759 */ "VLD4LNqWB_fixed_Asm_16\000" |
| 11900 | /* 10782 */ "VST4LNqWB_fixed_Asm_16\000" |
| 11901 | /* 10805 */ "VLD3DUPqWB_fixed_Asm_16\000" |
| 11902 | /* 10829 */ "VLD4DUPqWB_fixed_Asm_16\000" |
| 11903 | /* 10853 */ "VLD3dWB_register_Asm_16\000" |
| 11904 | /* 10877 */ "VST3dWB_register_Asm_16\000" |
| 11905 | /* 10901 */ "VLD4dWB_register_Asm_16\000" |
| 11906 | /* 10925 */ "VST4dWB_register_Asm_16\000" |
| 11907 | /* 10949 */ "VLD1LNdWB_register_Asm_16\000" |
| 11908 | /* 10975 */ "VST1LNdWB_register_Asm_16\000" |
| 11909 | /* 11001 */ "VLD2LNdWB_register_Asm_16\000" |
| 11910 | /* 11027 */ "VST2LNdWB_register_Asm_16\000" |
| 11911 | /* 11053 */ "VLD3LNdWB_register_Asm_16\000" |
| 11912 | /* 11079 */ "VST3LNdWB_register_Asm_16\000" |
| 11913 | /* 11105 */ "VLD4LNdWB_register_Asm_16\000" |
| 11914 | /* 11131 */ "VST4LNdWB_register_Asm_16\000" |
| 11915 | /* 11157 */ "VLD3DUPdWB_register_Asm_16\000" |
| 11916 | /* 11184 */ "VLD4DUPdWB_register_Asm_16\000" |
| 11917 | /* 11211 */ "VLD3qWB_register_Asm_16\000" |
| 11918 | /* 11235 */ "VST3qWB_register_Asm_16\000" |
| 11919 | /* 11259 */ "VLD4qWB_register_Asm_16\000" |
| 11920 | /* 11283 */ "VST4qWB_register_Asm_16\000" |
| 11921 | /* 11307 */ "VLD2LNqWB_register_Asm_16\000" |
| 11922 | /* 11333 */ "VST2LNqWB_register_Asm_16\000" |
| 11923 | /* 11359 */ "VLD3LNqWB_register_Asm_16\000" |
| 11924 | /* 11385 */ "VST3LNqWB_register_Asm_16\000" |
| 11925 | /* 11411 */ "VLD4LNqWB_register_Asm_16\000" |
| 11926 | /* 11437 */ "VST4LNqWB_register_Asm_16\000" |
| 11927 | /* 11463 */ "VLD3DUPqWB_register_Asm_16\000" |
| 11928 | /* 11490 */ "VLD4DUPqWB_register_Asm_16\000" |
| 11929 | /* 11517 */ "VLD3dAsm_16\000" |
| 11930 | /* 11529 */ "VST3dAsm_16\000" |
| 11931 | /* 11541 */ "VLD4dAsm_16\000" |
| 11932 | /* 11553 */ "VST4dAsm_16\000" |
| 11933 | /* 11565 */ "VLD1LNdAsm_16\000" |
| 11934 | /* 11579 */ "VST1LNdAsm_16\000" |
| 11935 | /* 11593 */ "VLD2LNdAsm_16\000" |
| 11936 | /* 11607 */ "VST2LNdAsm_16\000" |
| 11937 | /* 11621 */ "VLD3LNdAsm_16\000" |
| 11938 | /* 11635 */ "VST3LNdAsm_16\000" |
| 11939 | /* 11649 */ "VLD4LNdAsm_16\000" |
| 11940 | /* 11663 */ "VST4LNdAsm_16\000" |
| 11941 | /* 11677 */ "VLD3DUPdAsm_16\000" |
| 11942 | /* 11692 */ "VLD4DUPdAsm_16\000" |
| 11943 | /* 11707 */ "VLD3qAsm_16\000" |
| 11944 | /* 11719 */ "VST3qAsm_16\000" |
| 11945 | /* 11731 */ "VLD4qAsm_16\000" |
| 11946 | /* 11743 */ "VST4qAsm_16\000" |
| 11947 | /* 11755 */ "VLD2LNqAsm_16\000" |
| 11948 | /* 11769 */ "VST2LNqAsm_16\000" |
| 11949 | /* 11783 */ "VLD3LNqAsm_16\000" |
| 11950 | /* 11797 */ "VST3LNqAsm_16\000" |
| 11951 | /* 11811 */ "VLD4LNqAsm_16\000" |
| 11952 | /* 11825 */ "VST4LNqAsm_16\000" |
| 11953 | /* 11839 */ "VLD3DUPqAsm_16\000" |
| 11954 | /* 11854 */ "VLD4DUPqAsm_16\000" |
| 11955 | /* 11869 */ "VLD2b16\000" |
| 11956 | /* 11877 */ "VST2b16\000" |
| 11957 | /* 11885 */ "VLD1d16\000" |
| 11958 | /* 11893 */ "VST1d16\000" |
| 11959 | /* 11901 */ "VREV32d16\000" |
| 11960 | /* 11911 */ "VLD2d16\000" |
| 11961 | /* 11919 */ "VST2d16\000" |
| 11962 | /* 11927 */ "VLD3d16\000" |
| 11963 | /* 11935 */ "VST3d16\000" |
| 11964 | /* 11943 */ "VREV64d16\000" |
| 11965 | /* 11953 */ "VLD4d16\000" |
| 11966 | /* 11961 */ "VST4d16\000" |
| 11967 | /* 11969 */ "VLD1LNd16\000" |
| 11968 | /* 11979 */ "VST1LNd16\000" |
| 11969 | /* 11989 */ "VLD2LNd16\000" |
| 11970 | /* 11999 */ "VST2LNd16\000" |
| 11971 | /* 12009 */ "VLD3LNd16\000" |
| 11972 | /* 12019 */ "VST3LNd16\000" |
| 11973 | /* 12029 */ "VLD4LNd16\000" |
| 11974 | /* 12039 */ "VST4LNd16\000" |
| 11975 | /* 12049 */ "VTRNd16\000" |
| 11976 | /* 12057 */ "VZIPd16\000" |
| 11977 | /* 12065 */ "VLD1DUPd16\000" |
| 11978 | /* 12076 */ "VLD2DUPd16\000" |
| 11979 | /* 12087 */ "VLD3DUPd16\000" |
| 11980 | /* 12098 */ "VLD4DUPd16\000" |
| 11981 | /* 12109 */ "VUZPd16\000" |
| 11982 | /* 12117 */ "VEXTd16\000" |
| 11983 | /* 12125 */ "VCMLAv4f16\000" |
| 11984 | /* 12136 */ "VCADDv4f16\000" |
| 11985 | /* 12147 */ "VCGEzv4f16\000" |
| 11986 | /* 12158 */ "VCLEzv4f16\000" |
| 11987 | /* 12169 */ "VCEQzv4f16\000" |
| 11988 | /* 12180 */ "VCGTzv4f16\000" |
| 11989 | /* 12191 */ "VCLTzv4f16\000" |
| 11990 | /* 12202 */ "VCMLAv8f16\000" |
| 11991 | /* 12213 */ "VCADDv8f16\000" |
| 11992 | /* 12224 */ "MVE_VPTv8f16\000" |
| 11993 | /* 12237 */ "VCGEzv8f16\000" |
| 11994 | /* 12248 */ "VCLEzv8f16\000" |
| 11995 | /* 12259 */ "VCEQzv8f16\000" |
| 11996 | /* 12270 */ "VCGTzv8f16\000" |
| 11997 | /* 12281 */ "VCLTzv8f16\000" |
| 11998 | /* 12292 */ "MVE_VCMLAf16\000" |
| 11999 | /* 12305 */ "MVE_VFMAf16\000" |
| 12000 | /* 12317 */ "MVE_VMINNMAf16\000" |
| 12001 | /* 12332 */ "MVE_VMAXNMAf16\000" |
| 12002 | /* 12347 */ "MVE_VSUBf16\000" |
| 12003 | /* 12359 */ "MVE_VABDf16\000" |
| 12004 | /* 12371 */ "MVE_VCADDf16\000" |
| 12005 | /* 12384 */ "MVE_VADDf16\000" |
| 12006 | /* 12396 */ "MVE_VNEGf16\000" |
| 12007 | /* 12408 */ "MVE_VCMULf16\000" |
| 12008 | /* 12421 */ "MVE_VMULf16\000" |
| 12009 | /* 12433 */ "MVE_VMINNMf16\000" |
| 12010 | /* 12447 */ "MVE_VMAXNMf16\000" |
| 12011 | /* 12461 */ "MVE_VCMPf16\000" |
| 12012 | /* 12473 */ "MVE_VABSf16\000" |
| 12013 | /* 12485 */ "MVE_VFMSf16\000" |
| 12014 | /* 12497 */ "MVE_VFMA_qr_Sf16\000" |
| 12015 | /* 12514 */ "MVE_VMINNMAVf16\000" |
| 12016 | /* 12530 */ "MVE_VMAXNMAVf16\000" |
| 12017 | /* 12546 */ "MVE_VMINNMVf16\000" |
| 12018 | /* 12561 */ "MVE_VMAXNMVf16\000" |
| 12019 | /* 12576 */ "MVE_VFMA_qr_f16\000" |
| 12020 | /* 12592 */ "MVE_VSUB_qr_f16\000" |
| 12021 | /* 12608 */ "MVE_VADD_qr_f16\000" |
| 12022 | /* 12624 */ "MVE_VMUL_qr_f16\000" |
| 12023 | /* 12640 */ "VMLAv4i16\000" |
| 12024 | /* 12650 */ "VSUBv4i16\000" |
| 12025 | /* 12660 */ "VADDv4i16\000" |
| 12026 | /* 12670 */ "VQNEGv4i16\000" |
| 12027 | /* 12681 */ "VQRDMLAHv4i16\000" |
| 12028 | /* 12695 */ "VQDMULHv4i16\000" |
| 12029 | /* 12708 */ "VQRDMULHv4i16\000" |
| 12030 | /* 12722 */ "VQRDMLSHv4i16\000" |
| 12031 | /* 12736 */ "VSLIv4i16\000" |
| 12032 | /* 12746 */ "VSRIv4i16\000" |
| 12033 | /* 12756 */ "VMULv4i16\000" |
| 12034 | /* 12766 */ "VRSUBHNv4i16\000" |
| 12035 | /* 12779 */ "VSUBHNv4i16\000" |
| 12036 | /* 12791 */ "VRADDHNv4i16\000" |
| 12037 | /* 12804 */ "VADDHNv4i16\000" |
| 12038 | /* 12816 */ "VRSHRNv4i16\000" |
| 12039 | /* 12828 */ "VSHRNv4i16\000" |
| 12040 | /* 12839 */ "VQSHRUNv4i16\000" |
| 12041 | /* 12852 */ "VQRSHRUNv4i16\000" |
| 12042 | /* 12866 */ "VMVNv4i16\000" |
| 12043 | /* 12876 */ "VMOVNv4i16\000" |
| 12044 | /* 12887 */ "VCEQv4i16\000" |
| 12045 | /* 12897 */ "VQABSv4i16\000" |
| 12046 | /* 12908 */ "VABSv4i16\000" |
| 12047 | /* 12918 */ "VCLSv4i16\000" |
| 12048 | /* 12928 */ "VMLSv4i16\000" |
| 12049 | /* 12938 */ "VTSTv4i16\000" |
| 12050 | /* 12948 */ "VMOVv4i16\000" |
| 12051 | /* 12958 */ "VCLZv4i16\000" |
| 12052 | /* 12968 */ "VBICiv4i16\000" |
| 12053 | /* 12979 */ "VSHLiv4i16\000" |
| 12054 | /* 12990 */ "VORRiv4i16\000" |
| 12055 | /* 13001 */ "VQSHLsiv4i16\000" |
| 12056 | /* 13014 */ "VQSHLuiv4i16\000" |
| 12057 | /* 13027 */ "VMLAslv4i16\000" |
| 12058 | /* 13039 */ "VQRDMLAHslv4i16\000" |
| 12059 | /* 13055 */ "VQDMULHslv4i16\000" |
| 12060 | /* 13070 */ "VQRDMULHslv4i16\000" |
| 12061 | /* 13086 */ "VQRDMLSHslv4i16\000" |
| 12062 | /* 13102 */ "VQDMLALslv4i16\000" |
| 12063 | /* 13117 */ "VQDMULLslv4i16\000" |
| 12064 | /* 13132 */ "VQDMLSLslv4i16\000" |
| 12065 | /* 13147 */ "VMULslv4i16\000" |
| 12066 | /* 13159 */ "VMLSslv4i16\000" |
| 12067 | /* 13171 */ "VABAsv4i16\000" |
| 12068 | /* 13182 */ "VRSRAsv4i16\000" |
| 12069 | /* 13194 */ "VSRAsv4i16\000" |
| 12070 | /* 13205 */ "VHSUBsv4i16\000" |
| 12071 | /* 13217 */ "VQSUBsv4i16\000" |
| 12072 | /* 13229 */ "VABDsv4i16\000" |
| 12073 | /* 13240 */ "VRHADDsv4i16\000" |
| 12074 | /* 13253 */ "VHADDsv4i16\000" |
| 12075 | /* 13265 */ "VQADDsv4i16\000" |
| 12076 | /* 13277 */ "VCGEsv4i16\000" |
| 12077 | /* 13288 */ "VPADALsv4i16\000" |
| 12078 | /* 13301 */ "VPADDLsv4i16\000" |
| 12079 | /* 13314 */ "VQSHLsv4i16\000" |
| 12080 | /* 13326 */ "VQRSHLsv4i16\000" |
| 12081 | /* 13339 */ "VRSHLsv4i16\000" |
| 12082 | /* 13351 */ "VSHLsv4i16\000" |
| 12083 | /* 13362 */ "VMINsv4i16\000" |
| 12084 | /* 13373 */ "VQSHRNsv4i16\000" |
| 12085 | /* 13386 */ "VQRSHRNsv4i16\000" |
| 12086 | /* 13400 */ "VQMOVNsv4i16\000" |
| 12087 | /* 13413 */ "VRSHRsv4i16\000" |
| 12088 | /* 13425 */ "VSHRsv4i16\000" |
| 12089 | /* 13436 */ "VCGTsv4i16\000" |
| 12090 | /* 13447 */ "VMAXsv4i16\000" |
| 12091 | /* 13458 */ "VMLALslsv4i16\000" |
| 12092 | /* 13472 */ "VMULLslsv4i16\000" |
| 12093 | /* 13486 */ "VMLSLslsv4i16\000" |
| 12094 | /* 13500 */ "VABAuv4i16\000" |
| 12095 | /* 13511 */ "VRSRAuv4i16\000" |
| 12096 | /* 13523 */ "VSRAuv4i16\000" |
| 12097 | /* 13534 */ "VHSUBuv4i16\000" |
| 12098 | /* 13546 */ "VQSUBuv4i16\000" |
| 12099 | /* 13558 */ "VABDuv4i16\000" |
| 12100 | /* 13569 */ "VRHADDuv4i16\000" |
| 12101 | /* 13582 */ "VHADDuv4i16\000" |
| 12102 | /* 13594 */ "VQADDuv4i16\000" |
| 12103 | /* 13606 */ "VCGEuv4i16\000" |
| 12104 | /* 13617 */ "VPADALuv4i16\000" |
| 12105 | /* 13630 */ "VPADDLuv4i16\000" |
| 12106 | /* 13643 */ "VQSHLuv4i16\000" |
| 12107 | /* 13655 */ "VQRSHLuv4i16\000" |
| 12108 | /* 13668 */ "VRSHLuv4i16\000" |
| 12109 | /* 13680 */ "VSHLuv4i16\000" |
| 12110 | /* 13691 */ "VMINuv4i16\000" |
| 12111 | /* 13702 */ "VQSHRNuv4i16\000" |
| 12112 | /* 13715 */ "VQRSHRNuv4i16\000" |
| 12113 | /* 13729 */ "VQMOVNuv4i16\000" |
| 12114 | /* 13742 */ "VRSHRuv4i16\000" |
| 12115 | /* 13754 */ "VSHRuv4i16\000" |
| 12116 | /* 13765 */ "VCGTuv4i16\000" |
| 12117 | /* 13776 */ "VMAXuv4i16\000" |
| 12118 | /* 13787 */ "VMLALsluv4i16\000" |
| 12119 | /* 13801 */ "VMULLsluv4i16\000" |
| 12120 | /* 13815 */ "VMLSLsluv4i16\000" |
| 12121 | /* 13829 */ "VQSHLsuv4i16\000" |
| 12122 | /* 13842 */ "VQMOVNsuv4i16\000" |
| 12123 | /* 13856 */ "VCGEzv4i16\000" |
| 12124 | /* 13867 */ "VCLEzv4i16\000" |
| 12125 | /* 13878 */ "VCEQzv4i16\000" |
| 12126 | /* 13889 */ "VCGTzv4i16\000" |
| 12127 | /* 13900 */ "VCLTzv4i16\000" |
| 12128 | /* 13911 */ "VMLAv8i16\000" |
| 12129 | /* 13921 */ "VSUBv8i16\000" |
| 12130 | /* 13931 */ "VADDv8i16\000" |
| 12131 | /* 13941 */ "VQNEGv8i16\000" |
| 12132 | /* 13952 */ "VQRDMLAHv8i16\000" |
| 12133 | /* 13966 */ "VQDMULHv8i16\000" |
| 12134 | /* 13979 */ "VQRDMULHv8i16\000" |
| 12135 | /* 13993 */ "VQRDMLSHv8i16\000" |
| 12136 | /* 14007 */ "VSLIv8i16\000" |
| 12137 | /* 14017 */ "VSRIv8i16\000" |
| 12138 | /* 14027 */ "VMULv8i16\000" |
| 12139 | /* 14037 */ "VMVNv8i16\000" |
| 12140 | /* 14047 */ "VCEQv8i16\000" |
| 12141 | /* 14057 */ "VQABSv8i16\000" |
| 12142 | /* 14068 */ "VABSv8i16\000" |
| 12143 | /* 14078 */ "VCLSv8i16\000" |
| 12144 | /* 14088 */ "VMLSv8i16\000" |
| 12145 | /* 14098 */ "MVE_VPTv8i16\000" |
| 12146 | /* 14111 */ "VTSTv8i16\000" |
| 12147 | /* 14121 */ "VMOVv8i16\000" |
| 12148 | /* 14131 */ "VCLZv8i16\000" |
| 12149 | /* 14141 */ "VBICiv8i16\000" |
| 12150 | /* 14152 */ "VSHLiv8i16\000" |
| 12151 | /* 14163 */ "VORRiv8i16\000" |
| 12152 | /* 14174 */ "VQSHLsiv8i16\000" |
| 12153 | /* 14187 */ "VQSHLuiv8i16\000" |
| 12154 | /* 14200 */ "VMLAslv8i16\000" |
| 12155 | /* 14212 */ "VQRDMLAHslv8i16\000" |
| 12156 | /* 14228 */ "VQDMULHslv8i16\000" |
| 12157 | /* 14243 */ "VQRDMULHslv8i16\000" |
| 12158 | /* 14259 */ "VQRDMLSHslv8i16\000" |
| 12159 | /* 14275 */ "VMULslv8i16\000" |
| 12160 | /* 14287 */ "VMLSslv8i16\000" |
| 12161 | /* 14299 */ "VABAsv8i16\000" |
| 12162 | /* 14310 */ "VRSRAsv8i16\000" |
| 12163 | /* 14322 */ "VSRAsv8i16\000" |
| 12164 | /* 14333 */ "VHSUBsv8i16\000" |
| 12165 | /* 14345 */ "VQSUBsv8i16\000" |
| 12166 | /* 14357 */ "VABDsv8i16\000" |
| 12167 | /* 14368 */ "VRHADDsv8i16\000" |
| 12168 | /* 14381 */ "VHADDsv8i16\000" |
| 12169 | /* 14393 */ "VQADDsv8i16\000" |
| 12170 | /* 14405 */ "VCGEsv8i16\000" |
| 12171 | /* 14416 */ "VABALsv8i16\000" |
| 12172 | /* 14428 */ "VPADALsv8i16\000" |
| 12173 | /* 14441 */ "VMLALsv8i16\000" |
| 12174 | /* 14453 */ "VSUBLsv8i16\000" |
| 12175 | /* 14465 */ "VABDLsv8i16\000" |
| 12176 | /* 14477 */ "VPADDLsv8i16\000" |
| 12177 | /* 14490 */ "VADDLsv8i16\000" |
| 12178 | /* 14502 */ "VQSHLsv8i16\000" |
| 12179 | /* 14514 */ "VQRSHLsv8i16\000" |
| 12180 | /* 14527 */ "VRSHLsv8i16\000" |
| 12181 | /* 14539 */ "VSHLsv8i16\000" |
| 12182 | /* 14550 */ "VSHLLsv8i16\000" |
| 12183 | /* 14562 */ "VMULLsv8i16\000" |
| 12184 | /* 14574 */ "VMLSLsv8i16\000" |
| 12185 | /* 14586 */ "VMOVLsv8i16\000" |
| 12186 | /* 14598 */ "VMINsv8i16\000" |
| 12187 | /* 14609 */ "VRSHRsv8i16\000" |
| 12188 | /* 14621 */ "VSHRsv8i16\000" |
| 12189 | /* 14632 */ "VCGTsv8i16\000" |
| 12190 | /* 14643 */ "VSUBWsv8i16\000" |
| 12191 | /* 14655 */ "VADDWsv8i16\000" |
| 12192 | /* 14667 */ "VMAXsv8i16\000" |
| 12193 | /* 14678 */ "VABAuv8i16\000" |
| 12194 | /* 14689 */ "VRSRAuv8i16\000" |
| 12195 | /* 14701 */ "VSRAuv8i16\000" |
| 12196 | /* 14712 */ "VHSUBuv8i16\000" |
| 12197 | /* 14724 */ "VQSUBuv8i16\000" |
| 12198 | /* 14736 */ "VABDuv8i16\000" |
| 12199 | /* 14747 */ "VRHADDuv8i16\000" |
| 12200 | /* 14760 */ "VHADDuv8i16\000" |
| 12201 | /* 14772 */ "VQADDuv8i16\000" |
| 12202 | /* 14784 */ "VCGEuv8i16\000" |
| 12203 | /* 14795 */ "VABALuv8i16\000" |
| 12204 | /* 14807 */ "VPADALuv8i16\000" |
| 12205 | /* 14820 */ "VMLALuv8i16\000" |
| 12206 | /* 14832 */ "VSUBLuv8i16\000" |
| 12207 | /* 14844 */ "VABDLuv8i16\000" |
| 12208 | /* 14856 */ "VPADDLuv8i16\000" |
| 12209 | /* 14869 */ "VADDLuv8i16\000" |
| 12210 | /* 14881 */ "VQSHLuv8i16\000" |
| 12211 | /* 14893 */ "VQRSHLuv8i16\000" |
| 12212 | /* 14906 */ "VRSHLuv8i16\000" |
| 12213 | /* 14918 */ "VSHLuv8i16\000" |
| 12214 | /* 14929 */ "VSHLLuv8i16\000" |
| 12215 | /* 14941 */ "VMULLuv8i16\000" |
| 12216 | /* 14953 */ "VMLSLuv8i16\000" |
| 12217 | /* 14965 */ "VMOVLuv8i16\000" |
| 12218 | /* 14977 */ "VMINuv8i16\000" |
| 12219 | /* 14988 */ "VRSHRuv8i16\000" |
| 12220 | /* 15000 */ "VSHRuv8i16\000" |
| 12221 | /* 15011 */ "VCGTuv8i16\000" |
| 12222 | /* 15022 */ "VSUBWuv8i16\000" |
| 12223 | /* 15034 */ "VADDWuv8i16\000" |
| 12224 | /* 15046 */ "VMAXuv8i16\000" |
| 12225 | /* 15057 */ "VQSHLsuv8i16\000" |
| 12226 | /* 15070 */ "VCGEzv8i16\000" |
| 12227 | /* 15081 */ "VCLEzv8i16\000" |
| 12228 | /* 15092 */ "VCEQzv8i16\000" |
| 12229 | /* 15103 */ "VCGTzv8i16\000" |
| 12230 | /* 15114 */ "VCLTzv8i16\000" |
| 12231 | /* 15125 */ "MVE_VSUBi16\000" |
| 12232 | /* 15137 */ "t2MOVCCi16\000" |
| 12233 | /* 15148 */ "MVE_VCADDi16\000" |
| 12234 | /* 15161 */ "VPADDi16\000" |
| 12235 | /* 15170 */ "MVE_VADDi16\000" |
| 12236 | /* 15182 */ "MVE_VQDMULHi16\000" |
| 12237 | /* 15197 */ "MVE_VQRDMULHi16\000" |
| 12238 | /* 15213 */ "VSHLLi16\000" |
| 12239 | /* 15222 */ "MVE_VMULi16\000" |
| 12240 | /* 15234 */ "VSETLNi16\000" |
| 12241 | /* 15244 */ "MVE_VCMPi16\000" |
| 12242 | /* 15256 */ "t2MOVTi16\000" |
| 12243 | /* 15266 */ "t2MOVi16\000" |
| 12244 | /* 15275 */ "MVE_VMLA_qr_i16\000" |
| 12245 | /* 15291 */ "MVE_VSUB_qr_i16\000" |
| 12246 | /* 15307 */ "MVE_VADD_qr_i16\000" |
| 12247 | /* 15323 */ "MVE_VMUL_qr_i16\000" |
| 12248 | /* 15339 */ "MVE_VMLAS_qr_i16\000" |
| 12249 | /* 15356 */ "MVE_VBICimmi16\000" |
| 12250 | /* 15371 */ "MVE_VMVNimmi16\000" |
| 12251 | /* 15386 */ "MVE_VORRimmi16\000" |
| 12252 | /* 15401 */ "MVE_VMOVimmi16\000" |
| 12253 | /* 15416 */ "MVE_VSHL_immi16\000" |
| 12254 | /* 15432 */ "MVE_VSLIimm16\000" |
| 12255 | /* 15446 */ "MVE_VSRIimm16\000" |
| 12256 | /* 15460 */ "MVE_VMULLBp16\000" |
| 12257 | /* 15474 */ "MVE_VMULLTp16\000" |
| 12258 | /* 15488 */ "VLD1q16\000" |
| 12259 | /* 15496 */ "VST1q16\000" |
| 12260 | /* 15504 */ "VREV32q16\000" |
| 12261 | /* 15514 */ "VLD2q16\000" |
| 12262 | /* 15522 */ "VST2q16\000" |
| 12263 | /* 15530 */ "VLD3q16\000" |
| 12264 | /* 15538 */ "VST3q16\000" |
| 12265 | /* 15546 */ "VREV64q16\000" |
| 12266 | /* 15556 */ "VLD4q16\000" |
| 12267 | /* 15564 */ "VST4q16\000" |
| 12268 | /* 15572 */ "VLD2LNq16\000" |
| 12269 | /* 15582 */ "VST2LNq16\000" |
| 12270 | /* 15592 */ "VLD3LNq16\000" |
| 12271 | /* 15602 */ "VST3LNq16\000" |
| 12272 | /* 15612 */ "VLD4LNq16\000" |
| 12273 | /* 15622 */ "VST4LNq16\000" |
| 12274 | /* 15632 */ "VTRNq16\000" |
| 12275 | /* 15640 */ "VZIPq16\000" |
| 12276 | /* 15648 */ "VLD1DUPq16\000" |
| 12277 | /* 15659 */ "VLD3DUPq16\000" |
| 12278 | /* 15670 */ "VLD4DUPq16\000" |
| 12279 | /* 15681 */ "VUZPq16\000" |
| 12280 | /* 15689 */ "VEXTq16\000" |
| 12281 | /* 15697 */ "MVE_VPTv8s16\000" |
| 12282 | /* 15710 */ "MVE_VMINAs16\000" |
| 12283 | /* 15723 */ "MVE_VMAXAs16\000" |
| 12284 | /* 15736 */ "MVE_VMULLBs16\000" |
| 12285 | /* 15750 */ "MVE_VHSUBs16\000" |
| 12286 | /* 15763 */ "MVE_VQSUBs16\000" |
| 12287 | /* 15776 */ "MVE_VABDs16\000" |
| 12288 | /* 15788 */ "MVE_VHCADDs16\000" |
| 12289 | /* 15802 */ "MVE_VRHADDs16\000" |
| 12290 | /* 15816 */ "MVE_VHADDs16\000" |
| 12291 | /* 15829 */ "MVE_VQADDs16\000" |
| 12292 | /* 15842 */ "MVE_VQNEGs16\000" |
| 12293 | /* 15855 */ "MVE_VNEGs16\000" |
| 12294 | /* 15867 */ "MVE_VQDMLADHs16\000" |
| 12295 | /* 15883 */ "MVE_VQRDMLADHs16\000" |
| 12296 | /* 15900 */ "MVE_VQDMLSDHs16\000" |
| 12297 | /* 15916 */ "MVE_VQRDMLSDHs16\000" |
| 12298 | /* 15933 */ "MVE_VRMULHs16\000" |
| 12299 | /* 15947 */ "MVE_VMULHs16\000" |
| 12300 | /* 15960 */ "VPMINs16\000" |
| 12301 | /* 15969 */ "MVE_VMINs16\000" |
| 12302 | /* 15981 */ "VGETLNs16\000" |
| 12303 | /* 15991 */ "MVE_VCMPs16\000" |
| 12304 | /* 16003 */ "MVE_VQABSs16\000" |
| 12305 | /* 16016 */ "MVE_VABSs16\000" |
| 12306 | /* 16028 */ "MVE_VCLSs16\000" |
| 12307 | /* 16040 */ "MVE_VMULLTs16\000" |
| 12308 | /* 16054 */ "MVE_VABAVs16\000" |
| 12309 | /* 16067 */ "MVE_VMLADAVs16\000" |
| 12310 | /* 16082 */ "MVE_VMLALDAVs16\000" |
| 12311 | /* 16098 */ "MVE_VMLSLDAVs16\000" |
| 12312 | /* 16114 */ "MVE_VMLSDAVs16\000" |
| 12313 | /* 16129 */ "MVE_VMINAVs16\000" |
| 12314 | /* 16143 */ "MVE_VMAXAVs16\000" |
| 12315 | /* 16157 */ "MVE_VMINVs16\000" |
| 12316 | /* 16170 */ "MVE_VMAXVs16\000" |
| 12317 | /* 16183 */ "VPMAXs16\000" |
| 12318 | /* 16192 */ "MVE_VMAXs16\000" |
| 12319 | /* 16204 */ "MVE_VQDMLADHXs16\000" |
| 12320 | /* 16221 */ "MVE_VQRDMLADHXs16\000" |
| 12321 | /* 16239 */ "MVE_VQDMLSDHXs16\000" |
| 12322 | /* 16256 */ "MVE_VQRDMLSDHXs16\000" |
| 12323 | /* 16274 */ "MVE_VCLZs16\000" |
| 12324 | /* 16286 */ "MVE_VMOV_from_lane_s16\000" |
| 12325 | /* 16309 */ "MVE_VHSUB_qr_s16\000" |
| 12326 | /* 16326 */ "MVE_VQSUB_qr_s16\000" |
| 12327 | /* 16343 */ "MVE_VHADD_qr_s16\000" |
| 12328 | /* 16360 */ "MVE_VQADD_qr_s16\000" |
| 12329 | /* 16377 */ "MVE_VQDMULH_qr_s16\000" |
| 12330 | /* 16396 */ "MVE_VQRDMULH_qr_s16\000" |
| 12331 | /* 16416 */ "MVE_VMLADAVas16\000" |
| 12332 | /* 16432 */ "MVE_VMLALDAVas16\000" |
| 12333 | /* 16449 */ "MVE_VMLSLDAVas16\000" |
| 12334 | /* 16466 */ "MVE_VMLSDAVas16\000" |
| 12335 | /* 16482 */ "MVE_VQSHL_by_vecs16\000" |
| 12336 | /* 16502 */ "MVE_VQRSHL_by_vecs16\000" |
| 12337 | /* 16523 */ "MVE_VRSHL_by_vecs16\000" |
| 12338 | /* 16543 */ "MVE_VSHL_by_vecs16\000" |
| 12339 | /* 16562 */ "MVE_VQSHRNbhs16\000" |
| 12340 | /* 16578 */ "MVE_VQRSHRNbhs16\000" |
| 12341 | /* 16595 */ "MVE_VQSHRNths16\000" |
| 12342 | /* 16611 */ "MVE_VQRSHRNths16\000" |
| 12343 | /* 16628 */ "MVE_VQSHLimms16\000" |
| 12344 | /* 16644 */ "MVE_VRSHR_imms16\000" |
| 12345 | /* 16661 */ "MVE_VSHR_imms16\000" |
| 12346 | /* 16677 */ "MVE_VQSHLU_imms16\000" |
| 12347 | /* 16695 */ "MVE_VQDMLAH_qrs16\000" |
| 12348 | /* 16713 */ "MVE_VQRDMLAH_qrs16\000" |
| 12349 | /* 16732 */ "MVE_VQDMLASH_qrs16\000" |
| 12350 | /* 16751 */ "MVE_VQRDMLASH_qrs16\000" |
| 12351 | /* 16771 */ "MVE_VQSHL_qrs16\000" |
| 12352 | /* 16787 */ "MVE_VQRSHL_qrs16\000" |
| 12353 | /* 16804 */ "MVE_VRSHL_qrs16\000" |
| 12354 | /* 16820 */ "MVE_VSHL_qrs16\000" |
| 12355 | /* 16835 */ "MVE_VMLADAVxs16\000" |
| 12356 | /* 16851 */ "MVE_VMLALDAVxs16\000" |
| 12357 | /* 16868 */ "MVE_VMLSLDAVxs16\000" |
| 12358 | /* 16885 */ "MVE_VMLSDAVxs16\000" |
| 12359 | /* 16901 */ "MVE_VMLADAVaxs16\000" |
| 12360 | /* 16918 */ "MVE_VMLALDAVaxs16\000" |
| 12361 | /* 16936 */ "MVE_VMLSLDAVaxs16\000" |
| 12362 | /* 16954 */ "MVE_VMLSDAVaxs16\000" |
| 12363 | /* 16971 */ "MVE_VPTv8u16\000" |
| 12364 | /* 16984 */ "MVE_VMULLBu16\000" |
| 12365 | /* 16998 */ "MVE_VHSUBu16\000" |
| 12366 | /* 17011 */ "MVE_VQSUBu16\000" |
| 12367 | /* 17024 */ "MVE_VABDu16\000" |
| 12368 | /* 17036 */ "MVE_VRHADDu16\000" |
| 12369 | /* 17050 */ "MVE_VHADDu16\000" |
| 12370 | /* 17063 */ "MVE_VQADDu16\000" |
| 12371 | /* 17076 */ "MVE_VRMULHu16\000" |
| 12372 | /* 17090 */ "MVE_VMULHu16\000" |
| 12373 | /* 17103 */ "VPMINu16\000" |
| 12374 | /* 17112 */ "MVE_VMINu16\000" |
| 12375 | /* 17124 */ "VGETLNu16\000" |
| 12376 | /* 17134 */ "MVE_VCMPu16\000" |
| 12377 | /* 17146 */ "MVE_VDDUPu16\000" |
| 12378 | /* 17159 */ "MVE_VIDUPu16\000" |
| 12379 | /* 17172 */ "MVE_VDWDUPu16\000" |
| 12380 | /* 17186 */ "MVE_VIWDUPu16\000" |
| 12381 | /* 17200 */ "MVE_VMULLTu16\000" |
| 12382 | /* 17214 */ "MVE_VABAVu16\000" |
| 12383 | /* 17227 */ "MVE_VMLADAVu16\000" |
| 12384 | /* 17242 */ "MVE_VMLALDAVu16\000" |
| 12385 | /* 17258 */ "MVE_VMINVu16\000" |
| 12386 | /* 17271 */ "MVE_VMAXVu16\000" |
| 12387 | /* 17284 */ "VPMAXu16\000" |
| 12388 | /* 17293 */ "MVE_VMAXu16\000" |
| 12389 | /* 17305 */ "MVE_VMOV_from_lane_u16\000" |
| 12390 | /* 17328 */ "MVE_VHSUB_qr_u16\000" |
| 12391 | /* 17345 */ "MVE_VQSUB_qr_u16\000" |
| 12392 | /* 17362 */ "MVE_VHADD_qr_u16\000" |
| 12393 | /* 17379 */ "MVE_VQADD_qr_u16\000" |
| 12394 | /* 17396 */ "MVE_VMLADAVau16\000" |
| 12395 | /* 17412 */ "MVE_VMLALDAVau16\000" |
| 12396 | /* 17429 */ "MVE_VQSHL_by_vecu16\000" |
| 12397 | /* 17449 */ "MVE_VQRSHL_by_vecu16\000" |
| 12398 | /* 17470 */ "MVE_VRSHL_by_vecu16\000" |
| 12399 | /* 17490 */ "MVE_VSHL_by_vecu16\000" |
| 12400 | /* 17509 */ "MVE_VQSHRNbhu16\000" |
| 12401 | /* 17525 */ "MVE_VQRSHRNbhu16\000" |
| 12402 | /* 17542 */ "MVE_VQSHRNthu16\000" |
| 12403 | /* 17558 */ "MVE_VQRSHRNthu16\000" |
| 12404 | /* 17575 */ "MVE_VQSHLimmu16\000" |
| 12405 | /* 17591 */ "MVE_VRSHR_immu16\000" |
| 12406 | /* 17608 */ "MVE_VSHR_immu16\000" |
| 12407 | /* 17624 */ "MVE_VQSHL_qru16\000" |
| 12408 | /* 17640 */ "MVE_VQRSHL_qru16\000" |
| 12409 | /* 17657 */ "MVE_VRSHL_qru16\000" |
| 12410 | /* 17673 */ "MVE_VSHL_qru16\000" |
| 12411 | /* 17688 */ "t2USADA8\000" |
| 12412 | /* 17697 */ "t2SHSUB8\000" |
| 12413 | /* 17706 */ "t2UHSUB8\000" |
| 12414 | /* 17715 */ "t2QSUB8\000" |
| 12415 | /* 17723 */ "t2UQSUB8\000" |
| 12416 | /* 17732 */ "t2SSUB8\000" |
| 12417 | /* 17740 */ "t2USUB8\000" |
| 12418 | /* 17748 */ "t2USAD8\000" |
| 12419 | /* 17756 */ "t2SHADD8\000" |
| 12420 | /* 17765 */ "t2UHADD8\000" |
| 12421 | /* 17774 */ "t2QADD8\000" |
| 12422 | /* 17782 */ "t2UQADD8\000" |
| 12423 | /* 17791 */ "t2SADD8\000" |
| 12424 | /* 17799 */ "t2UADD8\000" |
| 12425 | /* 17807 */ "MVE_VCTP8\000" |
| 12426 | /* 17817 */ "MVE_VDUP8\000" |
| 12427 | /* 17827 */ "MVE_VBRSR8\000" |
| 12428 | /* 17838 */ "MVE_VLDRBU8\000" |
| 12429 | /* 17850 */ "MVE_VSTRBU8\000" |
| 12430 | /* 17862 */ "MVE_VLD20_8\000" |
| 12431 | /* 17874 */ "MVE_VST20_8\000" |
| 12432 | /* 17886 */ "MVE_VLD40_8\000" |
| 12433 | /* 17898 */ "MVE_VST40_8\000" |
| 12434 | /* 17910 */ "MVE_VLD21_8\000" |
| 12435 | /* 17922 */ "MVE_VST21_8\000" |
| 12436 | /* 17934 */ "MVE_VLD41_8\000" |
| 12437 | /* 17946 */ "MVE_VST41_8\000" |
| 12438 | /* 17958 */ "MVE_VREV32_8\000" |
| 12439 | /* 17971 */ "MVE_VLD42_8\000" |
| 12440 | /* 17983 */ "MVE_VST42_8\000" |
| 12441 | /* 17995 */ "MVE_VLD43_8\000" |
| 12442 | /* 18007 */ "MVE_VST43_8\000" |
| 12443 | /* 18019 */ "MVE_VREV64_8\000" |
| 12444 | /* 18032 */ "MVE_VREV16_8\000" |
| 12445 | /* 18045 */ "tCMP_SWAP_8\000" |
| 12446 | /* 18057 */ "MVE_DLSTP_8\000" |
| 12447 | /* 18069 */ "MVE_WLSTP_8\000" |
| 12448 | /* 18081 */ "MVE_VMOV_to_lane_8\000" |
| 12449 | /* 18100 */ "VLD3dWB_fixed_Asm_8\000" |
| 12450 | /* 18120 */ "VST3dWB_fixed_Asm_8\000" |
| 12451 | /* 18140 */ "VLD4dWB_fixed_Asm_8\000" |
| 12452 | /* 18160 */ "VST4dWB_fixed_Asm_8\000" |
| 12453 | /* 18180 */ "VLD1LNdWB_fixed_Asm_8\000" |
| 12454 | /* 18202 */ "VST1LNdWB_fixed_Asm_8\000" |
| 12455 | /* 18224 */ "VLD2LNdWB_fixed_Asm_8\000" |
| 12456 | /* 18246 */ "VST2LNdWB_fixed_Asm_8\000" |
| 12457 | /* 18268 */ "VLD3LNdWB_fixed_Asm_8\000" |
| 12458 | /* 18290 */ "VST3LNdWB_fixed_Asm_8\000" |
| 12459 | /* 18312 */ "VLD4LNdWB_fixed_Asm_8\000" |
| 12460 | /* 18334 */ "VST4LNdWB_fixed_Asm_8\000" |
| 12461 | /* 18356 */ "VLD3DUPdWB_fixed_Asm_8\000" |
| 12462 | /* 18379 */ "VLD4DUPdWB_fixed_Asm_8\000" |
| 12463 | /* 18402 */ "VLD3qWB_fixed_Asm_8\000" |
| 12464 | /* 18422 */ "VST3qWB_fixed_Asm_8\000" |
| 12465 | /* 18442 */ "VLD4qWB_fixed_Asm_8\000" |
| 12466 | /* 18462 */ "VST4qWB_fixed_Asm_8\000" |
| 12467 | /* 18482 */ "VLD3DUPqWB_fixed_Asm_8\000" |
| 12468 | /* 18505 */ "VLD4DUPqWB_fixed_Asm_8\000" |
| 12469 | /* 18528 */ "VLD3dWB_register_Asm_8\000" |
| 12470 | /* 18551 */ "VST3dWB_register_Asm_8\000" |
| 12471 | /* 18574 */ "VLD4dWB_register_Asm_8\000" |
| 12472 | /* 18597 */ "VST4dWB_register_Asm_8\000" |
| 12473 | /* 18620 */ "VLD1LNdWB_register_Asm_8\000" |
| 12474 | /* 18645 */ "VST1LNdWB_register_Asm_8\000" |
| 12475 | /* 18670 */ "VLD2LNdWB_register_Asm_8\000" |
| 12476 | /* 18695 */ "VST2LNdWB_register_Asm_8\000" |
| 12477 | /* 18720 */ "VLD3LNdWB_register_Asm_8\000" |
| 12478 | /* 18745 */ "VST3LNdWB_register_Asm_8\000" |
| 12479 | /* 18770 */ "VLD4LNdWB_register_Asm_8\000" |
| 12480 | /* 18795 */ "VST4LNdWB_register_Asm_8\000" |
| 12481 | /* 18820 */ "VLD3DUPdWB_register_Asm_8\000" |
| 12482 | /* 18846 */ "VLD4DUPdWB_register_Asm_8\000" |
| 12483 | /* 18872 */ "VLD3qWB_register_Asm_8\000" |
| 12484 | /* 18895 */ "VST3qWB_register_Asm_8\000" |
| 12485 | /* 18918 */ "VLD4qWB_register_Asm_8\000" |
| 12486 | /* 18941 */ "VST4qWB_register_Asm_8\000" |
| 12487 | /* 18964 */ "VLD3DUPqWB_register_Asm_8\000" |
| 12488 | /* 18990 */ "VLD4DUPqWB_register_Asm_8\000" |
| 12489 | /* 19016 */ "VLD3dAsm_8\000" |
| 12490 | /* 19027 */ "VST3dAsm_8\000" |
| 12491 | /* 19038 */ "VLD4dAsm_8\000" |
| 12492 | /* 19049 */ "VST4dAsm_8\000" |
| 12493 | /* 19060 */ "VLD1LNdAsm_8\000" |
| 12494 | /* 19073 */ "VST1LNdAsm_8\000" |
| 12495 | /* 19086 */ "VLD2LNdAsm_8\000" |
| 12496 | /* 19099 */ "VST2LNdAsm_8\000" |
| 12497 | /* 19112 */ "VLD3LNdAsm_8\000" |
| 12498 | /* 19125 */ "VST3LNdAsm_8\000" |
| 12499 | /* 19138 */ "VLD4LNdAsm_8\000" |
| 12500 | /* 19151 */ "VST4LNdAsm_8\000" |
| 12501 | /* 19164 */ "VLD3DUPdAsm_8\000" |
| 12502 | /* 19178 */ "VLD4DUPdAsm_8\000" |
| 12503 | /* 19192 */ "VLD3qAsm_8\000" |
| 12504 | /* 19203 */ "VST3qAsm_8\000" |
| 12505 | /* 19214 */ "VLD4qAsm_8\000" |
| 12506 | /* 19225 */ "VST4qAsm_8\000" |
| 12507 | /* 19236 */ "VLD3DUPqAsm_8\000" |
| 12508 | /* 19250 */ "VLD4DUPqAsm_8\000" |
| 12509 | /* 19264 */ "VLD2b8\000" |
| 12510 | /* 19271 */ "VST2b8\000" |
| 12511 | /* 19278 */ "VLD1d8\000" |
| 12512 | /* 19285 */ "VST1d8\000" |
| 12513 | /* 19292 */ "VREV32d8\000" |
| 12514 | /* 19301 */ "VLD2d8\000" |
| 12515 | /* 19308 */ "VST2d8\000" |
| 12516 | /* 19315 */ "VLD3d8\000" |
| 12517 | /* 19322 */ "VST3d8\000" |
| 12518 | /* 19329 */ "VREV64d8\000" |
| 12519 | /* 19338 */ "VLD4d8\000" |
| 12520 | /* 19345 */ "VST4d8\000" |
| 12521 | /* 19352 */ "VREV16d8\000" |
| 12522 | /* 19361 */ "VLD1LNd8\000" |
| 12523 | /* 19370 */ "VST1LNd8\000" |
| 12524 | /* 19379 */ "VLD2LNd8\000" |
| 12525 | /* 19388 */ "VST2LNd8\000" |
| 12526 | /* 19397 */ "VLD3LNd8\000" |
| 12527 | /* 19406 */ "VST3LNd8\000" |
| 12528 | /* 19415 */ "VLD4LNd8\000" |
| 12529 | /* 19424 */ "VST4LNd8\000" |
| 12530 | /* 19433 */ "VTRNd8\000" |
| 12531 | /* 19440 */ "VZIPd8\000" |
| 12532 | /* 19447 */ "VLD1DUPd8\000" |
| 12533 | /* 19457 */ "VLD2DUPd8\000" |
| 12534 | /* 19467 */ "VLD3DUPd8\000" |
| 12535 | /* 19477 */ "VLD4DUPd8\000" |
| 12536 | /* 19487 */ "VUZPd8\000" |
| 12537 | /* 19494 */ "VEXTd8\000" |
| 12538 | /* 19501 */ "VMLAv16i8\000" |
| 12539 | /* 19511 */ "VSUBv16i8\000" |
| 12540 | /* 19521 */ "VADDv16i8\000" |
| 12541 | /* 19531 */ "VQNEGv16i8\000" |
| 12542 | /* 19542 */ "VSLIv16i8\000" |
| 12543 | /* 19552 */ "VSRIv16i8\000" |
| 12544 | /* 19562 */ "VMULv16i8\000" |
| 12545 | /* 19572 */ "VCEQv16i8\000" |
| 12546 | /* 19582 */ "VQABSv16i8\000" |
| 12547 | /* 19593 */ "VABSv16i8\000" |
| 12548 | /* 19603 */ "VCLSv16i8\000" |
| 12549 | /* 19613 */ "VMLSv16i8\000" |
| 12550 | /* 19623 */ "MVE_VPTv16i8\000" |
| 12551 | /* 19636 */ "VTSTv16i8\000" |
| 12552 | /* 19646 */ "VMOVv16i8\000" |
| 12553 | /* 19656 */ "VCLZv16i8\000" |
| 12554 | /* 19666 */ "VSHLiv16i8\000" |
| 12555 | /* 19677 */ "VQSHLsiv16i8\000" |
| 12556 | /* 19690 */ "VQSHLuiv16i8\000" |
| 12557 | /* 19703 */ "VABAsv16i8\000" |
| 12558 | /* 19714 */ "VRSRAsv16i8\000" |
| 12559 | /* 19726 */ "VSRAsv16i8\000" |
| 12560 | /* 19737 */ "VHSUBsv16i8\000" |
| 12561 | /* 19749 */ "VQSUBsv16i8\000" |
| 12562 | /* 19761 */ "VABDsv16i8\000" |
| 12563 | /* 19772 */ "VRHADDsv16i8\000" |
| 12564 | /* 19785 */ "VHADDsv16i8\000" |
| 12565 | /* 19797 */ "VQADDsv16i8\000" |
| 12566 | /* 19809 */ "VCGEsv16i8\000" |
| 12567 | /* 19820 */ "VPADALsv16i8\000" |
| 12568 | /* 19833 */ "VPADDLsv16i8\000" |
| 12569 | /* 19846 */ "VQSHLsv16i8\000" |
| 12570 | /* 19858 */ "VQRSHLsv16i8\000" |
| 12571 | /* 19871 */ "VRSHLsv16i8\000" |
| 12572 | /* 19883 */ "VSHLsv16i8\000" |
| 12573 | /* 19894 */ "VMINsv16i8\000" |
| 12574 | /* 19905 */ "VRSHRsv16i8\000" |
| 12575 | /* 19917 */ "VSHRsv16i8\000" |
| 12576 | /* 19928 */ "VCGTsv16i8\000" |
| 12577 | /* 19939 */ "VMAXsv16i8\000" |
| 12578 | /* 19950 */ "VABAuv16i8\000" |
| 12579 | /* 19961 */ "VRSRAuv16i8\000" |
| 12580 | /* 19973 */ "VSRAuv16i8\000" |
| 12581 | /* 19984 */ "VHSUBuv16i8\000" |
| 12582 | /* 19996 */ "VQSUBuv16i8\000" |
| 12583 | /* 20008 */ "VABDuv16i8\000" |
| 12584 | /* 20019 */ "VRHADDuv16i8\000" |
| 12585 | /* 20032 */ "VHADDuv16i8\000" |
| 12586 | /* 20044 */ "VQADDuv16i8\000" |
| 12587 | /* 20056 */ "VCGEuv16i8\000" |
| 12588 | /* 20067 */ "VPADALuv16i8\000" |
| 12589 | /* 20080 */ "VPADDLuv16i8\000" |
| 12590 | /* 20093 */ "VQSHLuv16i8\000" |
| 12591 | /* 20105 */ "VQRSHLuv16i8\000" |
| 12592 | /* 20118 */ "VRSHLuv16i8\000" |
| 12593 | /* 20130 */ "VSHLuv16i8\000" |
| 12594 | /* 20141 */ "VMINuv16i8\000" |
| 12595 | /* 20152 */ "VRSHRuv16i8\000" |
| 12596 | /* 20164 */ "VSHRuv16i8\000" |
| 12597 | /* 20175 */ "VCGTuv16i8\000" |
| 12598 | /* 20186 */ "VMAXuv16i8\000" |
| 12599 | /* 20197 */ "VQSHLsuv16i8\000" |
| 12600 | /* 20210 */ "VCGEzv16i8\000" |
| 12601 | /* 20221 */ "VCLEzv16i8\000" |
| 12602 | /* 20232 */ "VCEQzv16i8\000" |
| 12603 | /* 20243 */ "VCGTzv16i8\000" |
| 12604 | /* 20254 */ "VCLTzv16i8\000" |
| 12605 | /* 20265 */ "VMLAv8i8\000" |
| 12606 | /* 20274 */ "VSUBv8i8\000" |
| 12607 | /* 20283 */ "VADDv8i8\000" |
| 12608 | /* 20292 */ "VQNEGv8i8\000" |
| 12609 | /* 20302 */ "VSLIv8i8\000" |
| 12610 | /* 20311 */ "VSRIv8i8\000" |
| 12611 | /* 20320 */ "VMULv8i8\000" |
| 12612 | /* 20329 */ "VRSUBHNv8i8\000" |
| 12613 | /* 20341 */ "VSUBHNv8i8\000" |
| 12614 | /* 20352 */ "VRADDHNv8i8\000" |
| 12615 | /* 20364 */ "VADDHNv8i8\000" |
| 12616 | /* 20375 */ "VRSHRNv8i8\000" |
| 12617 | /* 20386 */ "VSHRNv8i8\000" |
| 12618 | /* 20396 */ "VQSHRUNv8i8\000" |
| 12619 | /* 20408 */ "VQRSHRUNv8i8\000" |
| 12620 | /* 20421 */ "VMOVNv8i8\000" |
| 12621 | /* 20431 */ "VCEQv8i8\000" |
| 12622 | /* 20440 */ "VQABSv8i8\000" |
| 12623 | /* 20450 */ "VABSv8i8\000" |
| 12624 | /* 20459 */ "VCLSv8i8\000" |
| 12625 | /* 20468 */ "VMLSv8i8\000" |
| 12626 | /* 20477 */ "VTSTv8i8\000" |
| 12627 | /* 20486 */ "VMOVv8i8\000" |
| 12628 | /* 20495 */ "VCLZv8i8\000" |
| 12629 | /* 20504 */ "VSHLiv8i8\000" |
| 12630 | /* 20514 */ "VQSHLsiv8i8\000" |
| 12631 | /* 20526 */ "VQSHLuiv8i8\000" |
| 12632 | /* 20538 */ "VABAsv8i8\000" |
| 12633 | /* 20548 */ "VRSRAsv8i8\000" |
| 12634 | /* 20559 */ "VSRAsv8i8\000" |
| 12635 | /* 20569 */ "VHSUBsv8i8\000" |
| 12636 | /* 20580 */ "VQSUBsv8i8\000" |
| 12637 | /* 20591 */ "VABDsv8i8\000" |
| 12638 | /* 20601 */ "VRHADDsv8i8\000" |
| 12639 | /* 20613 */ "VHADDsv8i8\000" |
| 12640 | /* 20624 */ "VQADDsv8i8\000" |
| 12641 | /* 20635 */ "VCGEsv8i8\000" |
| 12642 | /* 20645 */ "VPADALsv8i8\000" |
| 12643 | /* 20657 */ "VPADDLsv8i8\000" |
| 12644 | /* 20669 */ "VQSHLsv8i8\000" |
| 12645 | /* 20680 */ "VQRSHLsv8i8\000" |
| 12646 | /* 20692 */ "VRSHLsv8i8\000" |
| 12647 | /* 20703 */ "VSHLsv8i8\000" |
| 12648 | /* 20713 */ "VMINsv8i8\000" |
| 12649 | /* 20723 */ "VQSHRNsv8i8\000" |
| 12650 | /* 20735 */ "VQRSHRNsv8i8\000" |
| 12651 | /* 20748 */ "VQMOVNsv8i8\000" |
| 12652 | /* 20760 */ "VRSHRsv8i8\000" |
| 12653 | /* 20771 */ "VSHRsv8i8\000" |
| 12654 | /* 20781 */ "VCGTsv8i8\000" |
| 12655 | /* 20791 */ "VMAXsv8i8\000" |
| 12656 | /* 20801 */ "VABAuv8i8\000" |
| 12657 | /* 20811 */ "VRSRAuv8i8\000" |
| 12658 | /* 20822 */ "VSRAuv8i8\000" |
| 12659 | /* 20832 */ "VHSUBuv8i8\000" |
| 12660 | /* 20843 */ "VQSUBuv8i8\000" |
| 12661 | /* 20854 */ "VABDuv8i8\000" |
| 12662 | /* 20864 */ "VRHADDuv8i8\000" |
| 12663 | /* 20876 */ "VHADDuv8i8\000" |
| 12664 | /* 20887 */ "VQADDuv8i8\000" |
| 12665 | /* 20898 */ "VCGEuv8i8\000" |
| 12666 | /* 20908 */ "VPADALuv8i8\000" |
| 12667 | /* 20920 */ "VPADDLuv8i8\000" |
| 12668 | /* 20932 */ "VQSHLuv8i8\000" |
| 12669 | /* 20943 */ "VQRSHLuv8i8\000" |
| 12670 | /* 20955 */ "VRSHLuv8i8\000" |
| 12671 | /* 20966 */ "VSHLuv8i8\000" |
| 12672 | /* 20976 */ "VMINuv8i8\000" |
| 12673 | /* 20986 */ "VQSHRNuv8i8\000" |
| 12674 | /* 20998 */ "VQRSHRNuv8i8\000" |
| 12675 | /* 21011 */ "VQMOVNuv8i8\000" |
| 12676 | /* 21023 */ "VRSHRuv8i8\000" |
| 12677 | /* 21034 */ "VSHRuv8i8\000" |
| 12678 | /* 21044 */ "VCGTuv8i8\000" |
| 12679 | /* 21054 */ "VMAXuv8i8\000" |
| 12680 | /* 21064 */ "VQSHLsuv8i8\000" |
| 12681 | /* 21076 */ "VQMOVNsuv8i8\000" |
| 12682 | /* 21089 */ "VCGEzv8i8\000" |
| 12683 | /* 21099 */ "VCLEzv8i8\000" |
| 12684 | /* 21109 */ "VCEQzv8i8\000" |
| 12685 | /* 21119 */ "VCGTzv8i8\000" |
| 12686 | /* 21129 */ "VCLTzv8i8\000" |
| 12687 | /* 21139 */ "t2LDRBi8\000" |
| 12688 | /* 21148 */ "t2STRBi8\000" |
| 12689 | /* 21157 */ "t2LDRSBi8\000" |
| 12690 | /* 21167 */ "MVE_VSUBi8\000" |
| 12691 | /* 21178 */ "tSUBi8\000" |
| 12692 | /* 21185 */ "MVE_VCADDi8\000" |
| 12693 | /* 21197 */ "VPADDi8\000" |
| 12694 | /* 21205 */ "MVE_VADDi8\000" |
| 12695 | /* 21216 */ "tADDi8\000" |
| 12696 | /* 21223 */ "t2PLDi8\000" |
| 12697 | /* 21231 */ "t2LDRDi8\000" |
| 12698 | /* 21240 */ "t2STRDi8\000" |
| 12699 | /* 21249 */ "MVE_VQDMULHi8\000" |
| 12700 | /* 21263 */ "MVE_VQRDMULHi8\000" |
| 12701 | /* 21278 */ "t2LDRHi8\000" |
| 12702 | /* 21287 */ "t2STRHi8\000" |
| 12703 | /* 21296 */ "t2LDRSHi8\000" |
| 12704 | /* 21306 */ "t2PLIi8\000" |
| 12705 | /* 21314 */ "VSHLLi8\000" |
| 12706 | /* 21322 */ "MVE_VMULi8\000" |
| 12707 | /* 21333 */ "VSETLNi8\000" |
| 12708 | /* 21342 */ "MVE_VCMPi8\000" |
| 12709 | /* 21353 */ "tCMPi8\000" |
| 12710 | /* 21360 */ "t2LDRi8\000" |
| 12711 | /* 21368 */ "t2STRi8\000" |
| 12712 | /* 21376 */ "tSUBSi8\000" |
| 12713 | /* 21384 */ "tADDSi8\000" |
| 12714 | /* 21392 */ "tMOVi8\000" |
| 12715 | /* 21399 */ "t2PLDWi8\000" |
| 12716 | /* 21408 */ "MVE_VMLA_qr_i8\000" |
| 12717 | /* 21423 */ "MVE_VSUB_qr_i8\000" |
| 12718 | /* 21438 */ "MVE_VADD_qr_i8\000" |
| 12719 | /* 21453 */ "MVE_VMUL_qr_i8\000" |
| 12720 | /* 21468 */ "MVE_VMLAS_qr_i8\000" |
| 12721 | /* 21484 */ "MVE_VMOVimmi8\000" |
| 12722 | /* 21498 */ "MVE_VSHL_immi8\000" |
| 12723 | /* 21513 */ "MVE_VSLIimm8\000" |
| 12724 | /* 21526 */ "MVE_VSRIimm8\000" |
| 12725 | /* 21539 */ "MVE_VMULLBp8\000" |
| 12726 | /* 21552 */ "VMULLp8\000" |
| 12727 | /* 21560 */ "MVE_VMULLTp8\000" |
| 12728 | /* 21573 */ "VLD1q8\000" |
| 12729 | /* 21580 */ "VST1q8\000" |
| 12730 | /* 21587 */ "VREV32q8\000" |
| 12731 | /* 21596 */ "VLD2q8\000" |
| 12732 | /* 21603 */ "VST2q8\000" |
| 12733 | /* 21610 */ "VLD3q8\000" |
| 12734 | /* 21617 */ "VST3q8\000" |
| 12735 | /* 21624 */ "VREV64q8\000" |
| 12736 | /* 21633 */ "VLD4q8\000" |
| 12737 | /* 21640 */ "VST4q8\000" |
| 12738 | /* 21647 */ "VREV16q8\000" |
| 12739 | /* 21656 */ "VTRNq8\000" |
| 12740 | /* 21663 */ "VZIPq8\000" |
| 12741 | /* 21670 */ "VLD1DUPq8\000" |
| 12742 | /* 21680 */ "VLD3DUPq8\000" |
| 12743 | /* 21690 */ "VLD4DUPq8\000" |
| 12744 | /* 21700 */ "VUZPq8\000" |
| 12745 | /* 21707 */ "VEXTq8\000" |
| 12746 | /* 21714 */ "MVE_VPTv16s8\000" |
| 12747 | /* 21727 */ "MVE_VMINAs8\000" |
| 12748 | /* 21739 */ "MVE_VMAXAs8\000" |
| 12749 | /* 21751 */ "MVE_VMULLBs8\000" |
| 12750 | /* 21764 */ "MVE_VHSUBs8\000" |
| 12751 | /* 21776 */ "MVE_VQSUBs8\000" |
| 12752 | /* 21788 */ "MVE_VABDs8\000" |
| 12753 | /* 21799 */ "MVE_VHCADDs8\000" |
| 12754 | /* 21812 */ "MVE_VRHADDs8\000" |
| 12755 | /* 21825 */ "MVE_VHADDs8\000" |
| 12756 | /* 21837 */ "MVE_VQADDs8\000" |
| 12757 | /* 21849 */ "MVE_VQNEGs8\000" |
| 12758 | /* 21861 */ "MVE_VNEGs8\000" |
| 12759 | /* 21872 */ "MVE_VQDMLADHs8\000" |
| 12760 | /* 21887 */ "MVE_VQRDMLADHs8\000" |
| 12761 | /* 21903 */ "MVE_VQDMLSDHs8\000" |
| 12762 | /* 21918 */ "MVE_VQRDMLSDHs8\000" |
| 12763 | /* 21934 */ "MVE_VRMULHs8\000" |
| 12764 | /* 21947 */ "MVE_VMULHs8\000" |
| 12765 | /* 21959 */ "VPMINs8\000" |
| 12766 | /* 21967 */ "MVE_VMINs8\000" |
| 12767 | /* 21978 */ "VGETLNs8\000" |
| 12768 | /* 21987 */ "MVE_VCMPs8\000" |
| 12769 | /* 21998 */ "MVE_VQABSs8\000" |
| 12770 | /* 22010 */ "MVE_VABSs8\000" |
| 12771 | /* 22021 */ "MVE_VCLSs8\000" |
| 12772 | /* 22032 */ "MVE_VMULLTs8\000" |
| 12773 | /* 22045 */ "MVE_VABAVs8\000" |
| 12774 | /* 22057 */ "MVE_VMLADAVs8\000" |
| 12775 | /* 22071 */ "MVE_VMLSDAVs8\000" |
| 12776 | /* 22085 */ "MVE_VMINAVs8\000" |
| 12777 | /* 22098 */ "MVE_VMAXAVs8\000" |
| 12778 | /* 22111 */ "MVE_VMINVs8\000" |
| 12779 | /* 22123 */ "MVE_VMAXVs8\000" |
| 12780 | /* 22135 */ "VPMAXs8\000" |
| 12781 | /* 22143 */ "MVE_VMAXs8\000" |
| 12782 | /* 22154 */ "MVE_VQDMLADHXs8\000" |
| 12783 | /* 22170 */ "MVE_VQRDMLADHXs8\000" |
| 12784 | /* 22187 */ "MVE_VQDMLSDHXs8\000" |
| 12785 | /* 22203 */ "MVE_VQRDMLSDHXs8\000" |
| 12786 | /* 22220 */ "MVE_VCLZs8\000" |
| 12787 | /* 22231 */ "MVE_VMOV_from_lane_s8\000" |
| 12788 | /* 22253 */ "MVE_VHSUB_qr_s8\000" |
| 12789 | /* 22269 */ "MVE_VQSUB_qr_s8\000" |
| 12790 | /* 22285 */ "MVE_VHADD_qr_s8\000" |
| 12791 | /* 22301 */ "MVE_VQADD_qr_s8\000" |
| 12792 | /* 22317 */ "MVE_VQDMULH_qr_s8\000" |
| 12793 | /* 22335 */ "MVE_VQRDMULH_qr_s8\000" |
| 12794 | /* 22354 */ "MVE_VMLADAVas8\000" |
| 12795 | /* 22369 */ "MVE_VMLSDAVas8\000" |
| 12796 | /* 22384 */ "MVE_VQSHL_by_vecs8\000" |
| 12797 | /* 22403 */ "MVE_VQRSHL_by_vecs8\000" |
| 12798 | /* 22423 */ "MVE_VRSHL_by_vecs8\000" |
| 12799 | /* 22442 */ "MVE_VSHL_by_vecs8\000" |
| 12800 | /* 22460 */ "MVE_VQSHLimms8\000" |
| 12801 | /* 22475 */ "MVE_VRSHR_imms8\000" |
| 12802 | /* 22491 */ "MVE_VSHR_imms8\000" |
| 12803 | /* 22506 */ "MVE_VQSHLU_imms8\000" |
| 12804 | /* 22523 */ "MVE_VQDMLAH_qrs8\000" |
| 12805 | /* 22540 */ "MVE_VQRDMLAH_qrs8\000" |
| 12806 | /* 22558 */ "MVE_VQDMLASH_qrs8\000" |
| 12807 | /* 22576 */ "MVE_VQRDMLASH_qrs8\000" |
| 12808 | /* 22595 */ "MVE_VQSHL_qrs8\000" |
| 12809 | /* 22610 */ "MVE_VQRSHL_qrs8\000" |
| 12810 | /* 22626 */ "MVE_VRSHL_qrs8\000" |
| 12811 | /* 22641 */ "MVE_VSHL_qrs8\000" |
| 12812 | /* 22655 */ "MVE_VMLADAVxs8\000" |
| 12813 | /* 22670 */ "MVE_VMLSDAVxs8\000" |
| 12814 | /* 22685 */ "MVE_VMLADAVaxs8\000" |
| 12815 | /* 22701 */ "MVE_VMLSDAVaxs8\000" |
| 12816 | /* 22717 */ "MVE_VPTv16u8\000" |
| 12817 | /* 22730 */ "MVE_VMULLBu8\000" |
| 12818 | /* 22743 */ "MVE_VHSUBu8\000" |
| 12819 | /* 22755 */ "MVE_VQSUBu8\000" |
| 12820 | /* 22767 */ "MVE_VABDu8\000" |
| 12821 | /* 22778 */ "MVE_VRHADDu8\000" |
| 12822 | /* 22791 */ "MVE_VHADDu8\000" |
| 12823 | /* 22803 */ "MVE_VQADDu8\000" |
| 12824 | /* 22815 */ "MVE_VRMULHu8\000" |
| 12825 | /* 22828 */ "MVE_VMULHu8\000" |
| 12826 | /* 22840 */ "VPMINu8\000" |
| 12827 | /* 22848 */ "MVE_VMINu8\000" |
| 12828 | /* 22859 */ "VGETLNu8\000" |
| 12829 | /* 22868 */ "MVE_VCMPu8\000" |
| 12830 | /* 22879 */ "MVE_VDDUPu8\000" |
| 12831 | /* 22891 */ "MVE_VIDUPu8\000" |
| 12832 | /* 22903 */ "MVE_VDWDUPu8\000" |
| 12833 | /* 22916 */ "MVE_VIWDUPu8\000" |
| 12834 | /* 22929 */ "MVE_VMULLTu8\000" |
| 12835 | /* 22942 */ "MVE_VABAVu8\000" |
| 12836 | /* 22954 */ "MVE_VMLADAVu8\000" |
| 12837 | /* 22968 */ "MVE_VMINVu8\000" |
| 12838 | /* 22980 */ "MVE_VMAXVu8\000" |
| 12839 | /* 22992 */ "VPMAXu8\000" |
| 12840 | /* 23000 */ "MVE_VMAXu8\000" |
| 12841 | /* 23011 */ "MVE_VMOV_from_lane_u8\000" |
| 12842 | /* 23033 */ "MVE_VHSUB_qr_u8\000" |
| 12843 | /* 23049 */ "MVE_VQSUB_qr_u8\000" |
| 12844 | /* 23065 */ "MVE_VHADD_qr_u8\000" |
| 12845 | /* 23081 */ "MVE_VQADD_qr_u8\000" |
| 12846 | /* 23097 */ "MVE_VMLADAVau8\000" |
| 12847 | /* 23112 */ "MVE_VQSHL_by_vecu8\000" |
| 12848 | /* 23131 */ "MVE_VQRSHL_by_vecu8\000" |
| 12849 | /* 23151 */ "MVE_VRSHL_by_vecu8\000" |
| 12850 | /* 23170 */ "MVE_VSHL_by_vecu8\000" |
| 12851 | /* 23188 */ "MVE_VQSHLimmu8\000" |
| 12852 | /* 23203 */ "MVE_VRSHR_immu8\000" |
| 12853 | /* 23219 */ "MVE_VSHR_immu8\000" |
| 12854 | /* 23234 */ "MVE_VQSHL_qru8\000" |
| 12855 | /* 23249 */ "MVE_VQRSHL_qru8\000" |
| 12856 | /* 23265 */ "MVE_VRSHL_qru8\000" |
| 12857 | /* 23280 */ "MVE_VSHL_qru8\000" |
| 12858 | /* 23294 */ "CDE_CX1A\000" |
| 12859 | /* 23303 */ "MVE_VRINTf32A\000" |
| 12860 | /* 23317 */ "CDE_CX2A\000" |
| 12861 | /* 23326 */ "CDE_CX3A\000" |
| 12862 | /* 23335 */ "MVE_VRINTf16A\000" |
| 12863 | /* 23349 */ "CDE_CX1DA\000" |
| 12864 | /* 23359 */ "CDE_CX2DA\000" |
| 12865 | /* 23369 */ "CDE_CX3DA\000" |
| 12866 | /* 23379 */ "RFEDA\000" |
| 12867 | /* 23385 */ "t2LDA\000" |
| 12868 | /* 23391 */ "sysLDMDA\000" |
| 12869 | /* 23400 */ "sysSTMDA\000" |
| 12870 | /* 23409 */ "SRSDA\000" |
| 12871 | /* 23415 */ "VLDMDIA\000" |
| 12872 | /* 23423 */ "VSTMDIA\000" |
| 12873 | /* 23431 */ "t2RFEIA\000" |
| 12874 | /* 23439 */ "t2LDMIA\000" |
| 12875 | /* 23447 */ "sysLDMIA\000" |
| 12876 | /* 23456 */ "tLDMIA\000" |
| 12877 | /* 23463 */ "t2STMIA\000" |
| 12878 | /* 23471 */ "sysSTMIA\000" |
| 12879 | /* 23480 */ "VLDMQIA\000" |
| 12880 | /* 23488 */ "VSTMQIA\000" |
| 12881 | /* 23496 */ "VLDMSIA\000" |
| 12882 | /* 23504 */ "VSTMSIA\000" |
| 12883 | /* 23512 */ "t2SRSIA\000" |
| 12884 | /* 23520 */ "FLDMXIA\000" |
| 12885 | /* 23528 */ "FSTMXIA\000" |
| 12886 | /* 23536 */ "t2MLA\000" |
| 12887 | /* 23542 */ "t2SMMLA\000" |
| 12888 | /* 23550 */ "VUSMMLA\000" |
| 12889 | /* 23558 */ "VSMMLA\000" |
| 12890 | /* 23565 */ "VUMMLA\000" |
| 12891 | /* 23572 */ "VMMLA\000" |
| 12892 | /* 23578 */ "G_FMA\000" |
| 12893 | /* 23584 */ "G_STRICT_FMA\000" |
| 12894 | /* 23597 */ "t2TTA\000" |
| 12895 | /* 23603 */ "t2CRC32B\000" |
| 12896 | /* 23612 */ "t2B\000" |
| 12897 | /* 23616 */ "t2LDAB\000" |
| 12898 | /* 23623 */ "t2SXTAB\000" |
| 12899 | /* 23631 */ "t2UXTAB\000" |
| 12900 | /* 23639 */ "t2SMLABB\000" |
| 12901 | /* 23648 */ "t2SMLALBB\000" |
| 12902 | /* 23658 */ "t2SMULBB\000" |
| 12903 | /* 23667 */ "t2TBB\000" |
| 12904 | /* 23673 */ "JUMPTABLE_TBB\000" |
| 12905 | /* 23687 */ "t2SpeculationBarrierISBDSBEndBB\000" |
| 12906 | /* 23719 */ "t2SpeculationBarrierSBEndBB\000" |
| 12907 | /* 23747 */ "t2CRC32CB\000" |
| 12908 | /* 23757 */ "t2RFEDB\000" |
| 12909 | /* 23765 */ "t2LDMDB\000" |
| 12910 | /* 23773 */ "sysLDMDB\000" |
| 12911 | /* 23782 */ "t2STMDB\000" |
| 12912 | /* 23790 */ "sysSTMDB\000" |
| 12913 | /* 23799 */ "t2SRSDB\000" |
| 12914 | /* 23807 */ "RFEIB\000" |
| 12915 | /* 23813 */ "sysLDMIB\000" |
| 12916 | /* 23822 */ "sysSTMIB\000" |
| 12917 | /* 23831 */ "SRSIB\000" |
| 12918 | /* 23837 */ "t2STLB\000" |
| 12919 | /* 23844 */ "t2DMB\000" |
| 12920 | /* 23850 */ "SWPB\000" |
| 12921 | /* 23855 */ "PICLDRB\000" |
| 12922 | /* 23863 */ "PICSTRB\000" |
| 12923 | /* 23871 */ "t2SB\000" |
| 12924 | /* 23876 */ "t2DSB\000" |
| 12925 | /* 23882 */ "t2ISB\000" |
| 12926 | /* 23888 */ "PICLDRSB\000" |
| 12927 | /* 23897 */ "tLDRSB\000" |
| 12928 | /* 23904 */ "tRSB\000" |
| 12929 | /* 23909 */ "t2TSB\000" |
| 12930 | /* 23915 */ "t2SMLATB\000" |
| 12931 | /* 23924 */ "t2PKHTB\000" |
| 12932 | /* 23932 */ "t2SMLALTB\000" |
| 12933 | /* 23942 */ "t2SMULTB\000" |
| 12934 | /* 23951 */ "BF16_VCVTB\000" |
| 12935 | /* 23962 */ "t2SXTB\000" |
| 12936 | /* 23969 */ "tSXTB\000" |
| 12937 | /* 23975 */ "t2UXTB\000" |
| 12938 | /* 23982 */ "tUXTB\000" |
| 12939 | /* 23988 */ "t2QDSUB\000" |
| 12940 | /* 23996 */ "G_FSUB\000" |
| 12941 | /* 24003 */ "G_STRICT_FSUB\000" |
| 12942 | /* 24017 */ "G_ATOMICRMW_FSUB\000" |
| 12943 | /* 24034 */ "t2QSUB\000" |
| 12944 | /* 24041 */ "G_SUB\000" |
| 12945 | /* 24047 */ "G_ATOMICRMW_SUB\000" |
| 12946 | /* 24063 */ "t2SMLAWB\000" |
| 12947 | /* 24072 */ "t2SMULWB\000" |
| 12948 | /* 24081 */ "t2LDAEXB\000" |
| 12949 | /* 24090 */ "t2STLEXB\000" |
| 12950 | /* 24099 */ "t2LDREXB\000" |
| 12951 | /* 24108 */ "t2STREXB\000" |
| 12952 | /* 24117 */ "tB\000" |
| 12953 | /* 24120 */ "SHA1C\000" |
| 12954 | /* 24126 */ "t2PAC\000" |
| 12955 | /* 24132 */ "MVE_VSBC\000" |
| 12956 | /* 24141 */ "tSBC\000" |
| 12957 | /* 24146 */ "MVE_VADC\000" |
| 12958 | /* 24155 */ "tADC\000" |
| 12959 | /* 24160 */ "t2BFC\000" |
| 12960 | /* 24166 */ "MVE_VBIC\000" |
| 12961 | /* 24175 */ "tBIC\000" |
| 12962 | /* 24180 */ "G_INTRINSIC\000" |
| 12963 | /* 24192 */ "MVE_VSHLC\000" |
| 12964 | /* 24202 */ "AESIMC\000" |
| 12965 | /* 24209 */ "t2SMC\000" |
| 12966 | /* 24215 */ "AESMC\000" |
| 12967 | /* 24221 */ "t2CSINC\000" |
| 12968 | /* 24229 */ "G_FPTRUNC\000" |
| 12969 | /* 24239 */ "G_INTRINSIC_TRUNC\000" |
| 12970 | /* 24257 */ "G_TRUNC\000" |
| 12971 | /* 24265 */ "G_BUILD_VECTOR_TRUNC\000" |
| 12972 | /* 24286 */ "G_DYN_STACKALLOC\000" |
| 12973 | /* 24303 */ "VMSR_FPSCR_NZCVQC\000" |
| 12974 | /* 24321 */ "VMRS_FPSCR_NZCVQC\000" |
| 12975 | /* 24339 */ "t2MRC\000" |
| 12976 | /* 24345 */ "t2MRRC\000" |
| 12977 | /* 24352 */ "MOVr_TC\000" |
| 12978 | /* 24360 */ "t2HVC\000" |
| 12979 | /* 24366 */ "tSVC\000" |
| 12980 | /* 24371 */ "VMSR_FPEXC\000" |
| 12981 | /* 24382 */ "VMRS_FPEXC\000" |
| 12982 | /* 24393 */ "CDE_CX1D\000" |
| 12983 | /* 24402 */ "CDE_CX2D\000" |
| 12984 | /* 24411 */ "CDE_CX3D\000" |
| 12985 | /* 24420 */ "VNMLAD\000" |
| 12986 | /* 24427 */ "t2SMLAD\000" |
| 12987 | /* 24435 */ "VMLAD\000" |
| 12988 | /* 24441 */ "VFMAD\000" |
| 12989 | /* 24447 */ "G_FMAD\000" |
| 12990 | /* 24454 */ "VFNMAD\000" |
| 12991 | /* 24461 */ "G_FPEXTLOAD\000" |
| 12992 | /* 24473 */ "G_INDEXED_SEXTLOAD\000" |
| 12993 | /* 24492 */ "G_SEXTLOAD\000" |
| 12994 | /* 24503 */ "G_INDEXED_ZEXTLOAD\000" |
| 12995 | /* 24522 */ "G_ZEXTLOAD\000" |
| 12996 | /* 24533 */ "G_INDEXED_LOAD\000" |
| 12997 | /* 24548 */ "G_LOAD\000" |
| 12998 | /* 24555 */ "VRINTAD\000" |
| 12999 | /* 24563 */ "t2SMUAD\000" |
| 13000 | /* 24571 */ "VSUBD\000" |
| 13001 | /* 24577 */ "tPICADD\000" |
| 13002 | /* 24585 */ "t2QDADD\000" |
| 13003 | /* 24593 */ "G_VECREDUCE_FADD\000" |
| 13004 | /* 24610 */ "G_FADD\000" |
| 13005 | /* 24617 */ "G_VECREDUCE_SEQ_FADD\000" |
| 13006 | /* 24638 */ "G_STRICT_FADD\000" |
| 13007 | /* 24652 */ "G_ATOMICRMW_FADD\000" |
| 13008 | /* 24669 */ "t2QADD\000" |
| 13009 | /* 24676 */ "G_VECREDUCE_ADD\000" |
| 13010 | /* 24692 */ "G_ADD\000" |
| 13011 | /* 24698 */ "G_PTR_ADD\000" |
| 13012 | /* 24708 */ "G_ATOMICRMW_ADD\000" |
| 13013 | /* 24724 */ "VADDD\000" |
| 13014 | /* 24730 */ "VSELGED\000" |
| 13015 | /* 24738 */ "VCMPED\000" |
| 13016 | /* 24745 */ "VNEGD\000" |
| 13017 | /* 24751 */ "VCVTBHD\000" |
| 13018 | /* 24759 */ "VTOSHD\000" |
| 13019 | /* 24766 */ "VCVTTHD\000" |
| 13020 | /* 24774 */ "VTOUHD\000" |
| 13021 | /* 24781 */ "VMSR_FPSID\000" |
| 13022 | /* 24792 */ "VMRS_FPSID\000" |
| 13023 | /* 24803 */ "t2SMLALD\000" |
| 13024 | /* 24812 */ "VFMALD\000" |
| 13025 | /* 24819 */ "t2SMLSLD\000" |
| 13026 | /* 24828 */ "VFMSLD\000" |
| 13027 | /* 24835 */ "VTOSLD\000" |
| 13028 | /* 24842 */ "VNMULD\000" |
| 13029 | /* 24849 */ "VMULD\000" |
| 13030 | /* 24855 */ "VTOULD\000" |
| 13031 | /* 24862 */ "VFP_VMINNMD\000" |
| 13032 | /* 24874 */ "VFP_VMAXNMD\000" |
| 13033 | /* 24886 */ "VSCCLRMD\000" |
| 13034 | /* 24895 */ "VRINTMD\000" |
| 13035 | /* 24903 */ "G_ATOMICRMW_NAND\000" |
| 13036 | /* 24920 */ "MVE_VAND\000" |
| 13037 | /* 24929 */ "G_VECREDUCE_AND\000" |
| 13038 | /* 24945 */ "G_AND\000" |
| 13039 | /* 24951 */ "G_ATOMICRMW_AND\000" |
| 13040 | /* 24967 */ "tAND\000" |
| 13041 | /* 24972 */ "tSETEND\000" |
| 13042 | /* 24980 */ "LIFETIME_END\000" |
| 13043 | /* 24993 */ "tBRIND\000" |
| 13044 | /* 25000 */ "G_BRCOND\000" |
| 13045 | /* 25009 */ "G_ATOMICRMW_USUB_COND\000" |
| 13046 | /* 25031 */ "VRINTND\000" |
| 13047 | /* 25039 */ "G_LLROUND\000" |
| 13048 | /* 25049 */ "G_LROUND\000" |
| 13049 | /* 25058 */ "G_INTRINSIC_ROUND\000" |
| 13050 | /* 25076 */ "G_INTRINSIC_FPTRUNC_ROUND\000" |
| 13051 | /* 25102 */ "tTAILJMPdND\000" |
| 13052 | /* 25114 */ "VSHTOD\000" |
| 13053 | /* 25121 */ "VUHTOD\000" |
| 13054 | /* 25128 */ "VSITOD\000" |
| 13055 | /* 25135 */ "VUITOD\000" |
| 13056 | /* 25142 */ "VSLTOD\000" |
| 13057 | /* 25149 */ "VULTOD\000" |
| 13058 | /* 25156 */ "VCMPD\000" |
| 13059 | /* 25162 */ "VRINTPD\000" |
| 13060 | /* 25170 */ "VLD3d32_UPD\000" |
| 13061 | /* 25182 */ "VST3d32_UPD\000" |
| 13062 | /* 25194 */ "VLD4d32_UPD\000" |
| 13063 | /* 25206 */ "VST4d32_UPD\000" |
| 13064 | /* 25218 */ "VLD1LNd32_UPD\000" |
| 13065 | /* 25232 */ "VST1LNd32_UPD\000" |
| 13066 | /* 25246 */ "VLD2LNd32_UPD\000" |
| 13067 | /* 25260 */ "VST2LNd32_UPD\000" |
| 13068 | /* 25274 */ "VLD3LNd32_UPD\000" |
| 13069 | /* 25288 */ "VST3LNd32_UPD\000" |
| 13070 | /* 25302 */ "VLD4LNd32_UPD\000" |
| 13071 | /* 25316 */ "VST4LNd32_UPD\000" |
| 13072 | /* 25330 */ "VLD3DUPd32_UPD\000" |
| 13073 | /* 25345 */ "VLD4DUPd32_UPD\000" |
| 13074 | /* 25360 */ "VLD3q32_UPD\000" |
| 13075 | /* 25372 */ "VST3q32_UPD\000" |
| 13076 | /* 25384 */ "VLD4q32_UPD\000" |
| 13077 | /* 25396 */ "VST4q32_UPD\000" |
| 13078 | /* 25408 */ "VLD2LNq32_UPD\000" |
| 13079 | /* 25422 */ "VST2LNq32_UPD\000" |
| 13080 | /* 25436 */ "VLD3LNq32_UPD\000" |
| 13081 | /* 25450 */ "VST3LNq32_UPD\000" |
| 13082 | /* 25464 */ "VLD4LNq32_UPD\000" |
| 13083 | /* 25478 */ "VST4LNq32_UPD\000" |
| 13084 | /* 25492 */ "VLD3DUPq32_UPD\000" |
| 13085 | /* 25507 */ "VLD4DUPq32_UPD\000" |
| 13086 | /* 25522 */ "VLD3d16_UPD\000" |
| 13087 | /* 25534 */ "VST3d16_UPD\000" |
| 13088 | /* 25546 */ "VLD4d16_UPD\000" |
| 13089 | /* 25558 */ "VST4d16_UPD\000" |
| 13090 | /* 25570 */ "VLD1LNd16_UPD\000" |
| 13091 | /* 25584 */ "VST1LNd16_UPD\000" |
| 13092 | /* 25598 */ "VLD2LNd16_UPD\000" |
| 13093 | /* 25612 */ "VST2LNd16_UPD\000" |
| 13094 | /* 25626 */ "VLD3LNd16_UPD\000" |
| 13095 | /* 25640 */ "VST3LNd16_UPD\000" |
| 13096 | /* 25654 */ "VLD4LNd16_UPD\000" |
| 13097 | /* 25668 */ "VST4LNd16_UPD\000" |
| 13098 | /* 25682 */ "VLD3DUPd16_UPD\000" |
| 13099 | /* 25697 */ "VLD4DUPd16_UPD\000" |
| 13100 | /* 25712 */ "VLD3q16_UPD\000" |
| 13101 | /* 25724 */ "VST3q16_UPD\000" |
| 13102 | /* 25736 */ "VLD4q16_UPD\000" |
| 13103 | /* 25748 */ "VST4q16_UPD\000" |
| 13104 | /* 25760 */ "VLD2LNq16_UPD\000" |
| 13105 | /* 25774 */ "VST2LNq16_UPD\000" |
| 13106 | /* 25788 */ "VLD3LNq16_UPD\000" |
| 13107 | /* 25802 */ "VST3LNq16_UPD\000" |
| 13108 | /* 25816 */ "VLD4LNq16_UPD\000" |
| 13109 | /* 25830 */ "VST4LNq16_UPD\000" |
| 13110 | /* 25844 */ "VLD3DUPq16_UPD\000" |
| 13111 | /* 25859 */ "VLD4DUPq16_UPD\000" |
| 13112 | /* 25874 */ "VLD3d8_UPD\000" |
| 13113 | /* 25885 */ "VST3d8_UPD\000" |
| 13114 | /* 25896 */ "VLD4d8_UPD\000" |
| 13115 | /* 25907 */ "VST4d8_UPD\000" |
| 13116 | /* 25918 */ "VLD1LNd8_UPD\000" |
| 13117 | /* 25931 */ "VST1LNd8_UPD\000" |
| 13118 | /* 25944 */ "VLD2LNd8_UPD\000" |
| 13119 | /* 25957 */ "VST2LNd8_UPD\000" |
| 13120 | /* 25970 */ "VLD3LNd8_UPD\000" |
| 13121 | /* 25983 */ "VST3LNd8_UPD\000" |
| 13122 | /* 25996 */ "VLD4LNd8_UPD\000" |
| 13123 | /* 26009 */ "VST4LNd8_UPD\000" |
| 13124 | /* 26022 */ "VLD3DUPd8_UPD\000" |
| 13125 | /* 26036 */ "VLD4DUPd8_UPD\000" |
| 13126 | /* 26050 */ "VLD3q8_UPD\000" |
| 13127 | /* 26061 */ "VST3q8_UPD\000" |
| 13128 | /* 26072 */ "VLD4q8_UPD\000" |
| 13129 | /* 26083 */ "VST4q8_UPD\000" |
| 13130 | /* 26094 */ "VLD3DUPq8_UPD\000" |
| 13131 | /* 26108 */ "VLD4DUPq8_UPD\000" |
| 13132 | /* 26122 */ "RFEDA_UPD\000" |
| 13133 | /* 26132 */ "sysLDMDA_UPD\000" |
| 13134 | /* 26145 */ "sysSTMDA_UPD\000" |
| 13135 | /* 26158 */ "SRSDA_UPD\000" |
| 13136 | /* 26168 */ "VLDMDIA_UPD\000" |
| 13137 | /* 26180 */ "VSTMDIA_UPD\000" |
| 13138 | /* 26192 */ "RFEIA_UPD\000" |
| 13139 | /* 26202 */ "t2LDMIA_UPD\000" |
| 13140 | /* 26214 */ "sysLDMIA_UPD\000" |
| 13141 | /* 26227 */ "tLDMIA_UPD\000" |
| 13142 | /* 26238 */ "t2STMIA_UPD\000" |
| 13143 | /* 26250 */ "sysSTMIA_UPD\000" |
| 13144 | /* 26263 */ "tSTMIA_UPD\000" |
| 13145 | /* 26274 */ "VLDMSIA_UPD\000" |
| 13146 | /* 26286 */ "VSTMSIA_UPD\000" |
| 13147 | /* 26298 */ "t2SRSIA_UPD\000" |
| 13148 | /* 26310 */ "FLDMXIA_UPD\000" |
| 13149 | /* 26322 */ "FSTMXIA_UPD\000" |
| 13150 | /* 26334 */ "VLDMDDB_UPD\000" |
| 13151 | /* 26346 */ "VSTMDDB_UPD\000" |
| 13152 | /* 26358 */ "RFEDB_UPD\000" |
| 13153 | /* 26368 */ "t2LDMDB_UPD\000" |
| 13154 | /* 26380 */ "sysLDMDB_UPD\000" |
| 13155 | /* 26393 */ "t2STMDB_UPD\000" |
| 13156 | /* 26405 */ "sysSTMDB_UPD\000" |
| 13157 | /* 26418 */ "VLDMSDB_UPD\000" |
| 13158 | /* 26430 */ "VSTMSDB_UPD\000" |
| 13159 | /* 26442 */ "t2SRSDB_UPD\000" |
| 13160 | /* 26454 */ "FLDMXDB_UPD\000" |
| 13161 | /* 26466 */ "FSTMXDB_UPD\000" |
| 13162 | /* 26478 */ "RFEIB_UPD\000" |
| 13163 | /* 26488 */ "sysLDMIB_UPD\000" |
| 13164 | /* 26501 */ "sysSTMIB_UPD\000" |
| 13165 | /* 26514 */ "SRSIB_UPD\000" |
| 13166 | /* 26524 */ "VLD3d32Pseudo_UPD\000" |
| 13167 | /* 26542 */ "VST3d32Pseudo_UPD\000" |
| 13168 | /* 26560 */ "VLD4d32Pseudo_UPD\000" |
| 13169 | /* 26578 */ "VST4d32Pseudo_UPD\000" |
| 13170 | /* 26596 */ "VLD2LNd32Pseudo_UPD\000" |
| 13171 | /* 26616 */ "VST2LNd32Pseudo_UPD\000" |
| 13172 | /* 26636 */ "VLD3LNd32Pseudo_UPD\000" |
| 13173 | /* 26656 */ "VST3LNd32Pseudo_UPD\000" |
| 13174 | /* 26676 */ "VLD4LNd32Pseudo_UPD\000" |
| 13175 | /* 26696 */ "VST4LNd32Pseudo_UPD\000" |
| 13176 | /* 26716 */ "VLD3DUPd32Pseudo_UPD\000" |
| 13177 | /* 26737 */ "VLD4DUPd32Pseudo_UPD\000" |
| 13178 | /* 26758 */ "VLD3q32Pseudo_UPD\000" |
| 13179 | /* 26776 */ "VST3q32Pseudo_UPD\000" |
| 13180 | /* 26794 */ "VLD4q32Pseudo_UPD\000" |
| 13181 | /* 26812 */ "VST4q32Pseudo_UPD\000" |
| 13182 | /* 26830 */ "VLD1LNq32Pseudo_UPD\000" |
| 13183 | /* 26850 */ "VST1LNq32Pseudo_UPD\000" |
| 13184 | /* 26870 */ "VLD2LNq32Pseudo_UPD\000" |
| 13185 | /* 26890 */ "VST2LNq32Pseudo_UPD\000" |
| 13186 | /* 26910 */ "VLD3LNq32Pseudo_UPD\000" |
| 13187 | /* 26930 */ "VST3LNq32Pseudo_UPD\000" |
| 13188 | /* 26950 */ "VLD4LNq32Pseudo_UPD\000" |
| 13189 | /* 26970 */ "VST4LNq32Pseudo_UPD\000" |
| 13190 | /* 26990 */ "VLD3d16Pseudo_UPD\000" |
| 13191 | /* 27008 */ "VST3d16Pseudo_UPD\000" |
| 13192 | /* 27026 */ "VLD4d16Pseudo_UPD\000" |
| 13193 | /* 27044 */ "VST4d16Pseudo_UPD\000" |
| 13194 | /* 27062 */ "VLD2LNd16Pseudo_UPD\000" |
| 13195 | /* 27082 */ "VST2LNd16Pseudo_UPD\000" |
| 13196 | /* 27102 */ "VLD3LNd16Pseudo_UPD\000" |
| 13197 | /* 27122 */ "VST3LNd16Pseudo_UPD\000" |
| 13198 | /* 27142 */ "VLD4LNd16Pseudo_UPD\000" |
| 13199 | /* 27162 */ "VST4LNd16Pseudo_UPD\000" |
| 13200 | /* 27182 */ "VLD3DUPd16Pseudo_UPD\000" |
| 13201 | /* 27203 */ "VLD4DUPd16Pseudo_UPD\000" |
| 13202 | /* 27224 */ "VLD3q16Pseudo_UPD\000" |
| 13203 | /* 27242 */ "VST3q16Pseudo_UPD\000" |
| 13204 | /* 27260 */ "VLD4q16Pseudo_UPD\000" |
| 13205 | /* 27278 */ "VST4q16Pseudo_UPD\000" |
| 13206 | /* 27296 */ "VLD1LNq16Pseudo_UPD\000" |
| 13207 | /* 27316 */ "VST1LNq16Pseudo_UPD\000" |
| 13208 | /* 27336 */ "VLD2LNq16Pseudo_UPD\000" |
| 13209 | /* 27356 */ "VST2LNq16Pseudo_UPD\000" |
| 13210 | /* 27376 */ "VLD3LNq16Pseudo_UPD\000" |
| 13211 | /* 27396 */ "VST3LNq16Pseudo_UPD\000" |
| 13212 | /* 27416 */ "VLD4LNq16Pseudo_UPD\000" |
| 13213 | /* 27436 */ "VST4LNq16Pseudo_UPD\000" |
| 13214 | /* 27456 */ "VLD3d8Pseudo_UPD\000" |
| 13215 | /* 27473 */ "VST3d8Pseudo_UPD\000" |
| 13216 | /* 27490 */ "VLD4d8Pseudo_UPD\000" |
| 13217 | /* 27507 */ "VST4d8Pseudo_UPD\000" |
| 13218 | /* 27524 */ "VLD2LNd8Pseudo_UPD\000" |
| 13219 | /* 27543 */ "VST2LNd8Pseudo_UPD\000" |
| 13220 | /* 27562 */ "VLD3LNd8Pseudo_UPD\000" |
| 13221 | /* 27581 */ "VST3LNd8Pseudo_UPD\000" |
| 13222 | /* 27600 */ "VLD4LNd8Pseudo_UPD\000" |
| 13223 | /* 27619 */ "VST4LNd8Pseudo_UPD\000" |
| 13224 | /* 27638 */ "VLD3DUPd8Pseudo_UPD\000" |
| 13225 | /* 27658 */ "VLD4DUPd8Pseudo_UPD\000" |
| 13226 | /* 27678 */ "VLD3q8Pseudo_UPD\000" |
| 13227 | /* 27695 */ "VST3q8Pseudo_UPD\000" |
| 13228 | /* 27712 */ "VLD4q8Pseudo_UPD\000" |
| 13229 | /* 27729 */ "VST4q8Pseudo_UPD\000" |
| 13230 | /* 27746 */ "VLD1LNq8Pseudo_UPD\000" |
| 13231 | /* 27765 */ "VST1LNq8Pseudo_UPD\000" |
| 13232 | /* 27784 */ "VLD1q32HighQPseudo_UPD\000" |
| 13233 | /* 27807 */ "VST1q32HighQPseudo_UPD\000" |
| 13234 | /* 27830 */ "VLD1q64HighQPseudo_UPD\000" |
| 13235 | /* 27853 */ "VST1q64HighQPseudo_UPD\000" |
| 13236 | /* 27876 */ "VLD1q16HighQPseudo_UPD\000" |
| 13237 | /* 27899 */ "VST1q16HighQPseudo_UPD\000" |
| 13238 | /* 27922 */ "VLD1q8HighQPseudo_UPD\000" |
| 13239 | /* 27944 */ "VST1q8HighQPseudo_UPD\000" |
| 13240 | /* 27966 */ "VLD1q32LowQPseudo_UPD\000" |
| 13241 | /* 27988 */ "VST1q32LowQPseudo_UPD\000" |
| 13242 | /* 28010 */ "VLD1q64LowQPseudo_UPD\000" |
| 13243 | /* 28032 */ "VST1q64LowQPseudo_UPD\000" |
| 13244 | /* 28054 */ "VLD1q16LowQPseudo_UPD\000" |
| 13245 | /* 28076 */ "VST1q16LowQPseudo_UPD\000" |
| 13246 | /* 28098 */ "VLD1q8LowQPseudo_UPD\000" |
| 13247 | /* 28119 */ "VST1q8LowQPseudo_UPD\000" |
| 13248 | /* 28140 */ "VLD1q32HighTPseudo_UPD\000" |
| 13249 | /* 28163 */ "VST1q32HighTPseudo_UPD\000" |
| 13250 | /* 28186 */ "VLD1q64HighTPseudo_UPD\000" |
| 13251 | /* 28209 */ "VST1q64HighTPseudo_UPD\000" |
| 13252 | /* 28232 */ "VLD1q16HighTPseudo_UPD\000" |
| 13253 | /* 28255 */ "VST1q16HighTPseudo_UPD\000" |
| 13254 | /* 28278 */ "VLD1q8HighTPseudo_UPD\000" |
| 13255 | /* 28300 */ "VST1q8HighTPseudo_UPD\000" |
| 13256 | /* 28322 */ "VLD1q32LowTPseudo_UPD\000" |
| 13257 | /* 28344 */ "VST1q32LowTPseudo_UPD\000" |
| 13258 | /* 28366 */ "VLD1q64LowTPseudo_UPD\000" |
| 13259 | /* 28388 */ "VST1q64LowTPseudo_UPD\000" |
| 13260 | /* 28410 */ "VLD1q16LowTPseudo_UPD\000" |
| 13261 | /* 28432 */ "VST1q16LowTPseudo_UPD\000" |
| 13262 | /* 28454 */ "VLD1q8LowTPseudo_UPD\000" |
| 13263 | /* 28475 */ "VST1q8LowTPseudo_UPD\000" |
| 13264 | /* 28496 */ "VLD3DUPq32OddPseudo_UPD\000" |
| 13265 | /* 28520 */ "VLD4DUPq32OddPseudo_UPD\000" |
| 13266 | /* 28544 */ "VLD3DUPq16OddPseudo_UPD\000" |
| 13267 | /* 28568 */ "VLD4DUPq16OddPseudo_UPD\000" |
| 13268 | /* 28592 */ "VLD3DUPq8OddPseudo_UPD\000" |
| 13269 | /* 28615 */ "VLD4DUPq8OddPseudo_UPD\000" |
| 13270 | /* 28638 */ "VLD3q32oddPseudo_UPD\000" |
| 13271 | /* 28659 */ "VST3q32oddPseudo_UPD\000" |
| 13272 | /* 28680 */ "VLD4q32oddPseudo_UPD\000" |
| 13273 | /* 28701 */ "VST4q32oddPseudo_UPD\000" |
| 13274 | /* 28722 */ "VLD3q16oddPseudo_UPD\000" |
| 13275 | /* 28743 */ "VST3q16oddPseudo_UPD\000" |
| 13276 | /* 28764 */ "VLD4q16oddPseudo_UPD\000" |
| 13277 | /* 28785 */ "VST4q16oddPseudo_UPD\000" |
| 13278 | /* 28806 */ "VLD3q8oddPseudo_UPD\000" |
| 13279 | /* 28826 */ "VST3q8oddPseudo_UPD\000" |
| 13280 | /* 28846 */ "VLD4q8oddPseudo_UPD\000" |
| 13281 | /* 28866 */ "VST4q8oddPseudo_UPD\000" |
| 13282 | /* 28886 */ "VSELEQD\000" |
| 13283 | /* 28894 */ "LOAD_STACK_GUARD\000" |
| 13284 | /* 28911 */ "VLDRD\000" |
| 13285 | /* 28917 */ "VTOSIRD\000" |
| 13286 | /* 28925 */ "VTOUIRD\000" |
| 13287 | /* 28933 */ "VMOVRRD\000" |
| 13288 | /* 28941 */ "VRINTRD\000" |
| 13289 | /* 28949 */ "VSTRD\000" |
| 13290 | /* 28955 */ "VCVTASD\000" |
| 13291 | /* 28963 */ "VABSD\000" |
| 13292 | /* 28969 */ "AESD\000" |
| 13293 | /* 28974 */ "VNMLSD\000" |
| 13294 | /* 28981 */ "t2SMLSD\000" |
| 13295 | /* 28989 */ "VMLSD\000" |
| 13296 | /* 28995 */ "VFMSD\000" |
| 13297 | /* 29001 */ "VFNMSD\000" |
| 13298 | /* 29008 */ "VCVTMSD\000" |
| 13299 | /* 29016 */ "VCVTNSD\000" |
| 13300 | /* 29024 */ "VCVTPSD\000" |
| 13301 | /* 29032 */ "VCVTSD\000" |
| 13302 | /* 29039 */ "t2SMUSD\000" |
| 13303 | /* 29047 */ "VSELVSD\000" |
| 13304 | /* 29055 */ "VSELGTD\000" |
| 13305 | /* 29063 */ "VUSDOTD\000" |
| 13306 | /* 29071 */ "VSDOTD\000" |
| 13307 | /* 29078 */ "VUDOTD\000" |
| 13308 | /* 29085 */ "BF16VDOTI_VDOTD\000" |
| 13309 | /* 29101 */ "BF16VDOTS_VDOTD\000" |
| 13310 | /* 29117 */ "VSQRTD\000" |
| 13311 | /* 29124 */ "FCONSTD\000" |
| 13312 | /* 29132 */ "VCVTAUD\000" |
| 13313 | /* 29140 */ "VCVTMUD\000" |
| 13314 | /* 29148 */ "VCVTNUD\000" |
| 13315 | /* 29156 */ "VCVTPUD\000" |
| 13316 | /* 29164 */ "VDIVD\000" |
| 13317 | /* 29170 */ "VMOVD\000" |
| 13318 | /* 29176 */ "t2LDAEXD\000" |
| 13319 | /* 29185 */ "t2STLEXD\000" |
| 13320 | /* 29194 */ "t2LDREXD\000" |
| 13321 | /* 29203 */ "t2STREXD\000" |
| 13322 | /* 29212 */ "VRINTXD\000" |
| 13323 | /* 29220 */ "VCMPEZD\000" |
| 13324 | /* 29228 */ "VTOSIZD\000" |
| 13325 | /* 29236 */ "VTOUIZD\000" |
| 13326 | /* 29244 */ "VCMPZD\000" |
| 13327 | /* 29251 */ "VRINTZD\000" |
| 13328 | /* 29259 */ "PSEUDO_PROBE\000" |
| 13329 | /* 29272 */ "G_SSUBE\000" |
| 13330 | /* 29280 */ "G_USUBE\000" |
| 13331 | /* 29288 */ "SPACE\000" |
| 13332 | /* 29294 */ "G_FENCE\000" |
| 13333 | /* 29302 */ "ARITH_FENCE\000" |
| 13334 | /* 29314 */ "REG_SEQUENCE\000" |
| 13335 | /* 29327 */ "G_SADDE\000" |
| 13336 | /* 29335 */ "G_UADDE\000" |
| 13337 | /* 29343 */ "G_GET_FPMODE\000" |
| 13338 | /* 29356 */ "G_RESET_FPMODE\000" |
| 13339 | /* 29371 */ "G_SET_FPMODE\000" |
| 13340 | /* 29384 */ "G_FMINNUM_IEEE\000" |
| 13341 | /* 29399 */ "G_FMAXNUM_IEEE\000" |
| 13342 | /* 29414 */ "t2LE\000" |
| 13343 | /* 29419 */ "G_VSCALE\000" |
| 13344 | /* 29428 */ "G_JUMP_TABLE\000" |
| 13345 | /* 29441 */ "BUNDLE\000" |
| 13346 | /* 29448 */ "G_MEMSET_INLINE\000" |
| 13347 | /* 29464 */ "G_MEMCPY_INLINE\000" |
| 13348 | /* 29480 */ "RELOC_NONE\000" |
| 13349 | /* 29491 */ "LOCAL_ESCAPE\000" |
| 13350 | /* 29504 */ "G_FPTRUNCSTORE\000" |
| 13351 | /* 29519 */ "G_STACKRESTORE\000" |
| 13352 | /* 29534 */ "G_INDEXED_STORE\000" |
| 13353 | /* 29550 */ "G_STORE\000" |
| 13354 | /* 29558 */ "t2LDC2_PRE\000" |
| 13355 | /* 29569 */ "t2STC2_PRE\000" |
| 13356 | /* 29580 */ "t2LDRB_PRE\000" |
| 13357 | /* 29591 */ "t2STRB_PRE\000" |
| 13358 | /* 29602 */ "t2LDRSB_PRE\000" |
| 13359 | /* 29614 */ "t2LDC_PRE\000" |
| 13360 | /* 29624 */ "t2STC_PRE\000" |
| 13361 | /* 29634 */ "t2LDRD_PRE\000" |
| 13362 | /* 29645 */ "t2STRD_PRE\000" |
| 13363 | /* 29656 */ "t2LDRH_PRE\000" |
| 13364 | /* 29667 */ "t2STRH_PRE\000" |
| 13365 | /* 29678 */ "t2LDRSH_PRE\000" |
| 13366 | /* 29690 */ "t2LDC2L_PRE\000" |
| 13367 | /* 29702 */ "t2STC2L_PRE\000" |
| 13368 | /* 29714 */ "t2LDCL_PRE\000" |
| 13369 | /* 29725 */ "t2STCL_PRE\000" |
| 13370 | /* 29736 */ "t2LDR_PRE\000" |
| 13371 | /* 29746 */ "t2STR_PRE\000" |
| 13372 | /* 29756 */ "AESE\000" |
| 13373 | /* 29761 */ "G_BITREVERSE\000" |
| 13374 | /* 29774 */ "FAKE_USE\000" |
| 13375 | /* 29783 */ "DBG_VALUE\000" |
| 13376 | /* 29793 */ "G_GLOBAL_VALUE\000" |
| 13377 | /* 29808 */ "G_PTRAUTH_GLOBAL_VALUE\000" |
| 13378 | /* 29831 */ "CONVERGENCECTRL_GLUE\000" |
| 13379 | /* 29852 */ "G_STACKSAVE\000" |
| 13380 | /* 29864 */ "G_MEMMOVE\000" |
| 13381 | /* 29874 */ "G_FREEZE\000" |
| 13382 | /* 29883 */ "G_FCANONICALIZE\000" |
| 13383 | /* 29899 */ "G_FMODF\000" |
| 13384 | /* 29907 */ "t2UDF\000" |
| 13385 | /* 29913 */ "tUDF\000" |
| 13386 | /* 29918 */ "INIT_UNDEF\000" |
| 13387 | /* 29929 */ "G_IMPLICIT_DEF\000" |
| 13388 | /* 29944 */ "DBG_INSTR_REF\000" |
| 13389 | /* 29958 */ "t2DBG\000" |
| 13390 | /* 29964 */ "t2PACG\000" |
| 13391 | /* 29971 */ "G_FNEG\000" |
| 13392 | /* 29978 */ "t2CSNEG\000" |
| 13393 | /* 29986 */ "EXTRACT_SUBREG\000" |
| 13394 | /* 30001 */ "INSERT_SUBREG\000" |
| 13395 | /* 30015 */ "G_SEXT_INREG\000" |
| 13396 | /* 30028 */ "LDRB_PRE_REG\000" |
| 13397 | /* 30041 */ "STRB_PRE_REG\000" |
| 13398 | /* 30054 */ "LDR_PRE_REG\000" |
| 13399 | /* 30066 */ "STR_PRE_REG\000" |
| 13400 | /* 30078 */ "SUBREG_TO_REG\000" |
| 13401 | /* 30092 */ "LDRB_POST_REG\000" |
| 13402 | /* 30106 */ "STRB_POST_REG\000" |
| 13403 | /* 30120 */ "LDR_POST_REG\000" |
| 13404 | /* 30133 */ "STR_POST_REG\000" |
| 13405 | /* 30146 */ "LDRBT_POST_REG\000" |
| 13406 | /* 30161 */ "STRBT_POST_REG\000" |
| 13407 | /* 30176 */ "LDRT_POST_REG\000" |
| 13408 | /* 30190 */ "STRT_POST_REG\000" |
| 13409 | /* 30204 */ "G_ATOMIC_CMPXCHG\000" |
| 13410 | /* 30221 */ "G_ATOMICRMW_XCHG\000" |
| 13411 | /* 30238 */ "G_GET_ROUNDING\000" |
| 13412 | /* 30253 */ "G_SET_ROUNDING\000" |
| 13413 | /* 30268 */ "G_FLOG\000" |
| 13414 | /* 30275 */ "G_VAARG\000" |
| 13415 | /* 30283 */ "PREALLOCATED_ARG\000" |
| 13416 | /* 30300 */ "t2SG\000" |
| 13417 | /* 30305 */ "t2AUTG\000" |
| 13418 | /* 30312 */ "SHA1H\000" |
| 13419 | /* 30318 */ "t2CRC32H\000" |
| 13420 | /* 30327 */ "SHA256H\000" |
| 13421 | /* 30335 */ "t2LDAH\000" |
| 13422 | /* 30342 */ "VNMLAH\000" |
| 13423 | /* 30349 */ "VMLAH\000" |
| 13424 | /* 30355 */ "VFMAH\000" |
| 13425 | /* 30361 */ "VFNMAH\000" |
| 13426 | /* 30368 */ "VRINTAH\000" |
| 13427 | /* 30376 */ "t2SXTAH\000" |
| 13428 | /* 30384 */ "t2UXTAH\000" |
| 13429 | /* 30392 */ "t2TBH\000" |
| 13430 | /* 30398 */ "JUMPTABLE_TBH\000" |
| 13431 | /* 30412 */ "VSUBH\000" |
| 13432 | /* 30418 */ "t2CRC32CH\000" |
| 13433 | /* 30428 */ "G_PREFETCH\000" |
| 13434 | /* 30439 */ "VCVTBDH\000" |
| 13435 | /* 30447 */ "VADDH\000" |
| 13436 | /* 30453 */ "VCVTTDH\000" |
| 13437 | /* 30461 */ "VSELGEH\000" |
| 13438 | /* 30469 */ "VCMPEH\000" |
| 13439 | /* 30476 */ "VNEGH\000" |
| 13440 | /* 30482 */ "VTOSHH\000" |
| 13441 | /* 30489 */ "VTOUHH\000" |
| 13442 | /* 30496 */ "VTOSLH\000" |
| 13443 | /* 30503 */ "t2STLH\000" |
| 13444 | /* 30510 */ "G_CLMULH\000" |
| 13445 | /* 30519 */ "VNMULH\000" |
| 13446 | /* 30526 */ "G_SMULH\000" |
| 13447 | /* 30534 */ "G_UMULH\000" |
| 13448 | /* 30542 */ "VMULH\000" |
| 13449 | /* 30548 */ "VTOULH\000" |
| 13450 | /* 30555 */ "VFP_VMINNMH\000" |
| 13451 | /* 30567 */ "VFP_VMAXNMH\000" |
| 13452 | /* 30579 */ "VRINTMH\000" |
| 13453 | /* 30587 */ "G_FTANH\000" |
| 13454 | /* 30595 */ "G_FSINH\000" |
| 13455 | /* 30603 */ "VRINTNH\000" |
| 13456 | /* 30611 */ "VSHTOH\000" |
| 13457 | /* 30618 */ "VUHTOH\000" |
| 13458 | /* 30625 */ "VSITOH\000" |
| 13459 | /* 30632 */ "VUITOH\000" |
| 13460 | /* 30639 */ "VSLTOH\000" |
| 13461 | /* 30646 */ "VULTOH\000" |
| 13462 | /* 30653 */ "VCMPH\000" |
| 13463 | /* 30659 */ "VRINTPH\000" |
| 13464 | /* 30667 */ "VSELEQH\000" |
| 13465 | /* 30675 */ "PICLDRH\000" |
| 13466 | /* 30683 */ "VLDRH\000" |
| 13467 | /* 30689 */ "VTOSIRH\000" |
| 13468 | /* 30697 */ "VTOUIRH\000" |
| 13469 | /* 30705 */ "VRINTRH\000" |
| 13470 | /* 30713 */ "PICSTRH\000" |
| 13471 | /* 30721 */ "VSTRH\000" |
| 13472 | /* 30727 */ "VMOVRH\000" |
| 13473 | /* 30734 */ "VCVTASH\000" |
| 13474 | /* 30742 */ "VABSH\000" |
| 13475 | /* 30748 */ "VCVTBSH\000" |
| 13476 | /* 30756 */ "VNMLSH\000" |
| 13477 | /* 30763 */ "VMLSH\000" |
| 13478 | /* 30769 */ "VFMSH\000" |
| 13479 | /* 30775 */ "VFNMSH\000" |
| 13480 | /* 30782 */ "VCVTMSH\000" |
| 13481 | /* 30790 */ "VINSH\000" |
| 13482 | /* 30796 */ "VCVTNSH\000" |
| 13483 | /* 30804 */ "G_FCOSH\000" |
| 13484 | /* 30812 */ "VCVTPSH\000" |
| 13485 | /* 30820 */ "PICLDRSH\000" |
| 13486 | /* 30829 */ "tLDRSH\000" |
| 13487 | /* 30836 */ "VCVTTSH\000" |
| 13488 | /* 30844 */ "tPUSH\000" |
| 13489 | /* 30850 */ "t2REVSH\000" |
| 13490 | /* 30858 */ "tREVSH\000" |
| 13491 | /* 30865 */ "VSELVSH\000" |
| 13492 | /* 30873 */ "VSELGTH\000" |
| 13493 | /* 30881 */ "VSQRTH\000" |
| 13494 | /* 30888 */ "FCONSTH\000" |
| 13495 | /* 30896 */ "t2SXTH\000" |
| 13496 | /* 30903 */ "tSXTH\000" |
| 13497 | /* 30909 */ "t2UXTH\000" |
| 13498 | /* 30916 */ "tUXTH\000" |
| 13499 | /* 30922 */ "VCVTAUH\000" |
| 13500 | /* 30930 */ "VCVTMUH\000" |
| 13501 | /* 30938 */ "VCVTNUH\000" |
| 13502 | /* 30946 */ "VCVTPUH\000" |
| 13503 | /* 30954 */ "VDIVH\000" |
| 13504 | /* 30960 */ "VMOVH\000" |
| 13505 | /* 30966 */ "t2LDAEXH\000" |
| 13506 | /* 30975 */ "t2STLEXH\000" |
| 13507 | /* 30984 */ "t2LDREXH\000" |
| 13508 | /* 30993 */ "t2STREXH\000" |
| 13509 | /* 31002 */ "VRINTXH\000" |
| 13510 | /* 31010 */ "VCMPEZH\000" |
| 13511 | /* 31018 */ "VTOSIZH\000" |
| 13512 | /* 31026 */ "VTOUIZH\000" |
| 13513 | /* 31034 */ "VCMPZH\000" |
| 13514 | /* 31041 */ "VRINTZH\000" |
| 13515 | /* 31049 */ "MVE_VSBCI\000" |
| 13516 | /* 31059 */ "MVE_VADCI\000" |
| 13517 | /* 31069 */ "VFMALDI\000" |
| 13518 | /* 31077 */ "VFMSLDI\000" |
| 13519 | /* 31085 */ "VUSDOTDI\000" |
| 13520 | /* 31094 */ "VSDOTDI\000" |
| 13521 | /* 31102 */ "VSUDOTDI\000" |
| 13522 | /* 31111 */ "VUDOTDI\000" |
| 13523 | /* 31119 */ "t2BFI\000" |
| 13524 | /* 31125 */ "DBG_PHI\000" |
| 13525 | /* 31133 */ "VBF16MALBQI\000" |
| 13526 | /* 31145 */ "VFMALQI\000" |
| 13527 | /* 31153 */ "VFMSLQI\000" |
| 13528 | /* 31161 */ "VBF16MALTQI\000" |
| 13529 | /* 31173 */ "VUSDOTQI\000" |
| 13530 | /* 31182 */ "VSDOTQI\000" |
| 13531 | /* 31190 */ "VSUDOTQI\000" |
| 13532 | /* 31199 */ "VUDOTQI\000" |
| 13533 | /* 31207 */ "G_FPTOSI\000" |
| 13534 | /* 31216 */ "t2BTI\000" |
| 13535 | /* 31222 */ "t2PACBTI\000" |
| 13536 | /* 31231 */ "t2CALL_BTI\000" |
| 13537 | /* 31242 */ "G_FPTOUI\000" |
| 13538 | /* 31251 */ "G_FPOWI\000" |
| 13539 | /* 31259 */ "t2BXJ\000" |
| 13540 | /* 31265 */ "WIN__DBZCHK\000" |
| 13541 | /* 31277 */ "COPY_LANEMASK\000" |
| 13542 | /* 31291 */ "G_PTRMASK\000" |
| 13543 | /* 31301 */ "WIN__CHKSTK\000" |
| 13544 | /* 31313 */ "t2UMAAL\000" |
| 13545 | /* 31321 */ "t2SMLAL\000" |
| 13546 | /* 31329 */ "t2UMLAL\000" |
| 13547 | /* 31337 */ "LOADDUAL\000" |
| 13548 | /* 31346 */ "STOREDUAL\000" |
| 13549 | /* 31356 */ "tBL\000" |
| 13550 | /* 31360 */ "GC_LABEL\000" |
| 13551 | /* 31369 */ "DBG_LABEL\000" |
| 13552 | /* 31379 */ "EH_LABEL\000" |
| 13553 | /* 31388 */ "ANNOTATION_LABEL\000" |
| 13554 | /* 31405 */ "ICALL_BRANCH_FUNNEL\000" |
| 13555 | /* 31425 */ "t2SEL\000" |
| 13556 | /* 31431 */ "t2CSEL\000" |
| 13557 | /* 31438 */ "MVE_VPSEL\000" |
| 13558 | /* 31448 */ "G_FSHL\000" |
| 13559 | /* 31455 */ "MVE_SQSHL\000" |
| 13560 | /* 31465 */ "MVE_UQSHL\000" |
| 13561 | /* 31475 */ "MVE_UQRSHL\000" |
| 13562 | /* 31486 */ "G_SHL\000" |
| 13563 | /* 31492 */ "G_FCEIL\000" |
| 13564 | /* 31500 */ "G_SAVGCEIL\000" |
| 13565 | /* 31511 */ "G_UAVGCEIL\000" |
| 13566 | /* 31522 */ "BMOVPCB_CALL\000" |
| 13567 | /* 31535 */ "PATCHABLE_TAIL_CALL\000" |
| 13568 | /* 31555 */ "tBLXNS_CALL\000" |
| 13569 | /* 31567 */ "PATCHABLE_TYPED_EVENT_CALL\000" |
| 13570 | /* 31594 */ "PATCHABLE_EVENT_CALL\000" |
| 13571 | /* 31615 */ "tBX_CALL\000" |
| 13572 | /* 31624 */ "BMOVPCRX_CALL\000" |
| 13573 | /* 31638 */ "FENTRY_CALL\000" |
| 13574 | /* 31650 */ "MVE_SQSHLL\000" |
| 13575 | /* 31661 */ "MVE_UQSHLL\000" |
| 13576 | /* 31672 */ "MVE_UQRSHLL\000" |
| 13577 | /* 31684 */ "KILL\000" |
| 13578 | /* 31689 */ "t2SMULL\000" |
| 13579 | /* 31697 */ "t2UMULL\000" |
| 13580 | /* 31705 */ "G_CONSTANT_POOL\000" |
| 13581 | /* 31721 */ "MVE_SQRSHRL\000" |
| 13582 | /* 31733 */ "MVE_SRSHRL\000" |
| 13583 | /* 31744 */ "MVE_URSHRL\000" |
| 13584 | /* 31755 */ "MVE_LSRL\000" |
| 13585 | /* 31764 */ "G_ROTL\000" |
| 13586 | /* 31771 */ "t2STL\000" |
| 13587 | /* 31777 */ "t2MUL\000" |
| 13588 | /* 31783 */ "G_VECREDUCE_FMUL\000" |
| 13589 | /* 31800 */ "G_FMUL\000" |
| 13590 | /* 31807 */ "G_VECREDUCE_SEQ_FMUL\000" |
| 13591 | /* 31828 */ "G_STRICT_FMUL\000" |
| 13592 | /* 31842 */ "G_CLMUL\000" |
| 13593 | /* 31850 */ "t2SMMUL\000" |
| 13594 | /* 31858 */ "G_VECREDUCE_MUL\000" |
| 13595 | /* 31874 */ "G_MUL\000" |
| 13596 | /* 31880 */ "tMUL\000" |
| 13597 | /* 31885 */ "SHA1M\000" |
| 13598 | /* 31891 */ "MVE_VRINTf32M\000" |
| 13599 | /* 31905 */ "MVE_VRINTf16M\000" |
| 13600 | /* 31919 */ "VLLDM\000" |
| 13601 | /* 31925 */ "G_FREM\000" |
| 13602 | /* 31932 */ "G_STRICT_FREM\000" |
| 13603 | /* 31946 */ "G_SREM\000" |
| 13604 | /* 31953 */ "G_UREM\000" |
| 13605 | /* 31960 */ "G_SDIVREM\000" |
| 13606 | /* 31970 */ "G_UDIVREM\000" |
| 13607 | /* 31980 */ "LDRB_PRE_IMM\000" |
| 13608 | /* 31993 */ "STRB_PRE_IMM\000" |
| 13609 | /* 32006 */ "LDR_PRE_IMM\000" |
| 13610 | /* 32018 */ "STR_PRE_IMM\000" |
| 13611 | /* 32030 */ "LDRB_POST_IMM\000" |
| 13612 | /* 32044 */ "STRB_POST_IMM\000" |
| 13613 | /* 32058 */ "LDR_POST_IMM\000" |
| 13614 | /* 32071 */ "STR_POST_IMM\000" |
| 13615 | /* 32084 */ "LDRBT_POST_IMM\000" |
| 13616 | /* 32099 */ "STRBT_POST_IMM\000" |
| 13617 | /* 32114 */ "LDRT_POST_IMM\000" |
| 13618 | /* 32128 */ "STRT_POST_IMM\000" |
| 13619 | /* 32142 */ "KCFI_CHECK_ARM\000" |
| 13620 | /* 32157 */ "t2CLRM\000" |
| 13621 | /* 32164 */ "INLINEASM\000" |
| 13622 | /* 32174 */ "VLSTM\000" |
| 13623 | /* 32180 */ "G_VECREDUCE_FMINIMUM\000" |
| 13624 | /* 32201 */ "G_FMINIMUM\000" |
| 13625 | /* 32212 */ "G_ATOMICRMW_FMINIMUM\000" |
| 13626 | /* 32233 */ "G_VECREDUCE_FMAXIMUM\000" |
| 13627 | /* 32254 */ "G_FMAXIMUM\000" |
| 13628 | /* 32265 */ "G_ATOMICRMW_FMAXIMUM\000" |
| 13629 | /* 32286 */ "G_VECREDUCE_FMINIMUMNUM\000" |
| 13630 | /* 32310 */ "G_FMINIMUMNUM\000" |
| 13631 | /* 32324 */ "G_ATOMICRMW_FMINIMUMNUM\000" |
| 13632 | /* 32348 */ "G_VECREDUCE_FMAXIMUMNUM\000" |
| 13633 | /* 32372 */ "G_FMAXIMUMNUM\000" |
| 13634 | /* 32386 */ "G_ATOMICRMW_FMAXIMUMNUM\000" |
| 13635 | /* 32410 */ "G_FMINNUM\000" |
| 13636 | /* 32420 */ "G_FMAXNUM\000" |
| 13637 | /* 32430 */ "t2MSR_M\000" |
| 13638 | /* 32438 */ "t2MRS_M\000" |
| 13639 | /* 32446 */ "MVE_VRINTf32N\000" |
| 13640 | /* 32460 */ "MVE_VRINTf16N\000" |
| 13641 | /* 32474 */ "t2SETPAN\000" |
| 13642 | /* 32483 */ "G_FATAN\000" |
| 13643 | /* 32491 */ "G_FTAN\000" |
| 13644 | /* 32498 */ "G_INTRINSIC_ROUNDEVEN\000" |
| 13645 | /* 32520 */ "G_ASSERT_ALIGN\000" |
| 13646 | /* 32535 */ "G_FCOPYSIGN\000" |
| 13647 | /* 32547 */ "G_VECREDUCE_FMIN\000" |
| 13648 | /* 32564 */ "G_ATOMICRMW_FMIN\000" |
| 13649 | /* 32581 */ "G_VECREDUCE_SMIN\000" |
| 13650 | /* 32598 */ "G_SMIN\000" |
| 13651 | /* 32605 */ "G_VECREDUCE_UMIN\000" |
| 13652 | /* 32622 */ "G_UMIN\000" |
| 13653 | /* 32629 */ "G_ATOMICRMW_UMIN\000" |
| 13654 | /* 32646 */ "G_ATOMICRMW_MIN\000" |
| 13655 | /* 32662 */ "G_FASIN\000" |
| 13656 | /* 32670 */ "G_FSIN\000" |
| 13657 | /* 32677 */ "tCMN\000" |
| 13658 | /* 32682 */ "CFI_INSTRUCTION\000" |
| 13659 | /* 32698 */ "t2LDC2_OPTION\000" |
| 13660 | /* 32712 */ "t2STC2_OPTION\000" |
| 13661 | /* 32726 */ "t2LDC_OPTION\000" |
| 13662 | /* 32739 */ "t2STC_OPTION\000" |
| 13663 | /* 32752 */ "t2LDC2L_OPTION\000" |
| 13664 | /* 32767 */ "t2STC2L_OPTION\000" |
| 13665 | /* 32782 */ "t2LDCL_OPTION\000" |
| 13666 | /* 32796 */ "t2STCL_OPTION\000" |
| 13667 | /* 32810 */ "G_CTLZ_ZERO_POISON\000" |
| 13668 | /* 32829 */ "G_CTTZ_ZERO_POISON\000" |
| 13669 | /* 32848 */ "MVE_VORN\000" |
| 13670 | /* 32857 */ "MVE_VMVN\000" |
| 13671 | /* 32866 */ "tMVN\000" |
| 13672 | /* 32871 */ "tADJCALLSTACKDOWN\000" |
| 13673 | /* 32889 */ "G_SSUBO\000" |
| 13674 | /* 32897 */ "G_USUBO\000" |
| 13675 | /* 32905 */ "G_SADDO\000" |
| 13676 | /* 32913 */ "G_UADDO\000" |
| 13677 | /* 32921 */ "JUMP_TABLE_DEBUG_INFO\000" |
| 13678 | /* 32943 */ "G_SMULO\000" |
| 13679 | /* 32951 */ "G_UMULO\000" |
| 13680 | /* 32959 */ "G_BZERO\000" |
| 13681 | /* 32967 */ "SHA1P\000" |
| 13682 | /* 32973 */ "MVE_VRINTf32P\000" |
| 13683 | /* 32987 */ "MVE_VRINTf16P\000" |
| 13684 | /* 33001 */ "STACKMAP\000" |
| 13685 | /* 33010 */ "G_DEBUGTRAP\000" |
| 13686 | /* 33022 */ "G_UBSANTRAP\000" |
| 13687 | /* 33034 */ "G_TRAP\000" |
| 13688 | /* 33041 */ "tTRAP\000" |
| 13689 | /* 33047 */ "G_ATOMICRMW_UDEC_WRAP\000" |
| 13690 | /* 33069 */ "G_ATOMICRMW_UINC_WRAP\000" |
| 13691 | /* 33091 */ "G_BSWAP\000" |
| 13692 | /* 33099 */ "t2CDP\000" |
| 13693 | /* 33105 */ "G_SITOFP\000" |
| 13694 | /* 33114 */ "G_UITOFP\000" |
| 13695 | /* 33123 */ "G_FCMP\000" |
| 13696 | /* 33130 */ "G_STRICT_FCMP\000" |
| 13697 | /* 33144 */ "G_ICMP\000" |
| 13698 | /* 33151 */ "G_SCMP\000" |
| 13699 | /* 33158 */ "G_UCMP\000" |
| 13700 | /* 33165 */ "CONVERGENCECTRL_LOOP\000" |
| 13701 | /* 33186 */ "G_CTPOP\000" |
| 13702 | /* 33194 */ "tPOP\000" |
| 13703 | /* 33199 */ "PATCHABLE_OP\000" |
| 13704 | /* 33212 */ "FAULTING_OP\000" |
| 13705 | /* 33224 */ "SEH_SaveSP\000" |
| 13706 | /* 33235 */ "tADDrSP\000" |
| 13707 | /* 33243 */ "MVE_LCTP\000" |
| 13708 | /* 33252 */ "MVE_LETP\000" |
| 13709 | /* 33261 */ "t2WhileLoopStartTP\000" |
| 13710 | /* 33280 */ "t2DoLoopStartTP\000" |
| 13711 | /* 33296 */ "tADJCALLSTACKUP\000" |
| 13712 | /* 33312 */ "PREALLOCATED_SETUP\000" |
| 13713 | /* 33331 */ "SWP\000" |
| 13714 | /* 33335 */ "G_FLDEXP\000" |
| 13715 | /* 33344 */ "G_STRICT_FLDEXP\000" |
| 13716 | /* 33360 */ "G_FEXP\000" |
| 13717 | /* 33367 */ "G_FFREXP\000" |
| 13718 | /* 33376 */ "VLD1d32Q\000" |
| 13719 | /* 33385 */ "VST1d32Q\000" |
| 13720 | /* 33394 */ "VLD1d64Q\000" |
| 13721 | /* 33403 */ "VST1d64Q\000" |
| 13722 | /* 33412 */ "VLD1d16Q\000" |
| 13723 | /* 33421 */ "VST1d16Q\000" |
| 13724 | /* 33430 */ "VLD1d8Q\000" |
| 13725 | /* 33438 */ "VST1d8Q\000" |
| 13726 | /* 33446 */ "VBF16MALBQ\000" |
| 13727 | /* 33457 */ "VFMALQ\000" |
| 13728 | /* 33464 */ "VFMSLQ\000" |
| 13729 | /* 33471 */ "VBF16MALTQ\000" |
| 13730 | /* 33482 */ "VUSDOTQ\000" |
| 13731 | /* 33490 */ "VSDOTQ\000" |
| 13732 | /* 33497 */ "VUDOTQ\000" |
| 13733 | /* 33504 */ "BF16VDOTI_VDOTQ\000" |
| 13734 | /* 33520 */ "BF16VDOTS_VDOTQ\000" |
| 13735 | /* 33536 */ "t2SMMLAR\000" |
| 13736 | /* 33545 */ "t2MSR_AR\000" |
| 13737 | /* 33554 */ "t2MRS_AR\000" |
| 13738 | /* 33563 */ "t2MRSsys_AR\000" |
| 13739 | /* 33575 */ "G_BR\000" |
| 13740 | /* 33580 */ "INLINEASM_BR\000" |
| 13741 | /* 33593 */ "t2MCR\000" |
| 13742 | /* 33599 */ "t2ADR\000" |
| 13743 | /* 33605 */ "tADR\000" |
| 13744 | /* 33610 */ "G_BLOCK_ADDR\000" |
| 13745 | /* 33623 */ "PICLDR\000" |
| 13746 | /* 33630 */ "MEMBARRIER\000" |
| 13747 | /* 33641 */ "G_CONSTANT_FOLD_BARRIER\000" |
| 13748 | /* 33665 */ "PATCHABLE_FUNCTION_ENTER\000" |
| 13749 | /* 33690 */ "G_READCYCLECOUNTER\000" |
| 13750 | /* 33709 */ "G_READSTEADYCOUNTER\000" |
| 13751 | /* 33729 */ "G_READ_REGISTER\000" |
| 13752 | /* 33745 */ "G_WRITE_REGISTER\000" |
| 13753 | /* 33762 */ "G_ASHR\000" |
| 13754 | /* 33769 */ "G_FSHR\000" |
| 13755 | /* 33776 */ "G_LSHR\000" |
| 13756 | /* 33783 */ "MVE_SQRSHR\000" |
| 13757 | /* 33794 */ "MVE_SRSHR\000" |
| 13758 | /* 33804 */ "MVE_URSHR\000" |
| 13759 | /* 33814 */ "VMOVHR\000" |
| 13760 | /* 33821 */ "MOVPCLR\000" |
| 13761 | /* 33829 */ "tBL_PUSHLR\000" |
| 13762 | /* 33840 */ "t2SMMULR\000" |
| 13763 | /* 33849 */ "t2SUBS_PC_LR\000" |
| 13764 | /* 33862 */ "SEH_SaveLR\000" |
| 13765 | /* 33873 */ "t2WhileLoopStartLR\000" |
| 13766 | /* 33892 */ "MVE_VEOR\000" |
| 13767 | /* 33901 */ "tEOR\000" |
| 13768 | /* 33906 */ "CONVERGENCECTRL_ANCHOR\000" |
| 13769 | /* 33929 */ "G_FFLOOR\000" |
| 13770 | /* 33938 */ "G_SAVGFLOOR\000" |
| 13771 | /* 33950 */ "G_UAVGFLOOR\000" |
| 13772 | /* 33962 */ "tROR\000" |
| 13773 | /* 33967 */ "G_EXTRACT_SUBVECTOR\000" |
| 13774 | /* 33987 */ "G_INSERT_SUBVECTOR\000" |
| 13775 | /* 34006 */ "G_BUILD_VECTOR\000" |
| 13776 | /* 34021 */ "G_SHUFFLE_VECTOR\000" |
| 13777 | /* 34038 */ "G_STEP_VECTOR\000" |
| 13778 | /* 34052 */ "G_SPLAT_VECTOR\000" |
| 13779 | /* 34067 */ "G_VECREDUCE_XOR\000" |
| 13780 | /* 34083 */ "G_XOR\000" |
| 13781 | /* 34089 */ "G_ATOMICRMW_XOR\000" |
| 13782 | /* 34105 */ "G_VECREDUCE_OR\000" |
| 13783 | /* 34120 */ "G_OR\000" |
| 13784 | /* 34125 */ "G_ATOMICRMW_OR\000" |
| 13785 | /* 34140 */ "VMSR_VPR\000" |
| 13786 | /* 34149 */ "VMRS_VPR\000" |
| 13787 | /* 34158 */ "t2MCRR\000" |
| 13788 | /* 34165 */ "VMOVDRR\000" |
| 13789 | /* 34173 */ "MVE_VORR\000" |
| 13790 | /* 34182 */ "tORR\000" |
| 13791 | /* 34187 */ "VMOVSRR\000" |
| 13792 | /* 34195 */ "t2SMMLSR\000" |
| 13793 | /* 34204 */ "VMSR\000" |
| 13794 | /* 34209 */ "VMOVSR\000" |
| 13795 | /* 34216 */ "G_ROTR\000" |
| 13796 | /* 34223 */ "G_INTTOPTR\000" |
| 13797 | /* 34234 */ "PICSTR\000" |
| 13798 | /* 34241 */ "VNMLAS\000" |
| 13799 | /* 34248 */ "VMLAS\000" |
| 13800 | /* 34254 */ "VFMAS\000" |
| 13801 | /* 34260 */ "VFNMAS\000" |
| 13802 | /* 34267 */ "VRINTAS\000" |
| 13803 | /* 34275 */ "G_FABS\000" |
| 13804 | /* 34282 */ "G_ABS\000" |
| 13805 | /* 34288 */ "tRSBS\000" |
| 13806 | /* 34294 */ "VSUBS\000" |
| 13807 | /* 34300 */ "tSBCS\000" |
| 13808 | /* 34306 */ "tADCS\000" |
| 13809 | /* 34312 */ "G_ABDS\000" |
| 13810 | /* 34319 */ "VADDS\000" |
| 13811 | /* 34325 */ "VCVTDS\000" |
| 13812 | /* 34332 */ "VSELGES\000" |
| 13813 | /* 34340 */ "VCMPES\000" |
| 13814 | /* 34347 */ "G_UNMERGE_VALUES\000" |
| 13815 | /* 34364 */ "G_MERGE_VALUES\000" |
| 13816 | /* 34379 */ "VNEGS\000" |
| 13817 | /* 34385 */ "VCVTBHS\000" |
| 13818 | /* 34393 */ "VTOSHS\000" |
| 13819 | /* 34400 */ "VCVTTHS\000" |
| 13820 | /* 34408 */ "VTOUHS\000" |
| 13821 | /* 34415 */ "t2DLS\000" |
| 13822 | /* 34421 */ "t2MLS\000" |
| 13823 | /* 34427 */ "t2SMMLS\000" |
| 13824 | /* 34435 */ "VTOSLS\000" |
| 13825 | /* 34442 */ "G_CTLS\000" |
| 13826 | /* 34449 */ "VNMULS\000" |
| 13827 | /* 34456 */ "VMULS\000" |
| 13828 | /* 34462 */ "VTOULS\000" |
| 13829 | /* 34469 */ "t2WLS\000" |
| 13830 | /* 34475 */ "VFP_VMINNMS\000" |
| 13831 | /* 34487 */ "VFP_VMAXNMS\000" |
| 13832 | /* 34499 */ "VSCCLRMS\000" |
| 13833 | /* 34508 */ "VRINTMS\000" |
| 13834 | /* 34516 */ "VRINTNS\000" |
| 13835 | /* 34524 */ "VMSR_FPCXTNS\000" |
| 13836 | /* 34537 */ "VMRS_FPCXTNS\000" |
| 13837 | /* 34550 */ "tBXNS\000" |
| 13838 | /* 34556 */ "G_FACOS\000" |
| 13839 | /* 34564 */ "G_FCOS\000" |
| 13840 | /* 34571 */ "G_FSINCOS\000" |
| 13841 | /* 34581 */ "VSHTOS\000" |
| 13842 | /* 34588 */ "VUHTOS\000" |
| 13843 | /* 34595 */ "VSITOS\000" |
| 13844 | /* 34602 */ "VUITOS\000" |
| 13845 | /* 34609 */ "VSLTOS\000" |
| 13846 | /* 34616 */ "VULTOS\000" |
| 13847 | /* 34623 */ "tCPS\000" |
| 13848 | /* 34628 */ "G_STRICT_FCMPS\000" |
| 13849 | /* 34643 */ "VCMPS\000" |
| 13850 | /* 34649 */ "VRINTPS\000" |
| 13851 | /* 34657 */ "VSELEQS\000" |
| 13852 | /* 34665 */ "JUMPTABLE_ADDRS\000" |
| 13853 | /* 34681 */ "VLDRS\000" |
| 13854 | /* 34687 */ "VTOSIRS\000" |
| 13855 | /* 34695 */ "VTOUIRS\000" |
| 13856 | /* 34703 */ "VMRS\000" |
| 13857 | /* 34708 */ "G_CONCAT_VECTORS\000" |
| 13858 | /* 34725 */ "VMOVRRS\000" |
| 13859 | /* 34733 */ "VRINTRS\000" |
| 13860 | /* 34741 */ "VSTRS\000" |
| 13861 | /* 34747 */ "VMOVRS\000" |
| 13862 | /* 34754 */ "COPY_TO_REGCLASS\000" |
| 13863 | /* 34771 */ "G_IS_FPCLASS\000" |
| 13864 | /* 34784 */ "VCVTASS\000" |
| 13865 | /* 34792 */ "VABSS\000" |
| 13866 | /* 34798 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000" |
| 13867 | /* 34828 */ "G_VECTOR_COMPRESS\000" |
| 13868 | /* 34846 */ "VNMLSS\000" |
| 13869 | /* 34853 */ "VMLSS\000" |
| 13870 | /* 34859 */ "VFMSS\000" |
| 13871 | /* 34865 */ "VFNMSS\000" |
| 13872 | /* 34872 */ "VCVTMSS\000" |
| 13873 | /* 34880 */ "VCVTNSS\000" |
| 13874 | /* 34888 */ "VCVTPSS\000" |
| 13875 | /* 34896 */ "VSELVSS\000" |
| 13876 | /* 34904 */ "G_INTRINSIC_W_SIDE_EFFECTS\000" |
| 13877 | /* 34931 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000" |
| 13878 | /* 34969 */ "VSELGTS\000" |
| 13879 | /* 34977 */ "VSQRTS\000" |
| 13880 | /* 34984 */ "JUMPTABLE_INSTS\000" |
| 13881 | /* 35000 */ "FCONSTS\000" |
| 13882 | /* 35008 */ "VMSR_FPCXTS\000" |
| 13883 | /* 35020 */ "VMRS_FPCXTS\000" |
| 13884 | /* 35032 */ "VCVTAUS\000" |
| 13885 | /* 35040 */ "VCVTMUS\000" |
| 13886 | /* 35048 */ "VCVTNUS\000" |
| 13887 | /* 35056 */ "VCVTPUS\000" |
| 13888 | /* 35064 */ "VDIVS\000" |
| 13889 | /* 35070 */ "VMOVS\000" |
| 13890 | /* 35076 */ "VRINTXS\000" |
| 13891 | /* 35084 */ "VCMPEZS\000" |
| 13892 | /* 35092 */ "VTOSIZS\000" |
| 13893 | /* 35100 */ "VTOUIZS\000" |
| 13894 | /* 35108 */ "VCMPZS\000" |
| 13895 | /* 35115 */ "VRINTZS\000" |
| 13896 | /* 35123 */ "G_TRUNC_SSAT_S\000" |
| 13897 | /* 35138 */ "VLD1d32T\000" |
| 13898 | /* 35147 */ "VST1d32T\000" |
| 13899 | /* 35156 */ "VLD1d64T\000" |
| 13900 | /* 35165 */ "VST1d64T\000" |
| 13901 | /* 35174 */ "VLD1d16T\000" |
| 13902 | /* 35183 */ "VST1d16T\000" |
| 13903 | /* 35192 */ "VLD1d8T\000" |
| 13904 | /* 35200 */ "VST1d8T\000" |
| 13905 | /* 35208 */ "G_SSUBSAT\000" |
| 13906 | /* 35218 */ "G_USUBSAT\000" |
| 13907 | /* 35228 */ "G_SADDSAT\000" |
| 13908 | /* 35238 */ "G_UADDSAT\000" |
| 13909 | /* 35248 */ "G_SSHLSAT\000" |
| 13910 | /* 35258 */ "G_USHLSAT\000" |
| 13911 | /* 35268 */ "t2SSAT\000" |
| 13912 | /* 35275 */ "t2USAT\000" |
| 13913 | /* 35282 */ "G_SMULFIXSAT\000" |
| 13914 | /* 35295 */ "G_UMULFIXSAT\000" |
| 13915 | /* 35308 */ "G_SDIVFIXSAT\000" |
| 13916 | /* 35321 */ "G_UDIVFIXSAT\000" |
| 13917 | /* 35334 */ "G_ATOMICRMW_USUB_SAT\000" |
| 13918 | /* 35355 */ "G_FPTOSI_SAT\000" |
| 13919 | /* 35368 */ "G_FPTOUI_SAT\000" |
| 13920 | /* 35381 */ "FMSTAT\000" |
| 13921 | /* 35388 */ "t2TTAT\000" |
| 13922 | /* 35395 */ "t2SMLABT\000" |
| 13923 | /* 35404 */ "t2PKHBT\000" |
| 13924 | /* 35412 */ "t2SMLALBT\000" |
| 13925 | /* 35422 */ "t2SMULBT\000" |
| 13926 | /* 35431 */ "t2LDRBT\000" |
| 13927 | /* 35439 */ "t2STRBT\000" |
| 13928 | /* 35447 */ "t2LDRSBT\000" |
| 13929 | /* 35456 */ "G_EXTRACT\000" |
| 13930 | /* 35466 */ "G_SELECT\000" |
| 13931 | /* 35475 */ "G_BRINDIRECT\000" |
| 13932 | /* 35488 */ "ERET\000" |
| 13933 | /* 35493 */ "CATCHRET\000" |
| 13934 | /* 35502 */ "CLEANUPRET\000" |
| 13935 | /* 35513 */ "t2LDMIA_RET\000" |
| 13936 | /* 35525 */ "PATCHABLE_RET\000" |
| 13937 | /* 35539 */ "tPOP_RET\000" |
| 13938 | /* 35548 */ "tBXNS_RET\000" |
| 13939 | /* 35558 */ "t2BXAUT_RET\000" |
| 13940 | /* 35570 */ "tBX_RET\000" |
| 13941 | /* 35578 */ "t2LDC2_OFFSET\000" |
| 13942 | /* 35592 */ "t2STC2_OFFSET\000" |
| 13943 | /* 35606 */ "t2LDC_OFFSET\000" |
| 13944 | /* 35619 */ "t2STC_OFFSET\000" |
| 13945 | /* 35632 */ "t2LDC2L_OFFSET\000" |
| 13946 | /* 35647 */ "t2STC2L_OFFSET\000" |
| 13947 | /* 35662 */ "t2LDCL_OFFSET\000" |
| 13948 | /* 35676 */ "t2STCL_OFFSET\000" |
| 13949 | /* 35690 */ "G_MEMSET\000" |
| 13950 | /* 35699 */ "t2LDRHT\000" |
| 13951 | /* 35707 */ "t2STRHT\000" |
| 13952 | /* 35715 */ "t2LDRSHT\000" |
| 13953 | /* 35724 */ "t2IT\000" |
| 13954 | /* 35729 */ "t2RBIT\000" |
| 13955 | /* 35736 */ "PATCHABLE_FUNCTION_EXIT\000" |
| 13956 | /* 35760 */ "G_BRJT\000" |
| 13957 | /* 35767 */ "t2TBB_JT\000" |
| 13958 | /* 35776 */ "tTBB_JT\000" |
| 13959 | /* 35784 */ "t2TBH_JT\000" |
| 13960 | /* 35793 */ "tTBH_JT\000" |
| 13961 | /* 35801 */ "t2BR_JT\000" |
| 13962 | /* 35809 */ "t2LEApcrelJT\000" |
| 13963 | /* 35822 */ "tLEApcrelJT\000" |
| 13964 | /* 35834 */ "G_EXTRACT_VECTOR_ELT\000" |
| 13965 | /* 35855 */ "G_INSERT_VECTOR_ELT\000" |
| 13966 | /* 35875 */ "tHLT\000" |
| 13967 | /* 35880 */ "G_FCONSTANT\000" |
| 13968 | /* 35892 */ "G_CONSTANT\000" |
| 13969 | /* 35903 */ "G_INTRINSIC_CONVERGENT\000" |
| 13970 | /* 35926 */ "t2HINT\000" |
| 13971 | /* 35933 */ "tHINT\000" |
| 13972 | /* 35939 */ "STATEPOINT\000" |
| 13973 | /* 35950 */ "PATCHPOINT\000" |
| 13974 | /* 35961 */ "G_PTRTOINT\000" |
| 13975 | /* 35972 */ "G_FRINT\000" |
| 13976 | /* 35980 */ "G_INTRINSIC_LLRINT\000" |
| 13977 | /* 35999 */ "G_INTRINSIC_LRINT\000" |
| 13978 | /* 36017 */ "G_FNEARBYINT\000" |
| 13979 | /* 36030 */ "MVE_VPNOT\000" |
| 13980 | /* 36040 */ "tBKPT\000" |
| 13981 | /* 36046 */ "G_VASTART\000" |
| 13982 | /* 36056 */ "LIFETIME_START\000" |
| 13983 | /* 36071 */ "G_INVOKE_REGION_START\000" |
| 13984 | /* 36093 */ "t2LDRT\000" |
| 13985 | /* 36100 */ "G_INSERT\000" |
| 13986 | /* 36109 */ "G_FSQRT\000" |
| 13987 | /* 36117 */ "G_STRICT_FSQRT\000" |
| 13988 | /* 36132 */ "t2STRT\000" |
| 13989 | /* 36139 */ "G_BITCAST\000" |
| 13990 | /* 36149 */ "G_ADDRSPACE_CAST\000" |
| 13991 | /* 36166 */ "DBG_VALUE_LIST\000" |
| 13992 | /* 36181 */ "VMSR_FPINST\000" |
| 13993 | /* 36193 */ "VMRS_FPINST\000" |
| 13994 | /* 36205 */ "MVE_MEMSETLOOPINST\000" |
| 13995 | /* 36224 */ "MVE_MEMCPYLOOPINST\000" |
| 13996 | /* 36243 */ "t2LDC2_POST\000" |
| 13997 | /* 36255 */ "t2STC2_POST\000" |
| 13998 | /* 36267 */ "t2LDRB_POST\000" |
| 13999 | /* 36279 */ "t2STRB_POST\000" |
| 14000 | /* 36291 */ "t2LDRSB_POST\000" |
| 14001 | /* 36304 */ "t2LDC_POST\000" |
| 14002 | /* 36315 */ "t2STC_POST\000" |
| 14003 | /* 36326 */ "t2LDRD_POST\000" |
| 14004 | /* 36338 */ "t2STRD_POST\000" |
| 14005 | /* 36350 */ "t2LDRH_POST\000" |
| 14006 | /* 36362 */ "t2STRH_POST\000" |
| 14007 | /* 36374 */ "t2LDRSH_POST\000" |
| 14008 | /* 36387 */ "t2LDC2L_POST\000" |
| 14009 | /* 36400 */ "t2STC2L_POST\000" |
| 14010 | /* 36413 */ "t2LDCL_POST\000" |
| 14011 | /* 36425 */ "t2STCL_POST\000" |
| 14012 | /* 36437 */ "t2LDR_POST\000" |
| 14013 | /* 36448 */ "t2STR_POST\000" |
| 14014 | /* 36459 */ "LDRBT_POST\000" |
| 14015 | /* 36470 */ "STRBT_POST\000" |
| 14016 | /* 36481 */ "LDRT_POST\000" |
| 14017 | /* 36491 */ "STRT_POST\000" |
| 14018 | /* 36501 */ "MVE_VPST\000" |
| 14019 | /* 36510 */ "tTST\000" |
| 14020 | /* 36515 */ "t2TT\000" |
| 14021 | /* 36520 */ "t2SMLATT\000" |
| 14022 | /* 36529 */ "t2SMLALTT\000" |
| 14023 | /* 36539 */ "t2SMULTT\000" |
| 14024 | /* 36548 */ "t2TTT\000" |
| 14025 | /* 36554 */ "BF16_VCVTT\000" |
| 14026 | /* 36565 */ "t2AUT\000" |
| 14027 | /* 36571 */ "t2BXAUT\000" |
| 14028 | /* 36579 */ "VJCVT\000" |
| 14029 | /* 36585 */ "BF16_VCVT\000" |
| 14030 | /* 36595 */ "t2SMLAWT\000" |
| 14031 | /* 36604 */ "t2SMULWT\000" |
| 14032 | /* 36613 */ "G_FPEXT\000" |
| 14033 | /* 36621 */ "G_SEXT\000" |
| 14034 | /* 36628 */ "G_ASSERT_SEXT\000" |
| 14035 | /* 36642 */ "G_ANYEXT\000" |
| 14036 | /* 36651 */ "G_ZEXT\000" |
| 14037 | /* 36658 */ "G_ASSERT_ZEXT\000" |
| 14038 | /* 36672 */ "G_ABDU\000" |
| 14039 | /* 36679 */ "G_TRUNC_SSAT_U\000" |
| 14040 | /* 36694 */ "G_TRUNC_USAT_U\000" |
| 14041 | /* 36709 */ "t2REV\000" |
| 14042 | /* 36715 */ "tREV\000" |
| 14043 | /* 36720 */ "G_FDIV\000" |
| 14044 | /* 36727 */ "G_STRICT_FDIV\000" |
| 14045 | /* 36741 */ "t2SDIV\000" |
| 14046 | /* 36748 */ "G_SDIV\000" |
| 14047 | /* 36755 */ "t2UDIV\000" |
| 14048 | /* 36762 */ "G_UDIV\000" |
| 14049 | /* 36769 */ "G_GET_FPENV\000" |
| 14050 | /* 36781 */ "G_RESET_FPENV\000" |
| 14051 | /* 36795 */ "G_SET_FPENV\000" |
| 14052 | /* 36807 */ "t2CSINV\000" |
| 14053 | /* 36815 */ "t2CRC32W\000" |
| 14054 | /* 36824 */ "t2RFEIAW\000" |
| 14055 | /* 36833 */ "t2RFEDBW\000" |
| 14056 | /* 36842 */ "t2CRC32CW\000" |
| 14057 | /* 36852 */ "G_FPOW\000" |
| 14058 | /* 36859 */ "MVE_VRINTf32X\000" |
| 14059 | /* 36873 */ "MVE_VRINTf16X\000" |
| 14060 | /* 36887 */ "G_VECREDUCE_FMAX\000" |
| 14061 | /* 36904 */ "G_ATOMICRMW_FMAX\000" |
| 14062 | /* 36921 */ "G_VECREDUCE_SMAX\000" |
| 14063 | /* 36938 */ "G_SMAX\000" |
| 14064 | /* 36945 */ "G_VECREDUCE_UMAX\000" |
| 14065 | /* 36962 */ "G_UMAX\000" |
| 14066 | /* 36969 */ "G_ATOMICRMW_UMAX\000" |
| 14067 | /* 36986 */ "G_ATOMICRMW_MAX\000" |
| 14068 | /* 37002 */ "t2SHSAX\000" |
| 14069 | /* 37010 */ "t2UHSAX\000" |
| 14070 | /* 37018 */ "t2QSAX\000" |
| 14071 | /* 37025 */ "t2UQSAX\000" |
| 14072 | /* 37033 */ "t2SSAX\000" |
| 14073 | /* 37040 */ "t2USAX\000" |
| 14074 | /* 37047 */ "tBX\000" |
| 14075 | /* 37051 */ "t2SMLADX\000" |
| 14076 | /* 37060 */ "t2SMUADX\000" |
| 14077 | /* 37069 */ "t2SMLALDX\000" |
| 14078 | /* 37079 */ "t2SMLSLDX\000" |
| 14079 | /* 37089 */ "t2SMLSDX\000" |
| 14080 | /* 37098 */ "t2SMUSDX\000" |
| 14081 | /* 37107 */ "t2LDAEX\000" |
| 14082 | /* 37115 */ "G_FRAME_INDEX\000" |
| 14083 | /* 37129 */ "t2STLEX\000" |
| 14084 | /* 37137 */ "t2LDREX\000" |
| 14085 | /* 37145 */ "t2CLREX\000" |
| 14086 | /* 37153 */ "t2STREX\000" |
| 14087 | /* 37161 */ "t2SBFX\000" |
| 14088 | /* 37168 */ "G_SBFX\000" |
| 14089 | /* 37175 */ "t2UBFX\000" |
| 14090 | /* 37182 */ "G_UBFX\000" |
| 14091 | /* 37189 */ "G_SMULFIX\000" |
| 14092 | /* 37199 */ "G_UMULFIX\000" |
| 14093 | /* 37209 */ "G_SDIVFIX\000" |
| 14094 | /* 37219 */ "G_UDIVFIX\000" |
| 14095 | /* 37229 */ "BLX\000" |
| 14096 | /* 37233 */ "MOVPCRX\000" |
| 14097 | /* 37241 */ "t2RRX\000" |
| 14098 | /* 37247 */ "t2SHASX\000" |
| 14099 | /* 37255 */ "t2UHASX\000" |
| 14100 | /* 37263 */ "t2QASX\000" |
| 14101 | /* 37270 */ "t2UQASX\000" |
| 14102 | /* 37278 */ "t2SASX\000" |
| 14103 | /* 37285 */ "t2UASX\000" |
| 14104 | /* 37292 */ "G_MEMCPY\000" |
| 14105 | /* 37301 */ "COPY\000" |
| 14106 | /* 37306 */ "CONSTPOOL_ENTRY\000" |
| 14107 | /* 37322 */ "CONVERGENCECTRL_ENTRY\000" |
| 14108 | /* 37344 */ "MVE_VRINTf32Z\000" |
| 14109 | /* 37358 */ "MVE_VRINTf16Z\000" |
| 14110 | /* 37372 */ "tCBZ\000" |
| 14111 | /* 37377 */ "t2CLZ\000" |
| 14112 | /* 37383 */ "G_CTLZ\000" |
| 14113 | /* 37390 */ "tCBNZ\000" |
| 14114 | /* 37396 */ "G_CTTZ\000" |
| 14115 | /* 37403 */ "MVE_VCVTs32f32a\000" |
| 14116 | /* 37419 */ "MVE_VCVTu32f32a\000" |
| 14117 | /* 37435 */ "MVE_VCVTs16f16a\000" |
| 14118 | /* 37451 */ "MVE_VCVTu16f16a\000" |
| 14119 | /* 37467 */ "MVE_VLD20_32_wb\000" |
| 14120 | /* 37483 */ "MVE_VST20_32_wb\000" |
| 14121 | /* 37499 */ "MVE_VLD40_32_wb\000" |
| 14122 | /* 37515 */ "MVE_VST40_32_wb\000" |
| 14123 | /* 37531 */ "MVE_VLD21_32_wb\000" |
| 14124 | /* 37547 */ "MVE_VST21_32_wb\000" |
| 14125 | /* 37563 */ "MVE_VLD41_32_wb\000" |
| 14126 | /* 37579 */ "MVE_VST41_32_wb\000" |
| 14127 | /* 37595 */ "MVE_VLD42_32_wb\000" |
| 14128 | /* 37611 */ "MVE_VST42_32_wb\000" |
| 14129 | /* 37627 */ "MVE_VLD43_32_wb\000" |
| 14130 | /* 37643 */ "MVE_VST43_32_wb\000" |
| 14131 | /* 37659 */ "MVE_VLD20_16_wb\000" |
| 14132 | /* 37675 */ "MVE_VST20_16_wb\000" |
| 14133 | /* 37691 */ "MVE_VLD40_16_wb\000" |
| 14134 | /* 37707 */ "MVE_VST40_16_wb\000" |
| 14135 | /* 37723 */ "MVE_VLD21_16_wb\000" |
| 14136 | /* 37739 */ "MVE_VST21_16_wb\000" |
| 14137 | /* 37755 */ "MVE_VLD41_16_wb\000" |
| 14138 | /* 37771 */ "MVE_VST41_16_wb\000" |
| 14139 | /* 37787 */ "MVE_VLD42_16_wb\000" |
| 14140 | /* 37803 */ "MVE_VST42_16_wb\000" |
| 14141 | /* 37819 */ "MVE_VLD43_16_wb\000" |
| 14142 | /* 37835 */ "MVE_VST43_16_wb\000" |
| 14143 | /* 37851 */ "MVE_VLD20_8_wb\000" |
| 14144 | /* 37866 */ "MVE_VST20_8_wb\000" |
| 14145 | /* 37881 */ "MVE_VLD40_8_wb\000" |
| 14146 | /* 37896 */ "MVE_VST40_8_wb\000" |
| 14147 | /* 37911 */ "MVE_VLD21_8_wb\000" |
| 14148 | /* 37926 */ "MVE_VST21_8_wb\000" |
| 14149 | /* 37941 */ "MVE_VLD41_8_wb\000" |
| 14150 | /* 37956 */ "MVE_VST41_8_wb\000" |
| 14151 | /* 37971 */ "MVE_VLD42_8_wb\000" |
| 14152 | /* 37986 */ "MVE_VST42_8_wb\000" |
| 14153 | /* 38001 */ "MVE_VLD43_8_wb\000" |
| 14154 | /* 38016 */ "MVE_VST43_8_wb\000" |
| 14155 | /* 38031 */ "t2Bcc\000" |
| 14156 | /* 38037 */ "tBcc\000" |
| 14157 | /* 38042 */ "VMOVDcc\000" |
| 14158 | /* 38050 */ "VMOVHcc\000" |
| 14159 | /* 38058 */ "VMOVScc\000" |
| 14160 | /* 38066 */ "MVE_VADDVs32acc\000" |
| 14161 | /* 38082 */ "MVE_VADDLVs32acc\000" |
| 14162 | /* 38099 */ "MVE_VADDVu32acc\000" |
| 14163 | /* 38115 */ "MVE_VADDLVu32acc\000" |
| 14164 | /* 38132 */ "MVE_VADDVs16acc\000" |
| 14165 | /* 38148 */ "MVE_VADDVu16acc\000" |
| 14166 | /* 38164 */ "MVE_VADDVs8acc\000" |
| 14167 | /* 38179 */ "MVE_VADDVu8acc\000" |
| 14168 | /* 38194 */ "MVE_VADDVs32no_acc\000" |
| 14169 | /* 38213 */ "MVE_VADDLVs32no_acc\000" |
| 14170 | /* 38233 */ "MVE_VADDVu32no_acc\000" |
| 14171 | /* 38252 */ "MVE_VADDLVu32no_acc\000" |
| 14172 | /* 38272 */ "MVE_VADDVs16no_acc\000" |
| 14173 | /* 38291 */ "MVE_VADDVu16no_acc\000" |
| 14174 | /* 38310 */ "MVE_VADDVs8no_acc\000" |
| 14175 | /* 38328 */ "MVE_VADDVu8no_acc\000" |
| 14176 | /* 38346 */ "t2LoopEndDec\000" |
| 14177 | /* 38359 */ "t2LoopDec\000" |
| 14178 | /* 38369 */ "CDE_VCX1_vec\000" |
| 14179 | /* 38382 */ "CDE_VCX2_vec\000" |
| 14180 | /* 38395 */ "CDE_VCX3_vec\000" |
| 14181 | /* 38408 */ "CDE_VCX1A_vec\000" |
| 14182 | /* 38422 */ "CDE_VCX2A_vec\000" |
| 14183 | /* 38436 */ "CDE_VCX3A_vec\000" |
| 14184 | /* 38450 */ "t2BFic\000" |
| 14185 | /* 38457 */ "t2LDRpci_pic\000" |
| 14186 | /* 38470 */ "tLDRpci_pic\000" |
| 14187 | /* 38482 */ "SEH_StackAlloc\000" |
| 14188 | /* 38497 */ "VDUPLN32d\000" |
| 14189 | /* 38507 */ "VDUP32d\000" |
| 14190 | /* 38515 */ "VNEGs32d\000" |
| 14191 | /* 38524 */ "VDUPLN16d\000" |
| 14192 | /* 38534 */ "VDUP16d\000" |
| 14193 | /* 38542 */ "VNEGs16d\000" |
| 14194 | /* 38551 */ "VDUPLN8d\000" |
| 14195 | /* 38560 */ "VDUP8d\000" |
| 14196 | /* 38567 */ "VNEGs8d\000" |
| 14197 | /* 38575 */ "VBICd\000" |
| 14198 | /* 38581 */ "VANDd\000" |
| 14199 | /* 38587 */ "VRECPEd\000" |
| 14200 | /* 38595 */ "VRSQRTEd\000" |
| 14201 | /* 38604 */ "VBIFd\000" |
| 14202 | /* 38610 */ "VBSLd\000" |
| 14203 | /* 38616 */ "VORNd\000" |
| 14204 | /* 38622 */ "VMVNd\000" |
| 14205 | /* 38628 */ "tTAILJMPd\000" |
| 14206 | /* 38638 */ "VBSPd\000" |
| 14207 | /* 38644 */ "VSWPd\000" |
| 14208 | /* 38650 */ "VEORd\000" |
| 14209 | /* 38656 */ "VORRd\000" |
| 14210 | /* 38662 */ "VBITd\000" |
| 14211 | /* 38668 */ "VCNTd\000" |
| 14212 | /* 38674 */ "MQQPRLoad\000" |
| 14213 | /* 38684 */ "MQQQQPRLoad\000" |
| 14214 | /* 38696 */ "BR_JTadd\000" |
| 14215 | /* 38705 */ "t2MSRbanked\000" |
| 14216 | /* 38717 */ "t2MRSbanked\000" |
| 14217 | /* 38729 */ "BL_pred\000" |
| 14218 | /* 38737 */ "BX_pred\000" |
| 14219 | /* 38745 */ "BLX_pred\000" |
| 14220 | /* 38754 */ "VCMLAv2f32_indexed\000" |
| 14221 | /* 38773 */ "VCMLAv4f32_indexed\000" |
| 14222 | /* 38792 */ "VCMLAv4f16_indexed\000" |
| 14223 | /* 38811 */ "VCMLAv8f16_indexed\000" |
| 14224 | /* 38830 */ "VLD2q32PseudoWB_fixed\000" |
| 14225 | /* 38852 */ "VST2q32PseudoWB_fixed\000" |
| 14226 | /* 38874 */ "VLD2q16PseudoWB_fixed\000" |
| 14227 | /* 38896 */ "VST2q16PseudoWB_fixed\000" |
| 14228 | /* 38918 */ "VLD2q8PseudoWB_fixed\000" |
| 14229 | /* 38939 */ "VST2q8PseudoWB_fixed\000" |
| 14230 | /* 38960 */ "VLD1d32QPseudoWB_fixed\000" |
| 14231 | /* 38983 */ "VST1d32QPseudoWB_fixed\000" |
| 14232 | /* 39006 */ "VLD1d64QPseudoWB_fixed\000" |
| 14233 | /* 39029 */ "VST1d64QPseudoWB_fixed\000" |
| 14234 | /* 39052 */ "VLD1d16QPseudoWB_fixed\000" |
| 14235 | /* 39075 */ "VST1d16QPseudoWB_fixed\000" |
| 14236 | /* 39098 */ "VLD1d8QPseudoWB_fixed\000" |
| 14237 | /* 39120 */ "VST1d8QPseudoWB_fixed\000" |
| 14238 | /* 39142 */ "VLD1d32TPseudoWB_fixed\000" |
| 14239 | /* 39165 */ "VST1d32TPseudoWB_fixed\000" |
| 14240 | /* 39188 */ "VLD1d64TPseudoWB_fixed\000" |
| 14241 | /* 39211 */ "VST1d64TPseudoWB_fixed\000" |
| 14242 | /* 39234 */ "VLD1d16TPseudoWB_fixed\000" |
| 14243 | /* 39257 */ "VST1d16TPseudoWB_fixed\000" |
| 14244 | /* 39280 */ "VLD1d8TPseudoWB_fixed\000" |
| 14245 | /* 39302 */ "VST1d8TPseudoWB_fixed\000" |
| 14246 | /* 39324 */ "VLD2DUPq32OddPseudoWB_fixed\000" |
| 14247 | /* 39352 */ "VLD2DUPq16OddPseudoWB_fixed\000" |
| 14248 | /* 39380 */ "VLD2DUPq8OddPseudoWB_fixed\000" |
| 14249 | /* 39407 */ "VLD2b32wb_fixed\000" |
| 14250 | /* 39423 */ "VST2b32wb_fixed\000" |
| 14251 | /* 39439 */ "VLD1d32wb_fixed\000" |
| 14252 | /* 39455 */ "VST1d32wb_fixed\000" |
| 14253 | /* 39471 */ "VLD2d32wb_fixed\000" |
| 14254 | /* 39487 */ "VST2d32wb_fixed\000" |
| 14255 | /* 39503 */ "VLD1DUPd32wb_fixed\000" |
| 14256 | /* 39522 */ "VLD2DUPd32wb_fixed\000" |
| 14257 | /* 39541 */ "VLD1q32wb_fixed\000" |
| 14258 | /* 39557 */ "VST1q32wb_fixed\000" |
| 14259 | /* 39573 */ "VLD2q32wb_fixed\000" |
| 14260 | /* 39589 */ "VST2q32wb_fixed\000" |
| 14261 | /* 39605 */ "VLD1DUPq32wb_fixed\000" |
| 14262 | /* 39624 */ "VLD2DUPd32x2wb_fixed\000" |
| 14263 | /* 39645 */ "VLD2DUPd16x2wb_fixed\000" |
| 14264 | /* 39666 */ "VLD2DUPd8x2wb_fixed\000" |
| 14265 | /* 39686 */ "VLD1d64wb_fixed\000" |
| 14266 | /* 39702 */ "VST1d64wb_fixed\000" |
| 14267 | /* 39718 */ "VLD1q64wb_fixed\000" |
| 14268 | /* 39734 */ "VST1q64wb_fixed\000" |
| 14269 | /* 39750 */ "VLD2b16wb_fixed\000" |
| 14270 | /* 39766 */ "VST2b16wb_fixed\000" |
| 14271 | /* 39782 */ "VLD1d16wb_fixed\000" |
| 14272 | /* 39798 */ "VST1d16wb_fixed\000" |
| 14273 | /* 39814 */ "VLD2d16wb_fixed\000" |
| 14274 | /* 39830 */ "VST2d16wb_fixed\000" |
| 14275 | /* 39846 */ "VLD1DUPd16wb_fixed\000" |
| 14276 | /* 39865 */ "VLD2DUPd16wb_fixed\000" |
| 14277 | /* 39884 */ "VLD1q16wb_fixed\000" |
| 14278 | /* 39900 */ "VST1q16wb_fixed\000" |
| 14279 | /* 39916 */ "VLD2q16wb_fixed\000" |
| 14280 | /* 39932 */ "VST2q16wb_fixed\000" |
| 14281 | /* 39948 */ "VLD1DUPq16wb_fixed\000" |
| 14282 | /* 39967 */ "VLD2b8wb_fixed\000" |
| 14283 | /* 39982 */ "VST2b8wb_fixed\000" |
| 14284 | /* 39997 */ "VLD1d8wb_fixed\000" |
| 14285 | /* 40012 */ "VST1d8wb_fixed\000" |
| 14286 | /* 40027 */ "VLD2d8wb_fixed\000" |
| 14287 | /* 40042 */ "VST2d8wb_fixed\000" |
| 14288 | /* 40057 */ "VLD1DUPd8wb_fixed\000" |
| 14289 | /* 40075 */ "VLD2DUPd8wb_fixed\000" |
| 14290 | /* 40093 */ "VLD1q8wb_fixed\000" |
| 14291 | /* 40108 */ "VST1q8wb_fixed\000" |
| 14292 | /* 40123 */ "VLD2q8wb_fixed\000" |
| 14293 | /* 40138 */ "VST2q8wb_fixed\000" |
| 14294 | /* 40153 */ "VLD1DUPq8wb_fixed\000" |
| 14295 | /* 40171 */ "VLD1d32Qwb_fixed\000" |
| 14296 | /* 40188 */ "VST1d32Qwb_fixed\000" |
| 14297 | /* 40205 */ "VLD1d64Qwb_fixed\000" |
| 14298 | /* 40222 */ "VST1d64Qwb_fixed\000" |
| 14299 | /* 40239 */ "VLD1d16Qwb_fixed\000" |
| 14300 | /* 40256 */ "VST1d16Qwb_fixed\000" |
| 14301 | /* 40273 */ "VLD1d8Qwb_fixed\000" |
| 14302 | /* 40289 */ "VST1d8Qwb_fixed\000" |
| 14303 | /* 40305 */ "VLD1d32Twb_fixed\000" |
| 14304 | /* 40322 */ "VST1d32Twb_fixed\000" |
| 14305 | /* 40339 */ "VLD1d64Twb_fixed\000" |
| 14306 | /* 40356 */ "VST1d64Twb_fixed\000" |
| 14307 | /* 40373 */ "VLD1d16Twb_fixed\000" |
| 14308 | /* 40390 */ "VST1d16Twb_fixed\000" |
| 14309 | /* 40407 */ "VLD1d8Twb_fixed\000" |
| 14310 | /* 40423 */ "VST1d8Twb_fixed\000" |
| 14311 | /* 40439 */ "VCVTs2fd\000" |
| 14312 | /* 40448 */ "VCVTxs2fd\000" |
| 14313 | /* 40458 */ "VCVTu2fd\000" |
| 14314 | /* 40467 */ "VCVTxu2fd\000" |
| 14315 | /* 40477 */ "VMLAfd\000" |
| 14316 | /* 40484 */ "VFMAfd\000" |
| 14317 | /* 40491 */ "VSUBfd\000" |
| 14318 | /* 40498 */ "VABDfd\000" |
| 14319 | /* 40505 */ "VADDfd\000" |
| 14320 | /* 40512 */ "VACGEfd\000" |
| 14321 | /* 40520 */ "VCGEfd\000" |
| 14322 | /* 40527 */ "VRECPEfd\000" |
| 14323 | /* 40536 */ "VRSQRTEfd\000" |
| 14324 | /* 40546 */ "VNEGfd\000" |
| 14325 | /* 40553 */ "VMULfd\000" |
| 14326 | /* 40560 */ "VMINfd\000" |
| 14327 | /* 40567 */ "VCEQfd\000" |
| 14328 | /* 40574 */ "VABSfd\000" |
| 14329 | /* 40581 */ "VMLSfd\000" |
| 14330 | /* 40588 */ "VFMSfd\000" |
| 14331 | /* 40595 */ "VRECPSfd\000" |
| 14332 | /* 40604 */ "VRSQRTSfd\000" |
| 14333 | /* 40614 */ "VACGTfd\000" |
| 14334 | /* 40622 */ "VCGTfd\000" |
| 14335 | /* 40629 */ "VMAXfd\000" |
| 14336 | /* 40636 */ "VMLAslfd\000" |
| 14337 | /* 40645 */ "VMULslfd\000" |
| 14338 | /* 40654 */ "VMLSslfd\000" |
| 14339 | /* 40663 */ "VCVTs2hd\000" |
| 14340 | /* 40672 */ "VCVTxs2hd\000" |
| 14341 | /* 40682 */ "VCVTu2hd\000" |
| 14342 | /* 40691 */ "VCVTxu2hd\000" |
| 14343 | /* 40701 */ "VMLAhd\000" |
| 14344 | /* 40708 */ "VFMAhd\000" |
| 14345 | /* 40715 */ "VSUBhd\000" |
| 14346 | /* 40722 */ "VABDhd\000" |
| 14347 | /* 40729 */ "VADDhd\000" |
| 14348 | /* 40736 */ "VACGEhd\000" |
| 14349 | /* 40744 */ "VCGEhd\000" |
| 14350 | /* 40751 */ "VRECPEhd\000" |
| 14351 | /* 40760 */ "VRSQRTEhd\000" |
| 14352 | /* 40770 */ "VNEGhd\000" |
| 14353 | /* 40777 */ "VMULhd\000" |
| 14354 | /* 40784 */ "VMINhd\000" |
| 14355 | /* 40791 */ "VCEQhd\000" |
| 14356 | /* 40798 */ "VABShd\000" |
| 14357 | /* 40805 */ "VMLShd\000" |
| 14358 | /* 40812 */ "VFMShd\000" |
| 14359 | /* 40819 */ "VRECPShd\000" |
| 14360 | /* 40828 */ "VRSQRTShd\000" |
| 14361 | /* 40838 */ "VACGThd\000" |
| 14362 | /* 40846 */ "VCGThd\000" |
| 14363 | /* 40853 */ "VMAXhd\000" |
| 14364 | /* 40860 */ "VMLAslhd\000" |
| 14365 | /* 40869 */ "VMULslhd\000" |
| 14366 | /* 40878 */ "VMLSslhd\000" |
| 14367 | /* 40887 */ "SEH_EpilogEnd\000" |
| 14368 | /* 40901 */ "SEH_PrologEnd\000" |
| 14369 | /* 40915 */ "t2LoopEnd\000" |
| 14370 | /* 40925 */ "VMULpd\000" |
| 14371 | /* 40932 */ "VCVTf2sd\000" |
| 14372 | /* 40941 */ "VCVTh2sd\000" |
| 14373 | /* 40950 */ "VCVTf2xsd\000" |
| 14374 | /* 40960 */ "VCVTh2xsd\000" |
| 14375 | /* 40970 */ "VCVTf2ud\000" |
| 14376 | /* 40979 */ "VCVTh2ud\000" |
| 14377 | /* 40988 */ "VCVTf2xud\000" |
| 14378 | /* 40998 */ "VCVTh2xud\000" |
| 14379 | /* 41008 */ "tADDframe\000" |
| 14380 | /* 41018 */ "MQQPRStore\000" |
| 14381 | /* 41029 */ "MQQQQPRStore\000" |
| 14382 | /* 41042 */ "VLDR_P0_pre\000" |
| 14383 | /* 41054 */ "VSTR_P0_pre\000" |
| 14384 | /* 41066 */ "MVE_VSTRB32_pre\000" |
| 14385 | /* 41082 */ "MVE_VSTRH32_pre\000" |
| 14386 | /* 41098 */ "MVE_VLDRBS32_pre\000" |
| 14387 | /* 41115 */ "MVE_VLDRHS32_pre\000" |
| 14388 | /* 41132 */ "MVE_VLDRBU32_pre\000" |
| 14389 | /* 41149 */ "MVE_VLDRHU32_pre\000" |
| 14390 | /* 41166 */ "MVE_VLDRWU32_pre\000" |
| 14391 | /* 41183 */ "MVE_VSTRWU32_pre\000" |
| 14392 | /* 41200 */ "MVE_VSTRB16_pre\000" |
| 14393 | /* 41216 */ "MVE_VLDRBS16_pre\000" |
| 14394 | /* 41233 */ "MVE_VLDRBU16_pre\000" |
| 14395 | /* 41250 */ "MVE_VLDRHU16_pre\000" |
| 14396 | /* 41267 */ "MVE_VSTRHU16_pre\000" |
| 14397 | /* 41284 */ "MVE_VLDRBU8_pre\000" |
| 14398 | /* 41300 */ "MVE_VSTRBU8_pre\000" |
| 14399 | /* 41316 */ "VLDR_FPSCR_NZCVQC_pre\000" |
| 14400 | /* 41338 */ "VSTR_FPSCR_NZCVQC_pre\000" |
| 14401 | /* 41360 */ "VLDR_FPSCR_pre\000" |
| 14402 | /* 41375 */ "VSTR_FPSCR_pre\000" |
| 14403 | /* 41390 */ "VLDR_VPR_pre\000" |
| 14404 | /* 41403 */ "VSTR_VPR_pre\000" |
| 14405 | /* 41416 */ "VLDR_FPCXTNS_pre\000" |
| 14406 | /* 41433 */ "VSTR_FPCXTNS_pre\000" |
| 14407 | /* 41450 */ "VLDR_FPCXTS_pre\000" |
| 14408 | /* 41466 */ "VSTR_FPCXTS_pre\000" |
| 14409 | /* 41482 */ "MVE_VLDRWU32_qi_pre\000" |
| 14410 | /* 41502 */ "MVE_VSTRW32_qi_pre\000" |
| 14411 | /* 41521 */ "MVE_VSTRD64_qi_pre\000" |
| 14412 | /* 41540 */ "MVE_VLDRDU64_qi_pre\000" |
| 14413 | /* 41560 */ "t2LEUpdate\000" |
| 14414 | /* 41571 */ "VCVTh2f\000" |
| 14415 | /* 41579 */ "VPADDf\000" |
| 14416 | /* 41586 */ "VRINTANDf\000" |
| 14417 | /* 41596 */ "NEON_VMINNMNDf\000" |
| 14418 | /* 41611 */ "NEON_VMAXNMNDf\000" |
| 14419 | /* 41626 */ "VRINTMNDf\000" |
| 14420 | /* 41636 */ "VRINTNNDf\000" |
| 14421 | /* 41646 */ "VRINTPNDf\000" |
| 14422 | /* 41656 */ "VRINTXNDf\000" |
| 14423 | /* 41666 */ "VRINTZNDf\000" |
| 14424 | /* 41676 */ "VCVTANSDf\000" |
| 14425 | /* 41686 */ "VCVTMNSDf\000" |
| 14426 | /* 41696 */ "VCVTNNSDf\000" |
| 14427 | /* 41706 */ "VCVTPNSDf\000" |
| 14428 | /* 41716 */ "VCVTANUDf\000" |
| 14429 | /* 41726 */ "VCVTMNUDf\000" |
| 14430 | /* 41736 */ "VCVTNNUDf\000" |
| 14431 | /* 41746 */ "VCVTPNUDf\000" |
| 14432 | /* 41756 */ "VPMINf\000" |
| 14433 | /* 41763 */ "VRINTANQf\000" |
| 14434 | /* 41773 */ "NEON_VMINNMNQf\000" |
| 14435 | /* 41788 */ "NEON_VMAXNMNQf\000" |
| 14436 | /* 41803 */ "VRINTMNQf\000" |
| 14437 | /* 41813 */ "VRINTNNQf\000" |
| 14438 | /* 41823 */ "VRINTPNQf\000" |
| 14439 | /* 41833 */ "VRINTXNQf\000" |
| 14440 | /* 41843 */ "VRINTZNQf\000" |
| 14441 | /* 41853 */ "VCVTANSQf\000" |
| 14442 | /* 41863 */ "VCVTMNSQf\000" |
| 14443 | /* 41873 */ "VCVTNNSQf\000" |
| 14444 | /* 41883 */ "VCVTPNSQf\000" |
| 14445 | /* 41893 */ "VCVTANUQf\000" |
| 14446 | /* 41903 */ "VCVTMNUQf\000" |
| 14447 | /* 41913 */ "VCVTNNUQf\000" |
| 14448 | /* 41923 */ "VCVTPNUQf\000" |
| 14449 | /* 41933 */ "VPMAXf\000" |
| 14450 | /* 41940 */ "VLDR_P0_off\000" |
| 14451 | /* 41952 */ "VSTR_P0_off\000" |
| 14452 | /* 41964 */ "VLDR_FPSCR_NZCVQC_off\000" |
| 14453 | /* 41986 */ "VSTR_FPSCR_NZCVQC_off\000" |
| 14454 | /* 42008 */ "VLDR_FPSCR_off\000" |
| 14455 | /* 42023 */ "VSTR_FPSCR_off\000" |
| 14456 | /* 42038 */ "VLDR_VPR_off\000" |
| 14457 | /* 42051 */ "VSTR_VPR_off\000" |
| 14458 | /* 42064 */ "VLDR_FPCXTNS_off\000" |
| 14459 | /* 42081 */ "VSTR_FPCXTNS_off\000" |
| 14460 | /* 42098 */ "VLDR_FPCXTS_off\000" |
| 14461 | /* 42114 */ "VSTR_FPCXTS_off\000" |
| 14462 | /* 42130 */ "tBX_RET_vararg\000" |
| 14463 | /* 42145 */ "VCVTf2h\000" |
| 14464 | /* 42153 */ "VPADDh\000" |
| 14465 | /* 42160 */ "VRINTANDh\000" |
| 14466 | /* 42170 */ "NEON_VMINNMNDh\000" |
| 14467 | /* 42185 */ "NEON_VMAXNMNDh\000" |
| 14468 | /* 42200 */ "VRINTMNDh\000" |
| 14469 | /* 42210 */ "VRINTNNDh\000" |
| 14470 | /* 42220 */ "VRINTPNDh\000" |
| 14471 | /* 42230 */ "VRINTXNDh\000" |
| 14472 | /* 42240 */ "VRINTZNDh\000" |
| 14473 | /* 42250 */ "VCVTANSDh\000" |
| 14474 | /* 42260 */ "VCVTMNSDh\000" |
| 14475 | /* 42270 */ "VCVTNNSDh\000" |
| 14476 | /* 42280 */ "VCVTPNSDh\000" |
| 14477 | /* 42290 */ "VCVTANUDh\000" |
| 14478 | /* 42300 */ "VCVTMNUDh\000" |
| 14479 | /* 42310 */ "VCVTNNUDh\000" |
| 14480 | /* 42320 */ "VCVTPNUDh\000" |
| 14481 | /* 42330 */ "VPMINh\000" |
| 14482 | /* 42337 */ "VRINTANQh\000" |
| 14483 | /* 42347 */ "NEON_VMINNMNQh\000" |
| 14484 | /* 42362 */ "NEON_VMAXNMNQh\000" |
| 14485 | /* 42377 */ "VRINTMNQh\000" |
| 14486 | /* 42387 */ "VRINTNNQh\000" |
| 14487 | /* 42397 */ "VRINTPNQh\000" |
| 14488 | /* 42407 */ "VRINTXNQh\000" |
| 14489 | /* 42417 */ "VRINTZNQh\000" |
| 14490 | /* 42427 */ "VCVTANSQh\000" |
| 14491 | /* 42437 */ "VCVTMNSQh\000" |
| 14492 | /* 42447 */ "VCVTNNSQh\000" |
| 14493 | /* 42457 */ "VCVTPNSQh\000" |
| 14494 | /* 42467 */ "VCVTANUQh\000" |
| 14495 | /* 42477 */ "VCVTMNUQh\000" |
| 14496 | /* 42487 */ "VCVTNNUQh\000" |
| 14497 | /* 42497 */ "VCVTPNUQh\000" |
| 14498 | /* 42507 */ "VPMAXh\000" |
| 14499 | /* 42514 */ "MVE_VCVTf16f32bh\000" |
| 14500 | /* 42531 */ "MVE_VRSHRNi32bh\000" |
| 14501 | /* 42547 */ "MVE_VSHRNi32bh\000" |
| 14502 | /* 42562 */ "MVE_VMOVNi32bh\000" |
| 14503 | /* 42577 */ "MVE_VQDMULLs32bh\000" |
| 14504 | /* 42594 */ "MVE_VQSHRUNs32bh\000" |
| 14505 | /* 42611 */ "MVE_VQRSHRUNs32bh\000" |
| 14506 | /* 42629 */ "MVE_VQMOVUNs32bh\000" |
| 14507 | /* 42646 */ "MVE_VQMOVNs32bh\000" |
| 14508 | /* 42662 */ "MVE_VQDMULL_qr_s32bh\000" |
| 14509 | /* 42683 */ "MVE_VQMOVNu32bh\000" |
| 14510 | /* 42699 */ "MVE_VCVTf32f16bh\000" |
| 14511 | /* 42716 */ "MVE_VRSHRNi16bh\000" |
| 14512 | /* 42732 */ "MVE_VSHRNi16bh\000" |
| 14513 | /* 42747 */ "MVE_VMOVNi16bh\000" |
| 14514 | /* 42762 */ "MVE_VQDMULLs16bh\000" |
| 14515 | /* 42779 */ "MVE_VMOVLs16bh\000" |
| 14516 | /* 42794 */ "MVE_VQSHRUNs16bh\000" |
| 14517 | /* 42811 */ "MVE_VQRSHRUNs16bh\000" |
| 14518 | /* 42829 */ "MVE_VQMOVUNs16bh\000" |
| 14519 | /* 42846 */ "MVE_VQMOVNs16bh\000" |
| 14520 | /* 42862 */ "MVE_VQDMULL_qr_s16bh\000" |
| 14521 | /* 42883 */ "MVE_VSHLL_imms16bh\000" |
| 14522 | /* 42902 */ "MVE_VSHLL_lws16bh\000" |
| 14523 | /* 42920 */ "MVE_VMOVLu16bh\000" |
| 14524 | /* 42935 */ "MVE_VQMOVNu16bh\000" |
| 14525 | /* 42951 */ "MVE_VSHLL_immu16bh\000" |
| 14526 | /* 42970 */ "MVE_VSHLL_lwu16bh\000" |
| 14527 | /* 42988 */ "MVE_VMOVLs8bh\000" |
| 14528 | /* 43002 */ "MVE_VSHLL_imms8bh\000" |
| 14529 | /* 43020 */ "MVE_VSHLL_lws8bh\000" |
| 14530 | /* 43037 */ "MVE_VMOVLu8bh\000" |
| 14531 | /* 43051 */ "MVE_VSHLL_immu8bh\000" |
| 14532 | /* 43069 */ "MVE_VSHLL_lwu8bh\000" |
| 14533 | /* 43086 */ "Int_eh_sjlj_setup_dispatch\000" |
| 14534 | /* 43113 */ "MVE_VCVTf16f32th\000" |
| 14535 | /* 43130 */ "MVE_VRSHRNi32th\000" |
| 14536 | /* 43146 */ "MVE_VSHRNi32th\000" |
| 14537 | /* 43161 */ "MVE_VMOVNi32th\000" |
| 14538 | /* 43176 */ "MVE_VQDMULLs32th\000" |
| 14539 | /* 43193 */ "MVE_VQSHRUNs32th\000" |
| 14540 | /* 43210 */ "MVE_VQRSHRUNs32th\000" |
| 14541 | /* 43228 */ "MVE_VQMOVUNs32th\000" |
| 14542 | /* 43245 */ "MVE_VQMOVNs32th\000" |
| 14543 | /* 43261 */ "MVE_VQDMULL_qr_s32th\000" |
| 14544 | /* 43282 */ "MVE_VQMOVNu32th\000" |
| 14545 | /* 43298 */ "MVE_VCVTf32f16th\000" |
| 14546 | /* 43315 */ "MVE_VRSHRNi16th\000" |
| 14547 | /* 43331 */ "MVE_VSHRNi16th\000" |
| 14548 | /* 43346 */ "MVE_VMOVNi16th\000" |
| 14549 | /* 43361 */ "MVE_VQDMULLs16th\000" |
| 14550 | /* 43378 */ "MVE_VMOVLs16th\000" |
| 14551 | /* 43393 */ "MVE_VQSHRUNs16th\000" |
| 14552 | /* 43410 */ "MVE_VQRSHRUNs16th\000" |
| 14553 | /* 43428 */ "MVE_VQMOVUNs16th\000" |
| 14554 | /* 43445 */ "MVE_VQMOVNs16th\000" |
| 14555 | /* 43461 */ "MVE_VQDMULL_qr_s16th\000" |
| 14556 | /* 43482 */ "MVE_VSHLL_imms16th\000" |
| 14557 | /* 43501 */ "MVE_VSHLL_lws16th\000" |
| 14558 | /* 43519 */ "MVE_VMOVLu16th\000" |
| 14559 | /* 43534 */ "MVE_VQMOVNu16th\000" |
| 14560 | /* 43550 */ "MVE_VSHLL_immu16th\000" |
| 14561 | /* 43569 */ "MVE_VSHLL_lwu16th\000" |
| 14562 | /* 43587 */ "MVE_VMOVLs8th\000" |
| 14563 | /* 43601 */ "MVE_VSHLL_imms8th\000" |
| 14564 | /* 43619 */ "MVE_VSHLL_lws8th\000" |
| 14565 | /* 43636 */ "MVE_VMOVLu8th\000" |
| 14566 | /* 43650 */ "MVE_VSHLL_immu8th\000" |
| 14567 | /* 43668 */ "MVE_VSHLL_lwu8th\000" |
| 14568 | /* 43685 */ "tLDRBi\000" |
| 14569 | /* 43692 */ "tSTRBi\000" |
| 14570 | /* 43699 */ "t2MVNCCi\000" |
| 14571 | /* 43708 */ "t2MOVCCi\000" |
| 14572 | /* 43717 */ "t2BFi\000" |
| 14573 | /* 43723 */ "tLDRHi\000" |
| 14574 | /* 43730 */ "tSTRHi\000" |
| 14575 | /* 43737 */ "t2BFLi\000" |
| 14576 | /* 43744 */ "MVE_LSLLi\000" |
| 14577 | /* 43754 */ "MVE_ASRLi\000" |
| 14578 | /* 43764 */ "LSLi\000" |
| 14579 | /* 43769 */ "t2MVNi\000" |
| 14580 | /* 43776 */ "tADDrSPi\000" |
| 14581 | /* 43785 */ "tLDRi\000" |
| 14582 | /* 43791 */ "RORi\000" |
| 14583 | /* 43796 */ "ASRi\000" |
| 14584 | /* 43801 */ "LSRi\000" |
| 14585 | /* 43806 */ "MSRi\000" |
| 14586 | /* 43811 */ "tSTRi\000" |
| 14587 | /* 43817 */ "LDRSBTi\000" |
| 14588 | /* 43825 */ "LDRHTi\000" |
| 14589 | /* 43832 */ "STRHTi\000" |
| 14590 | /* 43839 */ "LDRSHTi\000" |
| 14591 | /* 43847 */ "t2MOVi\000" |
| 14592 | /* 43854 */ "tBLXi\000" |
| 14593 | /* 43860 */ "RRXi\000" |
| 14594 | /* 43865 */ "t2LDRBpci\000" |
| 14595 | /* 43875 */ "t2LDRSBpci\000" |
| 14596 | /* 43886 */ "t2PLDpci\000" |
| 14597 | /* 43895 */ "t2LDRHpci\000" |
| 14598 | /* 43905 */ "t2LDRSHpci\000" |
| 14599 | /* 43916 */ "t2PLIpci\000" |
| 14600 | /* 43925 */ "t2LDRpci\000" |
| 14601 | /* 43934 */ "tLDRpci\000" |
| 14602 | /* 43942 */ "TCRETURNdi\000" |
| 14603 | /* 43953 */ "LDRSBTii\000" |
| 14604 | /* 43962 */ "LDRHTii\000" |
| 14605 | /* 43970 */ "LDRSHTii\000" |
| 14606 | /* 43979 */ "tSUBspi\000" |
| 14607 | /* 43987 */ "tADDspi\000" |
| 14608 | /* 43995 */ "tLDRspi\000" |
| 14609 | /* 44003 */ "tSTRspi\000" |
| 14610 | /* 44011 */ "MVE_VLDRWU32_qi\000" |
| 14611 | /* 44027 */ "MVE_VSTRW32_qi\000" |
| 14612 | /* 44042 */ "MVE_VSTRD64_qi\000" |
| 14613 | /* 44057 */ "MVE_VLDRDU64_qi\000" |
| 14614 | /* 44073 */ "t2RSBri\000" |
| 14615 | /* 44081 */ "t2SUBri\000" |
| 14616 | /* 44089 */ "t2SBCri\000" |
| 14617 | /* 44097 */ "t2ADCri\000" |
| 14618 | /* 44105 */ "t2BICri\000" |
| 14619 | /* 44113 */ "RSCri\000" |
| 14620 | /* 44119 */ "t2ADDri\000" |
| 14621 | /* 44127 */ "t2ANDri\000" |
| 14622 | /* 44135 */ "t2LSLri\000" |
| 14623 | /* 44143 */ "tLSLri\000" |
| 14624 | /* 44150 */ "t2CMNri\000" |
| 14625 | /* 44158 */ "t2ORNri\000" |
| 14626 | /* 44166 */ "TCRETURNri\000" |
| 14627 | /* 44177 */ "t2CMPri\000" |
| 14628 | /* 44185 */ "t2TEQri\000" |
| 14629 | /* 44193 */ "t2EORri\000" |
| 14630 | /* 44201 */ "t2RORri\000" |
| 14631 | /* 44209 */ "t2ORRri\000" |
| 14632 | /* 44217 */ "t2ASRri\000" |
| 14633 | /* 44225 */ "tASRri\000" |
| 14634 | /* 44232 */ "t2LSRri\000" |
| 14635 | /* 44240 */ "tLSRri\000" |
| 14636 | /* 44247 */ "t2RSBSri\000" |
| 14637 | /* 44256 */ "t2SUBSri\000" |
| 14638 | /* 44265 */ "t2ADDSri\000" |
| 14639 | /* 44274 */ "tLSLSri\000" |
| 14640 | /* 44282 */ "t2TSTri\000" |
| 14641 | /* 44290 */ "MOVCCsi\000" |
| 14642 | /* 44298 */ "MVNsi\000" |
| 14643 | /* 44304 */ "t2MOVSsi\000" |
| 14644 | /* 44313 */ "t2MOVsi\000" |
| 14645 | /* 44321 */ "RSBrsi\000" |
| 14646 | /* 44328 */ "SUBrsi\000" |
| 14647 | /* 44335 */ "SBCrsi\000" |
| 14648 | /* 44342 */ "ADCrsi\000" |
| 14649 | /* 44349 */ "BICrsi\000" |
| 14650 | /* 44356 */ "RSCrsi\000" |
| 14651 | /* 44363 */ "ADDrsi\000" |
| 14652 | /* 44370 */ "ANDrsi\000" |
| 14653 | /* 44377 */ "CMNrsi\000" |
| 14654 | /* 44384 */ "CMPrsi\000" |
| 14655 | /* 44391 */ "TEQrsi\000" |
| 14656 | /* 44398 */ "EORrsi\000" |
| 14657 | /* 44405 */ "ORRrsi\000" |
| 14658 | /* 44412 */ "RSBSrsi\000" |
| 14659 | /* 44420 */ "SUBSrsi\000" |
| 14660 | /* 44428 */ "ADDSrsi\000" |
| 14661 | /* 44436 */ "TSTrsi\000" |
| 14662 | /* 44443 */ "t2LEApcrel\000" |
| 14663 | /* 44454 */ "tLEApcrel\000" |
| 14664 | /* 44464 */ "t2LDRBpcrel\000" |
| 14665 | /* 44476 */ "t2LDRSBpcrel\000" |
| 14666 | /* 44489 */ "t2LDRHpcrel\000" |
| 14667 | /* 44501 */ "t2LDRSHpcrel\000" |
| 14668 | /* 44514 */ "t2LDRpcrel\000" |
| 14669 | /* 44525 */ "t2MOVTi16_ga_pcrel\000" |
| 14670 | /* 44544 */ "t2MOVi16_ga_pcrel\000" |
| 14671 | /* 44562 */ "t2LDRLIT_ga_pcrel\000" |
| 14672 | /* 44580 */ "tLDRLIT_ga_pcrel\000" |
| 14673 | /* 44597 */ "t2MOV_ga_pcrel\000" |
| 14674 | /* 44612 */ "t2LDRConstPool\000" |
| 14675 | /* 44627 */ "tLDRConstPool\000" |
| 14676 | /* 44641 */ "t2MOVCClsl\000" |
| 14677 | /* 44652 */ "MVE_VCVTs32f32m\000" |
| 14678 | /* 44668 */ "MVE_VCVTu32f32m\000" |
| 14679 | /* 44684 */ "MVE_VCVTs16f16m\000" |
| 14680 | /* 44700 */ "MVE_VCVTu16f16m\000" |
| 14681 | /* 44716 */ "t2SUBspImm\000" |
| 14682 | /* 44727 */ "t2ADDspImm\000" |
| 14683 | /* 44738 */ "t2MOVCCi32imm\000" |
| 14684 | /* 44752 */ "t2MOVi32imm\000" |
| 14685 | /* 44764 */ "tMOVi32imm\000" |
| 14686 | /* 44775 */ "t2LDRB_PRE_imm\000" |
| 14687 | /* 44790 */ "t2STRB_PRE_imm\000" |
| 14688 | /* 44805 */ "t2LDRSB_PRE_imm\000" |
| 14689 | /* 44821 */ "t2LDRH_PRE_imm\000" |
| 14690 | /* 44836 */ "t2STRH_PRE_imm\000" |
| 14691 | /* 44851 */ "t2LDRSH_PRE_imm\000" |
| 14692 | /* 44867 */ "t2LDR_PRE_imm\000" |
| 14693 | /* 44881 */ "t2STR_PRE_imm\000" |
| 14694 | /* 44895 */ "t2LDRB_OFFSET_imm\000" |
| 14695 | /* 44913 */ "t2STRB_OFFSET_imm\000" |
| 14696 | /* 44931 */ "t2LDRSB_OFFSET_imm\000" |
| 14697 | /* 44950 */ "t2LDRH_OFFSET_imm\000" |
| 14698 | /* 44968 */ "t2STRH_OFFSET_imm\000" |
| 14699 | /* 44986 */ "t2LDRSH_OFFSET_imm\000" |
| 14700 | /* 45005 */ "t2LDRB_POST_imm\000" |
| 14701 | /* 45021 */ "t2STRB_POST_imm\000" |
| 14702 | /* 45037 */ "t2LDRSB_POST_imm\000" |
| 14703 | /* 45054 */ "t2LDRH_POST_imm\000" |
| 14704 | /* 45070 */ "t2STRH_POST_imm\000" |
| 14705 | /* 45086 */ "t2LDRSH_POST_imm\000" |
| 14706 | /* 45103 */ "t2LDR_POST_imm\000" |
| 14707 | /* 45118 */ "t2STR_POST_imm\000" |
| 14708 | /* 45133 */ "ITasm\000" |
| 14709 | /* 45139 */ "MVE_VCVTs32f32n\000" |
| 14710 | /* 45155 */ "MVE_VCVTu32f32n\000" |
| 14711 | /* 45171 */ "MVE_VCVTf32s32n\000" |
| 14712 | /* 45187 */ "MVE_VCVTf32u32n\000" |
| 14713 | /* 45203 */ "MVE_VCVTs16f16n\000" |
| 14714 | /* 45219 */ "MVE_VCVTu16f16n\000" |
| 14715 | /* 45235 */ "MVE_VCVTf16s16n\000" |
| 14716 | /* 45251 */ "MVE_VCVTf16u16n\000" |
| 14717 | /* 45267 */ "VLD3d32Pseudo\000" |
| 14718 | /* 45281 */ "VST3d32Pseudo\000" |
| 14719 | /* 45295 */ "VLD4d32Pseudo\000" |
| 14720 | /* 45309 */ "VST4d32Pseudo\000" |
| 14721 | /* 45323 */ "VLD2LNd32Pseudo\000" |
| 14722 | /* 45339 */ "VST2LNd32Pseudo\000" |
| 14723 | /* 45355 */ "VLD3LNd32Pseudo\000" |
| 14724 | /* 45371 */ "VST3LNd32Pseudo\000" |
| 14725 | /* 45387 */ "VLD4LNd32Pseudo\000" |
| 14726 | /* 45403 */ "VST4LNd32Pseudo\000" |
| 14727 | /* 45419 */ "VLD3DUPd32Pseudo\000" |
| 14728 | /* 45436 */ "VLD4DUPd32Pseudo\000" |
| 14729 | /* 45453 */ "VLD2q32Pseudo\000" |
| 14730 | /* 45467 */ "VST2q32Pseudo\000" |
| 14731 | /* 45481 */ "VLD1LNq32Pseudo\000" |
| 14732 | /* 45497 */ "VST1LNq32Pseudo\000" |
| 14733 | /* 45513 */ "VLD2LNq32Pseudo\000" |
| 14734 | /* 45529 */ "VST2LNq32Pseudo\000" |
| 14735 | /* 45545 */ "VLD3LNq32Pseudo\000" |
| 14736 | /* 45561 */ "VST3LNq32Pseudo\000" |
| 14737 | /* 45577 */ "VLD4LNq32Pseudo\000" |
| 14738 | /* 45593 */ "VST4LNq32Pseudo\000" |
| 14739 | /* 45609 */ "VTBL3Pseudo\000" |
| 14740 | /* 45621 */ "VTBX3Pseudo\000" |
| 14741 | /* 45633 */ "VTBL4Pseudo\000" |
| 14742 | /* 45645 */ "VTBX4Pseudo\000" |
| 14743 | /* 45657 */ "VLD3d16Pseudo\000" |
| 14744 | /* 45671 */ "VST3d16Pseudo\000" |
| 14745 | /* 45685 */ "VLD4d16Pseudo\000" |
| 14746 | /* 45699 */ "VST4d16Pseudo\000" |
| 14747 | /* 45713 */ "VLD2LNd16Pseudo\000" |
| 14748 | /* 45729 */ "VST2LNd16Pseudo\000" |
| 14749 | /* 45745 */ "VLD3LNd16Pseudo\000" |
| 14750 | /* 45761 */ "VST3LNd16Pseudo\000" |
| 14751 | /* 45777 */ "VLD4LNd16Pseudo\000" |
| 14752 | /* 45793 */ "VST4LNd16Pseudo\000" |
| 14753 | /* 45809 */ "VLD3DUPd16Pseudo\000" |
| 14754 | /* 45826 */ "VLD4DUPd16Pseudo\000" |
| 14755 | /* 45843 */ "VLD2q16Pseudo\000" |
| 14756 | /* 45857 */ "VST2q16Pseudo\000" |
| 14757 | /* 45871 */ "VLD1LNq16Pseudo\000" |
| 14758 | /* 45887 */ "VST1LNq16Pseudo\000" |
| 14759 | /* 45903 */ "VLD2LNq16Pseudo\000" |
| 14760 | /* 45919 */ "VST2LNq16Pseudo\000" |
| 14761 | /* 45935 */ "VLD3LNq16Pseudo\000" |
| 14762 | /* 45951 */ "VST3LNq16Pseudo\000" |
| 14763 | /* 45967 */ "VLD4LNq16Pseudo\000" |
| 14764 | /* 45983 */ "VST4LNq16Pseudo\000" |
| 14765 | /* 45999 */ "VLD3d8Pseudo\000" |
| 14766 | /* 46012 */ "VST3d8Pseudo\000" |
| 14767 | /* 46025 */ "VLD4d8Pseudo\000" |
| 14768 | /* 46038 */ "VST4d8Pseudo\000" |
| 14769 | /* 46051 */ "VLD2LNd8Pseudo\000" |
| 14770 | /* 46066 */ "VST2LNd8Pseudo\000" |
| 14771 | /* 46081 */ "VLD3LNd8Pseudo\000" |
| 14772 | /* 46096 */ "VST3LNd8Pseudo\000" |
| 14773 | /* 46111 */ "VLD4LNd8Pseudo\000" |
| 14774 | /* 46126 */ "VST4LNd8Pseudo\000" |
| 14775 | /* 46141 */ "VLD3DUPd8Pseudo\000" |
| 14776 | /* 46157 */ "VLD4DUPd8Pseudo\000" |
| 14777 | /* 46173 */ "VLD2q8Pseudo\000" |
| 14778 | /* 46186 */ "VST2q8Pseudo\000" |
| 14779 | /* 46199 */ "VLD1LNq8Pseudo\000" |
| 14780 | /* 46214 */ "VST1LNq8Pseudo\000" |
| 14781 | /* 46229 */ "VLD1d32QPseudo\000" |
| 14782 | /* 46244 */ "VST1d32QPseudo\000" |
| 14783 | /* 46259 */ "VLD1d64QPseudo\000" |
| 14784 | /* 46274 */ "VST1d64QPseudo\000" |
| 14785 | /* 46289 */ "VLD1d16QPseudo\000" |
| 14786 | /* 46304 */ "VST1d16QPseudo\000" |
| 14787 | /* 46319 */ "VLD1d8QPseudo\000" |
| 14788 | /* 46333 */ "VST1d8QPseudo\000" |
| 14789 | /* 46347 */ "VLD1q32HighQPseudo\000" |
| 14790 | /* 46366 */ "VST1q32HighQPseudo\000" |
| 14791 | /* 46385 */ "VLD1q64HighQPseudo\000" |
| 14792 | /* 46404 */ "VST1q64HighQPseudo\000" |
| 14793 | /* 46423 */ "VLD1q16HighQPseudo\000" |
| 14794 | /* 46442 */ "VST1q16HighQPseudo\000" |
| 14795 | /* 46461 */ "VLD1q8HighQPseudo\000" |
| 14796 | /* 46479 */ "VST1q8HighQPseudo\000" |
| 14797 | /* 46497 */ "VLD1d32TPseudo\000" |
| 14798 | /* 46512 */ "VST1d32TPseudo\000" |
| 14799 | /* 46527 */ "VLD1d64TPseudo\000" |
| 14800 | /* 46542 */ "VST1d64TPseudo\000" |
| 14801 | /* 46557 */ "VLD1d16TPseudo\000" |
| 14802 | /* 46572 */ "VST1d16TPseudo\000" |
| 14803 | /* 46587 */ "VLD1d8TPseudo\000" |
| 14804 | /* 46601 */ "VST1d8TPseudo\000" |
| 14805 | /* 46615 */ "VLD1q32HighTPseudo\000" |
| 14806 | /* 46634 */ "VST1q32HighTPseudo\000" |
| 14807 | /* 46653 */ "VLD1q64HighTPseudo\000" |
| 14808 | /* 46672 */ "VST1q64HighTPseudo\000" |
| 14809 | /* 46691 */ "VLD1q16HighTPseudo\000" |
| 14810 | /* 46710 */ "VST1q16HighTPseudo\000" |
| 14811 | /* 46729 */ "VLD1q8HighTPseudo\000" |
| 14812 | /* 46747 */ "VST1q8HighTPseudo\000" |
| 14813 | /* 46765 */ "VLD2DUPq32OddPseudo\000" |
| 14814 | /* 46785 */ "VLD3DUPq32OddPseudo\000" |
| 14815 | /* 46805 */ "VLD4DUPq32OddPseudo\000" |
| 14816 | /* 46825 */ "VLD2DUPq16OddPseudo\000" |
| 14817 | /* 46845 */ "VLD3DUPq16OddPseudo\000" |
| 14818 | /* 46865 */ "VLD4DUPq16OddPseudo\000" |
| 14819 | /* 46885 */ "VLD2DUPq8OddPseudo\000" |
| 14820 | /* 46904 */ "VLD3DUPq8OddPseudo\000" |
| 14821 | /* 46923 */ "VLD4DUPq8OddPseudo\000" |
| 14822 | /* 46942 */ "VLD3q32oddPseudo\000" |
| 14823 | /* 46959 */ "VST3q32oddPseudo\000" |
| 14824 | /* 46976 */ "VLD4q32oddPseudo\000" |
| 14825 | /* 46993 */ "VST4q32oddPseudo\000" |
| 14826 | /* 47010 */ "VLD3q16oddPseudo\000" |
| 14827 | /* 47027 */ "VST3q16oddPseudo\000" |
| 14828 | /* 47044 */ "VLD4q16oddPseudo\000" |
| 14829 | /* 47061 */ "VST4q16oddPseudo\000" |
| 14830 | /* 47078 */ "VLD3q8oddPseudo\000" |
| 14831 | /* 47094 */ "VST3q8oddPseudo\000" |
| 14832 | /* 47110 */ "VLD4q8oddPseudo\000" |
| 14833 | /* 47126 */ "VST4q8oddPseudo\000" |
| 14834 | /* 47142 */ "t2BF_LabelPseudo\000" |
| 14835 | /* 47159 */ "VLD2DUPq32EvenPseudo\000" |
| 14836 | /* 47180 */ "VLD3DUPq32EvenPseudo\000" |
| 14837 | /* 47201 */ "VLD4DUPq32EvenPseudo\000" |
| 14838 | /* 47222 */ "VLD2DUPq16EvenPseudo\000" |
| 14839 | /* 47243 */ "VLD3DUPq16EvenPseudo\000" |
| 14840 | /* 47264 */ "VLD4DUPq16EvenPseudo\000" |
| 14841 | /* 47285 */ "VLD2DUPq8EvenPseudo\000" |
| 14842 | /* 47305 */ "VLD3DUPq8EvenPseudo\000" |
| 14843 | /* 47325 */ "VLD4DUPq8EvenPseudo\000" |
| 14844 | /* 47345 */ "tMOVCCr_pseudo\000" |
| 14845 | /* 47360 */ "t2CPS1p\000" |
| 14846 | /* 47368 */ "MVE_VCVTs32f32p\000" |
| 14847 | /* 47384 */ "MVE_VCVTu32f32p\000" |
| 14848 | /* 47400 */ "t2CPS2p\000" |
| 14849 | /* 47408 */ "t2CPS3p\000" |
| 14850 | /* 47416 */ "MVE_VCVTs16f16p\000" |
| 14851 | /* 47432 */ "MVE_VCVTu16f16p\000" |
| 14852 | /* 47448 */ "LDRcp\000" |
| 14853 | /* 47454 */ "CDE_VCX1_fpdp\000" |
| 14854 | /* 47468 */ "CDE_VCX2_fpdp\000" |
| 14855 | /* 47482 */ "CDE_VCX3_fpdp\000" |
| 14856 | /* 47496 */ "CDE_VCX1A_fpdp\000" |
| 14857 | /* 47511 */ "CDE_VCX2A_fpdp\000" |
| 14858 | /* 47526 */ "CDE_VCX3A_fpdp\000" |
| 14859 | /* 47541 */ "t2Int_eh_sjlj_setjmp_nofp\000" |
| 14860 | /* 47567 */ "BLX_noip\000" |
| 14861 | /* 47576 */ "BLX_pred_noip\000" |
| 14862 | /* 47590 */ "tBLXr_noip\000" |
| 14863 | /* 47601 */ "tInt_WIN_eh_sjlj_longjmp\000" |
| 14864 | /* 47626 */ "tInt_eh_sjlj_longjmp\000" |
| 14865 | /* 47647 */ "t2Int_eh_sjlj_setjmp\000" |
| 14866 | /* 47668 */ "tInt_eh_sjlj_setjmp\000" |
| 14867 | /* 47688 */ "SEH_Nop\000" |
| 14868 | /* 47696 */ "CDE_VCX1_fpsp\000" |
| 14869 | /* 47710 */ "CDE_VCX2_fpsp\000" |
| 14870 | /* 47724 */ "CDE_VCX3_fpsp\000" |
| 14871 | /* 47738 */ "CDE_VCX1A_fpsp\000" |
| 14872 | /* 47753 */ "CDE_VCX2A_fpsp\000" |
| 14873 | /* 47768 */ "CDE_VCX3A_fpsp\000" |
| 14874 | /* 47783 */ "t2WhileLoopSetup\000" |
| 14875 | /* 47800 */ "Int_eh_sjlj_dispatchsetup\000" |
| 14876 | /* 47826 */ "VDUPLN32q\000" |
| 14877 | /* 47836 */ "VDUP32q\000" |
| 14878 | /* 47844 */ "VNEGf32q\000" |
| 14879 | /* 47853 */ "VNEGs32q\000" |
| 14880 | /* 47862 */ "VDUPLN16q\000" |
| 14881 | /* 47872 */ "VDUP16q\000" |
| 14882 | /* 47880 */ "VNEGs16q\000" |
| 14883 | /* 47889 */ "VDUPLN8q\000" |
| 14884 | /* 47898 */ "VDUP8q\000" |
| 14885 | /* 47905 */ "VNEGs8q\000" |
| 14886 | /* 47913 */ "VBICq\000" |
| 14887 | /* 47919 */ "VANDq\000" |
| 14888 | /* 47925 */ "VRECPEq\000" |
| 14889 | /* 47933 */ "VRSQRTEq\000" |
| 14890 | /* 47942 */ "VBIFq\000" |
| 14891 | /* 47948 */ "VBSLq\000" |
| 14892 | /* 47954 */ "VORNq\000" |
| 14893 | /* 47960 */ "VMVNq\000" |
| 14894 | /* 47966 */ "VBSPq\000" |
| 14895 | /* 47972 */ "VSWPq\000" |
| 14896 | /* 47978 */ "VEORq\000" |
| 14897 | /* 47984 */ "VORRq\000" |
| 14898 | /* 47990 */ "VBITq\000" |
| 14899 | /* 47996 */ "VCNTq\000" |
| 14900 | /* 48002 */ "MVE_VMOV_rr_q\000" |
| 14901 | /* 48016 */ "VCVTs2fq\000" |
| 14902 | /* 48025 */ "VCVTxs2fq\000" |
| 14903 | /* 48035 */ "VCVTu2fq\000" |
| 14904 | /* 48044 */ "VCVTxu2fq\000" |
| 14905 | /* 48054 */ "VMLAfq\000" |
| 14906 | /* 48061 */ "VFMAfq\000" |
| 14907 | /* 48068 */ "VSUBfq\000" |
| 14908 | /* 48075 */ "VABDfq\000" |
| 14909 | /* 48082 */ "VADDfq\000" |
| 14910 | /* 48089 */ "VACGEfq\000" |
| 14911 | /* 48097 */ "VCGEfq\000" |
| 14912 | /* 48104 */ "VRECPEfq\000" |
| 14913 | /* 48113 */ "VRSQRTEfq\000" |
| 14914 | /* 48123 */ "VMULfq\000" |
| 14915 | /* 48130 */ "VMINfq\000" |
| 14916 | /* 48137 */ "VCEQfq\000" |
| 14917 | /* 48144 */ "VABSfq\000" |
| 14918 | /* 48151 */ "VMLSfq\000" |
| 14919 | /* 48158 */ "VFMSfq\000" |
| 14920 | /* 48165 */ "VRECPSfq\000" |
| 14921 | /* 48174 */ "VRSQRTSfq\000" |
| 14922 | /* 48184 */ "VACGTfq\000" |
| 14923 | /* 48192 */ "VCGTfq\000" |
| 14924 | /* 48199 */ "VMAXfq\000" |
| 14925 | /* 48206 */ "VMLAslfq\000" |
| 14926 | /* 48215 */ "VMULslfq\000" |
| 14927 | /* 48224 */ "VMLSslfq\000" |
| 14928 | /* 48233 */ "VCVTs2hq\000" |
| 14929 | /* 48242 */ "VCVTxs2hq\000" |
| 14930 | /* 48252 */ "VCVTu2hq\000" |
| 14931 | /* 48261 */ "VCVTxu2hq\000" |
| 14932 | /* 48271 */ "VMLAhq\000" |
| 14933 | /* 48278 */ "VFMAhq\000" |
| 14934 | /* 48285 */ "VSUBhq\000" |
| 14935 | /* 48292 */ "VABDhq\000" |
| 14936 | /* 48299 */ "VADDhq\000" |
| 14937 | /* 48306 */ "VACGEhq\000" |
| 14938 | /* 48314 */ "VCGEhq\000" |
| 14939 | /* 48321 */ "VRECPEhq\000" |
| 14940 | /* 48330 */ "VRSQRTEhq\000" |
| 14941 | /* 48340 */ "VNEGhq\000" |
| 14942 | /* 48347 */ "VMULhq\000" |
| 14943 | /* 48354 */ "VMINhq\000" |
| 14944 | /* 48361 */ "VCEQhq\000" |
| 14945 | /* 48368 */ "VABShq\000" |
| 14946 | /* 48375 */ "VMLShq\000" |
| 14947 | /* 48382 */ "VFMShq\000" |
| 14948 | /* 48389 */ "VRECPShq\000" |
| 14949 | /* 48398 */ "VRSQRTShq\000" |
| 14950 | /* 48408 */ "VACGThq\000" |
| 14951 | /* 48416 */ "VCGThq\000" |
| 14952 | /* 48423 */ "VMAXhq\000" |
| 14953 | /* 48430 */ "VMLAslhq\000" |
| 14954 | /* 48439 */ "VMULslhq\000" |
| 14955 | /* 48448 */ "VMLSslhq\000" |
| 14956 | /* 48457 */ "VMULpq\000" |
| 14957 | /* 48464 */ "MVE_VSTRB32_rq\000" |
| 14958 | /* 48479 */ "MVE_VSTRH32_rq\000" |
| 14959 | /* 48494 */ "MVE_VLDRBS32_rq\000" |
| 14960 | /* 48510 */ "MVE_VLDRHS32_rq\000" |
| 14961 | /* 48526 */ "MVE_VLDRBU32_rq\000" |
| 14962 | /* 48542 */ "MVE_VLDRHU32_rq\000" |
| 14963 | /* 48558 */ "MVE_VLDRWU32_rq\000" |
| 14964 | /* 48574 */ "MVE_VSTRW32_rq\000" |
| 14965 | /* 48589 */ "MVE_VSTRD64_rq\000" |
| 14966 | /* 48604 */ "MVE_VLDRDU64_rq\000" |
| 14967 | /* 48620 */ "MVE_VSTRB16_rq\000" |
| 14968 | /* 48635 */ "MVE_VSTRH16_rq\000" |
| 14969 | /* 48650 */ "MVE_VLDRBS16_rq\000" |
| 14970 | /* 48666 */ "MVE_VLDRBU16_rq\000" |
| 14971 | /* 48682 */ "MVE_VLDRHU16_rq\000" |
| 14972 | /* 48698 */ "MVE_VSTRB8_rq\000" |
| 14973 | /* 48712 */ "MVE_VLDRBU8_rq\000" |
| 14974 | /* 48727 */ "VCVTf2sq\000" |
| 14975 | /* 48736 */ "VCVTh2sq\000" |
| 14976 | /* 48745 */ "VCVTf2xsq\000" |
| 14977 | /* 48755 */ "VCVTh2xsq\000" |
| 14978 | /* 48765 */ "VCVTf2uq\000" |
| 14979 | /* 48774 */ "VCVTh2uq\000" |
| 14980 | /* 48783 */ "VCVTf2xuq\000" |
| 14981 | /* 48793 */ "VCVTh2xuq\000" |
| 14982 | /* 48803 */ "MVE_VPTv4f32r\000" |
| 14983 | /* 48817 */ "MVE_VCMPf32r\000" |
| 14984 | /* 48830 */ "MVE_VPTv4i32r\000" |
| 14985 | /* 48844 */ "MVE_VCMPi32r\000" |
| 14986 | /* 48857 */ "MVE_VPTv4s32r\000" |
| 14987 | /* 48871 */ "MVE_VCMPs32r\000" |
| 14988 | /* 48884 */ "MVE_VPTv4u32r\000" |
| 14989 | /* 48898 */ "MVE_VCMPu32r\000" |
| 14990 | /* 48911 */ "MVE_VPTv8f16r\000" |
| 14991 | /* 48925 */ "MVE_VCMPf16r\000" |
| 14992 | /* 48938 */ "MVE_VPTv8i16r\000" |
| 14993 | /* 48952 */ "MVE_VCMPi16r\000" |
| 14994 | /* 48965 */ "MVE_VPTv8s16r\000" |
| 14995 | /* 48979 */ "MVE_VCMPs16r\000" |
| 14996 | /* 48992 */ "MVE_VPTv8u16r\000" |
| 14997 | /* 49006 */ "MVE_VCMPu16r\000" |
| 14998 | /* 49019 */ "MVE_VPTv16i8r\000" |
| 14999 | /* 49033 */ "MVE_VCMPi8r\000" |
| 15000 | /* 49045 */ "MVE_VPTv16s8r\000" |
| 15001 | /* 49059 */ "MVE_VCMPs8r\000" |
| 15002 | /* 49071 */ "MVE_VPTv16u8r\000" |
| 15003 | /* 49085 */ "MVE_VCMPu8r\000" |
| 15004 | /* 49097 */ "tLDRBr\000" |
| 15005 | /* 49104 */ "tSTRBr\000" |
| 15006 | /* 49111 */ "t2MOVCCr\000" |
| 15007 | /* 49120 */ "t2BFr\000" |
| 15008 | /* 49126 */ "tLDRHr\000" |
| 15009 | /* 49133 */ "tSTRHr\000" |
| 15010 | /* 49140 */ "t2BFLr\000" |
| 15011 | /* 49147 */ "MVE_LSLLr\000" |
| 15012 | /* 49157 */ "MVE_ASRLr\000" |
| 15013 | /* 49167 */ "LSLr\000" |
| 15014 | /* 49172 */ "t2MVNr\000" |
| 15015 | /* 49179 */ "tCMPr\000" |
| 15016 | /* 49185 */ "tTAILJMPr\000" |
| 15017 | /* 49195 */ "tLDRr\000" |
| 15018 | /* 49201 */ "RORr\000" |
| 15019 | /* 49206 */ "ASRr\000" |
| 15020 | /* 49211 */ "LSRr\000" |
| 15021 | /* 49216 */ "tSTRr\000" |
| 15022 | /* 49222 */ "tBLXNSr\000" |
| 15023 | /* 49230 */ "tMOVSr\000" |
| 15024 | /* 49237 */ "LDRSBTr\000" |
| 15025 | /* 49245 */ "LDRHTr\000" |
| 15026 | /* 49252 */ "STRHTr\000" |
| 15027 | /* 49259 */ "LDRSHTr\000" |
| 15028 | /* 49267 */ "tBR_JTr\000" |
| 15029 | /* 49275 */ "t2MOVr\000" |
| 15030 | /* 49282 */ "tMOVr\000" |
| 15031 | /* 49288 */ "tBLXr\000" |
| 15032 | /* 49294 */ "tBfar\000" |
| 15033 | /* 49300 */ "LDRLIT_ga_pcrel_ldr\000" |
| 15034 | /* 49320 */ "MOV_ga_pcrel_ldr\000" |
| 15035 | /* 49337 */ "VLD2q32PseudoWB_register\000" |
| 15036 | /* 49362 */ "VST2q32PseudoWB_register\000" |
| 15037 | /* 49387 */ "VLD2q16PseudoWB_register\000" |
| 15038 | /* 49412 */ "VST2q16PseudoWB_register\000" |
| 15039 | /* 49437 */ "VLD2q8PseudoWB_register\000" |
| 15040 | /* 49461 */ "VST2q8PseudoWB_register\000" |
| 15041 | /* 49485 */ "VLD1d32QPseudoWB_register\000" |
| 15042 | /* 49511 */ "VST1d32QPseudoWB_register\000" |
| 15043 | /* 49537 */ "VLD1d64QPseudoWB_register\000" |
| 15044 | /* 49563 */ "VST1d64QPseudoWB_register\000" |
| 15045 | /* 49589 */ "VLD1d16QPseudoWB_register\000" |
| 15046 | /* 49615 */ "VST1d16QPseudoWB_register\000" |
| 15047 | /* 49641 */ "VLD1d8QPseudoWB_register\000" |
| 15048 | /* 49666 */ "VST1d8QPseudoWB_register\000" |
| 15049 | /* 49691 */ "VLD1d32TPseudoWB_register\000" |
| 15050 | /* 49717 */ "VST1d32TPseudoWB_register\000" |
| 15051 | /* 49743 */ "VLD1d64TPseudoWB_register\000" |
| 15052 | /* 49769 */ "VST1d64TPseudoWB_register\000" |
| 15053 | /* 49795 */ "VLD1d16TPseudoWB_register\000" |
| 15054 | /* 49821 */ "VST1d16TPseudoWB_register\000" |
| 15055 | /* 49847 */ "VLD1d8TPseudoWB_register\000" |
| 15056 | /* 49872 */ "VST1d8TPseudoWB_register\000" |
| 15057 | /* 49897 */ "VLD2DUPq32OddPseudoWB_register\000" |
| 15058 | /* 49928 */ "VLD2DUPq16OddPseudoWB_register\000" |
| 15059 | /* 49959 */ "VLD2DUPq8OddPseudoWB_register\000" |
| 15060 | /* 49989 */ "VLD2b32wb_register\000" |
| 15061 | /* 50008 */ "VST2b32wb_register\000" |
| 15062 | /* 50027 */ "VLD1d32wb_register\000" |
| 15063 | /* 50046 */ "VST1d32wb_register\000" |
| 15064 | /* 50065 */ "VLD2d32wb_register\000" |
| 15065 | /* 50084 */ "VST2d32wb_register\000" |
| 15066 | /* 50103 */ "VLD1DUPd32wb_register\000" |
| 15067 | /* 50125 */ "VLD2DUPd32wb_register\000" |
| 15068 | /* 50147 */ "VLD1q32wb_register\000" |
| 15069 | /* 50166 */ "VST1q32wb_register\000" |
| 15070 | /* 50185 */ "VLD2q32wb_register\000" |
| 15071 | /* 50204 */ "VST2q32wb_register\000" |
| 15072 | /* 50223 */ "VLD1DUPq32wb_register\000" |
| 15073 | /* 50245 */ "VLD2DUPd32x2wb_register\000" |
| 15074 | /* 50269 */ "VLD2DUPd16x2wb_register\000" |
| 15075 | /* 50293 */ "VLD2DUPd8x2wb_register\000" |
| 15076 | /* 50316 */ "VLD1d64wb_register\000" |
| 15077 | /* 50335 */ "VST1d64wb_register\000" |
| 15078 | /* 50354 */ "VLD1q64wb_register\000" |
| 15079 | /* 50373 */ "VST1q64wb_register\000" |
| 15080 | /* 50392 */ "VLD2b16wb_register\000" |
| 15081 | /* 50411 */ "VST2b16wb_register\000" |
| 15082 | /* 50430 */ "VLD1d16wb_register\000" |
| 15083 | /* 50449 */ "VST1d16wb_register\000" |
| 15084 | /* 50468 */ "VLD2d16wb_register\000" |
| 15085 | /* 50487 */ "VST2d16wb_register\000" |
| 15086 | /* 50506 */ "VLD1DUPd16wb_register\000" |
| 15087 | /* 50528 */ "VLD2DUPd16wb_register\000" |
| 15088 | /* 50550 */ "VLD1q16wb_register\000" |
| 15089 | /* 50569 */ "VST1q16wb_register\000" |
| 15090 | /* 50588 */ "VLD2q16wb_register\000" |
| 15091 | /* 50607 */ "VST2q16wb_register\000" |
| 15092 | /* 50626 */ "VLD1DUPq16wb_register\000" |
| 15093 | /* 50648 */ "VLD2b8wb_register\000" |
| 15094 | /* 50666 */ "VST2b8wb_register\000" |
| 15095 | /* 50684 */ "VLD1d8wb_register\000" |
| 15096 | /* 50702 */ "VST1d8wb_register\000" |
| 15097 | /* 50720 */ "VLD2d8wb_register\000" |
| 15098 | /* 50738 */ "VST2d8wb_register\000" |
| 15099 | /* 50756 */ "VLD1DUPd8wb_register\000" |
| 15100 | /* 50777 */ "VLD2DUPd8wb_register\000" |
| 15101 | /* 50798 */ "VLD1q8wb_register\000" |
| 15102 | /* 50816 */ "VST1q8wb_register\000" |
| 15103 | /* 50834 */ "VLD2q8wb_register\000" |
| 15104 | /* 50852 */ "VST2q8wb_register\000" |
| 15105 | /* 50870 */ "VLD1DUPq8wb_register\000" |
| 15106 | /* 50891 */ "VLD1d32Qwb_register\000" |
| 15107 | /* 50911 */ "VST1d32Qwb_register\000" |
| 15108 | /* 50931 */ "VLD1d64Qwb_register\000" |
| 15109 | /* 50951 */ "VST1d64Qwb_register\000" |
| 15110 | /* 50971 */ "VLD1d16Qwb_register\000" |
| 15111 | /* 50991 */ "VST1d16Qwb_register\000" |
| 15112 | /* 51011 */ "VLD1d8Qwb_register\000" |
| 15113 | /* 51030 */ "VST1d8Qwb_register\000" |
| 15114 | /* 51049 */ "VLD1d32Twb_register\000" |
| 15115 | /* 51069 */ "VST1d32Twb_register\000" |
| 15116 | /* 51089 */ "VLD1d64Twb_register\000" |
| 15117 | /* 51109 */ "VST1d64Twb_register\000" |
| 15118 | /* 51129 */ "VLD1d16Twb_register\000" |
| 15119 | /* 51149 */ "VST1d16Twb_register\000" |
| 15120 | /* 51169 */ "VLD1d8Twb_register\000" |
| 15121 | /* 51188 */ "VST1d8Twb_register\000" |
| 15122 | /* 51207 */ "tCMPhir\000" |
| 15123 | /* 51215 */ "t2MOVCCror\000" |
| 15124 | /* 51226 */ "tADDspr\000" |
| 15125 | /* 51234 */ "t2RSBrr\000" |
| 15126 | /* 51242 */ "t2SUBrr\000" |
| 15127 | /* 51250 */ "tSUBrr\000" |
| 15128 | /* 51257 */ "t2SBCrr\000" |
| 15129 | /* 51265 */ "t2ADCrr\000" |
| 15130 | /* 51273 */ "t2BICrr\000" |
| 15131 | /* 51281 */ "RSCrr\000" |
| 15132 | /* 51287 */ "t2ADDrr\000" |
| 15133 | /* 51295 */ "tADDrr\000" |
| 15134 | /* 51302 */ "t2ANDrr\000" |
| 15135 | /* 51310 */ "t2LSLrr\000" |
| 15136 | /* 51318 */ "tLSLrr\000" |
| 15137 | /* 51325 */ "t2CMNrr\000" |
| 15138 | /* 51333 */ "t2ORNrr\000" |
| 15139 | /* 51341 */ "t2CMPrr\000" |
| 15140 | /* 51349 */ "t2TEQrr\000" |
| 15141 | /* 51357 */ "t2EORrr\000" |
| 15142 | /* 51365 */ "t2RORrr\000" |
| 15143 | /* 51373 */ "t2ORRrr\000" |
| 15144 | /* 51381 */ "t2ASRrr\000" |
| 15145 | /* 51389 */ "tASRrr\000" |
| 15146 | /* 51396 */ "t2LSRrr\000" |
| 15147 | /* 51404 */ "tLSRrr\000" |
| 15148 | /* 51411 */ "t2SUBSrr\000" |
| 15149 | /* 51420 */ "tSUBSrr\000" |
| 15150 | /* 51428 */ "t2ADDSrr\000" |
| 15151 | /* 51437 */ "tADDSrr\000" |
| 15152 | /* 51445 */ "t2TSTrr\000" |
| 15153 | /* 51453 */ "MVE_VMOV_q_rr\000" |
| 15154 | /* 51467 */ "tADDhirr\000" |
| 15155 | /* 51476 */ "MOVCCsr\000" |
| 15156 | /* 51484 */ "MVNsr\000" |
| 15157 | /* 51490 */ "t2MOVSsr\000" |
| 15158 | /* 51499 */ "t2MOVsr\000" |
| 15159 | /* 51507 */ "t2MOVCCasr\000" |
| 15160 | /* 51518 */ "t2MOVCClsr\000" |
| 15161 | /* 51529 */ "RSBrsr\000" |
| 15162 | /* 51536 */ "SUBrsr\000" |
| 15163 | /* 51543 */ "SBCrsr\000" |
| 15164 | /* 51550 */ "ADCrsr\000" |
| 15165 | /* 51557 */ "BICrsr\000" |
| 15166 | /* 51564 */ "RSCrsr\000" |
| 15167 | /* 51571 */ "ADDrsr\000" |
| 15168 | /* 51578 */ "ANDrsr\000" |
| 15169 | /* 51585 */ "CMNrsr\000" |
| 15170 | /* 51592 */ "CMPrsr\000" |
| 15171 | /* 51599 */ "TEQrsr\000" |
| 15172 | /* 51606 */ "EORrsr\000" |
| 15173 | /* 51613 */ "ORRrsr\000" |
| 15174 | /* 51620 */ "RSBSrsr\000" |
| 15175 | /* 51628 */ "SUBSrsr\000" |
| 15176 | /* 51636 */ "ADDSrsr\000" |
| 15177 | /* 51644 */ "TSTrsr\000" |
| 15178 | /* 51651 */ "t2LDRBs\000" |
| 15179 | /* 51659 */ "t2STRBs\000" |
| 15180 | /* 51667 */ "t2LDRSBs\000" |
| 15181 | /* 51676 */ "t2PLDs\000" |
| 15182 | /* 51683 */ "t2LDRHs\000" |
| 15183 | /* 51691 */ "t2STRHs\000" |
| 15184 | /* 51699 */ "t2LDRSHs\000" |
| 15185 | /* 51708 */ "t2PLIs\000" |
| 15186 | /* 51715 */ "t2MVNs\000" |
| 15187 | /* 51722 */ "t2LDRs\000" |
| 15188 | /* 51729 */ "t2STRs\000" |
| 15189 | /* 51736 */ "t2PLDWs\000" |
| 15190 | /* 51744 */ "tLDRLIT_ga_abs\000" |
| 15191 | /* 51759 */ "SEH_SaveFRegs\000" |
| 15192 | /* 51773 */ "SEH_SaveRegs\000" |
| 15193 | /* 51786 */ "LDRBrs\000" |
| 15194 | /* 51793 */ "STRBrs\000" |
| 15195 | /* 51800 */ "t2RSBrs\000" |
| 15196 | /* 51808 */ "t2SUBrs\000" |
| 15197 | /* 51816 */ "t2SBCrs\000" |
| 15198 | /* 51824 */ "t2ADCrs\000" |
| 15199 | /* 51832 */ "t2BICrs\000" |
| 15200 | /* 51840 */ "t2ADDrs\000" |
| 15201 | /* 51848 */ "PLDrs\000" |
| 15202 | /* 51854 */ "t2ANDrs\000" |
| 15203 | /* 51862 */ "PLIrs\000" |
| 15204 | /* 51868 */ "t2CMNrs\000" |
| 15205 | /* 51876 */ "t2ORNrs\000" |
| 15206 | /* 51884 */ "t2CMPrs\000" |
| 15207 | /* 51892 */ "t2TEQrs\000" |
| 15208 | /* 51900 */ "LDRrs\000" |
| 15209 | /* 51906 */ "t2EORrs\000" |
| 15210 | /* 51914 */ "t2ORRrs\000" |
| 15211 | /* 51922 */ "STRrs\000" |
| 15212 | /* 51928 */ "t2RSBSrs\000" |
| 15213 | /* 51937 */ "t2SUBSrs\000" |
| 15214 | /* 51946 */ "t2ADDSrs\000" |
| 15215 | /* 51955 */ "t2TSTrs\000" |
| 15216 | /* 51963 */ "PLDWrs\000" |
| 15217 | /* 51970 */ "BR_JTm_rs\000" |
| 15218 | /* 51980 */ "MRSsys\000" |
| 15219 | /* 51987 */ "SEH_Nop_Ret\000" |
| 15220 | /* 51999 */ "SEH_SaveRegs_Ret\000" |
| 15221 | /* 52016 */ "tTPsoft\000" |
| 15222 | /* 52024 */ "SEH_EpilogStart\000" |
| 15223 | /* 52040 */ "t2WhileLoopStart\000" |
| 15224 | /* 52057 */ "t2DoLoopStart\000" |
| 15225 | /* 52071 */ "VLDR_P0_post\000" |
| 15226 | /* 52084 */ "VSTR_P0_post\000" |
| 15227 | /* 52097 */ "MVE_VSTRB32_post\000" |
| 15228 | /* 52114 */ "MVE_VSTRH32_post\000" |
| 15229 | /* 52131 */ "MVE_VLDRBS32_post\000" |
| 15230 | /* 52149 */ "MVE_VLDRHS32_post\000" |
| 15231 | /* 52167 */ "MVE_VLDRBU32_post\000" |
| 15232 | /* 52185 */ "MVE_VLDRHU32_post\000" |
| 15233 | /* 52203 */ "MVE_VLDRWU32_post\000" |
| 15234 | /* 52221 */ "MVE_VSTRWU32_post\000" |
| 15235 | /* 52239 */ "MVE_VSTRB16_post\000" |
| 15236 | /* 52256 */ "MVE_VLDRBS16_post\000" |
| 15237 | /* 52274 */ "MVE_VLDRBU16_post\000" |
| 15238 | /* 52292 */ "MVE_VLDRHU16_post\000" |
| 15239 | /* 52310 */ "MVE_VSTRHU16_post\000" |
| 15240 | /* 52328 */ "MVE_VLDRBU8_post\000" |
| 15241 | /* 52345 */ "MVE_VSTRBU8_post\000" |
| 15242 | /* 52362 */ "VLDR_FPSCR_NZCVQC_post\000" |
| 15243 | /* 52385 */ "VSTR_FPSCR_NZCVQC_post\000" |
| 15244 | /* 52408 */ "VLDR_FPSCR_post\000" |
| 15245 | /* 52424 */ "VSTR_FPSCR_post\000" |
| 15246 | /* 52440 */ "VLDR_VPR_post\000" |
| 15247 | /* 52454 */ "VSTR_VPR_post\000" |
| 15248 | /* 52468 */ "VLDR_FPCXTNS_post\000" |
| 15249 | /* 52486 */ "VSTR_FPCXTNS_post\000" |
| 15250 | /* 52504 */ "VLDR_FPCXTS_post\000" |
| 15251 | /* 52521 */ "VSTR_FPCXTS_post\000" |
| 15252 | /* 52538 */ "MVE_VSTRH32_rq_u\000" |
| 15253 | /* 52555 */ "MVE_VLDRHS32_rq_u\000" |
| 15254 | /* 52573 */ "MVE_VLDRHU32_rq_u\000" |
| 15255 | /* 52591 */ "MVE_VLDRWU32_rq_u\000" |
| 15256 | /* 52609 */ "MVE_VSTRW32_rq_u\000" |
| 15257 | /* 52626 */ "MVE_VSTRD64_rq_u\000" |
| 15258 | /* 52643 */ "MVE_VLDRDU64_rq_u\000" |
| 15259 | /* 52661 */ "MVE_VSTRH16_rq_u\000" |
| 15260 | /* 52678 */ "MVE_VLDRHU16_rq_u\000" |
| 15261 | /* 52696 */ "t2STRB_preidx\000" |
| 15262 | /* 52710 */ "t2STRH_preidx\000" |
| 15263 | /* 52724 */ "t2STR_preidx\000" |
| 15264 | /* 52737 */ "STRBi_preidx\000" |
| 15265 | /* 52750 */ "STRi_preidx\000" |
| 15266 | /* 52762 */ "STRBr_preidx\000" |
| 15267 | /* 52775 */ "STRr_preidx\000" |
| 15268 | /* 52787 */ "tLDR_postidx\000" |
| 15269 | /* 52800 */ "MVE_VCVTs32f32_fix\000" |
| 15270 | /* 52819 */ "MVE_VCVTu32f32_fix\000" |
| 15271 | /* 52838 */ "MVE_VCVTf32s32_fix\000" |
| 15272 | /* 52857 */ "MVE_VCVTf32u32_fix\000" |
| 15273 | /* 52876 */ "MVE_VCVTs16f16_fix\000" |
| 15274 | /* 52895 */ "MVE_VCVTu16f16_fix\000" |
| 15275 | /* 52914 */ "MVE_VCVTf16s16_fix\000" |
| 15276 | /* 52933 */ "MVE_VCVTf16u16_fix\000" |
| 15277 | /* 52952 */ "MQPRCopy\000" |
| 15278 | /* 52961 */ "MVE_VCVTs32f32z\000" |
| 15279 | /* 52977 */ "MVE_VCVTu32f32z\000" |
| 15280 | /* 52993 */ "MVE_VCVTs16f16z\000" |
| 15281 | /* 53009 */ "MVE_VCVTu16f16z\000" |
| 15282 | }; |
| 15283 | #ifdef __GNUC__ |
| 15284 | #pragma GCC diagnostic pop |
| 15285 | #endif |
| 15286 | |
| 15287 | extern const unsigned ARMInstrNameIndices[] = { |
| 15288 | 31129U, 32164U, 33580U, 32682U, 31379U, 31360U, 31388U, 31684U, |
| 15289 | 29986U, 30001U, 29931U, 29918U, 30078U, 34754U, 29783U, 36166U, |
| 15290 | 29944U, 31125U, 31369U, 29314U, 37301U, 31277U, 29441U, 36056U, |
| 15291 | 24980U, 29259U, 29302U, 33001U, 31638U, 35950U, 28894U, 33312U, |
| 15292 | 30283U, 35939U, 29491U, 33212U, 33199U, 33665U, 35525U, 35736U, |
| 15293 | 31535U, 31594U, 31567U, 31405U, 29774U, 33630U, 32921U, 29480U, |
| 15294 | 37322U, 33906U, 33165U, 29831U, 36628U, 36658U, 32520U, 24692U, |
| 15295 | 24041U, 31874U, 36748U, 36762U, 31946U, 31953U, 31960U, 31970U, |
| 15296 | 24945U, 34120U, 34083U, 34312U, 36672U, 33950U, 31511U, 33938U, |
| 15297 | 31500U, 29929U, 31127U, 37115U, 29793U, 29808U, 31705U, 35456U, |
| 15298 | 34347U, 36100U, 34364U, 34006U, 24265U, 34708U, 35961U, 34223U, |
| 15299 | 36139U, 29874U, 33641U, 25076U, 24239U, 25058U, 35999U, 35980U, |
| 15300 | 32498U, 33690U, 33709U, 24548U, 24492U, 24522U, 24461U, 24533U, |
| 15301 | 24473U, 24503U, 29550U, 29504U, 29534U, 34798U, 30204U, 30221U, |
| 15302 | 24708U, 24047U, 24951U, 24903U, 34125U, 34089U, 36986U, 32646U, |
| 15303 | 36969U, 32629U, 24652U, 24017U, 36904U, 32564U, 32265U, 32212U, |
| 15304 | 32386U, 32324U, 33069U, 33047U, 25009U, 35334U, 29294U, 30428U, |
| 15305 | 25000U, 35475U, 36071U, 24180U, 34904U, 35903U, 34931U, 36642U, |
| 15306 | 24257U, 35123U, 36679U, 36694U, 35892U, 35880U, 36046U, 30275U, |
| 15307 | 36621U, 30015U, 36651U, 31486U, 33776U, 33762U, 31448U, 33769U, |
| 15308 | 34216U, 31764U, 33144U, 33123U, 33151U, 33158U, 35466U, 32913U, |
| 15309 | 29335U, 32897U, 29280U, 32905U, 29327U, 32889U, 29272U, 32951U, |
| 15310 | 32943U, 30534U, 30526U, 35238U, 35228U, 35218U, 35208U, 35258U, |
| 15311 | 35248U, 37189U, 37199U, 35282U, 35295U, 37209U, 37219U, 35308U, |
| 15312 | 35321U, 24610U, 23996U, 31800U, 23578U, 24447U, 36720U, 31925U, |
| 15313 | 29899U, 36852U, 31251U, 33360U, 8358U, 9U, 30268U, 8319U, |
| 15314 | 0U, 33335U, 33367U, 29971U, 36613U, 24229U, 31207U, 31242U, |
| 15315 | 33105U, 33114U, 35355U, 35368U, 34275U, 32535U, 34771U, 29883U, |
| 15316 | 32410U, 32420U, 29384U, 29399U, 32201U, 32254U, 32310U, 32372U, |
| 15317 | 36769U, 36795U, 36781U, 29343U, 29371U, 29356U, 30238U, 30253U, |
| 15318 | 24698U, 31291U, 32598U, 36938U, 32622U, 36962U, 34282U, 25049U, |
| 15319 | 25039U, 33575U, 35760U, 29419U, 33987U, 33967U, 35855U, 35834U, |
| 15320 | 34021U, 34052U, 34038U, 34828U, 37396U, 32829U, 37383U, 32810U, |
| 15321 | 34442U, 33186U, 33091U, 29761U, 31842U, 30510U, 31492U, 34564U, |
| 15322 | 32670U, 34571U, 32491U, 34556U, 32662U, 32483U, 8342U, 30804U, |
| 15323 | 30595U, 30587U, 36109U, 33929U, 35972U, 36017U, 36149U, 33610U, |
| 15324 | 29428U, 24286U, 29852U, 29519U, 24638U, 24003U, 31828U, 36727U, |
| 15325 | 31932U, 23584U, 36117U, 33344U, 33130U, 34628U, 33729U, 33745U, |
| 15326 | 37292U, 29464U, 29864U, 35690U, 32959U, 29448U, 33034U, 33010U, |
| 15327 | 33022U, 24617U, 31807U, 24593U, 31783U, 36887U, 32547U, 32233U, |
| 15328 | 32180U, 32348U, 32286U, 24676U, 31858U, 24929U, 34105U, 34067U, |
| 15329 | 36921U, 32581U, 36945U, 32605U, 37168U, 37182U, 44267U, 51430U, |
| 15330 | 44428U, 51636U, 32872U, 33297U, 43796U, 49206U, 165U, 23610U, |
| 15331 | 9619U, 9612U, 47567U, 47576U, 33830U, 31522U, 31624U, 38696U, |
| 15332 | 287U, 51970U, 49268U, 31616U, 35493U, 35502U, 10209U, 690U, |
| 15333 | 8583U, 18046U, 37306U, 385U, 45133U, 47800U, 47627U, 47649U, |
| 15334 | 47543U, 43086U, 34665U, 34984U, 23673U, 30398U, 32142U, 145U, |
| 15335 | 8458U, 35515U, 36459U, 44614U, 43962U, 51745U, 44564U, 49300U, |
| 15336 | 43953U, 43970U, 36481U, 44445U, 35811U, 31337U, 43764U, 49167U, |
| 15337 | 43801U, 49211U, 173U, 37294U, 9697U, 43710U, 15139U, 44740U, |
| 15338 | 49113U, 44290U, 51476U, 37233U, 44527U, 44599U, 49320U, 44546U, |
| 15339 | 44754U, 52952U, 38674U, 41018U, 38684U, 41029U, 9735U, 36224U, |
| 15340 | 36205U, 43701U, 24578U, 33623U, 23855U, 30675U, 23888U, 30820U, |
| 15341 | 34234U, 23863U, 30713U, 43791U, 49201U, 37243U, 43860U, 44249U, |
| 15342 | 44412U, 51620U, 40887U, 52024U, 47688U, 51987U, 40901U, 51759U, |
| 15343 | 33862U, 51773U, 51999U, 33224U, 38482U, 9703U, 9719U, 29288U, |
| 15344 | 31346U, 36470U, 52737U, 52762U, 52712U, 36491U, 52750U, 52775U, |
| 15345 | 33851U, 44258U, 51413U, 44420U, 51628U, 23689U, 23721U, 38629U, |
| 15346 | 49186U, 9687U, 43942U, 44166U, 344U, 52017U, 9711U, 9727U, |
| 15347 | 11565U, 2068U, 19060U, 10351U, 854U, 18180U, 10949U, 1452U, |
| 15348 | 18620U, 11593U, 2096U, 19086U, 10397U, 900U, 18224U, 11001U, |
| 15349 | 1504U, 18670U, 11755U, 2258U, 10667U, 1170U, 11307U, 1810U, |
| 15350 | 11677U, 2180U, 19164U, 10535U, 1038U, 18356U, 11157U, 1660U, |
| 15351 | 18820U, 11839U, 2342U, 19236U, 10805U, 1308U, 18482U, 11463U, |
| 15352 | 1966U, 18964U, 11621U, 2124U, 19112U, 10443U, 946U, 18268U, |
| 15353 | 11053U, 1556U, 18720U, 11783U, 2286U, 10713U, 1216U, 11359U, |
| 15354 | 1862U, 11517U, 2020U, 19016U, 10267U, 770U, 18100U, 10853U, |
| 15355 | 1356U, 18528U, 11707U, 2210U, 19192U, 10583U, 1086U, 18402U, |
| 15356 | 11211U, 1714U, 18872U, 11692U, 2195U, 19178U, 10559U, 1062U, |
| 15357 | 18379U, 11184U, 1687U, 18846U, 11854U, 2357U, 19250U, 10829U, |
| 15358 | 1332U, 18505U, 11490U, 1993U, 18990U, 11649U, 2152U, 19138U, |
| 15359 | 10489U, 992U, 18312U, 11105U, 1608U, 18770U, 11811U, 2314U, |
| 15360 | 10759U, 1262U, 11411U, 1914U, 11541U, 2044U, 19038U, 10309U, |
| 15361 | 812U, 18140U, 10901U, 1404U, 18574U, 11731U, 2234U, 19214U, |
| 15362 | 10625U, 1128U, 18442U, 11259U, 1762U, 18918U, 18U, 38042U, |
| 15363 | 38050U, 41U, 38058U, 11579U, 2082U, 19073U, 10374U, 877U, |
| 15364 | 18202U, 10975U, 1478U, 18645U, 11607U, 2110U, 19099U, 10420U, |
| 15365 | 923U, 18246U, 11027U, 1530U, 18695U, 11769U, 2272U, 10690U, |
| 15366 | 1193U, 11333U, 1836U, 11635U, 2138U, 19125U, 10466U, 969U, |
| 15367 | 18290U, 11079U, 1582U, 18745U, 11797U, 2300U, 10736U, 1239U, |
| 15368 | 11385U, 1888U, 11529U, 2032U, 19027U, 10288U, 791U, 18120U, |
| 15369 | 10877U, 1380U, 18551U, 11719U, 2222U, 19203U, 10604U, 1107U, |
| 15370 | 18422U, 11235U, 1738U, 18895U, 11663U, 2166U, 19151U, 10512U, |
| 15371 | 1015U, 18334U, 11131U, 1634U, 18795U, 11825U, 2328U, 10782U, |
| 15372 | 1285U, 11437U, 1940U, 11553U, 2056U, 19049U, 10330U, 833U, |
| 15373 | 18160U, 10925U, 1428U, 18597U, 11743U, 2246U, 19225U, 10646U, |
| 15374 | 1149U, 18462U, 11283U, 1786U, 18941U, 31301U, 31265U, 44265U, |
| 15375 | 51428U, 51946U, 47142U, 35801U, 35558U, 31231U, 52057U, 33280U, |
| 15376 | 35513U, 44895U, 45005U, 44775U, 44464U, 44612U, 44950U, 45054U, |
| 15377 | 44821U, 44489U, 44562U, 44931U, 45037U, 44805U, 44476U, 44986U, |
| 15378 | 45086U, 44851U, 44501U, 45103U, 44867U, 38457U, 44514U, 44443U, |
| 15379 | 35809U, 38359U, 40915U, 38346U, 51507U, 43708U, 15137U, 44738U, |
| 15380 | 44641U, 51518U, 49111U, 51215U, 44304U, 51490U, 44525U, 44597U, |
| 15381 | 44544U, 44752U, 44313U, 51499U, 43699U, 44247U, 51928U, 44913U, |
| 15382 | 45021U, 44790U, 52696U, 44968U, 45070U, 44836U, 52710U, 45118U, |
| 15383 | 44881U, 52724U, 44256U, 51411U, 51937U, 23687U, 23719U, 35767U, |
| 15384 | 35784U, 47783U, 52040U, 33873U, 33261U, 34306U, 8564U, 21384U, |
| 15385 | 51437U, 41008U, 32871U, 33296U, 31555U, 47590U, 33829U, 24993U, |
| 15386 | 49267U, 35548U, 31615U, 35570U, 42130U, 49294U, 10208U, 689U, |
| 15387 | 18045U, 26227U, 44627U, 51744U, 44580U, 52787U, 38470U, 44454U, |
| 15388 | 35822U, 44274U, 47345U, 44764U, 35539U, 34288U, 34300U, 8556U, |
| 15389 | 21376U, 51420U, 38628U, 25102U, 49185U, 35776U, 35793U, 52016U, |
| 15390 | 44099U, 51267U, 44342U, 51550U, 44121U, 51289U, 44363U, 51571U, |
| 15391 | 33601U, 28969U, 29756U, 24202U, 24215U, 44129U, 51304U, 44370U, |
| 15392 | 51578U, 29085U, 33504U, 29101U, 33520U, 36585U, 23951U, 36554U, |
| 15393 | 24162U, 31121U, 44107U, 51275U, 44349U, 51557U, 36041U, 31357U, |
| 15394 | 37229U, 38745U, 43855U, 38729U, 37048U, 31261U, 35571U, 38737U, |
| 15395 | 38033U, 137U, 23294U, 24393U, 23349U, 8450U, 23317U, 24402U, |
| 15396 | 23359U, 8534U, 23326U, 24411U, 23369U, 47496U, 47738U, 38408U, |
| 15397 | 47454U, 47696U, 38369U, 47511U, 47753U, 38422U, 47468U, 47710U, |
| 15398 | 38382U, 47526U, 47768U, 38436U, 47482U, 47724U, 38395U, 33101U, |
| 15399 | 8353U, 37147U, 37379U, 44152U, 51327U, 44377U, 51585U, 44179U, |
| 15400 | 51343U, 44384U, 51592U, 47362U, 47402U, 47410U, 23605U, 23749U, |
| 15401 | 30420U, 36844U, 30320U, 36817U, 29960U, 23846U, 23878U, 44195U, |
| 15402 | 51359U, 44398U, 51606U, 35488U, 29124U, 30888U, 35000U, 26454U, |
| 15403 | 23520U, 26310U, 35381U, 26466U, 23528U, 26322U, 35928U, 35876U, |
| 15404 | 24362U, 23884U, 23387U, 23618U, 37109U, 24083U, 29178U, 30968U, |
| 15405 | 30337U, 35634U, 32754U, 36389U, 29692U, 35580U, 32700U, 36245U, |
| 15406 | 29560U, 35664U, 32784U, 36415U, 29716U, 35608U, 32728U, 36306U, |
| 15407 | 29616U, 23394U, 26135U, 23767U, 26370U, 23441U, 26204U, 23816U, |
| 15408 | 26491U, 32084U, 30146U, 32030U, 30092U, 31980U, 30028U, 181U, |
| 15409 | 51786U, 28912U, 36328U, 29636U, 37139U, 24101U, 29196U, 30986U, |
| 15410 | 30678U, 43825U, 49245U, 36352U, 29658U, 23891U, 43817U, 49237U, |
| 15411 | 36293U, 29604U, 30823U, 43839U, 49259U, 36376U, 29680U, 32114U, |
| 15412 | 30176U, 32058U, 30120U, 32006U, 30054U, 47448U, 261U, 51900U, |
| 15413 | 33595U, 8368U, 34160U, 8386U, 23538U, 34423U, 33821U, 15258U, |
| 15414 | 43849U, 15268U, 49277U, 24352U, 44315U, 51501U, 24341U, 8306U, |
| 15415 | 24347U, 8313U, 34704U, 38719U, 51980U, 34205U, 38707U, 43806U, |
| 15416 | 31779U, 43754U, 49157U, 10221U, 702U, 8595U, 18057U, 33243U, |
| 15417 | 33252U, 43744U, 49147U, 31755U, 33783U, 31721U, 31455U, 31650U, |
| 15418 | 33794U, 31733U, 31475U, 31672U, 31465U, 31661U, 33804U, 31744U, |
| 15419 | 16054U, 6573U, 22045U, 17214U, 7834U, 22942U, 12359U, 2856U, |
| 15420 | 15776U, 6269U, 21788U, 17024U, 7636U, 22767U, 12473U, 2970U, |
| 15421 | 16016U, 6535U, 22010U, 24146U, 31059U, 38082U, 38213U, 38115U, |
| 15422 | 38252U, 38132U, 38272U, 38066U, 38194U, 38164U, 38310U, 38148U, |
| 15423 | 38291U, 38099U, 38233U, 38179U, 38328U, 12608U, 3105U, 15307U, |
| 15424 | 5838U, 21438U, 12384U, 2881U, 15170U, 5710U, 21205U, 24920U, |
| 15425 | 24166U, 15356U, 5887U, 9927U, 429U, 17827U, 12371U, 2868U, |
| 15426 | 15148U, 5688U, 21185U, 16028U, 6547U, 22021U, 16274U, 6793U, |
| 15427 | 22220U, 12292U, 2789U, 12461U, 48925U, 2958U, 48817U, 15244U, |
| 15428 | 48952U, 5794U, 48844U, 21342U, 49033U, 15991U, 48979U, 6510U, |
| 15429 | 48871U, 21987U, 49059U, 17134U, 49006U, 7754U, 48898U, 22868U, |
| 15430 | 49085U, 12408U, 2905U, 9905U, 407U, 8572U, 17807U, 42514U, |
| 15431 | 43113U, 52914U, 45235U, 52933U, 45251U, 42699U, 43298U, 52838U, |
| 15432 | 45171U, 52857U, 45187U, 52876U, 37435U, 44684U, 45203U, 47416U, |
| 15433 | 52993U, 52800U, 37403U, 44652U, 45139U, 47368U, 52961U, 52895U, |
| 15434 | 37451U, 44700U, 45219U, 47432U, 53009U, 52819U, 37419U, 44668U, |
| 15435 | 45155U, 47384U, 52977U, 17146U, 7766U, 22879U, 9916U, 418U, |
| 15436 | 17817U, 17172U, 7792U, 22903U, 33892U, 12497U, 2994U, 12576U, |
| 15437 | 3073U, 12305U, 2802U, 12485U, 2982U, 16343U, 6839U, 22285U, |
| 15438 | 17362U, 7959U, 23065U, 15816U, 6309U, 21825U, 17050U, 7662U, |
| 15439 | 22791U, 15788U, 6281U, 21799U, 16309U, 6805U, 22253U, 17328U, |
| 15440 | 7925U, 23033U, 15750U, 6243U, 21764U, 16998U, 7610U, 22743U, |
| 15441 | 17159U, 7779U, 22891U, 17186U, 7806U, 22916U, 10024U, 37659U, |
| 15442 | 519U, 37467U, 17862U, 37851U, 10076U, 37723U, 571U, 37531U, |
| 15443 | 17910U, 37911U, 10050U, 37691U, 545U, 37499U, 17886U, 37881U, |
| 15444 | 10102U, 37755U, 597U, 37563U, 17934U, 37941U, 10142U, 37787U, |
| 15445 | 623U, 37595U, 17971U, 37971U, 10168U, 37819U, 649U, 37627U, |
| 15446 | 17995U, 38001U, 9939U, 52256U, 41216U, 48650U, 441U, 52131U, |
| 15447 | 41098U, 48494U, 9970U, 52274U, 41233U, 48666U, 467U, 52167U, |
| 15448 | 41132U, 48526U, 17838U, 52328U, 41284U, 48712U, 44057U, 41540U, |
| 15449 | 48604U, 52643U, 454U, 52149U, 41115U, 48510U, 52555U, 9983U, |
| 15450 | 52292U, 41250U, 48682U, 52678U, 480U, 52185U, 41149U, 48542U, |
| 15451 | 52573U, 493U, 52203U, 41166U, 44011U, 41482U, 48558U, 52591U, |
| 15452 | 16143U, 6662U, 22098U, 15723U, 6216U, 21739U, 12530U, 3027U, |
| 15453 | 12332U, 2829U, 12561U, 3058U, 12447U, 2944U, 16170U, 6689U, |
| 15454 | 22123U, 17271U, 7891U, 22980U, 16192U, 6711U, 22143U, 17293U, |
| 15455 | 7913U, 23000U, 16129U, 6648U, 22085U, 15710U, 6203U, 21727U, |
| 15456 | 12514U, 3011U, 12317U, 2814U, 12546U, 3043U, 12433U, 2930U, |
| 15457 | 16157U, 6676U, 22111U, 17258U, 7878U, 22968U, 15969U, 6498U, |
| 15458 | 21967U, 17112U, 7742U, 22848U, 16416U, 6950U, 22354U, 17396U, |
| 15459 | 8012U, 23097U, 16901U, 7513U, 22685U, 16067U, 6586U, 22057U, |
| 15460 | 17227U, 7847U, 22954U, 16835U, 7407U, 22655U, 16432U, 6966U, |
| 15461 | 17412U, 8028U, 16918U, 7530U, 16082U, 6601U, 17242U, 7862U, |
| 15462 | 16851U, 7423U, 15339U, 5870U, 21468U, 15275U, 5806U, 21408U, |
| 15463 | 16466U, 7000U, 22369U, 16954U, 7566U, 22701U, 16114U, 6633U, |
| 15464 | 22071U, 16885U, 7457U, 22670U, 16449U, 6983U, 16936U, 7548U, |
| 15465 | 16098U, 6617U, 16868U, 7440U, 42779U, 43378U, 42988U, 43587U, |
| 15466 | 42920U, 43519U, 43037U, 43636U, 42747U, 43346U, 42562U, 43161U, |
| 15467 | 728U, 16286U, 22231U, 17305U, 23011U, 51453U, 48002U, 10247U, |
| 15468 | 750U, 18081U, 3137U, 15401U, 5932U, 9627U, 21484U, 15947U, |
| 15469 | 6440U, 21947U, 17090U, 7702U, 22828U, 15460U, 21539U, 15736U, |
| 15470 | 6229U, 21751U, 16984U, 7596U, 22730U, 15474U, 21560U, 16040U, |
| 15471 | 6559U, 22032U, 17200U, 7820U, 22929U, 12624U, 3121U, 15323U, |
| 15472 | 5854U, 21453U, 12421U, 2918U, 15222U, 5762U, 21322U, 32857U, |
| 15473 | 15371U, 5902U, 12396U, 2893U, 15855U, 6348U, 21861U, 32848U, |
| 15474 | 34173U, 15386U, 5917U, 36030U, 31438U, 36501U, 19623U, 49019U, |
| 15475 | 21714U, 49045U, 22717U, 49071U, 2711U, 48803U, 4649U, 48830U, |
| 15476 | 6190U, 48857U, 7583U, 48884U, 12224U, 48911U, 14098U, 48938U, |
| 15477 | 15697U, 48965U, 16971U, 48992U, 16003U, 6522U, 21998U, 16360U, |
| 15478 | 6856U, 22301U, 17379U, 7976U, 23081U, 15829U, 6322U, 21837U, |
| 15479 | 17063U, 7675U, 22803U, 16204U, 6723U, 22154U, 15867U, 6360U, |
| 15480 | 21872U, 16695U, 7229U, 22523U, 16732U, 7266U, 22558U, 16239U, |
| 15481 | 6758U, 22187U, 15900U, 6393U, 21903U, 16377U, 6873U, 22317U, |
| 15482 | 15182U, 5722U, 21249U, 42862U, 43461U, 42662U, 43261U, 42762U, |
| 15483 | 43361U, 42577U, 43176U, 42846U, 43445U, 42646U, 43245U, 42935U, |
| 15484 | 43534U, 42683U, 43282U, 42829U, 43428U, 42629U, 43228U, 15842U, |
| 15485 | 6335U, 21849U, 16221U, 6740U, 22170U, 15883U, 6376U, 21887U, |
| 15486 | 16713U, 7247U, 22540U, 16751U, 7285U, 22576U, 16256U, 6775U, |
| 15487 | 22203U, 15916U, 6409U, 21918U, 16396U, 6892U, 22335U, 15197U, |
| 15488 | 5737U, 21263U, 16502U, 7036U, 22403U, 17449U, 8065U, 23131U, |
| 15489 | 16787U, 7321U, 22610U, 17640U, 8256U, 23249U, 16578U, 7112U, |
| 15490 | 17525U, 8141U, 16611U, 7145U, 17558U, 8174U, 42811U, 43410U, |
| 15491 | 42611U, 43210U, 16677U, 7211U, 22506U, 16482U, 7016U, 22384U, |
| 15492 | 17429U, 8045U, 23112U, 16771U, 7305U, 22595U, 17624U, 8240U, |
| 15493 | 23234U, 16628U, 7162U, 22460U, 17575U, 8191U, 23188U, 16562U, |
| 15494 | 7096U, 17509U, 8125U, 16595U, 7129U, 17542U, 8158U, 42794U, |
| 15495 | 43393U, 42594U, 43193U, 16326U, 6822U, 22269U, 17345U, 7942U, |
| 15496 | 23049U, 15763U, 6256U, 21776U, 17011U, 7623U, 22755U, 18032U, |
| 15497 | 10128U, 17958U, 10194U, 675U, 18019U, 15802U, 6295U, 21812U, |
| 15498 | 17036U, 7648U, 22778U, 23335U, 31905U, 32460U, 32987U, 36873U, |
| 15499 | 37358U, 23303U, 31891U, 32446U, 32973U, 36859U, 37344U, 6912U, |
| 15500 | 7993U, 7473U, 6453U, 7715U, 7369U, 6931U, 7493U, 6471U, |
| 15501 | 7388U, 15933U, 6426U, 21934U, 17076U, 7688U, 22815U, 16523U, |
| 15502 | 7057U, 22423U, 17470U, 8086U, 23151U, 16804U, 7338U, 22626U, |
| 15503 | 17657U, 8273U, 23265U, 42716U, 43315U, 42531U, 43130U, 16644U, |
| 15504 | 7178U, 22475U, 17591U, 8207U, 23203U, 24132U, 31049U, 24192U, |
| 15505 | 42883U, 43482U, 43002U, 43601U, 42951U, 43550U, 43051U, 43650U, |
| 15506 | 42902U, 43501U, 43020U, 43619U, 42970U, 43569U, 43069U, 43668U, |
| 15507 | 16543U, 7077U, 22442U, 17490U, 8106U, 23170U, 15416U, 5947U, |
| 15508 | 21498U, 16820U, 7354U, 22641U, 17673U, 8289U, 23280U, 42732U, |
| 15509 | 43331U, 42547U, 43146U, 16661U, 7195U, 22491U, 17608U, 8224U, |
| 15510 | 23219U, 15432U, 5963U, 21513U, 15446U, 5977U, 21526U, 10037U, |
| 15511 | 37675U, 532U, 37483U, 17874U, 37866U, 10089U, 37739U, 584U, |
| 15512 | 37547U, 17922U, 37926U, 10063U, 37707U, 558U, 37515U, 17898U, |
| 15513 | 37896U, 10115U, 37771U, 610U, 37579U, 17946U, 37956U, 10155U, |
| 15514 | 37803U, 636U, 37611U, 17983U, 37986U, 10181U, 37835U, 662U, |
| 15515 | 37643U, 18007U, 38016U, 9761U, 52239U, 41200U, 48620U, 361U, |
| 15516 | 52097U, 41066U, 48464U, 48698U, 17850U, 52345U, 41300U, 44042U, |
| 15517 | 41521U, 48589U, 52626U, 48635U, 52661U, 373U, 52114U, 41082U, |
| 15518 | 48479U, 52538U, 9996U, 52310U, 41267U, 44027U, 41502U, 48574U, |
| 15519 | 52609U, 506U, 52221U, 41183U, 12592U, 3089U, 15291U, 5822U, |
| 15520 | 21423U, 12347U, 2844U, 15125U, 5676U, 21167U, 10234U, 715U, |
| 15521 | 8608U, 18069U, 43771U, 49174U, 44298U, 51484U, 41611U, 42185U, |
| 15522 | 41788U, 42362U, 41596U, 42170U, 41773U, 42347U, 44211U, 51375U, |
| 15523 | 44405U, 51613U, 35406U, 23926U, 279U, 51963U, 212U, 51848U, |
| 15524 | 252U, 51862U, 24671U, 9870U, 17776U, 37265U, 24587U, 23990U, |
| 15525 | 37020U, 24036U, 9813U, 17717U, 35731U, 36711U, 10011U, 30852U, |
| 15526 | 23379U, 26122U, 23759U, 26358U, 23433U, 26192U, 23807U, 26478U, |
| 15527 | 44075U, 51236U, 44321U, 51529U, 44113U, 51281U, 44356U, 51564U, |
| 15528 | 9889U, 17793U, 37280U, 23873U, 44091U, 51259U, 44335U, 51543U, |
| 15529 | 37163U, 36743U, 31427U, 24973U, 32476U, 24120U, 30312U, 31885U, |
| 15530 | 32967U, 59U, 113U, 30327U, 8327U, 67U, 121U, 9850U, |
| 15531 | 17758U, 37249U, 37004U, 9793U, 17699U, 24211U, 23641U, 35397U, |
| 15532 | 24429U, 37053U, 31323U, 23650U, 35414U, 24805U, 37071U, 23934U, |
| 15533 | 36531U, 23917U, 36522U, 24065U, 36597U, 28983U, 37091U, 24821U, |
| 15534 | 37081U, 23544U, 33538U, 34429U, 34197U, 31852U, 33842U, 24565U, |
| 15535 | 37062U, 23660U, 35424U, 31691U, 23944U, 36541U, 24074U, 36606U, |
| 15536 | 29041U, 37100U, 23409U, 26158U, 23801U, 26444U, 23514U, 26300U, |
| 15537 | 23831U, 26514U, 35270U, 9954U, 37035U, 9832U, 17734U, 35649U, |
| 15538 | 32769U, 36402U, 29704U, 35594U, 32714U, 36257U, 29571U, 35678U, |
| 15539 | 32798U, 36427U, 29727U, 35621U, 32741U, 36317U, 29626U, 31773U, |
| 15540 | 23839U, 37131U, 24092U, 29187U, 30977U, 30505U, 23403U, 26148U, |
| 15541 | 23784U, 26395U, 23465U, 26240U, 23825U, 26504U, 32099U, 30161U, |
| 15542 | 32044U, 30106U, 31993U, 30041U, 191U, 51793U, 28950U, 36340U, |
| 15543 | 29647U, 37155U, 24110U, 29205U, 30995U, 30716U, 43832U, 49252U, |
| 15544 | 36364U, 29669U, 32128U, 30190U, 32071U, 30133U, 32018U, 30066U, |
| 15545 | 270U, 51922U, 44083U, 51244U, 44328U, 51536U, 24367U, 33331U, |
| 15546 | 23850U, 23625U, 9743U, 30378U, 23964U, 9775U, 30898U, 44187U, |
| 15547 | 51351U, 44391U, 51599U, 33017U, 23911U, 44284U, 51447U, 44436U, |
| 15548 | 51644U, 9898U, 17801U, 37287U, 37177U, 29909U, 36757U, 9860U, |
| 15549 | 17767U, 37257U, 37012U, 9803U, 17708U, 31315U, 31331U, 31699U, |
| 15550 | 9879U, 17784U, 37272U, 37027U, 9822U, 17725U, 17750U, 17690U, |
| 15551 | 35277U, 9963U, 37042U, 9841U, 17742U, 23633U, 9753U, 30386U, |
| 15552 | 23977U, 9784U, 30911U, 9146U, 4967U, 14416U, 9396U, 5346U, |
| 15553 | 14795U, 19703U, 3683U, 13171U, 4850U, 14299U, 20538U, 19950U, |
| 15554 | 4012U, 13500U, 5229U, 14678U, 20801U, 9182U, 5016U, 14465U, |
| 15555 | 9432U, 5395U, 14844U, 40498U, 48075U, 40722U, 48292U, 19761U, |
| 15556 | 3741U, 13229U, 4908U, 14357U, 20591U, 20008U, 4070U, 13558U, |
| 15557 | 5287U, 14736U, 20854U, 28963U, 30742U, 34792U, 40574U, 48144U, |
| 15558 | 40798U, 48368U, 19593U, 3420U, 12908U, 4619U, 14068U, 20450U, |
| 15559 | 40512U, 48089U, 40736U, 48306U, 40614U, 48184U, 40838U, 48408U, |
| 15560 | 24724U, 30447U, 3316U, 12804U, 20364U, 9194U, 5041U, 14490U, |
| 15561 | 9444U, 5420U, 14869U, 34319U, 9337U, 5206U, 14655U, 9587U, |
| 15562 | 5585U, 15034U, 40505U, 48082U, 40729U, 48299U, 19521U, 8647U, |
| 15563 | 3172U, 8983U, 12660U, 4443U, 13931U, 20283U, 38581U, 47919U, |
| 15564 | 33446U, 31133U, 33471U, 31161U, 38575U, 3480U, 12968U, 4692U, |
| 15565 | 14141U, 47913U, 38604U, 47942U, 38662U, 47990U, 38610U, 47948U, |
| 15566 | 38638U, 47966U, 2613U, 12136U, 2700U, 12213U, 40567U, 48137U, |
| 15567 | 40791U, 48361U, 19572U, 3399U, 12887U, 4598U, 14047U, 20431U, |
| 15568 | 20232U, 2656U, 4390U, 12169U, 2756U, 13878U, 5643U, 12259U, |
| 15569 | 15092U, 21109U, 40520U, 48097U, 40744U, 48314U, 19809U, 3789U, |
| 15570 | 13277U, 4956U, 14405U, 20635U, 20056U, 4118U, 13606U, 5335U, |
| 15571 | 14784U, 20898U, 20210U, 2634U, 4368U, 12147U, 2734U, 13856U, |
| 15572 | 5621U, 12237U, 15070U, 21089U, 40622U, 48192U, 40846U, 48416U, |
| 15573 | 19928U, 3948U, 13436U, 5183U, 14632U, 20781U, 20175U, 4277U, |
| 15574 | 13765U, 5562U, 15011U, 21044U, 20243U, 2667U, 4401U, 12180U, |
| 15575 | 2767U, 13889U, 5654U, 12270U, 15103U, 21119U, 20221U, 2645U, |
| 15576 | 4379U, 12158U, 2745U, 13867U, 5632U, 12248U, 15081U, 21099U, |
| 15577 | 19603U, 3430U, 12918U, 4629U, 14078U, 20459U, 20254U, 2678U, |
| 15578 | 4412U, 12191U, 2778U, 13900U, 5665U, 12281U, 15114U, 21129U, |
| 15579 | 19656U, 3470U, 12958U, 4682U, 14131U, 20495U, 2602U, 38754U, |
| 15580 | 12125U, 38792U, 2689U, 38773U, 12202U, 38811U, 25156U, 24738U, |
| 15581 | 30469U, 34340U, 29220U, 31010U, 35084U, 30653U, 34643U, 29244U, |
| 15582 | 31034U, 35108U, 38668U, 47996U, 41676U, 42250U, 41853U, 42427U, |
| 15583 | 41716U, 42290U, 41893U, 42467U, 28955U, 30734U, 34784U, 29132U, |
| 15584 | 30922U, 35032U, 30439U, 24751U, 34385U, 30748U, 34325U, 41686U, |
| 15585 | 42260U, 41863U, 42437U, 41726U, 42300U, 41903U, 42477U, 29008U, |
| 15586 | 30782U, 34872U, 29140U, 30930U, 35040U, 41696U, 42270U, 41873U, |
| 15587 | 42447U, 41736U, 42310U, 41913U, 42487U, 29016U, 30796U, 34880U, |
| 15588 | 29148U, 30938U, 35048U, 41706U, 42280U, 41883U, 42457U, 41746U, |
| 15589 | 42320U, 41923U, 42497U, 29024U, 30812U, 34888U, 29156U, 30946U, |
| 15590 | 35056U, 29032U, 30453U, 24766U, 34400U, 30836U, 42145U, 40932U, |
| 15591 | 48727U, 40970U, 48765U, 40950U, 48745U, 40988U, 48783U, 41571U, |
| 15592 | 40941U, 48736U, 40979U, 48774U, 40960U, 48755U, 40998U, 48793U, |
| 15593 | 40439U, 48016U, 40663U, 48233U, 40458U, 48035U, 40682U, 48252U, |
| 15594 | 40448U, 48025U, 40672U, 48242U, 40467U, 48044U, 40691U, 48261U, |
| 15595 | 29164U, 30954U, 35064U, 38534U, 47872U, 38507U, 47836U, 38560U, |
| 15596 | 47898U, 38524U, 47862U, 38497U, 47826U, 38551U, 47889U, 38650U, |
| 15597 | 47978U, 12117U, 2594U, 19494U, 15689U, 6182U, 9667U, 21707U, |
| 15598 | 24441U, 30355U, 24812U, 31069U, 33457U, 31145U, 34254U, 40484U, |
| 15599 | 48061U, 40708U, 48278U, 28995U, 30769U, 24828U, 31077U, 33464U, |
| 15600 | 31153U, 34859U, 40588U, 48158U, 40812U, 48382U, 24454U, 30361U, |
| 15601 | 34260U, 29001U, 30775U, 34865U, 24874U, 30567U, 34487U, 24862U, |
| 15602 | 30555U, 34475U, 5774U, 15981U, 21978U, 17124U, 22859U, 19785U, |
| 15603 | 3765U, 13253U, 4932U, 14381U, 20613U, 20032U, 4094U, 13582U, |
| 15604 | 5311U, 14760U, 20876U, 19737U, 3717U, 13205U, 4884U, 14333U, |
| 15605 | 20569U, 19984U, 4046U, 13534U, 5263U, 14712U, 20832U, 30790U, |
| 15606 | 36579U, 12065U, 39846U, 50506U, 2550U, 39503U, 50103U, 19447U, |
| 15607 | 40057U, 50756U, 15648U, 39948U, 50626U, 6141U, 39605U, 50223U, |
| 15608 | 21670U, 40153U, 50870U, 11969U, 25570U, 2462U, 25218U, 19361U, |
| 15609 | 25918U, 45871U, 27296U, 45481U, 26830U, 46199U, 27746U, 11885U, |
| 15610 | 33412U, 46289U, 39052U, 49589U, 40239U, 50971U, 35174U, 46557U, |
| 15611 | 39234U, 49795U, 40373U, 51129U, 39782U, 50430U, 2388U, 33376U, |
| 15612 | 46229U, 38960U, 49485U, 40171U, 50891U, 35138U, 46497U, 39142U, |
| 15613 | 49691U, 40305U, 51049U, 39439U, 50027U, 8621U, 33394U, 46259U, |
| 15614 | 39006U, 49537U, 40205U, 50931U, 35156U, 46527U, 39188U, 49743U, |
| 15615 | 40339U, 51089U, 39686U, 50316U, 19278U, 33430U, 46319U, 39098U, |
| 15616 | 49641U, 40273U, 51011U, 35192U, 46587U, 39280U, 49847U, 40407U, |
| 15617 | 51169U, 39997U, 50684U, 15488U, 46423U, 27876U, 46691U, 28232U, |
| 15618 | 28054U, 28410U, 39884U, 50550U, 5991U, 46347U, 27784U, 46615U, |
| 15619 | 28140U, 27966U, 28322U, 39541U, 50147U, 9651U, 46385U, 27830U, |
| 15620 | 46653U, 28186U, 28010U, 28366U, 39718U, 50354U, 21573U, 46461U, |
| 15621 | 27922U, 46729U, 28278U, 28098U, 28454U, 40093U, 50798U, 12076U, |
| 15622 | 39865U, 50528U, 8489U, 39645U, 50269U, 2561U, 39522U, 50125U, |
| 15623 | 8476U, 39624U, 50245U, 19457U, 40075U, 50777U, 8502U, 39666U, |
| 15624 | 50293U, 47222U, 46825U, 39352U, 49928U, 47159U, 46765U, 39324U, |
| 15625 | 49897U, 47285U, 46885U, 39380U, 49959U, 11989U, 45713U, 27062U, |
| 15626 | 25598U, 2482U, 45323U, 26596U, 25246U, 19379U, 46051U, 27524U, |
| 15627 | 25944U, 15572U, 45903U, 27336U, 25760U, 6065U, 45513U, 26870U, |
| 15628 | 25408U, 11869U, 39750U, 50392U, 2372U, 39407U, 49989U, 19264U, |
| 15629 | 39967U, 50648U, 11911U, 39814U, 50468U, 2404U, 39471U, 50065U, |
| 15630 | 19301U, 40027U, 50720U, 15514U, 45843U, 38874U, 49387U, 39916U, |
| 15631 | 50588U, 6007U, 45453U, 38830U, 49337U, 39573U, 50185U, 21596U, |
| 15632 | 46173U, 38918U, 49437U, 40123U, 50834U, 12087U, 45809U, 27182U, |
| 15633 | 25682U, 2572U, 45419U, 26716U, 25330U, 19467U, 46141U, 27638U, |
| 15634 | 26022U, 15659U, 47243U, 46845U, 28544U, 25844U, 6152U, 47180U, |
| 15635 | 46785U, 28496U, 25492U, 21680U, 47305U, 46904U, 28592U, 26094U, |
| 15636 | 12009U, 45745U, 27102U, 25626U, 2502U, 45355U, 26636U, 25274U, |
| 15637 | 19397U, 46081U, 27562U, 25970U, 15592U, 45935U, 27376U, 25788U, |
| 15638 | 6085U, 45545U, 26910U, 25436U, 11927U, 45657U, 26990U, 25522U, |
| 15639 | 2420U, 45267U, 26524U, 25170U, 19315U, 45999U, 27456U, 25874U, |
| 15640 | 15530U, 27224U, 25712U, 47010U, 28722U, 6023U, 26758U, 25360U, |
| 15641 | 46942U, 28638U, 21610U, 27678U, 26050U, 47078U, 28806U, 12098U, |
| 15642 | 45826U, 27203U, 25697U, 2583U, 45436U, 26737U, 25345U, 19477U, |
| 15643 | 46157U, 27658U, 26036U, 15670U, 47264U, 46865U, 28568U, 25859U, |
| 15644 | 6163U, 47201U, 46805U, 28520U, 25507U, 21690U, 47325U, 46923U, |
| 15645 | 28615U, 26108U, 12029U, 45777U, 27142U, 25654U, 2522U, 45387U, |
| 15646 | 26676U, 25302U, 19415U, 46111U, 27600U, 25996U, 15612U, 45967U, |
| 15647 | 27416U, 25816U, 6105U, 45577U, 26950U, 25464U, 11953U, 45685U, |
| 15648 | 27026U, 25546U, 2446U, 45295U, 26560U, 25194U, 19338U, 46025U, |
| 15649 | 27490U, 25896U, 15556U, 27260U, 25736U, 47044U, 28764U, 6049U, |
| 15650 | 26794U, 25384U, 46976U, 28680U, 21633U, 27712U, 26072U, 47110U, |
| 15651 | 28846U, 26334U, 23415U, 26168U, 23480U, 26418U, 23496U, 26274U, |
| 15652 | 28911U, 30683U, 34681U, 42064U, 52468U, 41416U, 42098U, 52504U, |
| 15653 | 41450U, 41964U, 52362U, 41316U, 42008U, 52408U, 41360U, 41940U, |
| 15654 | 52071U, 41042U, 42038U, 52440U, 41390U, 31919U, 8426U, 32174U, |
| 15655 | 8435U, 40629U, 48199U, 40853U, 48423U, 19939U, 3959U, 13447U, |
| 15656 | 5218U, 14667U, 20791U, 20186U, 4288U, 13776U, 5597U, 15046U, |
| 15657 | 21054U, 40560U, 48130U, 40784U, 48354U, 19894U, 3874U, 13362U, |
| 15658 | 5149U, 14598U, 20713U, 20141U, 4203U, 13691U, 5528U, 14977U, |
| 15659 | 20976U, 24435U, 30349U, 3970U, 13458U, 4299U, 13787U, 9158U, |
| 15660 | 4992U, 14441U, 9408U, 5371U, 14820U, 34248U, 40477U, 48054U, |
| 15661 | 40701U, 48271U, 40636U, 48206U, 40860U, 48430U, 3539U, 13027U, |
| 15662 | 4751U, 14200U, 19501U, 3152U, 12640U, 4423U, 13911U, 20265U, |
| 15663 | 28989U, 30763U, 3998U, 13486U, 4327U, 13815U, 9278U, 5125U, |
| 15664 | 14574U, 9528U, 5504U, 14953U, 34853U, 40581U, 48151U, 40805U, |
| 15665 | 48375U, 40654U, 48224U, 40878U, 48448U, 3671U, 13159U, 4838U, |
| 15666 | 14287U, 19613U, 3440U, 12928U, 4639U, 14088U, 20468U, 23572U, |
| 15667 | 29170U, 34165U, 30960U, 33814U, 9290U, 5137U, 14586U, 9540U, |
| 15668 | 5516U, 14965U, 3388U, 12876U, 20421U, 30727U, 28933U, 34725U, |
| 15669 | 34747U, 35070U, 34209U, 34187U, 19646U, 8677U, 2624U, 3460U, |
| 15670 | 9052U, 2724U, 12948U, 4672U, 14121U, 20486U, 34703U, 34537U, |
| 15671 | 35020U, 24382U, 36193U, 8413U, 24321U, 24792U, 48U, 94U, |
| 15672 | 8373U, 33U, 34149U, 34204U, 34524U, 35008U, 24371U, 36181U, |
| 15673 | 8400U, 24303U, 24781U, 25U, 34140U, 24849U, 30542U, 9642U, |
| 15674 | 21552U, 3984U, 13472U, 4313U, 13801U, 9266U, 5113U, 14562U, |
| 15675 | 9516U, 5492U, 14941U, 34456U, 40553U, 48123U, 40777U, 48347U, |
| 15676 | 40925U, 48457U, 40645U, 48215U, 40869U, 48439U, 3659U, 13147U, |
| 15677 | 4826U, 14275U, 19562U, 3268U, 12756U, 4578U, 14027U, 20320U, |
| 15678 | 38622U, 47960U, 3378U, 12866U, 4588U, 14037U, 24745U, 30476U, |
| 15679 | 34379U, 47844U, 40546U, 40770U, 48340U, 38542U, 47880U, 38515U, |
| 15680 | 47853U, 38567U, 47905U, 24420U, 30342U, 34241U, 28974U, 30756U, |
| 15681 | 34846U, 24842U, 30519U, 34449U, 38616U, 47954U, 38656U, 3502U, |
| 15682 | 12990U, 4714U, 14163U, 47984U, 19820U, 3800U, 13288U, 4979U, |
| 15683 | 14428U, 20645U, 20067U, 4129U, 13617U, 5358U, 14807U, 20908U, |
| 15684 | 19833U, 3813U, 13301U, 5028U, 14477U, 20657U, 20080U, 4142U, |
| 15685 | 13630U, 5407U, 14856U, 20920U, 41579U, 42153U, 15161U, 5701U, |
| 15686 | 21197U, 41933U, 42507U, 16183U, 6702U, 22135U, 17284U, 7904U, |
| 15687 | 22992U, 41756U, 42330U, 15960U, 6489U, 21959U, 17103U, 7733U, |
| 15688 | 22840U, 19582U, 3409U, 12897U, 4608U, 14057U, 20440U, 19797U, |
| 15689 | 8759U, 3777U, 9134U, 13265U, 4944U, 14393U, 20624U, 20044U, |
| 15690 | 8877U, 4106U, 9384U, 13594U, 5323U, 14772U, 20887U, 3614U, |
| 15691 | 13102U, 9013U, 4539U, 3644U, 13132U, 9039U, 4565U, 3567U, |
| 15692 | 13055U, 4779U, 14228U, 3207U, 12695U, 4478U, 13966U, 3629U, |
| 15693 | 13117U, 9026U, 4552U, 4354U, 13842U, 21076U, 3912U, 13400U, |
| 15694 | 20748U, 4241U, 13729U, 21011U, 19531U, 3182U, 12670U, 4453U, |
| 15695 | 13941U, 20292U, 3551U, 13039U, 4763U, 14212U, 3193U, 12681U, |
| 15696 | 4464U, 13952U, 3598U, 13086U, 4810U, 14259U, 3234U, 12722U, |
| 15697 | 4505U, 13993U, 3582U, 13070U, 4794U, 14243U, 3220U, 12708U, |
| 15698 | 4491U, 13979U, 19858U, 8783U, 3838U, 9218U, 13326U, 5065U, |
| 15699 | 14514U, 20680U, 20105U, 8901U, 4167U, 9468U, 13655U, 5444U, |
| 15700 | 14893U, 20943U, 3898U, 13386U, 20735U, 4227U, 13715U, 20998U, |
| 15701 | 3364U, 12852U, 20408U, 19677U, 8698U, 3513U, 9073U, 13001U, |
| 15702 | 4725U, 14174U, 20514U, 20197U, 8960U, 4341U, 9599U, 13829U, |
| 15703 | 5608U, 15057U, 21064U, 19846U, 8771U, 3826U, 9206U, 13314U, |
| 15704 | 5053U, 14502U, 20669U, 19690U, 8711U, 3526U, 9086U, 13014U, |
| 15705 | 4738U, 14187U, 20526U, 20093U, 8889U, 4155U, 9456U, 13643U, |
| 15706 | 5432U, 14881U, 20932U, 3885U, 13373U, 20723U, 4214U, 13702U, |
| 15707 | 20986U, 3351U, 12839U, 20396U, 19749U, 8747U, 3729U, 9122U, |
| 15708 | 13217U, 4896U, 14345U, 20580U, 19996U, 8865U, 4058U, 9372U, |
| 15709 | 13546U, 5275U, 14724U, 20843U, 3303U, 12791U, 20352U, 38587U, |
| 15710 | 40527U, 48104U, 40751U, 48321U, 47925U, 40595U, 48165U, 40819U, |
| 15711 | 48389U, 19352U, 21647U, 11901U, 19292U, 15504U, 21587U, 11943U, |
| 15712 | 2436U, 19329U, 15546U, 6039U, 21624U, 19772U, 3752U, 13240U, |
| 15713 | 4919U, 14368U, 20601U, 20019U, 4081U, 13569U, 5298U, 14747U, |
| 15714 | 20864U, 24555U, 30368U, 41586U, 42160U, 41763U, 42337U, 34267U, |
| 15715 | 24895U, 30579U, 41626U, 42200U, 41803U, 42377U, 34508U, 25031U, |
| 15716 | 30603U, 41636U, 42210U, 41813U, 42387U, 34516U, 25162U, 30659U, |
| 15717 | 41646U, 42220U, 41823U, 42397U, 34649U, 28941U, 30705U, 34733U, |
| 15718 | 29212U, 31002U, 41656U, 42230U, 41833U, 42407U, 35076U, 29251U, |
| 15719 | 31041U, 41666U, 42240U, 41843U, 42417U, 35115U, 19871U, 8796U, |
| 15720 | 3851U, 9231U, 13339U, 5078U, 14527U, 20692U, 20118U, 8914U, |
| 15721 | 4180U, 9481U, 13668U, 5457U, 14906U, 20955U, 3328U, 12816U, |
| 15722 | 20375U, 19905U, 8819U, 3925U, 9302U, 13413U, 5160U, 14609U, |
| 15723 | 20760U, 20152U, 8937U, 4254U, 9552U, 13742U, 5539U, 14988U, |
| 15724 | 21023U, 38595U, 40536U, 48113U, 40760U, 48330U, 47933U, 40604U, |
| 15725 | 48174U, 40828U, 48398U, 19714U, 8724U, 3694U, 9099U, 13182U, |
| 15726 | 4861U, 14310U, 20548U, 19961U, 8842U, 4023U, 9349U, 13511U, |
| 15727 | 5240U, 14689U, 20811U, 3278U, 12766U, 20329U, 24886U, 34499U, |
| 15728 | 29071U, 31094U, 33490U, 31182U, 28886U, 30667U, 34657U, 24730U, |
| 15729 | 30461U, 34332U, 29055U, 30873U, 34969U, 29047U, 30865U, 34896U, |
| 15730 | 15234U, 5784U, 21333U, 15213U, 5753U, 21314U, 9254U, 5101U, |
| 15731 | 14550U, 9504U, 5480U, 14929U, 19666U, 8687U, 3491U, 9062U, |
| 15732 | 12979U, 4703U, 14152U, 20504U, 19883U, 8808U, 3863U, 9243U, |
| 15733 | 13351U, 5090U, 14539U, 20703U, 20130U, 8926U, 4192U, 9493U, |
| 15734 | 13680U, 5469U, 14918U, 20966U, 3340U, 12828U, 20386U, 19917U, |
| 15735 | 8831U, 3937U, 9314U, 13425U, 5172U, 14621U, 20771U, 20164U, |
| 15736 | 8949U, 4266U, 9564U, 13754U, 5551U, 15000U, 21034U, 25114U, |
| 15737 | 30611U, 34581U, 25128U, 30625U, 34595U, 19542U, 8657U, 3248U, |
| 15738 | 8993U, 12736U, 4519U, 14007U, 20302U, 25142U, 30639U, 34609U, |
| 15739 | 23558U, 29117U, 30881U, 34977U, 19726U, 8736U, 3706U, 9111U, |
| 15740 | 13194U, 4873U, 14322U, 20559U, 19973U, 8854U, 4035U, 9361U, |
| 15741 | 13523U, 5252U, 14701U, 20822U, 19552U, 8667U, 3258U, 9003U, |
| 15742 | 12746U, 4529U, 14017U, 20311U, 11979U, 25584U, 2472U, 25232U, |
| 15743 | 19370U, 25931U, 45887U, 27316U, 45497U, 26850U, 46214U, 27765U, |
| 15744 | 11893U, 33421U, 46304U, 39075U, 49615U, 40256U, 50991U, 35183U, |
| 15745 | 46572U, 39257U, 49821U, 40390U, 51149U, 39798U, 50449U, 2396U, |
| 15746 | 33385U, 46244U, 38983U, 49511U, 40188U, 50911U, 35147U, 46512U, |
| 15747 | 39165U, 49717U, 40322U, 51069U, 39455U, 50046U, 8629U, 33403U, |
| 15748 | 46274U, 39029U, 49563U, 40222U, 50951U, 35165U, 46542U, 39211U, |
| 15749 | 49769U, 40356U, 51109U, 39702U, 50335U, 19285U, 33438U, 46333U, |
| 15750 | 39120U, 49666U, 40289U, 51030U, 35200U, 46601U, 39302U, 49872U, |
| 15751 | 40423U, 51188U, 40012U, 50702U, 15496U, 46442U, 27899U, 46710U, |
| 15752 | 28255U, 28076U, 28432U, 39900U, 50569U, 5999U, 46366U, 27807U, |
| 15753 | 46634U, 28163U, 27988U, 28344U, 39557U, 50166U, 9659U, 46404U, |
| 15754 | 27853U, 46672U, 28209U, 28032U, 28388U, 39734U, 50373U, 21580U, |
| 15755 | 46479U, 27944U, 46747U, 28300U, 28119U, 28475U, 40108U, 50816U, |
| 15756 | 11999U, 45729U, 27082U, 25612U, 2492U, 45339U, 26616U, 25260U, |
| 15757 | 19388U, 46066U, 27543U, 25957U, 15582U, 45919U, 27356U, 25774U, |
| 15758 | 6075U, 45529U, 26890U, 25422U, 11877U, 39766U, 50411U, 2380U, |
| 15759 | 39423U, 50008U, 19271U, 39982U, 50666U, 11919U, 39830U, 50487U, |
| 15760 | 2412U, 39487U, 50084U, 19308U, 40042U, 50738U, 15522U, 45857U, |
| 15761 | 38896U, 49412U, 39932U, 50607U, 6015U, 45467U, 38852U, 49362U, |
| 15762 | 39589U, 50204U, 21603U, 46186U, 38939U, 49461U, 40138U, 50852U, |
| 15763 | 12019U, 45761U, 27122U, 25640U, 2512U, 45371U, 26656U, 25288U, |
| 15764 | 19406U, 46096U, 27581U, 25983U, 15602U, 45951U, 27396U, 25802U, |
| 15765 | 6095U, 45561U, 26930U, 25450U, 11935U, 45671U, 27008U, 25534U, |
| 15766 | 2428U, 45281U, 26542U, 25182U, 19322U, 46012U, 27473U, 25885U, |
| 15767 | 15538U, 27242U, 25724U, 47027U, 28743U, 6031U, 26776U, 25372U, |
| 15768 | 46959U, 28659U, 21617U, 27695U, 26061U, 47094U, 28826U, 12039U, |
| 15769 | 45793U, 27162U, 25668U, 2532U, 45403U, 26696U, 25316U, 19424U, |
| 15770 | 46126U, 27619U, 26009U, 15622U, 45983U, 27436U, 25830U, 6115U, |
| 15771 | 45593U, 26970U, 25478U, 11961U, 45699U, 27044U, 25558U, 2454U, |
| 15772 | 45309U, 26578U, 25206U, 19345U, 46038U, 27507U, 25907U, 15564U, |
| 15773 | 27278U, 25748U, 47061U, 28785U, 6057U, 26812U, 25396U, 46993U, |
| 15774 | 28701U, 21640U, 27729U, 26083U, 47126U, 28866U, 26346U, 23423U, |
| 15775 | 26180U, 23488U, 26430U, 23504U, 26286U, 28949U, 30721U, 34741U, |
| 15776 | 42081U, 52486U, 41433U, 42114U, 52521U, 41466U, 41986U, 52385U, |
| 15777 | 41338U, 42023U, 52424U, 41375U, 41952U, 52084U, 41054U, 42051U, |
| 15778 | 52454U, 41403U, 24571U, 30412U, 3291U, 12779U, 20341U, 9170U, |
| 15779 | 5004U, 14453U, 9420U, 5383U, 14832U, 34294U, 9325U, 5194U, |
| 15780 | 14643U, 9575U, 5573U, 15022U, 40491U, 48068U, 40715U, 48285U, |
| 15781 | 19511U, 8637U, 3162U, 8973U, 12650U, 4433U, 13921U, 20274U, |
| 15782 | 31102U, 31190U, 38644U, 47972U, 88U, 8336U, 8514U, 45609U, |
| 15783 | 9675U, 45633U, 131U, 8444U, 8528U, 45621U, 9681U, 45645U, |
| 15784 | 24759U, 30482U, 34393U, 28917U, 30689U, 34687U, 29228U, 31018U, |
| 15785 | 35092U, 24835U, 30496U, 34435U, 24774U, 30489U, 34408U, 28925U, |
| 15786 | 30697U, 34695U, 29236U, 31026U, 35100U, 24855U, 30548U, 34462U, |
| 15787 | 12049U, 2542U, 19433U, 15632U, 6125U, 21656U, 19636U, 3450U, |
| 15788 | 12938U, 4662U, 14111U, 20477U, 29078U, 31111U, 33497U, 31199U, |
| 15789 | 25121U, 30618U, 34588U, 25135U, 30632U, 34602U, 25149U, 30646U, |
| 15790 | 34616U, 23565U, 29063U, 31085U, 33482U, 31173U, 23550U, 12109U, |
| 15791 | 19487U, 15681U, 6174U, 21700U, 12057U, 19440U, 15640U, 6133U, |
| 15792 | 21663U, 23391U, 26132U, 23773U, 26380U, 23447U, 26214U, 23813U, |
| 15793 | 26488U, 23400U, 26145U, 23790U, 26405U, 23471U, 26250U, 23822U, |
| 15794 | 26501U, 44097U, 51265U, 51824U, 44119U, 308U, 51287U, 51840U, |
| 15795 | 44727U, 331U, 33599U, 44127U, 51302U, 51854U, 44217U, 51381U, |
| 15796 | 163U, 36565U, 30305U, 23612U, 24160U, 31119U, 43737U, 49140U, |
| 15797 | 43717U, 38450U, 49120U, 44105U, 51273U, 51832U, 31216U, 36571U, |
| 15798 | 31259U, 38031U, 33099U, 8351U, 37145U, 32157U, 37377U, 44150U, |
| 15799 | 51325U, 51868U, 44177U, 51341U, 51884U, 47360U, 47400U, 47408U, |
| 15800 | 23603U, 23747U, 30418U, 36842U, 30318U, 36815U, 31431U, 24221U, |
| 15801 | 36807U, 29978U, 29958U, 105U, 8392U, 8520U, 34415U, 23844U, |
| 15802 | 23876U, 44193U, 51357U, 51906U, 35926U, 24360U, 23882U, 35724U, |
| 15803 | 47647U, 47541U, 23385U, 23616U, 37107U, 24081U, 29176U, 30966U, |
| 15804 | 30335U, 35632U, 32752U, 36387U, 29690U, 35578U, 32698U, 36243U, |
| 15805 | 29558U, 35662U, 32782U, 36413U, 29714U, 35606U, 32726U, 36304U, |
| 15806 | 29614U, 23765U, 26368U, 23439U, 26202U, 35431U, 36267U, 29580U, |
| 15807 | 179U, 21139U, 43865U, 51651U, 36326U, 29634U, 21231U, 37137U, |
| 15808 | 24099U, 29194U, 30984U, 35699U, 36350U, 29656U, 219U, 21278U, |
| 15809 | 43895U, 51683U, 35447U, 36291U, 29602U, 199U, 21157U, 43875U, |
| 15810 | 51667U, 35715U, 36374U, 29678U, 239U, 21296U, 43905U, 51699U, |
| 15811 | 36093U, 36437U, 29736U, 259U, 21360U, 43925U, 51722U, 29414U, |
| 15812 | 41560U, 44135U, 51310U, 44232U, 51396U, 171U, 33593U, 8366U, |
| 15813 | 34158U, 8384U, 23536U, 34421U, 15256U, 43847U, 15266U, 49275U, |
| 15814 | 24339U, 8304U, 24345U, 8311U, 33554U, 32438U, 38717U, 33563U, |
| 15815 | 33545U, 32430U, 38705U, 31777U, 43769U, 49172U, 51715U, 44158U, |
| 15816 | 51333U, 51876U, 44209U, 51373U, 51914U, 24126U, 31222U, 29964U, |
| 15817 | 35404U, 23924U, 277U, 21399U, 51736U, 210U, 21223U, 43886U, |
| 15818 | 51676U, 250U, 21306U, 43916U, 51708U, 24669U, 9868U, 17774U, |
| 15819 | 37263U, 24585U, 23988U, 37018U, 24034U, 9811U, 17715U, 35729U, |
| 15820 | 36709U, 10009U, 30850U, 23757U, 36833U, 23431U, 36824U, 44201U, |
| 15821 | 51365U, 37241U, 44073U, 51234U, 51800U, 9887U, 17791U, 37278U, |
| 15822 | 23871U, 44089U, 51257U, 51816U, 37161U, 36741U, 31425U, 32474U, |
| 15823 | 30300U, 9848U, 17756U, 37247U, 37002U, 9791U, 17697U, 24209U, |
| 15824 | 23639U, 35395U, 24427U, 37051U, 31321U, 23648U, 35412U, 24803U, |
| 15825 | 37069U, 23932U, 36529U, 23915U, 36520U, 24063U, 36595U, 28981U, |
| 15826 | 37089U, 24819U, 37079U, 23542U, 33536U, 34427U, 34195U, 31850U, |
| 15827 | 33840U, 24563U, 37060U, 23658U, 35422U, 31689U, 23942U, 36539U, |
| 15828 | 24072U, 36604U, 29039U, 37098U, 23799U, 26442U, 23512U, 26298U, |
| 15829 | 35268U, 9952U, 37033U, 9830U, 17732U, 35647U, 32767U, 36400U, |
| 15830 | 29702U, 35592U, 32712U, 36255U, 29569U, 35676U, 32796U, 36425U, |
| 15831 | 29725U, 35619U, 32739U, 36315U, 29624U, 31771U, 23837U, 37129U, |
| 15832 | 24090U, 29185U, 30975U, 30503U, 23782U, 26393U, 23463U, 26238U, |
| 15833 | 35439U, 36279U, 29591U, 189U, 21148U, 51659U, 36338U, 29645U, |
| 15834 | 21240U, 37153U, 24108U, 29203U, 30993U, 35707U, 36362U, 29667U, |
| 15835 | 229U, 21287U, 51691U, 36132U, 36448U, 29746U, 268U, 21368U, |
| 15836 | 51729U, 33849U, 44081U, 298U, 51242U, 51808U, 44716U, 318U, |
| 15837 | 23623U, 9741U, 30376U, 23962U, 9773U, 30896U, 23667U, 30392U, |
| 15838 | 44185U, 51349U, 51892U, 23909U, 44282U, 51445U, 51955U, 36515U, |
| 15839 | 23597U, 35388U, 36548U, 9896U, 17799U, 37285U, 37175U, 29907U, |
| 15840 | 36755U, 9858U, 17765U, 37255U, 37010U, 9801U, 17706U, 31313U, |
| 15841 | 31329U, 31697U, 9877U, 17782U, 37270U, 37025U, 9820U, 17723U, |
| 15842 | 17748U, 17688U, 35275U, 9961U, 37040U, 9839U, 17740U, 23631U, |
| 15843 | 9751U, 30384U, 23975U, 9782U, 30909U, 34469U, 24155U, 51467U, |
| 15844 | 8549U, 21216U, 33235U, 43776U, 51295U, 43987U, 51226U, 33605U, |
| 15845 | 24967U, 44225U, 51389U, 24117U, 24175U, 36040U, 31356U, 49222U, |
| 15846 | 43854U, 49288U, 37047U, 34550U, 38037U, 37390U, 37372U, 32677U, |
| 15847 | 51207U, 21353U, 49179U, 34623U, 33901U, 35933U, 35875U, 47601U, |
| 15848 | 47626U, 47668U, 23456U, 43685U, 49097U, 43723U, 49126U, 23897U, |
| 15849 | 30829U, 43785U, 43934U, 49195U, 43995U, 44143U, 51318U, 44240U, |
| 15850 | 51404U, 49230U, 21392U, 49282U, 31880U, 32866U, 34182U, 24577U, |
| 15851 | 33194U, 30844U, 36715U, 10017U, 30858U, 33962U, 23904U, 24141U, |
| 15852 | 24972U, 26263U, 43692U, 49104U, 43730U, 49133U, 43811U, 49216U, |
| 15853 | 44003U, 8542U, 21178U, 51250U, 43979U, 24366U, 23969U, 30903U, |
| 15854 | 33041U, 36510U, 29913U, 23982U, 30916U, 77U, |
| 15855 | }; |
| 15856 | |
| 15857 | extern const uint8_t ARMInstrDeprecationFeatures[] = { |
| 15858 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15859 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15860 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15861 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15862 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15863 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15864 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15865 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15866 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15867 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15868 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15869 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15870 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15871 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15872 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15873 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15874 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15875 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15876 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15877 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15878 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15879 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15880 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15881 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15882 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15883 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15884 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15885 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15886 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15887 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15888 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15889 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15890 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15891 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15892 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15893 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15894 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15895 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15896 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15897 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15898 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15899 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15900 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15901 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15902 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15903 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15904 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15905 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15906 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15907 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15908 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15909 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15910 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15911 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15912 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15913 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15914 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15915 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15916 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15917 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15918 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15919 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15920 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15921 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15922 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15923 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15924 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15925 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15926 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15927 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15928 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15929 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15930 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15931 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15932 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15933 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15934 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15935 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15936 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15937 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15938 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15939 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15940 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15941 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15942 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15943 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15944 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15945 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15946 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15947 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15948 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15949 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15950 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15951 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15952 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15953 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15954 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15955 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15956 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15957 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15958 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15959 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15960 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15961 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15962 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15963 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15964 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15965 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15966 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15967 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15968 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15969 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15970 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15971 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15972 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15973 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15974 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15975 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15976 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15977 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15978 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15979 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15980 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15981 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15982 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15983 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15984 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15985 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15986 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15987 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15988 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15989 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15990 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15991 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15992 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15993 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15994 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15995 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15996 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15997 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15998 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 15999 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16000 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16001 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16002 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16003 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16004 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16005 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16006 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16007 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16008 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16009 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16010 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16011 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16012 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16013 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16014 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16015 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16016 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16017 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16018 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16019 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16020 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16021 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16022 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16023 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16024 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16025 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16026 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16027 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16028 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16029 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16030 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16031 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16032 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16033 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16034 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16035 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16036 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16037 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16038 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16039 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16040 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16041 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16042 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16043 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16044 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16045 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16046 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16047 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16048 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16049 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16050 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16051 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16052 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16053 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16054 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16055 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16056 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16057 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16058 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16059 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16060 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16061 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16062 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16063 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16064 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16065 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16066 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16067 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16068 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16069 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16070 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16071 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16072 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16073 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16074 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16075 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16076 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16077 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16078 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16079 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16080 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16081 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16082 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16083 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16084 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16085 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16086 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16087 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16088 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16089 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16090 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16091 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16092 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16093 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16094 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16095 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16096 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16097 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16098 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16099 | uint8_t(-1), uint8_t(-1), uint8_t(-1), ARM::HasV8Ops, uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16100 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16101 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16102 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16103 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16104 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16105 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16106 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16107 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16108 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16109 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16110 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16111 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16112 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16113 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16114 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16115 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16116 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16117 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16118 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16119 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16120 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16121 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16122 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16123 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16124 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16125 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16126 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16127 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16128 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16129 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16130 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16131 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16132 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16133 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16134 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16135 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16136 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16137 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16138 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16139 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16140 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16141 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16142 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16143 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16144 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16145 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16146 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16147 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16148 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16149 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16150 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16151 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16152 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16153 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16154 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16155 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16156 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16157 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16158 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16159 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16160 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16161 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16162 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16163 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16164 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16165 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16166 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16167 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16168 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16169 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16170 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16171 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16172 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16173 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16174 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16175 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16176 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16177 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16178 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16179 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16180 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16181 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16182 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16183 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16184 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16185 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16186 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16187 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16188 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16189 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16190 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16191 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16192 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16193 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16194 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16195 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16196 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16197 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16198 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16199 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16200 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16201 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16202 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16203 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16204 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16205 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16206 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16207 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16208 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16209 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16210 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16211 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16212 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16213 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16214 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16215 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16216 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16217 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16218 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16219 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16220 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16221 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16222 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16223 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16224 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16225 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16226 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16227 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16228 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16229 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16230 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16231 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16232 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16233 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16234 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16235 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16236 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16237 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16238 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16239 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16240 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16241 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16242 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16243 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16244 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16245 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16246 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16247 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16248 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16249 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16250 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16251 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16252 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16253 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16254 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16255 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16256 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16257 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16258 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16259 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16260 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16261 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16262 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16263 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16264 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16265 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16266 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16267 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16268 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16269 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16270 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16271 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16272 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16273 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16274 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16275 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16276 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16277 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16278 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16279 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16280 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16281 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16282 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16283 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16284 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16285 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16286 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16287 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16288 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16289 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16290 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16291 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16292 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16293 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16294 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16295 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16296 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16297 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16298 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16299 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16300 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16301 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16302 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16303 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16304 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16305 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16306 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16307 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16308 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16309 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16310 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16311 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16312 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16313 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16314 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16315 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16316 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16317 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16318 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16319 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16320 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16321 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16322 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16323 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16324 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16325 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16326 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16327 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16328 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16329 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16330 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16331 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16332 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16333 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16334 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16335 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16336 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16337 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16338 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16339 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16340 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16341 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16342 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16343 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16344 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16345 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16346 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16347 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16348 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16349 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16350 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16351 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16352 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16353 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16354 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16355 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16356 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16357 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16358 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16359 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16360 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16361 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16362 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16363 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16364 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16365 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16366 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16367 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16368 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16369 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16370 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16371 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16372 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16373 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16374 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16375 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16376 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16377 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16378 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16379 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16380 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16381 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16382 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16383 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16384 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16385 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16386 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16387 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16388 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16389 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16390 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16391 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16392 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16393 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16394 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16395 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16396 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16397 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16398 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16399 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16400 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16401 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16402 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16403 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16404 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16405 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16406 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16407 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16408 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16409 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16410 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16411 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16412 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16413 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16414 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16415 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16416 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16417 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16418 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16419 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16420 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16421 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16422 | ARM::HasV8Ops, uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16423 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16424 | uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), |
| 16425 | }; |
| 16426 | |
| 16427 | bool ARMInstrComplexDeprecationInfo(MCInst &Inst, const MCSubtargetInfo &STI, std::string &Info) { |
| 16428 | switch (Inst.getOpcode()) { |
| 16429 | case ARM::LDMDA: return getARMLoadDeprecationInfo(Inst, STI, Info); |
| 16430 | case ARM::LDMDA_UPD: return getARMLoadDeprecationInfo(Inst, STI, Info); |
| 16431 | case ARM::LDMDB: return getARMLoadDeprecationInfo(Inst, STI, Info); |
| 16432 | case ARM::LDMDB_UPD: return getARMLoadDeprecationInfo(Inst, STI, Info); |
| 16433 | case ARM::LDMIA: return getARMLoadDeprecationInfo(Inst, STI, Info); |
| 16434 | case ARM::LDMIA_UPD: return getARMLoadDeprecationInfo(Inst, STI, Info); |
| 16435 | case ARM::LDMIB: return getARMLoadDeprecationInfo(Inst, STI, Info); |
| 16436 | case ARM::LDMIB_UPD: return getARMLoadDeprecationInfo(Inst, STI, Info); |
| 16437 | case ARM::MCR: return getMCRDeprecationInfo(Inst, STI, Info); |
| 16438 | case ARM::MRC: return getMRCDeprecationInfo(Inst, STI, Info); |
| 16439 | case ARM::STMDA: return getARMStoreDeprecationInfo(Inst, STI, Info); |
| 16440 | case ARM::STMDA_UPD: return getARMStoreDeprecationInfo(Inst, STI, Info); |
| 16441 | case ARM::STMDB: return getARMStoreDeprecationInfo(Inst, STI, Info); |
| 16442 | case ARM::STMDB_UPD: return getARMStoreDeprecationInfo(Inst, STI, Info); |
| 16443 | case ARM::STMIA: return getARMStoreDeprecationInfo(Inst, STI, Info); |
| 16444 | case ARM::STMIA_UPD: return getARMStoreDeprecationInfo(Inst, STI, Info); |
| 16445 | case ARM::STMIB: return getARMStoreDeprecationInfo(Inst, STI, Info); |
| 16446 | case ARM::STMIB_UPD: return getARMStoreDeprecationInfo(Inst, STI, Info); |
| 16447 | case ARM::t2MCR: return getMCRDeprecationInfo(Inst, STI, Info); |
| 16448 | } |
| 16449 | return false; |
| 16450 | } |
| 16451 | |
| 16452 | extern const int16_t ARMRegClassByHwModeTables[2][1] = { |
| 16453 | { // DefaultMode |
| 16454 | ARM::GPRRegClassID, // arm_ptr_rc |
| 16455 | }, |
| 16456 | { // Thumb1OnlyMode |
| 16457 | ARM::tGPRRegClassID, // arm_ptr_rc |
| 16458 | }, |
| 16459 | }; |
| 16460 | |
| 16461 | static inline void InitARMMCInstrInfo(MCInstrInfo *II) { |
| 16462 | II->InitMCInstrInfo(ARMDescs.Insts, ARMInstrNameIndices, ARMInstrNameData, ARMInstrDeprecationFeatures, ARMInstrComplexDeprecationInfo, 4534, &ARMRegClassByHwModeTables[0][0], 1); |
| 16463 | } |
| 16464 | |
| 16465 | |
| 16466 | } // namespace llvm |
| 16467 | |
| 16468 | #endif // GET_INSTRINFO_MC_DESC |
| 16469 | |
| 16470 | #ifdef GET_INSTRINFO_HEADER |
| 16471 | #undef GET_INSTRINFO_HEADER |
| 16472 | |
| 16473 | namespace llvm { |
| 16474 | |
| 16475 | struct ARMGenInstrInfo : public TargetInstrInfo { |
| 16476 | explicit ARMGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
| 16477 | ~ARMGenInstrInfo() override = default; |
| 16478 | }; |
| 16479 | extern const int16_t ARMRegClassByHwModeTables[2][1]; |
| 16480 | |
| 16481 | } // namespace llvm |
| 16482 | |
| 16483 | namespace llvm::ARM { |
| 16484 | |
| 16485 | constexpr unsigned SUBOP_VecListFourDByteIndexed_Vd = 0; |
| 16486 | constexpr unsigned SUBOP_VecListFourDByteIndexed_idx = 1; |
| 16487 | constexpr unsigned SUBOP_VecListFourDHWordIndexed_Vd = 0; |
| 16488 | constexpr unsigned SUBOP_VecListFourDHWordIndexed_idx = 1; |
| 16489 | constexpr unsigned SUBOP_VecListFourDWordIndexed_Vd = 0; |
| 16490 | constexpr unsigned SUBOP_VecListFourDWordIndexed_idx = 1; |
| 16491 | constexpr unsigned SUBOP_VecListFourQHWordIndexed_Vd = 0; |
| 16492 | constexpr unsigned SUBOP_VecListFourQHWordIndexed_idx = 1; |
| 16493 | constexpr unsigned SUBOP_VecListFourQWordIndexed_Vd = 0; |
| 16494 | constexpr unsigned SUBOP_VecListFourQWordIndexed_idx = 1; |
| 16495 | constexpr unsigned SUBOP_VecListOneDByteIndexed_Vd = 0; |
| 16496 | constexpr unsigned SUBOP_VecListOneDByteIndexed_idx = 1; |
| 16497 | constexpr unsigned SUBOP_VecListOneDHWordIndexed_Vd = 0; |
| 16498 | constexpr unsigned SUBOP_VecListOneDHWordIndexed_idx = 1; |
| 16499 | constexpr unsigned SUBOP_VecListOneDWordIndexed_Vd = 0; |
| 16500 | constexpr unsigned SUBOP_VecListOneDWordIndexed_idx = 1; |
| 16501 | constexpr unsigned SUBOP_VecListThreeDByteIndexed_Vd = 0; |
| 16502 | constexpr unsigned SUBOP_VecListThreeDByteIndexed_idx = 1; |
| 16503 | constexpr unsigned SUBOP_VecListThreeDHWordIndexed_Vd = 0; |
| 16504 | constexpr unsigned SUBOP_VecListThreeDHWordIndexed_idx = 1; |
| 16505 | constexpr unsigned SUBOP_VecListThreeDWordIndexed_Vd = 0; |
| 16506 | constexpr unsigned SUBOP_VecListThreeDWordIndexed_idx = 1; |
| 16507 | constexpr unsigned SUBOP_VecListThreeQHWordIndexed_Vd = 0; |
| 16508 | constexpr unsigned SUBOP_VecListThreeQHWordIndexed_idx = 1; |
| 16509 | constexpr unsigned SUBOP_VecListThreeQWordIndexed_Vd = 0; |
| 16510 | constexpr unsigned SUBOP_VecListThreeQWordIndexed_idx = 1; |
| 16511 | constexpr unsigned SUBOP_VecListTwoDByteIndexed_Vd = 0; |
| 16512 | constexpr unsigned SUBOP_VecListTwoDByteIndexed_idx = 1; |
| 16513 | constexpr unsigned SUBOP_VecListTwoDHWordIndexed_Vd = 0; |
| 16514 | constexpr unsigned SUBOP_VecListTwoDHWordIndexed_idx = 1; |
| 16515 | constexpr unsigned SUBOP_VecListTwoDWordIndexed_Vd = 0; |
| 16516 | constexpr unsigned SUBOP_VecListTwoDWordIndexed_idx = 1; |
| 16517 | constexpr unsigned SUBOP_VecListTwoQHWordIndexed_Vd = 0; |
| 16518 | constexpr unsigned SUBOP_VecListTwoQHWordIndexed_idx = 1; |
| 16519 | constexpr unsigned SUBOP_VecListTwoQWordIndexed_Vd = 0; |
| 16520 | constexpr unsigned SUBOP_VecListTwoQWordIndexed_idx = 1; |
| 16521 | constexpr unsigned SUBOP_addr_offset_none_base = 0; |
| 16522 | constexpr unsigned SUBOP_addrmode3_base = 0; |
| 16523 | constexpr unsigned SUBOP_addrmode3_offsreg = 1; |
| 16524 | constexpr unsigned SUBOP_addrmode3_offsimm = 2; |
| 16525 | constexpr unsigned SUBOP_addrmode3_pre_base = 0; |
| 16526 | constexpr unsigned SUBOP_addrmode3_pre_offsreg = 1; |
| 16527 | constexpr unsigned SUBOP_addrmode3_pre_offsimm = 2; |
| 16528 | constexpr unsigned SUBOP_addrmode5_base = 0; |
| 16529 | constexpr unsigned SUBOP_addrmode5_pre_base = 0; |
| 16530 | constexpr unsigned SUBOP_addrmode5fp16_base = 0; |
| 16531 | constexpr unsigned SUBOP_addrmode6_addr = 0; |
| 16532 | constexpr unsigned SUBOP_addrmode6_align = 1; |
| 16533 | constexpr unsigned SUBOP_addrmode6align16_addr = 0; |
| 16534 | constexpr unsigned SUBOP_addrmode6align16_align = 1; |
| 16535 | constexpr unsigned SUBOP_addrmode6align32_addr = 0; |
| 16536 | constexpr unsigned SUBOP_addrmode6align32_align = 1; |
| 16537 | constexpr unsigned SUBOP_addrmode6align64_addr = 0; |
| 16538 | constexpr unsigned SUBOP_addrmode6align64_align = 1; |
| 16539 | constexpr unsigned SUBOP_addrmode6align64or128_addr = 0; |
| 16540 | constexpr unsigned SUBOP_addrmode6align64or128_align = 1; |
| 16541 | constexpr unsigned SUBOP_addrmode6align64or128or256_addr = 0; |
| 16542 | constexpr unsigned SUBOP_addrmode6align64or128or256_align = 1; |
| 16543 | constexpr unsigned SUBOP_addrmode6alignNone_addr = 0; |
| 16544 | constexpr unsigned SUBOP_addrmode6alignNone_align = 1; |
| 16545 | constexpr unsigned SUBOP_addrmode6dup_addr = 0; |
| 16546 | constexpr unsigned SUBOP_addrmode6dupalign16_addr = 0; |
| 16547 | constexpr unsigned SUBOP_addrmode6dupalign32_addr = 0; |
| 16548 | constexpr unsigned SUBOP_addrmode6dupalign64_addr = 0; |
| 16549 | constexpr unsigned SUBOP_addrmode6dupalign64or128_addr = 0; |
| 16550 | constexpr unsigned SUBOP_addrmode6dupalignNone_addr = 0; |
| 16551 | constexpr unsigned SUBOP_addrmode6oneL32_addr = 0; |
| 16552 | constexpr unsigned SUBOP_addrmode_imm12_base = 0; |
| 16553 | constexpr unsigned SUBOP_addrmode_imm12_offsimm = 1; |
| 16554 | constexpr unsigned SUBOP_addrmode_imm12_pre_base = 0; |
| 16555 | constexpr unsigned SUBOP_addrmode_imm12_pre_offsimm = 1; |
| 16556 | constexpr unsigned SUBOP_addrmode_tbb_Rn = 0; |
| 16557 | constexpr unsigned SUBOP_addrmode_tbb_Rm = 1; |
| 16558 | constexpr unsigned SUBOP_addrmode_tbh_Rn = 0; |
| 16559 | constexpr unsigned SUBOP_addrmode_tbh_Rm = 1; |
| 16560 | constexpr unsigned SUBOP_ldst_so_reg_base = 0; |
| 16561 | constexpr unsigned SUBOP_ldst_so_reg_offsreg = 1; |
| 16562 | constexpr unsigned SUBOP_ldst_so_reg_shift = 2; |
| 16563 | constexpr unsigned SUBOP_t2_addr_offset_none_base = 0; |
| 16564 | constexpr unsigned SUBOP_t2_nosp_addr_offset_none_base = 0; |
| 16565 | constexpr unsigned SUBOP_t2addrmode_imm0_1020s4_base = 0; |
| 16566 | constexpr unsigned SUBOP_t2addrmode_imm0_1020s4_offsimm = 1; |
| 16567 | constexpr unsigned SUBOP_t2addrmode_imm7s4_base = 0; |
| 16568 | constexpr unsigned SUBOP_t2addrmode_imm7s4_offsimm = 1; |
| 16569 | constexpr unsigned SUBOP_t2addrmode_imm7s4_pre_base = 0; |
| 16570 | constexpr unsigned SUBOP_t2addrmode_imm7s4_pre_offsimm = 1; |
| 16571 | constexpr unsigned SUBOP_t2addrmode_imm8_base = 0; |
| 16572 | constexpr unsigned SUBOP_t2addrmode_imm8_offsimm = 1; |
| 16573 | constexpr unsigned SUBOP_t2addrmode_imm8_pre_base = 0; |
| 16574 | constexpr unsigned SUBOP_t2addrmode_imm8_pre_offsimm = 1; |
| 16575 | constexpr unsigned SUBOP_t2addrmode_imm8s4_base = 0; |
| 16576 | constexpr unsigned SUBOP_t2addrmode_imm8s4_offsimm = 1; |
| 16577 | constexpr unsigned SUBOP_t2addrmode_imm8s4_pre_base = 0; |
| 16578 | constexpr unsigned SUBOP_t2addrmode_imm8s4_pre_offsimm = 1; |
| 16579 | constexpr unsigned SUBOP_t2addrmode_imm12_base = 0; |
| 16580 | constexpr unsigned SUBOP_t2addrmode_imm12_offsimm = 1; |
| 16581 | constexpr unsigned SUBOP_t2addrmode_negimm8_base = 0; |
| 16582 | constexpr unsigned SUBOP_t2addrmode_negimm8_offsimm = 1; |
| 16583 | constexpr unsigned SUBOP_t2addrmode_posimm8_base = 0; |
| 16584 | constexpr unsigned SUBOP_t2addrmode_posimm8_offsimm = 1; |
| 16585 | constexpr unsigned SUBOP_t2addrmode_so_reg_base = 0; |
| 16586 | constexpr unsigned SUBOP_t2addrmode_so_reg_offsreg = 1; |
| 16587 | constexpr unsigned SUBOP_t2addrmode_so_reg_offsimm = 2; |
| 16588 | constexpr unsigned SUBOP_t_addr_offset_none_base = 0; |
| 16589 | constexpr unsigned SUBOP_t_addrmode_is1_base = 0; |
| 16590 | constexpr unsigned SUBOP_t_addrmode_is1_offsimm = 1; |
| 16591 | constexpr unsigned SUBOP_t_addrmode_is2_base = 0; |
| 16592 | constexpr unsigned SUBOP_t_addrmode_is2_offsimm = 1; |
| 16593 | constexpr unsigned SUBOP_t_addrmode_is4_base = 0; |
| 16594 | constexpr unsigned SUBOP_t_addrmode_is4_offsimm = 1; |
| 16595 | constexpr unsigned SUBOP_t_addrmode_rr_base = 0; |
| 16596 | constexpr unsigned SUBOP_t_addrmode_rr_offsreg = 1; |
| 16597 | constexpr unsigned SUBOP_t_addrmode_rr_sext_base = 0; |
| 16598 | constexpr unsigned SUBOP_t_addrmode_rr_sext_offsreg = 1; |
| 16599 | constexpr unsigned SUBOP_t_addrmode_rrs1_base = 0; |
| 16600 | constexpr unsigned SUBOP_t_addrmode_rrs1_offsreg = 1; |
| 16601 | constexpr unsigned SUBOP_t_addrmode_rrs2_base = 0; |
| 16602 | constexpr unsigned SUBOP_t_addrmode_rrs2_offsreg = 1; |
| 16603 | constexpr unsigned SUBOP_t_addrmode_rrs4_base = 0; |
| 16604 | constexpr unsigned SUBOP_t_addrmode_rrs4_offsreg = 1; |
| 16605 | constexpr unsigned SUBOP_t_addrmode_sp_base = 0; |
| 16606 | constexpr unsigned SUBOP_t_addrmode_sp_offsimm = 1; |
| 16607 | constexpr unsigned SUBOP_vpred_n_cond = 0; |
| 16608 | constexpr unsigned SUBOP_vpred_n_cond_reg = 1; |
| 16609 | constexpr unsigned SUBOP_vpred_n_tp_reg = 2; |
| 16610 | constexpr unsigned SUBOP_vpred_r_cond = 0; |
| 16611 | constexpr unsigned SUBOP_vpred_r_cond_reg = 1; |
| 16612 | constexpr unsigned SUBOP_vpred_r_tp_reg = 2; |
| 16613 | constexpr unsigned SUBOP_vpred_r_inactive = 3; |
| 16614 | |
| 16615 | } // namespace llvm::ARM |
| 16616 | |
| 16617 | #endif // GET_INSTRINFO_HEADER |
| 16618 | |
| 16619 | #ifdef GET_INSTRINFO_HELPER_DECLS |
| 16620 | #undef GET_INSTRINFO_HELPER_DECLS |
| 16621 | |
| 16622 | |
| 16623 | #endif // GET_INSTRINFO_HELPER_DECLS |
| 16624 | |
| 16625 | #ifdef GET_INSTRINFO_HELPERS |
| 16626 | #undef GET_INSTRINFO_HELPERS |
| 16627 | |
| 16628 | |
| 16629 | #endif // GET_INSTRINFO_HELPERS |
| 16630 | |
| 16631 | #ifdef GET_INSTRINFO_CTOR_DTOR |
| 16632 | #undef GET_INSTRINFO_CTOR_DTOR |
| 16633 | |
| 16634 | namespace llvm { |
| 16635 | |
| 16636 | extern const ARMInstrTable ARMDescs; |
| 16637 | extern const unsigned ARMInstrNameIndices[]; |
| 16638 | extern const char ARMInstrNameData[]; |
| 16639 | extern const uint8_t ARMInstrDeprecationFeatures[]; |
| 16640 | bool ARMInstrComplexDeprecationInfo(MCInst &Inst, const MCSubtargetInfo &STI, std::string &Info); |
| 16641 | ARMGenInstrInfo::ARMGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
| 16642 | : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode, ARMRegClassByHwModeTables[STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)]) { |
| 16643 | InitMCInstrInfo(ARMDescs.Insts, ARMInstrNameIndices, ARMInstrNameData, ARMInstrDeprecationFeatures, ARMInstrComplexDeprecationInfo, 4534, &ARMRegClassByHwModeTables[0][0], 1); |
| 16644 | } |
| 16645 | |
| 16646 | } // namespace llvm |
| 16647 | |
| 16648 | #endif // GET_INSTRINFO_CTOR_DTOR |
| 16649 | |
| 16650 | #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
| 16651 | #undef GET_INSTRINFO_MC_HELPER_DECLS |
| 16652 | |
| 16653 | namespace llvm { |
| 16654 | |
| 16655 | class MCInst; |
| 16656 | class FeatureBitset; |
| 16657 | |
| 16658 | extern const int16_t ARMRegClassByHwModeTables[2][1]; |
| 16659 | |
| 16660 | namespace ARM_MC { |
| 16661 | |
| 16662 | void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
| 16663 | |
| 16664 | } // namespace ARM_MC |
| 16665 | |
| 16666 | } // namespace llvm |
| 16667 | |
| 16668 | #endif // GET_INSTRINFO_MC_HELPER_DECLS |
| 16669 | |
| 16670 | #ifdef GET_INSTRINFO_MC_HELPERS |
| 16671 | #undef GET_INSTRINFO_MC_HELPERS |
| 16672 | |
| 16673 | namespace llvm::ARM_MC { |
| 16674 | |
| 16675 | |
| 16676 | } // namespace llvm::ARM_MC |
| 16677 | |
| 16678 | #endif // GET_INSTRINFO_MC_HELPERS |
| 16679 | |
| 16680 | #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ |
| 16681 | defined(GET_AVAILABLE_OPCODE_CHECKER) |
| 16682 | #define GET_COMPUTE_FEATURES |
| 16683 | #endif |
| 16684 | #ifdef GET_COMPUTE_FEATURES |
| 16685 | #undef GET_COMPUTE_FEATURES |
| 16686 | |
| 16687 | namespace llvm::ARM_MC { |
| 16688 | |
| 16689 | // Bits for subtarget features that participate in instruction matching. |
| 16690 | enum SubtargetFeatureBits : uint8_t { |
| 16691 | Feature_HasV4TBit = 35, |
| 16692 | Feature_HasV5TBit = 36, |
| 16693 | Feature_HasV5TEBit = 37, |
| 16694 | Feature_HasV6Bit = 38, |
| 16695 | Feature_HasV6MBit = 40, |
| 16696 | Feature_HasV8MBaselineBit = 45, |
| 16697 | Feature_HasV8MMainlineBit = 46, |
| 16698 | Feature_HasV8_1MMainlineBit = 47, |
| 16699 | Feature_HasMVEIntBit = 26, |
| 16700 | Feature_HasMVEFloatBit = 25, |
| 16701 | Feature_HasCDEBit = 4, |
| 16702 | Feature_HasFPRegsBit = 18, |
| 16703 | Feature_HasFPRegs16Bit = 19, |
| 16704 | Feature_HasNoFPRegs16Bit = 29, |
| 16705 | Feature_HasFPRegs64Bit = 20, |
| 16706 | Feature_HasFPRegsV8_1MBit = 21, |
| 16707 | Feature_HasV6T2Bit = 41, |
| 16708 | Feature_HasV6KBit = 39, |
| 16709 | Feature_HasV7Bit = 42, |
| 16710 | Feature_HasV8Bit = 44, |
| 16711 | Feature_PreV8Bit = 64, |
| 16712 | Feature_HasV8_1aBit = 48, |
| 16713 | Feature_HasV8_2aBit = 49, |
| 16714 | Feature_HasV8_3aBit = 50, |
| 16715 | Feature_HasV8_4aBit = 51, |
| 16716 | Feature_HasV8_5aBit = 52, |
| 16717 | Feature_HasV8_6aBit = 53, |
| 16718 | Feature_HasV8_7aBit = 54, |
| 16719 | Feature_HasVFP2Bit = 55, |
| 16720 | Feature_HasVFP3Bit = 56, |
| 16721 | Feature_HasVFP4Bit = 57, |
| 16722 | Feature_HasDPVFPBit = 10, |
| 16723 | Feature_HasFPARMv8Bit = 17, |
| 16724 | Feature_HasNEONBit = 28, |
| 16725 | Feature_HasSHA2Bit = 33, |
| 16726 | Feature_HasAESBit = 1, |
| 16727 | Feature_HasCryptoBit = 7, |
| 16728 | Feature_HasDotProdBit = 14, |
| 16729 | Feature_HasCRCBit = 6, |
| 16730 | Feature_HasRASBit = 31, |
| 16731 | Feature_HasLOBBit = 23, |
| 16732 | Feature_HasPACBTIBit = 30, |
| 16733 | Feature_HasFP16Bit = 15, |
| 16734 | Feature_HasFullFP16Bit = 22, |
| 16735 | Feature_HasFP16FMLBit = 16, |
| 16736 | Feature_HasBF16Bit = 3, |
| 16737 | Feature_HasMatMulInt8Bit = 27, |
| 16738 | Feature_HasDivideInThumbBit = 13, |
| 16739 | Feature_HasDivideInARMBit = 12, |
| 16740 | Feature_HasDSPBit = 11, |
| 16741 | Feature_HasDBBit = 8, |
| 16742 | Feature_HasDFBBit = 9, |
| 16743 | Feature_HasV7ClrexBit = 43, |
| 16744 | Feature_HasAcquireReleaseBit = 2, |
| 16745 | Feature_HasMPBit = 24, |
| 16746 | Feature_HasVirtualizationBit = 58, |
| 16747 | Feature_HasTrustZoneBit = 34, |
| 16748 | Feature_Has8MSecExtBit = 0, |
| 16749 | Feature_IsThumbBit = 62, |
| 16750 | Feature_IsThumb2Bit = 63, |
| 16751 | Feature_IsMClassBit = 60, |
| 16752 | Feature_IsNotMClassBit = 61, |
| 16753 | Feature_IsARMBit = 59, |
| 16754 | Feature_UseNegativeImmediatesBit = 65, |
| 16755 | Feature_HasSBBit = 32, |
| 16756 | Feature_HasCLRBHBBit = 5, |
| 16757 | }; |
| 16758 | |
| 16759 | inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
| 16760 | FeatureBitset Features; |
| 16761 | if (FB[ARM::HasV4TOps]) |
| 16762 | Features.set(Feature_HasV4TBit); |
| 16763 | if (FB[ARM::HasV5TOps]) |
| 16764 | Features.set(Feature_HasV5TBit); |
| 16765 | if (FB[ARM::HasV5TEOps]) |
| 16766 | Features.set(Feature_HasV5TEBit); |
| 16767 | if (FB[ARM::HasV6Ops]) |
| 16768 | Features.set(Feature_HasV6Bit); |
| 16769 | if (FB[ARM::HasV6MOps]) |
| 16770 | Features.set(Feature_HasV6MBit); |
| 16771 | if (FB[ARM::HasV8MBaselineOps]) |
| 16772 | Features.set(Feature_HasV8MBaselineBit); |
| 16773 | if (FB[ARM::HasV8MMainlineOps]) |
| 16774 | Features.set(Feature_HasV8MMainlineBit); |
| 16775 | if (FB[ARM::HasV8_1MMainlineOps]) |
| 16776 | Features.set(Feature_HasV8_1MMainlineBit); |
| 16777 | if (FB[ARM::HasMVEIntegerOps]) |
| 16778 | Features.set(Feature_HasMVEIntBit); |
| 16779 | if (FB[ARM::HasMVEFloatOps]) |
| 16780 | Features.set(Feature_HasMVEFloatBit); |
| 16781 | if (FB[ARM::HasCDEOps]) |
| 16782 | Features.set(Feature_HasCDEBit); |
| 16783 | if (FB[ARM::FeatureFPRegs]) |
| 16784 | Features.set(Feature_HasFPRegsBit); |
| 16785 | if (FB[ARM::FeatureFPRegs16]) |
| 16786 | Features.set(Feature_HasFPRegs16Bit); |
| 16787 | if (!(FB[ARM::FeatureFPRegs16])) |
| 16788 | Features.set(Feature_HasNoFPRegs16Bit); |
| 16789 | if (FB[ARM::FeatureFPRegs64]) |
| 16790 | Features.set(Feature_HasFPRegs64Bit); |
| 16791 | if (FB[ARM::FeatureFPRegs] && FB[ARM::HasV8_1MMainlineOps]) |
| 16792 | Features.set(Feature_HasFPRegsV8_1MBit); |
| 16793 | if (FB[ARM::HasV6T2Ops]) |
| 16794 | Features.set(Feature_HasV6T2Bit); |
| 16795 | if (FB[ARM::HasV6KOps]) |
| 16796 | Features.set(Feature_HasV6KBit); |
| 16797 | if (FB[ARM::HasV7Ops]) |
| 16798 | Features.set(Feature_HasV7Bit); |
| 16799 | if (FB[ARM::HasV8Ops]) |
| 16800 | Features.set(Feature_HasV8Bit); |
| 16801 | if (!(FB[ARM::HasV8Ops])) |
| 16802 | Features.set(Feature_PreV8Bit); |
| 16803 | if (FB[ARM::HasV8_1aOps]) |
| 16804 | Features.set(Feature_HasV8_1aBit); |
| 16805 | if (FB[ARM::HasV8_2aOps]) |
| 16806 | Features.set(Feature_HasV8_2aBit); |
| 16807 | if (FB[ARM::HasV8_3aOps]) |
| 16808 | Features.set(Feature_HasV8_3aBit); |
| 16809 | if (FB[ARM::HasV8_4aOps]) |
| 16810 | Features.set(Feature_HasV8_4aBit); |
| 16811 | if (FB[ARM::HasV8_5aOps]) |
| 16812 | Features.set(Feature_HasV8_5aBit); |
| 16813 | if (FB[ARM::HasV8_6aOps]) |
| 16814 | Features.set(Feature_HasV8_6aBit); |
| 16815 | if (FB[ARM::HasV8_7aOps]) |
| 16816 | Features.set(Feature_HasV8_7aBit); |
| 16817 | if (FB[ARM::FeatureVFP2_SP]) |
| 16818 | Features.set(Feature_HasVFP2Bit); |
| 16819 | if (FB[ARM::FeatureVFP3_D16_SP]) |
| 16820 | Features.set(Feature_HasVFP3Bit); |
| 16821 | if (FB[ARM::FeatureVFP4_D16_SP]) |
| 16822 | Features.set(Feature_HasVFP4Bit); |
| 16823 | if (FB[ARM::FeatureFP64]) |
| 16824 | Features.set(Feature_HasDPVFPBit); |
| 16825 | if (FB[ARM::FeatureFPARMv8_D16_SP]) |
| 16826 | Features.set(Feature_HasFPARMv8Bit); |
| 16827 | if (FB[ARM::FeatureNEON]) |
| 16828 | Features.set(Feature_HasNEONBit); |
| 16829 | if (FB[ARM::FeatureSHA2]) |
| 16830 | Features.set(Feature_HasSHA2Bit); |
| 16831 | if (FB[ARM::FeatureAES]) |
| 16832 | Features.set(Feature_HasAESBit); |
| 16833 | if (FB[ARM::FeatureCrypto]) |
| 16834 | Features.set(Feature_HasCryptoBit); |
| 16835 | if (FB[ARM::FeatureDotProd]) |
| 16836 | Features.set(Feature_HasDotProdBit); |
| 16837 | if (FB[ARM::FeatureCRC]) |
| 16838 | Features.set(Feature_HasCRCBit); |
| 16839 | if (FB[ARM::FeatureRAS]) |
| 16840 | Features.set(Feature_HasRASBit); |
| 16841 | if (FB[ARM::FeatureLOB]) |
| 16842 | Features.set(Feature_HasLOBBit); |
| 16843 | if (FB[ARM::FeaturePACBTI]) |
| 16844 | Features.set(Feature_HasPACBTIBit); |
| 16845 | if (FB[ARM::FeatureFP16]) |
| 16846 | Features.set(Feature_HasFP16Bit); |
| 16847 | if (FB[ARM::FeatureFullFP16]) |
| 16848 | Features.set(Feature_HasFullFP16Bit); |
| 16849 | if (FB[ARM::FeatureFP16FML]) |
| 16850 | Features.set(Feature_HasFP16FMLBit); |
| 16851 | if (FB[ARM::FeatureBF16]) |
| 16852 | Features.set(Feature_HasBF16Bit); |
| 16853 | if (FB[ARM::FeatureMatMulInt8]) |
| 16854 | Features.set(Feature_HasMatMulInt8Bit); |
| 16855 | if (FB[ARM::FeatureHWDivThumb]) |
| 16856 | Features.set(Feature_HasDivideInThumbBit); |
| 16857 | if (FB[ARM::FeatureHWDivARM]) |
| 16858 | Features.set(Feature_HasDivideInARMBit); |
| 16859 | if (FB[ARM::FeatureDSP]) |
| 16860 | Features.set(Feature_HasDSPBit); |
| 16861 | if (FB[ARM::FeatureDB]) |
| 16862 | Features.set(Feature_HasDBBit); |
| 16863 | if (FB[ARM::FeatureDFB]) |
| 16864 | Features.set(Feature_HasDFBBit); |
| 16865 | if (FB[ARM::FeatureV7Clrex]) |
| 16866 | Features.set(Feature_HasV7ClrexBit); |
| 16867 | if (FB[ARM::FeatureAcquireRelease]) |
| 16868 | Features.set(Feature_HasAcquireReleaseBit); |
| 16869 | if (FB[ARM::FeatureMP]) |
| 16870 | Features.set(Feature_HasMPBit); |
| 16871 | if (FB[ARM::FeatureVirtualization]) |
| 16872 | Features.set(Feature_HasVirtualizationBit); |
| 16873 | if (FB[ARM::FeatureTrustZone]) |
| 16874 | Features.set(Feature_HasTrustZoneBit); |
| 16875 | if (FB[ARM::Feature8MSecExt]) |
| 16876 | Features.set(Feature_Has8MSecExtBit); |
| 16877 | if (FB[ARM::ModeThumb]) |
| 16878 | Features.set(Feature_IsThumbBit); |
| 16879 | if (FB[ARM::ModeThumb] && FB[ARM::FeatureThumb2]) |
| 16880 | Features.set(Feature_IsThumb2Bit); |
| 16881 | if (FB[ARM::FeatureMClass]) |
| 16882 | Features.set(Feature_IsMClassBit); |
| 16883 | if (!(FB[ARM::FeatureMClass])) |
| 16884 | Features.set(Feature_IsNotMClassBit); |
| 16885 | if (!(FB[ARM::ModeThumb])) |
| 16886 | Features.set(Feature_IsARMBit); |
| 16887 | if (!(FB[ARM::FeatureNoNegativeImmediates])) |
| 16888 | Features.set(Feature_UseNegativeImmediatesBit); |
| 16889 | if (FB[ARM::FeatureSB]) |
| 16890 | Features.set(Feature_HasSBBit); |
| 16891 | if (FB[ARM::FeatureCLRBHB]) |
| 16892 | Features.set(Feature_HasCLRBHBBit); |
| 16893 | return Features; |
| 16894 | } |
| 16895 | |
| 16896 | inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { |
| 16897 | enum : uint8_t { |
| 16898 | CEFBS_None, |
| 16899 | CEFBS_Has8MSecExt, |
| 16900 | CEFBS_HasBF16, |
| 16901 | CEFBS_HasCDE, |
| 16902 | CEFBS_HasDotProd, |
| 16903 | CEFBS_HasFP16, |
| 16904 | CEFBS_HasFPARMv8, |
| 16905 | CEFBS_HasFPRegs, |
| 16906 | CEFBS_HasFPRegs16, |
| 16907 | CEFBS_HasFPRegs64, |
| 16908 | CEFBS_HasFPRegsV8_1M, |
| 16909 | CEFBS_HasFullFP16, |
| 16910 | CEFBS_HasMVEFloat, |
| 16911 | CEFBS_HasMVEInt, |
| 16912 | CEFBS_HasMatMulInt8, |
| 16913 | CEFBS_HasNEON, |
| 16914 | CEFBS_HasV8_1MMainline, |
| 16915 | CEFBS_HasVFP2, |
| 16916 | CEFBS_HasVFP3, |
| 16917 | CEFBS_HasVFP4, |
| 16918 | CEFBS_IsARM, |
| 16919 | CEFBS_IsThumb, |
| 16920 | CEFBS_IsThumb2, |
| 16921 | CEFBS_HasBF16_HasNEON, |
| 16922 | CEFBS_HasCDE_HasFPRegs, |
| 16923 | CEFBS_HasCDE_HasMVEInt, |
| 16924 | CEFBS_HasDSP_IsThumb2, |
| 16925 | CEFBS_HasFPARMv8_HasDPVFP, |
| 16926 | CEFBS_HasFPARMv8_HasNEON, |
| 16927 | CEFBS_HasFPARMv8_HasV8_3a, |
| 16928 | CEFBS_HasFPRegs_HasV8_1MMainline, |
| 16929 | CEFBS_HasNEON_HasFP16, |
| 16930 | CEFBS_HasNEON_HasFP16FML, |
| 16931 | CEFBS_HasNEON_HasFullFP16, |
| 16932 | CEFBS_HasNEON_HasV8_1a, |
| 16933 | CEFBS_HasNEON_HasV8_3a, |
| 16934 | CEFBS_HasNEON_HasVFP4, |
| 16935 | CEFBS_HasV7_IsMClass, |
| 16936 | CEFBS_HasV8_HasAES, |
| 16937 | CEFBS_HasV8_HasNEON, |
| 16938 | CEFBS_HasV8_HasSHA2, |
| 16939 | CEFBS_HasV8MMainline_Has8MSecExt, |
| 16940 | CEFBS_HasV8_1MMainline_Has8MSecExt, |
| 16941 | CEFBS_HasV8_1MMainline_HasFPRegs, |
| 16942 | CEFBS_HasV8_1MMainline_HasMVEInt, |
| 16943 | CEFBS_HasVFP2_HasDPVFP, |
| 16944 | CEFBS_HasVFP3_HasDPVFP, |
| 16945 | CEFBS_HasVFP4_HasDPVFP, |
| 16946 | CEFBS_IsARM_HasAcquireRelease, |
| 16947 | CEFBS_IsARM_HasCRC, |
| 16948 | CEFBS_IsARM_HasDB, |
| 16949 | CEFBS_IsARM_HasDivideInARM, |
| 16950 | CEFBS_IsARM_HasSB, |
| 16951 | CEFBS_IsARM_HasTrustZone, |
| 16952 | CEFBS_IsARM_HasV4T, |
| 16953 | CEFBS_IsARM_HasV5T, |
| 16954 | CEFBS_IsARM_HasV5TE, |
| 16955 | CEFBS_IsARM_HasV6, |
| 16956 | CEFBS_IsARM_HasV6K, |
| 16957 | CEFBS_IsARM_HasV6T2, |
| 16958 | CEFBS_IsARM_HasV7, |
| 16959 | CEFBS_IsARM_HasV8, |
| 16960 | CEFBS_IsARM_HasV8_4a, |
| 16961 | CEFBS_IsARM_HasVFP2, |
| 16962 | CEFBS_IsARM_HasVirtualization, |
| 16963 | CEFBS_IsARM_PreV8, |
| 16964 | CEFBS_IsThumb_Has8MSecExt, |
| 16965 | CEFBS_IsThumb_HasAcquireRelease, |
| 16966 | CEFBS_IsThumb_HasDB, |
| 16967 | CEFBS_IsThumb_HasV5T, |
| 16968 | CEFBS_IsThumb_HasV6, |
| 16969 | CEFBS_IsThumb_HasV6M, |
| 16970 | CEFBS_IsThumb_HasV7Clrex, |
| 16971 | CEFBS_IsThumb_HasV8, |
| 16972 | CEFBS_IsThumb_HasV8MBaseline, |
| 16973 | CEFBS_IsThumb_HasV8_4a, |
| 16974 | CEFBS_IsThumb_HasVirtualization, |
| 16975 | CEFBS_IsThumb_IsMClass, |
| 16976 | CEFBS_IsThumb_IsNotMClass, |
| 16977 | CEFBS_IsThumb2_HasCRC, |
| 16978 | CEFBS_IsThumb2_HasDSP, |
| 16979 | CEFBS_IsThumb2_HasSB, |
| 16980 | CEFBS_IsThumb2_HasTrustZone, |
| 16981 | CEFBS_IsThumb2_HasV7, |
| 16982 | CEFBS_IsThumb2_HasV8, |
| 16983 | CEFBS_IsThumb2_HasVFP2, |
| 16984 | CEFBS_IsThumb2_HasVirtualization, |
| 16985 | CEFBS_IsThumb2_IsNotMClass, |
| 16986 | CEFBS_IsThumb2_PreV8, |
| 16987 | CEFBS_PreV8_IsThumb2, |
| 16988 | CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, |
| 16989 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, |
| 16990 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, |
| 16991 | CEFBS_HasV8_HasNEON_HasFullFP16, |
| 16992 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, |
| 16993 | CEFBS_IsARM_HasV7_HasMP, |
| 16994 | CEFBS_IsARM_HasV8_HasV8_1a, |
| 16995 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, |
| 16996 | CEFBS_IsThumb_HasV5T_IsNotMClass, |
| 16997 | CEFBS_IsThumb2_HasV7_HasMP, |
| 16998 | CEFBS_IsThumb2_HasV8_HasV8_1a, |
| 16999 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, |
| 17000 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, |
| 17001 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, |
| 17002 | }; |
| 17003 | |
| 17004 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 17005 | {}, // CEFBS_None |
| 17006 | {Feature_Has8MSecExtBit, }, |
| 17007 | {Feature_HasBF16Bit, }, |
| 17008 | {Feature_HasCDEBit, }, |
| 17009 | {Feature_HasDotProdBit, }, |
| 17010 | {Feature_HasFP16Bit, }, |
| 17011 | {Feature_HasFPARMv8Bit, }, |
| 17012 | {Feature_HasFPRegsBit, }, |
| 17013 | {Feature_HasFPRegs16Bit, }, |
| 17014 | {Feature_HasFPRegs64Bit, }, |
| 17015 | {Feature_HasFPRegsV8_1MBit, }, |
| 17016 | {Feature_HasFullFP16Bit, }, |
| 17017 | {Feature_HasMVEFloatBit, }, |
| 17018 | {Feature_HasMVEIntBit, }, |
| 17019 | {Feature_HasMatMulInt8Bit, }, |
| 17020 | {Feature_HasNEONBit, }, |
| 17021 | {Feature_HasV8_1MMainlineBit, }, |
| 17022 | {Feature_HasVFP2Bit, }, |
| 17023 | {Feature_HasVFP3Bit, }, |
| 17024 | {Feature_HasVFP4Bit, }, |
| 17025 | {Feature_IsARMBit, }, |
| 17026 | {Feature_IsThumbBit, }, |
| 17027 | {Feature_IsThumb2Bit, }, |
| 17028 | {Feature_HasBF16Bit, Feature_HasNEONBit, }, |
| 17029 | {Feature_HasCDEBit, Feature_HasFPRegsBit, }, |
| 17030 | {Feature_HasCDEBit, Feature_HasMVEIntBit, }, |
| 17031 | {Feature_HasDSPBit, Feature_IsThumb2Bit, }, |
| 17032 | {Feature_HasFPARMv8Bit, Feature_HasDPVFPBit, }, |
| 17033 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, |
| 17034 | {Feature_HasFPARMv8Bit, Feature_HasV8_3aBit, }, |
| 17035 | {Feature_HasFPRegsBit, Feature_HasV8_1MMainlineBit, }, |
| 17036 | {Feature_HasNEONBit, Feature_HasFP16Bit, }, |
| 17037 | {Feature_HasNEONBit, Feature_HasFP16FMLBit, }, |
| 17038 | {Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 17039 | {Feature_HasNEONBit, Feature_HasV8_1aBit, }, |
| 17040 | {Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 17041 | {Feature_HasNEONBit, Feature_HasVFP4Bit, }, |
| 17042 | {Feature_HasV7Bit, Feature_IsMClassBit, }, |
| 17043 | {Feature_HasV8Bit, Feature_HasAESBit, }, |
| 17044 | {Feature_HasV8Bit, Feature_HasNEONBit, }, |
| 17045 | {Feature_HasV8Bit, Feature_HasSHA2Bit, }, |
| 17046 | {Feature_HasV8MMainlineBit, Feature_Has8MSecExtBit, }, |
| 17047 | {Feature_HasV8_1MMainlineBit, Feature_Has8MSecExtBit, }, |
| 17048 | {Feature_HasV8_1MMainlineBit, Feature_HasFPRegsBit, }, |
| 17049 | {Feature_HasV8_1MMainlineBit, Feature_HasMVEIntBit, }, |
| 17050 | {Feature_HasVFP2Bit, Feature_HasDPVFPBit, }, |
| 17051 | {Feature_HasVFP3Bit, Feature_HasDPVFPBit, }, |
| 17052 | {Feature_HasVFP4Bit, Feature_HasDPVFPBit, }, |
| 17053 | {Feature_IsARMBit, Feature_HasAcquireReleaseBit, }, |
| 17054 | {Feature_IsARMBit, Feature_HasCRCBit, }, |
| 17055 | {Feature_IsARMBit, Feature_HasDBBit, }, |
| 17056 | {Feature_IsARMBit, Feature_HasDivideInARMBit, }, |
| 17057 | {Feature_IsARMBit, Feature_HasSBBit, }, |
| 17058 | {Feature_IsARMBit, Feature_HasTrustZoneBit, }, |
| 17059 | {Feature_IsARMBit, Feature_HasV4TBit, }, |
| 17060 | {Feature_IsARMBit, Feature_HasV5TBit, }, |
| 17061 | {Feature_IsARMBit, Feature_HasV5TEBit, }, |
| 17062 | {Feature_IsARMBit, Feature_HasV6Bit, }, |
| 17063 | {Feature_IsARMBit, Feature_HasV6KBit, }, |
| 17064 | {Feature_IsARMBit, Feature_HasV6T2Bit, }, |
| 17065 | {Feature_IsARMBit, Feature_HasV7Bit, }, |
| 17066 | {Feature_IsARMBit, Feature_HasV8Bit, }, |
| 17067 | {Feature_IsARMBit, Feature_HasV8_4aBit, }, |
| 17068 | {Feature_IsARMBit, Feature_HasVFP2Bit, }, |
| 17069 | {Feature_IsARMBit, Feature_HasVirtualizationBit, }, |
| 17070 | {Feature_IsARMBit, Feature_PreV8Bit, }, |
| 17071 | {Feature_IsThumbBit, Feature_Has8MSecExtBit, }, |
| 17072 | {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, }, |
| 17073 | {Feature_IsThumbBit, Feature_HasDBBit, }, |
| 17074 | {Feature_IsThumbBit, Feature_HasV5TBit, }, |
| 17075 | {Feature_IsThumbBit, Feature_HasV6Bit, }, |
| 17076 | {Feature_IsThumbBit, Feature_HasV6MBit, }, |
| 17077 | {Feature_IsThumbBit, Feature_HasV7ClrexBit, }, |
| 17078 | {Feature_IsThumbBit, Feature_HasV8Bit, }, |
| 17079 | {Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, |
| 17080 | {Feature_IsThumbBit, Feature_HasV8_4aBit, }, |
| 17081 | {Feature_IsThumbBit, Feature_HasVirtualizationBit, }, |
| 17082 | {Feature_IsThumbBit, Feature_IsMClassBit, }, |
| 17083 | {Feature_IsThumbBit, Feature_IsNotMClassBit, }, |
| 17084 | {Feature_IsThumb2Bit, Feature_HasCRCBit, }, |
| 17085 | {Feature_IsThumb2Bit, Feature_HasDSPBit, }, |
| 17086 | {Feature_IsThumb2Bit, Feature_HasSBBit, }, |
| 17087 | {Feature_IsThumb2Bit, Feature_HasTrustZoneBit, }, |
| 17088 | {Feature_IsThumb2Bit, Feature_HasV7Bit, }, |
| 17089 | {Feature_IsThumb2Bit, Feature_HasV8Bit, }, |
| 17090 | {Feature_IsThumb2Bit, Feature_HasVFP2Bit, }, |
| 17091 | {Feature_IsThumb2Bit, Feature_HasVirtualizationBit, }, |
| 17092 | {Feature_IsThumb2Bit, Feature_IsNotMClassBit, }, |
| 17093 | {Feature_IsThumb2Bit, Feature_PreV8Bit, }, |
| 17094 | {Feature_PreV8Bit, Feature_IsThumb2Bit, }, |
| 17095 | {Feature_HasDivideInThumbBit, Feature_IsThumbBit, Feature_HasV8MBaselineBit, }, |
| 17096 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 17097 | {Feature_HasNEONBit, Feature_HasV8_3aBit, Feature_HasFullFP16Bit, }, |
| 17098 | {Feature_HasV8Bit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| 17099 | {Feature_IsARMBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, |
| 17100 | {Feature_IsARMBit, Feature_HasV7Bit, Feature_HasMPBit, }, |
| 17101 | {Feature_IsARMBit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, |
| 17102 | {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, }, |
| 17103 | {Feature_IsThumbBit, Feature_HasV5TBit, Feature_IsNotMClassBit, }, |
| 17104 | {Feature_IsThumb2Bit, Feature_HasV7Bit, Feature_HasMPBit, }, |
| 17105 | {Feature_IsThumb2Bit, Feature_HasV8Bit, Feature_HasV8_1aBit, }, |
| 17106 | {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasLOBBit, }, |
| 17107 | {Feature_IsThumb2Bit, Feature_HasV8_1MMainlineBit, Feature_HasPACBTIBit, }, |
| 17108 | {Feature_IsThumbBit, Feature_HasAcquireReleaseBit, Feature_HasV7ClrexBit, Feature_IsNotMClassBit, }, |
| 17109 | }; |
| 17110 | static constexpr uint8_t RequiredFeaturesRefs[] = { |
| 17111 | CEFBS_None, // PHI |
| 17112 | CEFBS_None, // INLINEASM |
| 17113 | CEFBS_None, // INLINEASM_BR |
| 17114 | CEFBS_None, // CFI_INSTRUCTION |
| 17115 | CEFBS_None, // EH_LABEL |
| 17116 | CEFBS_None, // GC_LABEL |
| 17117 | CEFBS_None, // ANNOTATION_LABEL |
| 17118 | CEFBS_None, // KILL |
| 17119 | CEFBS_None, // EXTRACT_SUBREG |
| 17120 | CEFBS_None, // INSERT_SUBREG |
| 17121 | CEFBS_None, // IMPLICIT_DEF |
| 17122 | CEFBS_None, // INIT_UNDEF |
| 17123 | CEFBS_None, // SUBREG_TO_REG |
| 17124 | CEFBS_None, // COPY_TO_REGCLASS |
| 17125 | CEFBS_None, // DBG_VALUE |
| 17126 | CEFBS_None, // DBG_VALUE_LIST |
| 17127 | CEFBS_None, // DBG_INSTR_REF |
| 17128 | CEFBS_None, // DBG_PHI |
| 17129 | CEFBS_None, // DBG_LABEL |
| 17130 | CEFBS_None, // REG_SEQUENCE |
| 17131 | CEFBS_None, // COPY |
| 17132 | CEFBS_None, // COPY_LANEMASK |
| 17133 | CEFBS_None, // BUNDLE |
| 17134 | CEFBS_None, // LIFETIME_START |
| 17135 | CEFBS_None, // LIFETIME_END |
| 17136 | CEFBS_None, // PSEUDO_PROBE |
| 17137 | CEFBS_None, // ARITH_FENCE |
| 17138 | CEFBS_None, // STACKMAP |
| 17139 | CEFBS_None, // FENTRY_CALL |
| 17140 | CEFBS_None, // PATCHPOINT |
| 17141 | CEFBS_None, // LOAD_STACK_GUARD |
| 17142 | CEFBS_None, // PREALLOCATED_SETUP |
| 17143 | CEFBS_None, // PREALLOCATED_ARG |
| 17144 | CEFBS_None, // STATEPOINT |
| 17145 | CEFBS_None, // LOCAL_ESCAPE |
| 17146 | CEFBS_None, // FAULTING_OP |
| 17147 | CEFBS_None, // PATCHABLE_OP |
| 17148 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER |
| 17149 | CEFBS_None, // PATCHABLE_RET |
| 17150 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT |
| 17151 | CEFBS_None, // PATCHABLE_TAIL_CALL |
| 17152 | CEFBS_None, // PATCHABLE_EVENT_CALL |
| 17153 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL |
| 17154 | CEFBS_None, // ICALL_BRANCH_FUNNEL |
| 17155 | CEFBS_None, // FAKE_USE |
| 17156 | CEFBS_None, // MEMBARRIER |
| 17157 | CEFBS_None, // JUMP_TABLE_DEBUG_INFO |
| 17158 | CEFBS_None, // RELOC_NONE |
| 17159 | CEFBS_None, // CONVERGENCECTRL_ENTRY |
| 17160 | CEFBS_None, // CONVERGENCECTRL_ANCHOR |
| 17161 | CEFBS_None, // CONVERGENCECTRL_LOOP |
| 17162 | CEFBS_None, // CONVERGENCECTRL_GLUE |
| 17163 | CEFBS_None, // G_ASSERT_SEXT |
| 17164 | CEFBS_None, // G_ASSERT_ZEXT |
| 17165 | CEFBS_None, // G_ASSERT_ALIGN |
| 17166 | CEFBS_None, // G_ADD |
| 17167 | CEFBS_None, // G_SUB |
| 17168 | CEFBS_None, // G_MUL |
| 17169 | CEFBS_None, // G_SDIV |
| 17170 | CEFBS_None, // G_UDIV |
| 17171 | CEFBS_None, // G_SREM |
| 17172 | CEFBS_None, // G_UREM |
| 17173 | CEFBS_None, // G_SDIVREM |
| 17174 | CEFBS_None, // G_UDIVREM |
| 17175 | CEFBS_None, // G_AND |
| 17176 | CEFBS_None, // G_OR |
| 17177 | CEFBS_None, // G_XOR |
| 17178 | CEFBS_None, // G_ABDS |
| 17179 | CEFBS_None, // G_ABDU |
| 17180 | CEFBS_None, // G_UAVGFLOOR |
| 17181 | CEFBS_None, // G_UAVGCEIL |
| 17182 | CEFBS_None, // G_SAVGFLOOR |
| 17183 | CEFBS_None, // G_SAVGCEIL |
| 17184 | CEFBS_None, // G_IMPLICIT_DEF |
| 17185 | CEFBS_None, // G_PHI |
| 17186 | CEFBS_None, // G_FRAME_INDEX |
| 17187 | CEFBS_None, // G_GLOBAL_VALUE |
| 17188 | CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE |
| 17189 | CEFBS_None, // G_CONSTANT_POOL |
| 17190 | CEFBS_None, // G_EXTRACT |
| 17191 | CEFBS_None, // G_UNMERGE_VALUES |
| 17192 | CEFBS_None, // G_INSERT |
| 17193 | CEFBS_None, // G_MERGE_VALUES |
| 17194 | CEFBS_None, // G_BUILD_VECTOR |
| 17195 | CEFBS_None, // G_BUILD_VECTOR_TRUNC |
| 17196 | CEFBS_None, // G_CONCAT_VECTORS |
| 17197 | CEFBS_None, // G_PTRTOINT |
| 17198 | CEFBS_None, // G_INTTOPTR |
| 17199 | CEFBS_None, // G_BITCAST |
| 17200 | CEFBS_None, // G_FREEZE |
| 17201 | CEFBS_None, // G_CONSTANT_FOLD_BARRIER |
| 17202 | CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND |
| 17203 | CEFBS_None, // G_INTRINSIC_TRUNC |
| 17204 | CEFBS_None, // G_INTRINSIC_ROUND |
| 17205 | CEFBS_None, // G_INTRINSIC_LRINT |
| 17206 | CEFBS_None, // G_INTRINSIC_LLRINT |
| 17207 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN |
| 17208 | CEFBS_None, // G_READCYCLECOUNTER |
| 17209 | CEFBS_None, // G_READSTEADYCOUNTER |
| 17210 | CEFBS_None, // G_LOAD |
| 17211 | CEFBS_None, // G_SEXTLOAD |
| 17212 | CEFBS_None, // G_ZEXTLOAD |
| 17213 | CEFBS_None, // G_FPEXTLOAD |
| 17214 | CEFBS_None, // G_INDEXED_LOAD |
| 17215 | CEFBS_None, // G_INDEXED_SEXTLOAD |
| 17216 | CEFBS_None, // G_INDEXED_ZEXTLOAD |
| 17217 | CEFBS_None, // G_STORE |
| 17218 | CEFBS_None, // G_FPTRUNCSTORE |
| 17219 | CEFBS_None, // G_INDEXED_STORE |
| 17220 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 17221 | CEFBS_None, // G_ATOMIC_CMPXCHG |
| 17222 | CEFBS_None, // G_ATOMICRMW_XCHG |
| 17223 | CEFBS_None, // G_ATOMICRMW_ADD |
| 17224 | CEFBS_None, // G_ATOMICRMW_SUB |
| 17225 | CEFBS_None, // G_ATOMICRMW_AND |
| 17226 | CEFBS_None, // G_ATOMICRMW_NAND |
| 17227 | CEFBS_None, // G_ATOMICRMW_OR |
| 17228 | CEFBS_None, // G_ATOMICRMW_XOR |
| 17229 | CEFBS_None, // G_ATOMICRMW_MAX |
| 17230 | CEFBS_None, // G_ATOMICRMW_MIN |
| 17231 | CEFBS_None, // G_ATOMICRMW_UMAX |
| 17232 | CEFBS_None, // G_ATOMICRMW_UMIN |
| 17233 | CEFBS_None, // G_ATOMICRMW_FADD |
| 17234 | CEFBS_None, // G_ATOMICRMW_FSUB |
| 17235 | CEFBS_None, // G_ATOMICRMW_FMAX |
| 17236 | CEFBS_None, // G_ATOMICRMW_FMIN |
| 17237 | CEFBS_None, // G_ATOMICRMW_FMAXIMUM |
| 17238 | CEFBS_None, // G_ATOMICRMW_FMINIMUM |
| 17239 | CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM |
| 17240 | CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM |
| 17241 | CEFBS_None, // G_ATOMICRMW_UINC_WRAP |
| 17242 | CEFBS_None, // G_ATOMICRMW_UDEC_WRAP |
| 17243 | CEFBS_None, // G_ATOMICRMW_USUB_COND |
| 17244 | CEFBS_None, // G_ATOMICRMW_USUB_SAT |
| 17245 | CEFBS_None, // G_FENCE |
| 17246 | CEFBS_None, // G_PREFETCH |
| 17247 | CEFBS_None, // G_BRCOND |
| 17248 | CEFBS_None, // G_BRINDIRECT |
| 17249 | CEFBS_None, // G_INVOKE_REGION_START |
| 17250 | CEFBS_None, // G_INTRINSIC |
| 17251 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS |
| 17252 | CEFBS_None, // G_INTRINSIC_CONVERGENT |
| 17253 | CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 17254 | CEFBS_None, // G_ANYEXT |
| 17255 | CEFBS_None, // G_TRUNC |
| 17256 | CEFBS_None, // G_TRUNC_SSAT_S |
| 17257 | CEFBS_None, // G_TRUNC_SSAT_U |
| 17258 | CEFBS_None, // G_TRUNC_USAT_U |
| 17259 | CEFBS_None, // G_CONSTANT |
| 17260 | CEFBS_None, // G_FCONSTANT |
| 17261 | CEFBS_None, // G_VASTART |
| 17262 | CEFBS_None, // G_VAARG |
| 17263 | CEFBS_None, // G_SEXT |
| 17264 | CEFBS_None, // G_SEXT_INREG |
| 17265 | CEFBS_None, // G_ZEXT |
| 17266 | CEFBS_None, // G_SHL |
| 17267 | CEFBS_None, // G_LSHR |
| 17268 | CEFBS_None, // G_ASHR |
| 17269 | CEFBS_None, // G_FSHL |
| 17270 | CEFBS_None, // G_FSHR |
| 17271 | CEFBS_None, // G_ROTR |
| 17272 | CEFBS_None, // G_ROTL |
| 17273 | CEFBS_None, // G_ICMP |
| 17274 | CEFBS_None, // G_FCMP |
| 17275 | CEFBS_None, // G_SCMP |
| 17276 | CEFBS_None, // G_UCMP |
| 17277 | CEFBS_None, // G_SELECT |
| 17278 | CEFBS_None, // G_UADDO |
| 17279 | CEFBS_None, // G_UADDE |
| 17280 | CEFBS_None, // G_USUBO |
| 17281 | CEFBS_None, // G_USUBE |
| 17282 | CEFBS_None, // G_SADDO |
| 17283 | CEFBS_None, // G_SADDE |
| 17284 | CEFBS_None, // G_SSUBO |
| 17285 | CEFBS_None, // G_SSUBE |
| 17286 | CEFBS_None, // G_UMULO |
| 17287 | CEFBS_None, // G_SMULO |
| 17288 | CEFBS_None, // G_UMULH |
| 17289 | CEFBS_None, // G_SMULH |
| 17290 | CEFBS_None, // G_UADDSAT |
| 17291 | CEFBS_None, // G_SADDSAT |
| 17292 | CEFBS_None, // G_USUBSAT |
| 17293 | CEFBS_None, // G_SSUBSAT |
| 17294 | CEFBS_None, // G_USHLSAT |
| 17295 | CEFBS_None, // G_SSHLSAT |
| 17296 | CEFBS_None, // G_SMULFIX |
| 17297 | CEFBS_None, // G_UMULFIX |
| 17298 | CEFBS_None, // G_SMULFIXSAT |
| 17299 | CEFBS_None, // G_UMULFIXSAT |
| 17300 | CEFBS_None, // G_SDIVFIX |
| 17301 | CEFBS_None, // G_UDIVFIX |
| 17302 | CEFBS_None, // G_SDIVFIXSAT |
| 17303 | CEFBS_None, // G_UDIVFIXSAT |
| 17304 | CEFBS_None, // G_FADD |
| 17305 | CEFBS_None, // G_FSUB |
| 17306 | CEFBS_None, // G_FMUL |
| 17307 | CEFBS_None, // G_FMA |
| 17308 | CEFBS_None, // G_FMAD |
| 17309 | CEFBS_None, // G_FDIV |
| 17310 | CEFBS_None, // G_FREM |
| 17311 | CEFBS_None, // G_FMODF |
| 17312 | CEFBS_None, // G_FPOW |
| 17313 | CEFBS_None, // G_FPOWI |
| 17314 | CEFBS_None, // G_FEXP |
| 17315 | CEFBS_None, // G_FEXP2 |
| 17316 | CEFBS_None, // G_FEXP10 |
| 17317 | CEFBS_None, // G_FLOG |
| 17318 | CEFBS_None, // G_FLOG2 |
| 17319 | CEFBS_None, // G_FLOG10 |
| 17320 | CEFBS_None, // G_FLDEXP |
| 17321 | CEFBS_None, // G_FFREXP |
| 17322 | CEFBS_None, // G_FNEG |
| 17323 | CEFBS_None, // G_FPEXT |
| 17324 | CEFBS_None, // G_FPTRUNC |
| 17325 | CEFBS_None, // G_FPTOSI |
| 17326 | CEFBS_None, // G_FPTOUI |
| 17327 | CEFBS_None, // G_SITOFP |
| 17328 | CEFBS_None, // G_UITOFP |
| 17329 | CEFBS_None, // G_FPTOSI_SAT |
| 17330 | CEFBS_None, // G_FPTOUI_SAT |
| 17331 | CEFBS_None, // G_FABS |
| 17332 | CEFBS_None, // G_FCOPYSIGN |
| 17333 | CEFBS_None, // G_IS_FPCLASS |
| 17334 | CEFBS_None, // G_FCANONICALIZE |
| 17335 | CEFBS_None, // G_FMINNUM |
| 17336 | CEFBS_None, // G_FMAXNUM |
| 17337 | CEFBS_None, // G_FMINNUM_IEEE |
| 17338 | CEFBS_None, // G_FMAXNUM_IEEE |
| 17339 | CEFBS_None, // G_FMINIMUM |
| 17340 | CEFBS_None, // G_FMAXIMUM |
| 17341 | CEFBS_None, // G_FMINIMUMNUM |
| 17342 | CEFBS_None, // G_FMAXIMUMNUM |
| 17343 | CEFBS_None, // G_GET_FPENV |
| 17344 | CEFBS_None, // G_SET_FPENV |
| 17345 | CEFBS_None, // G_RESET_FPENV |
| 17346 | CEFBS_None, // G_GET_FPMODE |
| 17347 | CEFBS_None, // G_SET_FPMODE |
| 17348 | CEFBS_None, // G_RESET_FPMODE |
| 17349 | CEFBS_None, // G_GET_ROUNDING |
| 17350 | CEFBS_None, // G_SET_ROUNDING |
| 17351 | CEFBS_None, // G_PTR_ADD |
| 17352 | CEFBS_None, // G_PTRMASK |
| 17353 | CEFBS_None, // G_SMIN |
| 17354 | CEFBS_None, // G_SMAX |
| 17355 | CEFBS_None, // G_UMIN |
| 17356 | CEFBS_None, // G_UMAX |
| 17357 | CEFBS_None, // G_ABS |
| 17358 | CEFBS_None, // G_LROUND |
| 17359 | CEFBS_None, // G_LLROUND |
| 17360 | CEFBS_None, // G_BR |
| 17361 | CEFBS_None, // G_BRJT |
| 17362 | CEFBS_None, // G_VSCALE |
| 17363 | CEFBS_None, // G_INSERT_SUBVECTOR |
| 17364 | CEFBS_None, // G_EXTRACT_SUBVECTOR |
| 17365 | CEFBS_None, // G_INSERT_VECTOR_ELT |
| 17366 | CEFBS_None, // G_EXTRACT_VECTOR_ELT |
| 17367 | CEFBS_None, // G_SHUFFLE_VECTOR |
| 17368 | CEFBS_None, // G_SPLAT_VECTOR |
| 17369 | CEFBS_None, // G_STEP_VECTOR |
| 17370 | CEFBS_None, // G_VECTOR_COMPRESS |
| 17371 | CEFBS_None, // G_CTTZ |
| 17372 | CEFBS_None, // G_CTTZ_ZERO_POISON |
| 17373 | CEFBS_None, // G_CTLZ |
| 17374 | CEFBS_None, // G_CTLZ_ZERO_POISON |
| 17375 | CEFBS_None, // G_CTLS |
| 17376 | CEFBS_None, // G_CTPOP |
| 17377 | CEFBS_None, // G_BSWAP |
| 17378 | CEFBS_None, // G_BITREVERSE |
| 17379 | CEFBS_None, // G_CLMUL |
| 17380 | CEFBS_None, // G_CLMULH |
| 17381 | CEFBS_None, // G_FCEIL |
| 17382 | CEFBS_None, // G_FCOS |
| 17383 | CEFBS_None, // G_FSIN |
| 17384 | CEFBS_None, // G_FSINCOS |
| 17385 | CEFBS_None, // G_FTAN |
| 17386 | CEFBS_None, // G_FACOS |
| 17387 | CEFBS_None, // G_FASIN |
| 17388 | CEFBS_None, // G_FATAN |
| 17389 | CEFBS_None, // G_FATAN2 |
| 17390 | CEFBS_None, // G_FCOSH |
| 17391 | CEFBS_None, // G_FSINH |
| 17392 | CEFBS_None, // G_FTANH |
| 17393 | CEFBS_None, // G_FSQRT |
| 17394 | CEFBS_None, // G_FFLOOR |
| 17395 | CEFBS_None, // G_FRINT |
| 17396 | CEFBS_None, // G_FNEARBYINT |
| 17397 | CEFBS_None, // G_ADDRSPACE_CAST |
| 17398 | CEFBS_None, // G_BLOCK_ADDR |
| 17399 | CEFBS_None, // G_JUMP_TABLE |
| 17400 | CEFBS_None, // G_DYN_STACKALLOC |
| 17401 | CEFBS_None, // G_STACKSAVE |
| 17402 | CEFBS_None, // G_STACKRESTORE |
| 17403 | CEFBS_None, // G_STRICT_FADD |
| 17404 | CEFBS_None, // G_STRICT_FSUB |
| 17405 | CEFBS_None, // G_STRICT_FMUL |
| 17406 | CEFBS_None, // G_STRICT_FDIV |
| 17407 | CEFBS_None, // G_STRICT_FREM |
| 17408 | CEFBS_None, // G_STRICT_FMA |
| 17409 | CEFBS_None, // G_STRICT_FSQRT |
| 17410 | CEFBS_None, // G_STRICT_FLDEXP |
| 17411 | CEFBS_None, // G_STRICT_FCMP |
| 17412 | CEFBS_None, // G_STRICT_FCMPS |
| 17413 | CEFBS_None, // G_READ_REGISTER |
| 17414 | CEFBS_None, // G_WRITE_REGISTER |
| 17415 | CEFBS_None, // G_MEMCPY |
| 17416 | CEFBS_None, // G_MEMCPY_INLINE |
| 17417 | CEFBS_None, // G_MEMMOVE |
| 17418 | CEFBS_None, // G_MEMSET |
| 17419 | CEFBS_None, // G_BZERO |
| 17420 | CEFBS_None, // G_MEMSET_INLINE |
| 17421 | CEFBS_None, // G_TRAP |
| 17422 | CEFBS_None, // G_DEBUGTRAP |
| 17423 | CEFBS_None, // G_UBSANTRAP |
| 17424 | CEFBS_None, // G_VECREDUCE_SEQ_FADD |
| 17425 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL |
| 17426 | CEFBS_None, // G_VECREDUCE_FADD |
| 17427 | CEFBS_None, // G_VECREDUCE_FMUL |
| 17428 | CEFBS_None, // G_VECREDUCE_FMAX |
| 17429 | CEFBS_None, // G_VECREDUCE_FMIN |
| 17430 | CEFBS_None, // G_VECREDUCE_FMAXIMUM |
| 17431 | CEFBS_None, // G_VECREDUCE_FMINIMUM |
| 17432 | CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM |
| 17433 | CEFBS_None, // G_VECREDUCE_FMINIMUMNUM |
| 17434 | CEFBS_None, // G_VECREDUCE_ADD |
| 17435 | CEFBS_None, // G_VECREDUCE_MUL |
| 17436 | CEFBS_None, // G_VECREDUCE_AND |
| 17437 | CEFBS_None, // G_VECREDUCE_OR |
| 17438 | CEFBS_None, // G_VECREDUCE_XOR |
| 17439 | CEFBS_None, // G_VECREDUCE_SMAX |
| 17440 | CEFBS_None, // G_VECREDUCE_SMIN |
| 17441 | CEFBS_None, // G_VECREDUCE_UMAX |
| 17442 | CEFBS_None, // G_VECREDUCE_UMIN |
| 17443 | CEFBS_None, // G_SBFX |
| 17444 | CEFBS_None, // G_UBFX |
| 17445 | CEFBS_IsARM, // ADDSri |
| 17446 | CEFBS_IsARM, // ADDSrr |
| 17447 | CEFBS_IsARM, // ADDSrsi |
| 17448 | CEFBS_IsARM, // ADDSrsr |
| 17449 | CEFBS_None, // ADJCALLSTACKDOWN |
| 17450 | CEFBS_None, // ADJCALLSTACKUP |
| 17451 | CEFBS_IsARM, // ASRi |
| 17452 | CEFBS_IsARM, // ASRr |
| 17453 | CEFBS_IsARM, // ASRs1 |
| 17454 | CEFBS_IsARM, // B |
| 17455 | CEFBS_None, // BCCZi64 |
| 17456 | CEFBS_None, // BCCi64 |
| 17457 | CEFBS_IsARM_HasV5T, // BLX_noip |
| 17458 | CEFBS_IsARM_HasV5T, // BLX_pred_noip |
| 17459 | CEFBS_IsARM, // BL_PUSHLR |
| 17460 | CEFBS_IsARM, // BMOVPCB_CALL |
| 17461 | CEFBS_IsARM, // BMOVPCRX_CALL |
| 17462 | CEFBS_IsARM, // BR_JTadd |
| 17463 | CEFBS_IsARM, // BR_JTm_i12 |
| 17464 | CEFBS_IsARM, // BR_JTm_rs |
| 17465 | CEFBS_IsARM, // BR_JTr |
| 17466 | CEFBS_IsARM_HasV4T, // BX_CALL |
| 17467 | CEFBS_None, // CATCHRET |
| 17468 | CEFBS_None, // CLEANUPRET |
| 17469 | CEFBS_None, // CMP_SWAP_16 |
| 17470 | CEFBS_None, // CMP_SWAP_32 |
| 17471 | CEFBS_None, // CMP_SWAP_64 |
| 17472 | CEFBS_None, // CMP_SWAP_8 |
| 17473 | CEFBS_None, // CONSTPOOL_ENTRY |
| 17474 | CEFBS_None, // COPY_STRUCT_BYVAL_I32 |
| 17475 | CEFBS_IsARM, // ITasm |
| 17476 | CEFBS_None, // Int_eh_sjlj_dispatchsetup |
| 17477 | CEFBS_IsARM, // Int_eh_sjlj_longjmp |
| 17478 | CEFBS_IsARM_HasVFP2, // Int_eh_sjlj_setjmp |
| 17479 | CEFBS_IsARM, // Int_eh_sjlj_setjmp_nofp |
| 17480 | CEFBS_None, // Int_eh_sjlj_setup_dispatch |
| 17481 | CEFBS_None, // JUMPTABLE_ADDRS |
| 17482 | CEFBS_None, // JUMPTABLE_INSTS |
| 17483 | CEFBS_None, // JUMPTABLE_TBB |
| 17484 | CEFBS_None, // JUMPTABLE_TBH |
| 17485 | CEFBS_IsARM, // KCFI_CHECK_ARM |
| 17486 | CEFBS_None, // KCFI_CHECK_Thumb1 |
| 17487 | CEFBS_IsThumb2, // KCFI_CHECK_Thumb2 |
| 17488 | CEFBS_IsARM, // LDMIA_RET |
| 17489 | CEFBS_IsARM, // LDRBT_POST |
| 17490 | CEFBS_IsARM, // LDRConstPool |
| 17491 | CEFBS_IsARM, // LDRHTii |
| 17492 | CEFBS_IsARM, // LDRLIT_ga_abs |
| 17493 | CEFBS_IsARM, // LDRLIT_ga_pcrel |
| 17494 | CEFBS_IsARM, // LDRLIT_ga_pcrel_ldr |
| 17495 | CEFBS_IsARM, // LDRSBTii |
| 17496 | CEFBS_IsARM, // LDRSHTii |
| 17497 | CEFBS_IsARM, // LDRT_POST |
| 17498 | CEFBS_IsARM, // LEApcrel |
| 17499 | CEFBS_IsARM, // LEApcrelJT |
| 17500 | CEFBS_IsARM_HasV5TE, // LOADDUAL |
| 17501 | CEFBS_IsARM, // LSLi |
| 17502 | CEFBS_IsARM, // LSLr |
| 17503 | CEFBS_IsARM, // LSRi |
| 17504 | CEFBS_IsARM, // LSRr |
| 17505 | CEFBS_IsARM, // LSRs1 |
| 17506 | CEFBS_None, // MEMCPY |
| 17507 | CEFBS_IsARM, // MLAv5 |
| 17508 | CEFBS_IsARM, // MOVCCi |
| 17509 | CEFBS_IsARM_HasV6T2, // MOVCCi16 |
| 17510 | CEFBS_IsARM_HasV6T2, // MOVCCi32imm |
| 17511 | CEFBS_IsARM, // MOVCCr |
| 17512 | CEFBS_IsARM, // MOVCCsi |
| 17513 | CEFBS_IsARM, // MOVCCsr |
| 17514 | CEFBS_IsARM, // MOVPCRX |
| 17515 | CEFBS_None, // MOVTi16_ga_pcrel |
| 17516 | CEFBS_IsARM, // MOV_ga_pcrel |
| 17517 | CEFBS_IsARM, // MOV_ga_pcrel_ldr |
| 17518 | CEFBS_None, // MOVi16_ga_pcrel |
| 17519 | CEFBS_IsARM, // MOVi32imm |
| 17520 | CEFBS_HasMVEInt, // MQPRCopy |
| 17521 | CEFBS_HasMVEInt, // MQQPRLoad |
| 17522 | CEFBS_HasMVEInt, // MQQPRStore |
| 17523 | CEFBS_HasMVEInt, // MQQQQPRLoad |
| 17524 | CEFBS_HasMVEInt, // MQQQQPRStore |
| 17525 | CEFBS_IsARM, // MULv5 |
| 17526 | CEFBS_None, // MVE_MEMCPYLOOPINST |
| 17527 | CEFBS_None, // MVE_MEMSETLOOPINST |
| 17528 | CEFBS_IsARM, // MVNCCi |
| 17529 | CEFBS_IsARM, // PICADD |
| 17530 | CEFBS_IsARM, // PICLDR |
| 17531 | CEFBS_IsARM, // PICLDRB |
| 17532 | CEFBS_IsARM, // PICLDRH |
| 17533 | CEFBS_IsARM, // PICLDRSB |
| 17534 | CEFBS_IsARM, // PICLDRSH |
| 17535 | CEFBS_IsARM, // PICSTR |
| 17536 | CEFBS_IsARM, // PICSTRB |
| 17537 | CEFBS_IsARM, // PICSTRH |
| 17538 | CEFBS_IsARM, // RORi |
| 17539 | CEFBS_IsARM, // RORr |
| 17540 | CEFBS_IsARM, // RRX |
| 17541 | CEFBS_IsARM, // RRXi |
| 17542 | CEFBS_IsARM, // RSBSri |
| 17543 | CEFBS_IsARM, // RSBSrsi |
| 17544 | CEFBS_IsARM, // RSBSrsr |
| 17545 | CEFBS_None, // SEH_EpilogEnd |
| 17546 | CEFBS_None, // SEH_EpilogStart |
| 17547 | CEFBS_None, // SEH_Nop |
| 17548 | CEFBS_None, // SEH_Nop_Ret |
| 17549 | CEFBS_None, // SEH_PrologEnd |
| 17550 | CEFBS_None, // SEH_SaveFRegs |
| 17551 | CEFBS_None, // SEH_SaveLR |
| 17552 | CEFBS_None, // SEH_SaveRegs |
| 17553 | CEFBS_None, // SEH_SaveRegs_Ret |
| 17554 | CEFBS_None, // SEH_SaveSP |
| 17555 | CEFBS_None, // SEH_StackAlloc |
| 17556 | CEFBS_IsARM, // SMLALv5 |
| 17557 | CEFBS_IsARM, // SMULLv5 |
| 17558 | CEFBS_None, // SPACE |
| 17559 | CEFBS_IsARM_HasV5TE, // STOREDUAL |
| 17560 | CEFBS_IsARM, // STRBT_POST |
| 17561 | CEFBS_IsARM, // STRBi_preidx |
| 17562 | CEFBS_IsARM, // STRBr_preidx |
| 17563 | CEFBS_IsARM, // STRH_preidx |
| 17564 | CEFBS_IsARM, // STRT_POST |
| 17565 | CEFBS_IsARM, // STRi_preidx |
| 17566 | CEFBS_IsARM, // STRr_preidx |
| 17567 | CEFBS_IsARM, // SUBS_PC_LR |
| 17568 | CEFBS_IsARM, // SUBSri |
| 17569 | CEFBS_IsARM, // SUBSrr |
| 17570 | CEFBS_IsARM, // SUBSrsi |
| 17571 | CEFBS_IsARM, // SUBSrsr |
| 17572 | CEFBS_None, // SpeculationBarrierISBDSBEndBB |
| 17573 | CEFBS_None, // SpeculationBarrierSBEndBB |
| 17574 | CEFBS_IsARM, // TAILJMPd |
| 17575 | CEFBS_IsARM_HasV4T, // TAILJMPr |
| 17576 | CEFBS_IsARM, // TAILJMPr4 |
| 17577 | CEFBS_None, // TCRETURNdi |
| 17578 | CEFBS_None, // TCRETURNri |
| 17579 | CEFBS_None, // TCRETURNrinotr12 |
| 17580 | CEFBS_IsARM, // TPsoft |
| 17581 | CEFBS_IsARM, // UMLALv5 |
| 17582 | CEFBS_IsARM, // UMULLv5 |
| 17583 | CEFBS_HasNEON, // VLD1LNdAsm_16 |
| 17584 | CEFBS_HasNEON, // VLD1LNdAsm_32 |
| 17585 | CEFBS_HasNEON, // VLD1LNdAsm_8 |
| 17586 | CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_16 |
| 17587 | CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_32 |
| 17588 | CEFBS_HasNEON, // VLD1LNdWB_fixed_Asm_8 |
| 17589 | CEFBS_HasNEON, // VLD1LNdWB_register_Asm_16 |
| 17590 | CEFBS_HasNEON, // VLD1LNdWB_register_Asm_32 |
| 17591 | CEFBS_HasNEON, // VLD1LNdWB_register_Asm_8 |
| 17592 | CEFBS_HasNEON, // VLD2LNdAsm_16 |
| 17593 | CEFBS_HasNEON, // VLD2LNdAsm_32 |
| 17594 | CEFBS_HasNEON, // VLD2LNdAsm_8 |
| 17595 | CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_16 |
| 17596 | CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_32 |
| 17597 | CEFBS_HasNEON, // VLD2LNdWB_fixed_Asm_8 |
| 17598 | CEFBS_HasNEON, // VLD2LNdWB_register_Asm_16 |
| 17599 | CEFBS_HasNEON, // VLD2LNdWB_register_Asm_32 |
| 17600 | CEFBS_HasNEON, // VLD2LNdWB_register_Asm_8 |
| 17601 | CEFBS_HasNEON, // VLD2LNqAsm_16 |
| 17602 | CEFBS_HasNEON, // VLD2LNqAsm_32 |
| 17603 | CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_16 |
| 17604 | CEFBS_HasNEON, // VLD2LNqWB_fixed_Asm_32 |
| 17605 | CEFBS_HasNEON, // VLD2LNqWB_register_Asm_16 |
| 17606 | CEFBS_HasNEON, // VLD2LNqWB_register_Asm_32 |
| 17607 | CEFBS_HasNEON, // VLD3DUPdAsm_16 |
| 17608 | CEFBS_HasNEON, // VLD3DUPdAsm_32 |
| 17609 | CEFBS_HasNEON, // VLD3DUPdAsm_8 |
| 17610 | CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_16 |
| 17611 | CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_32 |
| 17612 | CEFBS_HasNEON, // VLD3DUPdWB_fixed_Asm_8 |
| 17613 | CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_16 |
| 17614 | CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_32 |
| 17615 | CEFBS_HasNEON, // VLD3DUPdWB_register_Asm_8 |
| 17616 | CEFBS_HasNEON, // VLD3DUPqAsm_16 |
| 17617 | CEFBS_HasNEON, // VLD3DUPqAsm_32 |
| 17618 | CEFBS_HasNEON, // VLD3DUPqAsm_8 |
| 17619 | CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_16 |
| 17620 | CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_32 |
| 17621 | CEFBS_HasNEON, // VLD3DUPqWB_fixed_Asm_8 |
| 17622 | CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_16 |
| 17623 | CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_32 |
| 17624 | CEFBS_HasNEON, // VLD3DUPqWB_register_Asm_8 |
| 17625 | CEFBS_HasNEON, // VLD3LNdAsm_16 |
| 17626 | CEFBS_HasNEON, // VLD3LNdAsm_32 |
| 17627 | CEFBS_HasNEON, // VLD3LNdAsm_8 |
| 17628 | CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_16 |
| 17629 | CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_32 |
| 17630 | CEFBS_HasNEON, // VLD3LNdWB_fixed_Asm_8 |
| 17631 | CEFBS_HasNEON, // VLD3LNdWB_register_Asm_16 |
| 17632 | CEFBS_HasNEON, // VLD3LNdWB_register_Asm_32 |
| 17633 | CEFBS_HasNEON, // VLD3LNdWB_register_Asm_8 |
| 17634 | CEFBS_HasNEON, // VLD3LNqAsm_16 |
| 17635 | CEFBS_HasNEON, // VLD3LNqAsm_32 |
| 17636 | CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_16 |
| 17637 | CEFBS_HasNEON, // VLD3LNqWB_fixed_Asm_32 |
| 17638 | CEFBS_HasNEON, // VLD3LNqWB_register_Asm_16 |
| 17639 | CEFBS_HasNEON, // VLD3LNqWB_register_Asm_32 |
| 17640 | CEFBS_HasNEON, // VLD3dAsm_16 |
| 17641 | CEFBS_HasNEON, // VLD3dAsm_32 |
| 17642 | CEFBS_HasNEON, // VLD3dAsm_8 |
| 17643 | CEFBS_HasNEON, // VLD3dWB_fixed_Asm_16 |
| 17644 | CEFBS_HasNEON, // VLD3dWB_fixed_Asm_32 |
| 17645 | CEFBS_HasNEON, // VLD3dWB_fixed_Asm_8 |
| 17646 | CEFBS_HasNEON, // VLD3dWB_register_Asm_16 |
| 17647 | CEFBS_HasNEON, // VLD3dWB_register_Asm_32 |
| 17648 | CEFBS_HasNEON, // VLD3dWB_register_Asm_8 |
| 17649 | CEFBS_HasNEON, // VLD3qAsm_16 |
| 17650 | CEFBS_HasNEON, // VLD3qAsm_32 |
| 17651 | CEFBS_HasNEON, // VLD3qAsm_8 |
| 17652 | CEFBS_HasNEON, // VLD3qWB_fixed_Asm_16 |
| 17653 | CEFBS_HasNEON, // VLD3qWB_fixed_Asm_32 |
| 17654 | CEFBS_HasNEON, // VLD3qWB_fixed_Asm_8 |
| 17655 | CEFBS_HasNEON, // VLD3qWB_register_Asm_16 |
| 17656 | CEFBS_HasNEON, // VLD3qWB_register_Asm_32 |
| 17657 | CEFBS_HasNEON, // VLD3qWB_register_Asm_8 |
| 17658 | CEFBS_HasNEON, // VLD4DUPdAsm_16 |
| 17659 | CEFBS_HasNEON, // VLD4DUPdAsm_32 |
| 17660 | CEFBS_HasNEON, // VLD4DUPdAsm_8 |
| 17661 | CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_16 |
| 17662 | CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_32 |
| 17663 | CEFBS_HasNEON, // VLD4DUPdWB_fixed_Asm_8 |
| 17664 | CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_16 |
| 17665 | CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_32 |
| 17666 | CEFBS_HasNEON, // VLD4DUPdWB_register_Asm_8 |
| 17667 | CEFBS_HasNEON, // VLD4DUPqAsm_16 |
| 17668 | CEFBS_HasNEON, // VLD4DUPqAsm_32 |
| 17669 | CEFBS_HasNEON, // VLD4DUPqAsm_8 |
| 17670 | CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_16 |
| 17671 | CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_32 |
| 17672 | CEFBS_HasNEON, // VLD4DUPqWB_fixed_Asm_8 |
| 17673 | CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_16 |
| 17674 | CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_32 |
| 17675 | CEFBS_HasNEON, // VLD4DUPqWB_register_Asm_8 |
| 17676 | CEFBS_HasNEON, // VLD4LNdAsm_16 |
| 17677 | CEFBS_HasNEON, // VLD4LNdAsm_32 |
| 17678 | CEFBS_HasNEON, // VLD4LNdAsm_8 |
| 17679 | CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_16 |
| 17680 | CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_32 |
| 17681 | CEFBS_HasNEON, // VLD4LNdWB_fixed_Asm_8 |
| 17682 | CEFBS_HasNEON, // VLD4LNdWB_register_Asm_16 |
| 17683 | CEFBS_HasNEON, // VLD4LNdWB_register_Asm_32 |
| 17684 | CEFBS_HasNEON, // VLD4LNdWB_register_Asm_8 |
| 17685 | CEFBS_HasNEON, // VLD4LNqAsm_16 |
| 17686 | CEFBS_HasNEON, // VLD4LNqAsm_32 |
| 17687 | CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_16 |
| 17688 | CEFBS_HasNEON, // VLD4LNqWB_fixed_Asm_32 |
| 17689 | CEFBS_HasNEON, // VLD4LNqWB_register_Asm_16 |
| 17690 | CEFBS_HasNEON, // VLD4LNqWB_register_Asm_32 |
| 17691 | CEFBS_HasNEON, // VLD4dAsm_16 |
| 17692 | CEFBS_HasNEON, // VLD4dAsm_32 |
| 17693 | CEFBS_HasNEON, // VLD4dAsm_8 |
| 17694 | CEFBS_HasNEON, // VLD4dWB_fixed_Asm_16 |
| 17695 | CEFBS_HasNEON, // VLD4dWB_fixed_Asm_32 |
| 17696 | CEFBS_HasNEON, // VLD4dWB_fixed_Asm_8 |
| 17697 | CEFBS_HasNEON, // VLD4dWB_register_Asm_16 |
| 17698 | CEFBS_HasNEON, // VLD4dWB_register_Asm_32 |
| 17699 | CEFBS_HasNEON, // VLD4dWB_register_Asm_8 |
| 17700 | CEFBS_HasNEON, // VLD4qAsm_16 |
| 17701 | CEFBS_HasNEON, // VLD4qAsm_32 |
| 17702 | CEFBS_HasNEON, // VLD4qAsm_8 |
| 17703 | CEFBS_HasNEON, // VLD4qWB_fixed_Asm_16 |
| 17704 | CEFBS_HasNEON, // VLD4qWB_fixed_Asm_32 |
| 17705 | CEFBS_HasNEON, // VLD4qWB_fixed_Asm_8 |
| 17706 | CEFBS_HasNEON, // VLD4qWB_register_Asm_16 |
| 17707 | CEFBS_HasNEON, // VLD4qWB_register_Asm_32 |
| 17708 | CEFBS_HasNEON, // VLD4qWB_register_Asm_8 |
| 17709 | CEFBS_None, // VMOVD0 |
| 17710 | CEFBS_HasFPRegs64, // VMOVDcc |
| 17711 | CEFBS_HasFPRegs, // VMOVHcc |
| 17712 | CEFBS_None, // VMOVQ0 |
| 17713 | CEFBS_HasFPRegs, // VMOVScc |
| 17714 | CEFBS_HasNEON, // VST1LNdAsm_16 |
| 17715 | CEFBS_HasNEON, // VST1LNdAsm_32 |
| 17716 | CEFBS_HasNEON, // VST1LNdAsm_8 |
| 17717 | CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_16 |
| 17718 | CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_32 |
| 17719 | CEFBS_HasNEON, // VST1LNdWB_fixed_Asm_8 |
| 17720 | CEFBS_HasNEON, // VST1LNdWB_register_Asm_16 |
| 17721 | CEFBS_HasNEON, // VST1LNdWB_register_Asm_32 |
| 17722 | CEFBS_HasNEON, // VST1LNdWB_register_Asm_8 |
| 17723 | CEFBS_HasNEON, // VST2LNdAsm_16 |
| 17724 | CEFBS_HasNEON, // VST2LNdAsm_32 |
| 17725 | CEFBS_HasNEON, // VST2LNdAsm_8 |
| 17726 | CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_16 |
| 17727 | CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_32 |
| 17728 | CEFBS_HasNEON, // VST2LNdWB_fixed_Asm_8 |
| 17729 | CEFBS_HasNEON, // VST2LNdWB_register_Asm_16 |
| 17730 | CEFBS_HasNEON, // VST2LNdWB_register_Asm_32 |
| 17731 | CEFBS_HasNEON, // VST2LNdWB_register_Asm_8 |
| 17732 | CEFBS_HasNEON, // VST2LNqAsm_16 |
| 17733 | CEFBS_HasNEON, // VST2LNqAsm_32 |
| 17734 | CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_16 |
| 17735 | CEFBS_HasNEON, // VST2LNqWB_fixed_Asm_32 |
| 17736 | CEFBS_HasNEON, // VST2LNqWB_register_Asm_16 |
| 17737 | CEFBS_HasNEON, // VST2LNqWB_register_Asm_32 |
| 17738 | CEFBS_HasNEON, // VST3LNdAsm_16 |
| 17739 | CEFBS_HasNEON, // VST3LNdAsm_32 |
| 17740 | CEFBS_HasNEON, // VST3LNdAsm_8 |
| 17741 | CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_16 |
| 17742 | CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_32 |
| 17743 | CEFBS_HasNEON, // VST3LNdWB_fixed_Asm_8 |
| 17744 | CEFBS_HasNEON, // VST3LNdWB_register_Asm_16 |
| 17745 | CEFBS_HasNEON, // VST3LNdWB_register_Asm_32 |
| 17746 | CEFBS_HasNEON, // VST3LNdWB_register_Asm_8 |
| 17747 | CEFBS_HasNEON, // VST3LNqAsm_16 |
| 17748 | CEFBS_HasNEON, // VST3LNqAsm_32 |
| 17749 | CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_16 |
| 17750 | CEFBS_HasNEON, // VST3LNqWB_fixed_Asm_32 |
| 17751 | CEFBS_HasNEON, // VST3LNqWB_register_Asm_16 |
| 17752 | CEFBS_HasNEON, // VST3LNqWB_register_Asm_32 |
| 17753 | CEFBS_HasNEON, // VST3dAsm_16 |
| 17754 | CEFBS_HasNEON, // VST3dAsm_32 |
| 17755 | CEFBS_HasNEON, // VST3dAsm_8 |
| 17756 | CEFBS_HasNEON, // VST3dWB_fixed_Asm_16 |
| 17757 | CEFBS_HasNEON, // VST3dWB_fixed_Asm_32 |
| 17758 | CEFBS_HasNEON, // VST3dWB_fixed_Asm_8 |
| 17759 | CEFBS_HasNEON, // VST3dWB_register_Asm_16 |
| 17760 | CEFBS_HasNEON, // VST3dWB_register_Asm_32 |
| 17761 | CEFBS_HasNEON, // VST3dWB_register_Asm_8 |
| 17762 | CEFBS_HasNEON, // VST3qAsm_16 |
| 17763 | CEFBS_HasNEON, // VST3qAsm_32 |
| 17764 | CEFBS_HasNEON, // VST3qAsm_8 |
| 17765 | CEFBS_HasNEON, // VST3qWB_fixed_Asm_16 |
| 17766 | CEFBS_HasNEON, // VST3qWB_fixed_Asm_32 |
| 17767 | CEFBS_HasNEON, // VST3qWB_fixed_Asm_8 |
| 17768 | CEFBS_HasNEON, // VST3qWB_register_Asm_16 |
| 17769 | CEFBS_HasNEON, // VST3qWB_register_Asm_32 |
| 17770 | CEFBS_HasNEON, // VST3qWB_register_Asm_8 |
| 17771 | CEFBS_HasNEON, // VST4LNdAsm_16 |
| 17772 | CEFBS_HasNEON, // VST4LNdAsm_32 |
| 17773 | CEFBS_HasNEON, // VST4LNdAsm_8 |
| 17774 | CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_16 |
| 17775 | CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_32 |
| 17776 | CEFBS_HasNEON, // VST4LNdWB_fixed_Asm_8 |
| 17777 | CEFBS_HasNEON, // VST4LNdWB_register_Asm_16 |
| 17778 | CEFBS_HasNEON, // VST4LNdWB_register_Asm_32 |
| 17779 | CEFBS_HasNEON, // VST4LNdWB_register_Asm_8 |
| 17780 | CEFBS_HasNEON, // VST4LNqAsm_16 |
| 17781 | CEFBS_HasNEON, // VST4LNqAsm_32 |
| 17782 | CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_16 |
| 17783 | CEFBS_HasNEON, // VST4LNqWB_fixed_Asm_32 |
| 17784 | CEFBS_HasNEON, // VST4LNqWB_register_Asm_16 |
| 17785 | CEFBS_HasNEON, // VST4LNqWB_register_Asm_32 |
| 17786 | CEFBS_HasNEON, // VST4dAsm_16 |
| 17787 | CEFBS_HasNEON, // VST4dAsm_32 |
| 17788 | CEFBS_HasNEON, // VST4dAsm_8 |
| 17789 | CEFBS_HasNEON, // VST4dWB_fixed_Asm_16 |
| 17790 | CEFBS_HasNEON, // VST4dWB_fixed_Asm_32 |
| 17791 | CEFBS_HasNEON, // VST4dWB_fixed_Asm_8 |
| 17792 | CEFBS_HasNEON, // VST4dWB_register_Asm_16 |
| 17793 | CEFBS_HasNEON, // VST4dWB_register_Asm_32 |
| 17794 | CEFBS_HasNEON, // VST4dWB_register_Asm_8 |
| 17795 | CEFBS_HasNEON, // VST4qAsm_16 |
| 17796 | CEFBS_HasNEON, // VST4qAsm_32 |
| 17797 | CEFBS_HasNEON, // VST4qAsm_8 |
| 17798 | CEFBS_HasNEON, // VST4qWB_fixed_Asm_16 |
| 17799 | CEFBS_HasNEON, // VST4qWB_fixed_Asm_32 |
| 17800 | CEFBS_HasNEON, // VST4qWB_fixed_Asm_8 |
| 17801 | CEFBS_HasNEON, // VST4qWB_register_Asm_16 |
| 17802 | CEFBS_HasNEON, // VST4qWB_register_Asm_32 |
| 17803 | CEFBS_HasNEON, // VST4qWB_register_Asm_8 |
| 17804 | CEFBS_None, // WIN__CHKSTK |
| 17805 | CEFBS_None, // WIN__DBZCHK |
| 17806 | CEFBS_IsThumb2, // t2ADDSri |
| 17807 | CEFBS_IsThumb2, // t2ADDSrr |
| 17808 | CEFBS_IsThumb2, // t2ADDSrs |
| 17809 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BF_LabelPseudo |
| 17810 | CEFBS_IsThumb_HasV8MBaseline, // t2BR_JT |
| 17811 | CEFBS_IsThumb, // t2BXAUT_RET |
| 17812 | CEFBS_IsThumb2, // t2CALL_BTI |
| 17813 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DoLoopStart |
| 17814 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DoLoopStartTP |
| 17815 | CEFBS_IsThumb2, // t2LDMIA_RET |
| 17816 | CEFBS_IsThumb2, // t2LDRB_OFFSET_imm |
| 17817 | CEFBS_IsThumb2, // t2LDRB_POST_imm |
| 17818 | CEFBS_IsThumb2, // t2LDRB_PRE_imm |
| 17819 | CEFBS_IsThumb2, // t2LDRBpcrel |
| 17820 | CEFBS_IsThumb2, // t2LDRConstPool |
| 17821 | CEFBS_IsThumb2, // t2LDRH_OFFSET_imm |
| 17822 | CEFBS_IsThumb2, // t2LDRH_POST_imm |
| 17823 | CEFBS_IsThumb2, // t2LDRH_PRE_imm |
| 17824 | CEFBS_IsThumb2, // t2LDRHpcrel |
| 17825 | CEFBS_IsThumb_HasV8MBaseline, // t2LDRLIT_ga_pcrel |
| 17826 | CEFBS_IsThumb2, // t2LDRSB_OFFSET_imm |
| 17827 | CEFBS_IsThumb2, // t2LDRSB_POST_imm |
| 17828 | CEFBS_IsThumb2, // t2LDRSB_PRE_imm |
| 17829 | CEFBS_IsThumb2, // t2LDRSBpcrel |
| 17830 | CEFBS_IsThumb2, // t2LDRSH_OFFSET_imm |
| 17831 | CEFBS_IsThumb2, // t2LDRSH_POST_imm |
| 17832 | CEFBS_IsThumb2, // t2LDRSH_PRE_imm |
| 17833 | CEFBS_IsThumb2, // t2LDRSHpcrel |
| 17834 | CEFBS_IsThumb2, // t2LDR_POST_imm |
| 17835 | CEFBS_IsThumb2, // t2LDR_PRE_imm |
| 17836 | CEFBS_IsThumb2, // t2LDRpci_pic |
| 17837 | CEFBS_IsThumb2, // t2LDRpcrel |
| 17838 | CEFBS_IsThumb2, // t2LEApcrel |
| 17839 | CEFBS_IsThumb2, // t2LEApcrelJT |
| 17840 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopDec |
| 17841 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopEnd |
| 17842 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LoopEndDec |
| 17843 | CEFBS_IsThumb2, // t2MOVCCasr |
| 17844 | CEFBS_IsThumb2, // t2MOVCCi |
| 17845 | CEFBS_IsThumb2, // t2MOVCCi16 |
| 17846 | CEFBS_IsThumb2, // t2MOVCCi32imm |
| 17847 | CEFBS_IsThumb2, // t2MOVCClsl |
| 17848 | CEFBS_IsThumb2, // t2MOVCClsr |
| 17849 | CEFBS_IsThumb2, // t2MOVCCr |
| 17850 | CEFBS_IsThumb2, // t2MOVCCror |
| 17851 | CEFBS_IsThumb2, // t2MOVSsi |
| 17852 | CEFBS_IsThumb2, // t2MOVSsr |
| 17853 | CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16_ga_pcrel |
| 17854 | CEFBS_IsThumb_HasV8MBaseline, // t2MOV_ga_pcrel |
| 17855 | CEFBS_None, // t2MOVi16_ga_pcrel |
| 17856 | CEFBS_IsThumb, // t2MOVi32imm |
| 17857 | CEFBS_IsThumb2, // t2MOVsi |
| 17858 | CEFBS_IsThumb2, // t2MOVsr |
| 17859 | CEFBS_IsThumb2, // t2MVNCCi |
| 17860 | CEFBS_IsThumb2, // t2RSBSri |
| 17861 | CEFBS_IsThumb2, // t2RSBSrs |
| 17862 | CEFBS_IsThumb2, // t2STRB_OFFSET_imm |
| 17863 | CEFBS_IsThumb2, // t2STRB_POST_imm |
| 17864 | CEFBS_IsThumb2, // t2STRB_PRE_imm |
| 17865 | CEFBS_IsThumb2, // t2STRB_preidx |
| 17866 | CEFBS_IsThumb2, // t2STRH_OFFSET_imm |
| 17867 | CEFBS_IsThumb2, // t2STRH_POST_imm |
| 17868 | CEFBS_IsThumb2, // t2STRH_PRE_imm |
| 17869 | CEFBS_IsThumb2, // t2STRH_preidx |
| 17870 | CEFBS_IsThumb2, // t2STR_POST_imm |
| 17871 | CEFBS_IsThumb2, // t2STR_PRE_imm |
| 17872 | CEFBS_IsThumb2, // t2STR_preidx |
| 17873 | CEFBS_IsThumb2, // t2SUBSri |
| 17874 | CEFBS_IsThumb2, // t2SUBSrr |
| 17875 | CEFBS_IsThumb2, // t2SUBSrs |
| 17876 | CEFBS_None, // t2SpeculationBarrierISBDSBEndBB |
| 17877 | CEFBS_None, // t2SpeculationBarrierSBEndBB |
| 17878 | CEFBS_IsThumb2, // t2TBB_JT |
| 17879 | CEFBS_IsThumb2, // t2TBH_JT |
| 17880 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopSetup |
| 17881 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStart |
| 17882 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStartLR |
| 17883 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WhileLoopStartTP |
| 17884 | CEFBS_None, // tADCS |
| 17885 | CEFBS_None, // tADDSi3 |
| 17886 | CEFBS_None, // tADDSi8 |
| 17887 | CEFBS_None, // tADDSrr |
| 17888 | CEFBS_IsThumb, // tADDframe |
| 17889 | CEFBS_IsThumb, // tADJCALLSTACKDOWN |
| 17890 | CEFBS_IsThumb, // tADJCALLSTACKUP |
| 17891 | CEFBS_IsThumb_Has8MSecExt, // tBLXNS_CALL |
| 17892 | CEFBS_IsThumb_HasV5T, // tBLXr_noip |
| 17893 | CEFBS_IsThumb, // tBL_PUSHLR |
| 17894 | CEFBS_IsThumb, // tBRIND |
| 17895 | CEFBS_IsThumb, // tBR_JTr |
| 17896 | CEFBS_IsThumb, // tBXNS_RET |
| 17897 | CEFBS_IsThumb, // tBX_CALL |
| 17898 | CEFBS_IsThumb, // tBX_RET |
| 17899 | CEFBS_IsThumb, // tBX_RET_vararg |
| 17900 | CEFBS_IsThumb, // tBfar |
| 17901 | CEFBS_None, // tCMP_SWAP_16 |
| 17902 | CEFBS_None, // tCMP_SWAP_32 |
| 17903 | CEFBS_None, // tCMP_SWAP_8 |
| 17904 | CEFBS_IsThumb, // tLDMIA_UPD |
| 17905 | CEFBS_IsThumb, // tLDRConstPool |
| 17906 | CEFBS_IsThumb, // tLDRLIT_ga_abs |
| 17907 | CEFBS_IsThumb, // tLDRLIT_ga_pcrel |
| 17908 | CEFBS_IsThumb, // tLDR_postidx |
| 17909 | CEFBS_IsThumb, // tLDRpci_pic |
| 17910 | CEFBS_IsThumb, // tLEApcrel |
| 17911 | CEFBS_IsThumb, // tLEApcrelJT |
| 17912 | CEFBS_None, // tLSLSri |
| 17913 | CEFBS_None, // tMOVCCr_pseudo |
| 17914 | CEFBS_None, // tMOVi32imm |
| 17915 | CEFBS_IsThumb, // tPOP_RET |
| 17916 | CEFBS_None, // tRSBS |
| 17917 | CEFBS_None, // tSBCS |
| 17918 | CEFBS_None, // tSUBSi3 |
| 17919 | CEFBS_None, // tSUBSi8 |
| 17920 | CEFBS_None, // tSUBSrr |
| 17921 | CEFBS_IsThumb_HasV8MBaseline, // tTAILJMPd |
| 17922 | CEFBS_IsThumb, // tTAILJMPdND |
| 17923 | CEFBS_IsThumb, // tTAILJMPr |
| 17924 | CEFBS_IsThumb, // tTBB_JT |
| 17925 | CEFBS_IsThumb, // tTBH_JT |
| 17926 | CEFBS_IsThumb, // tTPsoft |
| 17927 | CEFBS_IsARM, // ADCri |
| 17928 | CEFBS_IsARM, // ADCrr |
| 17929 | CEFBS_IsARM, // ADCrsi |
| 17930 | CEFBS_IsARM, // ADCrsr |
| 17931 | CEFBS_IsARM, // ADDri |
| 17932 | CEFBS_IsARM, // ADDrr |
| 17933 | CEFBS_IsARM, // ADDrsi |
| 17934 | CEFBS_IsARM, // ADDrsr |
| 17935 | CEFBS_IsARM, // ADR |
| 17936 | CEFBS_HasV8_HasAES, // AESD |
| 17937 | CEFBS_HasV8_HasAES, // AESE |
| 17938 | CEFBS_HasV8_HasAES, // AESIMC |
| 17939 | CEFBS_HasV8_HasAES, // AESMC |
| 17940 | CEFBS_IsARM, // ANDri |
| 17941 | CEFBS_IsARM, // ANDrr |
| 17942 | CEFBS_IsARM, // ANDrsi |
| 17943 | CEFBS_IsARM, // ANDrsr |
| 17944 | CEFBS_HasBF16_HasNEON, // BF16VDOTI_VDOTD |
| 17945 | CEFBS_HasBF16_HasNEON, // BF16VDOTI_VDOTQ |
| 17946 | CEFBS_HasBF16_HasNEON, // BF16VDOTS_VDOTD |
| 17947 | CEFBS_HasBF16_HasNEON, // BF16VDOTS_VDOTQ |
| 17948 | CEFBS_HasBF16_HasNEON, // BF16_VCVT |
| 17949 | CEFBS_HasBF16, // BF16_VCVTB |
| 17950 | CEFBS_HasBF16, // BF16_VCVTT |
| 17951 | CEFBS_IsARM_HasV6T2, // BFC |
| 17952 | CEFBS_IsARM_HasV6T2, // BFI |
| 17953 | CEFBS_IsARM, // BICri |
| 17954 | CEFBS_IsARM, // BICrr |
| 17955 | CEFBS_IsARM, // BICrsi |
| 17956 | CEFBS_IsARM, // BICrsr |
| 17957 | CEFBS_IsARM, // BKPT |
| 17958 | CEFBS_IsARM, // BL |
| 17959 | CEFBS_IsARM_HasV5T, // BLX |
| 17960 | CEFBS_IsARM_HasV5T, // BLX_pred |
| 17961 | CEFBS_IsARM_HasV5T, // BLXi |
| 17962 | CEFBS_IsARM, // BL_pred |
| 17963 | CEFBS_IsARM_HasV4T, // BX |
| 17964 | CEFBS_IsARM, // BXJ |
| 17965 | CEFBS_IsARM_HasV4T, // BX_RET |
| 17966 | CEFBS_IsARM_HasV4T, // BX_pred |
| 17967 | CEFBS_IsARM, // Bcc |
| 17968 | CEFBS_HasCDE, // CDE_CX1 |
| 17969 | CEFBS_HasCDE, // CDE_CX1A |
| 17970 | CEFBS_HasCDE, // CDE_CX1D |
| 17971 | CEFBS_HasCDE, // CDE_CX1DA |
| 17972 | CEFBS_HasCDE, // CDE_CX2 |
| 17973 | CEFBS_HasCDE, // CDE_CX2A |
| 17974 | CEFBS_HasCDE, // CDE_CX2D |
| 17975 | CEFBS_HasCDE, // CDE_CX2DA |
| 17976 | CEFBS_HasCDE, // CDE_CX3 |
| 17977 | CEFBS_HasCDE, // CDE_CX3A |
| 17978 | CEFBS_HasCDE, // CDE_CX3D |
| 17979 | CEFBS_HasCDE, // CDE_CX3DA |
| 17980 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1A_fpdp |
| 17981 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1A_fpsp |
| 17982 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX1A_vec |
| 17983 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1_fpdp |
| 17984 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX1_fpsp |
| 17985 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX1_vec |
| 17986 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2A_fpdp |
| 17987 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2A_fpsp |
| 17988 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX2A_vec |
| 17989 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2_fpdp |
| 17990 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX2_fpsp |
| 17991 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX2_vec |
| 17992 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3A_fpdp |
| 17993 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3A_fpsp |
| 17994 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX3A_vec |
| 17995 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3_fpdp |
| 17996 | CEFBS_HasCDE_HasFPRegs, // CDE_VCX3_fpsp |
| 17997 | CEFBS_HasCDE_HasMVEInt, // CDE_VCX3_vec |
| 17998 | CEFBS_IsARM_PreV8, // CDP |
| 17999 | CEFBS_IsARM_PreV8, // CDP2 |
| 18000 | CEFBS_IsARM_HasV6K, // CLREX |
| 18001 | CEFBS_IsARM_HasV5T, // CLZ |
| 18002 | CEFBS_IsARM, // CMNri |
| 18003 | CEFBS_IsARM, // CMNrr |
| 18004 | CEFBS_IsARM, // CMNrsi |
| 18005 | CEFBS_IsARM, // CMNrsr |
| 18006 | CEFBS_IsARM, // CMPri |
| 18007 | CEFBS_IsARM, // CMPrr |
| 18008 | CEFBS_IsARM, // CMPrsi |
| 18009 | CEFBS_IsARM, // CMPrsr |
| 18010 | CEFBS_IsARM, // CPS1p |
| 18011 | CEFBS_IsARM, // CPS2p |
| 18012 | CEFBS_IsARM, // CPS3p |
| 18013 | CEFBS_IsARM_HasCRC, // CRC32B |
| 18014 | CEFBS_IsARM_HasCRC, // CRC32CB |
| 18015 | CEFBS_IsARM_HasCRC, // CRC32CH |
| 18016 | CEFBS_IsARM_HasCRC, // CRC32CW |
| 18017 | CEFBS_IsARM_HasCRC, // CRC32H |
| 18018 | CEFBS_IsARM_HasCRC, // CRC32W |
| 18019 | CEFBS_IsARM_HasV7, // DBG |
| 18020 | CEFBS_IsARM_HasDB, // DMB |
| 18021 | CEFBS_IsARM_HasDB, // DSB |
| 18022 | CEFBS_IsARM, // EORri |
| 18023 | CEFBS_IsARM, // EORrr |
| 18024 | CEFBS_IsARM, // EORrsi |
| 18025 | CEFBS_IsARM, // EORrsr |
| 18026 | CEFBS_IsARM_HasVirtualization, // ERET |
| 18027 | CEFBS_HasVFP3_HasDPVFP, // FCONSTD |
| 18028 | CEFBS_HasFullFP16, // FCONSTH |
| 18029 | CEFBS_HasVFP3, // FCONSTS |
| 18030 | CEFBS_HasFPRegs, // FLDMXDB_UPD |
| 18031 | CEFBS_HasFPRegs, // FLDMXIA |
| 18032 | CEFBS_HasFPRegs, // FLDMXIA_UPD |
| 18033 | CEFBS_HasFPRegs, // FMSTAT |
| 18034 | CEFBS_HasFPRegs, // FSTMXDB_UPD |
| 18035 | CEFBS_HasFPRegs, // FSTMXIA |
| 18036 | CEFBS_HasFPRegs, // FSTMXIA_UPD |
| 18037 | CEFBS_IsARM_HasV6, // HINT |
| 18038 | CEFBS_IsARM_HasV8, // HLT |
| 18039 | CEFBS_IsARM_HasVirtualization, // HVC |
| 18040 | CEFBS_IsARM_HasDB, // ISB |
| 18041 | CEFBS_IsARM_HasAcquireRelease, // LDA |
| 18042 | CEFBS_IsARM_HasAcquireRelease, // LDAB |
| 18043 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEX |
| 18044 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXB |
| 18045 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXD |
| 18046 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // LDAEXH |
| 18047 | CEFBS_IsARM_HasAcquireRelease, // LDAH |
| 18048 | CEFBS_IsARM_PreV8, // LDC2L_OFFSET |
| 18049 | CEFBS_IsARM_PreV8, // LDC2L_OPTION |
| 18050 | CEFBS_IsARM_PreV8, // LDC2L_POST |
| 18051 | CEFBS_IsARM_PreV8, // LDC2L_PRE |
| 18052 | CEFBS_IsARM_PreV8, // LDC2_OFFSET |
| 18053 | CEFBS_IsARM_PreV8, // LDC2_OPTION |
| 18054 | CEFBS_IsARM_PreV8, // LDC2_POST |
| 18055 | CEFBS_IsARM_PreV8, // LDC2_PRE |
| 18056 | CEFBS_IsARM, // LDCL_OFFSET |
| 18057 | CEFBS_IsARM, // LDCL_OPTION |
| 18058 | CEFBS_IsARM, // LDCL_POST |
| 18059 | CEFBS_IsARM, // LDCL_PRE |
| 18060 | CEFBS_IsARM, // LDC_OFFSET |
| 18061 | CEFBS_IsARM, // LDC_OPTION |
| 18062 | CEFBS_IsARM, // LDC_POST |
| 18063 | CEFBS_IsARM, // LDC_PRE |
| 18064 | CEFBS_IsARM, // LDMDA |
| 18065 | CEFBS_IsARM, // LDMDA_UPD |
| 18066 | CEFBS_IsARM, // LDMDB |
| 18067 | CEFBS_IsARM, // LDMDB_UPD |
| 18068 | CEFBS_IsARM, // LDMIA |
| 18069 | CEFBS_IsARM, // LDMIA_UPD |
| 18070 | CEFBS_IsARM, // LDMIB |
| 18071 | CEFBS_IsARM, // LDMIB_UPD |
| 18072 | CEFBS_IsARM, // LDRBT_POST_IMM |
| 18073 | CEFBS_IsARM, // LDRBT_POST_REG |
| 18074 | CEFBS_IsARM, // LDRB_POST_IMM |
| 18075 | CEFBS_IsARM, // LDRB_POST_REG |
| 18076 | CEFBS_IsARM, // LDRB_PRE_IMM |
| 18077 | CEFBS_IsARM, // LDRB_PRE_REG |
| 18078 | CEFBS_IsARM, // LDRBi12 |
| 18079 | CEFBS_IsARM, // LDRBrs |
| 18080 | CEFBS_IsARM_HasV5TE, // LDRD |
| 18081 | CEFBS_IsARM, // LDRD_POST |
| 18082 | CEFBS_IsARM, // LDRD_PRE |
| 18083 | CEFBS_IsARM, // LDREX |
| 18084 | CEFBS_IsARM, // LDREXB |
| 18085 | CEFBS_IsARM, // LDREXD |
| 18086 | CEFBS_IsARM, // LDREXH |
| 18087 | CEFBS_IsARM, // LDRH |
| 18088 | CEFBS_IsARM, // LDRHTi |
| 18089 | CEFBS_IsARM, // LDRHTr |
| 18090 | CEFBS_IsARM, // LDRH_POST |
| 18091 | CEFBS_IsARM, // LDRH_PRE |
| 18092 | CEFBS_IsARM, // LDRSB |
| 18093 | CEFBS_IsARM, // LDRSBTi |
| 18094 | CEFBS_IsARM, // LDRSBTr |
| 18095 | CEFBS_IsARM, // LDRSB_POST |
| 18096 | CEFBS_IsARM, // LDRSB_PRE |
| 18097 | CEFBS_IsARM, // LDRSH |
| 18098 | CEFBS_IsARM, // LDRSHTi |
| 18099 | CEFBS_IsARM, // LDRSHTr |
| 18100 | CEFBS_IsARM, // LDRSH_POST |
| 18101 | CEFBS_IsARM, // LDRSH_PRE |
| 18102 | CEFBS_IsARM, // LDRT_POST_IMM |
| 18103 | CEFBS_IsARM, // LDRT_POST_REG |
| 18104 | CEFBS_IsARM, // LDR_POST_IMM |
| 18105 | CEFBS_IsARM, // LDR_POST_REG |
| 18106 | CEFBS_IsARM, // LDR_PRE_IMM |
| 18107 | CEFBS_IsARM, // LDR_PRE_REG |
| 18108 | CEFBS_IsARM, // LDRcp |
| 18109 | CEFBS_IsARM, // LDRi12 |
| 18110 | CEFBS_IsARM, // LDRrs |
| 18111 | CEFBS_IsARM, // MCR |
| 18112 | CEFBS_IsARM_PreV8, // MCR2 |
| 18113 | CEFBS_IsARM, // MCRR |
| 18114 | CEFBS_IsARM_PreV8, // MCRR2 |
| 18115 | CEFBS_IsARM_HasV6, // MLA |
| 18116 | CEFBS_IsARM_HasV6T2, // MLS |
| 18117 | CEFBS_IsARM, // MOVPCLR |
| 18118 | CEFBS_IsARM_HasV6T2, // MOVTi16 |
| 18119 | CEFBS_IsARM, // MOVi |
| 18120 | CEFBS_IsARM_HasV6T2, // MOVi16 |
| 18121 | CEFBS_IsARM, // MOVr |
| 18122 | CEFBS_IsARM, // MOVr_TC |
| 18123 | CEFBS_IsARM, // MOVsi |
| 18124 | CEFBS_IsARM, // MOVsr |
| 18125 | CEFBS_IsARM, // MRC |
| 18126 | CEFBS_IsARM_PreV8, // MRC2 |
| 18127 | CEFBS_IsARM, // MRRC |
| 18128 | CEFBS_IsARM_PreV8, // MRRC2 |
| 18129 | CEFBS_IsARM, // MRS |
| 18130 | CEFBS_IsARM_HasVirtualization, // MRSbanked |
| 18131 | CEFBS_IsARM, // MRSsys |
| 18132 | CEFBS_IsARM, // MSR |
| 18133 | CEFBS_IsARM_HasVirtualization, // MSRbanked |
| 18134 | CEFBS_IsARM, // MSRi |
| 18135 | CEFBS_IsARM_HasV6, // MUL |
| 18136 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLi |
| 18137 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_ASRLr |
| 18138 | CEFBS_HasMVEInt, // MVE_DLSTP_16 |
| 18139 | CEFBS_HasMVEInt, // MVE_DLSTP_32 |
| 18140 | CEFBS_HasMVEInt, // MVE_DLSTP_64 |
| 18141 | CEFBS_HasMVEInt, // MVE_DLSTP_8 |
| 18142 | CEFBS_HasMVEInt, // MVE_LCTP |
| 18143 | CEFBS_HasMVEInt, // MVE_LETP |
| 18144 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLi |
| 18145 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSLLr |
| 18146 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_LSRL |
| 18147 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHR |
| 18148 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQRSHRL |
| 18149 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHL |
| 18150 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SQSHLL |
| 18151 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHR |
| 18152 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_SRSHRL |
| 18153 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHL |
| 18154 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQRSHLL |
| 18155 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHL |
| 18156 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_UQSHLL |
| 18157 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHR |
| 18158 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_URSHRL |
| 18159 | CEFBS_HasMVEInt, // MVE_VABAVs16 |
| 18160 | CEFBS_HasMVEInt, // MVE_VABAVs32 |
| 18161 | CEFBS_HasMVEInt, // MVE_VABAVs8 |
| 18162 | CEFBS_HasMVEInt, // MVE_VABAVu16 |
| 18163 | CEFBS_HasMVEInt, // MVE_VABAVu32 |
| 18164 | CEFBS_HasMVEInt, // MVE_VABAVu8 |
| 18165 | CEFBS_HasMVEFloat, // MVE_VABDf16 |
| 18166 | CEFBS_HasMVEFloat, // MVE_VABDf32 |
| 18167 | CEFBS_HasMVEInt, // MVE_VABDs16 |
| 18168 | CEFBS_HasMVEInt, // MVE_VABDs32 |
| 18169 | CEFBS_HasMVEInt, // MVE_VABDs8 |
| 18170 | CEFBS_HasMVEInt, // MVE_VABDu16 |
| 18171 | CEFBS_HasMVEInt, // MVE_VABDu32 |
| 18172 | CEFBS_HasMVEInt, // MVE_VABDu8 |
| 18173 | CEFBS_HasMVEFloat, // MVE_VABSf16 |
| 18174 | CEFBS_HasMVEFloat, // MVE_VABSf32 |
| 18175 | CEFBS_HasMVEInt, // MVE_VABSs16 |
| 18176 | CEFBS_HasMVEInt, // MVE_VABSs32 |
| 18177 | CEFBS_HasMVEInt, // MVE_VABSs8 |
| 18178 | CEFBS_HasMVEInt, // MVE_VADC |
| 18179 | CEFBS_HasMVEInt, // MVE_VADCI |
| 18180 | CEFBS_HasMVEInt, // MVE_VADDLVs32acc |
| 18181 | CEFBS_HasMVEInt, // MVE_VADDLVs32no_acc |
| 18182 | CEFBS_HasMVEInt, // MVE_VADDLVu32acc |
| 18183 | CEFBS_HasMVEInt, // MVE_VADDLVu32no_acc |
| 18184 | CEFBS_HasMVEInt, // MVE_VADDVs16acc |
| 18185 | CEFBS_HasMVEInt, // MVE_VADDVs16no_acc |
| 18186 | CEFBS_HasMVEInt, // MVE_VADDVs32acc |
| 18187 | CEFBS_HasMVEInt, // MVE_VADDVs32no_acc |
| 18188 | CEFBS_HasMVEInt, // MVE_VADDVs8acc |
| 18189 | CEFBS_HasMVEInt, // MVE_VADDVs8no_acc |
| 18190 | CEFBS_HasMVEInt, // MVE_VADDVu16acc |
| 18191 | CEFBS_HasMVEInt, // MVE_VADDVu16no_acc |
| 18192 | CEFBS_HasMVEInt, // MVE_VADDVu32acc |
| 18193 | CEFBS_HasMVEInt, // MVE_VADDVu32no_acc |
| 18194 | CEFBS_HasMVEInt, // MVE_VADDVu8acc |
| 18195 | CEFBS_HasMVEInt, // MVE_VADDVu8no_acc |
| 18196 | CEFBS_HasMVEFloat, // MVE_VADD_qr_f16 |
| 18197 | CEFBS_HasMVEFloat, // MVE_VADD_qr_f32 |
| 18198 | CEFBS_HasMVEInt, // MVE_VADD_qr_i16 |
| 18199 | CEFBS_HasMVEInt, // MVE_VADD_qr_i32 |
| 18200 | CEFBS_HasMVEInt, // MVE_VADD_qr_i8 |
| 18201 | CEFBS_HasMVEFloat, // MVE_VADDf16 |
| 18202 | CEFBS_HasMVEFloat, // MVE_VADDf32 |
| 18203 | CEFBS_HasMVEInt, // MVE_VADDi16 |
| 18204 | CEFBS_HasMVEInt, // MVE_VADDi32 |
| 18205 | CEFBS_HasMVEInt, // MVE_VADDi8 |
| 18206 | CEFBS_HasMVEInt, // MVE_VAND |
| 18207 | CEFBS_HasMVEInt, // MVE_VBIC |
| 18208 | CEFBS_HasMVEInt, // MVE_VBICimmi16 |
| 18209 | CEFBS_HasMVEInt, // MVE_VBICimmi32 |
| 18210 | CEFBS_HasMVEInt, // MVE_VBRSR16 |
| 18211 | CEFBS_HasMVEInt, // MVE_VBRSR32 |
| 18212 | CEFBS_HasMVEInt, // MVE_VBRSR8 |
| 18213 | CEFBS_HasMVEFloat, // MVE_VCADDf16 |
| 18214 | CEFBS_HasMVEFloat, // MVE_VCADDf32 |
| 18215 | CEFBS_HasMVEInt, // MVE_VCADDi16 |
| 18216 | CEFBS_HasMVEInt, // MVE_VCADDi32 |
| 18217 | CEFBS_HasMVEInt, // MVE_VCADDi8 |
| 18218 | CEFBS_HasMVEInt, // MVE_VCLSs16 |
| 18219 | CEFBS_HasMVEInt, // MVE_VCLSs32 |
| 18220 | CEFBS_HasMVEInt, // MVE_VCLSs8 |
| 18221 | CEFBS_HasMVEInt, // MVE_VCLZs16 |
| 18222 | CEFBS_HasMVEInt, // MVE_VCLZs32 |
| 18223 | CEFBS_HasMVEInt, // MVE_VCLZs8 |
| 18224 | CEFBS_HasMVEFloat, // MVE_VCMLAf16 |
| 18225 | CEFBS_HasMVEFloat, // MVE_VCMLAf32 |
| 18226 | CEFBS_HasMVEFloat, // MVE_VCMPf16 |
| 18227 | CEFBS_HasMVEFloat, // MVE_VCMPf16r |
| 18228 | CEFBS_HasMVEFloat, // MVE_VCMPf32 |
| 18229 | CEFBS_HasMVEFloat, // MVE_VCMPf32r |
| 18230 | CEFBS_HasMVEInt, // MVE_VCMPi16 |
| 18231 | CEFBS_HasMVEInt, // MVE_VCMPi16r |
| 18232 | CEFBS_HasMVEInt, // MVE_VCMPi32 |
| 18233 | CEFBS_HasMVEInt, // MVE_VCMPi32r |
| 18234 | CEFBS_HasMVEInt, // MVE_VCMPi8 |
| 18235 | CEFBS_HasMVEInt, // MVE_VCMPi8r |
| 18236 | CEFBS_HasMVEInt, // MVE_VCMPs16 |
| 18237 | CEFBS_HasMVEInt, // MVE_VCMPs16r |
| 18238 | CEFBS_HasMVEInt, // MVE_VCMPs32 |
| 18239 | CEFBS_HasMVEInt, // MVE_VCMPs32r |
| 18240 | CEFBS_HasMVEInt, // MVE_VCMPs8 |
| 18241 | CEFBS_HasMVEInt, // MVE_VCMPs8r |
| 18242 | CEFBS_HasMVEInt, // MVE_VCMPu16 |
| 18243 | CEFBS_HasMVEInt, // MVE_VCMPu16r |
| 18244 | CEFBS_HasMVEInt, // MVE_VCMPu32 |
| 18245 | CEFBS_HasMVEInt, // MVE_VCMPu32r |
| 18246 | CEFBS_HasMVEInt, // MVE_VCMPu8 |
| 18247 | CEFBS_HasMVEInt, // MVE_VCMPu8r |
| 18248 | CEFBS_HasMVEFloat, // MVE_VCMULf16 |
| 18249 | CEFBS_HasMVEFloat, // MVE_VCMULf32 |
| 18250 | CEFBS_HasMVEInt, // MVE_VCTP16 |
| 18251 | CEFBS_HasMVEInt, // MVE_VCTP32 |
| 18252 | CEFBS_HasMVEInt, // MVE_VCTP64 |
| 18253 | CEFBS_HasMVEInt, // MVE_VCTP8 |
| 18254 | CEFBS_HasMVEFloat, // MVE_VCVTf16f32bh |
| 18255 | CEFBS_HasMVEFloat, // MVE_VCVTf16f32th |
| 18256 | CEFBS_HasMVEFloat, // MVE_VCVTf16s16_fix |
| 18257 | CEFBS_HasMVEFloat, // MVE_VCVTf16s16n |
| 18258 | CEFBS_HasMVEFloat, // MVE_VCVTf16u16_fix |
| 18259 | CEFBS_HasMVEFloat, // MVE_VCVTf16u16n |
| 18260 | CEFBS_HasMVEFloat, // MVE_VCVTf32f16bh |
| 18261 | CEFBS_HasMVEFloat, // MVE_VCVTf32f16th |
| 18262 | CEFBS_HasMVEFloat, // MVE_VCVTf32s32_fix |
| 18263 | CEFBS_HasMVEFloat, // MVE_VCVTf32s32n |
| 18264 | CEFBS_HasMVEFloat, // MVE_VCVTf32u32_fix |
| 18265 | CEFBS_HasMVEFloat, // MVE_VCVTf32u32n |
| 18266 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16_fix |
| 18267 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16a |
| 18268 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16m |
| 18269 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16n |
| 18270 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16p |
| 18271 | CEFBS_HasMVEFloat, // MVE_VCVTs16f16z |
| 18272 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32_fix |
| 18273 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32a |
| 18274 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32m |
| 18275 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32n |
| 18276 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32p |
| 18277 | CEFBS_HasMVEFloat, // MVE_VCVTs32f32z |
| 18278 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16_fix |
| 18279 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16a |
| 18280 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16m |
| 18281 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16n |
| 18282 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16p |
| 18283 | CEFBS_HasMVEFloat, // MVE_VCVTu16f16z |
| 18284 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32_fix |
| 18285 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32a |
| 18286 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32m |
| 18287 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32n |
| 18288 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32p |
| 18289 | CEFBS_HasMVEFloat, // MVE_VCVTu32f32z |
| 18290 | CEFBS_HasMVEInt, // MVE_VDDUPu16 |
| 18291 | CEFBS_HasMVEInt, // MVE_VDDUPu32 |
| 18292 | CEFBS_HasMVEInt, // MVE_VDDUPu8 |
| 18293 | CEFBS_HasMVEInt, // MVE_VDUP16 |
| 18294 | CEFBS_HasMVEInt, // MVE_VDUP32 |
| 18295 | CEFBS_HasMVEInt, // MVE_VDUP8 |
| 18296 | CEFBS_HasMVEInt, // MVE_VDWDUPu16 |
| 18297 | CEFBS_HasMVEInt, // MVE_VDWDUPu32 |
| 18298 | CEFBS_HasMVEInt, // MVE_VDWDUPu8 |
| 18299 | CEFBS_HasMVEInt, // MVE_VEOR |
| 18300 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf16 |
| 18301 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_Sf32 |
| 18302 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_f16 |
| 18303 | CEFBS_HasMVEFloat, // MVE_VFMA_qr_f32 |
| 18304 | CEFBS_HasMVEFloat, // MVE_VFMAf16 |
| 18305 | CEFBS_HasMVEFloat, // MVE_VFMAf32 |
| 18306 | CEFBS_HasMVEFloat, // MVE_VFMSf16 |
| 18307 | CEFBS_HasMVEFloat, // MVE_VFMSf32 |
| 18308 | CEFBS_HasMVEInt, // MVE_VHADD_qr_s16 |
| 18309 | CEFBS_HasMVEInt, // MVE_VHADD_qr_s32 |
| 18310 | CEFBS_HasMVEInt, // MVE_VHADD_qr_s8 |
| 18311 | CEFBS_HasMVEInt, // MVE_VHADD_qr_u16 |
| 18312 | CEFBS_HasMVEInt, // MVE_VHADD_qr_u32 |
| 18313 | CEFBS_HasMVEInt, // MVE_VHADD_qr_u8 |
| 18314 | CEFBS_HasMVEInt, // MVE_VHADDs16 |
| 18315 | CEFBS_HasMVEInt, // MVE_VHADDs32 |
| 18316 | CEFBS_HasMVEInt, // MVE_VHADDs8 |
| 18317 | CEFBS_HasMVEInt, // MVE_VHADDu16 |
| 18318 | CEFBS_HasMVEInt, // MVE_VHADDu32 |
| 18319 | CEFBS_HasMVEInt, // MVE_VHADDu8 |
| 18320 | CEFBS_HasMVEInt, // MVE_VHCADDs16 |
| 18321 | CEFBS_HasMVEInt, // MVE_VHCADDs32 |
| 18322 | CEFBS_HasMVEInt, // MVE_VHCADDs8 |
| 18323 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_s16 |
| 18324 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_s32 |
| 18325 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_s8 |
| 18326 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_u16 |
| 18327 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_u32 |
| 18328 | CEFBS_HasMVEInt, // MVE_VHSUB_qr_u8 |
| 18329 | CEFBS_HasMVEInt, // MVE_VHSUBs16 |
| 18330 | CEFBS_HasMVEInt, // MVE_VHSUBs32 |
| 18331 | CEFBS_HasMVEInt, // MVE_VHSUBs8 |
| 18332 | CEFBS_HasMVEInt, // MVE_VHSUBu16 |
| 18333 | CEFBS_HasMVEInt, // MVE_VHSUBu32 |
| 18334 | CEFBS_HasMVEInt, // MVE_VHSUBu8 |
| 18335 | CEFBS_HasMVEInt, // MVE_VIDUPu16 |
| 18336 | CEFBS_HasMVEInt, // MVE_VIDUPu32 |
| 18337 | CEFBS_HasMVEInt, // MVE_VIDUPu8 |
| 18338 | CEFBS_HasMVEInt, // MVE_VIWDUPu16 |
| 18339 | CEFBS_HasMVEInt, // MVE_VIWDUPu32 |
| 18340 | CEFBS_HasMVEInt, // MVE_VIWDUPu8 |
| 18341 | CEFBS_HasMVEInt, // MVE_VLD20_16 |
| 18342 | CEFBS_HasMVEInt, // MVE_VLD20_16_wb |
| 18343 | CEFBS_HasMVEInt, // MVE_VLD20_32 |
| 18344 | CEFBS_HasMVEInt, // MVE_VLD20_32_wb |
| 18345 | CEFBS_HasMVEInt, // MVE_VLD20_8 |
| 18346 | CEFBS_HasMVEInt, // MVE_VLD20_8_wb |
| 18347 | CEFBS_HasMVEInt, // MVE_VLD21_16 |
| 18348 | CEFBS_HasMVEInt, // MVE_VLD21_16_wb |
| 18349 | CEFBS_HasMVEInt, // MVE_VLD21_32 |
| 18350 | CEFBS_HasMVEInt, // MVE_VLD21_32_wb |
| 18351 | CEFBS_HasMVEInt, // MVE_VLD21_8 |
| 18352 | CEFBS_HasMVEInt, // MVE_VLD21_8_wb |
| 18353 | CEFBS_HasMVEInt, // MVE_VLD40_16 |
| 18354 | CEFBS_HasMVEInt, // MVE_VLD40_16_wb |
| 18355 | CEFBS_HasMVEInt, // MVE_VLD40_32 |
| 18356 | CEFBS_HasMVEInt, // MVE_VLD40_32_wb |
| 18357 | CEFBS_HasMVEInt, // MVE_VLD40_8 |
| 18358 | CEFBS_HasMVEInt, // MVE_VLD40_8_wb |
| 18359 | CEFBS_HasMVEInt, // MVE_VLD41_16 |
| 18360 | CEFBS_HasMVEInt, // MVE_VLD41_16_wb |
| 18361 | CEFBS_HasMVEInt, // MVE_VLD41_32 |
| 18362 | CEFBS_HasMVEInt, // MVE_VLD41_32_wb |
| 18363 | CEFBS_HasMVEInt, // MVE_VLD41_8 |
| 18364 | CEFBS_HasMVEInt, // MVE_VLD41_8_wb |
| 18365 | CEFBS_HasMVEInt, // MVE_VLD42_16 |
| 18366 | CEFBS_HasMVEInt, // MVE_VLD42_16_wb |
| 18367 | CEFBS_HasMVEInt, // MVE_VLD42_32 |
| 18368 | CEFBS_HasMVEInt, // MVE_VLD42_32_wb |
| 18369 | CEFBS_HasMVEInt, // MVE_VLD42_8 |
| 18370 | CEFBS_HasMVEInt, // MVE_VLD42_8_wb |
| 18371 | CEFBS_HasMVEInt, // MVE_VLD43_16 |
| 18372 | CEFBS_HasMVEInt, // MVE_VLD43_16_wb |
| 18373 | CEFBS_HasMVEInt, // MVE_VLD43_32 |
| 18374 | CEFBS_HasMVEInt, // MVE_VLD43_32_wb |
| 18375 | CEFBS_HasMVEInt, // MVE_VLD43_8 |
| 18376 | CEFBS_HasMVEInt, // MVE_VLD43_8_wb |
| 18377 | CEFBS_HasMVEInt, // MVE_VLDRBS16 |
| 18378 | CEFBS_HasMVEInt, // MVE_VLDRBS16_post |
| 18379 | CEFBS_HasMVEInt, // MVE_VLDRBS16_pre |
| 18380 | CEFBS_HasMVEInt, // MVE_VLDRBS16_rq |
| 18381 | CEFBS_HasMVEInt, // MVE_VLDRBS32 |
| 18382 | CEFBS_HasMVEInt, // MVE_VLDRBS32_post |
| 18383 | CEFBS_HasMVEInt, // MVE_VLDRBS32_pre |
| 18384 | CEFBS_HasMVEInt, // MVE_VLDRBS32_rq |
| 18385 | CEFBS_HasMVEInt, // MVE_VLDRBU16 |
| 18386 | CEFBS_HasMVEInt, // MVE_VLDRBU16_post |
| 18387 | CEFBS_HasMVEInt, // MVE_VLDRBU16_pre |
| 18388 | CEFBS_HasMVEInt, // MVE_VLDRBU16_rq |
| 18389 | CEFBS_HasMVEInt, // MVE_VLDRBU32 |
| 18390 | CEFBS_HasMVEInt, // MVE_VLDRBU32_post |
| 18391 | CEFBS_HasMVEInt, // MVE_VLDRBU32_pre |
| 18392 | CEFBS_HasMVEInt, // MVE_VLDRBU32_rq |
| 18393 | CEFBS_HasMVEInt, // MVE_VLDRBU8 |
| 18394 | CEFBS_HasMVEInt, // MVE_VLDRBU8_post |
| 18395 | CEFBS_HasMVEInt, // MVE_VLDRBU8_pre |
| 18396 | CEFBS_HasMVEInt, // MVE_VLDRBU8_rq |
| 18397 | CEFBS_HasMVEInt, // MVE_VLDRDU64_qi |
| 18398 | CEFBS_HasMVEInt, // MVE_VLDRDU64_qi_pre |
| 18399 | CEFBS_HasMVEInt, // MVE_VLDRDU64_rq |
| 18400 | CEFBS_HasMVEInt, // MVE_VLDRDU64_rq_u |
| 18401 | CEFBS_HasMVEInt, // MVE_VLDRHS32 |
| 18402 | CEFBS_HasMVEInt, // MVE_VLDRHS32_post |
| 18403 | CEFBS_HasMVEInt, // MVE_VLDRHS32_pre |
| 18404 | CEFBS_HasMVEInt, // MVE_VLDRHS32_rq |
| 18405 | CEFBS_HasMVEInt, // MVE_VLDRHS32_rq_u |
| 18406 | CEFBS_HasMVEInt, // MVE_VLDRHU16 |
| 18407 | CEFBS_HasMVEInt, // MVE_VLDRHU16_post |
| 18408 | CEFBS_HasMVEInt, // MVE_VLDRHU16_pre |
| 18409 | CEFBS_HasMVEInt, // MVE_VLDRHU16_rq |
| 18410 | CEFBS_HasMVEInt, // MVE_VLDRHU16_rq_u |
| 18411 | CEFBS_HasMVEInt, // MVE_VLDRHU32 |
| 18412 | CEFBS_HasMVEInt, // MVE_VLDRHU32_post |
| 18413 | CEFBS_HasMVEInt, // MVE_VLDRHU32_pre |
| 18414 | CEFBS_HasMVEInt, // MVE_VLDRHU32_rq |
| 18415 | CEFBS_HasMVEInt, // MVE_VLDRHU32_rq_u |
| 18416 | CEFBS_HasMVEInt, // MVE_VLDRWU32 |
| 18417 | CEFBS_HasMVEInt, // MVE_VLDRWU32_post |
| 18418 | CEFBS_HasMVEInt, // MVE_VLDRWU32_pre |
| 18419 | CEFBS_HasMVEInt, // MVE_VLDRWU32_qi |
| 18420 | CEFBS_HasMVEInt, // MVE_VLDRWU32_qi_pre |
| 18421 | CEFBS_HasMVEInt, // MVE_VLDRWU32_rq |
| 18422 | CEFBS_HasMVEInt, // MVE_VLDRWU32_rq_u |
| 18423 | CEFBS_HasMVEInt, // MVE_VMAXAVs16 |
| 18424 | CEFBS_HasMVEInt, // MVE_VMAXAVs32 |
| 18425 | CEFBS_HasMVEInt, // MVE_VMAXAVs8 |
| 18426 | CEFBS_HasMVEInt, // MVE_VMAXAs16 |
| 18427 | CEFBS_HasMVEInt, // MVE_VMAXAs32 |
| 18428 | CEFBS_HasMVEInt, // MVE_VMAXAs8 |
| 18429 | CEFBS_HasMVEFloat, // MVE_VMAXNMAVf16 |
| 18430 | CEFBS_HasMVEFloat, // MVE_VMAXNMAVf32 |
| 18431 | CEFBS_HasMVEFloat, // MVE_VMAXNMAf16 |
| 18432 | CEFBS_HasMVEFloat, // MVE_VMAXNMAf32 |
| 18433 | CEFBS_HasMVEFloat, // MVE_VMAXNMVf16 |
| 18434 | CEFBS_HasMVEFloat, // MVE_VMAXNMVf32 |
| 18435 | CEFBS_HasMVEFloat, // MVE_VMAXNMf16 |
| 18436 | CEFBS_HasMVEFloat, // MVE_VMAXNMf32 |
| 18437 | CEFBS_HasMVEInt, // MVE_VMAXVs16 |
| 18438 | CEFBS_HasMVEInt, // MVE_VMAXVs32 |
| 18439 | CEFBS_HasMVEInt, // MVE_VMAXVs8 |
| 18440 | CEFBS_HasMVEInt, // MVE_VMAXVu16 |
| 18441 | CEFBS_HasMVEInt, // MVE_VMAXVu32 |
| 18442 | CEFBS_HasMVEInt, // MVE_VMAXVu8 |
| 18443 | CEFBS_HasMVEInt, // MVE_VMAXs16 |
| 18444 | CEFBS_HasMVEInt, // MVE_VMAXs32 |
| 18445 | CEFBS_HasMVEInt, // MVE_VMAXs8 |
| 18446 | CEFBS_HasMVEInt, // MVE_VMAXu16 |
| 18447 | CEFBS_HasMVEInt, // MVE_VMAXu32 |
| 18448 | CEFBS_HasMVEInt, // MVE_VMAXu8 |
| 18449 | CEFBS_HasMVEInt, // MVE_VMINAVs16 |
| 18450 | CEFBS_HasMVEInt, // MVE_VMINAVs32 |
| 18451 | CEFBS_HasMVEInt, // MVE_VMINAVs8 |
| 18452 | CEFBS_HasMVEInt, // MVE_VMINAs16 |
| 18453 | CEFBS_HasMVEInt, // MVE_VMINAs32 |
| 18454 | CEFBS_HasMVEInt, // MVE_VMINAs8 |
| 18455 | CEFBS_HasMVEFloat, // MVE_VMINNMAVf16 |
| 18456 | CEFBS_HasMVEFloat, // MVE_VMINNMAVf32 |
| 18457 | CEFBS_HasMVEFloat, // MVE_VMINNMAf16 |
| 18458 | CEFBS_HasMVEFloat, // MVE_VMINNMAf32 |
| 18459 | CEFBS_HasMVEFloat, // MVE_VMINNMVf16 |
| 18460 | CEFBS_HasMVEFloat, // MVE_VMINNMVf32 |
| 18461 | CEFBS_HasMVEFloat, // MVE_VMINNMf16 |
| 18462 | CEFBS_HasMVEFloat, // MVE_VMINNMf32 |
| 18463 | CEFBS_HasMVEInt, // MVE_VMINVs16 |
| 18464 | CEFBS_HasMVEInt, // MVE_VMINVs32 |
| 18465 | CEFBS_HasMVEInt, // MVE_VMINVs8 |
| 18466 | CEFBS_HasMVEInt, // MVE_VMINVu16 |
| 18467 | CEFBS_HasMVEInt, // MVE_VMINVu32 |
| 18468 | CEFBS_HasMVEInt, // MVE_VMINVu8 |
| 18469 | CEFBS_HasMVEInt, // MVE_VMINs16 |
| 18470 | CEFBS_HasMVEInt, // MVE_VMINs32 |
| 18471 | CEFBS_HasMVEInt, // MVE_VMINs8 |
| 18472 | CEFBS_HasMVEInt, // MVE_VMINu16 |
| 18473 | CEFBS_HasMVEInt, // MVE_VMINu32 |
| 18474 | CEFBS_HasMVEInt, // MVE_VMINu8 |
| 18475 | CEFBS_HasMVEInt, // MVE_VMLADAVas16 |
| 18476 | CEFBS_HasMVEInt, // MVE_VMLADAVas32 |
| 18477 | CEFBS_HasMVEInt, // MVE_VMLADAVas8 |
| 18478 | CEFBS_HasMVEInt, // MVE_VMLADAVau16 |
| 18479 | CEFBS_HasMVEInt, // MVE_VMLADAVau32 |
| 18480 | CEFBS_HasMVEInt, // MVE_VMLADAVau8 |
| 18481 | CEFBS_HasMVEInt, // MVE_VMLADAVaxs16 |
| 18482 | CEFBS_HasMVEInt, // MVE_VMLADAVaxs32 |
| 18483 | CEFBS_HasMVEInt, // MVE_VMLADAVaxs8 |
| 18484 | CEFBS_HasMVEInt, // MVE_VMLADAVs16 |
| 18485 | CEFBS_HasMVEInt, // MVE_VMLADAVs32 |
| 18486 | CEFBS_HasMVEInt, // MVE_VMLADAVs8 |
| 18487 | CEFBS_HasMVEInt, // MVE_VMLADAVu16 |
| 18488 | CEFBS_HasMVEInt, // MVE_VMLADAVu32 |
| 18489 | CEFBS_HasMVEInt, // MVE_VMLADAVu8 |
| 18490 | CEFBS_HasMVEInt, // MVE_VMLADAVxs16 |
| 18491 | CEFBS_HasMVEInt, // MVE_VMLADAVxs32 |
| 18492 | CEFBS_HasMVEInt, // MVE_VMLADAVxs8 |
| 18493 | CEFBS_HasMVEInt, // MVE_VMLALDAVas16 |
| 18494 | CEFBS_HasMVEInt, // MVE_VMLALDAVas32 |
| 18495 | CEFBS_HasMVEInt, // MVE_VMLALDAVau16 |
| 18496 | CEFBS_HasMVEInt, // MVE_VMLALDAVau32 |
| 18497 | CEFBS_HasMVEInt, // MVE_VMLALDAVaxs16 |
| 18498 | CEFBS_HasMVEInt, // MVE_VMLALDAVaxs32 |
| 18499 | CEFBS_HasMVEInt, // MVE_VMLALDAVs16 |
| 18500 | CEFBS_HasMVEInt, // MVE_VMLALDAVs32 |
| 18501 | CEFBS_HasMVEInt, // MVE_VMLALDAVu16 |
| 18502 | CEFBS_HasMVEInt, // MVE_VMLALDAVu32 |
| 18503 | CEFBS_HasMVEInt, // MVE_VMLALDAVxs16 |
| 18504 | CEFBS_HasMVEInt, // MVE_VMLALDAVxs32 |
| 18505 | CEFBS_HasMVEInt, // MVE_VMLAS_qr_i16 |
| 18506 | CEFBS_HasMVEInt, // MVE_VMLAS_qr_i32 |
| 18507 | CEFBS_HasMVEInt, // MVE_VMLAS_qr_i8 |
| 18508 | CEFBS_HasMVEInt, // MVE_VMLA_qr_i16 |
| 18509 | CEFBS_HasMVEInt, // MVE_VMLA_qr_i32 |
| 18510 | CEFBS_HasMVEInt, // MVE_VMLA_qr_i8 |
| 18511 | CEFBS_HasMVEInt, // MVE_VMLSDAVas16 |
| 18512 | CEFBS_HasMVEInt, // MVE_VMLSDAVas32 |
| 18513 | CEFBS_HasMVEInt, // MVE_VMLSDAVas8 |
| 18514 | CEFBS_HasMVEInt, // MVE_VMLSDAVaxs16 |
| 18515 | CEFBS_HasMVEInt, // MVE_VMLSDAVaxs32 |
| 18516 | CEFBS_HasMVEInt, // MVE_VMLSDAVaxs8 |
| 18517 | CEFBS_HasMVEInt, // MVE_VMLSDAVs16 |
| 18518 | CEFBS_HasMVEInt, // MVE_VMLSDAVs32 |
| 18519 | CEFBS_HasMVEInt, // MVE_VMLSDAVs8 |
| 18520 | CEFBS_HasMVEInt, // MVE_VMLSDAVxs16 |
| 18521 | CEFBS_HasMVEInt, // MVE_VMLSDAVxs32 |
| 18522 | CEFBS_HasMVEInt, // MVE_VMLSDAVxs8 |
| 18523 | CEFBS_HasMVEInt, // MVE_VMLSLDAVas16 |
| 18524 | CEFBS_HasMVEInt, // MVE_VMLSLDAVas32 |
| 18525 | CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs16 |
| 18526 | CEFBS_HasMVEInt, // MVE_VMLSLDAVaxs32 |
| 18527 | CEFBS_HasMVEInt, // MVE_VMLSLDAVs16 |
| 18528 | CEFBS_HasMVEInt, // MVE_VMLSLDAVs32 |
| 18529 | CEFBS_HasMVEInt, // MVE_VMLSLDAVxs16 |
| 18530 | CEFBS_HasMVEInt, // MVE_VMLSLDAVxs32 |
| 18531 | CEFBS_HasMVEInt, // MVE_VMOVLs16bh |
| 18532 | CEFBS_HasMVEInt, // MVE_VMOVLs16th |
| 18533 | CEFBS_HasMVEInt, // MVE_VMOVLs8bh |
| 18534 | CEFBS_HasMVEInt, // MVE_VMOVLs8th |
| 18535 | CEFBS_HasMVEInt, // MVE_VMOVLu16bh |
| 18536 | CEFBS_HasMVEInt, // MVE_VMOVLu16th |
| 18537 | CEFBS_HasMVEInt, // MVE_VMOVLu8bh |
| 18538 | CEFBS_HasMVEInt, // MVE_VMOVLu8th |
| 18539 | CEFBS_HasMVEInt, // MVE_VMOVNi16bh |
| 18540 | CEFBS_HasMVEInt, // MVE_VMOVNi16th |
| 18541 | CEFBS_HasMVEInt, // MVE_VMOVNi32bh |
| 18542 | CEFBS_HasMVEInt, // MVE_VMOVNi32th |
| 18543 | CEFBS_HasFPRegsV8_1M, // MVE_VMOV_from_lane_32 |
| 18544 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s16 |
| 18545 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_s8 |
| 18546 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u16 |
| 18547 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_from_lane_u8 |
| 18548 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_q_rr |
| 18549 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_rr_q |
| 18550 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_16 |
| 18551 | CEFBS_HasFPRegsV8_1M, // MVE_VMOV_to_lane_32 |
| 18552 | CEFBS_HasV8_1MMainline_HasMVEInt, // MVE_VMOV_to_lane_8 |
| 18553 | CEFBS_HasMVEInt, // MVE_VMOVimmf32 |
| 18554 | CEFBS_HasMVEInt, // MVE_VMOVimmi16 |
| 18555 | CEFBS_HasMVEInt, // MVE_VMOVimmi32 |
| 18556 | CEFBS_HasMVEInt, // MVE_VMOVimmi64 |
| 18557 | CEFBS_HasMVEInt, // MVE_VMOVimmi8 |
| 18558 | CEFBS_HasMVEInt, // MVE_VMULHs16 |
| 18559 | CEFBS_HasMVEInt, // MVE_VMULHs32 |
| 18560 | CEFBS_HasMVEInt, // MVE_VMULHs8 |
| 18561 | CEFBS_HasMVEInt, // MVE_VMULHu16 |
| 18562 | CEFBS_HasMVEInt, // MVE_VMULHu32 |
| 18563 | CEFBS_HasMVEInt, // MVE_VMULHu8 |
| 18564 | CEFBS_HasMVEInt, // MVE_VMULLBp16 |
| 18565 | CEFBS_HasMVEInt, // MVE_VMULLBp8 |
| 18566 | CEFBS_HasMVEInt, // MVE_VMULLBs16 |
| 18567 | CEFBS_HasMVEInt, // MVE_VMULLBs32 |
| 18568 | CEFBS_HasMVEInt, // MVE_VMULLBs8 |
| 18569 | CEFBS_HasMVEInt, // MVE_VMULLBu16 |
| 18570 | CEFBS_HasMVEInt, // MVE_VMULLBu32 |
| 18571 | CEFBS_HasMVEInt, // MVE_VMULLBu8 |
| 18572 | CEFBS_HasMVEInt, // MVE_VMULLTp16 |
| 18573 | CEFBS_HasMVEInt, // MVE_VMULLTp8 |
| 18574 | CEFBS_HasMVEInt, // MVE_VMULLTs16 |
| 18575 | CEFBS_HasMVEInt, // MVE_VMULLTs32 |
| 18576 | CEFBS_HasMVEInt, // MVE_VMULLTs8 |
| 18577 | CEFBS_HasMVEInt, // MVE_VMULLTu16 |
| 18578 | CEFBS_HasMVEInt, // MVE_VMULLTu32 |
| 18579 | CEFBS_HasMVEInt, // MVE_VMULLTu8 |
| 18580 | CEFBS_HasMVEFloat, // MVE_VMUL_qr_f16 |
| 18581 | CEFBS_HasMVEFloat, // MVE_VMUL_qr_f32 |
| 18582 | CEFBS_HasMVEInt, // MVE_VMUL_qr_i16 |
| 18583 | CEFBS_HasMVEInt, // MVE_VMUL_qr_i32 |
| 18584 | CEFBS_HasMVEInt, // MVE_VMUL_qr_i8 |
| 18585 | CEFBS_HasMVEFloat, // MVE_VMULf16 |
| 18586 | CEFBS_HasMVEFloat, // MVE_VMULf32 |
| 18587 | CEFBS_HasMVEInt, // MVE_VMULi16 |
| 18588 | CEFBS_HasMVEInt, // MVE_VMULi32 |
| 18589 | CEFBS_HasMVEInt, // MVE_VMULi8 |
| 18590 | CEFBS_HasMVEInt, // MVE_VMVN |
| 18591 | CEFBS_HasMVEInt, // MVE_VMVNimmi16 |
| 18592 | CEFBS_HasMVEInt, // MVE_VMVNimmi32 |
| 18593 | CEFBS_HasMVEFloat, // MVE_VNEGf16 |
| 18594 | CEFBS_HasMVEFloat, // MVE_VNEGf32 |
| 18595 | CEFBS_HasMVEInt, // MVE_VNEGs16 |
| 18596 | CEFBS_HasMVEInt, // MVE_VNEGs32 |
| 18597 | CEFBS_HasMVEInt, // MVE_VNEGs8 |
| 18598 | CEFBS_HasMVEInt, // MVE_VORN |
| 18599 | CEFBS_HasMVEInt, // MVE_VORR |
| 18600 | CEFBS_HasMVEInt, // MVE_VORRimmi16 |
| 18601 | CEFBS_HasMVEInt, // MVE_VORRimmi32 |
| 18602 | CEFBS_HasMVEInt, // MVE_VPNOT |
| 18603 | CEFBS_HasMVEInt, // MVE_VPSEL |
| 18604 | CEFBS_HasMVEInt, // MVE_VPST |
| 18605 | CEFBS_HasMVEInt, // MVE_VPTv16i8 |
| 18606 | CEFBS_HasMVEInt, // MVE_VPTv16i8r |
| 18607 | CEFBS_HasMVEInt, // MVE_VPTv16s8 |
| 18608 | CEFBS_HasMVEInt, // MVE_VPTv16s8r |
| 18609 | CEFBS_HasMVEInt, // MVE_VPTv16u8 |
| 18610 | CEFBS_HasMVEInt, // MVE_VPTv16u8r |
| 18611 | CEFBS_HasMVEFloat, // MVE_VPTv4f32 |
| 18612 | CEFBS_HasMVEFloat, // MVE_VPTv4f32r |
| 18613 | CEFBS_HasMVEInt, // MVE_VPTv4i32 |
| 18614 | CEFBS_HasMVEInt, // MVE_VPTv4i32r |
| 18615 | CEFBS_HasMVEInt, // MVE_VPTv4s32 |
| 18616 | CEFBS_HasMVEInt, // MVE_VPTv4s32r |
| 18617 | CEFBS_HasMVEInt, // MVE_VPTv4u32 |
| 18618 | CEFBS_HasMVEInt, // MVE_VPTv4u32r |
| 18619 | CEFBS_HasMVEFloat, // MVE_VPTv8f16 |
| 18620 | CEFBS_HasMVEFloat, // MVE_VPTv8f16r |
| 18621 | CEFBS_HasMVEInt, // MVE_VPTv8i16 |
| 18622 | CEFBS_HasMVEInt, // MVE_VPTv8i16r |
| 18623 | CEFBS_HasMVEInt, // MVE_VPTv8s16 |
| 18624 | CEFBS_HasMVEInt, // MVE_VPTv8s16r |
| 18625 | CEFBS_HasMVEInt, // MVE_VPTv8u16 |
| 18626 | CEFBS_HasMVEInt, // MVE_VPTv8u16r |
| 18627 | CEFBS_HasMVEInt, // MVE_VQABSs16 |
| 18628 | CEFBS_HasMVEInt, // MVE_VQABSs32 |
| 18629 | CEFBS_HasMVEInt, // MVE_VQABSs8 |
| 18630 | CEFBS_HasMVEInt, // MVE_VQADD_qr_s16 |
| 18631 | CEFBS_HasMVEInt, // MVE_VQADD_qr_s32 |
| 18632 | CEFBS_HasMVEInt, // MVE_VQADD_qr_s8 |
| 18633 | CEFBS_HasMVEInt, // MVE_VQADD_qr_u16 |
| 18634 | CEFBS_HasMVEInt, // MVE_VQADD_qr_u32 |
| 18635 | CEFBS_HasMVEInt, // MVE_VQADD_qr_u8 |
| 18636 | CEFBS_HasMVEInt, // MVE_VQADDs16 |
| 18637 | CEFBS_HasMVEInt, // MVE_VQADDs32 |
| 18638 | CEFBS_HasMVEInt, // MVE_VQADDs8 |
| 18639 | CEFBS_HasMVEInt, // MVE_VQADDu16 |
| 18640 | CEFBS_HasMVEInt, // MVE_VQADDu32 |
| 18641 | CEFBS_HasMVEInt, // MVE_VQADDu8 |
| 18642 | CEFBS_HasMVEInt, // MVE_VQDMLADHXs16 |
| 18643 | CEFBS_HasMVEInt, // MVE_VQDMLADHXs32 |
| 18644 | CEFBS_HasMVEInt, // MVE_VQDMLADHXs8 |
| 18645 | CEFBS_HasMVEInt, // MVE_VQDMLADHs16 |
| 18646 | CEFBS_HasMVEInt, // MVE_VQDMLADHs32 |
| 18647 | CEFBS_HasMVEInt, // MVE_VQDMLADHs8 |
| 18648 | CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs16 |
| 18649 | CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs32 |
| 18650 | CEFBS_HasMVEInt, // MVE_VQDMLAH_qrs8 |
| 18651 | CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs16 |
| 18652 | CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs32 |
| 18653 | CEFBS_HasMVEInt, // MVE_VQDMLASH_qrs8 |
| 18654 | CEFBS_HasMVEInt, // MVE_VQDMLSDHXs16 |
| 18655 | CEFBS_HasMVEInt, // MVE_VQDMLSDHXs32 |
| 18656 | CEFBS_HasMVEInt, // MVE_VQDMLSDHXs8 |
| 18657 | CEFBS_HasMVEInt, // MVE_VQDMLSDHs16 |
| 18658 | CEFBS_HasMVEInt, // MVE_VQDMLSDHs32 |
| 18659 | CEFBS_HasMVEInt, // MVE_VQDMLSDHs8 |
| 18660 | CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s16 |
| 18661 | CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s32 |
| 18662 | CEFBS_HasMVEInt, // MVE_VQDMULH_qr_s8 |
| 18663 | CEFBS_HasMVEInt, // MVE_VQDMULHi16 |
| 18664 | CEFBS_HasMVEInt, // MVE_VQDMULHi32 |
| 18665 | CEFBS_HasMVEInt, // MVE_VQDMULHi8 |
| 18666 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16bh |
| 18667 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s16th |
| 18668 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32bh |
| 18669 | CEFBS_HasMVEInt, // MVE_VQDMULL_qr_s32th |
| 18670 | CEFBS_HasMVEInt, // MVE_VQDMULLs16bh |
| 18671 | CEFBS_HasMVEInt, // MVE_VQDMULLs16th |
| 18672 | CEFBS_HasMVEInt, // MVE_VQDMULLs32bh |
| 18673 | CEFBS_HasMVEInt, // MVE_VQDMULLs32th |
| 18674 | CEFBS_HasMVEInt, // MVE_VQMOVNs16bh |
| 18675 | CEFBS_HasMVEInt, // MVE_VQMOVNs16th |
| 18676 | CEFBS_HasMVEInt, // MVE_VQMOVNs32bh |
| 18677 | CEFBS_HasMVEInt, // MVE_VQMOVNs32th |
| 18678 | CEFBS_HasMVEInt, // MVE_VQMOVNu16bh |
| 18679 | CEFBS_HasMVEInt, // MVE_VQMOVNu16th |
| 18680 | CEFBS_HasMVEInt, // MVE_VQMOVNu32bh |
| 18681 | CEFBS_HasMVEInt, // MVE_VQMOVNu32th |
| 18682 | CEFBS_HasMVEInt, // MVE_VQMOVUNs16bh |
| 18683 | CEFBS_HasMVEInt, // MVE_VQMOVUNs16th |
| 18684 | CEFBS_HasMVEInt, // MVE_VQMOVUNs32bh |
| 18685 | CEFBS_HasMVEInt, // MVE_VQMOVUNs32th |
| 18686 | CEFBS_HasMVEInt, // MVE_VQNEGs16 |
| 18687 | CEFBS_HasMVEInt, // MVE_VQNEGs32 |
| 18688 | CEFBS_HasMVEInt, // MVE_VQNEGs8 |
| 18689 | CEFBS_HasMVEInt, // MVE_VQRDMLADHXs16 |
| 18690 | CEFBS_HasMVEInt, // MVE_VQRDMLADHXs32 |
| 18691 | CEFBS_HasMVEInt, // MVE_VQRDMLADHXs8 |
| 18692 | CEFBS_HasMVEInt, // MVE_VQRDMLADHs16 |
| 18693 | CEFBS_HasMVEInt, // MVE_VQRDMLADHs32 |
| 18694 | CEFBS_HasMVEInt, // MVE_VQRDMLADHs8 |
| 18695 | CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs16 |
| 18696 | CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs32 |
| 18697 | CEFBS_HasMVEInt, // MVE_VQRDMLAH_qrs8 |
| 18698 | CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs16 |
| 18699 | CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs32 |
| 18700 | CEFBS_HasMVEInt, // MVE_VQRDMLASH_qrs8 |
| 18701 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs16 |
| 18702 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs32 |
| 18703 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHXs8 |
| 18704 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHs16 |
| 18705 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHs32 |
| 18706 | CEFBS_HasMVEInt, // MVE_VQRDMLSDHs8 |
| 18707 | CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s16 |
| 18708 | CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s32 |
| 18709 | CEFBS_HasMVEInt, // MVE_VQRDMULH_qr_s8 |
| 18710 | CEFBS_HasMVEInt, // MVE_VQRDMULHi16 |
| 18711 | CEFBS_HasMVEInt, // MVE_VQRDMULHi32 |
| 18712 | CEFBS_HasMVEInt, // MVE_VQRDMULHi8 |
| 18713 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs16 |
| 18714 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs32 |
| 18715 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecs8 |
| 18716 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu16 |
| 18717 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu32 |
| 18718 | CEFBS_HasMVEInt, // MVE_VQRSHL_by_vecu8 |
| 18719 | CEFBS_HasMVEInt, // MVE_VQRSHL_qrs16 |
| 18720 | CEFBS_HasMVEInt, // MVE_VQRSHL_qrs32 |
| 18721 | CEFBS_HasMVEInt, // MVE_VQRSHL_qrs8 |
| 18722 | CEFBS_HasMVEInt, // MVE_VQRSHL_qru16 |
| 18723 | CEFBS_HasMVEInt, // MVE_VQRSHL_qru32 |
| 18724 | CEFBS_HasMVEInt, // MVE_VQRSHL_qru8 |
| 18725 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhs16 |
| 18726 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhs32 |
| 18727 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhu16 |
| 18728 | CEFBS_HasMVEInt, // MVE_VQRSHRNbhu32 |
| 18729 | CEFBS_HasMVEInt, // MVE_VQRSHRNths16 |
| 18730 | CEFBS_HasMVEInt, // MVE_VQRSHRNths32 |
| 18731 | CEFBS_HasMVEInt, // MVE_VQRSHRNthu16 |
| 18732 | CEFBS_HasMVEInt, // MVE_VQRSHRNthu32 |
| 18733 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs16bh |
| 18734 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs16th |
| 18735 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs32bh |
| 18736 | CEFBS_HasMVEInt, // MVE_VQRSHRUNs32th |
| 18737 | CEFBS_HasMVEInt, // MVE_VQSHLU_imms16 |
| 18738 | CEFBS_HasMVEInt, // MVE_VQSHLU_imms32 |
| 18739 | CEFBS_HasMVEInt, // MVE_VQSHLU_imms8 |
| 18740 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs16 |
| 18741 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs32 |
| 18742 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecs8 |
| 18743 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu16 |
| 18744 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu32 |
| 18745 | CEFBS_HasMVEInt, // MVE_VQSHL_by_vecu8 |
| 18746 | CEFBS_HasMVEInt, // MVE_VQSHL_qrs16 |
| 18747 | CEFBS_HasMVEInt, // MVE_VQSHL_qrs32 |
| 18748 | CEFBS_HasMVEInt, // MVE_VQSHL_qrs8 |
| 18749 | CEFBS_HasMVEInt, // MVE_VQSHL_qru16 |
| 18750 | CEFBS_HasMVEInt, // MVE_VQSHL_qru32 |
| 18751 | CEFBS_HasMVEInt, // MVE_VQSHL_qru8 |
| 18752 | CEFBS_HasMVEInt, // MVE_VQSHLimms16 |
| 18753 | CEFBS_HasMVEInt, // MVE_VQSHLimms32 |
| 18754 | CEFBS_HasMVEInt, // MVE_VQSHLimms8 |
| 18755 | CEFBS_HasMVEInt, // MVE_VQSHLimmu16 |
| 18756 | CEFBS_HasMVEInt, // MVE_VQSHLimmu32 |
| 18757 | CEFBS_HasMVEInt, // MVE_VQSHLimmu8 |
| 18758 | CEFBS_HasMVEInt, // MVE_VQSHRNbhs16 |
| 18759 | CEFBS_HasMVEInt, // MVE_VQSHRNbhs32 |
| 18760 | CEFBS_HasMVEInt, // MVE_VQSHRNbhu16 |
| 18761 | CEFBS_HasMVEInt, // MVE_VQSHRNbhu32 |
| 18762 | CEFBS_HasMVEInt, // MVE_VQSHRNths16 |
| 18763 | CEFBS_HasMVEInt, // MVE_VQSHRNths32 |
| 18764 | CEFBS_HasMVEInt, // MVE_VQSHRNthu16 |
| 18765 | CEFBS_HasMVEInt, // MVE_VQSHRNthu32 |
| 18766 | CEFBS_HasMVEInt, // MVE_VQSHRUNs16bh |
| 18767 | CEFBS_HasMVEInt, // MVE_VQSHRUNs16th |
| 18768 | CEFBS_HasMVEInt, // MVE_VQSHRUNs32bh |
| 18769 | CEFBS_HasMVEInt, // MVE_VQSHRUNs32th |
| 18770 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_s16 |
| 18771 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_s32 |
| 18772 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_s8 |
| 18773 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_u16 |
| 18774 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_u32 |
| 18775 | CEFBS_HasMVEInt, // MVE_VQSUB_qr_u8 |
| 18776 | CEFBS_HasMVEInt, // MVE_VQSUBs16 |
| 18777 | CEFBS_HasMVEInt, // MVE_VQSUBs32 |
| 18778 | CEFBS_HasMVEInt, // MVE_VQSUBs8 |
| 18779 | CEFBS_HasMVEInt, // MVE_VQSUBu16 |
| 18780 | CEFBS_HasMVEInt, // MVE_VQSUBu32 |
| 18781 | CEFBS_HasMVEInt, // MVE_VQSUBu8 |
| 18782 | CEFBS_HasMVEInt, // MVE_VREV16_8 |
| 18783 | CEFBS_HasMVEInt, // MVE_VREV32_16 |
| 18784 | CEFBS_HasMVEInt, // MVE_VREV32_8 |
| 18785 | CEFBS_HasMVEInt, // MVE_VREV64_16 |
| 18786 | CEFBS_HasMVEInt, // MVE_VREV64_32 |
| 18787 | CEFBS_HasMVEInt, // MVE_VREV64_8 |
| 18788 | CEFBS_HasMVEInt, // MVE_VRHADDs16 |
| 18789 | CEFBS_HasMVEInt, // MVE_VRHADDs32 |
| 18790 | CEFBS_HasMVEInt, // MVE_VRHADDs8 |
| 18791 | CEFBS_HasMVEInt, // MVE_VRHADDu16 |
| 18792 | CEFBS_HasMVEInt, // MVE_VRHADDu32 |
| 18793 | CEFBS_HasMVEInt, // MVE_VRHADDu8 |
| 18794 | CEFBS_HasMVEFloat, // MVE_VRINTf16A |
| 18795 | CEFBS_HasMVEFloat, // MVE_VRINTf16M |
| 18796 | CEFBS_HasMVEFloat, // MVE_VRINTf16N |
| 18797 | CEFBS_HasMVEFloat, // MVE_VRINTf16P |
| 18798 | CEFBS_HasMVEFloat, // MVE_VRINTf16X |
| 18799 | CEFBS_HasMVEFloat, // MVE_VRINTf16Z |
| 18800 | CEFBS_HasMVEFloat, // MVE_VRINTf32A |
| 18801 | CEFBS_HasMVEFloat, // MVE_VRINTf32M |
| 18802 | CEFBS_HasMVEFloat, // MVE_VRINTf32N |
| 18803 | CEFBS_HasMVEFloat, // MVE_VRINTf32P |
| 18804 | CEFBS_HasMVEFloat, // MVE_VRINTf32X |
| 18805 | CEFBS_HasMVEFloat, // MVE_VRINTf32Z |
| 18806 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHas32 |
| 18807 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHau32 |
| 18808 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHaxs32 |
| 18809 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHs32 |
| 18810 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHu32 |
| 18811 | CEFBS_HasMVEInt, // MVE_VRMLALDAVHxs32 |
| 18812 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHas32 |
| 18813 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHaxs32 |
| 18814 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHs32 |
| 18815 | CEFBS_HasMVEInt, // MVE_VRMLSLDAVHxs32 |
| 18816 | CEFBS_HasMVEInt, // MVE_VRMULHs16 |
| 18817 | CEFBS_HasMVEInt, // MVE_VRMULHs32 |
| 18818 | CEFBS_HasMVEInt, // MVE_VRMULHs8 |
| 18819 | CEFBS_HasMVEInt, // MVE_VRMULHu16 |
| 18820 | CEFBS_HasMVEInt, // MVE_VRMULHu32 |
| 18821 | CEFBS_HasMVEInt, // MVE_VRMULHu8 |
| 18822 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs16 |
| 18823 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs32 |
| 18824 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecs8 |
| 18825 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu16 |
| 18826 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu32 |
| 18827 | CEFBS_HasMVEInt, // MVE_VRSHL_by_vecu8 |
| 18828 | CEFBS_HasMVEInt, // MVE_VRSHL_qrs16 |
| 18829 | CEFBS_HasMVEInt, // MVE_VRSHL_qrs32 |
| 18830 | CEFBS_HasMVEInt, // MVE_VRSHL_qrs8 |
| 18831 | CEFBS_HasMVEInt, // MVE_VRSHL_qru16 |
| 18832 | CEFBS_HasMVEInt, // MVE_VRSHL_qru32 |
| 18833 | CEFBS_HasMVEInt, // MVE_VRSHL_qru8 |
| 18834 | CEFBS_HasMVEInt, // MVE_VRSHRNi16bh |
| 18835 | CEFBS_HasMVEInt, // MVE_VRSHRNi16th |
| 18836 | CEFBS_HasMVEInt, // MVE_VRSHRNi32bh |
| 18837 | CEFBS_HasMVEInt, // MVE_VRSHRNi32th |
| 18838 | CEFBS_HasMVEInt, // MVE_VRSHR_imms16 |
| 18839 | CEFBS_HasMVEInt, // MVE_VRSHR_imms32 |
| 18840 | CEFBS_HasMVEInt, // MVE_VRSHR_imms8 |
| 18841 | CEFBS_HasMVEInt, // MVE_VRSHR_immu16 |
| 18842 | CEFBS_HasMVEInt, // MVE_VRSHR_immu32 |
| 18843 | CEFBS_HasMVEInt, // MVE_VRSHR_immu8 |
| 18844 | CEFBS_HasMVEInt, // MVE_VSBC |
| 18845 | CEFBS_HasMVEInt, // MVE_VSBCI |
| 18846 | CEFBS_HasMVEInt, // MVE_VSHLC |
| 18847 | CEFBS_HasMVEInt, // MVE_VSHLL_imms16bh |
| 18848 | CEFBS_HasMVEInt, // MVE_VSHLL_imms16th |
| 18849 | CEFBS_HasMVEInt, // MVE_VSHLL_imms8bh |
| 18850 | CEFBS_HasMVEInt, // MVE_VSHLL_imms8th |
| 18851 | CEFBS_HasMVEInt, // MVE_VSHLL_immu16bh |
| 18852 | CEFBS_HasMVEInt, // MVE_VSHLL_immu16th |
| 18853 | CEFBS_HasMVEInt, // MVE_VSHLL_immu8bh |
| 18854 | CEFBS_HasMVEInt, // MVE_VSHLL_immu8th |
| 18855 | CEFBS_HasMVEInt, // MVE_VSHLL_lws16bh |
| 18856 | CEFBS_HasMVEInt, // MVE_VSHLL_lws16th |
| 18857 | CEFBS_HasMVEInt, // MVE_VSHLL_lws8bh |
| 18858 | CEFBS_HasMVEInt, // MVE_VSHLL_lws8th |
| 18859 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu16bh |
| 18860 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu16th |
| 18861 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu8bh |
| 18862 | CEFBS_HasMVEInt, // MVE_VSHLL_lwu8th |
| 18863 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecs16 |
| 18864 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecs32 |
| 18865 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecs8 |
| 18866 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecu16 |
| 18867 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecu32 |
| 18868 | CEFBS_HasMVEInt, // MVE_VSHL_by_vecu8 |
| 18869 | CEFBS_HasMVEInt, // MVE_VSHL_immi16 |
| 18870 | CEFBS_HasMVEInt, // MVE_VSHL_immi32 |
| 18871 | CEFBS_HasMVEInt, // MVE_VSHL_immi8 |
| 18872 | CEFBS_HasMVEInt, // MVE_VSHL_qrs16 |
| 18873 | CEFBS_HasMVEInt, // MVE_VSHL_qrs32 |
| 18874 | CEFBS_HasMVEInt, // MVE_VSHL_qrs8 |
| 18875 | CEFBS_HasMVEInt, // MVE_VSHL_qru16 |
| 18876 | CEFBS_HasMVEInt, // MVE_VSHL_qru32 |
| 18877 | CEFBS_HasMVEInt, // MVE_VSHL_qru8 |
| 18878 | CEFBS_HasMVEInt, // MVE_VSHRNi16bh |
| 18879 | CEFBS_HasMVEInt, // MVE_VSHRNi16th |
| 18880 | CEFBS_HasMVEInt, // MVE_VSHRNi32bh |
| 18881 | CEFBS_HasMVEInt, // MVE_VSHRNi32th |
| 18882 | CEFBS_HasMVEInt, // MVE_VSHR_imms16 |
| 18883 | CEFBS_HasMVEInt, // MVE_VSHR_imms32 |
| 18884 | CEFBS_HasMVEInt, // MVE_VSHR_imms8 |
| 18885 | CEFBS_HasMVEInt, // MVE_VSHR_immu16 |
| 18886 | CEFBS_HasMVEInt, // MVE_VSHR_immu32 |
| 18887 | CEFBS_HasMVEInt, // MVE_VSHR_immu8 |
| 18888 | CEFBS_HasMVEInt, // MVE_VSLIimm16 |
| 18889 | CEFBS_HasMVEInt, // MVE_VSLIimm32 |
| 18890 | CEFBS_HasMVEInt, // MVE_VSLIimm8 |
| 18891 | CEFBS_HasMVEInt, // MVE_VSRIimm16 |
| 18892 | CEFBS_HasMVEInt, // MVE_VSRIimm32 |
| 18893 | CEFBS_HasMVEInt, // MVE_VSRIimm8 |
| 18894 | CEFBS_HasMVEInt, // MVE_VST20_16 |
| 18895 | CEFBS_HasMVEInt, // MVE_VST20_16_wb |
| 18896 | CEFBS_HasMVEInt, // MVE_VST20_32 |
| 18897 | CEFBS_HasMVEInt, // MVE_VST20_32_wb |
| 18898 | CEFBS_HasMVEInt, // MVE_VST20_8 |
| 18899 | CEFBS_HasMVEInt, // MVE_VST20_8_wb |
| 18900 | CEFBS_HasMVEInt, // MVE_VST21_16 |
| 18901 | CEFBS_HasMVEInt, // MVE_VST21_16_wb |
| 18902 | CEFBS_HasMVEInt, // MVE_VST21_32 |
| 18903 | CEFBS_HasMVEInt, // MVE_VST21_32_wb |
| 18904 | CEFBS_HasMVEInt, // MVE_VST21_8 |
| 18905 | CEFBS_HasMVEInt, // MVE_VST21_8_wb |
| 18906 | CEFBS_HasMVEInt, // MVE_VST40_16 |
| 18907 | CEFBS_HasMVEInt, // MVE_VST40_16_wb |
| 18908 | CEFBS_HasMVEInt, // MVE_VST40_32 |
| 18909 | CEFBS_HasMVEInt, // MVE_VST40_32_wb |
| 18910 | CEFBS_HasMVEInt, // MVE_VST40_8 |
| 18911 | CEFBS_HasMVEInt, // MVE_VST40_8_wb |
| 18912 | CEFBS_HasMVEInt, // MVE_VST41_16 |
| 18913 | CEFBS_HasMVEInt, // MVE_VST41_16_wb |
| 18914 | CEFBS_HasMVEInt, // MVE_VST41_32 |
| 18915 | CEFBS_HasMVEInt, // MVE_VST41_32_wb |
| 18916 | CEFBS_HasMVEInt, // MVE_VST41_8 |
| 18917 | CEFBS_HasMVEInt, // MVE_VST41_8_wb |
| 18918 | CEFBS_HasMVEInt, // MVE_VST42_16 |
| 18919 | CEFBS_HasMVEInt, // MVE_VST42_16_wb |
| 18920 | CEFBS_HasMVEInt, // MVE_VST42_32 |
| 18921 | CEFBS_HasMVEInt, // MVE_VST42_32_wb |
| 18922 | CEFBS_HasMVEInt, // MVE_VST42_8 |
| 18923 | CEFBS_HasMVEInt, // MVE_VST42_8_wb |
| 18924 | CEFBS_HasMVEInt, // MVE_VST43_16 |
| 18925 | CEFBS_HasMVEInt, // MVE_VST43_16_wb |
| 18926 | CEFBS_HasMVEInt, // MVE_VST43_32 |
| 18927 | CEFBS_HasMVEInt, // MVE_VST43_32_wb |
| 18928 | CEFBS_HasMVEInt, // MVE_VST43_8 |
| 18929 | CEFBS_HasMVEInt, // MVE_VST43_8_wb |
| 18930 | CEFBS_HasMVEInt, // MVE_VSTRB16 |
| 18931 | CEFBS_HasMVEInt, // MVE_VSTRB16_post |
| 18932 | CEFBS_HasMVEInt, // MVE_VSTRB16_pre |
| 18933 | CEFBS_HasMVEInt, // MVE_VSTRB16_rq |
| 18934 | CEFBS_HasMVEInt, // MVE_VSTRB32 |
| 18935 | CEFBS_HasMVEInt, // MVE_VSTRB32_post |
| 18936 | CEFBS_HasMVEInt, // MVE_VSTRB32_pre |
| 18937 | CEFBS_HasMVEInt, // MVE_VSTRB32_rq |
| 18938 | CEFBS_HasMVEInt, // MVE_VSTRB8_rq |
| 18939 | CEFBS_HasMVEInt, // MVE_VSTRBU8 |
| 18940 | CEFBS_HasMVEInt, // MVE_VSTRBU8_post |
| 18941 | CEFBS_HasMVEInt, // MVE_VSTRBU8_pre |
| 18942 | CEFBS_HasMVEInt, // MVE_VSTRD64_qi |
| 18943 | CEFBS_HasMVEInt, // MVE_VSTRD64_qi_pre |
| 18944 | CEFBS_HasMVEInt, // MVE_VSTRD64_rq |
| 18945 | CEFBS_HasMVEInt, // MVE_VSTRD64_rq_u |
| 18946 | CEFBS_HasMVEInt, // MVE_VSTRH16_rq |
| 18947 | CEFBS_HasMVEInt, // MVE_VSTRH16_rq_u |
| 18948 | CEFBS_HasMVEInt, // MVE_VSTRH32 |
| 18949 | CEFBS_HasMVEInt, // MVE_VSTRH32_post |
| 18950 | CEFBS_HasMVEInt, // MVE_VSTRH32_pre |
| 18951 | CEFBS_HasMVEInt, // MVE_VSTRH32_rq |
| 18952 | CEFBS_HasMVEInt, // MVE_VSTRH32_rq_u |
| 18953 | CEFBS_HasMVEInt, // MVE_VSTRHU16 |
| 18954 | CEFBS_HasMVEInt, // MVE_VSTRHU16_post |
| 18955 | CEFBS_HasMVEInt, // MVE_VSTRHU16_pre |
| 18956 | CEFBS_HasMVEInt, // MVE_VSTRW32_qi |
| 18957 | CEFBS_HasMVEInt, // MVE_VSTRW32_qi_pre |
| 18958 | CEFBS_HasMVEInt, // MVE_VSTRW32_rq |
| 18959 | CEFBS_HasMVEInt, // MVE_VSTRW32_rq_u |
| 18960 | CEFBS_HasMVEInt, // MVE_VSTRWU32 |
| 18961 | CEFBS_HasMVEInt, // MVE_VSTRWU32_post |
| 18962 | CEFBS_HasMVEInt, // MVE_VSTRWU32_pre |
| 18963 | CEFBS_HasMVEFloat, // MVE_VSUB_qr_f16 |
| 18964 | CEFBS_HasMVEFloat, // MVE_VSUB_qr_f32 |
| 18965 | CEFBS_HasMVEInt, // MVE_VSUB_qr_i16 |
| 18966 | CEFBS_HasMVEInt, // MVE_VSUB_qr_i32 |
| 18967 | CEFBS_HasMVEInt, // MVE_VSUB_qr_i8 |
| 18968 | CEFBS_HasMVEFloat, // MVE_VSUBf16 |
| 18969 | CEFBS_HasMVEFloat, // MVE_VSUBf32 |
| 18970 | CEFBS_HasMVEInt, // MVE_VSUBi16 |
| 18971 | CEFBS_HasMVEInt, // MVE_VSUBi32 |
| 18972 | CEFBS_HasMVEInt, // MVE_VSUBi8 |
| 18973 | CEFBS_HasMVEInt, // MVE_WLSTP_16 |
| 18974 | CEFBS_HasMVEInt, // MVE_WLSTP_32 |
| 18975 | CEFBS_HasMVEInt, // MVE_WLSTP_64 |
| 18976 | CEFBS_HasMVEInt, // MVE_WLSTP_8 |
| 18977 | CEFBS_IsARM, // MVNi |
| 18978 | CEFBS_IsARM, // MVNr |
| 18979 | CEFBS_IsARM, // MVNsi |
| 18980 | CEFBS_IsARM, // MVNsr |
| 18981 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMAXNMNDf |
| 18982 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMAXNMNDh |
| 18983 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMAXNMNQf |
| 18984 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMAXNMNQh |
| 18985 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMINNMNDf |
| 18986 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMINNMNDh |
| 18987 | CEFBS_HasFPARMv8_HasNEON, // NEON_VMINNMNQf |
| 18988 | CEFBS_HasFPARMv8_HasNEON_HasFullFP16, // NEON_VMINNMNQh |
| 18989 | CEFBS_IsARM, // ORRri |
| 18990 | CEFBS_IsARM, // ORRrr |
| 18991 | CEFBS_IsARM, // ORRrsi |
| 18992 | CEFBS_IsARM, // ORRrsr |
| 18993 | CEFBS_IsARM_HasV6, // PKHBT |
| 18994 | CEFBS_IsARM_HasV6, // PKHTB |
| 18995 | CEFBS_IsARM_HasV7_HasMP, // PLDWi12 |
| 18996 | CEFBS_IsARM_HasV7_HasMP, // PLDWrs |
| 18997 | CEFBS_IsARM, // PLDi12 |
| 18998 | CEFBS_IsARM, // PLDrs |
| 18999 | CEFBS_IsARM_HasV7, // PLIi12 |
| 19000 | CEFBS_IsARM_HasV7, // PLIrs |
| 19001 | CEFBS_IsARM, // QADD |
| 19002 | CEFBS_IsARM, // QADD16 |
| 19003 | CEFBS_IsARM, // QADD8 |
| 19004 | CEFBS_IsARM, // QASX |
| 19005 | CEFBS_IsARM, // QDADD |
| 19006 | CEFBS_IsARM, // QDSUB |
| 19007 | CEFBS_IsARM, // QSAX |
| 19008 | CEFBS_IsARM, // QSUB |
| 19009 | CEFBS_IsARM, // QSUB16 |
| 19010 | CEFBS_IsARM, // QSUB8 |
| 19011 | CEFBS_IsARM_HasV6T2, // RBIT |
| 19012 | CEFBS_IsARM_HasV6, // REV |
| 19013 | CEFBS_IsARM_HasV6, // REV16 |
| 19014 | CEFBS_IsARM_HasV6, // REVSH |
| 19015 | CEFBS_IsARM, // RFEDA |
| 19016 | CEFBS_IsARM, // RFEDA_UPD |
| 19017 | CEFBS_IsARM, // RFEDB |
| 19018 | CEFBS_IsARM, // RFEDB_UPD |
| 19019 | CEFBS_IsARM, // RFEIA |
| 19020 | CEFBS_IsARM, // RFEIA_UPD |
| 19021 | CEFBS_IsARM, // RFEIB |
| 19022 | CEFBS_IsARM, // RFEIB_UPD |
| 19023 | CEFBS_IsARM, // RSBri |
| 19024 | CEFBS_IsARM, // RSBrr |
| 19025 | CEFBS_IsARM, // RSBrsi |
| 19026 | CEFBS_IsARM, // RSBrsr |
| 19027 | CEFBS_IsARM, // RSCri |
| 19028 | CEFBS_IsARM, // RSCrr |
| 19029 | CEFBS_IsARM, // RSCrsi |
| 19030 | CEFBS_IsARM, // RSCrsr |
| 19031 | CEFBS_IsARM, // SADD16 |
| 19032 | CEFBS_IsARM, // SADD8 |
| 19033 | CEFBS_IsARM, // SASX |
| 19034 | CEFBS_IsARM_HasSB, // SB |
| 19035 | CEFBS_IsARM, // SBCri |
| 19036 | CEFBS_IsARM, // SBCrr |
| 19037 | CEFBS_IsARM, // SBCrsi |
| 19038 | CEFBS_IsARM, // SBCrsr |
| 19039 | CEFBS_IsARM_HasV6T2, // SBFX |
| 19040 | CEFBS_IsARM_HasDivideInARM, // SDIV |
| 19041 | CEFBS_IsARM_HasV6, // SEL |
| 19042 | CEFBS_IsARM, // SETEND |
| 19043 | CEFBS_IsARM_HasV8_HasV8_1a, // SETPAN |
| 19044 | CEFBS_HasV8_HasSHA2, // SHA1C |
| 19045 | CEFBS_HasV8_HasSHA2, // SHA1H |
| 19046 | CEFBS_HasV8_HasSHA2, // SHA1M |
| 19047 | CEFBS_HasV8_HasSHA2, // SHA1P |
| 19048 | CEFBS_HasV8_HasSHA2, // SHA1SU0 |
| 19049 | CEFBS_HasV8_HasSHA2, // SHA1SU1 |
| 19050 | CEFBS_HasV8_HasSHA2, // SHA256H |
| 19051 | CEFBS_HasV8_HasSHA2, // SHA256H2 |
| 19052 | CEFBS_HasV8_HasSHA2, // SHA256SU0 |
| 19053 | CEFBS_HasV8_HasSHA2, // SHA256SU1 |
| 19054 | CEFBS_IsARM, // SHADD16 |
| 19055 | CEFBS_IsARM, // SHADD8 |
| 19056 | CEFBS_IsARM, // SHASX |
| 19057 | CEFBS_IsARM, // SHSAX |
| 19058 | CEFBS_IsARM, // SHSUB16 |
| 19059 | CEFBS_IsARM, // SHSUB8 |
| 19060 | CEFBS_IsARM_HasTrustZone, // SMC |
| 19061 | CEFBS_IsARM_HasV5TE, // SMLABB |
| 19062 | CEFBS_IsARM_HasV5TE, // SMLABT |
| 19063 | CEFBS_IsARM_HasV6, // SMLAD |
| 19064 | CEFBS_IsARM_HasV6, // SMLADX |
| 19065 | CEFBS_IsARM_HasV6, // SMLAL |
| 19066 | CEFBS_IsARM_HasV5TE, // SMLALBB |
| 19067 | CEFBS_IsARM_HasV5TE, // SMLALBT |
| 19068 | CEFBS_IsARM_HasV6, // SMLALD |
| 19069 | CEFBS_IsARM_HasV6, // SMLALDX |
| 19070 | CEFBS_IsARM_HasV5TE, // SMLALTB |
| 19071 | CEFBS_IsARM_HasV5TE, // SMLALTT |
| 19072 | CEFBS_IsARM_HasV5TE, // SMLATB |
| 19073 | CEFBS_IsARM_HasV5TE, // SMLATT |
| 19074 | CEFBS_IsARM_HasV5TE, // SMLAWB |
| 19075 | CEFBS_IsARM_HasV5TE, // SMLAWT |
| 19076 | CEFBS_IsARM_HasV6, // SMLSD |
| 19077 | CEFBS_IsARM_HasV6, // SMLSDX |
| 19078 | CEFBS_IsARM_HasV6, // SMLSLD |
| 19079 | CEFBS_IsARM_HasV6, // SMLSLDX |
| 19080 | CEFBS_IsARM_HasV6, // SMMLA |
| 19081 | CEFBS_IsARM_HasV6, // SMMLAR |
| 19082 | CEFBS_IsARM_HasV6, // SMMLS |
| 19083 | CEFBS_IsARM_HasV6, // SMMLSR |
| 19084 | CEFBS_IsARM_HasV6, // SMMUL |
| 19085 | CEFBS_IsARM_HasV6, // SMMULR |
| 19086 | CEFBS_IsARM_HasV6, // SMUAD |
| 19087 | CEFBS_IsARM_HasV6, // SMUADX |
| 19088 | CEFBS_IsARM_HasV5TE, // SMULBB |
| 19089 | CEFBS_IsARM_HasV5TE, // SMULBT |
| 19090 | CEFBS_IsARM_HasV6, // SMULL |
| 19091 | CEFBS_IsARM_HasV5TE, // SMULTB |
| 19092 | CEFBS_IsARM_HasV5TE, // SMULTT |
| 19093 | CEFBS_IsARM_HasV5TE, // SMULWB |
| 19094 | CEFBS_IsARM_HasV5TE, // SMULWT |
| 19095 | CEFBS_IsARM_HasV6, // SMUSD |
| 19096 | CEFBS_IsARM_HasV6, // SMUSDX |
| 19097 | CEFBS_IsARM, // SRSDA |
| 19098 | CEFBS_IsARM, // SRSDA_UPD |
| 19099 | CEFBS_IsARM, // SRSDB |
| 19100 | CEFBS_IsARM, // SRSDB_UPD |
| 19101 | CEFBS_IsARM, // SRSIA |
| 19102 | CEFBS_IsARM, // SRSIA_UPD |
| 19103 | CEFBS_IsARM, // SRSIB |
| 19104 | CEFBS_IsARM, // SRSIB_UPD |
| 19105 | CEFBS_IsARM_HasV6, // SSAT |
| 19106 | CEFBS_IsARM_HasV6, // SSAT16 |
| 19107 | CEFBS_IsARM, // SSAX |
| 19108 | CEFBS_IsARM, // SSUB16 |
| 19109 | CEFBS_IsARM, // SSUB8 |
| 19110 | CEFBS_IsARM_PreV8, // STC2L_OFFSET |
| 19111 | CEFBS_IsARM_PreV8, // STC2L_OPTION |
| 19112 | CEFBS_IsARM_PreV8, // STC2L_POST |
| 19113 | CEFBS_IsARM_PreV8, // STC2L_PRE |
| 19114 | CEFBS_IsARM_PreV8, // STC2_OFFSET |
| 19115 | CEFBS_IsARM_PreV8, // STC2_OPTION |
| 19116 | CEFBS_IsARM_PreV8, // STC2_POST |
| 19117 | CEFBS_IsARM_PreV8, // STC2_PRE |
| 19118 | CEFBS_IsARM, // STCL_OFFSET |
| 19119 | CEFBS_IsARM, // STCL_OPTION |
| 19120 | CEFBS_IsARM, // STCL_POST |
| 19121 | CEFBS_IsARM, // STCL_PRE |
| 19122 | CEFBS_IsARM, // STC_OFFSET |
| 19123 | CEFBS_IsARM, // STC_OPTION |
| 19124 | CEFBS_IsARM, // STC_POST |
| 19125 | CEFBS_IsARM, // STC_PRE |
| 19126 | CEFBS_IsARM_HasAcquireRelease, // STL |
| 19127 | CEFBS_IsARM_HasAcquireRelease, // STLB |
| 19128 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEX |
| 19129 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXB |
| 19130 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXD |
| 19131 | CEFBS_IsARM_HasAcquireRelease_HasV7Clrex, // STLEXH |
| 19132 | CEFBS_IsARM_HasAcquireRelease, // STLH |
| 19133 | CEFBS_IsARM, // STMDA |
| 19134 | CEFBS_IsARM, // STMDA_UPD |
| 19135 | CEFBS_IsARM, // STMDB |
| 19136 | CEFBS_IsARM, // STMDB_UPD |
| 19137 | CEFBS_IsARM, // STMIA |
| 19138 | CEFBS_IsARM, // STMIA_UPD |
| 19139 | CEFBS_IsARM, // STMIB |
| 19140 | CEFBS_IsARM, // STMIB_UPD |
| 19141 | CEFBS_IsARM, // STRBT_POST_IMM |
| 19142 | CEFBS_IsARM, // STRBT_POST_REG |
| 19143 | CEFBS_IsARM, // STRB_POST_IMM |
| 19144 | CEFBS_IsARM, // STRB_POST_REG |
| 19145 | CEFBS_IsARM, // STRB_PRE_IMM |
| 19146 | CEFBS_IsARM, // STRB_PRE_REG |
| 19147 | CEFBS_IsARM, // STRBi12 |
| 19148 | CEFBS_IsARM, // STRBrs |
| 19149 | CEFBS_IsARM_HasV5TE, // STRD |
| 19150 | CEFBS_IsARM, // STRD_POST |
| 19151 | CEFBS_IsARM, // STRD_PRE |
| 19152 | CEFBS_IsARM, // STREX |
| 19153 | CEFBS_IsARM, // STREXB |
| 19154 | CEFBS_IsARM, // STREXD |
| 19155 | CEFBS_IsARM, // STREXH |
| 19156 | CEFBS_IsARM, // STRH |
| 19157 | CEFBS_IsARM, // STRHTi |
| 19158 | CEFBS_IsARM, // STRHTr |
| 19159 | CEFBS_IsARM, // STRH_POST |
| 19160 | CEFBS_IsARM, // STRH_PRE |
| 19161 | CEFBS_IsARM, // STRT_POST_IMM |
| 19162 | CEFBS_IsARM, // STRT_POST_REG |
| 19163 | CEFBS_IsARM, // STR_POST_IMM |
| 19164 | CEFBS_IsARM, // STR_POST_REG |
| 19165 | CEFBS_IsARM, // STR_PRE_IMM |
| 19166 | CEFBS_IsARM, // STR_PRE_REG |
| 19167 | CEFBS_IsARM, // STRi12 |
| 19168 | CEFBS_IsARM, // STRrs |
| 19169 | CEFBS_IsARM, // SUBri |
| 19170 | CEFBS_IsARM, // SUBrr |
| 19171 | CEFBS_IsARM, // SUBrsi |
| 19172 | CEFBS_IsARM, // SUBrsr |
| 19173 | CEFBS_IsARM, // SVC |
| 19174 | CEFBS_IsARM_PreV8, // SWP |
| 19175 | CEFBS_IsARM_PreV8, // SWPB |
| 19176 | CEFBS_IsARM_HasV6, // SXTAB |
| 19177 | CEFBS_IsARM_HasV6, // SXTAB16 |
| 19178 | CEFBS_IsARM_HasV6, // SXTAH |
| 19179 | CEFBS_IsARM_HasV6, // SXTB |
| 19180 | CEFBS_IsARM_HasV6, // SXTB16 |
| 19181 | CEFBS_IsARM_HasV6, // SXTH |
| 19182 | CEFBS_IsARM, // TEQri |
| 19183 | CEFBS_IsARM, // TEQrr |
| 19184 | CEFBS_IsARM, // TEQrsi |
| 19185 | CEFBS_IsARM, // TEQrsr |
| 19186 | CEFBS_IsARM, // TRAP |
| 19187 | CEFBS_IsARM_HasV8_4a, // TSB |
| 19188 | CEFBS_IsARM, // TSTri |
| 19189 | CEFBS_IsARM, // TSTrr |
| 19190 | CEFBS_IsARM, // TSTrsi |
| 19191 | CEFBS_IsARM, // TSTrsr |
| 19192 | CEFBS_IsARM, // UADD16 |
| 19193 | CEFBS_IsARM, // UADD8 |
| 19194 | CEFBS_IsARM, // UASX |
| 19195 | CEFBS_IsARM_HasV6T2, // UBFX |
| 19196 | CEFBS_IsARM, // UDF |
| 19197 | CEFBS_IsARM_HasDivideInARM, // UDIV |
| 19198 | CEFBS_IsARM, // UHADD16 |
| 19199 | CEFBS_IsARM, // UHADD8 |
| 19200 | CEFBS_IsARM, // UHASX |
| 19201 | CEFBS_IsARM, // UHSAX |
| 19202 | CEFBS_IsARM, // UHSUB16 |
| 19203 | CEFBS_IsARM, // UHSUB8 |
| 19204 | CEFBS_IsARM_HasV6, // UMAAL |
| 19205 | CEFBS_IsARM_HasV6, // UMLAL |
| 19206 | CEFBS_IsARM_HasV6, // UMULL |
| 19207 | CEFBS_IsARM, // UQADD16 |
| 19208 | CEFBS_IsARM, // UQADD8 |
| 19209 | CEFBS_IsARM, // UQASX |
| 19210 | CEFBS_IsARM, // UQSAX |
| 19211 | CEFBS_IsARM, // UQSUB16 |
| 19212 | CEFBS_IsARM, // UQSUB8 |
| 19213 | CEFBS_IsARM_HasV6, // USAD8 |
| 19214 | CEFBS_IsARM_HasV6, // USADA8 |
| 19215 | CEFBS_IsARM_HasV6, // USAT |
| 19216 | CEFBS_IsARM_HasV6, // USAT16 |
| 19217 | CEFBS_IsARM, // USAX |
| 19218 | CEFBS_IsARM, // USUB16 |
| 19219 | CEFBS_IsARM, // USUB8 |
| 19220 | CEFBS_IsARM_HasV6, // UXTAB |
| 19221 | CEFBS_IsARM_HasV6, // UXTAB16 |
| 19222 | CEFBS_IsARM_HasV6, // UXTAH |
| 19223 | CEFBS_IsARM_HasV6, // UXTB |
| 19224 | CEFBS_IsARM_HasV6, // UXTB16 |
| 19225 | CEFBS_IsARM_HasV6, // UXTH |
| 19226 | CEFBS_HasNEON, // VABALsv2i64 |
| 19227 | CEFBS_HasNEON, // VABALsv4i32 |
| 19228 | CEFBS_HasNEON, // VABALsv8i16 |
| 19229 | CEFBS_HasNEON, // VABALuv2i64 |
| 19230 | CEFBS_HasNEON, // VABALuv4i32 |
| 19231 | CEFBS_HasNEON, // VABALuv8i16 |
| 19232 | CEFBS_HasNEON, // VABAsv16i8 |
| 19233 | CEFBS_HasNEON, // VABAsv2i32 |
| 19234 | CEFBS_HasNEON, // VABAsv4i16 |
| 19235 | CEFBS_HasNEON, // VABAsv4i32 |
| 19236 | CEFBS_HasNEON, // VABAsv8i16 |
| 19237 | CEFBS_HasNEON, // VABAsv8i8 |
| 19238 | CEFBS_HasNEON, // VABAuv16i8 |
| 19239 | CEFBS_HasNEON, // VABAuv2i32 |
| 19240 | CEFBS_HasNEON, // VABAuv4i16 |
| 19241 | CEFBS_HasNEON, // VABAuv4i32 |
| 19242 | CEFBS_HasNEON, // VABAuv8i16 |
| 19243 | CEFBS_HasNEON, // VABAuv8i8 |
| 19244 | CEFBS_HasNEON, // VABDLsv2i64 |
| 19245 | CEFBS_HasNEON, // VABDLsv4i32 |
| 19246 | CEFBS_HasNEON, // VABDLsv8i16 |
| 19247 | CEFBS_HasNEON, // VABDLuv2i64 |
| 19248 | CEFBS_HasNEON, // VABDLuv4i32 |
| 19249 | CEFBS_HasNEON, // VABDLuv8i16 |
| 19250 | CEFBS_HasNEON, // VABDfd |
| 19251 | CEFBS_HasNEON, // VABDfq |
| 19252 | CEFBS_HasNEON_HasFullFP16, // VABDhd |
| 19253 | CEFBS_HasNEON_HasFullFP16, // VABDhq |
| 19254 | CEFBS_HasNEON, // VABDsv16i8 |
| 19255 | CEFBS_HasNEON, // VABDsv2i32 |
| 19256 | CEFBS_HasNEON, // VABDsv4i16 |
| 19257 | CEFBS_HasNEON, // VABDsv4i32 |
| 19258 | CEFBS_HasNEON, // VABDsv8i16 |
| 19259 | CEFBS_HasNEON, // VABDsv8i8 |
| 19260 | CEFBS_HasNEON, // VABDuv16i8 |
| 19261 | CEFBS_HasNEON, // VABDuv2i32 |
| 19262 | CEFBS_HasNEON, // VABDuv4i16 |
| 19263 | CEFBS_HasNEON, // VABDuv4i32 |
| 19264 | CEFBS_HasNEON, // VABDuv8i16 |
| 19265 | CEFBS_HasNEON, // VABDuv8i8 |
| 19266 | CEFBS_HasVFP2_HasDPVFP, // VABSD |
| 19267 | CEFBS_HasFullFP16, // VABSH |
| 19268 | CEFBS_HasVFP2, // VABSS |
| 19269 | CEFBS_HasNEON, // VABSfd |
| 19270 | CEFBS_HasNEON, // VABSfq |
| 19271 | CEFBS_HasNEON_HasFullFP16, // VABShd |
| 19272 | CEFBS_HasNEON_HasFullFP16, // VABShq |
| 19273 | CEFBS_HasNEON, // VABSv16i8 |
| 19274 | CEFBS_HasNEON, // VABSv2i32 |
| 19275 | CEFBS_HasNEON, // VABSv4i16 |
| 19276 | CEFBS_HasNEON, // VABSv4i32 |
| 19277 | CEFBS_HasNEON, // VABSv8i16 |
| 19278 | CEFBS_HasNEON, // VABSv8i8 |
| 19279 | CEFBS_HasNEON, // VACGEfd |
| 19280 | CEFBS_HasNEON, // VACGEfq |
| 19281 | CEFBS_HasNEON_HasFullFP16, // VACGEhd |
| 19282 | CEFBS_HasNEON_HasFullFP16, // VACGEhq |
| 19283 | CEFBS_HasNEON, // VACGTfd |
| 19284 | CEFBS_HasNEON, // VACGTfq |
| 19285 | CEFBS_HasNEON_HasFullFP16, // VACGThd |
| 19286 | CEFBS_HasNEON_HasFullFP16, // VACGThq |
| 19287 | CEFBS_HasVFP2_HasDPVFP, // VADDD |
| 19288 | CEFBS_HasFullFP16, // VADDH |
| 19289 | CEFBS_HasNEON, // VADDHNv2i32 |
| 19290 | CEFBS_HasNEON, // VADDHNv4i16 |
| 19291 | CEFBS_HasNEON, // VADDHNv8i8 |
| 19292 | CEFBS_HasNEON, // VADDLsv2i64 |
| 19293 | CEFBS_HasNEON, // VADDLsv4i32 |
| 19294 | CEFBS_HasNEON, // VADDLsv8i16 |
| 19295 | CEFBS_HasNEON, // VADDLuv2i64 |
| 19296 | CEFBS_HasNEON, // VADDLuv4i32 |
| 19297 | CEFBS_HasNEON, // VADDLuv8i16 |
| 19298 | CEFBS_HasVFP2, // VADDS |
| 19299 | CEFBS_HasNEON, // VADDWsv2i64 |
| 19300 | CEFBS_HasNEON, // VADDWsv4i32 |
| 19301 | CEFBS_HasNEON, // VADDWsv8i16 |
| 19302 | CEFBS_HasNEON, // VADDWuv2i64 |
| 19303 | CEFBS_HasNEON, // VADDWuv4i32 |
| 19304 | CEFBS_HasNEON, // VADDWuv8i16 |
| 19305 | CEFBS_HasNEON, // VADDfd |
| 19306 | CEFBS_HasNEON, // VADDfq |
| 19307 | CEFBS_HasNEON_HasFullFP16, // VADDhd |
| 19308 | CEFBS_HasNEON_HasFullFP16, // VADDhq |
| 19309 | CEFBS_HasNEON, // VADDv16i8 |
| 19310 | CEFBS_HasNEON, // VADDv1i64 |
| 19311 | CEFBS_HasNEON, // VADDv2i32 |
| 19312 | CEFBS_HasNEON, // VADDv2i64 |
| 19313 | CEFBS_HasNEON, // VADDv4i16 |
| 19314 | CEFBS_HasNEON, // VADDv4i32 |
| 19315 | CEFBS_HasNEON, // VADDv8i16 |
| 19316 | CEFBS_HasNEON, // VADDv8i8 |
| 19317 | CEFBS_HasNEON, // VANDd |
| 19318 | CEFBS_HasNEON, // VANDq |
| 19319 | CEFBS_HasBF16_HasNEON, // VBF16MALBQ |
| 19320 | CEFBS_HasBF16_HasNEON, // VBF16MALBQI |
| 19321 | CEFBS_HasBF16_HasNEON, // VBF16MALTQ |
| 19322 | CEFBS_HasBF16_HasNEON, // VBF16MALTQI |
| 19323 | CEFBS_HasNEON, // VBICd |
| 19324 | CEFBS_HasNEON, // VBICiv2i32 |
| 19325 | CEFBS_HasNEON, // VBICiv4i16 |
| 19326 | CEFBS_HasNEON, // VBICiv4i32 |
| 19327 | CEFBS_HasNEON, // VBICiv8i16 |
| 19328 | CEFBS_HasNEON, // VBICq |
| 19329 | CEFBS_HasNEON, // VBIFd |
| 19330 | CEFBS_HasNEON, // VBIFq |
| 19331 | CEFBS_HasNEON, // VBITd |
| 19332 | CEFBS_HasNEON, // VBITq |
| 19333 | CEFBS_HasNEON, // VBSLd |
| 19334 | CEFBS_HasNEON, // VBSLq |
| 19335 | CEFBS_HasNEON, // VBSPd |
| 19336 | CEFBS_HasNEON, // VBSPq |
| 19337 | CEFBS_HasNEON_HasV8_3a, // VCADDv2f32 |
| 19338 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv4f16 |
| 19339 | CEFBS_HasNEON_HasV8_3a, // VCADDv4f32 |
| 19340 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCADDv8f16 |
| 19341 | CEFBS_HasNEON, // VCEQfd |
| 19342 | CEFBS_HasNEON, // VCEQfq |
| 19343 | CEFBS_HasNEON_HasFullFP16, // VCEQhd |
| 19344 | CEFBS_HasNEON_HasFullFP16, // VCEQhq |
| 19345 | CEFBS_HasNEON, // VCEQv16i8 |
| 19346 | CEFBS_HasNEON, // VCEQv2i32 |
| 19347 | CEFBS_HasNEON, // VCEQv4i16 |
| 19348 | CEFBS_HasNEON, // VCEQv4i32 |
| 19349 | CEFBS_HasNEON, // VCEQv8i16 |
| 19350 | CEFBS_HasNEON, // VCEQv8i8 |
| 19351 | CEFBS_HasNEON, // VCEQzv16i8 |
| 19352 | CEFBS_HasNEON, // VCEQzv2f32 |
| 19353 | CEFBS_HasNEON, // VCEQzv2i32 |
| 19354 | CEFBS_HasNEON_HasFullFP16, // VCEQzv4f16 |
| 19355 | CEFBS_HasNEON, // VCEQzv4f32 |
| 19356 | CEFBS_HasNEON, // VCEQzv4i16 |
| 19357 | CEFBS_HasNEON, // VCEQzv4i32 |
| 19358 | CEFBS_HasNEON_HasFullFP16, // VCEQzv8f16 |
| 19359 | CEFBS_HasNEON, // VCEQzv8i16 |
| 19360 | CEFBS_HasNEON, // VCEQzv8i8 |
| 19361 | CEFBS_HasNEON, // VCGEfd |
| 19362 | CEFBS_HasNEON, // VCGEfq |
| 19363 | CEFBS_HasNEON_HasFullFP16, // VCGEhd |
| 19364 | CEFBS_HasNEON_HasFullFP16, // VCGEhq |
| 19365 | CEFBS_HasNEON, // VCGEsv16i8 |
| 19366 | CEFBS_HasNEON, // VCGEsv2i32 |
| 19367 | CEFBS_HasNEON, // VCGEsv4i16 |
| 19368 | CEFBS_HasNEON, // VCGEsv4i32 |
| 19369 | CEFBS_HasNEON, // VCGEsv8i16 |
| 19370 | CEFBS_HasNEON, // VCGEsv8i8 |
| 19371 | CEFBS_HasNEON, // VCGEuv16i8 |
| 19372 | CEFBS_HasNEON, // VCGEuv2i32 |
| 19373 | CEFBS_HasNEON, // VCGEuv4i16 |
| 19374 | CEFBS_HasNEON, // VCGEuv4i32 |
| 19375 | CEFBS_HasNEON, // VCGEuv8i16 |
| 19376 | CEFBS_HasNEON, // VCGEuv8i8 |
| 19377 | CEFBS_HasNEON, // VCGEzv16i8 |
| 19378 | CEFBS_HasNEON, // VCGEzv2f32 |
| 19379 | CEFBS_HasNEON, // VCGEzv2i32 |
| 19380 | CEFBS_HasNEON_HasFullFP16, // VCGEzv4f16 |
| 19381 | CEFBS_HasNEON, // VCGEzv4f32 |
| 19382 | CEFBS_HasNEON, // VCGEzv4i16 |
| 19383 | CEFBS_HasNEON, // VCGEzv4i32 |
| 19384 | CEFBS_HasNEON_HasFullFP16, // VCGEzv8f16 |
| 19385 | CEFBS_HasNEON, // VCGEzv8i16 |
| 19386 | CEFBS_HasNEON, // VCGEzv8i8 |
| 19387 | CEFBS_HasNEON, // VCGTfd |
| 19388 | CEFBS_HasNEON, // VCGTfq |
| 19389 | CEFBS_HasNEON_HasFullFP16, // VCGThd |
| 19390 | CEFBS_HasNEON_HasFullFP16, // VCGThq |
| 19391 | CEFBS_HasNEON, // VCGTsv16i8 |
| 19392 | CEFBS_HasNEON, // VCGTsv2i32 |
| 19393 | CEFBS_HasNEON, // VCGTsv4i16 |
| 19394 | CEFBS_HasNEON, // VCGTsv4i32 |
| 19395 | CEFBS_HasNEON, // VCGTsv8i16 |
| 19396 | CEFBS_HasNEON, // VCGTsv8i8 |
| 19397 | CEFBS_HasNEON, // VCGTuv16i8 |
| 19398 | CEFBS_HasNEON, // VCGTuv2i32 |
| 19399 | CEFBS_HasNEON, // VCGTuv4i16 |
| 19400 | CEFBS_HasNEON, // VCGTuv4i32 |
| 19401 | CEFBS_HasNEON, // VCGTuv8i16 |
| 19402 | CEFBS_HasNEON, // VCGTuv8i8 |
| 19403 | CEFBS_HasNEON, // VCGTzv16i8 |
| 19404 | CEFBS_HasNEON, // VCGTzv2f32 |
| 19405 | CEFBS_HasNEON, // VCGTzv2i32 |
| 19406 | CEFBS_HasNEON_HasFullFP16, // VCGTzv4f16 |
| 19407 | CEFBS_HasNEON, // VCGTzv4f32 |
| 19408 | CEFBS_HasNEON, // VCGTzv4i16 |
| 19409 | CEFBS_HasNEON, // VCGTzv4i32 |
| 19410 | CEFBS_HasNEON_HasFullFP16, // VCGTzv8f16 |
| 19411 | CEFBS_HasNEON, // VCGTzv8i16 |
| 19412 | CEFBS_HasNEON, // VCGTzv8i8 |
| 19413 | CEFBS_HasNEON, // VCLEzv16i8 |
| 19414 | CEFBS_HasNEON, // VCLEzv2f32 |
| 19415 | CEFBS_HasNEON, // VCLEzv2i32 |
| 19416 | CEFBS_HasNEON_HasFullFP16, // VCLEzv4f16 |
| 19417 | CEFBS_HasNEON, // VCLEzv4f32 |
| 19418 | CEFBS_HasNEON, // VCLEzv4i16 |
| 19419 | CEFBS_HasNEON, // VCLEzv4i32 |
| 19420 | CEFBS_HasNEON_HasFullFP16, // VCLEzv8f16 |
| 19421 | CEFBS_HasNEON, // VCLEzv8i16 |
| 19422 | CEFBS_HasNEON, // VCLEzv8i8 |
| 19423 | CEFBS_HasNEON, // VCLSv16i8 |
| 19424 | CEFBS_HasNEON, // VCLSv2i32 |
| 19425 | CEFBS_HasNEON, // VCLSv4i16 |
| 19426 | CEFBS_HasNEON, // VCLSv4i32 |
| 19427 | CEFBS_HasNEON, // VCLSv8i16 |
| 19428 | CEFBS_HasNEON, // VCLSv8i8 |
| 19429 | CEFBS_HasNEON, // VCLTzv16i8 |
| 19430 | CEFBS_HasNEON, // VCLTzv2f32 |
| 19431 | CEFBS_HasNEON, // VCLTzv2i32 |
| 19432 | CEFBS_HasNEON_HasFullFP16, // VCLTzv4f16 |
| 19433 | CEFBS_HasNEON, // VCLTzv4f32 |
| 19434 | CEFBS_HasNEON, // VCLTzv4i16 |
| 19435 | CEFBS_HasNEON, // VCLTzv4i32 |
| 19436 | CEFBS_HasNEON_HasFullFP16, // VCLTzv8f16 |
| 19437 | CEFBS_HasNEON, // VCLTzv8i16 |
| 19438 | CEFBS_HasNEON, // VCLTzv8i8 |
| 19439 | CEFBS_HasNEON, // VCLZv16i8 |
| 19440 | CEFBS_HasNEON, // VCLZv2i32 |
| 19441 | CEFBS_HasNEON, // VCLZv4i16 |
| 19442 | CEFBS_HasNEON, // VCLZv4i32 |
| 19443 | CEFBS_HasNEON, // VCLZv8i16 |
| 19444 | CEFBS_HasNEON, // VCLZv8i8 |
| 19445 | CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32 |
| 19446 | CEFBS_HasNEON_HasV8_3a, // VCMLAv2f32_indexed |
| 19447 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16 |
| 19448 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv4f16_indexed |
| 19449 | CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32 |
| 19450 | CEFBS_HasNEON_HasV8_3a, // VCMLAv4f32_indexed |
| 19451 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16 |
| 19452 | CEFBS_HasNEON_HasV8_3a_HasFullFP16, // VCMLAv8f16_indexed |
| 19453 | CEFBS_HasVFP2_HasDPVFP, // VCMPD |
| 19454 | CEFBS_HasVFP2_HasDPVFP, // VCMPED |
| 19455 | CEFBS_HasFullFP16, // VCMPEH |
| 19456 | CEFBS_HasVFP2, // VCMPES |
| 19457 | CEFBS_HasVFP2_HasDPVFP, // VCMPEZD |
| 19458 | CEFBS_HasFullFP16, // VCMPEZH |
| 19459 | CEFBS_HasVFP2, // VCMPEZS |
| 19460 | CEFBS_HasFullFP16, // VCMPH |
| 19461 | CEFBS_HasVFP2, // VCMPS |
| 19462 | CEFBS_HasVFP2_HasDPVFP, // VCMPZD |
| 19463 | CEFBS_HasFullFP16, // VCMPZH |
| 19464 | CEFBS_HasVFP2, // VCMPZS |
| 19465 | CEFBS_HasNEON, // VCNTd |
| 19466 | CEFBS_HasNEON, // VCNTq |
| 19467 | CEFBS_HasV8_HasNEON, // VCVTANSDf |
| 19468 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSDh |
| 19469 | CEFBS_HasV8_HasNEON, // VCVTANSQf |
| 19470 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANSQh |
| 19471 | CEFBS_HasV8_HasNEON, // VCVTANUDf |
| 19472 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUDh |
| 19473 | CEFBS_HasV8_HasNEON, // VCVTANUQf |
| 19474 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTANUQh |
| 19475 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTASD |
| 19476 | CEFBS_HasFullFP16, // VCVTASH |
| 19477 | CEFBS_HasFPARMv8, // VCVTASS |
| 19478 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTAUD |
| 19479 | CEFBS_HasFullFP16, // VCVTAUH |
| 19480 | CEFBS_HasFPARMv8, // VCVTAUS |
| 19481 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTBDH |
| 19482 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTBHD |
| 19483 | CEFBS_HasFP16, // VCVTBHS |
| 19484 | CEFBS_HasFP16, // VCVTBSH |
| 19485 | CEFBS_HasVFP2_HasDPVFP, // VCVTDS |
| 19486 | CEFBS_HasV8_HasNEON, // VCVTMNSDf |
| 19487 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSDh |
| 19488 | CEFBS_HasV8_HasNEON, // VCVTMNSQf |
| 19489 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNSQh |
| 19490 | CEFBS_HasV8_HasNEON, // VCVTMNUDf |
| 19491 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUDh |
| 19492 | CEFBS_HasV8_HasNEON, // VCVTMNUQf |
| 19493 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTMNUQh |
| 19494 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTMSD |
| 19495 | CEFBS_HasFullFP16, // VCVTMSH |
| 19496 | CEFBS_HasFPARMv8, // VCVTMSS |
| 19497 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTMUD |
| 19498 | CEFBS_HasFullFP16, // VCVTMUH |
| 19499 | CEFBS_HasFPARMv8, // VCVTMUS |
| 19500 | CEFBS_HasV8_HasNEON, // VCVTNNSDf |
| 19501 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSDh |
| 19502 | CEFBS_HasV8_HasNEON, // VCVTNNSQf |
| 19503 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNSQh |
| 19504 | CEFBS_HasV8_HasNEON, // VCVTNNUDf |
| 19505 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUDh |
| 19506 | CEFBS_HasV8_HasNEON, // VCVTNNUQf |
| 19507 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTNNUQh |
| 19508 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTNSD |
| 19509 | CEFBS_HasFullFP16, // VCVTNSH |
| 19510 | CEFBS_HasFPARMv8, // VCVTNSS |
| 19511 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTNUD |
| 19512 | CEFBS_HasFullFP16, // VCVTNUH |
| 19513 | CEFBS_HasFPARMv8, // VCVTNUS |
| 19514 | CEFBS_HasV8_HasNEON, // VCVTPNSDf |
| 19515 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSDh |
| 19516 | CEFBS_HasV8_HasNEON, // VCVTPNSQf |
| 19517 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNSQh |
| 19518 | CEFBS_HasV8_HasNEON, // VCVTPNUDf |
| 19519 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUDh |
| 19520 | CEFBS_HasV8_HasNEON, // VCVTPNUQf |
| 19521 | CEFBS_HasV8_HasNEON_HasFullFP16, // VCVTPNUQh |
| 19522 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTPSD |
| 19523 | CEFBS_HasFullFP16, // VCVTPSH |
| 19524 | CEFBS_HasFPARMv8, // VCVTPSS |
| 19525 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTPUD |
| 19526 | CEFBS_HasFullFP16, // VCVTPUH |
| 19527 | CEFBS_HasFPARMv8, // VCVTPUS |
| 19528 | CEFBS_HasVFP2_HasDPVFP, // VCVTSD |
| 19529 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTTDH |
| 19530 | CEFBS_HasFPARMv8_HasDPVFP, // VCVTTHD |
| 19531 | CEFBS_HasFP16, // VCVTTHS |
| 19532 | CEFBS_HasFP16, // VCVTTSH |
| 19533 | CEFBS_HasNEON_HasFP16, // VCVTf2h |
| 19534 | CEFBS_HasNEON, // VCVTf2sd |
| 19535 | CEFBS_HasNEON, // VCVTf2sq |
| 19536 | CEFBS_HasNEON, // VCVTf2ud |
| 19537 | CEFBS_HasNEON, // VCVTf2uq |
| 19538 | CEFBS_HasNEON, // VCVTf2xsd |
| 19539 | CEFBS_HasNEON, // VCVTf2xsq |
| 19540 | CEFBS_HasNEON, // VCVTf2xud |
| 19541 | CEFBS_HasNEON, // VCVTf2xuq |
| 19542 | CEFBS_HasNEON_HasFP16, // VCVTh2f |
| 19543 | CEFBS_HasNEON_HasFullFP16, // VCVTh2sd |
| 19544 | CEFBS_HasNEON_HasFullFP16, // VCVTh2sq |
| 19545 | CEFBS_HasNEON_HasFullFP16, // VCVTh2ud |
| 19546 | CEFBS_HasNEON_HasFullFP16, // VCVTh2uq |
| 19547 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xsd |
| 19548 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xsq |
| 19549 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xud |
| 19550 | CEFBS_HasNEON_HasFullFP16, // VCVTh2xuq |
| 19551 | CEFBS_HasNEON, // VCVTs2fd |
| 19552 | CEFBS_HasNEON, // VCVTs2fq |
| 19553 | CEFBS_HasNEON_HasFullFP16, // VCVTs2hd |
| 19554 | CEFBS_HasNEON_HasFullFP16, // VCVTs2hq |
| 19555 | CEFBS_HasNEON, // VCVTu2fd |
| 19556 | CEFBS_HasNEON, // VCVTu2fq |
| 19557 | CEFBS_HasNEON_HasFullFP16, // VCVTu2hd |
| 19558 | CEFBS_HasNEON_HasFullFP16, // VCVTu2hq |
| 19559 | CEFBS_HasNEON, // VCVTxs2fd |
| 19560 | CEFBS_HasNEON, // VCVTxs2fq |
| 19561 | CEFBS_HasNEON_HasFullFP16, // VCVTxs2hd |
| 19562 | CEFBS_HasNEON_HasFullFP16, // VCVTxs2hq |
| 19563 | CEFBS_HasNEON, // VCVTxu2fd |
| 19564 | CEFBS_HasNEON, // VCVTxu2fq |
| 19565 | CEFBS_HasNEON_HasFullFP16, // VCVTxu2hd |
| 19566 | CEFBS_HasNEON_HasFullFP16, // VCVTxu2hq |
| 19567 | CEFBS_HasVFP2_HasDPVFP, // VDIVD |
| 19568 | CEFBS_HasFullFP16, // VDIVH |
| 19569 | CEFBS_HasVFP2, // VDIVS |
| 19570 | CEFBS_HasNEON, // VDUP16d |
| 19571 | CEFBS_HasNEON, // VDUP16q |
| 19572 | CEFBS_HasNEON, // VDUP32d |
| 19573 | CEFBS_HasNEON, // VDUP32q |
| 19574 | CEFBS_HasNEON, // VDUP8d |
| 19575 | CEFBS_HasNEON, // VDUP8q |
| 19576 | CEFBS_HasNEON, // VDUPLN16d |
| 19577 | CEFBS_HasNEON, // VDUPLN16q |
| 19578 | CEFBS_HasNEON, // VDUPLN32d |
| 19579 | CEFBS_HasNEON, // VDUPLN32q |
| 19580 | CEFBS_HasNEON, // VDUPLN8d |
| 19581 | CEFBS_HasNEON, // VDUPLN8q |
| 19582 | CEFBS_HasNEON, // VEORd |
| 19583 | CEFBS_HasNEON, // VEORq |
| 19584 | CEFBS_HasNEON, // VEXTd16 |
| 19585 | CEFBS_HasNEON, // VEXTd32 |
| 19586 | CEFBS_HasNEON, // VEXTd8 |
| 19587 | CEFBS_HasNEON, // VEXTq16 |
| 19588 | CEFBS_HasNEON, // VEXTq32 |
| 19589 | CEFBS_HasNEON, // VEXTq64 |
| 19590 | CEFBS_HasNEON, // VEXTq8 |
| 19591 | CEFBS_HasVFP4_HasDPVFP, // VFMAD |
| 19592 | CEFBS_HasFullFP16, // VFMAH |
| 19593 | CEFBS_HasNEON_HasFP16FML, // VFMALD |
| 19594 | CEFBS_HasNEON_HasFP16FML, // VFMALDI |
| 19595 | CEFBS_HasNEON_HasFP16FML, // VFMALQ |
| 19596 | CEFBS_HasNEON_HasFP16FML, // VFMALQI |
| 19597 | CEFBS_HasVFP4, // VFMAS |
| 19598 | CEFBS_HasNEON_HasVFP4, // VFMAfd |
| 19599 | CEFBS_HasNEON_HasVFP4, // VFMAfq |
| 19600 | CEFBS_HasNEON_HasFullFP16, // VFMAhd |
| 19601 | CEFBS_HasNEON_HasFullFP16, // VFMAhq |
| 19602 | CEFBS_HasVFP4_HasDPVFP, // VFMSD |
| 19603 | CEFBS_HasFullFP16, // VFMSH |
| 19604 | CEFBS_HasNEON_HasFP16FML, // VFMSLD |
| 19605 | CEFBS_HasNEON_HasFP16FML, // VFMSLDI |
| 19606 | CEFBS_HasNEON_HasFP16FML, // VFMSLQ |
| 19607 | CEFBS_HasNEON_HasFP16FML, // VFMSLQI |
| 19608 | CEFBS_HasVFP4, // VFMSS |
| 19609 | CEFBS_HasNEON_HasVFP4, // VFMSfd |
| 19610 | CEFBS_HasNEON_HasVFP4, // VFMSfq |
| 19611 | CEFBS_HasNEON_HasFullFP16, // VFMShd |
| 19612 | CEFBS_HasNEON_HasFullFP16, // VFMShq |
| 19613 | CEFBS_HasVFP4_HasDPVFP, // VFNMAD |
| 19614 | CEFBS_HasFullFP16, // VFNMAH |
| 19615 | CEFBS_HasVFP4, // VFNMAS |
| 19616 | CEFBS_HasVFP4_HasDPVFP, // VFNMSD |
| 19617 | CEFBS_HasFullFP16, // VFNMSH |
| 19618 | CEFBS_HasVFP4, // VFNMSS |
| 19619 | CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMAXNMD |
| 19620 | CEFBS_HasFullFP16, // VFP_VMAXNMH |
| 19621 | CEFBS_HasFPARMv8, // VFP_VMAXNMS |
| 19622 | CEFBS_HasFPARMv8_HasDPVFP, // VFP_VMINNMD |
| 19623 | CEFBS_HasFullFP16, // VFP_VMINNMH |
| 19624 | CEFBS_HasFPARMv8, // VFP_VMINNMS |
| 19625 | CEFBS_HasFPRegs, // VGETLNi32 |
| 19626 | CEFBS_HasNEON, // VGETLNs16 |
| 19627 | CEFBS_HasNEON, // VGETLNs8 |
| 19628 | CEFBS_HasNEON, // VGETLNu16 |
| 19629 | CEFBS_HasNEON, // VGETLNu8 |
| 19630 | CEFBS_HasNEON, // VHADDsv16i8 |
| 19631 | CEFBS_HasNEON, // VHADDsv2i32 |
| 19632 | CEFBS_HasNEON, // VHADDsv4i16 |
| 19633 | CEFBS_HasNEON, // VHADDsv4i32 |
| 19634 | CEFBS_HasNEON, // VHADDsv8i16 |
| 19635 | CEFBS_HasNEON, // VHADDsv8i8 |
| 19636 | CEFBS_HasNEON, // VHADDuv16i8 |
| 19637 | CEFBS_HasNEON, // VHADDuv2i32 |
| 19638 | CEFBS_HasNEON, // VHADDuv4i16 |
| 19639 | CEFBS_HasNEON, // VHADDuv4i32 |
| 19640 | CEFBS_HasNEON, // VHADDuv8i16 |
| 19641 | CEFBS_HasNEON, // VHADDuv8i8 |
| 19642 | CEFBS_HasNEON, // VHSUBsv16i8 |
| 19643 | CEFBS_HasNEON, // VHSUBsv2i32 |
| 19644 | CEFBS_HasNEON, // VHSUBsv4i16 |
| 19645 | CEFBS_HasNEON, // VHSUBsv4i32 |
| 19646 | CEFBS_HasNEON, // VHSUBsv8i16 |
| 19647 | CEFBS_HasNEON, // VHSUBsv8i8 |
| 19648 | CEFBS_HasNEON, // VHSUBuv16i8 |
| 19649 | CEFBS_HasNEON, // VHSUBuv2i32 |
| 19650 | CEFBS_HasNEON, // VHSUBuv4i16 |
| 19651 | CEFBS_HasNEON, // VHSUBuv4i32 |
| 19652 | CEFBS_HasNEON, // VHSUBuv8i16 |
| 19653 | CEFBS_HasNEON, // VHSUBuv8i8 |
| 19654 | CEFBS_HasFullFP16, // VINSH |
| 19655 | CEFBS_HasFPARMv8_HasV8_3a, // VJCVT |
| 19656 | CEFBS_HasNEON, // VLD1DUPd16 |
| 19657 | CEFBS_HasNEON, // VLD1DUPd16wb_fixed |
| 19658 | CEFBS_HasNEON, // VLD1DUPd16wb_register |
| 19659 | CEFBS_HasNEON, // VLD1DUPd32 |
| 19660 | CEFBS_HasNEON, // VLD1DUPd32wb_fixed |
| 19661 | CEFBS_HasNEON, // VLD1DUPd32wb_register |
| 19662 | CEFBS_HasNEON, // VLD1DUPd8 |
| 19663 | CEFBS_HasNEON, // VLD1DUPd8wb_fixed |
| 19664 | CEFBS_HasNEON, // VLD1DUPd8wb_register |
| 19665 | CEFBS_HasNEON, // VLD1DUPq16 |
| 19666 | CEFBS_HasNEON, // VLD1DUPq16wb_fixed |
| 19667 | CEFBS_HasNEON, // VLD1DUPq16wb_register |
| 19668 | CEFBS_HasNEON, // VLD1DUPq32 |
| 19669 | CEFBS_HasNEON, // VLD1DUPq32wb_fixed |
| 19670 | CEFBS_HasNEON, // VLD1DUPq32wb_register |
| 19671 | CEFBS_HasNEON, // VLD1DUPq8 |
| 19672 | CEFBS_HasNEON, // VLD1DUPq8wb_fixed |
| 19673 | CEFBS_HasNEON, // VLD1DUPq8wb_register |
| 19674 | CEFBS_HasNEON, // VLD1LNd16 |
| 19675 | CEFBS_HasNEON, // VLD1LNd16_UPD |
| 19676 | CEFBS_HasNEON, // VLD1LNd32 |
| 19677 | CEFBS_HasNEON, // VLD1LNd32_UPD |
| 19678 | CEFBS_HasNEON, // VLD1LNd8 |
| 19679 | CEFBS_HasNEON, // VLD1LNd8_UPD |
| 19680 | CEFBS_HasNEON, // VLD1LNq16Pseudo |
| 19681 | CEFBS_HasNEON, // VLD1LNq16Pseudo_UPD |
| 19682 | CEFBS_HasNEON, // VLD1LNq32Pseudo |
| 19683 | CEFBS_HasNEON, // VLD1LNq32Pseudo_UPD |
| 19684 | CEFBS_HasNEON, // VLD1LNq8Pseudo |
| 19685 | CEFBS_HasNEON, // VLD1LNq8Pseudo_UPD |
| 19686 | CEFBS_HasNEON, // VLD1d16 |
| 19687 | CEFBS_HasNEON, // VLD1d16Q |
| 19688 | CEFBS_HasNEON, // VLD1d16QPseudo |
| 19689 | CEFBS_HasNEON, // VLD1d16QPseudoWB_fixed |
| 19690 | CEFBS_HasNEON, // VLD1d16QPseudoWB_register |
| 19691 | CEFBS_HasNEON, // VLD1d16Qwb_fixed |
| 19692 | CEFBS_HasNEON, // VLD1d16Qwb_register |
| 19693 | CEFBS_HasNEON, // VLD1d16T |
| 19694 | CEFBS_HasNEON, // VLD1d16TPseudo |
| 19695 | CEFBS_HasNEON, // VLD1d16TPseudoWB_fixed |
| 19696 | CEFBS_HasNEON, // VLD1d16TPseudoWB_register |
| 19697 | CEFBS_HasNEON, // VLD1d16Twb_fixed |
| 19698 | CEFBS_HasNEON, // VLD1d16Twb_register |
| 19699 | CEFBS_HasNEON, // VLD1d16wb_fixed |
| 19700 | CEFBS_HasNEON, // VLD1d16wb_register |
| 19701 | CEFBS_HasNEON, // VLD1d32 |
| 19702 | CEFBS_HasNEON, // VLD1d32Q |
| 19703 | CEFBS_HasNEON, // VLD1d32QPseudo |
| 19704 | CEFBS_HasNEON, // VLD1d32QPseudoWB_fixed |
| 19705 | CEFBS_HasNEON, // VLD1d32QPseudoWB_register |
| 19706 | CEFBS_HasNEON, // VLD1d32Qwb_fixed |
| 19707 | CEFBS_HasNEON, // VLD1d32Qwb_register |
| 19708 | CEFBS_HasNEON, // VLD1d32T |
| 19709 | CEFBS_HasNEON, // VLD1d32TPseudo |
| 19710 | CEFBS_HasNEON, // VLD1d32TPseudoWB_fixed |
| 19711 | CEFBS_HasNEON, // VLD1d32TPseudoWB_register |
| 19712 | CEFBS_HasNEON, // VLD1d32Twb_fixed |
| 19713 | CEFBS_HasNEON, // VLD1d32Twb_register |
| 19714 | CEFBS_HasNEON, // VLD1d32wb_fixed |
| 19715 | CEFBS_HasNEON, // VLD1d32wb_register |
| 19716 | CEFBS_HasNEON, // VLD1d64 |
| 19717 | CEFBS_HasNEON, // VLD1d64Q |
| 19718 | CEFBS_HasNEON, // VLD1d64QPseudo |
| 19719 | CEFBS_HasNEON, // VLD1d64QPseudoWB_fixed |
| 19720 | CEFBS_HasNEON, // VLD1d64QPseudoWB_register |
| 19721 | CEFBS_HasNEON, // VLD1d64Qwb_fixed |
| 19722 | CEFBS_HasNEON, // VLD1d64Qwb_register |
| 19723 | CEFBS_HasNEON, // VLD1d64T |
| 19724 | CEFBS_HasNEON, // VLD1d64TPseudo |
| 19725 | CEFBS_HasNEON, // VLD1d64TPseudoWB_fixed |
| 19726 | CEFBS_HasNEON, // VLD1d64TPseudoWB_register |
| 19727 | CEFBS_HasNEON, // VLD1d64Twb_fixed |
| 19728 | CEFBS_HasNEON, // VLD1d64Twb_register |
| 19729 | CEFBS_HasNEON, // VLD1d64wb_fixed |
| 19730 | CEFBS_HasNEON, // VLD1d64wb_register |
| 19731 | CEFBS_HasNEON, // VLD1d8 |
| 19732 | CEFBS_HasNEON, // VLD1d8Q |
| 19733 | CEFBS_HasNEON, // VLD1d8QPseudo |
| 19734 | CEFBS_HasNEON, // VLD1d8QPseudoWB_fixed |
| 19735 | CEFBS_HasNEON, // VLD1d8QPseudoWB_register |
| 19736 | CEFBS_HasNEON, // VLD1d8Qwb_fixed |
| 19737 | CEFBS_HasNEON, // VLD1d8Qwb_register |
| 19738 | CEFBS_HasNEON, // VLD1d8T |
| 19739 | CEFBS_HasNEON, // VLD1d8TPseudo |
| 19740 | CEFBS_HasNEON, // VLD1d8TPseudoWB_fixed |
| 19741 | CEFBS_HasNEON, // VLD1d8TPseudoWB_register |
| 19742 | CEFBS_HasNEON, // VLD1d8Twb_fixed |
| 19743 | CEFBS_HasNEON, // VLD1d8Twb_register |
| 19744 | CEFBS_HasNEON, // VLD1d8wb_fixed |
| 19745 | CEFBS_HasNEON, // VLD1d8wb_register |
| 19746 | CEFBS_HasNEON, // VLD1q16 |
| 19747 | CEFBS_HasNEON, // VLD1q16HighQPseudo |
| 19748 | CEFBS_HasNEON, // VLD1q16HighQPseudo_UPD |
| 19749 | CEFBS_HasNEON, // VLD1q16HighTPseudo |
| 19750 | CEFBS_HasNEON, // VLD1q16HighTPseudo_UPD |
| 19751 | CEFBS_HasNEON, // VLD1q16LowQPseudo_UPD |
| 19752 | CEFBS_HasNEON, // VLD1q16LowTPseudo_UPD |
| 19753 | CEFBS_HasNEON, // VLD1q16wb_fixed |
| 19754 | CEFBS_HasNEON, // VLD1q16wb_register |
| 19755 | CEFBS_HasNEON, // VLD1q32 |
| 19756 | CEFBS_HasNEON, // VLD1q32HighQPseudo |
| 19757 | CEFBS_HasNEON, // VLD1q32HighQPseudo_UPD |
| 19758 | CEFBS_HasNEON, // VLD1q32HighTPseudo |
| 19759 | CEFBS_HasNEON, // VLD1q32HighTPseudo_UPD |
| 19760 | CEFBS_HasNEON, // VLD1q32LowQPseudo_UPD |
| 19761 | CEFBS_HasNEON, // VLD1q32LowTPseudo_UPD |
| 19762 | CEFBS_HasNEON, // VLD1q32wb_fixed |
| 19763 | CEFBS_HasNEON, // VLD1q32wb_register |
| 19764 | CEFBS_HasNEON, // VLD1q64 |
| 19765 | CEFBS_HasNEON, // VLD1q64HighQPseudo |
| 19766 | CEFBS_HasNEON, // VLD1q64HighQPseudo_UPD |
| 19767 | CEFBS_HasNEON, // VLD1q64HighTPseudo |
| 19768 | CEFBS_HasNEON, // VLD1q64HighTPseudo_UPD |
| 19769 | CEFBS_HasNEON, // VLD1q64LowQPseudo_UPD |
| 19770 | CEFBS_HasNEON, // VLD1q64LowTPseudo_UPD |
| 19771 | CEFBS_HasNEON, // VLD1q64wb_fixed |
| 19772 | CEFBS_HasNEON, // VLD1q64wb_register |
| 19773 | CEFBS_HasNEON, // VLD1q8 |
| 19774 | CEFBS_HasNEON, // VLD1q8HighQPseudo |
| 19775 | CEFBS_HasNEON, // VLD1q8HighQPseudo_UPD |
| 19776 | CEFBS_HasNEON, // VLD1q8HighTPseudo |
| 19777 | CEFBS_HasNEON, // VLD1q8HighTPseudo_UPD |
| 19778 | CEFBS_HasNEON, // VLD1q8LowQPseudo_UPD |
| 19779 | CEFBS_HasNEON, // VLD1q8LowTPseudo_UPD |
| 19780 | CEFBS_HasNEON, // VLD1q8wb_fixed |
| 19781 | CEFBS_HasNEON, // VLD1q8wb_register |
| 19782 | CEFBS_HasNEON, // VLD2DUPd16 |
| 19783 | CEFBS_HasNEON, // VLD2DUPd16wb_fixed |
| 19784 | CEFBS_HasNEON, // VLD2DUPd16wb_register |
| 19785 | CEFBS_HasNEON, // VLD2DUPd16x2 |
| 19786 | CEFBS_HasNEON, // VLD2DUPd16x2wb_fixed |
| 19787 | CEFBS_HasNEON, // VLD2DUPd16x2wb_register |
| 19788 | CEFBS_HasNEON, // VLD2DUPd32 |
| 19789 | CEFBS_HasNEON, // VLD2DUPd32wb_fixed |
| 19790 | CEFBS_HasNEON, // VLD2DUPd32wb_register |
| 19791 | CEFBS_HasNEON, // VLD2DUPd32x2 |
| 19792 | CEFBS_HasNEON, // VLD2DUPd32x2wb_fixed |
| 19793 | CEFBS_HasNEON, // VLD2DUPd32x2wb_register |
| 19794 | CEFBS_HasNEON, // VLD2DUPd8 |
| 19795 | CEFBS_HasNEON, // VLD2DUPd8wb_fixed |
| 19796 | CEFBS_HasNEON, // VLD2DUPd8wb_register |
| 19797 | CEFBS_HasNEON, // VLD2DUPd8x2 |
| 19798 | CEFBS_HasNEON, // VLD2DUPd8x2wb_fixed |
| 19799 | CEFBS_HasNEON, // VLD2DUPd8x2wb_register |
| 19800 | CEFBS_HasNEON, // VLD2DUPq16EvenPseudo |
| 19801 | CEFBS_HasNEON, // VLD2DUPq16OddPseudo |
| 19802 | CEFBS_HasNEON, // VLD2DUPq16OddPseudoWB_fixed |
| 19803 | CEFBS_HasNEON, // VLD2DUPq16OddPseudoWB_register |
| 19804 | CEFBS_HasNEON, // VLD2DUPq32EvenPseudo |
| 19805 | CEFBS_HasNEON, // VLD2DUPq32OddPseudo |
| 19806 | CEFBS_HasNEON, // VLD2DUPq32OddPseudoWB_fixed |
| 19807 | CEFBS_HasNEON, // VLD2DUPq32OddPseudoWB_register |
| 19808 | CEFBS_HasNEON, // VLD2DUPq8EvenPseudo |
| 19809 | CEFBS_HasNEON, // VLD2DUPq8OddPseudo |
| 19810 | CEFBS_HasNEON, // VLD2DUPq8OddPseudoWB_fixed |
| 19811 | CEFBS_HasNEON, // VLD2DUPq8OddPseudoWB_register |
| 19812 | CEFBS_HasNEON, // VLD2LNd16 |
| 19813 | CEFBS_HasNEON, // VLD2LNd16Pseudo |
| 19814 | CEFBS_HasNEON, // VLD2LNd16Pseudo_UPD |
| 19815 | CEFBS_HasNEON, // VLD2LNd16_UPD |
| 19816 | CEFBS_HasNEON, // VLD2LNd32 |
| 19817 | CEFBS_HasNEON, // VLD2LNd32Pseudo |
| 19818 | CEFBS_HasNEON, // VLD2LNd32Pseudo_UPD |
| 19819 | CEFBS_HasNEON, // VLD2LNd32_UPD |
| 19820 | CEFBS_HasNEON, // VLD2LNd8 |
| 19821 | CEFBS_HasNEON, // VLD2LNd8Pseudo |
| 19822 | CEFBS_HasNEON, // VLD2LNd8Pseudo_UPD |
| 19823 | CEFBS_HasNEON, // VLD2LNd8_UPD |
| 19824 | CEFBS_HasNEON, // VLD2LNq16 |
| 19825 | CEFBS_HasNEON, // VLD2LNq16Pseudo |
| 19826 | CEFBS_HasNEON, // VLD2LNq16Pseudo_UPD |
| 19827 | CEFBS_HasNEON, // VLD2LNq16_UPD |
| 19828 | CEFBS_HasNEON, // VLD2LNq32 |
| 19829 | CEFBS_HasNEON, // VLD2LNq32Pseudo |
| 19830 | CEFBS_HasNEON, // VLD2LNq32Pseudo_UPD |
| 19831 | CEFBS_HasNEON, // VLD2LNq32_UPD |
| 19832 | CEFBS_HasNEON, // VLD2b16 |
| 19833 | CEFBS_HasNEON, // VLD2b16wb_fixed |
| 19834 | CEFBS_HasNEON, // VLD2b16wb_register |
| 19835 | CEFBS_HasNEON, // VLD2b32 |
| 19836 | CEFBS_HasNEON, // VLD2b32wb_fixed |
| 19837 | CEFBS_HasNEON, // VLD2b32wb_register |
| 19838 | CEFBS_HasNEON, // VLD2b8 |
| 19839 | CEFBS_HasNEON, // VLD2b8wb_fixed |
| 19840 | CEFBS_HasNEON, // VLD2b8wb_register |
| 19841 | CEFBS_HasNEON, // VLD2d16 |
| 19842 | CEFBS_HasNEON, // VLD2d16wb_fixed |
| 19843 | CEFBS_HasNEON, // VLD2d16wb_register |
| 19844 | CEFBS_HasNEON, // VLD2d32 |
| 19845 | CEFBS_HasNEON, // VLD2d32wb_fixed |
| 19846 | CEFBS_HasNEON, // VLD2d32wb_register |
| 19847 | CEFBS_HasNEON, // VLD2d8 |
| 19848 | CEFBS_HasNEON, // VLD2d8wb_fixed |
| 19849 | CEFBS_HasNEON, // VLD2d8wb_register |
| 19850 | CEFBS_HasNEON, // VLD2q16 |
| 19851 | CEFBS_HasNEON, // VLD2q16Pseudo |
| 19852 | CEFBS_HasNEON, // VLD2q16PseudoWB_fixed |
| 19853 | CEFBS_HasNEON, // VLD2q16PseudoWB_register |
| 19854 | CEFBS_HasNEON, // VLD2q16wb_fixed |
| 19855 | CEFBS_HasNEON, // VLD2q16wb_register |
| 19856 | CEFBS_HasNEON, // VLD2q32 |
| 19857 | CEFBS_HasNEON, // VLD2q32Pseudo |
| 19858 | CEFBS_HasNEON, // VLD2q32PseudoWB_fixed |
| 19859 | CEFBS_HasNEON, // VLD2q32PseudoWB_register |
| 19860 | CEFBS_HasNEON, // VLD2q32wb_fixed |
| 19861 | CEFBS_HasNEON, // VLD2q32wb_register |
| 19862 | CEFBS_HasNEON, // VLD2q8 |
| 19863 | CEFBS_HasNEON, // VLD2q8Pseudo |
| 19864 | CEFBS_HasNEON, // VLD2q8PseudoWB_fixed |
| 19865 | CEFBS_HasNEON, // VLD2q8PseudoWB_register |
| 19866 | CEFBS_HasNEON, // VLD2q8wb_fixed |
| 19867 | CEFBS_HasNEON, // VLD2q8wb_register |
| 19868 | CEFBS_HasNEON, // VLD3DUPd16 |
| 19869 | CEFBS_HasNEON, // VLD3DUPd16Pseudo |
| 19870 | CEFBS_HasNEON, // VLD3DUPd16Pseudo_UPD |
| 19871 | CEFBS_HasNEON, // VLD3DUPd16_UPD |
| 19872 | CEFBS_HasNEON, // VLD3DUPd32 |
| 19873 | CEFBS_HasNEON, // VLD3DUPd32Pseudo |
| 19874 | CEFBS_HasNEON, // VLD3DUPd32Pseudo_UPD |
| 19875 | CEFBS_HasNEON, // VLD3DUPd32_UPD |
| 19876 | CEFBS_HasNEON, // VLD3DUPd8 |
| 19877 | CEFBS_HasNEON, // VLD3DUPd8Pseudo |
| 19878 | CEFBS_HasNEON, // VLD3DUPd8Pseudo_UPD |
| 19879 | CEFBS_HasNEON, // VLD3DUPd8_UPD |
| 19880 | CEFBS_HasNEON, // VLD3DUPq16 |
| 19881 | CEFBS_HasNEON, // VLD3DUPq16EvenPseudo |
| 19882 | CEFBS_HasNEON, // VLD3DUPq16OddPseudo |
| 19883 | CEFBS_HasNEON, // VLD3DUPq16OddPseudo_UPD |
| 19884 | CEFBS_HasNEON, // VLD3DUPq16_UPD |
| 19885 | CEFBS_HasNEON, // VLD3DUPq32 |
| 19886 | CEFBS_HasNEON, // VLD3DUPq32EvenPseudo |
| 19887 | CEFBS_HasNEON, // VLD3DUPq32OddPseudo |
| 19888 | CEFBS_HasNEON, // VLD3DUPq32OddPseudo_UPD |
| 19889 | CEFBS_HasNEON, // VLD3DUPq32_UPD |
| 19890 | CEFBS_HasNEON, // VLD3DUPq8 |
| 19891 | CEFBS_HasNEON, // VLD3DUPq8EvenPseudo |
| 19892 | CEFBS_HasNEON, // VLD3DUPq8OddPseudo |
| 19893 | CEFBS_HasNEON, // VLD3DUPq8OddPseudo_UPD |
| 19894 | CEFBS_HasNEON, // VLD3DUPq8_UPD |
| 19895 | CEFBS_HasNEON, // VLD3LNd16 |
| 19896 | CEFBS_HasNEON, // VLD3LNd16Pseudo |
| 19897 | CEFBS_HasNEON, // VLD3LNd16Pseudo_UPD |
| 19898 | CEFBS_HasNEON, // VLD3LNd16_UPD |
| 19899 | CEFBS_HasNEON, // VLD3LNd32 |
| 19900 | CEFBS_HasNEON, // VLD3LNd32Pseudo |
| 19901 | CEFBS_HasNEON, // VLD3LNd32Pseudo_UPD |
| 19902 | CEFBS_HasNEON, // VLD3LNd32_UPD |
| 19903 | CEFBS_HasNEON, // VLD3LNd8 |
| 19904 | CEFBS_HasNEON, // VLD3LNd8Pseudo |
| 19905 | CEFBS_HasNEON, // VLD3LNd8Pseudo_UPD |
| 19906 | CEFBS_HasNEON, // VLD3LNd8_UPD |
| 19907 | CEFBS_HasNEON, // VLD3LNq16 |
| 19908 | CEFBS_HasNEON, // VLD3LNq16Pseudo |
| 19909 | CEFBS_HasNEON, // VLD3LNq16Pseudo_UPD |
| 19910 | CEFBS_HasNEON, // VLD3LNq16_UPD |
| 19911 | CEFBS_HasNEON, // VLD3LNq32 |
| 19912 | CEFBS_HasNEON, // VLD3LNq32Pseudo |
| 19913 | CEFBS_HasNEON, // VLD3LNq32Pseudo_UPD |
| 19914 | CEFBS_HasNEON, // VLD3LNq32_UPD |
| 19915 | CEFBS_HasNEON, // VLD3d16 |
| 19916 | CEFBS_HasNEON, // VLD3d16Pseudo |
| 19917 | CEFBS_HasNEON, // VLD3d16Pseudo_UPD |
| 19918 | CEFBS_HasNEON, // VLD3d16_UPD |
| 19919 | CEFBS_HasNEON, // VLD3d32 |
| 19920 | CEFBS_HasNEON, // VLD3d32Pseudo |
| 19921 | CEFBS_HasNEON, // VLD3d32Pseudo_UPD |
| 19922 | CEFBS_HasNEON, // VLD3d32_UPD |
| 19923 | CEFBS_HasNEON, // VLD3d8 |
| 19924 | CEFBS_HasNEON, // VLD3d8Pseudo |
| 19925 | CEFBS_HasNEON, // VLD3d8Pseudo_UPD |
| 19926 | CEFBS_HasNEON, // VLD3d8_UPD |
| 19927 | CEFBS_HasNEON, // VLD3q16 |
| 19928 | CEFBS_HasNEON, // VLD3q16Pseudo_UPD |
| 19929 | CEFBS_HasNEON, // VLD3q16_UPD |
| 19930 | CEFBS_HasNEON, // VLD3q16oddPseudo |
| 19931 | CEFBS_HasNEON, // VLD3q16oddPseudo_UPD |
| 19932 | CEFBS_HasNEON, // VLD3q32 |
| 19933 | CEFBS_HasNEON, // VLD3q32Pseudo_UPD |
| 19934 | CEFBS_HasNEON, // VLD3q32_UPD |
| 19935 | CEFBS_HasNEON, // VLD3q32oddPseudo |
| 19936 | CEFBS_HasNEON, // VLD3q32oddPseudo_UPD |
| 19937 | CEFBS_HasNEON, // VLD3q8 |
| 19938 | CEFBS_HasNEON, // VLD3q8Pseudo_UPD |
| 19939 | CEFBS_HasNEON, // VLD3q8_UPD |
| 19940 | CEFBS_HasNEON, // VLD3q8oddPseudo |
| 19941 | CEFBS_HasNEON, // VLD3q8oddPseudo_UPD |
| 19942 | CEFBS_HasNEON, // VLD4DUPd16 |
| 19943 | CEFBS_HasNEON, // VLD4DUPd16Pseudo |
| 19944 | CEFBS_HasNEON, // VLD4DUPd16Pseudo_UPD |
| 19945 | CEFBS_HasNEON, // VLD4DUPd16_UPD |
| 19946 | CEFBS_HasNEON, // VLD4DUPd32 |
| 19947 | CEFBS_HasNEON, // VLD4DUPd32Pseudo |
| 19948 | CEFBS_HasNEON, // VLD4DUPd32Pseudo_UPD |
| 19949 | CEFBS_HasNEON, // VLD4DUPd32_UPD |
| 19950 | CEFBS_HasNEON, // VLD4DUPd8 |
| 19951 | CEFBS_HasNEON, // VLD4DUPd8Pseudo |
| 19952 | CEFBS_HasNEON, // VLD4DUPd8Pseudo_UPD |
| 19953 | CEFBS_HasNEON, // VLD4DUPd8_UPD |
| 19954 | CEFBS_HasNEON, // VLD4DUPq16 |
| 19955 | CEFBS_HasNEON, // VLD4DUPq16EvenPseudo |
| 19956 | CEFBS_HasNEON, // VLD4DUPq16OddPseudo |
| 19957 | CEFBS_HasNEON, // VLD4DUPq16OddPseudo_UPD |
| 19958 | CEFBS_HasNEON, // VLD4DUPq16_UPD |
| 19959 | CEFBS_HasNEON, // VLD4DUPq32 |
| 19960 | CEFBS_HasNEON, // VLD4DUPq32EvenPseudo |
| 19961 | CEFBS_HasNEON, // VLD4DUPq32OddPseudo |
| 19962 | CEFBS_HasNEON, // VLD4DUPq32OddPseudo_UPD |
| 19963 | CEFBS_HasNEON, // VLD4DUPq32_UPD |
| 19964 | CEFBS_HasNEON, // VLD4DUPq8 |
| 19965 | CEFBS_HasNEON, // VLD4DUPq8EvenPseudo |
| 19966 | CEFBS_HasNEON, // VLD4DUPq8OddPseudo |
| 19967 | CEFBS_HasNEON, // VLD4DUPq8OddPseudo_UPD |
| 19968 | CEFBS_HasNEON, // VLD4DUPq8_UPD |
| 19969 | CEFBS_HasNEON, // VLD4LNd16 |
| 19970 | CEFBS_HasNEON, // VLD4LNd16Pseudo |
| 19971 | CEFBS_HasNEON, // VLD4LNd16Pseudo_UPD |
| 19972 | CEFBS_HasNEON, // VLD4LNd16_UPD |
| 19973 | CEFBS_HasNEON, // VLD4LNd32 |
| 19974 | CEFBS_HasNEON, // VLD4LNd32Pseudo |
| 19975 | CEFBS_HasNEON, // VLD4LNd32Pseudo_UPD |
| 19976 | CEFBS_HasNEON, // VLD4LNd32_UPD |
| 19977 | CEFBS_HasNEON, // VLD4LNd8 |
| 19978 | CEFBS_HasNEON, // VLD4LNd8Pseudo |
| 19979 | CEFBS_HasNEON, // VLD4LNd8Pseudo_UPD |
| 19980 | CEFBS_HasNEON, // VLD4LNd8_UPD |
| 19981 | CEFBS_HasNEON, // VLD4LNq16 |
| 19982 | CEFBS_HasNEON, // VLD4LNq16Pseudo |
| 19983 | CEFBS_HasNEON, // VLD4LNq16Pseudo_UPD |
| 19984 | CEFBS_HasNEON, // VLD4LNq16_UPD |
| 19985 | CEFBS_HasNEON, // VLD4LNq32 |
| 19986 | CEFBS_HasNEON, // VLD4LNq32Pseudo |
| 19987 | CEFBS_HasNEON, // VLD4LNq32Pseudo_UPD |
| 19988 | CEFBS_HasNEON, // VLD4LNq32_UPD |
| 19989 | CEFBS_HasNEON, // VLD4d16 |
| 19990 | CEFBS_HasNEON, // VLD4d16Pseudo |
| 19991 | CEFBS_HasNEON, // VLD4d16Pseudo_UPD |
| 19992 | CEFBS_HasNEON, // VLD4d16_UPD |
| 19993 | CEFBS_HasNEON, // VLD4d32 |
| 19994 | CEFBS_HasNEON, // VLD4d32Pseudo |
| 19995 | CEFBS_HasNEON, // VLD4d32Pseudo_UPD |
| 19996 | CEFBS_HasNEON, // VLD4d32_UPD |
| 19997 | CEFBS_HasNEON, // VLD4d8 |
| 19998 | CEFBS_HasNEON, // VLD4d8Pseudo |
| 19999 | CEFBS_HasNEON, // VLD4d8Pseudo_UPD |
| 20000 | CEFBS_HasNEON, // VLD4d8_UPD |
| 20001 | CEFBS_HasNEON, // VLD4q16 |
| 20002 | CEFBS_HasNEON, // VLD4q16Pseudo_UPD |
| 20003 | CEFBS_HasNEON, // VLD4q16_UPD |
| 20004 | CEFBS_HasNEON, // VLD4q16oddPseudo |
| 20005 | CEFBS_HasNEON, // VLD4q16oddPseudo_UPD |
| 20006 | CEFBS_HasNEON, // VLD4q32 |
| 20007 | CEFBS_HasNEON, // VLD4q32Pseudo_UPD |
| 20008 | CEFBS_HasNEON, // VLD4q32_UPD |
| 20009 | CEFBS_HasNEON, // VLD4q32oddPseudo |
| 20010 | CEFBS_HasNEON, // VLD4q32oddPseudo_UPD |
| 20011 | CEFBS_HasNEON, // VLD4q8 |
| 20012 | CEFBS_HasNEON, // VLD4q8Pseudo_UPD |
| 20013 | CEFBS_HasNEON, // VLD4q8_UPD |
| 20014 | CEFBS_HasNEON, // VLD4q8oddPseudo |
| 20015 | CEFBS_HasNEON, // VLD4q8oddPseudo_UPD |
| 20016 | CEFBS_HasFPRegs, // VLDMDDB_UPD |
| 20017 | CEFBS_HasFPRegs, // VLDMDIA |
| 20018 | CEFBS_HasFPRegs, // VLDMDIA_UPD |
| 20019 | CEFBS_HasVFP2, // VLDMQIA |
| 20020 | CEFBS_HasFPRegs, // VLDMSDB_UPD |
| 20021 | CEFBS_HasFPRegs, // VLDMSIA |
| 20022 | CEFBS_HasFPRegs, // VLDMSIA_UPD |
| 20023 | CEFBS_HasFPRegs, // VLDRD |
| 20024 | CEFBS_HasFPRegs16, // VLDRH |
| 20025 | CEFBS_HasFPRegs, // VLDRS |
| 20026 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_off |
| 20027 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_post |
| 20028 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTNS_pre |
| 20029 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_off |
| 20030 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_post |
| 20031 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLDR_FPCXTS_pre |
| 20032 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_off |
| 20033 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_post |
| 20034 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_NZCVQC_pre |
| 20035 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_off |
| 20036 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_post |
| 20037 | CEFBS_HasFPRegs_HasV8_1MMainline, // VLDR_FPSCR_pre |
| 20038 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_off |
| 20039 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_post |
| 20040 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_P0_pre |
| 20041 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_off |
| 20042 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_post |
| 20043 | CEFBS_HasV8_1MMainline_HasMVEInt, // VLDR_VPR_pre |
| 20044 | CEFBS_HasV8MMainline_Has8MSecExt, // VLLDM |
| 20045 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLLDM_T2 |
| 20046 | CEFBS_HasV8MMainline_Has8MSecExt, // VLSTM |
| 20047 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VLSTM_T2 |
| 20048 | CEFBS_HasNEON, // VMAXfd |
| 20049 | CEFBS_HasNEON, // VMAXfq |
| 20050 | CEFBS_HasNEON_HasFullFP16, // VMAXhd |
| 20051 | CEFBS_HasNEON_HasFullFP16, // VMAXhq |
| 20052 | CEFBS_HasNEON, // VMAXsv16i8 |
| 20053 | CEFBS_HasNEON, // VMAXsv2i32 |
| 20054 | CEFBS_HasNEON, // VMAXsv4i16 |
| 20055 | CEFBS_HasNEON, // VMAXsv4i32 |
| 20056 | CEFBS_HasNEON, // VMAXsv8i16 |
| 20057 | CEFBS_HasNEON, // VMAXsv8i8 |
| 20058 | CEFBS_HasNEON, // VMAXuv16i8 |
| 20059 | CEFBS_HasNEON, // VMAXuv2i32 |
| 20060 | CEFBS_HasNEON, // VMAXuv4i16 |
| 20061 | CEFBS_HasNEON, // VMAXuv4i32 |
| 20062 | CEFBS_HasNEON, // VMAXuv8i16 |
| 20063 | CEFBS_HasNEON, // VMAXuv8i8 |
| 20064 | CEFBS_HasNEON, // VMINfd |
| 20065 | CEFBS_HasNEON, // VMINfq |
| 20066 | CEFBS_HasNEON_HasFullFP16, // VMINhd |
| 20067 | CEFBS_HasNEON_HasFullFP16, // VMINhq |
| 20068 | CEFBS_HasNEON, // VMINsv16i8 |
| 20069 | CEFBS_HasNEON, // VMINsv2i32 |
| 20070 | CEFBS_HasNEON, // VMINsv4i16 |
| 20071 | CEFBS_HasNEON, // VMINsv4i32 |
| 20072 | CEFBS_HasNEON, // VMINsv8i16 |
| 20073 | CEFBS_HasNEON, // VMINsv8i8 |
| 20074 | CEFBS_HasNEON, // VMINuv16i8 |
| 20075 | CEFBS_HasNEON, // VMINuv2i32 |
| 20076 | CEFBS_HasNEON, // VMINuv4i16 |
| 20077 | CEFBS_HasNEON, // VMINuv4i32 |
| 20078 | CEFBS_HasNEON, // VMINuv8i16 |
| 20079 | CEFBS_HasNEON, // VMINuv8i8 |
| 20080 | CEFBS_HasVFP2_HasDPVFP, // VMLAD |
| 20081 | CEFBS_HasFullFP16, // VMLAH |
| 20082 | CEFBS_HasNEON, // VMLALslsv2i32 |
| 20083 | CEFBS_HasNEON, // VMLALslsv4i16 |
| 20084 | CEFBS_HasNEON, // VMLALsluv2i32 |
| 20085 | CEFBS_HasNEON, // VMLALsluv4i16 |
| 20086 | CEFBS_HasNEON, // VMLALsv2i64 |
| 20087 | CEFBS_HasNEON, // VMLALsv4i32 |
| 20088 | CEFBS_HasNEON, // VMLALsv8i16 |
| 20089 | CEFBS_HasNEON, // VMLALuv2i64 |
| 20090 | CEFBS_HasNEON, // VMLALuv4i32 |
| 20091 | CEFBS_HasNEON, // VMLALuv8i16 |
| 20092 | CEFBS_HasVFP2, // VMLAS |
| 20093 | CEFBS_HasNEON, // VMLAfd |
| 20094 | CEFBS_HasNEON, // VMLAfq |
| 20095 | CEFBS_HasNEON_HasFullFP16, // VMLAhd |
| 20096 | CEFBS_HasNEON_HasFullFP16, // VMLAhq |
| 20097 | CEFBS_HasNEON, // VMLAslfd |
| 20098 | CEFBS_HasNEON, // VMLAslfq |
| 20099 | CEFBS_HasNEON_HasFullFP16, // VMLAslhd |
| 20100 | CEFBS_HasNEON_HasFullFP16, // VMLAslhq |
| 20101 | CEFBS_HasNEON, // VMLAslv2i32 |
| 20102 | CEFBS_HasNEON, // VMLAslv4i16 |
| 20103 | CEFBS_HasNEON, // VMLAslv4i32 |
| 20104 | CEFBS_HasNEON, // VMLAslv8i16 |
| 20105 | CEFBS_HasNEON, // VMLAv16i8 |
| 20106 | CEFBS_HasNEON, // VMLAv2i32 |
| 20107 | CEFBS_HasNEON, // VMLAv4i16 |
| 20108 | CEFBS_HasNEON, // VMLAv4i32 |
| 20109 | CEFBS_HasNEON, // VMLAv8i16 |
| 20110 | CEFBS_HasNEON, // VMLAv8i8 |
| 20111 | CEFBS_HasVFP2_HasDPVFP, // VMLSD |
| 20112 | CEFBS_HasFullFP16, // VMLSH |
| 20113 | CEFBS_HasNEON, // VMLSLslsv2i32 |
| 20114 | CEFBS_HasNEON, // VMLSLslsv4i16 |
| 20115 | CEFBS_HasNEON, // VMLSLsluv2i32 |
| 20116 | CEFBS_HasNEON, // VMLSLsluv4i16 |
| 20117 | CEFBS_HasNEON, // VMLSLsv2i64 |
| 20118 | CEFBS_HasNEON, // VMLSLsv4i32 |
| 20119 | CEFBS_HasNEON, // VMLSLsv8i16 |
| 20120 | CEFBS_HasNEON, // VMLSLuv2i64 |
| 20121 | CEFBS_HasNEON, // VMLSLuv4i32 |
| 20122 | CEFBS_HasNEON, // VMLSLuv8i16 |
| 20123 | CEFBS_HasVFP2, // VMLSS |
| 20124 | CEFBS_HasNEON, // VMLSfd |
| 20125 | CEFBS_HasNEON, // VMLSfq |
| 20126 | CEFBS_HasNEON_HasFullFP16, // VMLShd |
| 20127 | CEFBS_HasNEON_HasFullFP16, // VMLShq |
| 20128 | CEFBS_HasNEON, // VMLSslfd |
| 20129 | CEFBS_HasNEON, // VMLSslfq |
| 20130 | CEFBS_HasNEON_HasFullFP16, // VMLSslhd |
| 20131 | CEFBS_HasNEON_HasFullFP16, // VMLSslhq |
| 20132 | CEFBS_HasNEON, // VMLSslv2i32 |
| 20133 | CEFBS_HasNEON, // VMLSslv4i16 |
| 20134 | CEFBS_HasNEON, // VMLSslv4i32 |
| 20135 | CEFBS_HasNEON, // VMLSslv8i16 |
| 20136 | CEFBS_HasNEON, // VMLSv16i8 |
| 20137 | CEFBS_HasNEON, // VMLSv2i32 |
| 20138 | CEFBS_HasNEON, // VMLSv4i16 |
| 20139 | CEFBS_HasNEON, // VMLSv4i32 |
| 20140 | CEFBS_HasNEON, // VMLSv8i16 |
| 20141 | CEFBS_HasNEON, // VMLSv8i8 |
| 20142 | CEFBS_HasBF16_HasNEON, // VMMLA |
| 20143 | CEFBS_HasFPRegs64, // VMOVD |
| 20144 | CEFBS_HasFPRegs, // VMOVDRR |
| 20145 | CEFBS_HasFullFP16, // VMOVH |
| 20146 | CEFBS_HasFPRegs16, // VMOVHR |
| 20147 | CEFBS_HasNEON, // VMOVLsv2i64 |
| 20148 | CEFBS_HasNEON, // VMOVLsv4i32 |
| 20149 | CEFBS_HasNEON, // VMOVLsv8i16 |
| 20150 | CEFBS_HasNEON, // VMOVLuv2i64 |
| 20151 | CEFBS_HasNEON, // VMOVLuv4i32 |
| 20152 | CEFBS_HasNEON, // VMOVLuv8i16 |
| 20153 | CEFBS_HasNEON, // VMOVNv2i32 |
| 20154 | CEFBS_HasNEON, // VMOVNv4i16 |
| 20155 | CEFBS_HasNEON, // VMOVNv8i8 |
| 20156 | CEFBS_HasFPRegs16, // VMOVRH |
| 20157 | CEFBS_HasFPRegs, // VMOVRRD |
| 20158 | CEFBS_HasFPRegs, // VMOVRRS |
| 20159 | CEFBS_HasFPRegs, // VMOVRS |
| 20160 | CEFBS_HasFPRegs, // VMOVS |
| 20161 | CEFBS_HasFPRegs, // VMOVSR |
| 20162 | CEFBS_HasFPRegs, // VMOVSRR |
| 20163 | CEFBS_HasNEON, // VMOVv16i8 |
| 20164 | CEFBS_HasNEON, // VMOVv1i64 |
| 20165 | CEFBS_HasNEON, // VMOVv2f32 |
| 20166 | CEFBS_HasNEON, // VMOVv2i32 |
| 20167 | CEFBS_HasNEON, // VMOVv2i64 |
| 20168 | CEFBS_HasNEON, // VMOVv4f32 |
| 20169 | CEFBS_HasNEON, // VMOVv4i16 |
| 20170 | CEFBS_HasNEON, // VMOVv4i32 |
| 20171 | CEFBS_HasNEON, // VMOVv8i16 |
| 20172 | CEFBS_HasNEON, // VMOVv8i8 |
| 20173 | CEFBS_HasFPRegs, // VMRS |
| 20174 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTNS |
| 20175 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMRS_FPCXTS |
| 20176 | CEFBS_HasVFP2, // VMRS_FPEXC |
| 20177 | CEFBS_HasVFP2, // VMRS_FPINST |
| 20178 | CEFBS_HasVFP2, // VMRS_FPINST2 |
| 20179 | CEFBS_HasV8_1MMainline_HasFPRegs, // VMRS_FPSCR_NZCVQC |
| 20180 | CEFBS_HasVFP2, // VMRS_FPSID |
| 20181 | CEFBS_HasVFP2, // VMRS_MVFR0 |
| 20182 | CEFBS_HasVFP2, // VMRS_MVFR1 |
| 20183 | CEFBS_HasFPARMv8, // VMRS_MVFR2 |
| 20184 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_P0 |
| 20185 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMRS_VPR |
| 20186 | CEFBS_HasFPRegs, // VMSR |
| 20187 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTNS |
| 20188 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VMSR_FPCXTS |
| 20189 | CEFBS_HasVFP2, // VMSR_FPEXC |
| 20190 | CEFBS_HasVFP2, // VMSR_FPINST |
| 20191 | CEFBS_HasVFP2, // VMSR_FPINST2 |
| 20192 | CEFBS_HasV8_1MMainline_HasFPRegs, // VMSR_FPSCR_NZCVQC |
| 20193 | CEFBS_HasVFP2, // VMSR_FPSID |
| 20194 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_P0 |
| 20195 | CEFBS_HasV8_1MMainline_HasMVEInt, // VMSR_VPR |
| 20196 | CEFBS_HasVFP2_HasDPVFP, // VMULD |
| 20197 | CEFBS_HasFullFP16, // VMULH |
| 20198 | CEFBS_HasV8_HasAES, // VMULLp64 |
| 20199 | CEFBS_HasNEON, // VMULLp8 |
| 20200 | CEFBS_HasNEON, // VMULLslsv2i32 |
| 20201 | CEFBS_HasNEON, // VMULLslsv4i16 |
| 20202 | CEFBS_HasNEON, // VMULLsluv2i32 |
| 20203 | CEFBS_HasNEON, // VMULLsluv4i16 |
| 20204 | CEFBS_HasNEON, // VMULLsv2i64 |
| 20205 | CEFBS_HasNEON, // VMULLsv4i32 |
| 20206 | CEFBS_HasNEON, // VMULLsv8i16 |
| 20207 | CEFBS_HasNEON, // VMULLuv2i64 |
| 20208 | CEFBS_HasNEON, // VMULLuv4i32 |
| 20209 | CEFBS_HasNEON, // VMULLuv8i16 |
| 20210 | CEFBS_HasVFP2, // VMULS |
| 20211 | CEFBS_HasNEON, // VMULfd |
| 20212 | CEFBS_HasNEON, // VMULfq |
| 20213 | CEFBS_HasNEON_HasFullFP16, // VMULhd |
| 20214 | CEFBS_HasNEON_HasFullFP16, // VMULhq |
| 20215 | CEFBS_HasNEON, // VMULpd |
| 20216 | CEFBS_HasNEON, // VMULpq |
| 20217 | CEFBS_HasNEON, // VMULslfd |
| 20218 | CEFBS_HasNEON, // VMULslfq |
| 20219 | CEFBS_HasNEON_HasFullFP16, // VMULslhd |
| 20220 | CEFBS_HasNEON_HasFullFP16, // VMULslhq |
| 20221 | CEFBS_HasNEON, // VMULslv2i32 |
| 20222 | CEFBS_HasNEON, // VMULslv4i16 |
| 20223 | CEFBS_HasNEON, // VMULslv4i32 |
| 20224 | CEFBS_HasNEON, // VMULslv8i16 |
| 20225 | CEFBS_HasNEON, // VMULv16i8 |
| 20226 | CEFBS_HasNEON, // VMULv2i32 |
| 20227 | CEFBS_HasNEON, // VMULv4i16 |
| 20228 | CEFBS_HasNEON, // VMULv4i32 |
| 20229 | CEFBS_HasNEON, // VMULv8i16 |
| 20230 | CEFBS_HasNEON, // VMULv8i8 |
| 20231 | CEFBS_HasNEON, // VMVNd |
| 20232 | CEFBS_HasNEON, // VMVNq |
| 20233 | CEFBS_HasNEON, // VMVNv2i32 |
| 20234 | CEFBS_HasNEON, // VMVNv4i16 |
| 20235 | CEFBS_HasNEON, // VMVNv4i32 |
| 20236 | CEFBS_HasNEON, // VMVNv8i16 |
| 20237 | CEFBS_HasVFP2_HasDPVFP, // VNEGD |
| 20238 | CEFBS_HasFullFP16, // VNEGH |
| 20239 | CEFBS_HasVFP2, // VNEGS |
| 20240 | CEFBS_HasNEON, // VNEGf32q |
| 20241 | CEFBS_HasNEON, // VNEGfd |
| 20242 | CEFBS_HasNEON_HasFullFP16, // VNEGhd |
| 20243 | CEFBS_HasNEON_HasFullFP16, // VNEGhq |
| 20244 | CEFBS_HasNEON, // VNEGs16d |
| 20245 | CEFBS_HasNEON, // VNEGs16q |
| 20246 | CEFBS_HasNEON, // VNEGs32d |
| 20247 | CEFBS_HasNEON, // VNEGs32q |
| 20248 | CEFBS_HasNEON, // VNEGs8d |
| 20249 | CEFBS_HasNEON, // VNEGs8q |
| 20250 | CEFBS_HasVFP2_HasDPVFP, // VNMLAD |
| 20251 | CEFBS_HasFullFP16, // VNMLAH |
| 20252 | CEFBS_HasVFP2, // VNMLAS |
| 20253 | CEFBS_HasVFP2_HasDPVFP, // VNMLSD |
| 20254 | CEFBS_HasFullFP16, // VNMLSH |
| 20255 | CEFBS_HasVFP2, // VNMLSS |
| 20256 | CEFBS_HasVFP2_HasDPVFP, // VNMULD |
| 20257 | CEFBS_HasFullFP16, // VNMULH |
| 20258 | CEFBS_HasVFP2, // VNMULS |
| 20259 | CEFBS_HasNEON, // VORNd |
| 20260 | CEFBS_HasNEON, // VORNq |
| 20261 | CEFBS_HasNEON, // VORRd |
| 20262 | CEFBS_HasNEON, // VORRiv2i32 |
| 20263 | CEFBS_HasNEON, // VORRiv4i16 |
| 20264 | CEFBS_HasNEON, // VORRiv4i32 |
| 20265 | CEFBS_HasNEON, // VORRiv8i16 |
| 20266 | CEFBS_HasNEON, // VORRq |
| 20267 | CEFBS_HasNEON, // VPADALsv16i8 |
| 20268 | CEFBS_HasNEON, // VPADALsv2i32 |
| 20269 | CEFBS_HasNEON, // VPADALsv4i16 |
| 20270 | CEFBS_HasNEON, // VPADALsv4i32 |
| 20271 | CEFBS_HasNEON, // VPADALsv8i16 |
| 20272 | CEFBS_HasNEON, // VPADALsv8i8 |
| 20273 | CEFBS_HasNEON, // VPADALuv16i8 |
| 20274 | CEFBS_HasNEON, // VPADALuv2i32 |
| 20275 | CEFBS_HasNEON, // VPADALuv4i16 |
| 20276 | CEFBS_HasNEON, // VPADALuv4i32 |
| 20277 | CEFBS_HasNEON, // VPADALuv8i16 |
| 20278 | CEFBS_HasNEON, // VPADALuv8i8 |
| 20279 | CEFBS_HasNEON, // VPADDLsv16i8 |
| 20280 | CEFBS_HasNEON, // VPADDLsv2i32 |
| 20281 | CEFBS_HasNEON, // VPADDLsv4i16 |
| 20282 | CEFBS_HasNEON, // VPADDLsv4i32 |
| 20283 | CEFBS_HasNEON, // VPADDLsv8i16 |
| 20284 | CEFBS_HasNEON, // VPADDLsv8i8 |
| 20285 | CEFBS_HasNEON, // VPADDLuv16i8 |
| 20286 | CEFBS_HasNEON, // VPADDLuv2i32 |
| 20287 | CEFBS_HasNEON, // VPADDLuv4i16 |
| 20288 | CEFBS_HasNEON, // VPADDLuv4i32 |
| 20289 | CEFBS_HasNEON, // VPADDLuv8i16 |
| 20290 | CEFBS_HasNEON, // VPADDLuv8i8 |
| 20291 | CEFBS_HasNEON, // VPADDf |
| 20292 | CEFBS_HasNEON_HasFullFP16, // VPADDh |
| 20293 | CEFBS_HasNEON, // VPADDi16 |
| 20294 | CEFBS_HasNEON, // VPADDi32 |
| 20295 | CEFBS_HasNEON, // VPADDi8 |
| 20296 | CEFBS_HasNEON, // VPMAXf |
| 20297 | CEFBS_HasNEON_HasFullFP16, // VPMAXh |
| 20298 | CEFBS_HasNEON, // VPMAXs16 |
| 20299 | CEFBS_HasNEON, // VPMAXs32 |
| 20300 | CEFBS_HasNEON, // VPMAXs8 |
| 20301 | CEFBS_HasNEON, // VPMAXu16 |
| 20302 | CEFBS_HasNEON, // VPMAXu32 |
| 20303 | CEFBS_HasNEON, // VPMAXu8 |
| 20304 | CEFBS_HasNEON, // VPMINf |
| 20305 | CEFBS_HasNEON_HasFullFP16, // VPMINh |
| 20306 | CEFBS_HasNEON, // VPMINs16 |
| 20307 | CEFBS_HasNEON, // VPMINs32 |
| 20308 | CEFBS_HasNEON, // VPMINs8 |
| 20309 | CEFBS_HasNEON, // VPMINu16 |
| 20310 | CEFBS_HasNEON, // VPMINu32 |
| 20311 | CEFBS_HasNEON, // VPMINu8 |
| 20312 | CEFBS_HasNEON, // VQABSv16i8 |
| 20313 | CEFBS_HasNEON, // VQABSv2i32 |
| 20314 | CEFBS_HasNEON, // VQABSv4i16 |
| 20315 | CEFBS_HasNEON, // VQABSv4i32 |
| 20316 | CEFBS_HasNEON, // VQABSv8i16 |
| 20317 | CEFBS_HasNEON, // VQABSv8i8 |
| 20318 | CEFBS_HasNEON, // VQADDsv16i8 |
| 20319 | CEFBS_HasNEON, // VQADDsv1i64 |
| 20320 | CEFBS_HasNEON, // VQADDsv2i32 |
| 20321 | CEFBS_HasNEON, // VQADDsv2i64 |
| 20322 | CEFBS_HasNEON, // VQADDsv4i16 |
| 20323 | CEFBS_HasNEON, // VQADDsv4i32 |
| 20324 | CEFBS_HasNEON, // VQADDsv8i16 |
| 20325 | CEFBS_HasNEON, // VQADDsv8i8 |
| 20326 | CEFBS_HasNEON, // VQADDuv16i8 |
| 20327 | CEFBS_HasNEON, // VQADDuv1i64 |
| 20328 | CEFBS_HasNEON, // VQADDuv2i32 |
| 20329 | CEFBS_HasNEON, // VQADDuv2i64 |
| 20330 | CEFBS_HasNEON, // VQADDuv4i16 |
| 20331 | CEFBS_HasNEON, // VQADDuv4i32 |
| 20332 | CEFBS_HasNEON, // VQADDuv8i16 |
| 20333 | CEFBS_HasNEON, // VQADDuv8i8 |
| 20334 | CEFBS_HasNEON, // VQDMLALslv2i32 |
| 20335 | CEFBS_HasNEON, // VQDMLALslv4i16 |
| 20336 | CEFBS_HasNEON, // VQDMLALv2i64 |
| 20337 | CEFBS_HasNEON, // VQDMLALv4i32 |
| 20338 | CEFBS_HasNEON, // VQDMLSLslv2i32 |
| 20339 | CEFBS_HasNEON, // VQDMLSLslv4i16 |
| 20340 | CEFBS_HasNEON, // VQDMLSLv2i64 |
| 20341 | CEFBS_HasNEON, // VQDMLSLv4i32 |
| 20342 | CEFBS_HasNEON, // VQDMULHslv2i32 |
| 20343 | CEFBS_HasNEON, // VQDMULHslv4i16 |
| 20344 | CEFBS_HasNEON, // VQDMULHslv4i32 |
| 20345 | CEFBS_HasNEON, // VQDMULHslv8i16 |
| 20346 | CEFBS_HasNEON, // VQDMULHv2i32 |
| 20347 | CEFBS_HasNEON, // VQDMULHv4i16 |
| 20348 | CEFBS_HasNEON, // VQDMULHv4i32 |
| 20349 | CEFBS_HasNEON, // VQDMULHv8i16 |
| 20350 | CEFBS_HasNEON, // VQDMULLslv2i32 |
| 20351 | CEFBS_HasNEON, // VQDMULLslv4i16 |
| 20352 | CEFBS_HasNEON, // VQDMULLv2i64 |
| 20353 | CEFBS_HasNEON, // VQDMULLv4i32 |
| 20354 | CEFBS_HasNEON, // VQMOVNsuv2i32 |
| 20355 | CEFBS_HasNEON, // VQMOVNsuv4i16 |
| 20356 | CEFBS_HasNEON, // VQMOVNsuv8i8 |
| 20357 | CEFBS_HasNEON, // VQMOVNsv2i32 |
| 20358 | CEFBS_HasNEON, // VQMOVNsv4i16 |
| 20359 | CEFBS_HasNEON, // VQMOVNsv8i8 |
| 20360 | CEFBS_HasNEON, // VQMOVNuv2i32 |
| 20361 | CEFBS_HasNEON, // VQMOVNuv4i16 |
| 20362 | CEFBS_HasNEON, // VQMOVNuv8i8 |
| 20363 | CEFBS_HasNEON, // VQNEGv16i8 |
| 20364 | CEFBS_HasNEON, // VQNEGv2i32 |
| 20365 | CEFBS_HasNEON, // VQNEGv4i16 |
| 20366 | CEFBS_HasNEON, // VQNEGv4i32 |
| 20367 | CEFBS_HasNEON, // VQNEGv8i16 |
| 20368 | CEFBS_HasNEON, // VQNEGv8i8 |
| 20369 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv2i32 |
| 20370 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i16 |
| 20371 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv4i32 |
| 20372 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHslv8i16 |
| 20373 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv2i32 |
| 20374 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i16 |
| 20375 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv4i32 |
| 20376 | CEFBS_HasNEON_HasV8_1a, // VQRDMLAHv8i16 |
| 20377 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv2i32 |
| 20378 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i16 |
| 20379 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv4i32 |
| 20380 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHslv8i16 |
| 20381 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv2i32 |
| 20382 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i16 |
| 20383 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv4i32 |
| 20384 | CEFBS_HasNEON_HasV8_1a, // VQRDMLSHv8i16 |
| 20385 | CEFBS_HasNEON, // VQRDMULHslv2i32 |
| 20386 | CEFBS_HasNEON, // VQRDMULHslv4i16 |
| 20387 | CEFBS_HasNEON, // VQRDMULHslv4i32 |
| 20388 | CEFBS_HasNEON, // VQRDMULHslv8i16 |
| 20389 | CEFBS_HasNEON, // VQRDMULHv2i32 |
| 20390 | CEFBS_HasNEON, // VQRDMULHv4i16 |
| 20391 | CEFBS_HasNEON, // VQRDMULHv4i32 |
| 20392 | CEFBS_HasNEON, // VQRDMULHv8i16 |
| 20393 | CEFBS_HasNEON, // VQRSHLsv16i8 |
| 20394 | CEFBS_HasNEON, // VQRSHLsv1i64 |
| 20395 | CEFBS_HasNEON, // VQRSHLsv2i32 |
| 20396 | CEFBS_HasNEON, // VQRSHLsv2i64 |
| 20397 | CEFBS_HasNEON, // VQRSHLsv4i16 |
| 20398 | CEFBS_HasNEON, // VQRSHLsv4i32 |
| 20399 | CEFBS_HasNEON, // VQRSHLsv8i16 |
| 20400 | CEFBS_HasNEON, // VQRSHLsv8i8 |
| 20401 | CEFBS_HasNEON, // VQRSHLuv16i8 |
| 20402 | CEFBS_HasNEON, // VQRSHLuv1i64 |
| 20403 | CEFBS_HasNEON, // VQRSHLuv2i32 |
| 20404 | CEFBS_HasNEON, // VQRSHLuv2i64 |
| 20405 | CEFBS_HasNEON, // VQRSHLuv4i16 |
| 20406 | CEFBS_HasNEON, // VQRSHLuv4i32 |
| 20407 | CEFBS_HasNEON, // VQRSHLuv8i16 |
| 20408 | CEFBS_HasNEON, // VQRSHLuv8i8 |
| 20409 | CEFBS_HasNEON, // VQRSHRNsv2i32 |
| 20410 | CEFBS_HasNEON, // VQRSHRNsv4i16 |
| 20411 | CEFBS_HasNEON, // VQRSHRNsv8i8 |
| 20412 | CEFBS_HasNEON, // VQRSHRNuv2i32 |
| 20413 | CEFBS_HasNEON, // VQRSHRNuv4i16 |
| 20414 | CEFBS_HasNEON, // VQRSHRNuv8i8 |
| 20415 | CEFBS_HasNEON, // VQRSHRUNv2i32 |
| 20416 | CEFBS_HasNEON, // VQRSHRUNv4i16 |
| 20417 | CEFBS_HasNEON, // VQRSHRUNv8i8 |
| 20418 | CEFBS_HasNEON, // VQSHLsiv16i8 |
| 20419 | CEFBS_HasNEON, // VQSHLsiv1i64 |
| 20420 | CEFBS_HasNEON, // VQSHLsiv2i32 |
| 20421 | CEFBS_HasNEON, // VQSHLsiv2i64 |
| 20422 | CEFBS_HasNEON, // VQSHLsiv4i16 |
| 20423 | CEFBS_HasNEON, // VQSHLsiv4i32 |
| 20424 | CEFBS_HasNEON, // VQSHLsiv8i16 |
| 20425 | CEFBS_HasNEON, // VQSHLsiv8i8 |
| 20426 | CEFBS_HasNEON, // VQSHLsuv16i8 |
| 20427 | CEFBS_HasNEON, // VQSHLsuv1i64 |
| 20428 | CEFBS_HasNEON, // VQSHLsuv2i32 |
| 20429 | CEFBS_HasNEON, // VQSHLsuv2i64 |
| 20430 | CEFBS_HasNEON, // VQSHLsuv4i16 |
| 20431 | CEFBS_HasNEON, // VQSHLsuv4i32 |
| 20432 | CEFBS_HasNEON, // VQSHLsuv8i16 |
| 20433 | CEFBS_HasNEON, // VQSHLsuv8i8 |
| 20434 | CEFBS_HasNEON, // VQSHLsv16i8 |
| 20435 | CEFBS_HasNEON, // VQSHLsv1i64 |
| 20436 | CEFBS_HasNEON, // VQSHLsv2i32 |
| 20437 | CEFBS_HasNEON, // VQSHLsv2i64 |
| 20438 | CEFBS_HasNEON, // VQSHLsv4i16 |
| 20439 | CEFBS_HasNEON, // VQSHLsv4i32 |
| 20440 | CEFBS_HasNEON, // VQSHLsv8i16 |
| 20441 | CEFBS_HasNEON, // VQSHLsv8i8 |
| 20442 | CEFBS_HasNEON, // VQSHLuiv16i8 |
| 20443 | CEFBS_HasNEON, // VQSHLuiv1i64 |
| 20444 | CEFBS_HasNEON, // VQSHLuiv2i32 |
| 20445 | CEFBS_HasNEON, // VQSHLuiv2i64 |
| 20446 | CEFBS_HasNEON, // VQSHLuiv4i16 |
| 20447 | CEFBS_HasNEON, // VQSHLuiv4i32 |
| 20448 | CEFBS_HasNEON, // VQSHLuiv8i16 |
| 20449 | CEFBS_HasNEON, // VQSHLuiv8i8 |
| 20450 | CEFBS_HasNEON, // VQSHLuv16i8 |
| 20451 | CEFBS_HasNEON, // VQSHLuv1i64 |
| 20452 | CEFBS_HasNEON, // VQSHLuv2i32 |
| 20453 | CEFBS_HasNEON, // VQSHLuv2i64 |
| 20454 | CEFBS_HasNEON, // VQSHLuv4i16 |
| 20455 | CEFBS_HasNEON, // VQSHLuv4i32 |
| 20456 | CEFBS_HasNEON, // VQSHLuv8i16 |
| 20457 | CEFBS_HasNEON, // VQSHLuv8i8 |
| 20458 | CEFBS_HasNEON, // VQSHRNsv2i32 |
| 20459 | CEFBS_HasNEON, // VQSHRNsv4i16 |
| 20460 | CEFBS_HasNEON, // VQSHRNsv8i8 |
| 20461 | CEFBS_HasNEON, // VQSHRNuv2i32 |
| 20462 | CEFBS_HasNEON, // VQSHRNuv4i16 |
| 20463 | CEFBS_HasNEON, // VQSHRNuv8i8 |
| 20464 | CEFBS_HasNEON, // VQSHRUNv2i32 |
| 20465 | CEFBS_HasNEON, // VQSHRUNv4i16 |
| 20466 | CEFBS_HasNEON, // VQSHRUNv8i8 |
| 20467 | CEFBS_HasNEON, // VQSUBsv16i8 |
| 20468 | CEFBS_HasNEON, // VQSUBsv1i64 |
| 20469 | CEFBS_HasNEON, // VQSUBsv2i32 |
| 20470 | CEFBS_HasNEON, // VQSUBsv2i64 |
| 20471 | CEFBS_HasNEON, // VQSUBsv4i16 |
| 20472 | CEFBS_HasNEON, // VQSUBsv4i32 |
| 20473 | CEFBS_HasNEON, // VQSUBsv8i16 |
| 20474 | CEFBS_HasNEON, // VQSUBsv8i8 |
| 20475 | CEFBS_HasNEON, // VQSUBuv16i8 |
| 20476 | CEFBS_HasNEON, // VQSUBuv1i64 |
| 20477 | CEFBS_HasNEON, // VQSUBuv2i32 |
| 20478 | CEFBS_HasNEON, // VQSUBuv2i64 |
| 20479 | CEFBS_HasNEON, // VQSUBuv4i16 |
| 20480 | CEFBS_HasNEON, // VQSUBuv4i32 |
| 20481 | CEFBS_HasNEON, // VQSUBuv8i16 |
| 20482 | CEFBS_HasNEON, // VQSUBuv8i8 |
| 20483 | CEFBS_HasNEON, // VRADDHNv2i32 |
| 20484 | CEFBS_HasNEON, // VRADDHNv4i16 |
| 20485 | CEFBS_HasNEON, // VRADDHNv8i8 |
| 20486 | CEFBS_HasNEON, // VRECPEd |
| 20487 | CEFBS_HasNEON, // VRECPEfd |
| 20488 | CEFBS_HasNEON, // VRECPEfq |
| 20489 | CEFBS_HasNEON_HasFullFP16, // VRECPEhd |
| 20490 | CEFBS_HasNEON_HasFullFP16, // VRECPEhq |
| 20491 | CEFBS_HasNEON, // VRECPEq |
| 20492 | CEFBS_HasNEON, // VRECPSfd |
| 20493 | CEFBS_HasNEON, // VRECPSfq |
| 20494 | CEFBS_HasNEON_HasFullFP16, // VRECPShd |
| 20495 | CEFBS_HasNEON_HasFullFP16, // VRECPShq |
| 20496 | CEFBS_HasNEON, // VREV16d8 |
| 20497 | CEFBS_HasNEON, // VREV16q8 |
| 20498 | CEFBS_HasNEON, // VREV32d16 |
| 20499 | CEFBS_HasNEON, // VREV32d8 |
| 20500 | CEFBS_HasNEON, // VREV32q16 |
| 20501 | CEFBS_HasNEON, // VREV32q8 |
| 20502 | CEFBS_HasNEON, // VREV64d16 |
| 20503 | CEFBS_HasNEON, // VREV64d32 |
| 20504 | CEFBS_HasNEON, // VREV64d8 |
| 20505 | CEFBS_HasNEON, // VREV64q16 |
| 20506 | CEFBS_HasNEON, // VREV64q32 |
| 20507 | CEFBS_HasNEON, // VREV64q8 |
| 20508 | CEFBS_HasNEON, // VRHADDsv16i8 |
| 20509 | CEFBS_HasNEON, // VRHADDsv2i32 |
| 20510 | CEFBS_HasNEON, // VRHADDsv4i16 |
| 20511 | CEFBS_HasNEON, // VRHADDsv4i32 |
| 20512 | CEFBS_HasNEON, // VRHADDsv8i16 |
| 20513 | CEFBS_HasNEON, // VRHADDsv8i8 |
| 20514 | CEFBS_HasNEON, // VRHADDuv16i8 |
| 20515 | CEFBS_HasNEON, // VRHADDuv2i32 |
| 20516 | CEFBS_HasNEON, // VRHADDuv4i16 |
| 20517 | CEFBS_HasNEON, // VRHADDuv4i32 |
| 20518 | CEFBS_HasNEON, // VRHADDuv8i16 |
| 20519 | CEFBS_HasNEON, // VRHADDuv8i8 |
| 20520 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTAD |
| 20521 | CEFBS_HasFullFP16, // VRINTAH |
| 20522 | CEFBS_HasV8_HasNEON, // VRINTANDf |
| 20523 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANDh |
| 20524 | CEFBS_HasV8_HasNEON, // VRINTANQf |
| 20525 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTANQh |
| 20526 | CEFBS_HasFPARMv8, // VRINTAS |
| 20527 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTMD |
| 20528 | CEFBS_HasFullFP16, // VRINTMH |
| 20529 | CEFBS_HasV8_HasNEON, // VRINTMNDf |
| 20530 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNDh |
| 20531 | CEFBS_HasV8_HasNEON, // VRINTMNQf |
| 20532 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTMNQh |
| 20533 | CEFBS_HasFPARMv8, // VRINTMS |
| 20534 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTND |
| 20535 | CEFBS_HasFullFP16, // VRINTNH |
| 20536 | CEFBS_HasV8_HasNEON, // VRINTNNDf |
| 20537 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNDh |
| 20538 | CEFBS_HasV8_HasNEON, // VRINTNNQf |
| 20539 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTNNQh |
| 20540 | CEFBS_HasFPARMv8, // VRINTNS |
| 20541 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTPD |
| 20542 | CEFBS_HasFullFP16, // VRINTPH |
| 20543 | CEFBS_HasV8_HasNEON, // VRINTPNDf |
| 20544 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNDh |
| 20545 | CEFBS_HasV8_HasNEON, // VRINTPNQf |
| 20546 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTPNQh |
| 20547 | CEFBS_HasFPARMv8, // VRINTPS |
| 20548 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTRD |
| 20549 | CEFBS_HasFullFP16, // VRINTRH |
| 20550 | CEFBS_HasFPARMv8, // VRINTRS |
| 20551 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTXD |
| 20552 | CEFBS_HasFullFP16, // VRINTXH |
| 20553 | CEFBS_HasV8_HasNEON, // VRINTXNDf |
| 20554 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNDh |
| 20555 | CEFBS_HasV8_HasNEON, // VRINTXNQf |
| 20556 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTXNQh |
| 20557 | CEFBS_HasFPARMv8, // VRINTXS |
| 20558 | CEFBS_HasFPARMv8_HasDPVFP, // VRINTZD |
| 20559 | CEFBS_HasFullFP16, // VRINTZH |
| 20560 | CEFBS_HasV8_HasNEON, // VRINTZNDf |
| 20561 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNDh |
| 20562 | CEFBS_HasV8_HasNEON, // VRINTZNQf |
| 20563 | CEFBS_HasV8_HasNEON_HasFullFP16, // VRINTZNQh |
| 20564 | CEFBS_HasFPARMv8, // VRINTZS |
| 20565 | CEFBS_HasNEON, // VRSHLsv16i8 |
| 20566 | CEFBS_HasNEON, // VRSHLsv1i64 |
| 20567 | CEFBS_HasNEON, // VRSHLsv2i32 |
| 20568 | CEFBS_HasNEON, // VRSHLsv2i64 |
| 20569 | CEFBS_HasNEON, // VRSHLsv4i16 |
| 20570 | CEFBS_HasNEON, // VRSHLsv4i32 |
| 20571 | CEFBS_HasNEON, // VRSHLsv8i16 |
| 20572 | CEFBS_HasNEON, // VRSHLsv8i8 |
| 20573 | CEFBS_HasNEON, // VRSHLuv16i8 |
| 20574 | CEFBS_HasNEON, // VRSHLuv1i64 |
| 20575 | CEFBS_HasNEON, // VRSHLuv2i32 |
| 20576 | CEFBS_HasNEON, // VRSHLuv2i64 |
| 20577 | CEFBS_HasNEON, // VRSHLuv4i16 |
| 20578 | CEFBS_HasNEON, // VRSHLuv4i32 |
| 20579 | CEFBS_HasNEON, // VRSHLuv8i16 |
| 20580 | CEFBS_HasNEON, // VRSHLuv8i8 |
| 20581 | CEFBS_HasNEON, // VRSHRNv2i32 |
| 20582 | CEFBS_HasNEON, // VRSHRNv4i16 |
| 20583 | CEFBS_HasNEON, // VRSHRNv8i8 |
| 20584 | CEFBS_HasNEON, // VRSHRsv16i8 |
| 20585 | CEFBS_HasNEON, // VRSHRsv1i64 |
| 20586 | CEFBS_HasNEON, // VRSHRsv2i32 |
| 20587 | CEFBS_HasNEON, // VRSHRsv2i64 |
| 20588 | CEFBS_HasNEON, // VRSHRsv4i16 |
| 20589 | CEFBS_HasNEON, // VRSHRsv4i32 |
| 20590 | CEFBS_HasNEON, // VRSHRsv8i16 |
| 20591 | CEFBS_HasNEON, // VRSHRsv8i8 |
| 20592 | CEFBS_HasNEON, // VRSHRuv16i8 |
| 20593 | CEFBS_HasNEON, // VRSHRuv1i64 |
| 20594 | CEFBS_HasNEON, // VRSHRuv2i32 |
| 20595 | CEFBS_HasNEON, // VRSHRuv2i64 |
| 20596 | CEFBS_HasNEON, // VRSHRuv4i16 |
| 20597 | CEFBS_HasNEON, // VRSHRuv4i32 |
| 20598 | CEFBS_HasNEON, // VRSHRuv8i16 |
| 20599 | CEFBS_HasNEON, // VRSHRuv8i8 |
| 20600 | CEFBS_HasNEON, // VRSQRTEd |
| 20601 | CEFBS_HasNEON, // VRSQRTEfd |
| 20602 | CEFBS_HasNEON, // VRSQRTEfq |
| 20603 | CEFBS_HasNEON_HasFullFP16, // VRSQRTEhd |
| 20604 | CEFBS_HasNEON_HasFullFP16, // VRSQRTEhq |
| 20605 | CEFBS_HasNEON, // VRSQRTEq |
| 20606 | CEFBS_HasNEON, // VRSQRTSfd |
| 20607 | CEFBS_HasNEON, // VRSQRTSfq |
| 20608 | CEFBS_HasNEON_HasFullFP16, // VRSQRTShd |
| 20609 | CEFBS_HasNEON_HasFullFP16, // VRSQRTShq |
| 20610 | CEFBS_HasNEON, // VRSRAsv16i8 |
| 20611 | CEFBS_HasNEON, // VRSRAsv1i64 |
| 20612 | CEFBS_HasNEON, // VRSRAsv2i32 |
| 20613 | CEFBS_HasNEON, // VRSRAsv2i64 |
| 20614 | CEFBS_HasNEON, // VRSRAsv4i16 |
| 20615 | CEFBS_HasNEON, // VRSRAsv4i32 |
| 20616 | CEFBS_HasNEON, // VRSRAsv8i16 |
| 20617 | CEFBS_HasNEON, // VRSRAsv8i8 |
| 20618 | CEFBS_HasNEON, // VRSRAuv16i8 |
| 20619 | CEFBS_HasNEON, // VRSRAuv1i64 |
| 20620 | CEFBS_HasNEON, // VRSRAuv2i32 |
| 20621 | CEFBS_HasNEON, // VRSRAuv2i64 |
| 20622 | CEFBS_HasNEON, // VRSRAuv4i16 |
| 20623 | CEFBS_HasNEON, // VRSRAuv4i32 |
| 20624 | CEFBS_HasNEON, // VRSRAuv8i16 |
| 20625 | CEFBS_HasNEON, // VRSRAuv8i8 |
| 20626 | CEFBS_HasNEON, // VRSUBHNv2i32 |
| 20627 | CEFBS_HasNEON, // VRSUBHNv4i16 |
| 20628 | CEFBS_HasNEON, // VRSUBHNv8i8 |
| 20629 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMD |
| 20630 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSCCLRMS |
| 20631 | CEFBS_HasDotProd, // VSDOTD |
| 20632 | CEFBS_HasDotProd, // VSDOTDI |
| 20633 | CEFBS_HasDotProd, // VSDOTQ |
| 20634 | CEFBS_HasDotProd, // VSDOTQI |
| 20635 | CEFBS_HasFPARMv8_HasDPVFP, // VSELEQD |
| 20636 | CEFBS_HasFullFP16, // VSELEQH |
| 20637 | CEFBS_HasFPARMv8, // VSELEQS |
| 20638 | CEFBS_HasFPARMv8_HasDPVFP, // VSELGED |
| 20639 | CEFBS_HasFullFP16, // VSELGEH |
| 20640 | CEFBS_HasFPARMv8, // VSELGES |
| 20641 | CEFBS_HasFPARMv8_HasDPVFP, // VSELGTD |
| 20642 | CEFBS_HasFullFP16, // VSELGTH |
| 20643 | CEFBS_HasFPARMv8, // VSELGTS |
| 20644 | CEFBS_HasFPARMv8_HasDPVFP, // VSELVSD |
| 20645 | CEFBS_HasFullFP16, // VSELVSH |
| 20646 | CEFBS_HasFPARMv8, // VSELVSS |
| 20647 | CEFBS_HasNEON, // VSETLNi16 |
| 20648 | CEFBS_HasVFP2, // VSETLNi32 |
| 20649 | CEFBS_HasNEON, // VSETLNi8 |
| 20650 | CEFBS_HasNEON, // VSHLLi16 |
| 20651 | CEFBS_HasNEON, // VSHLLi32 |
| 20652 | CEFBS_HasNEON, // VSHLLi8 |
| 20653 | CEFBS_HasNEON, // VSHLLsv2i64 |
| 20654 | CEFBS_HasNEON, // VSHLLsv4i32 |
| 20655 | CEFBS_HasNEON, // VSHLLsv8i16 |
| 20656 | CEFBS_HasNEON, // VSHLLuv2i64 |
| 20657 | CEFBS_HasNEON, // VSHLLuv4i32 |
| 20658 | CEFBS_HasNEON, // VSHLLuv8i16 |
| 20659 | CEFBS_HasNEON, // VSHLiv16i8 |
| 20660 | CEFBS_HasNEON, // VSHLiv1i64 |
| 20661 | CEFBS_HasNEON, // VSHLiv2i32 |
| 20662 | CEFBS_HasNEON, // VSHLiv2i64 |
| 20663 | CEFBS_HasNEON, // VSHLiv4i16 |
| 20664 | CEFBS_HasNEON, // VSHLiv4i32 |
| 20665 | CEFBS_HasNEON, // VSHLiv8i16 |
| 20666 | CEFBS_HasNEON, // VSHLiv8i8 |
| 20667 | CEFBS_HasNEON, // VSHLsv16i8 |
| 20668 | CEFBS_HasNEON, // VSHLsv1i64 |
| 20669 | CEFBS_HasNEON, // VSHLsv2i32 |
| 20670 | CEFBS_HasNEON, // VSHLsv2i64 |
| 20671 | CEFBS_HasNEON, // VSHLsv4i16 |
| 20672 | CEFBS_HasNEON, // VSHLsv4i32 |
| 20673 | CEFBS_HasNEON, // VSHLsv8i16 |
| 20674 | CEFBS_HasNEON, // VSHLsv8i8 |
| 20675 | CEFBS_HasNEON, // VSHLuv16i8 |
| 20676 | CEFBS_HasNEON, // VSHLuv1i64 |
| 20677 | CEFBS_HasNEON, // VSHLuv2i32 |
| 20678 | CEFBS_HasNEON, // VSHLuv2i64 |
| 20679 | CEFBS_HasNEON, // VSHLuv4i16 |
| 20680 | CEFBS_HasNEON, // VSHLuv4i32 |
| 20681 | CEFBS_HasNEON, // VSHLuv8i16 |
| 20682 | CEFBS_HasNEON, // VSHLuv8i8 |
| 20683 | CEFBS_HasNEON, // VSHRNv2i32 |
| 20684 | CEFBS_HasNEON, // VSHRNv4i16 |
| 20685 | CEFBS_HasNEON, // VSHRNv8i8 |
| 20686 | CEFBS_HasNEON, // VSHRsv16i8 |
| 20687 | CEFBS_HasNEON, // VSHRsv1i64 |
| 20688 | CEFBS_HasNEON, // VSHRsv2i32 |
| 20689 | CEFBS_HasNEON, // VSHRsv2i64 |
| 20690 | CEFBS_HasNEON, // VSHRsv4i16 |
| 20691 | CEFBS_HasNEON, // VSHRsv4i32 |
| 20692 | CEFBS_HasNEON, // VSHRsv8i16 |
| 20693 | CEFBS_HasNEON, // VSHRsv8i8 |
| 20694 | CEFBS_HasNEON, // VSHRuv16i8 |
| 20695 | CEFBS_HasNEON, // VSHRuv1i64 |
| 20696 | CEFBS_HasNEON, // VSHRuv2i32 |
| 20697 | CEFBS_HasNEON, // VSHRuv2i64 |
| 20698 | CEFBS_HasNEON, // VSHRuv4i16 |
| 20699 | CEFBS_HasNEON, // VSHRuv4i32 |
| 20700 | CEFBS_HasNEON, // VSHRuv8i16 |
| 20701 | CEFBS_HasNEON, // VSHRuv8i8 |
| 20702 | CEFBS_HasVFP2_HasDPVFP, // VSHTOD |
| 20703 | CEFBS_HasFullFP16, // VSHTOH |
| 20704 | CEFBS_HasVFP2, // VSHTOS |
| 20705 | CEFBS_HasVFP2_HasDPVFP, // VSITOD |
| 20706 | CEFBS_HasFullFP16, // VSITOH |
| 20707 | CEFBS_HasVFP2, // VSITOS |
| 20708 | CEFBS_HasNEON, // VSLIv16i8 |
| 20709 | CEFBS_HasNEON, // VSLIv1i64 |
| 20710 | CEFBS_HasNEON, // VSLIv2i32 |
| 20711 | CEFBS_HasNEON, // VSLIv2i64 |
| 20712 | CEFBS_HasNEON, // VSLIv4i16 |
| 20713 | CEFBS_HasNEON, // VSLIv4i32 |
| 20714 | CEFBS_HasNEON, // VSLIv8i16 |
| 20715 | CEFBS_HasNEON, // VSLIv8i8 |
| 20716 | CEFBS_HasVFP2_HasDPVFP, // VSLTOD |
| 20717 | CEFBS_HasFullFP16, // VSLTOH |
| 20718 | CEFBS_HasVFP2, // VSLTOS |
| 20719 | CEFBS_HasMatMulInt8, // VSMMLA |
| 20720 | CEFBS_HasVFP2_HasDPVFP, // VSQRTD |
| 20721 | CEFBS_HasFullFP16, // VSQRTH |
| 20722 | CEFBS_HasVFP2, // VSQRTS |
| 20723 | CEFBS_HasNEON, // VSRAsv16i8 |
| 20724 | CEFBS_HasNEON, // VSRAsv1i64 |
| 20725 | CEFBS_HasNEON, // VSRAsv2i32 |
| 20726 | CEFBS_HasNEON, // VSRAsv2i64 |
| 20727 | CEFBS_HasNEON, // VSRAsv4i16 |
| 20728 | CEFBS_HasNEON, // VSRAsv4i32 |
| 20729 | CEFBS_HasNEON, // VSRAsv8i16 |
| 20730 | CEFBS_HasNEON, // VSRAsv8i8 |
| 20731 | CEFBS_HasNEON, // VSRAuv16i8 |
| 20732 | CEFBS_HasNEON, // VSRAuv1i64 |
| 20733 | CEFBS_HasNEON, // VSRAuv2i32 |
| 20734 | CEFBS_HasNEON, // VSRAuv2i64 |
| 20735 | CEFBS_HasNEON, // VSRAuv4i16 |
| 20736 | CEFBS_HasNEON, // VSRAuv4i32 |
| 20737 | CEFBS_HasNEON, // VSRAuv8i16 |
| 20738 | CEFBS_HasNEON, // VSRAuv8i8 |
| 20739 | CEFBS_HasNEON, // VSRIv16i8 |
| 20740 | CEFBS_HasNEON, // VSRIv1i64 |
| 20741 | CEFBS_HasNEON, // VSRIv2i32 |
| 20742 | CEFBS_HasNEON, // VSRIv2i64 |
| 20743 | CEFBS_HasNEON, // VSRIv4i16 |
| 20744 | CEFBS_HasNEON, // VSRIv4i32 |
| 20745 | CEFBS_HasNEON, // VSRIv8i16 |
| 20746 | CEFBS_HasNEON, // VSRIv8i8 |
| 20747 | CEFBS_HasNEON, // VST1LNd16 |
| 20748 | CEFBS_HasNEON, // VST1LNd16_UPD |
| 20749 | CEFBS_HasNEON, // VST1LNd32 |
| 20750 | CEFBS_HasNEON, // VST1LNd32_UPD |
| 20751 | CEFBS_HasNEON, // VST1LNd8 |
| 20752 | CEFBS_HasNEON, // VST1LNd8_UPD |
| 20753 | CEFBS_HasNEON, // VST1LNq16Pseudo |
| 20754 | CEFBS_HasNEON, // VST1LNq16Pseudo_UPD |
| 20755 | CEFBS_HasNEON, // VST1LNq32Pseudo |
| 20756 | CEFBS_HasNEON, // VST1LNq32Pseudo_UPD |
| 20757 | CEFBS_HasNEON, // VST1LNq8Pseudo |
| 20758 | CEFBS_HasNEON, // VST1LNq8Pseudo_UPD |
| 20759 | CEFBS_HasNEON, // VST1d16 |
| 20760 | CEFBS_HasNEON, // VST1d16Q |
| 20761 | CEFBS_HasNEON, // VST1d16QPseudo |
| 20762 | CEFBS_HasNEON, // VST1d16QPseudoWB_fixed |
| 20763 | CEFBS_HasNEON, // VST1d16QPseudoWB_register |
| 20764 | CEFBS_HasNEON, // VST1d16Qwb_fixed |
| 20765 | CEFBS_HasNEON, // VST1d16Qwb_register |
| 20766 | CEFBS_HasNEON, // VST1d16T |
| 20767 | CEFBS_HasNEON, // VST1d16TPseudo |
| 20768 | CEFBS_HasNEON, // VST1d16TPseudoWB_fixed |
| 20769 | CEFBS_HasNEON, // VST1d16TPseudoWB_register |
| 20770 | CEFBS_HasNEON, // VST1d16Twb_fixed |
| 20771 | CEFBS_HasNEON, // VST1d16Twb_register |
| 20772 | CEFBS_HasNEON, // VST1d16wb_fixed |
| 20773 | CEFBS_HasNEON, // VST1d16wb_register |
| 20774 | CEFBS_HasNEON, // VST1d32 |
| 20775 | CEFBS_HasNEON, // VST1d32Q |
| 20776 | CEFBS_HasNEON, // VST1d32QPseudo |
| 20777 | CEFBS_HasNEON, // VST1d32QPseudoWB_fixed |
| 20778 | CEFBS_HasNEON, // VST1d32QPseudoWB_register |
| 20779 | CEFBS_HasNEON, // VST1d32Qwb_fixed |
| 20780 | CEFBS_HasNEON, // VST1d32Qwb_register |
| 20781 | CEFBS_HasNEON, // VST1d32T |
| 20782 | CEFBS_HasNEON, // VST1d32TPseudo |
| 20783 | CEFBS_HasNEON, // VST1d32TPseudoWB_fixed |
| 20784 | CEFBS_HasNEON, // VST1d32TPseudoWB_register |
| 20785 | CEFBS_HasNEON, // VST1d32Twb_fixed |
| 20786 | CEFBS_HasNEON, // VST1d32Twb_register |
| 20787 | CEFBS_HasNEON, // VST1d32wb_fixed |
| 20788 | CEFBS_HasNEON, // VST1d32wb_register |
| 20789 | CEFBS_HasNEON, // VST1d64 |
| 20790 | CEFBS_HasNEON, // VST1d64Q |
| 20791 | CEFBS_HasNEON, // VST1d64QPseudo |
| 20792 | CEFBS_HasNEON, // VST1d64QPseudoWB_fixed |
| 20793 | CEFBS_HasNEON, // VST1d64QPseudoWB_register |
| 20794 | CEFBS_HasNEON, // VST1d64Qwb_fixed |
| 20795 | CEFBS_HasNEON, // VST1d64Qwb_register |
| 20796 | CEFBS_HasNEON, // VST1d64T |
| 20797 | CEFBS_HasNEON, // VST1d64TPseudo |
| 20798 | CEFBS_HasNEON, // VST1d64TPseudoWB_fixed |
| 20799 | CEFBS_HasNEON, // VST1d64TPseudoWB_register |
| 20800 | CEFBS_HasNEON, // VST1d64Twb_fixed |
| 20801 | CEFBS_HasNEON, // VST1d64Twb_register |
| 20802 | CEFBS_HasNEON, // VST1d64wb_fixed |
| 20803 | CEFBS_HasNEON, // VST1d64wb_register |
| 20804 | CEFBS_HasNEON, // VST1d8 |
| 20805 | CEFBS_HasNEON, // VST1d8Q |
| 20806 | CEFBS_HasNEON, // VST1d8QPseudo |
| 20807 | CEFBS_HasNEON, // VST1d8QPseudoWB_fixed |
| 20808 | CEFBS_HasNEON, // VST1d8QPseudoWB_register |
| 20809 | CEFBS_HasNEON, // VST1d8Qwb_fixed |
| 20810 | CEFBS_HasNEON, // VST1d8Qwb_register |
| 20811 | CEFBS_HasNEON, // VST1d8T |
| 20812 | CEFBS_HasNEON, // VST1d8TPseudo |
| 20813 | CEFBS_HasNEON, // VST1d8TPseudoWB_fixed |
| 20814 | CEFBS_HasNEON, // VST1d8TPseudoWB_register |
| 20815 | CEFBS_HasNEON, // VST1d8Twb_fixed |
| 20816 | CEFBS_HasNEON, // VST1d8Twb_register |
| 20817 | CEFBS_HasNEON, // VST1d8wb_fixed |
| 20818 | CEFBS_HasNEON, // VST1d8wb_register |
| 20819 | CEFBS_HasNEON, // VST1q16 |
| 20820 | CEFBS_HasNEON, // VST1q16HighQPseudo |
| 20821 | CEFBS_HasNEON, // VST1q16HighQPseudo_UPD |
| 20822 | CEFBS_HasNEON, // VST1q16HighTPseudo |
| 20823 | CEFBS_HasNEON, // VST1q16HighTPseudo_UPD |
| 20824 | CEFBS_HasNEON, // VST1q16LowQPseudo_UPD |
| 20825 | CEFBS_HasNEON, // VST1q16LowTPseudo_UPD |
| 20826 | CEFBS_HasNEON, // VST1q16wb_fixed |
| 20827 | CEFBS_HasNEON, // VST1q16wb_register |
| 20828 | CEFBS_HasNEON, // VST1q32 |
| 20829 | CEFBS_HasNEON, // VST1q32HighQPseudo |
| 20830 | CEFBS_HasNEON, // VST1q32HighQPseudo_UPD |
| 20831 | CEFBS_HasNEON, // VST1q32HighTPseudo |
| 20832 | CEFBS_HasNEON, // VST1q32HighTPseudo_UPD |
| 20833 | CEFBS_HasNEON, // VST1q32LowQPseudo_UPD |
| 20834 | CEFBS_HasNEON, // VST1q32LowTPseudo_UPD |
| 20835 | CEFBS_HasNEON, // VST1q32wb_fixed |
| 20836 | CEFBS_HasNEON, // VST1q32wb_register |
| 20837 | CEFBS_HasNEON, // VST1q64 |
| 20838 | CEFBS_HasNEON, // VST1q64HighQPseudo |
| 20839 | CEFBS_HasNEON, // VST1q64HighQPseudo_UPD |
| 20840 | CEFBS_HasNEON, // VST1q64HighTPseudo |
| 20841 | CEFBS_HasNEON, // VST1q64HighTPseudo_UPD |
| 20842 | CEFBS_HasNEON, // VST1q64LowQPseudo_UPD |
| 20843 | CEFBS_HasNEON, // VST1q64LowTPseudo_UPD |
| 20844 | CEFBS_HasNEON, // VST1q64wb_fixed |
| 20845 | CEFBS_HasNEON, // VST1q64wb_register |
| 20846 | CEFBS_HasNEON, // VST1q8 |
| 20847 | CEFBS_HasNEON, // VST1q8HighQPseudo |
| 20848 | CEFBS_HasNEON, // VST1q8HighQPseudo_UPD |
| 20849 | CEFBS_HasNEON, // VST1q8HighTPseudo |
| 20850 | CEFBS_HasNEON, // VST1q8HighTPseudo_UPD |
| 20851 | CEFBS_HasNEON, // VST1q8LowQPseudo_UPD |
| 20852 | CEFBS_HasNEON, // VST1q8LowTPseudo_UPD |
| 20853 | CEFBS_HasNEON, // VST1q8wb_fixed |
| 20854 | CEFBS_HasNEON, // VST1q8wb_register |
| 20855 | CEFBS_HasNEON, // VST2LNd16 |
| 20856 | CEFBS_HasNEON, // VST2LNd16Pseudo |
| 20857 | CEFBS_HasNEON, // VST2LNd16Pseudo_UPD |
| 20858 | CEFBS_HasNEON, // VST2LNd16_UPD |
| 20859 | CEFBS_HasNEON, // VST2LNd32 |
| 20860 | CEFBS_HasNEON, // VST2LNd32Pseudo |
| 20861 | CEFBS_HasNEON, // VST2LNd32Pseudo_UPD |
| 20862 | CEFBS_HasNEON, // VST2LNd32_UPD |
| 20863 | CEFBS_HasNEON, // VST2LNd8 |
| 20864 | CEFBS_HasNEON, // VST2LNd8Pseudo |
| 20865 | CEFBS_HasNEON, // VST2LNd8Pseudo_UPD |
| 20866 | CEFBS_HasNEON, // VST2LNd8_UPD |
| 20867 | CEFBS_HasNEON, // VST2LNq16 |
| 20868 | CEFBS_HasNEON, // VST2LNq16Pseudo |
| 20869 | CEFBS_HasNEON, // VST2LNq16Pseudo_UPD |
| 20870 | CEFBS_HasNEON, // VST2LNq16_UPD |
| 20871 | CEFBS_HasNEON, // VST2LNq32 |
| 20872 | CEFBS_HasNEON, // VST2LNq32Pseudo |
| 20873 | CEFBS_HasNEON, // VST2LNq32Pseudo_UPD |
| 20874 | CEFBS_HasNEON, // VST2LNq32_UPD |
| 20875 | CEFBS_HasNEON, // VST2b16 |
| 20876 | CEFBS_HasNEON, // VST2b16wb_fixed |
| 20877 | CEFBS_HasNEON, // VST2b16wb_register |
| 20878 | CEFBS_HasNEON, // VST2b32 |
| 20879 | CEFBS_HasNEON, // VST2b32wb_fixed |
| 20880 | CEFBS_HasNEON, // VST2b32wb_register |
| 20881 | CEFBS_HasNEON, // VST2b8 |
| 20882 | CEFBS_HasNEON, // VST2b8wb_fixed |
| 20883 | CEFBS_HasNEON, // VST2b8wb_register |
| 20884 | CEFBS_HasNEON, // VST2d16 |
| 20885 | CEFBS_HasNEON, // VST2d16wb_fixed |
| 20886 | CEFBS_HasNEON, // VST2d16wb_register |
| 20887 | CEFBS_HasNEON, // VST2d32 |
| 20888 | CEFBS_HasNEON, // VST2d32wb_fixed |
| 20889 | CEFBS_HasNEON, // VST2d32wb_register |
| 20890 | CEFBS_HasNEON, // VST2d8 |
| 20891 | CEFBS_HasNEON, // VST2d8wb_fixed |
| 20892 | CEFBS_HasNEON, // VST2d8wb_register |
| 20893 | CEFBS_HasNEON, // VST2q16 |
| 20894 | CEFBS_HasNEON, // VST2q16Pseudo |
| 20895 | CEFBS_HasNEON, // VST2q16PseudoWB_fixed |
| 20896 | CEFBS_HasNEON, // VST2q16PseudoWB_register |
| 20897 | CEFBS_HasNEON, // VST2q16wb_fixed |
| 20898 | CEFBS_HasNEON, // VST2q16wb_register |
| 20899 | CEFBS_HasNEON, // VST2q32 |
| 20900 | CEFBS_HasNEON, // VST2q32Pseudo |
| 20901 | CEFBS_HasNEON, // VST2q32PseudoWB_fixed |
| 20902 | CEFBS_HasNEON, // VST2q32PseudoWB_register |
| 20903 | CEFBS_HasNEON, // VST2q32wb_fixed |
| 20904 | CEFBS_HasNEON, // VST2q32wb_register |
| 20905 | CEFBS_HasNEON, // VST2q8 |
| 20906 | CEFBS_HasNEON, // VST2q8Pseudo |
| 20907 | CEFBS_HasNEON, // VST2q8PseudoWB_fixed |
| 20908 | CEFBS_HasNEON, // VST2q8PseudoWB_register |
| 20909 | CEFBS_HasNEON, // VST2q8wb_fixed |
| 20910 | CEFBS_HasNEON, // VST2q8wb_register |
| 20911 | CEFBS_HasNEON, // VST3LNd16 |
| 20912 | CEFBS_HasNEON, // VST3LNd16Pseudo |
| 20913 | CEFBS_HasNEON, // VST3LNd16Pseudo_UPD |
| 20914 | CEFBS_HasNEON, // VST3LNd16_UPD |
| 20915 | CEFBS_HasNEON, // VST3LNd32 |
| 20916 | CEFBS_HasNEON, // VST3LNd32Pseudo |
| 20917 | CEFBS_HasNEON, // VST3LNd32Pseudo_UPD |
| 20918 | CEFBS_HasNEON, // VST3LNd32_UPD |
| 20919 | CEFBS_HasNEON, // VST3LNd8 |
| 20920 | CEFBS_HasNEON, // VST3LNd8Pseudo |
| 20921 | CEFBS_HasNEON, // VST3LNd8Pseudo_UPD |
| 20922 | CEFBS_HasNEON, // VST3LNd8_UPD |
| 20923 | CEFBS_HasNEON, // VST3LNq16 |
| 20924 | CEFBS_HasNEON, // VST3LNq16Pseudo |
| 20925 | CEFBS_HasNEON, // VST3LNq16Pseudo_UPD |
| 20926 | CEFBS_HasNEON, // VST3LNq16_UPD |
| 20927 | CEFBS_HasNEON, // VST3LNq32 |
| 20928 | CEFBS_HasNEON, // VST3LNq32Pseudo |
| 20929 | CEFBS_HasNEON, // VST3LNq32Pseudo_UPD |
| 20930 | CEFBS_HasNEON, // VST3LNq32_UPD |
| 20931 | CEFBS_HasNEON, // VST3d16 |
| 20932 | CEFBS_HasNEON, // VST3d16Pseudo |
| 20933 | CEFBS_HasNEON, // VST3d16Pseudo_UPD |
| 20934 | CEFBS_HasNEON, // VST3d16_UPD |
| 20935 | CEFBS_HasNEON, // VST3d32 |
| 20936 | CEFBS_HasNEON, // VST3d32Pseudo |
| 20937 | CEFBS_HasNEON, // VST3d32Pseudo_UPD |
| 20938 | CEFBS_HasNEON, // VST3d32_UPD |
| 20939 | CEFBS_HasNEON, // VST3d8 |
| 20940 | CEFBS_HasNEON, // VST3d8Pseudo |
| 20941 | CEFBS_HasNEON, // VST3d8Pseudo_UPD |
| 20942 | CEFBS_HasNEON, // VST3d8_UPD |
| 20943 | CEFBS_HasNEON, // VST3q16 |
| 20944 | CEFBS_HasNEON, // VST3q16Pseudo_UPD |
| 20945 | CEFBS_HasNEON, // VST3q16_UPD |
| 20946 | CEFBS_HasNEON, // VST3q16oddPseudo |
| 20947 | CEFBS_HasNEON, // VST3q16oddPseudo_UPD |
| 20948 | CEFBS_HasNEON, // VST3q32 |
| 20949 | CEFBS_HasNEON, // VST3q32Pseudo_UPD |
| 20950 | CEFBS_HasNEON, // VST3q32_UPD |
| 20951 | CEFBS_HasNEON, // VST3q32oddPseudo |
| 20952 | CEFBS_HasNEON, // VST3q32oddPseudo_UPD |
| 20953 | CEFBS_HasNEON, // VST3q8 |
| 20954 | CEFBS_HasNEON, // VST3q8Pseudo_UPD |
| 20955 | CEFBS_HasNEON, // VST3q8_UPD |
| 20956 | CEFBS_HasNEON, // VST3q8oddPseudo |
| 20957 | CEFBS_HasNEON, // VST3q8oddPseudo_UPD |
| 20958 | CEFBS_HasNEON, // VST4LNd16 |
| 20959 | CEFBS_HasNEON, // VST4LNd16Pseudo |
| 20960 | CEFBS_HasNEON, // VST4LNd16Pseudo_UPD |
| 20961 | CEFBS_HasNEON, // VST4LNd16_UPD |
| 20962 | CEFBS_HasNEON, // VST4LNd32 |
| 20963 | CEFBS_HasNEON, // VST4LNd32Pseudo |
| 20964 | CEFBS_HasNEON, // VST4LNd32Pseudo_UPD |
| 20965 | CEFBS_HasNEON, // VST4LNd32_UPD |
| 20966 | CEFBS_HasNEON, // VST4LNd8 |
| 20967 | CEFBS_HasNEON, // VST4LNd8Pseudo |
| 20968 | CEFBS_HasNEON, // VST4LNd8Pseudo_UPD |
| 20969 | CEFBS_HasNEON, // VST4LNd8_UPD |
| 20970 | CEFBS_HasNEON, // VST4LNq16 |
| 20971 | CEFBS_HasNEON, // VST4LNq16Pseudo |
| 20972 | CEFBS_HasNEON, // VST4LNq16Pseudo_UPD |
| 20973 | CEFBS_HasNEON, // VST4LNq16_UPD |
| 20974 | CEFBS_HasNEON, // VST4LNq32 |
| 20975 | CEFBS_HasNEON, // VST4LNq32Pseudo |
| 20976 | CEFBS_HasNEON, // VST4LNq32Pseudo_UPD |
| 20977 | CEFBS_HasNEON, // VST4LNq32_UPD |
| 20978 | CEFBS_HasNEON, // VST4d16 |
| 20979 | CEFBS_HasNEON, // VST4d16Pseudo |
| 20980 | CEFBS_HasNEON, // VST4d16Pseudo_UPD |
| 20981 | CEFBS_HasNEON, // VST4d16_UPD |
| 20982 | CEFBS_HasNEON, // VST4d32 |
| 20983 | CEFBS_HasNEON, // VST4d32Pseudo |
| 20984 | CEFBS_HasNEON, // VST4d32Pseudo_UPD |
| 20985 | CEFBS_HasNEON, // VST4d32_UPD |
| 20986 | CEFBS_HasNEON, // VST4d8 |
| 20987 | CEFBS_HasNEON, // VST4d8Pseudo |
| 20988 | CEFBS_HasNEON, // VST4d8Pseudo_UPD |
| 20989 | CEFBS_HasNEON, // VST4d8_UPD |
| 20990 | CEFBS_HasNEON, // VST4q16 |
| 20991 | CEFBS_HasNEON, // VST4q16Pseudo_UPD |
| 20992 | CEFBS_HasNEON, // VST4q16_UPD |
| 20993 | CEFBS_HasNEON, // VST4q16oddPseudo |
| 20994 | CEFBS_HasNEON, // VST4q16oddPseudo_UPD |
| 20995 | CEFBS_HasNEON, // VST4q32 |
| 20996 | CEFBS_HasNEON, // VST4q32Pseudo_UPD |
| 20997 | CEFBS_HasNEON, // VST4q32_UPD |
| 20998 | CEFBS_HasNEON, // VST4q32oddPseudo |
| 20999 | CEFBS_HasNEON, // VST4q32oddPseudo_UPD |
| 21000 | CEFBS_HasNEON, // VST4q8 |
| 21001 | CEFBS_HasNEON, // VST4q8Pseudo_UPD |
| 21002 | CEFBS_HasNEON, // VST4q8_UPD |
| 21003 | CEFBS_HasNEON, // VST4q8oddPseudo |
| 21004 | CEFBS_HasNEON, // VST4q8oddPseudo_UPD |
| 21005 | CEFBS_HasFPRegs, // VSTMDDB_UPD |
| 21006 | CEFBS_HasFPRegs, // VSTMDIA |
| 21007 | CEFBS_HasFPRegs, // VSTMDIA_UPD |
| 21008 | CEFBS_HasVFP2, // VSTMQIA |
| 21009 | CEFBS_HasFPRegs, // VSTMSDB_UPD |
| 21010 | CEFBS_HasFPRegs, // VSTMSIA |
| 21011 | CEFBS_HasFPRegs, // VSTMSIA_UPD |
| 21012 | CEFBS_HasFPRegs, // VSTRD |
| 21013 | CEFBS_HasFPRegs16, // VSTRH |
| 21014 | CEFBS_HasFPRegs, // VSTRS |
| 21015 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_off |
| 21016 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_post |
| 21017 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTNS_pre |
| 21018 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_off |
| 21019 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_post |
| 21020 | CEFBS_HasV8_1MMainline_Has8MSecExt, // VSTR_FPCXTS_pre |
| 21021 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_off |
| 21022 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_post |
| 21023 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_NZCVQC_pre |
| 21024 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_off |
| 21025 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_post |
| 21026 | CEFBS_HasFPRegs_HasV8_1MMainline, // VSTR_FPSCR_pre |
| 21027 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_off |
| 21028 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_post |
| 21029 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_P0_pre |
| 21030 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_off |
| 21031 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_post |
| 21032 | CEFBS_HasV8_1MMainline_HasMVEInt, // VSTR_VPR_pre |
| 21033 | CEFBS_HasVFP2_HasDPVFP, // VSUBD |
| 21034 | CEFBS_HasFullFP16, // VSUBH |
| 21035 | CEFBS_HasNEON, // VSUBHNv2i32 |
| 21036 | CEFBS_HasNEON, // VSUBHNv4i16 |
| 21037 | CEFBS_HasNEON, // VSUBHNv8i8 |
| 21038 | CEFBS_HasNEON, // VSUBLsv2i64 |
| 21039 | CEFBS_HasNEON, // VSUBLsv4i32 |
| 21040 | CEFBS_HasNEON, // VSUBLsv8i16 |
| 21041 | CEFBS_HasNEON, // VSUBLuv2i64 |
| 21042 | CEFBS_HasNEON, // VSUBLuv4i32 |
| 21043 | CEFBS_HasNEON, // VSUBLuv8i16 |
| 21044 | CEFBS_HasVFP2, // VSUBS |
| 21045 | CEFBS_HasNEON, // VSUBWsv2i64 |
| 21046 | CEFBS_HasNEON, // VSUBWsv4i32 |
| 21047 | CEFBS_HasNEON, // VSUBWsv8i16 |
| 21048 | CEFBS_HasNEON, // VSUBWuv2i64 |
| 21049 | CEFBS_HasNEON, // VSUBWuv4i32 |
| 21050 | CEFBS_HasNEON, // VSUBWuv8i16 |
| 21051 | CEFBS_HasNEON, // VSUBfd |
| 21052 | CEFBS_HasNEON, // VSUBfq |
| 21053 | CEFBS_HasNEON_HasFullFP16, // VSUBhd |
| 21054 | CEFBS_HasNEON_HasFullFP16, // VSUBhq |
| 21055 | CEFBS_HasNEON, // VSUBv16i8 |
| 21056 | CEFBS_HasNEON, // VSUBv1i64 |
| 21057 | CEFBS_HasNEON, // VSUBv2i32 |
| 21058 | CEFBS_HasNEON, // VSUBv2i64 |
| 21059 | CEFBS_HasNEON, // VSUBv4i16 |
| 21060 | CEFBS_HasNEON, // VSUBv4i32 |
| 21061 | CEFBS_HasNEON, // VSUBv8i16 |
| 21062 | CEFBS_HasNEON, // VSUBv8i8 |
| 21063 | CEFBS_HasMatMulInt8, // VSUDOTDI |
| 21064 | CEFBS_HasMatMulInt8, // VSUDOTQI |
| 21065 | CEFBS_HasNEON, // VSWPd |
| 21066 | CEFBS_HasNEON, // VSWPq |
| 21067 | CEFBS_HasNEON, // VTBL1 |
| 21068 | CEFBS_HasNEON, // VTBL2 |
| 21069 | CEFBS_HasNEON, // VTBL3 |
| 21070 | CEFBS_HasNEON, // VTBL3Pseudo |
| 21071 | CEFBS_HasNEON, // VTBL4 |
| 21072 | CEFBS_HasNEON, // VTBL4Pseudo |
| 21073 | CEFBS_HasNEON, // VTBX1 |
| 21074 | CEFBS_HasNEON, // VTBX2 |
| 21075 | CEFBS_HasNEON, // VTBX3 |
| 21076 | CEFBS_HasNEON, // VTBX3Pseudo |
| 21077 | CEFBS_HasNEON, // VTBX4 |
| 21078 | CEFBS_HasNEON, // VTBX4Pseudo |
| 21079 | CEFBS_HasVFP2_HasDPVFP, // VTOSHD |
| 21080 | CEFBS_HasFullFP16, // VTOSHH |
| 21081 | CEFBS_HasVFP2, // VTOSHS |
| 21082 | CEFBS_HasVFP2_HasDPVFP, // VTOSIRD |
| 21083 | CEFBS_HasFullFP16, // VTOSIRH |
| 21084 | CEFBS_HasVFP2, // VTOSIRS |
| 21085 | CEFBS_HasVFP2_HasDPVFP, // VTOSIZD |
| 21086 | CEFBS_HasFullFP16, // VTOSIZH |
| 21087 | CEFBS_HasVFP2, // VTOSIZS |
| 21088 | CEFBS_HasVFP2_HasDPVFP, // VTOSLD |
| 21089 | CEFBS_HasFullFP16, // VTOSLH |
| 21090 | CEFBS_HasVFP2, // VTOSLS |
| 21091 | CEFBS_HasVFP2_HasDPVFP, // VTOUHD |
| 21092 | CEFBS_HasFullFP16, // VTOUHH |
| 21093 | CEFBS_HasVFP2, // VTOUHS |
| 21094 | CEFBS_HasVFP2_HasDPVFP, // VTOUIRD |
| 21095 | CEFBS_HasFullFP16, // VTOUIRH |
| 21096 | CEFBS_HasVFP2, // VTOUIRS |
| 21097 | CEFBS_HasVFP2_HasDPVFP, // VTOUIZD |
| 21098 | CEFBS_HasFullFP16, // VTOUIZH |
| 21099 | CEFBS_HasVFP2, // VTOUIZS |
| 21100 | CEFBS_HasVFP2_HasDPVFP, // VTOULD |
| 21101 | CEFBS_HasFullFP16, // VTOULH |
| 21102 | CEFBS_HasVFP2, // VTOULS |
| 21103 | CEFBS_HasNEON, // VTRNd16 |
| 21104 | CEFBS_HasNEON, // VTRNd32 |
| 21105 | CEFBS_HasNEON, // VTRNd8 |
| 21106 | CEFBS_HasNEON, // VTRNq16 |
| 21107 | CEFBS_HasNEON, // VTRNq32 |
| 21108 | CEFBS_HasNEON, // VTRNq8 |
| 21109 | CEFBS_HasNEON, // VTSTv16i8 |
| 21110 | CEFBS_HasNEON, // VTSTv2i32 |
| 21111 | CEFBS_HasNEON, // VTSTv4i16 |
| 21112 | CEFBS_HasNEON, // VTSTv4i32 |
| 21113 | CEFBS_HasNEON, // VTSTv8i16 |
| 21114 | CEFBS_HasNEON, // VTSTv8i8 |
| 21115 | CEFBS_HasDotProd, // VUDOTD |
| 21116 | CEFBS_HasDotProd, // VUDOTDI |
| 21117 | CEFBS_HasDotProd, // VUDOTQ |
| 21118 | CEFBS_HasDotProd, // VUDOTQI |
| 21119 | CEFBS_HasVFP2_HasDPVFP, // VUHTOD |
| 21120 | CEFBS_HasFullFP16, // VUHTOH |
| 21121 | CEFBS_HasVFP2, // VUHTOS |
| 21122 | CEFBS_HasVFP2_HasDPVFP, // VUITOD |
| 21123 | CEFBS_HasFullFP16, // VUITOH |
| 21124 | CEFBS_HasVFP2, // VUITOS |
| 21125 | CEFBS_HasVFP2_HasDPVFP, // VULTOD |
| 21126 | CEFBS_HasFullFP16, // VULTOH |
| 21127 | CEFBS_HasVFP2, // VULTOS |
| 21128 | CEFBS_HasMatMulInt8, // VUMMLA |
| 21129 | CEFBS_HasMatMulInt8, // VUSDOTD |
| 21130 | CEFBS_HasMatMulInt8, // VUSDOTDI |
| 21131 | CEFBS_HasMatMulInt8, // VUSDOTQ |
| 21132 | CEFBS_HasMatMulInt8, // VUSDOTQI |
| 21133 | CEFBS_HasMatMulInt8, // VUSMMLA |
| 21134 | CEFBS_HasNEON, // VUZPd16 |
| 21135 | CEFBS_HasNEON, // VUZPd8 |
| 21136 | CEFBS_HasNEON, // VUZPq16 |
| 21137 | CEFBS_HasNEON, // VUZPq32 |
| 21138 | CEFBS_HasNEON, // VUZPq8 |
| 21139 | CEFBS_HasNEON, // VZIPd16 |
| 21140 | CEFBS_HasNEON, // VZIPd8 |
| 21141 | CEFBS_HasNEON, // VZIPq16 |
| 21142 | CEFBS_HasNEON, // VZIPq32 |
| 21143 | CEFBS_HasNEON, // VZIPq8 |
| 21144 | CEFBS_IsARM, // sysLDMDA |
| 21145 | CEFBS_IsARM, // sysLDMDA_UPD |
| 21146 | CEFBS_IsARM, // sysLDMDB |
| 21147 | CEFBS_IsARM, // sysLDMDB_UPD |
| 21148 | CEFBS_IsARM, // sysLDMIA |
| 21149 | CEFBS_IsARM, // sysLDMIA_UPD |
| 21150 | CEFBS_IsARM, // sysLDMIB |
| 21151 | CEFBS_IsARM, // sysLDMIB_UPD |
| 21152 | CEFBS_IsARM, // sysSTMDA |
| 21153 | CEFBS_IsARM, // sysSTMDA_UPD |
| 21154 | CEFBS_IsARM, // sysSTMDB |
| 21155 | CEFBS_IsARM, // sysSTMDB_UPD |
| 21156 | CEFBS_IsARM, // sysSTMIA |
| 21157 | CEFBS_IsARM, // sysSTMIA_UPD |
| 21158 | CEFBS_IsARM, // sysSTMIB |
| 21159 | CEFBS_IsARM, // sysSTMIB_UPD |
| 21160 | CEFBS_IsThumb2, // t2ADCri |
| 21161 | CEFBS_IsThumb2, // t2ADCrr |
| 21162 | CEFBS_IsThumb2, // t2ADCrs |
| 21163 | CEFBS_IsThumb2, // t2ADDri |
| 21164 | CEFBS_IsThumb2, // t2ADDri12 |
| 21165 | CEFBS_IsThumb2, // t2ADDrr |
| 21166 | CEFBS_IsThumb2, // t2ADDrs |
| 21167 | CEFBS_IsThumb2, // t2ADDspImm |
| 21168 | CEFBS_IsThumb2, // t2ADDspImm12 |
| 21169 | CEFBS_IsThumb2, // t2ADR |
| 21170 | CEFBS_IsThumb2, // t2ANDri |
| 21171 | CEFBS_IsThumb2, // t2ANDrr |
| 21172 | CEFBS_IsThumb2, // t2ANDrs |
| 21173 | CEFBS_IsThumb2, // t2ASRri |
| 21174 | CEFBS_IsThumb2, // t2ASRrr |
| 21175 | CEFBS_IsThumb2, // t2ASRs1 |
| 21176 | CEFBS_HasV7_IsMClass, // t2AUT |
| 21177 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, // t2AUTG |
| 21178 | CEFBS_IsThumb_HasV8MBaseline, // t2B |
| 21179 | CEFBS_IsThumb2, // t2BFC |
| 21180 | CEFBS_IsThumb2, // t2BFI |
| 21181 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLi |
| 21182 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFLr |
| 21183 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFi |
| 21184 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFic |
| 21185 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2BFr |
| 21186 | CEFBS_IsThumb2, // t2BICri |
| 21187 | CEFBS_IsThumb2, // t2BICrr |
| 21188 | CEFBS_IsThumb2, // t2BICrs |
| 21189 | CEFBS_HasV7_IsMClass, // t2BTI |
| 21190 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, // t2BXAUT |
| 21191 | CEFBS_IsThumb2_IsNotMClass, // t2BXJ |
| 21192 | CEFBS_IsThumb2, // t2Bcc |
| 21193 | CEFBS_IsThumb2_PreV8, // t2CDP |
| 21194 | CEFBS_IsThumb2_PreV8, // t2CDP2 |
| 21195 | CEFBS_IsThumb_HasV7Clrex, // t2CLREX |
| 21196 | CEFBS_HasV8_1MMainline, // t2CLRM |
| 21197 | CEFBS_IsThumb2, // t2CLZ |
| 21198 | CEFBS_IsThumb2, // t2CMNri |
| 21199 | CEFBS_IsThumb2, // t2CMNrr |
| 21200 | CEFBS_IsThumb2, // t2CMNrs |
| 21201 | CEFBS_IsThumb2, // t2CMPri |
| 21202 | CEFBS_IsThumb2, // t2CMPrr |
| 21203 | CEFBS_IsThumb2, // t2CMPrs |
| 21204 | CEFBS_IsThumb2_IsNotMClass, // t2CPS1p |
| 21205 | CEFBS_IsThumb2_IsNotMClass, // t2CPS2p |
| 21206 | CEFBS_IsThumb2_IsNotMClass, // t2CPS3p |
| 21207 | CEFBS_IsThumb2_HasCRC, // t2CRC32B |
| 21208 | CEFBS_IsThumb2_HasCRC, // t2CRC32CB |
| 21209 | CEFBS_IsThumb2_HasCRC, // t2CRC32CH |
| 21210 | CEFBS_IsThumb2_HasCRC, // t2CRC32CW |
| 21211 | CEFBS_IsThumb2_HasCRC, // t2CRC32H |
| 21212 | CEFBS_IsThumb2_HasCRC, // t2CRC32W |
| 21213 | CEFBS_HasV8_1MMainline, // t2CSEL |
| 21214 | CEFBS_HasV8_1MMainline, // t2CSINC |
| 21215 | CEFBS_HasV8_1MMainline, // t2CSINV |
| 21216 | CEFBS_HasV8_1MMainline, // t2CSNEG |
| 21217 | CEFBS_IsThumb2, // t2DBG |
| 21218 | CEFBS_IsThumb2_HasV8, // t2DCPS1 |
| 21219 | CEFBS_IsThumb2_HasV8, // t2DCPS2 |
| 21220 | CEFBS_IsThumb2_HasV8, // t2DCPS3 |
| 21221 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2DLS |
| 21222 | CEFBS_IsThumb_HasDB, // t2DMB |
| 21223 | CEFBS_IsThumb_HasDB, // t2DSB |
| 21224 | CEFBS_IsThumb2, // t2EORri |
| 21225 | CEFBS_IsThumb2, // t2EORrr |
| 21226 | CEFBS_IsThumb2, // t2EORrs |
| 21227 | CEFBS_IsThumb2, // t2HINT |
| 21228 | CEFBS_IsThumb2_HasVirtualization, // t2HVC |
| 21229 | CEFBS_IsThumb_HasDB, // t2ISB |
| 21230 | CEFBS_IsThumb2, // t2IT |
| 21231 | CEFBS_IsThumb2_HasVFP2, // t2Int_eh_sjlj_setjmp |
| 21232 | CEFBS_IsThumb2, // t2Int_eh_sjlj_setjmp_nofp |
| 21233 | CEFBS_IsThumb_HasAcquireRelease, // t2LDA |
| 21234 | CEFBS_IsThumb_HasAcquireRelease, // t2LDAB |
| 21235 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEX |
| 21236 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXB |
| 21237 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2LDAEXD |
| 21238 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2LDAEXH |
| 21239 | CEFBS_IsThumb_HasAcquireRelease, // t2LDAH |
| 21240 | CEFBS_PreV8_IsThumb2, // t2LDC2L_OFFSET |
| 21241 | CEFBS_PreV8_IsThumb2, // t2LDC2L_OPTION |
| 21242 | CEFBS_PreV8_IsThumb2, // t2LDC2L_POST |
| 21243 | CEFBS_PreV8_IsThumb2, // t2LDC2L_PRE |
| 21244 | CEFBS_PreV8_IsThumb2, // t2LDC2_OFFSET |
| 21245 | CEFBS_PreV8_IsThumb2, // t2LDC2_OPTION |
| 21246 | CEFBS_PreV8_IsThumb2, // t2LDC2_POST |
| 21247 | CEFBS_PreV8_IsThumb2, // t2LDC2_PRE |
| 21248 | CEFBS_IsThumb2, // t2LDCL_OFFSET |
| 21249 | CEFBS_IsThumb2, // t2LDCL_OPTION |
| 21250 | CEFBS_IsThumb2, // t2LDCL_POST |
| 21251 | CEFBS_IsThumb2, // t2LDCL_PRE |
| 21252 | CEFBS_IsThumb2, // t2LDC_OFFSET |
| 21253 | CEFBS_IsThumb2, // t2LDC_OPTION |
| 21254 | CEFBS_IsThumb2, // t2LDC_POST |
| 21255 | CEFBS_IsThumb2, // t2LDC_PRE |
| 21256 | CEFBS_IsThumb2, // t2LDMDB |
| 21257 | CEFBS_IsThumb2, // t2LDMDB_UPD |
| 21258 | CEFBS_IsThumb2, // t2LDMIA |
| 21259 | CEFBS_IsThumb2, // t2LDMIA_UPD |
| 21260 | CEFBS_IsThumb2, // t2LDRBT |
| 21261 | CEFBS_IsThumb2, // t2LDRB_POST |
| 21262 | CEFBS_IsThumb2, // t2LDRB_PRE |
| 21263 | CEFBS_IsThumb2, // t2LDRBi12 |
| 21264 | CEFBS_IsThumb2, // t2LDRBi8 |
| 21265 | CEFBS_IsThumb2, // t2LDRBpci |
| 21266 | CEFBS_IsThumb2, // t2LDRBs |
| 21267 | CEFBS_IsThumb2, // t2LDRD_POST |
| 21268 | CEFBS_IsThumb2, // t2LDRD_PRE |
| 21269 | CEFBS_IsThumb2, // t2LDRDi8 |
| 21270 | CEFBS_IsThumb_HasV8MBaseline, // t2LDREX |
| 21271 | CEFBS_IsThumb_HasV8MBaseline, // t2LDREXB |
| 21272 | CEFBS_IsThumb2_IsNotMClass, // t2LDREXD |
| 21273 | CEFBS_IsThumb_HasV8MBaseline, // t2LDREXH |
| 21274 | CEFBS_IsThumb2, // t2LDRHT |
| 21275 | CEFBS_IsThumb2, // t2LDRH_POST |
| 21276 | CEFBS_IsThumb2, // t2LDRH_PRE |
| 21277 | CEFBS_IsThumb2, // t2LDRHi12 |
| 21278 | CEFBS_IsThumb2, // t2LDRHi8 |
| 21279 | CEFBS_IsThumb2, // t2LDRHpci |
| 21280 | CEFBS_IsThumb2, // t2LDRHs |
| 21281 | CEFBS_IsThumb2, // t2LDRSBT |
| 21282 | CEFBS_IsThumb2, // t2LDRSB_POST |
| 21283 | CEFBS_IsThumb2, // t2LDRSB_PRE |
| 21284 | CEFBS_IsThumb2, // t2LDRSBi12 |
| 21285 | CEFBS_IsThumb2, // t2LDRSBi8 |
| 21286 | CEFBS_IsThumb2, // t2LDRSBpci |
| 21287 | CEFBS_IsThumb2, // t2LDRSBs |
| 21288 | CEFBS_IsThumb2, // t2LDRSHT |
| 21289 | CEFBS_IsThumb2, // t2LDRSH_POST |
| 21290 | CEFBS_IsThumb2, // t2LDRSH_PRE |
| 21291 | CEFBS_IsThumb2, // t2LDRSHi12 |
| 21292 | CEFBS_IsThumb2, // t2LDRSHi8 |
| 21293 | CEFBS_IsThumb2, // t2LDRSHpci |
| 21294 | CEFBS_IsThumb2, // t2LDRSHs |
| 21295 | CEFBS_IsThumb2, // t2LDRT |
| 21296 | CEFBS_IsThumb2, // t2LDR_POST |
| 21297 | CEFBS_IsThumb2, // t2LDR_PRE |
| 21298 | CEFBS_IsThumb2, // t2LDRi12 |
| 21299 | CEFBS_IsThumb2, // t2LDRi8 |
| 21300 | CEFBS_IsThumb2, // t2LDRpci |
| 21301 | CEFBS_IsThumb2, // t2LDRs |
| 21302 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LE |
| 21303 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2LEUpdate |
| 21304 | CEFBS_IsThumb2, // t2LSLri |
| 21305 | CEFBS_IsThumb2, // t2LSLrr |
| 21306 | CEFBS_IsThumb2, // t2LSRri |
| 21307 | CEFBS_IsThumb2, // t2LSRrr |
| 21308 | CEFBS_IsThumb2, // t2LSRs1 |
| 21309 | CEFBS_IsThumb2, // t2MCR |
| 21310 | CEFBS_IsThumb2_PreV8, // t2MCR2 |
| 21311 | CEFBS_IsThumb2, // t2MCRR |
| 21312 | CEFBS_IsThumb2_PreV8, // t2MCRR2 |
| 21313 | CEFBS_IsThumb2, // t2MLA |
| 21314 | CEFBS_IsThumb2, // t2MLS |
| 21315 | CEFBS_IsThumb_HasV8MBaseline, // t2MOVTi16 |
| 21316 | CEFBS_IsThumb2, // t2MOVi |
| 21317 | CEFBS_IsThumb_HasV8MBaseline, // t2MOVi16 |
| 21318 | CEFBS_IsThumb2, // t2MOVr |
| 21319 | CEFBS_IsThumb2, // t2MRC |
| 21320 | CEFBS_IsThumb2_PreV8, // t2MRC2 |
| 21321 | CEFBS_IsThumb2, // t2MRRC |
| 21322 | CEFBS_IsThumb2_PreV8, // t2MRRC2 |
| 21323 | CEFBS_IsThumb2_IsNotMClass, // t2MRS_AR |
| 21324 | CEFBS_IsThumb_IsMClass, // t2MRS_M |
| 21325 | CEFBS_IsThumb_HasVirtualization, // t2MRSbanked |
| 21326 | CEFBS_IsThumb2_IsNotMClass, // t2MRSsys_AR |
| 21327 | CEFBS_IsThumb2_IsNotMClass, // t2MSR_AR |
| 21328 | CEFBS_IsThumb_IsMClass, // t2MSR_M |
| 21329 | CEFBS_IsThumb_HasVirtualization, // t2MSRbanked |
| 21330 | CEFBS_IsThumb2, // t2MUL |
| 21331 | CEFBS_IsThumb2, // t2MVNi |
| 21332 | CEFBS_IsThumb2, // t2MVNr |
| 21333 | CEFBS_IsThumb2, // t2MVNs |
| 21334 | CEFBS_IsThumb2, // t2ORNri |
| 21335 | CEFBS_IsThumb2, // t2ORNrr |
| 21336 | CEFBS_IsThumb2, // t2ORNrs |
| 21337 | CEFBS_IsThumb2, // t2ORRri |
| 21338 | CEFBS_IsThumb2, // t2ORRrr |
| 21339 | CEFBS_IsThumb2, // t2ORRrs |
| 21340 | CEFBS_HasV7_IsMClass, // t2PAC |
| 21341 | CEFBS_HasV7_IsMClass, // t2PACBTI |
| 21342 | CEFBS_IsThumb2_HasV8_1MMainline_HasPACBTI, // t2PACG |
| 21343 | CEFBS_HasDSP_IsThumb2, // t2PKHBT |
| 21344 | CEFBS_HasDSP_IsThumb2, // t2PKHTB |
| 21345 | CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi12 |
| 21346 | CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWi8 |
| 21347 | CEFBS_IsThumb2_HasV7_HasMP, // t2PLDWs |
| 21348 | CEFBS_IsThumb2, // t2PLDi12 |
| 21349 | CEFBS_IsThumb2, // t2PLDi8 |
| 21350 | CEFBS_IsThumb2, // t2PLDpci |
| 21351 | CEFBS_IsThumb2, // t2PLDs |
| 21352 | CEFBS_IsThumb2_HasV7, // t2PLIi12 |
| 21353 | CEFBS_IsThumb2_HasV7, // t2PLIi8 |
| 21354 | CEFBS_IsThumb2_HasV7, // t2PLIpci |
| 21355 | CEFBS_IsThumb2_HasV7, // t2PLIs |
| 21356 | CEFBS_IsThumb2_HasDSP, // t2QADD |
| 21357 | CEFBS_IsThumb2_HasDSP, // t2QADD16 |
| 21358 | CEFBS_IsThumb2_HasDSP, // t2QADD8 |
| 21359 | CEFBS_IsThumb2_HasDSP, // t2QASX |
| 21360 | CEFBS_IsThumb2_HasDSP, // t2QDADD |
| 21361 | CEFBS_IsThumb2_HasDSP, // t2QDSUB |
| 21362 | CEFBS_IsThumb2_HasDSP, // t2QSAX |
| 21363 | CEFBS_IsThumb2_HasDSP, // t2QSUB |
| 21364 | CEFBS_IsThumb2_HasDSP, // t2QSUB16 |
| 21365 | CEFBS_IsThumb2_HasDSP, // t2QSUB8 |
| 21366 | CEFBS_IsThumb2, // t2RBIT |
| 21367 | CEFBS_IsThumb2, // t2REV |
| 21368 | CEFBS_IsThumb2, // t2REV16 |
| 21369 | CEFBS_IsThumb2, // t2REVSH |
| 21370 | CEFBS_IsThumb2_IsNotMClass, // t2RFEDB |
| 21371 | CEFBS_IsThumb2_IsNotMClass, // t2RFEDBW |
| 21372 | CEFBS_IsThumb2_IsNotMClass, // t2RFEIA |
| 21373 | CEFBS_IsThumb2_IsNotMClass, // t2RFEIAW |
| 21374 | CEFBS_IsThumb2, // t2RORri |
| 21375 | CEFBS_IsThumb2, // t2RORrr |
| 21376 | CEFBS_IsThumb2, // t2RRX |
| 21377 | CEFBS_IsThumb2, // t2RSBri |
| 21378 | CEFBS_IsThumb2, // t2RSBrr |
| 21379 | CEFBS_IsThumb2, // t2RSBrs |
| 21380 | CEFBS_IsThumb2_HasDSP, // t2SADD16 |
| 21381 | CEFBS_IsThumb2_HasDSP, // t2SADD8 |
| 21382 | CEFBS_IsThumb2_HasDSP, // t2SASX |
| 21383 | CEFBS_IsThumb2_HasSB, // t2SB |
| 21384 | CEFBS_IsThumb2, // t2SBCri |
| 21385 | CEFBS_IsThumb2, // t2SBCrr |
| 21386 | CEFBS_IsThumb2, // t2SBCrs |
| 21387 | CEFBS_IsThumb2, // t2SBFX |
| 21388 | CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2SDIV |
| 21389 | CEFBS_IsThumb2_HasDSP, // t2SEL |
| 21390 | CEFBS_IsThumb2_HasV8_HasV8_1a, // t2SETPAN |
| 21391 | CEFBS_Has8MSecExt, // t2SG |
| 21392 | CEFBS_IsThumb2_HasDSP, // t2SHADD16 |
| 21393 | CEFBS_IsThumb2_HasDSP, // t2SHADD8 |
| 21394 | CEFBS_IsThumb2_HasDSP, // t2SHASX |
| 21395 | CEFBS_IsThumb2_HasDSP, // t2SHSAX |
| 21396 | CEFBS_IsThumb2_HasDSP, // t2SHSUB16 |
| 21397 | CEFBS_IsThumb2_HasDSP, // t2SHSUB8 |
| 21398 | CEFBS_IsThumb2_HasTrustZone, // t2SMC |
| 21399 | CEFBS_IsThumb2_HasDSP, // t2SMLABB |
| 21400 | CEFBS_IsThumb2_HasDSP, // t2SMLABT |
| 21401 | CEFBS_IsThumb2_HasDSP, // t2SMLAD |
| 21402 | CEFBS_IsThumb2_HasDSP, // t2SMLADX |
| 21403 | CEFBS_IsThumb2, // t2SMLAL |
| 21404 | CEFBS_IsThumb2_HasDSP, // t2SMLALBB |
| 21405 | CEFBS_IsThumb2_HasDSP, // t2SMLALBT |
| 21406 | CEFBS_IsThumb2_HasDSP, // t2SMLALD |
| 21407 | CEFBS_IsThumb2_HasDSP, // t2SMLALDX |
| 21408 | CEFBS_IsThumb2_HasDSP, // t2SMLALTB |
| 21409 | CEFBS_IsThumb2_HasDSP, // t2SMLALTT |
| 21410 | CEFBS_IsThumb2_HasDSP, // t2SMLATB |
| 21411 | CEFBS_IsThumb2_HasDSP, // t2SMLATT |
| 21412 | CEFBS_IsThumb2_HasDSP, // t2SMLAWB |
| 21413 | CEFBS_IsThumb2_HasDSP, // t2SMLAWT |
| 21414 | CEFBS_IsThumb2_HasDSP, // t2SMLSD |
| 21415 | CEFBS_IsThumb2_HasDSP, // t2SMLSDX |
| 21416 | CEFBS_IsThumb2_HasDSP, // t2SMLSLD |
| 21417 | CEFBS_IsThumb2_HasDSP, // t2SMLSLDX |
| 21418 | CEFBS_IsThumb2_HasDSP, // t2SMMLA |
| 21419 | CEFBS_IsThumb2_HasDSP, // t2SMMLAR |
| 21420 | CEFBS_IsThumb2_HasDSP, // t2SMMLS |
| 21421 | CEFBS_IsThumb2_HasDSP, // t2SMMLSR |
| 21422 | CEFBS_IsThumb2_HasDSP, // t2SMMUL |
| 21423 | CEFBS_IsThumb2_HasDSP, // t2SMMULR |
| 21424 | CEFBS_IsThumb2_HasDSP, // t2SMUAD |
| 21425 | CEFBS_IsThumb2_HasDSP, // t2SMUADX |
| 21426 | CEFBS_IsThumb2_HasDSP, // t2SMULBB |
| 21427 | CEFBS_IsThumb2_HasDSP, // t2SMULBT |
| 21428 | CEFBS_IsThumb2, // t2SMULL |
| 21429 | CEFBS_IsThumb2_HasDSP, // t2SMULTB |
| 21430 | CEFBS_IsThumb2_HasDSP, // t2SMULTT |
| 21431 | CEFBS_IsThumb2_HasDSP, // t2SMULWB |
| 21432 | CEFBS_IsThumb2_HasDSP, // t2SMULWT |
| 21433 | CEFBS_IsThumb2_HasDSP, // t2SMUSD |
| 21434 | CEFBS_IsThumb2_HasDSP, // t2SMUSDX |
| 21435 | CEFBS_IsThumb2_IsNotMClass, // t2SRSDB |
| 21436 | CEFBS_IsThumb2_IsNotMClass, // t2SRSDB_UPD |
| 21437 | CEFBS_IsThumb2_IsNotMClass, // t2SRSIA |
| 21438 | CEFBS_IsThumb2_IsNotMClass, // t2SRSIA_UPD |
| 21439 | CEFBS_IsThumb2, // t2SSAT |
| 21440 | CEFBS_IsThumb2_HasDSP, // t2SSAT16 |
| 21441 | CEFBS_IsThumb2_HasDSP, // t2SSAX |
| 21442 | CEFBS_IsThumb2_HasDSP, // t2SSUB16 |
| 21443 | CEFBS_IsThumb2_HasDSP, // t2SSUB8 |
| 21444 | CEFBS_PreV8_IsThumb2, // t2STC2L_OFFSET |
| 21445 | CEFBS_PreV8_IsThumb2, // t2STC2L_OPTION |
| 21446 | CEFBS_PreV8_IsThumb2, // t2STC2L_POST |
| 21447 | CEFBS_PreV8_IsThumb2, // t2STC2L_PRE |
| 21448 | CEFBS_PreV8_IsThumb2, // t2STC2_OFFSET |
| 21449 | CEFBS_PreV8_IsThumb2, // t2STC2_OPTION |
| 21450 | CEFBS_PreV8_IsThumb2, // t2STC2_POST |
| 21451 | CEFBS_PreV8_IsThumb2, // t2STC2_PRE |
| 21452 | CEFBS_IsThumb2, // t2STCL_OFFSET |
| 21453 | CEFBS_IsThumb2, // t2STCL_OPTION |
| 21454 | CEFBS_IsThumb2, // t2STCL_POST |
| 21455 | CEFBS_IsThumb2, // t2STCL_PRE |
| 21456 | CEFBS_IsThumb2, // t2STC_OFFSET |
| 21457 | CEFBS_IsThumb2, // t2STC_OPTION |
| 21458 | CEFBS_IsThumb2, // t2STC_POST |
| 21459 | CEFBS_IsThumb2, // t2STC_PRE |
| 21460 | CEFBS_IsThumb_HasAcquireRelease, // t2STL |
| 21461 | CEFBS_IsThumb_HasAcquireRelease, // t2STLB |
| 21462 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEX |
| 21463 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXB |
| 21464 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex_IsNotMClass, // t2STLEXD |
| 21465 | CEFBS_IsThumb_HasAcquireRelease_HasV7Clrex, // t2STLEXH |
| 21466 | CEFBS_IsThumb_HasAcquireRelease, // t2STLH |
| 21467 | CEFBS_IsThumb2, // t2STMDB |
| 21468 | CEFBS_IsThumb2, // t2STMDB_UPD |
| 21469 | CEFBS_IsThumb2, // t2STMIA |
| 21470 | CEFBS_IsThumb2, // t2STMIA_UPD |
| 21471 | CEFBS_IsThumb2, // t2STRBT |
| 21472 | CEFBS_IsThumb2, // t2STRB_POST |
| 21473 | CEFBS_IsThumb2, // t2STRB_PRE |
| 21474 | CEFBS_IsThumb2, // t2STRBi12 |
| 21475 | CEFBS_IsThumb2, // t2STRBi8 |
| 21476 | CEFBS_IsThumb2, // t2STRBs |
| 21477 | CEFBS_IsThumb2, // t2STRD_POST |
| 21478 | CEFBS_IsThumb2, // t2STRD_PRE |
| 21479 | CEFBS_IsThumb2, // t2STRDi8 |
| 21480 | CEFBS_IsThumb_HasV8MBaseline, // t2STREX |
| 21481 | CEFBS_IsThumb_HasV8MBaseline, // t2STREXB |
| 21482 | CEFBS_IsThumb2_IsNotMClass, // t2STREXD |
| 21483 | CEFBS_IsThumb_HasV8MBaseline, // t2STREXH |
| 21484 | CEFBS_IsThumb2, // t2STRHT |
| 21485 | CEFBS_IsThumb2, // t2STRH_POST |
| 21486 | CEFBS_IsThumb2, // t2STRH_PRE |
| 21487 | CEFBS_IsThumb2, // t2STRHi12 |
| 21488 | CEFBS_IsThumb2, // t2STRHi8 |
| 21489 | CEFBS_IsThumb2, // t2STRHs |
| 21490 | CEFBS_IsThumb2, // t2STRT |
| 21491 | CEFBS_IsThumb2, // t2STR_POST |
| 21492 | CEFBS_IsThumb2, // t2STR_PRE |
| 21493 | CEFBS_IsThumb2, // t2STRi12 |
| 21494 | CEFBS_IsThumb2, // t2STRi8 |
| 21495 | CEFBS_IsThumb2, // t2STRs |
| 21496 | CEFBS_IsThumb2_IsNotMClass, // t2SUBS_PC_LR |
| 21497 | CEFBS_IsThumb2, // t2SUBri |
| 21498 | CEFBS_IsThumb2, // t2SUBri12 |
| 21499 | CEFBS_IsThumb2, // t2SUBrr |
| 21500 | CEFBS_IsThumb2, // t2SUBrs |
| 21501 | CEFBS_IsThumb2, // t2SUBspImm |
| 21502 | CEFBS_IsThumb2, // t2SUBspImm12 |
| 21503 | CEFBS_HasDSP_IsThumb2, // t2SXTAB |
| 21504 | CEFBS_HasDSP_IsThumb2, // t2SXTAB16 |
| 21505 | CEFBS_HasDSP_IsThumb2, // t2SXTAH |
| 21506 | CEFBS_IsThumb2, // t2SXTB |
| 21507 | CEFBS_HasDSP_IsThumb2, // t2SXTB16 |
| 21508 | CEFBS_IsThumb2, // t2SXTH |
| 21509 | CEFBS_IsThumb2, // t2TBB |
| 21510 | CEFBS_IsThumb2, // t2TBH |
| 21511 | CEFBS_IsThumb2, // t2TEQri |
| 21512 | CEFBS_IsThumb2, // t2TEQrr |
| 21513 | CEFBS_IsThumb2, // t2TEQrs |
| 21514 | CEFBS_IsThumb_HasV8_4a, // t2TSB |
| 21515 | CEFBS_IsThumb2, // t2TSTri |
| 21516 | CEFBS_IsThumb2, // t2TSTrr |
| 21517 | CEFBS_IsThumb2, // t2TSTrs |
| 21518 | CEFBS_IsThumb_Has8MSecExt, // t2TT |
| 21519 | CEFBS_IsThumb_Has8MSecExt, // t2TTA |
| 21520 | CEFBS_IsThumb_Has8MSecExt, // t2TTAT |
| 21521 | CEFBS_IsThumb_Has8MSecExt, // t2TTT |
| 21522 | CEFBS_IsThumb2_HasDSP, // t2UADD16 |
| 21523 | CEFBS_IsThumb2_HasDSP, // t2UADD8 |
| 21524 | CEFBS_IsThumb2_HasDSP, // t2UASX |
| 21525 | CEFBS_IsThumb2, // t2UBFX |
| 21526 | CEFBS_IsThumb2, // t2UDF |
| 21527 | CEFBS_HasDivideInThumb_IsThumb_HasV8MBaseline, // t2UDIV |
| 21528 | CEFBS_IsThumb2_HasDSP, // t2UHADD16 |
| 21529 | CEFBS_IsThumb2_HasDSP, // t2UHADD8 |
| 21530 | CEFBS_IsThumb2_HasDSP, // t2UHASX |
| 21531 | CEFBS_IsThumb2_HasDSP, // t2UHSAX |
| 21532 | CEFBS_IsThumb2_HasDSP, // t2UHSUB16 |
| 21533 | CEFBS_IsThumb2_HasDSP, // t2UHSUB8 |
| 21534 | CEFBS_IsThumb2_HasDSP, // t2UMAAL |
| 21535 | CEFBS_IsThumb2, // t2UMLAL |
| 21536 | CEFBS_IsThumb2, // t2UMULL |
| 21537 | CEFBS_IsThumb2_HasDSP, // t2UQADD16 |
| 21538 | CEFBS_IsThumb2_HasDSP, // t2UQADD8 |
| 21539 | CEFBS_IsThumb2_HasDSP, // t2UQASX |
| 21540 | CEFBS_IsThumb2_HasDSP, // t2UQSAX |
| 21541 | CEFBS_IsThumb2_HasDSP, // t2UQSUB16 |
| 21542 | CEFBS_IsThumb2_HasDSP, // t2UQSUB8 |
| 21543 | CEFBS_IsThumb2_HasDSP, // t2USAD8 |
| 21544 | CEFBS_IsThumb2_HasDSP, // t2USADA8 |
| 21545 | CEFBS_IsThumb2, // t2USAT |
| 21546 | CEFBS_IsThumb2_HasDSP, // t2USAT16 |
| 21547 | CEFBS_IsThumb2_HasDSP, // t2USAX |
| 21548 | CEFBS_IsThumb2_HasDSP, // t2USUB16 |
| 21549 | CEFBS_IsThumb2_HasDSP, // t2USUB8 |
| 21550 | CEFBS_HasDSP_IsThumb2, // t2UXTAB |
| 21551 | CEFBS_HasDSP_IsThumb2, // t2UXTAB16 |
| 21552 | CEFBS_HasDSP_IsThumb2, // t2UXTAH |
| 21553 | CEFBS_IsThumb2, // t2UXTB |
| 21554 | CEFBS_HasDSP_IsThumb2, // t2UXTB16 |
| 21555 | CEFBS_IsThumb2, // t2UXTH |
| 21556 | CEFBS_IsThumb2_HasV8_1MMainline_HasLOB, // t2WLS |
| 21557 | CEFBS_IsThumb, // tADC |
| 21558 | CEFBS_IsThumb, // tADDhirr |
| 21559 | CEFBS_IsThumb, // tADDi3 |
| 21560 | CEFBS_IsThumb, // tADDi8 |
| 21561 | CEFBS_IsThumb, // tADDrSP |
| 21562 | CEFBS_IsThumb, // tADDrSPi |
| 21563 | CEFBS_IsThumb, // tADDrr |
| 21564 | CEFBS_IsThumb, // tADDspi |
| 21565 | CEFBS_IsThumb, // tADDspr |
| 21566 | CEFBS_IsThumb, // tADR |
| 21567 | CEFBS_IsThumb, // tAND |
| 21568 | CEFBS_IsThumb, // tASRri |
| 21569 | CEFBS_IsThumb, // tASRrr |
| 21570 | CEFBS_IsThumb, // tB |
| 21571 | CEFBS_IsThumb, // tBIC |
| 21572 | CEFBS_IsThumb, // tBKPT |
| 21573 | CEFBS_IsThumb, // tBL |
| 21574 | CEFBS_IsThumb_Has8MSecExt, // tBLXNSr |
| 21575 | CEFBS_IsThumb_HasV5T_IsNotMClass, // tBLXi |
| 21576 | CEFBS_IsThumb_HasV5T, // tBLXr |
| 21577 | CEFBS_IsThumb, // tBX |
| 21578 | CEFBS_IsThumb_Has8MSecExt, // tBXNS |
| 21579 | CEFBS_IsThumb, // tBcc |
| 21580 | CEFBS_IsThumb_HasV8MBaseline, // tCBNZ |
| 21581 | CEFBS_IsThumb_HasV8MBaseline, // tCBZ |
| 21582 | CEFBS_IsThumb, // tCMN |
| 21583 | CEFBS_IsThumb, // tCMPhir |
| 21584 | CEFBS_IsThumb, // tCMPi8 |
| 21585 | CEFBS_IsThumb, // tCMPr |
| 21586 | CEFBS_IsThumb, // tCPS |
| 21587 | CEFBS_IsThumb, // tEOR |
| 21588 | CEFBS_IsThumb_HasV6M, // tHINT |
| 21589 | CEFBS_IsThumb_HasV8, // tHLT |
| 21590 | CEFBS_IsThumb, // tInt_WIN_eh_sjlj_longjmp |
| 21591 | CEFBS_IsThumb, // tInt_eh_sjlj_longjmp |
| 21592 | CEFBS_IsThumb, // tInt_eh_sjlj_setjmp |
| 21593 | CEFBS_IsThumb, // tLDMIA |
| 21594 | CEFBS_IsThumb, // tLDRBi |
| 21595 | CEFBS_IsThumb, // tLDRBr |
| 21596 | CEFBS_IsThumb, // tLDRHi |
| 21597 | CEFBS_IsThumb, // tLDRHr |
| 21598 | CEFBS_IsThumb, // tLDRSB |
| 21599 | CEFBS_IsThumb, // tLDRSH |
| 21600 | CEFBS_IsThumb, // tLDRi |
| 21601 | CEFBS_IsThumb, // tLDRpci |
| 21602 | CEFBS_IsThumb, // tLDRr |
| 21603 | CEFBS_IsThumb, // tLDRspi |
| 21604 | CEFBS_IsThumb, // tLSLri |
| 21605 | CEFBS_IsThumb, // tLSLrr |
| 21606 | CEFBS_IsThumb, // tLSRri |
| 21607 | CEFBS_IsThumb, // tLSRrr |
| 21608 | CEFBS_IsThumb, // tMOVSr |
| 21609 | CEFBS_IsThumb, // tMOVi8 |
| 21610 | CEFBS_IsThumb, // tMOVr |
| 21611 | CEFBS_IsThumb, // tMUL |
| 21612 | CEFBS_IsThumb, // tMVN |
| 21613 | CEFBS_IsThumb, // tORR |
| 21614 | CEFBS_IsThumb, // tPICADD |
| 21615 | CEFBS_IsThumb, // tPOP |
| 21616 | CEFBS_IsThumb, // tPUSH |
| 21617 | CEFBS_IsThumb_HasV6, // tREV |
| 21618 | CEFBS_IsThumb_HasV6, // tREV16 |
| 21619 | CEFBS_IsThumb_HasV6, // tREVSH |
| 21620 | CEFBS_IsThumb, // tROR |
| 21621 | CEFBS_IsThumb, // tRSB |
| 21622 | CEFBS_IsThumb, // tSBC |
| 21623 | CEFBS_IsThumb_IsNotMClass, // tSETEND |
| 21624 | CEFBS_IsThumb, // tSTMIA_UPD |
| 21625 | CEFBS_IsThumb, // tSTRBi |
| 21626 | CEFBS_IsThumb, // tSTRBr |
| 21627 | CEFBS_IsThumb, // tSTRHi |
| 21628 | CEFBS_IsThumb, // tSTRHr |
| 21629 | CEFBS_IsThumb, // tSTRi |
| 21630 | CEFBS_IsThumb, // tSTRr |
| 21631 | CEFBS_IsThumb, // tSTRspi |
| 21632 | CEFBS_IsThumb, // tSUBi3 |
| 21633 | CEFBS_IsThumb, // tSUBi8 |
| 21634 | CEFBS_IsThumb, // tSUBrr |
| 21635 | CEFBS_IsThumb, // tSUBspi |
| 21636 | CEFBS_IsThumb, // tSVC |
| 21637 | CEFBS_IsThumb_HasV6, // tSXTB |
| 21638 | CEFBS_IsThumb_HasV6, // tSXTH |
| 21639 | CEFBS_IsThumb, // tTRAP |
| 21640 | CEFBS_IsThumb, // tTST |
| 21641 | CEFBS_IsThumb, // tUDF |
| 21642 | CEFBS_IsThumb_HasV6, // tUXTB |
| 21643 | CEFBS_IsThumb_HasV6, // tUXTH |
| 21644 | CEFBS_IsThumb, // t__brkdiv0 |
| 21645 | }; |
| 21646 | |
| 21647 | assert(Opcode < 4534); |
| 21648 | return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
| 21649 | } |
| 21650 | |
| 21651 | |
| 21652 | } // namespace llvm::ARM_MC |
| 21653 | |
| 21654 | #endif // GET_COMPUTE_FEATURES |
| 21655 | |
| 21656 | #ifdef GET_AVAILABLE_OPCODE_CHECKER |
| 21657 | #undef GET_AVAILABLE_OPCODE_CHECKER |
| 21658 | |
| 21659 | namespace llvm::ARM_MC { |
| 21660 | |
| 21661 | bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { |
| 21662 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 21663 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 21664 | FeatureBitset MissingFeatures = |
| 21665 | (AvailableFeatures & RequiredFeatures) ^ |
| 21666 | RequiredFeatures; |
| 21667 | return !MissingFeatures.any(); |
| 21668 | } |
| 21669 | |
| 21670 | } // namespace llvm::ARM_MC |
| 21671 | |
| 21672 | #endif // GET_AVAILABLE_OPCODE_CHECKER |
| 21673 | |
| 21674 | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| 21675 | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| 21676 | |
| 21677 | #include <sstream> |
| 21678 | |
| 21679 | namespace llvm::ARM_MC { |
| 21680 | |
| 21681 | #ifndef NDEBUG |
| 21682 | static const char *SubtargetFeatureNames[] = { |
| 21683 | "Feature_Has8MSecExt", |
| 21684 | "Feature_HasAES", |
| 21685 | "Feature_HasAcquireRelease", |
| 21686 | "Feature_HasBF16", |
| 21687 | "Feature_HasCDE", |
| 21688 | "Feature_HasCLRBHB", |
| 21689 | "Feature_HasCRC", |
| 21690 | "Feature_HasCrypto", |
| 21691 | "Feature_HasDB", |
| 21692 | "Feature_HasDFB", |
| 21693 | "Feature_HasDPVFP", |
| 21694 | "Feature_HasDSP", |
| 21695 | "Feature_HasDivideInARM", |
| 21696 | "Feature_HasDivideInThumb", |
| 21697 | "Feature_HasDotProd", |
| 21698 | "Feature_HasFP16", |
| 21699 | "Feature_HasFP16FML", |
| 21700 | "Feature_HasFPARMv8", |
| 21701 | "Feature_HasFPRegs", |
| 21702 | "Feature_HasFPRegs16", |
| 21703 | "Feature_HasFPRegs64", |
| 21704 | "Feature_HasFPRegsV8_1M", |
| 21705 | "Feature_HasFullFP16", |
| 21706 | "Feature_HasLOB", |
| 21707 | "Feature_HasMP", |
| 21708 | "Feature_HasMVEFloat", |
| 21709 | "Feature_HasMVEInt", |
| 21710 | "Feature_HasMatMulInt8", |
| 21711 | "Feature_HasNEON", |
| 21712 | "Feature_HasNoFPRegs16", |
| 21713 | "Feature_HasPACBTI", |
| 21714 | "Feature_HasRAS", |
| 21715 | "Feature_HasSB", |
| 21716 | "Feature_HasSHA2", |
| 21717 | "Feature_HasTrustZone", |
| 21718 | "Feature_HasV4T", |
| 21719 | "Feature_HasV5T", |
| 21720 | "Feature_HasV5TE", |
| 21721 | "Feature_HasV6", |
| 21722 | "Feature_HasV6K", |
| 21723 | "Feature_HasV6M", |
| 21724 | "Feature_HasV6T2", |
| 21725 | "Feature_HasV7", |
| 21726 | "Feature_HasV7Clrex", |
| 21727 | "Feature_HasV8", |
| 21728 | "Feature_HasV8MBaseline", |
| 21729 | "Feature_HasV8MMainline", |
| 21730 | "Feature_HasV8_1MMainline", |
| 21731 | "Feature_HasV8_1a", |
| 21732 | "Feature_HasV8_2a", |
| 21733 | "Feature_HasV8_3a", |
| 21734 | "Feature_HasV8_4a", |
| 21735 | "Feature_HasV8_5a", |
| 21736 | "Feature_HasV8_6a", |
| 21737 | "Feature_HasV8_7a", |
| 21738 | "Feature_HasVFP2", |
| 21739 | "Feature_HasVFP3", |
| 21740 | "Feature_HasVFP4", |
| 21741 | "Feature_HasVirtualization", |
| 21742 | "Feature_IsARM", |
| 21743 | "Feature_IsMClass", |
| 21744 | "Feature_IsNotMClass", |
| 21745 | "Feature_IsThumb", |
| 21746 | "Feature_IsThumb2", |
| 21747 | "Feature_PreV8", |
| 21748 | "Feature_UseNegativeImmediates", |
| 21749 | nullptr |
| 21750 | }; |
| 21751 | |
| 21752 | #endif // NDEBUG |
| 21753 | |
| 21754 | void verifyInstructionPredicates( |
| 21755 | unsigned Opcode, const FeatureBitset &Features) { |
| 21756 | #ifndef NDEBUG |
| 21757 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 21758 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 21759 | FeatureBitset MissingFeatures = |
| 21760 | (AvailableFeatures & RequiredFeatures) ^ |
| 21761 | RequiredFeatures; |
| 21762 | if (MissingFeatures.any()) { |
| 21763 | std::ostringstream Msg; |
| 21764 | Msg << "Attempting to emit "<< &ARMInstrNameData[ARMInstrNameIndices[Opcode]] |
| 21765 | << " instruction but the "; |
| 21766 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| 21767 | if (MissingFeatures.test(i)) |
| 21768 | Msg << SubtargetFeatureNames[i] << " "; |
| 21769 | Msg << "predicate(s) are not met"; |
| 21770 | report_fatal_error(Msg.str().c_str()); |
| 21771 | } |
| 21772 | #endif // NDEBUG |
| 21773 | } |
| 21774 | |
| 21775 | } // namespace llvm::ARM_MC |
| 21776 | |
| 21777 | #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
| 21778 | |
| 21779 |
Generated while processing llvm_projects/llvm/lib/Target/ARM/A15SDOptimizer.cpp
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