1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12const MCRegisterClass &getARMMCRegisterClass(unsigned RC);
13namespace ARM {
14
15enum : unsigned {
16 NoRegister,
17 APSR = 1,
18 APSR_NZCV = 2,
19 CPSR = 3,
20 FPCXTNS = 4,
21 FPCXTS = 5,
22 FPEXC = 6,
23 FPINST = 7,
24 FPSCR = 8,
25 FPSCR_NZCV = 9,
26 FPSCR_NZCVQC = 10,
27 FPSCR_RM = 11,
28 FPSID = 12,
29 ITSTATE = 13,
30 LR = 14,
31 PC = 15,
32 RA_AUTH_CODE = 16,
33 SP = 17,
34 SPSR = 18,
35 VPR = 19,
36 ZR = 20,
37 D0 = 21,
38 D1 = 22,
39 D2 = 23,
40 D3 = 24,
41 D4 = 25,
42 D5 = 26,
43 D6 = 27,
44 D7 = 28,
45 D8 = 29,
46 D9 = 30,
47 D10 = 31,
48 D11 = 32,
49 D12 = 33,
50 D13 = 34,
51 D14 = 35,
52 D15 = 36,
53 D16 = 37,
54 D17 = 38,
55 D18 = 39,
56 D19 = 40,
57 D20 = 41,
58 D21 = 42,
59 D22 = 43,
60 D23 = 44,
61 D24 = 45,
62 D25 = 46,
63 D26 = 47,
64 D27 = 48,
65 D28 = 49,
66 D29 = 50,
67 D30 = 51,
68 D31 = 52,
69 FPINST2 = 53,
70 MVFR0 = 54,
71 MVFR1 = 55,
72 MVFR2 = 56,
73 P0 = 57,
74 Q0 = 58,
75 Q1 = 59,
76 Q2 = 60,
77 Q3 = 61,
78 Q4 = 62,
79 Q5 = 63,
80 Q6 = 64,
81 Q7 = 65,
82 Q8 = 66,
83 Q9 = 67,
84 Q10 = 68,
85 Q11 = 69,
86 Q12 = 70,
87 Q13 = 71,
88 Q14 = 72,
89 Q15 = 73,
90 R0 = 74,
91 R1 = 75,
92 R2 = 76,
93 R3 = 77,
94 R4 = 78,
95 R5 = 79,
96 R6 = 80,
97 R7 = 81,
98 R8 = 82,
99 R9 = 83,
100 R10 = 84,
101 R11 = 85,
102 R12 = 86,
103 S0 = 87,
104 S1 = 88,
105 S2 = 89,
106 S3 = 90,
107 S4 = 91,
108 S5 = 92,
109 S6 = 93,
110 S7 = 94,
111 S8 = 95,
112 S9 = 96,
113 S10 = 97,
114 S11 = 98,
115 S12 = 99,
116 S13 = 100,
117 S14 = 101,
118 S15 = 102,
119 S16 = 103,
120 S17 = 104,
121 S18 = 105,
122 S19 = 106,
123 S20 = 107,
124 S21 = 108,
125 S22 = 109,
126 S23 = 110,
127 S24 = 111,
128 S25 = 112,
129 S26 = 113,
130 S27 = 114,
131 S28 = 115,
132 S29 = 116,
133 S30 = 117,
134 S31 = 118,
135 D0_D2 = 119,
136 D1_D3 = 120,
137 D2_D4 = 121,
138 D3_D5 = 122,
139 D4_D6 = 123,
140 D5_D7 = 124,
141 D6_D8 = 125,
142 D7_D9 = 126,
143 D8_D10 = 127,
144 D9_D11 = 128,
145 D10_D12 = 129,
146 D11_D13 = 130,
147 D12_D14 = 131,
148 D13_D15 = 132,
149 D14_D16 = 133,
150 D15_D17 = 134,
151 D16_D18 = 135,
152 D17_D19 = 136,
153 D18_D20 = 137,
154 D19_D21 = 138,
155 D20_D22 = 139,
156 D21_D23 = 140,
157 D22_D24 = 141,
158 D23_D25 = 142,
159 D24_D26 = 143,
160 D25_D27 = 144,
161 D26_D28 = 145,
162 D27_D29 = 146,
163 D28_D30 = 147,
164 D29_D31 = 148,
165 Q0_Q1 = 149,
166 Q1_Q2 = 150,
167 Q2_Q3 = 151,
168 Q3_Q4 = 152,
169 Q4_Q5 = 153,
170 Q5_Q6 = 154,
171 Q6_Q7 = 155,
172 Q7_Q8 = 156,
173 Q8_Q9 = 157,
174 Q9_Q10 = 158,
175 Q10_Q11 = 159,
176 Q11_Q12 = 160,
177 Q12_Q13 = 161,
178 Q13_Q14 = 162,
179 Q14_Q15 = 163,
180 Q0_Q1_Q2_Q3 = 164,
181 Q1_Q2_Q3_Q4 = 165,
182 Q2_Q3_Q4_Q5 = 166,
183 Q3_Q4_Q5_Q6 = 167,
184 Q4_Q5_Q6_Q7 = 168,
185 Q5_Q6_Q7_Q8 = 169,
186 Q6_Q7_Q8_Q9 = 170,
187 Q7_Q8_Q9_Q10 = 171,
188 Q8_Q9_Q10_Q11 = 172,
189 Q9_Q10_Q11_Q12 = 173,
190 Q10_Q11_Q12_Q13 = 174,
191 Q11_Q12_Q13_Q14 = 175,
192 Q12_Q13_Q14_Q15 = 176,
193 R0_R1 = 177,
194 R2_R3 = 178,
195 R4_R5 = 179,
196 R6_R7 = 180,
197 R8_R9 = 181,
198 R10_R11 = 182,
199 R12_SP = 183,
200 D0_D1_D2 = 184,
201 D1_D2_D3 = 185,
202 D2_D3_D4 = 186,
203 D3_D4_D5 = 187,
204 D4_D5_D6 = 188,
205 D5_D6_D7 = 189,
206 D6_D7_D8 = 190,
207 D7_D8_D9 = 191,
208 D8_D9_D10 = 192,
209 D9_D10_D11 = 193,
210 D10_D11_D12 = 194,
211 D11_D12_D13 = 195,
212 D12_D13_D14 = 196,
213 D13_D14_D15 = 197,
214 D14_D15_D16 = 198,
215 D15_D16_D17 = 199,
216 D16_D17_D18 = 200,
217 D17_D18_D19 = 201,
218 D18_D19_D20 = 202,
219 D19_D20_D21 = 203,
220 D20_D21_D22 = 204,
221 D21_D22_D23 = 205,
222 D22_D23_D24 = 206,
223 D23_D24_D25 = 207,
224 D24_D25_D26 = 208,
225 D25_D26_D27 = 209,
226 D26_D27_D28 = 210,
227 D27_D28_D29 = 211,
228 D28_D29_D30 = 212,
229 D29_D30_D31 = 213,
230 D0_D2_D4 = 214,
231 D1_D3_D5 = 215,
232 D2_D4_D6 = 216,
233 D3_D5_D7 = 217,
234 D4_D6_D8 = 218,
235 D5_D7_D9 = 219,
236 D6_D8_D10 = 220,
237 D7_D9_D11 = 221,
238 D8_D10_D12 = 222,
239 D9_D11_D13 = 223,
240 D10_D12_D14 = 224,
241 D11_D13_D15 = 225,
242 D12_D14_D16 = 226,
243 D13_D15_D17 = 227,
244 D14_D16_D18 = 228,
245 D15_D17_D19 = 229,
246 D16_D18_D20 = 230,
247 D17_D19_D21 = 231,
248 D18_D20_D22 = 232,
249 D19_D21_D23 = 233,
250 D20_D22_D24 = 234,
251 D21_D23_D25 = 235,
252 D22_D24_D26 = 236,
253 D23_D25_D27 = 237,
254 D24_D26_D28 = 238,
255 D25_D27_D29 = 239,
256 D26_D28_D30 = 240,
257 D27_D29_D31 = 241,
258 D0_D2_D4_D6 = 242,
259 D1_D3_D5_D7 = 243,
260 D2_D4_D6_D8 = 244,
261 D3_D5_D7_D9 = 245,
262 D4_D6_D8_D10 = 246,
263 D5_D7_D9_D11 = 247,
264 D6_D8_D10_D12 = 248,
265 D7_D9_D11_D13 = 249,
266 D8_D10_D12_D14 = 250,
267 D9_D11_D13_D15 = 251,
268 D10_D12_D14_D16 = 252,
269 D11_D13_D15_D17 = 253,
270 D12_D14_D16_D18 = 254,
271 D13_D15_D17_D19 = 255,
272 D14_D16_D18_D20 = 256,
273 D15_D17_D19_D21 = 257,
274 D16_D18_D20_D22 = 258,
275 D17_D19_D21_D23 = 259,
276 D18_D20_D22_D24 = 260,
277 D19_D21_D23_D25 = 261,
278 D20_D22_D24_D26 = 262,
279 D21_D23_D25_D27 = 263,
280 D22_D24_D26_D28 = 264,
281 D23_D25_D27_D29 = 265,
282 D24_D26_D28_D30 = 266,
283 D25_D27_D29_D31 = 267,
284 D1_D2 = 268,
285 D3_D4 = 269,
286 D5_D6 = 270,
287 D7_D8 = 271,
288 D9_D10 = 272,
289 D11_D12 = 273,
290 D13_D14 = 274,
291 D15_D16 = 275,
292 D17_D18 = 276,
293 D19_D20 = 277,
294 D21_D22 = 278,
295 D23_D24 = 279,
296 D25_D26 = 280,
297 D27_D28 = 281,
298 D29_D30 = 282,
299 D1_D2_D3_D4 = 283,
300 D3_D4_D5_D6 = 284,
301 D5_D6_D7_D8 = 285,
302 D7_D8_D9_D10 = 286,
303 D9_D10_D11_D12 = 287,
304 D11_D12_D13_D14 = 288,
305 D13_D14_D15_D16 = 289,
306 D15_D16_D17_D18 = 290,
307 D17_D18_D19_D20 = 291,
308 D19_D20_D21_D22 = 292,
309 D21_D22_D23_D24 = 293,
310 D23_D24_D25_D26 = 294,
311 D25_D26_D27_D28 = 295,
312 D27_D28_D29_D30 = 296,
313 NUM_TARGET_REGS // 297
314};
315
316} // namespace ARM
317
318// Register classes
319
320namespace ARM {
321
322enum {
323 HPRRegClassID = 0,
324 FPWithVPRRegClassID = 1,
325 SPRRegClassID = 2,
326 FPWithVPR_with_ssub_0RegClassID = 3,
327 GPRRegClassID = 4,
328 GPRwithAPSRRegClassID = 5,
329 GPRwithZRRegClassID = 6,
330 SPR_8RegClassID = 7,
331 GPRnopcRegClassID = 8,
332 GPRnospRegClassID = 9,
333 GPRwithAPSR_NZCVnospRegClassID = 10,
334 GPRwithAPSRnospRegClassID = 11,
335 GPRwithZRnospRegClassID = 12,
336 GPRnoipRegClassID = 13,
337 rGPRRegClassID = 14,
338 GPRnoip_and_GPRnopcRegClassID = 15,
339 GPRnoip_and_GPRnospRegClassID = 16,
340 GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID = 17,
341 tGPRwithpcRegClassID = 18,
342 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID = 19,
343 hGPRRegClassID = 20,
344 tGPRRegClassID = 21,
345 tGPREvenRegClassID = 22,
346 GPRnopc_and_hGPRRegClassID = 23,
347 GPRnosp_and_hGPRRegClassID = 24,
348 GPRnoip_and_hGPRRegClassID = 25,
349 GPRnoip_and_tGPREvenRegClassID = 26,
350 GPRnosp_and_GPRnopc_and_hGPRRegClassID = 27,
351 tGPROddRegClassID = 28,
352 GPRnopc_and_GPRnoip_and_hGPRRegClassID = 29,
353 GPRnosp_and_GPRnoip_and_hGPRRegClassID = 30,
354 tcGPRRegClassID = 31,
355 GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 32,
356 hGPR_and_tGPREvenRegClassID = 33,
357 tGPR_and_tGPREvenRegClassID = 34,
358 tGPR_and_tGPROddRegClassID = 35,
359 tcGPRnotr12RegClassID = 36,
360 tGPREven_and_tcGPRRegClassID = 37,
361 FP_STATUS_REGSRegClassID = 38,
362 hGPR_and_GPRnoip_and_tGPREvenRegClassID = 39,
363 hGPR_and_tGPROddRegClassID = 40,
364 tGPREven_and_tcGPRnotr12RegClassID = 41,
365 tGPROdd_and_tcGPRRegClassID = 42,
366 CCRRegClassID = 43,
367 FPCXTRegsRegClassID = 44,
368 GPRlrRegClassID = 45,
369 GPRspRegClassID = 46,
370 VCCRRegClassID = 47,
371 cl_FPSCR_NZCVRegClassID = 48,
372 hGPR_and_tGPRwithpcRegClassID = 49,
373 hGPR_and_tcGPRRegClassID = 50,
374 DPRRegClassID = 51,
375 DPR_VFP2RegClassID = 52,
376 DPR_8RegClassID = 53,
377 GPRPairRegClassID = 54,
378 GPRPairnospRegClassID = 55,
379 GPRPair_with_gsub_0_in_tGPRRegClassID = 56,
380 GPRPair_with_gsub_0_in_hGPRRegClassID = 57,
381 GPRPair_with_gsub_0_in_tcGPRRegClassID = 58,
382 GPRPair_with_gsub_0_in_tcGPRnotr12RegClassID = 59,
383 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID = 60,
384 GPRPair_with_gsub_1_in_GPRspRegClassID = 61,
385 DPairSpcRegClassID = 62,
386 DPairSpc_with_ssub_0RegClassID = 63,
387 DPairSpc_with_ssub_4RegClassID = 64,
388 DPairSpc_with_dsub_0_in_DPR_8RegClassID = 65,
389 DPairSpc_with_dsub_2_in_DPR_8RegClassID = 66,
390 DPairRegClassID = 67,
391 DPair_with_ssub_0RegClassID = 68,
392 QPRRegClassID = 69,
393 DPair_with_ssub_2RegClassID = 70,
394 DPair_with_dsub_0_in_DPR_8RegClassID = 71,
395 MQPRRegClassID = 72,
396 QPR_VFP2RegClassID = 73,
397 DPair_with_dsub_1_in_DPR_8RegClassID = 74,
398 QPR_8RegClassID = 75,
399 DTripleRegClassID = 76,
400 DTripleSpcRegClassID = 77,
401 DTripleSpc_with_ssub_0RegClassID = 78,
402 DTriple_with_ssub_0RegClassID = 79,
403 DTriple_with_qsub_0_in_QPRRegClassID = 80,
404 DTriple_with_ssub_2RegClassID = 81,
405 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
406 DTripleSpc_with_ssub_4RegClassID = 83,
407 DTriple_with_ssub_4RegClassID = 84,
408 DTripleSpc_with_ssub_8RegClassID = 85,
409 DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 86,
410 DTriple_with_dsub_0_in_DPR_8RegClassID = 87,
411 DTriple_with_qsub_0_in_MQPRRegClassID = 88,
412 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
413 DTriple_with_dsub_1_in_DPR_8RegClassID = 90,
414 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 91,
415 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID = 92,
416 DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 93,
417 DTriple_with_dsub_2_in_DPR_8RegClassID = 94,
418 DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 95,
419 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 96,
420 DTriple_with_qsub_0_in_QPR_8RegClassID = 97,
421 DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID = 98,
422 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 99,
423 DQuadSpcRegClassID = 100,
424 DQuadSpc_with_ssub_0RegClassID = 101,
425 DQuadSpc_with_ssub_4RegClassID = 102,
426 DQuadSpc_with_ssub_8RegClassID = 103,
427 DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 104,
428 DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 105,
429 DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 106,
430 DQuadRegClassID = 107,
431 DQuad_with_ssub_0RegClassID = 108,
432 DQuad_with_ssub_2RegClassID = 109,
433 QQPRRegClassID = 110,
434 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 111,
435 DQuad_with_ssub_4RegClassID = 112,
436 DQuad_with_ssub_6RegClassID = 113,
437 DQuad_with_dsub_0_in_DPR_8RegClassID = 114,
438 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 115,
439 QQPR_with_ssub_0RegClassID = 116,
440 DQuad_with_dsub_1_in_DPR_8RegClassID = 117,
441 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 118,
442 MQQPRRegClassID = 119,
443 DQuad_with_dsub_2_in_DPR_8RegClassID = 120,
444 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 121,
445 DQuad_with_dsub_3_in_DPR_8RegClassID = 122,
446 DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 123,
447 MQQPR_with_qsub_0_in_QPR_8RegClassID = 124,
448 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 125,
449 MQQPR_with_dsub_2_in_DPR_8RegClassID = 126,
450 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID = 127,
451 QQQQPRRegClassID = 128,
452 QQQQPR_with_ssub_0RegClassID = 129,
453 QQQQPR_with_ssub_4RegClassID = 130,
454 QQQQPR_with_ssub_8RegClassID = 131,
455 MQQQQPRRegClassID = 132,
456 MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID = 133,
457 MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID = 134,
458 MQQQQPR_with_qsub_2_in_QPR_8RegClassID = 135,
459 MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8RegClassID = 136,
460
461};
462
463} // namespace ARM
464
465// Register alternate name indices
466
467namespace ARM {
468
469enum {
470 NoRegAltName, // 0
471 RegNamesRaw, // 1
472 NUM_TARGET_REG_ALT_NAMES = 2
473};
474
475} // namespace ARM
476
477// Subregister indices
478
479namespace ARM {
480
481enum : uint16_t {
482 NoSubRegister,
483 dsub_0, // 1
484 dsub_1, // 2
485 dsub_2, // 3
486 dsub_3, // 4
487 dsub_4, // 5
488 dsub_5, // 6
489 dsub_6, // 7
490 dsub_7, // 8
491 gsub_0, // 9
492 gsub_1, // 10
493 qqsub_0, // 11
494 qqsub_1, // 12
495 qsub_0, // 13
496 qsub_1, // 14
497 qsub_2, // 15
498 qsub_3, // 16
499 ssub_0, // 17
500 ssub_1, // 18
501 ssub_2, // 19
502 ssub_3, // 20
503 ssub_4, // 21
504 ssub_5, // 22
505 ssub_6, // 23
506 ssub_7, // 24
507 ssub_8, // 25
508 ssub_9, // 26
509 ssub_10, // 27
510 ssub_11, // 28
511 ssub_12, // 29
512 ssub_13, // 30
513 ssub_14, // 31
514 ssub_15, // 32
515 ssub_0_ssub_1_ssub_4_ssub_5, // 33
516 ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34
517 ssub_2_ssub_3_ssub_6_ssub_7, // 35
518 ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36
519 ssub_2_ssub_3_ssub_4_ssub_5, // 37
520 ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38
521 ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39
522 ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40
523 ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41
524 ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42
525 ssub_4_ssub_5_ssub_8_ssub_9, // 43
526 ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44
527 ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45
528 ssub_6_ssub_7_dsub_5, // 46
529 ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47
530 ssub_6_ssub_7_dsub_5_dsub_7, // 48
531 ssub_6_ssub_7_ssub_8_ssub_9, // 49
532 ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50
533 ssub_8_ssub_9_ssub_12_ssub_13, // 51
534 ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52
535 dsub_5_dsub_7, // 53
536 dsub_5_ssub_12_ssub_13_dsub_7, // 54
537 dsub_5_ssub_12_ssub_13, // 55
538 ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56
539 NUM_TARGET_SUBREGS
540};
541
542} // namespace ARM
543// Register pressure sets enum.
544namespace ARM {
545
546enum RegisterPressureSets {
547 FPCXTRegs = 0,
548 GPRlr = 1,
549 VCCR = 2,
550 hGPR_and_tGPRwithpc = 3,
551 cl_FPSCR_NZCV = 4,
552 GPRsp = 5,
553 tGPROdd = 6,
554 tcGPR = 7,
555 hGPR = 8,
556 tGPROdd_with_tcGPR = 9,
557 tGPR = 10,
558 tGPR_with_tcGPR = 11,
559 tGPREven = 12,
560 hGPR_with_tGPREven = 13,
561 hGPR_with_tGPROdd = 14,
562 hGPR_with_tcGPR = 15,
563 tGPR_with_tGPREven = 16,
564 GPR = 17,
565 GPRwithZR = 18,
566 GPRwithAPSR_with_GPRwithZR = 19,
567 DQuad_with_dsub_0_in_DPR_8 = 20,
568 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR = 21,
569 HPR = 22,
570 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 23,
571 DPair_with_ssub_0 = 24,
572 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 25,
573 DPairSpc_with_ssub_0 = 26,
574 DQuad_with_ssub_0 = 27,
575 DTripleSpc_with_ssub_0 = 28,
576 QQQQPR_with_ssub_0 = 29,
577 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 30,
578 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 31,
579 DTriple_with_qsub_0_in_QPR = 32,
580 DPR = 33,
581};
582
583} // namespace ARM
584
585} // namespace llvm
586