1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass ARMMCRegisterClasses[];
13
14namespace ARM {
15
16enum : unsigned {
17 NoRegister,
18 APSR = 1,
19 APSR_NZCV = 2,
20 CPSR = 3,
21 FPCXTNS = 4,
22 FPCXTS = 5,
23 FPEXC = 6,
24 FPINST = 7,
25 FPSCR = 8,
26 FPSCR_NZCV = 9,
27 FPSCR_NZCVQC = 10,
28 FPSCR_RM = 11,
29 FPSID = 12,
30 ITSTATE = 13,
31 LR = 14,
32 PC = 15,
33 RA_AUTH_CODE = 16,
34 SP = 17,
35 SPSR = 18,
36 VPR = 19,
37 ZR = 20,
38 D0 = 21,
39 D1 = 22,
40 D2 = 23,
41 D3 = 24,
42 D4 = 25,
43 D5 = 26,
44 D6 = 27,
45 D7 = 28,
46 D8 = 29,
47 D9 = 30,
48 D10 = 31,
49 D11 = 32,
50 D12 = 33,
51 D13 = 34,
52 D14 = 35,
53 D15 = 36,
54 D16 = 37,
55 D17 = 38,
56 D18 = 39,
57 D19 = 40,
58 D20 = 41,
59 D21 = 42,
60 D22 = 43,
61 D23 = 44,
62 D24 = 45,
63 D25 = 46,
64 D26 = 47,
65 D27 = 48,
66 D28 = 49,
67 D29 = 50,
68 D30 = 51,
69 D31 = 52,
70 FPINST2 = 53,
71 MVFR0 = 54,
72 MVFR1 = 55,
73 MVFR2 = 56,
74 P0 = 57,
75 Q0 = 58,
76 Q1 = 59,
77 Q2 = 60,
78 Q3 = 61,
79 Q4 = 62,
80 Q5 = 63,
81 Q6 = 64,
82 Q7 = 65,
83 Q8 = 66,
84 Q9 = 67,
85 Q10 = 68,
86 Q11 = 69,
87 Q12 = 70,
88 Q13 = 71,
89 Q14 = 72,
90 Q15 = 73,
91 R0 = 74,
92 R1 = 75,
93 R2 = 76,
94 R3 = 77,
95 R4 = 78,
96 R5 = 79,
97 R6 = 80,
98 R7 = 81,
99 R8 = 82,
100 R9 = 83,
101 R10 = 84,
102 R11 = 85,
103 R12 = 86,
104 S0 = 87,
105 S1 = 88,
106 S2 = 89,
107 S3 = 90,
108 S4 = 91,
109 S5 = 92,
110 S6 = 93,
111 S7 = 94,
112 S8 = 95,
113 S9 = 96,
114 S10 = 97,
115 S11 = 98,
116 S12 = 99,
117 S13 = 100,
118 S14 = 101,
119 S15 = 102,
120 S16 = 103,
121 S17 = 104,
122 S18 = 105,
123 S19 = 106,
124 S20 = 107,
125 S21 = 108,
126 S22 = 109,
127 S23 = 110,
128 S24 = 111,
129 S25 = 112,
130 S26 = 113,
131 S27 = 114,
132 S28 = 115,
133 S29 = 116,
134 S30 = 117,
135 S31 = 118,
136 D0_D2 = 119,
137 D1_D3 = 120,
138 D2_D4 = 121,
139 D3_D5 = 122,
140 D4_D6 = 123,
141 D5_D7 = 124,
142 D6_D8 = 125,
143 D7_D9 = 126,
144 D8_D10 = 127,
145 D9_D11 = 128,
146 D10_D12 = 129,
147 D11_D13 = 130,
148 D12_D14 = 131,
149 D13_D15 = 132,
150 D14_D16 = 133,
151 D15_D17 = 134,
152 D16_D18 = 135,
153 D17_D19 = 136,
154 D18_D20 = 137,
155 D19_D21 = 138,
156 D20_D22 = 139,
157 D21_D23 = 140,
158 D22_D24 = 141,
159 D23_D25 = 142,
160 D24_D26 = 143,
161 D25_D27 = 144,
162 D26_D28 = 145,
163 D27_D29 = 146,
164 D28_D30 = 147,
165 D29_D31 = 148,
166 Q0_Q1 = 149,
167 Q1_Q2 = 150,
168 Q2_Q3 = 151,
169 Q3_Q4 = 152,
170 Q4_Q5 = 153,
171 Q5_Q6 = 154,
172 Q6_Q7 = 155,
173 Q7_Q8 = 156,
174 Q8_Q9 = 157,
175 Q9_Q10 = 158,
176 Q10_Q11 = 159,
177 Q11_Q12 = 160,
178 Q12_Q13 = 161,
179 Q13_Q14 = 162,
180 Q14_Q15 = 163,
181 Q0_Q1_Q2_Q3 = 164,
182 Q1_Q2_Q3_Q4 = 165,
183 Q2_Q3_Q4_Q5 = 166,
184 Q3_Q4_Q5_Q6 = 167,
185 Q4_Q5_Q6_Q7 = 168,
186 Q5_Q6_Q7_Q8 = 169,
187 Q6_Q7_Q8_Q9 = 170,
188 Q7_Q8_Q9_Q10 = 171,
189 Q8_Q9_Q10_Q11 = 172,
190 Q9_Q10_Q11_Q12 = 173,
191 Q10_Q11_Q12_Q13 = 174,
192 Q11_Q12_Q13_Q14 = 175,
193 Q12_Q13_Q14_Q15 = 176,
194 R0_R1 = 177,
195 R2_R3 = 178,
196 R4_R5 = 179,
197 R6_R7 = 180,
198 R8_R9 = 181,
199 R10_R11 = 182,
200 R12_SP = 183,
201 D0_D1_D2 = 184,
202 D1_D2_D3 = 185,
203 D2_D3_D4 = 186,
204 D3_D4_D5 = 187,
205 D4_D5_D6 = 188,
206 D5_D6_D7 = 189,
207 D6_D7_D8 = 190,
208 D7_D8_D9 = 191,
209 D8_D9_D10 = 192,
210 D9_D10_D11 = 193,
211 D10_D11_D12 = 194,
212 D11_D12_D13 = 195,
213 D12_D13_D14 = 196,
214 D13_D14_D15 = 197,
215 D14_D15_D16 = 198,
216 D15_D16_D17 = 199,
217 D16_D17_D18 = 200,
218 D17_D18_D19 = 201,
219 D18_D19_D20 = 202,
220 D19_D20_D21 = 203,
221 D20_D21_D22 = 204,
222 D21_D22_D23 = 205,
223 D22_D23_D24 = 206,
224 D23_D24_D25 = 207,
225 D24_D25_D26 = 208,
226 D25_D26_D27 = 209,
227 D26_D27_D28 = 210,
228 D27_D28_D29 = 211,
229 D28_D29_D30 = 212,
230 D29_D30_D31 = 213,
231 D0_D2_D4 = 214,
232 D1_D3_D5 = 215,
233 D2_D4_D6 = 216,
234 D3_D5_D7 = 217,
235 D4_D6_D8 = 218,
236 D5_D7_D9 = 219,
237 D6_D8_D10 = 220,
238 D7_D9_D11 = 221,
239 D8_D10_D12 = 222,
240 D9_D11_D13 = 223,
241 D10_D12_D14 = 224,
242 D11_D13_D15 = 225,
243 D12_D14_D16 = 226,
244 D13_D15_D17 = 227,
245 D14_D16_D18 = 228,
246 D15_D17_D19 = 229,
247 D16_D18_D20 = 230,
248 D17_D19_D21 = 231,
249 D18_D20_D22 = 232,
250 D19_D21_D23 = 233,
251 D20_D22_D24 = 234,
252 D21_D23_D25 = 235,
253 D22_D24_D26 = 236,
254 D23_D25_D27 = 237,
255 D24_D26_D28 = 238,
256 D25_D27_D29 = 239,
257 D26_D28_D30 = 240,
258 D27_D29_D31 = 241,
259 D0_D2_D4_D6 = 242,
260 D1_D3_D5_D7 = 243,
261 D2_D4_D6_D8 = 244,
262 D3_D5_D7_D9 = 245,
263 D4_D6_D8_D10 = 246,
264 D5_D7_D9_D11 = 247,
265 D6_D8_D10_D12 = 248,
266 D7_D9_D11_D13 = 249,
267 D8_D10_D12_D14 = 250,
268 D9_D11_D13_D15 = 251,
269 D10_D12_D14_D16 = 252,
270 D11_D13_D15_D17 = 253,
271 D12_D14_D16_D18 = 254,
272 D13_D15_D17_D19 = 255,
273 D14_D16_D18_D20 = 256,
274 D15_D17_D19_D21 = 257,
275 D16_D18_D20_D22 = 258,
276 D17_D19_D21_D23 = 259,
277 D18_D20_D22_D24 = 260,
278 D19_D21_D23_D25 = 261,
279 D20_D22_D24_D26 = 262,
280 D21_D23_D25_D27 = 263,
281 D22_D24_D26_D28 = 264,
282 D23_D25_D27_D29 = 265,
283 D24_D26_D28_D30 = 266,
284 D25_D27_D29_D31 = 267,
285 D1_D2 = 268,
286 D3_D4 = 269,
287 D5_D6 = 270,
288 D7_D8 = 271,
289 D9_D10 = 272,
290 D11_D12 = 273,
291 D13_D14 = 274,
292 D15_D16 = 275,
293 D17_D18 = 276,
294 D19_D20 = 277,
295 D21_D22 = 278,
296 D23_D24 = 279,
297 D25_D26 = 280,
298 D27_D28 = 281,
299 D29_D30 = 282,
300 D1_D2_D3_D4 = 283,
301 D3_D4_D5_D6 = 284,
302 D5_D6_D7_D8 = 285,
303 D7_D8_D9_D10 = 286,
304 D9_D10_D11_D12 = 287,
305 D11_D12_D13_D14 = 288,
306 D13_D14_D15_D16 = 289,
307 D15_D16_D17_D18 = 290,
308 D17_D18_D19_D20 = 291,
309 D19_D20_D21_D22 = 292,
310 D21_D22_D23_D24 = 293,
311 D23_D24_D25_D26 = 294,
312 D25_D26_D27_D28 = 295,
313 D27_D28_D29_D30 = 296,
314 NUM_TARGET_REGS // 297
315};
316
317} // namespace ARM
318
319// Register classes
320
321namespace ARM {
322
323enum {
324 HPRRegClassID = 0,
325 FPWithVPRRegClassID = 1,
326 SPRRegClassID = 2,
327 FPWithVPR_with_ssub_0RegClassID = 3,
328 GPRRegClassID = 4,
329 GPRwithAPSRRegClassID = 5,
330 GPRwithZRRegClassID = 6,
331 SPR_8RegClassID = 7,
332 GPRnopcRegClassID = 8,
333 GPRnospRegClassID = 9,
334 GPRwithAPSR_NZCVnospRegClassID = 10,
335 GPRwithAPSRnospRegClassID = 11,
336 GPRwithZRnospRegClassID = 12,
337 GPRnoipRegClassID = 13,
338 rGPRRegClassID = 14,
339 GPRnoip_and_GPRnopcRegClassID = 15,
340 GPRnoip_and_GPRnospRegClassID = 16,
341 GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID = 17,
342 tGPRwithpcRegClassID = 18,
343 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID = 19,
344 hGPRRegClassID = 20,
345 tGPRRegClassID = 21,
346 tGPREvenRegClassID = 22,
347 GPRnopc_and_hGPRRegClassID = 23,
348 GPRnosp_and_hGPRRegClassID = 24,
349 GPRnoip_and_hGPRRegClassID = 25,
350 GPRnoip_and_tGPREvenRegClassID = 26,
351 GPRnosp_and_GPRnopc_and_hGPRRegClassID = 27,
352 tGPROddRegClassID = 28,
353 GPRnopc_and_GPRnoip_and_hGPRRegClassID = 29,
354 GPRnosp_and_GPRnoip_and_hGPRRegClassID = 30,
355 tcGPRRegClassID = 31,
356 GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 32,
357 hGPR_and_tGPREvenRegClassID = 33,
358 tGPR_and_tGPREvenRegClassID = 34,
359 tGPR_and_tGPROddRegClassID = 35,
360 tcGPRnotr12RegClassID = 36,
361 tGPREven_and_tcGPRRegClassID = 37,
362 FP_STATUS_REGSRegClassID = 38,
363 hGPR_and_GPRnoip_and_tGPREvenRegClassID = 39,
364 hGPR_and_tGPROddRegClassID = 40,
365 tGPREven_and_tcGPRnotr12RegClassID = 41,
366 tGPROdd_and_tcGPRRegClassID = 42,
367 CCRRegClassID = 43,
368 FPCXTRegsRegClassID = 44,
369 GPRlrRegClassID = 45,
370 GPRspRegClassID = 46,
371 VCCRRegClassID = 47,
372 cl_FPSCR_NZCVRegClassID = 48,
373 hGPR_and_tGPRwithpcRegClassID = 49,
374 hGPR_and_tcGPRRegClassID = 50,
375 DPRRegClassID = 51,
376 DPR_VFP2RegClassID = 52,
377 DPR_8RegClassID = 53,
378 GPRPairRegClassID = 54,
379 GPRPairnospRegClassID = 55,
380 GPRPair_with_gsub_0_in_tGPRRegClassID = 56,
381 GPRPair_with_gsub_0_in_hGPRRegClassID = 57,
382 GPRPair_with_gsub_0_in_tcGPRRegClassID = 58,
383 GPRPair_with_gsub_0_in_tcGPRnotr12RegClassID = 59,
384 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID = 60,
385 GPRPair_with_gsub_1_in_GPRspRegClassID = 61,
386 DPairSpcRegClassID = 62,
387 DPairSpc_with_ssub_0RegClassID = 63,
388 DPairSpc_with_ssub_4RegClassID = 64,
389 DPairSpc_with_dsub_0_in_DPR_8RegClassID = 65,
390 DPairSpc_with_dsub_2_in_DPR_8RegClassID = 66,
391 DPairRegClassID = 67,
392 DPair_with_ssub_0RegClassID = 68,
393 QPRRegClassID = 69,
394 DPair_with_ssub_2RegClassID = 70,
395 DPair_with_dsub_0_in_DPR_8RegClassID = 71,
396 MQPRRegClassID = 72,
397 QPR_VFP2RegClassID = 73,
398 DPair_with_dsub_1_in_DPR_8RegClassID = 74,
399 QPR_8RegClassID = 75,
400 DTripleRegClassID = 76,
401 DTripleSpcRegClassID = 77,
402 DTripleSpc_with_ssub_0RegClassID = 78,
403 DTriple_with_ssub_0RegClassID = 79,
404 DTriple_with_qsub_0_in_QPRRegClassID = 80,
405 DTriple_with_ssub_2RegClassID = 81,
406 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
407 DTripleSpc_with_ssub_4RegClassID = 83,
408 DTriple_with_ssub_4RegClassID = 84,
409 DTripleSpc_with_ssub_8RegClassID = 85,
410 DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 86,
411 DTriple_with_dsub_0_in_DPR_8RegClassID = 87,
412 DTriple_with_qsub_0_in_MQPRRegClassID = 88,
413 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
414 DTriple_with_dsub_1_in_DPR_8RegClassID = 90,
415 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 91,
416 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID = 92,
417 DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 93,
418 DTriple_with_dsub_2_in_DPR_8RegClassID = 94,
419 DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 95,
420 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 96,
421 DTriple_with_qsub_0_in_QPR_8RegClassID = 97,
422 DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID = 98,
423 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 99,
424 DQuadSpcRegClassID = 100,
425 DQuadSpc_with_ssub_0RegClassID = 101,
426 DQuadSpc_with_ssub_4RegClassID = 102,
427 DQuadSpc_with_ssub_8RegClassID = 103,
428 DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 104,
429 DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 105,
430 DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 106,
431 DQuadRegClassID = 107,
432 DQuad_with_ssub_0RegClassID = 108,
433 DQuad_with_ssub_2RegClassID = 109,
434 QQPRRegClassID = 110,
435 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 111,
436 DQuad_with_ssub_4RegClassID = 112,
437 DQuad_with_ssub_6RegClassID = 113,
438 DQuad_with_dsub_0_in_DPR_8RegClassID = 114,
439 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 115,
440 QQPR_with_ssub_0RegClassID = 116,
441 DQuad_with_dsub_1_in_DPR_8RegClassID = 117,
442 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 118,
443 MQQPRRegClassID = 119,
444 DQuad_with_dsub_2_in_DPR_8RegClassID = 120,
445 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 121,
446 DQuad_with_dsub_3_in_DPR_8RegClassID = 122,
447 DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 123,
448 MQQPR_with_qsub_0_in_QPR_8RegClassID = 124,
449 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 125,
450 MQQPR_with_dsub_2_in_DPR_8RegClassID = 126,
451 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID = 127,
452 QQQQPRRegClassID = 128,
453 QQQQPR_with_ssub_0RegClassID = 129,
454 QQQQPR_with_ssub_4RegClassID = 130,
455 QQQQPR_with_ssub_8RegClassID = 131,
456 MQQQQPRRegClassID = 132,
457 MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID = 133,
458 MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID = 134,
459 MQQQQPR_with_qsub_2_in_QPR_8RegClassID = 135,
460 MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8RegClassID = 136,
461
462};
463
464} // namespace ARM
465
466// Register alternate name indices
467
468namespace ARM {
469
470enum {
471 NoRegAltName, // 0
472 RegNamesRaw, // 1
473 NUM_TARGET_REG_ALT_NAMES = 2
474};
475
476} // namespace ARM
477
478// Subregister indices
479
480namespace ARM {
481
482enum : uint16_t {
483 NoSubRegister,
484 dsub_0, // 1
485 dsub_1, // 2
486 dsub_2, // 3
487 dsub_3, // 4
488 dsub_4, // 5
489 dsub_5, // 6
490 dsub_6, // 7
491 dsub_7, // 8
492 gsub_0, // 9
493 gsub_1, // 10
494 qqsub_0, // 11
495 qqsub_1, // 12
496 qsub_0, // 13
497 qsub_1, // 14
498 qsub_2, // 15
499 qsub_3, // 16
500 ssub_0, // 17
501 ssub_1, // 18
502 ssub_2, // 19
503 ssub_3, // 20
504 ssub_4, // 21
505 ssub_5, // 22
506 ssub_6, // 23
507 ssub_7, // 24
508 ssub_8, // 25
509 ssub_9, // 26
510 ssub_10, // 27
511 ssub_11, // 28
512 ssub_12, // 29
513 ssub_13, // 30
514 ssub_14, // 31
515 ssub_15, // 32
516 ssub_0_ssub_1_ssub_4_ssub_5, // 33
517 ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34
518 ssub_2_ssub_3_ssub_6_ssub_7, // 35
519 ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36
520 ssub_2_ssub_3_ssub_4_ssub_5, // 37
521 ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38
522 ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39
523 ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40
524 ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41
525 ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42
526 ssub_4_ssub_5_ssub_8_ssub_9, // 43
527 ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44
528 ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45
529 ssub_6_ssub_7_dsub_5, // 46
530 ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47
531 ssub_6_ssub_7_dsub_5_dsub_7, // 48
532 ssub_6_ssub_7_ssub_8_ssub_9, // 49
533 ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50
534 ssub_8_ssub_9_ssub_12_ssub_13, // 51
535 ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52
536 dsub_5_dsub_7, // 53
537 dsub_5_ssub_12_ssub_13_dsub_7, // 54
538 dsub_5_ssub_12_ssub_13, // 55
539 ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56
540 NUM_TARGET_SUBREGS
541};
542
543} // namespace ARM
544// Register pressure sets enum.
545namespace ARM {
546
547enum RegisterPressureSets {
548 FPCXTRegs = 0,
549 GPRlr = 1,
550 VCCR = 2,
551 hGPR_and_tGPRwithpc = 3,
552 cl_FPSCR_NZCV = 4,
553 GPRsp = 5,
554 tGPROdd = 6,
555 tcGPR = 7,
556 hGPR = 8,
557 tGPROdd_with_tcGPR = 9,
558 tGPR = 10,
559 tGPR_with_tcGPR = 11,
560 tGPREven = 12,
561 hGPR_with_tGPREven = 13,
562 hGPR_with_tGPROdd = 14,
563 hGPR_with_tcGPR = 15,
564 tGPR_with_tGPREven = 16,
565 GPR = 17,
566 GPRwithZR = 18,
567 GPRwithAPSR_with_GPRwithZR = 19,
568 DQuad_with_dsub_0_in_DPR_8 = 20,
569 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR = 21,
570 HPR = 22,
571 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 23,
572 DPair_with_ssub_0 = 24,
573 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 25,
574 DPairSpc_with_ssub_0 = 26,
575 DQuad_with_ssub_0 = 27,
576 DTripleSpc_with_ssub_0 = 28,
577 QQQQPR_with_ssub_0 = 29,
578 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 30,
579 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 31,
580 DTriple_with_qsub_0_in_QPR = 32,
581 DPR = 33,
582};
583
584} // namespace ARM
585
586} // namespace llvm
587