1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass ARMMCRegisterClasses[];
13
14namespace ARM {
15enum : unsigned {
16 NoRegister,
17 APSR = 1,
18 APSR_NZCV = 2,
19 CPSR = 3,
20 FPCXTNS = 4,
21 FPCXTS = 5,
22 FPEXC = 6,
23 FPINST = 7,
24 FPSCR = 8,
25 FPSCR_NZCV = 9,
26 FPSCR_NZCVQC = 10,
27 FPSCR_RM = 11,
28 FPSID = 12,
29 ITSTATE = 13,
30 LR = 14,
31 PC = 15,
32 RA_AUTH_CODE = 16,
33 SP = 17,
34 SPSR = 18,
35 VPR = 19,
36 ZR = 20,
37 D0 = 21,
38 D1 = 22,
39 D2 = 23,
40 D3 = 24,
41 D4 = 25,
42 D5 = 26,
43 D6 = 27,
44 D7 = 28,
45 D8 = 29,
46 D9 = 30,
47 D10 = 31,
48 D11 = 32,
49 D12 = 33,
50 D13 = 34,
51 D14 = 35,
52 D15 = 36,
53 D16 = 37,
54 D17 = 38,
55 D18 = 39,
56 D19 = 40,
57 D20 = 41,
58 D21 = 42,
59 D22 = 43,
60 D23 = 44,
61 D24 = 45,
62 D25 = 46,
63 D26 = 47,
64 D27 = 48,
65 D28 = 49,
66 D29 = 50,
67 D30 = 51,
68 D31 = 52,
69 FPINST2 = 53,
70 MVFR0 = 54,
71 MVFR1 = 55,
72 MVFR2 = 56,
73 P0 = 57,
74 Q0 = 58,
75 Q1 = 59,
76 Q2 = 60,
77 Q3 = 61,
78 Q4 = 62,
79 Q5 = 63,
80 Q6 = 64,
81 Q7 = 65,
82 Q8 = 66,
83 Q9 = 67,
84 Q10 = 68,
85 Q11 = 69,
86 Q12 = 70,
87 Q13 = 71,
88 Q14 = 72,
89 Q15 = 73,
90 R0 = 74,
91 R1 = 75,
92 R2 = 76,
93 R3 = 77,
94 R4 = 78,
95 R5 = 79,
96 R6 = 80,
97 R7 = 81,
98 R8 = 82,
99 R9 = 83,
100 R10 = 84,
101 R11 = 85,
102 R12 = 86,
103 S0 = 87,
104 S1 = 88,
105 S2 = 89,
106 S3 = 90,
107 S4 = 91,
108 S5 = 92,
109 S6 = 93,
110 S7 = 94,
111 S8 = 95,
112 S9 = 96,
113 S10 = 97,
114 S11 = 98,
115 S12 = 99,
116 S13 = 100,
117 S14 = 101,
118 S15 = 102,
119 S16 = 103,
120 S17 = 104,
121 S18 = 105,
122 S19 = 106,
123 S20 = 107,
124 S21 = 108,
125 S22 = 109,
126 S23 = 110,
127 S24 = 111,
128 S25 = 112,
129 S26 = 113,
130 S27 = 114,
131 S28 = 115,
132 S29 = 116,
133 S30 = 117,
134 S31 = 118,
135 D0_D2 = 119,
136 D1_D3 = 120,
137 D2_D4 = 121,
138 D3_D5 = 122,
139 D4_D6 = 123,
140 D5_D7 = 124,
141 D6_D8 = 125,
142 D7_D9 = 126,
143 D8_D10 = 127,
144 D9_D11 = 128,
145 D10_D12 = 129,
146 D11_D13 = 130,
147 D12_D14 = 131,
148 D13_D15 = 132,
149 D14_D16 = 133,
150 D15_D17 = 134,
151 D16_D18 = 135,
152 D17_D19 = 136,
153 D18_D20 = 137,
154 D19_D21 = 138,
155 D20_D22 = 139,
156 D21_D23 = 140,
157 D22_D24 = 141,
158 D23_D25 = 142,
159 D24_D26 = 143,
160 D25_D27 = 144,
161 D26_D28 = 145,
162 D27_D29 = 146,
163 D28_D30 = 147,
164 D29_D31 = 148,
165 Q0_Q1 = 149,
166 Q1_Q2 = 150,
167 Q2_Q3 = 151,
168 Q3_Q4 = 152,
169 Q4_Q5 = 153,
170 Q5_Q6 = 154,
171 Q6_Q7 = 155,
172 Q7_Q8 = 156,
173 Q8_Q9 = 157,
174 Q9_Q10 = 158,
175 Q10_Q11 = 159,
176 Q11_Q12 = 160,
177 Q12_Q13 = 161,
178 Q13_Q14 = 162,
179 Q14_Q15 = 163,
180 Q0_Q1_Q2_Q3 = 164,
181 Q1_Q2_Q3_Q4 = 165,
182 Q2_Q3_Q4_Q5 = 166,
183 Q3_Q4_Q5_Q6 = 167,
184 Q4_Q5_Q6_Q7 = 168,
185 Q5_Q6_Q7_Q8 = 169,
186 Q6_Q7_Q8_Q9 = 170,
187 Q7_Q8_Q9_Q10 = 171,
188 Q8_Q9_Q10_Q11 = 172,
189 Q9_Q10_Q11_Q12 = 173,
190 Q10_Q11_Q12_Q13 = 174,
191 Q11_Q12_Q13_Q14 = 175,
192 Q12_Q13_Q14_Q15 = 176,
193 R0_R1 = 177,
194 R2_R3 = 178,
195 R4_R5 = 179,
196 R6_R7 = 180,
197 R8_R9 = 181,
198 R10_R11 = 182,
199 R12_SP = 183,
200 D0_D1_D2 = 184,
201 D1_D2_D3 = 185,
202 D2_D3_D4 = 186,
203 D3_D4_D5 = 187,
204 D4_D5_D6 = 188,
205 D5_D6_D7 = 189,
206 D6_D7_D8 = 190,
207 D7_D8_D9 = 191,
208 D8_D9_D10 = 192,
209 D9_D10_D11 = 193,
210 D10_D11_D12 = 194,
211 D11_D12_D13 = 195,
212 D12_D13_D14 = 196,
213 D13_D14_D15 = 197,
214 D14_D15_D16 = 198,
215 D15_D16_D17 = 199,
216 D16_D17_D18 = 200,
217 D17_D18_D19 = 201,
218 D18_D19_D20 = 202,
219 D19_D20_D21 = 203,
220 D20_D21_D22 = 204,
221 D21_D22_D23 = 205,
222 D22_D23_D24 = 206,
223 D23_D24_D25 = 207,
224 D24_D25_D26 = 208,
225 D25_D26_D27 = 209,
226 D26_D27_D28 = 210,
227 D27_D28_D29 = 211,
228 D28_D29_D30 = 212,
229 D29_D30_D31 = 213,
230 D0_D2_D4 = 214,
231 D1_D3_D5 = 215,
232 D2_D4_D6 = 216,
233 D3_D5_D7 = 217,
234 D4_D6_D8 = 218,
235 D5_D7_D9 = 219,
236 D6_D8_D10 = 220,
237 D7_D9_D11 = 221,
238 D8_D10_D12 = 222,
239 D9_D11_D13 = 223,
240 D10_D12_D14 = 224,
241 D11_D13_D15 = 225,
242 D12_D14_D16 = 226,
243 D13_D15_D17 = 227,
244 D14_D16_D18 = 228,
245 D15_D17_D19 = 229,
246 D16_D18_D20 = 230,
247 D17_D19_D21 = 231,
248 D18_D20_D22 = 232,
249 D19_D21_D23 = 233,
250 D20_D22_D24 = 234,
251 D21_D23_D25 = 235,
252 D22_D24_D26 = 236,
253 D23_D25_D27 = 237,
254 D24_D26_D28 = 238,
255 D25_D27_D29 = 239,
256 D26_D28_D30 = 240,
257 D27_D29_D31 = 241,
258 D0_D2_D4_D6 = 242,
259 D1_D3_D5_D7 = 243,
260 D2_D4_D6_D8 = 244,
261 D3_D5_D7_D9 = 245,
262 D4_D6_D8_D10 = 246,
263 D5_D7_D9_D11 = 247,
264 D6_D8_D10_D12 = 248,
265 D7_D9_D11_D13 = 249,
266 D8_D10_D12_D14 = 250,
267 D9_D11_D13_D15 = 251,
268 D10_D12_D14_D16 = 252,
269 D11_D13_D15_D17 = 253,
270 D12_D14_D16_D18 = 254,
271 D13_D15_D17_D19 = 255,
272 D14_D16_D18_D20 = 256,
273 D15_D17_D19_D21 = 257,
274 D16_D18_D20_D22 = 258,
275 D17_D19_D21_D23 = 259,
276 D18_D20_D22_D24 = 260,
277 D19_D21_D23_D25 = 261,
278 D20_D22_D24_D26 = 262,
279 D21_D23_D25_D27 = 263,
280 D22_D24_D26_D28 = 264,
281 D23_D25_D27_D29 = 265,
282 D24_D26_D28_D30 = 266,
283 D25_D27_D29_D31 = 267,
284 D1_D2 = 268,
285 D3_D4 = 269,
286 D5_D6 = 270,
287 D7_D8 = 271,
288 D9_D10 = 272,
289 D11_D12 = 273,
290 D13_D14 = 274,
291 D15_D16 = 275,
292 D17_D18 = 276,
293 D19_D20 = 277,
294 D21_D22 = 278,
295 D23_D24 = 279,
296 D25_D26 = 280,
297 D27_D28 = 281,
298 D29_D30 = 282,
299 D1_D2_D3_D4 = 283,
300 D3_D4_D5_D6 = 284,
301 D5_D6_D7_D8 = 285,
302 D7_D8_D9_D10 = 286,
303 D9_D10_D11_D12 = 287,
304 D11_D12_D13_D14 = 288,
305 D13_D14_D15_D16 = 289,
306 D15_D16_D17_D18 = 290,
307 D17_D18_D19_D20 = 291,
308 D19_D20_D21_D22 = 292,
309 D21_D22_D23_D24 = 293,
310 D23_D24_D25_D26 = 294,
311 D25_D26_D27_D28 = 295,
312 D27_D28_D29_D30 = 296,
313 NUM_TARGET_REGS // 297
314};
315} // end namespace ARM
316
317// Register classes
318
319namespace ARM {
320enum {
321 HPRRegClassID = 0,
322 FPWithVPRRegClassID = 1,
323 SPRRegClassID = 2,
324 FPWithVPR_with_ssub_0RegClassID = 3,
325 GPRRegClassID = 4,
326 GPRwithAPSRRegClassID = 5,
327 GPRwithZRRegClassID = 6,
328 SPR_8RegClassID = 7,
329 GPRnopcRegClassID = 8,
330 GPRnospRegClassID = 9,
331 GPRwithAPSR_NZCVnospRegClassID = 10,
332 GPRwithAPSRnospRegClassID = 11,
333 GPRwithZRnospRegClassID = 12,
334 GPRnoipRegClassID = 13,
335 rGPRRegClassID = 14,
336 GPRnoip_and_GPRnopcRegClassID = 15,
337 GPRnoip_and_GPRnospRegClassID = 16,
338 GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID = 17,
339 tGPRwithpcRegClassID = 18,
340 FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID = 19,
341 hGPRRegClassID = 20,
342 tGPRRegClassID = 21,
343 tGPREvenRegClassID = 22,
344 GPRnopc_and_hGPRRegClassID = 23,
345 GPRnosp_and_hGPRRegClassID = 24,
346 GPRnoip_and_hGPRRegClassID = 25,
347 GPRnoip_and_tGPREvenRegClassID = 26,
348 GPRnosp_and_GPRnopc_and_hGPRRegClassID = 27,
349 tGPROddRegClassID = 28,
350 GPRnopc_and_GPRnoip_and_hGPRRegClassID = 29,
351 GPRnosp_and_GPRnoip_and_hGPRRegClassID = 30,
352 tcGPRRegClassID = 31,
353 GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 32,
354 hGPR_and_tGPREvenRegClassID = 33,
355 tGPR_and_tGPREvenRegClassID = 34,
356 tGPR_and_tGPROddRegClassID = 35,
357 tcGPRnotr12RegClassID = 36,
358 tGPREven_and_tcGPRRegClassID = 37,
359 FP_STATUS_REGSRegClassID = 38,
360 hGPR_and_GPRnoip_and_tGPREvenRegClassID = 39,
361 hGPR_and_tGPROddRegClassID = 40,
362 tGPREven_and_tcGPRnotr12RegClassID = 41,
363 tGPROdd_and_tcGPRRegClassID = 42,
364 CCRRegClassID = 43,
365 FPCXTRegsRegClassID = 44,
366 GPRlrRegClassID = 45,
367 GPRspRegClassID = 46,
368 VCCRRegClassID = 47,
369 cl_FPSCR_NZCVRegClassID = 48,
370 hGPR_and_tGPRwithpcRegClassID = 49,
371 hGPR_and_tcGPRRegClassID = 50,
372 DPRRegClassID = 51,
373 DPR_VFP2RegClassID = 52,
374 DPR_8RegClassID = 53,
375 GPRPairRegClassID = 54,
376 GPRPairnospRegClassID = 55,
377 GPRPair_with_gsub_0_in_tGPRRegClassID = 56,
378 GPRPair_with_gsub_0_in_hGPRRegClassID = 57,
379 GPRPair_with_gsub_0_in_tcGPRRegClassID = 58,
380 GPRPair_with_gsub_0_in_tcGPRnotr12RegClassID = 59,
381 GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID = 60,
382 GPRPair_with_gsub_1_in_GPRspRegClassID = 61,
383 DPairSpcRegClassID = 62,
384 DPairSpc_with_ssub_0RegClassID = 63,
385 DPairSpc_with_ssub_4RegClassID = 64,
386 DPairSpc_with_dsub_0_in_DPR_8RegClassID = 65,
387 DPairSpc_with_dsub_2_in_DPR_8RegClassID = 66,
388 DPairRegClassID = 67,
389 DPair_with_ssub_0RegClassID = 68,
390 QPRRegClassID = 69,
391 DPair_with_ssub_2RegClassID = 70,
392 DPair_with_dsub_0_in_DPR_8RegClassID = 71,
393 MQPRRegClassID = 72,
394 QPR_VFP2RegClassID = 73,
395 DPair_with_dsub_1_in_DPR_8RegClassID = 74,
396 QPR_8RegClassID = 75,
397 DTripleRegClassID = 76,
398 DTripleSpcRegClassID = 77,
399 DTripleSpc_with_ssub_0RegClassID = 78,
400 DTriple_with_ssub_0RegClassID = 79,
401 DTriple_with_qsub_0_in_QPRRegClassID = 80,
402 DTriple_with_ssub_2RegClassID = 81,
403 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
404 DTripleSpc_with_ssub_4RegClassID = 83,
405 DTriple_with_ssub_4RegClassID = 84,
406 DTripleSpc_with_ssub_8RegClassID = 85,
407 DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 86,
408 DTriple_with_dsub_0_in_DPR_8RegClassID = 87,
409 DTriple_with_qsub_0_in_MQPRRegClassID = 88,
410 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
411 DTriple_with_dsub_1_in_DPR_8RegClassID = 90,
412 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 91,
413 DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID = 92,
414 DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 93,
415 DTriple_with_dsub_2_in_DPR_8RegClassID = 94,
416 DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 95,
417 DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 96,
418 DTriple_with_qsub_0_in_QPR_8RegClassID = 97,
419 DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID = 98,
420 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 99,
421 DQuadSpcRegClassID = 100,
422 DQuadSpc_with_ssub_0RegClassID = 101,
423 DQuadSpc_with_ssub_4RegClassID = 102,
424 DQuadSpc_with_ssub_8RegClassID = 103,
425 DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 104,
426 DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 105,
427 DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 106,
428 DQuadRegClassID = 107,
429 DQuad_with_ssub_0RegClassID = 108,
430 DQuad_with_ssub_2RegClassID = 109,
431 QQPRRegClassID = 110,
432 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 111,
433 DQuad_with_ssub_4RegClassID = 112,
434 DQuad_with_ssub_6RegClassID = 113,
435 DQuad_with_dsub_0_in_DPR_8RegClassID = 114,
436 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 115,
437 QQPR_with_ssub_0RegClassID = 116,
438 DQuad_with_dsub_1_in_DPR_8RegClassID = 117,
439 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 118,
440 MQQPRRegClassID = 119,
441 DQuad_with_dsub_2_in_DPR_8RegClassID = 120,
442 DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 121,
443 DQuad_with_dsub_3_in_DPR_8RegClassID = 122,
444 DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 123,
445 MQQPR_with_qsub_0_in_QPR_8RegClassID = 124,
446 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 125,
447 MQQPR_with_dsub_2_in_DPR_8RegClassID = 126,
448 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID = 127,
449 QQQQPRRegClassID = 128,
450 QQQQPR_with_ssub_0RegClassID = 129,
451 QQQQPR_with_ssub_4RegClassID = 130,
452 QQQQPR_with_ssub_8RegClassID = 131,
453 MQQQQPRRegClassID = 132,
454 MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID = 133,
455 MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID = 134,
456 MQQQQPR_with_qsub_2_in_QPR_8RegClassID = 135,
457 MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8RegClassID = 136,
458
459};
460} // end namespace ARM
461
462
463// Register alternate name indices
464
465namespace ARM {
466enum {
467 NoRegAltName, // 0
468 RegNamesRaw, // 1
469 NUM_TARGET_REG_ALT_NAMES = 2
470};
471} // end namespace ARM
472
473
474// Subregister indices
475
476namespace ARM {
477enum : uint16_t {
478 NoSubRegister,
479 dsub_0, // 1
480 dsub_1, // 2
481 dsub_2, // 3
482 dsub_3, // 4
483 dsub_4, // 5
484 dsub_5, // 6
485 dsub_6, // 7
486 dsub_7, // 8
487 gsub_0, // 9
488 gsub_1, // 10
489 qqsub_0, // 11
490 qqsub_1, // 12
491 qsub_0, // 13
492 qsub_1, // 14
493 qsub_2, // 15
494 qsub_3, // 16
495 ssub_0, // 17
496 ssub_1, // 18
497 ssub_2, // 19
498 ssub_3, // 20
499 ssub_4, // 21
500 ssub_5, // 22
501 ssub_6, // 23
502 ssub_7, // 24
503 ssub_8, // 25
504 ssub_9, // 26
505 ssub_10, // 27
506 ssub_11, // 28
507 ssub_12, // 29
508 ssub_13, // 30
509 ssub_14, // 31
510 ssub_15, // 32
511 ssub_0_ssub_1_ssub_4_ssub_5, // 33
512 ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34
513 ssub_2_ssub_3_ssub_6_ssub_7, // 35
514 ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36
515 ssub_2_ssub_3_ssub_4_ssub_5, // 37
516 ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38
517 ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39
518 ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40
519 ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41
520 ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42
521 ssub_4_ssub_5_ssub_8_ssub_9, // 43
522 ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44
523 ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45
524 ssub_6_ssub_7_dsub_5, // 46
525 ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47
526 ssub_6_ssub_7_dsub_5_dsub_7, // 48
527 ssub_6_ssub_7_ssub_8_ssub_9, // 49
528 ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50
529 ssub_8_ssub_9_ssub_12_ssub_13, // 51
530 ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52
531 dsub_5_dsub_7, // 53
532 dsub_5_ssub_12_ssub_13_dsub_7, // 54
533 dsub_5_ssub_12_ssub_13, // 55
534 ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56
535 NUM_TARGET_SUBREGS
536};
537} // end namespace ARM
538
539// Register pressure sets enum.
540namespace ARM {
541enum RegisterPressureSets {
542 FPCXTRegs = 0,
543 GPRlr = 1,
544 VCCR = 2,
545 hGPR_and_tGPRwithpc = 3,
546 cl_FPSCR_NZCV = 4,
547 GPRsp = 5,
548 tGPROdd = 6,
549 tcGPR = 7,
550 hGPR = 8,
551 tGPROdd_with_tcGPR = 9,
552 tGPR = 10,
553 tGPR_with_tcGPR = 11,
554 tGPREven = 12,
555 hGPR_with_tGPREven = 13,
556 hGPR_with_tGPROdd = 14,
557 hGPR_with_tcGPR = 15,
558 tGPR_with_tGPREven = 16,
559 GPR = 17,
560 GPRwithZR = 18,
561 GPRwithAPSR_with_GPRwithZR = 19,
562 DQuad_with_dsub_0_in_DPR_8 = 20,
563 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR = 21,
564 HPR = 22,
565 DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 23,
566 DPair_with_ssub_0 = 24,
567 DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 25,
568 DPairSpc_with_ssub_0 = 26,
569 DQuad_with_ssub_0 = 27,
570 DTripleSpc_with_ssub_0 = 28,
571 QQQQPR_with_ssub_0 = 29,
572 DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 30,
573 DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 31,
574 DTriple_with_qsub_0_in_QPR = 32,
575 DPR = 33,
576};
577} // end namespace ARM
578
579} // end namespace llvm
580
581