1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: ARM.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::ARMISD {
14
15enum GenNodeType : unsigned {
16 ADDC = ISD::BUILTIN_OP_END,
17 ADDE,
18 ASRL,
19 ASRS1,
20 BCC_i64,
21 BFI,
22 BR2_JT,
23 BRCOND,
24 BR_JT,
25 CALL,
26 CALL_NOLINK,
27 CALL_PRED,
28 CMN,
29 CMOV,
30 CMP,
31 CMPFP,
32 CMPFPE,
33 CMPFPEw0,
34 CMPFPw0,
35 CMPZ,
36 COPY_STRUCT_BYVAL,
37 CSINC,
38 CSINV,
39 CSNEG,
40 EH_SJLJ_LONGJMP,
41 EH_SJLJ_SETJMP,
42 EH_SJLJ_SETUP_DISPATCH,
43 FMSTAT,
44 INTRET_GLUE,
45 LDRD,
46 LE,
47 LOOP_DEC,
48 LSLL,
49 LSLS,
50 LSRL,
51 LSRS1,
52 MEMBARRIER_MCR,
53 MEMCPY,
54 MEMCPYLOOP,
55 MEMSETLOOP,
56 PIC_ADD,
57 PREDICATE_CAST,
58 PRELOAD,
59 QADD16b,
60 QADD8b,
61 QSUB16b,
62 QSUB8b,
63 RET_GLUE,
64 RRX,
65 SERET_GLUE,
66 SMLAL,
67 SMLALBB,
68 SMLALBT,
69 SMLALD,
70 SMLALDX,
71 SMLALTB,
72 SMLALTT,
73 SMLSLD,
74 SMLSLDX,
75 SMMLAR,
76 SMMLSR,
77 SMULWB,
78 SMULWT,
79 SSAT,
80 STRD,
81 SUBC,
82 SUBE,
83 TC_RETURN,
84 THREAD_POINTER,
85 UMAAL,
86 UMLAL,
87 UQADD16b,
88 UQADD8b,
89 UQSUB16b,
90 UQSUB8b,
91 USAT,
92 VADDLVAps,
93 VADDLVApu,
94 VADDLVAs,
95 VADDLVAu,
96 VADDLVps,
97 VADDLVpu,
98 VADDLVs,
99 VADDLVu,
100 VADDVps,
101 VADDVpu,
102 VADDVs,
103 VADDVu,
104 VBICIMM,
105 VBSP,
106 VCMP,
107 VCMPZ,
108 VCVTL,
109 VCVTN,
110 VDUP,
111 VDUPLANE,
112 VECTOR_REG_CAST,
113 VEXT,
114 VGETLANEs,
115 VGETLANEu,
116 VIDUP,
117 VMAXVs,
118 VMAXVu,
119 VMINVs,
120 VMINVu,
121 VMLALVAps,
122 VMLALVApu,
123 VMLALVAs,
124 VMLALVAu,
125 VMLALVps,
126 VMLALVpu,
127 VMLALVs,
128 VMLALVu,
129 VMLAVps,
130 VMLAVpu,
131 VMLAVs,
132 VMLAVu,
133 VMOVDRR,
134 VMOVFPIMM,
135 VMOVIMM,
136 VMOVN,
137 VMOVRRD,
138 VMOVSR,
139 VMOVhr,
140 VMOVrh,
141 VMULLs,
142 VMULLu,
143 VMVNIMM,
144 VORRIMM,
145 VQDMULH,
146 VQMOVNs,
147 VQMOVNu,
148 VQRSHRNsIMM,
149 VQRSHRNsuIMM,
150 VQRSHRNuIMM,
151 VQSHLsIMM,
152 VQSHLsuIMM,
153 VQSHLuIMM,
154 VQSHRNsIMM,
155 VQSHRNsuIMM,
156 VQSHRNuIMM,
157 VREV16,
158 VREV32,
159 VREV64,
160 VRSHRNIMM,
161 VRSHRsIMM,
162 VRSHRuIMM,
163 VSHLIMM,
164 VSHLs,
165 VSHLu,
166 VSHRNIMM,
167 VSHRsIMM,
168 VSHRuIMM,
169 VSLIIMM,
170 VSRIIMM,
171 VST2_UPD,
172 VST4_UPD,
173 VTBL1,
174 VTBL2,
175 VTRN,
176 VTST,
177 VUZP,
178 VZIP,
179 WIN__CHKSTK,
180 WIN__DBZCHK,
181 WLS,
182 WLSSETUP,
183 Wrapper,
184 WrapperJT,
185 WrapperPIC,
186 t2CALL_BTI,
187 tSECALL,
188};
189
190static constexpr unsigned GENERATED_OPCODE_END = tSECALL + 1;
191
192} // namespace llvm::ARMISD
193
194#endif // GET_SDNODE_ENUM
195
196#ifdef GET_SDNODE_DESC
197#undef GET_SDNODE_DESC
198
199namespace llvm {
200
201
202#ifdef __GNUC__
203#pragma GCC diagnostic push
204#pragma GCC diagnostic ignored "-Woverlength-strings"
205#endif
206static constexpr char ARMSDNodeNamesStorage[] =
207 "\0"
208 "ARMISD::ADDC\0"
209 "ARMISD::ADDE\0"
210 "ARMISD::ASRL\0"
211 "ARMISD::ASRS1\0"
212 "ARMISD::BCC_i64\0"
213 "ARMISD::BFI\0"
214 "ARMISD::BR2_JT\0"
215 "ARMISD::BRCOND\0"
216 "ARMISD::BR_JT\0"
217 "ARMISD::CALL\0"
218 "ARMISD::CALL_NOLINK\0"
219 "ARMISD::CALL_PRED\0"
220 "ARMISD::CMN\0"
221 "ARMISD::CMOV\0"
222 "ARMISD::CMP\0"
223 "ARMISD::CMPFP\0"
224 "ARMISD::CMPFPE\0"
225 "ARMISD::CMPFPEw0\0"
226 "ARMISD::CMPFPw0\0"
227 "ARMISD::CMPZ\0"
228 "ARMISD::COPY_STRUCT_BYVAL\0"
229 "ARMISD::CSINC\0"
230 "ARMISD::CSINV\0"
231 "ARMISD::CSNEG\0"
232 "ARMISD::EH_SJLJ_LONGJMP\0"
233 "ARMISD::EH_SJLJ_SETJMP\0"
234 "ARMISD::EH_SJLJ_SETUP_DISPATCH\0"
235 "ARMISD::FMSTAT\0"
236 "ARMISD::INTRET_GLUE\0"
237 "ARMISD::LDRD\0"
238 "ARMISD::LE\0"
239 "ARMISD::LOOP_DEC\0"
240 "ARMISD::LSLL\0"
241 "ARMISD::LSLS\0"
242 "ARMISD::LSRL\0"
243 "ARMISD::LSRS1\0"
244 "ARMISD::MEMBARRIER_MCR\0"
245 "ARMISD::MEMCPY\0"
246 "ARMISD::MEMCPYLOOP\0"
247 "ARMISD::MEMSETLOOP\0"
248 "ARMISD::PIC_ADD\0"
249 "ARMISD::PREDICATE_CAST\0"
250 "ARMISD::PRELOAD\0"
251 "ARMISD::QADD16b\0"
252 "ARMISD::QADD8b\0"
253 "ARMISD::QSUB16b\0"
254 "ARMISD::QSUB8b\0"
255 "ARMISD::RET_GLUE\0"
256 "ARMISD::RRX\0"
257 "ARMISD::SERET_GLUE\0"
258 "ARMISD::SMLAL\0"
259 "ARMISD::SMLALBB\0"
260 "ARMISD::SMLALBT\0"
261 "ARMISD::SMLALD\0"
262 "ARMISD::SMLALDX\0"
263 "ARMISD::SMLALTB\0"
264 "ARMISD::SMLALTT\0"
265 "ARMISD::SMLSLD\0"
266 "ARMISD::SMLSLDX\0"
267 "ARMISD::SMMLAR\0"
268 "ARMISD::SMMLSR\0"
269 "ARMISD::SMULWB\0"
270 "ARMISD::SMULWT\0"
271 "ARMISD::SSAT\0"
272 "ARMISD::STRD\0"
273 "ARMISD::SUBC\0"
274 "ARMISD::SUBE\0"
275 "ARMISD::TC_RETURN\0"
276 "ARMISD::THREAD_POINTER\0"
277 "ARMISD::UMAAL\0"
278 "ARMISD::UMLAL\0"
279 "ARMISD::UQADD16b\0"
280 "ARMISD::UQADD8b\0"
281 "ARMISD::UQSUB16b\0"
282 "ARMISD::UQSUB8b\0"
283 "ARMISD::USAT\0"
284 "ARMISD::VADDLVAps\0"
285 "ARMISD::VADDLVApu\0"
286 "ARMISD::VADDLVAs\0"
287 "ARMISD::VADDLVAu\0"
288 "ARMISD::VADDLVps\0"
289 "ARMISD::VADDLVpu\0"
290 "ARMISD::VADDLVs\0"
291 "ARMISD::VADDLVu\0"
292 "ARMISD::VADDVps\0"
293 "ARMISD::VADDVpu\0"
294 "ARMISD::VADDVs\0"
295 "ARMISD::VADDVu\0"
296 "ARMISD::VBICIMM\0"
297 "ARMISD::VBSP\0"
298 "ARMISD::VCMP\0"
299 "ARMISD::VCMPZ\0"
300 "ARMISD::VCVTL\0"
301 "ARMISD::VCVTN\0"
302 "ARMISD::VDUP\0"
303 "ARMISD::VDUPLANE\0"
304 "ARMISD::VECTOR_REG_CAST\0"
305 "ARMISD::VEXT\0"
306 "ARMISD::VGETLANEs\0"
307 "ARMISD::VGETLANEu\0"
308 "ARMISD::VIDUP\0"
309 "ARMISD::VMAXVs\0"
310 "ARMISD::VMAXVu\0"
311 "ARMISD::VMINVs\0"
312 "ARMISD::VMINVu\0"
313 "ARMISD::VMLALVAps\0"
314 "ARMISD::VMLALVApu\0"
315 "ARMISD::VMLALVAs\0"
316 "ARMISD::VMLALVAu\0"
317 "ARMISD::VMLALVps\0"
318 "ARMISD::VMLALVpu\0"
319 "ARMISD::VMLALVs\0"
320 "ARMISD::VMLALVu\0"
321 "ARMISD::VMLAVps\0"
322 "ARMISD::VMLAVpu\0"
323 "ARMISD::VMLAVs\0"
324 "ARMISD::VMLAVu\0"
325 "ARMISD::VMOVDRR\0"
326 "ARMISD::VMOVFPIMM\0"
327 "ARMISD::VMOVIMM\0"
328 "ARMISD::VMOVN\0"
329 "ARMISD::VMOVRRD\0"
330 "ARMISD::VMOVSR\0"
331 "ARMISD::VMOVhr\0"
332 "ARMISD::VMOVrh\0"
333 "ARMISD::VMULLs\0"
334 "ARMISD::VMULLu\0"
335 "ARMISD::VMVNIMM\0"
336 "ARMISD::VORRIMM\0"
337 "ARMISD::VQDMULH\0"
338 "ARMISD::VQMOVNs\0"
339 "ARMISD::VQMOVNu\0"
340 "ARMISD::VQRSHRNsIMM\0"
341 "ARMISD::VQRSHRNsuIMM\0"
342 "ARMISD::VQRSHRNuIMM\0"
343 "ARMISD::VQSHLsIMM\0"
344 "ARMISD::VQSHLsuIMM\0"
345 "ARMISD::VQSHLuIMM\0"
346 "ARMISD::VQSHRNsIMM\0"
347 "ARMISD::VQSHRNsuIMM\0"
348 "ARMISD::VQSHRNuIMM\0"
349 "ARMISD::VREV16\0"
350 "ARMISD::VREV32\0"
351 "ARMISD::VREV64\0"
352 "ARMISD::VRSHRNIMM\0"
353 "ARMISD::VRSHRsIMM\0"
354 "ARMISD::VRSHRuIMM\0"
355 "ARMISD::VSHLIMM\0"
356 "ARMISD::VSHLs\0"
357 "ARMISD::VSHLu\0"
358 "ARMISD::VSHRNIMM\0"
359 "ARMISD::VSHRsIMM\0"
360 "ARMISD::VSHRuIMM\0"
361 "ARMISD::VSLIIMM\0"
362 "ARMISD::VSRIIMM\0"
363 "ARMISD::VST2_UPD\0"
364 "ARMISD::VST4_UPD\0"
365 "ARMISD::VTBL1\0"
366 "ARMISD::VTBL2\0"
367 "ARMISD::VTRN\0"
368 "ARMISD::VTST\0"
369 "ARMISD::VUZP\0"
370 "ARMISD::VZIP\0"
371 "ARMISD::WIN__CHKSTK\0"
372 "ARMISD::WIN__DBZCHK\0"
373 "ARMISD::WLS\0"
374 "ARMISD::WLSSETUP\0"
375 "ARMISD::Wrapper\0"
376 "ARMISD::WrapperJT\0"
377 "ARMISD::WrapperPIC\0"
378 "ARMISD::t2CALL_BTI\0"
379 "ARMISD::tSECALL\0"
380 ;
381#ifdef __GNUC__
382#pragma GCC diagnostic pop
383#endif
384
385static constexpr llvm::StringTable
386ARMSDNodeNames = ARMSDNodeNamesStorage;
387
388static const VTByHwModePair ARMVTByHwModeTable[] = {
389 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
390};
391
392static const SDTypeConstraint ARMSDTypeConstraints[] = {
393 /* 0 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::Other},
394 /* 3 */ {SDTCisSameAs, 0, 5, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
395 /* 9 */ {SDTCisVT, 2, 0, 0, MVT::f64}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
396 /* 12 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
397 /* 15 */ {SDTCisVT, 5, 0, 0, MVT::Other}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
398 /* 21 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
399 /* 24 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
400 /* 27 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
401 /* 30 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::f32},
402 /* 32 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::f64},
403 /* 35 */ {SDTCisVT, 3, 0, 0, MVT::v8i8}, {SDTCisVT, 2, 0, 0, MVT::v8i8}, {SDTCisVT, 1, 0, 0, MVT::v8i8}, {SDTCisVT, 0, 0, 0, MVT::v8i8},
404 /* 39 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
405 /* 42 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::v16i8}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
406 /* 45 */ {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisSameAs, 3, 6, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 3, 5, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 3, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
407 /* 53 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisSameAs, 3, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
408 /* 59 */ {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
409 /* 61 */ {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
410 /* 64 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
411 /* 68 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
412 /* 71 */ {SDTCisVT, 1, 0, 0, MVT::Other}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
413 /* 73 */ {SDTCisSameAs, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
414 /* 76 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
415 /* 79 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
416 /* 82 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
417 /* 85 */ {SDTCisVec, 6, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
418 /* 92 */ {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
419 /* 96 */ {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
420 /* 101 */ {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
421 /* 104 */ {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
422 /* 108 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
423 /* 111 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
424 /* 114 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
425 /* 116 */ {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
426 /* 120 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
427 /* 124 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
428 /* 127 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
429 /* 131 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
430 /* 135 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
431 /* 138 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
432 /* 140 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
433 /* 143 */ {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
434 /* 148 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
435 /* 151 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
436 /* 153 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
437 /* 158 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
438 /* 162 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
439 /* 166 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
440};
441
442static const SDNodeDesc ARMSDNodeDescs[] = {
443 {2, 2, 0, 0, 0, 1, 154, 4}, // ADDC
444 {2, 3, 0, 0, 0, 14, 153, 5}, // ADDE
445 {2, 3, 0, 0, 0, 27, 143, 5}, // ASRL
446 {2, 1, 0, 0, 0, 40, 73, 3}, // ASRS1
447 {0, 6, 0|1<<SDNPHasChain, 0, 0, 54, 15, 6}, // BCC_i64
448 {1, 3, 0, 0, 0, 70, 17, 4}, // BFI
449 {0, 3, 0|1<<SDNPHasChain, 0, 0, 82, 39, 3}, // BR2_JT
450 {0, 3, 0|1<<SDNPHasChain, 0, 0, 97, 0, 3}, // BRCOND
451 {0, 2, 0|1<<SDNPHasChain, 0, 0, 112, 40, 2}, // BR_JT
452 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 126, 41, 1}, // CALL
453 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 139, 41, 1}, // CALL_NOLINK
454 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 159, 41, 1}, // CALL_PRED
455 {1, 2, 0, 0, 0, 177, 21, 3}, // CMN
456 {1, 4, 0, 0, 0, 189, 162, 4}, // CMOV
457 {1, 2, 0, 0, 0, 202, 21, 3}, // CMP
458 {1, 2, 0, 0, 0, 214, 24, 3}, // CMPFP
459 {1, 2, 0, 0, 0, 228, 24, 3}, // CMPFPE
460 {1, 1, 0, 0, 0, 243, 25, 2}, // CMPFPEw0
461 {1, 1, 0, 0, 0, 260, 25, 2}, // CMPFPw0
462 {1, 2, 0, 0, 0, 276, 21, 3}, // CMPZ
463 {0, 4, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 289, 17, 4}, // COPY_STRUCT_BYVAL
464 {1, 4, 0, 0, 0, 315, 158, 4}, // CSINC
465 {1, 4, 0, 0, 0, 329, 158, 4}, // CSINV
466 {1, 4, 0, 0, 0, 343, 158, 4}, // CSNEG
467 {0, 2, 0|1<<SDNPHasChain, 0, 0, 357, 59, 2}, // EH_SJLJ_LONGJMP
468 {1, 2, 0|1<<SDNPHasChain, 0, 0, 381, 76, 3}, // EH_SJLJ_SETJMP
469 {0, 0, 0|1<<SDNPHasChain, 0, 0, 404, 0, 0}, // EH_SJLJ_SETUP_DISPATCH
470 {1, 1, 0, 0, 0, 435, 19, 2}, // FMSTAT
471 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 450, 41, 1}, // INTRET_GLUE
472 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 470, 12, 3}, // LDRD
473 {0, 2, 0|1<<SDNPHasChain, 0, 0, 483, 71, 2}, // LE
474 {1, 2, 0|1<<SDNPHasChain, 0, 0, 494, 140, 3}, // LOOP_DEC
475 {2, 3, 0, 0, 0, 511, 143, 5}, // LSLL
476 {2, 2, 0, 0, 0, 524, 154, 4}, // LSLS
477 {2, 3, 0, 0, 0, 537, 143, 5}, // LSRL
478 {2, 1, 0, 0, 0, 550, 73, 3}, // LSRS1
479 {0, 1, 0|1<<SDNPHasChain, 0, 0, 564, 67, 1}, // MEMBARRIER_MCR
480 {2, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 587, 16, 5}, // MEMCPY
481 {0, 3, 0|1<<SDNPHasChain, 0, 0, 602, 50, 3}, // MEMCPYLOOP
482 {0, 3, 0|1<<SDNPHasChain, 0, 0, 621, 42, 3}, // MEMSETLOOP
483 {1, 2, 0, 0, 0, 640, 148, 3}, // PIC_ADD
484 {1, 1, 0, 0, 0, 656, 0, 0}, // PREDICATE_CAST
485 {0, 3, 0|1<<SDNPHasChain, 0, 0, 679, 61, 3}, // PRELOAD
486 {1, 2, 0, 0, 0, 695, 18, 3}, // QADD16b
487 {1, 2, 0, 0, 0, 711, 18, 3}, // QADD8b
488 {1, 2, 0, 0, 0, 726, 18, 3}, // QSUB16b
489 {1, 2, 0, 0, 0, 742, 18, 3}, // QSUB8b
490 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 757, 0, 0}, // RET_GLUE
491 {1, 2, 0, 0, 0, 774, 108, 3}, // RRX
492 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 786, 0, 0}, // SERET_GLUE
493 {2, 4, 0, 0, 0, 805, 3, 6}, // SMLAL
494 {2, 4, 0, 0, 0, 819, 3, 6}, // SMLALBB
495 {2, 4, 0, 0, 0, 835, 3, 6}, // SMLALBT
496 {2, 4, 0, 0, 0, 851, 3, 6}, // SMLALD
497 {2, 4, 0, 0, 0, 866, 3, 6}, // SMLALDX
498 {2, 4, 0, 0, 0, 882, 3, 6}, // SMLALTB
499 {2, 4, 0, 0, 0, 898, 3, 6}, // SMLALTT
500 {2, 4, 0, 0, 0, 914, 3, 6}, // SMLSLD
501 {2, 4, 0, 0, 0, 929, 3, 6}, // SMLSLDX
502 {1, 3, 0, 0, 0, 945, 5, 4}, // SMMLAR
503 {1, 3, 0, 0, 0, 960, 5, 4}, // SMMLSR
504 {1, 2, 0, 0, 0, 975, 140, 3}, // SMULWB
505 {1, 2, 0, 0, 0, 990, 140, 3}, // SMULWT
506 {1, 2, 0, 0, 0, 1005, 151, 2}, // SSAT
507 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1018, 12, 3}, // STRD
508 {2, 2, 0, 0, 0, 1031, 154, 4}, // SUBC
509 {2, 3, 0, 0, 0, 1044, 153, 5}, // SUBE
510 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 1057, 41, 1}, // TC_RETURN
511 {1, 0, 0, 0, 0, 1075, 41, 1}, // THREAD_POINTER
512 {2, 4, 0, 0, 0, 1098, 3, 6}, // UMAAL
513 {2, 4, 0, 0, 0, 1112, 3, 6}, // UMLAL
514 {1, 2, 0, 0, 0, 1126, 18, 3}, // UQADD16b
515 {1, 2, 0, 0, 0, 1143, 18, 3}, // UQADD8b
516 {1, 2, 0, 0, 0, 1159, 18, 3}, // UQSUB16b
517 {1, 2, 0, 0, 0, 1176, 18, 3}, // UQSUB8b
518 {1, 2, 0, 0, 0, 1192, 151, 2}, // USAT
519 {2, 4, 0, 0, 0, 1205, 86, 6}, // VADDLVAps
520 {2, 4, 0, 0, 0, 1223, 86, 6}, // VADDLVApu
521 {2, 3, 0, 0, 0, 1241, 87, 5}, // VADDLVAs
522 {2, 3, 0, 0, 0, 1258, 87, 5}, // VADDLVAu
523 {2, 2, 0, 0, 0, 1275, 92, 4}, // VADDLVps
524 {2, 2, 0, 0, 0, 1292, 92, 4}, // VADDLVpu
525 {2, 1, 0, 0, 0, 1309, 93, 3}, // VADDLVs
526 {2, 1, 0, 0, 0, 1325, 93, 3}, // VADDLVu
527 {1, 2, 0, 0, 0, 1341, 105, 3}, // VADDVps
528 {1, 2, 0, 0, 0, 1357, 105, 3}, // VADDVpu
529 {1, 1, 0, 0, 0, 1373, 101, 3}, // VADDVs
530 {1, 1, 0, 0, 0, 1388, 101, 3}, // VADDVu
531 {1, 2, 0, 0, 0, 1403, 124, 3}, // VBICIMM
532 {1, 3, 0, 0, 0, 1419, 116, 4}, // VBSP
533 {1, 3, 0, 0, 0, 1432, 111, 3}, // VCMP
534 {1, 2, 0, 0, 0, 1445, 166, 1}, // VCMPZ
535 {1, 2, 0, 0, 0, 1459, 135, 3}, // VCVTL
536 {1, 3, 0, 0, 0, 1473, 127, 4}, // VCVTN
537 {1, 1, 0, 0, 0, 1487, 119, 1}, // VDUP
538 {1, 2, 0, 0, 0, 1500, 135, 3}, // VDUPLANE
539 {1, 1, 0, 0, 0, 1517, 0, 0}, // VECTOR_REG_CAST
540 {1, 3, 0, 0, 0, 1541, 120, 4}, // VEXT
541 {1, 2, 0, 0, 0, 1554, 27, 3}, // VGETLANEs
542 {1, 2, 0, 0, 0, 1572, 27, 3}, // VGETLANEu
543 {2, 2, 0, 0, 0, 1590, 131, 4}, // VIDUP
544 {1, 2, 0, 0, 0, 1604, 93, 3}, // VMAXVs
545 {1, 2, 0, 0, 0, 1619, 93, 3}, // VMAXVu
546 {1, 2, 0, 0, 0, 1634, 93, 3}, // VMINVs
547 {1, 2, 0, 0, 0, 1649, 93, 3}, // VMINVu
548 {2, 5, 0, 0, 0, 1664, 85, 7}, // VMLALVAps
549 {2, 5, 0, 0, 0, 1682, 85, 7}, // VMLALVApu
550 {2, 4, 0, 0, 0, 1700, 86, 6}, // VMLALVAs
551 {2, 4, 0, 0, 0, 1717, 86, 6}, // VMLALVAu
552 {2, 3, 0, 0, 0, 1734, 96, 5}, // VMLALVps
553 {2, 3, 0, 0, 0, 1751, 96, 5}, // VMLALVpu
554 {2, 2, 0, 0, 0, 1768, 97, 4}, // VMLALVs
555 {2, 2, 0, 0, 0, 1784, 97, 4}, // VMLALVu
556 {1, 3, 0, 0, 0, 1800, 104, 4}, // VMLAVps
557 {1, 3, 0, 0, 0, 1816, 104, 4}, // VMLAVpu
558 {1, 2, 0, 0, 0, 1832, 105, 3}, // VMLAVs
559 {1, 2, 0, 0, 0, 1847, 105, 3}, // VMLAVu
560 {1, 2, 0, 0, 0, 1862, 32, 3}, // VMOVDRR
561 {1, 1, 0, 0, 0, 1878, 133, 2}, // VMOVFPIMM
562 {1, 1, 0, 0, 0, 1896, 133, 2}, // VMOVIMM
563 {1, 3, 0, 0, 0, 1912, 120, 4}, // VMOVN
564 {2, 1, 0, 0, 0, 1926, 9, 3}, // VMOVRRD
565 {1, 1, 0, 0, 0, 1942, 30, 2}, // VMOVSR
566 {1, 1, 0, 0, 0, 1957, 114, 2}, // VMOVhr
567 {1, 1, 0, 0, 0, 1972, 25, 2}, // VMOVrh
568 {1, 2, 0, 0, 0, 1987, 79, 3}, // VMULLs
569 {1, 2, 0, 0, 0, 2002, 79, 3}, // VMULLu
570 {1, 1, 0, 0, 0, 2017, 133, 2}, // VMVNIMM
571 {1, 2, 0, 0, 0, 2033, 124, 3}, // VORRIMM
572 {1, 2, 0, 0, 0, 2049, 140, 3}, // VQDMULH
573 {1, 3, 0, 0, 0, 2065, 127, 4}, // VQMOVNs
574 {1, 3, 0, 0, 0, 2081, 127, 4}, // VQMOVNu
575 {1, 2, 0, 0, 0, 2097, 82, 3}, // VQRSHRNsIMM
576 {1, 2, 0, 0, 0, 2117, 82, 3}, // VQRSHRNsuIMM
577 {1, 2, 0, 0, 0, 2138, 82, 3}, // VQRSHRNuIMM
578 {1, 2, 0, 0, 0, 2158, 68, 3}, // VQSHLsIMM
579 {1, 2, 0, 0, 0, 2176, 68, 3}, // VQSHLsuIMM
580 {1, 2, 0, 0, 0, 2195, 68, 3}, // VQSHLuIMM
581 {1, 2, 0, 0, 0, 2213, 82, 3}, // VQSHRNsIMM
582 {1, 2, 0, 0, 0, 2232, 82, 3}, // VQSHRNsuIMM
583 {1, 2, 0, 0, 0, 2252, 82, 3}, // VQSHRNuIMM
584 {1, 1, 0, 0, 0, 2271, 118, 2}, // VREV16
585 {1, 1, 0, 0, 0, 2286, 118, 2}, // VREV32
586 {1, 1, 0, 0, 0, 2301, 118, 2}, // VREV64
587 {1, 2, 0, 0, 0, 2316, 82, 3}, // VRSHRNIMM
588 {1, 2, 0, 0, 0, 2334, 68, 3}, // VRSHRsIMM
589 {1, 2, 0, 0, 0, 2352, 68, 3}, // VRSHRuIMM
590 {1, 2, 0, 0, 0, 2370, 68, 3}, // VSHLIMM
591 {1, 2, 0, 0, 0, 2386, 65, 3}, // VSHLs
592 {1, 2, 0, 0, 0, 2400, 65, 3}, // VSHLu
593 {1, 2, 0, 0, 0, 2414, 82, 3}, // VSHRNIMM
594 {1, 2, 0, 0, 0, 2431, 68, 3}, // VSHRsIMM
595 {1, 2, 0, 0, 0, 2448, 68, 3}, // VSHRuIMM
596 {1, 3, 0, 0, 0, 2465, 64, 4}, // VSLIIMM
597 {1, 3, 0, 0, 0, 2481, 64, 4}, // VSRIIMM
598 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2497, 53, 6}, // VST2_UPD
599 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2514, 45, 8}, // VST4_UPD
600 {1, 2, 0, 0, 0, 2531, 36, 3}, // VTBL1
601 {1, 3, 0, 0, 0, 2545, 35, 4}, // VTBL2
602 {2, 2, 0, 0, 0, 2559, 116, 4}, // VTRN
603 {1, 2, 0, 0, 0, 2572, 112, 2}, // VTST
604 {2, 2, 0, 0, 0, 2585, 116, 4}, // VUZP
605 {2, 2, 0, 0, 0, 2598, 116, 4}, // VZIP
606 {0, 0, 0|1<<SDNPHasChain, 0, 0, 2611, 0, 0}, // WIN__CHKSTK
607 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue, 0, 0, 2631, 8, 1}, // WIN__DBZCHK
608 {0, 2, 0|1<<SDNPHasChain, 0, 0, 2651, 71, 2}, // WLS
609 {1, 1, 0, 0, 0, 2663, 109, 2}, // WLSSETUP
610 {1, 1, 0, 0, 0, 2680, 138, 2}, // Wrapper
611 {1, 1, 0, 0, 0, 2696, 138, 2}, // WrapperJT
612 {1, 1, 0, 0, 0, 2714, 138, 2}, // WrapperPIC
613 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 2733, 41, 1}, // t2CALL_BTI
614 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 2752, 41, 1}, // tSECALL
615};
616
617static const SDNodeInfo ARMGenSDNodeInfo(
618 /*NumOpcodes=*/172, ARMSDNodeDescs, ARMSDNodeNames,
619 ARMVTByHwModeTable, ARMSDTypeConstraints);
620
621} // namespace llvm
622
623#endif // GET_SDNODE_DESC
624
625