1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AVR.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands);
18 void convertToMapAndConstraints(unsigned Kind,
19 const OperandVector &Operands) override;
20 unsigned MatchInstructionImpl(const OperandVector &Operands,
21 MCInst &Inst,
22 uint64_t &ErrorInfo,
23 FeatureBitset &MissingFeatures,
24 bool matchingInlineAsm,
25 unsigned VariantID = 0);
26 unsigned MatchInstructionImpl(const OperandVector &Operands,
27 MCInst &Inst,
28 uint64_t &ErrorInfo,
29 bool matchingInlineAsm,
30 unsigned VariantID = 0) {
31 FeatureBitset MissingFeatures;
32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33 matchingInlineAsm, VariantID);
34 }
35
36 ParseStatus MatchOperandParserImpl(
37 OperandVector &Operands,
38 StringRef Mnemonic,
39 bool ParseForAllFeatures = false);
40 ParseStatus tryCustomParseOperand(
41 OperandVector &Operands,
42 unsigned MCK);
43
44#endif // GET_ASSEMBLER_HEADER
45
46
47#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
48#undef GET_OPERAND_DIAGNOSTIC_TYPES
49
50#endif // GET_OPERAND_DIAGNOSTIC_TYPES
51
52
53#ifdef GET_REGISTER_MATCHER
54#undef GET_REGISTER_MATCHER
55
56// Bits for subtarget features that participate in instruction matching.
57enum SubtargetFeatureBits : uint8_t {
58 Feature_HasSRAMBit = 14,
59 Feature_HasJMPCALLBit = 7,
60 Feature_HasIJMPCALLBit = 6,
61 Feature_HasEIJMPCALLBit = 3,
62 Feature_HasADDSUBIWBit = 0,
63 Feature_HasSmallStackBit = 15,
64 Feature_HasMOVWBit = 10,
65 Feature_HasLPMBit = 8,
66 Feature_HasLPMXBit = 9,
67 Feature_HasELPMBit = 4,
68 Feature_HasELPMXBit = 5,
69 Feature_HasSPMBit = 12,
70 Feature_HasSPMXBit = 13,
71 Feature_HasDESBit = 2,
72 Feature_SupportsRMWBit = 18,
73 Feature_SupportsMultiplicationBit = 17,
74 Feature_HasBREAKBit = 1,
75 Feature_HasTinyEncodingBit = 16,
76 Feature_HasNonTinyEncodingBit = 11,
77};
78
79static MCRegister MatchRegisterName(StringRef Name) {
80 switch (Name.size()) {
81 default: break;
82 case 2: // 11 strings to match.
83 switch (Name[0]) {
84 default: break;
85 case 'S': // 1 string to match.
86 if (Name[1] != 'P')
87 break;
88 return AVR::SP; // "SP"
89 case 'r': // 10 strings to match.
90 switch (Name[1]) {
91 default: break;
92 case '0': // 1 string to match.
93 return AVR::R0; // "r0"
94 case '1': // 1 string to match.
95 return AVR::R1; // "r1"
96 case '2': // 1 string to match.
97 return AVR::R2; // "r2"
98 case '3': // 1 string to match.
99 return AVR::R3; // "r3"
100 case '4': // 1 string to match.
101 return AVR::R4; // "r4"
102 case '5': // 1 string to match.
103 return AVR::R5; // "r5"
104 case '6': // 1 string to match.
105 return AVR::R6; // "r6"
106 case '7': // 1 string to match.
107 return AVR::R7; // "r7"
108 case '8': // 1 string to match.
109 return AVR::R8; // "r8"
110 case '9': // 1 string to match.
111 return AVR::R9; // "r9"
112 }
113 break;
114 }
115 break;
116 case 3: // 24 strings to match.
117 switch (Name[0]) {
118 default: break;
119 case 'S': // 2 strings to match.
120 if (Name[1] != 'P')
121 break;
122 switch (Name[2]) {
123 default: break;
124 case 'H': // 1 string to match.
125 return AVR::SPH; // "SPH"
126 case 'L': // 1 string to match.
127 return AVR::SPL; // "SPL"
128 }
129 break;
130 case 'r': // 22 strings to match.
131 switch (Name[1]) {
132 default: break;
133 case '1': // 10 strings to match.
134 switch (Name[2]) {
135 default: break;
136 case '0': // 1 string to match.
137 return AVR::R10; // "r10"
138 case '1': // 1 string to match.
139 return AVR::R11; // "r11"
140 case '2': // 1 string to match.
141 return AVR::R12; // "r12"
142 case '3': // 1 string to match.
143 return AVR::R13; // "r13"
144 case '4': // 1 string to match.
145 return AVR::R14; // "r14"
146 case '5': // 1 string to match.
147 return AVR::R15; // "r15"
148 case '6': // 1 string to match.
149 return AVR::R16; // "r16"
150 case '7': // 1 string to match.
151 return AVR::R17; // "r17"
152 case '8': // 1 string to match.
153 return AVR::R18; // "r18"
154 case '9': // 1 string to match.
155 return AVR::R19; // "r19"
156 }
157 break;
158 case '2': // 10 strings to match.
159 switch (Name[2]) {
160 default: break;
161 case '0': // 1 string to match.
162 return AVR::R20; // "r20"
163 case '1': // 1 string to match.
164 return AVR::R21; // "r21"
165 case '2': // 1 string to match.
166 return AVR::R22; // "r22"
167 case '3': // 1 string to match.
168 return AVR::R23; // "r23"
169 case '4': // 1 string to match.
170 return AVR::R24; // "r24"
171 case '5': // 1 string to match.
172 return AVR::R25; // "r25"
173 case '6': // 1 string to match.
174 return AVR::R26; // "r26"
175 case '7': // 1 string to match.
176 return AVR::R27; // "r27"
177 case '8': // 1 string to match.
178 return AVR::R28; // "r28"
179 case '9': // 1 string to match.
180 return AVR::R29; // "r29"
181 }
182 break;
183 case '3': // 2 strings to match.
184 switch (Name[2]) {
185 default: break;
186 case '0': // 1 string to match.
187 return AVR::R30; // "r30"
188 case '1': // 1 string to match.
189 return AVR::R31; // "r31"
190 }
191 break;
192 }
193 break;
194 }
195 break;
196 case 5: // 6 strings to match.
197 switch (Name[0]) {
198 default: break;
199 case 'F': // 1 string to match.
200 if (memcmp(Name.data()+1, "LAGS", 4) != 0)
201 break;
202 return AVR::SREG; // "FLAGS"
203 case 'r': // 5 strings to match.
204 switch (Name[1]) {
205 default: break;
206 case '1': // 1 string to match.
207 if (memcmp(Name.data()+2, ":r0", 3) != 0)
208 break;
209 return AVR::R1R0; // "r1:r0"
210 case '3': // 1 string to match.
211 if (memcmp(Name.data()+2, ":r2", 3) != 0)
212 break;
213 return AVR::R3R2; // "r3:r2"
214 case '5': // 1 string to match.
215 if (memcmp(Name.data()+2, ":r4", 3) != 0)
216 break;
217 return AVR::R5R4; // "r5:r4"
218 case '7': // 1 string to match.
219 if (memcmp(Name.data()+2, ":r6", 3) != 0)
220 break;
221 return AVR::R7R6; // "r7:r6"
222 case '9': // 1 string to match.
223 if (memcmp(Name.data()+2, ":r8", 3) != 0)
224 break;
225 return AVR::R9R8; // "r9:r8"
226 }
227 break;
228 }
229 break;
230 case 6: // 1 string to match.
231 if (memcmp(Name.data()+0, "r10:r9", 6) != 0)
232 break;
233 return AVR::R10R9; // "r10:r9"
234 case 7: // 19 strings to match.
235 if (Name[0] != 'r')
236 break;
237 switch (Name[1]) {
238 default: break;
239 case '1': // 9 strings to match.
240 switch (Name[2]) {
241 default: break;
242 case '1': // 1 string to match.
243 if (memcmp(Name.data()+3, ":r10", 4) != 0)
244 break;
245 return AVR::R11R10; // "r11:r10"
246 case '2': // 1 string to match.
247 if (memcmp(Name.data()+3, ":r11", 4) != 0)
248 break;
249 return AVR::R12R11; // "r12:r11"
250 case '3': // 1 string to match.
251 if (memcmp(Name.data()+3, ":r12", 4) != 0)
252 break;
253 return AVR::R13R12; // "r13:r12"
254 case '4': // 1 string to match.
255 if (memcmp(Name.data()+3, ":r13", 4) != 0)
256 break;
257 return AVR::R14R13; // "r14:r13"
258 case '5': // 1 string to match.
259 if (memcmp(Name.data()+3, ":r14", 4) != 0)
260 break;
261 return AVR::R15R14; // "r15:r14"
262 case '6': // 1 string to match.
263 if (memcmp(Name.data()+3, ":r15", 4) != 0)
264 break;
265 return AVR::R16R15; // "r16:r15"
266 case '7': // 1 string to match.
267 if (memcmp(Name.data()+3, ":r16", 4) != 0)
268 break;
269 return AVR::R17R16; // "r17:r16"
270 case '8': // 1 string to match.
271 if (memcmp(Name.data()+3, ":r17", 4) != 0)
272 break;
273 return AVR::R18R17; // "r18:r17"
274 case '9': // 1 string to match.
275 if (memcmp(Name.data()+3, ":r18", 4) != 0)
276 break;
277 return AVR::R19R18; // "r19:r18"
278 }
279 break;
280 case '2': // 9 strings to match.
281 switch (Name[2]) {
282 default: break;
283 case '0': // 1 string to match.
284 if (memcmp(Name.data()+3, ":r19", 4) != 0)
285 break;
286 return AVR::R20R19; // "r20:r19"
287 case '1': // 1 string to match.
288 if (memcmp(Name.data()+3, ":r20", 4) != 0)
289 break;
290 return AVR::R21R20; // "r21:r20"
291 case '2': // 1 string to match.
292 if (memcmp(Name.data()+3, ":r21", 4) != 0)
293 break;
294 return AVR::R22R21; // "r22:r21"
295 case '3': // 1 string to match.
296 if (memcmp(Name.data()+3, ":r22", 4) != 0)
297 break;
298 return AVR::R23R22; // "r23:r22"
299 case '4': // 1 string to match.
300 if (memcmp(Name.data()+3, ":r23", 4) != 0)
301 break;
302 return AVR::R24R23; // "r24:r23"
303 case '5': // 1 string to match.
304 if (memcmp(Name.data()+3, ":r24", 4) != 0)
305 break;
306 return AVR::R25R24; // "r25:r24"
307 case '6': // 1 string to match.
308 if (memcmp(Name.data()+3, ":r25", 4) != 0)
309 break;
310 return AVR::R26R25; // "r26:r25"
311 case '7': // 1 string to match.
312 if (memcmp(Name.data()+3, ":r26", 4) != 0)
313 break;
314 return AVR::R27R26; // "r27:r26"
315 case '9': // 1 string to match.
316 if (memcmp(Name.data()+3, ":r28", 4) != 0)
317 break;
318 return AVR::R29R28; // "r29:r28"
319 }
320 break;
321 case '3': // 1 string to match.
322 if (memcmp(Name.data()+2, "1:r30", 5) != 0)
323 break;
324 return AVR::R31R30; // "r31:r30"
325 }
326 break;
327 }
328 return AVR::NoRegister;
329}
330
331static MCRegister MatchRegisterAltName(StringRef Name) {
332 switch (Name.size()) {
333 default: break;
334 case 1: // 3 strings to match.
335 switch (Name[0]) {
336 default: break;
337 case 'X': // 1 string to match.
338 return AVR::R27R26; // "X"
339 case 'Y': // 1 string to match.
340 return AVR::R29R28; // "Y"
341 case 'Z': // 1 string to match.
342 return AVR::R31R30; // "Z"
343 }
344 break;
345 case 2: // 6 strings to match.
346 switch (Name[0]) {
347 default: break;
348 case 'x': // 2 strings to match.
349 switch (Name[1]) {
350 default: break;
351 case 'h': // 1 string to match.
352 return AVR::R27; // "xh"
353 case 'l': // 1 string to match.
354 return AVR::R26; // "xl"
355 }
356 break;
357 case 'y': // 2 strings to match.
358 switch (Name[1]) {
359 default: break;
360 case 'h': // 1 string to match.
361 return AVR::R29; // "yh"
362 case 'l': // 1 string to match.
363 return AVR::R28; // "yl"
364 }
365 break;
366 case 'z': // 2 strings to match.
367 switch (Name[1]) {
368 default: break;
369 case 'h': // 1 string to match.
370 return AVR::R31; // "zh"
371 case 'l': // 1 string to match.
372 return AVR::R30; // "zl"
373 }
374 break;
375 }
376 break;
377 }
378 return AVR::NoRegister;
379}
380
381#endif // GET_REGISTER_MATCHER
382
383
384#ifdef GET_SUBTARGET_FEATURE_NAME
385#undef GET_SUBTARGET_FEATURE_NAME
386
387// User-level names for subtarget features that participate in
388// instruction matching.
389static const char *getSubtargetFeatureName(uint64_t Val) {
390 switch(Val) {
391 case Feature_HasSRAMBit: return "";
392 case Feature_HasJMPCALLBit: return "";
393 case Feature_HasIJMPCALLBit: return "";
394 case Feature_HasEIJMPCALLBit: return "";
395 case Feature_HasADDSUBIWBit: return "";
396 case Feature_HasSmallStackBit: return "";
397 case Feature_HasMOVWBit: return "";
398 case Feature_HasLPMBit: return "";
399 case Feature_HasLPMXBit: return "";
400 case Feature_HasELPMBit: return "";
401 case Feature_HasELPMXBit: return "";
402 case Feature_HasSPMBit: return "";
403 case Feature_HasSPMXBit: return "";
404 case Feature_HasDESBit: return "";
405 case Feature_SupportsRMWBit: return "";
406 case Feature_SupportsMultiplicationBit: return "";
407 case Feature_HasBREAKBit: return "";
408 case Feature_HasTinyEncodingBit: return "";
409 case Feature_HasNonTinyEncodingBit: return "";
410 default: return "(unknown)";
411 }
412}
413
414#endif // GET_SUBTARGET_FEATURE_NAME
415
416
417#ifdef GET_MATCHER_IMPLEMENTATION
418#undef GET_MATCHER_IMPLEMENTATION
419
420enum {
421 Tie0_1_1,
422 Tie0_2_2,
423 Tie1_2_2,
424 Tie1_3_3,
425};
426
427static const uint8_t TiedAsmOperandTable[][3] = {
428 /* Tie0_1_1 */ { 0, 1, 1 },
429 /* Tie0_2_2 */ { 0, 2, 2 },
430 /* Tie1_2_2 */ { 1, 2, 2 },
431 /* Tie1_3_3 */ { 1, 3, 3 },
432};
433
434namespace {
435enum OperatorConversionKind {
436 CVT_Done,
437 CVT_Reg,
438 CVT_Tied,
439 CVT_95_Reg,
440 CVT_95_addImmOperands,
441 CVT_imm_95_0,
442 CVT_imm_95_5,
443 CVT_imm_95_7,
444 CVT_imm_95_6,
445 CVT_imm_95_3,
446 CVT_95_addImmCom8Operands,
447 CVT_imm_95_2,
448 CVT_imm_95_4,
449 CVT_imm_95_1,
450 CVT_95_addMemriOperands,
451 CVT_imm_95_255,
452 CVT_NUM_CONVERTERS
453};
454
455enum InstructionConversionKind {
456 Convert__Reg1_0__Tie0_1_1__Reg1_1,
457 Convert__Reg1_0__Tie0_1_1__Imm1_1,
458 Convert__Reg1_0__Tie0_1_1,
459 Convert__Imm1_0,
460 Convert__Imm1_0__Imm1_1,
461 Convert__imm_95_0__Imm1_0,
462 Convert_NoOperands,
463 Convert__imm_95_5__Imm1_0,
464 Convert__imm_95_7__Imm1_0,
465 Convert__imm_95_6__Imm1_0,
466 Convert__imm_95_3__Imm1_0,
467 Convert__Reg1_0__Imm1_1,
468 Convert__Reg1_0__Tie0_1_1__ImmCom81_1,
469 Convert__imm_95_0,
470 Convert__imm_95_5,
471 Convert__imm_95_7,
472 Convert__imm_95_2,
473 Convert__Reg1_0__Tie0_1_1__Reg1_0,
474 Convert__imm_95_4,
475 Convert__imm_95_6,
476 Convert__imm_95_3,
477 Convert__imm_95_1,
478 Convert__Reg1_0__Reg1_1,
479 Convert__Reg1_1__Reg1_0,
480 Convert__Reg1_0__Reg1_2__Tie1_3_3,
481 Convert__Reg1_0__Reg1_1__Tie1_2_2,
482 Convert__Reg1_0__Memri2_1,
483 Convert__Imm1_0__Reg1_1,
484 Convert__Reg1_0,
485 Convert__Reg1_0__imm_95_255,
486 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0,
487 Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0,
488 Convert__Memri2_0__Reg1_1,
489 CVT_NUM_SIGNATURES
490};
491
492} // end anonymous namespace
493
494static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
495 // Convert__Reg1_0__Tie0_1_1__Reg1_1
496 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
497 // Convert__Reg1_0__Tie0_1_1__Imm1_1
498 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
499 // Convert__Reg1_0__Tie0_1_1
500 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
501 // Convert__Imm1_0
502 { CVT_95_addImmOperands, 1, CVT_Done },
503 // Convert__Imm1_0__Imm1_1
504 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
505 // Convert__imm_95_0__Imm1_0
506 { CVT_imm_95_0, 0, CVT_95_addImmOperands, 1, CVT_Done },
507 // Convert_NoOperands
508 { CVT_Done },
509 // Convert__imm_95_5__Imm1_0
510 { CVT_imm_95_5, 0, CVT_95_addImmOperands, 1, CVT_Done },
511 // Convert__imm_95_7__Imm1_0
512 { CVT_imm_95_7, 0, CVT_95_addImmOperands, 1, CVT_Done },
513 // Convert__imm_95_6__Imm1_0
514 { CVT_imm_95_6, 0, CVT_95_addImmOperands, 1, CVT_Done },
515 // Convert__imm_95_3__Imm1_0
516 { CVT_imm_95_3, 0, CVT_95_addImmOperands, 1, CVT_Done },
517 // Convert__Reg1_0__Imm1_1
518 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
519 // Convert__Reg1_0__Tie0_1_1__ImmCom81_1
520 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmCom8Operands, 2, CVT_Done },
521 // Convert__imm_95_0
522 { CVT_imm_95_0, 0, CVT_Done },
523 // Convert__imm_95_5
524 { CVT_imm_95_5, 0, CVT_Done },
525 // Convert__imm_95_7
526 { CVT_imm_95_7, 0, CVT_Done },
527 // Convert__imm_95_2
528 { CVT_imm_95_2, 0, CVT_Done },
529 // Convert__Reg1_0__Tie0_1_1__Reg1_0
530 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
531 // Convert__imm_95_4
532 { CVT_imm_95_4, 0, CVT_Done },
533 // Convert__imm_95_6
534 { CVT_imm_95_6, 0, CVT_Done },
535 // Convert__imm_95_3
536 { CVT_imm_95_3, 0, CVT_Done },
537 // Convert__imm_95_1
538 { CVT_imm_95_1, 0, CVT_Done },
539 // Convert__Reg1_0__Reg1_1
540 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
541 // Convert__Reg1_1__Reg1_0
542 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
543 // Convert__Reg1_0__Reg1_2__Tie1_3_3
544 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_Done },
545 // Convert__Reg1_0__Reg1_1__Tie1_2_2
546 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie1_2_2, CVT_Done },
547 // Convert__Reg1_0__Memri2_1
548 { CVT_95_Reg, 1, CVT_95_addMemriOperands, 2, CVT_Done },
549 // Convert__Imm1_0__Reg1_1
550 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
551 // Convert__Reg1_0
552 { CVT_95_Reg, 1, CVT_Done },
553 // Convert__Reg1_0__imm_95_255
554 { CVT_95_Reg, 1, CVT_imm_95_255, 0, CVT_Done },
555 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0
556 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
557 // Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0
558 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
559 // Convert__Memri2_0__Reg1_1
560 { CVT_95_addMemriOperands, 1, CVT_95_Reg, 2, CVT_Done },
561};
562
563void AVRAsmParser::
564convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
565 const OperandVector &Operands) {
566 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
567 const uint8_t *Converter = ConversionTable[Kind];
568 Inst.setOpcode(Opcode);
569 for (const uint8_t *p = Converter; *p; p += 2) {
570 unsigned OpIdx = *(p + 1);
571 switch (*p) {
572 default: llvm_unreachable("invalid conversion entry!");
573 case CVT_Reg:
574 static_cast<AVROperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
575 break;
576 case CVT_Tied: {
577 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
578 std::begin(TiedAsmOperandTable)) &&
579 "Tied operand not found");
580 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
581 if (TiedResOpnd != (uint8_t)-1)
582 Inst.addOperand(Inst.getOperand(TiedResOpnd));
583 break;
584 }
585 case CVT_95_Reg:
586 static_cast<AVROperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
587 break;
588 case CVT_95_addImmOperands:
589 static_cast<AVROperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
590 break;
591 case CVT_imm_95_0:
592 Inst.addOperand(MCOperand::createImm(0));
593 break;
594 case CVT_imm_95_5:
595 Inst.addOperand(MCOperand::createImm(5));
596 break;
597 case CVT_imm_95_7:
598 Inst.addOperand(MCOperand::createImm(7));
599 break;
600 case CVT_imm_95_6:
601 Inst.addOperand(MCOperand::createImm(6));
602 break;
603 case CVT_imm_95_3:
604 Inst.addOperand(MCOperand::createImm(3));
605 break;
606 case CVT_95_addImmCom8Operands:
607 static_cast<AVROperand &>(*Operands[OpIdx]).addImmCom8Operands(Inst, 1);
608 break;
609 case CVT_imm_95_2:
610 Inst.addOperand(MCOperand::createImm(2));
611 break;
612 case CVT_imm_95_4:
613 Inst.addOperand(MCOperand::createImm(4));
614 break;
615 case CVT_imm_95_1:
616 Inst.addOperand(MCOperand::createImm(1));
617 break;
618 case CVT_95_addMemriOperands:
619 static_cast<AVROperand &>(*Operands[OpIdx]).addMemriOperands(Inst, 2);
620 break;
621 case CVT_imm_95_255:
622 Inst.addOperand(MCOperand::createImm(255));
623 break;
624 }
625 }
626}
627
628void AVRAsmParser::
629convertToMapAndConstraints(unsigned Kind,
630 const OperandVector &Operands) {
631 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
632 unsigned NumMCOperands = 0;
633 const uint8_t *Converter = ConversionTable[Kind];
634 for (const uint8_t *p = Converter; *p; p += 2) {
635 switch (*p) {
636 default: llvm_unreachable("invalid conversion entry!");
637 case CVT_Reg:
638 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
639 Operands[*(p + 1)]->setConstraint("r");
640 ++NumMCOperands;
641 break;
642 case CVT_Tied:
643 ++NumMCOperands;
644 break;
645 case CVT_95_Reg:
646 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
647 Operands[*(p + 1)]->setConstraint("r");
648 NumMCOperands += 1;
649 break;
650 case CVT_95_addImmOperands:
651 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
652 Operands[*(p + 1)]->setConstraint("m");
653 NumMCOperands += 1;
654 break;
655 case CVT_imm_95_0:
656 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
657 Operands[*(p + 1)]->setConstraint("");
658 ++NumMCOperands;
659 break;
660 case CVT_imm_95_5:
661 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
662 Operands[*(p + 1)]->setConstraint("");
663 ++NumMCOperands;
664 break;
665 case CVT_imm_95_7:
666 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
667 Operands[*(p + 1)]->setConstraint("");
668 ++NumMCOperands;
669 break;
670 case CVT_imm_95_6:
671 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
672 Operands[*(p + 1)]->setConstraint("");
673 ++NumMCOperands;
674 break;
675 case CVT_imm_95_3:
676 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
677 Operands[*(p + 1)]->setConstraint("");
678 ++NumMCOperands;
679 break;
680 case CVT_95_addImmCom8Operands:
681 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
682 Operands[*(p + 1)]->setConstraint("m");
683 NumMCOperands += 1;
684 break;
685 case CVT_imm_95_2:
686 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
687 Operands[*(p + 1)]->setConstraint("");
688 ++NumMCOperands;
689 break;
690 case CVT_imm_95_4:
691 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
692 Operands[*(p + 1)]->setConstraint("");
693 ++NumMCOperands;
694 break;
695 case CVT_imm_95_1:
696 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
697 Operands[*(p + 1)]->setConstraint("");
698 ++NumMCOperands;
699 break;
700 case CVT_95_addMemriOperands:
701 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
702 Operands[*(p + 1)]->setConstraint("m");
703 NumMCOperands += 2;
704 break;
705 case CVT_imm_95_255:
706 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
707 Operands[*(p + 1)]->setConstraint("");
708 ++NumMCOperands;
709 break;
710 }
711 }
712}
713
714namespace {
715
716/// MatchClassKind - The kinds of classes which participate in
717/// instruction matching.
718enum MatchClassKind {
719 InvalidMatchClass = 0,
720 OptionalMatchClass = 1,
721 MCK__43_, // '+'
722 MCK__MINUS_, // '-'
723 MCK_LAST_TOKEN = MCK__MINUS_,
724 MCK_Reg31, // derived register class
725 MCK_Reg16, // derived register class
726 MCK_CCR, // register class 'CCR'
727 MCK_GPRSP, // register class 'GPRSP'
728 MCK_ZREG, // register class 'ZREG'
729 MCK_Reg17, // derived register class
730 MCK_PTRDISPREGS, // register class 'PTRDISPREGS'
731 MCK_Reg18, // derived register class
732 MCK_PTRREGS, // register class 'PTRREGS'
733 MCK_DREGSLD8lo, // register class 'DREGSLD8lo'
734 MCK_IWREGS, // register class 'IWREGS'
735 MCK_Reg26, // derived register class
736 MCK_Reg19, // derived register class
737 MCK_Reg27, // derived register class
738 MCK_Reg25, // derived register class
739 MCK_DLDREGS, // register class 'DLDREGS'
740 MCK_DREGSlo, // register class 'DREGSlo'
741 MCK_LD8lo, // register class 'LD8lo'
742 MCK_Reg30, // derived register class
743 MCK_Reg29, // derived register class
744 MCK_Reg22, // derived register class
745 MCK_Reg23, // derived register class
746 MCK_Reg14, // derived register class
747 MCK_Reg15, // derived register class
748 MCK_Reg4, // derived register class
749 MCK_Reg20, // derived register class
750 MCK_DREGSMOVW, // register class 'DREGSMOVW'
751 MCK_GPR8lo, // register class 'GPR8lo'
752 MCK_LD8, // register class 'LD8'
753 MCK_DREGSNOZ, // register class 'DREGSNOZ'
754 MCK_DREGS, // register class 'DREGS'
755 MCK_GPR8NOZ, // register class 'GPR8NOZ'
756 MCK_GPR8, // register class 'GPR8'
757 MCK_LAST_REGISTER = MCK_GPR8,
758 MCK_Imm, // user defined class 'ImmAsmOperand'
759 MCK_Memri, // user defined class 'MemriAsmOperand'
760 MCK_ImmCom8, // user defined class 'imm_com8_asmoperand'
761 NumMatchClassKinds
762};
763
764} // end anonymous namespace
765
766static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
767 return MCTargetAsmParser::Match_InvalidOperand;
768}
769
770static MatchClassKind matchTokenString(StringRef Name) {
771 switch (Name.size()) {
772 default: break;
773 case 1: // 2 strings to match.
774 switch (Name[0]) {
775 default: break;
776 case '+': // 1 string to match.
777 return MCK__43_; // "+"
778 case '-': // 1 string to match.
779 return MCK__MINUS_; // "-"
780 }
781 break;
782 }
783 return InvalidMatchClass;
784}
785
786/// isSubclass - Compute whether \p A is a subclass of \p B.
787static bool isSubclass(MatchClassKind A, MatchClassKind B) {
788 if (A == B)
789 return true;
790
791 [[maybe_unused]] static constexpr struct {
792 uint32_t Offset;
793 uint16_t Start;
794 uint16_t Length;
795 } Table[] = {
796 {0, 0, 0},
797 {0, 0, 0},
798 {0, 0, 0},
799 {0, 0, 0},
800 {0, 17, 18},
801 {18, 9, 26},
802 {44, 0, 0},
803 {44, 0, 0},
804 {44, 10, 25},
805 {69, 11, 24},
806 {93, 12, 23},
807 {116, 14, 21},
808 {137, 14, 21},
809 {158, 15, 20},
810 {178, 19, 16},
811 {194, 17, 18},
812 {212, 19, 16},
813 {228, 25, 10},
814 {238, 24, 11},
815 {249, 26, 9},
816 {258, 22, 13},
817 {271, 28, 9},
818 {280, 23, 12},
819 {292, 33, 2},
820 {294, 25, 10},
821 {304, 27, 8},
822 {312, 27, 8},
823 {320, 34, 1},
824 {321, 32, 5},
825 {326, 30, 5},
826 {331, 34, 1},
827 {332, 35, 2},
828 {334, 36, 1},
829 {335, 34, 1},
830 {336, 0, 0},
831 {336, 36, 1},
832 {337, 0, 0},
833 {337, 0, 0},
834 {337, 0, 0},
835 {337, 0, 0},
836 };
837
838 static constexpr uint8_t Data[] = {
839 0x41,
840 0x05,
841 0xBF,
842 0x12,
843 0xDE,
844 0x5C,
845 0x21,
846 0x30,
847 0x71,
848 0x25,
849 0xBC,
850 0xB9,
851 0x10,
852 0x98,
853 0x58,
854 0xC2,
855 0x9B,
856 0x43,
857 0x60,
858 0xE2,
859 0x87,
860 0x37,
861 0x07,
862 0x26,
863 0x0E,
864 0x1E,
865 0x1C,
866 0xDE,
867 0x5C,
868 0xF0,
869 0x83,
870 0x27,
871 0x0E,
872 0xE6,
873 0xC8,
874 0x01,
875 0xFC,
876 0xC1,
877 0xC1,
878 0x81,
879 0x73,
880 0xFE,
881 0x01,
882 };
883
884 auto &Entry = Table[A];
885 unsigned Idx = B - Entry.Start;
886 if (Idx >= Entry.Length)
887 return false;
888 Idx += Entry.Offset;
889 return (Data[Idx / 8] >> (Idx % 8)) & 1;
890}
891
892static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
893 AVROperand &Operand = (AVROperand &)GOp;
894 if (Kind == InvalidMatchClass)
895 return MCTargetAsmParser::Match_InvalidOperand;
896
897 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
898 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
899 MCTargetAsmParser::Match_Success :
900 MCTargetAsmParser::Match_InvalidOperand;
901
902 switch (Kind) {
903 default: break;
904 case MCK_Imm: {
905 DiagnosticPredicate DP(Operand.isImm());
906 if (DP.isMatch())
907 return MCTargetAsmParser::Match_Success;
908 break;
909 }
910 case MCK_Memri: {
911 DiagnosticPredicate DP(Operand.isMemri());
912 if (DP.isMatch())
913 return MCTargetAsmParser::Match_Success;
914 break;
915 }
916 case MCK_ImmCom8: {
917 DiagnosticPredicate DP(Operand.isImmCom8());
918 if (DP.isMatch())
919 return MCTargetAsmParser::Match_Success;
920 break;
921 }
922 } // end switch (Kind)
923
924 if (Operand.isReg()) {
925 static constexpr uint16_t Table[AVR::NUM_TARGET_REGS] = {
926 InvalidMatchClass,
927 MCK_GPRSP,
928 InvalidMatchClass,
929 InvalidMatchClass,
930 MCK_CCR,
931 MCK_GPR8lo,
932 MCK_GPR8lo,
933 MCK_GPR8lo,
934 MCK_GPR8lo,
935 MCK_GPR8lo,
936 MCK_GPR8lo,
937 MCK_GPR8lo,
938 MCK_GPR8lo,
939 MCK_GPR8lo,
940 MCK_GPR8lo,
941 MCK_GPR8lo,
942 MCK_GPR8lo,
943 MCK_GPR8lo,
944 MCK_GPR8lo,
945 MCK_GPR8lo,
946 MCK_GPR8lo,
947 MCK_LD8lo,
948 MCK_LD8lo,
949 MCK_LD8lo,
950 MCK_LD8lo,
951 MCK_LD8lo,
952 MCK_LD8lo,
953 MCK_LD8lo,
954 MCK_LD8lo,
955 MCK_Reg4,
956 MCK_Reg4,
957 MCK_Reg4,
958 MCK_Reg4,
959 MCK_Reg4,
960 MCK_Reg4,
961 MCK_LD8,
962 MCK_LD8,
963 MCK_DREGSlo,
964 MCK_DREGSlo,
965 MCK_DREGSlo,
966 MCK_DREGSlo,
967 MCK_DREGSlo,
968 MCK_Reg30,
969 MCK_DREGSlo,
970 MCK_Reg30,
971 MCK_DREGSlo,
972 MCK_Reg30,
973 MCK_DREGSlo,
974 MCK_Reg31,
975 MCK_DREGSLD8lo,
976 MCK_Reg26,
977 MCK_DREGSLD8lo,
978 MCK_Reg26,
979 MCK_DREGSLD8lo,
980 MCK_Reg26,
981 MCK_DREGSLD8lo,
982 MCK_Reg25,
983 MCK_Reg18,
984 MCK_Reg22,
985 MCK_Reg17,
986 MCK_Reg16,
987 MCK_ZREG,
988 };
989
990 MCRegister Reg = Operand.getReg();
991 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
992 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
993 getDiagKindFromRegisterClass(Kind);
994 }
995
996 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
997 return getDiagKindFromRegisterClass(Kind);
998
999 return MCTargetAsmParser::Match_InvalidOperand;
1000}
1001
1002#ifndef NDEBUG
1003const char *getMatchClassName(MatchClassKind Kind) {
1004 switch (Kind) {
1005 case InvalidMatchClass: return "InvalidMatchClass";
1006 case OptionalMatchClass: return "OptionalMatchClass";
1007 case MCK__43_: return "MCK__43_";
1008 case MCK__MINUS_: return "MCK__MINUS_";
1009 case MCK_Reg31: return "MCK_Reg31";
1010 case MCK_Reg16: return "MCK_Reg16";
1011 case MCK_CCR: return "MCK_CCR";
1012 case MCK_GPRSP: return "MCK_GPRSP";
1013 case MCK_ZREG: return "MCK_ZREG";
1014 case MCK_Reg17: return "MCK_Reg17";
1015 case MCK_PTRDISPREGS: return "MCK_PTRDISPREGS";
1016 case MCK_Reg18: return "MCK_Reg18";
1017 case MCK_PTRREGS: return "MCK_PTRREGS";
1018 case MCK_DREGSLD8lo: return "MCK_DREGSLD8lo";
1019 case MCK_IWREGS: return "MCK_IWREGS";
1020 case MCK_Reg26: return "MCK_Reg26";
1021 case MCK_Reg19: return "MCK_Reg19";
1022 case MCK_Reg27: return "MCK_Reg27";
1023 case MCK_Reg25: return "MCK_Reg25";
1024 case MCK_DLDREGS: return "MCK_DLDREGS";
1025 case MCK_DREGSlo: return "MCK_DREGSlo";
1026 case MCK_LD8lo: return "MCK_LD8lo";
1027 case MCK_Reg30: return "MCK_Reg30";
1028 case MCK_Reg29: return "MCK_Reg29";
1029 case MCK_Reg22: return "MCK_Reg22";
1030 case MCK_Reg23: return "MCK_Reg23";
1031 case MCK_Reg14: return "MCK_Reg14";
1032 case MCK_Reg15: return "MCK_Reg15";
1033 case MCK_Reg4: return "MCK_Reg4";
1034 case MCK_Reg20: return "MCK_Reg20";
1035 case MCK_DREGSMOVW: return "MCK_DREGSMOVW";
1036 case MCK_GPR8lo: return "MCK_GPR8lo";
1037 case MCK_LD8: return "MCK_LD8";
1038 case MCK_DREGSNOZ: return "MCK_DREGSNOZ";
1039 case MCK_DREGS: return "MCK_DREGS";
1040 case MCK_GPR8NOZ: return "MCK_GPR8NOZ";
1041 case MCK_GPR8: return "MCK_GPR8";
1042 case MCK_Imm: return "MCK_Imm";
1043 case MCK_Memri: return "MCK_Memri";
1044 case MCK_ImmCom8: return "MCK_ImmCom8";
1045 case NumMatchClassKinds: return "NumMatchClassKinds";
1046 }
1047 llvm_unreachable("unhandled MatchClassKind!");
1048}
1049
1050#endif // NDEBUG
1051FeatureBitset AVRAsmParser::
1052ComputeAvailableFeatures(const FeatureBitset &FB) const {
1053 FeatureBitset Features;
1054 if (FB[AVR::FeatureSRAM])
1055 Features.set(Feature_HasSRAMBit);
1056 if (FB[AVR::FeatureJMPCALL])
1057 Features.set(Feature_HasJMPCALLBit);
1058 if (FB[AVR::FeatureIJMPCALL])
1059 Features.set(Feature_HasIJMPCALLBit);
1060 if (FB[AVR::FeatureEIJMPCALL])
1061 Features.set(Feature_HasEIJMPCALLBit);
1062 if (FB[AVR::FeatureADDSUBIW])
1063 Features.set(Feature_HasADDSUBIWBit);
1064 if (FB[AVR::FeatureSmallStack])
1065 Features.set(Feature_HasSmallStackBit);
1066 if (FB[AVR::FeatureMOVW])
1067 Features.set(Feature_HasMOVWBit);
1068 if (FB[AVR::FeatureLPM])
1069 Features.set(Feature_HasLPMBit);
1070 if (FB[AVR::FeatureLPMX])
1071 Features.set(Feature_HasLPMXBit);
1072 if (FB[AVR::FeatureELPM])
1073 Features.set(Feature_HasELPMBit);
1074 if (FB[AVR::FeatureELPMX])
1075 Features.set(Feature_HasELPMXBit);
1076 if (FB[AVR::FeatureSPM])
1077 Features.set(Feature_HasSPMBit);
1078 if (FB[AVR::FeatureSPMX])
1079 Features.set(Feature_HasSPMXBit);
1080 if (FB[AVR::FeatureDES])
1081 Features.set(Feature_HasDESBit);
1082 if (FB[AVR::FeatureRMW])
1083 Features.set(Feature_SupportsRMWBit);
1084 if (FB[AVR::FeatureMultiplication])
1085 Features.set(Feature_SupportsMultiplicationBit);
1086 if (FB[AVR::FeatureBREAK])
1087 Features.set(Feature_HasBREAKBit);
1088 if (FB[AVR::FeatureTinyEncoding])
1089 Features.set(Feature_HasTinyEncodingBit);
1090 if (!FB[AVR::FeatureTinyEncoding])
1091 Features.set(Feature_HasNonTinyEncodingBit);
1092 return Features;
1093}
1094
1095static bool checkAsmTiedOperandConstraints(const AVRAsmParser&AsmParser,
1096 unsigned Kind, const OperandVector &Operands,
1097 uint64_t &ErrorInfo) {
1098 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1099 const uint8_t *Converter = ConversionTable[Kind];
1100 for (const uint8_t *p = Converter; *p; p += 2) {
1101 switch (*p) {
1102 case CVT_Tied: {
1103 unsigned OpIdx = *(p + 1);
1104 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1105 std::begin(TiedAsmOperandTable)) &&
1106 "Tied operand not found");
1107 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
1108 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
1109 if (OpndNum1 != OpndNum2) {
1110 auto &SrcOp1 = Operands[OpndNum1];
1111 auto &SrcOp2 = Operands[OpndNum2];
1112 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
1113 ErrorInfo = OpndNum2;
1114 return false;
1115 }
1116 }
1117 break;
1118 }
1119 default:
1120 break;
1121 }
1122 }
1123 return true;
1124}
1125
1126static const char MnemonicTable[] =
1127 "\003adc\003add\004adiw\003and\004andi\003asr\004bclr\003bld\004brbc\004"
1128 "brbs\004brcc\004brcs\005break\004breq\004brge\004brhc\004brhs\004brid\004"
1129 "brie\004brlo\004brlt\004brmi\004brne\004brpl\004brsh\004brtc\004brts\004"
1130 "brvc\004brvs\004bset\003bst\004call\003cbi\003cbr\003clc\003clh\003cli\003"
1131 "cln\003clr\003cls\003clt\003clv\003clz\003com\002cp\003cpc\003cpi\004cp"
1132 "se\003dec\003des\006eicall\005eijmp\004elpm\003eor\004fmul\005fmuls\006"
1133 "fmulsu\005icall\004ijmp\002in\003inc\003jmp\003lac\003las\003lat\002ld\003"
1134 "ldd\003ldi\003lds\003lpm\003lsl\003lsr\003mov\004movw\003mul\004muls\005"
1135 "mulsu\003neg\003nop\002or\003ori\003out\003pop\004push\005rcall\003ret\004"
1136 "reti\004rjmp\003rol\003ror\003sbc\004sbci\003sbi\004sbic\004sbis\004sbi"
1137 "w\003sbr\004sbrc\004sbrs\003sec\003seh\003sei\003sen\003ser\003ses\003s"
1138 "et\003sev\003sez\005sleep\003spm\002st\003std\003sts\003sub\004subi\004"
1139 "swap\003tst\003wdr\003xch";
1140
1141// Feature bitsets.
1142enum : uint8_t {
1143 AMFBS_None,
1144 AMFBS_HasADDSUBIW,
1145 AMFBS_HasBREAK,
1146 AMFBS_HasDES,
1147 AMFBS_HasEIJMPCALL,
1148 AMFBS_HasELPM,
1149 AMFBS_HasELPMX,
1150 AMFBS_HasIJMPCALL,
1151 AMFBS_HasJMPCALL,
1152 AMFBS_HasLPM,
1153 AMFBS_HasLPMX,
1154 AMFBS_HasMOVW,
1155 AMFBS_HasSPM,
1156 AMFBS_HasSPMX,
1157 AMFBS_HasSRAM,
1158 AMFBS_SupportsMultiplication,
1159 AMFBS_SupportsRMW,
1160 AMFBS_HasSRAM_HasNonTinyEncoding,
1161 AMFBS_HasSRAM_HasTinyEncoding,
1162};
1163
1164static constexpr FeatureBitset FeatureBitsets[] = {
1165 {}, // AMFBS_None
1166 {Feature_HasADDSUBIWBit, },
1167 {Feature_HasBREAKBit, },
1168 {Feature_HasDESBit, },
1169 {Feature_HasEIJMPCALLBit, },
1170 {Feature_HasELPMBit, },
1171 {Feature_HasELPMXBit, },
1172 {Feature_HasIJMPCALLBit, },
1173 {Feature_HasJMPCALLBit, },
1174 {Feature_HasLPMBit, },
1175 {Feature_HasLPMXBit, },
1176 {Feature_HasMOVWBit, },
1177 {Feature_HasSPMBit, },
1178 {Feature_HasSPMXBit, },
1179 {Feature_HasSRAMBit, },
1180 {Feature_SupportsMultiplicationBit, },
1181 {Feature_SupportsRMWBit, },
1182 {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, },
1183 {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, },
1184};
1185
1186namespace {
1187 struct MatchEntry {
1188 uint16_t Mnemonic;
1189 uint16_t Opcode;
1190 uint8_t ConvertFn;
1191 uint8_t RequiredFeaturesIdx;
1192 uint8_t Classes[3];
1193 StringRef getMnemonic() const {
1194 return StringRef(MnemonicTable + Mnemonic + 1,
1195 MnemonicTable[Mnemonic]);
1196 }
1197 };
1198
1199 // Predicate for searching for an opcode.
1200 struct LessOpcode {
1201 bool operator()(const MatchEntry &LHS, StringRef RHS) {
1202 return LHS.getMnemonic() < RHS;
1203 }
1204 bool operator()(StringRef LHS, const MatchEntry &RHS) {
1205 return LHS < RHS.getMnemonic();
1206 }
1207 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
1208 return LHS.getMnemonic() < RHS.getMnemonic();
1209 }
1210 };
1211} // end anonymous namespace
1212
1213static const MatchEntry MatchTable0[] = {
1214 { 0 /* adc */, AVR::ADCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1215 { 4 /* add */, AVR::ADDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1216 { 8 /* adiw */, AVR::ADIWRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_HasADDSUBIW, { MCK_IWREGS, MCK_Imm }, },
1217 { 13 /* and */, AVR::ANDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1218 { 17 /* andi */, AVR::ANDIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1219 { 22 /* asr */, AVR::ASRRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1220 { 26 /* bclr */, AVR::BCLRs, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1221 { 31 /* bld */, AVR::BLD, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1222 { 35 /* brbc */, AVR::BRBCsk, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1223 { 40 /* brbs */, AVR::BRBSsk, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1224 { 45 /* brcc */, AVR::BRBCsk, Convert__imm_95_0__Imm1_0, AMFBS_None, { MCK_Imm }, },
1225 { 50 /* brcs */, AVR::BRBSsk, Convert__imm_95_0__Imm1_0, AMFBS_None, { MCK_Imm }, },
1226 { 55 /* break */, AVR::BREAK, Convert_NoOperands, AMFBS_HasBREAK, { }, },
1227 { 61 /* breq */, AVR::BREQk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1228 { 66 /* brge */, AVR::BRGEk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1229 { 71 /* brhc */, AVR::BRBCsk, Convert__imm_95_5__Imm1_0, AMFBS_None, { MCK_Imm }, },
1230 { 76 /* brhs */, AVR::BRBSsk, Convert__imm_95_5__Imm1_0, AMFBS_None, { MCK_Imm }, },
1231 { 81 /* brid */, AVR::BRBCsk, Convert__imm_95_7__Imm1_0, AMFBS_None, { MCK_Imm }, },
1232 { 86 /* brie */, AVR::BRBSsk, Convert__imm_95_7__Imm1_0, AMFBS_None, { MCK_Imm }, },
1233 { 91 /* brlo */, AVR::BRLOk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1234 { 96 /* brlt */, AVR::BRLTk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1235 { 101 /* brmi */, AVR::BRMIk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1236 { 106 /* brne */, AVR::BRNEk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1237 { 111 /* brpl */, AVR::BRPLk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1238 { 116 /* brsh */, AVR::BRSHk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1239 { 121 /* brtc */, AVR::BRBCsk, Convert__imm_95_6__Imm1_0, AMFBS_None, { MCK_Imm }, },
1240 { 126 /* brts */, AVR::BRBSsk, Convert__imm_95_6__Imm1_0, AMFBS_None, { MCK_Imm }, },
1241 { 131 /* brvc */, AVR::BRBCsk, Convert__imm_95_3__Imm1_0, AMFBS_None, { MCK_Imm }, },
1242 { 136 /* brvs */, AVR::BRBSsk, Convert__imm_95_3__Imm1_0, AMFBS_None, { MCK_Imm }, },
1243 { 141 /* bset */, AVR::BSETs, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1244 { 146 /* bst */, AVR::BST, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1245 { 150 /* call */, AVR::CALLk, Convert__Imm1_0, AMFBS_HasJMPCALL, { MCK_Imm }, },
1246 { 155 /* cbi */, AVR::CBIAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1247 { 159 /* cbr */, AVR::ANDIRdK, Convert__Reg1_0__Tie0_1_1__ImmCom81_1, AMFBS_None, { MCK_LD8, MCK_ImmCom8 }, },
1248 { 163 /* clc */, AVR::BCLRs, Convert__imm_95_0, AMFBS_None, { }, },
1249 { 167 /* clh */, AVR::BCLRs, Convert__imm_95_5, AMFBS_None, { }, },
1250 { 171 /* cli */, AVR::BCLRs, Convert__imm_95_7, AMFBS_None, { }, },
1251 { 175 /* cln */, AVR::BCLRs, Convert__imm_95_2, AMFBS_None, { }, },
1252 { 179 /* clr */, AVR::EORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1253 { 183 /* cls */, AVR::BCLRs, Convert__imm_95_4, AMFBS_None, { }, },
1254 { 187 /* clt */, AVR::BCLRs, Convert__imm_95_6, AMFBS_None, { }, },
1255 { 191 /* clv */, AVR::BCLRs, Convert__imm_95_3, AMFBS_None, { }, },
1256 { 195 /* clz */, AVR::BCLRs, Convert__imm_95_1, AMFBS_None, { }, },
1257 { 199 /* com */, AVR::COMRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1258 { 203 /* cp */, AVR::CPRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1259 { 206 /* cpc */, AVR::CPCRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1260 { 210 /* cpi */, AVR::CPIRdK, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1261 { 214 /* cpse */, AVR::CPSE, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1262 { 219 /* dec */, AVR::DECRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1263 { 223 /* des */, AVR::DESK, Convert__Imm1_0, AMFBS_HasDES, { MCK_Imm }, },
1264 { 227 /* eicall */, AVR::EICALL, Convert_NoOperands, AMFBS_HasEIJMPCALL, { }, },
1265 { 234 /* eijmp */, AVR::EIJMP, Convert_NoOperands, AMFBS_HasEIJMPCALL, { }, },
1266 { 240 /* elpm */, AVR::ELPM, Convert_NoOperands, AMFBS_HasELPM, { }, },
1267 { 240 /* elpm */, AVR::ELPMRdZ, Convert__Reg1_0__Reg1_1, AMFBS_HasELPMX, { MCK_GPR8, MCK_ZREG }, },
1268 { 240 /* elpm */, AVR::ELPMRdZPi, Convert__Reg1_0__Reg1_1, AMFBS_HasELPMX, { MCK_GPR8, MCK_ZREG, MCK__43_ }, },
1269 { 245 /* eor */, AVR::EORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1270 { 249 /* fmul */, AVR::FMUL, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1271 { 254 /* fmuls */, AVR::FMULS, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1272 { 260 /* fmulsu */, AVR::FMULSU, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1273 { 267 /* icall */, AVR::ICALL, Convert_NoOperands, AMFBS_HasIJMPCALL, { }, },
1274 { 273 /* ijmp */, AVR::IJMP, Convert_NoOperands, AMFBS_HasIJMPCALL, { }, },
1275 { 278 /* in */, AVR::INRdA, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1276 { 281 /* inc */, AVR::INCRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1277 { 285 /* jmp */, AVR::JMPk, Convert__Imm1_0, AMFBS_HasJMPCALL, { MCK_Imm }, },
1278 { 289 /* lac */, AVR::LACZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1279 { 293 /* las */, AVR::LASZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1280 { 297 /* lat */, AVR::LATZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1281 { 301 /* ld */, AVR::LDRdPtr, Convert__Reg1_0__Reg1_1, AMFBS_HasSRAM, { MCK_GPR8, MCK_PTRREGS }, },
1282 { 301 /* ld */, AVR::LDRdPtrPd, Convert__Reg1_0__Reg1_2__Tie1_3_3, AMFBS_HasSRAM, { MCK_GPR8, MCK__MINUS_, MCK_PTRREGS }, },
1283 { 301 /* ld */, AVR::LDRdPtrPi, Convert__Reg1_0__Reg1_1__Tie1_2_2, AMFBS_HasSRAM, { MCK_GPR8, MCK_PTRREGS, MCK__43_ }, },
1284 { 304 /* ldd */, AVR::LDDRdPtrQ, Convert__Reg1_0__Memri2_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_GPR8, MCK_Memri }, },
1285 { 308 /* ldi */, AVR::LDIRdK, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1286 { 312 /* lds */, AVR::LDSRdKTiny, Convert__Reg1_0__Imm1_1, AMFBS_HasSRAM_HasTinyEncoding, { MCK_LD8, MCK_Imm }, },
1287 { 312 /* lds */, AVR::LDSRdK, Convert__Reg1_0__Imm1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_GPR8, MCK_Imm }, },
1288 { 316 /* lpm */, AVR::LPM, Convert_NoOperands, AMFBS_HasLPM, { }, },
1289 { 316 /* lpm */, AVR::LPMRdZ, Convert__Reg1_0__Reg1_1, AMFBS_HasLPMX, { MCK_GPR8, MCK_ZREG }, },
1290 { 316 /* lpm */, AVR::LPMRdZPi, Convert__Reg1_0__Reg1_1, AMFBS_HasLPMX, { MCK_GPR8, MCK_ZREG, MCK__43_ }, },
1291 { 320 /* lsl */, AVR::ADDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1292 { 324 /* lsr */, AVR::LSRRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1293 { 328 /* mov */, AVR::MOVRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1294 { 332 /* movw */, AVR::MOVWRdRr, Convert__Reg1_0__Reg1_1, AMFBS_HasMOVW, { MCK_DREGS, MCK_DREGS }, },
1295 { 337 /* mul */, AVR::MULRdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_GPR8, MCK_GPR8 }, },
1296 { 341 /* muls */, AVR::MULSRdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8, MCK_LD8 }, },
1297 { 346 /* mulsu */, AVR::MULSURdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1298 { 352 /* neg */, AVR::NEGRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1299 { 356 /* nop */, AVR::NOP, Convert_NoOperands, AMFBS_None, { }, },
1300 { 360 /* or */, AVR::ORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1301 { 363 /* ori */, AVR::ORIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1302 { 367 /* out */, AVR::OUTARr, Convert__Imm1_0__Reg1_1, AMFBS_None, { MCK_Imm, MCK_GPR8 }, },
1303 { 371 /* pop */, AVR::POPRd, Convert__Reg1_0, AMFBS_HasSRAM, { MCK_GPR8 }, },
1304 { 375 /* push */, AVR::PUSHRr, Convert__Reg1_0, AMFBS_HasSRAM, { MCK_GPR8 }, },
1305 { 380 /* rcall */, AVR::RCALLk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1306 { 386 /* ret */, AVR::RET, Convert_NoOperands, AMFBS_None, { }, },
1307 { 390 /* reti */, AVR::RETI, Convert_NoOperands, AMFBS_None, { }, },
1308 { 395 /* rjmp */, AVR::RJMPk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1309 { 400 /* rol */, AVR::ADCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1310 { 404 /* ror */, AVR::RORRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1311 { 408 /* sbc */, AVR::SBCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1312 { 412 /* sbci */, AVR::SBCIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1313 { 417 /* sbi */, AVR::SBIAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1314 { 421 /* sbic */, AVR::SBICAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1315 { 426 /* sbis */, AVR::SBISAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1316 { 431 /* sbiw */, AVR::SBIWRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_HasADDSUBIW, { MCK_IWREGS, MCK_Imm }, },
1317 { 436 /* sbr */, AVR::ORIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1318 { 440 /* sbrc */, AVR::SBRCRrB, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1319 { 445 /* sbrs */, AVR::SBRSRrB, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1320 { 450 /* sec */, AVR::BSETs, Convert__imm_95_0, AMFBS_None, { }, },
1321 { 454 /* seh */, AVR::BSETs, Convert__imm_95_5, AMFBS_None, { }, },
1322 { 458 /* sei */, AVR::BSETs, Convert__imm_95_7, AMFBS_None, { }, },
1323 { 462 /* sen */, AVR::BSETs, Convert__imm_95_2, AMFBS_None, { }, },
1324 { 466 /* ser */, AVR::LDIRdK, Convert__Reg1_0__imm_95_255, AMFBS_None, { MCK_LD8 }, },
1325 { 470 /* ses */, AVR::BSETs, Convert__imm_95_4, AMFBS_None, { }, },
1326 { 474 /* set */, AVR::BSETs, Convert__imm_95_6, AMFBS_None, { }, },
1327 { 478 /* sev */, AVR::BSETs, Convert__imm_95_3, AMFBS_None, { }, },
1328 { 482 /* sez */, AVR::BSETs, Convert__imm_95_1, AMFBS_None, { }, },
1329 { 486 /* sleep */, AVR::SLEEP, Convert_NoOperands, AMFBS_None, { }, },
1330 { 492 /* spm */, AVR::SPM, Convert_NoOperands, AMFBS_HasSPM, { }, },
1331 { 492 /* spm */, AVR::SPMZPi, Convert__Reg1_0, AMFBS_HasSPMX, { MCK_ZREG, MCK__43_ }, },
1332 { 496 /* st */, AVR::STPtrRr, Convert__Reg1_0__Reg1_1, AMFBS_HasSRAM, { MCK_PTRREGS, MCK_GPR8 }, },
1333 { 496 /* st */, AVR::STPtrPdRr, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0, AMFBS_HasSRAM, { MCK__MINUS_, MCK_PTRREGS, MCK_GPR8 }, },
1334 { 496 /* st */, AVR::STPtrPiRr, Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0, AMFBS_HasSRAM, { MCK_PTRREGS, MCK__43_, MCK_GPR8 }, },
1335 { 499 /* std */, AVR::STDPtrQRr, Convert__Memri2_0__Reg1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_Memri, MCK_GPR8 }, },
1336 { 503 /* sts */, AVR::STSKRrTiny, Convert__Imm1_0__Reg1_1, AMFBS_HasSRAM_HasTinyEncoding, { MCK_Imm, MCK_LD8 }, },
1337 { 503 /* sts */, AVR::STSKRr, Convert__Imm1_0__Reg1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_Imm, MCK_GPR8 }, },
1338 { 507 /* sub */, AVR::SUBRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1339 { 511 /* subi */, AVR::SUBIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1340 { 516 /* swap */, AVR::SWAPRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1341 { 521 /* tst */, AVR::ANDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1342 { 525 /* wdr */, AVR::WDR, Convert_NoOperands, AMFBS_None, { }, },
1343 { 529 /* xch */, AVR::XCHZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1344};
1345
1346#include "llvm/Support/Debug.h"
1347#include "llvm/Support/Format.h"
1348
1349unsigned AVRAsmParser::
1350MatchInstructionImpl(const OperandVector &Operands,
1351 MCInst &Inst,
1352 uint64_t &ErrorInfo,
1353 FeatureBitset &MissingFeatures,
1354 bool matchingInlineAsm, unsigned VariantID) {
1355 // Eliminate obvious mismatches.
1356 if (Operands.size() > 4) {
1357 ErrorInfo = 4;
1358 return Match_InvalidOperand;
1359 }
1360
1361 // Get the current feature set.
1362 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1363
1364 // Get the instruction mnemonic, which is the first token.
1365 StringRef Mnemonic = ((AVROperand &)*Operands[0]).getToken();
1366
1367 // Some state to try to produce better error messages.
1368 bool HadMatchOtherThanFeatures = false;
1369 bool HadMatchOtherThanPredicate = false;
1370 unsigned RetCode = Match_InvalidOperand;
1371 MissingFeatures.set();
1372 // Set ErrorInfo to the operand that mismatches if it is
1373 // wrong for all instances of the instruction.
1374 ErrorInfo = ~0ULL;
1375 // Find the appropriate table for this asm variant.
1376 const MatchEntry *Start, *End;
1377 switch (VariantID) {
1378 default: llvm_unreachable("invalid variant!");
1379 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1380 }
1381 // Search the table.
1382 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1383
1384 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
1385 std::distance(MnemonicRange.first, MnemonicRange.second) <<
1386 " encodings with mnemonic '" << Mnemonic << "'\n");
1387
1388 // Return a more specific error code if no mnemonics match.
1389 if (MnemonicRange.first == MnemonicRange.second)
1390 return Match_MnemonicFail;
1391
1392 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1393 it != ie; ++it) {
1394 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1395 bool HasRequiredFeatures =
1396 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
1397 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
1398 << MII.getName(it->Opcode) << "\n");
1399 // equal_range guarantees that instruction mnemonic matches.
1400 assert(Mnemonic == it->getMnemonic());
1401 bool OperandsValid = true;
1402 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 3; ++FormalIdx) {
1403 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
1404 DEBUG_WITH_TYPE("asm-matcher",
1405 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
1406 << " against actual operand at index " << ActualIdx);
1407 if (ActualIdx < Operands.size())
1408 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
1409 Operands[ActualIdx]->print(dbgs(), *getContext().getAsmInfo()); dbgs() << "): ");
1410 else
1411 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
1412 if (ActualIdx >= Operands.size()) {
1413 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
1414 if (Formal == InvalidMatchClass) {
1415 break;
1416 }
1417 if (isSubclass(Formal, OptionalMatchClass)) {
1418 continue;
1419 }
1420 OperandsValid = false;
1421 ErrorInfo = ActualIdx;
1422 break;
1423 }
1424 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
1425 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
1426 if (Diag == Match_Success) {
1427 DEBUG_WITH_TYPE("asm-matcher",
1428 dbgs() << "match success using generic matcher\n");
1429 ++ActualIdx;
1430 continue;
1431 }
1432 // If the generic handler indicates an invalid operand
1433 // failure, check for a special case.
1434 if (Diag != Match_Success) {
1435 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
1436 if (TargetDiag == Match_Success) {
1437 DEBUG_WITH_TYPE("asm-matcher",
1438 dbgs() << "match success using target matcher\n");
1439 ++ActualIdx;
1440 continue;
1441 }
1442 // If the target matcher returned a specific error code use
1443 // that, else use the one from the generic matcher.
1444 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
1445 Diag = TargetDiag;
1446 }
1447 // If current formal operand wasn't matched and it is optional
1448 // then try to match next formal operand
1449 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
1450 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
1451 continue;
1452 }
1453 // If this operand is broken for all of the instances of this
1454 // mnemonic, keep track of it so we can report loc info.
1455 // If we already had a match that only failed due to a
1456 // target predicate, that diagnostic is preferred.
1457 if (!HadMatchOtherThanPredicate &&
1458 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
1459 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
1460 RetCode = Diag;
1461 ErrorInfo = ActualIdx;
1462 }
1463 // Otherwise, just reject this instance of the mnemonic.
1464 OperandsValid = false;
1465 break;
1466 }
1467
1468 if (!OperandsValid) {
1469 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
1470 "operand mismatches, ignoring "
1471 "this opcode\n");
1472 continue;
1473 }
1474 if (!HasRequiredFeatures) {
1475 HadMatchOtherThanFeatures = true;
1476 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
1477 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
1478 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
1479 if (NewMissingFeatures[I])
1480 dbgs() << ' ' << I;
1481 dbgs() << "\n");
1482 if (NewMissingFeatures.count() <=
1483 MissingFeatures.count())
1484 MissingFeatures = NewMissingFeatures;
1485 continue;
1486 }
1487
1488 Inst.clear();
1489
1490 Inst.setOpcode(it->Opcode);
1491 // We have a potential match but have not rendered the operands.
1492 // Check the target predicate to handle any context sensitive
1493 // constraints.
1494 // For example, Ties that are referenced multiple times must be
1495 // checked here to ensure the input is the same for each match
1496 // constraints. If we leave it any later the ties will have been
1497 // canonicalized
1498 unsigned MatchResult;
1499 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
1500 Inst.clear();
1501 DEBUG_WITH_TYPE(
1502 "asm-matcher",
1503 dbgs() << "Early target match predicate failed with diag code "
1504 << MatchResult << "\n");
1505 RetCode = MatchResult;
1506 HadMatchOtherThanPredicate = true;
1507 continue;
1508 }
1509
1510 if (matchingInlineAsm) {
1511 convertToMapAndConstraints(it->ConvertFn, Operands);
1512 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1513 ErrorInfo))
1514 return Match_InvalidTiedOperand;
1515
1516 return Match_Success;
1517 }
1518
1519 // We have selected a definite instruction, convert the parsed
1520 // operands into the appropriate MCInst.
1521 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
1522
1523 // We have a potential match. Check the target predicate to
1524 // handle any context sensitive constraints.
1525 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
1526 DEBUG_WITH_TYPE("asm-matcher",
1527 dbgs() << "Target match predicate failed with diag code "
1528 << MatchResult << "\n");
1529 Inst.clear();
1530 RetCode = MatchResult;
1531 HadMatchOtherThanPredicate = true;
1532 continue;
1533 }
1534
1535 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1536 ErrorInfo))
1537 return Match_InvalidTiedOperand;
1538
1539 DEBUG_WITH_TYPE(
1540 "asm-matcher",
1541 dbgs() << "Opcode result: complete match, selecting this opcode\n");
1542 return Match_Success;
1543 }
1544
1545 // Okay, we had no match. Try to return a useful error code.
1546 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
1547 return RetCode;
1548
1549 ErrorInfo = 0;
1550 return Match_MissingFeature;
1551}
1552
1553namespace {
1554 struct OperandMatchEntry {
1555 uint16_t Mnemonic;
1556 uint8_t OperandMask;
1557 uint8_t Class;
1558 uint8_t RequiredFeaturesIdx;
1559
1560 StringRef getMnemonic() const {
1561 return StringRef(MnemonicTable + Mnemonic + 1,
1562 MnemonicTable[Mnemonic]);
1563 }
1564 };
1565
1566 // Predicate for searching for an opcode.
1567 struct LessOpcodeOperand {
1568 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
1569 return LHS.getMnemonic() < RHS;
1570 }
1571 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
1572 return LHS < RHS.getMnemonic();
1573 }
1574 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
1575 return LHS.getMnemonic() < RHS.getMnemonic();
1576 }
1577 };
1578} // end anonymous namespace
1579
1580static const OperandMatchEntry OperandMatchTable[2] = {
1581 /* Operand List Mnemonic, Mask, Operand Class, Features */
1582 { 304 /* ldd */, 2 /* 1 */, MCK_Memri, AMFBS_HasSRAM_HasNonTinyEncoding },
1583 { 499 /* std */, 1 /* 0 */, MCK_Memri, AMFBS_HasSRAM_HasNonTinyEncoding },
1584};
1585
1586ParseStatus AVRAsmParser::
1587tryCustomParseOperand(OperandVector &Operands,
1588 unsigned MCK) {
1589
1590 switch(MCK) {
1591 case MCK_Memri:
1592 return parseMemriOperand(Operands);
1593 default:
1594 return ParseStatus::NoMatch;
1595 }
1596 return ParseStatus::NoMatch;
1597}
1598
1599ParseStatus AVRAsmParser::
1600MatchOperandParserImpl(OperandVector &Operands,
1601 StringRef Mnemonic,
1602 bool ParseForAllFeatures) {
1603 // Get the current feature set.
1604 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1605
1606 // Get the next operand index.
1607 unsigned NextOpNum = Operands.size() - 1;
1608 // Search the table.
1609 auto MnemonicRange =
1610 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
1611 Mnemonic, LessOpcodeOperand());
1612
1613 if (MnemonicRange.first == MnemonicRange.second)
1614 return ParseStatus::NoMatch;
1615
1616 for (const OperandMatchEntry *it = MnemonicRange.first,
1617 *ie = MnemonicRange.second; it != ie; ++it) {
1618 // equal_range guarantees that instruction mnemonic matches.
1619 assert(Mnemonic == it->getMnemonic());
1620
1621 // check if the available features match
1622 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1623 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
1624 continue;
1625
1626 // check if the operand in question has a custom parser.
1627 if (!(it->OperandMask & (1 << NextOpNum)))
1628 continue;
1629
1630 // call custom parse method to handle the operand
1631 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
1632 if (!Result.isNoMatch())
1633 return Result;
1634 }
1635
1636 // Okay, we had no match.
1637 return ParseStatus::NoMatch;
1638}
1639
1640#endif // GET_MATCHER_IMPLEMENTATION
1641
1642
1643#ifdef GET_MNEMONIC_SPELL_CHECKER
1644#undef GET_MNEMONIC_SPELL_CHECKER
1645
1646static std::string AVRMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
1647 const unsigned MaxEditDist = 2;
1648 std::vector<StringRef> Candidates;
1649 StringRef Prev = "";
1650
1651 // Find the appropriate table for this asm variant.
1652 const MatchEntry *Start, *End;
1653 switch (VariantID) {
1654 default: llvm_unreachable("invalid variant!");
1655 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1656 }
1657
1658 for (auto I = Start; I < End; I++) {
1659 // Ignore unsupported instructions.
1660 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
1661 if ((FBS & RequiredFeatures) != RequiredFeatures)
1662 continue;
1663
1664 StringRef T = I->getMnemonic();
1665 // Avoid recomputing the edit distance for the same string.
1666 if (T == Prev)
1667 continue;
1668
1669 Prev = T;
1670 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
1671 if (Dist <= MaxEditDist)
1672 Candidates.push_back(T);
1673 }
1674
1675 if (Candidates.empty())
1676 return "";
1677
1678 std::string Res = ", did you mean: ";
1679 unsigned i = 0;
1680 for (; i < Candidates.size() - 1; i++)
1681 Res += Candidates[i].str() + ", ";
1682 return Res + Candidates[i].str() + "?";
1683}
1684
1685#endif // GET_MNEMONIC_SPELL_CHECKER
1686
1687
1688#ifdef GET_MNEMONIC_CHECKER
1689#undef GET_MNEMONIC_CHECKER
1690
1691static bool AVRCheckMnemonic(StringRef Mnemonic,
1692 const FeatureBitset &AvailableFeatures,
1693 unsigned VariantID) {
1694 // Find the appropriate table for this asm variant.
1695 const MatchEntry *Start, *End;
1696 switch (VariantID) {
1697 default: llvm_unreachable("invalid variant!");
1698 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1699 }
1700
1701 // Search the table.
1702 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1703
1704 if (MnemonicRange.first == MnemonicRange.second)
1705 return false;
1706
1707 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1708 it != ie; ++it) {
1709 const FeatureBitset &RequiredFeatures =
1710 FeatureBitsets[it->RequiredFeaturesIdx];
1711 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
1712 return true;
1713 }
1714 return false;
1715}
1716
1717#endif // GET_MNEMONIC_CHECKER
1718
1719