1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AVR.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10
11#ifdef GET_ASSEMBLER_HEADER
12#undef GET_ASSEMBLER_HEADER
13 // This should be included into the middle of the declaration of
14 // your subclasses implementation of MCTargetAsmParser.
15 FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17 const OperandVector &Operands);
18 void convertToMapAndConstraints(unsigned Kind,
19 const OperandVector &Operands) override;
20 unsigned MatchInstructionImpl(const OperandVector &Operands,
21 MCInst &Inst,
22 uint64_t &ErrorInfo,
23 FeatureBitset &MissingFeatures,
24 bool matchingInlineAsm,
25 unsigned VariantID = 0);
26 unsigned MatchInstructionImpl(const OperandVector &Operands,
27 MCInst &Inst,
28 uint64_t &ErrorInfo,
29 bool matchingInlineAsm,
30 unsigned VariantID = 0) {
31 FeatureBitset MissingFeatures;
32 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33 matchingInlineAsm, VariantID);
34 }
35
36 ParseStatus MatchOperandParserImpl(
37 OperandVector &Operands,
38 StringRef Mnemonic,
39 bool ParseForAllFeatures = false);
40 ParseStatus tryCustomParseOperand(
41 OperandVector &Operands,
42 unsigned MCK);
43
44#endif // GET_ASSEMBLER_HEADER
45
46
47#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
48#undef GET_OPERAND_DIAGNOSTIC_TYPES
49
50#endif // GET_OPERAND_DIAGNOSTIC_TYPES
51
52
53#ifdef GET_REGISTER_MATCHER
54#undef GET_REGISTER_MATCHER
55
56// Bits for subtarget features that participate in instruction matching.
57enum SubtargetFeatureBits : uint8_t {
58 Feature_HasSRAMBit = 14,
59 Feature_HasJMPCALLBit = 7,
60 Feature_HasIJMPCALLBit = 6,
61 Feature_HasEIJMPCALLBit = 3,
62 Feature_HasADDSUBIWBit = 0,
63 Feature_HasSmallStackBit = 15,
64 Feature_HasMOVWBit = 10,
65 Feature_HasLPMBit = 8,
66 Feature_HasLPMXBit = 9,
67 Feature_HasELPMBit = 4,
68 Feature_HasELPMXBit = 5,
69 Feature_HasSPMBit = 12,
70 Feature_HasSPMXBit = 13,
71 Feature_HasDESBit = 2,
72 Feature_SupportsRMWBit = 18,
73 Feature_SupportsMultiplicationBit = 17,
74 Feature_HasBREAKBit = 1,
75 Feature_HasTinyEncodingBit = 16,
76 Feature_HasNonTinyEncodingBit = 11,
77};
78
79static MCRegister MatchRegisterName(StringRef Name) {
80 switch (Name.size()) {
81 default: break;
82 case 2: // 11 strings to match.
83 switch (Name[0]) {
84 default: break;
85 case 'S': // 1 string to match.
86 if (Name[1] != 'P')
87 break;
88 return AVR::SP; // "SP"
89 case 'r': // 10 strings to match.
90 switch (Name[1]) {
91 default: break;
92 case '0': // 1 string to match.
93 return AVR::R0; // "r0"
94 case '1': // 1 string to match.
95 return AVR::R1; // "r1"
96 case '2': // 1 string to match.
97 return AVR::R2; // "r2"
98 case '3': // 1 string to match.
99 return AVR::R3; // "r3"
100 case '4': // 1 string to match.
101 return AVR::R4; // "r4"
102 case '5': // 1 string to match.
103 return AVR::R5; // "r5"
104 case '6': // 1 string to match.
105 return AVR::R6; // "r6"
106 case '7': // 1 string to match.
107 return AVR::R7; // "r7"
108 case '8': // 1 string to match.
109 return AVR::R8; // "r8"
110 case '9': // 1 string to match.
111 return AVR::R9; // "r9"
112 }
113 break;
114 }
115 break;
116 case 3: // 24 strings to match.
117 switch (Name[0]) {
118 default: break;
119 case 'S': // 2 strings to match.
120 if (Name[1] != 'P')
121 break;
122 switch (Name[2]) {
123 default: break;
124 case 'H': // 1 string to match.
125 return AVR::SPH; // "SPH"
126 case 'L': // 1 string to match.
127 return AVR::SPL; // "SPL"
128 }
129 break;
130 case 'r': // 22 strings to match.
131 switch (Name[1]) {
132 default: break;
133 case '1': // 10 strings to match.
134 switch (Name[2]) {
135 default: break;
136 case '0': // 1 string to match.
137 return AVR::R10; // "r10"
138 case '1': // 1 string to match.
139 return AVR::R11; // "r11"
140 case '2': // 1 string to match.
141 return AVR::R12; // "r12"
142 case '3': // 1 string to match.
143 return AVR::R13; // "r13"
144 case '4': // 1 string to match.
145 return AVR::R14; // "r14"
146 case '5': // 1 string to match.
147 return AVR::R15; // "r15"
148 case '6': // 1 string to match.
149 return AVR::R16; // "r16"
150 case '7': // 1 string to match.
151 return AVR::R17; // "r17"
152 case '8': // 1 string to match.
153 return AVR::R18; // "r18"
154 case '9': // 1 string to match.
155 return AVR::R19; // "r19"
156 }
157 break;
158 case '2': // 10 strings to match.
159 switch (Name[2]) {
160 default: break;
161 case '0': // 1 string to match.
162 return AVR::R20; // "r20"
163 case '1': // 1 string to match.
164 return AVR::R21; // "r21"
165 case '2': // 1 string to match.
166 return AVR::R22; // "r22"
167 case '3': // 1 string to match.
168 return AVR::R23; // "r23"
169 case '4': // 1 string to match.
170 return AVR::R24; // "r24"
171 case '5': // 1 string to match.
172 return AVR::R25; // "r25"
173 case '6': // 1 string to match.
174 return AVR::R26; // "r26"
175 case '7': // 1 string to match.
176 return AVR::R27; // "r27"
177 case '8': // 1 string to match.
178 return AVR::R28; // "r28"
179 case '9': // 1 string to match.
180 return AVR::R29; // "r29"
181 }
182 break;
183 case '3': // 2 strings to match.
184 switch (Name[2]) {
185 default: break;
186 case '0': // 1 string to match.
187 return AVR::R30; // "r30"
188 case '1': // 1 string to match.
189 return AVR::R31; // "r31"
190 }
191 break;
192 }
193 break;
194 }
195 break;
196 case 5: // 6 strings to match.
197 switch (Name[0]) {
198 default: break;
199 case 'F': // 1 string to match.
200 if (memcmp(Name.data()+1, "LAGS", 4) != 0)
201 break;
202 return AVR::SREG; // "FLAGS"
203 case 'r': // 5 strings to match.
204 switch (Name[1]) {
205 default: break;
206 case '1': // 1 string to match.
207 if (memcmp(Name.data()+2, ":r0", 3) != 0)
208 break;
209 return AVR::R1R0; // "r1:r0"
210 case '3': // 1 string to match.
211 if (memcmp(Name.data()+2, ":r2", 3) != 0)
212 break;
213 return AVR::R3R2; // "r3:r2"
214 case '5': // 1 string to match.
215 if (memcmp(Name.data()+2, ":r4", 3) != 0)
216 break;
217 return AVR::R5R4; // "r5:r4"
218 case '7': // 1 string to match.
219 if (memcmp(Name.data()+2, ":r6", 3) != 0)
220 break;
221 return AVR::R7R6; // "r7:r6"
222 case '9': // 1 string to match.
223 if (memcmp(Name.data()+2, ":r8", 3) != 0)
224 break;
225 return AVR::R9R8; // "r9:r8"
226 }
227 break;
228 }
229 break;
230 case 6: // 1 string to match.
231 if (memcmp(Name.data()+0, "r10:r9", 6) != 0)
232 break;
233 return AVR::R10R9; // "r10:r9"
234 case 7: // 19 strings to match.
235 if (Name[0] != 'r')
236 break;
237 switch (Name[1]) {
238 default: break;
239 case '1': // 9 strings to match.
240 switch (Name[2]) {
241 default: break;
242 case '1': // 1 string to match.
243 if (memcmp(Name.data()+3, ":r10", 4) != 0)
244 break;
245 return AVR::R11R10; // "r11:r10"
246 case '2': // 1 string to match.
247 if (memcmp(Name.data()+3, ":r11", 4) != 0)
248 break;
249 return AVR::R12R11; // "r12:r11"
250 case '3': // 1 string to match.
251 if (memcmp(Name.data()+3, ":r12", 4) != 0)
252 break;
253 return AVR::R13R12; // "r13:r12"
254 case '4': // 1 string to match.
255 if (memcmp(Name.data()+3, ":r13", 4) != 0)
256 break;
257 return AVR::R14R13; // "r14:r13"
258 case '5': // 1 string to match.
259 if (memcmp(Name.data()+3, ":r14", 4) != 0)
260 break;
261 return AVR::R15R14; // "r15:r14"
262 case '6': // 1 string to match.
263 if (memcmp(Name.data()+3, ":r15", 4) != 0)
264 break;
265 return AVR::R16R15; // "r16:r15"
266 case '7': // 1 string to match.
267 if (memcmp(Name.data()+3, ":r16", 4) != 0)
268 break;
269 return AVR::R17R16; // "r17:r16"
270 case '8': // 1 string to match.
271 if (memcmp(Name.data()+3, ":r17", 4) != 0)
272 break;
273 return AVR::R18R17; // "r18:r17"
274 case '9': // 1 string to match.
275 if (memcmp(Name.data()+3, ":r18", 4) != 0)
276 break;
277 return AVR::R19R18; // "r19:r18"
278 }
279 break;
280 case '2': // 9 strings to match.
281 switch (Name[2]) {
282 default: break;
283 case '0': // 1 string to match.
284 if (memcmp(Name.data()+3, ":r19", 4) != 0)
285 break;
286 return AVR::R20R19; // "r20:r19"
287 case '1': // 1 string to match.
288 if (memcmp(Name.data()+3, ":r20", 4) != 0)
289 break;
290 return AVR::R21R20; // "r21:r20"
291 case '2': // 1 string to match.
292 if (memcmp(Name.data()+3, ":r21", 4) != 0)
293 break;
294 return AVR::R22R21; // "r22:r21"
295 case '3': // 1 string to match.
296 if (memcmp(Name.data()+3, ":r22", 4) != 0)
297 break;
298 return AVR::R23R22; // "r23:r22"
299 case '4': // 1 string to match.
300 if (memcmp(Name.data()+3, ":r23", 4) != 0)
301 break;
302 return AVR::R24R23; // "r24:r23"
303 case '5': // 1 string to match.
304 if (memcmp(Name.data()+3, ":r24", 4) != 0)
305 break;
306 return AVR::R25R24; // "r25:r24"
307 case '6': // 1 string to match.
308 if (memcmp(Name.data()+3, ":r25", 4) != 0)
309 break;
310 return AVR::R26R25; // "r26:r25"
311 case '7': // 1 string to match.
312 if (memcmp(Name.data()+3, ":r26", 4) != 0)
313 break;
314 return AVR::R27R26; // "r27:r26"
315 case '9': // 1 string to match.
316 if (memcmp(Name.data()+3, ":r28", 4) != 0)
317 break;
318 return AVR::R29R28; // "r29:r28"
319 }
320 break;
321 case '3': // 1 string to match.
322 if (memcmp(Name.data()+2, "1:r30", 5) != 0)
323 break;
324 return AVR::R31R30; // "r31:r30"
325 }
326 break;
327 }
328 return AVR::NoRegister;
329}
330
331static MCRegister MatchRegisterAltName(StringRef Name) {
332 switch (Name.size()) {
333 default: break;
334 case 1: // 3 strings to match.
335 switch (Name[0]) {
336 default: break;
337 case 'X': // 1 string to match.
338 return AVR::R27R26; // "X"
339 case 'Y': // 1 string to match.
340 return AVR::R29R28; // "Y"
341 case 'Z': // 1 string to match.
342 return AVR::R31R30; // "Z"
343 }
344 break;
345 case 2: // 6 strings to match.
346 switch (Name[0]) {
347 default: break;
348 case 'x': // 2 strings to match.
349 switch (Name[1]) {
350 default: break;
351 case 'h': // 1 string to match.
352 return AVR::R27; // "xh"
353 case 'l': // 1 string to match.
354 return AVR::R26; // "xl"
355 }
356 break;
357 case 'y': // 2 strings to match.
358 switch (Name[1]) {
359 default: break;
360 case 'h': // 1 string to match.
361 return AVR::R29; // "yh"
362 case 'l': // 1 string to match.
363 return AVR::R28; // "yl"
364 }
365 break;
366 case 'z': // 2 strings to match.
367 switch (Name[1]) {
368 default: break;
369 case 'h': // 1 string to match.
370 return AVR::R31; // "zh"
371 case 'l': // 1 string to match.
372 return AVR::R30; // "zl"
373 }
374 break;
375 }
376 break;
377 }
378 return AVR::NoRegister;
379}
380
381#endif // GET_REGISTER_MATCHER
382
383
384#ifdef GET_SUBTARGET_FEATURE_NAME
385#undef GET_SUBTARGET_FEATURE_NAME
386
387// User-level names for subtarget features that participate in
388// instruction matching.
389static const char *getSubtargetFeatureName(uint64_t Val) {
390 switch(Val) {
391 case Feature_HasSRAMBit: return "";
392 case Feature_HasJMPCALLBit: return "";
393 case Feature_HasIJMPCALLBit: return "";
394 case Feature_HasEIJMPCALLBit: return "";
395 case Feature_HasADDSUBIWBit: return "";
396 case Feature_HasSmallStackBit: return "";
397 case Feature_HasMOVWBit: return "";
398 case Feature_HasLPMBit: return "";
399 case Feature_HasLPMXBit: return "";
400 case Feature_HasELPMBit: return "";
401 case Feature_HasELPMXBit: return "";
402 case Feature_HasSPMBit: return "";
403 case Feature_HasSPMXBit: return "";
404 case Feature_HasDESBit: return "";
405 case Feature_SupportsRMWBit: return "";
406 case Feature_SupportsMultiplicationBit: return "";
407 case Feature_HasBREAKBit: return "";
408 case Feature_HasTinyEncodingBit: return "";
409 case Feature_HasNonTinyEncodingBit: return "";
410 default: return "(unknown)";
411 }
412}
413
414#endif // GET_SUBTARGET_FEATURE_NAME
415
416
417#ifdef GET_MATCHER_IMPLEMENTATION
418#undef GET_MATCHER_IMPLEMENTATION
419
420enum {
421 Tie0_1_1,
422 Tie0_2_2,
423 Tie1_2_2,
424 Tie1_3_3,
425};
426
427static const uint8_t TiedAsmOperandTable[][3] = {
428 /* Tie0_1_1 */ { 0, 1, 1 },
429 /* Tie0_2_2 */ { 0, 2, 2 },
430 /* Tie1_2_2 */ { 1, 2, 2 },
431 /* Tie1_3_3 */ { 1, 3, 3 },
432};
433
434namespace {
435enum OperatorConversionKind {
436 CVT_Done,
437 CVT_Reg,
438 CVT_Tied,
439 CVT_95_Reg,
440 CVT_95_addImmOperands,
441 CVT_imm_95_0,
442 CVT_imm_95_5,
443 CVT_imm_95_7,
444 CVT_imm_95_6,
445 CVT_imm_95_3,
446 CVT_95_addImmCom8Operands,
447 CVT_imm_95_2,
448 CVT_imm_95_4,
449 CVT_imm_95_1,
450 CVT_95_addMemriOperands,
451 CVT_imm_95_255,
452 CVT_NUM_CONVERTERS
453};
454
455enum InstructionConversionKind {
456 Convert__Reg1_0__Tie0_1_1__Reg1_1,
457 Convert__Reg1_0__Tie0_1_1__Imm1_1,
458 Convert__Reg1_0__Tie0_1_1,
459 Convert__Imm1_0,
460 Convert__Imm1_0__Imm1_1,
461 Convert__imm_95_0__Imm1_0,
462 Convert_NoOperands,
463 Convert__imm_95_5__Imm1_0,
464 Convert__imm_95_7__Imm1_0,
465 Convert__imm_95_6__Imm1_0,
466 Convert__imm_95_3__Imm1_0,
467 Convert__Reg1_0__Imm1_1,
468 Convert__Reg1_0__Tie0_1_1__ImmCom81_1,
469 Convert__imm_95_0,
470 Convert__imm_95_5,
471 Convert__imm_95_7,
472 Convert__imm_95_2,
473 Convert__Reg1_0__Tie0_1_1__Reg1_0,
474 Convert__imm_95_4,
475 Convert__imm_95_6,
476 Convert__imm_95_3,
477 Convert__imm_95_1,
478 Convert__Reg1_0__Reg1_1,
479 Convert__Reg1_1__Reg1_0,
480 Convert__Reg1_0__Reg1_2__Tie1_3_3,
481 Convert__Reg1_0__Reg1_1__Tie1_2_2,
482 Convert__Reg1_0__Memri2_1,
483 Convert__Imm1_0__Reg1_1,
484 Convert__Reg1_0,
485 Convert__Reg1_0__imm_95_255,
486 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0,
487 Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0,
488 Convert__Memri2_0__Reg1_1,
489 CVT_NUM_SIGNATURES
490};
491
492} // end anonymous namespace
493
494static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
495 // Convert__Reg1_0__Tie0_1_1__Reg1_1
496 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
497 // Convert__Reg1_0__Tie0_1_1__Imm1_1
498 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
499 // Convert__Reg1_0__Tie0_1_1
500 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
501 // Convert__Imm1_0
502 { CVT_95_addImmOperands, 1, CVT_Done },
503 // Convert__Imm1_0__Imm1_1
504 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
505 // Convert__imm_95_0__Imm1_0
506 { CVT_imm_95_0, 0, CVT_95_addImmOperands, 1, CVT_Done },
507 // Convert_NoOperands
508 { CVT_Done },
509 // Convert__imm_95_5__Imm1_0
510 { CVT_imm_95_5, 0, CVT_95_addImmOperands, 1, CVT_Done },
511 // Convert__imm_95_7__Imm1_0
512 { CVT_imm_95_7, 0, CVT_95_addImmOperands, 1, CVT_Done },
513 // Convert__imm_95_6__Imm1_0
514 { CVT_imm_95_6, 0, CVT_95_addImmOperands, 1, CVT_Done },
515 // Convert__imm_95_3__Imm1_0
516 { CVT_imm_95_3, 0, CVT_95_addImmOperands, 1, CVT_Done },
517 // Convert__Reg1_0__Imm1_1
518 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
519 // Convert__Reg1_0__Tie0_1_1__ImmCom81_1
520 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmCom8Operands, 2, CVT_Done },
521 // Convert__imm_95_0
522 { CVT_imm_95_0, 0, CVT_Done },
523 // Convert__imm_95_5
524 { CVT_imm_95_5, 0, CVT_Done },
525 // Convert__imm_95_7
526 { CVT_imm_95_7, 0, CVT_Done },
527 // Convert__imm_95_2
528 { CVT_imm_95_2, 0, CVT_Done },
529 // Convert__Reg1_0__Tie0_1_1__Reg1_0
530 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
531 // Convert__imm_95_4
532 { CVT_imm_95_4, 0, CVT_Done },
533 // Convert__imm_95_6
534 { CVT_imm_95_6, 0, CVT_Done },
535 // Convert__imm_95_3
536 { CVT_imm_95_3, 0, CVT_Done },
537 // Convert__imm_95_1
538 { CVT_imm_95_1, 0, CVT_Done },
539 // Convert__Reg1_0__Reg1_1
540 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
541 // Convert__Reg1_1__Reg1_0
542 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
543 // Convert__Reg1_0__Reg1_2__Tie1_3_3
544 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Tied, Tie1_3_3, CVT_Done },
545 // Convert__Reg1_0__Reg1_1__Tie1_2_2
546 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie1_2_2, CVT_Done },
547 // Convert__Reg1_0__Memri2_1
548 { CVT_95_Reg, 1, CVT_95_addMemriOperands, 2, CVT_Done },
549 // Convert__Imm1_0__Reg1_1
550 { CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
551 // Convert__Reg1_0
552 { CVT_95_Reg, 1, CVT_Done },
553 // Convert__Reg1_0__imm_95_255
554 { CVT_95_Reg, 1, CVT_imm_95_255, 0, CVT_Done },
555 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0
556 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
557 // Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0
558 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
559 // Convert__Memri2_0__Reg1_1
560 { CVT_95_addMemriOperands, 1, CVT_95_Reg, 2, CVT_Done },
561};
562
563void AVRAsmParser::
564convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
565 const OperandVector &Operands) {
566 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
567 const uint8_t *Converter = ConversionTable[Kind];
568 Inst.setOpcode(Opcode);
569 for (const uint8_t *p = Converter; *p; p += 2) {
570 unsigned OpIdx = *(p + 1);
571 switch (*p) {
572 default: llvm_unreachable("invalid conversion entry!");
573 case CVT_Reg:
574 static_cast<AVROperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
575 break;
576 case CVT_Tied: {
577 assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) -
578 std::begin(TiedAsmOperandTable)) &&
579 "Tied operand not found");
580 unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0];
581 if (TiedResOpnd != (uint8_t)-1)
582 Inst.addOperand(Inst.getOperand(TiedResOpnd));
583 break;
584 }
585 case CVT_95_Reg:
586 static_cast<AVROperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
587 break;
588 case CVT_95_addImmOperands:
589 static_cast<AVROperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
590 break;
591 case CVT_imm_95_0:
592 Inst.addOperand(MCOperand::createImm(0));
593 break;
594 case CVT_imm_95_5:
595 Inst.addOperand(MCOperand::createImm(5));
596 break;
597 case CVT_imm_95_7:
598 Inst.addOperand(MCOperand::createImm(7));
599 break;
600 case CVT_imm_95_6:
601 Inst.addOperand(MCOperand::createImm(6));
602 break;
603 case CVT_imm_95_3:
604 Inst.addOperand(MCOperand::createImm(3));
605 break;
606 case CVT_95_addImmCom8Operands:
607 static_cast<AVROperand &>(*Operands[OpIdx]).addImmCom8Operands(Inst, 1);
608 break;
609 case CVT_imm_95_2:
610 Inst.addOperand(MCOperand::createImm(2));
611 break;
612 case CVT_imm_95_4:
613 Inst.addOperand(MCOperand::createImm(4));
614 break;
615 case CVT_imm_95_1:
616 Inst.addOperand(MCOperand::createImm(1));
617 break;
618 case CVT_95_addMemriOperands:
619 static_cast<AVROperand &>(*Operands[OpIdx]).addMemriOperands(Inst, 2);
620 break;
621 case CVT_imm_95_255:
622 Inst.addOperand(MCOperand::createImm(255));
623 break;
624 }
625 }
626}
627
628void AVRAsmParser::
629convertToMapAndConstraints(unsigned Kind,
630 const OperandVector &Operands) {
631 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
632 unsigned NumMCOperands = 0;
633 const uint8_t *Converter = ConversionTable[Kind];
634 for (const uint8_t *p = Converter; *p; p += 2) {
635 switch (*p) {
636 default: llvm_unreachable("invalid conversion entry!");
637 case CVT_Reg:
638 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
639 Operands[*(p + 1)]->setConstraint("r");
640 ++NumMCOperands;
641 break;
642 case CVT_Tied:
643 ++NumMCOperands;
644 break;
645 case CVT_95_Reg:
646 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
647 Operands[*(p + 1)]->setConstraint("r");
648 NumMCOperands += 1;
649 break;
650 case CVT_95_addImmOperands:
651 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
652 Operands[*(p + 1)]->setConstraint("m");
653 NumMCOperands += 1;
654 break;
655 case CVT_imm_95_0:
656 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
657 Operands[*(p + 1)]->setConstraint("");
658 ++NumMCOperands;
659 break;
660 case CVT_imm_95_5:
661 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
662 Operands[*(p + 1)]->setConstraint("");
663 ++NumMCOperands;
664 break;
665 case CVT_imm_95_7:
666 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
667 Operands[*(p + 1)]->setConstraint("");
668 ++NumMCOperands;
669 break;
670 case CVT_imm_95_6:
671 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
672 Operands[*(p + 1)]->setConstraint("");
673 ++NumMCOperands;
674 break;
675 case CVT_imm_95_3:
676 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
677 Operands[*(p + 1)]->setConstraint("");
678 ++NumMCOperands;
679 break;
680 case CVT_95_addImmCom8Operands:
681 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
682 Operands[*(p + 1)]->setConstraint("m");
683 NumMCOperands += 1;
684 break;
685 case CVT_imm_95_2:
686 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
687 Operands[*(p + 1)]->setConstraint("");
688 ++NumMCOperands;
689 break;
690 case CVT_imm_95_4:
691 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
692 Operands[*(p + 1)]->setConstraint("");
693 ++NumMCOperands;
694 break;
695 case CVT_imm_95_1:
696 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
697 Operands[*(p + 1)]->setConstraint("");
698 ++NumMCOperands;
699 break;
700 case CVT_95_addMemriOperands:
701 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
702 Operands[*(p + 1)]->setConstraint("m");
703 NumMCOperands += 2;
704 break;
705 case CVT_imm_95_255:
706 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
707 Operands[*(p + 1)]->setConstraint("");
708 ++NumMCOperands;
709 break;
710 }
711 }
712}
713
714namespace {
715
716/// MatchClassKind - The kinds of classes which participate in
717/// instruction matching.
718enum MatchClassKind {
719 InvalidMatchClass = 0,
720 OptionalMatchClass = 1,
721 MCK__43_, // '+'
722 MCK__MINUS_, // '-'
723 MCK_LAST_TOKEN = MCK__MINUS_,
724 MCK_Reg31, // derived register class
725 MCK_Reg16, // derived register class
726 MCK_CCR, // register class 'CCR'
727 MCK_GPRSP, // register class 'GPRSP'
728 MCK_ZREG, // register class 'ZREG'
729 MCK_Reg17, // derived register class
730 MCK_PTRDISPREGS, // register class 'PTRDISPREGS'
731 MCK_Reg18, // derived register class
732 MCK_PTRREGS, // register class 'PTRREGS'
733 MCK_DREGSLD8lo, // register class 'DREGSLD8lo'
734 MCK_IWREGS, // register class 'IWREGS'
735 MCK_Reg26, // derived register class
736 MCK_Reg19, // derived register class
737 MCK_Reg27, // derived register class
738 MCK_Reg25, // derived register class
739 MCK_DLDREGS, // register class 'DLDREGS'
740 MCK_DREGSlo, // register class 'DREGSlo'
741 MCK_LD8lo, // register class 'LD8lo'
742 MCK_Reg30, // derived register class
743 MCK_Reg29, // derived register class
744 MCK_Reg22, // derived register class
745 MCK_Reg23, // derived register class
746 MCK_Reg14, // derived register class
747 MCK_Reg15, // derived register class
748 MCK_Reg4, // derived register class
749 MCK_Reg20, // derived register class
750 MCK_DREGSMOVW, // register class 'DREGSMOVW'
751 MCK_GPR8lo, // register class 'GPR8lo'
752 MCK_LD8, // register class 'LD8'
753 MCK_DREGSNOZ, // register class 'DREGSNOZ'
754 MCK_DREGS, // register class 'DREGS'
755 MCK_GPR8NOZ, // register class 'GPR8NOZ'
756 MCK_GPR8, // register class 'GPR8'
757 MCK_LAST_REGISTER = MCK_GPR8,
758 MCK_Imm, // user defined class 'ImmAsmOperand'
759 MCK_Memri, // user defined class 'MemriAsmOperand'
760 MCK_ImmCom8, // user defined class 'imm_com8_asmoperand'
761 NumMatchClassKinds
762};
763
764} // end anonymous namespace
765
766static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
767 return MCTargetAsmParser::Match_InvalidOperand;
768}
769
770[[maybe_unused]] static const MCRegisterClass *getRegClassFromMatchKind(MatchClassKind Kind) {
771 switch (Kind) {
772 case MCK_CCR:
773 return &getAVRMCRegisterClass(AVR::CCRRegClassID);
774 case MCK_GPRSP:
775 return &getAVRMCRegisterClass(AVR::GPRSPRegClassID);
776 case MCK_ZREG:
777 return &getAVRMCRegisterClass(AVR::ZREGRegClassID);
778 case MCK_PTRDISPREGS:
779 return &getAVRMCRegisterClass(AVR::PTRDISPREGSRegClassID);
780 case MCK_PTRREGS:
781 return &getAVRMCRegisterClass(AVR::PTRREGSRegClassID);
782 case MCK_DREGSLD8lo:
783 return &getAVRMCRegisterClass(AVR::DREGSLD8loRegClassID);
784 case MCK_IWREGS:
785 return &getAVRMCRegisterClass(AVR::IWREGSRegClassID);
786 case MCK_DLDREGS:
787 return &getAVRMCRegisterClass(AVR::DLDREGSRegClassID);
788 case MCK_DREGSlo:
789 return &getAVRMCRegisterClass(AVR::DREGSloRegClassID);
790 case MCK_LD8lo:
791 return &getAVRMCRegisterClass(AVR::LD8loRegClassID);
792 case MCK_DREGSMOVW:
793 return &getAVRMCRegisterClass(AVR::DREGSMOVWRegClassID);
794 case MCK_GPR8lo:
795 return &getAVRMCRegisterClass(AVR::GPR8loRegClassID);
796 case MCK_LD8:
797 return &getAVRMCRegisterClass(AVR::LD8RegClassID);
798 case MCK_DREGSNOZ:
799 return &getAVRMCRegisterClass(AVR::DREGSNOZRegClassID);
800 case MCK_DREGS:
801 return &getAVRMCRegisterClass(AVR::DREGSRegClassID);
802 case MCK_GPR8NOZ:
803 return &getAVRMCRegisterClass(AVR::GPR8NOZRegClassID);
804 case MCK_GPR8:
805 return &getAVRMCRegisterClass(AVR::GPR8RegClassID);
806 default:
807 return nullptr;
808 }
809}
810
811static MatchClassKind matchTokenString(StringRef Name) {
812 switch (Name.size()) {
813 default: break;
814 case 1: // 2 strings to match.
815 switch (Name[0]) {
816 default: break;
817 case '+': // 1 string to match.
818 return MCK__43_; // "+"
819 case '-': // 1 string to match.
820 return MCK__MINUS_; // "-"
821 }
822 break;
823 }
824 return InvalidMatchClass;
825}
826
827/// isSubclass - Compute whether \p A is a subclass of \p B.
828static bool isSubclass(MatchClassKind A, MatchClassKind B) {
829 if (A == B)
830 return true;
831
832 [[maybe_unused]] static constexpr struct {
833 uint32_t Offset;
834 uint16_t Start;
835 uint16_t Length;
836 } Table[] = {
837 {0, 0, 0},
838 {0, 0, 0},
839 {0, 0, 0},
840 {0, 0, 0},
841 {0, 17, 18},
842 {18, 9, 26},
843 {44, 0, 0},
844 {44, 0, 0},
845 {44, 10, 25},
846 {69, 11, 24},
847 {93, 12, 23},
848 {116, 14, 21},
849 {137, 14, 21},
850 {158, 15, 20},
851 {178, 19, 16},
852 {194, 17, 18},
853 {212, 19, 16},
854 {228, 25, 10},
855 {238, 24, 11},
856 {249, 26, 9},
857 {258, 22, 13},
858 {271, 28, 9},
859 {280, 23, 12},
860 {292, 33, 2},
861 {294, 25, 10},
862 {304, 27, 8},
863 {312, 27, 8},
864 {320, 34, 1},
865 {321, 32, 5},
866 {326, 30, 5},
867 {331, 34, 1},
868 {332, 35, 2},
869 {334, 36, 1},
870 {335, 34, 1},
871 {336, 0, 0},
872 {336, 36, 1},
873 {337, 0, 0},
874 {337, 0, 0},
875 {337, 0, 0},
876 {337, 0, 0},
877 };
878
879 static constexpr uint8_t Data[] = {
880 0x41,
881 0x05,
882 0xBF,
883 0x12,
884 0xDE,
885 0x5C,
886 0x21,
887 0x30,
888 0x71,
889 0x25,
890 0xBC,
891 0xB9,
892 0x10,
893 0x98,
894 0x58,
895 0xC2,
896 0x9B,
897 0x43,
898 0x60,
899 0xE2,
900 0x87,
901 0x37,
902 0x07,
903 0x26,
904 0x0E,
905 0x1E,
906 0x1C,
907 0xDE,
908 0x5C,
909 0xF0,
910 0x83,
911 0x27,
912 0x0E,
913 0xE6,
914 0xC8,
915 0x01,
916 0xFC,
917 0xC1,
918 0xC1,
919 0x81,
920 0x73,
921 0xFE,
922 0x01,
923 };
924
925 auto &Entry = Table[A];
926 unsigned Idx = B - Entry.Start;
927 if (Idx >= Entry.Length)
928 return false;
929 Idx += Entry.Offset;
930 return (Data[Idx / 8] >> (Idx % 8)) & 1;
931}
932
933static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind, const MCSubtargetInfo &STI) {
934 AVROperand &Operand = (AVROperand &)GOp;
935 if (Kind == InvalidMatchClass)
936 return MCTargetAsmParser::Match_InvalidOperand;
937
938 if (Kind <= MCK_LAST_TOKEN) {
939 if (Operand.isToken() &&
940 isSubclass(matchTokenString(Operand.getToken()), Kind))
941 return MCTargetAsmParser::Match_Success;
942 return MCTargetAsmParser::Match_InvalidOperand;
943 }
944
945 switch (Kind) {
946 default: break;
947 case MCK_Imm: {
948 DiagnosticPredicate DP(Operand.isImm());
949 if (DP.isMatch())
950 return MCTargetAsmParser::Match_Success;
951 break;
952 }
953 case MCK_Memri: {
954 DiagnosticPredicate DP(Operand.isMemri());
955 if (DP.isMatch())
956 return MCTargetAsmParser::Match_Success;
957 break;
958 }
959 case MCK_ImmCom8: {
960 DiagnosticPredicate DP(Operand.isImmCom8());
961 if (DP.isMatch())
962 return MCTargetAsmParser::Match_Success;
963 break;
964 }
965 } // end switch (Kind)
966
967 if (Operand.isReg()) {
968 static constexpr uint16_t Table[AVR::NUM_TARGET_REGS] = {
969 InvalidMatchClass,
970 MCK_GPRSP,
971 InvalidMatchClass,
972 InvalidMatchClass,
973 MCK_CCR,
974 MCK_GPR8lo,
975 MCK_GPR8lo,
976 MCK_GPR8lo,
977 MCK_GPR8lo,
978 MCK_GPR8lo,
979 MCK_GPR8lo,
980 MCK_GPR8lo,
981 MCK_GPR8lo,
982 MCK_GPR8lo,
983 MCK_GPR8lo,
984 MCK_GPR8lo,
985 MCK_GPR8lo,
986 MCK_GPR8lo,
987 MCK_GPR8lo,
988 MCK_GPR8lo,
989 MCK_GPR8lo,
990 MCK_LD8lo,
991 MCK_LD8lo,
992 MCK_LD8lo,
993 MCK_LD8lo,
994 MCK_LD8lo,
995 MCK_LD8lo,
996 MCK_LD8lo,
997 MCK_LD8lo,
998 MCK_Reg4,
999 MCK_Reg4,
1000 MCK_Reg4,
1001 MCK_Reg4,
1002 MCK_Reg4,
1003 MCK_Reg4,
1004 MCK_LD8,
1005 MCK_LD8,
1006 MCK_DREGSlo,
1007 MCK_DREGSlo,
1008 MCK_DREGSlo,
1009 MCK_DREGSlo,
1010 MCK_DREGSlo,
1011 MCK_Reg30,
1012 MCK_DREGSlo,
1013 MCK_Reg30,
1014 MCK_DREGSlo,
1015 MCK_Reg30,
1016 MCK_DREGSlo,
1017 MCK_Reg31,
1018 MCK_DREGSLD8lo,
1019 MCK_Reg26,
1020 MCK_DREGSLD8lo,
1021 MCK_Reg26,
1022 MCK_DREGSLD8lo,
1023 MCK_Reg26,
1024 MCK_DREGSLD8lo,
1025 MCK_Reg25,
1026 MCK_Reg18,
1027 MCK_Reg22,
1028 MCK_Reg17,
1029 MCK_Reg16,
1030 MCK_ZREG,
1031 };
1032
1033 MCRegister Reg = Operand.getReg();
1034 MatchClassKind OpKind = Reg.isPhysical() ? (MatchClassKind)Table[Reg.id()] : InvalidMatchClass;
1035 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
1036 getDiagKindFromRegisterClass(Kind);
1037 }
1038
1039 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
1040 return getDiagKindFromRegisterClass(Kind);
1041
1042 return MCTargetAsmParser::Match_InvalidOperand;
1043}
1044
1045#ifndef NDEBUG
1046const char *getMatchClassName(MatchClassKind Kind) {
1047 switch (Kind) {
1048 case InvalidMatchClass: return "InvalidMatchClass";
1049 case OptionalMatchClass: return "OptionalMatchClass";
1050 case MCK__43_: return "MCK__43_";
1051 case MCK__MINUS_: return "MCK__MINUS_";
1052 case MCK_Reg31: return "MCK_Reg31";
1053 case MCK_Reg16: return "MCK_Reg16";
1054 case MCK_CCR: return "MCK_CCR";
1055 case MCK_GPRSP: return "MCK_GPRSP";
1056 case MCK_ZREG: return "MCK_ZREG";
1057 case MCK_Reg17: return "MCK_Reg17";
1058 case MCK_PTRDISPREGS: return "MCK_PTRDISPREGS";
1059 case MCK_Reg18: return "MCK_Reg18";
1060 case MCK_PTRREGS: return "MCK_PTRREGS";
1061 case MCK_DREGSLD8lo: return "MCK_DREGSLD8lo";
1062 case MCK_IWREGS: return "MCK_IWREGS";
1063 case MCK_Reg26: return "MCK_Reg26";
1064 case MCK_Reg19: return "MCK_Reg19";
1065 case MCK_Reg27: return "MCK_Reg27";
1066 case MCK_Reg25: return "MCK_Reg25";
1067 case MCK_DLDREGS: return "MCK_DLDREGS";
1068 case MCK_DREGSlo: return "MCK_DREGSlo";
1069 case MCK_LD8lo: return "MCK_LD8lo";
1070 case MCK_Reg30: return "MCK_Reg30";
1071 case MCK_Reg29: return "MCK_Reg29";
1072 case MCK_Reg22: return "MCK_Reg22";
1073 case MCK_Reg23: return "MCK_Reg23";
1074 case MCK_Reg14: return "MCK_Reg14";
1075 case MCK_Reg15: return "MCK_Reg15";
1076 case MCK_Reg4: return "MCK_Reg4";
1077 case MCK_Reg20: return "MCK_Reg20";
1078 case MCK_DREGSMOVW: return "MCK_DREGSMOVW";
1079 case MCK_GPR8lo: return "MCK_GPR8lo";
1080 case MCK_LD8: return "MCK_LD8";
1081 case MCK_DREGSNOZ: return "MCK_DREGSNOZ";
1082 case MCK_DREGS: return "MCK_DREGS";
1083 case MCK_GPR8NOZ: return "MCK_GPR8NOZ";
1084 case MCK_GPR8: return "MCK_GPR8";
1085 case MCK_Imm: return "MCK_Imm";
1086 case MCK_Memri: return "MCK_Memri";
1087 case MCK_ImmCom8: return "MCK_ImmCom8";
1088 case NumMatchClassKinds: return "NumMatchClassKinds";
1089 }
1090 llvm_unreachable("unhandled MatchClassKind!");
1091}
1092
1093#endif // NDEBUG
1094FeatureBitset AVRAsmParser::
1095ComputeAvailableFeatures(const FeatureBitset &FB) const {
1096 FeatureBitset Features;
1097 if (FB[AVR::FeatureSRAM])
1098 Features.set(Feature_HasSRAMBit);
1099 if (FB[AVR::FeatureJMPCALL])
1100 Features.set(Feature_HasJMPCALLBit);
1101 if (FB[AVR::FeatureIJMPCALL])
1102 Features.set(Feature_HasIJMPCALLBit);
1103 if (FB[AVR::FeatureEIJMPCALL])
1104 Features.set(Feature_HasEIJMPCALLBit);
1105 if (FB[AVR::FeatureADDSUBIW])
1106 Features.set(Feature_HasADDSUBIWBit);
1107 if (FB[AVR::FeatureSmallStack])
1108 Features.set(Feature_HasSmallStackBit);
1109 if (FB[AVR::FeatureMOVW])
1110 Features.set(Feature_HasMOVWBit);
1111 if (FB[AVR::FeatureLPM])
1112 Features.set(Feature_HasLPMBit);
1113 if (FB[AVR::FeatureLPMX])
1114 Features.set(Feature_HasLPMXBit);
1115 if (FB[AVR::FeatureELPM])
1116 Features.set(Feature_HasELPMBit);
1117 if (FB[AVR::FeatureELPMX])
1118 Features.set(Feature_HasELPMXBit);
1119 if (FB[AVR::FeatureSPM])
1120 Features.set(Feature_HasSPMBit);
1121 if (FB[AVR::FeatureSPMX])
1122 Features.set(Feature_HasSPMXBit);
1123 if (FB[AVR::FeatureDES])
1124 Features.set(Feature_HasDESBit);
1125 if (FB[AVR::FeatureRMW])
1126 Features.set(Feature_SupportsRMWBit);
1127 if (FB[AVR::FeatureMultiplication])
1128 Features.set(Feature_SupportsMultiplicationBit);
1129 if (FB[AVR::FeatureBREAK])
1130 Features.set(Feature_HasBREAKBit);
1131 if (FB[AVR::FeatureTinyEncoding])
1132 Features.set(Feature_HasTinyEncodingBit);
1133 if (!(FB[AVR::FeatureTinyEncoding]))
1134 Features.set(Feature_HasNonTinyEncodingBit);
1135 return Features;
1136}
1137
1138static bool checkAsmTiedOperandConstraints(const AVRAsmParser&AsmParser,
1139 unsigned Kind, const OperandVector &Operands,
1140 uint64_t &ErrorInfo) {
1141 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1142 const uint8_t *Converter = ConversionTable[Kind];
1143 for (const uint8_t *p = Converter; *p; p += 2) {
1144 switch (*p) {
1145 case CVT_Tied: {
1146 unsigned OpIdx = *(p + 1);
1147 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1148 std::begin(TiedAsmOperandTable)) &&
1149 "Tied operand not found");
1150 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
1151 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
1152 if (OpndNum1 != OpndNum2) {
1153 auto &SrcOp1 = Operands[OpndNum1];
1154 auto &SrcOp2 = Operands[OpndNum2];
1155 if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
1156 ErrorInfo = OpndNum2;
1157 return false;
1158 }
1159 }
1160 break;
1161 }
1162 default:
1163 break;
1164 }
1165 }
1166 return true;
1167}
1168
1169static const char MnemonicTable[] =
1170 "\003adc\003add\004adiw\003and\004andi\003asr\004bclr\003bld\004brbc\004"
1171 "brbs\004brcc\004brcs\005break\004breq\004brge\004brhc\004brhs\004brid\004"
1172 "brie\004brlo\004brlt\004brmi\004brne\004brpl\004brsh\004brtc\004brts\004"
1173 "brvc\004brvs\004bset\003bst\004call\003cbi\003cbr\003clc\003clh\003cli\003"
1174 "cln\003clr\003cls\003clt\003clv\003clz\003com\002cp\003cpc\003cpi\004cp"
1175 "se\003dec\003des\006eicall\005eijmp\004elpm\003eor\004fmul\005fmuls\006"
1176 "fmulsu\005icall\004ijmp\002in\003inc\003jmp\003lac\003las\003lat\002ld\003"
1177 "ldd\003ldi\003lds\003lpm\003lsl\003lsr\003mov\004movw\003mul\004muls\005"
1178 "mulsu\003neg\003nop\002or\003ori\003out\003pop\004push\005rcall\003ret\004"
1179 "reti\004rjmp\003rol\003ror\003sbc\004sbci\003sbi\004sbic\004sbis\004sbi"
1180 "w\003sbr\004sbrc\004sbrs\003sec\003seh\003sei\003sen\003ser\003ses\003s"
1181 "et\003sev\003sez\005sleep\003spm\002st\003std\003sts\003sub\004subi\004"
1182 "swap\003tst\003wdr\003xch";
1183
1184// Feature bitsets.
1185enum : uint8_t {
1186 AMFBS_None,
1187 AMFBS_HasADDSUBIW,
1188 AMFBS_HasBREAK,
1189 AMFBS_HasDES,
1190 AMFBS_HasEIJMPCALL,
1191 AMFBS_HasELPM,
1192 AMFBS_HasELPMX,
1193 AMFBS_HasIJMPCALL,
1194 AMFBS_HasJMPCALL,
1195 AMFBS_HasLPM,
1196 AMFBS_HasLPMX,
1197 AMFBS_HasMOVW,
1198 AMFBS_HasSPM,
1199 AMFBS_HasSPMX,
1200 AMFBS_HasSRAM,
1201 AMFBS_SupportsMultiplication,
1202 AMFBS_SupportsRMW,
1203 AMFBS_HasSRAM_HasNonTinyEncoding,
1204 AMFBS_HasSRAM_HasTinyEncoding,
1205};
1206
1207static constexpr FeatureBitset FeatureBitsets[] = {
1208 {}, // AMFBS_None
1209 {Feature_HasADDSUBIWBit, }, // AMFBS_HasADDSUBIW
1210 {Feature_HasBREAKBit, }, // AMFBS_HasBREAK
1211 {Feature_HasDESBit, }, // AMFBS_HasDES
1212 {Feature_HasEIJMPCALLBit, }, // AMFBS_HasEIJMPCALL
1213 {Feature_HasELPMBit, }, // AMFBS_HasELPM
1214 {Feature_HasELPMXBit, }, // AMFBS_HasELPMX
1215 {Feature_HasIJMPCALLBit, }, // AMFBS_HasIJMPCALL
1216 {Feature_HasJMPCALLBit, }, // AMFBS_HasJMPCALL
1217 {Feature_HasLPMBit, }, // AMFBS_HasLPM
1218 {Feature_HasLPMXBit, }, // AMFBS_HasLPMX
1219 {Feature_HasMOVWBit, }, // AMFBS_HasMOVW
1220 {Feature_HasSPMBit, }, // AMFBS_HasSPM
1221 {Feature_HasSPMXBit, }, // AMFBS_HasSPMX
1222 {Feature_HasSRAMBit, }, // AMFBS_HasSRAM
1223 {Feature_SupportsMultiplicationBit, }, // AMFBS_SupportsMultiplication
1224 {Feature_SupportsRMWBit, }, // AMFBS_SupportsRMW
1225 {Feature_HasSRAMBit, Feature_HasNonTinyEncodingBit, }, // AMFBS_HasSRAM_HasNonTinyEncoding
1226 {Feature_HasSRAMBit, Feature_HasTinyEncodingBit, }, // AMFBS_HasSRAM_HasTinyEncoding
1227};
1228
1229namespace {
1230 struct MatchEntry {
1231 uint16_t Mnemonic;
1232 uint32_t Opcode;
1233 uint8_t ConvertFn;
1234 uint8_t RequiredFeaturesIdx;
1235 uint8_t Classes[3];
1236 StringRef getMnemonic() const {
1237 return StringRef(MnemonicTable + Mnemonic + 1,
1238 MnemonicTable[Mnemonic]);
1239 }
1240 };
1241
1242 // Predicate for searching for an opcode.
1243 struct LessOpcode {
1244 bool operator()(const MatchEntry &LHS, StringRef RHS) {
1245 return LHS.getMnemonic() < RHS;
1246 }
1247 bool operator()(StringRef LHS, const MatchEntry &RHS) {
1248 return LHS < RHS.getMnemonic();
1249 }
1250 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
1251 return LHS.getMnemonic() < RHS.getMnemonic();
1252 }
1253 };
1254} // end anonymous namespace
1255
1256static const MatchEntry MatchTable0[] = {
1257 { 0 /* adc */, AVR::ADCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1258 { 4 /* add */, AVR::ADDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1259 { 8 /* adiw */, AVR::ADIWRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_HasADDSUBIW, { MCK_IWREGS, MCK_Imm }, },
1260 { 13 /* and */, AVR::ANDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1261 { 17 /* andi */, AVR::ANDIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1262 { 22 /* asr */, AVR::ASRRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1263 { 26 /* bclr */, AVR::BCLRs, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1264 { 31 /* bld */, AVR::BLD, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1265 { 35 /* brbc */, AVR::BRBCsk, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1266 { 40 /* brbs */, AVR::BRBSsk, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1267 { 45 /* brcc */, AVR::BRBCsk, Convert__imm_95_0__Imm1_0, AMFBS_None, { MCK_Imm }, },
1268 { 50 /* brcs */, AVR::BRBSsk, Convert__imm_95_0__Imm1_0, AMFBS_None, { MCK_Imm }, },
1269 { 55 /* break */, AVR::BREAK, Convert_NoOperands, AMFBS_HasBREAK, { }, },
1270 { 61 /* breq */, AVR::BREQk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1271 { 66 /* brge */, AVR::BRGEk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1272 { 71 /* brhc */, AVR::BRBCsk, Convert__imm_95_5__Imm1_0, AMFBS_None, { MCK_Imm }, },
1273 { 76 /* brhs */, AVR::BRBSsk, Convert__imm_95_5__Imm1_0, AMFBS_None, { MCK_Imm }, },
1274 { 81 /* brid */, AVR::BRBCsk, Convert__imm_95_7__Imm1_0, AMFBS_None, { MCK_Imm }, },
1275 { 86 /* brie */, AVR::BRBSsk, Convert__imm_95_7__Imm1_0, AMFBS_None, { MCK_Imm }, },
1276 { 91 /* brlo */, AVR::BRLOk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1277 { 96 /* brlt */, AVR::BRLTk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1278 { 101 /* brmi */, AVR::BRMIk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1279 { 106 /* brne */, AVR::BRNEk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1280 { 111 /* brpl */, AVR::BRPLk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1281 { 116 /* brsh */, AVR::BRSHk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1282 { 121 /* brtc */, AVR::BRBCsk, Convert__imm_95_6__Imm1_0, AMFBS_None, { MCK_Imm }, },
1283 { 126 /* brts */, AVR::BRBSsk, Convert__imm_95_6__Imm1_0, AMFBS_None, { MCK_Imm }, },
1284 { 131 /* brvc */, AVR::BRBCsk, Convert__imm_95_3__Imm1_0, AMFBS_None, { MCK_Imm }, },
1285 { 136 /* brvs */, AVR::BRBSsk, Convert__imm_95_3__Imm1_0, AMFBS_None, { MCK_Imm }, },
1286 { 141 /* bset */, AVR::BSETs, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1287 { 146 /* bst */, AVR::BST, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1288 { 150 /* call */, AVR::CALLk, Convert__Imm1_0, AMFBS_HasJMPCALL, { MCK_Imm }, },
1289 { 155 /* cbi */, AVR::CBIAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1290 { 159 /* cbr */, AVR::ANDIRdK, Convert__Reg1_0__Tie0_1_1__ImmCom81_1, AMFBS_None, { MCK_LD8, MCK_ImmCom8 }, },
1291 { 163 /* clc */, AVR::BCLRs, Convert__imm_95_0, AMFBS_None, { }, },
1292 { 167 /* clh */, AVR::BCLRs, Convert__imm_95_5, AMFBS_None, { }, },
1293 { 171 /* cli */, AVR::BCLRs, Convert__imm_95_7, AMFBS_None, { }, },
1294 { 175 /* cln */, AVR::BCLRs, Convert__imm_95_2, AMFBS_None, { }, },
1295 { 179 /* clr */, AVR::EORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1296 { 183 /* cls */, AVR::BCLRs, Convert__imm_95_4, AMFBS_None, { }, },
1297 { 187 /* clt */, AVR::BCLRs, Convert__imm_95_6, AMFBS_None, { }, },
1298 { 191 /* clv */, AVR::BCLRs, Convert__imm_95_3, AMFBS_None, { }, },
1299 { 195 /* clz */, AVR::BCLRs, Convert__imm_95_1, AMFBS_None, { }, },
1300 { 199 /* com */, AVR::COMRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1301 { 203 /* cp */, AVR::CPRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1302 { 206 /* cpc */, AVR::CPCRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1303 { 210 /* cpi */, AVR::CPIRdK, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1304 { 214 /* cpse */, AVR::CPSE, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1305 { 219 /* dec */, AVR::DECRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1306 { 223 /* des */, AVR::DESK, Convert__Imm1_0, AMFBS_HasDES, { MCK_Imm }, },
1307 { 227 /* eicall */, AVR::EICALL, Convert_NoOperands, AMFBS_HasEIJMPCALL, { }, },
1308 { 234 /* eijmp */, AVR::EIJMP, Convert_NoOperands, AMFBS_HasEIJMPCALL, { }, },
1309 { 240 /* elpm */, AVR::ELPM, Convert_NoOperands, AMFBS_HasELPM, { }, },
1310 { 240 /* elpm */, AVR::ELPMRdZ, Convert__Reg1_0__Reg1_1, AMFBS_HasELPMX, { MCK_GPR8, MCK_ZREG }, },
1311 { 240 /* elpm */, AVR::ELPMRdZPi, Convert__Reg1_0__Reg1_1, AMFBS_HasELPMX, { MCK_GPR8, MCK_ZREG, MCK__43_ }, },
1312 { 245 /* eor */, AVR::EORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1313 { 249 /* fmul */, AVR::FMUL, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1314 { 254 /* fmuls */, AVR::FMULS, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1315 { 260 /* fmulsu */, AVR::FMULSU, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1316 { 267 /* icall */, AVR::ICALL, Convert_NoOperands, AMFBS_HasIJMPCALL, { }, },
1317 { 273 /* ijmp */, AVR::IJMP, Convert_NoOperands, AMFBS_HasIJMPCALL, { }, },
1318 { 278 /* in */, AVR::INRdA, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1319 { 281 /* inc */, AVR::INCRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1320 { 285 /* jmp */, AVR::JMPk, Convert__Imm1_0, AMFBS_HasJMPCALL, { MCK_Imm }, },
1321 { 289 /* lac */, AVR::LACZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1322 { 293 /* las */, AVR::LASZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1323 { 297 /* lat */, AVR::LATZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1324 { 301 /* ld */, AVR::LDRdPtr, Convert__Reg1_0__Reg1_1, AMFBS_HasSRAM, { MCK_GPR8, MCK_PTRREGS }, },
1325 { 301 /* ld */, AVR::LDRdPtrPd, Convert__Reg1_0__Reg1_2__Tie1_3_3, AMFBS_HasSRAM, { MCK_GPR8, MCK__MINUS_, MCK_PTRREGS }, },
1326 { 301 /* ld */, AVR::LDRdPtrPi, Convert__Reg1_0__Reg1_1__Tie1_2_2, AMFBS_HasSRAM, { MCK_GPR8, MCK_PTRREGS, MCK__43_ }, },
1327 { 304 /* ldd */, AVR::LDDRdPtrQ, Convert__Reg1_0__Memri2_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_GPR8, MCK_Memri }, },
1328 { 308 /* ldi */, AVR::LDIRdK, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1329 { 312 /* lds */, AVR::LDSRdKTiny, Convert__Reg1_0__Imm1_1, AMFBS_HasSRAM_HasTinyEncoding, { MCK_LD8, MCK_Imm }, },
1330 { 312 /* lds */, AVR::LDSRdK, Convert__Reg1_0__Imm1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_GPR8, MCK_Imm }, },
1331 { 316 /* lpm */, AVR::LPM, Convert_NoOperands, AMFBS_HasLPM, { }, },
1332 { 316 /* lpm */, AVR::LPMRdZ, Convert__Reg1_0__Reg1_1, AMFBS_HasLPMX, { MCK_GPR8, MCK_ZREG }, },
1333 { 316 /* lpm */, AVR::LPMRdZPi, Convert__Reg1_0__Reg1_1, AMFBS_HasLPMX, { MCK_GPR8, MCK_ZREG, MCK__43_ }, },
1334 { 320 /* lsl */, AVR::ADDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1335 { 324 /* lsr */, AVR::LSRRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1336 { 328 /* mov */, AVR::MOVRdRr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1337 { 332 /* movw */, AVR::MOVWRdRr, Convert__Reg1_0__Reg1_1, AMFBS_HasMOVW, { MCK_DREGS, MCK_DREGS }, },
1338 { 337 /* mul */, AVR::MULRdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_GPR8, MCK_GPR8 }, },
1339 { 341 /* muls */, AVR::MULSRdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8, MCK_LD8 }, },
1340 { 346 /* mulsu */, AVR::MULSURdRr, Convert__Reg1_0__Reg1_1, AMFBS_SupportsMultiplication, { MCK_LD8lo, MCK_LD8lo }, },
1341 { 352 /* neg */, AVR::NEGRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1342 { 356 /* nop */, AVR::NOP, Convert_NoOperands, AMFBS_None, { }, },
1343 { 360 /* or */, AVR::ORRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1344 { 363 /* ori */, AVR::ORIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1345 { 367 /* out */, AVR::OUTARr, Convert__Imm1_0__Reg1_1, AMFBS_None, { MCK_Imm, MCK_GPR8 }, },
1346 { 371 /* pop */, AVR::POPRd, Convert__Reg1_0, AMFBS_HasSRAM, { MCK_GPR8 }, },
1347 { 375 /* push */, AVR::PUSHRr, Convert__Reg1_0, AMFBS_HasSRAM, { MCK_GPR8 }, },
1348 { 380 /* rcall */, AVR::RCALLk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1349 { 386 /* ret */, AVR::RET, Convert_NoOperands, AMFBS_None, { }, },
1350 { 390 /* reti */, AVR::RETI, Convert_NoOperands, AMFBS_None, { }, },
1351 { 395 /* rjmp */, AVR::RJMPk, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
1352 { 400 /* rol */, AVR::ADCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1353 { 404 /* ror */, AVR::RORRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1354 { 408 /* sbc */, AVR::SBCRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1355 { 412 /* sbci */, AVR::SBCIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1356 { 417 /* sbi */, AVR::SBIAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1357 { 421 /* sbic */, AVR::SBICAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1358 { 426 /* sbis */, AVR::SBISAb, Convert__Imm1_0__Imm1_1, AMFBS_None, { MCK_Imm, MCK_Imm }, },
1359 { 431 /* sbiw */, AVR::SBIWRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_HasADDSUBIW, { MCK_IWREGS, MCK_Imm }, },
1360 { 436 /* sbr */, AVR::ORIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1361 { 440 /* sbrc */, AVR::SBRCRrB, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1362 { 445 /* sbrs */, AVR::SBRSRrB, Convert__Reg1_0__Imm1_1, AMFBS_None, { MCK_GPR8, MCK_Imm }, },
1363 { 450 /* sec */, AVR::BSETs, Convert__imm_95_0, AMFBS_None, { }, },
1364 { 454 /* seh */, AVR::BSETs, Convert__imm_95_5, AMFBS_None, { }, },
1365 { 458 /* sei */, AVR::BSETs, Convert__imm_95_7, AMFBS_None, { }, },
1366 { 462 /* sen */, AVR::BSETs, Convert__imm_95_2, AMFBS_None, { }, },
1367 { 466 /* ser */, AVR::LDIRdK, Convert__Reg1_0__imm_95_255, AMFBS_None, { MCK_LD8 }, },
1368 { 470 /* ses */, AVR::BSETs, Convert__imm_95_4, AMFBS_None, { }, },
1369 { 474 /* set */, AVR::BSETs, Convert__imm_95_6, AMFBS_None, { }, },
1370 { 478 /* sev */, AVR::BSETs, Convert__imm_95_3, AMFBS_None, { }, },
1371 { 482 /* sez */, AVR::BSETs, Convert__imm_95_1, AMFBS_None, { }, },
1372 { 486 /* sleep */, AVR::SLEEP, Convert_NoOperands, AMFBS_None, { }, },
1373 { 492 /* spm */, AVR::SPM, Convert_NoOperands, AMFBS_HasSPM, { }, },
1374 { 492 /* spm */, AVR::SPMZPi, Convert__Reg1_0, AMFBS_HasSPMX, { MCK_ZREG, MCK__43_ }, },
1375 { 496 /* st */, AVR::STPtrRr, Convert__Reg1_0__Reg1_1, AMFBS_HasSRAM, { MCK_PTRREGS, MCK_GPR8 }, },
1376 { 496 /* st */, AVR::STPtrPdRr, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0, AMFBS_HasSRAM, { MCK__MINUS_, MCK_PTRREGS, MCK_GPR8 }, },
1377 { 496 /* st */, AVR::STPtrPiRr, Convert__Reg1_0__Tie0_1_1__Reg1_2__imm_95_0, AMFBS_HasSRAM, { MCK_PTRREGS, MCK__43_, MCK_GPR8 }, },
1378 { 499 /* std */, AVR::STDPtrQRr, Convert__Memri2_0__Reg1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_Memri, MCK_GPR8 }, },
1379 { 503 /* sts */, AVR::STSKRrTiny, Convert__Imm1_0__Reg1_1, AMFBS_HasSRAM_HasTinyEncoding, { MCK_Imm, MCK_LD8 }, },
1380 { 503 /* sts */, AVR::STSKRr, Convert__Imm1_0__Reg1_1, AMFBS_HasSRAM_HasNonTinyEncoding, { MCK_Imm, MCK_GPR8 }, },
1381 { 507 /* sub */, AVR::SUBRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_None, { MCK_GPR8, MCK_GPR8 }, },
1382 { 511 /* subi */, AVR::SUBIRdK, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_LD8, MCK_Imm }, },
1383 { 516 /* swap */, AVR::SWAPRd, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GPR8 }, },
1384 { 521 /* tst */, AVR::ANDRdRr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GPR8 }, },
1385 { 525 /* wdr */, AVR::WDR, Convert_NoOperands, AMFBS_None, { }, },
1386 { 529 /* xch */, AVR::XCHZRd, Convert__Reg1_1__Reg1_0, AMFBS_SupportsRMW, { MCK_ZREG, MCK_GPR8 }, },
1387};
1388
1389#include "llvm/Support/Debug.h"
1390#include "llvm/Support/Format.h"
1391
1392unsigned AVRAsmParser::
1393MatchInstructionImpl(const OperandVector &Operands,
1394 MCInst &Inst,
1395 uint64_t &ErrorInfo,
1396 FeatureBitset &MissingFeatures,
1397 bool matchingInlineAsm, unsigned VariantID) {
1398 // Eliminate obvious mismatches.
1399 if (Operands.size() > 4) {
1400 ErrorInfo = 4;
1401 return Match_InvalidOperand;
1402 }
1403
1404 // Get the current feature set.
1405 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1406
1407 // Get the instruction mnemonic, which is the first token.
1408 StringRef Mnemonic = ((AVROperand &)*Operands[0]).getToken();
1409
1410 // Some state to try to produce better error messages.
1411 bool HadMatchOtherThanFeatures = false;
1412 bool HadMatchOtherThanPredicate = false;
1413 unsigned RetCode = Match_InvalidOperand;
1414 MissingFeatures.set();
1415 // Set ErrorInfo to the operand that mismatches if it is
1416 // wrong for all instances of the instruction.
1417 ErrorInfo = ~0ULL;
1418 // Find the appropriate table for this asm variant.
1419 const MatchEntry *Start, *End;
1420 switch (VariantID) {
1421 default: llvm_unreachable("invalid variant!");
1422 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1423 }
1424 // Search the table.
1425 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1426
1427 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
1428 std::distance(MnemonicRange.first, MnemonicRange.second) <<
1429 " encodings with mnemonic '" << Mnemonic << "'\n");
1430
1431 // Return a more specific error code if no mnemonics match.
1432 if (MnemonicRange.first == MnemonicRange.second)
1433 return Match_MnemonicFail;
1434
1435 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1436 it != ie; ++it) {
1437 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1438 bool HasRequiredFeatures =
1439 (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
1440 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
1441 << MII.getName(it->Opcode) << "\n");
1442 // equal_range guarantees that instruction mnemonic matches.
1443 assert(Mnemonic == it->getMnemonic());
1444 bool OperandsValid = true;
1445 unsigned ActualIdx = 1;
1446 for (unsigned FormalIdx = 0; FormalIdx != 3; ++FormalIdx) {
1447 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
1448 DEBUG_WITH_TYPE("asm-matcher",
1449 dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
1450 << " against actual operand at index " << ActualIdx);
1451 if (ActualIdx < Operands.size())
1452 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
1453 Operands[ActualIdx]->print(dbgs(), getContext().getAsmInfo()); dbgs() << "): ");
1454 else
1455 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
1456 if (ActualIdx >= Operands.size()) {
1457 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
1458 if (Formal == InvalidMatchClass) {
1459 break;
1460 }
1461 if (isSubclass(Formal, OptionalMatchClass)) {
1462 continue;
1463 }
1464 OperandsValid = false;
1465 ErrorInfo = ActualIdx;
1466 break;
1467 }
1468 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
1469 unsigned Diag = validateOperandClass(Actual, Formal, *STI);
1470 if (Diag == Match_Success) {
1471 DEBUG_WITH_TYPE("asm-matcher",
1472 dbgs() << "match success using generic matcher\n");
1473 ++ActualIdx;
1474 continue;
1475 }
1476 // If the generic handler indicates an invalid operand
1477 // failure, check for a special case.
1478 if (Diag != Match_Success) {
1479 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
1480 if (TargetDiag == Match_Success) {
1481 DEBUG_WITH_TYPE("asm-matcher",
1482 dbgs() << "match success using target matcher\n");
1483 ++ActualIdx;
1484 continue;
1485 }
1486 // If the target matcher returned a specific error code use
1487 // that, else use the one from the generic matcher.
1488 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
1489 Diag = TargetDiag;
1490 }
1491 // If current formal operand wasn't matched and it is optional
1492 // then try to match next formal operand
1493 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
1494 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
1495 continue;
1496 }
1497 // If this operand is broken for all of the instances of this
1498 // mnemonic, keep track of it so we can report loc info.
1499 // If we already had a match that only failed due to a
1500 // target predicate, that diagnostic is preferred.
1501 if (!HadMatchOtherThanPredicate &&
1502 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
1503 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
1504 RetCode = Diag;
1505 ErrorInfo = ActualIdx;
1506 }
1507 // Otherwise, just reject this instance of the mnemonic.
1508 OperandsValid = false;
1509 break;
1510 }
1511
1512 if (!OperandsValid) {
1513 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
1514 "operand mismatches, ignoring "
1515 "this opcode\n");
1516 continue;
1517 }
1518 if (!HasRequiredFeatures) {
1519 HadMatchOtherThanFeatures = true;
1520 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
1521 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
1522 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
1523 if (NewMissingFeatures[I])
1524 dbgs() << ' ' << I;
1525 dbgs() << "\n");
1526 if (NewMissingFeatures.count() <=
1527 MissingFeatures.count())
1528 MissingFeatures = NewMissingFeatures;
1529 continue;
1530 }
1531
1532 Inst.clear();
1533
1534 Inst.setOpcode(it->Opcode);
1535 // We have a potential match but have not rendered the operands.
1536 // Check the target predicate to handle any context sensitive
1537 // constraints.
1538 // For example, Ties that are referenced multiple times must be
1539 // checked here to ensure the input is the same for each match
1540 // constraints. If we leave it any later the ties will have been
1541 // canonicalized
1542 unsigned MatchResult;
1543 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
1544 Inst.clear();
1545 DEBUG_WITH_TYPE(
1546 "asm-matcher",
1547 dbgs() << "Early target match predicate failed with diag code "
1548 << MatchResult << "\n");
1549 RetCode = MatchResult;
1550 HadMatchOtherThanPredicate = true;
1551 continue;
1552 }
1553
1554 if (matchingInlineAsm) {
1555 convertToMapAndConstraints(it->ConvertFn, Operands);
1556 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1557 ErrorInfo))
1558 return Match_InvalidTiedOperand;
1559
1560 return Match_Success;
1561 }
1562
1563 // We have selected a definite instruction, convert the parsed
1564 // operands into the appropriate MCInst.
1565 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
1566
1567 // We have a potential match. Check the target predicate to
1568 // handle any context sensitive constraints.
1569 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
1570 DEBUG_WITH_TYPE("asm-matcher",
1571 dbgs() << "Target match predicate failed with diag code "
1572 << MatchResult << "\n");
1573 Inst.clear();
1574 RetCode = MatchResult;
1575 HadMatchOtherThanPredicate = true;
1576 continue;
1577 }
1578
1579 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands,
1580 ErrorInfo))
1581 return Match_InvalidTiedOperand;
1582
1583 DEBUG_WITH_TYPE(
1584 "asm-matcher",
1585 dbgs() << "Opcode result: complete match, selecting this opcode\n");
1586 return Match_Success;
1587 }
1588
1589 // Okay, we had no match. Try to return a useful error code.
1590 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
1591 return RetCode;
1592
1593 ErrorInfo = 0;
1594 return Match_MissingFeature;
1595}
1596
1597namespace {
1598 struct OperandMatchEntry {
1599 uint16_t Mnemonic;
1600 uint8_t OperandMask;
1601 uint8_t Class;
1602 uint8_t RequiredFeaturesIdx;
1603
1604 StringRef getMnemonic() const {
1605 return StringRef(MnemonicTable + Mnemonic + 1,
1606 MnemonicTable[Mnemonic]);
1607 }
1608 };
1609
1610 // Predicate for searching for an opcode.
1611 struct LessOpcodeOperand {
1612 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
1613 return LHS.getMnemonic() < RHS;
1614 }
1615 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
1616 return LHS < RHS.getMnemonic();
1617 }
1618 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
1619 return LHS.getMnemonic() < RHS.getMnemonic();
1620 }
1621 };
1622} // end anonymous namespace
1623
1624static const OperandMatchEntry OperandMatchTable[2] = {
1625 /* Operand List Mnemonic, Mask, Operand Class, Features */
1626 { 304 /* ldd */, 2 /* 1 */, MCK_Memri, AMFBS_HasSRAM_HasNonTinyEncoding },
1627 { 499 /* std */, 1 /* 0 */, MCK_Memri, AMFBS_HasSRAM_HasNonTinyEncoding },
1628};
1629
1630ParseStatus AVRAsmParser::
1631tryCustomParseOperand(OperandVector &Operands,
1632 unsigned MCK) {
1633
1634 switch(MCK) {
1635 case MCK_Memri:
1636 return parseMemriOperand(Operands);
1637 default:
1638 return ParseStatus::NoMatch;
1639 }
1640 return ParseStatus::NoMatch;
1641}
1642
1643ParseStatus AVRAsmParser::
1644MatchOperandParserImpl(OperandVector &Operands,
1645 StringRef Mnemonic,
1646 bool ParseForAllFeatures) {
1647 // Get the current feature set.
1648 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1649
1650 // Get the next operand index.
1651 unsigned NextOpNum = Operands.size() - 1;
1652 // Search the table.
1653 auto MnemonicRange =
1654 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
1655 Mnemonic, LessOpcodeOperand());
1656
1657 if (MnemonicRange.first == MnemonicRange.second)
1658 return ParseStatus::NoMatch;
1659
1660 for (const OperandMatchEntry *it = MnemonicRange.first,
1661 *ie = MnemonicRange.second; it != ie; ++it) {
1662 // equal_range guarantees that instruction mnemonic matches.
1663 assert(Mnemonic == it->getMnemonic());
1664
1665 // check if the available features match
1666 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1667 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
1668 continue;
1669
1670 // check if the operand in question has a custom parser.
1671 if (!(it->OperandMask & (1 << NextOpNum)))
1672 continue;
1673
1674 // call custom parse method to handle the operand
1675 ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
1676 if (!Result.isNoMatch())
1677 return Result;
1678 }
1679
1680 // Okay, we had no match.
1681 return ParseStatus::NoMatch;
1682}
1683
1684#endif // GET_MATCHER_IMPLEMENTATION
1685
1686
1687#ifdef GET_MNEMONIC_SPELL_CHECKER
1688#undef GET_MNEMONIC_SPELL_CHECKER
1689
1690static std::string AVRMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
1691 const unsigned MaxEditDist = 2;
1692 std::vector<StringRef> Candidates;
1693 StringRef Prev = "";
1694
1695 // Find the appropriate table for this asm variant.
1696 const MatchEntry *Start, *End;
1697 switch (VariantID) {
1698 default: llvm_unreachable("invalid variant!");
1699 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1700 }
1701
1702 for (auto I = Start; I < End; I++) {
1703 // Ignore unsupported instructions.
1704 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
1705 if ((FBS & RequiredFeatures) != RequiredFeatures)
1706 continue;
1707
1708 StringRef T = I->getMnemonic();
1709 // Avoid recomputing the edit distance for the same string.
1710 if (T == Prev)
1711 continue;
1712
1713 Prev = T;
1714 unsigned Dist = S.edit_distance(T, false, MaxEditDist);
1715 if (Dist <= MaxEditDist)
1716 Candidates.push_back(T);
1717 }
1718
1719 if (Candidates.empty())
1720 return "";
1721
1722 std::string Res = ", did you mean: ";
1723 unsigned i = 0;
1724 for (; i < Candidates.size() - 1; i++)
1725 Res += Candidates[i].str() + ", ";
1726 return Res + Candidates[i].str() + "?";
1727}
1728
1729#endif // GET_MNEMONIC_SPELL_CHECKER
1730
1731
1732#ifdef GET_MNEMONIC_CHECKER
1733#undef GET_MNEMONIC_CHECKER
1734
1735static bool AVRCheckMnemonic(StringRef Mnemonic,
1736 const FeatureBitset &AvailableFeatures,
1737 unsigned VariantID) {
1738 // Find the appropriate table for this asm variant.
1739 const MatchEntry *Start, *End;
1740 switch (VariantID) {
1741 default: llvm_unreachable("invalid variant!");
1742 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1743 }
1744
1745 // Search the table.
1746 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1747
1748 if (MnemonicRange.first == MnemonicRange.second)
1749 return false;
1750
1751 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1752 it != ie; ++it) {
1753 const FeatureBitset &RequiredFeatures =
1754 FeatureBitsets[it->RequiredFeaturesIdx];
1755 if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
1756 return true;
1757 }
1758 return false;
1759}
1760
1761#endif // GET_MNEMONIC_CHECKER
1762
1763