1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* * AVR Disassembler *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#include "llvm/MC/MCInst.h"
11#include "llvm/MC/MCSubtargetInfo.h"
12#include "llvm/Support/DataTypes.h"
13#include "llvm/Support/Debug.h"
14#include "llvm/Support/LEB128.h"
15#include "llvm/Support/raw_ostream.h"
16#include "llvm/TargetParser/SubtargetFeature.h"
17#include <assert.h>
18
19namespace {
20
21// InsnBitWidth is essentially a type trait used by the decoder emitter to query
22// the supported bitwidth for a given type. But default, the value is 0, making
23// it an invalid type for use as `InsnType` when instantiating the decoder.
24// Individual targets are expected to provide specializations for these based
25// on their usage.
26template <typename T> constexpr uint32_t InsnBitWidth = 0;
27
28static const uint8_t DecoderTable16[865] = {
29 OPC_SwitchField, 14, 2, // 0: switch Inst[15:14] {
30 0, 168, 1, // 3: case 0x0: {
31 OPC_SwitchField, 12, 2, // 6: switch Inst[13:12] {
32 0, 99, // 9: case 0x0: {
33 OPC_SwitchField, 10, 2, // 11: switch Inst[11:10] {
34 0, 76, // 14: case 0x0: {
35 OPC_SwitchField, 8, 2, // 16: switch Inst[9:8] {
36 0, 8, // 19: case 0x0: {
37 OPC_CheckField, 0, 8, 0, // 21: check Inst[7:0] == 0x0
38 OPC_Decode, 226, 3, 0, // 25: decode to NOP using decoder 0
39 // 25: }
40 1, 6, // 29: case 0x1: {
41 OPC_CheckPredicate, 0, // 31: check predicate 0
42 OPC_Decode, 221, 3, 1, // 33: decode to MOVWRdRr using decoder 1
43 // 33: }
44 2, 6, // 37: case 0x2: {
45 OPC_CheckPredicate, 1, // 39: check predicate 1
46 OPC_Decode, 223, 3, 2, // 41: decode to MULSRdRr using decoder 2
47 // 41: }
48 3, 0, // 45: case 0x3: {
49 OPC_SwitchField, 3, 1, // 47: switch Inst[3] {
50 0, 19, // 50: case 0x0: {
51 OPC_SwitchField, 7, 1, // 52: switch Inst[7] {
52 0, 6, // 55: case 0x0: {
53 OPC_CheckPredicate, 1, // 57: check predicate 1
54 OPC_Decode, 224, 3, 3, // 59: decode to MULSURdRr using decoder 3
55 // 59: }
56 1, 0, // 63: case 0x1: {
57 OPC_CheckPredicate, 1, // 65: check predicate 1
58 OPC_Decode, 199, 3, 3, // 67: decode to FMULS using decoder 3
59 // 67: }
60 // 67: } // switch Inst[7]
61 // 67: }
62 1, 0, // 71: case 0x1: {
63 OPC_SwitchField, 7, 1, // 73: switch Inst[7] {
64 0, 6, // 76: case 0x0: {
65 OPC_CheckPredicate, 1, // 78: check predicate 1
66 OPC_Decode, 198, 3, 3, // 80: decode to FMUL using decoder 3
67 // 80: }
68 1, 0, // 84: case 0x1: {
69 OPC_CheckPredicate, 1, // 86: check predicate 1
70 OPC_Decode, 200, 3, 3, // 88: decode to FMULSU using decoder 3
71 // 88: }
72 // 88: } // switch Inst[7]
73 // 88: }
74 // 88: } // switch Inst[3]
75 // 88: }
76 // 88: } // switch Inst[9:8]
77 // 88: }
78 1, 4, // 92: case 0x1: {
79 OPC_Decode, 186, 3, 4, // 94: decode to CPCRdRr using decoder 4
80 // 94: }
81 2, 4, // 98: case 0x2: {
82 OPC_Decode, 238, 3, 5, // 100: decode to SBCRdRr using decoder 5
83 // 100: }
84 3, 0, // 104: case 0x3: {
85 OPC_Decode, 163, 3, 5, // 106: decode to ADDRdRr using decoder 5
86 // 106: }
87 // 106: } // switch Inst[11:10]
88 // 106: }
89 1, 27, // 110: case 0x1: {
90 OPC_SwitchField, 10, 2, // 112: switch Inst[11:10] {
91 0, 4, // 115: case 0x0: {
92 OPC_Decode, 189, 3, 4, // 117: decode to CPSE using decoder 4
93 // 117: }
94 1, 4, // 121: case 0x1: {
95 OPC_Decode, 188, 3, 4, // 123: decode to CPRdRr using decoder 4
96 // 123: }
97 2, 4, // 127: case 0x2: {
98 OPC_Decode, 255, 3, 5, // 129: decode to SUBRdRr using decoder 5
99 // 129: }
100 3, 0, // 133: case 0x3: {
101 OPC_Decode, 162, 3, 5, // 135: decode to ADCRdRr using decoder 5
102 // 135: }
103 // 135: } // switch Inst[11:10]
104 // 135: }
105 2, 27, // 139: case 0x2: {
106 OPC_SwitchField, 10, 2, // 141: switch Inst[11:10] {
107 0, 4, // 144: case 0x0: {
108 OPC_Decode, 166, 3, 5, // 146: decode to ANDRdRr using decoder 5
109 // 146: }
110 1, 4, // 150: case 0x1: {
111 OPC_Decode, 197, 3, 5, // 152: decode to EORRdRr using decoder 5
112 // 152: }
113 2, 4, // 156: case 0x2: {
114 OPC_Decode, 228, 3, 5, // 158: decode to ORRdRr using decoder 5
115 // 158: }
116 3, 0, // 162: case 0x3: {
117 OPC_Decode, 220, 3, 4, // 164: decode to MOVRdRr using decoder 4
118 // 164: }
119 // 164: } // switch Inst[11:10]
120 // 164: }
121 3, 0, // 168: case 0x3: {
122 OPC_Decode, 187, 3, 6, // 170: decode to CPIRdK using decoder 6
123 // 170: }
124 // 170: } // switch Inst[13:12]
125 // 170: }
126 1, 27, // 174: case 0x1: {
127 OPC_SwitchField, 12, 2, // 176: switch Inst[13:12] {
128 0, 4, // 179: case 0x0: {
129 OPC_Decode, 237, 3, 7, // 181: decode to SBCIRdK using decoder 7
130 // 181: }
131 1, 4, // 185: case 0x1: {
132 OPC_Decode, 254, 3, 7, // 187: decode to SUBIRdK using decoder 7
133 // 187: }
134 2, 4, // 191: case 0x2: {
135 OPC_Decode, 227, 3, 7, // 193: decode to ORIRdK using decoder 7
136 // 193: }
137 3, 0, // 197: case 0x3: {
138 OPC_Decode, 165, 3, 7, // 199: decode to ANDIRdK using decoder 7
139 // 199: }
140 // 199: } // switch Inst[13:12]
141 // 199: }
142 2, 255, 3, // 203: case 0x2: {
143 OPC_SwitchField, 12, 1, // 206: switch Inst[12] {
144 0, 125, // 209: case 0x0: {
145 OPC_SwitchField, 9, 1, // 211: switch Inst[9] {
146 0, 59, // 214: case 0x0: {
147 OPC_Scope, 51, // 216: try {
148 OPC_SwitchField, 0, 2, // 218: switch Inst[1:0] {
149 0, 14, // 221: case 0x0: {
150 OPC_CheckPredicate, 2, // 223: check predicate 2
151 OPC_CheckField, 13, 1, 0, // 225: check Inst[13] == 0x0
152 OPC_CheckField, 10, 2, 0, // 229: check Inst[11:10] == 0x0
153 OPC_Decode, 211, 3, 8, // 233: decode to LDRdPtr using decoder 8
154 // 233: }
155 1, 14, // 237: case 0x1: {
156 OPC_CheckPredicate, 2, // 239: check predicate 2
157 OPC_CheckField, 13, 1, 0, // 241: check Inst[13] == 0x0
158 OPC_CheckField, 10, 2, 0, // 245: check Inst[11:10] == 0x0
159 OPC_Decode, 213, 3, 8, // 249: decode to LDRdPtrPi using decoder 8
160 // 249: }
161 2, 0, // 253: case 0x2: {
162 OPC_CheckPredicate, 2, // 255: check predicate 2
163 OPC_CheckField, 13, 1, 0, // 257: check Inst[13] == 0x0
164 OPC_CheckField, 10, 2, 0, // 261: check Inst[11:10] == 0x0
165 OPC_Decode, 212, 3, 8, // 265: decode to LDRdPtrPd using decoder 8
166 // 265: }
167 // 265: } // switch Inst[1:0]
168 // 265: } else try {
169 OPC_CheckPredicate, 3, // 269: check predicate 3
170 OPC_Decode, 209, 3, 9, // 271: decode to LDDRdPtrQ using decoder 9
171 // 271: }
172 // 271: }
173 1, 0, // 275: case 0x1: {
174 OPC_Scope, 51, // 277: try {
175 OPC_SwitchField, 0, 2, // 279: switch Inst[1:0] {
176 0, 14, // 282: case 0x0: {
177 OPC_CheckPredicate, 2, // 284: check predicate 2
178 OPC_CheckField, 13, 1, 0, // 286: check Inst[13] == 0x0
179 OPC_CheckField, 10, 2, 0, // 290: check Inst[11:10] == 0x0
180 OPC_Decode, 251, 3, 8, // 294: decode to STPtrRr using decoder 8
181 // 294: }
182 1, 14, // 298: case 0x1: {
183 OPC_CheckPredicate, 2, // 300: check predicate 2
184 OPC_CheckField, 13, 1, 0, // 302: check Inst[13] == 0x0
185 OPC_CheckField, 10, 2, 0, // 306: check Inst[11:10] == 0x0
186 OPC_Decode, 250, 3, 8, // 310: decode to STPtrPiRr using decoder 8
187 // 310: }
188 2, 0, // 314: case 0x2: {
189 OPC_CheckPredicate, 2, // 316: check predicate 2
190 OPC_CheckField, 13, 1, 0, // 318: check Inst[13] == 0x0
191 OPC_CheckField, 10, 2, 0, // 322: check Inst[11:10] == 0x0
192 OPC_Decode, 249, 3, 8, // 326: decode to STPtrPdRr using decoder 8
193 // 326: }
194 // 326: } // switch Inst[1:0]
195 // 326: } else try {
196 OPC_CheckPredicate, 3, // 330: check predicate 3
197 OPC_Decode, 248, 3, 10, // 332: decode to STDPtrQRr using decoder 10
198 // 332: }
199 // 332: }
200 // 332: } // switch Inst[9]
201 // 332: }
202 1, 0, // 336: case 0x1: {
203 OPC_SwitchField, 11, 1, // 338: switch Inst[11] {
204 0, 192, 2, // 341: case 0x0: {
205 OPC_SwitchField, 13, 1, // 344: switch Inst[13] {
206 0, 180, 2, // 347: case 0x0: {
207 OPC_SwitchField, 9, 2, // 350: switch Inst[10:9] {
208 0, 43, // 353: case 0x0: {
209 OPC_SwitchField, 0, 4, // 355: switch Inst[3:0] {
210 4, 6, // 358: case 0x4: {
211 OPC_CheckPredicate, 4, // 360: check predicate 4
212 OPC_Decode, 217, 3, 11, // 362: decode to LPMRdZ using decoder 11
213 // 362: }
214 5, 6, // 366: case 0x5: {
215 OPC_CheckPredicate, 4, // 368: check predicate 4
216 OPC_Decode, 218, 3, 11, // 370: decode to LPMRdZPi using decoder 11
217 // 370: }
218 6, 6, // 374: case 0x6: {
219 OPC_CheckPredicate, 5, // 376: check predicate 5
220 OPC_Decode, 195, 3, 11, // 378: decode to ELPMRdZ using decoder 11
221 // 378: }
222 7, 6, // 382: case 0x7: {
223 OPC_CheckPredicate, 5, // 384: check predicate 5
224 OPC_Decode, 196, 3, 11, // 386: decode to ELPMRdZPi using decoder 11
225 // 386: }
226 15, 0, // 390: case 0xf: {
227 OPC_CheckPredicate, 2, // 392: check predicate 2
228 OPC_Decode, 230, 3, 12, // 394: decode to POPRd using decoder 12
229 // 394: }
230 // 394: } // switch Inst[3:0]
231 // 394: }
232 1, 43, // 398: case 0x1: {
233 OPC_SwitchField, 0, 4, // 400: switch Inst[3:0] {
234 4, 6, // 403: case 0x4: {
235 OPC_CheckPredicate, 6, // 405: check predicate 6
236 OPC_Decode, 130, 4, 11, // 407: decode to XCHZRd using decoder 11
237 // 407: }
238 5, 6, // 411: case 0x5: {
239 OPC_CheckPredicate, 6, // 413: check predicate 6
240 OPC_Decode, 207, 3, 11, // 415: decode to LASZRd using decoder 11
241 // 415: }
242 6, 6, // 419: case 0x6: {
243 OPC_CheckPredicate, 6, // 421: check predicate 6
244 OPC_Decode, 206, 3, 11, // 423: decode to LACZRd using decoder 11
245 // 423: }
246 7, 6, // 427: case 0x7: {
247 OPC_CheckPredicate, 6, // 429: check predicate 6
248 OPC_Decode, 208, 3, 11, // 431: decode to LATZRd using decoder 11
249 // 431: }
250 15, 0, // 435: case 0xf: {
251 OPC_CheckPredicate, 2, // 437: check predicate 2
252 OPC_Decode, 231, 3, 12, // 439: decode to PUSHRr using decoder 12
253 // 439: }
254 // 439: } // switch Inst[3:0]
255 // 439: }
256 2, 191, 1, // 443: case 0x2: {
257 OPC_SwitchField, 0, 4, // 446: switch Inst[3:0] {
258 0, 4, // 449: case 0x0: {
259 OPC_Decode, 185, 3, 13, // 451: decode to COMRd using decoder 13
260 // 451: }
261 1, 4, // 455: case 0x1: {
262 OPC_Decode, 225, 3, 13, // 457: decode to NEGRd using decoder 13
263 // 457: }
264 2, 4, // 461: case 0x2: {
265 OPC_Decode, 128, 4, 13, // 463: decode to SWAPRd using decoder 13
266 // 463: }
267 3, 4, // 467: case 0x3: {
268 OPC_Decode, 203, 3, 13, // 469: decode to INCRd using decoder 13
269 // 469: }
270 5, 4, // 473: case 0x5: {
271 OPC_Decode, 167, 3, 13, // 475: decode to ASRRd using decoder 13
272 // 475: }
273 6, 4, // 479: case 0x6: {
274 OPC_Decode, 219, 3, 13, // 481: decode to LSRRd using decoder 13
275 // 481: }
276 7, 4, // 485: case 0x7: {
277 OPC_Decode, 236, 3, 13, // 487: decode to RORRd using decoder 13
278 // 487: }
279 8, 89, // 491: case 0x8: {
280 OPC_SwitchField, 7, 2, // 493: switch Inst[8:7] {
281 0, 4, // 496: case 0x0: {
282 OPC_Decode, 181, 3, 14, // 498: decode to BSETs using decoder 14
283 // 498: }
284 1, 4, // 502: case 0x1: {
285 OPC_Decode, 168, 3, 14, // 504: decode to BCLRs using decoder 14
286 // 504: }
287 2, 15, // 508: case 0x2: {
288 OPC_SwitchField, 4, 3, // 510: switch Inst[6:4] {
289 0, 4, // 513: case 0x0: {
290 OPC_Decode, 233, 3, 0, // 515: decode to RET using decoder 0
291 // 515: }
292 1, 0, // 519: case 0x1: {
293 OPC_Decode, 234, 3, 0, // 521: decode to RETI using decoder 0
294 // 521: }
295 // 521: } // switch Inst[6:4]
296 // 521: }
297 3, 0, // 525: case 0x3: {
298 OPC_SwitchField, 4, 3, // 527: switch Inst[6:4] {
299 0, 4, // 530: case 0x0: {
300 OPC_Decode, 245, 3, 0, // 532: decode to SLEEP using decoder 0
301 // 532: }
302 1, 6, // 536: case 0x1: {
303 OPC_CheckPredicate, 7, // 538: check predicate 7
304 OPC_Decode, 172, 3, 0, // 540: decode to BREAK using decoder 0
305 // 540: }
306 2, 4, // 544: case 0x2: {
307 OPC_Decode, 129, 4, 0, // 546: decode to WDR using decoder 0
308 // 546: }
309 4, 6, // 550: case 0x4: {
310 OPC_CheckPredicate, 8, // 552: check predicate 8
311 OPC_Decode, 216, 3, 0, // 554: decode to LPM using decoder 0
312 // 554: }
313 5, 6, // 558: case 0x5: {
314 OPC_CheckPredicate, 9, // 560: check predicate 9
315 OPC_Decode, 194, 3, 0, // 562: decode to ELPM using decoder 0
316 // 562: }
317 6, 6, // 566: case 0x6: {
318 OPC_CheckPredicate, 10, // 568: check predicate 10
319 OPC_Decode, 246, 3, 0, // 570: decode to SPM using decoder 0
320 // 570: }
321 7, 0, // 574: case 0x7: {
322 OPC_CheckPredicate, 11, // 576: check predicate 11
323 OPC_Decode, 247, 3, 15, // 578: decode to SPMZPi using decoder 15
324 // 578: }
325 // 578: } // switch Inst[6:4]
326 // 578: }
327 // 578: } // switch Inst[8:7]
328 // 578: }
329 9, 35, // 582: case 0x9: {
330 OPC_SwitchField, 4, 5, // 584: switch Inst[8:4] {
331 0, 6, // 587: case 0x0: {
332 OPC_CheckPredicate, 12, // 589: check predicate 12
333 OPC_Decode, 202, 3, 0, // 591: decode to IJMP using decoder 0
334 // 591: }
335 1, 6, // 595: case 0x1: {
336 OPC_CheckPredicate, 13, // 597: check predicate 13
337 OPC_Decode, 193, 3, 0, // 599: decode to EIJMP using decoder 0
338 // 599: }
339 16, 6, // 603: case 0x10: {
340 OPC_CheckPredicate, 12, // 605: check predicate 12
341 OPC_Decode, 201, 3, 0, // 607: decode to ICALL using decoder 0
342 // 607: }
343 17, 0, // 611: case 0x11: {
344 OPC_CheckPredicate, 13, // 613: check predicate 13
345 OPC_Decode, 192, 3, 0, // 615: decode to EICALL using decoder 0
346 // 615: }
347 // 615: } // switch Inst[8:4]
348 // 615: }
349 10, 4, // 619: case 0xa: {
350 OPC_Decode, 190, 3, 13, // 621: decode to DECRd using decoder 13
351 // 621: }
352 11, 0, // 625: case 0xb: {
353 OPC_CheckPredicate, 14, // 627: check predicate 14
354 OPC_CheckField, 8, 1, 0, // 629: check Inst[8] == 0x0
355 OPC_Decode, 191, 3, 16, // 633: decode to DESK using decoder 16
356 // 633: }
357 // 633: } // switch Inst[3:0]
358 // 633: }
359 3, 0, // 637: case 0x3: {
360 OPC_SwitchField, 8, 1, // 639: switch Inst[8] {
361 0, 6, // 642: case 0x0: {
362 OPC_CheckPredicate, 15, // 644: check predicate 15
363 OPC_Decode, 164, 3, 17, // 646: decode to ADIWRdK using decoder 17
364 // 646: }
365 1, 0, // 650: case 0x1: {
366 OPC_CheckPredicate, 15, // 652: check predicate 15
367 OPC_Decode, 242, 3, 17, // 654: decode to SBIWRdK using decoder 17
368 // 654: }
369 // 654: } // switch Inst[8]
370 // 654: }
371 // 654: } // switch Inst[10:9]
372 // 654: }
373 1, 0, // 658: case 0x1: {
374 OPC_Decode, 204, 3, 18, // 660: decode to INRdA using decoder 18
375 // 660: }
376 // 660: } // switch Inst[13]
377 // 660: }
378 1, 0, // 664: case 0x1: {
379 OPC_SwitchField, 13, 1, // 666: switch Inst[13] {
380 0, 40, // 669: case 0x0: {
381 OPC_SwitchField, 10, 1, // 671: switch Inst[10] {
382 0, 27, // 674: case 0x0: {
383 OPC_SwitchField, 8, 2, // 676: switch Inst[9:8] {
384 0, 4, // 679: case 0x0: {
385 OPC_Decode, 184, 3, 19, // 681: decode to CBIAb using decoder 19
386 // 681: }
387 1, 4, // 685: case 0x1: {
388 OPC_Decode, 240, 3, 19, // 687: decode to SBICAb using decoder 19
389 // 687: }
390 2, 4, // 691: case 0x2: {
391 OPC_Decode, 239, 3, 19, // 693: decode to SBIAb using decoder 19
392 // 693: }
393 3, 0, // 697: case 0x3: {
394 OPC_Decode, 241, 3, 19, // 699: decode to SBISAb using decoder 19
395 // 699: }
396 // 699: } // switch Inst[9:8]
397 // 699: }
398 1, 0, // 703: case 0x1: {
399 OPC_CheckPredicate, 1, // 705: check predicate 1
400 OPC_Decode, 222, 3, 4, // 707: decode to MULRdRr using decoder 4
401 // 707: }
402 // 707: } // switch Inst[10]
403 // 707: }
404 1, 0, // 711: case 0x1: {
405 OPC_Decode, 229, 3, 20, // 713: decode to OUTARr using decoder 20
406 // 713: }
407 // 713: } // switch Inst[13]
408 // 713: }
409 // 713: } // switch Inst[11]
410 // 713: }
411 // 713: } // switch Inst[12]
412 // 713: }
413 3, 0, // 717: case 0x3: {
414 OPC_SwitchField, 12, 2, // 719: switch Inst[13:12] {
415 0, 4, // 722: case 0x0: {
416 OPC_Decode, 235, 3, 21, // 724: decode to RJMPk using decoder 21
417 // 724: }
418 1, 4, // 728: case 0x1: {
419 OPC_Decode, 232, 3, 21, // 730: decode to RCALLk using decoder 21
420 // 730: }
421 2, 4, // 734: case 0x2: {
422 OPC_Decode, 210, 3, 6, // 736: decode to LDIRdK using decoder 6
423 // 736: }
424 3, 0, // 740: case 0x3: {
425 OPC_SwitchField, 10, 2, // 742: switch Inst[11:10] {
426 0, 33, // 745: case 0x0: {
427 OPC_Scope, 27, // 747: try {
428 OPC_SwitchField, 0, 3, // 749: switch Inst[2:0] {
429 0, 4, // 752: case 0x0: {
430 OPC_Decode, 175, 3, 22, // 754: decode to BRLOk using decoder 22
431 // 754: }
432 1, 4, // 758: case 0x1: {
433 OPC_Decode, 173, 3, 22, // 760: decode to BREQk using decoder 22
434 // 760: }
435 2, 4, // 764: case 0x2: {
436 OPC_Decode, 177, 3, 22, // 766: decode to BRMIk using decoder 22
437 // 766: }
438 4, 0, // 770: case 0x4: {
439 OPC_Decode, 176, 3, 22, // 772: decode to BRLTk using decoder 22
440 // 772: }
441 // 772: } // switch Inst[2:0]
442 // 772: } else try {
443 OPC_Decode, 171, 3, 23, // 776: decode to BRBSsk using decoder 23
444 // 776: }
445 // 776: }
446 1, 33, // 780: case 0x1: {
447 OPC_Scope, 27, // 782: try {
448 OPC_SwitchField, 0, 3, // 784: switch Inst[2:0] {
449 0, 4, // 787: case 0x0: {
450 OPC_Decode, 180, 3, 22, // 789: decode to BRSHk using decoder 22
451 // 789: }
452 1, 4, // 793: case 0x1: {
453 OPC_Decode, 178, 3, 22, // 795: decode to BRNEk using decoder 22
454 // 795: }
455 2, 4, // 799: case 0x2: {
456 OPC_Decode, 179, 3, 22, // 801: decode to BRPLk using decoder 22
457 // 801: }
458 4, 0, // 805: case 0x4: {
459 OPC_Decode, 174, 3, 22, // 807: decode to BRGEk using decoder 22
460 // 807: }
461 // 807: } // switch Inst[2:0]
462 // 807: } else try {
463 OPC_Decode, 170, 3, 23, // 811: decode to BRBCsk using decoder 23
464 // 811: }
465 // 811: }
466 2, 23, // 815: case 0x2: {
467 OPC_SwitchField, 9, 1, // 817: switch Inst[9] {
468 0, 8, // 820: case 0x0: {
469 OPC_CheckField, 3, 1, 0, // 822: check Inst[3] == 0x0
470 OPC_Decode, 169, 3, 24, // 826: decode to BLD using decoder 24
471 // 826: }
472 1, 0, // 830: case 0x1: {
473 OPC_CheckField, 3, 1, 0, // 832: check Inst[3] == 0x0
474 OPC_Decode, 182, 3, 25, // 836: decode to BST using decoder 25
475 // 836: }
476 // 836: } // switch Inst[9]
477 // 836: }
478 3, 0, // 840: case 0x3: {
479 OPC_SwitchField, 9, 1, // 842: switch Inst[9] {
480 0, 8, // 845: case 0x0: {
481 OPC_CheckField, 3, 1, 0, // 847: check Inst[3] == 0x0
482 OPC_Decode, 243, 3, 25, // 851: decode to SBRCRrB using decoder 25
483 // 851: }
484 1, 0, // 855: case 0x1: {
485 OPC_CheckField, 3, 1, 0, // 857: check Inst[3] == 0x0
486 OPC_Decode, 244, 3, 25, // 861: decode to SBRSRrB using decoder 25
487 // 861: }
488 // 861: } // switch Inst[9]
489 // 861: }
490 // 861: } // switch Inst[11:10]
491 // 861: }
492 // 861: } // switch Inst[13:12]
493 // 861: }
494 // 861: } // switch Inst[15:14]
495};
496static const uint8_t DecoderTableAVRTiny16[19] = {
497 OPC_SwitchField, 11, 5, // 0: switch Inst[15:11] {
498 20, 6, // 3: case 0x14: {
499 OPC_CheckPredicate, 16, // 5: check predicate 16
500 OPC_Decode, 215, 3, 26, // 7: decode to LDSRdKTiny using decoder 26
501 // 7: }
502 21, 0, // 11: case 0x15: {
503 OPC_CheckPredicate, 16, // 13: check predicate 16
504 OPC_Decode, 253, 3, 27, // 15: decode to STSKRrTiny using decoder 27
505 // 15: }
506 // 15: } // switch Inst[15:11]
507};
508static const uint8_t DecoderTable32[56] = {
509 OPC_SwitchField, 17, 3, // 0: switch Inst[19:17] {
510 0, 27, // 3: case 0x0: {
511 OPC_SwitchField, 25, 7, // 5: switch Inst[31:25] {
512 72, 10, // 8: case 0x48: {
513 OPC_CheckPredicate, 3, // 10: check predicate 3
514 OPC_CheckField, 16, 1, 0, // 12: check Inst[16] == 0x0
515 OPC_Decode, 214, 3, 28, // 16: decode to LDSRdK using decoder 28
516 // 16: }
517 73, 0, // 20: case 0x49: {
518 OPC_CheckPredicate, 3, // 22: check predicate 3
519 OPC_CheckField, 16, 1, 0, // 24: check Inst[16] == 0x0
520 OPC_Decode, 252, 3, 29, // 28: decode to STSKRr using decoder 29
521 // 28: }
522 // 28: } // switch Inst[31:25]
523 // 28: }
524 6, 10, // 32: case 0x6: {
525 OPC_CheckPredicate, 17, // 34: check predicate 17
526 OPC_CheckField, 25, 7, 74, // 36: check Inst[31:25] == 0x4a
527 OPC_Decode, 205, 3, 30, // 40: decode to JMPk using decoder 30
528 // 40: }
529 7, 0, // 44: case 0x7: {
530 OPC_CheckPredicate, 17, // 46: check predicate 17
531 OPC_CheckField, 25, 7, 74, // 48: check Inst[31:25] == 0x4a
532 OPC_Decode, 183, 3, 30, // 52: decode to CALLk using decoder 30
533 // 52: }
534 // 52: } // switch Inst[19:17]
535};
536// Handling 31 cases.
537template <typename InsnType>
538static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) {
539 DecodeComplete = true;
540 using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>;
541 TmpType tmp;
542 switch (Idx) {
543 default: llvm_unreachable("Invalid decoder index!");
544 case 0:
545 return S;
546 case 1:
547 tmp = fieldFromInstruction(insn, 4, 4);
548 if (!Check(S, DecodeDREGSRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
549 tmp = fieldFromInstruction(insn, 0, 4);
550 if (!Check(S, DecodeDREGSRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
551 return S;
552 case 2:
553 tmp = fieldFromInstruction(insn, 4, 4);
554 if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
555 tmp = fieldFromInstruction(insn, 0, 4);
556 if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
557 return S;
558 case 3:
559 tmp = fieldFromInstruction(insn, 4, 3);
560 if (!Check(S, DecodeLD8loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
561 tmp = fieldFromInstruction(insn, 0, 3);
562 if (!Check(S, DecodeLD8loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
563 return S;
564 case 4:
565 tmp = fieldFromInstruction(insn, 4, 5);
566 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
567 tmp = 0x0;
568 tmp |= fieldFromInstruction(insn, 0, 4);
569 tmp |= fieldFromInstruction(insn, 9, 1) << 4;
570 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
571 return S;
572 case 5:
573 tmp = fieldFromInstruction(insn, 4, 5);
574 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
575 tmp = fieldFromInstruction(insn, 4, 5);
576 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
577 tmp = 0x0;
578 tmp |= fieldFromInstruction(insn, 0, 4);
579 tmp |= fieldFromInstruction(insn, 9, 1) << 4;
580 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
581 return S;
582 case 6:
583 tmp = fieldFromInstruction(insn, 4, 4);
584 if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
585 tmp = 0x0;
586 tmp |= fieldFromInstruction(insn, 0, 4);
587 tmp |= fieldFromInstruction(insn, 8, 4) << 4;
588 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
589 return S;
590 case 7:
591 tmp = fieldFromInstruction(insn, 4, 4);
592 if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
593 tmp = fieldFromInstruction(insn, 4, 4);
594 if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
595 tmp = 0x0;
596 tmp |= fieldFromInstruction(insn, 0, 4);
597 tmp |= fieldFromInstruction(insn, 8, 4) << 4;
598 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
599 return S;
600 case 8:
601 if (!Check(S, decodeLoadStore(MI, insn, Address, Decoder))) { return MCDisassembler::Fail; }
602 return S;
603 case 9:
604 tmp = fieldFromInstruction(insn, 4, 5);
605 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
606 tmp = 0x0;
607 tmp |= fieldFromInstruction(insn, 0, 3);
608 tmp |= fieldFromInstruction(insn, 3, 1) << 6;
609 tmp |= fieldFromInstruction(insn, 10, 2) << 3;
610 tmp |= fieldFromInstruction(insn, 13, 1) << 5;
611 if (!Check(S, decodeMemri(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
612 return S;
613 case 10:
614 tmp = 0x0;
615 tmp |= fieldFromInstruction(insn, 0, 3);
616 tmp |= fieldFromInstruction(insn, 3, 1) << 6;
617 tmp |= fieldFromInstruction(insn, 10, 2) << 3;
618 tmp |= fieldFromInstruction(insn, 13, 1) << 5;
619 if (!Check(S, decodeMemri(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
620 tmp = fieldFromInstruction(insn, 4, 5);
621 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
622 return S;
623 case 11:
624 tmp = fieldFromInstruction(insn, 4, 5);
625 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
626 if (!Check(Out&: S, In: DecodeZREGRegisterClass(Inst&: MI, Decoder)))
627 return MCDisassembler::Fail;
628 return S;
629 case 12:
630 tmp = fieldFromInstruction(insn, 4, 5);
631 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
632 return S;
633 case 13:
634 tmp = fieldFromInstruction(insn, 4, 5);
635 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
636 tmp = fieldFromInstruction(insn, 4, 5);
637 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
638 return S;
639 case 14:
640 tmp = fieldFromInstruction(insn, 4, 3);
641 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
642 return S;
643 case 15:
644 if (!Check(Out&: S, In: DecodeZREGRegisterClass(Inst&: MI, Decoder)))
645 return MCDisassembler::Fail;
646 return S;
647 case 16:
648 tmp = fieldFromInstruction(insn, 4, 4);
649 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
650 return S;
651 case 17:
652 tmp = fieldFromInstruction(insn, 4, 2);
653 if (!Check(S, DecodeIWREGSRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
654 tmp = fieldFromInstruction(insn, 4, 2);
655 if (!Check(S, DecodeIWREGSRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
656 tmp = 0x0;
657 tmp |= fieldFromInstruction(insn, 0, 4);
658 tmp |= fieldFromInstruction(insn, 6, 2) << 4;
659 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
660 return S;
661 case 18:
662 tmp = fieldFromInstruction(insn, 4, 5);
663 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
664 tmp = 0x0;
665 tmp |= fieldFromInstruction(insn, 0, 4);
666 tmp |= fieldFromInstruction(insn, 9, 2) << 4;
667 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
668 return S;
669 case 19:
670 tmp = fieldFromInstruction(insn, 3, 5);
671 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
672 tmp = fieldFromInstruction(insn, 0, 3);
673 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
674 return S;
675 case 20:
676 tmp = 0x0;
677 tmp |= fieldFromInstruction(insn, 0, 4);
678 tmp |= fieldFromInstruction(insn, 9, 2) << 4;
679 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
680 tmp = fieldFromInstruction(insn, 4, 5);
681 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
682 return S;
683 case 21:
684 tmp = fieldFromInstruction(insn, 0, 12);
685 if (!Check(S, decodeRelCondBrTarget13(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
686 return S;
687 case 22:
688 tmp = fieldFromInstruction(insn, 3, 7);
689 if (!Check(S, decodeRelCondBrTarget7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
690 return S;
691 case 23:
692 tmp = fieldFromInstruction(insn, 0, 3);
693 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
694 tmp = fieldFromInstruction(insn, 3, 7);
695 if (!Check(S, decodeRelCondBrTarget7(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
696 return S;
697 case 24:
698 tmp = fieldFromInstruction(insn, 4, 5);
699 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
700 tmp = fieldFromInstruction(insn, 4, 5);
701 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
702 tmp = fieldFromInstruction(insn, 0, 3);
703 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
704 return S;
705 case 25:
706 tmp = fieldFromInstruction(insn, 4, 5);
707 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
708 tmp = fieldFromInstruction(insn, 0, 3);
709 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
710 return S;
711 case 26:
712 tmp = fieldFromInstruction(insn, 4, 4);
713 if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
714 tmp = 0x0;
715 tmp |= fieldFromInstruction(insn, 0, 4);
716 tmp |= fieldFromInstruction(insn, 8, 3) << 4;
717 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
718 return S;
719 case 27:
720 tmp = 0x0;
721 tmp |= fieldFromInstruction(insn, 0, 4);
722 tmp |= fieldFromInstruction(insn, 8, 3) << 4;
723 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
724 tmp = fieldFromInstruction(insn, 4, 4);
725 if (!Check(S, DecodeLD8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
726 return S;
727 case 28:
728 tmp = fieldFromInstruction(insn, 20, 5);
729 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
730 tmp = fieldFromInstruction(insn, 0, 16);
731 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
732 return S;
733 case 29:
734 tmp = fieldFromInstruction(insn, 0, 16);
735 MI.addOperand(Op: MCOperand::createImm(Val: tmp));
736 tmp = fieldFromInstruction(insn, 20, 5);
737 if (!Check(S, DecodeGPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
738 return S;
739 case 30:
740 tmp = 0x0;
741 tmp |= fieldFromInstruction(insn, 0, 17);
742 tmp |= fieldFromInstruction(insn, 20, 5) << 17;
743 if (!Check(S, decodeCallTarget(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
744 return S;
745 }
746}
747static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset &FB) {
748 switch (Idx) {
749 default: llvm_unreachable("Invalid index!");
750 case 0:
751 return FB[AVR::FeatureMOVW];
752 case 1:
753 return FB[AVR::FeatureMultiplication];
754 case 2:
755 return FB[AVR::FeatureSRAM];
756 case 3:
757 return FB[AVR::FeatureSRAM] && !FB[AVR::FeatureTinyEncoding];
758 case 4:
759 return FB[AVR::FeatureLPMX];
760 case 5:
761 return FB[AVR::FeatureELPMX];
762 case 6:
763 return FB[AVR::FeatureRMW];
764 case 7:
765 return FB[AVR::FeatureBREAK];
766 case 8:
767 return FB[AVR::FeatureLPM];
768 case 9:
769 return FB[AVR::FeatureELPM];
770 case 10:
771 return FB[AVR::FeatureSPM];
772 case 11:
773 return FB[AVR::FeatureSPMX];
774 case 12:
775 return FB[AVR::FeatureIJMPCALL];
776 case 13:
777 return FB[AVR::FeatureEIJMPCALL];
778 case 14:
779 return FB[AVR::FeatureDES];
780 case 15:
781 return FB[AVR::FeatureADDSUBIW];
782 case 16:
783 return FB[AVR::FeatureSRAM] && FB[AVR::FeatureTinyEncoding];
784 case 17:
785 return FB[AVR::FeatureJMPCALL];
786 }
787}
788
789
790template <typename InsnType>
791static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
792 InsnType insn, uint64_t Address,
793 const MCDisassembler *DisAsm,
794 const MCSubtargetInfo &STI) {
795 const FeatureBitset &Bits = STI.getFeatureBits();
796 const uint8_t *Ptr = DecodeTable;
797
798 SmallVector<const uint8_t *, 8> ScopeStack;
799 DecodeStatus S = MCDisassembler::Success;
800 while (true) {
801 ptrdiff_t Loc = Ptr - DecodeTable;
802 const uint8_t DecoderOp = *Ptr++;
803 switch (DecoderOp) {
804 default:
805 errs() << Loc << ": Unexpected decode table opcode: "
806 << (int)DecoderOp << '\n';
807 return MCDisassembler::Fail;
808 case OPC_Scope: {
809 unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr);
810 const uint8_t *SkipTo = Ptr + NumToSkip;
811 ScopeStack.push_back(Elt: SkipTo);
812 LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable
813 << ")\n");
814 continue;
815 }
816 case OPC_SwitchField: {
817 // Decode the start value.
818 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
819 unsigned Len = *Ptr++;
820 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
821 uint64_t CaseValue;
822 unsigned CaseSize;
823 while (true) {
824 CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr);
825 CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr);
826 if (FieldValue == CaseValue || !CaseSize)
827 break;
828 Ptr += CaseSize;
829 }
830 if (FieldValue == CaseValue) {
831 LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len
832 << "): " << FieldValue << '\n');
833 continue;
834 }
835 break;
836 }
837 case OPC_CheckField: {
838 // Decode the start value.
839 unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr);
840 unsigned Len = *Ptr;
841 uint64_t FieldValue = fieldFromInstruction(insn, Start, Len);
842 // Decode the field value.
843 unsigned PtrLen = 0;
844 uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen);
845 Ptr += PtrLen;
846 bool Failed = ExpectedValue != FieldValue;
847
848 LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len
849 << ", " << ExpectedValue << "): FieldValue = "
850 << FieldValue << ", ExpectedValue = " << ExpectedValue
851 << ": " << (Failed ? "FAIL, " : "PASS\n"););
852 if (!Failed)
853 continue;
854 break;
855 }
856 case OPC_CheckPredicate: {
857 // Decode the Predicate Index value.
858 unsigned PIdx = decodeULEB128AndIncUnsafe(p&: Ptr);
859 // Check the predicate.
860 bool Failed = !checkDecoderPredicate(Idx: PIdx, FB: Bits);
861
862 LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate(" << PIdx << "): "
863 << (Failed ? "FAIL, " : "PASS\n"););
864 if (!Failed)
865 continue;
866 break;
867 }
868 case OPC_Decode: {
869 // Decode the Opcode value.
870 unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr);
871 unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr);
872
873 MI.clear();
874 MI.setOpcode(Opc);
875 bool DecodeComplete;
876 S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm,
877 DecodeComplete);
878 LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
879 << ", using decoder " << DecodeIdx << ": "
880 << (S ? "PASS, " : "FAIL, "));
881
882 if (DecodeComplete) {
883 LLVM_DEBUG(dbgs() << "decoding complete\n");
884 return S;
885 }
886 assert(S == MCDisassembler::Fail);
887 // Reset decode status. This also drops a SoftFail status that could be
888 // set before the decode attempt.
889 S = MCDisassembler::Success;
890 break;
891 }
892 }
893 if (ScopeStack.empty()) {
894 LLVM_DEBUG(dbgs() << "returning Fail\n");
895 return MCDisassembler::Fail;
896 }
897 Ptr = ScopeStack.pop_back_val();
898 LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n');
899 }
900 llvm_unreachable("bogosity detected in disassembler state machine!");
901}
902
903
904} // namespace
905