1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass AVRMCRegisterClasses[];
13
14namespace AVR {
15
16enum : unsigned {
17 NoRegister,
18 SP = 1,
19 SPH = 2,
20 SPL = 3,
21 SREG = 4,
22 R0 = 5,
23 R1 = 6,
24 R2 = 7,
25 R3 = 8,
26 R4 = 9,
27 R5 = 10,
28 R6 = 11,
29 R7 = 12,
30 R8 = 13,
31 R9 = 14,
32 R10 = 15,
33 R11 = 16,
34 R12 = 17,
35 R13 = 18,
36 R14 = 19,
37 R15 = 20,
38 R16 = 21,
39 R17 = 22,
40 R18 = 23,
41 R19 = 24,
42 R20 = 25,
43 R21 = 26,
44 R22 = 27,
45 R23 = 28,
46 R24 = 29,
47 R25 = 30,
48 R26 = 31,
49 R27 = 32,
50 R28 = 33,
51 R29 = 34,
52 R30 = 35,
53 R31 = 36,
54 R1R0 = 37,
55 R3R2 = 38,
56 R5R4 = 39,
57 R7R6 = 40,
58 R9R8 = 41,
59 R10R9 = 42,
60 R11R10 = 43,
61 R12R11 = 44,
62 R13R12 = 45,
63 R14R13 = 46,
64 R15R14 = 47,
65 R16R15 = 48,
66 R17R16 = 49,
67 R18R17 = 50,
68 R19R18 = 51,
69 R20R19 = 52,
70 R21R20 = 53,
71 R22R21 = 54,
72 R23R22 = 55,
73 R24R23 = 56,
74 R25R24 = 57,
75 R26R25 = 58,
76 R27R26 = 59,
77 R29R28 = 60,
78 R31R30 = 61,
79 NUM_TARGET_REGS // 62
80};
81
82} // namespace AVR
83
84// Register classes
85
86namespace AVR {
87
88enum {
89 GPR8RegClassID = 0,
90 GPR8NOZRegClassID = 1,
91 GPR8loRegClassID = 2,
92 LD8RegClassID = 3,
93 GPR8NOZ_and_LD8RegClassID = 4,
94 LD8loRegClassID = 5,
95 CCRRegClassID = 6,
96 DREGSRegClassID = 7,
97 DREGSNOZRegClassID = 8,
98 DREGSMOVWRegClassID = 9,
99 DREGSMOVW_and_DREGSNOZRegClassID = 10,
100 DREGS_with_sub_hi_in_LD8RegClassID = 11,
101 DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID = 12,
102 DREGS_with_sub_lo_in_LD8RegClassID = 13,
103 DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID = 14,
104 DREGS_with_sub_lo_in_GPR8loRegClassID = 15,
105 DREGS_with_sub_hi_in_GPR8loRegClassID = 16,
106 DLDREGSRegClassID = 17,
107 DREGS_with_sub_hi_in_LD8loRegClassID = 18,
108 DREGS_with_sub_lo_in_LD8loRegClassID = 19,
109 DREGSloRegClassID = 20,
110 DLDREGS_and_DREGSNOZRegClassID = 21,
111 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID = 22,
112 DREGSLD8loRegClassID = 23,
113 IWREGSRegClassID = 24,
114 DREGSNOZ_and_IWREGSRegClassID = 25,
115 PTRREGSRegClassID = 26,
116 DREGSNOZ_and_PTRREGSRegClassID = 27,
117 PTRDISPREGSRegClassID = 28,
118 DREGSNOZ_and_PTRDISPREGSRegClassID = 29,
119 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID = 30,
120 GPRSPRegClassID = 31,
121 ZREGRegClassID = 32,
122
123};
124
125} // namespace AVR
126
127// Register alternate name indices
128
129namespace AVR {
130
131enum {
132 NoRegAltName, // 0
133 ptr, // 1
134 NUM_TARGET_REG_ALT_NAMES = 2
135};
136
137} // namespace AVR
138
139// Subregister indices
140
141namespace AVR {
142
143enum : uint16_t {
144 NoSubRegister,
145 sub_hi, // 1
146 sub_lo, // 2
147 NUM_TARGET_SUBREGS
148};
149
150} // namespace AVR
151// Register pressure sets enum.
152namespace AVR {
153
154enum RegisterPressureSets {
155 CCR = 0,
156 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo = 1,
157 GPRSP = 2,
158 IWREGS = 3,
159 LD8lo = 4,
160 LD8 = 5,
161 GPR8lo = 6,
162 GPR8lo_with_LD8lo = 7,
163 GPR8 = 8,
164};
165
166} // namespace AVR
167
168} // namespace llvm
169