1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11class MCRegisterClass;
12extern const MCRegisterClass AVRMCRegisterClasses[];
13
14namespace AVR {
15enum : unsigned {
16 NoRegister,
17 SP = 1,
18 SPH = 2,
19 SPL = 3,
20 SREG = 4,
21 R0 = 5,
22 R1 = 6,
23 R2 = 7,
24 R3 = 8,
25 R4 = 9,
26 R5 = 10,
27 R6 = 11,
28 R7 = 12,
29 R8 = 13,
30 R9 = 14,
31 R10 = 15,
32 R11 = 16,
33 R12 = 17,
34 R13 = 18,
35 R14 = 19,
36 R15 = 20,
37 R16 = 21,
38 R17 = 22,
39 R18 = 23,
40 R19 = 24,
41 R20 = 25,
42 R21 = 26,
43 R22 = 27,
44 R23 = 28,
45 R24 = 29,
46 R25 = 30,
47 R26 = 31,
48 R27 = 32,
49 R28 = 33,
50 R29 = 34,
51 R30 = 35,
52 R31 = 36,
53 R1R0 = 37,
54 R3R2 = 38,
55 R5R4 = 39,
56 R7R6 = 40,
57 R9R8 = 41,
58 R10R9 = 42,
59 R11R10 = 43,
60 R12R11 = 44,
61 R13R12 = 45,
62 R14R13 = 46,
63 R15R14 = 47,
64 R16R15 = 48,
65 R17R16 = 49,
66 R18R17 = 50,
67 R19R18 = 51,
68 R20R19 = 52,
69 R21R20 = 53,
70 R22R21 = 54,
71 R23R22 = 55,
72 R24R23 = 56,
73 R25R24 = 57,
74 R26R25 = 58,
75 R27R26 = 59,
76 R29R28 = 60,
77 R31R30 = 61,
78 NUM_TARGET_REGS // 62
79};
80} // end namespace AVR
81
82// Register classes
83
84namespace AVR {
85enum {
86 GPR8RegClassID = 0,
87 GPR8NOZRegClassID = 1,
88 GPR8loRegClassID = 2,
89 LD8RegClassID = 3,
90 GPR8NOZ_and_LD8RegClassID = 4,
91 LD8loRegClassID = 5,
92 CCRRegClassID = 6,
93 DREGSRegClassID = 7,
94 DREGSNOZRegClassID = 8,
95 DREGSMOVWRegClassID = 9,
96 DREGSMOVW_and_DREGSNOZRegClassID = 10,
97 DREGS_with_sub_hi_in_LD8RegClassID = 11,
98 DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID = 12,
99 DREGS_with_sub_lo_in_LD8RegClassID = 13,
100 DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID = 14,
101 DREGS_with_sub_lo_in_GPR8loRegClassID = 15,
102 DREGS_with_sub_hi_in_GPR8loRegClassID = 16,
103 DLDREGSRegClassID = 17,
104 DREGS_with_sub_hi_in_LD8loRegClassID = 18,
105 DREGS_with_sub_lo_in_LD8loRegClassID = 19,
106 DREGSloRegClassID = 20,
107 DLDREGS_and_DREGSNOZRegClassID = 21,
108 DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID = 22,
109 DREGSLD8loRegClassID = 23,
110 IWREGSRegClassID = 24,
111 DREGSNOZ_and_IWREGSRegClassID = 25,
112 PTRREGSRegClassID = 26,
113 DREGSNOZ_and_PTRREGSRegClassID = 27,
114 PTRDISPREGSRegClassID = 28,
115 DREGSNOZ_and_PTRDISPREGSRegClassID = 29,
116 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID = 30,
117 GPRSPRegClassID = 31,
118 ZREGRegClassID = 32,
119
120};
121} // end namespace AVR
122
123
124// Register alternate name indices
125
126namespace AVR {
127enum {
128 NoRegAltName, // 0
129 ptr, // 1
130 NUM_TARGET_REG_ALT_NAMES = 2
131};
132} // end namespace AVR
133
134
135// Subregister indices
136
137namespace AVR {
138enum : uint16_t {
139 NoSubRegister,
140 sub_hi, // 1
141 sub_lo, // 2
142 NUM_TARGET_SUBREGS
143};
144} // end namespace AVR
145
146// Register pressure sets enum.
147namespace AVR {
148enum RegisterPressureSets {
149 CCR = 0,
150 DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo = 1,
151 GPRSP = 2,
152 IWREGS = 3,
153 LD8lo = 4,
154 LD8 = 5,
155 GPR8lo = 6,
156 GPR8lo_with_LD8lo = 7,
157 GPR8 = 8,
158};
159} // end namespace AVR
160
161} // end namespace llvm
162
163