| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* * BPF Disassembler *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | |
| 10 | #include "llvm/MC/MCInst.h" |
| 11 | #include "llvm/MC/MCSubtargetInfo.h" |
| 12 | #include "llvm/Support/DataTypes.h" |
| 13 | #include "llvm/Support/Debug.h" |
| 14 | #include "llvm/Support/LEB128.h" |
| 15 | #include "llvm/Support/raw_ostream.h" |
| 16 | #include "llvm/TargetParser/SubtargetFeature.h" |
| 17 | #include <assert.h> |
| 18 | |
| 19 | namespace { |
| 20 | |
| 21 | // InsnBitWidth is essentially a type trait used by the decoder emitter to query |
| 22 | // the supported bitwidth for a given type. But default, the value is 0, making |
| 23 | // it an invalid type for use as `InsnType` when instantiating the decoder. |
| 24 | // Individual targets are expected to provide specializations for these based |
| 25 | // on their usage. |
| 26 | template <typename T> constexpr uint32_t InsnBitWidth = 0; |
| 27 | |
| 28 | static const uint8_t DecoderTableBPF64[1279] = { |
| 29 | OPC_SwitchField, 56, 8, // 0: switch Inst[63:56] { |
| 30 | 4, 8, // 3: case 0x4: { |
| 31 | OPC_CheckField, 32, 16, 0, // 5: check Inst[47:32] == 0x0 |
| 32 | OPC_Decode, 210, 2, 0, // 9: decode to ADD_ri_32 using decoder 0 |
| 33 | // 9: } |
| 34 | 5, 4, // 13: case 0x5: { |
| 35 | OPC_Decode, 240, 2, 1, // 15: decode to JMP using decoder 1 |
| 36 | // 15: } |
| 37 | 6, 4, // 19: case 0x6: { |
| 38 | OPC_Decode, 241, 2, 2, // 21: decode to JMPL using decoder 2 |
| 39 | // 21: } |
| 40 | 7, 8, // 25: case 0x7: { |
| 41 | OPC_CheckField, 32, 16, 0, // 27: check Inst[47:32] == 0x0 |
| 42 | OPC_Decode, 209, 2, 3, // 31: decode to ADD_ri using decoder 3 |
| 43 | // 31: } |
| 44 | 12, 8, // 35: case 0xc: { |
| 45 | OPC_CheckField, 32, 16, 0, // 37: check Inst[47:32] == 0x0 |
| 46 | OPC_Decode, 212, 2, 4, // 41: decode to ADD_rr_32 using decoder 4 |
| 47 | // 41: } |
| 48 | 13, 4, // 45: case 0xd: { |
| 49 | OPC_Decode, 154, 3, 5, // 47: decode to JX using decoder 5 |
| 50 | // 47: } |
| 51 | 15, 8, // 51: case 0xf: { |
| 52 | OPC_CheckField, 32, 16, 0, // 53: check Inst[47:32] == 0x0 |
| 53 | OPC_Decode, 211, 2, 6, // 57: decode to ADD_rr using decoder 6 |
| 54 | // 57: } |
| 55 | 20, 8, // 61: case 0x14: { |
| 56 | OPC_CheckField, 32, 16, 0, // 63: check Inst[47:32] == 0x0 |
| 57 | OPC_Decode, 242, 3, 0, // 67: decode to SUB_ri_32 using decoder 0 |
| 58 | // 67: } |
| 59 | 21, 4, // 71: case 0x15: { |
| 60 | OPC_Decode, 236, 2, 7, // 73: decode to JEQ_ri using decoder 7 |
| 61 | // 73: } |
| 62 | 22, 4, // 77: case 0x16: { |
| 63 | OPC_Decode, 237, 2, 8, // 79: decode to JEQ_ri_32 using decoder 8 |
| 64 | // 79: } |
| 65 | 23, 8, // 83: case 0x17: { |
| 66 | OPC_CheckField, 32, 16, 0, // 85: check Inst[47:32] == 0x0 |
| 67 | OPC_Decode, 241, 3, 3, // 89: decode to SUB_ri using decoder 3 |
| 68 | // 89: } |
| 69 | 24, 18, // 93: case 0x18: { |
| 70 | OPC_CheckField, 32, 16, 0, // 95: check Inst[47:32] == 0x0 |
| 71 | OPC_Scope, 8, // 99: try { |
| 72 | OPC_CheckField, 52, 4, 0, // 101: check Inst[55:52] == 0x0 |
| 73 | OPC_Decode, 175, 3, 9, // 105: decode to LD_imm64 using decoder 9 |
| 74 | // 105: } else try { |
| 75 | OPC_Decode, 176, 3, 10, // 109: decode to LD_pseudo using decoder 10 |
| 76 | // 109: } |
| 77 | // 109: } |
| 78 | 28, 8, // 113: case 0x1c: { |
| 79 | OPC_CheckField, 32, 16, 0, // 115: check Inst[47:32] == 0x0 |
| 80 | OPC_Decode, 244, 3, 4, // 119: decode to SUB_rr_32 using decoder 4 |
| 81 | // 119: } |
| 82 | 29, 4, // 123: case 0x1d: { |
| 83 | OPC_Decode, 238, 2, 11, // 125: decode to JEQ_rr using decoder 11 |
| 84 | // 125: } |
| 85 | 30, 4, // 129: case 0x1e: { |
| 86 | OPC_Decode, 239, 2, 12, // 131: decode to JEQ_rr_32 using decoder 12 |
| 87 | // 131: } |
| 88 | 31, 8, // 135: case 0x1f: { |
| 89 | OPC_CheckField, 32, 16, 0, // 137: check Inst[47:32] == 0x0 |
| 90 | OPC_Decode, 243, 3, 6, // 141: decode to SUB_rr using decoder 6 |
| 91 | // 141: } |
| 92 | 32, 4, // 145: case 0x20: { |
| 93 | OPC_Decode, 171, 3, 2, // 147: decode to LD_ABS_W using decoder 2 |
| 94 | // 147: } |
| 95 | 36, 8, // 151: case 0x24: { |
| 96 | OPC_CheckField, 32, 16, 0, // 153: check Inst[47:32] == 0x0 |
| 97 | OPC_Decode, 195, 3, 0, // 157: decode to MUL_ri_32 using decoder 0 |
| 98 | // 157: } |
| 99 | 37, 4, // 161: case 0x25: { |
| 100 | OPC_Decode, 142, 3, 7, // 163: decode to JUGT_ri using decoder 7 |
| 101 | // 163: } |
| 102 | 38, 4, // 167: case 0x26: { |
| 103 | OPC_Decode, 143, 3, 8, // 169: decode to JUGT_ri_32 using decoder 8 |
| 104 | // 169: } |
| 105 | 39, 8, // 173: case 0x27: { |
| 106 | OPC_CheckField, 32, 16, 0, // 175: check Inst[47:32] == 0x0 |
| 107 | OPC_Decode, 194, 3, 3, // 179: decode to MUL_ri using decoder 3 |
| 108 | // 179: } |
| 109 | 40, 4, // 183: case 0x28: { |
| 110 | OPC_Decode, 170, 3, 2, // 185: decode to LD_ABS_H using decoder 2 |
| 111 | // 185: } |
| 112 | 44, 8, // 189: case 0x2c: { |
| 113 | OPC_CheckField, 32, 16, 0, // 191: check Inst[47:32] == 0x0 |
| 114 | OPC_Decode, 197, 3, 4, // 195: decode to MUL_rr_32 using decoder 4 |
| 115 | // 195: } |
| 116 | 45, 4, // 199: case 0x2d: { |
| 117 | OPC_Decode, 144, 3, 11, // 201: decode to JUGT_rr using decoder 11 |
| 118 | // 201: } |
| 119 | 46, 4, // 205: case 0x2e: { |
| 120 | OPC_Decode, 145, 3, 12, // 207: decode to JUGT_rr_32 using decoder 12 |
| 121 | // 207: } |
| 122 | 47, 8, // 211: case 0x2f: { |
| 123 | OPC_CheckField, 32, 16, 0, // 213: check Inst[47:32] == 0x0 |
| 124 | OPC_Decode, 196, 3, 6, // 217: decode to MUL_rr using decoder 6 |
| 125 | // 217: } |
| 126 | 48, 4, // 221: case 0x30: { |
| 127 | OPC_Decode, 169, 3, 2, // 223: decode to LD_ABS_B using decoder 2 |
| 128 | // 223: } |
| 129 | 52, 15, // 227: case 0x34: { |
| 130 | OPC_SwitchField, 32, 16, // 229: switch Inst[47:32] { |
| 131 | 0, 4, // 232: case 0x0: { |
| 132 | OPC_Decode, 230, 2, 0, // 234: decode to DIV_ri_32 using decoder 0 |
| 133 | // 234: } |
| 134 | 1, 0, // 238: case 0x1: { |
| 135 | OPC_Decode, 207, 3, 0, // 240: decode to SDIV_ri_32 using decoder 0 |
| 136 | // 240: } |
| 137 | // 240: } // switch Inst[47:32] |
| 138 | // 240: } |
| 139 | 53, 4, // 244: case 0x35: { |
| 140 | OPC_Decode, 138, 3, 7, // 246: decode to JUGE_ri using decoder 7 |
| 141 | // 246: } |
| 142 | 54, 4, // 250: case 0x36: { |
| 143 | OPC_Decode, 139, 3, 8, // 252: decode to JUGE_ri_32 using decoder 8 |
| 144 | // 252: } |
| 145 | 55, 15, // 256: case 0x37: { |
| 146 | OPC_SwitchField, 32, 16, // 258: switch Inst[47:32] { |
| 147 | 0, 4, // 261: case 0x0: { |
| 148 | OPC_Decode, 229, 2, 3, // 263: decode to DIV_ri using decoder 3 |
| 149 | // 263: } |
| 150 | 1, 0, // 267: case 0x1: { |
| 151 | OPC_Decode, 206, 3, 3, // 269: decode to SDIV_ri using decoder 3 |
| 152 | // 269: } |
| 153 | // 269: } // switch Inst[47:32] |
| 154 | // 269: } |
| 155 | 60, 15, // 273: case 0x3c: { |
| 156 | OPC_SwitchField, 32, 16, // 275: switch Inst[47:32] { |
| 157 | 0, 4, // 278: case 0x0: { |
| 158 | OPC_Decode, 232, 2, 4, // 280: decode to DIV_rr_32 using decoder 4 |
| 159 | // 280: } |
| 160 | 1, 0, // 284: case 0x1: { |
| 161 | OPC_Decode, 209, 3, 4, // 286: decode to SDIV_rr_32 using decoder 4 |
| 162 | // 286: } |
| 163 | // 286: } // switch Inst[47:32] |
| 164 | // 286: } |
| 165 | 61, 4, // 290: case 0x3d: { |
| 166 | OPC_Decode, 140, 3, 11, // 292: decode to JUGE_rr using decoder 11 |
| 167 | // 292: } |
| 168 | 62, 4, // 296: case 0x3e: { |
| 169 | OPC_Decode, 141, 3, 12, // 298: decode to JUGE_rr_32 using decoder 12 |
| 170 | // 298: } |
| 171 | 63, 15, // 302: case 0x3f: { |
| 172 | OPC_SwitchField, 32, 16, // 304: switch Inst[47:32] { |
| 173 | 0, 4, // 307: case 0x0: { |
| 174 | OPC_Decode, 231, 2, 6, // 309: decode to DIV_rr using decoder 6 |
| 175 | // 309: } |
| 176 | 1, 0, // 313: case 0x1: { |
| 177 | OPC_Decode, 208, 3, 6, // 315: decode to SDIV_rr using decoder 6 |
| 178 | // 315: } |
| 179 | // 315: } // switch Inst[47:32] |
| 180 | // 315: } |
| 181 | 64, 4, // 319: case 0x40: { |
| 182 | OPC_Decode, 174, 3, 13, // 321: decode to LD_IND_W using decoder 13 |
| 183 | // 321: } |
| 184 | 68, 8, // 325: case 0x44: { |
| 185 | OPC_CheckField, 32, 16, 0, // 327: check Inst[47:32] == 0x0 |
| 186 | OPC_Decode, 202, 3, 0, // 331: decode to OR_ri_32 using decoder 0 |
| 187 | // 331: } |
| 188 | 69, 4, // 335: case 0x45: { |
| 189 | OPC_Decode, 246, 2, 7, // 337: decode to JSET_ri using decoder 7 |
| 190 | // 337: } |
| 191 | 70, 4, // 341: case 0x46: { |
| 192 | OPC_Decode, 247, 2, 8, // 343: decode to JSET_ri_32 using decoder 8 |
| 193 | // 343: } |
| 194 | 71, 8, // 347: case 0x47: { |
| 195 | OPC_CheckField, 32, 16, 0, // 349: check Inst[47:32] == 0x0 |
| 196 | OPC_Decode, 201, 3, 3, // 353: decode to OR_ri using decoder 3 |
| 197 | // 353: } |
| 198 | 72, 4, // 357: case 0x48: { |
| 199 | OPC_Decode, 173, 3, 13, // 359: decode to LD_IND_H using decoder 13 |
| 200 | // 359: } |
| 201 | 76, 8, // 363: case 0x4c: { |
| 202 | OPC_CheckField, 32, 16, 0, // 365: check Inst[47:32] == 0x0 |
| 203 | OPC_Decode, 204, 3, 4, // 369: decode to OR_rr_32 using decoder 4 |
| 204 | // 369: } |
| 205 | 77, 4, // 373: case 0x4d: { |
| 206 | OPC_Decode, 248, 2, 11, // 375: decode to JSET_rr using decoder 11 |
| 207 | // 375: } |
| 208 | 78, 4, // 379: case 0x4e: { |
| 209 | OPC_Decode, 249, 2, 12, // 381: decode to JSET_rr_32 using decoder 12 |
| 210 | // 381: } |
| 211 | 79, 8, // 385: case 0x4f: { |
| 212 | OPC_CheckField, 32, 16, 0, // 387: check Inst[47:32] == 0x0 |
| 213 | OPC_Decode, 203, 3, 6, // 391: decode to OR_rr using decoder 6 |
| 214 | // 391: } |
| 215 | 80, 4, // 395: case 0x50: { |
| 216 | OPC_Decode, 172, 3, 13, // 397: decode to LD_IND_B using decoder 13 |
| 217 | // 397: } |
| 218 | 84, 8, // 401: case 0x54: { |
| 219 | OPC_CheckField, 32, 16, 0, // 403: check Inst[47:32] == 0x0 |
| 220 | OPC_Decode, 214, 2, 0, // 407: decode to AND_ri_32 using decoder 0 |
| 221 | // 407: } |
| 222 | 85, 4, // 411: case 0x55: { |
| 223 | OPC_Decode, 242, 2, 7, // 413: decode to JNE_ri using decoder 7 |
| 224 | // 413: } |
| 225 | 86, 4, // 417: case 0x56: { |
| 226 | OPC_Decode, 243, 2, 8, // 419: decode to JNE_ri_32 using decoder 8 |
| 227 | // 419: } |
| 228 | 87, 8, // 423: case 0x57: { |
| 229 | OPC_CheckField, 32, 16, 0, // 425: check Inst[47:32] == 0x0 |
| 230 | OPC_Decode, 213, 2, 3, // 429: decode to AND_ri using decoder 3 |
| 231 | // 429: } |
| 232 | 92, 8, // 433: case 0x5c: { |
| 233 | OPC_CheckField, 32, 16, 0, // 435: check Inst[47:32] == 0x0 |
| 234 | OPC_Decode, 216, 2, 4, // 439: decode to AND_rr_32 using decoder 4 |
| 235 | // 439: } |
| 236 | 93, 4, // 443: case 0x5d: { |
| 237 | OPC_Decode, 244, 2, 11, // 445: decode to JNE_rr using decoder 11 |
| 238 | // 445: } |
| 239 | 94, 4, // 449: case 0x5e: { |
| 240 | OPC_Decode, 245, 2, 12, // 451: decode to JNE_rr_32 using decoder 12 |
| 241 | // 451: } |
| 242 | 95, 8, // 455: case 0x5f: { |
| 243 | OPC_CheckField, 32, 16, 0, // 457: check Inst[47:32] == 0x0 |
| 244 | OPC_Decode, 215, 2, 6, // 461: decode to AND_rr using decoder 6 |
| 245 | // 461: } |
| 246 | 97, 4, // 465: case 0x61: { |
| 247 | OPC_Decode, 165, 3, 14, // 467: decode to LDW using decoder 14 |
| 248 | // 467: } |
| 249 | 98, 4, // 471: case 0x62: { |
| 250 | OPC_Decode, 240, 3, 15, // 473: decode to STW_imm using decoder 15 |
| 251 | // 473: } |
| 252 | 99, 4, // 477: case 0x63: { |
| 253 | OPC_Decode, 237, 3, 16, // 479: decode to STW using decoder 16 |
| 254 | // 479: } |
| 255 | 100, 8, // 483: case 0x64: { |
| 256 | OPC_CheckField, 32, 16, 0, // 485: check Inst[47:32] == 0x0 |
| 257 | OPC_Decode, 211, 3, 0, // 489: decode to SLL_ri_32 using decoder 0 |
| 258 | // 489: } |
| 259 | 101, 4, // 493: case 0x65: { |
| 260 | OPC_Decode, 254, 2, 7, // 495: decode to JSGT_ri using decoder 7 |
| 261 | // 495: } |
| 262 | 102, 4, // 499: case 0x66: { |
| 263 | OPC_Decode, 255, 2, 8, // 501: decode to JSGT_ri_32 using decoder 8 |
| 264 | // 501: } |
| 265 | 103, 8, // 505: case 0x67: { |
| 266 | OPC_CheckField, 32, 16, 0, // 507: check Inst[47:32] == 0x0 |
| 267 | OPC_Decode, 210, 3, 3, // 511: decode to SLL_ri using decoder 3 |
| 268 | // 511: } |
| 269 | 105, 4, // 515: case 0x69: { |
| 270 | OPC_Decode, 161, 3, 14, // 517: decode to LDH using decoder 14 |
| 271 | // 517: } |
| 272 | 106, 4, // 521: case 0x6a: { |
| 273 | OPC_Decode, 236, 3, 15, // 523: decode to STH_imm using decoder 15 |
| 274 | // 523: } |
| 275 | 107, 4, // 527: case 0x6b: { |
| 276 | OPC_Decode, 233, 3, 16, // 529: decode to STH using decoder 16 |
| 277 | // 529: } |
| 278 | 108, 8, // 533: case 0x6c: { |
| 279 | OPC_CheckField, 32, 16, 0, // 535: check Inst[47:32] == 0x0 |
| 280 | OPC_Decode, 213, 3, 4, // 539: decode to SLL_rr_32 using decoder 4 |
| 281 | // 539: } |
| 282 | 109, 4, // 543: case 0x6d: { |
| 283 | OPC_Decode, 128, 3, 11, // 545: decode to JSGT_rr using decoder 11 |
| 284 | // 545: } |
| 285 | 110, 4, // 549: case 0x6e: { |
| 286 | OPC_Decode, 129, 3, 12, // 551: decode to JSGT_rr_32 using decoder 12 |
| 287 | // 551: } |
| 288 | 111, 8, // 555: case 0x6f: { |
| 289 | OPC_CheckField, 32, 16, 0, // 557: check Inst[47:32] == 0x0 |
| 290 | OPC_Decode, 212, 3, 6, // 561: decode to SLL_rr using decoder 6 |
| 291 | // 561: } |
| 292 | 113, 4, // 565: case 0x71: { |
| 293 | OPC_Decode, 155, 3, 14, // 567: decode to LDB using decoder 14 |
| 294 | // 567: } |
| 295 | 114, 4, // 571: case 0x72: { |
| 296 | OPC_Decode, 229, 3, 15, // 573: decode to STB_imm using decoder 15 |
| 297 | // 573: } |
| 298 | 115, 4, // 577: case 0x73: { |
| 299 | OPC_Decode, 226, 3, 16, // 579: decode to STB using decoder 16 |
| 300 | // 579: } |
| 301 | 116, 8, // 583: case 0x74: { |
| 302 | OPC_CheckField, 32, 16, 0, // 585: check Inst[47:32] == 0x0 |
| 303 | OPC_Decode, 223, 3, 0, // 589: decode to SRL_ri_32 using decoder 0 |
| 304 | // 589: } |
| 305 | 117, 4, // 593: case 0x75: { |
| 306 | OPC_Decode, 250, 2, 7, // 595: decode to JSGE_ri using decoder 7 |
| 307 | // 595: } |
| 308 | 118, 4, // 599: case 0x76: { |
| 309 | OPC_Decode, 251, 2, 8, // 601: decode to JSGE_ri_32 using decoder 8 |
| 310 | // 601: } |
| 311 | 119, 8, // 605: case 0x77: { |
| 312 | OPC_CheckField, 32, 16, 0, // 607: check Inst[47:32] == 0x0 |
| 313 | OPC_Decode, 222, 3, 3, // 611: decode to SRL_ri using decoder 3 |
| 314 | // 611: } |
| 315 | 121, 4, // 615: case 0x79: { |
| 316 | OPC_Decode, 159, 3, 14, // 617: decode to LDD using decoder 14 |
| 317 | // 617: } |
| 318 | 122, 4, // 621: case 0x7a: { |
| 319 | OPC_Decode, 232, 3, 15, // 623: decode to STD_imm using decoder 15 |
| 320 | // 623: } |
| 321 | 123, 4, // 627: case 0x7b: { |
| 322 | OPC_Decode, 230, 3, 16, // 629: decode to STD using decoder 16 |
| 323 | // 629: } |
| 324 | 124, 8, // 633: case 0x7c: { |
| 325 | OPC_CheckField, 32, 16, 0, // 635: check Inst[47:32] == 0x0 |
| 326 | OPC_Decode, 225, 3, 4, // 639: decode to SRL_rr_32 using decoder 4 |
| 327 | // 639: } |
| 328 | 125, 4, // 643: case 0x7d: { |
| 329 | OPC_Decode, 252, 2, 11, // 645: decode to JSGE_rr using decoder 11 |
| 330 | // 645: } |
| 331 | 126, 4, // 649: case 0x7e: { |
| 332 | OPC_Decode, 253, 2, 12, // 651: decode to JSGE_rr_32 using decoder 12 |
| 333 | // 651: } |
| 334 | 127, 8, // 655: case 0x7f: { |
| 335 | OPC_CheckField, 32, 16, 0, // 657: check Inst[47:32] == 0x0 |
| 336 | OPC_Decode, 224, 3, 6, // 661: decode to SRL_rr using decoder 6 |
| 337 | // 661: } |
| 338 | 129, 1, 4, // 665: case 0x81: { |
| 339 | OPC_Decode, 168, 3, 14, // 668: decode to LDWSX using decoder 14 |
| 340 | // 668: } |
| 341 | 132, 1, 4, // 672: case 0x84: { |
| 342 | OPC_Decode, 198, 3, 17, // 675: decode to NEG_32 using decoder 17 |
| 343 | // 675: } |
| 344 | 133, 1, 4, // 679: case 0x85: { |
| 345 | OPC_Decode, 233, 2, 2, // 682: decode to JAL using decoder 2 |
| 346 | // 682: } |
| 347 | 135, 1, 4, // 686: case 0x87: { |
| 348 | OPC_Decode, 199, 3, 18, // 689: decode to NEG_64 using decoder 18 |
| 349 | // 689: } |
| 350 | 137, 1, 4, // 693: case 0x89: { |
| 351 | OPC_Decode, 164, 3, 14, // 696: decode to LDHSX using decoder 14 |
| 352 | // 696: } |
| 353 | 141, 1, 4, // 700: case 0x8d: { |
| 354 | OPC_Decode, 234, 2, 5, // 703: decode to JALX using decoder 5 |
| 355 | // 703: } |
| 356 | 145, 1, 4, // 707: case 0x91: { |
| 357 | OPC_Decode, 158, 3, 14, // 710: decode to LDBSX using decoder 14 |
| 358 | // 710: } |
| 359 | 148, 1, 15, // 714: case 0x94: { |
| 360 | OPC_SwitchField, 32, 16, // 717: switch Inst[47:32] { |
| 361 | 0, 4, // 720: case 0x0: { |
| 362 | OPC_Decode, 181, 3, 0, // 722: decode to MOD_ri_32 using decoder 0 |
| 363 | // 722: } |
| 364 | 1, 0, // 726: case 0x1: { |
| 365 | OPC_Decode, 215, 3, 0, // 728: decode to SMOD_ri_32 using decoder 0 |
| 366 | // 728: } |
| 367 | // 728: } // switch Inst[47:32] |
| 368 | // 728: } |
| 369 | 149, 1, 8, // 732: case 0x95: { |
| 370 | OPC_CheckField, 0, 32, 0, // 735: check Inst[31:0] == 0x0 |
| 371 | OPC_Decode, 205, 3, 19, // 739: decode to RET using decoder 19 |
| 372 | // 739: } |
| 373 | 151, 1, 15, // 743: case 0x97: { |
| 374 | OPC_SwitchField, 32, 16, // 746: switch Inst[47:32] { |
| 375 | 0, 4, // 749: case 0x0: { |
| 376 | OPC_Decode, 180, 3, 3, // 751: decode to MOD_ri using decoder 3 |
| 377 | // 751: } |
| 378 | 1, 0, // 755: case 0x1: { |
| 379 | OPC_Decode, 214, 3, 3, // 757: decode to SMOD_ri using decoder 3 |
| 380 | // 757: } |
| 381 | // 757: } // switch Inst[47:32] |
| 382 | // 757: } |
| 383 | 156, 1, 15, // 761: case 0x9c: { |
| 384 | OPC_SwitchField, 32, 16, // 764: switch Inst[47:32] { |
| 385 | 0, 4, // 767: case 0x0: { |
| 386 | OPC_Decode, 183, 3, 4, // 769: decode to MOD_rr_32 using decoder 4 |
| 387 | // 769: } |
| 388 | 1, 0, // 773: case 0x1: { |
| 389 | OPC_Decode, 217, 3, 4, // 775: decode to SMOD_rr_32 using decoder 4 |
| 390 | // 775: } |
| 391 | // 775: } // switch Inst[47:32] |
| 392 | // 775: } |
| 393 | 159, 1, 15, // 779: case 0x9f: { |
| 394 | OPC_SwitchField, 32, 16, // 782: switch Inst[47:32] { |
| 395 | 0, 4, // 785: case 0x0: { |
| 396 | OPC_Decode, 182, 3, 6, // 787: decode to MOD_rr using decoder 6 |
| 397 | // 787: } |
| 398 | 1, 0, // 791: case 0x1: { |
| 399 | OPC_Decode, 216, 3, 6, // 793: decode to SMOD_rr using decoder 6 |
| 400 | // 793: } |
| 401 | // 793: } // switch Inst[47:32] |
| 402 | // 793: } |
| 403 | 164, 1, 8, // 797: case 0xa4: { |
| 404 | OPC_CheckField, 32, 16, 0, // 800: check Inst[47:32] == 0x0 |
| 405 | OPC_Decode, 135, 4, 0, // 804: decode to XOR_ri_32 using decoder 0 |
| 406 | // 804: } |
| 407 | 165, 1, 4, // 808: case 0xa5: { |
| 408 | OPC_Decode, 150, 3, 7, // 811: decode to JULT_ri using decoder 7 |
| 409 | // 811: } |
| 410 | 166, 1, 4, // 815: case 0xa6: { |
| 411 | OPC_Decode, 151, 3, 8, // 818: decode to JULT_ri_32 using decoder 8 |
| 412 | // 818: } |
| 413 | 167, 1, 8, // 822: case 0xa7: { |
| 414 | OPC_CheckField, 32, 16, 0, // 825: check Inst[47:32] == 0x0 |
| 415 | OPC_Decode, 134, 4, 3, // 829: decode to XOR_ri using decoder 3 |
| 416 | // 829: } |
| 417 | 172, 1, 8, // 833: case 0xac: { |
| 418 | OPC_CheckField, 32, 16, 0, // 836: check Inst[47:32] == 0x0 |
| 419 | OPC_Decode, 137, 4, 4, // 840: decode to XOR_rr_32 using decoder 4 |
| 420 | // 840: } |
| 421 | 173, 1, 4, // 844: case 0xad: { |
| 422 | OPC_Decode, 152, 3, 11, // 847: decode to JULT_rr using decoder 11 |
| 423 | // 847: } |
| 424 | 174, 1, 4, // 851: case 0xae: { |
| 425 | OPC_Decode, 153, 3, 12, // 854: decode to JULT_rr_32 using decoder 12 |
| 426 | // 854: } |
| 427 | 175, 1, 8, // 858: case 0xaf: { |
| 428 | OPC_CheckField, 32, 16, 0, // 861: check Inst[47:32] == 0x0 |
| 429 | OPC_Decode, 136, 4, 6, // 865: decode to XOR_rr using decoder 6 |
| 430 | // 865: } |
| 431 | 180, 1, 8, // 869: case 0xb4: { |
| 432 | OPC_CheckField, 32, 16, 0, // 872: check Inst[47:32] == 0x0 |
| 433 | OPC_Decode, 191, 3, 20, // 876: decode to MOV_ri_32 using decoder 20 |
| 434 | // 876: } |
| 435 | 181, 1, 4, // 880: case 0xb5: { |
| 436 | OPC_Decode, 146, 3, 7, // 883: decode to JULE_ri using decoder 7 |
| 437 | // 883: } |
| 438 | 182, 1, 4, // 887: case 0xb6: { |
| 439 | OPC_Decode, 147, 3, 8, // 890: decode to JULE_ri_32 using decoder 8 |
| 440 | // 890: } |
| 441 | 183, 1, 8, // 894: case 0xb7: { |
| 442 | OPC_CheckField, 32, 16, 0, // 897: check Inst[47:32] == 0x0 |
| 443 | OPC_Decode, 190, 3, 9, // 901: decode to MOV_ri using decoder 9 |
| 444 | // 901: } |
| 445 | 188, 1, 21, // 905: case 0xbc: { |
| 446 | OPC_SwitchField, 32, 16, // 908: switch Inst[47:32] { |
| 447 | 0, 4, // 911: case 0x0: { |
| 448 | OPC_Decode, 193, 3, 21, // 913: decode to MOV_rr_32 using decoder 21 |
| 449 | // 913: } |
| 450 | 8, 4, // 917: case 0x8: { |
| 451 | OPC_Decode, 187, 3, 21, // 919: decode to MOVSX_rr_32_8 using decoder 21 |
| 452 | // 919: } |
| 453 | 16, 0, // 923: case 0x10: { |
| 454 | OPC_Decode, 186, 3, 21, // 925: decode to MOVSX_rr_32_16 using decoder 21 |
| 455 | // 925: } |
| 456 | // 925: } // switch Inst[47:32] |
| 457 | // 925: } |
| 458 | 189, 1, 4, // 929: case 0xbd: { |
| 459 | OPC_Decode, 148, 3, 11, // 932: decode to JULE_rr using decoder 11 |
| 460 | // 932: } |
| 461 | 190, 1, 4, // 936: case 0xbe: { |
| 462 | OPC_Decode, 149, 3, 12, // 939: decode to JULE_rr_32 using decoder 12 |
| 463 | // 939: } |
| 464 | 191, 1, 33, // 943: case 0xbf: { |
| 465 | OPC_SwitchField, 32, 16, // 946: switch Inst[47:32] { |
| 466 | 0, 4, // 949: case 0x0: { |
| 467 | OPC_Decode, 192, 3, 22, // 951: decode to MOV_rr using decoder 22 |
| 468 | // 951: } |
| 469 | 1, 4, // 955: case 0x1: { |
| 470 | OPC_Decode, 208, 2, 23, // 957: decode to ADDR_SPACE_CAST using decoder 23 |
| 471 | // 957: } |
| 472 | 8, 4, // 961: case 0x8: { |
| 473 | OPC_Decode, 188, 3, 22, // 963: decode to MOVSX_rr_8 using decoder 22 |
| 474 | // 963: } |
| 475 | 16, 4, // 967: case 0x10: { |
| 476 | OPC_Decode, 184, 3, 22, // 969: decode to MOVSX_rr_16 using decoder 22 |
| 477 | // 969: } |
| 478 | 32, 0, // 973: case 0x20: { |
| 479 | OPC_Decode, 185, 3, 22, // 975: decode to MOVSX_rr_32 using decoder 22 |
| 480 | // 975: } |
| 481 | // 975: } // switch Inst[47:32] |
| 482 | // 975: } |
| 483 | 195, 1, 8, // 979: case 0xc3: { |
| 484 | OPC_CheckField, 4, 4, 0, // 982: check Inst[7:4] == 0x0 |
| 485 | OPC_Decode, 246, 3, 24, // 986: decode to XADDW using decoder 24 |
| 486 | // 986: } |
| 487 | 196, 1, 8, // 990: case 0xc4: { |
| 488 | OPC_CheckField, 32, 16, 0, // 993: check Inst[47:32] == 0x0 |
| 489 | OPC_Decode, 219, 3, 0, // 997: decode to SRA_ri_32 using decoder 0 |
| 490 | // 997: } |
| 491 | 197, 1, 4, // 1001: case 0xc5: { |
| 492 | OPC_Decode, 134, 3, 7, // 1004: decode to JSLT_ri using decoder 7 |
| 493 | // 1004: } |
| 494 | 198, 1, 4, // 1008: case 0xc6: { |
| 495 | OPC_Decode, 135, 3, 8, // 1011: decode to JSLT_ri_32 using decoder 8 |
| 496 | // 1011: } |
| 497 | 199, 1, 8, // 1015: case 0xc7: { |
| 498 | OPC_CheckField, 32, 16, 0, // 1018: check Inst[47:32] == 0x0 |
| 499 | OPC_Decode, 218, 3, 3, // 1022: decode to SRA_ri using decoder 3 |
| 500 | // 1022: } |
| 501 | 204, 1, 8, // 1026: case 0xcc: { |
| 502 | OPC_CheckField, 32, 16, 0, // 1029: check Inst[47:32] == 0x0 |
| 503 | OPC_Decode, 221, 3, 4, // 1033: decode to SRA_rr_32 using decoder 4 |
| 504 | // 1033: } |
| 505 | 205, 1, 4, // 1037: case 0xcd: { |
| 506 | OPC_Decode, 136, 3, 11, // 1040: decode to JSLT_rr using decoder 11 |
| 507 | // 1040: } |
| 508 | 206, 1, 4, // 1044: case 0xce: { |
| 509 | OPC_Decode, 137, 3, 12, // 1047: decode to JSLT_rr_32 using decoder 12 |
| 510 | // 1047: } |
| 511 | 207, 1, 8, // 1051: case 0xcf: { |
| 512 | OPC_CheckField, 32, 16, 0, // 1054: check Inst[47:32] == 0x0 |
| 513 | OPC_Decode, 220, 3, 6, // 1058: decode to SRA_rr using decoder 6 |
| 514 | // 1058: } |
| 515 | 212, 1, 21, // 1062: case 0xd4: { |
| 516 | OPC_SwitchField, 0, 32, // 1065: switch Inst[31:0] { |
| 517 | 16, 4, // 1068: case 0x10: { |
| 518 | OPC_Decode, 177, 3, 18, // 1070: decode to LE16 using decoder 18 |
| 519 | // 1070: } |
| 520 | 32, 4, // 1074: case 0x20: { |
| 521 | OPC_Decode, 178, 3, 18, // 1076: decode to LE32 using decoder 18 |
| 522 | // 1076: } |
| 523 | 64, 0, // 1080: case 0x40: { |
| 524 | OPC_Decode, 179, 3, 18, // 1082: decode to LE64 using decoder 18 |
| 525 | // 1082: } |
| 526 | // 1082: } // switch Inst[31:0] |
| 527 | // 1082: } |
| 528 | 213, 1, 4, // 1086: case 0xd5: { |
| 529 | OPC_Decode, 130, 3, 7, // 1089: decode to JSLE_ri using decoder 7 |
| 530 | // 1089: } |
| 531 | 214, 1, 4, // 1093: case 0xd6: { |
| 532 | OPC_Decode, 131, 3, 8, // 1096: decode to JSLE_ri_32 using decoder 8 |
| 533 | // 1096: } |
| 534 | 215, 1, 21, // 1100: case 0xd7: { |
| 535 | OPC_SwitchField, 0, 32, // 1103: switch Inst[31:0] { |
| 536 | 16, 4, // 1106: case 0x10: { |
| 537 | OPC_Decode, 220, 2, 18, // 1108: decode to BSWAP16 using decoder 18 |
| 538 | // 1108: } |
| 539 | 32, 4, // 1112: case 0x20: { |
| 540 | OPC_Decode, 221, 2, 18, // 1114: decode to BSWAP32 using decoder 18 |
| 541 | // 1114: } |
| 542 | 64, 0, // 1118: case 0x40: { |
| 543 | OPC_Decode, 222, 2, 18, // 1120: decode to BSWAP64 using decoder 18 |
| 544 | // 1120: } |
| 545 | // 1120: } // switch Inst[31:0] |
| 546 | // 1120: } |
| 547 | 219, 1, 107, // 1124: case 0xdb: { |
| 548 | OPC_SwitchField, 4, 4, // 1127: switch Inst[7:4] { |
| 549 | 0, 24, // 1130: case 0x0: { |
| 550 | OPC_Scope, 8, // 1132: try { |
| 551 | OPC_CheckField, 0, 4, 1, // 1134: check Inst[3:0] == 0x1 |
| 552 | OPC_Decode, 252, 3, 24, // 1138: decode to XFADDD using decoder 24 |
| 553 | OPC_Scope, 8, // 1142: } else try { |
| 554 | OPC_CheckField, 8, 1, 1, // 1144: check Inst[8] == 0x1 |
| 555 | OPC_Decode, 160, 3, 14, // 1148: decode to LDDACQ using decoder 14 |
| 556 | // 1148: } else try { |
| 557 | OPC_Decode, 245, 3, 24, // 1152: decode to XADDD using decoder 24 |
| 558 | // 1152: } |
| 559 | // 1152: } |
| 560 | 1, 8, // 1156: case 0x1: { |
| 561 | OPC_CheckField, 8, 1, 1, // 1158: check Inst[8] == 0x1 |
| 562 | OPC_Decode, 231, 3, 16, // 1162: decode to STDREL using decoder 16 |
| 563 | // 1162: } |
| 564 | 4, 14, // 1166: case 0x4: { |
| 565 | OPC_Scope, 8, // 1168: try { |
| 566 | OPC_CheckField, 0, 4, 1, // 1170: check Inst[3:0] == 0x1 |
| 567 | OPC_Decode, 128, 4, 24, // 1174: decode to XFORD using decoder 24 |
| 568 | // 1174: } else try { |
| 569 | OPC_Decode, 132, 4, 24, // 1178: decode to XORD using decoder 24 |
| 570 | // 1178: } |
| 571 | // 1178: } |
| 572 | 5, 14, // 1182: case 0x5: { |
| 573 | OPC_Scope, 8, // 1184: try { |
| 574 | OPC_CheckField, 0, 4, 1, // 1186: check Inst[3:0] == 0x1 |
| 575 | OPC_Decode, 254, 3, 24, // 1190: decode to XFANDD using decoder 24 |
| 576 | // 1190: } else try { |
| 577 | OPC_Decode, 248, 3, 24, // 1194: decode to XANDD using decoder 24 |
| 578 | // 1194: } |
| 579 | // 1194: } |
| 580 | 10, 14, // 1198: case 0xa: { |
| 581 | OPC_Scope, 8, // 1200: try { |
| 582 | OPC_CheckField, 0, 4, 1, // 1202: check Inst[3:0] == 0x1 |
| 583 | OPC_Decode, 130, 4, 24, // 1206: decode to XFXORD using decoder 24 |
| 584 | // 1206: } else try { |
| 585 | OPC_Decode, 138, 4, 24, // 1210: decode to XXORD using decoder 24 |
| 586 | // 1210: } |
| 587 | // 1210: } |
| 588 | 14, 8, // 1214: case 0xe: { |
| 589 | OPC_CheckField, 0, 4, 1, // 1216: check Inst[3:0] == 0x1 |
| 590 | OPC_Decode, 250, 3, 24, // 1220: decode to XCHGD using decoder 24 |
| 591 | // 1220: } |
| 592 | 15, 0, // 1224: case 0xf: { |
| 593 | OPC_CheckField, 0, 4, 1, // 1226: check Inst[3:0] == 0x1 |
| 594 | OPC_Decode, 223, 2, 25, // 1230: decode to CMPXCHGD using decoder 25 |
| 595 | // 1230: } |
| 596 | // 1230: } // switch Inst[7:4] |
| 597 | // 1230: } |
| 598 | 220, 1, 21, // 1234: case 0xdc: { |
| 599 | OPC_SwitchField, 0, 32, // 1237: switch Inst[31:0] { |
| 600 | 16, 4, // 1240: case 0x10: { |
| 601 | OPC_Decode, 217, 2, 18, // 1242: decode to BE16 using decoder 18 |
| 602 | // 1242: } |
| 603 | 32, 4, // 1246: case 0x20: { |
| 604 | OPC_Decode, 218, 2, 18, // 1248: decode to BE32 using decoder 18 |
| 605 | // 1248: } |
| 606 | 64, 0, // 1252: case 0x40: { |
| 607 | OPC_Decode, 219, 2, 18, // 1254: decode to BE64 using decoder 18 |
| 608 | // 1254: } |
| 609 | // 1254: } // switch Inst[31:0] |
| 610 | // 1254: } |
| 611 | 221, 1, 4, // 1258: case 0xdd: { |
| 612 | OPC_Decode, 132, 3, 11, // 1261: decode to JSLE_rr using decoder 11 |
| 613 | // 1261: } |
| 614 | 222, 1, 4, // 1265: case 0xde: { |
| 615 | OPC_Decode, 133, 3, 12, // 1268: decode to JSLE_rr_32 using decoder 12 |
| 616 | // 1268: } |
| 617 | 229, 1, 0, // 1272: case 0xe5: { |
| 618 | OPC_Decode, 235, 2, 1, // 1275: decode to JCOND using decoder 1 |
| 619 | // 1275: } |
| 620 | // 1275: } // switch Inst[63:56] |
| 621 | }; |
| 622 | static const uint8_t DecoderTableBPFALU3264[185] = { |
| 623 | OPC_SwitchField, 56, 8, // 0: switch Inst[63:56] { |
| 624 | 97, 4, // 3: case 0x61: { |
| 625 | OPC_Decode, 166, 3, 26, // 5: decode to LDW32 using decoder 26 |
| 626 | // 5: } |
| 627 | 99, 4, // 9: case 0x63: { |
| 628 | OPC_Decode, 238, 3, 27, // 11: decode to STW32 using decoder 27 |
| 629 | // 11: } |
| 630 | 105, 4, // 15: case 0x69: { |
| 631 | OPC_Decode, 162, 3, 26, // 17: decode to LDH32 using decoder 26 |
| 632 | // 17: } |
| 633 | 107, 4, // 21: case 0x6b: { |
| 634 | OPC_Decode, 234, 3, 27, // 23: decode to STH32 using decoder 27 |
| 635 | // 23: } |
| 636 | 113, 4, // 27: case 0x71: { |
| 637 | OPC_Decode, 156, 3, 26, // 29: decode to LDB32 using decoder 26 |
| 638 | // 29: } |
| 639 | 115, 4, // 33: case 0x73: { |
| 640 | OPC_Decode, 227, 3, 27, // 35: decode to STB32 using decoder 27 |
| 641 | // 35: } |
| 642 | 195, 1, 107, // 39: case 0xc3: { |
| 643 | OPC_SwitchField, 4, 4, // 42: switch Inst[7:4] { |
| 644 | 0, 24, // 45: case 0x0: { |
| 645 | OPC_Scope, 8, // 47: try { |
| 646 | OPC_CheckField, 0, 4, 1, // 49: check Inst[3:0] == 0x1 |
| 647 | OPC_Decode, 253, 3, 28, // 53: decode to XFADDW32 using decoder 28 |
| 648 | OPC_Scope, 8, // 57: } else try { |
| 649 | OPC_CheckField, 8, 1, 1, // 59: check Inst[8] == 0x1 |
| 650 | OPC_Decode, 167, 3, 26, // 63: decode to LDWACQ32 using decoder 26 |
| 651 | // 63: } else try { |
| 652 | OPC_Decode, 247, 3, 28, // 67: decode to XADDW32 using decoder 28 |
| 653 | // 67: } |
| 654 | // 67: } |
| 655 | 1, 8, // 71: case 0x1: { |
| 656 | OPC_CheckField, 8, 1, 1, // 73: check Inst[8] == 0x1 |
| 657 | OPC_Decode, 239, 3, 27, // 77: decode to STWREL32 using decoder 27 |
| 658 | // 77: } |
| 659 | 4, 14, // 81: case 0x4: { |
| 660 | OPC_Scope, 8, // 83: try { |
| 661 | OPC_CheckField, 0, 4, 1, // 85: check Inst[3:0] == 0x1 |
| 662 | OPC_Decode, 129, 4, 28, // 89: decode to XFORW32 using decoder 28 |
| 663 | // 89: } else try { |
| 664 | OPC_Decode, 133, 4, 28, // 93: decode to XORW32 using decoder 28 |
| 665 | // 93: } |
| 666 | // 93: } |
| 667 | 5, 14, // 97: case 0x5: { |
| 668 | OPC_Scope, 8, // 99: try { |
| 669 | OPC_CheckField, 0, 4, 1, // 101: check Inst[3:0] == 0x1 |
| 670 | OPC_Decode, 255, 3, 28, // 105: decode to XFANDW32 using decoder 28 |
| 671 | // 105: } else try { |
| 672 | OPC_Decode, 249, 3, 28, // 109: decode to XANDW32 using decoder 28 |
| 673 | // 109: } |
| 674 | // 109: } |
| 675 | 10, 14, // 113: case 0xa: { |
| 676 | OPC_Scope, 8, // 115: try { |
| 677 | OPC_CheckField, 0, 4, 1, // 117: check Inst[3:0] == 0x1 |
| 678 | OPC_Decode, 131, 4, 28, // 121: decode to XFXORW32 using decoder 28 |
| 679 | // 121: } else try { |
| 680 | OPC_Decode, 139, 4, 28, // 125: decode to XXORW32 using decoder 28 |
| 681 | // 125: } |
| 682 | // 125: } |
| 683 | 14, 8, // 129: case 0xe: { |
| 684 | OPC_CheckField, 0, 4, 1, // 131: check Inst[3:0] == 0x1 |
| 685 | OPC_Decode, 251, 3, 28, // 135: decode to XCHGW32 using decoder 28 |
| 686 | // 135: } |
| 687 | 15, 0, // 139: case 0xf: { |
| 688 | OPC_CheckField, 0, 4, 1, // 141: check Inst[3:0] == 0x1 |
| 689 | OPC_Decode, 224, 2, 29, // 145: decode to CMPXCHGW32 using decoder 29 |
| 690 | // 145: } |
| 691 | // 145: } // switch Inst[7:4] |
| 692 | // 145: } |
| 693 | 203, 1, 15, // 149: case 0xcb: { |
| 694 | OPC_SwitchField, 4, 5, // 152: switch Inst[8:4] { |
| 695 | 16, 4, // 155: case 0x10: { |
| 696 | OPC_Decode, 163, 3, 26, // 157: decode to LDHACQ32 using decoder 26 |
| 697 | // 157: } |
| 698 | 17, 0, // 161: case 0x11: { |
| 699 | OPC_Decode, 235, 3, 27, // 163: decode to STHREL32 using decoder 27 |
| 700 | // 163: } |
| 701 | // 163: } // switch Inst[8:4] |
| 702 | // 163: } |
| 703 | 211, 1, 0, // 167: case 0xd3: { |
| 704 | OPC_SwitchField, 4, 5, // 170: switch Inst[8:4] { |
| 705 | 16, 4, // 173: case 0x10: { |
| 706 | OPC_Decode, 157, 3, 26, // 175: decode to LDBACQ32 using decoder 26 |
| 707 | // 175: } |
| 708 | 17, 0, // 179: case 0x11: { |
| 709 | OPC_Decode, 228, 3, 27, // 181: decode to STBREL32 using decoder 27 |
| 710 | // 181: } |
| 711 | // 181: } // switch Inst[8:4] |
| 712 | // 181: } |
| 713 | // 181: } // switch Inst[63:56] |
| 714 | }; |
| 715 | // Handling 30 cases. |
| 716 | template <typename InsnType> |
| 717 | static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) { |
| 718 | DecodeComplete = true; |
| 719 | using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>; |
| 720 | TmpType tmp; |
| 721 | switch (Idx) { |
| 722 | default: llvm_unreachable("Invalid decoder index!" ); |
| 723 | case 0: |
| 724 | tmp = fieldFromInstruction(insn, 48, 4); |
| 725 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 726 | tmp = fieldFromInstruction(insn, 48, 4); |
| 727 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 728 | tmp = fieldFromInstruction(insn, 0, 32); |
| 729 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 730 | return S; |
| 731 | case 1: |
| 732 | tmp = fieldFromInstruction(insn, 32, 16); |
| 733 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 734 | return S; |
| 735 | case 2: |
| 736 | tmp = fieldFromInstruction(insn, 0, 32); |
| 737 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 738 | return S; |
| 739 | case 3: |
| 740 | tmp = fieldFromInstruction(insn, 48, 4); |
| 741 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 742 | tmp = fieldFromInstruction(insn, 48, 4); |
| 743 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 744 | tmp = fieldFromInstruction(insn, 0, 32); |
| 745 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 746 | return S; |
| 747 | case 4: |
| 748 | tmp = fieldFromInstruction(insn, 48, 4); |
| 749 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 750 | tmp = fieldFromInstruction(insn, 48, 4); |
| 751 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 752 | tmp = fieldFromInstruction(insn, 52, 4); |
| 753 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 754 | return S; |
| 755 | case 5: |
| 756 | tmp = fieldFromInstruction(insn, 48, 4); |
| 757 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 758 | return S; |
| 759 | case 6: |
| 760 | tmp = fieldFromInstruction(insn, 48, 4); |
| 761 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 762 | tmp = fieldFromInstruction(insn, 48, 4); |
| 763 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 764 | tmp = fieldFromInstruction(insn, 52, 4); |
| 765 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 766 | return S; |
| 767 | case 7: |
| 768 | tmp = fieldFromInstruction(insn, 48, 4); |
| 769 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 770 | tmp = fieldFromInstruction(insn, 0, 32); |
| 771 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 772 | tmp = fieldFromInstruction(insn, 32, 16); |
| 773 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 774 | return S; |
| 775 | case 8: |
| 776 | tmp = fieldFromInstruction(insn, 48, 4); |
| 777 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 778 | tmp = fieldFromInstruction(insn, 0, 32); |
| 779 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 780 | tmp = fieldFromInstruction(insn, 32, 16); |
| 781 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 782 | return S; |
| 783 | case 9: |
| 784 | tmp = fieldFromInstruction(insn, 48, 4); |
| 785 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 786 | tmp = fieldFromInstruction(insn, 0, 32); |
| 787 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 788 | return S; |
| 789 | case 10: |
| 790 | tmp = fieldFromInstruction(insn, 48, 4); |
| 791 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 792 | tmp = fieldFromInstruction(insn, 52, 4); |
| 793 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 794 | tmp = fieldFromInstruction(insn, 0, 32); |
| 795 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 796 | return S; |
| 797 | case 11: |
| 798 | tmp = fieldFromInstruction(insn, 48, 4); |
| 799 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 800 | tmp = fieldFromInstruction(insn, 52, 4); |
| 801 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 802 | tmp = fieldFromInstruction(insn, 32, 16); |
| 803 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 804 | return S; |
| 805 | case 12: |
| 806 | tmp = fieldFromInstruction(insn, 48, 4); |
| 807 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 808 | tmp = fieldFromInstruction(insn, 52, 4); |
| 809 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 810 | tmp = fieldFromInstruction(insn, 32, 16); |
| 811 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 812 | return S; |
| 813 | case 13: |
| 814 | tmp = fieldFromInstruction(insn, 52, 4); |
| 815 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 816 | return S; |
| 817 | case 14: |
| 818 | tmp = fieldFromInstruction(insn, 48, 4); |
| 819 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 820 | tmp = 0x0; |
| 821 | tmp |= fieldFromInstruction(insn, 32, 16); |
| 822 | tmp |= fieldFromInstruction(insn, 52, 4) << 16; |
| 823 | if (!Check(S, decodeMemoryOpValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 824 | return S; |
| 825 | case 15: |
| 826 | tmp = fieldFromInstruction(insn, 0, 32); |
| 827 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 828 | tmp = fieldFromInstruction(insn, 32, 20); |
| 829 | if (!Check(S, decodeMemoryOpValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 830 | return S; |
| 831 | case 16: |
| 832 | tmp = fieldFromInstruction(insn, 52, 4); |
| 833 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 834 | tmp = fieldFromInstruction(insn, 32, 20); |
| 835 | if (!Check(S, decodeMemoryOpValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 836 | return S; |
| 837 | case 17: |
| 838 | tmp = fieldFromInstruction(insn, 48, 4); |
| 839 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 840 | tmp = fieldFromInstruction(insn, 48, 4); |
| 841 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 842 | return S; |
| 843 | case 18: |
| 844 | tmp = fieldFromInstruction(insn, 48, 4); |
| 845 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 846 | tmp = fieldFromInstruction(insn, 48, 4); |
| 847 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 848 | return S; |
| 849 | case 19: |
| 850 | return S; |
| 851 | case 20: |
| 852 | tmp = fieldFromInstruction(insn, 48, 4); |
| 853 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 854 | tmp = fieldFromInstruction(insn, 0, 32); |
| 855 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 856 | return S; |
| 857 | case 21: |
| 858 | tmp = fieldFromInstruction(insn, 48, 4); |
| 859 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 860 | tmp = fieldFromInstruction(insn, 52, 4); |
| 861 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 862 | return S; |
| 863 | case 22: |
| 864 | tmp = fieldFromInstruction(insn, 48, 4); |
| 865 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 866 | tmp = fieldFromInstruction(insn, 52, 4); |
| 867 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 868 | return S; |
| 869 | case 23: |
| 870 | tmp = fieldFromInstruction(insn, 48, 4); |
| 871 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 872 | tmp = fieldFromInstruction(insn, 52, 4); |
| 873 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 874 | tmp = fieldFromInstruction(insn, 16, 16); |
| 875 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 876 | tmp = fieldFromInstruction(insn, 0, 16); |
| 877 | MI.addOperand(Op: MCOperand::createImm(Val: tmp)); |
| 878 | return S; |
| 879 | case 24: |
| 880 | tmp = fieldFromInstruction(insn, 52, 4); |
| 881 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 882 | tmp = fieldFromInstruction(insn, 32, 20); |
| 883 | if (!Check(S, decodeMemoryOpValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 884 | tmp = fieldFromInstruction(insn, 52, 4); |
| 885 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 886 | return S; |
| 887 | case 25: |
| 888 | tmp = fieldFromInstruction(insn, 32, 20); |
| 889 | if (!Check(S, decodeMemoryOpValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 890 | tmp = fieldFromInstruction(insn, 52, 4); |
| 891 | if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 892 | return S; |
| 893 | case 26: |
| 894 | tmp = fieldFromInstruction(insn, 48, 4); |
| 895 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 896 | tmp = 0x0; |
| 897 | tmp |= fieldFromInstruction(insn, 32, 16); |
| 898 | tmp |= fieldFromInstruction(insn, 52, 4) << 16; |
| 899 | if (!Check(S, decodeMemoryOpValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 900 | return S; |
| 901 | case 27: |
| 902 | tmp = fieldFromInstruction(insn, 52, 4); |
| 903 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 904 | tmp = fieldFromInstruction(insn, 32, 20); |
| 905 | if (!Check(S, decodeMemoryOpValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 906 | return S; |
| 907 | case 28: |
| 908 | tmp = fieldFromInstruction(insn, 52, 4); |
| 909 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 910 | tmp = fieldFromInstruction(insn, 32, 20); |
| 911 | if (!Check(S, decodeMemoryOpValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 912 | tmp = fieldFromInstruction(insn, 52, 4); |
| 913 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 914 | return S; |
| 915 | case 29: |
| 916 | tmp = fieldFromInstruction(insn, 32, 20); |
| 917 | if (!Check(S, decodeMemoryOpValue(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 918 | tmp = fieldFromInstruction(insn, 52, 4); |
| 919 | if (!Check(S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 920 | return S; |
| 921 | } |
| 922 | } |
| 923 | |
| 924 | template <typename InsnType> |
| 925 | static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, |
| 926 | InsnType insn, uint64_t Address, |
| 927 | const MCDisassembler *DisAsm, |
| 928 | const MCSubtargetInfo &STI) { |
| 929 | const uint8_t *Ptr = DecodeTable; |
| 930 | |
| 931 | SmallVector<const uint8_t *, 8> ScopeStack; |
| 932 | DecodeStatus S = MCDisassembler::Success; |
| 933 | while (true) { |
| 934 | ptrdiff_t Loc = Ptr - DecodeTable; |
| 935 | const uint8_t DecoderOp = *Ptr++; |
| 936 | switch (DecoderOp) { |
| 937 | default: |
| 938 | errs() << Loc << ": Unexpected decode table opcode: " |
| 939 | << (int)DecoderOp << '\n'; |
| 940 | return MCDisassembler::Fail; |
| 941 | case OPC_Scope: { |
| 942 | unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 943 | const uint8_t *SkipTo = Ptr + NumToSkip; |
| 944 | ScopeStack.push_back(Elt: SkipTo); |
| 945 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope(" << SkipTo - DecodeTable |
| 946 | << ")\n" ); |
| 947 | continue; |
| 948 | } |
| 949 | case OPC_SwitchField: { |
| 950 | // Decode the start value. |
| 951 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 952 | unsigned Len = *Ptr++; |
| 953 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 954 | uint64_t CaseValue; |
| 955 | unsigned CaseSize; |
| 956 | while (true) { |
| 957 | CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 958 | CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 959 | if (FieldValue == CaseValue || !CaseSize) |
| 960 | break; |
| 961 | Ptr += CaseSize; |
| 962 | } |
| 963 | if (FieldValue == CaseValue) { |
| 964 | LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField(" << Start << ", " << Len |
| 965 | << "): " << FieldValue << '\n'); |
| 966 | continue; |
| 967 | } |
| 968 | break; |
| 969 | } |
| 970 | case OPC_CheckField: { |
| 971 | // Decode the start value. |
| 972 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 973 | unsigned Len = *Ptr; |
| 974 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 975 | // Decode the field value. |
| 976 | unsigned PtrLen = 0; |
| 977 | uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen); |
| 978 | Ptr += PtrLen; |
| 979 | bool Failed = ExpectedValue != FieldValue; |
| 980 | |
| 981 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", " << Len |
| 982 | << ", " << ExpectedValue << "): FieldValue = " |
| 983 | << FieldValue << ", ExpectedValue = " << ExpectedValue |
| 984 | << ": " << (Failed ? "FAIL, " : "PASS\n" );); |
| 985 | if (!Failed) |
| 986 | continue; |
| 987 | break; |
| 988 | } |
| 989 | case OPC_Decode: { |
| 990 | // Decode the Opcode value. |
| 991 | unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 992 | unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 993 | |
| 994 | MI.clear(); |
| 995 | MI.setOpcode(Opc); |
| 996 | bool DecodeComplete; |
| 997 | S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm, |
| 998 | DecodeComplete); |
| 999 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc |
| 1000 | << ", using decoder " << DecodeIdx << ": " |
| 1001 | << (S ? "PASS, " : "FAIL, " )); |
| 1002 | |
| 1003 | if (DecodeComplete) { |
| 1004 | LLVM_DEBUG(dbgs() << "decoding complete\n" ); |
| 1005 | return S; |
| 1006 | } |
| 1007 | assert(S == MCDisassembler::Fail); |
| 1008 | // Reset decode status. This also drops a SoftFail status that could be |
| 1009 | // set before the decode attempt. |
| 1010 | S = MCDisassembler::Success; |
| 1011 | break; |
| 1012 | } |
| 1013 | } |
| 1014 | if (ScopeStack.empty()) { |
| 1015 | LLVM_DEBUG(dbgs() << "returning Fail\n" ); |
| 1016 | return MCDisassembler::Fail; |
| 1017 | } |
| 1018 | Ptr = ScopeStack.pop_back_val(); |
| 1019 | LLVM_DEBUG(dbgs() << "continuing at " << Ptr - DecodeTable << '\n'); |
| 1020 | } |
| 1021 | llvm_unreachable("bogosity detected in disassembler state machine!" ); |
| 1022 | } |
| 1023 | |
| 1024 | |
| 1025 | } // namespace |
| 1026 | |