1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::BPF {
13
14 enum {
15 PHI = 0, // Target.td:1324
16 INLINEASM = 1, // Target.td:1330
17 INLINEASM_BR = 2, // Target.td:1336
18 CFI_INSTRUCTION = 3, // Target.td:1345
19 EH_LABEL = 4, // Target.td:1354
20 GC_LABEL = 5, // Target.td:1363
21 ANNOTATION_LABEL = 6, // Target.td:1372
22 KILL = 7, // Target.td:1380
23 EXTRACT_SUBREG = 8, // Target.td:1387
24 INSERT_SUBREG = 9, // Target.td:1393
25 IMPLICIT_DEF = 10, // Target.td:1400
26 INIT_UNDEF = 11, // Target.td:1409
27 SUBREG_TO_REG = 12, // Target.td:1416
28 COPY_TO_REGCLASS = 13, // Target.td:1422
29 DBG_VALUE = 14, // Target.td:1429
30 DBG_VALUE_LIST = 15, // Target.td:1436
31 DBG_INSTR_REF = 16, // Target.td:1443
32 DBG_PHI = 17, // Target.td:1450
33 DBG_LABEL = 18, // Target.td:1457
34 REG_SEQUENCE = 19, // Target.td:1464
35 COPY = 20, // Target.td:1471
36 COPY_LANEMASK = 21, // Target.td:1479
37 BUNDLE = 22, // Target.td:1486
38 LIFETIME_START = 23, // Target.td:1492
39 LIFETIME_END = 24, // Target.td:1499
40 PSEUDO_PROBE = 25, // Target.td:1506
41 ARITH_FENCE = 26, // Target.td:1513
42 STACKMAP = 27, // Target.td:1522
43 FENTRY_CALL = 28, // Target.td:1657
44 PATCHPOINT = 29, // Target.td:1530
45 LOAD_STACK_GUARD = 30, // Target.td:1548
46 PREALLOCATED_SETUP = 31, // Target.td:1556
47 PREALLOCATED_ARG = 32, // Target.td:1562
48 STATEPOINT = 33, // Target.td:1539
49 LOCAL_ESCAPE = 34, // Target.td:1568
50 FAULTING_OP = 35, // Target.td:1577
51 PATCHABLE_OP = 36, // Target.td:1597
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1605
53 PATCHABLE_RET = 38, // Target.td:1612
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1621
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1629
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1637
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1647
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1667
59 FAKE_USE = 44, // Target.td:1587
60 MEMBARRIER = 45, // Target.td:1673
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1681
62 RELOC_NONE = 47, // Target.td:1689
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1701
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1697
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1705
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1709
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1929
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1921
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1936
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1516
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1529
96 G_INSERT = 81, // GenericOpcodes.td:1538
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1548
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1568
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1578
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1585
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1943
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1481
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1482
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1483
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1484
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1485
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1486
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1487
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1488
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1494
150 G_PREFETCH = 135, // GenericOpcodes.td:1501
151 G_BRCOND = 136, // GenericOpcodes.td:1641
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1650
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1673
154 G_INTRINSIC = 139, // GenericOpcodes.td:1593
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1600
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1609
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1617
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1631
265 G_BRJT = 250, // GenericOpcodes.td:1661
266 G_VSCALE = 251, // GenericOpcodes.td:1559
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1705
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1713
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1721
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1729
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1740
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1748
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1756
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1763
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1813
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1814
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1815
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1816
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1817
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1818
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1819
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1820
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1821
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1822
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1680
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1690
318 G_MEMCPY = 303, // GenericOpcodes.td:1828
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1836
320 G_MEMMOVE = 305, // GenericOpcodes.td:1844
321 G_MEMSET = 306, // GenericOpcodes.td:1852
322 G_BZERO = 307, // GenericOpcodes.td:1859
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1866
324 G_TRAP = 309, // GenericOpcodes.td:1876
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1883
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1889
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1779
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1785
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1791
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1792
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1794
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1795
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1796
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1797
335 G_VECREDUCE_ADD = 320, // GenericOpcodes.td:1799
336 G_VECREDUCE_MUL = 321, // GenericOpcodes.td:1800
337 G_VECREDUCE_AND = 322, // GenericOpcodes.td:1801
338 G_VECREDUCE_OR = 323, // GenericOpcodes.td:1802
339 G_VECREDUCE_XOR = 324, // GenericOpcodes.td:1803
340 G_VECREDUCE_SMAX = 325, // GenericOpcodes.td:1804
341 G_VECREDUCE_SMIN = 326, // GenericOpcodes.td:1805
342 G_VECREDUCE_UMAX = 327, // GenericOpcodes.td:1806
343 G_VECREDUCE_UMIN = 328, // GenericOpcodes.td:1807
344 G_SBFX = 329, // GenericOpcodes.td:1901
345 G_UBFX = 330, // GenericOpcodes.td:1909
346 ADJCALLSTACKDOWN = 331, // BPFInstrInfo.td:849
347 ADJCALLSTACKUP = 332, // BPFInstrInfo.td:852
348 FI_ri = 333, // BPFInstrInfo.td:515
349 LDIMM64 = 334, // BPFInstrInfo.td:1425
350 LOAD_STACK_ARG_PSEUDO = 335, // BPFInstrInfo.td:320
351 MEMCPY = 336, // BPFInstrInfo.td:1416
352 STORE_STACK_ARG_IMM_PSEUDO = 337, // BPFInstrInfo.td:330
353 STORE_STACK_ARG_PSEUDO = 338, // BPFInstrInfo.td:326
354 Select = 339, // BPFInstrInfo.td:858
355 Select_32 = 340, // BPFInstrInfo.td:878
356 Select_32_64 = 341, // BPFInstrInfo.td:888
357 Select_64_32 = 342, // BPFInstrInfo.td:868
358 Select_Ri = 343, // BPFInstrInfo.td:863
359 Select_Ri_32 = 344, // BPFInstrInfo.td:883
360 Select_Ri_32_64 = 345, // BPFInstrInfo.td:893
361 Select_Ri_64_32 = 346, // BPFInstrInfo.td:873
362 ADDR_SPACE_CAST = 347, // BPFInstrInfo.td:486
363 ADD_ri = 348, // BPFInstrInfo.td:366
364 ADD_ri_32 = 349, // BPFInstrInfo.td:376
365 ADD_rr = 350, // BPFInstrInfo.td:361
366 ADD_rr_32 = 351, // BPFInstrInfo.td:371
367 AND_ri = 352, // BPFInstrInfo.td:366
368 AND_ri_32 = 353, // BPFInstrInfo.td:376
369 AND_rr = 354, // BPFInstrInfo.td:361
370 AND_rr_32 = 355, // BPFInstrInfo.td:371
371 BE16 = 356, // BPFInstrInfo.td:1225
372 BE32 = 357, // BPFInstrInfo.td:1226
373 BE64 = 358, // BPFInstrInfo.td:1227
374 BSWAP16 = 359, // BPFInstrInfo.td:1218
375 BSWAP32 = 360, // BPFInstrInfo.td:1219
376 BSWAP64 = 361, // BPFInstrInfo.td:1220
377 CMPXCHGD = 362, // BPFInstrInfo.td:1198
378 CMPXCHGW32 = 363, // BPFInstrInfo.td:1194
379 CORE_LD32 = 364, // BPFInstrInfo.td:687
380 CORE_LD64 = 365, // BPFInstrInfo.td:686
381 CORE_SHIFT = 366, // BPFInstrInfo.td:694
382 CORE_ST = 367, // BPFInstrInfo.td:688
383 DIV_ri = 368, // BPFInstrInfo.td:366
384 DIV_ri_32 = 369, // BPFInstrInfo.td:376
385 DIV_rr = 370, // BPFInstrInfo.td:361
386 DIV_rr_32 = 371, // BPFInstrInfo.td:371
387 JAL = 372, // BPFInstrInfo.td:813
388 JALX = 373, // BPFInstrInfo.td:814
389 JCOND = 374, // BPFInstrInfo.td:310
390 JEQ_ri = 375, // BPFInstrInfo.td:292
391 JEQ_ri_32 = 376, // BPFInstrInfo.td:294
392 JEQ_rr = 377, // BPFInstrInfo.td:291
393 JEQ_rr_32 = 378, // BPFInstrInfo.td:293
394 JMP = 379, // BPFInstrInfo.td:807
395 JMPL = 380, // BPFInstrInfo.td:808
396 JNE_ri = 381, // BPFInstrInfo.td:292
397 JNE_ri_32 = 382, // BPFInstrInfo.td:294
398 JNE_rr = 383, // BPFInstrInfo.td:291
399 JNE_rr_32 = 384, // BPFInstrInfo.td:293
400 JSET_ri = 385, // BPFInstrInfo.td:292
401 JSET_ri_32 = 386, // BPFInstrInfo.td:294
402 JSET_rr = 387, // BPFInstrInfo.td:291
403 JSET_rr_32 = 388, // BPFInstrInfo.td:293
404 JSGE_ri = 389, // BPFInstrInfo.td:292
405 JSGE_ri_32 = 390, // BPFInstrInfo.td:294
406 JSGE_rr = 391, // BPFInstrInfo.td:291
407 JSGE_rr_32 = 392, // BPFInstrInfo.td:293
408 JSGT_ri = 393, // BPFInstrInfo.td:292
409 JSGT_ri_32 = 394, // BPFInstrInfo.td:294
410 JSGT_rr = 395, // BPFInstrInfo.td:291
411 JSGT_rr_32 = 396, // BPFInstrInfo.td:293
412 JSLE_ri = 397, // BPFInstrInfo.td:292
413 JSLE_ri_32 = 398, // BPFInstrInfo.td:294
414 JSLE_rr = 399, // BPFInstrInfo.td:291
415 JSLE_rr_32 = 400, // BPFInstrInfo.td:293
416 JSLT_ri = 401, // BPFInstrInfo.td:292
417 JSLT_ri_32 = 402, // BPFInstrInfo.td:294
418 JSLT_rr = 403, // BPFInstrInfo.td:291
419 JSLT_rr_32 = 404, // BPFInstrInfo.td:293
420 JUGE_ri = 405, // BPFInstrInfo.td:292
421 JUGE_ri_32 = 406, // BPFInstrInfo.td:294
422 JUGE_rr = 407, // BPFInstrInfo.td:291
423 JUGE_rr_32 = 408, // BPFInstrInfo.td:293
424 JUGT_ri = 409, // BPFInstrInfo.td:292
425 JUGT_ri_32 = 410, // BPFInstrInfo.td:294
426 JUGT_rr = 411, // BPFInstrInfo.td:291
427 JUGT_rr_32 = 412, // BPFInstrInfo.td:293
428 JULE_ri = 413, // BPFInstrInfo.td:292
429 JULE_ri_32 = 414, // BPFInstrInfo.td:294
430 JULE_rr = 415, // BPFInstrInfo.td:291
431 JULE_rr_32 = 416, // BPFInstrInfo.td:293
432 JULT_ri = 417, // BPFInstrInfo.td:292
433 JULT_ri_32 = 418, // BPFInstrInfo.td:294
434 JULT_rr = 419, // BPFInstrInfo.td:291
435 JULT_rr_32 = 420, // BPFInstrInfo.td:293
436 JX = 421, // BPFInstrInfo.td:314
437 LDB = 422, // BPFInstrInfo.td:705
438 LDB32 = 423, // BPFInstrInfo.td:1353
439 LDBACQ32 = 424, // BPFInstrInfo.td:1358
440 LDBSX = 425, // BPFInstrInfo.td:711
441 LDD = 426, // BPFInstrInfo.td:714
442 LDDACQ = 427, // BPFInstrInfo.td:748
443 LDH = 428, // BPFInstrInfo.td:704
444 LDH32 = 429, // BPFInstrInfo.td:1352
445 LDHACQ32 = 430, // BPFInstrInfo.td:1357
446 LDHSX = 431, // BPFInstrInfo.td:710
447 LDW = 432, // BPFInstrInfo.td:703
448 LDW32 = 433, // BPFInstrInfo.td:1351
449 LDWACQ32 = 434, // BPFInstrInfo.td:1356
450 LDWSX = 435, // BPFInstrInfo.td:709
451 LD_ABS_B = 436, // BPFInstrInfo.td:1262
452 LD_ABS_H = 437, // BPFInstrInfo.td:1263
453 LD_ABS_W = 438, // BPFInstrInfo.td:1264
454 LD_IND_B = 439, // BPFInstrInfo.td:1266
455 LD_IND_H = 440, // BPFInstrInfo.td:1267
456 LD_IND_W = 441, // BPFInstrInfo.td:1268
457 LD_imm64 = 442, // BPFInstrInfo.td:440
458 LD_pseudo = 443, // BPFInstrInfo.td:531
459 LE16 = 444, // BPFInstrInfo.td:1230
460 LE32 = 445, // BPFInstrInfo.td:1231
461 LE64 = 446, // BPFInstrInfo.td:1232
462 MOD_ri = 447, // BPFInstrInfo.td:366
463 MOD_ri_32 = 448, // BPFInstrInfo.td:376
464 MOD_rr = 449, // BPFInstrInfo.td:361
465 MOD_rr_32 = 450, // BPFInstrInfo.td:371
466 MOVSX_rr_16 = 451, // BPFInstrInfo.td:467
467 MOVSX_rr_32 = 452, // BPFInstrInfo.td:471
468 MOVSX_rr_32_16 = 453, // BPFInstrInfo.td:479
469 MOVSX_rr_32_8 = 454, // BPFInstrInfo.td:475
470 MOVSX_rr_8 = 455, // BPFInstrInfo.td:463
471 MOV_32_64 = 456, // BPFInstrInfo.td:1271
472 MOV_ri = 457, // BPFInstrInfo.td:446
473 MOV_ri_32 = 458, // BPFInstrInfo.td:456
474 MOV_rr = 459, // BPFInstrInfo.td:441
475 MOV_rr_32 = 460, // BPFInstrInfo.td:451
476 MUL_ri = 461, // BPFInstrInfo.td:366
477 MUL_ri_32 = 462, // BPFInstrInfo.td:376
478 MUL_rr = 463, // BPFInstrInfo.td:361
479 MUL_rr_32 = 464, // BPFInstrInfo.td:371
480 NEG_32 = 465, // BPFInstrInfo.td:417
481 NEG_64 = 466, // BPFInstrInfo.td:414
482 NOP = 467, // BPFInstrInfo.td:830
483 OR_ri = 468, // BPFInstrInfo.td:366
484 OR_ri_32 = 469, // BPFInstrInfo.td:376
485 OR_rr = 470, // BPFInstrInfo.td:361
486 OR_rr_32 = 471, // BPFInstrInfo.td:371
487 RET = 472, // BPFInstrInfo.td:844
488 SDIV_ri = 473, // BPFInstrInfo.td:366
489 SDIV_ri_32 = 474, // BPFInstrInfo.td:376
490 SDIV_rr = 475, // BPFInstrInfo.td:361
491 SDIV_rr_32 = 476, // BPFInstrInfo.td:371
492 SLL_ri = 477, // BPFInstrInfo.td:366
493 SLL_ri_32 = 478, // BPFInstrInfo.td:376
494 SLL_rr = 479, // BPFInstrInfo.td:361
495 SLL_rr_32 = 480, // BPFInstrInfo.td:371
496 SMOD_ri = 481, // BPFInstrInfo.td:366
497 SMOD_ri_32 = 482, // BPFInstrInfo.td:376
498 SMOD_rr = 483, // BPFInstrInfo.td:361
499 SMOD_rr_32 = 484, // BPFInstrInfo.td:371
500 SRA_ri = 485, // BPFInstrInfo.td:366
501 SRA_ri_32 = 486, // BPFInstrInfo.td:376
502 SRA_rr = 487, // BPFInstrInfo.td:361
503 SRA_rr_32 = 488, // BPFInstrInfo.td:371
504 SRL_ri = 489, // BPFInstrInfo.td:366
505 SRL_ri_32 = 490, // BPFInstrInfo.td:376
506 SRL_rr = 491, // BPFInstrInfo.td:361
507 SRL_rr_32 = 492, // BPFInstrInfo.td:371
508 STB = 493, // BPFInstrInfo.td:571
509 STB32 = 494, // BPFInstrInfo.td:1320
510 STBREL32 = 495, // BPFInstrInfo.td:1325
511 STB_imm = 496, // BPFInstrInfo.td:607
512 STD = 497, // BPFInstrInfo.td:573
513 STDREL = 498, // BPFInstrInfo.td:651
514 STD_imm = 499, // BPFInstrInfo.td:604
515 STH = 500, // BPFInstrInfo.td:570
516 STH32 = 501, // BPFInstrInfo.td:1319
517 STHREL32 = 502, // BPFInstrInfo.td:1324
518 STH_imm = 503, // BPFInstrInfo.td:606
519 STW = 504, // BPFInstrInfo.td:569
520 STW32 = 505, // BPFInstrInfo.td:1318
521 STWREL32 = 506, // BPFInstrInfo.td:1323
522 STW_imm = 507, // BPFInstrInfo.td:605
523 SUB_ri = 508, // BPFInstrInfo.td:366
524 SUB_ri_32 = 509, // BPFInstrInfo.td:376
525 SUB_rr = 510, // BPFInstrInfo.td:361
526 SUB_rr_32 = 511, // BPFInstrInfo.td:371
527 XADDD = 512, // BPFInstrInfo.td:947
528 XADDW = 513, // BPFInstrInfo.td:946
529 XADDW32 = 514, // BPFInstrInfo.td:941
530 XANDD = 515, // BPFInstrInfo.td:948
531 XANDW32 = 516, // BPFInstrInfo.td:942
532 XCHGD = 517, // BPFInstrInfo.td:1154
533 XCHGW32 = 518, // BPFInstrInfo.td:1151
534 XFADDD = 519, // BPFInstrInfo.td:1004
535 XFADDW32 = 520, // BPFInstrInfo.td:997
536 XFANDD = 521, // BPFInstrInfo.td:1006
537 XFANDW32 = 522, // BPFInstrInfo.td:998
538 XFORD = 523, // BPFInstrInfo.td:1007
539 XFORW32 = 524, // BPFInstrInfo.td:999
540 XFXORD = 525, // BPFInstrInfo.td:1008
541 XFXORW32 = 526, // BPFInstrInfo.td:1000
542 XORD = 527, // BPFInstrInfo.td:949
543 XORW32 = 528, // BPFInstrInfo.td:943
544 XOR_ri = 529, // BPFInstrInfo.td:366
545 XOR_ri_32 = 530, // BPFInstrInfo.td:376
546 XOR_rr = 531, // BPFInstrInfo.td:361
547 XOR_rr_32 = 532, // BPFInstrInfo.td:371
548 XXORD = 533, // BPFInstrInfo.td:950
549 XXORW32 = 534, // BPFInstrInfo.td:944
550 INSTRUCTION_LIST_END = 535
551 };
552
553} // namespace llvm::BPF
554
555#endif // GET_INSTRINFO_ENUM
556
557#ifdef GET_INSTRINFO_SCHED_ENUM
558#undef GET_INSTRINFO_SCHED_ENUM
559
560namespace llvm::BPF::Sched {
561
562 enum {
563 NoInstrModel = 0,
564 SCHED_LIST_END = 1
565 };
566
567} // namespace llvm::BPF::Sched
568
569#endif // GET_INSTRINFO_SCHED_ENUM
570
571#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
572
573namespace llvm {
574
575struct BPFInstrTable {
576 MCInstrDesc Insts[535];
577 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
578 MCPhysReg ImplicitOps[14];
579 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
580 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
581 MCOperandInfo OperandInfo[282];
582};
583} // namespace llvm
584
585#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
586
587#ifdef GET_INSTRINFO_MC_DESC
588#undef GET_INSTRINFO_MC_DESC
589
590namespace llvm {
591
592static_assert((sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
593static constexpr unsigned BPFOpInfoBase = (sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) / sizeof(MCOperandInfo);
594
595extern const BPFInstrTable BPFDescs = {
596 {
597 { 534, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORW32
598 { 533, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORD
599 { 532, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr_32
600 { 531, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr
601 { 530, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri_32
602 { 529, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri
603 { 528, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORW32
604 { 527, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORD
605 { 526, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORW32
606 { 525, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORD
607 { 524, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORW32
608 { 523, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORD
609 { 522, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDW32
610 { 521, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDD
611 { 520, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDW32
612 { 519, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDD
613 { 518, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGW32
614 { 517, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGD
615 { 516, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDW32
616 { 515, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDD
617 { 514, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW32
618 { 513, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW
619 { 512, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDD
620 { 511, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr_32
621 { 510, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr
622 { 509, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri_32
623 { 508, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri
624 { 507, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_imm
625 { 506, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWREL32
626 { 505, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW32
627 { 504, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW
628 { 503, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_imm
629 { 502, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STHREL32
630 { 501, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH32
631 { 500, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH
632 { 499, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD_imm
633 { 498, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDREL
634 { 497, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD
635 { 496, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_imm
636 { 495, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STBREL32
637 { 494, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB32
638 { 493, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB
639 { 492, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr_32
640 { 491, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr
641 { 490, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri_32
642 { 489, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri
643 { 488, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr_32
644 { 487, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr
645 { 486, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri_32
646 { 485, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri
647 { 484, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr_32
648 { 483, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr
649 { 482, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri_32
650 { 481, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri
651 { 480, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr_32
652 { 479, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr
653 { 478, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri_32
654 { 477, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri
655 { 476, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr_32
656 { 475, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr
657 { 474, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri_32
658 { 473, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri
659 { 472, 0, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
660 { 471, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr_32
661 { 470, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr
662 { 469, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri_32
663 { 468, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri
664 { 467, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
665 { 466, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_64
666 { 465, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 269, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_32
667 { 464, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr_32
668 { 463, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr
669 { 462, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri_32
670 { 461, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri
671 { 460, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr_32
672 { 459, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr
673 { 458, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 267, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri_32
674 { 457, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri
675 { 456, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 265, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_32_64
676 { 455, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_8
677 { 454, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_8
678 { 453, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_16
679 { 452, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32
680 { 451, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_16
681 { 450, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr_32
682 { 449, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr
683 { 448, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri_32
684 { 447, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri
685 { 446, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE64
686 { 445, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE32
687 { 444, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE16
688 { 443, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_pseudo
689 { 442, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_imm64
690 { 441, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_W
691 { 440, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_H
692 { 439, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_B
693 { 438, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_W
694 { 437, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_H
695 { 436, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_B
696 { 435, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSX
697 { 434, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWACQ32
698 { 433, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW32
699 { 432, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW
700 { 431, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHSX
701 { 430, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHACQ32
702 { 429, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH32
703 { 428, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH
704 { 427, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDDACQ
705 { 426, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDD
706 { 425, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBSX
707 { 424, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBACQ32
708 { 423, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB32
709 { 422, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB
710 { 421, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JX
711 { 420, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr_32
712 { 419, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr
713 { 418, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri_32
714 { 417, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri
715 { 416, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr_32
716 { 415, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr
717 { 414, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri_32
718 { 413, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri
719 { 412, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr_32
720 { 411, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr
721 { 410, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri_32
722 { 409, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri
723 { 408, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr_32
724 { 407, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr
725 { 406, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri_32
726 { 405, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri
727 { 404, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr_32
728 { 403, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr
729 { 402, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri_32
730 { 401, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri
731 { 400, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr_32
732 { 399, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr
733 { 398, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri_32
734 { 397, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri
735 { 396, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr_32
736 { 395, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr
737 { 394, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri_32
738 { 393, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri
739 { 392, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr_32
740 { 391, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr
741 { 390, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri_32
742 { 389, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri
743 { 388, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr_32
744 { 387, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr
745 { 386, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri_32
746 { 385, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri
747 { 384, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr_32
748 { 383, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr
749 { 382, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri_32
750 { 381, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri
751 { 380, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMPL
752 { 379, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
753 { 378, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr_32
754 { 377, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr
755 { 376, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri_32
756 { 375, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri
757 { 374, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCOND
758 { 373, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 28, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JALX
759 { 372, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 0, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JAL
760 { 371, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr_32
761 { 370, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr
762 { 369, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri_32
763 { 368, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri
764 { 367, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 242, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_ST
765 { 366, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 238, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_SHIFT
766 { 365, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 234, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD64
767 { 364, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 230, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD32
768 { 363, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 227, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGW32
769 { 362, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 224, 2, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGD
770 { 361, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP64
771 { 360, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP32
772 { 359, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP16
773 { 358, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE64
774 { 357, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE32
775 { 356, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE16
776 { 355, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr_32
777 { 354, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr
778 { 353, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri_32
779 { 352, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri
780 { 351, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr_32
781 { 350, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr
782 { 349, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri_32
783 { 348, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri
784 { 347, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDR_SPACE_CAST
785 { 346, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 204, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_64_32
786 { 345, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 198, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32_64
787 { 344, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 192, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32
788 { 343, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri
789 { 342, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_64_32
790 { 341, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 174, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32_64
791 { 340, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 168, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32
792 { 339, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select
793 { 338, 2, 0, 8, 0, 0, 0, BPFOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_STACK_ARG_PSEUDO
794 { 337, 2, 0, 8, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_STACK_ARG_IMM_PSEUDO
795 { 336, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY
796 { 335, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_STACK_ARG_PSEUDO
797 { 334, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIMM64
798 { 333, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FI_ri
799 { 332, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
800 { 331, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
801 { 330, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
802 { 329, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
803 { 328, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
804 { 327, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
805 { 326, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
806 { 325, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
807 { 324, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
808 { 323, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
809 { 322, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
810 { 321, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
811 { 320, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
812 { 319, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
813 { 318, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
814 { 317, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
815 { 316, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
816 { 315, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
817 { 314, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
818 { 313, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
819 { 312, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
820 { 311, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
821 { 310, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
822 { 309, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
823 { 308, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
824 { 307, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
825 { 306, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
826 { 305, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
827 { 304, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
828 { 303, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
829 { 302, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
830 { 301, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
831 { 300, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
832 { 299, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
833 { 298, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
834 { 297, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
835 { 296, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
836 { 295, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
837 { 294, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
838 { 293, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
839 { 292, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
840 { 291, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
841 { 290, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
842 { 289, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
843 { 288, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
844 { 287, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
845 { 286, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
846 { 285, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
847 { 284, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
848 { 283, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
849 { 282, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
850 { 281, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
851 { 280, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
852 { 279, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
853 { 278, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
854 { 277, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
855 { 276, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
856 { 275, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
857 { 274, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
858 { 273, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
859 { 272, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
860 { 271, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
861 { 270, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
862 { 269, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
863 { 268, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
864 { 267, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
865 { 266, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
866 { 265, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
867 { 264, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
868 { 263, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
869 { 262, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
870 { 261, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
871 { 260, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
872 { 259, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
873 { 258, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
874 { 257, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
875 { 256, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
876 { 255, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
877 { 254, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
878 { 253, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
879 { 252, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
880 { 251, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
881 { 250, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
882 { 249, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
883 { 248, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
884 { 247, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
885 { 246, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
886 { 245, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
887 { 244, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
888 { 243, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
889 { 242, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
890 { 241, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
891 { 240, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
892 { 239, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
893 { 238, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
894 { 237, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
895 { 236, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
896 { 235, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
897 { 234, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
898 { 233, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
899 { 232, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
900 { 231, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
901 { 230, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
902 { 229, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
903 { 228, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
904 { 227, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
905 { 226, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
906 { 225, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
907 { 224, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
908 { 223, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
909 { 222, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
910 { 221, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
911 { 220, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
912 { 219, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
913 { 218, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
914 { 217, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
915 { 216, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
916 { 215, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
917 { 214, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
918 { 213, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
919 { 212, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
920 { 211, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
921 { 210, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
922 { 209, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
923 { 208, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
924 { 207, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
925 { 206, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
926 { 205, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
927 { 204, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
928 { 203, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
929 { 202, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
930 { 201, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
931 { 200, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
932 { 199, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
933 { 198, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
934 { 197, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
935 { 196, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
936 { 195, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
937 { 194, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
938 { 193, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
939 { 192, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
940 { 191, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
941 { 190, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
942 { 189, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
943 { 188, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
944 { 187, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
945 { 186, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
946 { 185, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
947 { 184, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
948 { 183, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
949 { 182, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
950 { 181, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
951 { 180, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
952 { 179, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
953 { 178, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
954 { 177, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
955 { 176, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
956 { 175, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
957 { 174, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
958 { 173, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
959 { 172, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
960 { 171, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
961 { 170, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
962 { 169, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
963 { 168, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
964 { 167, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
965 { 166, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
966 { 165, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
967 { 164, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
968 { 163, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
969 { 162, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
970 { 161, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
971 { 160, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
972 { 159, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
973 { 158, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
974 { 157, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
975 { 156, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
976 { 155, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
977 { 154, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
978 { 153, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
979 { 152, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
980 { 151, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
981 { 150, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
982 { 149, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
983 { 148, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
984 { 147, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
985 { 146, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
986 { 145, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
987 { 144, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
988 { 143, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
989 { 142, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
990 { 141, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
991 { 140, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
992 { 139, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
993 { 138, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
994 { 137, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
995 { 136, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
996 { 135, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
997 { 134, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
998 { 133, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
999 { 132, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1000 { 131, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1001 { 130, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1002 { 129, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1003 { 128, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1004 { 127, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1005 { 126, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1006 { 125, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1007 { 124, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1008 { 123, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1009 { 122, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1010 { 121, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1011 { 120, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1012 { 119, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1013 { 118, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1014 { 117, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1015 { 116, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1016 { 115, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1017 { 114, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1018 { 113, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1019 { 112, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1020 { 111, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1021 { 110, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1022 { 109, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1023 { 108, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1024 { 107, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1025 { 106, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1026 { 105, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1027 { 104, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1028 { 103, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1029 { 102, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1030 { 101, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1031 { 100, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1032 { 99, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1033 { 98, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1034 { 97, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1035 { 96, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1036 { 95, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1037 { 94, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1038 { 93, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1039 { 92, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1040 { 91, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1041 { 90, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1042 { 89, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1043 { 88, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1044 { 87, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1045 { 86, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1046 { 85, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1047 { 84, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1048 { 83, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1049 { 82, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1050 { 81, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1051 { 80, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1052 { 79, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1053 { 78, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1054 { 77, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1055 { 76, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1056 { 75, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1057 { 74, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1058 { 73, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1059 { 72, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1060 { 71, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1061 { 70, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1062 { 69, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1063 { 68, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1064 { 67, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1065 { 66, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1066 { 65, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1067 { 64, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1068 { 63, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1069 { 62, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1070 { 61, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1071 { 60, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1072 { 59, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1073 { 58, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1074 { 57, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1075 { 56, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1076 { 55, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1077 { 54, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1078 { 53, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1079 { 52, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1080 { 51, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1081 { 50, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1082 { 49, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1083 { 48, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1084 { 47, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1085 { 46, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1086 { 45, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1087 { 44, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1088 { 43, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1089 { 42, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13973
1090 { 41, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13972
1091 { 40, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1092 { 39, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1093 { 38, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1094 { 37, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1095 { 36, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1096 { 35, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1097 { 34, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1098 { 33, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1099 { 32, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13971
1100 { 31, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1101 { 30, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13555
1102 { 29, 6, 1, 0, 0, 0, 0, BPFOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1103 { 28, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1104 { 27, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1105 { 26, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1106 { 25, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1107 { 24, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1108 { 23, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1109 { 22, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1110 { 21, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1111 { 20, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1112 { 19, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1113 { 18, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1114 { 17, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1115 { 16, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1116 { 15, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1117 { 14, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1118 { 13, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1119 { 12, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1120 { 11, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1121 { 10, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1122 { 9, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1123 { 8, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1124 { 7, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1125 { 6, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1126 { 5, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1127 { 4, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1128 { 3, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1129 { 2, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1130 { 1, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1131 { 0, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1132 }, {
1133 /* 0 */
1134 /* 0 */ BPF::R11, BPF::R11,
1135 /* 2 */ BPF::R0, BPF::R0,
1136 /* 4 */ BPF::W0, BPF::W0,
1137 /* 6 */ BPF::R11,
1138 /* 7 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1139 }, {
1140 0
1141 }, {
1142 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1143 /* 1 */
1144 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1145 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1146 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1147 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1148 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1149 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1150 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1151 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1152 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1153 /* 28 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1154 /* 29 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1155 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1156 /* 34 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1157 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1158 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1159 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1160 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1161 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1162 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1163 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1164 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1165 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1166 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1167 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1168 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1169 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1170 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1171 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1172 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1173 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1174 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1175 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1176 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1177 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1178 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1179 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1180 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1181 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1182 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1183 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1184 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1185 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1186 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1187 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1188 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1189 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1190 /* 151 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1191 /* 154 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1192 /* 156 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1193 /* 160 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1194 /* 162 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1195 /* 168 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1196 /* 174 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1197 /* 180 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1198 /* 186 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1199 /* 192 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1200 /* 198 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1201 /* 204 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1202 /* 210 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1203 /* 213 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1204 /* 216 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1205 /* 219 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1206 /* 222 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1207 /* 224 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1208 /* 227 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1209 /* 230 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1210 /* 234 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1211 /* 238 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1212 /* 242 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1213 /* 246 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1214 /* 249 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1215 /* 252 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1216 /* 255 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1217 /* 258 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1218 /* 261 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1219 /* 263 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1220 /* 265 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1221 /* 267 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1222 /* 269 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1223 /* 271 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1224 /* 274 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1225 /* 278 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1226 }
1227};
1228
1229
1230#ifdef __GNUC__
1231#pragma GCC diagnostic push
1232#pragma GCC diagnostic ignored "-Woverlength-strings"
1233#endif
1234extern const char BPFInstrNameData[] = {
1235 /* 0 */ "G_FLOG10\000"
1236 /* 9 */ "G_FEXP10\000"
1237 /* 18 */ "LDB32\000"
1238 /* 24 */ "STB32\000"
1239 /* 30 */ "CORE_LD32\000"
1240 /* 40 */ "BE32\000"
1241 /* 45 */ "LE32\000"
1242 /* 50 */ "LDH32\000"
1243 /* 56 */ "STH32\000"
1244 /* 62 */ "STBREL32\000"
1245 /* 71 */ "STHREL32\000"
1246 /* 80 */ "STWREL32\000"
1247 /* 89 */ "BSWAP32\000"
1248 /* 97 */ "LDBACQ32\000"
1249 /* 106 */ "LDHACQ32\000"
1250 /* 115 */ "LDWACQ32\000"
1251 /* 124 */ "XFADDW32\000"
1252 /* 133 */ "XADDW32\000"
1253 /* 141 */ "LDW32\000"
1254 /* 147 */ "XFANDW32\000"
1255 /* 156 */ "XANDW32\000"
1256 /* 164 */ "CMPXCHGW32\000"
1257 /* 175 */ "XFORW32\000"
1258 /* 183 */ "XFXORW32\000"
1259 /* 192 */ "XXORW32\000"
1260 /* 200 */ "STW32\000"
1261 /* 206 */ "Select_Ri_64_32\000"
1262 /* 222 */ "Select_64_32\000"
1263 /* 235 */ "NEG_32\000"
1264 /* 242 */ "Select_Ri_32\000"
1265 /* 255 */ "SRA_ri_32\000"
1266 /* 265 */ "SUB_ri_32\000"
1267 /* 275 */ "ADD_ri_32\000"
1268 /* 285 */ "AND_ri_32\000"
1269 /* 295 */ "SMOD_ri_32\000"
1270 /* 306 */ "JSGE_ri_32\000"
1271 /* 317 */ "JUGE_ri_32\000"
1272 /* 328 */ "JSLE_ri_32\000"
1273 /* 339 */ "JULE_ri_32\000"
1274 /* 350 */ "JNE_ri_32\000"
1275 /* 360 */ "SLL_ri_32\000"
1276 /* 370 */ "SRL_ri_32\000"
1277 /* 380 */ "MUL_ri_32\000"
1278 /* 390 */ "JEQ_ri_32\000"
1279 /* 400 */ "XOR_ri_32\000"
1280 /* 410 */ "JSET_ri_32\000"
1281 /* 421 */ "JSGT_ri_32\000"
1282 /* 432 */ "JUGT_ri_32\000"
1283 /* 443 */ "JSLT_ri_32\000"
1284 /* 454 */ "JULT_ri_32\000"
1285 /* 465 */ "SDIV_ri_32\000"
1286 /* 476 */ "MOV_ri_32\000"
1287 /* 486 */ "SRA_rr_32\000"
1288 /* 496 */ "SUB_rr_32\000"
1289 /* 506 */ "ADD_rr_32\000"
1290 /* 516 */ "AND_rr_32\000"
1291 /* 526 */ "SMOD_rr_32\000"
1292 /* 537 */ "JSGE_rr_32\000"
1293 /* 548 */ "JUGE_rr_32\000"
1294 /* 559 */ "JSLE_rr_32\000"
1295 /* 570 */ "JULE_rr_32\000"
1296 /* 581 */ "JNE_rr_32\000"
1297 /* 591 */ "SLL_rr_32\000"
1298 /* 601 */ "SRL_rr_32\000"
1299 /* 611 */ "MUL_rr_32\000"
1300 /* 621 */ "JEQ_rr_32\000"
1301 /* 631 */ "XOR_rr_32\000"
1302 /* 641 */ "JSET_rr_32\000"
1303 /* 652 */ "JSGT_rr_32\000"
1304 /* 663 */ "JUGT_rr_32\000"
1305 /* 674 */ "JSLT_rr_32\000"
1306 /* 685 */ "JULT_rr_32\000"
1307 /* 696 */ "SDIV_rr_32\000"
1308 /* 707 */ "MOV_rr_32\000"
1309 /* 717 */ "MOVSX_rr_32\000"
1310 /* 729 */ "Select_32\000"
1311 /* 739 */ "G_FLOG2\000"
1312 /* 747 */ "G_FATAN2\000"
1313 /* 756 */ "G_FEXP2\000"
1314 /* 764 */ "CORE_LD64\000"
1315 /* 774 */ "BE64\000"
1316 /* 779 */ "LE64\000"
1317 /* 784 */ "LDIMM64\000"
1318 /* 792 */ "BSWAP64\000"
1319 /* 800 */ "MOV_32_64\000"
1320 /* 810 */ "Select_Ri_32_64\000"
1321 /* 826 */ "Select_32_64\000"
1322 /* 839 */ "NEG_64\000"
1323 /* 846 */ "LD_imm64\000"
1324 /* 855 */ "BE16\000"
1325 /* 860 */ "LE16\000"
1326 /* 865 */ "BSWAP16\000"
1327 /* 873 */ "MOVSX_rr_32_16\000"
1328 /* 888 */ "MOVSX_rr_16\000"
1329 /* 900 */ "MOVSX_rr_32_8\000"
1330 /* 914 */ "MOVSX_rr_8\000"
1331 /* 925 */ "G_FMA\000"
1332 /* 931 */ "G_STRICT_FMA\000"
1333 /* 944 */ "LDB\000"
1334 /* 948 */ "STB\000"
1335 /* 952 */ "G_FSUB\000"
1336 /* 959 */ "G_STRICT_FSUB\000"
1337 /* 973 */ "G_ATOMICRMW_FSUB\000"
1338 /* 990 */ "G_SUB\000"
1339 /* 996 */ "G_ATOMICRMW_SUB\000"
1340 /* 1012 */ "LD_IND_B\000"
1341 /* 1021 */ "LD_ABS_B\000"
1342 /* 1030 */ "G_INTRINSIC\000"
1343 /* 1042 */ "G_FPTRUNC\000"
1344 /* 1052 */ "G_INTRINSIC_TRUNC\000"
1345 /* 1070 */ "G_TRUNC\000"
1346 /* 1078 */ "G_BUILD_VECTOR_TRUNC\000"
1347 /* 1099 */ "G_DYN_STACKALLOC\000"
1348 /* 1116 */ "G_FMAD\000"
1349 /* 1123 */ "G_FPEXTLOAD\000"
1350 /* 1135 */ "G_INDEXED_SEXTLOAD\000"
1351 /* 1154 */ "G_SEXTLOAD\000"
1352 /* 1165 */ "G_INDEXED_ZEXTLOAD\000"
1353 /* 1184 */ "G_ZEXTLOAD\000"
1354 /* 1195 */ "G_INDEXED_LOAD\000"
1355 /* 1210 */ "G_LOAD\000"
1356 /* 1217 */ "G_VECREDUCE_FADD\000"
1357 /* 1234 */ "G_FADD\000"
1358 /* 1241 */ "G_VECREDUCE_SEQ_FADD\000"
1359 /* 1262 */ "G_STRICT_FADD\000"
1360 /* 1276 */ "G_ATOMICRMW_FADD\000"
1361 /* 1293 */ "G_VECREDUCE_ADD\000"
1362 /* 1309 */ "G_ADD\000"
1363 /* 1315 */ "G_PTR_ADD\000"
1364 /* 1325 */ "G_ATOMICRMW_ADD\000"
1365 /* 1341 */ "XFADDD\000"
1366 /* 1348 */ "XADDD\000"
1367 /* 1354 */ "LDD\000"
1368 /* 1358 */ "XFANDD\000"
1369 /* 1365 */ "XANDD\000"
1370 /* 1371 */ "CMPXCHGD\000"
1371 /* 1380 */ "G_ATOMICRMW_NAND\000"
1372 /* 1397 */ "G_VECREDUCE_AND\000"
1373 /* 1413 */ "G_AND\000"
1374 /* 1419 */ "G_ATOMICRMW_AND\000"
1375 /* 1435 */ "LIFETIME_END\000"
1376 /* 1448 */ "JCOND\000"
1377 /* 1454 */ "G_BRCOND\000"
1378 /* 1463 */ "G_ATOMICRMW_USUB_COND\000"
1379 /* 1485 */ "G_LLROUND\000"
1380 /* 1495 */ "G_LROUND\000"
1381 /* 1504 */ "G_INTRINSIC_ROUND\000"
1382 /* 1522 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1383 /* 1548 */ "LOAD_STACK_GUARD\000"
1384 /* 1565 */ "XFORD\000"
1385 /* 1571 */ "XFXORD\000"
1386 /* 1578 */ "XXORD\000"
1387 /* 1584 */ "STD\000"
1388 /* 1588 */ "PSEUDO_PROBE\000"
1389 /* 1601 */ "G_SSUBE\000"
1390 /* 1609 */ "G_USUBE\000"
1391 /* 1617 */ "G_FENCE\000"
1392 /* 1625 */ "ARITH_FENCE\000"
1393 /* 1637 */ "REG_SEQUENCE\000"
1394 /* 1650 */ "G_SADDE\000"
1395 /* 1658 */ "G_UADDE\000"
1396 /* 1666 */ "G_GET_FPMODE\000"
1397 /* 1679 */ "G_RESET_FPMODE\000"
1398 /* 1694 */ "G_SET_FPMODE\000"
1399 /* 1707 */ "G_FMINNUM_IEEE\000"
1400 /* 1722 */ "G_FMAXNUM_IEEE\000"
1401 /* 1737 */ "G_VSCALE\000"
1402 /* 1746 */ "G_JUMP_TABLE\000"
1403 /* 1759 */ "BUNDLE\000"
1404 /* 1766 */ "G_MEMSET_INLINE\000"
1405 /* 1782 */ "G_MEMCPY_INLINE\000"
1406 /* 1798 */ "RELOC_NONE\000"
1407 /* 1809 */ "LOCAL_ESCAPE\000"
1408 /* 1822 */ "G_FPTRUNCSTORE\000"
1409 /* 1837 */ "G_STACKRESTORE\000"
1410 /* 1852 */ "G_INDEXED_STORE\000"
1411 /* 1868 */ "G_STORE\000"
1412 /* 1876 */ "G_BITREVERSE\000"
1413 /* 1889 */ "FAKE_USE\000"
1414 /* 1898 */ "DBG_VALUE\000"
1415 /* 1908 */ "G_GLOBAL_VALUE\000"
1416 /* 1923 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1417 /* 1946 */ "CONVERGENCECTRL_GLUE\000"
1418 /* 1967 */ "G_STACKSAVE\000"
1419 /* 1979 */ "G_MEMMOVE\000"
1420 /* 1989 */ "G_FREEZE\000"
1421 /* 1998 */ "G_FCANONICALIZE\000"
1422 /* 2014 */ "G_FMODF\000"
1423 /* 2022 */ "INIT_UNDEF\000"
1424 /* 2033 */ "G_IMPLICIT_DEF\000"
1425 /* 2048 */ "DBG_INSTR_REF\000"
1426 /* 2062 */ "G_FNEG\000"
1427 /* 2069 */ "EXTRACT_SUBREG\000"
1428 /* 2084 */ "INSERT_SUBREG\000"
1429 /* 2098 */ "G_SEXT_INREG\000"
1430 /* 2111 */ "SUBREG_TO_REG\000"
1431 /* 2125 */ "G_ATOMIC_CMPXCHG\000"
1432 /* 2142 */ "G_ATOMICRMW_XCHG\000"
1433 /* 2159 */ "G_GET_ROUNDING\000"
1434 /* 2174 */ "G_SET_ROUNDING\000"
1435 /* 2189 */ "G_FLOG\000"
1436 /* 2196 */ "G_VAARG\000"
1437 /* 2204 */ "PREALLOCATED_ARG\000"
1438 /* 2221 */ "G_PREFETCH\000"
1439 /* 2232 */ "LDH\000"
1440 /* 2236 */ "G_SMULH\000"
1441 /* 2244 */ "G_UMULH\000"
1442 /* 2252 */ "G_FTANH\000"
1443 /* 2260 */ "G_FSINH\000"
1444 /* 2268 */ "G_FCOSH\000"
1445 /* 2276 */ "STH\000"
1446 /* 2280 */ "LD_IND_H\000"
1447 /* 2289 */ "LD_ABS_H\000"
1448 /* 2298 */ "DBG_PHI\000"
1449 /* 2306 */ "G_FPTOSI\000"
1450 /* 2315 */ "G_FPTOUI\000"
1451 /* 2324 */ "G_FPOWI\000"
1452 /* 2332 */ "COPY_LANEMASK\000"
1453 /* 2346 */ "G_PTRMASK\000"
1454 /* 2356 */ "JAL\000"
1455 /* 2360 */ "GC_LABEL\000"
1456 /* 2369 */ "DBG_LABEL\000"
1457 /* 2379 */ "EH_LABEL\000"
1458 /* 2388 */ "ANNOTATION_LABEL\000"
1459 /* 2405 */ "ICALL_BRANCH_FUNNEL\000"
1460 /* 2425 */ "STDREL\000"
1461 /* 2432 */ "G_FSHL\000"
1462 /* 2439 */ "G_SHL\000"
1463 /* 2445 */ "G_FCEIL\000"
1464 /* 2453 */ "G_SAVGCEIL\000"
1465 /* 2464 */ "G_UAVGCEIL\000"
1466 /* 2475 */ "PATCHABLE_TAIL_CALL\000"
1467 /* 2495 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1468 /* 2522 */ "PATCHABLE_EVENT_CALL\000"
1469 /* 2543 */ "FENTRY_CALL\000"
1470 /* 2555 */ "KILL\000"
1471 /* 2560 */ "G_CONSTANT_POOL\000"
1472 /* 2576 */ "JMPL\000"
1473 /* 2581 */ "G_ROTL\000"
1474 /* 2588 */ "G_VECREDUCE_FMUL\000"
1475 /* 2605 */ "G_FMUL\000"
1476 /* 2612 */ "G_VECREDUCE_SEQ_FMUL\000"
1477 /* 2633 */ "G_STRICT_FMUL\000"
1478 /* 2647 */ "G_CLMUL\000"
1479 /* 2655 */ "G_VECREDUCE_MUL\000"
1480 /* 2671 */ "G_MUL\000"
1481 /* 2677 */ "G_FREM\000"
1482 /* 2684 */ "G_STRICT_FREM\000"
1483 /* 2698 */ "G_SREM\000"
1484 /* 2705 */ "G_UREM\000"
1485 /* 2712 */ "G_SDIVREM\000"
1486 /* 2722 */ "G_UDIVREM\000"
1487 /* 2732 */ "INLINEASM\000"
1488 /* 2742 */ "G_VECREDUCE_FMINIMUM\000"
1489 /* 2763 */ "G_FMINIMUM\000"
1490 /* 2774 */ "G_ATOMICRMW_FMINIMUM\000"
1491 /* 2795 */ "G_VECREDUCE_FMAXIMUM\000"
1492 /* 2816 */ "G_FMAXIMUM\000"
1493 /* 2827 */ "G_ATOMICRMW_FMAXIMUM\000"
1494 /* 2848 */ "G_FMINIMUMNUM\000"
1495 /* 2862 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1496 /* 2886 */ "G_FMAXIMUMNUM\000"
1497 /* 2900 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1498 /* 2924 */ "G_FMINNUM\000"
1499 /* 2934 */ "G_FMAXNUM\000"
1500 /* 2944 */ "G_FATAN\000"
1501 /* 2952 */ "G_FTAN\000"
1502 /* 2959 */ "G_INTRINSIC_ROUNDEVEN\000"
1503 /* 2981 */ "G_ASSERT_ALIGN\000"
1504 /* 2996 */ "G_FCOPYSIGN\000"
1505 /* 3008 */ "G_VECREDUCE_FMIN\000"
1506 /* 3025 */ "G_ATOMICRMW_FMIN\000"
1507 /* 3042 */ "G_VECREDUCE_SMIN\000"
1508 /* 3059 */ "G_SMIN\000"
1509 /* 3066 */ "G_VECREDUCE_UMIN\000"
1510 /* 3083 */ "G_UMIN\000"
1511 /* 3090 */ "G_ATOMICRMW_UMIN\000"
1512 /* 3107 */ "G_ATOMICRMW_MIN\000"
1513 /* 3123 */ "G_FASIN\000"
1514 /* 3131 */ "G_FSIN\000"
1515 /* 3138 */ "CFI_INSTRUCTION\000"
1516 /* 3154 */ "G_CTLZ_ZERO_POISON\000"
1517 /* 3173 */ "G_CTTZ_ZERO_POISON\000"
1518 /* 3192 */ "ADJCALLSTACKDOWN\000"
1519 /* 3209 */ "G_SSUBO\000"
1520 /* 3217 */ "G_USUBO\000"
1521 /* 3225 */ "G_SADDO\000"
1522 /* 3233 */ "G_UADDO\000"
1523 /* 3241 */ "LOAD_STACK_ARG_PSEUDO\000"
1524 /* 3263 */ "STORE_STACK_ARG_PSEUDO\000"
1525 /* 3286 */ "STORE_STACK_ARG_IMM_PSEUDO\000"
1526 /* 3313 */ "JUMP_TABLE_DEBUG_INFO\000"
1527 /* 3335 */ "G_SMULO\000"
1528 /* 3343 */ "G_UMULO\000"
1529 /* 3351 */ "G_BZERO\000"
1530 /* 3359 */ "STACKMAP\000"
1531 /* 3368 */ "G_DEBUGTRAP\000"
1532 /* 3380 */ "G_UBSANTRAP\000"
1533 /* 3392 */ "G_TRAP\000"
1534 /* 3399 */ "G_ATOMICRMW_UDEC_WRAP\000"
1535 /* 3421 */ "G_ATOMICRMW_UINC_WRAP\000"
1536 /* 3443 */ "G_BSWAP\000"
1537 /* 3451 */ "G_SITOFP\000"
1538 /* 3460 */ "G_UITOFP\000"
1539 /* 3469 */ "G_FCMP\000"
1540 /* 3476 */ "G_STRICT_FCMP\000"
1541 /* 3490 */ "G_ICMP\000"
1542 /* 3497 */ "G_SCMP\000"
1543 /* 3504 */ "G_UCMP\000"
1544 /* 3511 */ "JMP\000"
1545 /* 3515 */ "NOP\000"
1546 /* 3519 */ "CONVERGENCECTRL_LOOP\000"
1547 /* 3540 */ "G_CTPOP\000"
1548 /* 3548 */ "PATCHABLE_OP\000"
1549 /* 3561 */ "FAULTING_OP\000"
1550 /* 3573 */ "ADJCALLSTACKUP\000"
1551 /* 3588 */ "PREALLOCATED_SETUP\000"
1552 /* 3607 */ "G_FLDEXP\000"
1553 /* 3616 */ "G_STRICT_FLDEXP\000"
1554 /* 3632 */ "G_FEXP\000"
1555 /* 3639 */ "G_FFREXP\000"
1556 /* 3648 */ "LDDACQ\000"
1557 /* 3655 */ "G_BR\000"
1558 /* 3660 */ "INLINEASM_BR\000"
1559 /* 3673 */ "G_BLOCK_ADDR\000"
1560 /* 3686 */ "MEMBARRIER\000"
1561 /* 3697 */ "G_CONSTANT_FOLD_BARRIER\000"
1562 /* 3721 */ "PATCHABLE_FUNCTION_ENTER\000"
1563 /* 3746 */ "G_READCYCLECOUNTER\000"
1564 /* 3765 */ "G_READSTEADYCOUNTER\000"
1565 /* 3785 */ "G_READ_REGISTER\000"
1566 /* 3801 */ "G_WRITE_REGISTER\000"
1567 /* 3818 */ "G_ASHR\000"
1568 /* 3825 */ "G_FSHR\000"
1569 /* 3832 */ "G_LSHR\000"
1570 /* 3839 */ "CONVERGENCECTRL_ANCHOR\000"
1571 /* 3862 */ "G_FFLOOR\000"
1572 /* 3871 */ "G_SAVGFLOOR\000"
1573 /* 3883 */ "G_UAVGFLOOR\000"
1574 /* 3895 */ "G_EXTRACT_SUBVECTOR\000"
1575 /* 3915 */ "G_INSERT_SUBVECTOR\000"
1576 /* 3934 */ "G_BUILD_VECTOR\000"
1577 /* 3949 */ "G_SHUFFLE_VECTOR\000"
1578 /* 3966 */ "G_STEP_VECTOR\000"
1579 /* 3980 */ "G_SPLAT_VECTOR\000"
1580 /* 3995 */ "G_VECREDUCE_XOR\000"
1581 /* 4011 */ "G_XOR\000"
1582 /* 4017 */ "G_ATOMICRMW_XOR\000"
1583 /* 4033 */ "G_VECREDUCE_OR\000"
1584 /* 4048 */ "G_OR\000"
1585 /* 4053 */ "G_ATOMICRMW_OR\000"
1586 /* 4068 */ "G_ROTR\000"
1587 /* 4075 */ "G_INTTOPTR\000"
1588 /* 4086 */ "G_FABS\000"
1589 /* 4093 */ "G_ABS\000"
1590 /* 4099 */ "G_ABDS\000"
1591 /* 4106 */ "G_UNMERGE_VALUES\000"
1592 /* 4123 */ "G_MERGE_VALUES\000"
1593 /* 4138 */ "G_CTLS\000"
1594 /* 4145 */ "G_FACOS\000"
1595 /* 4153 */ "G_FCOS\000"
1596 /* 4160 */ "G_FSINCOS\000"
1597 /* 4170 */ "G_STRICT_FCMPS\000"
1598 /* 4185 */ "G_CONCAT_VECTORS\000"
1599 /* 4202 */ "COPY_TO_REGCLASS\000"
1600 /* 4219 */ "G_IS_FPCLASS\000"
1601 /* 4232 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1602 /* 4262 */ "G_VECTOR_COMPRESS\000"
1603 /* 4280 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1604 /* 4307 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1605 /* 4345 */ "G_TRUNC_SSAT_S\000"
1606 /* 4360 */ "G_SSUBSAT\000"
1607 /* 4370 */ "G_USUBSAT\000"
1608 /* 4380 */ "G_SADDSAT\000"
1609 /* 4390 */ "G_UADDSAT\000"
1610 /* 4400 */ "G_SSHLSAT\000"
1611 /* 4410 */ "G_USHLSAT\000"
1612 /* 4420 */ "G_SMULFIXSAT\000"
1613 /* 4433 */ "G_UMULFIXSAT\000"
1614 /* 4446 */ "G_SDIVFIXSAT\000"
1615 /* 4459 */ "G_UDIVFIXSAT\000"
1616 /* 4472 */ "G_ATOMICRMW_USUB_SAT\000"
1617 /* 4493 */ "G_FPTOSI_SAT\000"
1618 /* 4506 */ "G_FPTOUI_SAT\000"
1619 /* 4519 */ "G_EXTRACT\000"
1620 /* 4529 */ "G_SELECT\000"
1621 /* 4538 */ "G_BRINDIRECT\000"
1622 /* 4551 */ "PATCHABLE_RET\000"
1623 /* 4565 */ "G_MEMSET\000"
1624 /* 4574 */ "CORE_SHIFT\000"
1625 /* 4585 */ "PATCHABLE_FUNCTION_EXIT\000"
1626 /* 4609 */ "G_BRJT\000"
1627 /* 4616 */ "G_EXTRACT_VECTOR_ELT\000"
1628 /* 4637 */ "G_INSERT_VECTOR_ELT\000"
1629 /* 4657 */ "G_FCONSTANT\000"
1630 /* 4669 */ "G_CONSTANT\000"
1631 /* 4680 */ "G_INTRINSIC_CONVERGENT\000"
1632 /* 4703 */ "STATEPOINT\000"
1633 /* 4714 */ "PATCHPOINT\000"
1634 /* 4725 */ "G_PTRTOINT\000"
1635 /* 4736 */ "G_FRINT\000"
1636 /* 4744 */ "G_INTRINSIC_LLRINT\000"
1637 /* 4763 */ "G_INTRINSIC_LRINT\000"
1638 /* 4781 */ "G_FNEARBYINT\000"
1639 /* 4794 */ "G_VASTART\000"
1640 /* 4804 */ "LIFETIME_START\000"
1641 /* 4819 */ "G_INVOKE_REGION_START\000"
1642 /* 4841 */ "G_INSERT\000"
1643 /* 4850 */ "G_FSQRT\000"
1644 /* 4858 */ "G_STRICT_FSQRT\000"
1645 /* 4873 */ "G_BITCAST\000"
1646 /* 4883 */ "G_ADDRSPACE_CAST\000"
1647 /* 4900 */ "ADDR_SPACE_CAST\000"
1648 /* 4916 */ "DBG_VALUE_LIST\000"
1649 /* 4931 */ "CORE_ST\000"
1650 /* 4939 */ "G_FPEXT\000"
1651 /* 4947 */ "G_SEXT\000"
1652 /* 4954 */ "G_ASSERT_SEXT\000"
1653 /* 4968 */ "G_ANYEXT\000"
1654 /* 4977 */ "G_ZEXT\000"
1655 /* 4984 */ "G_ASSERT_ZEXT\000"
1656 /* 4998 */ "G_ABDU\000"
1657 /* 5005 */ "G_TRUNC_SSAT_U\000"
1658 /* 5020 */ "G_TRUNC_USAT_U\000"
1659 /* 5035 */ "G_FDIV\000"
1660 /* 5042 */ "G_STRICT_FDIV\000"
1661 /* 5056 */ "G_SDIV\000"
1662 /* 5063 */ "G_UDIV\000"
1663 /* 5070 */ "G_GET_FPENV\000"
1664 /* 5082 */ "G_RESET_FPENV\000"
1665 /* 5096 */ "G_SET_FPENV\000"
1666 /* 5108 */ "XADDW\000"
1667 /* 5114 */ "LDW\000"
1668 /* 5118 */ "G_FPOW\000"
1669 /* 5125 */ "STW\000"
1670 /* 5129 */ "LD_IND_W\000"
1671 /* 5138 */ "LD_ABS_W\000"
1672 /* 5147 */ "G_VECREDUCE_FMAX\000"
1673 /* 5164 */ "G_ATOMICRMW_FMAX\000"
1674 /* 5181 */ "G_VECREDUCE_SMAX\000"
1675 /* 5198 */ "G_SMAX\000"
1676 /* 5205 */ "G_VECREDUCE_UMAX\000"
1677 /* 5222 */ "G_UMAX\000"
1678 /* 5229 */ "G_ATOMICRMW_UMAX\000"
1679 /* 5246 */ "G_ATOMICRMW_MAX\000"
1680 /* 5262 */ "G_FRAME_INDEX\000"
1681 /* 5276 */ "G_SBFX\000"
1682 /* 5283 */ "G_UBFX\000"
1683 /* 5290 */ "G_SMULFIX\000"
1684 /* 5300 */ "G_UMULFIX\000"
1685 /* 5310 */ "G_SDIVFIX\000"
1686 /* 5320 */ "G_UDIVFIX\000"
1687 /* 5330 */ "JX\000"
1688 /* 5333 */ "JALX\000"
1689 /* 5338 */ "LDBSX\000"
1690 /* 5344 */ "LDHSX\000"
1691 /* 5350 */ "LDWSX\000"
1692 /* 5356 */ "G_MEMCPY\000"
1693 /* 5365 */ "COPY\000"
1694 /* 5370 */ "CONVERGENCECTRL_ENTRY\000"
1695 /* 5392 */ "G_CTLZ\000"
1696 /* 5399 */ "G_CTTZ\000"
1697 /* 5406 */ "Select_Ri\000"
1698 /* 5416 */ "SRA_ri\000"
1699 /* 5423 */ "SUB_ri\000"
1700 /* 5430 */ "ADD_ri\000"
1701 /* 5437 */ "AND_ri\000"
1702 /* 5444 */ "SMOD_ri\000"
1703 /* 5452 */ "JSGE_ri\000"
1704 /* 5460 */ "JUGE_ri\000"
1705 /* 5468 */ "JSLE_ri\000"
1706 /* 5476 */ "JULE_ri\000"
1707 /* 5484 */ "JNE_ri\000"
1708 /* 5491 */ "FI_ri\000"
1709 /* 5497 */ "SLL_ri\000"
1710 /* 5504 */ "SRL_ri\000"
1711 /* 5511 */ "MUL_ri\000"
1712 /* 5518 */ "JEQ_ri\000"
1713 /* 5525 */ "XOR_ri\000"
1714 /* 5532 */ "JSET_ri\000"
1715 /* 5540 */ "JSGT_ri\000"
1716 /* 5548 */ "JUGT_ri\000"
1717 /* 5556 */ "JSLT_ri\000"
1718 /* 5564 */ "JULT_ri\000"
1719 /* 5572 */ "SDIV_ri\000"
1720 /* 5580 */ "MOV_ri\000"
1721 /* 5587 */ "STB_imm\000"
1722 /* 5595 */ "STD_imm\000"
1723 /* 5603 */ "STH_imm\000"
1724 /* 5611 */ "STW_imm\000"
1725 /* 5619 */ "LD_pseudo\000"
1726 /* 5629 */ "SRA_rr\000"
1727 /* 5636 */ "SUB_rr\000"
1728 /* 5643 */ "ADD_rr\000"
1729 /* 5650 */ "AND_rr\000"
1730 /* 5657 */ "SMOD_rr\000"
1731 /* 5665 */ "JSGE_rr\000"
1732 /* 5673 */ "JUGE_rr\000"
1733 /* 5681 */ "JSLE_rr\000"
1734 /* 5689 */ "JULE_rr\000"
1735 /* 5697 */ "JNE_rr\000"
1736 /* 5704 */ "SLL_rr\000"
1737 /* 5711 */ "SRL_rr\000"
1738 /* 5718 */ "MUL_rr\000"
1739 /* 5725 */ "JEQ_rr\000"
1740 /* 5732 */ "XOR_rr\000"
1741 /* 5739 */ "JSET_rr\000"
1742 /* 5747 */ "JSGT_rr\000"
1743 /* 5755 */ "JUGT_rr\000"
1744 /* 5763 */ "JSLT_rr\000"
1745 /* 5771 */ "JULT_rr\000"
1746 /* 5779 */ "SDIV_rr\000"
1747 /* 5787 */ "MOV_rr\000"
1748 /* 5794 */ "Select\000"
1749};
1750#ifdef __GNUC__
1751#pragma GCC diagnostic pop
1752#endif
1753
1754extern const unsigned BPFInstrNameIndices[] = {
1755 2302U, 2732U, 3660U, 3138U, 2379U, 2360U, 2388U, 2555U,
1756 2069U, 2084U, 2035U, 2022U, 2111U, 4202U, 1898U, 4916U,
1757 2048U, 2298U, 2369U, 1637U, 5365U, 2332U, 1759U, 4804U,
1758 1435U, 1588U, 1625U, 3359U, 2543U, 4714U, 1548U, 3588U,
1759 2204U, 4703U, 1809U, 3561U, 3548U, 3721U, 4551U, 4585U,
1760 2475U, 2522U, 2495U, 2405U, 1889U, 3686U, 3313U, 1798U,
1761 5370U, 3839U, 3519U, 1946U, 4954U, 4984U, 2981U, 1309U,
1762 990U, 2671U, 5056U, 5063U, 2698U, 2705U, 2712U, 2722U,
1763 1413U, 4048U, 4011U, 4099U, 4998U, 3883U, 2464U, 3871U,
1764 2453U, 2033U, 2300U, 5262U, 1908U, 1923U, 2560U, 4519U,
1765 4106U, 4841U, 4123U, 3934U, 1078U, 4185U, 4725U, 4075U,
1766 4873U, 1989U, 3697U, 1522U, 1052U, 1504U, 4763U, 4744U,
1767 2959U, 3746U, 3765U, 1210U, 1154U, 1184U, 1123U, 1195U,
1768 1135U, 1165U, 1868U, 1822U, 1852U, 4232U, 2125U, 2142U,
1769 1325U, 996U, 1419U, 1380U, 4053U, 4017U, 5246U, 3107U,
1770 5229U, 3090U, 1276U, 973U, 5164U, 3025U, 2827U, 2774U,
1771 2900U, 2862U, 3421U, 3399U, 1463U, 4472U, 1617U, 2221U,
1772 1454U, 4538U, 4819U, 1030U, 4280U, 4680U, 4307U, 4968U,
1773 1070U, 4345U, 5005U, 5020U, 4669U, 4657U, 4794U, 2196U,
1774 4947U, 2098U, 4977U, 2439U, 3832U, 3818U, 2432U, 3825U,
1775 4068U, 2581U, 3490U, 3469U, 3497U, 3504U, 4529U, 3233U,
1776 1658U, 3217U, 1609U, 3225U, 1650U, 3209U, 1601U, 3343U,
1777 3335U, 2244U, 2236U, 4390U, 4380U, 4370U, 4360U, 4410U,
1778 4400U, 5290U, 5300U, 4420U, 4433U, 5310U, 5320U, 4446U,
1779 4459U, 1234U, 952U, 2605U, 925U, 1116U, 5035U, 2677U,
1780 2014U, 5118U, 2324U, 3632U, 756U, 9U, 2189U, 739U,
1781 0U, 3607U, 3639U, 2062U, 4939U, 1042U, 2306U, 2315U,
1782 3451U, 3460U, 4493U, 4506U, 4086U, 2996U, 4219U, 1998U,
1783 2924U, 2934U, 1707U, 1722U, 2763U, 2816U, 2848U, 2886U,
1784 5070U, 5096U, 5082U, 1666U, 1694U, 1679U, 2159U, 2174U,
1785 1315U, 2346U, 3059U, 5198U, 3083U, 5222U, 4093U, 1495U,
1786 1485U, 3655U, 4609U, 1737U, 3915U, 3895U, 4637U, 4616U,
1787 3949U, 3980U, 3966U, 4262U, 5399U, 3173U, 5392U, 3154U,
1788 4138U, 3540U, 3443U, 1876U, 2647U, 2445U, 4153U, 3131U,
1789 4160U, 2952U, 4145U, 3123U, 2944U, 747U, 2268U, 2260U,
1790 2252U, 4850U, 3862U, 4736U, 4781U, 4883U, 3673U, 1746U,
1791 1099U, 1967U, 1837U, 1262U, 959U, 2633U, 5042U, 2684U,
1792 931U, 4858U, 3616U, 3476U, 4170U, 3785U, 3801U, 5356U,
1793 1782U, 1979U, 4565U, 3351U, 1766U, 3392U, 3368U, 3380U,
1794 1241U, 2612U, 1217U, 2588U, 5147U, 3008U, 2795U, 2742U,
1795 1293U, 2655U, 1397U, 4033U, 3995U, 5181U, 3042U, 5205U,
1796 3066U, 5276U, 5283U, 3192U, 3573U, 5491U, 784U, 3241U,
1797 5358U, 3286U, 3263U, 5794U, 729U, 826U, 222U, 5406U,
1798 242U, 810U, 206U, 4900U, 5430U, 275U, 5643U, 506U,
1799 5437U, 285U, 5650U, 516U, 855U, 40U, 774U, 865U,
1800 89U, 792U, 1371U, 164U, 30U, 764U, 4574U, 4931U,
1801 5573U, 466U, 5780U, 697U, 2356U, 5333U, 1448U, 5518U,
1802 390U, 5725U, 621U, 3511U, 2576U, 5484U, 350U, 5697U,
1803 581U, 5532U, 410U, 5739U, 641U, 5452U, 306U, 5665U,
1804 537U, 5540U, 421U, 5747U, 652U, 5468U, 328U, 5681U,
1805 559U, 5556U, 443U, 5763U, 674U, 5460U, 317U, 5673U,
1806 548U, 5548U, 432U, 5755U, 663U, 5476U, 339U, 5689U,
1807 570U, 5564U, 454U, 5771U, 685U, 5330U, 944U, 18U,
1808 97U, 5338U, 1354U, 3648U, 2232U, 50U, 106U, 5344U,
1809 5114U, 141U, 115U, 5350U, 1021U, 2289U, 5138U, 1012U,
1810 2280U, 5129U, 846U, 5619U, 860U, 45U, 779U, 5445U,
1811 296U, 5658U, 527U, 888U, 717U, 873U, 900U, 914U,
1812 800U, 5580U, 476U, 5787U, 707U, 5511U, 380U, 5718U,
1813 611U, 235U, 839U, 3515U, 5526U, 401U, 5733U, 632U,
1814 4561U, 5572U, 465U, 5779U, 696U, 5497U, 360U, 5704U,
1815 591U, 5444U, 295U, 5657U, 526U, 5416U, 255U, 5629U,
1816 486U, 5504U, 370U, 5711U, 601U, 948U, 24U, 62U,
1817 5587U, 1584U, 2425U, 5595U, 2276U, 56U, 71U, 5603U,
1818 5125U, 200U, 80U, 5611U, 5423U, 265U, 5636U, 496U,
1819 1348U, 5108U, 133U, 1365U, 156U, 1374U, 167U, 1341U,
1820 124U, 1358U, 147U, 1565U, 175U, 1571U, 183U, 1573U,
1821 185U, 5525U, 400U, 5732U, 631U, 1578U, 192U,
1822};
1823
1824static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
1825 II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 535, nullptr, 0);
1826}
1827
1828
1829} // namespace llvm
1830
1831#endif // GET_INSTRINFO_MC_DESC
1832
1833#ifdef GET_INSTRINFO_HEADER
1834#undef GET_INSTRINFO_HEADER
1835
1836namespace llvm {
1837
1838struct BPFGenInstrInfo : public TargetInstrInfo {
1839 explicit BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1840 ~BPFGenInstrInfo() override = default;
1841};
1842
1843} // namespace llvm
1844
1845namespace llvm::BPF {
1846
1847
1848} // namespace llvm::BPF
1849
1850#endif // GET_INSTRINFO_HEADER
1851
1852#ifdef GET_INSTRINFO_HELPER_DECLS
1853#undef GET_INSTRINFO_HELPER_DECLS
1854
1855
1856#endif // GET_INSTRINFO_HELPER_DECLS
1857
1858#ifdef GET_INSTRINFO_HELPERS
1859#undef GET_INSTRINFO_HELPERS
1860
1861
1862#endif // GET_INSTRINFO_HELPERS
1863
1864#ifdef GET_INSTRINFO_CTOR_DTOR
1865#undef GET_INSTRINFO_CTOR_DTOR
1866
1867namespace llvm {
1868
1869extern const BPFInstrTable BPFDescs;
1870extern const unsigned BPFInstrNameIndices[];
1871extern const char BPFInstrNameData[];
1872BPFGenInstrInfo::BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1873 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1874 InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 535);
1875}
1876
1877} // namespace llvm
1878
1879#endif // GET_INSTRINFO_CTOR_DTOR
1880
1881#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1882#undef GET_INSTRINFO_MC_HELPER_DECLS
1883
1884namespace llvm {
1885
1886class MCInst;
1887class FeatureBitset;
1888
1889namespace BPF_MC {
1890
1891void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1892
1893} // namespace BPF_MC
1894
1895} // namespace llvm
1896
1897#endif // GET_INSTRINFO_MC_HELPER_DECLS
1898
1899#ifdef GET_INSTRINFO_MC_HELPERS
1900#undef GET_INSTRINFO_MC_HELPERS
1901
1902namespace llvm::BPF_MC {
1903
1904
1905} // namespace llvm::BPF_MC
1906
1907#endif // GET_INSTRINFO_MC_HELPERS
1908
1909#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1910 defined(GET_AVAILABLE_OPCODE_CHECKER)
1911#define GET_COMPUTE_FEATURES
1912#endif
1913#ifdef GET_COMPUTE_FEATURES
1914#undef GET_COMPUTE_FEATURES
1915
1916namespace llvm::BPF_MC {
1917
1918// Bits for subtarget features that participate in instruction matching.
1919enum SubtargetFeatureBits : uint8_t {
1920};
1921
1922inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1923 FeatureBitset Features;
1924 return Features;
1925}
1926
1927inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1928 enum : uint8_t {
1929 CEFBS_None,
1930 };
1931
1932 static constexpr FeatureBitset FeatureBitsets[] = {
1933 {}, // CEFBS_None
1934 };
1935 static constexpr uint8_t RequiredFeaturesRefs[] = {
1936 CEFBS_None, // PHI
1937 CEFBS_None, // INLINEASM
1938 CEFBS_None, // INLINEASM_BR
1939 CEFBS_None, // CFI_INSTRUCTION
1940 CEFBS_None, // EH_LABEL
1941 CEFBS_None, // GC_LABEL
1942 CEFBS_None, // ANNOTATION_LABEL
1943 CEFBS_None, // KILL
1944 CEFBS_None, // EXTRACT_SUBREG
1945 CEFBS_None, // INSERT_SUBREG
1946 CEFBS_None, // IMPLICIT_DEF
1947 CEFBS_None, // INIT_UNDEF
1948 CEFBS_None, // SUBREG_TO_REG
1949 CEFBS_None, // COPY_TO_REGCLASS
1950 CEFBS_None, // DBG_VALUE
1951 CEFBS_None, // DBG_VALUE_LIST
1952 CEFBS_None, // DBG_INSTR_REF
1953 CEFBS_None, // DBG_PHI
1954 CEFBS_None, // DBG_LABEL
1955 CEFBS_None, // REG_SEQUENCE
1956 CEFBS_None, // COPY
1957 CEFBS_None, // COPY_LANEMASK
1958 CEFBS_None, // BUNDLE
1959 CEFBS_None, // LIFETIME_START
1960 CEFBS_None, // LIFETIME_END
1961 CEFBS_None, // PSEUDO_PROBE
1962 CEFBS_None, // ARITH_FENCE
1963 CEFBS_None, // STACKMAP
1964 CEFBS_None, // FENTRY_CALL
1965 CEFBS_None, // PATCHPOINT
1966 CEFBS_None, // LOAD_STACK_GUARD
1967 CEFBS_None, // PREALLOCATED_SETUP
1968 CEFBS_None, // PREALLOCATED_ARG
1969 CEFBS_None, // STATEPOINT
1970 CEFBS_None, // LOCAL_ESCAPE
1971 CEFBS_None, // FAULTING_OP
1972 CEFBS_None, // PATCHABLE_OP
1973 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1974 CEFBS_None, // PATCHABLE_RET
1975 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1976 CEFBS_None, // PATCHABLE_TAIL_CALL
1977 CEFBS_None, // PATCHABLE_EVENT_CALL
1978 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1979 CEFBS_None, // ICALL_BRANCH_FUNNEL
1980 CEFBS_None, // FAKE_USE
1981 CEFBS_None, // MEMBARRIER
1982 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1983 CEFBS_None, // RELOC_NONE
1984 CEFBS_None, // CONVERGENCECTRL_ENTRY
1985 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1986 CEFBS_None, // CONVERGENCECTRL_LOOP
1987 CEFBS_None, // CONVERGENCECTRL_GLUE
1988 CEFBS_None, // G_ASSERT_SEXT
1989 CEFBS_None, // G_ASSERT_ZEXT
1990 CEFBS_None, // G_ASSERT_ALIGN
1991 CEFBS_None, // G_ADD
1992 CEFBS_None, // G_SUB
1993 CEFBS_None, // G_MUL
1994 CEFBS_None, // G_SDIV
1995 CEFBS_None, // G_UDIV
1996 CEFBS_None, // G_SREM
1997 CEFBS_None, // G_UREM
1998 CEFBS_None, // G_SDIVREM
1999 CEFBS_None, // G_UDIVREM
2000 CEFBS_None, // G_AND
2001 CEFBS_None, // G_OR
2002 CEFBS_None, // G_XOR
2003 CEFBS_None, // G_ABDS
2004 CEFBS_None, // G_ABDU
2005 CEFBS_None, // G_UAVGFLOOR
2006 CEFBS_None, // G_UAVGCEIL
2007 CEFBS_None, // G_SAVGFLOOR
2008 CEFBS_None, // G_SAVGCEIL
2009 CEFBS_None, // G_IMPLICIT_DEF
2010 CEFBS_None, // G_PHI
2011 CEFBS_None, // G_FRAME_INDEX
2012 CEFBS_None, // G_GLOBAL_VALUE
2013 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2014 CEFBS_None, // G_CONSTANT_POOL
2015 CEFBS_None, // G_EXTRACT
2016 CEFBS_None, // G_UNMERGE_VALUES
2017 CEFBS_None, // G_INSERT
2018 CEFBS_None, // G_MERGE_VALUES
2019 CEFBS_None, // G_BUILD_VECTOR
2020 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2021 CEFBS_None, // G_CONCAT_VECTORS
2022 CEFBS_None, // G_PTRTOINT
2023 CEFBS_None, // G_INTTOPTR
2024 CEFBS_None, // G_BITCAST
2025 CEFBS_None, // G_FREEZE
2026 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2027 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2028 CEFBS_None, // G_INTRINSIC_TRUNC
2029 CEFBS_None, // G_INTRINSIC_ROUND
2030 CEFBS_None, // G_INTRINSIC_LRINT
2031 CEFBS_None, // G_INTRINSIC_LLRINT
2032 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2033 CEFBS_None, // G_READCYCLECOUNTER
2034 CEFBS_None, // G_READSTEADYCOUNTER
2035 CEFBS_None, // G_LOAD
2036 CEFBS_None, // G_SEXTLOAD
2037 CEFBS_None, // G_ZEXTLOAD
2038 CEFBS_None, // G_FPEXTLOAD
2039 CEFBS_None, // G_INDEXED_LOAD
2040 CEFBS_None, // G_INDEXED_SEXTLOAD
2041 CEFBS_None, // G_INDEXED_ZEXTLOAD
2042 CEFBS_None, // G_STORE
2043 CEFBS_None, // G_FPTRUNCSTORE
2044 CEFBS_None, // G_INDEXED_STORE
2045 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2046 CEFBS_None, // G_ATOMIC_CMPXCHG
2047 CEFBS_None, // G_ATOMICRMW_XCHG
2048 CEFBS_None, // G_ATOMICRMW_ADD
2049 CEFBS_None, // G_ATOMICRMW_SUB
2050 CEFBS_None, // G_ATOMICRMW_AND
2051 CEFBS_None, // G_ATOMICRMW_NAND
2052 CEFBS_None, // G_ATOMICRMW_OR
2053 CEFBS_None, // G_ATOMICRMW_XOR
2054 CEFBS_None, // G_ATOMICRMW_MAX
2055 CEFBS_None, // G_ATOMICRMW_MIN
2056 CEFBS_None, // G_ATOMICRMW_UMAX
2057 CEFBS_None, // G_ATOMICRMW_UMIN
2058 CEFBS_None, // G_ATOMICRMW_FADD
2059 CEFBS_None, // G_ATOMICRMW_FSUB
2060 CEFBS_None, // G_ATOMICRMW_FMAX
2061 CEFBS_None, // G_ATOMICRMW_FMIN
2062 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2063 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2064 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2065 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2066 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2067 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2068 CEFBS_None, // G_ATOMICRMW_USUB_COND
2069 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2070 CEFBS_None, // G_FENCE
2071 CEFBS_None, // G_PREFETCH
2072 CEFBS_None, // G_BRCOND
2073 CEFBS_None, // G_BRINDIRECT
2074 CEFBS_None, // G_INVOKE_REGION_START
2075 CEFBS_None, // G_INTRINSIC
2076 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2077 CEFBS_None, // G_INTRINSIC_CONVERGENT
2078 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2079 CEFBS_None, // G_ANYEXT
2080 CEFBS_None, // G_TRUNC
2081 CEFBS_None, // G_TRUNC_SSAT_S
2082 CEFBS_None, // G_TRUNC_SSAT_U
2083 CEFBS_None, // G_TRUNC_USAT_U
2084 CEFBS_None, // G_CONSTANT
2085 CEFBS_None, // G_FCONSTANT
2086 CEFBS_None, // G_VASTART
2087 CEFBS_None, // G_VAARG
2088 CEFBS_None, // G_SEXT
2089 CEFBS_None, // G_SEXT_INREG
2090 CEFBS_None, // G_ZEXT
2091 CEFBS_None, // G_SHL
2092 CEFBS_None, // G_LSHR
2093 CEFBS_None, // G_ASHR
2094 CEFBS_None, // G_FSHL
2095 CEFBS_None, // G_FSHR
2096 CEFBS_None, // G_ROTR
2097 CEFBS_None, // G_ROTL
2098 CEFBS_None, // G_ICMP
2099 CEFBS_None, // G_FCMP
2100 CEFBS_None, // G_SCMP
2101 CEFBS_None, // G_UCMP
2102 CEFBS_None, // G_SELECT
2103 CEFBS_None, // G_UADDO
2104 CEFBS_None, // G_UADDE
2105 CEFBS_None, // G_USUBO
2106 CEFBS_None, // G_USUBE
2107 CEFBS_None, // G_SADDO
2108 CEFBS_None, // G_SADDE
2109 CEFBS_None, // G_SSUBO
2110 CEFBS_None, // G_SSUBE
2111 CEFBS_None, // G_UMULO
2112 CEFBS_None, // G_SMULO
2113 CEFBS_None, // G_UMULH
2114 CEFBS_None, // G_SMULH
2115 CEFBS_None, // G_UADDSAT
2116 CEFBS_None, // G_SADDSAT
2117 CEFBS_None, // G_USUBSAT
2118 CEFBS_None, // G_SSUBSAT
2119 CEFBS_None, // G_USHLSAT
2120 CEFBS_None, // G_SSHLSAT
2121 CEFBS_None, // G_SMULFIX
2122 CEFBS_None, // G_UMULFIX
2123 CEFBS_None, // G_SMULFIXSAT
2124 CEFBS_None, // G_UMULFIXSAT
2125 CEFBS_None, // G_SDIVFIX
2126 CEFBS_None, // G_UDIVFIX
2127 CEFBS_None, // G_SDIVFIXSAT
2128 CEFBS_None, // G_UDIVFIXSAT
2129 CEFBS_None, // G_FADD
2130 CEFBS_None, // G_FSUB
2131 CEFBS_None, // G_FMUL
2132 CEFBS_None, // G_FMA
2133 CEFBS_None, // G_FMAD
2134 CEFBS_None, // G_FDIV
2135 CEFBS_None, // G_FREM
2136 CEFBS_None, // G_FMODF
2137 CEFBS_None, // G_FPOW
2138 CEFBS_None, // G_FPOWI
2139 CEFBS_None, // G_FEXP
2140 CEFBS_None, // G_FEXP2
2141 CEFBS_None, // G_FEXP10
2142 CEFBS_None, // G_FLOG
2143 CEFBS_None, // G_FLOG2
2144 CEFBS_None, // G_FLOG10
2145 CEFBS_None, // G_FLDEXP
2146 CEFBS_None, // G_FFREXP
2147 CEFBS_None, // G_FNEG
2148 CEFBS_None, // G_FPEXT
2149 CEFBS_None, // G_FPTRUNC
2150 CEFBS_None, // G_FPTOSI
2151 CEFBS_None, // G_FPTOUI
2152 CEFBS_None, // G_SITOFP
2153 CEFBS_None, // G_UITOFP
2154 CEFBS_None, // G_FPTOSI_SAT
2155 CEFBS_None, // G_FPTOUI_SAT
2156 CEFBS_None, // G_FABS
2157 CEFBS_None, // G_FCOPYSIGN
2158 CEFBS_None, // G_IS_FPCLASS
2159 CEFBS_None, // G_FCANONICALIZE
2160 CEFBS_None, // G_FMINNUM
2161 CEFBS_None, // G_FMAXNUM
2162 CEFBS_None, // G_FMINNUM_IEEE
2163 CEFBS_None, // G_FMAXNUM_IEEE
2164 CEFBS_None, // G_FMINIMUM
2165 CEFBS_None, // G_FMAXIMUM
2166 CEFBS_None, // G_FMINIMUMNUM
2167 CEFBS_None, // G_FMAXIMUMNUM
2168 CEFBS_None, // G_GET_FPENV
2169 CEFBS_None, // G_SET_FPENV
2170 CEFBS_None, // G_RESET_FPENV
2171 CEFBS_None, // G_GET_FPMODE
2172 CEFBS_None, // G_SET_FPMODE
2173 CEFBS_None, // G_RESET_FPMODE
2174 CEFBS_None, // G_GET_ROUNDING
2175 CEFBS_None, // G_SET_ROUNDING
2176 CEFBS_None, // G_PTR_ADD
2177 CEFBS_None, // G_PTRMASK
2178 CEFBS_None, // G_SMIN
2179 CEFBS_None, // G_SMAX
2180 CEFBS_None, // G_UMIN
2181 CEFBS_None, // G_UMAX
2182 CEFBS_None, // G_ABS
2183 CEFBS_None, // G_LROUND
2184 CEFBS_None, // G_LLROUND
2185 CEFBS_None, // G_BR
2186 CEFBS_None, // G_BRJT
2187 CEFBS_None, // G_VSCALE
2188 CEFBS_None, // G_INSERT_SUBVECTOR
2189 CEFBS_None, // G_EXTRACT_SUBVECTOR
2190 CEFBS_None, // G_INSERT_VECTOR_ELT
2191 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2192 CEFBS_None, // G_SHUFFLE_VECTOR
2193 CEFBS_None, // G_SPLAT_VECTOR
2194 CEFBS_None, // G_STEP_VECTOR
2195 CEFBS_None, // G_VECTOR_COMPRESS
2196 CEFBS_None, // G_CTTZ
2197 CEFBS_None, // G_CTTZ_ZERO_POISON
2198 CEFBS_None, // G_CTLZ
2199 CEFBS_None, // G_CTLZ_ZERO_POISON
2200 CEFBS_None, // G_CTLS
2201 CEFBS_None, // G_CTPOP
2202 CEFBS_None, // G_BSWAP
2203 CEFBS_None, // G_BITREVERSE
2204 CEFBS_None, // G_CLMUL
2205 CEFBS_None, // G_FCEIL
2206 CEFBS_None, // G_FCOS
2207 CEFBS_None, // G_FSIN
2208 CEFBS_None, // G_FSINCOS
2209 CEFBS_None, // G_FTAN
2210 CEFBS_None, // G_FACOS
2211 CEFBS_None, // G_FASIN
2212 CEFBS_None, // G_FATAN
2213 CEFBS_None, // G_FATAN2
2214 CEFBS_None, // G_FCOSH
2215 CEFBS_None, // G_FSINH
2216 CEFBS_None, // G_FTANH
2217 CEFBS_None, // G_FSQRT
2218 CEFBS_None, // G_FFLOOR
2219 CEFBS_None, // G_FRINT
2220 CEFBS_None, // G_FNEARBYINT
2221 CEFBS_None, // G_ADDRSPACE_CAST
2222 CEFBS_None, // G_BLOCK_ADDR
2223 CEFBS_None, // G_JUMP_TABLE
2224 CEFBS_None, // G_DYN_STACKALLOC
2225 CEFBS_None, // G_STACKSAVE
2226 CEFBS_None, // G_STACKRESTORE
2227 CEFBS_None, // G_STRICT_FADD
2228 CEFBS_None, // G_STRICT_FSUB
2229 CEFBS_None, // G_STRICT_FMUL
2230 CEFBS_None, // G_STRICT_FDIV
2231 CEFBS_None, // G_STRICT_FREM
2232 CEFBS_None, // G_STRICT_FMA
2233 CEFBS_None, // G_STRICT_FSQRT
2234 CEFBS_None, // G_STRICT_FLDEXP
2235 CEFBS_None, // G_STRICT_FCMP
2236 CEFBS_None, // G_STRICT_FCMPS
2237 CEFBS_None, // G_READ_REGISTER
2238 CEFBS_None, // G_WRITE_REGISTER
2239 CEFBS_None, // G_MEMCPY
2240 CEFBS_None, // G_MEMCPY_INLINE
2241 CEFBS_None, // G_MEMMOVE
2242 CEFBS_None, // G_MEMSET
2243 CEFBS_None, // G_BZERO
2244 CEFBS_None, // G_MEMSET_INLINE
2245 CEFBS_None, // G_TRAP
2246 CEFBS_None, // G_DEBUGTRAP
2247 CEFBS_None, // G_UBSANTRAP
2248 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2249 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2250 CEFBS_None, // G_VECREDUCE_FADD
2251 CEFBS_None, // G_VECREDUCE_FMUL
2252 CEFBS_None, // G_VECREDUCE_FMAX
2253 CEFBS_None, // G_VECREDUCE_FMIN
2254 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2255 CEFBS_None, // G_VECREDUCE_FMINIMUM
2256 CEFBS_None, // G_VECREDUCE_ADD
2257 CEFBS_None, // G_VECREDUCE_MUL
2258 CEFBS_None, // G_VECREDUCE_AND
2259 CEFBS_None, // G_VECREDUCE_OR
2260 CEFBS_None, // G_VECREDUCE_XOR
2261 CEFBS_None, // G_VECREDUCE_SMAX
2262 CEFBS_None, // G_VECREDUCE_SMIN
2263 CEFBS_None, // G_VECREDUCE_UMAX
2264 CEFBS_None, // G_VECREDUCE_UMIN
2265 CEFBS_None, // G_SBFX
2266 CEFBS_None, // G_UBFX
2267 CEFBS_None, // ADJCALLSTACKDOWN
2268 CEFBS_None, // ADJCALLSTACKUP
2269 CEFBS_None, // FI_ri
2270 CEFBS_None, // LDIMM64
2271 CEFBS_None, // LOAD_STACK_ARG_PSEUDO
2272 CEFBS_None, // MEMCPY
2273 CEFBS_None, // STORE_STACK_ARG_IMM_PSEUDO
2274 CEFBS_None, // STORE_STACK_ARG_PSEUDO
2275 CEFBS_None, // Select
2276 CEFBS_None, // Select_32
2277 CEFBS_None, // Select_32_64
2278 CEFBS_None, // Select_64_32
2279 CEFBS_None, // Select_Ri
2280 CEFBS_None, // Select_Ri_32
2281 CEFBS_None, // Select_Ri_32_64
2282 CEFBS_None, // Select_Ri_64_32
2283 CEFBS_None, // ADDR_SPACE_CAST
2284 CEFBS_None, // ADD_ri
2285 CEFBS_None, // ADD_ri_32
2286 CEFBS_None, // ADD_rr
2287 CEFBS_None, // ADD_rr_32
2288 CEFBS_None, // AND_ri
2289 CEFBS_None, // AND_ri_32
2290 CEFBS_None, // AND_rr
2291 CEFBS_None, // AND_rr_32
2292 CEFBS_None, // BE16
2293 CEFBS_None, // BE32
2294 CEFBS_None, // BE64
2295 CEFBS_None, // BSWAP16
2296 CEFBS_None, // BSWAP32
2297 CEFBS_None, // BSWAP64
2298 CEFBS_None, // CMPXCHGD
2299 CEFBS_None, // CMPXCHGW32
2300 CEFBS_None, // CORE_LD32
2301 CEFBS_None, // CORE_LD64
2302 CEFBS_None, // CORE_SHIFT
2303 CEFBS_None, // CORE_ST
2304 CEFBS_None, // DIV_ri
2305 CEFBS_None, // DIV_ri_32
2306 CEFBS_None, // DIV_rr
2307 CEFBS_None, // DIV_rr_32
2308 CEFBS_None, // JAL
2309 CEFBS_None, // JALX
2310 CEFBS_None, // JCOND
2311 CEFBS_None, // JEQ_ri
2312 CEFBS_None, // JEQ_ri_32
2313 CEFBS_None, // JEQ_rr
2314 CEFBS_None, // JEQ_rr_32
2315 CEFBS_None, // JMP
2316 CEFBS_None, // JMPL
2317 CEFBS_None, // JNE_ri
2318 CEFBS_None, // JNE_ri_32
2319 CEFBS_None, // JNE_rr
2320 CEFBS_None, // JNE_rr_32
2321 CEFBS_None, // JSET_ri
2322 CEFBS_None, // JSET_ri_32
2323 CEFBS_None, // JSET_rr
2324 CEFBS_None, // JSET_rr_32
2325 CEFBS_None, // JSGE_ri
2326 CEFBS_None, // JSGE_ri_32
2327 CEFBS_None, // JSGE_rr
2328 CEFBS_None, // JSGE_rr_32
2329 CEFBS_None, // JSGT_ri
2330 CEFBS_None, // JSGT_ri_32
2331 CEFBS_None, // JSGT_rr
2332 CEFBS_None, // JSGT_rr_32
2333 CEFBS_None, // JSLE_ri
2334 CEFBS_None, // JSLE_ri_32
2335 CEFBS_None, // JSLE_rr
2336 CEFBS_None, // JSLE_rr_32
2337 CEFBS_None, // JSLT_ri
2338 CEFBS_None, // JSLT_ri_32
2339 CEFBS_None, // JSLT_rr
2340 CEFBS_None, // JSLT_rr_32
2341 CEFBS_None, // JUGE_ri
2342 CEFBS_None, // JUGE_ri_32
2343 CEFBS_None, // JUGE_rr
2344 CEFBS_None, // JUGE_rr_32
2345 CEFBS_None, // JUGT_ri
2346 CEFBS_None, // JUGT_ri_32
2347 CEFBS_None, // JUGT_rr
2348 CEFBS_None, // JUGT_rr_32
2349 CEFBS_None, // JULE_ri
2350 CEFBS_None, // JULE_ri_32
2351 CEFBS_None, // JULE_rr
2352 CEFBS_None, // JULE_rr_32
2353 CEFBS_None, // JULT_ri
2354 CEFBS_None, // JULT_ri_32
2355 CEFBS_None, // JULT_rr
2356 CEFBS_None, // JULT_rr_32
2357 CEFBS_None, // JX
2358 CEFBS_None, // LDB
2359 CEFBS_None, // LDB32
2360 CEFBS_None, // LDBACQ32
2361 CEFBS_None, // LDBSX
2362 CEFBS_None, // LDD
2363 CEFBS_None, // LDDACQ
2364 CEFBS_None, // LDH
2365 CEFBS_None, // LDH32
2366 CEFBS_None, // LDHACQ32
2367 CEFBS_None, // LDHSX
2368 CEFBS_None, // LDW
2369 CEFBS_None, // LDW32
2370 CEFBS_None, // LDWACQ32
2371 CEFBS_None, // LDWSX
2372 CEFBS_None, // LD_ABS_B
2373 CEFBS_None, // LD_ABS_H
2374 CEFBS_None, // LD_ABS_W
2375 CEFBS_None, // LD_IND_B
2376 CEFBS_None, // LD_IND_H
2377 CEFBS_None, // LD_IND_W
2378 CEFBS_None, // LD_imm64
2379 CEFBS_None, // LD_pseudo
2380 CEFBS_None, // LE16
2381 CEFBS_None, // LE32
2382 CEFBS_None, // LE64
2383 CEFBS_None, // MOD_ri
2384 CEFBS_None, // MOD_ri_32
2385 CEFBS_None, // MOD_rr
2386 CEFBS_None, // MOD_rr_32
2387 CEFBS_None, // MOVSX_rr_16
2388 CEFBS_None, // MOVSX_rr_32
2389 CEFBS_None, // MOVSX_rr_32_16
2390 CEFBS_None, // MOVSX_rr_32_8
2391 CEFBS_None, // MOVSX_rr_8
2392 CEFBS_None, // MOV_32_64
2393 CEFBS_None, // MOV_ri
2394 CEFBS_None, // MOV_ri_32
2395 CEFBS_None, // MOV_rr
2396 CEFBS_None, // MOV_rr_32
2397 CEFBS_None, // MUL_ri
2398 CEFBS_None, // MUL_ri_32
2399 CEFBS_None, // MUL_rr
2400 CEFBS_None, // MUL_rr_32
2401 CEFBS_None, // NEG_32
2402 CEFBS_None, // NEG_64
2403 CEFBS_None, // NOP
2404 CEFBS_None, // OR_ri
2405 CEFBS_None, // OR_ri_32
2406 CEFBS_None, // OR_rr
2407 CEFBS_None, // OR_rr_32
2408 CEFBS_None, // RET
2409 CEFBS_None, // SDIV_ri
2410 CEFBS_None, // SDIV_ri_32
2411 CEFBS_None, // SDIV_rr
2412 CEFBS_None, // SDIV_rr_32
2413 CEFBS_None, // SLL_ri
2414 CEFBS_None, // SLL_ri_32
2415 CEFBS_None, // SLL_rr
2416 CEFBS_None, // SLL_rr_32
2417 CEFBS_None, // SMOD_ri
2418 CEFBS_None, // SMOD_ri_32
2419 CEFBS_None, // SMOD_rr
2420 CEFBS_None, // SMOD_rr_32
2421 CEFBS_None, // SRA_ri
2422 CEFBS_None, // SRA_ri_32
2423 CEFBS_None, // SRA_rr
2424 CEFBS_None, // SRA_rr_32
2425 CEFBS_None, // SRL_ri
2426 CEFBS_None, // SRL_ri_32
2427 CEFBS_None, // SRL_rr
2428 CEFBS_None, // SRL_rr_32
2429 CEFBS_None, // STB
2430 CEFBS_None, // STB32
2431 CEFBS_None, // STBREL32
2432 CEFBS_None, // STB_imm
2433 CEFBS_None, // STD
2434 CEFBS_None, // STDREL
2435 CEFBS_None, // STD_imm
2436 CEFBS_None, // STH
2437 CEFBS_None, // STH32
2438 CEFBS_None, // STHREL32
2439 CEFBS_None, // STH_imm
2440 CEFBS_None, // STW
2441 CEFBS_None, // STW32
2442 CEFBS_None, // STWREL32
2443 CEFBS_None, // STW_imm
2444 CEFBS_None, // SUB_ri
2445 CEFBS_None, // SUB_ri_32
2446 CEFBS_None, // SUB_rr
2447 CEFBS_None, // SUB_rr_32
2448 CEFBS_None, // XADDD
2449 CEFBS_None, // XADDW
2450 CEFBS_None, // XADDW32
2451 CEFBS_None, // XANDD
2452 CEFBS_None, // XANDW32
2453 CEFBS_None, // XCHGD
2454 CEFBS_None, // XCHGW32
2455 CEFBS_None, // XFADDD
2456 CEFBS_None, // XFADDW32
2457 CEFBS_None, // XFANDD
2458 CEFBS_None, // XFANDW32
2459 CEFBS_None, // XFORD
2460 CEFBS_None, // XFORW32
2461 CEFBS_None, // XFXORD
2462 CEFBS_None, // XFXORW32
2463 CEFBS_None, // XORD
2464 CEFBS_None, // XORW32
2465 CEFBS_None, // XOR_ri
2466 CEFBS_None, // XOR_ri_32
2467 CEFBS_None, // XOR_rr
2468 CEFBS_None, // XOR_rr_32
2469 CEFBS_None, // XXORD
2470 CEFBS_None, // XXORW32
2471 };
2472
2473 assert(Opcode < 535);
2474 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2475}
2476
2477
2478} // namespace llvm::BPF_MC
2479
2480#endif // GET_COMPUTE_FEATURES
2481
2482#ifdef GET_AVAILABLE_OPCODE_CHECKER
2483#undef GET_AVAILABLE_OPCODE_CHECKER
2484
2485namespace llvm::BPF_MC {
2486
2487bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2488 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2489 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2490 FeatureBitset MissingFeatures =
2491 (AvailableFeatures & RequiredFeatures) ^
2492 RequiredFeatures;
2493 return !MissingFeatures.any();
2494}
2495
2496} // namespace llvm::BPF_MC
2497
2498#endif // GET_AVAILABLE_OPCODE_CHECKER
2499
2500#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2501#undef ENABLE_INSTR_PREDICATE_VERIFIER
2502
2503#include <sstream>
2504
2505namespace llvm::BPF_MC {
2506
2507#ifndef NDEBUG
2508static const char *SubtargetFeatureNames[] = {
2509 nullptr
2510};
2511
2512#endif // NDEBUG
2513
2514void verifyInstructionPredicates(
2515 unsigned Opcode, const FeatureBitset &Features) {
2516#ifndef NDEBUG
2517 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2518 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2519 FeatureBitset MissingFeatures =
2520 (AvailableFeatures & RequiredFeatures) ^
2521 RequiredFeatures;
2522 if (MissingFeatures.any()) {
2523 std::ostringstream Msg;
2524 Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
2525 << " instruction but the ";
2526 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2527 if (MissingFeatures.test(i))
2528 Msg << SubtargetFeatureNames[i] << " ";
2529 Msg << "predicate(s) are not met";
2530 report_fatal_error(Msg.str().c_str());
2531 }
2532#endif // NDEBUG
2533}
2534
2535} // namespace llvm::BPF_MC
2536
2537#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2538
2539