1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::BPF {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1530
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543
96 G_INSERT = 81, // GenericOpcodes.td:1552
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1562
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330
114 G_LOAD = 99, // GenericOpcodes.td:1357
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1366
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1374
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1383
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410
121 G_STORE = 106, // GenericOpcodes.td:1418
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1436
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1508
150 G_PREFETCH = 135, // GenericOpcodes.td:1515
151 G_BRCOND = 136, // GenericOpcodes.td:1655
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1664
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687
154 G_INTRINSIC = 139, // GenericOpcodes.td:1607
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:609
183 G_UADDE = 168, // GenericOpcodes.td:617
184 G_USUBO = 169, // GenericOpcodes.td:639
185 G_USUBE = 170, // GenericOpcodes.td:645
186 G_SADDO = 171, // GenericOpcodes.td:624
187 G_SADDE = 172, // GenericOpcodes.td:632
188 G_SSUBO = 173, // GenericOpcodes.td:652
189 G_SSUBE = 174, // GenericOpcodes.td:659
190 G_UMULO = 175, // GenericOpcodes.td:666
191 G_SMULO = 176, // GenericOpcodes.td:674
192 G_UMULH = 177, // GenericOpcodes.td:683
193 G_SMULH = 178, // GenericOpcodes.td:692
194 G_UADDSAT = 179, // GenericOpcodes.td:704
195 G_SADDSAT = 180, // GenericOpcodes.td:712
196 G_USUBSAT = 181, // GenericOpcodes.td:720
197 G_SSUBSAT = 182, // GenericOpcodes.td:728
198 G_USHLSAT = 183, // GenericOpcodes.td:736
199 G_SSHLSAT = 184, // GenericOpcodes.td:744
200 G_SMULFIX = 185, // GenericOpcodes.td:756
201 G_UMULFIX = 186, // GenericOpcodes.td:763
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:773
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:780
204 G_SDIVFIX = 189, // GenericOpcodes.td:791
205 G_UDIVFIX = 190, // GenericOpcodes.td:798
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:808
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:815
208 G_FADD = 193, // GenericOpcodes.td:988
209 G_FSUB = 194, // GenericOpcodes.td:996
210 G_FMUL = 195, // GenericOpcodes.td:1004
211 G_FMA = 196, // GenericOpcodes.td:1013
212 G_FMAD = 197, // GenericOpcodes.td:1022
213 G_FDIV = 198, // GenericOpcodes.td:1030
214 G_FREM = 199, // GenericOpcodes.td:1037
215 G_FMODF = 200, // GenericOpcodes.td:1044
216 G_FPOW = 201, // GenericOpcodes.td:1051
217 G_FPOWI = 202, // GenericOpcodes.td:1058
218 G_FEXP = 203, // GenericOpcodes.td:1065
219 G_FEXP2 = 204, // GenericOpcodes.td:1072
220 G_FEXP10 = 205, // GenericOpcodes.td:1079
221 G_FLOG = 206, // GenericOpcodes.td:1086
222 G_FLOG2 = 207, // GenericOpcodes.td:1093
223 G_FLOG10 = 208, // GenericOpcodes.td:1100
224 G_FLDEXP = 209, // GenericOpcodes.td:1107
225 G_FFREXP = 210, // GenericOpcodes.td:1114
226 G_FNEG = 211, // GenericOpcodes.td:826
227 G_FPEXT = 212, // GenericOpcodes.td:832
228 G_FPTRUNC = 213, // GenericOpcodes.td:838
229 G_FPTOSI = 214, // GenericOpcodes.td:844
230 G_FPTOUI = 215, // GenericOpcodes.td:850
231 G_SITOFP = 216, // GenericOpcodes.td:856
232 G_UITOFP = 217, // GenericOpcodes.td:862
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:868
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:874
235 G_FABS = 220, // GenericOpcodes.td:880
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:886
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:899
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:892
239 G_FMINNUM = 224, // GenericOpcodes.td:912
240 G_FMAXNUM = 225, // GenericOpcodes.td:919
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944
243 G_FMINIMUM = 228, // GenericOpcodes.td:954
244 G_FMAXIMUM = 229, // GenericOpcodes.td:961
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:969
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976
247 G_GET_FPENV = 232, // GenericOpcodes.td:1244
248 G_SET_FPENV = 233, // GenericOpcodes.td:1251
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1258
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1265
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1272
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1279
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1336
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1342
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1645
265 G_BRJT = 250, // GenericOpcodes.td:1675
266 G_VSCALE = 251, // GenericOpcodes.td:1573
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1770
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_FCEIL = 270, // GenericOpcodes.td:1121
286 G_FCOS = 271, // GenericOpcodes.td:1128
287 G_FSIN = 272, // GenericOpcodes.td:1135
288 G_FSINCOS = 273, // GenericOpcodes.td:1142
289 G_FTAN = 274, // GenericOpcodes.td:1149
290 G_FACOS = 275, // GenericOpcodes.td:1156
291 G_FASIN = 276, // GenericOpcodes.td:1163
292 G_FATAN = 277, // GenericOpcodes.td:1170
293 G_FATAN2 = 278, // GenericOpcodes.td:1177
294 G_FCOSH = 279, // GenericOpcodes.td:1184
295 G_FSINH = 280, // GenericOpcodes.td:1191
296 G_FTANH = 281, // GenericOpcodes.td:1198
297 G_FSQRT = 282, // GenericOpcodes.td:1208
298 G_FFLOOR = 283, // GenericOpcodes.td:1215
299 G_FRINT = 284, // GenericOpcodes.td:1222
300 G_FNEARBYINT = 285, // GenericOpcodes.td:1229
301 G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248
302 G_BLOCK_ADDR = 287, // GenericOpcodes.td:254
303 G_JUMP_TABLE = 288, // GenericOpcodes.td:260
304 G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266
305 G_STACKSAVE = 290, // GenericOpcodes.td:272
306 G_STACKRESTORE = 291, // GenericOpcodes.td:278
307 G_STRICT_FADD = 292, // GenericOpcodes.td:1829
308 G_STRICT_FSUB = 293, // GenericOpcodes.td:1830
309 G_STRICT_FMUL = 294, // GenericOpcodes.td:1831
310 G_STRICT_FDIV = 295, // GenericOpcodes.td:1832
311 G_STRICT_FREM = 296, // GenericOpcodes.td:1833
312 G_STRICT_FMA = 297, // GenericOpcodes.td:1834
313 G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835
314 G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836
315 G_STRICT_FCMP = 300, // GenericOpcodes.td:1837
316 G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838
317 G_READ_REGISTER = 302, // GenericOpcodes.td:1694
318 G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704
319 G_MEMCPY = 304, // GenericOpcodes.td:1844
320 G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852
321 G_MEMMOVE = 306, // GenericOpcodes.td:1860
322 G_MEMSET = 307, // GenericOpcodes.td:1868
323 G_BZERO = 308, // GenericOpcodes.td:1875
324 G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882
325 G_TRAP = 310, // GenericOpcodes.td:1892
326 G_DEBUGTRAP = 311, // GenericOpcodes.td:1899
327 G_UBSANTRAP = 312, // GenericOpcodes.td:1905
328 G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793
329 G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799
330 G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805
331 G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806
332 G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808
333 G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809
334 G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810
335 G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811
336 G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812
337 G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813
338 G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815
339 G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816
340 G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817
341 G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818
342 G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819
343 G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820
344 G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821
345 G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822
346 G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823
347 G_SBFX = 332, // GenericOpcodes.td:1917
348 G_UBFX = 333, // GenericOpcodes.td:1925
349 ADJCALLSTACKDOWN = 334, // BPFInstrInfo.td:849
350 ADJCALLSTACKUP = 335, // BPFInstrInfo.td:852
351 FI_ri = 336, // BPFInstrInfo.td:515
352 LDIMM64 = 337, // BPFInstrInfo.td:1425
353 LOAD_STACK_ARG_PSEUDO = 338, // BPFInstrInfo.td:320
354 MEMCPY = 339, // BPFInstrInfo.td:1416
355 STORE_STACK_ARG_IMM_PSEUDO = 340, // BPFInstrInfo.td:330
356 STORE_STACK_ARG_PSEUDO = 341, // BPFInstrInfo.td:326
357 Select = 342, // BPFInstrInfo.td:858
358 Select_32 = 343, // BPFInstrInfo.td:878
359 Select_32_64 = 344, // BPFInstrInfo.td:888
360 Select_64_32 = 345, // BPFInstrInfo.td:868
361 Select_Ri = 346, // BPFInstrInfo.td:863
362 Select_Ri_32 = 347, // BPFInstrInfo.td:883
363 Select_Ri_32_64 = 348, // BPFInstrInfo.td:893
364 Select_Ri_64_32 = 349, // BPFInstrInfo.td:873
365 ADDR_SPACE_CAST = 350, // BPFInstrInfo.td:486
366 ADD_ri = 351, // BPFInstrInfo.td:366
367 ADD_ri_32 = 352, // BPFInstrInfo.td:376
368 ADD_rr = 353, // BPFInstrInfo.td:361
369 ADD_rr_32 = 354, // BPFInstrInfo.td:371
370 AND_ri = 355, // BPFInstrInfo.td:366
371 AND_ri_32 = 356, // BPFInstrInfo.td:376
372 AND_rr = 357, // BPFInstrInfo.td:361
373 AND_rr_32 = 358, // BPFInstrInfo.td:371
374 BE16 = 359, // BPFInstrInfo.td:1225
375 BE32 = 360, // BPFInstrInfo.td:1226
376 BE64 = 361, // BPFInstrInfo.td:1227
377 BSWAP16 = 362, // BPFInstrInfo.td:1218
378 BSWAP32 = 363, // BPFInstrInfo.td:1219
379 BSWAP64 = 364, // BPFInstrInfo.td:1220
380 CMPXCHGD = 365, // BPFInstrInfo.td:1198
381 CMPXCHGW32 = 366, // BPFInstrInfo.td:1194
382 CORE_LD32 = 367, // BPFInstrInfo.td:687
383 CORE_LD64 = 368, // BPFInstrInfo.td:686
384 CORE_SHIFT = 369, // BPFInstrInfo.td:694
385 CORE_ST = 370, // BPFInstrInfo.td:688
386 DIV_ri = 371, // BPFInstrInfo.td:366
387 DIV_ri_32 = 372, // BPFInstrInfo.td:376
388 DIV_rr = 373, // BPFInstrInfo.td:361
389 DIV_rr_32 = 374, // BPFInstrInfo.td:371
390 JAL = 375, // BPFInstrInfo.td:813
391 JALX = 376, // BPFInstrInfo.td:814
392 JCOND = 377, // BPFInstrInfo.td:310
393 JEQ_ri = 378, // BPFInstrInfo.td:292
394 JEQ_ri_32 = 379, // BPFInstrInfo.td:294
395 JEQ_rr = 380, // BPFInstrInfo.td:291
396 JEQ_rr_32 = 381, // BPFInstrInfo.td:293
397 JMP = 382, // BPFInstrInfo.td:807
398 JMPL = 383, // BPFInstrInfo.td:808
399 JNE_ri = 384, // BPFInstrInfo.td:292
400 JNE_ri_32 = 385, // BPFInstrInfo.td:294
401 JNE_rr = 386, // BPFInstrInfo.td:291
402 JNE_rr_32 = 387, // BPFInstrInfo.td:293
403 JSET_ri = 388, // BPFInstrInfo.td:292
404 JSET_ri_32 = 389, // BPFInstrInfo.td:294
405 JSET_rr = 390, // BPFInstrInfo.td:291
406 JSET_rr_32 = 391, // BPFInstrInfo.td:293
407 JSGE_ri = 392, // BPFInstrInfo.td:292
408 JSGE_ri_32 = 393, // BPFInstrInfo.td:294
409 JSGE_rr = 394, // BPFInstrInfo.td:291
410 JSGE_rr_32 = 395, // BPFInstrInfo.td:293
411 JSGT_ri = 396, // BPFInstrInfo.td:292
412 JSGT_ri_32 = 397, // BPFInstrInfo.td:294
413 JSGT_rr = 398, // BPFInstrInfo.td:291
414 JSGT_rr_32 = 399, // BPFInstrInfo.td:293
415 JSLE_ri = 400, // BPFInstrInfo.td:292
416 JSLE_ri_32 = 401, // BPFInstrInfo.td:294
417 JSLE_rr = 402, // BPFInstrInfo.td:291
418 JSLE_rr_32 = 403, // BPFInstrInfo.td:293
419 JSLT_ri = 404, // BPFInstrInfo.td:292
420 JSLT_ri_32 = 405, // BPFInstrInfo.td:294
421 JSLT_rr = 406, // BPFInstrInfo.td:291
422 JSLT_rr_32 = 407, // BPFInstrInfo.td:293
423 JUGE_ri = 408, // BPFInstrInfo.td:292
424 JUGE_ri_32 = 409, // BPFInstrInfo.td:294
425 JUGE_rr = 410, // BPFInstrInfo.td:291
426 JUGE_rr_32 = 411, // BPFInstrInfo.td:293
427 JUGT_ri = 412, // BPFInstrInfo.td:292
428 JUGT_ri_32 = 413, // BPFInstrInfo.td:294
429 JUGT_rr = 414, // BPFInstrInfo.td:291
430 JUGT_rr_32 = 415, // BPFInstrInfo.td:293
431 JULE_ri = 416, // BPFInstrInfo.td:292
432 JULE_ri_32 = 417, // BPFInstrInfo.td:294
433 JULE_rr = 418, // BPFInstrInfo.td:291
434 JULE_rr_32 = 419, // BPFInstrInfo.td:293
435 JULT_ri = 420, // BPFInstrInfo.td:292
436 JULT_ri_32 = 421, // BPFInstrInfo.td:294
437 JULT_rr = 422, // BPFInstrInfo.td:291
438 JULT_rr_32 = 423, // BPFInstrInfo.td:293
439 JX = 424, // BPFInstrInfo.td:314
440 LDB = 425, // BPFInstrInfo.td:705
441 LDB32 = 426, // BPFInstrInfo.td:1353
442 LDBACQ32 = 427, // BPFInstrInfo.td:1358
443 LDBSX = 428, // BPFInstrInfo.td:711
444 LDD = 429, // BPFInstrInfo.td:714
445 LDDACQ = 430, // BPFInstrInfo.td:748
446 LDH = 431, // BPFInstrInfo.td:704
447 LDH32 = 432, // BPFInstrInfo.td:1352
448 LDHACQ32 = 433, // BPFInstrInfo.td:1357
449 LDHSX = 434, // BPFInstrInfo.td:710
450 LDW = 435, // BPFInstrInfo.td:703
451 LDW32 = 436, // BPFInstrInfo.td:1351
452 LDWACQ32 = 437, // BPFInstrInfo.td:1356
453 LDWSX = 438, // BPFInstrInfo.td:709
454 LD_ABS_B = 439, // BPFInstrInfo.td:1262
455 LD_ABS_H = 440, // BPFInstrInfo.td:1263
456 LD_ABS_W = 441, // BPFInstrInfo.td:1264
457 LD_IND_B = 442, // BPFInstrInfo.td:1266
458 LD_IND_H = 443, // BPFInstrInfo.td:1267
459 LD_IND_W = 444, // BPFInstrInfo.td:1268
460 LD_imm64 = 445, // BPFInstrInfo.td:440
461 LD_pseudo = 446, // BPFInstrInfo.td:531
462 LE16 = 447, // BPFInstrInfo.td:1230
463 LE32 = 448, // BPFInstrInfo.td:1231
464 LE64 = 449, // BPFInstrInfo.td:1232
465 MOD_ri = 450, // BPFInstrInfo.td:366
466 MOD_ri_32 = 451, // BPFInstrInfo.td:376
467 MOD_rr = 452, // BPFInstrInfo.td:361
468 MOD_rr_32 = 453, // BPFInstrInfo.td:371
469 MOVSX_rr_16 = 454, // BPFInstrInfo.td:467
470 MOVSX_rr_32 = 455, // BPFInstrInfo.td:471
471 MOVSX_rr_32_16 = 456, // BPFInstrInfo.td:479
472 MOVSX_rr_32_8 = 457, // BPFInstrInfo.td:475
473 MOVSX_rr_8 = 458, // BPFInstrInfo.td:463
474 MOV_32_64 = 459, // BPFInstrInfo.td:1271
475 MOV_ri = 460, // BPFInstrInfo.td:446
476 MOV_ri_32 = 461, // BPFInstrInfo.td:456
477 MOV_rr = 462, // BPFInstrInfo.td:441
478 MOV_rr_32 = 463, // BPFInstrInfo.td:451
479 MUL_ri = 464, // BPFInstrInfo.td:366
480 MUL_ri_32 = 465, // BPFInstrInfo.td:376
481 MUL_rr = 466, // BPFInstrInfo.td:361
482 MUL_rr_32 = 467, // BPFInstrInfo.td:371
483 NEG_32 = 468, // BPFInstrInfo.td:417
484 NEG_64 = 469, // BPFInstrInfo.td:414
485 NOP = 470, // BPFInstrInfo.td:830
486 OR_ri = 471, // BPFInstrInfo.td:366
487 OR_ri_32 = 472, // BPFInstrInfo.td:376
488 OR_rr = 473, // BPFInstrInfo.td:361
489 OR_rr_32 = 474, // BPFInstrInfo.td:371
490 RET = 475, // BPFInstrInfo.td:844
491 SDIV_ri = 476, // BPFInstrInfo.td:366
492 SDIV_ri_32 = 477, // BPFInstrInfo.td:376
493 SDIV_rr = 478, // BPFInstrInfo.td:361
494 SDIV_rr_32 = 479, // BPFInstrInfo.td:371
495 SLL_ri = 480, // BPFInstrInfo.td:366
496 SLL_ri_32 = 481, // BPFInstrInfo.td:376
497 SLL_rr = 482, // BPFInstrInfo.td:361
498 SLL_rr_32 = 483, // BPFInstrInfo.td:371
499 SMOD_ri = 484, // BPFInstrInfo.td:366
500 SMOD_ri_32 = 485, // BPFInstrInfo.td:376
501 SMOD_rr = 486, // BPFInstrInfo.td:361
502 SMOD_rr_32 = 487, // BPFInstrInfo.td:371
503 SRA_ri = 488, // BPFInstrInfo.td:366
504 SRA_ri_32 = 489, // BPFInstrInfo.td:376
505 SRA_rr = 490, // BPFInstrInfo.td:361
506 SRA_rr_32 = 491, // BPFInstrInfo.td:371
507 SRL_ri = 492, // BPFInstrInfo.td:366
508 SRL_ri_32 = 493, // BPFInstrInfo.td:376
509 SRL_rr = 494, // BPFInstrInfo.td:361
510 SRL_rr_32 = 495, // BPFInstrInfo.td:371
511 STB = 496, // BPFInstrInfo.td:571
512 STB32 = 497, // BPFInstrInfo.td:1320
513 STBREL32 = 498, // BPFInstrInfo.td:1325
514 STB_imm = 499, // BPFInstrInfo.td:607
515 STD = 500, // BPFInstrInfo.td:573
516 STDREL = 501, // BPFInstrInfo.td:651
517 STD_imm = 502, // BPFInstrInfo.td:604
518 STH = 503, // BPFInstrInfo.td:570
519 STH32 = 504, // BPFInstrInfo.td:1319
520 STHREL32 = 505, // BPFInstrInfo.td:1324
521 STH_imm = 506, // BPFInstrInfo.td:606
522 STW = 507, // BPFInstrInfo.td:569
523 STW32 = 508, // BPFInstrInfo.td:1318
524 STWREL32 = 509, // BPFInstrInfo.td:1323
525 STW_imm = 510, // BPFInstrInfo.td:605
526 SUB_ri = 511, // BPFInstrInfo.td:366
527 SUB_ri_32 = 512, // BPFInstrInfo.td:376
528 SUB_rr = 513, // BPFInstrInfo.td:361
529 SUB_rr_32 = 514, // BPFInstrInfo.td:371
530 XADDD = 515, // BPFInstrInfo.td:947
531 XADDW = 516, // BPFInstrInfo.td:946
532 XADDW32 = 517, // BPFInstrInfo.td:941
533 XANDD = 518, // BPFInstrInfo.td:948
534 XANDW32 = 519, // BPFInstrInfo.td:942
535 XCHGD = 520, // BPFInstrInfo.td:1154
536 XCHGW32 = 521, // BPFInstrInfo.td:1151
537 XFADDD = 522, // BPFInstrInfo.td:1004
538 XFADDW32 = 523, // BPFInstrInfo.td:997
539 XFANDD = 524, // BPFInstrInfo.td:1006
540 XFANDW32 = 525, // BPFInstrInfo.td:998
541 XFORD = 526, // BPFInstrInfo.td:1007
542 XFORW32 = 527, // BPFInstrInfo.td:999
543 XFXORD = 528, // BPFInstrInfo.td:1008
544 XFXORW32 = 529, // BPFInstrInfo.td:1000
545 XORD = 530, // BPFInstrInfo.td:949
546 XORW32 = 531, // BPFInstrInfo.td:943
547 XOR_ri = 532, // BPFInstrInfo.td:366
548 XOR_ri_32 = 533, // BPFInstrInfo.td:376
549 XOR_rr = 534, // BPFInstrInfo.td:361
550 XOR_rr_32 = 535, // BPFInstrInfo.td:371
551 XXORD = 536, // BPFInstrInfo.td:950
552 XXORW32 = 537, // BPFInstrInfo.td:944
553 INSTRUCTION_LIST_END = 538
554 };
555
556} // namespace llvm::BPF
557
558#endif // GET_INSTRINFO_ENUM
559
560#ifdef GET_INSTRINFO_SCHED_ENUM
561#undef GET_INSTRINFO_SCHED_ENUM
562
563namespace llvm::BPF::Sched {
564
565 enum {
566 NoInstrModel = 0,
567 SCHED_LIST_END = 1
568 };
569
570} // namespace llvm::BPF::Sched
571
572#endif // GET_INSTRINFO_SCHED_ENUM
573
574#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
575
576namespace llvm {
577
578struct BPFInstrTable {
579 MCInstrDesc Insts[538];
580 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
581 MCPhysReg ImplicitOps[14];
582 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
583 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
584 MCOperandInfo OperandInfo[282];
585};
586} // namespace llvm
587
588#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
589
590#ifdef GET_INSTRINFO_MC_DESC
591#undef GET_INSTRINFO_MC_DESC
592
593namespace llvm {
594
595static_assert((sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
596static constexpr unsigned BPFOpInfoBase = (sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) / sizeof(MCOperandInfo);
597
598extern const BPFInstrTable BPFDescs = {
599 {
600 { 537, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORW32
601 { 536, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORD
602 { 535, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr_32
603 { 534, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr
604 { 533, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri_32
605 { 532, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri
606 { 531, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORW32
607 { 530, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORD
608 { 529, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORW32
609 { 528, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORD
610 { 527, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORW32
611 { 526, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORD
612 { 525, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDW32
613 { 524, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDD
614 { 523, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDW32
615 { 522, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDD
616 { 521, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGW32
617 { 520, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGD
618 { 519, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDW32
619 { 518, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDD
620 { 517, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW32
621 { 516, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW
622 { 515, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDD
623 { 514, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr_32
624 { 513, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr
625 { 512, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri_32
626 { 511, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri
627 { 510, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_imm
628 { 509, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWREL32
629 { 508, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW32
630 { 507, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW
631 { 506, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_imm
632 { 505, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STHREL32
633 { 504, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH32
634 { 503, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH
635 { 502, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD_imm
636 { 501, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDREL
637 { 500, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD
638 { 499, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_imm
639 { 498, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STBREL32
640 { 497, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB32
641 { 496, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB
642 { 495, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr_32
643 { 494, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr
644 { 493, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri_32
645 { 492, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri
646 { 491, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr_32
647 { 490, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr
648 { 489, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri_32
649 { 488, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri
650 { 487, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr_32
651 { 486, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr
652 { 485, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri_32
653 { 484, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri
654 { 483, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr_32
655 { 482, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr
656 { 481, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri_32
657 { 480, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri
658 { 479, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr_32
659 { 478, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr
660 { 477, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri_32
661 { 476, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri
662 { 475, 0, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
663 { 474, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr_32
664 { 473, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr
665 { 472, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri_32
666 { 471, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri
667 { 470, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
668 { 469, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_64
669 { 468, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 269, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_32
670 { 467, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr_32
671 { 466, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr
672 { 465, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri_32
673 { 464, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri
674 { 463, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr_32
675 { 462, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr
676 { 461, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 267, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri_32
677 { 460, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri
678 { 459, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 265, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_32_64
679 { 458, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_8
680 { 457, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_8
681 { 456, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_16
682 { 455, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32
683 { 454, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_16
684 { 453, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr_32
685 { 452, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr
686 { 451, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri_32
687 { 450, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri
688 { 449, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE64
689 { 448, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE32
690 { 447, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE16
691 { 446, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_pseudo
692 { 445, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_imm64
693 { 444, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_W
694 { 443, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_H
695 { 442, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_B
696 { 441, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_W
697 { 440, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_H
698 { 439, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_B
699 { 438, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSX
700 { 437, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWACQ32
701 { 436, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW32
702 { 435, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW
703 { 434, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHSX
704 { 433, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHACQ32
705 { 432, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH32
706 { 431, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH
707 { 430, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDDACQ
708 { 429, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDD
709 { 428, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBSX
710 { 427, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBACQ32
711 { 426, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB32
712 { 425, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB
713 { 424, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JX
714 { 423, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr_32
715 { 422, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr
716 { 421, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri_32
717 { 420, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri
718 { 419, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr_32
719 { 418, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr
720 { 417, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri_32
721 { 416, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri
722 { 415, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr_32
723 { 414, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr
724 { 413, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri_32
725 { 412, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri
726 { 411, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr_32
727 { 410, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr
728 { 409, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri_32
729 { 408, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri
730 { 407, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr_32
731 { 406, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr
732 { 405, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri_32
733 { 404, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri
734 { 403, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr_32
735 { 402, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr
736 { 401, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri_32
737 { 400, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri
738 { 399, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr_32
739 { 398, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr
740 { 397, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri_32
741 { 396, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri
742 { 395, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr_32
743 { 394, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr
744 { 393, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri_32
745 { 392, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri
746 { 391, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr_32
747 { 390, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr
748 { 389, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri_32
749 { 388, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri
750 { 387, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr_32
751 { 386, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr
752 { 385, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri_32
753 { 384, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri
754 { 383, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMPL
755 { 382, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
756 { 381, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr_32
757 { 380, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr
758 { 379, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri_32
759 { 378, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri
760 { 377, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCOND
761 { 376, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 28, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JALX
762 { 375, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 0, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JAL
763 { 374, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr_32
764 { 373, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr
765 { 372, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri_32
766 { 371, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri
767 { 370, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 242, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_ST
768 { 369, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 238, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_SHIFT
769 { 368, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 234, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD64
770 { 367, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 230, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD32
771 { 366, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 227, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGW32
772 { 365, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 224, 2, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGD
773 { 364, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP64
774 { 363, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP32
775 { 362, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP16
776 { 361, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE64
777 { 360, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE32
778 { 359, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE16
779 { 358, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr_32
780 { 357, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr
781 { 356, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri_32
782 { 355, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri
783 { 354, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr_32
784 { 353, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr
785 { 352, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri_32
786 { 351, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri
787 { 350, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDR_SPACE_CAST
788 { 349, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 204, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_64_32
789 { 348, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 198, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32_64
790 { 347, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 192, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32
791 { 346, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri
792 { 345, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_64_32
793 { 344, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 174, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32_64
794 { 343, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 168, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32
795 { 342, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select
796 { 341, 2, 0, 8, 0, 0, 0, BPFOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_STACK_ARG_PSEUDO
797 { 340, 2, 0, 8, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_STACK_ARG_IMM_PSEUDO
798 { 339, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY
799 { 338, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_STACK_ARG_PSEUDO
800 { 337, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIMM64
801 { 336, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FI_ri
802 { 335, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
803 { 334, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
804 { 333, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
805 { 332, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
806 { 331, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
807 { 330, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
808 { 329, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
809 { 328, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
810 { 327, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
811 { 326, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
812 { 325, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
813 { 324, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
814 { 323, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
815 { 322, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
816 { 321, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
817 { 320, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
818 { 319, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
819 { 318, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
820 { 317, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
821 { 316, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
822 { 315, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
823 { 314, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
824 { 313, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
825 { 312, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
826 { 311, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
827 { 310, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
828 { 309, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
829 { 308, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
830 { 307, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
831 { 306, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
832 { 305, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
833 { 304, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
834 { 303, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
835 { 302, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
836 { 301, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
837 { 300, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
838 { 299, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
839 { 298, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
840 { 297, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
841 { 296, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
842 { 295, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
843 { 294, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
844 { 293, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
845 { 292, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
846 { 291, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
847 { 290, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
848 { 289, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
849 { 288, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
850 { 287, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
851 { 286, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
852 { 285, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
853 { 284, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
854 { 283, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
855 { 282, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
856 { 281, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
857 { 280, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
858 { 279, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
859 { 278, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
860 { 277, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
861 { 276, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
862 { 275, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
863 { 274, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
864 { 273, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
865 { 272, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
866 { 271, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
867 { 270, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
868 { 269, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
869 { 268, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
870 { 267, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
871 { 266, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
872 { 265, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
873 { 264, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
874 { 263, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
875 { 262, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
876 { 261, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
877 { 260, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
878 { 259, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
879 { 258, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
880 { 257, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
881 { 256, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
882 { 255, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
883 { 254, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
884 { 253, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
885 { 252, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
886 { 251, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
887 { 250, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
888 { 249, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
889 { 248, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
890 { 247, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
891 { 246, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
892 { 245, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
893 { 244, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
894 { 243, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
895 { 242, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
896 { 241, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
897 { 240, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
898 { 239, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
899 { 238, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
900 { 237, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
901 { 236, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
902 { 235, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
903 { 234, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
904 { 233, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
905 { 232, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
906 { 231, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
907 { 230, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
908 { 229, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
909 { 228, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
910 { 227, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
911 { 226, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
912 { 225, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
913 { 224, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
914 { 223, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
915 { 222, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
916 { 221, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
917 { 220, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
918 { 219, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
919 { 218, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
920 { 217, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
921 { 216, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
922 { 215, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
923 { 214, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
924 { 213, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
925 { 212, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
926 { 211, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
927 { 210, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
928 { 209, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
929 { 208, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
930 { 207, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
931 { 206, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
932 { 205, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
933 { 204, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
934 { 203, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
935 { 202, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
936 { 201, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
937 { 200, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
938 { 199, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
939 { 198, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
940 { 197, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
941 { 196, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
942 { 195, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
943 { 194, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
944 { 193, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
945 { 192, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
946 { 191, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
947 { 190, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
948 { 189, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
949 { 188, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
950 { 187, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
951 { 186, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
952 { 185, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
953 { 184, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
954 { 183, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
955 { 182, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
956 { 181, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
957 { 180, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
958 { 179, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
959 { 178, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
960 { 177, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
961 { 176, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
962 { 175, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
963 { 174, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
964 { 173, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
965 { 172, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
966 { 171, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
967 { 170, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
968 { 169, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
969 { 168, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
970 { 167, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
971 { 166, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
972 { 165, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
973 { 164, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
974 { 163, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
975 { 162, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
976 { 161, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
977 { 160, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
978 { 159, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
979 { 158, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
980 { 157, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
981 { 156, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
982 { 155, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
983 { 154, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
984 { 153, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
985 { 152, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
986 { 151, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
987 { 150, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
988 { 149, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
989 { 148, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
990 { 147, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
991 { 146, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
992 { 145, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
993 { 144, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
994 { 143, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
995 { 142, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
996 { 141, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
997 { 140, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
998 { 139, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
999 { 138, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1000 { 137, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1001 { 136, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1002 { 135, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1003 { 134, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1004 { 133, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1005 { 132, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1006 { 131, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1007 { 130, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1008 { 129, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1009 { 128, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1010 { 127, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1011 { 126, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1012 { 125, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1013 { 124, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1014 { 123, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1015 { 122, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1016 { 121, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1017 { 120, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1018 { 119, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1019 { 118, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1020 { 117, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1021 { 116, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1022 { 115, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1023 { 114, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1024 { 113, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1025 { 112, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1026 { 111, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1027 { 110, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1028 { 109, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1029 { 108, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1030 { 107, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1031 { 106, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1032 { 105, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1033 { 104, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1034 { 103, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1035 { 102, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1036 { 101, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1037 { 100, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1038 { 99, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1039 { 98, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1040 { 97, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1041 { 96, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1042 { 95, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1043 { 94, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1044 { 93, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1045 { 92, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1046 { 91, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1047 { 90, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1048 { 89, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1049 { 88, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1050 { 87, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1051 { 86, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1052 { 85, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1053 { 84, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1054 { 83, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1055 { 82, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1056 { 81, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1057 { 80, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1058 { 79, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1059 { 78, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1060 { 77, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1061 { 76, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1062 { 75, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1063 { 74, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1064 { 73, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1065 { 72, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1066 { 71, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1067 { 70, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1068 { 69, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1069 { 68, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1070 { 67, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1071 { 66, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1072 { 65, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1073 { 64, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1074 { 63, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1075 { 62, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1076 { 61, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1077 { 60, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1078 { 59, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1079 { 58, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1080 { 57, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1081 { 56, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1082 { 55, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1083 { 54, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1084 { 53, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1085 { 52, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1086 { 51, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1087 { 50, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1088 { 49, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1089 { 48, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1090 { 47, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1091 { 46, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1092 { 45, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1093 { 44, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1094 { 43, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1095 { 42, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14771
1096 { 41, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14770
1097 { 40, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1098 { 39, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1099 { 38, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1100 { 37, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1101 { 36, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1102 { 35, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1103 { 34, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1104 { 33, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1105 { 32, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14769
1106 { 31, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1107 { 30, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14348
1108 { 29, 6, 1, 0, 0, 0, 0, BPFOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1109 { 28, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1110 { 27, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1111 { 26, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1112 { 25, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1113 { 24, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1114 { 23, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1115 { 22, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1116 { 21, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1117 { 20, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1118 { 19, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1119 { 18, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1120 { 17, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1121 { 16, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1122 { 15, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1123 { 14, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1124 { 13, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1125 { 12, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1126 { 11, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1127 { 10, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1128 { 9, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1129 { 8, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1130 { 7, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1131 { 6, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1132 { 5, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1133 { 4, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1134 { 3, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1135 { 2, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1136 { 1, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1137 { 0, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1138 }, {
1139 /* 0 */
1140 /* 0 */ BPF::R11, BPF::R11,
1141 /* 2 */ BPF::R0, BPF::R0,
1142 /* 4 */ BPF::W0, BPF::W0,
1143 /* 6 */ BPF::R11,
1144 /* 7 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1145 }, {
1146 0
1147 }, {
1148 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1149 /* 1 */
1150 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1151 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1152 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1153 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1154 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1155 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1156 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1157 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1158 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1159 /* 28 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1160 /* 29 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1161 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1162 /* 34 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1163 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1164 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1165 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1166 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1167 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1168 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1169 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1170 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1171 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1172 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1173 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1174 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1175 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1176 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1177 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1178 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1179 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1180 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1181 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1182 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1183 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1184 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1185 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1186 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1187 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1188 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1189 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1190 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1191 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1192 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1193 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1194 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1195 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1196 /* 151 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1197 /* 154 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1198 /* 156 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1199 /* 160 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1200 /* 162 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1201 /* 168 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1202 /* 174 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1203 /* 180 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1204 /* 186 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1205 /* 192 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1206 /* 198 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1207 /* 204 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1208 /* 210 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1209 /* 213 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1210 /* 216 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1211 /* 219 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1212 /* 222 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1213 /* 224 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1214 /* 227 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1215 /* 230 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1216 /* 234 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1217 /* 238 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1218 /* 242 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1219 /* 246 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1220 /* 249 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1221 /* 252 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1222 /* 255 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1223 /* 258 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1224 /* 261 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1225 /* 263 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1226 /* 265 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1227 /* 267 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1228 /* 269 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1229 /* 271 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1230 /* 274 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1231 /* 278 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1232 }
1233};
1234
1235
1236#ifdef __GNUC__
1237#pragma GCC diagnostic push
1238#pragma GCC diagnostic ignored "-Woverlength-strings"
1239#endif
1240extern const char BPFInstrNameData[] = {
1241 /* 0 */ "G_FLOG10\000"
1242 /* 9 */ "G_FEXP10\000"
1243 /* 18 */ "LDB32\000"
1244 /* 24 */ "STB32\000"
1245 /* 30 */ "CORE_LD32\000"
1246 /* 40 */ "BE32\000"
1247 /* 45 */ "LE32\000"
1248 /* 50 */ "LDH32\000"
1249 /* 56 */ "STH32\000"
1250 /* 62 */ "STBREL32\000"
1251 /* 71 */ "STHREL32\000"
1252 /* 80 */ "STWREL32\000"
1253 /* 89 */ "BSWAP32\000"
1254 /* 97 */ "LDBACQ32\000"
1255 /* 106 */ "LDHACQ32\000"
1256 /* 115 */ "LDWACQ32\000"
1257 /* 124 */ "XFADDW32\000"
1258 /* 133 */ "XADDW32\000"
1259 /* 141 */ "LDW32\000"
1260 /* 147 */ "XFANDW32\000"
1261 /* 156 */ "XANDW32\000"
1262 /* 164 */ "CMPXCHGW32\000"
1263 /* 175 */ "XFORW32\000"
1264 /* 183 */ "XFXORW32\000"
1265 /* 192 */ "XXORW32\000"
1266 /* 200 */ "STW32\000"
1267 /* 206 */ "Select_Ri_64_32\000"
1268 /* 222 */ "Select_64_32\000"
1269 /* 235 */ "NEG_32\000"
1270 /* 242 */ "Select_Ri_32\000"
1271 /* 255 */ "SRA_ri_32\000"
1272 /* 265 */ "SUB_ri_32\000"
1273 /* 275 */ "ADD_ri_32\000"
1274 /* 285 */ "AND_ri_32\000"
1275 /* 295 */ "SMOD_ri_32\000"
1276 /* 306 */ "JSGE_ri_32\000"
1277 /* 317 */ "JUGE_ri_32\000"
1278 /* 328 */ "JSLE_ri_32\000"
1279 /* 339 */ "JULE_ri_32\000"
1280 /* 350 */ "JNE_ri_32\000"
1281 /* 360 */ "SLL_ri_32\000"
1282 /* 370 */ "SRL_ri_32\000"
1283 /* 380 */ "MUL_ri_32\000"
1284 /* 390 */ "JEQ_ri_32\000"
1285 /* 400 */ "XOR_ri_32\000"
1286 /* 410 */ "JSET_ri_32\000"
1287 /* 421 */ "JSGT_ri_32\000"
1288 /* 432 */ "JUGT_ri_32\000"
1289 /* 443 */ "JSLT_ri_32\000"
1290 /* 454 */ "JULT_ri_32\000"
1291 /* 465 */ "SDIV_ri_32\000"
1292 /* 476 */ "MOV_ri_32\000"
1293 /* 486 */ "SRA_rr_32\000"
1294 /* 496 */ "SUB_rr_32\000"
1295 /* 506 */ "ADD_rr_32\000"
1296 /* 516 */ "AND_rr_32\000"
1297 /* 526 */ "SMOD_rr_32\000"
1298 /* 537 */ "JSGE_rr_32\000"
1299 /* 548 */ "JUGE_rr_32\000"
1300 /* 559 */ "JSLE_rr_32\000"
1301 /* 570 */ "JULE_rr_32\000"
1302 /* 581 */ "JNE_rr_32\000"
1303 /* 591 */ "SLL_rr_32\000"
1304 /* 601 */ "SRL_rr_32\000"
1305 /* 611 */ "MUL_rr_32\000"
1306 /* 621 */ "JEQ_rr_32\000"
1307 /* 631 */ "XOR_rr_32\000"
1308 /* 641 */ "JSET_rr_32\000"
1309 /* 652 */ "JSGT_rr_32\000"
1310 /* 663 */ "JUGT_rr_32\000"
1311 /* 674 */ "JSLT_rr_32\000"
1312 /* 685 */ "JULT_rr_32\000"
1313 /* 696 */ "SDIV_rr_32\000"
1314 /* 707 */ "MOV_rr_32\000"
1315 /* 717 */ "MOVSX_rr_32\000"
1316 /* 729 */ "Select_32\000"
1317 /* 739 */ "G_FLOG2\000"
1318 /* 747 */ "G_FATAN2\000"
1319 /* 756 */ "G_FEXP2\000"
1320 /* 764 */ "CORE_LD64\000"
1321 /* 774 */ "BE64\000"
1322 /* 779 */ "LE64\000"
1323 /* 784 */ "LDIMM64\000"
1324 /* 792 */ "BSWAP64\000"
1325 /* 800 */ "MOV_32_64\000"
1326 /* 810 */ "Select_Ri_32_64\000"
1327 /* 826 */ "Select_32_64\000"
1328 /* 839 */ "NEG_64\000"
1329 /* 846 */ "LD_imm64\000"
1330 /* 855 */ "BE16\000"
1331 /* 860 */ "LE16\000"
1332 /* 865 */ "BSWAP16\000"
1333 /* 873 */ "MOVSX_rr_32_16\000"
1334 /* 888 */ "MOVSX_rr_16\000"
1335 /* 900 */ "MOVSX_rr_32_8\000"
1336 /* 914 */ "MOVSX_rr_8\000"
1337 /* 925 */ "G_FMA\000"
1338 /* 931 */ "G_STRICT_FMA\000"
1339 /* 944 */ "LDB\000"
1340 /* 948 */ "STB\000"
1341 /* 952 */ "G_FSUB\000"
1342 /* 959 */ "G_STRICT_FSUB\000"
1343 /* 973 */ "G_ATOMICRMW_FSUB\000"
1344 /* 990 */ "G_SUB\000"
1345 /* 996 */ "G_ATOMICRMW_SUB\000"
1346 /* 1012 */ "LD_IND_B\000"
1347 /* 1021 */ "LD_ABS_B\000"
1348 /* 1030 */ "G_INTRINSIC\000"
1349 /* 1042 */ "G_FPTRUNC\000"
1350 /* 1052 */ "G_INTRINSIC_TRUNC\000"
1351 /* 1070 */ "G_TRUNC\000"
1352 /* 1078 */ "G_BUILD_VECTOR_TRUNC\000"
1353 /* 1099 */ "G_DYN_STACKALLOC\000"
1354 /* 1116 */ "G_FMAD\000"
1355 /* 1123 */ "G_FPEXTLOAD\000"
1356 /* 1135 */ "G_INDEXED_SEXTLOAD\000"
1357 /* 1154 */ "G_SEXTLOAD\000"
1358 /* 1165 */ "G_INDEXED_ZEXTLOAD\000"
1359 /* 1184 */ "G_ZEXTLOAD\000"
1360 /* 1195 */ "G_INDEXED_LOAD\000"
1361 /* 1210 */ "G_LOAD\000"
1362 /* 1217 */ "G_VECREDUCE_FADD\000"
1363 /* 1234 */ "G_FADD\000"
1364 /* 1241 */ "G_VECREDUCE_SEQ_FADD\000"
1365 /* 1262 */ "G_STRICT_FADD\000"
1366 /* 1276 */ "G_ATOMICRMW_FADD\000"
1367 /* 1293 */ "G_VECREDUCE_ADD\000"
1368 /* 1309 */ "G_ADD\000"
1369 /* 1315 */ "G_PTR_ADD\000"
1370 /* 1325 */ "G_ATOMICRMW_ADD\000"
1371 /* 1341 */ "XFADDD\000"
1372 /* 1348 */ "XADDD\000"
1373 /* 1354 */ "LDD\000"
1374 /* 1358 */ "XFANDD\000"
1375 /* 1365 */ "XANDD\000"
1376 /* 1371 */ "CMPXCHGD\000"
1377 /* 1380 */ "G_ATOMICRMW_NAND\000"
1378 /* 1397 */ "G_VECREDUCE_AND\000"
1379 /* 1413 */ "G_AND\000"
1380 /* 1419 */ "G_ATOMICRMW_AND\000"
1381 /* 1435 */ "LIFETIME_END\000"
1382 /* 1448 */ "JCOND\000"
1383 /* 1454 */ "G_BRCOND\000"
1384 /* 1463 */ "G_ATOMICRMW_USUB_COND\000"
1385 /* 1485 */ "G_LLROUND\000"
1386 /* 1495 */ "G_LROUND\000"
1387 /* 1504 */ "G_INTRINSIC_ROUND\000"
1388 /* 1522 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1389 /* 1548 */ "LOAD_STACK_GUARD\000"
1390 /* 1565 */ "XFORD\000"
1391 /* 1571 */ "XFXORD\000"
1392 /* 1578 */ "XXORD\000"
1393 /* 1584 */ "STD\000"
1394 /* 1588 */ "PSEUDO_PROBE\000"
1395 /* 1601 */ "G_SSUBE\000"
1396 /* 1609 */ "G_USUBE\000"
1397 /* 1617 */ "G_FENCE\000"
1398 /* 1625 */ "ARITH_FENCE\000"
1399 /* 1637 */ "REG_SEQUENCE\000"
1400 /* 1650 */ "G_SADDE\000"
1401 /* 1658 */ "G_UADDE\000"
1402 /* 1666 */ "G_GET_FPMODE\000"
1403 /* 1679 */ "G_RESET_FPMODE\000"
1404 /* 1694 */ "G_SET_FPMODE\000"
1405 /* 1707 */ "G_FMINNUM_IEEE\000"
1406 /* 1722 */ "G_FMAXNUM_IEEE\000"
1407 /* 1737 */ "G_VSCALE\000"
1408 /* 1746 */ "G_JUMP_TABLE\000"
1409 /* 1759 */ "BUNDLE\000"
1410 /* 1766 */ "G_MEMSET_INLINE\000"
1411 /* 1782 */ "G_MEMCPY_INLINE\000"
1412 /* 1798 */ "RELOC_NONE\000"
1413 /* 1809 */ "LOCAL_ESCAPE\000"
1414 /* 1822 */ "G_FPTRUNCSTORE\000"
1415 /* 1837 */ "G_STACKRESTORE\000"
1416 /* 1852 */ "G_INDEXED_STORE\000"
1417 /* 1868 */ "G_STORE\000"
1418 /* 1876 */ "G_BITREVERSE\000"
1419 /* 1889 */ "FAKE_USE\000"
1420 /* 1898 */ "DBG_VALUE\000"
1421 /* 1908 */ "G_GLOBAL_VALUE\000"
1422 /* 1923 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1423 /* 1946 */ "CONVERGENCECTRL_GLUE\000"
1424 /* 1967 */ "G_STACKSAVE\000"
1425 /* 1979 */ "G_MEMMOVE\000"
1426 /* 1989 */ "G_FREEZE\000"
1427 /* 1998 */ "G_FCANONICALIZE\000"
1428 /* 2014 */ "G_FMODF\000"
1429 /* 2022 */ "INIT_UNDEF\000"
1430 /* 2033 */ "G_IMPLICIT_DEF\000"
1431 /* 2048 */ "DBG_INSTR_REF\000"
1432 /* 2062 */ "G_FNEG\000"
1433 /* 2069 */ "EXTRACT_SUBREG\000"
1434 /* 2084 */ "INSERT_SUBREG\000"
1435 /* 2098 */ "G_SEXT_INREG\000"
1436 /* 2111 */ "SUBREG_TO_REG\000"
1437 /* 2125 */ "G_ATOMIC_CMPXCHG\000"
1438 /* 2142 */ "G_ATOMICRMW_XCHG\000"
1439 /* 2159 */ "G_GET_ROUNDING\000"
1440 /* 2174 */ "G_SET_ROUNDING\000"
1441 /* 2189 */ "G_FLOG\000"
1442 /* 2196 */ "G_VAARG\000"
1443 /* 2204 */ "PREALLOCATED_ARG\000"
1444 /* 2221 */ "G_PREFETCH\000"
1445 /* 2232 */ "LDH\000"
1446 /* 2236 */ "G_CLMULH\000"
1447 /* 2245 */ "G_SMULH\000"
1448 /* 2253 */ "G_UMULH\000"
1449 /* 2261 */ "G_FTANH\000"
1450 /* 2269 */ "G_FSINH\000"
1451 /* 2277 */ "G_FCOSH\000"
1452 /* 2285 */ "STH\000"
1453 /* 2289 */ "LD_IND_H\000"
1454 /* 2298 */ "LD_ABS_H\000"
1455 /* 2307 */ "DBG_PHI\000"
1456 /* 2315 */ "G_FPTOSI\000"
1457 /* 2324 */ "G_FPTOUI\000"
1458 /* 2333 */ "G_FPOWI\000"
1459 /* 2341 */ "COPY_LANEMASK\000"
1460 /* 2355 */ "G_PTRMASK\000"
1461 /* 2365 */ "JAL\000"
1462 /* 2369 */ "GC_LABEL\000"
1463 /* 2378 */ "DBG_LABEL\000"
1464 /* 2388 */ "EH_LABEL\000"
1465 /* 2397 */ "ANNOTATION_LABEL\000"
1466 /* 2414 */ "ICALL_BRANCH_FUNNEL\000"
1467 /* 2434 */ "STDREL\000"
1468 /* 2441 */ "G_FSHL\000"
1469 /* 2448 */ "G_SHL\000"
1470 /* 2454 */ "G_FCEIL\000"
1471 /* 2462 */ "G_SAVGCEIL\000"
1472 /* 2473 */ "G_UAVGCEIL\000"
1473 /* 2484 */ "PATCHABLE_TAIL_CALL\000"
1474 /* 2504 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1475 /* 2531 */ "PATCHABLE_EVENT_CALL\000"
1476 /* 2552 */ "FENTRY_CALL\000"
1477 /* 2564 */ "KILL\000"
1478 /* 2569 */ "G_CONSTANT_POOL\000"
1479 /* 2585 */ "JMPL\000"
1480 /* 2590 */ "G_ROTL\000"
1481 /* 2597 */ "G_VECREDUCE_FMUL\000"
1482 /* 2614 */ "G_FMUL\000"
1483 /* 2621 */ "G_VECREDUCE_SEQ_FMUL\000"
1484 /* 2642 */ "G_STRICT_FMUL\000"
1485 /* 2656 */ "G_CLMUL\000"
1486 /* 2664 */ "G_VECREDUCE_MUL\000"
1487 /* 2680 */ "G_MUL\000"
1488 /* 2686 */ "G_FREM\000"
1489 /* 2693 */ "G_STRICT_FREM\000"
1490 /* 2707 */ "G_SREM\000"
1491 /* 2714 */ "G_UREM\000"
1492 /* 2721 */ "G_SDIVREM\000"
1493 /* 2731 */ "G_UDIVREM\000"
1494 /* 2741 */ "INLINEASM\000"
1495 /* 2751 */ "G_VECREDUCE_FMINIMUM\000"
1496 /* 2772 */ "G_FMINIMUM\000"
1497 /* 2783 */ "G_ATOMICRMW_FMINIMUM\000"
1498 /* 2804 */ "G_VECREDUCE_FMAXIMUM\000"
1499 /* 2825 */ "G_FMAXIMUM\000"
1500 /* 2836 */ "G_ATOMICRMW_FMAXIMUM\000"
1501 /* 2857 */ "G_VECREDUCE_FMINIMUMNUM\000"
1502 /* 2881 */ "G_FMINIMUMNUM\000"
1503 /* 2895 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1504 /* 2919 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1505 /* 2943 */ "G_FMAXIMUMNUM\000"
1506 /* 2957 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1507 /* 2981 */ "G_FMINNUM\000"
1508 /* 2991 */ "G_FMAXNUM\000"
1509 /* 3001 */ "G_FATAN\000"
1510 /* 3009 */ "G_FTAN\000"
1511 /* 3016 */ "G_INTRINSIC_ROUNDEVEN\000"
1512 /* 3038 */ "G_ASSERT_ALIGN\000"
1513 /* 3053 */ "G_FCOPYSIGN\000"
1514 /* 3065 */ "G_VECREDUCE_FMIN\000"
1515 /* 3082 */ "G_ATOMICRMW_FMIN\000"
1516 /* 3099 */ "G_VECREDUCE_SMIN\000"
1517 /* 3116 */ "G_SMIN\000"
1518 /* 3123 */ "G_VECREDUCE_UMIN\000"
1519 /* 3140 */ "G_UMIN\000"
1520 /* 3147 */ "G_ATOMICRMW_UMIN\000"
1521 /* 3164 */ "G_ATOMICRMW_MIN\000"
1522 /* 3180 */ "G_FASIN\000"
1523 /* 3188 */ "G_FSIN\000"
1524 /* 3195 */ "CFI_INSTRUCTION\000"
1525 /* 3211 */ "G_CTLZ_ZERO_POISON\000"
1526 /* 3230 */ "G_CTTZ_ZERO_POISON\000"
1527 /* 3249 */ "ADJCALLSTACKDOWN\000"
1528 /* 3266 */ "G_SSUBO\000"
1529 /* 3274 */ "G_USUBO\000"
1530 /* 3282 */ "G_SADDO\000"
1531 /* 3290 */ "G_UADDO\000"
1532 /* 3298 */ "LOAD_STACK_ARG_PSEUDO\000"
1533 /* 3320 */ "STORE_STACK_ARG_PSEUDO\000"
1534 /* 3343 */ "STORE_STACK_ARG_IMM_PSEUDO\000"
1535 /* 3370 */ "JUMP_TABLE_DEBUG_INFO\000"
1536 /* 3392 */ "G_SMULO\000"
1537 /* 3400 */ "G_UMULO\000"
1538 /* 3408 */ "G_BZERO\000"
1539 /* 3416 */ "STACKMAP\000"
1540 /* 3425 */ "G_DEBUGTRAP\000"
1541 /* 3437 */ "G_UBSANTRAP\000"
1542 /* 3449 */ "G_TRAP\000"
1543 /* 3456 */ "G_ATOMICRMW_UDEC_WRAP\000"
1544 /* 3478 */ "G_ATOMICRMW_UINC_WRAP\000"
1545 /* 3500 */ "G_BSWAP\000"
1546 /* 3508 */ "G_SITOFP\000"
1547 /* 3517 */ "G_UITOFP\000"
1548 /* 3526 */ "G_FCMP\000"
1549 /* 3533 */ "G_STRICT_FCMP\000"
1550 /* 3547 */ "G_ICMP\000"
1551 /* 3554 */ "G_SCMP\000"
1552 /* 3561 */ "G_UCMP\000"
1553 /* 3568 */ "JMP\000"
1554 /* 3572 */ "NOP\000"
1555 /* 3576 */ "CONVERGENCECTRL_LOOP\000"
1556 /* 3597 */ "G_CTPOP\000"
1557 /* 3605 */ "PATCHABLE_OP\000"
1558 /* 3618 */ "FAULTING_OP\000"
1559 /* 3630 */ "ADJCALLSTACKUP\000"
1560 /* 3645 */ "PREALLOCATED_SETUP\000"
1561 /* 3664 */ "G_FLDEXP\000"
1562 /* 3673 */ "G_STRICT_FLDEXP\000"
1563 /* 3689 */ "G_FEXP\000"
1564 /* 3696 */ "G_FFREXP\000"
1565 /* 3705 */ "LDDACQ\000"
1566 /* 3712 */ "G_BR\000"
1567 /* 3717 */ "INLINEASM_BR\000"
1568 /* 3730 */ "G_BLOCK_ADDR\000"
1569 /* 3743 */ "MEMBARRIER\000"
1570 /* 3754 */ "G_CONSTANT_FOLD_BARRIER\000"
1571 /* 3778 */ "PATCHABLE_FUNCTION_ENTER\000"
1572 /* 3803 */ "G_READCYCLECOUNTER\000"
1573 /* 3822 */ "G_READSTEADYCOUNTER\000"
1574 /* 3842 */ "G_READ_REGISTER\000"
1575 /* 3858 */ "G_WRITE_REGISTER\000"
1576 /* 3875 */ "G_ASHR\000"
1577 /* 3882 */ "G_FSHR\000"
1578 /* 3889 */ "G_LSHR\000"
1579 /* 3896 */ "CONVERGENCECTRL_ANCHOR\000"
1580 /* 3919 */ "G_FFLOOR\000"
1581 /* 3928 */ "G_SAVGFLOOR\000"
1582 /* 3940 */ "G_UAVGFLOOR\000"
1583 /* 3952 */ "G_EXTRACT_SUBVECTOR\000"
1584 /* 3972 */ "G_INSERT_SUBVECTOR\000"
1585 /* 3991 */ "G_BUILD_VECTOR\000"
1586 /* 4006 */ "G_SHUFFLE_VECTOR\000"
1587 /* 4023 */ "G_STEP_VECTOR\000"
1588 /* 4037 */ "G_SPLAT_VECTOR\000"
1589 /* 4052 */ "G_VECREDUCE_XOR\000"
1590 /* 4068 */ "G_XOR\000"
1591 /* 4074 */ "G_ATOMICRMW_XOR\000"
1592 /* 4090 */ "G_VECREDUCE_OR\000"
1593 /* 4105 */ "G_OR\000"
1594 /* 4110 */ "G_ATOMICRMW_OR\000"
1595 /* 4125 */ "G_ROTR\000"
1596 /* 4132 */ "G_INTTOPTR\000"
1597 /* 4143 */ "G_FABS\000"
1598 /* 4150 */ "G_ABS\000"
1599 /* 4156 */ "G_ABDS\000"
1600 /* 4163 */ "G_UNMERGE_VALUES\000"
1601 /* 4180 */ "G_MERGE_VALUES\000"
1602 /* 4195 */ "G_CTLS\000"
1603 /* 4202 */ "G_FACOS\000"
1604 /* 4210 */ "G_FCOS\000"
1605 /* 4217 */ "G_FSINCOS\000"
1606 /* 4227 */ "G_STRICT_FCMPS\000"
1607 /* 4242 */ "G_CONCAT_VECTORS\000"
1608 /* 4259 */ "COPY_TO_REGCLASS\000"
1609 /* 4276 */ "G_IS_FPCLASS\000"
1610 /* 4289 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1611 /* 4319 */ "G_VECTOR_COMPRESS\000"
1612 /* 4337 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1613 /* 4364 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1614 /* 4402 */ "G_TRUNC_SSAT_S\000"
1615 /* 4417 */ "G_SSUBSAT\000"
1616 /* 4427 */ "G_USUBSAT\000"
1617 /* 4437 */ "G_SADDSAT\000"
1618 /* 4447 */ "G_UADDSAT\000"
1619 /* 4457 */ "G_SSHLSAT\000"
1620 /* 4467 */ "G_USHLSAT\000"
1621 /* 4477 */ "G_SMULFIXSAT\000"
1622 /* 4490 */ "G_UMULFIXSAT\000"
1623 /* 4503 */ "G_SDIVFIXSAT\000"
1624 /* 4516 */ "G_UDIVFIXSAT\000"
1625 /* 4529 */ "G_ATOMICRMW_USUB_SAT\000"
1626 /* 4550 */ "G_FPTOSI_SAT\000"
1627 /* 4563 */ "G_FPTOUI_SAT\000"
1628 /* 4576 */ "G_EXTRACT\000"
1629 /* 4586 */ "G_SELECT\000"
1630 /* 4595 */ "G_BRINDIRECT\000"
1631 /* 4608 */ "PATCHABLE_RET\000"
1632 /* 4622 */ "G_MEMSET\000"
1633 /* 4631 */ "CORE_SHIFT\000"
1634 /* 4642 */ "PATCHABLE_FUNCTION_EXIT\000"
1635 /* 4666 */ "G_BRJT\000"
1636 /* 4673 */ "G_EXTRACT_VECTOR_ELT\000"
1637 /* 4694 */ "G_INSERT_VECTOR_ELT\000"
1638 /* 4714 */ "G_FCONSTANT\000"
1639 /* 4726 */ "G_CONSTANT\000"
1640 /* 4737 */ "G_INTRINSIC_CONVERGENT\000"
1641 /* 4760 */ "STATEPOINT\000"
1642 /* 4771 */ "PATCHPOINT\000"
1643 /* 4782 */ "G_PTRTOINT\000"
1644 /* 4793 */ "G_FRINT\000"
1645 /* 4801 */ "G_INTRINSIC_LLRINT\000"
1646 /* 4820 */ "G_INTRINSIC_LRINT\000"
1647 /* 4838 */ "G_FNEARBYINT\000"
1648 /* 4851 */ "G_VASTART\000"
1649 /* 4861 */ "LIFETIME_START\000"
1650 /* 4876 */ "G_INVOKE_REGION_START\000"
1651 /* 4898 */ "G_INSERT\000"
1652 /* 4907 */ "G_FSQRT\000"
1653 /* 4915 */ "G_STRICT_FSQRT\000"
1654 /* 4930 */ "G_BITCAST\000"
1655 /* 4940 */ "G_ADDRSPACE_CAST\000"
1656 /* 4957 */ "ADDR_SPACE_CAST\000"
1657 /* 4973 */ "DBG_VALUE_LIST\000"
1658 /* 4988 */ "CORE_ST\000"
1659 /* 4996 */ "G_FPEXT\000"
1660 /* 5004 */ "G_SEXT\000"
1661 /* 5011 */ "G_ASSERT_SEXT\000"
1662 /* 5025 */ "G_ANYEXT\000"
1663 /* 5034 */ "G_ZEXT\000"
1664 /* 5041 */ "G_ASSERT_ZEXT\000"
1665 /* 5055 */ "G_ABDU\000"
1666 /* 5062 */ "G_TRUNC_SSAT_U\000"
1667 /* 5077 */ "G_TRUNC_USAT_U\000"
1668 /* 5092 */ "G_FDIV\000"
1669 /* 5099 */ "G_STRICT_FDIV\000"
1670 /* 5113 */ "G_SDIV\000"
1671 /* 5120 */ "G_UDIV\000"
1672 /* 5127 */ "G_GET_FPENV\000"
1673 /* 5139 */ "G_RESET_FPENV\000"
1674 /* 5153 */ "G_SET_FPENV\000"
1675 /* 5165 */ "XADDW\000"
1676 /* 5171 */ "LDW\000"
1677 /* 5175 */ "G_FPOW\000"
1678 /* 5182 */ "STW\000"
1679 /* 5186 */ "LD_IND_W\000"
1680 /* 5195 */ "LD_ABS_W\000"
1681 /* 5204 */ "G_VECREDUCE_FMAX\000"
1682 /* 5221 */ "G_ATOMICRMW_FMAX\000"
1683 /* 5238 */ "G_VECREDUCE_SMAX\000"
1684 /* 5255 */ "G_SMAX\000"
1685 /* 5262 */ "G_VECREDUCE_UMAX\000"
1686 /* 5279 */ "G_UMAX\000"
1687 /* 5286 */ "G_ATOMICRMW_UMAX\000"
1688 /* 5303 */ "G_ATOMICRMW_MAX\000"
1689 /* 5319 */ "G_FRAME_INDEX\000"
1690 /* 5333 */ "G_SBFX\000"
1691 /* 5340 */ "G_UBFX\000"
1692 /* 5347 */ "G_SMULFIX\000"
1693 /* 5357 */ "G_UMULFIX\000"
1694 /* 5367 */ "G_SDIVFIX\000"
1695 /* 5377 */ "G_UDIVFIX\000"
1696 /* 5387 */ "JX\000"
1697 /* 5390 */ "JALX\000"
1698 /* 5395 */ "LDBSX\000"
1699 /* 5401 */ "LDHSX\000"
1700 /* 5407 */ "LDWSX\000"
1701 /* 5413 */ "G_MEMCPY\000"
1702 /* 5422 */ "COPY\000"
1703 /* 5427 */ "CONVERGENCECTRL_ENTRY\000"
1704 /* 5449 */ "G_CTLZ\000"
1705 /* 5456 */ "G_CTTZ\000"
1706 /* 5463 */ "Select_Ri\000"
1707 /* 5473 */ "SRA_ri\000"
1708 /* 5480 */ "SUB_ri\000"
1709 /* 5487 */ "ADD_ri\000"
1710 /* 5494 */ "AND_ri\000"
1711 /* 5501 */ "SMOD_ri\000"
1712 /* 5509 */ "JSGE_ri\000"
1713 /* 5517 */ "JUGE_ri\000"
1714 /* 5525 */ "JSLE_ri\000"
1715 /* 5533 */ "JULE_ri\000"
1716 /* 5541 */ "JNE_ri\000"
1717 /* 5548 */ "FI_ri\000"
1718 /* 5554 */ "SLL_ri\000"
1719 /* 5561 */ "SRL_ri\000"
1720 /* 5568 */ "MUL_ri\000"
1721 /* 5575 */ "JEQ_ri\000"
1722 /* 5582 */ "XOR_ri\000"
1723 /* 5589 */ "JSET_ri\000"
1724 /* 5597 */ "JSGT_ri\000"
1725 /* 5605 */ "JUGT_ri\000"
1726 /* 5613 */ "JSLT_ri\000"
1727 /* 5621 */ "JULT_ri\000"
1728 /* 5629 */ "SDIV_ri\000"
1729 /* 5637 */ "MOV_ri\000"
1730 /* 5644 */ "STB_imm\000"
1731 /* 5652 */ "STD_imm\000"
1732 /* 5660 */ "STH_imm\000"
1733 /* 5668 */ "STW_imm\000"
1734 /* 5676 */ "LD_pseudo\000"
1735 /* 5686 */ "SRA_rr\000"
1736 /* 5693 */ "SUB_rr\000"
1737 /* 5700 */ "ADD_rr\000"
1738 /* 5707 */ "AND_rr\000"
1739 /* 5714 */ "SMOD_rr\000"
1740 /* 5722 */ "JSGE_rr\000"
1741 /* 5730 */ "JUGE_rr\000"
1742 /* 5738 */ "JSLE_rr\000"
1743 /* 5746 */ "JULE_rr\000"
1744 /* 5754 */ "JNE_rr\000"
1745 /* 5761 */ "SLL_rr\000"
1746 /* 5768 */ "SRL_rr\000"
1747 /* 5775 */ "MUL_rr\000"
1748 /* 5782 */ "JEQ_rr\000"
1749 /* 5789 */ "XOR_rr\000"
1750 /* 5796 */ "JSET_rr\000"
1751 /* 5804 */ "JSGT_rr\000"
1752 /* 5812 */ "JUGT_rr\000"
1753 /* 5820 */ "JSLT_rr\000"
1754 /* 5828 */ "JULT_rr\000"
1755 /* 5836 */ "SDIV_rr\000"
1756 /* 5844 */ "MOV_rr\000"
1757 /* 5851 */ "Select\000"
1758};
1759#ifdef __GNUC__
1760#pragma GCC diagnostic pop
1761#endif
1762
1763extern const unsigned BPFInstrNameIndices[] = {
1764 2311U, 2741U, 3717U, 3195U, 2388U, 2369U, 2397U, 2564U,
1765 2069U, 2084U, 2035U, 2022U, 2111U, 4259U, 1898U, 4973U,
1766 2048U, 2307U, 2378U, 1637U, 5422U, 2341U, 1759U, 4861U,
1767 1435U, 1588U, 1625U, 3416U, 2552U, 4771U, 1548U, 3645U,
1768 2204U, 4760U, 1809U, 3618U, 3605U, 3778U, 4608U, 4642U,
1769 2484U, 2531U, 2504U, 2414U, 1889U, 3743U, 3370U, 1798U,
1770 5427U, 3896U, 3576U, 1946U, 5011U, 5041U, 3038U, 1309U,
1771 990U, 2680U, 5113U, 5120U, 2707U, 2714U, 2721U, 2731U,
1772 1413U, 4105U, 4068U, 4156U, 5055U, 3940U, 2473U, 3928U,
1773 2462U, 2033U, 2309U, 5319U, 1908U, 1923U, 2569U, 4576U,
1774 4163U, 4898U, 4180U, 3991U, 1078U, 4242U, 4782U, 4132U,
1775 4930U, 1989U, 3754U, 1522U, 1052U, 1504U, 4820U, 4801U,
1776 3016U, 3803U, 3822U, 1210U, 1154U, 1184U, 1123U, 1195U,
1777 1135U, 1165U, 1868U, 1822U, 1852U, 4289U, 2125U, 2142U,
1778 1325U, 996U, 1419U, 1380U, 4110U, 4074U, 5303U, 3164U,
1779 5286U, 3147U, 1276U, 973U, 5221U, 3082U, 2836U, 2783U,
1780 2957U, 2895U, 3478U, 3456U, 1463U, 4529U, 1617U, 2221U,
1781 1454U, 4595U, 4876U, 1030U, 4337U, 4737U, 4364U, 5025U,
1782 1070U, 4402U, 5062U, 5077U, 4726U, 4714U, 4851U, 2196U,
1783 5004U, 2098U, 5034U, 2448U, 3889U, 3875U, 2441U, 3882U,
1784 4125U, 2590U, 3547U, 3526U, 3554U, 3561U, 4586U, 3290U,
1785 1658U, 3274U, 1609U, 3282U, 1650U, 3266U, 1601U, 3400U,
1786 3392U, 2253U, 2245U, 4447U, 4437U, 4427U, 4417U, 4467U,
1787 4457U, 5347U, 5357U, 4477U, 4490U, 5367U, 5377U, 4503U,
1788 4516U, 1234U, 952U, 2614U, 925U, 1116U, 5092U, 2686U,
1789 2014U, 5175U, 2333U, 3689U, 756U, 9U, 2189U, 739U,
1790 0U, 3664U, 3696U, 2062U, 4996U, 1042U, 2315U, 2324U,
1791 3508U, 3517U, 4550U, 4563U, 4143U, 3053U, 4276U, 1998U,
1792 2981U, 2991U, 1707U, 1722U, 2772U, 2825U, 2881U, 2943U,
1793 5127U, 5153U, 5139U, 1666U, 1694U, 1679U, 2159U, 2174U,
1794 1315U, 2355U, 3116U, 5255U, 3140U, 5279U, 4150U, 1495U,
1795 1485U, 3712U, 4666U, 1737U, 3972U, 3952U, 4694U, 4673U,
1796 4006U, 4037U, 4023U, 4319U, 5456U, 3230U, 5449U, 3211U,
1797 4195U, 3597U, 3500U, 1876U, 2656U, 2236U, 2454U, 4210U,
1798 3188U, 4217U, 3009U, 4202U, 3180U, 3001U, 747U, 2277U,
1799 2269U, 2261U, 4907U, 3919U, 4793U, 4838U, 4940U, 3730U,
1800 1746U, 1099U, 1967U, 1837U, 1262U, 959U, 2642U, 5099U,
1801 2693U, 931U, 4915U, 3673U, 3533U, 4227U, 3842U, 3858U,
1802 5413U, 1782U, 1979U, 4622U, 3408U, 1766U, 3449U, 3425U,
1803 3437U, 1241U, 2621U, 1217U, 2597U, 5204U, 3065U, 2804U,
1804 2751U, 2919U, 2857U, 1293U, 2664U, 1397U, 4090U, 4052U,
1805 5238U, 3099U, 5262U, 3123U, 5333U, 5340U, 3249U, 3630U,
1806 5548U, 784U, 3298U, 5415U, 3343U, 3320U, 5851U, 729U,
1807 826U, 222U, 5463U, 242U, 810U, 206U, 4957U, 5487U,
1808 275U, 5700U, 506U, 5494U, 285U, 5707U, 516U, 855U,
1809 40U, 774U, 865U, 89U, 792U, 1371U, 164U, 30U,
1810 764U, 4631U, 4988U, 5630U, 466U, 5837U, 697U, 2365U,
1811 5390U, 1448U, 5575U, 390U, 5782U, 621U, 3568U, 2585U,
1812 5541U, 350U, 5754U, 581U, 5589U, 410U, 5796U, 641U,
1813 5509U, 306U, 5722U, 537U, 5597U, 421U, 5804U, 652U,
1814 5525U, 328U, 5738U, 559U, 5613U, 443U, 5820U, 674U,
1815 5517U, 317U, 5730U, 548U, 5605U, 432U, 5812U, 663U,
1816 5533U, 339U, 5746U, 570U, 5621U, 454U, 5828U, 685U,
1817 5387U, 944U, 18U, 97U, 5395U, 1354U, 3705U, 2232U,
1818 50U, 106U, 5401U, 5171U, 141U, 115U, 5407U, 1021U,
1819 2298U, 5195U, 1012U, 2289U, 5186U, 846U, 5676U, 860U,
1820 45U, 779U, 5502U, 296U, 5715U, 527U, 888U, 717U,
1821 873U, 900U, 914U, 800U, 5637U, 476U, 5844U, 707U,
1822 5568U, 380U, 5775U, 611U, 235U, 839U, 3572U, 5583U,
1823 401U, 5790U, 632U, 4618U, 5629U, 465U, 5836U, 696U,
1824 5554U, 360U, 5761U, 591U, 5501U, 295U, 5714U, 526U,
1825 5473U, 255U, 5686U, 486U, 5561U, 370U, 5768U, 601U,
1826 948U, 24U, 62U, 5644U, 1584U, 2434U, 5652U, 2285U,
1827 56U, 71U, 5660U, 5182U, 200U, 80U, 5668U, 5480U,
1828 265U, 5693U, 496U, 1348U, 5165U, 133U, 1365U, 156U,
1829 1374U, 167U, 1341U, 124U, 1358U, 147U, 1565U, 175U,
1830 1571U, 183U, 1573U, 185U, 5582U, 400U, 5789U, 631U,
1831 1578U, 192U,
1832};
1833
1834static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
1835 II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 538, nullptr, 0);
1836}
1837
1838
1839} // namespace llvm
1840
1841#endif // GET_INSTRINFO_MC_DESC
1842
1843#ifdef GET_INSTRINFO_HEADER
1844#undef GET_INSTRINFO_HEADER
1845
1846namespace llvm {
1847
1848struct BPFGenInstrInfo : public TargetInstrInfo {
1849 explicit BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1850 ~BPFGenInstrInfo() override = default;
1851};
1852
1853} // namespace llvm
1854
1855namespace llvm::BPF {
1856
1857
1858} // namespace llvm::BPF
1859
1860#endif // GET_INSTRINFO_HEADER
1861
1862#ifdef GET_INSTRINFO_HELPER_DECLS
1863#undef GET_INSTRINFO_HELPER_DECLS
1864
1865
1866#endif // GET_INSTRINFO_HELPER_DECLS
1867
1868#ifdef GET_INSTRINFO_HELPERS
1869#undef GET_INSTRINFO_HELPERS
1870
1871
1872#endif // GET_INSTRINFO_HELPERS
1873
1874#ifdef GET_INSTRINFO_CTOR_DTOR
1875#undef GET_INSTRINFO_CTOR_DTOR
1876
1877namespace llvm {
1878
1879extern const BPFInstrTable BPFDescs;
1880extern const unsigned BPFInstrNameIndices[];
1881extern const char BPFInstrNameData[];
1882BPFGenInstrInfo::BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1883 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1884 InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 538);
1885}
1886
1887} // namespace llvm
1888
1889#endif // GET_INSTRINFO_CTOR_DTOR
1890
1891#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1892#undef GET_INSTRINFO_MC_HELPER_DECLS
1893
1894namespace llvm {
1895
1896class MCInst;
1897class FeatureBitset;
1898
1899namespace BPF_MC {
1900
1901void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1902
1903} // namespace BPF_MC
1904
1905} // namespace llvm
1906
1907#endif // GET_INSTRINFO_MC_HELPER_DECLS
1908
1909#ifdef GET_INSTRINFO_MC_HELPERS
1910#undef GET_INSTRINFO_MC_HELPERS
1911
1912namespace llvm::BPF_MC {
1913
1914
1915} // namespace llvm::BPF_MC
1916
1917#endif // GET_INSTRINFO_MC_HELPERS
1918
1919#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1920 defined(GET_AVAILABLE_OPCODE_CHECKER)
1921#define GET_COMPUTE_FEATURES
1922#endif
1923#ifdef GET_COMPUTE_FEATURES
1924#undef GET_COMPUTE_FEATURES
1925
1926namespace llvm::BPF_MC {
1927
1928// Bits for subtarget features that participate in instruction matching.
1929enum SubtargetFeatureBits : uint8_t {
1930};
1931
1932inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1933 FeatureBitset Features;
1934 return Features;
1935}
1936
1937inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1938 enum : uint8_t {
1939 CEFBS_None,
1940 };
1941
1942 static constexpr FeatureBitset FeatureBitsets[] = {
1943 {}, // CEFBS_None
1944 };
1945 static constexpr uint8_t RequiredFeaturesRefs[] = {
1946 CEFBS_None, // PHI
1947 CEFBS_None, // INLINEASM
1948 CEFBS_None, // INLINEASM_BR
1949 CEFBS_None, // CFI_INSTRUCTION
1950 CEFBS_None, // EH_LABEL
1951 CEFBS_None, // GC_LABEL
1952 CEFBS_None, // ANNOTATION_LABEL
1953 CEFBS_None, // KILL
1954 CEFBS_None, // EXTRACT_SUBREG
1955 CEFBS_None, // INSERT_SUBREG
1956 CEFBS_None, // IMPLICIT_DEF
1957 CEFBS_None, // INIT_UNDEF
1958 CEFBS_None, // SUBREG_TO_REG
1959 CEFBS_None, // COPY_TO_REGCLASS
1960 CEFBS_None, // DBG_VALUE
1961 CEFBS_None, // DBG_VALUE_LIST
1962 CEFBS_None, // DBG_INSTR_REF
1963 CEFBS_None, // DBG_PHI
1964 CEFBS_None, // DBG_LABEL
1965 CEFBS_None, // REG_SEQUENCE
1966 CEFBS_None, // COPY
1967 CEFBS_None, // COPY_LANEMASK
1968 CEFBS_None, // BUNDLE
1969 CEFBS_None, // LIFETIME_START
1970 CEFBS_None, // LIFETIME_END
1971 CEFBS_None, // PSEUDO_PROBE
1972 CEFBS_None, // ARITH_FENCE
1973 CEFBS_None, // STACKMAP
1974 CEFBS_None, // FENTRY_CALL
1975 CEFBS_None, // PATCHPOINT
1976 CEFBS_None, // LOAD_STACK_GUARD
1977 CEFBS_None, // PREALLOCATED_SETUP
1978 CEFBS_None, // PREALLOCATED_ARG
1979 CEFBS_None, // STATEPOINT
1980 CEFBS_None, // LOCAL_ESCAPE
1981 CEFBS_None, // FAULTING_OP
1982 CEFBS_None, // PATCHABLE_OP
1983 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1984 CEFBS_None, // PATCHABLE_RET
1985 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1986 CEFBS_None, // PATCHABLE_TAIL_CALL
1987 CEFBS_None, // PATCHABLE_EVENT_CALL
1988 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1989 CEFBS_None, // ICALL_BRANCH_FUNNEL
1990 CEFBS_None, // FAKE_USE
1991 CEFBS_None, // MEMBARRIER
1992 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1993 CEFBS_None, // RELOC_NONE
1994 CEFBS_None, // CONVERGENCECTRL_ENTRY
1995 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1996 CEFBS_None, // CONVERGENCECTRL_LOOP
1997 CEFBS_None, // CONVERGENCECTRL_GLUE
1998 CEFBS_None, // G_ASSERT_SEXT
1999 CEFBS_None, // G_ASSERT_ZEXT
2000 CEFBS_None, // G_ASSERT_ALIGN
2001 CEFBS_None, // G_ADD
2002 CEFBS_None, // G_SUB
2003 CEFBS_None, // G_MUL
2004 CEFBS_None, // G_SDIV
2005 CEFBS_None, // G_UDIV
2006 CEFBS_None, // G_SREM
2007 CEFBS_None, // G_UREM
2008 CEFBS_None, // G_SDIVREM
2009 CEFBS_None, // G_UDIVREM
2010 CEFBS_None, // G_AND
2011 CEFBS_None, // G_OR
2012 CEFBS_None, // G_XOR
2013 CEFBS_None, // G_ABDS
2014 CEFBS_None, // G_ABDU
2015 CEFBS_None, // G_UAVGFLOOR
2016 CEFBS_None, // G_UAVGCEIL
2017 CEFBS_None, // G_SAVGFLOOR
2018 CEFBS_None, // G_SAVGCEIL
2019 CEFBS_None, // G_IMPLICIT_DEF
2020 CEFBS_None, // G_PHI
2021 CEFBS_None, // G_FRAME_INDEX
2022 CEFBS_None, // G_GLOBAL_VALUE
2023 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2024 CEFBS_None, // G_CONSTANT_POOL
2025 CEFBS_None, // G_EXTRACT
2026 CEFBS_None, // G_UNMERGE_VALUES
2027 CEFBS_None, // G_INSERT
2028 CEFBS_None, // G_MERGE_VALUES
2029 CEFBS_None, // G_BUILD_VECTOR
2030 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2031 CEFBS_None, // G_CONCAT_VECTORS
2032 CEFBS_None, // G_PTRTOINT
2033 CEFBS_None, // G_INTTOPTR
2034 CEFBS_None, // G_BITCAST
2035 CEFBS_None, // G_FREEZE
2036 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2037 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2038 CEFBS_None, // G_INTRINSIC_TRUNC
2039 CEFBS_None, // G_INTRINSIC_ROUND
2040 CEFBS_None, // G_INTRINSIC_LRINT
2041 CEFBS_None, // G_INTRINSIC_LLRINT
2042 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2043 CEFBS_None, // G_READCYCLECOUNTER
2044 CEFBS_None, // G_READSTEADYCOUNTER
2045 CEFBS_None, // G_LOAD
2046 CEFBS_None, // G_SEXTLOAD
2047 CEFBS_None, // G_ZEXTLOAD
2048 CEFBS_None, // G_FPEXTLOAD
2049 CEFBS_None, // G_INDEXED_LOAD
2050 CEFBS_None, // G_INDEXED_SEXTLOAD
2051 CEFBS_None, // G_INDEXED_ZEXTLOAD
2052 CEFBS_None, // G_STORE
2053 CEFBS_None, // G_FPTRUNCSTORE
2054 CEFBS_None, // G_INDEXED_STORE
2055 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2056 CEFBS_None, // G_ATOMIC_CMPXCHG
2057 CEFBS_None, // G_ATOMICRMW_XCHG
2058 CEFBS_None, // G_ATOMICRMW_ADD
2059 CEFBS_None, // G_ATOMICRMW_SUB
2060 CEFBS_None, // G_ATOMICRMW_AND
2061 CEFBS_None, // G_ATOMICRMW_NAND
2062 CEFBS_None, // G_ATOMICRMW_OR
2063 CEFBS_None, // G_ATOMICRMW_XOR
2064 CEFBS_None, // G_ATOMICRMW_MAX
2065 CEFBS_None, // G_ATOMICRMW_MIN
2066 CEFBS_None, // G_ATOMICRMW_UMAX
2067 CEFBS_None, // G_ATOMICRMW_UMIN
2068 CEFBS_None, // G_ATOMICRMW_FADD
2069 CEFBS_None, // G_ATOMICRMW_FSUB
2070 CEFBS_None, // G_ATOMICRMW_FMAX
2071 CEFBS_None, // G_ATOMICRMW_FMIN
2072 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2073 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2074 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2075 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2076 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2077 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2078 CEFBS_None, // G_ATOMICRMW_USUB_COND
2079 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2080 CEFBS_None, // G_FENCE
2081 CEFBS_None, // G_PREFETCH
2082 CEFBS_None, // G_BRCOND
2083 CEFBS_None, // G_BRINDIRECT
2084 CEFBS_None, // G_INVOKE_REGION_START
2085 CEFBS_None, // G_INTRINSIC
2086 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2087 CEFBS_None, // G_INTRINSIC_CONVERGENT
2088 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2089 CEFBS_None, // G_ANYEXT
2090 CEFBS_None, // G_TRUNC
2091 CEFBS_None, // G_TRUNC_SSAT_S
2092 CEFBS_None, // G_TRUNC_SSAT_U
2093 CEFBS_None, // G_TRUNC_USAT_U
2094 CEFBS_None, // G_CONSTANT
2095 CEFBS_None, // G_FCONSTANT
2096 CEFBS_None, // G_VASTART
2097 CEFBS_None, // G_VAARG
2098 CEFBS_None, // G_SEXT
2099 CEFBS_None, // G_SEXT_INREG
2100 CEFBS_None, // G_ZEXT
2101 CEFBS_None, // G_SHL
2102 CEFBS_None, // G_LSHR
2103 CEFBS_None, // G_ASHR
2104 CEFBS_None, // G_FSHL
2105 CEFBS_None, // G_FSHR
2106 CEFBS_None, // G_ROTR
2107 CEFBS_None, // G_ROTL
2108 CEFBS_None, // G_ICMP
2109 CEFBS_None, // G_FCMP
2110 CEFBS_None, // G_SCMP
2111 CEFBS_None, // G_UCMP
2112 CEFBS_None, // G_SELECT
2113 CEFBS_None, // G_UADDO
2114 CEFBS_None, // G_UADDE
2115 CEFBS_None, // G_USUBO
2116 CEFBS_None, // G_USUBE
2117 CEFBS_None, // G_SADDO
2118 CEFBS_None, // G_SADDE
2119 CEFBS_None, // G_SSUBO
2120 CEFBS_None, // G_SSUBE
2121 CEFBS_None, // G_UMULO
2122 CEFBS_None, // G_SMULO
2123 CEFBS_None, // G_UMULH
2124 CEFBS_None, // G_SMULH
2125 CEFBS_None, // G_UADDSAT
2126 CEFBS_None, // G_SADDSAT
2127 CEFBS_None, // G_USUBSAT
2128 CEFBS_None, // G_SSUBSAT
2129 CEFBS_None, // G_USHLSAT
2130 CEFBS_None, // G_SSHLSAT
2131 CEFBS_None, // G_SMULFIX
2132 CEFBS_None, // G_UMULFIX
2133 CEFBS_None, // G_SMULFIXSAT
2134 CEFBS_None, // G_UMULFIXSAT
2135 CEFBS_None, // G_SDIVFIX
2136 CEFBS_None, // G_UDIVFIX
2137 CEFBS_None, // G_SDIVFIXSAT
2138 CEFBS_None, // G_UDIVFIXSAT
2139 CEFBS_None, // G_FADD
2140 CEFBS_None, // G_FSUB
2141 CEFBS_None, // G_FMUL
2142 CEFBS_None, // G_FMA
2143 CEFBS_None, // G_FMAD
2144 CEFBS_None, // G_FDIV
2145 CEFBS_None, // G_FREM
2146 CEFBS_None, // G_FMODF
2147 CEFBS_None, // G_FPOW
2148 CEFBS_None, // G_FPOWI
2149 CEFBS_None, // G_FEXP
2150 CEFBS_None, // G_FEXP2
2151 CEFBS_None, // G_FEXP10
2152 CEFBS_None, // G_FLOG
2153 CEFBS_None, // G_FLOG2
2154 CEFBS_None, // G_FLOG10
2155 CEFBS_None, // G_FLDEXP
2156 CEFBS_None, // G_FFREXP
2157 CEFBS_None, // G_FNEG
2158 CEFBS_None, // G_FPEXT
2159 CEFBS_None, // G_FPTRUNC
2160 CEFBS_None, // G_FPTOSI
2161 CEFBS_None, // G_FPTOUI
2162 CEFBS_None, // G_SITOFP
2163 CEFBS_None, // G_UITOFP
2164 CEFBS_None, // G_FPTOSI_SAT
2165 CEFBS_None, // G_FPTOUI_SAT
2166 CEFBS_None, // G_FABS
2167 CEFBS_None, // G_FCOPYSIGN
2168 CEFBS_None, // G_IS_FPCLASS
2169 CEFBS_None, // G_FCANONICALIZE
2170 CEFBS_None, // G_FMINNUM
2171 CEFBS_None, // G_FMAXNUM
2172 CEFBS_None, // G_FMINNUM_IEEE
2173 CEFBS_None, // G_FMAXNUM_IEEE
2174 CEFBS_None, // G_FMINIMUM
2175 CEFBS_None, // G_FMAXIMUM
2176 CEFBS_None, // G_FMINIMUMNUM
2177 CEFBS_None, // G_FMAXIMUMNUM
2178 CEFBS_None, // G_GET_FPENV
2179 CEFBS_None, // G_SET_FPENV
2180 CEFBS_None, // G_RESET_FPENV
2181 CEFBS_None, // G_GET_FPMODE
2182 CEFBS_None, // G_SET_FPMODE
2183 CEFBS_None, // G_RESET_FPMODE
2184 CEFBS_None, // G_GET_ROUNDING
2185 CEFBS_None, // G_SET_ROUNDING
2186 CEFBS_None, // G_PTR_ADD
2187 CEFBS_None, // G_PTRMASK
2188 CEFBS_None, // G_SMIN
2189 CEFBS_None, // G_SMAX
2190 CEFBS_None, // G_UMIN
2191 CEFBS_None, // G_UMAX
2192 CEFBS_None, // G_ABS
2193 CEFBS_None, // G_LROUND
2194 CEFBS_None, // G_LLROUND
2195 CEFBS_None, // G_BR
2196 CEFBS_None, // G_BRJT
2197 CEFBS_None, // G_VSCALE
2198 CEFBS_None, // G_INSERT_SUBVECTOR
2199 CEFBS_None, // G_EXTRACT_SUBVECTOR
2200 CEFBS_None, // G_INSERT_VECTOR_ELT
2201 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2202 CEFBS_None, // G_SHUFFLE_VECTOR
2203 CEFBS_None, // G_SPLAT_VECTOR
2204 CEFBS_None, // G_STEP_VECTOR
2205 CEFBS_None, // G_VECTOR_COMPRESS
2206 CEFBS_None, // G_CTTZ
2207 CEFBS_None, // G_CTTZ_ZERO_POISON
2208 CEFBS_None, // G_CTLZ
2209 CEFBS_None, // G_CTLZ_ZERO_POISON
2210 CEFBS_None, // G_CTLS
2211 CEFBS_None, // G_CTPOP
2212 CEFBS_None, // G_BSWAP
2213 CEFBS_None, // G_BITREVERSE
2214 CEFBS_None, // G_CLMUL
2215 CEFBS_None, // G_CLMULH
2216 CEFBS_None, // G_FCEIL
2217 CEFBS_None, // G_FCOS
2218 CEFBS_None, // G_FSIN
2219 CEFBS_None, // G_FSINCOS
2220 CEFBS_None, // G_FTAN
2221 CEFBS_None, // G_FACOS
2222 CEFBS_None, // G_FASIN
2223 CEFBS_None, // G_FATAN
2224 CEFBS_None, // G_FATAN2
2225 CEFBS_None, // G_FCOSH
2226 CEFBS_None, // G_FSINH
2227 CEFBS_None, // G_FTANH
2228 CEFBS_None, // G_FSQRT
2229 CEFBS_None, // G_FFLOOR
2230 CEFBS_None, // G_FRINT
2231 CEFBS_None, // G_FNEARBYINT
2232 CEFBS_None, // G_ADDRSPACE_CAST
2233 CEFBS_None, // G_BLOCK_ADDR
2234 CEFBS_None, // G_JUMP_TABLE
2235 CEFBS_None, // G_DYN_STACKALLOC
2236 CEFBS_None, // G_STACKSAVE
2237 CEFBS_None, // G_STACKRESTORE
2238 CEFBS_None, // G_STRICT_FADD
2239 CEFBS_None, // G_STRICT_FSUB
2240 CEFBS_None, // G_STRICT_FMUL
2241 CEFBS_None, // G_STRICT_FDIV
2242 CEFBS_None, // G_STRICT_FREM
2243 CEFBS_None, // G_STRICT_FMA
2244 CEFBS_None, // G_STRICT_FSQRT
2245 CEFBS_None, // G_STRICT_FLDEXP
2246 CEFBS_None, // G_STRICT_FCMP
2247 CEFBS_None, // G_STRICT_FCMPS
2248 CEFBS_None, // G_READ_REGISTER
2249 CEFBS_None, // G_WRITE_REGISTER
2250 CEFBS_None, // G_MEMCPY
2251 CEFBS_None, // G_MEMCPY_INLINE
2252 CEFBS_None, // G_MEMMOVE
2253 CEFBS_None, // G_MEMSET
2254 CEFBS_None, // G_BZERO
2255 CEFBS_None, // G_MEMSET_INLINE
2256 CEFBS_None, // G_TRAP
2257 CEFBS_None, // G_DEBUGTRAP
2258 CEFBS_None, // G_UBSANTRAP
2259 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2260 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2261 CEFBS_None, // G_VECREDUCE_FADD
2262 CEFBS_None, // G_VECREDUCE_FMUL
2263 CEFBS_None, // G_VECREDUCE_FMAX
2264 CEFBS_None, // G_VECREDUCE_FMIN
2265 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2266 CEFBS_None, // G_VECREDUCE_FMINIMUM
2267 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2268 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2269 CEFBS_None, // G_VECREDUCE_ADD
2270 CEFBS_None, // G_VECREDUCE_MUL
2271 CEFBS_None, // G_VECREDUCE_AND
2272 CEFBS_None, // G_VECREDUCE_OR
2273 CEFBS_None, // G_VECREDUCE_XOR
2274 CEFBS_None, // G_VECREDUCE_SMAX
2275 CEFBS_None, // G_VECREDUCE_SMIN
2276 CEFBS_None, // G_VECREDUCE_UMAX
2277 CEFBS_None, // G_VECREDUCE_UMIN
2278 CEFBS_None, // G_SBFX
2279 CEFBS_None, // G_UBFX
2280 CEFBS_None, // ADJCALLSTACKDOWN
2281 CEFBS_None, // ADJCALLSTACKUP
2282 CEFBS_None, // FI_ri
2283 CEFBS_None, // LDIMM64
2284 CEFBS_None, // LOAD_STACK_ARG_PSEUDO
2285 CEFBS_None, // MEMCPY
2286 CEFBS_None, // STORE_STACK_ARG_IMM_PSEUDO
2287 CEFBS_None, // STORE_STACK_ARG_PSEUDO
2288 CEFBS_None, // Select
2289 CEFBS_None, // Select_32
2290 CEFBS_None, // Select_32_64
2291 CEFBS_None, // Select_64_32
2292 CEFBS_None, // Select_Ri
2293 CEFBS_None, // Select_Ri_32
2294 CEFBS_None, // Select_Ri_32_64
2295 CEFBS_None, // Select_Ri_64_32
2296 CEFBS_None, // ADDR_SPACE_CAST
2297 CEFBS_None, // ADD_ri
2298 CEFBS_None, // ADD_ri_32
2299 CEFBS_None, // ADD_rr
2300 CEFBS_None, // ADD_rr_32
2301 CEFBS_None, // AND_ri
2302 CEFBS_None, // AND_ri_32
2303 CEFBS_None, // AND_rr
2304 CEFBS_None, // AND_rr_32
2305 CEFBS_None, // BE16
2306 CEFBS_None, // BE32
2307 CEFBS_None, // BE64
2308 CEFBS_None, // BSWAP16
2309 CEFBS_None, // BSWAP32
2310 CEFBS_None, // BSWAP64
2311 CEFBS_None, // CMPXCHGD
2312 CEFBS_None, // CMPXCHGW32
2313 CEFBS_None, // CORE_LD32
2314 CEFBS_None, // CORE_LD64
2315 CEFBS_None, // CORE_SHIFT
2316 CEFBS_None, // CORE_ST
2317 CEFBS_None, // DIV_ri
2318 CEFBS_None, // DIV_ri_32
2319 CEFBS_None, // DIV_rr
2320 CEFBS_None, // DIV_rr_32
2321 CEFBS_None, // JAL
2322 CEFBS_None, // JALX
2323 CEFBS_None, // JCOND
2324 CEFBS_None, // JEQ_ri
2325 CEFBS_None, // JEQ_ri_32
2326 CEFBS_None, // JEQ_rr
2327 CEFBS_None, // JEQ_rr_32
2328 CEFBS_None, // JMP
2329 CEFBS_None, // JMPL
2330 CEFBS_None, // JNE_ri
2331 CEFBS_None, // JNE_ri_32
2332 CEFBS_None, // JNE_rr
2333 CEFBS_None, // JNE_rr_32
2334 CEFBS_None, // JSET_ri
2335 CEFBS_None, // JSET_ri_32
2336 CEFBS_None, // JSET_rr
2337 CEFBS_None, // JSET_rr_32
2338 CEFBS_None, // JSGE_ri
2339 CEFBS_None, // JSGE_ri_32
2340 CEFBS_None, // JSGE_rr
2341 CEFBS_None, // JSGE_rr_32
2342 CEFBS_None, // JSGT_ri
2343 CEFBS_None, // JSGT_ri_32
2344 CEFBS_None, // JSGT_rr
2345 CEFBS_None, // JSGT_rr_32
2346 CEFBS_None, // JSLE_ri
2347 CEFBS_None, // JSLE_ri_32
2348 CEFBS_None, // JSLE_rr
2349 CEFBS_None, // JSLE_rr_32
2350 CEFBS_None, // JSLT_ri
2351 CEFBS_None, // JSLT_ri_32
2352 CEFBS_None, // JSLT_rr
2353 CEFBS_None, // JSLT_rr_32
2354 CEFBS_None, // JUGE_ri
2355 CEFBS_None, // JUGE_ri_32
2356 CEFBS_None, // JUGE_rr
2357 CEFBS_None, // JUGE_rr_32
2358 CEFBS_None, // JUGT_ri
2359 CEFBS_None, // JUGT_ri_32
2360 CEFBS_None, // JUGT_rr
2361 CEFBS_None, // JUGT_rr_32
2362 CEFBS_None, // JULE_ri
2363 CEFBS_None, // JULE_ri_32
2364 CEFBS_None, // JULE_rr
2365 CEFBS_None, // JULE_rr_32
2366 CEFBS_None, // JULT_ri
2367 CEFBS_None, // JULT_ri_32
2368 CEFBS_None, // JULT_rr
2369 CEFBS_None, // JULT_rr_32
2370 CEFBS_None, // JX
2371 CEFBS_None, // LDB
2372 CEFBS_None, // LDB32
2373 CEFBS_None, // LDBACQ32
2374 CEFBS_None, // LDBSX
2375 CEFBS_None, // LDD
2376 CEFBS_None, // LDDACQ
2377 CEFBS_None, // LDH
2378 CEFBS_None, // LDH32
2379 CEFBS_None, // LDHACQ32
2380 CEFBS_None, // LDHSX
2381 CEFBS_None, // LDW
2382 CEFBS_None, // LDW32
2383 CEFBS_None, // LDWACQ32
2384 CEFBS_None, // LDWSX
2385 CEFBS_None, // LD_ABS_B
2386 CEFBS_None, // LD_ABS_H
2387 CEFBS_None, // LD_ABS_W
2388 CEFBS_None, // LD_IND_B
2389 CEFBS_None, // LD_IND_H
2390 CEFBS_None, // LD_IND_W
2391 CEFBS_None, // LD_imm64
2392 CEFBS_None, // LD_pseudo
2393 CEFBS_None, // LE16
2394 CEFBS_None, // LE32
2395 CEFBS_None, // LE64
2396 CEFBS_None, // MOD_ri
2397 CEFBS_None, // MOD_ri_32
2398 CEFBS_None, // MOD_rr
2399 CEFBS_None, // MOD_rr_32
2400 CEFBS_None, // MOVSX_rr_16
2401 CEFBS_None, // MOVSX_rr_32
2402 CEFBS_None, // MOVSX_rr_32_16
2403 CEFBS_None, // MOVSX_rr_32_8
2404 CEFBS_None, // MOVSX_rr_8
2405 CEFBS_None, // MOV_32_64
2406 CEFBS_None, // MOV_ri
2407 CEFBS_None, // MOV_ri_32
2408 CEFBS_None, // MOV_rr
2409 CEFBS_None, // MOV_rr_32
2410 CEFBS_None, // MUL_ri
2411 CEFBS_None, // MUL_ri_32
2412 CEFBS_None, // MUL_rr
2413 CEFBS_None, // MUL_rr_32
2414 CEFBS_None, // NEG_32
2415 CEFBS_None, // NEG_64
2416 CEFBS_None, // NOP
2417 CEFBS_None, // OR_ri
2418 CEFBS_None, // OR_ri_32
2419 CEFBS_None, // OR_rr
2420 CEFBS_None, // OR_rr_32
2421 CEFBS_None, // RET
2422 CEFBS_None, // SDIV_ri
2423 CEFBS_None, // SDIV_ri_32
2424 CEFBS_None, // SDIV_rr
2425 CEFBS_None, // SDIV_rr_32
2426 CEFBS_None, // SLL_ri
2427 CEFBS_None, // SLL_ri_32
2428 CEFBS_None, // SLL_rr
2429 CEFBS_None, // SLL_rr_32
2430 CEFBS_None, // SMOD_ri
2431 CEFBS_None, // SMOD_ri_32
2432 CEFBS_None, // SMOD_rr
2433 CEFBS_None, // SMOD_rr_32
2434 CEFBS_None, // SRA_ri
2435 CEFBS_None, // SRA_ri_32
2436 CEFBS_None, // SRA_rr
2437 CEFBS_None, // SRA_rr_32
2438 CEFBS_None, // SRL_ri
2439 CEFBS_None, // SRL_ri_32
2440 CEFBS_None, // SRL_rr
2441 CEFBS_None, // SRL_rr_32
2442 CEFBS_None, // STB
2443 CEFBS_None, // STB32
2444 CEFBS_None, // STBREL32
2445 CEFBS_None, // STB_imm
2446 CEFBS_None, // STD
2447 CEFBS_None, // STDREL
2448 CEFBS_None, // STD_imm
2449 CEFBS_None, // STH
2450 CEFBS_None, // STH32
2451 CEFBS_None, // STHREL32
2452 CEFBS_None, // STH_imm
2453 CEFBS_None, // STW
2454 CEFBS_None, // STW32
2455 CEFBS_None, // STWREL32
2456 CEFBS_None, // STW_imm
2457 CEFBS_None, // SUB_ri
2458 CEFBS_None, // SUB_ri_32
2459 CEFBS_None, // SUB_rr
2460 CEFBS_None, // SUB_rr_32
2461 CEFBS_None, // XADDD
2462 CEFBS_None, // XADDW
2463 CEFBS_None, // XADDW32
2464 CEFBS_None, // XANDD
2465 CEFBS_None, // XANDW32
2466 CEFBS_None, // XCHGD
2467 CEFBS_None, // XCHGW32
2468 CEFBS_None, // XFADDD
2469 CEFBS_None, // XFADDW32
2470 CEFBS_None, // XFANDD
2471 CEFBS_None, // XFANDW32
2472 CEFBS_None, // XFORD
2473 CEFBS_None, // XFORW32
2474 CEFBS_None, // XFXORD
2475 CEFBS_None, // XFXORW32
2476 CEFBS_None, // XORD
2477 CEFBS_None, // XORW32
2478 CEFBS_None, // XOR_ri
2479 CEFBS_None, // XOR_ri_32
2480 CEFBS_None, // XOR_rr
2481 CEFBS_None, // XOR_rr_32
2482 CEFBS_None, // XXORD
2483 CEFBS_None, // XXORW32
2484 };
2485
2486 assert(Opcode < 538);
2487 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2488}
2489
2490
2491} // namespace llvm::BPF_MC
2492
2493#endif // GET_COMPUTE_FEATURES
2494
2495#ifdef GET_AVAILABLE_OPCODE_CHECKER
2496#undef GET_AVAILABLE_OPCODE_CHECKER
2497
2498namespace llvm::BPF_MC {
2499
2500bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2501 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2502 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2503 FeatureBitset MissingFeatures =
2504 (AvailableFeatures & RequiredFeatures) ^
2505 RequiredFeatures;
2506 return !MissingFeatures.any();
2507}
2508
2509} // namespace llvm::BPF_MC
2510
2511#endif // GET_AVAILABLE_OPCODE_CHECKER
2512
2513#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2514#undef ENABLE_INSTR_PREDICATE_VERIFIER
2515
2516#include <sstream>
2517
2518namespace llvm::BPF_MC {
2519
2520#ifndef NDEBUG
2521static const char *SubtargetFeatureNames[] = {
2522 nullptr
2523};
2524
2525#endif // NDEBUG
2526
2527void verifyInstructionPredicates(
2528 unsigned Opcode, const FeatureBitset &Features) {
2529#ifndef NDEBUG
2530 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2531 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2532 FeatureBitset MissingFeatures =
2533 (AvailableFeatures & RequiredFeatures) ^
2534 RequiredFeatures;
2535 if (MissingFeatures.any()) {
2536 std::ostringstream Msg;
2537 Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
2538 << " instruction but the ";
2539 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2540 if (MissingFeatures.test(i))
2541 Msg << SubtargetFeatureNames[i] << " ";
2542 Msg << "predicate(s) are not met";
2543 report_fatal_error(Msg.str().c_str());
2544 }
2545#endif // NDEBUG
2546}
2547
2548} // namespace llvm::BPF_MC
2549
2550#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2551
2552