1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::BPF {
13
14 enum {
15 PHI = 0, // Target.td:1301
16 INLINEASM = 1, // Target.td:1307
17 INLINEASM_BR = 2, // Target.td:1313
18 CFI_INSTRUCTION = 3, // Target.td:1322
19 EH_LABEL = 4, // Target.td:1331
20 GC_LABEL = 5, // Target.td:1340
21 ANNOTATION_LABEL = 6, // Target.td:1349
22 KILL = 7, // Target.td:1357
23 EXTRACT_SUBREG = 8, // Target.td:1364
24 INSERT_SUBREG = 9, // Target.td:1370
25 IMPLICIT_DEF = 10, // Target.td:1377
26 INIT_UNDEF = 11, // Target.td:1386
27 SUBREG_TO_REG = 12, // Target.td:1393
28 COPY_TO_REGCLASS = 13, // Target.td:1399
29 DBG_VALUE = 14, // Target.td:1406
30 DBG_VALUE_LIST = 15, // Target.td:1413
31 DBG_INSTR_REF = 16, // Target.td:1420
32 DBG_PHI = 17, // Target.td:1427
33 DBG_LABEL = 18, // Target.td:1434
34 REG_SEQUENCE = 19, // Target.td:1441
35 COPY = 20, // Target.td:1448
36 COPY_LANEMASK = 21, // Target.td:1456
37 BUNDLE = 22, // Target.td:1463
38 LIFETIME_START = 23, // Target.td:1469
39 LIFETIME_END = 24, // Target.td:1476
40 PSEUDO_PROBE = 25, // Target.td:1483
41 ARITH_FENCE = 26, // Target.td:1490
42 STACKMAP = 27, // Target.td:1499
43 FENTRY_CALL = 28, // Target.td:1634
44 PATCHPOINT = 29, // Target.td:1507
45 LOAD_STACK_GUARD = 30, // Target.td:1525
46 PREALLOCATED_SETUP = 31, // Target.td:1533
47 PREALLOCATED_ARG = 32, // Target.td:1539
48 STATEPOINT = 33, // Target.td:1516
49 LOCAL_ESCAPE = 34, // Target.td:1545
50 FAULTING_OP = 35, // Target.td:1554
51 PATCHABLE_OP = 36, // Target.td:1574
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1582
53 PATCHABLE_RET = 38, // Target.td:1589
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1598
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1606
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1614
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1624
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1644
59 FAKE_USE = 44, // Target.td:1564
60 MEMBARRIER = 45, // Target.td:1650
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1658
62 RELOC_NONE = 47, // Target.td:1666
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1678
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1674
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1682
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1686
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1867
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1859
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1874
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1474
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1486
96 G_INSERT = 81, // GenericOpcodes.td:1494
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1504
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1523
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1532
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1539
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1881
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_FMAXIMUMNUM = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_FMINIMUMNUM = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_UINC_WRAP = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_UDEC_WRAP = 129, // GenericOpcodes.td:1448
145 G_ATOMICRMW_USUB_COND = 130, // GenericOpcodes.td:1449
146 G_ATOMICRMW_USUB_SAT = 131, // GenericOpcodes.td:1450
147 G_FENCE = 132, // GenericOpcodes.td:1452
148 G_PREFETCH = 133, // GenericOpcodes.td:1459
149 G_BRCOND = 134, // GenericOpcodes.td:1594
150 G_BRINDIRECT = 135, // GenericOpcodes.td:1603
151 G_INVOKE_REGION_START = 136, // GenericOpcodes.td:1626
152 G_INTRINSIC = 137, // GenericOpcodes.td:1546
153 G_INTRINSIC_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1553
154 G_INTRINSIC_CONVERGENT = 139, // GenericOpcodes.td:1562
155 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1570
156 G_ANYEXT = 141, // GenericOpcodes.td:44
157 G_TRUNC = 142, // GenericOpcodes.td:83
158 G_TRUNC_SSAT_S = 143, // GenericOpcodes.td:90
159 G_TRUNC_SSAT_U = 144, // GenericOpcodes.td:97
160 G_TRUNC_USAT_U = 145, // GenericOpcodes.td:104
161 G_CONSTANT = 146, // GenericOpcodes.td:165
162 G_FCONSTANT = 147, // GenericOpcodes.td:172
163 G_VASTART = 148, // GenericOpcodes.td:178
164 G_VAARG = 149, // GenericOpcodes.td:185
165 G_SEXT = 150, // GenericOpcodes.td:52
166 G_SEXT_INREG = 151, // GenericOpcodes.td:66
167 G_ZEXT = 152, // GenericOpcodes.td:74
168 G_SHL = 153, // GenericOpcodes.td:396
169 G_LSHR = 154, // GenericOpcodes.td:403
170 G_ASHR = 155, // GenericOpcodes.td:410
171 G_FSHL = 156, // GenericOpcodes.td:462
172 G_FSHR = 157, // GenericOpcodes.td:470
173 G_ROTR = 158, // GenericOpcodes.td:477
174 G_ROTL = 159, // GenericOpcodes.td:484
175 G_ICMP = 160, // GenericOpcodes.td:491
176 G_FCMP = 161, // GenericOpcodes.td:498
177 G_SCMP = 162, // GenericOpcodes.td:505
178 G_UCMP = 163, // GenericOpcodes.td:512
179 G_SELECT = 164, // GenericOpcodes.td:519
180 G_UADDO = 165, // GenericOpcodes.td:584
181 G_UADDE = 166, // GenericOpcodes.td:592
182 G_USUBO = 167, // GenericOpcodes.td:614
183 G_USUBE = 168, // GenericOpcodes.td:620
184 G_SADDO = 169, // GenericOpcodes.td:599
185 G_SADDE = 170, // GenericOpcodes.td:607
186 G_SSUBO = 171, // GenericOpcodes.td:627
187 G_SSUBE = 172, // GenericOpcodes.td:634
188 G_UMULO = 173, // GenericOpcodes.td:641
189 G_SMULO = 174, // GenericOpcodes.td:649
190 G_UMULH = 175, // GenericOpcodes.td:658
191 G_SMULH = 176, // GenericOpcodes.td:667
192 G_UADDSAT = 177, // GenericOpcodes.td:679
193 G_SADDSAT = 178, // GenericOpcodes.td:687
194 G_USUBSAT = 179, // GenericOpcodes.td:695
195 G_SSUBSAT = 180, // GenericOpcodes.td:703
196 G_USHLSAT = 181, // GenericOpcodes.td:711
197 G_SSHLSAT = 182, // GenericOpcodes.td:719
198 G_SMULFIX = 183, // GenericOpcodes.td:731
199 G_UMULFIX = 184, // GenericOpcodes.td:738
200 G_SMULFIXSAT = 185, // GenericOpcodes.td:748
201 G_UMULFIXSAT = 186, // GenericOpcodes.td:755
202 G_SDIVFIX = 187, // GenericOpcodes.td:766
203 G_UDIVFIX = 188, // GenericOpcodes.td:773
204 G_SDIVFIXSAT = 189, // GenericOpcodes.td:783
205 G_UDIVFIXSAT = 190, // GenericOpcodes.td:790
206 G_FADD = 191, // GenericOpcodes.td:963
207 G_FSUB = 192, // GenericOpcodes.td:971
208 G_FMUL = 193, // GenericOpcodes.td:979
209 G_FMA = 194, // GenericOpcodes.td:988
210 G_FMAD = 195, // GenericOpcodes.td:997
211 G_FDIV = 196, // GenericOpcodes.td:1005
212 G_FREM = 197, // GenericOpcodes.td:1012
213 G_FMODF = 198, // GenericOpcodes.td:1019
214 G_FPOW = 199, // GenericOpcodes.td:1026
215 G_FPOWI = 200, // GenericOpcodes.td:1033
216 G_FEXP = 201, // GenericOpcodes.td:1040
217 G_FEXP2 = 202, // GenericOpcodes.td:1047
218 G_FEXP10 = 203, // GenericOpcodes.td:1054
219 G_FLOG = 204, // GenericOpcodes.td:1061
220 G_FLOG2 = 205, // GenericOpcodes.td:1068
221 G_FLOG10 = 206, // GenericOpcodes.td:1075
222 G_FLDEXP = 207, // GenericOpcodes.td:1082
223 G_FFREXP = 208, // GenericOpcodes.td:1089
224 G_FNEG = 209, // GenericOpcodes.td:801
225 G_FPEXT = 210, // GenericOpcodes.td:807
226 G_FPTRUNC = 211, // GenericOpcodes.td:813
227 G_FPTOSI = 212, // GenericOpcodes.td:819
228 G_FPTOUI = 213, // GenericOpcodes.td:825
229 G_SITOFP = 214, // GenericOpcodes.td:831
230 G_UITOFP = 215, // GenericOpcodes.td:837
231 G_FPTOSI_SAT = 216, // GenericOpcodes.td:843
232 G_FPTOUI_SAT = 217, // GenericOpcodes.td:849
233 G_FABS = 218, // GenericOpcodes.td:855
234 G_FCOPYSIGN = 219, // GenericOpcodes.td:861
235 G_IS_FPCLASS = 220, // GenericOpcodes.td:874
236 G_FCANONICALIZE = 221, // GenericOpcodes.td:867
237 G_FMINNUM = 222, // GenericOpcodes.td:887
238 G_FMAXNUM = 223, // GenericOpcodes.td:894
239 G_FMINNUM_IEEE = 224, // GenericOpcodes.td:912
240 G_FMAXNUM_IEEE = 225, // GenericOpcodes.td:919
241 G_FMINIMUM = 226, // GenericOpcodes.td:929
242 G_FMAXIMUM = 227, // GenericOpcodes.td:936
243 G_FMINIMUMNUM = 228, // GenericOpcodes.td:944
244 G_FMAXIMUMNUM = 229, // GenericOpcodes.td:951
245 G_GET_FPENV = 230, // GenericOpcodes.td:1219
246 G_SET_FPENV = 231, // GenericOpcodes.td:1226
247 G_RESET_FPENV = 232, // GenericOpcodes.td:1233
248 G_GET_FPMODE = 233, // GenericOpcodes.td:1240
249 G_SET_FPMODE = 234, // GenericOpcodes.td:1247
250 G_RESET_FPMODE = 235, // GenericOpcodes.td:1254
251 G_GET_ROUNDING = 236, // GenericOpcodes.td:1311
252 G_SET_ROUNDING = 237, // GenericOpcodes.td:1317
253 G_PTR_ADD = 238, // GenericOpcodes.td:526
254 G_PTRMASK = 239, // GenericOpcodes.td:534
255 G_SMIN = 240, // GenericOpcodes.td:541
256 G_SMAX = 241, // GenericOpcodes.td:549
257 G_UMIN = 242, // GenericOpcodes.td:557
258 G_UMAX = 243, // GenericOpcodes.td:565
259 G_ABS = 244, // GenericOpcodes.td:573
260 G_LROUND = 245, // GenericOpcodes.td:283
261 G_LLROUND = 246, // GenericOpcodes.td:289
262 G_BR = 247, // GenericOpcodes.td:1584
263 G_BRJT = 248, // GenericOpcodes.td:1614
264 G_VSCALE = 249, // GenericOpcodes.td:1514
265 G_INSERT_SUBVECTOR = 250, // GenericOpcodes.td:1658
266 G_EXTRACT_SUBVECTOR = 251, // GenericOpcodes.td:1665
267 G_INSERT_VECTOR_ELT = 252, // GenericOpcodes.td:1672
268 G_EXTRACT_VECTOR_ELT = 253, // GenericOpcodes.td:1679
269 G_SHUFFLE_VECTOR = 254, // GenericOpcodes.td:1689
270 G_SPLAT_VECTOR = 255, // GenericOpcodes.td:1696
271 G_STEP_VECTOR = 256, // GenericOpcodes.td:1703
272 G_VECTOR_COMPRESS = 257, // GenericOpcodes.td:1710
273 G_CTTZ = 258, // GenericOpcodes.td:205
274 G_CTTZ_ZERO_UNDEF = 259, // GenericOpcodes.td:211
275 G_CTLZ = 260, // GenericOpcodes.td:193
276 G_CTLZ_ZERO_UNDEF = 261, // GenericOpcodes.td:199
277 G_CTLS = 262, // GenericOpcodes.td:217
278 G_CTPOP = 263, // GenericOpcodes.td:223
279 G_BSWAP = 264, // GenericOpcodes.td:229
280 G_BITREVERSE = 265, // GenericOpcodes.td:235
281 G_FCEIL = 266, // GenericOpcodes.td:1096
282 G_FCOS = 267, // GenericOpcodes.td:1103
283 G_FSIN = 268, // GenericOpcodes.td:1110
284 G_FSINCOS = 269, // GenericOpcodes.td:1117
285 G_FTAN = 270, // GenericOpcodes.td:1124
286 G_FACOS = 271, // GenericOpcodes.td:1131
287 G_FASIN = 272, // GenericOpcodes.td:1138
288 G_FATAN = 273, // GenericOpcodes.td:1145
289 G_FATAN2 = 274, // GenericOpcodes.td:1152
290 G_FCOSH = 275, // GenericOpcodes.td:1159
291 G_FSINH = 276, // GenericOpcodes.td:1166
292 G_FTANH = 277, // GenericOpcodes.td:1173
293 G_FSQRT = 278, // GenericOpcodes.td:1183
294 G_FFLOOR = 279, // GenericOpcodes.td:1190
295 G_FRINT = 280, // GenericOpcodes.td:1197
296 G_FNEARBYINT = 281, // GenericOpcodes.td:1204
297 G_ADDRSPACE_CAST = 282, // GenericOpcodes.td:241
298 G_BLOCK_ADDR = 283, // GenericOpcodes.td:247
299 G_JUMP_TABLE = 284, // GenericOpcodes.td:253
300 G_DYN_STACKALLOC = 285, // GenericOpcodes.td:259
301 G_STACKSAVE = 286, // GenericOpcodes.td:265
302 G_STACKRESTORE = 287, // GenericOpcodes.td:271
303 G_STRICT_FADD = 288, // GenericOpcodes.td:1760
304 G_STRICT_FSUB = 289, // GenericOpcodes.td:1761
305 G_STRICT_FMUL = 290, // GenericOpcodes.td:1762
306 G_STRICT_FDIV = 291, // GenericOpcodes.td:1763
307 G_STRICT_FREM = 292, // GenericOpcodes.td:1764
308 G_STRICT_FMA = 293, // GenericOpcodes.td:1765
309 G_STRICT_FSQRT = 294, // GenericOpcodes.td:1766
310 G_STRICT_FLDEXP = 295, // GenericOpcodes.td:1767
311 G_READ_REGISTER = 296, // GenericOpcodes.td:1633
312 G_WRITE_REGISTER = 297, // GenericOpcodes.td:1643
313 G_MEMCPY = 298, // GenericOpcodes.td:1773
314 G_MEMCPY_INLINE = 299, // GenericOpcodes.td:1781
315 G_MEMMOVE = 300, // GenericOpcodes.td:1789
316 G_MEMSET = 301, // GenericOpcodes.td:1797
317 G_BZERO = 302, // GenericOpcodes.td:1804
318 G_TRAP = 303, // GenericOpcodes.td:1814
319 G_DEBUGTRAP = 304, // GenericOpcodes.td:1821
320 G_UBSANTRAP = 305, // GenericOpcodes.td:1827
321 G_VECREDUCE_SEQ_FADD = 306, // GenericOpcodes.td:1726
322 G_VECREDUCE_SEQ_FMUL = 307, // GenericOpcodes.td:1732
323 G_VECREDUCE_FADD = 308, // GenericOpcodes.td:1738
324 G_VECREDUCE_FMUL = 309, // GenericOpcodes.td:1739
325 G_VECREDUCE_FMAX = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMIN = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_FMAXIMUM = 312, // GenericOpcodes.td:1743
328 G_VECREDUCE_FMINIMUM = 313, // GenericOpcodes.td:1744
329 G_VECREDUCE_ADD = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_MUL = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_AND = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_OR = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_XOR = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_SMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_SMIN = 320, // GenericOpcodes.td:1752
336 G_VECREDUCE_UMAX = 321, // GenericOpcodes.td:1753
337 G_VECREDUCE_UMIN = 322, // GenericOpcodes.td:1754
338 G_SBFX = 323, // GenericOpcodes.td:1839
339 G_UBFX = 324, // GenericOpcodes.td:1847
340 ADJCALLSTACKDOWN = 325, // BPFInstrInfo.td:817
341 ADJCALLSTACKUP = 326, // BPFInstrInfo.td:820
342 FI_ri = 327, // BPFInstrInfo.td:483
343 LDIMM64 = 328, // BPFInstrInfo.td:1393
344 MEMCPY = 329, // BPFInstrInfo.td:1384
345 Select = 330, // BPFInstrInfo.td:826
346 Select_32 = 331, // BPFInstrInfo.td:846
347 Select_32_64 = 332, // BPFInstrInfo.td:856
348 Select_64_32 = 333, // BPFInstrInfo.td:836
349 Select_Ri = 334, // BPFInstrInfo.td:831
350 Select_Ri_32 = 335, // BPFInstrInfo.td:851
351 Select_Ri_32_64 = 336, // BPFInstrInfo.td:861
352 Select_Ri_64_32 = 337, // BPFInstrInfo.td:841
353 ADDR_SPACE_CAST = 338, // BPFInstrInfo.td:454
354 ADD_ri = 339, // BPFInstrInfo.td:334
355 ADD_ri_32 = 340, // BPFInstrInfo.td:344
356 ADD_rr = 341, // BPFInstrInfo.td:329
357 ADD_rr_32 = 342, // BPFInstrInfo.td:339
358 AND_ri = 343, // BPFInstrInfo.td:334
359 AND_ri_32 = 344, // BPFInstrInfo.td:344
360 AND_rr = 345, // BPFInstrInfo.td:329
361 AND_rr_32 = 346, // BPFInstrInfo.td:339
362 BE16 = 347, // BPFInstrInfo.td:1193
363 BE32 = 348, // BPFInstrInfo.td:1194
364 BE64 = 349, // BPFInstrInfo.td:1195
365 BSWAP16 = 350, // BPFInstrInfo.td:1186
366 BSWAP32 = 351, // BPFInstrInfo.td:1187
367 BSWAP64 = 352, // BPFInstrInfo.td:1188
368 CMPXCHGD = 353, // BPFInstrInfo.td:1166
369 CMPXCHGW32 = 354, // BPFInstrInfo.td:1162
370 CORE_LD32 = 355, // BPFInstrInfo.td:655
371 CORE_LD64 = 356, // BPFInstrInfo.td:654
372 CORE_SHIFT = 357, // BPFInstrInfo.td:662
373 CORE_ST = 358, // BPFInstrInfo.td:656
374 DIV_ri = 359, // BPFInstrInfo.td:334
375 DIV_ri_32 = 360, // BPFInstrInfo.td:344
376 DIV_rr = 361, // BPFInstrInfo.td:329
377 DIV_rr_32 = 362, // BPFInstrInfo.td:339
378 JAL = 363, // BPFInstrInfo.td:781
379 JALX = 364, // BPFInstrInfo.td:782
380 JCOND = 365, // BPFInstrInfo.td:294
381 JEQ_ri = 366, // BPFInstrInfo.td:276
382 JEQ_ri_32 = 367, // BPFInstrInfo.td:278
383 JEQ_rr = 368, // BPFInstrInfo.td:275
384 JEQ_rr_32 = 369, // BPFInstrInfo.td:277
385 JMP = 370, // BPFInstrInfo.td:775
386 JMPL = 371, // BPFInstrInfo.td:776
387 JNE_ri = 372, // BPFInstrInfo.td:276
388 JNE_ri_32 = 373, // BPFInstrInfo.td:278
389 JNE_rr = 374, // BPFInstrInfo.td:275
390 JNE_rr_32 = 375, // BPFInstrInfo.td:277
391 JSET_ri = 376, // BPFInstrInfo.td:276
392 JSET_ri_32 = 377, // BPFInstrInfo.td:278
393 JSET_rr = 378, // BPFInstrInfo.td:275
394 JSET_rr_32 = 379, // BPFInstrInfo.td:277
395 JSGE_ri = 380, // BPFInstrInfo.td:276
396 JSGE_ri_32 = 381, // BPFInstrInfo.td:278
397 JSGE_rr = 382, // BPFInstrInfo.td:275
398 JSGE_rr_32 = 383, // BPFInstrInfo.td:277
399 JSGT_ri = 384, // BPFInstrInfo.td:276
400 JSGT_ri_32 = 385, // BPFInstrInfo.td:278
401 JSGT_rr = 386, // BPFInstrInfo.td:275
402 JSGT_rr_32 = 387, // BPFInstrInfo.td:277
403 JSLE_ri = 388, // BPFInstrInfo.td:276
404 JSLE_ri_32 = 389, // BPFInstrInfo.td:278
405 JSLE_rr = 390, // BPFInstrInfo.td:275
406 JSLE_rr_32 = 391, // BPFInstrInfo.td:277
407 JSLT_ri = 392, // BPFInstrInfo.td:276
408 JSLT_ri_32 = 393, // BPFInstrInfo.td:278
409 JSLT_rr = 394, // BPFInstrInfo.td:275
410 JSLT_rr_32 = 395, // BPFInstrInfo.td:277
411 JUGE_ri = 396, // BPFInstrInfo.td:276
412 JUGE_ri_32 = 397, // BPFInstrInfo.td:278
413 JUGE_rr = 398, // BPFInstrInfo.td:275
414 JUGE_rr_32 = 399, // BPFInstrInfo.td:277
415 JUGT_ri = 400, // BPFInstrInfo.td:276
416 JUGT_ri_32 = 401, // BPFInstrInfo.td:278
417 JUGT_rr = 402, // BPFInstrInfo.td:275
418 JUGT_rr_32 = 403, // BPFInstrInfo.td:277
419 JULE_ri = 404, // BPFInstrInfo.td:276
420 JULE_ri_32 = 405, // BPFInstrInfo.td:278
421 JULE_rr = 406, // BPFInstrInfo.td:275
422 JULE_rr_32 = 407, // BPFInstrInfo.td:277
423 JULT_ri = 408, // BPFInstrInfo.td:276
424 JULT_ri_32 = 409, // BPFInstrInfo.td:278
425 JULT_rr = 410, // BPFInstrInfo.td:275
426 JULT_rr_32 = 411, // BPFInstrInfo.td:277
427 JX = 412, // BPFInstrInfo.td:298
428 LDB = 413, // BPFInstrInfo.td:673
429 LDB32 = 414, // BPFInstrInfo.td:1321
430 LDBACQ32 = 415, // BPFInstrInfo.td:1326
431 LDBSX = 416, // BPFInstrInfo.td:679
432 LDD = 417, // BPFInstrInfo.td:682
433 LDDACQ = 418, // BPFInstrInfo.td:716
434 LDH = 419, // BPFInstrInfo.td:672
435 LDH32 = 420, // BPFInstrInfo.td:1320
436 LDHACQ32 = 421, // BPFInstrInfo.td:1325
437 LDHSX = 422, // BPFInstrInfo.td:678
438 LDW = 423, // BPFInstrInfo.td:671
439 LDW32 = 424, // BPFInstrInfo.td:1319
440 LDWACQ32 = 425, // BPFInstrInfo.td:1324
441 LDWSX = 426, // BPFInstrInfo.td:677
442 LD_ABS_B = 427, // BPFInstrInfo.td:1230
443 LD_ABS_H = 428, // BPFInstrInfo.td:1231
444 LD_ABS_W = 429, // BPFInstrInfo.td:1232
445 LD_IND_B = 430, // BPFInstrInfo.td:1234
446 LD_IND_H = 431, // BPFInstrInfo.td:1235
447 LD_IND_W = 432, // BPFInstrInfo.td:1236
448 LD_imm64 = 433, // BPFInstrInfo.td:408
449 LD_pseudo = 434, // BPFInstrInfo.td:499
450 LE16 = 435, // BPFInstrInfo.td:1198
451 LE32 = 436, // BPFInstrInfo.td:1199
452 LE64 = 437, // BPFInstrInfo.td:1200
453 MOD_ri = 438, // BPFInstrInfo.td:334
454 MOD_ri_32 = 439, // BPFInstrInfo.td:344
455 MOD_rr = 440, // BPFInstrInfo.td:329
456 MOD_rr_32 = 441, // BPFInstrInfo.td:339
457 MOVSX_rr_16 = 442, // BPFInstrInfo.td:435
458 MOVSX_rr_32 = 443, // BPFInstrInfo.td:439
459 MOVSX_rr_32_16 = 444, // BPFInstrInfo.td:447
460 MOVSX_rr_32_8 = 445, // BPFInstrInfo.td:443
461 MOVSX_rr_8 = 446, // BPFInstrInfo.td:431
462 MOV_32_64 = 447, // BPFInstrInfo.td:1239
463 MOV_ri = 448, // BPFInstrInfo.td:414
464 MOV_ri_32 = 449, // BPFInstrInfo.td:424
465 MOV_rr = 450, // BPFInstrInfo.td:409
466 MOV_rr_32 = 451, // BPFInstrInfo.td:419
467 MUL_ri = 452, // BPFInstrInfo.td:334
468 MUL_ri_32 = 453, // BPFInstrInfo.td:344
469 MUL_rr = 454, // BPFInstrInfo.td:329
470 MUL_rr_32 = 455, // BPFInstrInfo.td:339
471 NEG_32 = 456, // BPFInstrInfo.td:385
472 NEG_64 = 457, // BPFInstrInfo.td:382
473 NOP = 458, // BPFInstrInfo.td:798
474 OR_ri = 459, // BPFInstrInfo.td:334
475 OR_ri_32 = 460, // BPFInstrInfo.td:344
476 OR_rr = 461, // BPFInstrInfo.td:329
477 OR_rr_32 = 462, // BPFInstrInfo.td:339
478 RET = 463, // BPFInstrInfo.td:812
479 SDIV_ri = 464, // BPFInstrInfo.td:334
480 SDIV_ri_32 = 465, // BPFInstrInfo.td:344
481 SDIV_rr = 466, // BPFInstrInfo.td:329
482 SDIV_rr_32 = 467, // BPFInstrInfo.td:339
483 SLL_ri = 468, // BPFInstrInfo.td:334
484 SLL_ri_32 = 469, // BPFInstrInfo.td:344
485 SLL_rr = 470, // BPFInstrInfo.td:329
486 SLL_rr_32 = 471, // BPFInstrInfo.td:339
487 SMOD_ri = 472, // BPFInstrInfo.td:334
488 SMOD_ri_32 = 473, // BPFInstrInfo.td:344
489 SMOD_rr = 474, // BPFInstrInfo.td:329
490 SMOD_rr_32 = 475, // BPFInstrInfo.td:339
491 SRA_ri = 476, // BPFInstrInfo.td:334
492 SRA_ri_32 = 477, // BPFInstrInfo.td:344
493 SRA_rr = 478, // BPFInstrInfo.td:329
494 SRA_rr_32 = 479, // BPFInstrInfo.td:339
495 SRL_ri = 480, // BPFInstrInfo.td:334
496 SRL_ri_32 = 481, // BPFInstrInfo.td:344
497 SRL_rr = 482, // BPFInstrInfo.td:329
498 SRL_rr_32 = 483, // BPFInstrInfo.td:339
499 STB = 484, // BPFInstrInfo.td:539
500 STB32 = 485, // BPFInstrInfo.td:1288
501 STBREL32 = 486, // BPFInstrInfo.td:1293
502 STB_imm = 487, // BPFInstrInfo.td:575
503 STD = 488, // BPFInstrInfo.td:541
504 STDREL = 489, // BPFInstrInfo.td:619
505 STD_imm = 490, // BPFInstrInfo.td:572
506 STH = 491, // BPFInstrInfo.td:538
507 STH32 = 492, // BPFInstrInfo.td:1287
508 STHREL32 = 493, // BPFInstrInfo.td:1292
509 STH_imm = 494, // BPFInstrInfo.td:574
510 STW = 495, // BPFInstrInfo.td:537
511 STW32 = 496, // BPFInstrInfo.td:1286
512 STWREL32 = 497, // BPFInstrInfo.td:1291
513 STW_imm = 498, // BPFInstrInfo.td:573
514 SUB_ri = 499, // BPFInstrInfo.td:334
515 SUB_ri_32 = 500, // BPFInstrInfo.td:344
516 SUB_rr = 501, // BPFInstrInfo.td:329
517 SUB_rr_32 = 502, // BPFInstrInfo.td:339
518 XADDD = 503, // BPFInstrInfo.td:915
519 XADDW = 504, // BPFInstrInfo.td:914
520 XADDW32 = 505, // BPFInstrInfo.td:909
521 XANDD = 506, // BPFInstrInfo.td:916
522 XANDW32 = 507, // BPFInstrInfo.td:910
523 XCHGD = 508, // BPFInstrInfo.td:1122
524 XCHGW32 = 509, // BPFInstrInfo.td:1119
525 XFADDD = 510, // BPFInstrInfo.td:972
526 XFADDW32 = 511, // BPFInstrInfo.td:965
527 XFANDD = 512, // BPFInstrInfo.td:974
528 XFANDW32 = 513, // BPFInstrInfo.td:966
529 XFORD = 514, // BPFInstrInfo.td:975
530 XFORW32 = 515, // BPFInstrInfo.td:967
531 XFXORD = 516, // BPFInstrInfo.td:976
532 XFXORW32 = 517, // BPFInstrInfo.td:968
533 XORD = 518, // BPFInstrInfo.td:917
534 XORW32 = 519, // BPFInstrInfo.td:911
535 XOR_ri = 520, // BPFInstrInfo.td:334
536 XOR_ri_32 = 521, // BPFInstrInfo.td:344
537 XOR_rr = 522, // BPFInstrInfo.td:329
538 XOR_rr_32 = 523, // BPFInstrInfo.td:339
539 XXORD = 524, // BPFInstrInfo.td:918
540 XXORW32 = 525, // BPFInstrInfo.td:912
541 INSTRUCTION_LIST_END = 526
542 };
543
544} // namespace llvm::BPF
545
546#endif // GET_INSTRINFO_ENUM
547
548#ifdef GET_INSTRINFO_SCHED_ENUM
549#undef GET_INSTRINFO_SCHED_ENUM
550
551namespace llvm::BPF::Sched {
552
553 enum {
554 NoInstrModel = 0,
555 SCHED_LIST_END = 1
556 };
557
558} // namespace llvm::BPF::Sched
559
560#endif // GET_INSTRINFO_SCHED_ENUM
561
562#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
563
564namespace llvm {
565
566struct BPFInstrTable {
567 MCInstrDesc Insts[526];
568 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
569 MCPhysReg ImplicitOps[14];
570 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
571 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
572 MCOperandInfo OperandInfo[280];
573};
574} // namespace llvm
575
576#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
577
578#ifdef GET_INSTRINFO_MC_DESC
579#undef GET_INSTRINFO_MC_DESC
580
581namespace llvm {
582
583static_assert((sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
584static constexpr unsigned BPFOpInfoBase = (sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) / sizeof(MCOperandInfo);
585
586extern const BPFInstrTable BPFDescs = {
587 {
588 { 525, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORW32
589 { 524, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORD
590 { 523, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr_32
591 { 522, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr
592 { 521, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri_32
593 { 520, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri
594 { 519, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORW32
595 { 518, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORD
596 { 517, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORW32
597 { 516, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORD
598 { 515, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORW32
599 { 514, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORD
600 { 513, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDW32
601 { 512, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDD
602 { 511, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDW32
603 { 510, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDD
604 { 509, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGW32
605 { 508, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGD
606 { 507, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDW32
607 { 506, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDD
608 { 505, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW32
609 { 504, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW
610 { 503, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 272, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDD
611 { 502, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr_32
612 { 501, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr
613 { 500, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri_32
614 { 499, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri
615 { 498, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 269, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_imm
616 { 497, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWREL32
617 { 496, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW32
618 { 495, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW
619 { 494, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 269, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_imm
620 { 493, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STHREL32
621 { 492, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH32
622 { 491, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH
623 { 490, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 269, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD_imm
624 { 489, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDREL
625 { 488, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD
626 { 487, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 269, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_imm
627 { 486, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STBREL32
628 { 485, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB32
629 { 484, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB
630 { 483, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr_32
631 { 482, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr
632 { 481, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri_32
633 { 480, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri
634 { 479, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr_32
635 { 478, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr
636 { 477, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri_32
637 { 476, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri
638 { 475, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr_32
639 { 474, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr
640 { 473, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri_32
641 { 472, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri
642 { 471, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr_32
643 { 470, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr
644 { 469, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri_32
645 { 468, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri
646 { 467, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr_32
647 { 466, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr
648 { 465, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri_32
649 { 464, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri
650 { 463, 0, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
651 { 462, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr_32
652 { 461, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr
653 { 460, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri_32
654 { 459, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri
655 { 458, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
656 { 457, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_64
657 { 456, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 267, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_32
658 { 455, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr_32
659 { 454, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr
660 { 453, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri_32
661 { 452, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri
662 { 451, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr_32
663 { 450, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 259, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr
664 { 449, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 265, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri_32
665 { 448, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri
666 { 447, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_32_64
667 { 446, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 259, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_8
668 { 445, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_8
669 { 444, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_16
670 { 443, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 259, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32
671 { 442, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 259, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_16
672 { 441, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr_32
673 { 440, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr
674 { 439, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri_32
675 { 438, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri
676 { 437, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE64
677 { 436, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE32
678 { 435, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE16
679 { 434, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_pseudo
680 { 433, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_imm64
681 { 432, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_W
682 { 431, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_H
683 { 430, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_B
684 { 429, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_W
685 { 428, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_H
686 { 427, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_B
687 { 426, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSX
688 { 425, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWACQ32
689 { 424, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW32
690 { 423, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW
691 { 422, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHSX
692 { 421, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHACQ32
693 { 420, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH32
694 { 419, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH
695 { 418, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDDACQ
696 { 417, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDD
697 { 416, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBSX
698 { 415, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBACQ32
699 { 414, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 256, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB32
700 { 413, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB
701 { 412, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JX
702 { 411, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr_32
703 { 410, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr
704 { 409, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri_32
705 { 408, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri
706 { 407, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr_32
707 { 406, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr
708 { 405, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri_32
709 { 404, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri
710 { 403, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr_32
711 { 402, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr
712 { 401, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri_32
713 { 400, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri
714 { 399, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr_32
715 { 398, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr
716 { 397, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri_32
717 { 396, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri
718 { 395, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr_32
719 { 394, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr
720 { 393, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri_32
721 { 392, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri
722 { 391, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr_32
723 { 390, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr
724 { 389, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri_32
725 { 388, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri
726 { 387, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr_32
727 { 386, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr
728 { 385, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri_32
729 { 384, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri
730 { 383, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr_32
731 { 382, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr
732 { 381, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri_32
733 { 380, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri
734 { 379, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr_32
735 { 378, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr
736 { 377, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri_32
737 { 376, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri
738 { 375, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr_32
739 { 374, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr
740 { 373, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri_32
741 { 372, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri
742 { 371, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMPL
743 { 370, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
744 { 369, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 253, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr_32
745 { 368, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 250, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr
746 { 367, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 247, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri_32
747 { 366, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri
748 { 365, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCOND
749 { 364, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 28, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JALX
750 { 363, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 0, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JAL
751 { 362, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr_32
752 { 361, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr
753 { 360, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri_32
754 { 359, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri
755 { 358, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_ST
756 { 357, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_SHIFT
757 { 356, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD64
758 { 355, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 228, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD32
759 { 354, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 225, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGW32
760 { 353, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 222, 2, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGD
761 { 352, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP64
762 { 351, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP32
763 { 350, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP16
764 { 349, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE64
765 { 348, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE32
766 { 347, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 220, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE16
767 { 346, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr_32
768 { 345, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr
769 { 344, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri_32
770 { 343, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri
771 { 342, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 217, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr_32
772 { 341, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 214, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr
773 { 340, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 211, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri_32
774 { 339, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 208, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri
775 { 338, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDR_SPACE_CAST
776 { 337, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 202, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_64_32
777 { 336, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 196, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32_64
778 { 335, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 190, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32
779 { 334, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 184, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri
780 { 333, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 178, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_64_32
781 { 332, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 172, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32_64
782 { 331, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 166, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32
783 { 330, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select
784 { 329, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY
785 { 328, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIMM64
786 { 327, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FI_ri
787 { 326, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
788 { 325, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
789 { 324, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
790 { 323, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
791 { 322, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
792 { 321, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
793 { 320, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
794 { 319, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
795 { 318, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
796 { 317, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
797 { 316, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
798 { 315, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
799 { 314, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
800 { 313, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
801 { 312, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
802 { 311, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
803 { 310, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
804 { 309, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
805 { 308, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
806 { 307, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
807 { 306, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
808 { 305, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
809 { 304, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
810 { 303, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
811 { 302, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
812 { 301, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
813 { 300, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
814 { 299, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
815 { 298, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
816 { 297, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
817 { 296, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
818 { 295, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
819 { 294, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
820 { 293, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
821 { 292, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
822 { 291, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
823 { 290, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
824 { 289, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
825 { 288, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
826 { 287, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
827 { 286, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
828 { 285, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
829 { 284, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
830 { 283, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
831 { 282, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
832 { 281, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
833 { 280, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
834 { 279, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
835 { 278, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
836 { 277, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
837 { 276, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
838 { 275, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
839 { 274, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
840 { 273, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
841 { 272, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
842 { 271, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
843 { 270, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
844 { 269, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
845 { 268, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
846 { 267, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
847 { 266, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
848 { 265, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
849 { 264, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
850 { 263, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
851 { 262, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
852 { 261, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
853 { 260, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
854 { 259, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
855 { 258, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
856 { 257, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
857 { 256, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
858 { 255, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
859 { 254, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
860 { 253, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
861 { 252, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
862 { 251, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
863 { 250, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
864 { 249, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
865 { 248, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
866 { 247, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
867 { 246, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
868 { 245, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
869 { 244, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
870 { 243, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
871 { 242, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
872 { 241, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
873 { 240, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
874 { 239, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
875 { 238, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
876 { 237, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
877 { 236, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
878 { 235, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
879 { 234, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
880 { 233, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
881 { 232, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
882 { 231, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
883 { 230, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
884 { 229, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
885 { 228, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
886 { 227, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
887 { 226, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
888 { 225, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
889 { 224, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
890 { 223, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
891 { 222, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
892 { 221, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
893 { 220, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
894 { 219, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
895 { 218, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
896 { 217, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
897 { 216, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
898 { 215, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
899 { 214, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
900 { 213, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
901 { 212, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
902 { 211, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
903 { 210, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
904 { 209, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
905 { 208, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
906 { 207, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
907 { 206, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
908 { 205, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
909 { 204, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
910 { 203, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
911 { 202, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
912 { 201, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
913 { 200, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
914 { 199, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
915 { 198, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
916 { 197, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
917 { 196, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
918 { 195, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
919 { 194, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
920 { 193, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
921 { 192, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
922 { 191, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
923 { 190, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
924 { 189, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
925 { 188, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
926 { 187, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
927 { 186, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
928 { 185, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
929 { 184, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
930 { 183, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
931 { 182, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
932 { 181, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
933 { 180, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
934 { 179, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
935 { 178, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
936 { 177, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
937 { 176, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
938 { 175, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
939 { 174, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
940 { 173, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
941 { 172, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
942 { 171, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
943 { 170, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
944 { 169, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
945 { 168, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
946 { 167, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
947 { 166, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
948 { 165, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
949 { 164, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
950 { 163, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
951 { 162, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
952 { 161, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
953 { 160, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
954 { 159, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
955 { 158, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
956 { 157, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
957 { 156, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
958 { 155, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
959 { 154, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
960 { 153, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
961 { 152, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
962 { 151, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
963 { 150, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
964 { 149, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
965 { 148, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
966 { 147, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
967 { 146, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
968 { 145, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
969 { 144, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
970 { 143, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
971 { 142, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
972 { 141, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
973 { 140, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
974 { 139, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
975 { 138, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
976 { 137, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
977 { 136, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
978 { 135, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
979 { 134, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
980 { 133, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
981 { 132, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
982 { 131, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
983 { 130, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
984 { 129, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
985 { 128, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
986 { 127, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
987 { 126, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
988 { 125, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
989 { 124, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
990 { 123, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
991 { 122, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
992 { 121, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
993 { 120, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
994 { 119, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
995 { 118, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
996 { 117, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
997 { 116, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
998 { 115, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
999 { 114, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1000 { 113, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1001 { 112, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1002 { 111, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1003 { 110, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1004 { 109, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1005 { 108, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1006 { 107, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1007 { 106, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1008 { 105, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1009 { 104, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1010 { 103, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1011 { 102, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1012 { 101, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1013 { 100, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1014 { 99, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1015 { 98, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1016 { 97, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1017 { 96, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1018 { 95, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1019 { 94, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1020 { 93, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1021 { 92, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1022 { 91, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1023 { 90, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1024 { 89, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1025 { 88, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1026 { 87, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1027 { 86, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1028 { 85, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1029 { 84, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1030 { 83, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1031 { 82, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1032 { 81, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1033 { 80, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1034 { 79, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1035 { 78, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1036 { 77, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1037 { 76, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1038 { 75, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1039 { 74, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1040 { 73, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1041 { 72, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1042 { 71, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1043 { 70, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1044 { 69, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1045 { 68, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1046 { 67, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1047 { 66, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1048 { 65, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1049 { 64, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1050 { 63, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1051 { 62, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1052 { 61, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1053 { 60, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1054 { 59, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1055 { 58, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1056 { 57, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1057 { 56, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1058 { 55, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1059 { 54, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1060 { 53, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1061 { 52, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1062 { 51, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1063 { 50, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1064 { 49, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1065 { 48, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1066 { 47, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1067 { 46, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1068 { 45, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1069 { 44, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1070 { 43, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1071 { 42, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13959
1072 { 41, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13958
1073 { 40, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1074 { 39, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1075 { 38, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1076 { 37, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1077 { 36, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1078 { 35, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1079 { 34, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1080 { 33, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1081 { 32, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13957
1082 { 31, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1083 { 30, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13542
1084 { 29, 6, 1, 0, 0, 0, 0, BPFOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1085 { 28, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1086 { 27, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1087 { 26, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1088 { 25, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1089 { 24, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1090 { 23, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1091 { 22, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1092 { 21, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1093 { 20, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1094 { 19, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1095 { 18, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1096 { 17, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1097 { 16, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1098 { 15, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1099 { 14, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1100 { 13, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1101 { 12, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1102 { 11, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1103 { 10, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1104 { 9, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1105 { 8, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1106 { 7, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1107 { 6, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1108 { 5, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1109 { 4, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1110 { 3, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1111 { 2, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1112 { 1, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1113 { 0, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1114 }, {
1115 /* 0 */
1116 /* 0 */ BPF::R11, BPF::R11,
1117 /* 2 */ BPF::R0, BPF::R0,
1118 /* 4 */ BPF::W0, BPF::W0,
1119 /* 6 */ BPF::R11,
1120 /* 7 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1121 }, {
1122 0
1123 }, {
1124 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1125 /* 1 */
1126 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1127 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1128 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1129 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1130 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1131 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1132 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1133 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1134 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1135 /* 28 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1136 /* 29 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1137 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1138 /* 34 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1139 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1140 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1141 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1142 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1143 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1144 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1145 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1146 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1147 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1148 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1149 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1150 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1151 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1152 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1153 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1154 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1155 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1156 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1157 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1158 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1159 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1160 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1161 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1162 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1163 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1164 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1165 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1166 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1167 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1168 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1169 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1170 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1171 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1172 /* 151 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1173 /* 154 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1174 /* 156 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1175 /* 160 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1176 /* 166 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1177 /* 172 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1178 /* 178 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1179 /* 184 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1180 /* 190 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1181 /* 196 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1182 /* 202 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1183 /* 208 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1184 /* 211 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1185 /* 214 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1186 /* 217 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1187 /* 220 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1188 /* 222 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1189 /* 225 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1190 /* 228 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1191 /* 232 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1192 /* 236 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1193 /* 240 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1194 /* 244 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1195 /* 247 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1196 /* 250 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1197 /* 253 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1198 /* 256 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1199 /* 259 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1200 /* 261 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1201 /* 263 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1202 /* 265 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1203 /* 267 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1204 /* 269 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1205 /* 272 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1206 /* 276 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1207 }
1208};
1209
1210
1211#ifdef __GNUC__
1212#pragma GCC diagnostic push
1213#pragma GCC diagnostic ignored "-Woverlength-strings"
1214#endif
1215extern const char BPFInstrNameData[] = {
1216 /* 0 */ "G_FLOG10\000"
1217 /* 9 */ "G_FEXP10\000"
1218 /* 18 */ "LDB32\000"
1219 /* 24 */ "STB32\000"
1220 /* 30 */ "CORE_LD32\000"
1221 /* 40 */ "BE32\000"
1222 /* 45 */ "LE32\000"
1223 /* 50 */ "LDH32\000"
1224 /* 56 */ "STH32\000"
1225 /* 62 */ "STBREL32\000"
1226 /* 71 */ "STHREL32\000"
1227 /* 80 */ "STWREL32\000"
1228 /* 89 */ "BSWAP32\000"
1229 /* 97 */ "LDBACQ32\000"
1230 /* 106 */ "LDHACQ32\000"
1231 /* 115 */ "LDWACQ32\000"
1232 /* 124 */ "XFADDW32\000"
1233 /* 133 */ "XADDW32\000"
1234 /* 141 */ "LDW32\000"
1235 /* 147 */ "XFANDW32\000"
1236 /* 156 */ "XANDW32\000"
1237 /* 164 */ "CMPXCHGW32\000"
1238 /* 175 */ "XFORW32\000"
1239 /* 183 */ "XFXORW32\000"
1240 /* 192 */ "XXORW32\000"
1241 /* 200 */ "STW32\000"
1242 /* 206 */ "Select_Ri_64_32\000"
1243 /* 222 */ "Select_64_32\000"
1244 /* 235 */ "NEG_32\000"
1245 /* 242 */ "Select_Ri_32\000"
1246 /* 255 */ "SRA_ri_32\000"
1247 /* 265 */ "SUB_ri_32\000"
1248 /* 275 */ "ADD_ri_32\000"
1249 /* 285 */ "AND_ri_32\000"
1250 /* 295 */ "SMOD_ri_32\000"
1251 /* 306 */ "JSGE_ri_32\000"
1252 /* 317 */ "JUGE_ri_32\000"
1253 /* 328 */ "JSLE_ri_32\000"
1254 /* 339 */ "JULE_ri_32\000"
1255 /* 350 */ "JNE_ri_32\000"
1256 /* 360 */ "SLL_ri_32\000"
1257 /* 370 */ "SRL_ri_32\000"
1258 /* 380 */ "MUL_ri_32\000"
1259 /* 390 */ "JEQ_ri_32\000"
1260 /* 400 */ "XOR_ri_32\000"
1261 /* 410 */ "JSET_ri_32\000"
1262 /* 421 */ "JSGT_ri_32\000"
1263 /* 432 */ "JUGT_ri_32\000"
1264 /* 443 */ "JSLT_ri_32\000"
1265 /* 454 */ "JULT_ri_32\000"
1266 /* 465 */ "SDIV_ri_32\000"
1267 /* 476 */ "MOV_ri_32\000"
1268 /* 486 */ "SRA_rr_32\000"
1269 /* 496 */ "SUB_rr_32\000"
1270 /* 506 */ "ADD_rr_32\000"
1271 /* 516 */ "AND_rr_32\000"
1272 /* 526 */ "SMOD_rr_32\000"
1273 /* 537 */ "JSGE_rr_32\000"
1274 /* 548 */ "JUGE_rr_32\000"
1275 /* 559 */ "JSLE_rr_32\000"
1276 /* 570 */ "JULE_rr_32\000"
1277 /* 581 */ "JNE_rr_32\000"
1278 /* 591 */ "SLL_rr_32\000"
1279 /* 601 */ "SRL_rr_32\000"
1280 /* 611 */ "MUL_rr_32\000"
1281 /* 621 */ "JEQ_rr_32\000"
1282 /* 631 */ "XOR_rr_32\000"
1283 /* 641 */ "JSET_rr_32\000"
1284 /* 652 */ "JSGT_rr_32\000"
1285 /* 663 */ "JUGT_rr_32\000"
1286 /* 674 */ "JSLT_rr_32\000"
1287 /* 685 */ "JULT_rr_32\000"
1288 /* 696 */ "SDIV_rr_32\000"
1289 /* 707 */ "MOV_rr_32\000"
1290 /* 717 */ "MOVSX_rr_32\000"
1291 /* 729 */ "Select_32\000"
1292 /* 739 */ "G_FLOG2\000"
1293 /* 747 */ "G_FATAN2\000"
1294 /* 756 */ "G_FEXP2\000"
1295 /* 764 */ "CORE_LD64\000"
1296 /* 774 */ "BE64\000"
1297 /* 779 */ "LE64\000"
1298 /* 784 */ "LDIMM64\000"
1299 /* 792 */ "BSWAP64\000"
1300 /* 800 */ "MOV_32_64\000"
1301 /* 810 */ "Select_Ri_32_64\000"
1302 /* 826 */ "Select_32_64\000"
1303 /* 839 */ "NEG_64\000"
1304 /* 846 */ "LD_imm64\000"
1305 /* 855 */ "BE16\000"
1306 /* 860 */ "LE16\000"
1307 /* 865 */ "BSWAP16\000"
1308 /* 873 */ "MOVSX_rr_32_16\000"
1309 /* 888 */ "MOVSX_rr_16\000"
1310 /* 900 */ "MOVSX_rr_32_8\000"
1311 /* 914 */ "MOVSX_rr_8\000"
1312 /* 925 */ "G_FMA\000"
1313 /* 931 */ "G_STRICT_FMA\000"
1314 /* 944 */ "LDB\000"
1315 /* 948 */ "STB\000"
1316 /* 952 */ "G_FSUB\000"
1317 /* 959 */ "G_STRICT_FSUB\000"
1318 /* 973 */ "G_ATOMICRMW_FSUB\000"
1319 /* 990 */ "G_SUB\000"
1320 /* 996 */ "G_ATOMICRMW_SUB\000"
1321 /* 1012 */ "LD_IND_B\000"
1322 /* 1021 */ "LD_ABS_B\000"
1323 /* 1030 */ "G_INTRINSIC\000"
1324 /* 1042 */ "G_FPTRUNC\000"
1325 /* 1052 */ "G_INTRINSIC_TRUNC\000"
1326 /* 1070 */ "G_TRUNC\000"
1327 /* 1078 */ "G_BUILD_VECTOR_TRUNC\000"
1328 /* 1099 */ "G_DYN_STACKALLOC\000"
1329 /* 1116 */ "G_FMAD\000"
1330 /* 1123 */ "G_INDEXED_SEXTLOAD\000"
1331 /* 1142 */ "G_SEXTLOAD\000"
1332 /* 1153 */ "G_INDEXED_ZEXTLOAD\000"
1333 /* 1172 */ "G_ZEXTLOAD\000"
1334 /* 1183 */ "G_INDEXED_LOAD\000"
1335 /* 1198 */ "G_LOAD\000"
1336 /* 1205 */ "G_VECREDUCE_FADD\000"
1337 /* 1222 */ "G_FADD\000"
1338 /* 1229 */ "G_VECREDUCE_SEQ_FADD\000"
1339 /* 1250 */ "G_STRICT_FADD\000"
1340 /* 1264 */ "G_ATOMICRMW_FADD\000"
1341 /* 1281 */ "G_VECREDUCE_ADD\000"
1342 /* 1297 */ "G_ADD\000"
1343 /* 1303 */ "G_PTR_ADD\000"
1344 /* 1313 */ "G_ATOMICRMW_ADD\000"
1345 /* 1329 */ "XFADDD\000"
1346 /* 1336 */ "XADDD\000"
1347 /* 1342 */ "LDD\000"
1348 /* 1346 */ "XFANDD\000"
1349 /* 1353 */ "XANDD\000"
1350 /* 1359 */ "CMPXCHGD\000"
1351 /* 1368 */ "G_ATOMICRMW_NAND\000"
1352 /* 1385 */ "G_VECREDUCE_AND\000"
1353 /* 1401 */ "G_AND\000"
1354 /* 1407 */ "G_ATOMICRMW_AND\000"
1355 /* 1423 */ "LIFETIME_END\000"
1356 /* 1436 */ "JCOND\000"
1357 /* 1442 */ "G_BRCOND\000"
1358 /* 1451 */ "G_ATOMICRMW_USUB_COND\000"
1359 /* 1473 */ "G_LLROUND\000"
1360 /* 1483 */ "G_LROUND\000"
1361 /* 1492 */ "G_INTRINSIC_ROUND\000"
1362 /* 1510 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1363 /* 1536 */ "LOAD_STACK_GUARD\000"
1364 /* 1553 */ "XFORD\000"
1365 /* 1559 */ "XFXORD\000"
1366 /* 1566 */ "XXORD\000"
1367 /* 1572 */ "STD\000"
1368 /* 1576 */ "PSEUDO_PROBE\000"
1369 /* 1589 */ "G_SSUBE\000"
1370 /* 1597 */ "G_USUBE\000"
1371 /* 1605 */ "G_FENCE\000"
1372 /* 1613 */ "ARITH_FENCE\000"
1373 /* 1625 */ "REG_SEQUENCE\000"
1374 /* 1638 */ "G_SADDE\000"
1375 /* 1646 */ "G_UADDE\000"
1376 /* 1654 */ "G_GET_FPMODE\000"
1377 /* 1667 */ "G_RESET_FPMODE\000"
1378 /* 1682 */ "G_SET_FPMODE\000"
1379 /* 1695 */ "G_FMINNUM_IEEE\000"
1380 /* 1710 */ "G_FMAXNUM_IEEE\000"
1381 /* 1725 */ "G_VSCALE\000"
1382 /* 1734 */ "G_JUMP_TABLE\000"
1383 /* 1747 */ "BUNDLE\000"
1384 /* 1754 */ "G_MEMCPY_INLINE\000"
1385 /* 1770 */ "RELOC_NONE\000"
1386 /* 1781 */ "LOCAL_ESCAPE\000"
1387 /* 1794 */ "G_STACKRESTORE\000"
1388 /* 1809 */ "G_INDEXED_STORE\000"
1389 /* 1825 */ "G_STORE\000"
1390 /* 1833 */ "G_BITREVERSE\000"
1391 /* 1846 */ "FAKE_USE\000"
1392 /* 1855 */ "DBG_VALUE\000"
1393 /* 1865 */ "G_GLOBAL_VALUE\000"
1394 /* 1880 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1395 /* 1903 */ "CONVERGENCECTRL_GLUE\000"
1396 /* 1924 */ "G_STACKSAVE\000"
1397 /* 1936 */ "G_MEMMOVE\000"
1398 /* 1946 */ "G_FREEZE\000"
1399 /* 1955 */ "G_FCANONICALIZE\000"
1400 /* 1971 */ "G_FMODF\000"
1401 /* 1979 */ "G_CTLZ_ZERO_UNDEF\000"
1402 /* 1997 */ "G_CTTZ_ZERO_UNDEF\000"
1403 /* 2015 */ "INIT_UNDEF\000"
1404 /* 2026 */ "G_IMPLICIT_DEF\000"
1405 /* 2041 */ "DBG_INSTR_REF\000"
1406 /* 2055 */ "G_FNEG\000"
1407 /* 2062 */ "EXTRACT_SUBREG\000"
1408 /* 2077 */ "INSERT_SUBREG\000"
1409 /* 2091 */ "G_SEXT_INREG\000"
1410 /* 2104 */ "SUBREG_TO_REG\000"
1411 /* 2118 */ "G_ATOMIC_CMPXCHG\000"
1412 /* 2135 */ "G_ATOMICRMW_XCHG\000"
1413 /* 2152 */ "G_GET_ROUNDING\000"
1414 /* 2167 */ "G_SET_ROUNDING\000"
1415 /* 2182 */ "G_FLOG\000"
1416 /* 2189 */ "G_VAARG\000"
1417 /* 2197 */ "PREALLOCATED_ARG\000"
1418 /* 2214 */ "G_PREFETCH\000"
1419 /* 2225 */ "LDH\000"
1420 /* 2229 */ "G_SMULH\000"
1421 /* 2237 */ "G_UMULH\000"
1422 /* 2245 */ "G_FTANH\000"
1423 /* 2253 */ "G_FSINH\000"
1424 /* 2261 */ "G_FCOSH\000"
1425 /* 2269 */ "STH\000"
1426 /* 2273 */ "LD_IND_H\000"
1427 /* 2282 */ "LD_ABS_H\000"
1428 /* 2291 */ "DBG_PHI\000"
1429 /* 2299 */ "G_FPTOSI\000"
1430 /* 2308 */ "G_FPTOUI\000"
1431 /* 2317 */ "G_FPOWI\000"
1432 /* 2325 */ "COPY_LANEMASK\000"
1433 /* 2339 */ "G_PTRMASK\000"
1434 /* 2349 */ "JAL\000"
1435 /* 2353 */ "GC_LABEL\000"
1436 /* 2362 */ "DBG_LABEL\000"
1437 /* 2372 */ "EH_LABEL\000"
1438 /* 2381 */ "ANNOTATION_LABEL\000"
1439 /* 2398 */ "ICALL_BRANCH_FUNNEL\000"
1440 /* 2418 */ "STDREL\000"
1441 /* 2425 */ "G_FSHL\000"
1442 /* 2432 */ "G_SHL\000"
1443 /* 2438 */ "G_FCEIL\000"
1444 /* 2446 */ "G_SAVGCEIL\000"
1445 /* 2457 */ "G_UAVGCEIL\000"
1446 /* 2468 */ "PATCHABLE_TAIL_CALL\000"
1447 /* 2488 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1448 /* 2515 */ "PATCHABLE_EVENT_CALL\000"
1449 /* 2536 */ "FENTRY_CALL\000"
1450 /* 2548 */ "KILL\000"
1451 /* 2553 */ "G_CONSTANT_POOL\000"
1452 /* 2569 */ "JMPL\000"
1453 /* 2574 */ "G_ROTL\000"
1454 /* 2581 */ "G_VECREDUCE_FMUL\000"
1455 /* 2598 */ "G_FMUL\000"
1456 /* 2605 */ "G_VECREDUCE_SEQ_FMUL\000"
1457 /* 2626 */ "G_STRICT_FMUL\000"
1458 /* 2640 */ "G_VECREDUCE_MUL\000"
1459 /* 2656 */ "G_MUL\000"
1460 /* 2662 */ "G_FREM\000"
1461 /* 2669 */ "G_STRICT_FREM\000"
1462 /* 2683 */ "G_SREM\000"
1463 /* 2690 */ "G_UREM\000"
1464 /* 2697 */ "G_SDIVREM\000"
1465 /* 2707 */ "G_UDIVREM\000"
1466 /* 2717 */ "INLINEASM\000"
1467 /* 2727 */ "G_VECREDUCE_FMINIMUM\000"
1468 /* 2748 */ "G_FMINIMUM\000"
1469 /* 2759 */ "G_ATOMICRMW_FMINIMUM\000"
1470 /* 2780 */ "G_VECREDUCE_FMAXIMUM\000"
1471 /* 2801 */ "G_FMAXIMUM\000"
1472 /* 2812 */ "G_ATOMICRMW_FMAXIMUM\000"
1473 /* 2833 */ "G_FMINIMUMNUM\000"
1474 /* 2847 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1475 /* 2871 */ "G_FMAXIMUMNUM\000"
1476 /* 2885 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1477 /* 2909 */ "G_FMINNUM\000"
1478 /* 2919 */ "G_FMAXNUM\000"
1479 /* 2929 */ "G_FATAN\000"
1480 /* 2937 */ "G_FTAN\000"
1481 /* 2944 */ "G_INTRINSIC_ROUNDEVEN\000"
1482 /* 2966 */ "G_ASSERT_ALIGN\000"
1483 /* 2981 */ "G_FCOPYSIGN\000"
1484 /* 2993 */ "G_VECREDUCE_FMIN\000"
1485 /* 3010 */ "G_ATOMICRMW_FMIN\000"
1486 /* 3027 */ "G_VECREDUCE_SMIN\000"
1487 /* 3044 */ "G_SMIN\000"
1488 /* 3051 */ "G_VECREDUCE_UMIN\000"
1489 /* 3068 */ "G_UMIN\000"
1490 /* 3075 */ "G_ATOMICRMW_UMIN\000"
1491 /* 3092 */ "G_ATOMICRMW_MIN\000"
1492 /* 3108 */ "G_FASIN\000"
1493 /* 3116 */ "G_FSIN\000"
1494 /* 3123 */ "CFI_INSTRUCTION\000"
1495 /* 3139 */ "ADJCALLSTACKDOWN\000"
1496 /* 3156 */ "G_SSUBO\000"
1497 /* 3164 */ "G_USUBO\000"
1498 /* 3172 */ "G_SADDO\000"
1499 /* 3180 */ "G_UADDO\000"
1500 /* 3188 */ "JUMP_TABLE_DEBUG_INFO\000"
1501 /* 3210 */ "G_SMULO\000"
1502 /* 3218 */ "G_UMULO\000"
1503 /* 3226 */ "G_BZERO\000"
1504 /* 3234 */ "STACKMAP\000"
1505 /* 3243 */ "G_DEBUGTRAP\000"
1506 /* 3255 */ "G_UBSANTRAP\000"
1507 /* 3267 */ "G_TRAP\000"
1508 /* 3274 */ "G_ATOMICRMW_UDEC_WRAP\000"
1509 /* 3296 */ "G_ATOMICRMW_UINC_WRAP\000"
1510 /* 3318 */ "G_BSWAP\000"
1511 /* 3326 */ "G_SITOFP\000"
1512 /* 3335 */ "G_UITOFP\000"
1513 /* 3344 */ "G_FCMP\000"
1514 /* 3351 */ "G_ICMP\000"
1515 /* 3358 */ "G_SCMP\000"
1516 /* 3365 */ "G_UCMP\000"
1517 /* 3372 */ "JMP\000"
1518 /* 3376 */ "NOP\000"
1519 /* 3380 */ "CONVERGENCECTRL_LOOP\000"
1520 /* 3401 */ "G_CTPOP\000"
1521 /* 3409 */ "PATCHABLE_OP\000"
1522 /* 3422 */ "FAULTING_OP\000"
1523 /* 3434 */ "ADJCALLSTACKUP\000"
1524 /* 3449 */ "PREALLOCATED_SETUP\000"
1525 /* 3468 */ "G_FLDEXP\000"
1526 /* 3477 */ "G_STRICT_FLDEXP\000"
1527 /* 3493 */ "G_FEXP\000"
1528 /* 3500 */ "G_FFREXP\000"
1529 /* 3509 */ "LDDACQ\000"
1530 /* 3516 */ "G_BR\000"
1531 /* 3521 */ "INLINEASM_BR\000"
1532 /* 3534 */ "G_BLOCK_ADDR\000"
1533 /* 3547 */ "MEMBARRIER\000"
1534 /* 3558 */ "G_CONSTANT_FOLD_BARRIER\000"
1535 /* 3582 */ "PATCHABLE_FUNCTION_ENTER\000"
1536 /* 3607 */ "G_READCYCLECOUNTER\000"
1537 /* 3626 */ "G_READSTEADYCOUNTER\000"
1538 /* 3646 */ "G_READ_REGISTER\000"
1539 /* 3662 */ "G_WRITE_REGISTER\000"
1540 /* 3679 */ "G_ASHR\000"
1541 /* 3686 */ "G_FSHR\000"
1542 /* 3693 */ "G_LSHR\000"
1543 /* 3700 */ "CONVERGENCECTRL_ANCHOR\000"
1544 /* 3723 */ "G_FFLOOR\000"
1545 /* 3732 */ "G_SAVGFLOOR\000"
1546 /* 3744 */ "G_UAVGFLOOR\000"
1547 /* 3756 */ "G_EXTRACT_SUBVECTOR\000"
1548 /* 3776 */ "G_INSERT_SUBVECTOR\000"
1549 /* 3795 */ "G_BUILD_VECTOR\000"
1550 /* 3810 */ "G_SHUFFLE_VECTOR\000"
1551 /* 3827 */ "G_STEP_VECTOR\000"
1552 /* 3841 */ "G_SPLAT_VECTOR\000"
1553 /* 3856 */ "G_VECREDUCE_XOR\000"
1554 /* 3872 */ "G_XOR\000"
1555 /* 3878 */ "G_ATOMICRMW_XOR\000"
1556 /* 3894 */ "G_VECREDUCE_OR\000"
1557 /* 3909 */ "G_OR\000"
1558 /* 3914 */ "G_ATOMICRMW_OR\000"
1559 /* 3929 */ "G_ROTR\000"
1560 /* 3936 */ "G_INTTOPTR\000"
1561 /* 3947 */ "G_FABS\000"
1562 /* 3954 */ "G_ABS\000"
1563 /* 3960 */ "G_ABDS\000"
1564 /* 3967 */ "G_UNMERGE_VALUES\000"
1565 /* 3984 */ "G_MERGE_VALUES\000"
1566 /* 3999 */ "G_CTLS\000"
1567 /* 4006 */ "G_FACOS\000"
1568 /* 4014 */ "G_FCOS\000"
1569 /* 4021 */ "G_FSINCOS\000"
1570 /* 4031 */ "G_CONCAT_VECTORS\000"
1571 /* 4048 */ "COPY_TO_REGCLASS\000"
1572 /* 4065 */ "G_IS_FPCLASS\000"
1573 /* 4078 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1574 /* 4108 */ "G_VECTOR_COMPRESS\000"
1575 /* 4126 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1576 /* 4153 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1577 /* 4191 */ "G_TRUNC_SSAT_S\000"
1578 /* 4206 */ "G_SSUBSAT\000"
1579 /* 4216 */ "G_USUBSAT\000"
1580 /* 4226 */ "G_SADDSAT\000"
1581 /* 4236 */ "G_UADDSAT\000"
1582 /* 4246 */ "G_SSHLSAT\000"
1583 /* 4256 */ "G_USHLSAT\000"
1584 /* 4266 */ "G_SMULFIXSAT\000"
1585 /* 4279 */ "G_UMULFIXSAT\000"
1586 /* 4292 */ "G_SDIVFIXSAT\000"
1587 /* 4305 */ "G_UDIVFIXSAT\000"
1588 /* 4318 */ "G_ATOMICRMW_USUB_SAT\000"
1589 /* 4339 */ "G_FPTOSI_SAT\000"
1590 /* 4352 */ "G_FPTOUI_SAT\000"
1591 /* 4365 */ "G_EXTRACT\000"
1592 /* 4375 */ "G_SELECT\000"
1593 /* 4384 */ "G_BRINDIRECT\000"
1594 /* 4397 */ "PATCHABLE_RET\000"
1595 /* 4411 */ "G_MEMSET\000"
1596 /* 4420 */ "CORE_SHIFT\000"
1597 /* 4431 */ "PATCHABLE_FUNCTION_EXIT\000"
1598 /* 4455 */ "G_BRJT\000"
1599 /* 4462 */ "G_EXTRACT_VECTOR_ELT\000"
1600 /* 4483 */ "G_INSERT_VECTOR_ELT\000"
1601 /* 4503 */ "G_FCONSTANT\000"
1602 /* 4515 */ "G_CONSTANT\000"
1603 /* 4526 */ "G_INTRINSIC_CONVERGENT\000"
1604 /* 4549 */ "STATEPOINT\000"
1605 /* 4560 */ "PATCHPOINT\000"
1606 /* 4571 */ "G_PTRTOINT\000"
1607 /* 4582 */ "G_FRINT\000"
1608 /* 4590 */ "G_INTRINSIC_LLRINT\000"
1609 /* 4609 */ "G_INTRINSIC_LRINT\000"
1610 /* 4627 */ "G_FNEARBYINT\000"
1611 /* 4640 */ "G_VASTART\000"
1612 /* 4650 */ "LIFETIME_START\000"
1613 /* 4665 */ "G_INVOKE_REGION_START\000"
1614 /* 4687 */ "G_INSERT\000"
1615 /* 4696 */ "G_FSQRT\000"
1616 /* 4704 */ "G_STRICT_FSQRT\000"
1617 /* 4719 */ "G_BITCAST\000"
1618 /* 4729 */ "G_ADDRSPACE_CAST\000"
1619 /* 4746 */ "ADDR_SPACE_CAST\000"
1620 /* 4762 */ "DBG_VALUE_LIST\000"
1621 /* 4777 */ "CORE_ST\000"
1622 /* 4785 */ "G_FPEXT\000"
1623 /* 4793 */ "G_SEXT\000"
1624 /* 4800 */ "G_ASSERT_SEXT\000"
1625 /* 4814 */ "G_ANYEXT\000"
1626 /* 4823 */ "G_ZEXT\000"
1627 /* 4830 */ "G_ASSERT_ZEXT\000"
1628 /* 4844 */ "G_ABDU\000"
1629 /* 4851 */ "G_TRUNC_SSAT_U\000"
1630 /* 4866 */ "G_TRUNC_USAT_U\000"
1631 /* 4881 */ "G_FDIV\000"
1632 /* 4888 */ "G_STRICT_FDIV\000"
1633 /* 4902 */ "G_SDIV\000"
1634 /* 4909 */ "G_UDIV\000"
1635 /* 4916 */ "G_GET_FPENV\000"
1636 /* 4928 */ "G_RESET_FPENV\000"
1637 /* 4942 */ "G_SET_FPENV\000"
1638 /* 4954 */ "XADDW\000"
1639 /* 4960 */ "LDW\000"
1640 /* 4964 */ "G_FPOW\000"
1641 /* 4971 */ "STW\000"
1642 /* 4975 */ "LD_IND_W\000"
1643 /* 4984 */ "LD_ABS_W\000"
1644 /* 4993 */ "G_VECREDUCE_FMAX\000"
1645 /* 5010 */ "G_ATOMICRMW_FMAX\000"
1646 /* 5027 */ "G_VECREDUCE_SMAX\000"
1647 /* 5044 */ "G_SMAX\000"
1648 /* 5051 */ "G_VECREDUCE_UMAX\000"
1649 /* 5068 */ "G_UMAX\000"
1650 /* 5075 */ "G_ATOMICRMW_UMAX\000"
1651 /* 5092 */ "G_ATOMICRMW_MAX\000"
1652 /* 5108 */ "G_FRAME_INDEX\000"
1653 /* 5122 */ "G_SBFX\000"
1654 /* 5129 */ "G_UBFX\000"
1655 /* 5136 */ "G_SMULFIX\000"
1656 /* 5146 */ "G_UMULFIX\000"
1657 /* 5156 */ "G_SDIVFIX\000"
1658 /* 5166 */ "G_UDIVFIX\000"
1659 /* 5176 */ "JX\000"
1660 /* 5179 */ "JALX\000"
1661 /* 5184 */ "LDBSX\000"
1662 /* 5190 */ "LDHSX\000"
1663 /* 5196 */ "LDWSX\000"
1664 /* 5202 */ "G_MEMCPY\000"
1665 /* 5211 */ "COPY\000"
1666 /* 5216 */ "CONVERGENCECTRL_ENTRY\000"
1667 /* 5238 */ "G_CTLZ\000"
1668 /* 5245 */ "G_CTTZ\000"
1669 /* 5252 */ "Select_Ri\000"
1670 /* 5262 */ "SRA_ri\000"
1671 /* 5269 */ "SUB_ri\000"
1672 /* 5276 */ "ADD_ri\000"
1673 /* 5283 */ "AND_ri\000"
1674 /* 5290 */ "SMOD_ri\000"
1675 /* 5298 */ "JSGE_ri\000"
1676 /* 5306 */ "JUGE_ri\000"
1677 /* 5314 */ "JSLE_ri\000"
1678 /* 5322 */ "JULE_ri\000"
1679 /* 5330 */ "JNE_ri\000"
1680 /* 5337 */ "FI_ri\000"
1681 /* 5343 */ "SLL_ri\000"
1682 /* 5350 */ "SRL_ri\000"
1683 /* 5357 */ "MUL_ri\000"
1684 /* 5364 */ "JEQ_ri\000"
1685 /* 5371 */ "XOR_ri\000"
1686 /* 5378 */ "JSET_ri\000"
1687 /* 5386 */ "JSGT_ri\000"
1688 /* 5394 */ "JUGT_ri\000"
1689 /* 5402 */ "JSLT_ri\000"
1690 /* 5410 */ "JULT_ri\000"
1691 /* 5418 */ "SDIV_ri\000"
1692 /* 5426 */ "MOV_ri\000"
1693 /* 5433 */ "STB_imm\000"
1694 /* 5441 */ "STD_imm\000"
1695 /* 5449 */ "STH_imm\000"
1696 /* 5457 */ "STW_imm\000"
1697 /* 5465 */ "LD_pseudo\000"
1698 /* 5475 */ "SRA_rr\000"
1699 /* 5482 */ "SUB_rr\000"
1700 /* 5489 */ "ADD_rr\000"
1701 /* 5496 */ "AND_rr\000"
1702 /* 5503 */ "SMOD_rr\000"
1703 /* 5511 */ "JSGE_rr\000"
1704 /* 5519 */ "JUGE_rr\000"
1705 /* 5527 */ "JSLE_rr\000"
1706 /* 5535 */ "JULE_rr\000"
1707 /* 5543 */ "JNE_rr\000"
1708 /* 5550 */ "SLL_rr\000"
1709 /* 5557 */ "SRL_rr\000"
1710 /* 5564 */ "MUL_rr\000"
1711 /* 5571 */ "JEQ_rr\000"
1712 /* 5578 */ "XOR_rr\000"
1713 /* 5585 */ "JSET_rr\000"
1714 /* 5593 */ "JSGT_rr\000"
1715 /* 5601 */ "JUGT_rr\000"
1716 /* 5609 */ "JSLT_rr\000"
1717 /* 5617 */ "JULT_rr\000"
1718 /* 5625 */ "SDIV_rr\000"
1719 /* 5633 */ "MOV_rr\000"
1720 /* 5640 */ "Select\000"
1721};
1722#ifdef __GNUC__
1723#pragma GCC diagnostic pop
1724#endif
1725
1726extern const unsigned BPFInstrNameIndices[] = {
1727 2295U, 2717U, 3521U, 3123U, 2372U, 2353U, 2381U, 2548U,
1728 2062U, 2077U, 2028U, 2015U, 2104U, 4048U, 1855U, 4762U,
1729 2041U, 2291U, 2362U, 1625U, 5211U, 2325U, 1747U, 4650U,
1730 1423U, 1576U, 1613U, 3234U, 2536U, 4560U, 1536U, 3449U,
1731 2197U, 4549U, 1781U, 3422U, 3409U, 3582U, 4397U, 4431U,
1732 2468U, 2515U, 2488U, 2398U, 1846U, 3547U, 3188U, 1770U,
1733 5216U, 3700U, 3380U, 1903U, 4800U, 4830U, 2966U, 1297U,
1734 990U, 2656U, 4902U, 4909U, 2683U, 2690U, 2697U, 2707U,
1735 1401U, 3909U, 3872U, 3960U, 4844U, 3744U, 2457U, 3732U,
1736 2446U, 2026U, 2293U, 5108U, 1865U, 1880U, 2553U, 4365U,
1737 3967U, 4687U, 3984U, 3795U, 1078U, 4031U, 4571U, 3936U,
1738 4719U, 1946U, 3558U, 1510U, 1052U, 1492U, 4609U, 4590U,
1739 2944U, 3607U, 3626U, 1198U, 1142U, 1172U, 1183U, 1123U,
1740 1153U, 1825U, 1809U, 4078U, 2118U, 2135U, 1313U, 996U,
1741 1407U, 1368U, 3914U, 3878U, 5092U, 3092U, 5075U, 3075U,
1742 1264U, 973U, 5010U, 3010U, 2812U, 2759U, 2885U, 2847U,
1743 3296U, 3274U, 1451U, 4318U, 1605U, 2214U, 1442U, 4384U,
1744 4665U, 1030U, 4126U, 4526U, 4153U, 4814U, 1070U, 4191U,
1745 4851U, 4866U, 4515U, 4503U, 4640U, 2189U, 4793U, 2091U,
1746 4823U, 2432U, 3693U, 3679U, 2425U, 3686U, 3929U, 2574U,
1747 3351U, 3344U, 3358U, 3365U, 4375U, 3180U, 1646U, 3164U,
1748 1597U, 3172U, 1638U, 3156U, 1589U, 3218U, 3210U, 2237U,
1749 2229U, 4236U, 4226U, 4216U, 4206U, 4256U, 4246U, 5136U,
1750 5146U, 4266U, 4279U, 5156U, 5166U, 4292U, 4305U, 1222U,
1751 952U, 2598U, 925U, 1116U, 4881U, 2662U, 1971U, 4964U,
1752 2317U, 3493U, 756U, 9U, 2182U, 739U, 0U, 3468U,
1753 3500U, 2055U, 4785U, 1042U, 2299U, 2308U, 3326U, 3335U,
1754 4339U, 4352U, 3947U, 2981U, 4065U, 1955U, 2909U, 2919U,
1755 1695U, 1710U, 2748U, 2801U, 2833U, 2871U, 4916U, 4942U,
1756 4928U, 1654U, 1682U, 1667U, 2152U, 2167U, 1303U, 2339U,
1757 3044U, 5044U, 3068U, 5068U, 3954U, 1483U, 1473U, 3516U,
1758 4455U, 1725U, 3776U, 3756U, 4483U, 4462U, 3810U, 3841U,
1759 3827U, 4108U, 5245U, 1997U, 5238U, 1979U, 3999U, 3401U,
1760 3318U, 1833U, 2438U, 4014U, 3116U, 4021U, 2937U, 4006U,
1761 3108U, 2929U, 747U, 2261U, 2253U, 2245U, 4696U, 3723U,
1762 4582U, 4627U, 4729U, 3534U, 1734U, 1099U, 1924U, 1794U,
1763 1250U, 959U, 2626U, 4888U, 2669U, 931U, 4704U, 3477U,
1764 3646U, 3662U, 5202U, 1754U, 1936U, 4411U, 3226U, 3267U,
1765 3243U, 3255U, 1229U, 2605U, 1205U, 2581U, 4993U, 2993U,
1766 2780U, 2727U, 1281U, 2640U, 1385U, 3894U, 3856U, 5027U,
1767 3027U, 5051U, 3051U, 5122U, 5129U, 3139U, 3434U, 5337U,
1768 784U, 5204U, 5640U, 729U, 826U, 222U, 5252U, 242U,
1769 810U, 206U, 4746U, 5276U, 275U, 5489U, 506U, 5283U,
1770 285U, 5496U, 516U, 855U, 40U, 774U, 865U, 89U,
1771 792U, 1359U, 164U, 30U, 764U, 4420U, 4777U, 5419U,
1772 466U, 5626U, 697U, 2349U, 5179U, 1436U, 5364U, 390U,
1773 5571U, 621U, 3372U, 2569U, 5330U, 350U, 5543U, 581U,
1774 5378U, 410U, 5585U, 641U, 5298U, 306U, 5511U, 537U,
1775 5386U, 421U, 5593U, 652U, 5314U, 328U, 5527U, 559U,
1776 5402U, 443U, 5609U, 674U, 5306U, 317U, 5519U, 548U,
1777 5394U, 432U, 5601U, 663U, 5322U, 339U, 5535U, 570U,
1778 5410U, 454U, 5617U, 685U, 5176U, 944U, 18U, 97U,
1779 5184U, 1342U, 3509U, 2225U, 50U, 106U, 5190U, 4960U,
1780 141U, 115U, 5196U, 1021U, 2282U, 4984U, 1012U, 2273U,
1781 4975U, 846U, 5465U, 860U, 45U, 779U, 5291U, 296U,
1782 5504U, 527U, 888U, 717U, 873U, 900U, 914U, 800U,
1783 5426U, 476U, 5633U, 707U, 5357U, 380U, 5564U, 611U,
1784 235U, 839U, 3376U, 5372U, 401U, 5579U, 632U, 4407U,
1785 5418U, 465U, 5625U, 696U, 5343U, 360U, 5550U, 591U,
1786 5290U, 295U, 5503U, 526U, 5262U, 255U, 5475U, 486U,
1787 5350U, 370U, 5557U, 601U, 948U, 24U, 62U, 5433U,
1788 1572U, 2418U, 5441U, 2269U, 56U, 71U, 5449U, 4971U,
1789 200U, 80U, 5457U, 5269U, 265U, 5482U, 496U, 1336U,
1790 4954U, 133U, 1353U, 156U, 1362U, 167U, 1329U, 124U,
1791 1346U, 147U, 1553U, 175U, 1559U, 183U, 1561U, 185U,
1792 5371U, 400U, 5578U, 631U, 1566U, 192U,
1793};
1794
1795static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
1796 II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 526, nullptr, 0);
1797}
1798
1799
1800} // namespace llvm
1801
1802#endif // GET_INSTRINFO_MC_DESC
1803
1804#ifdef GET_INSTRINFO_HEADER
1805#undef GET_INSTRINFO_HEADER
1806
1807namespace llvm {
1808
1809struct BPFGenInstrInfo : public TargetInstrInfo {
1810 explicit BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1811 ~BPFGenInstrInfo() override = default;
1812};
1813
1814} // namespace llvm
1815
1816namespace llvm::BPF {
1817
1818
1819} // namespace llvm::BPF
1820
1821#endif // GET_INSTRINFO_HEADER
1822
1823#ifdef GET_INSTRINFO_HELPER_DECLS
1824#undef GET_INSTRINFO_HELPER_DECLS
1825
1826
1827#endif // GET_INSTRINFO_HELPER_DECLS
1828
1829#ifdef GET_INSTRINFO_HELPERS
1830#undef GET_INSTRINFO_HELPERS
1831
1832
1833#endif // GET_INSTRINFO_HELPERS
1834
1835#ifdef GET_INSTRINFO_CTOR_DTOR
1836#undef GET_INSTRINFO_CTOR_DTOR
1837
1838namespace llvm {
1839
1840extern const BPFInstrTable BPFDescs;
1841extern const unsigned BPFInstrNameIndices[];
1842extern const char BPFInstrNameData[];
1843BPFGenInstrInfo::BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1844 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1845 InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 526);
1846}
1847
1848} // namespace llvm
1849
1850#endif // GET_INSTRINFO_CTOR_DTOR
1851
1852#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1853#undef GET_INSTRINFO_MC_HELPER_DECLS
1854
1855namespace llvm {
1856
1857class MCInst;
1858class FeatureBitset;
1859
1860namespace BPF_MC {
1861
1862void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1863
1864} // namespace BPF_MC
1865
1866} // namespace llvm
1867
1868#endif // GET_INSTRINFO_MC_HELPER_DECLS
1869
1870#ifdef GET_INSTRINFO_MC_HELPERS
1871#undef GET_INSTRINFO_MC_HELPERS
1872
1873namespace llvm::BPF_MC {
1874
1875
1876} // namespace llvm::BPF_MC
1877
1878#endif // GET_INSTRINFO_MC_HELPERS
1879
1880#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1881 defined(GET_AVAILABLE_OPCODE_CHECKER)
1882#define GET_COMPUTE_FEATURES
1883#endif
1884#ifdef GET_COMPUTE_FEATURES
1885#undef GET_COMPUTE_FEATURES
1886
1887namespace llvm::BPF_MC {
1888
1889// Bits for subtarget features that participate in instruction matching.
1890enum SubtargetFeatureBits : uint8_t {
1891};
1892
1893inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1894 FeatureBitset Features;
1895 return Features;
1896}
1897
1898inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1899 enum : uint8_t {
1900 CEFBS_None,
1901 };
1902
1903 static constexpr FeatureBitset FeatureBitsets[] = {
1904 {}, // CEFBS_None
1905 };
1906 static constexpr uint8_t RequiredFeaturesRefs[] = {
1907 CEFBS_None, // PHI
1908 CEFBS_None, // INLINEASM
1909 CEFBS_None, // INLINEASM_BR
1910 CEFBS_None, // CFI_INSTRUCTION
1911 CEFBS_None, // EH_LABEL
1912 CEFBS_None, // GC_LABEL
1913 CEFBS_None, // ANNOTATION_LABEL
1914 CEFBS_None, // KILL
1915 CEFBS_None, // EXTRACT_SUBREG
1916 CEFBS_None, // INSERT_SUBREG
1917 CEFBS_None, // IMPLICIT_DEF
1918 CEFBS_None, // INIT_UNDEF
1919 CEFBS_None, // SUBREG_TO_REG
1920 CEFBS_None, // COPY_TO_REGCLASS
1921 CEFBS_None, // DBG_VALUE
1922 CEFBS_None, // DBG_VALUE_LIST
1923 CEFBS_None, // DBG_INSTR_REF
1924 CEFBS_None, // DBG_PHI
1925 CEFBS_None, // DBG_LABEL
1926 CEFBS_None, // REG_SEQUENCE
1927 CEFBS_None, // COPY
1928 CEFBS_None, // COPY_LANEMASK
1929 CEFBS_None, // BUNDLE
1930 CEFBS_None, // LIFETIME_START
1931 CEFBS_None, // LIFETIME_END
1932 CEFBS_None, // PSEUDO_PROBE
1933 CEFBS_None, // ARITH_FENCE
1934 CEFBS_None, // STACKMAP
1935 CEFBS_None, // FENTRY_CALL
1936 CEFBS_None, // PATCHPOINT
1937 CEFBS_None, // LOAD_STACK_GUARD
1938 CEFBS_None, // PREALLOCATED_SETUP
1939 CEFBS_None, // PREALLOCATED_ARG
1940 CEFBS_None, // STATEPOINT
1941 CEFBS_None, // LOCAL_ESCAPE
1942 CEFBS_None, // FAULTING_OP
1943 CEFBS_None, // PATCHABLE_OP
1944 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1945 CEFBS_None, // PATCHABLE_RET
1946 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1947 CEFBS_None, // PATCHABLE_TAIL_CALL
1948 CEFBS_None, // PATCHABLE_EVENT_CALL
1949 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1950 CEFBS_None, // ICALL_BRANCH_FUNNEL
1951 CEFBS_None, // FAKE_USE
1952 CEFBS_None, // MEMBARRIER
1953 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1954 CEFBS_None, // RELOC_NONE
1955 CEFBS_None, // CONVERGENCECTRL_ENTRY
1956 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1957 CEFBS_None, // CONVERGENCECTRL_LOOP
1958 CEFBS_None, // CONVERGENCECTRL_GLUE
1959 CEFBS_None, // G_ASSERT_SEXT
1960 CEFBS_None, // G_ASSERT_ZEXT
1961 CEFBS_None, // G_ASSERT_ALIGN
1962 CEFBS_None, // G_ADD
1963 CEFBS_None, // G_SUB
1964 CEFBS_None, // G_MUL
1965 CEFBS_None, // G_SDIV
1966 CEFBS_None, // G_UDIV
1967 CEFBS_None, // G_SREM
1968 CEFBS_None, // G_UREM
1969 CEFBS_None, // G_SDIVREM
1970 CEFBS_None, // G_UDIVREM
1971 CEFBS_None, // G_AND
1972 CEFBS_None, // G_OR
1973 CEFBS_None, // G_XOR
1974 CEFBS_None, // G_ABDS
1975 CEFBS_None, // G_ABDU
1976 CEFBS_None, // G_UAVGFLOOR
1977 CEFBS_None, // G_UAVGCEIL
1978 CEFBS_None, // G_SAVGFLOOR
1979 CEFBS_None, // G_SAVGCEIL
1980 CEFBS_None, // G_IMPLICIT_DEF
1981 CEFBS_None, // G_PHI
1982 CEFBS_None, // G_FRAME_INDEX
1983 CEFBS_None, // G_GLOBAL_VALUE
1984 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
1985 CEFBS_None, // G_CONSTANT_POOL
1986 CEFBS_None, // G_EXTRACT
1987 CEFBS_None, // G_UNMERGE_VALUES
1988 CEFBS_None, // G_INSERT
1989 CEFBS_None, // G_MERGE_VALUES
1990 CEFBS_None, // G_BUILD_VECTOR
1991 CEFBS_None, // G_BUILD_VECTOR_TRUNC
1992 CEFBS_None, // G_CONCAT_VECTORS
1993 CEFBS_None, // G_PTRTOINT
1994 CEFBS_None, // G_INTTOPTR
1995 CEFBS_None, // G_BITCAST
1996 CEFBS_None, // G_FREEZE
1997 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
1998 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
1999 CEFBS_None, // G_INTRINSIC_TRUNC
2000 CEFBS_None, // G_INTRINSIC_ROUND
2001 CEFBS_None, // G_INTRINSIC_LRINT
2002 CEFBS_None, // G_INTRINSIC_LLRINT
2003 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2004 CEFBS_None, // G_READCYCLECOUNTER
2005 CEFBS_None, // G_READSTEADYCOUNTER
2006 CEFBS_None, // G_LOAD
2007 CEFBS_None, // G_SEXTLOAD
2008 CEFBS_None, // G_ZEXTLOAD
2009 CEFBS_None, // G_INDEXED_LOAD
2010 CEFBS_None, // G_INDEXED_SEXTLOAD
2011 CEFBS_None, // G_INDEXED_ZEXTLOAD
2012 CEFBS_None, // G_STORE
2013 CEFBS_None, // G_INDEXED_STORE
2014 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2015 CEFBS_None, // G_ATOMIC_CMPXCHG
2016 CEFBS_None, // G_ATOMICRMW_XCHG
2017 CEFBS_None, // G_ATOMICRMW_ADD
2018 CEFBS_None, // G_ATOMICRMW_SUB
2019 CEFBS_None, // G_ATOMICRMW_AND
2020 CEFBS_None, // G_ATOMICRMW_NAND
2021 CEFBS_None, // G_ATOMICRMW_OR
2022 CEFBS_None, // G_ATOMICRMW_XOR
2023 CEFBS_None, // G_ATOMICRMW_MAX
2024 CEFBS_None, // G_ATOMICRMW_MIN
2025 CEFBS_None, // G_ATOMICRMW_UMAX
2026 CEFBS_None, // G_ATOMICRMW_UMIN
2027 CEFBS_None, // G_ATOMICRMW_FADD
2028 CEFBS_None, // G_ATOMICRMW_FSUB
2029 CEFBS_None, // G_ATOMICRMW_FMAX
2030 CEFBS_None, // G_ATOMICRMW_FMIN
2031 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2032 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2033 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2034 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2035 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2036 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2037 CEFBS_None, // G_ATOMICRMW_USUB_COND
2038 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2039 CEFBS_None, // G_FENCE
2040 CEFBS_None, // G_PREFETCH
2041 CEFBS_None, // G_BRCOND
2042 CEFBS_None, // G_BRINDIRECT
2043 CEFBS_None, // G_INVOKE_REGION_START
2044 CEFBS_None, // G_INTRINSIC
2045 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2046 CEFBS_None, // G_INTRINSIC_CONVERGENT
2047 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2048 CEFBS_None, // G_ANYEXT
2049 CEFBS_None, // G_TRUNC
2050 CEFBS_None, // G_TRUNC_SSAT_S
2051 CEFBS_None, // G_TRUNC_SSAT_U
2052 CEFBS_None, // G_TRUNC_USAT_U
2053 CEFBS_None, // G_CONSTANT
2054 CEFBS_None, // G_FCONSTANT
2055 CEFBS_None, // G_VASTART
2056 CEFBS_None, // G_VAARG
2057 CEFBS_None, // G_SEXT
2058 CEFBS_None, // G_SEXT_INREG
2059 CEFBS_None, // G_ZEXT
2060 CEFBS_None, // G_SHL
2061 CEFBS_None, // G_LSHR
2062 CEFBS_None, // G_ASHR
2063 CEFBS_None, // G_FSHL
2064 CEFBS_None, // G_FSHR
2065 CEFBS_None, // G_ROTR
2066 CEFBS_None, // G_ROTL
2067 CEFBS_None, // G_ICMP
2068 CEFBS_None, // G_FCMP
2069 CEFBS_None, // G_SCMP
2070 CEFBS_None, // G_UCMP
2071 CEFBS_None, // G_SELECT
2072 CEFBS_None, // G_UADDO
2073 CEFBS_None, // G_UADDE
2074 CEFBS_None, // G_USUBO
2075 CEFBS_None, // G_USUBE
2076 CEFBS_None, // G_SADDO
2077 CEFBS_None, // G_SADDE
2078 CEFBS_None, // G_SSUBO
2079 CEFBS_None, // G_SSUBE
2080 CEFBS_None, // G_UMULO
2081 CEFBS_None, // G_SMULO
2082 CEFBS_None, // G_UMULH
2083 CEFBS_None, // G_SMULH
2084 CEFBS_None, // G_UADDSAT
2085 CEFBS_None, // G_SADDSAT
2086 CEFBS_None, // G_USUBSAT
2087 CEFBS_None, // G_SSUBSAT
2088 CEFBS_None, // G_USHLSAT
2089 CEFBS_None, // G_SSHLSAT
2090 CEFBS_None, // G_SMULFIX
2091 CEFBS_None, // G_UMULFIX
2092 CEFBS_None, // G_SMULFIXSAT
2093 CEFBS_None, // G_UMULFIXSAT
2094 CEFBS_None, // G_SDIVFIX
2095 CEFBS_None, // G_UDIVFIX
2096 CEFBS_None, // G_SDIVFIXSAT
2097 CEFBS_None, // G_UDIVFIXSAT
2098 CEFBS_None, // G_FADD
2099 CEFBS_None, // G_FSUB
2100 CEFBS_None, // G_FMUL
2101 CEFBS_None, // G_FMA
2102 CEFBS_None, // G_FMAD
2103 CEFBS_None, // G_FDIV
2104 CEFBS_None, // G_FREM
2105 CEFBS_None, // G_FMODF
2106 CEFBS_None, // G_FPOW
2107 CEFBS_None, // G_FPOWI
2108 CEFBS_None, // G_FEXP
2109 CEFBS_None, // G_FEXP2
2110 CEFBS_None, // G_FEXP10
2111 CEFBS_None, // G_FLOG
2112 CEFBS_None, // G_FLOG2
2113 CEFBS_None, // G_FLOG10
2114 CEFBS_None, // G_FLDEXP
2115 CEFBS_None, // G_FFREXP
2116 CEFBS_None, // G_FNEG
2117 CEFBS_None, // G_FPEXT
2118 CEFBS_None, // G_FPTRUNC
2119 CEFBS_None, // G_FPTOSI
2120 CEFBS_None, // G_FPTOUI
2121 CEFBS_None, // G_SITOFP
2122 CEFBS_None, // G_UITOFP
2123 CEFBS_None, // G_FPTOSI_SAT
2124 CEFBS_None, // G_FPTOUI_SAT
2125 CEFBS_None, // G_FABS
2126 CEFBS_None, // G_FCOPYSIGN
2127 CEFBS_None, // G_IS_FPCLASS
2128 CEFBS_None, // G_FCANONICALIZE
2129 CEFBS_None, // G_FMINNUM
2130 CEFBS_None, // G_FMAXNUM
2131 CEFBS_None, // G_FMINNUM_IEEE
2132 CEFBS_None, // G_FMAXNUM_IEEE
2133 CEFBS_None, // G_FMINIMUM
2134 CEFBS_None, // G_FMAXIMUM
2135 CEFBS_None, // G_FMINIMUMNUM
2136 CEFBS_None, // G_FMAXIMUMNUM
2137 CEFBS_None, // G_GET_FPENV
2138 CEFBS_None, // G_SET_FPENV
2139 CEFBS_None, // G_RESET_FPENV
2140 CEFBS_None, // G_GET_FPMODE
2141 CEFBS_None, // G_SET_FPMODE
2142 CEFBS_None, // G_RESET_FPMODE
2143 CEFBS_None, // G_GET_ROUNDING
2144 CEFBS_None, // G_SET_ROUNDING
2145 CEFBS_None, // G_PTR_ADD
2146 CEFBS_None, // G_PTRMASK
2147 CEFBS_None, // G_SMIN
2148 CEFBS_None, // G_SMAX
2149 CEFBS_None, // G_UMIN
2150 CEFBS_None, // G_UMAX
2151 CEFBS_None, // G_ABS
2152 CEFBS_None, // G_LROUND
2153 CEFBS_None, // G_LLROUND
2154 CEFBS_None, // G_BR
2155 CEFBS_None, // G_BRJT
2156 CEFBS_None, // G_VSCALE
2157 CEFBS_None, // G_INSERT_SUBVECTOR
2158 CEFBS_None, // G_EXTRACT_SUBVECTOR
2159 CEFBS_None, // G_INSERT_VECTOR_ELT
2160 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2161 CEFBS_None, // G_SHUFFLE_VECTOR
2162 CEFBS_None, // G_SPLAT_VECTOR
2163 CEFBS_None, // G_STEP_VECTOR
2164 CEFBS_None, // G_VECTOR_COMPRESS
2165 CEFBS_None, // G_CTTZ
2166 CEFBS_None, // G_CTTZ_ZERO_UNDEF
2167 CEFBS_None, // G_CTLZ
2168 CEFBS_None, // G_CTLZ_ZERO_UNDEF
2169 CEFBS_None, // G_CTLS
2170 CEFBS_None, // G_CTPOP
2171 CEFBS_None, // G_BSWAP
2172 CEFBS_None, // G_BITREVERSE
2173 CEFBS_None, // G_FCEIL
2174 CEFBS_None, // G_FCOS
2175 CEFBS_None, // G_FSIN
2176 CEFBS_None, // G_FSINCOS
2177 CEFBS_None, // G_FTAN
2178 CEFBS_None, // G_FACOS
2179 CEFBS_None, // G_FASIN
2180 CEFBS_None, // G_FATAN
2181 CEFBS_None, // G_FATAN2
2182 CEFBS_None, // G_FCOSH
2183 CEFBS_None, // G_FSINH
2184 CEFBS_None, // G_FTANH
2185 CEFBS_None, // G_FSQRT
2186 CEFBS_None, // G_FFLOOR
2187 CEFBS_None, // G_FRINT
2188 CEFBS_None, // G_FNEARBYINT
2189 CEFBS_None, // G_ADDRSPACE_CAST
2190 CEFBS_None, // G_BLOCK_ADDR
2191 CEFBS_None, // G_JUMP_TABLE
2192 CEFBS_None, // G_DYN_STACKALLOC
2193 CEFBS_None, // G_STACKSAVE
2194 CEFBS_None, // G_STACKRESTORE
2195 CEFBS_None, // G_STRICT_FADD
2196 CEFBS_None, // G_STRICT_FSUB
2197 CEFBS_None, // G_STRICT_FMUL
2198 CEFBS_None, // G_STRICT_FDIV
2199 CEFBS_None, // G_STRICT_FREM
2200 CEFBS_None, // G_STRICT_FMA
2201 CEFBS_None, // G_STRICT_FSQRT
2202 CEFBS_None, // G_STRICT_FLDEXP
2203 CEFBS_None, // G_READ_REGISTER
2204 CEFBS_None, // G_WRITE_REGISTER
2205 CEFBS_None, // G_MEMCPY
2206 CEFBS_None, // G_MEMCPY_INLINE
2207 CEFBS_None, // G_MEMMOVE
2208 CEFBS_None, // G_MEMSET
2209 CEFBS_None, // G_BZERO
2210 CEFBS_None, // G_TRAP
2211 CEFBS_None, // G_DEBUGTRAP
2212 CEFBS_None, // G_UBSANTRAP
2213 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2214 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2215 CEFBS_None, // G_VECREDUCE_FADD
2216 CEFBS_None, // G_VECREDUCE_FMUL
2217 CEFBS_None, // G_VECREDUCE_FMAX
2218 CEFBS_None, // G_VECREDUCE_FMIN
2219 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2220 CEFBS_None, // G_VECREDUCE_FMINIMUM
2221 CEFBS_None, // G_VECREDUCE_ADD
2222 CEFBS_None, // G_VECREDUCE_MUL
2223 CEFBS_None, // G_VECREDUCE_AND
2224 CEFBS_None, // G_VECREDUCE_OR
2225 CEFBS_None, // G_VECREDUCE_XOR
2226 CEFBS_None, // G_VECREDUCE_SMAX
2227 CEFBS_None, // G_VECREDUCE_SMIN
2228 CEFBS_None, // G_VECREDUCE_UMAX
2229 CEFBS_None, // G_VECREDUCE_UMIN
2230 CEFBS_None, // G_SBFX
2231 CEFBS_None, // G_UBFX
2232 CEFBS_None, // ADJCALLSTACKDOWN
2233 CEFBS_None, // ADJCALLSTACKUP
2234 CEFBS_None, // FI_ri
2235 CEFBS_None, // LDIMM64
2236 CEFBS_None, // MEMCPY
2237 CEFBS_None, // Select
2238 CEFBS_None, // Select_32
2239 CEFBS_None, // Select_32_64
2240 CEFBS_None, // Select_64_32
2241 CEFBS_None, // Select_Ri
2242 CEFBS_None, // Select_Ri_32
2243 CEFBS_None, // Select_Ri_32_64
2244 CEFBS_None, // Select_Ri_64_32
2245 CEFBS_None, // ADDR_SPACE_CAST
2246 CEFBS_None, // ADD_ri
2247 CEFBS_None, // ADD_ri_32
2248 CEFBS_None, // ADD_rr
2249 CEFBS_None, // ADD_rr_32
2250 CEFBS_None, // AND_ri
2251 CEFBS_None, // AND_ri_32
2252 CEFBS_None, // AND_rr
2253 CEFBS_None, // AND_rr_32
2254 CEFBS_None, // BE16
2255 CEFBS_None, // BE32
2256 CEFBS_None, // BE64
2257 CEFBS_None, // BSWAP16
2258 CEFBS_None, // BSWAP32
2259 CEFBS_None, // BSWAP64
2260 CEFBS_None, // CMPXCHGD
2261 CEFBS_None, // CMPXCHGW32
2262 CEFBS_None, // CORE_LD32
2263 CEFBS_None, // CORE_LD64
2264 CEFBS_None, // CORE_SHIFT
2265 CEFBS_None, // CORE_ST
2266 CEFBS_None, // DIV_ri
2267 CEFBS_None, // DIV_ri_32
2268 CEFBS_None, // DIV_rr
2269 CEFBS_None, // DIV_rr_32
2270 CEFBS_None, // JAL
2271 CEFBS_None, // JALX
2272 CEFBS_None, // JCOND
2273 CEFBS_None, // JEQ_ri
2274 CEFBS_None, // JEQ_ri_32
2275 CEFBS_None, // JEQ_rr
2276 CEFBS_None, // JEQ_rr_32
2277 CEFBS_None, // JMP
2278 CEFBS_None, // JMPL
2279 CEFBS_None, // JNE_ri
2280 CEFBS_None, // JNE_ri_32
2281 CEFBS_None, // JNE_rr
2282 CEFBS_None, // JNE_rr_32
2283 CEFBS_None, // JSET_ri
2284 CEFBS_None, // JSET_ri_32
2285 CEFBS_None, // JSET_rr
2286 CEFBS_None, // JSET_rr_32
2287 CEFBS_None, // JSGE_ri
2288 CEFBS_None, // JSGE_ri_32
2289 CEFBS_None, // JSGE_rr
2290 CEFBS_None, // JSGE_rr_32
2291 CEFBS_None, // JSGT_ri
2292 CEFBS_None, // JSGT_ri_32
2293 CEFBS_None, // JSGT_rr
2294 CEFBS_None, // JSGT_rr_32
2295 CEFBS_None, // JSLE_ri
2296 CEFBS_None, // JSLE_ri_32
2297 CEFBS_None, // JSLE_rr
2298 CEFBS_None, // JSLE_rr_32
2299 CEFBS_None, // JSLT_ri
2300 CEFBS_None, // JSLT_ri_32
2301 CEFBS_None, // JSLT_rr
2302 CEFBS_None, // JSLT_rr_32
2303 CEFBS_None, // JUGE_ri
2304 CEFBS_None, // JUGE_ri_32
2305 CEFBS_None, // JUGE_rr
2306 CEFBS_None, // JUGE_rr_32
2307 CEFBS_None, // JUGT_ri
2308 CEFBS_None, // JUGT_ri_32
2309 CEFBS_None, // JUGT_rr
2310 CEFBS_None, // JUGT_rr_32
2311 CEFBS_None, // JULE_ri
2312 CEFBS_None, // JULE_ri_32
2313 CEFBS_None, // JULE_rr
2314 CEFBS_None, // JULE_rr_32
2315 CEFBS_None, // JULT_ri
2316 CEFBS_None, // JULT_ri_32
2317 CEFBS_None, // JULT_rr
2318 CEFBS_None, // JULT_rr_32
2319 CEFBS_None, // JX
2320 CEFBS_None, // LDB
2321 CEFBS_None, // LDB32
2322 CEFBS_None, // LDBACQ32
2323 CEFBS_None, // LDBSX
2324 CEFBS_None, // LDD
2325 CEFBS_None, // LDDACQ
2326 CEFBS_None, // LDH
2327 CEFBS_None, // LDH32
2328 CEFBS_None, // LDHACQ32
2329 CEFBS_None, // LDHSX
2330 CEFBS_None, // LDW
2331 CEFBS_None, // LDW32
2332 CEFBS_None, // LDWACQ32
2333 CEFBS_None, // LDWSX
2334 CEFBS_None, // LD_ABS_B
2335 CEFBS_None, // LD_ABS_H
2336 CEFBS_None, // LD_ABS_W
2337 CEFBS_None, // LD_IND_B
2338 CEFBS_None, // LD_IND_H
2339 CEFBS_None, // LD_IND_W
2340 CEFBS_None, // LD_imm64
2341 CEFBS_None, // LD_pseudo
2342 CEFBS_None, // LE16
2343 CEFBS_None, // LE32
2344 CEFBS_None, // LE64
2345 CEFBS_None, // MOD_ri
2346 CEFBS_None, // MOD_ri_32
2347 CEFBS_None, // MOD_rr
2348 CEFBS_None, // MOD_rr_32
2349 CEFBS_None, // MOVSX_rr_16
2350 CEFBS_None, // MOVSX_rr_32
2351 CEFBS_None, // MOVSX_rr_32_16
2352 CEFBS_None, // MOVSX_rr_32_8
2353 CEFBS_None, // MOVSX_rr_8
2354 CEFBS_None, // MOV_32_64
2355 CEFBS_None, // MOV_ri
2356 CEFBS_None, // MOV_ri_32
2357 CEFBS_None, // MOV_rr
2358 CEFBS_None, // MOV_rr_32
2359 CEFBS_None, // MUL_ri
2360 CEFBS_None, // MUL_ri_32
2361 CEFBS_None, // MUL_rr
2362 CEFBS_None, // MUL_rr_32
2363 CEFBS_None, // NEG_32
2364 CEFBS_None, // NEG_64
2365 CEFBS_None, // NOP
2366 CEFBS_None, // OR_ri
2367 CEFBS_None, // OR_ri_32
2368 CEFBS_None, // OR_rr
2369 CEFBS_None, // OR_rr_32
2370 CEFBS_None, // RET
2371 CEFBS_None, // SDIV_ri
2372 CEFBS_None, // SDIV_ri_32
2373 CEFBS_None, // SDIV_rr
2374 CEFBS_None, // SDIV_rr_32
2375 CEFBS_None, // SLL_ri
2376 CEFBS_None, // SLL_ri_32
2377 CEFBS_None, // SLL_rr
2378 CEFBS_None, // SLL_rr_32
2379 CEFBS_None, // SMOD_ri
2380 CEFBS_None, // SMOD_ri_32
2381 CEFBS_None, // SMOD_rr
2382 CEFBS_None, // SMOD_rr_32
2383 CEFBS_None, // SRA_ri
2384 CEFBS_None, // SRA_ri_32
2385 CEFBS_None, // SRA_rr
2386 CEFBS_None, // SRA_rr_32
2387 CEFBS_None, // SRL_ri
2388 CEFBS_None, // SRL_ri_32
2389 CEFBS_None, // SRL_rr
2390 CEFBS_None, // SRL_rr_32
2391 CEFBS_None, // STB
2392 CEFBS_None, // STB32
2393 CEFBS_None, // STBREL32
2394 CEFBS_None, // STB_imm
2395 CEFBS_None, // STD
2396 CEFBS_None, // STDREL
2397 CEFBS_None, // STD_imm
2398 CEFBS_None, // STH
2399 CEFBS_None, // STH32
2400 CEFBS_None, // STHREL32
2401 CEFBS_None, // STH_imm
2402 CEFBS_None, // STW
2403 CEFBS_None, // STW32
2404 CEFBS_None, // STWREL32
2405 CEFBS_None, // STW_imm
2406 CEFBS_None, // SUB_ri
2407 CEFBS_None, // SUB_ri_32
2408 CEFBS_None, // SUB_rr
2409 CEFBS_None, // SUB_rr_32
2410 CEFBS_None, // XADDD
2411 CEFBS_None, // XADDW
2412 CEFBS_None, // XADDW32
2413 CEFBS_None, // XANDD
2414 CEFBS_None, // XANDW32
2415 CEFBS_None, // XCHGD
2416 CEFBS_None, // XCHGW32
2417 CEFBS_None, // XFADDD
2418 CEFBS_None, // XFADDW32
2419 CEFBS_None, // XFANDD
2420 CEFBS_None, // XFANDW32
2421 CEFBS_None, // XFORD
2422 CEFBS_None, // XFORW32
2423 CEFBS_None, // XFXORD
2424 CEFBS_None, // XFXORW32
2425 CEFBS_None, // XORD
2426 CEFBS_None, // XORW32
2427 CEFBS_None, // XOR_ri
2428 CEFBS_None, // XOR_ri_32
2429 CEFBS_None, // XOR_rr
2430 CEFBS_None, // XOR_rr_32
2431 CEFBS_None, // XXORD
2432 CEFBS_None, // XXORW32
2433 };
2434
2435 assert(Opcode < 526);
2436 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2437}
2438
2439
2440} // namespace llvm::BPF_MC
2441
2442#endif // GET_COMPUTE_FEATURES
2443
2444#ifdef GET_AVAILABLE_OPCODE_CHECKER
2445#undef GET_AVAILABLE_OPCODE_CHECKER
2446
2447namespace llvm::BPF_MC {
2448
2449bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2450 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2451 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2452 FeatureBitset MissingFeatures =
2453 (AvailableFeatures & RequiredFeatures) ^
2454 RequiredFeatures;
2455 return !MissingFeatures.any();
2456}
2457
2458} // namespace llvm::BPF_MC
2459
2460#endif // GET_AVAILABLE_OPCODE_CHECKER
2461
2462#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2463#undef ENABLE_INSTR_PREDICATE_VERIFIER
2464
2465#include <sstream>
2466
2467namespace llvm::BPF_MC {
2468
2469#ifndef NDEBUG
2470static const char *SubtargetFeatureNames[] = {
2471 nullptr
2472};
2473
2474#endif // NDEBUG
2475
2476void verifyInstructionPredicates(
2477 unsigned Opcode, const FeatureBitset &Features) {
2478#ifndef NDEBUG
2479 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2480 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2481 FeatureBitset MissingFeatures =
2482 (AvailableFeatures & RequiredFeatures) ^
2483 RequiredFeatures;
2484 if (MissingFeatures.any()) {
2485 std::ostringstream Msg;
2486 Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
2487 << " instruction but the ";
2488 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2489 if (MissingFeatures.test(i))
2490 Msg << SubtargetFeatureNames[i] << " ";
2491 Msg << "predicate(s) are not met";
2492 report_fatal_error(Msg.str().c_str());
2493 }
2494#endif // NDEBUG
2495}
2496
2497} // namespace llvm::BPF_MC
2498
2499#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2500
2501