1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::BPF {
13
14 enum {
15 PHI = 0, // Target.td:1200
16 INLINEASM = 1, // Target.td:1206
17 INLINEASM_BR = 2, // Target.td:1212
18 CFI_INSTRUCTION = 3, // Target.td:1221
19 EH_LABEL = 4, // Target.td:1230
20 GC_LABEL = 5, // Target.td:1239
21 ANNOTATION_LABEL = 6, // Target.td:1248
22 KILL = 7, // Target.td:1256
23 EXTRACT_SUBREG = 8, // Target.td:1263
24 INSERT_SUBREG = 9, // Target.td:1269
25 IMPLICIT_DEF = 10, // Target.td:1276
26 INIT_UNDEF = 11, // Target.td:1285
27 SUBREG_TO_REG = 12, // Target.td:1292
28 COPY_TO_REGCLASS = 13, // Target.td:1298
29 DBG_VALUE = 14, // Target.td:1305
30 DBG_VALUE_LIST = 15, // Target.td:1312
31 DBG_INSTR_REF = 16, // Target.td:1319
32 DBG_PHI = 17, // Target.td:1326
33 DBG_LABEL = 18, // Target.td:1333
34 REG_SEQUENCE = 19, // Target.td:1340
35 COPY = 20, // Target.td:1347
36 COPY_LANEMASK = 21, // Target.td:1355
37 BUNDLE = 22, // Target.td:1362
38 LIFETIME_START = 23, // Target.td:1368
39 LIFETIME_END = 24, // Target.td:1375
40 PSEUDO_PROBE = 25, // Target.td:1382
41 ARITH_FENCE = 26, // Target.td:1389
42 STACKMAP = 27, // Target.td:1398
43 FENTRY_CALL = 28, // Target.td:1533
44 PATCHPOINT = 29, // Target.td:1406
45 LOAD_STACK_GUARD = 30, // Target.td:1424
46 PREALLOCATED_SETUP = 31, // Target.td:1432
47 PREALLOCATED_ARG = 32, // Target.td:1438
48 STATEPOINT = 33, // Target.td:1415
49 LOCAL_ESCAPE = 34, // Target.td:1444
50 FAULTING_OP = 35, // Target.td:1453
51 PATCHABLE_OP = 36, // Target.td:1473
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1481
53 PATCHABLE_RET = 38, // Target.td:1488
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1497
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1505
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1513
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1523
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1543
59 FAKE_USE = 44, // Target.td:1463
60 MEMBARRIER = 45, // Target.td:1549
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1557
62 RELOC_NONE = 47, // Target.td:1565
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1576
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1572
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1580
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1584
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1865
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1857
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1872
70 G_ADD = 55, // GenericOpcodes.td:300
71 G_SUB = 56, // GenericOpcodes.td:308
72 G_MUL = 57, // GenericOpcodes.td:316
73 G_SDIV = 58, // GenericOpcodes.td:324
74 G_UDIV = 59, // GenericOpcodes.td:332
75 G_SREM = 60, // GenericOpcodes.td:340
76 G_UREM = 61, // GenericOpcodes.td:348
77 G_SDIVREM = 62, // GenericOpcodes.td:356
78 G_UDIVREM = 63, // GenericOpcodes.td:364
79 G_AND = 64, // GenericOpcodes.td:372
80 G_OR = 65, // GenericOpcodes.td:380
81 G_XOR = 66, // GenericOpcodes.td:388
82 G_ABDS = 67, // GenericOpcodes.td:417
83 G_ABDU = 68, // GenericOpcodes.td:425
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:433
85 G_UAVGCEIL = 70, // GenericOpcodes.td:440
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:447
87 G_SAVGCEIL = 72, // GenericOpcodes.td:454
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:110
89 G_PHI = 74, // GenericOpcodes.td:116
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:122
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:128
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:134
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:140
94 G_EXTRACT = 79, // GenericOpcodes.td:1472
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1484
96 G_INSERT = 81, // GenericOpcodes.td:1492
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1502
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1521
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1530
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1537
101 G_PTRTOINT = 86, // GenericOpcodes.td:152
102 G_INTTOPTR = 87, // GenericOpcodes.td:146
103 G_BITCAST = 88, // GenericOpcodes.td:158
104 G_FREEZE = 89, // GenericOpcodes.td:277
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1879
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1263
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1269
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1275
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1281
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1287
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1293
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1299
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1305
114 G_LOAD = 99, // GenericOpcodes.td:1332
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1340
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1348
117 G_INDEXED_LOAD = 102, // GenericOpcodes.td:1358
118 G_INDEXED_SEXTLOAD = 103, // GenericOpcodes.td:1366
119 G_INDEXED_ZEXTLOAD = 104, // GenericOpcodes.td:1374
120 G_STORE = 105, // GenericOpcodes.td:1382
121 G_INDEXED_STORE = 106, // GenericOpcodes.td:1390
122 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 107, // GenericOpcodes.td:1400
123 G_ATOMIC_CMPXCHG = 108, // GenericOpcodes.td:1410
124 G_ATOMICRMW_XCHG = 109, // GenericOpcodes.td:1428
125 G_ATOMICRMW_ADD = 110, // GenericOpcodes.td:1429
126 G_ATOMICRMW_SUB = 111, // GenericOpcodes.td:1430
127 G_ATOMICRMW_AND = 112, // GenericOpcodes.td:1431
128 G_ATOMICRMW_NAND = 113, // GenericOpcodes.td:1432
129 G_ATOMICRMW_OR = 114, // GenericOpcodes.td:1433
130 G_ATOMICRMW_XOR = 115, // GenericOpcodes.td:1434
131 G_ATOMICRMW_MAX = 116, // GenericOpcodes.td:1435
132 G_ATOMICRMW_MIN = 117, // GenericOpcodes.td:1436
133 G_ATOMICRMW_UMAX = 118, // GenericOpcodes.td:1437
134 G_ATOMICRMW_UMIN = 119, // GenericOpcodes.td:1438
135 G_ATOMICRMW_FADD = 120, // GenericOpcodes.td:1439
136 G_ATOMICRMW_FSUB = 121, // GenericOpcodes.td:1440
137 G_ATOMICRMW_FMAX = 122, // GenericOpcodes.td:1441
138 G_ATOMICRMW_FMIN = 123, // GenericOpcodes.td:1442
139 G_ATOMICRMW_FMAXIMUM = 124, // GenericOpcodes.td:1443
140 G_ATOMICRMW_FMINIMUM = 125, // GenericOpcodes.td:1444
141 G_ATOMICRMW_UINC_WRAP = 126, // GenericOpcodes.td:1445
142 G_ATOMICRMW_UDEC_WRAP = 127, // GenericOpcodes.td:1446
143 G_ATOMICRMW_USUB_COND = 128, // GenericOpcodes.td:1447
144 G_ATOMICRMW_USUB_SAT = 129, // GenericOpcodes.td:1448
145 G_FENCE = 130, // GenericOpcodes.td:1450
146 G_PREFETCH = 131, // GenericOpcodes.td:1457
147 G_BRCOND = 132, // GenericOpcodes.td:1592
148 G_BRINDIRECT = 133, // GenericOpcodes.td:1601
149 G_INVOKE_REGION_START = 134, // GenericOpcodes.td:1624
150 G_INTRINSIC = 135, // GenericOpcodes.td:1544
151 G_INTRINSIC_W_SIDE_EFFECTS = 136, // GenericOpcodes.td:1551
152 G_INTRINSIC_CONVERGENT = 137, // GenericOpcodes.td:1560
153 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1568
154 G_ANYEXT = 139, // GenericOpcodes.td:44
155 G_TRUNC = 140, // GenericOpcodes.td:83
156 G_TRUNC_SSAT_S = 141, // GenericOpcodes.td:90
157 G_TRUNC_SSAT_U = 142, // GenericOpcodes.td:97
158 G_TRUNC_USAT_U = 143, // GenericOpcodes.td:104
159 G_CONSTANT = 144, // GenericOpcodes.td:165
160 G_FCONSTANT = 145, // GenericOpcodes.td:172
161 G_VASTART = 146, // GenericOpcodes.td:178
162 G_VAARG = 147, // GenericOpcodes.td:185
163 G_SEXT = 148, // GenericOpcodes.td:52
164 G_SEXT_INREG = 149, // GenericOpcodes.td:66
165 G_ZEXT = 150, // GenericOpcodes.td:74
166 G_SHL = 151, // GenericOpcodes.td:396
167 G_LSHR = 152, // GenericOpcodes.td:403
168 G_ASHR = 153, // GenericOpcodes.td:410
169 G_FSHL = 154, // GenericOpcodes.td:462
170 G_FSHR = 155, // GenericOpcodes.td:470
171 G_ROTR = 156, // GenericOpcodes.td:477
172 G_ROTL = 157, // GenericOpcodes.td:484
173 G_ICMP = 158, // GenericOpcodes.td:491
174 G_FCMP = 159, // GenericOpcodes.td:498
175 G_SCMP = 160, // GenericOpcodes.td:505
176 G_UCMP = 161, // GenericOpcodes.td:512
177 G_SELECT = 162, // GenericOpcodes.td:519
178 G_UADDO = 163, // GenericOpcodes.td:584
179 G_UADDE = 164, // GenericOpcodes.td:592
180 G_USUBO = 165, // GenericOpcodes.td:614
181 G_USUBE = 166, // GenericOpcodes.td:620
182 G_SADDO = 167, // GenericOpcodes.td:599
183 G_SADDE = 168, // GenericOpcodes.td:607
184 G_SSUBO = 169, // GenericOpcodes.td:627
185 G_SSUBE = 170, // GenericOpcodes.td:634
186 G_UMULO = 171, // GenericOpcodes.td:641
187 G_SMULO = 172, // GenericOpcodes.td:649
188 G_UMULH = 173, // GenericOpcodes.td:658
189 G_SMULH = 174, // GenericOpcodes.td:667
190 G_UADDSAT = 175, // GenericOpcodes.td:679
191 G_SADDSAT = 176, // GenericOpcodes.td:687
192 G_USUBSAT = 177, // GenericOpcodes.td:695
193 G_SSUBSAT = 178, // GenericOpcodes.td:703
194 G_USHLSAT = 179, // GenericOpcodes.td:711
195 G_SSHLSAT = 180, // GenericOpcodes.td:719
196 G_SMULFIX = 181, // GenericOpcodes.td:731
197 G_UMULFIX = 182, // GenericOpcodes.td:738
198 G_SMULFIXSAT = 183, // GenericOpcodes.td:748
199 G_UMULFIXSAT = 184, // GenericOpcodes.td:755
200 G_SDIVFIX = 185, // GenericOpcodes.td:766
201 G_UDIVFIX = 186, // GenericOpcodes.td:773
202 G_SDIVFIXSAT = 187, // GenericOpcodes.td:783
203 G_UDIVFIXSAT = 188, // GenericOpcodes.td:790
204 G_FADD = 189, // GenericOpcodes.td:963
205 G_FSUB = 190, // GenericOpcodes.td:971
206 G_FMUL = 191, // GenericOpcodes.td:979
207 G_FMA = 192, // GenericOpcodes.td:988
208 G_FMAD = 193, // GenericOpcodes.td:997
209 G_FDIV = 194, // GenericOpcodes.td:1005
210 G_FREM = 195, // GenericOpcodes.td:1012
211 G_FMODF = 196, // GenericOpcodes.td:1019
212 G_FPOW = 197, // GenericOpcodes.td:1026
213 G_FPOWI = 198, // GenericOpcodes.td:1033
214 G_FEXP = 199, // GenericOpcodes.td:1040
215 G_FEXP2 = 200, // GenericOpcodes.td:1047
216 G_FEXP10 = 201, // GenericOpcodes.td:1054
217 G_FLOG = 202, // GenericOpcodes.td:1061
218 G_FLOG2 = 203, // GenericOpcodes.td:1068
219 G_FLOG10 = 204, // GenericOpcodes.td:1075
220 G_FLDEXP = 205, // GenericOpcodes.td:1082
221 G_FFREXP = 206, // GenericOpcodes.td:1089
222 G_FNEG = 207, // GenericOpcodes.td:801
223 G_FPEXT = 208, // GenericOpcodes.td:807
224 G_FPTRUNC = 209, // GenericOpcodes.td:813
225 G_FPTOSI = 210, // GenericOpcodes.td:819
226 G_FPTOUI = 211, // GenericOpcodes.td:825
227 G_SITOFP = 212, // GenericOpcodes.td:831
228 G_UITOFP = 213, // GenericOpcodes.td:837
229 G_FPTOSI_SAT = 214, // GenericOpcodes.td:843
230 G_FPTOUI_SAT = 215, // GenericOpcodes.td:849
231 G_FABS = 216, // GenericOpcodes.td:855
232 G_FCOPYSIGN = 217, // GenericOpcodes.td:861
233 G_IS_FPCLASS = 218, // GenericOpcodes.td:874
234 G_FCANONICALIZE = 219, // GenericOpcodes.td:867
235 G_FMINNUM = 220, // GenericOpcodes.td:887
236 G_FMAXNUM = 221, // GenericOpcodes.td:894
237 G_FMINNUM_IEEE = 222, // GenericOpcodes.td:912
238 G_FMAXNUM_IEEE = 223, // GenericOpcodes.td:919
239 G_FMINIMUM = 224, // GenericOpcodes.td:929
240 G_FMAXIMUM = 225, // GenericOpcodes.td:936
241 G_FMINIMUMNUM = 226, // GenericOpcodes.td:944
242 G_FMAXIMUMNUM = 227, // GenericOpcodes.td:951
243 G_GET_FPENV = 228, // GenericOpcodes.td:1219
244 G_SET_FPENV = 229, // GenericOpcodes.td:1226
245 G_RESET_FPENV = 230, // GenericOpcodes.td:1233
246 G_GET_FPMODE = 231, // GenericOpcodes.td:1240
247 G_SET_FPMODE = 232, // GenericOpcodes.td:1247
248 G_RESET_FPMODE = 233, // GenericOpcodes.td:1254
249 G_GET_ROUNDING = 234, // GenericOpcodes.td:1311
250 G_SET_ROUNDING = 235, // GenericOpcodes.td:1317
251 G_PTR_ADD = 236, // GenericOpcodes.td:526
252 G_PTRMASK = 237, // GenericOpcodes.td:534
253 G_SMIN = 238, // GenericOpcodes.td:541
254 G_SMAX = 239, // GenericOpcodes.td:549
255 G_UMIN = 240, // GenericOpcodes.td:557
256 G_UMAX = 241, // GenericOpcodes.td:565
257 G_ABS = 242, // GenericOpcodes.td:573
258 G_LROUND = 243, // GenericOpcodes.td:283
259 G_LLROUND = 244, // GenericOpcodes.td:289
260 G_BR = 245, // GenericOpcodes.td:1582
261 G_BRJT = 246, // GenericOpcodes.td:1612
262 G_VSCALE = 247, // GenericOpcodes.td:1512
263 G_INSERT_SUBVECTOR = 248, // GenericOpcodes.td:1656
264 G_EXTRACT_SUBVECTOR = 249, // GenericOpcodes.td:1663
265 G_INSERT_VECTOR_ELT = 250, // GenericOpcodes.td:1670
266 G_EXTRACT_VECTOR_ELT = 251, // GenericOpcodes.td:1677
267 G_SHUFFLE_VECTOR = 252, // GenericOpcodes.td:1687
268 G_SPLAT_VECTOR = 253, // GenericOpcodes.td:1694
269 G_STEP_VECTOR = 254, // GenericOpcodes.td:1701
270 G_VECTOR_COMPRESS = 255, // GenericOpcodes.td:1708
271 G_CTTZ = 256, // GenericOpcodes.td:205
272 G_CTTZ_ZERO_UNDEF = 257, // GenericOpcodes.td:211
273 G_CTLZ = 258, // GenericOpcodes.td:193
274 G_CTLZ_ZERO_UNDEF = 259, // GenericOpcodes.td:199
275 G_CTLS = 260, // GenericOpcodes.td:217
276 G_CTPOP = 261, // GenericOpcodes.td:223
277 G_BSWAP = 262, // GenericOpcodes.td:229
278 G_BITREVERSE = 263, // GenericOpcodes.td:235
279 G_FCEIL = 264, // GenericOpcodes.td:1096
280 G_FCOS = 265, // GenericOpcodes.td:1103
281 G_FSIN = 266, // GenericOpcodes.td:1110
282 G_FSINCOS = 267, // GenericOpcodes.td:1117
283 G_FTAN = 268, // GenericOpcodes.td:1124
284 G_FACOS = 269, // GenericOpcodes.td:1131
285 G_FASIN = 270, // GenericOpcodes.td:1138
286 G_FATAN = 271, // GenericOpcodes.td:1145
287 G_FATAN2 = 272, // GenericOpcodes.td:1152
288 G_FCOSH = 273, // GenericOpcodes.td:1159
289 G_FSINH = 274, // GenericOpcodes.td:1166
290 G_FTANH = 275, // GenericOpcodes.td:1173
291 G_FSQRT = 276, // GenericOpcodes.td:1183
292 G_FFLOOR = 277, // GenericOpcodes.td:1190
293 G_FRINT = 278, // GenericOpcodes.td:1197
294 G_FNEARBYINT = 279, // GenericOpcodes.td:1204
295 G_ADDRSPACE_CAST = 280, // GenericOpcodes.td:241
296 G_BLOCK_ADDR = 281, // GenericOpcodes.td:247
297 G_JUMP_TABLE = 282, // GenericOpcodes.td:253
298 G_DYN_STACKALLOC = 283, // GenericOpcodes.td:259
299 G_STACKSAVE = 284, // GenericOpcodes.td:265
300 G_STACKRESTORE = 285, // GenericOpcodes.td:271
301 G_STRICT_FADD = 286, // GenericOpcodes.td:1758
302 G_STRICT_FSUB = 287, // GenericOpcodes.td:1759
303 G_STRICT_FMUL = 288, // GenericOpcodes.td:1760
304 G_STRICT_FDIV = 289, // GenericOpcodes.td:1761
305 G_STRICT_FREM = 290, // GenericOpcodes.td:1762
306 G_STRICT_FMA = 291, // GenericOpcodes.td:1763
307 G_STRICT_FSQRT = 292, // GenericOpcodes.td:1764
308 G_STRICT_FLDEXP = 293, // GenericOpcodes.td:1765
309 G_READ_REGISTER = 294, // GenericOpcodes.td:1631
310 G_WRITE_REGISTER = 295, // GenericOpcodes.td:1641
311 G_MEMCPY = 296, // GenericOpcodes.td:1771
312 G_MEMCPY_INLINE = 297, // GenericOpcodes.td:1779
313 G_MEMMOVE = 298, // GenericOpcodes.td:1787
314 G_MEMSET = 299, // GenericOpcodes.td:1795
315 G_BZERO = 300, // GenericOpcodes.td:1802
316 G_TRAP = 301, // GenericOpcodes.td:1812
317 G_DEBUGTRAP = 302, // GenericOpcodes.td:1819
318 G_UBSANTRAP = 303, // GenericOpcodes.td:1825
319 G_VECREDUCE_SEQ_FADD = 304, // GenericOpcodes.td:1724
320 G_VECREDUCE_SEQ_FMUL = 305, // GenericOpcodes.td:1730
321 G_VECREDUCE_FADD = 306, // GenericOpcodes.td:1736
322 G_VECREDUCE_FMUL = 307, // GenericOpcodes.td:1737
323 G_VECREDUCE_FMAX = 308, // GenericOpcodes.td:1739
324 G_VECREDUCE_FMIN = 309, // GenericOpcodes.td:1740
325 G_VECREDUCE_FMAXIMUM = 310, // GenericOpcodes.td:1741
326 G_VECREDUCE_FMINIMUM = 311, // GenericOpcodes.td:1742
327 G_VECREDUCE_ADD = 312, // GenericOpcodes.td:1744
328 G_VECREDUCE_MUL = 313, // GenericOpcodes.td:1745
329 G_VECREDUCE_AND = 314, // GenericOpcodes.td:1746
330 G_VECREDUCE_OR = 315, // GenericOpcodes.td:1747
331 G_VECREDUCE_XOR = 316, // GenericOpcodes.td:1748
332 G_VECREDUCE_SMAX = 317, // GenericOpcodes.td:1749
333 G_VECREDUCE_SMIN = 318, // GenericOpcodes.td:1750
334 G_VECREDUCE_UMAX = 319, // GenericOpcodes.td:1751
335 G_VECREDUCE_UMIN = 320, // GenericOpcodes.td:1752
336 G_SBFX = 321, // GenericOpcodes.td:1837
337 G_UBFX = 322, // GenericOpcodes.td:1845
338 ADJCALLSTACKDOWN = 323, // BPFInstrInfo.td:817
339 ADJCALLSTACKUP = 324, // BPFInstrInfo.td:820
340 FI_ri = 325, // BPFInstrInfo.td:483
341 LDIMM64 = 326, // BPFInstrInfo.td:1393
342 MEMCPY = 327, // BPFInstrInfo.td:1384
343 Select = 328, // BPFInstrInfo.td:826
344 Select_32 = 329, // BPFInstrInfo.td:846
345 Select_32_64 = 330, // BPFInstrInfo.td:856
346 Select_64_32 = 331, // BPFInstrInfo.td:836
347 Select_Ri = 332, // BPFInstrInfo.td:831
348 Select_Ri_32 = 333, // BPFInstrInfo.td:851
349 Select_Ri_32_64 = 334, // BPFInstrInfo.td:861
350 Select_Ri_64_32 = 335, // BPFInstrInfo.td:841
351 ADDR_SPACE_CAST = 336, // BPFInstrInfo.td:454
352 ADD_ri = 337, // BPFInstrInfo.td:334
353 ADD_ri_32 = 338, // BPFInstrInfo.td:344
354 ADD_rr = 339, // BPFInstrInfo.td:329
355 ADD_rr_32 = 340, // BPFInstrInfo.td:339
356 AND_ri = 341, // BPFInstrInfo.td:334
357 AND_ri_32 = 342, // BPFInstrInfo.td:344
358 AND_rr = 343, // BPFInstrInfo.td:329
359 AND_rr_32 = 344, // BPFInstrInfo.td:339
360 BE16 = 345, // BPFInstrInfo.td:1193
361 BE32 = 346, // BPFInstrInfo.td:1194
362 BE64 = 347, // BPFInstrInfo.td:1195
363 BSWAP16 = 348, // BPFInstrInfo.td:1186
364 BSWAP32 = 349, // BPFInstrInfo.td:1187
365 BSWAP64 = 350, // BPFInstrInfo.td:1188
366 CMPXCHGD = 351, // BPFInstrInfo.td:1166
367 CMPXCHGW32 = 352, // BPFInstrInfo.td:1162
368 CORE_LD32 = 353, // BPFInstrInfo.td:655
369 CORE_LD64 = 354, // BPFInstrInfo.td:654
370 CORE_SHIFT = 355, // BPFInstrInfo.td:662
371 CORE_ST = 356, // BPFInstrInfo.td:656
372 DIV_ri = 357, // BPFInstrInfo.td:334
373 DIV_ri_32 = 358, // BPFInstrInfo.td:344
374 DIV_rr = 359, // BPFInstrInfo.td:329
375 DIV_rr_32 = 360, // BPFInstrInfo.td:339
376 JAL = 361, // BPFInstrInfo.td:781
377 JALX = 362, // BPFInstrInfo.td:782
378 JCOND = 363, // BPFInstrInfo.td:294
379 JEQ_ri = 364, // BPFInstrInfo.td:276
380 JEQ_ri_32 = 365, // BPFInstrInfo.td:278
381 JEQ_rr = 366, // BPFInstrInfo.td:275
382 JEQ_rr_32 = 367, // BPFInstrInfo.td:277
383 JMP = 368, // BPFInstrInfo.td:775
384 JMPL = 369, // BPFInstrInfo.td:776
385 JNE_ri = 370, // BPFInstrInfo.td:276
386 JNE_ri_32 = 371, // BPFInstrInfo.td:278
387 JNE_rr = 372, // BPFInstrInfo.td:275
388 JNE_rr_32 = 373, // BPFInstrInfo.td:277
389 JSET_ri = 374, // BPFInstrInfo.td:276
390 JSET_ri_32 = 375, // BPFInstrInfo.td:278
391 JSET_rr = 376, // BPFInstrInfo.td:275
392 JSET_rr_32 = 377, // BPFInstrInfo.td:277
393 JSGE_ri = 378, // BPFInstrInfo.td:276
394 JSGE_ri_32 = 379, // BPFInstrInfo.td:278
395 JSGE_rr = 380, // BPFInstrInfo.td:275
396 JSGE_rr_32 = 381, // BPFInstrInfo.td:277
397 JSGT_ri = 382, // BPFInstrInfo.td:276
398 JSGT_ri_32 = 383, // BPFInstrInfo.td:278
399 JSGT_rr = 384, // BPFInstrInfo.td:275
400 JSGT_rr_32 = 385, // BPFInstrInfo.td:277
401 JSLE_ri = 386, // BPFInstrInfo.td:276
402 JSLE_ri_32 = 387, // BPFInstrInfo.td:278
403 JSLE_rr = 388, // BPFInstrInfo.td:275
404 JSLE_rr_32 = 389, // BPFInstrInfo.td:277
405 JSLT_ri = 390, // BPFInstrInfo.td:276
406 JSLT_ri_32 = 391, // BPFInstrInfo.td:278
407 JSLT_rr = 392, // BPFInstrInfo.td:275
408 JSLT_rr_32 = 393, // BPFInstrInfo.td:277
409 JUGE_ri = 394, // BPFInstrInfo.td:276
410 JUGE_ri_32 = 395, // BPFInstrInfo.td:278
411 JUGE_rr = 396, // BPFInstrInfo.td:275
412 JUGE_rr_32 = 397, // BPFInstrInfo.td:277
413 JUGT_ri = 398, // BPFInstrInfo.td:276
414 JUGT_ri_32 = 399, // BPFInstrInfo.td:278
415 JUGT_rr = 400, // BPFInstrInfo.td:275
416 JUGT_rr_32 = 401, // BPFInstrInfo.td:277
417 JULE_ri = 402, // BPFInstrInfo.td:276
418 JULE_ri_32 = 403, // BPFInstrInfo.td:278
419 JULE_rr = 404, // BPFInstrInfo.td:275
420 JULE_rr_32 = 405, // BPFInstrInfo.td:277
421 JULT_ri = 406, // BPFInstrInfo.td:276
422 JULT_ri_32 = 407, // BPFInstrInfo.td:278
423 JULT_rr = 408, // BPFInstrInfo.td:275
424 JULT_rr_32 = 409, // BPFInstrInfo.td:277
425 JX = 410, // BPFInstrInfo.td:298
426 LDB = 411, // BPFInstrInfo.td:673
427 LDB32 = 412, // BPFInstrInfo.td:1321
428 LDBACQ32 = 413, // BPFInstrInfo.td:1326
429 LDBSX = 414, // BPFInstrInfo.td:679
430 LDD = 415, // BPFInstrInfo.td:682
431 LDDACQ = 416, // BPFInstrInfo.td:716
432 LDH = 417, // BPFInstrInfo.td:672
433 LDH32 = 418, // BPFInstrInfo.td:1320
434 LDHACQ32 = 419, // BPFInstrInfo.td:1325
435 LDHSX = 420, // BPFInstrInfo.td:678
436 LDW = 421, // BPFInstrInfo.td:671
437 LDW32 = 422, // BPFInstrInfo.td:1319
438 LDWACQ32 = 423, // BPFInstrInfo.td:1324
439 LDWSX = 424, // BPFInstrInfo.td:677
440 LD_ABS_B = 425, // BPFInstrInfo.td:1230
441 LD_ABS_H = 426, // BPFInstrInfo.td:1231
442 LD_ABS_W = 427, // BPFInstrInfo.td:1232
443 LD_IND_B = 428, // BPFInstrInfo.td:1234
444 LD_IND_H = 429, // BPFInstrInfo.td:1235
445 LD_IND_W = 430, // BPFInstrInfo.td:1236
446 LD_imm64 = 431, // BPFInstrInfo.td:408
447 LD_pseudo = 432, // BPFInstrInfo.td:499
448 LE16 = 433, // BPFInstrInfo.td:1198
449 LE32 = 434, // BPFInstrInfo.td:1199
450 LE64 = 435, // BPFInstrInfo.td:1200
451 MOD_ri = 436, // BPFInstrInfo.td:334
452 MOD_ri_32 = 437, // BPFInstrInfo.td:344
453 MOD_rr = 438, // BPFInstrInfo.td:329
454 MOD_rr_32 = 439, // BPFInstrInfo.td:339
455 MOVSX_rr_16 = 440, // BPFInstrInfo.td:435
456 MOVSX_rr_32 = 441, // BPFInstrInfo.td:439
457 MOVSX_rr_32_16 = 442, // BPFInstrInfo.td:447
458 MOVSX_rr_32_8 = 443, // BPFInstrInfo.td:443
459 MOVSX_rr_8 = 444, // BPFInstrInfo.td:431
460 MOV_32_64 = 445, // BPFInstrInfo.td:1239
461 MOV_ri = 446, // BPFInstrInfo.td:414
462 MOV_ri_32 = 447, // BPFInstrInfo.td:424
463 MOV_rr = 448, // BPFInstrInfo.td:409
464 MOV_rr_32 = 449, // BPFInstrInfo.td:419
465 MUL_ri = 450, // BPFInstrInfo.td:334
466 MUL_ri_32 = 451, // BPFInstrInfo.td:344
467 MUL_rr = 452, // BPFInstrInfo.td:329
468 MUL_rr_32 = 453, // BPFInstrInfo.td:339
469 NEG_32 = 454, // BPFInstrInfo.td:385
470 NEG_64 = 455, // BPFInstrInfo.td:382
471 NOP = 456, // BPFInstrInfo.td:798
472 OR_ri = 457, // BPFInstrInfo.td:334
473 OR_ri_32 = 458, // BPFInstrInfo.td:344
474 OR_rr = 459, // BPFInstrInfo.td:329
475 OR_rr_32 = 460, // BPFInstrInfo.td:339
476 RET = 461, // BPFInstrInfo.td:812
477 SDIV_ri = 462, // BPFInstrInfo.td:334
478 SDIV_ri_32 = 463, // BPFInstrInfo.td:344
479 SDIV_rr = 464, // BPFInstrInfo.td:329
480 SDIV_rr_32 = 465, // BPFInstrInfo.td:339
481 SLL_ri = 466, // BPFInstrInfo.td:334
482 SLL_ri_32 = 467, // BPFInstrInfo.td:344
483 SLL_rr = 468, // BPFInstrInfo.td:329
484 SLL_rr_32 = 469, // BPFInstrInfo.td:339
485 SMOD_ri = 470, // BPFInstrInfo.td:334
486 SMOD_ri_32 = 471, // BPFInstrInfo.td:344
487 SMOD_rr = 472, // BPFInstrInfo.td:329
488 SMOD_rr_32 = 473, // BPFInstrInfo.td:339
489 SRA_ri = 474, // BPFInstrInfo.td:334
490 SRA_ri_32 = 475, // BPFInstrInfo.td:344
491 SRA_rr = 476, // BPFInstrInfo.td:329
492 SRA_rr_32 = 477, // BPFInstrInfo.td:339
493 SRL_ri = 478, // BPFInstrInfo.td:334
494 SRL_ri_32 = 479, // BPFInstrInfo.td:344
495 SRL_rr = 480, // BPFInstrInfo.td:329
496 SRL_rr_32 = 481, // BPFInstrInfo.td:339
497 STB = 482, // BPFInstrInfo.td:539
498 STB32 = 483, // BPFInstrInfo.td:1288
499 STBREL32 = 484, // BPFInstrInfo.td:1293
500 STB_imm = 485, // BPFInstrInfo.td:575
501 STD = 486, // BPFInstrInfo.td:541
502 STDREL = 487, // BPFInstrInfo.td:619
503 STD_imm = 488, // BPFInstrInfo.td:572
504 STH = 489, // BPFInstrInfo.td:538
505 STH32 = 490, // BPFInstrInfo.td:1287
506 STHREL32 = 491, // BPFInstrInfo.td:1292
507 STH_imm = 492, // BPFInstrInfo.td:574
508 STW = 493, // BPFInstrInfo.td:537
509 STW32 = 494, // BPFInstrInfo.td:1286
510 STWREL32 = 495, // BPFInstrInfo.td:1291
511 STW_imm = 496, // BPFInstrInfo.td:573
512 SUB_ri = 497, // BPFInstrInfo.td:334
513 SUB_ri_32 = 498, // BPFInstrInfo.td:344
514 SUB_rr = 499, // BPFInstrInfo.td:329
515 SUB_rr_32 = 500, // BPFInstrInfo.td:339
516 XADDD = 501, // BPFInstrInfo.td:915
517 XADDW = 502, // BPFInstrInfo.td:914
518 XADDW32 = 503, // BPFInstrInfo.td:909
519 XANDD = 504, // BPFInstrInfo.td:916
520 XANDW32 = 505, // BPFInstrInfo.td:910
521 XCHGD = 506, // BPFInstrInfo.td:1122
522 XCHGW32 = 507, // BPFInstrInfo.td:1119
523 XFADDD = 508, // BPFInstrInfo.td:972
524 XFADDW32 = 509, // BPFInstrInfo.td:965
525 XFANDD = 510, // BPFInstrInfo.td:974
526 XFANDW32 = 511, // BPFInstrInfo.td:966
527 XFORD = 512, // BPFInstrInfo.td:975
528 XFORW32 = 513, // BPFInstrInfo.td:967
529 XFXORD = 514, // BPFInstrInfo.td:976
530 XFXORW32 = 515, // BPFInstrInfo.td:968
531 XORD = 516, // BPFInstrInfo.td:917
532 XORW32 = 517, // BPFInstrInfo.td:911
533 XOR_ri = 518, // BPFInstrInfo.td:334
534 XOR_ri_32 = 519, // BPFInstrInfo.td:344
535 XOR_rr = 520, // BPFInstrInfo.td:329
536 XOR_rr_32 = 521, // BPFInstrInfo.td:339
537 XXORD = 522, // BPFInstrInfo.td:918
538 XXORW32 = 523, // BPFInstrInfo.td:912
539 INSTRUCTION_LIST_END = 524
540 };
541
542} // namespace llvm::BPF
543
544#endif // GET_INSTRINFO_ENUM
545
546#ifdef GET_INSTRINFO_SCHED_ENUM
547#undef GET_INSTRINFO_SCHED_ENUM
548
549namespace llvm::BPF::Sched {
550
551 enum {
552 NoInstrModel = 0,
553 SCHED_LIST_END = 1
554 };
555
556} // namespace llvm::BPF::Sched
557
558#endif // GET_INSTRINFO_SCHED_ENUM
559
560#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
561
562namespace llvm {
563
564struct BPFInstrTable {
565 MCInstrDesc Insts[524];
566 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
567 MCPhysReg ImplicitOps[14];
568 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
569 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
570 MCOperandInfo OperandInfo[284];
571};
572} // namespace llvm
573
574#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
575
576#ifdef GET_INSTRINFO_MC_DESC
577#undef GET_INSTRINFO_MC_DESC
578
579namespace llvm {
580
581static_assert((sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
582static constexpr unsigned BPFOpInfoBase = (sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) / sizeof(MCOperandInfo);
583
584extern const BPFInstrTable BPFDescs = {
585 {
586 { 523, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 280, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORW32
587 { 522, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORD
588 { 521, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr_32
589 { 520, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr
590 { 519, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri_32
591 { 518, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri
592 { 517, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 280, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORW32
593 { 516, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORD
594 { 515, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 280, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORW32
595 { 514, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORD
596 { 513, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 280, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORW32
597 { 512, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORD
598 { 511, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 280, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDW32
599 { 510, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDD
600 { 509, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 280, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDW32
601 { 508, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDD
602 { 507, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 280, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGW32
603 { 506, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGD
604 { 505, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 280, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDW32
605 { 504, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDD
606 { 503, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 280, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW32
607 { 502, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW
608 { 501, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 276, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDD
609 { 500, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr_32
610 { 499, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr
611 { 498, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri_32
612 { 497, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri
613 { 496, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 273, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_imm
614 { 495, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWREL32
615 { 494, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW32
616 { 493, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW
617 { 492, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 273, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_imm
618 { 491, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STHREL32
619 { 490, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH32
620 { 489, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH
621 { 488, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 273, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD_imm
622 { 487, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDREL
623 { 486, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD
624 { 485, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 273, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_imm
625 { 484, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STBREL32
626 { 483, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB32
627 { 482, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB
628 { 481, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr_32
629 { 480, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr
630 { 479, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri_32
631 { 478, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri
632 { 477, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr_32
633 { 476, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr
634 { 475, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri_32
635 { 474, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri
636 { 473, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr_32
637 { 472, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr
638 { 471, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri_32
639 { 470, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri
640 { 469, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr_32
641 { 468, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr
642 { 467, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri_32
643 { 466, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri
644 { 465, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr_32
645 { 464, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr
646 { 463, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri_32
647 { 462, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri
648 { 461, 0, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
649 { 460, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr_32
650 { 459, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr
651 { 458, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri_32
652 { 457, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri
653 { 456, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
654 { 455, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_64
655 { 454, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_32
656 { 453, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr_32
657 { 452, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr
658 { 451, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri_32
659 { 450, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri
660 { 449, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 265, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr_32
661 { 448, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr
662 { 447, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 269, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri_32
663 { 446, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 158, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri
664 { 445, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 267, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_32_64
665 { 444, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_8
666 { 443, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 265, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_8
667 { 442, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 265, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_16
668 { 441, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32
669 { 440, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_16
670 { 439, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr_32
671 { 438, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr
672 { 437, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri_32
673 { 436, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri
674 { 435, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE64
675 { 434, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE32
676 { 433, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE16
677 { 432, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_pseudo
678 { 431, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 38, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_imm64
679 { 430, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 32, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_W
680 { 429, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 32, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_H
681 { 428, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 32, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_B
682 { 427, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_W
683 { 426, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_H
684 { 425, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_B
685 { 424, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSX
686 { 423, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWACQ32
687 { 422, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW32
688 { 421, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW
689 { 420, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHSX
690 { 419, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHACQ32
691 { 418, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH32
692 { 417, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH
693 { 416, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDDACQ
694 { 415, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDD
695 { 414, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBSX
696 { 413, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBACQ32
697 { 412, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 260, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB32
698 { 411, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB
699 { 410, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JX
700 { 409, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr_32
701 { 408, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr
702 { 407, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri_32
703 { 406, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri
704 { 405, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr_32
705 { 404, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr
706 { 403, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri_32
707 { 402, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri
708 { 401, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr_32
709 { 400, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr
710 { 399, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri_32
711 { 398, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri
712 { 397, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr_32
713 { 396, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr
714 { 395, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri_32
715 { 394, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri
716 { 393, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr_32
717 { 392, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr
718 { 391, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri_32
719 { 390, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri
720 { 389, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr_32
721 { 388, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr
722 { 387, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri_32
723 { 386, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri
724 { 385, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr_32
725 { 384, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr
726 { 383, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri_32
727 { 382, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri
728 { 381, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr_32
729 { 380, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr
730 { 379, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri_32
731 { 378, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri
732 { 377, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr_32
733 { 376, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr
734 { 375, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri_32
735 { 374, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri
736 { 373, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr_32
737 { 372, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr
738 { 371, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri_32
739 { 370, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri
740 { 369, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMPL
741 { 368, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
742 { 367, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 257, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr_32
743 { 366, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 254, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr
744 { 365, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 251, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri_32
745 { 364, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 248, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri
746 { 363, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCOND
747 { 362, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 32, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JALX
748 { 361, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 0, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JAL
749 { 360, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr_32
750 { 359, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr
751 { 358, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri_32
752 { 357, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri
753 { 356, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 244, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_ST
754 { 355, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 240, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_SHIFT
755 { 354, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 236, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD64
756 { 353, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 232, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD32
757 { 352, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 229, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGW32
758 { 351, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 226, 2, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGD
759 { 350, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP64
760 { 349, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP32
761 { 348, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP16
762 { 347, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE64
763 { 346, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE32
764 { 345, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 224, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE16
765 { 344, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr_32
766 { 343, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr
767 { 342, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri_32
768 { 341, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri
769 { 340, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 221, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr_32
770 { 339, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 218, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr
771 { 338, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 215, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri_32
772 { 337, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 212, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri
773 { 336, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 160, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDR_SPACE_CAST
774 { 335, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 206, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_64_32
775 { 334, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 200, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32_64
776 { 333, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 194, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32
777 { 332, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 188, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri
778 { 331, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 182, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_64_32
779 { 330, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 176, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32_64
780 { 329, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 170, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32
781 { 328, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 164, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select
782 { 327, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY
783 { 326, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 158, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIMM64
784 { 325, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 155, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FI_ri
785 { 324, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
786 { 323, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
787 { 322, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
788 { 321, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
789 { 320, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
790 { 319, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
791 { 318, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
792 { 317, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
793 { 316, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
794 { 315, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
795 { 314, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
796 { 313, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
797 { 312, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
798 { 311, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
799 { 310, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
800 { 309, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
801 { 308, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
802 { 307, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
803 { 306, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
804 { 305, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
805 { 304, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
806 { 303, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
807 { 302, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
808 { 301, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
809 { 300, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
810 { 299, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
811 { 298, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
812 { 297, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
813 { 296, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
814 { 295, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 145, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
815 { 294, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
816 { 293, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
817 { 292, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
818 { 291, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
819 { 290, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
820 { 289, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
821 { 288, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
822 { 287, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
823 { 286, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
824 { 285, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
825 { 284, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
826 { 283, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
827 { 282, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
828 { 281, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
829 { 280, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
830 { 279, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
831 { 278, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
832 { 277, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
833 { 276, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
834 { 275, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
835 { 274, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
836 { 273, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
837 { 272, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
838 { 271, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
839 { 270, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
840 { 269, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
841 { 268, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
842 { 267, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
843 { 266, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
844 { 265, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
845 { 264, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
846 { 263, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
847 { 262, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
848 { 261, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
849 { 260, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
850 { 259, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_UNDEF
851 { 258, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
852 { 257, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_UNDEF
853 { 256, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
854 { 255, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
855 { 254, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
856 { 253, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
857 { 252, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
858 { 251, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 134, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
859 { 250, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
860 { 249, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
861 { 248, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
862 { 247, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
863 { 246, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 127, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
864 { 245, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
865 { 244, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
866 { 243, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
867 { 242, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
868 { 241, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
869 { 240, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
870 { 239, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
871 { 238, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
872 { 237, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
873 { 236, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
874 { 235, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
875 { 234, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
876 { 233, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
877 { 232, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
878 { 231, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
879 { 230, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
880 { 229, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
881 { 228, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
882 { 227, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
883 { 226, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
884 { 225, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
885 { 224, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
886 { 223, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
887 { 222, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
888 { 221, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
889 { 220, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
890 { 219, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
891 { 218, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
892 { 217, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
893 { 216, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
894 { 215, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
895 { 214, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
896 { 213, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
897 { 212, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
898 { 211, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
899 { 210, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
900 { 209, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
901 { 208, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
902 { 207, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
903 { 206, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
904 { 205, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
905 { 204, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
906 { 203, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
907 { 202, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
908 { 201, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
909 { 200, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
910 { 199, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
911 { 198, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
912 { 197, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
913 { 196, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
914 { 195, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
915 { 194, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
916 { 193, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
917 { 192, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
918 { 191, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
919 { 190, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
920 { 189, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
921 { 188, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
922 { 187, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
923 { 186, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
924 { 185, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
925 { 184, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
926 { 183, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
927 { 182, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
928 { 181, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
929 { 180, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
930 { 179, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
931 { 178, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
932 { 177, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
933 { 176, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
934 { 175, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
935 { 174, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
936 { 173, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
937 { 172, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
938 { 171, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
939 { 170, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
940 { 169, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
941 { 168, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
942 { 167, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
943 { 166, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
944 { 165, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
945 { 164, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 118, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
946 { 163, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
947 { 162, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
948 { 161, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
949 { 160, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 115, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
950 { 159, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
951 { 158, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
952 { 157, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
953 { 156, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
954 { 155, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
955 { 154, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
956 { 153, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
957 { 152, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
958 { 151, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 104, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
959 { 150, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
960 { 149, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
961 { 148, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
962 { 147, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 101, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
963 { 146, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
964 { 145, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
965 { 144, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
966 { 143, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
967 { 142, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
968 { 141, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
969 { 140, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
970 { 139, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
971 { 138, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
972 { 137, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
973 { 136, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
974 { 135, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
975 { 134, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
976 { 133, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
977 { 132, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
978 { 131, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
979 { 130, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 24, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
980 { 129, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
981 { 128, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
982 { 127, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
983 { 126, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
984 { 125, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
985 { 124, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
986 { 123, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
987 { 122, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
988 { 121, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
989 { 120, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
990 { 119, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
991 { 118, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
992 { 117, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
993 { 116, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
994 { 115, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
995 { 114, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
996 { 113, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
997 { 112, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
998 { 111, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
999 { 110, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1000 { 109, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 94, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1001 { 108, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1002 { 107, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 85, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1003 { 106, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 80, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1004 { 105, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1005 { 104, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1006 { 103, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1007 { 102, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 75, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1008 { 101, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1009 { 100, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1010 { 99, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1011 { 98, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1012 { 97, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1013 { 96, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1014 { 95, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1015 { 94, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1016 { 93, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1017 { 92, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1018 { 91, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 72, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1019 { 90, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1020 { 89, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 70, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1021 { 88, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1022 { 87, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1023 { 86, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1024 { 85, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1025 { 84, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1026 { 83, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1027 { 82, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1028 { 81, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1029 { 80, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 64, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1030 { 79, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 61, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1031 { 78, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1032 { 77, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 56, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1033 { 76, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1034 { 75, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 54, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1035 { 74, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1036 { 73, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 53, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1037 { 72, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1038 { 71, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1039 { 70, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1040 { 69, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1041 { 68, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1042 { 67, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1043 { 66, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1044 { 65, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1045 { 64, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1046 { 63, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1047 { 62, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1048 { 61, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1049 { 60, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1050 { 59, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1051 { 58, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1052 { 57, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1053 { 56, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1054 { 55, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 46, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1055 { 54, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1056 { 53, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1057 { 52, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 43, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1058 { 51, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1059 { 50, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1060 { 49, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1061 { 48, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1062 { 47, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1063 { 46, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1064 { 45, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1065 { 44, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1066 { 43, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1067 { 42, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 40, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14718
1068 { 41, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 38, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14717
1069 { 40, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1070 { 39, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1071 { 38, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1072 { 37, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1073 { 36, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1074 { 35, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1075 { 34, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1076 { 33, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1077 { 32, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 33, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14716
1078 { 31, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1079 { 30, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14301
1080 { 29, 6, 1, 0, 0, 0, 0, BPFOpInfoBase + 26, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1081 { 28, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1082 { 27, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 24, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1083 { 26, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1084 { 25, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1085 { 24, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1086 { 23, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1087 { 22, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1088 { 21, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1089 { 20, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1090 { 19, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 13, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1091 { 18, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1092 { 17, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1093 { 16, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1094 { 15, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1095 { 14, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1096 { 13, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1097 { 12, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1098 { 11, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1099 { 10, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1100 { 9, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1101 { 8, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1102 { 7, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1103 { 6, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1104 { 5, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1105 { 4, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1106 { 3, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1107 { 2, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1108 { 1, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1109 { 0, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1110 }, {
1111 /* 0 */
1112 /* 0 */ BPF::R11, BPF::R11,
1113 /* 2 */ BPF::R0, BPF::R0,
1114 /* 4 */ BPF::W0, BPF::W0,
1115 /* 6 */ BPF::R11,
1116 /* 7 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1117 }, {
1118 0
1119 }, {
1120 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1121 /* 1 */
1122 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1123 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1124 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1125 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1126 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1127 /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1128 /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1129 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1130 /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1131 /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1132 /* 32 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1133 /* 33 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1134 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1135 /* 38 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1136 /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1137 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1138 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1139 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1140 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1141 /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1142 /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1143 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1144 /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1145 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1146 /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1147 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1148 /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1149 /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1150 /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1151 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1152 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1153 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1154 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1155 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1156 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1157 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1158 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1159 /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1160 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1161 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1162 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1163 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1164 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1165 /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1166 /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1167 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1168 /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1169 /* 155 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1170 /* 158 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1171 /* 160 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1172 /* 164 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1173 /* 170 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1174 /* 176 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1175 /* 182 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1176 /* 188 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1177 /* 194 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1178 /* 200 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1179 /* 206 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1180 /* 212 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1181 /* 215 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1182 /* 218 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1183 /* 221 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1184 /* 224 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1185 /* 226 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1186 /* 229 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1187 /* 232 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1188 /* 236 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1189 /* 240 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1190 /* 244 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1191 /* 248 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1192 /* 251 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1193 /* 254 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1194 /* 257 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1195 /* 260 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1196 /* 263 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1197 /* 265 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1198 /* 267 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1199 /* 269 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1200 /* 271 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1201 /* 273 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1202 /* 276 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1203 /* 280 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1204 }
1205};
1206
1207
1208#ifdef __GNUC__
1209#pragma GCC diagnostic push
1210#pragma GCC diagnostic ignored "-Woverlength-strings"
1211#endif
1212extern const char BPFInstrNameData[] = {
1213 /* 0 */ "G_FLOG10\000"
1214 /* 9 */ "G_FEXP10\000"
1215 /* 18 */ "LDB32\000"
1216 /* 24 */ "STB32\000"
1217 /* 30 */ "CORE_LD32\000"
1218 /* 40 */ "BE32\000"
1219 /* 45 */ "LE32\000"
1220 /* 50 */ "LDH32\000"
1221 /* 56 */ "STH32\000"
1222 /* 62 */ "STBREL32\000"
1223 /* 71 */ "STHREL32\000"
1224 /* 80 */ "STWREL32\000"
1225 /* 89 */ "BSWAP32\000"
1226 /* 97 */ "LDBACQ32\000"
1227 /* 106 */ "LDHACQ32\000"
1228 /* 115 */ "LDWACQ32\000"
1229 /* 124 */ "XFADDW32\000"
1230 /* 133 */ "XADDW32\000"
1231 /* 141 */ "LDW32\000"
1232 /* 147 */ "XFANDW32\000"
1233 /* 156 */ "XANDW32\000"
1234 /* 164 */ "CMPXCHGW32\000"
1235 /* 175 */ "XFORW32\000"
1236 /* 183 */ "XFXORW32\000"
1237 /* 192 */ "XXORW32\000"
1238 /* 200 */ "STW32\000"
1239 /* 206 */ "Select_Ri_64_32\000"
1240 /* 222 */ "Select_64_32\000"
1241 /* 235 */ "NEG_32\000"
1242 /* 242 */ "Select_Ri_32\000"
1243 /* 255 */ "SRA_ri_32\000"
1244 /* 265 */ "SUB_ri_32\000"
1245 /* 275 */ "ADD_ri_32\000"
1246 /* 285 */ "AND_ri_32\000"
1247 /* 295 */ "SMOD_ri_32\000"
1248 /* 306 */ "JSGE_ri_32\000"
1249 /* 317 */ "JUGE_ri_32\000"
1250 /* 328 */ "JSLE_ri_32\000"
1251 /* 339 */ "JULE_ri_32\000"
1252 /* 350 */ "JNE_ri_32\000"
1253 /* 360 */ "SLL_ri_32\000"
1254 /* 370 */ "SRL_ri_32\000"
1255 /* 380 */ "MUL_ri_32\000"
1256 /* 390 */ "JEQ_ri_32\000"
1257 /* 400 */ "XOR_ri_32\000"
1258 /* 410 */ "JSET_ri_32\000"
1259 /* 421 */ "JSGT_ri_32\000"
1260 /* 432 */ "JUGT_ri_32\000"
1261 /* 443 */ "JSLT_ri_32\000"
1262 /* 454 */ "JULT_ri_32\000"
1263 /* 465 */ "SDIV_ri_32\000"
1264 /* 476 */ "MOV_ri_32\000"
1265 /* 486 */ "SRA_rr_32\000"
1266 /* 496 */ "SUB_rr_32\000"
1267 /* 506 */ "ADD_rr_32\000"
1268 /* 516 */ "AND_rr_32\000"
1269 /* 526 */ "SMOD_rr_32\000"
1270 /* 537 */ "JSGE_rr_32\000"
1271 /* 548 */ "JUGE_rr_32\000"
1272 /* 559 */ "JSLE_rr_32\000"
1273 /* 570 */ "JULE_rr_32\000"
1274 /* 581 */ "JNE_rr_32\000"
1275 /* 591 */ "SLL_rr_32\000"
1276 /* 601 */ "SRL_rr_32\000"
1277 /* 611 */ "MUL_rr_32\000"
1278 /* 621 */ "JEQ_rr_32\000"
1279 /* 631 */ "XOR_rr_32\000"
1280 /* 641 */ "JSET_rr_32\000"
1281 /* 652 */ "JSGT_rr_32\000"
1282 /* 663 */ "JUGT_rr_32\000"
1283 /* 674 */ "JSLT_rr_32\000"
1284 /* 685 */ "JULT_rr_32\000"
1285 /* 696 */ "SDIV_rr_32\000"
1286 /* 707 */ "MOV_rr_32\000"
1287 /* 717 */ "MOVSX_rr_32\000"
1288 /* 729 */ "Select_32\000"
1289 /* 739 */ "G_FLOG2\000"
1290 /* 747 */ "G_FATAN2\000"
1291 /* 756 */ "G_FEXP2\000"
1292 /* 764 */ "CORE_LD64\000"
1293 /* 774 */ "BE64\000"
1294 /* 779 */ "LE64\000"
1295 /* 784 */ "LDIMM64\000"
1296 /* 792 */ "BSWAP64\000"
1297 /* 800 */ "MOV_32_64\000"
1298 /* 810 */ "Select_Ri_32_64\000"
1299 /* 826 */ "Select_32_64\000"
1300 /* 839 */ "NEG_64\000"
1301 /* 846 */ "LD_imm64\000"
1302 /* 855 */ "BE16\000"
1303 /* 860 */ "LE16\000"
1304 /* 865 */ "BSWAP16\000"
1305 /* 873 */ "MOVSX_rr_32_16\000"
1306 /* 888 */ "MOVSX_rr_16\000"
1307 /* 900 */ "MOVSX_rr_32_8\000"
1308 /* 914 */ "MOVSX_rr_8\000"
1309 /* 925 */ "G_FMA\000"
1310 /* 931 */ "G_STRICT_FMA\000"
1311 /* 944 */ "LDB\000"
1312 /* 948 */ "STB\000"
1313 /* 952 */ "G_FSUB\000"
1314 /* 959 */ "G_STRICT_FSUB\000"
1315 /* 973 */ "G_ATOMICRMW_FSUB\000"
1316 /* 990 */ "G_SUB\000"
1317 /* 996 */ "G_ATOMICRMW_SUB\000"
1318 /* 1012 */ "LD_IND_B\000"
1319 /* 1021 */ "LD_ABS_B\000"
1320 /* 1030 */ "G_INTRINSIC\000"
1321 /* 1042 */ "G_FPTRUNC\000"
1322 /* 1052 */ "G_INTRINSIC_TRUNC\000"
1323 /* 1070 */ "G_TRUNC\000"
1324 /* 1078 */ "G_BUILD_VECTOR_TRUNC\000"
1325 /* 1099 */ "G_DYN_STACKALLOC\000"
1326 /* 1116 */ "G_FMAD\000"
1327 /* 1123 */ "G_INDEXED_SEXTLOAD\000"
1328 /* 1142 */ "G_SEXTLOAD\000"
1329 /* 1153 */ "G_INDEXED_ZEXTLOAD\000"
1330 /* 1172 */ "G_ZEXTLOAD\000"
1331 /* 1183 */ "G_INDEXED_LOAD\000"
1332 /* 1198 */ "G_LOAD\000"
1333 /* 1205 */ "G_VECREDUCE_FADD\000"
1334 /* 1222 */ "G_FADD\000"
1335 /* 1229 */ "G_VECREDUCE_SEQ_FADD\000"
1336 /* 1250 */ "G_STRICT_FADD\000"
1337 /* 1264 */ "G_ATOMICRMW_FADD\000"
1338 /* 1281 */ "G_VECREDUCE_ADD\000"
1339 /* 1297 */ "G_ADD\000"
1340 /* 1303 */ "G_PTR_ADD\000"
1341 /* 1313 */ "G_ATOMICRMW_ADD\000"
1342 /* 1329 */ "XFADDD\000"
1343 /* 1336 */ "XADDD\000"
1344 /* 1342 */ "LDD\000"
1345 /* 1346 */ "XFANDD\000"
1346 /* 1353 */ "XANDD\000"
1347 /* 1359 */ "CMPXCHGD\000"
1348 /* 1368 */ "G_ATOMICRMW_NAND\000"
1349 /* 1385 */ "G_VECREDUCE_AND\000"
1350 /* 1401 */ "G_AND\000"
1351 /* 1407 */ "G_ATOMICRMW_AND\000"
1352 /* 1423 */ "LIFETIME_END\000"
1353 /* 1436 */ "JCOND\000"
1354 /* 1442 */ "G_BRCOND\000"
1355 /* 1451 */ "G_ATOMICRMW_USUB_COND\000"
1356 /* 1473 */ "G_LLROUND\000"
1357 /* 1483 */ "G_LROUND\000"
1358 /* 1492 */ "G_INTRINSIC_ROUND\000"
1359 /* 1510 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1360 /* 1536 */ "LOAD_STACK_GUARD\000"
1361 /* 1553 */ "XFORD\000"
1362 /* 1559 */ "XFXORD\000"
1363 /* 1566 */ "XXORD\000"
1364 /* 1572 */ "STD\000"
1365 /* 1576 */ "PSEUDO_PROBE\000"
1366 /* 1589 */ "G_SSUBE\000"
1367 /* 1597 */ "G_USUBE\000"
1368 /* 1605 */ "G_FENCE\000"
1369 /* 1613 */ "ARITH_FENCE\000"
1370 /* 1625 */ "REG_SEQUENCE\000"
1371 /* 1638 */ "G_SADDE\000"
1372 /* 1646 */ "G_UADDE\000"
1373 /* 1654 */ "G_GET_FPMODE\000"
1374 /* 1667 */ "G_RESET_FPMODE\000"
1375 /* 1682 */ "G_SET_FPMODE\000"
1376 /* 1695 */ "G_FMINNUM_IEEE\000"
1377 /* 1710 */ "G_FMAXNUM_IEEE\000"
1378 /* 1725 */ "G_VSCALE\000"
1379 /* 1734 */ "G_JUMP_TABLE\000"
1380 /* 1747 */ "BUNDLE\000"
1381 /* 1754 */ "G_MEMCPY_INLINE\000"
1382 /* 1770 */ "RELOC_NONE\000"
1383 /* 1781 */ "LOCAL_ESCAPE\000"
1384 /* 1794 */ "G_STACKRESTORE\000"
1385 /* 1809 */ "G_INDEXED_STORE\000"
1386 /* 1825 */ "G_STORE\000"
1387 /* 1833 */ "G_BITREVERSE\000"
1388 /* 1846 */ "FAKE_USE\000"
1389 /* 1855 */ "DBG_VALUE\000"
1390 /* 1865 */ "G_GLOBAL_VALUE\000"
1391 /* 1880 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1392 /* 1903 */ "CONVERGENCECTRL_GLUE\000"
1393 /* 1924 */ "G_STACKSAVE\000"
1394 /* 1936 */ "G_MEMMOVE\000"
1395 /* 1946 */ "G_FREEZE\000"
1396 /* 1955 */ "G_FCANONICALIZE\000"
1397 /* 1971 */ "G_FMODF\000"
1398 /* 1979 */ "G_CTLZ_ZERO_UNDEF\000"
1399 /* 1997 */ "G_CTTZ_ZERO_UNDEF\000"
1400 /* 2015 */ "INIT_UNDEF\000"
1401 /* 2026 */ "G_IMPLICIT_DEF\000"
1402 /* 2041 */ "DBG_INSTR_REF\000"
1403 /* 2055 */ "G_FNEG\000"
1404 /* 2062 */ "EXTRACT_SUBREG\000"
1405 /* 2077 */ "INSERT_SUBREG\000"
1406 /* 2091 */ "G_SEXT_INREG\000"
1407 /* 2104 */ "SUBREG_TO_REG\000"
1408 /* 2118 */ "G_ATOMIC_CMPXCHG\000"
1409 /* 2135 */ "G_ATOMICRMW_XCHG\000"
1410 /* 2152 */ "G_GET_ROUNDING\000"
1411 /* 2167 */ "G_SET_ROUNDING\000"
1412 /* 2182 */ "G_FLOG\000"
1413 /* 2189 */ "G_VAARG\000"
1414 /* 2197 */ "PREALLOCATED_ARG\000"
1415 /* 2214 */ "G_PREFETCH\000"
1416 /* 2225 */ "LDH\000"
1417 /* 2229 */ "G_SMULH\000"
1418 /* 2237 */ "G_UMULH\000"
1419 /* 2245 */ "G_FTANH\000"
1420 /* 2253 */ "G_FSINH\000"
1421 /* 2261 */ "G_FCOSH\000"
1422 /* 2269 */ "STH\000"
1423 /* 2273 */ "LD_IND_H\000"
1424 /* 2282 */ "LD_ABS_H\000"
1425 /* 2291 */ "DBG_PHI\000"
1426 /* 2299 */ "G_FPTOSI\000"
1427 /* 2308 */ "G_FPTOUI\000"
1428 /* 2317 */ "G_FPOWI\000"
1429 /* 2325 */ "COPY_LANEMASK\000"
1430 /* 2339 */ "G_PTRMASK\000"
1431 /* 2349 */ "JAL\000"
1432 /* 2353 */ "GC_LABEL\000"
1433 /* 2362 */ "DBG_LABEL\000"
1434 /* 2372 */ "EH_LABEL\000"
1435 /* 2381 */ "ANNOTATION_LABEL\000"
1436 /* 2398 */ "ICALL_BRANCH_FUNNEL\000"
1437 /* 2418 */ "STDREL\000"
1438 /* 2425 */ "G_FSHL\000"
1439 /* 2432 */ "G_SHL\000"
1440 /* 2438 */ "G_FCEIL\000"
1441 /* 2446 */ "G_SAVGCEIL\000"
1442 /* 2457 */ "G_UAVGCEIL\000"
1443 /* 2468 */ "PATCHABLE_TAIL_CALL\000"
1444 /* 2488 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1445 /* 2515 */ "PATCHABLE_EVENT_CALL\000"
1446 /* 2536 */ "FENTRY_CALL\000"
1447 /* 2548 */ "KILL\000"
1448 /* 2553 */ "G_CONSTANT_POOL\000"
1449 /* 2569 */ "JMPL\000"
1450 /* 2574 */ "G_ROTL\000"
1451 /* 2581 */ "G_VECREDUCE_FMUL\000"
1452 /* 2598 */ "G_FMUL\000"
1453 /* 2605 */ "G_VECREDUCE_SEQ_FMUL\000"
1454 /* 2626 */ "G_STRICT_FMUL\000"
1455 /* 2640 */ "G_VECREDUCE_MUL\000"
1456 /* 2656 */ "G_MUL\000"
1457 /* 2662 */ "G_FREM\000"
1458 /* 2669 */ "G_STRICT_FREM\000"
1459 /* 2683 */ "G_SREM\000"
1460 /* 2690 */ "G_UREM\000"
1461 /* 2697 */ "G_SDIVREM\000"
1462 /* 2707 */ "G_UDIVREM\000"
1463 /* 2717 */ "INLINEASM\000"
1464 /* 2727 */ "G_VECREDUCE_FMINIMUM\000"
1465 /* 2748 */ "G_FMINIMUM\000"
1466 /* 2759 */ "G_ATOMICRMW_FMINIMUM\000"
1467 /* 2780 */ "G_VECREDUCE_FMAXIMUM\000"
1468 /* 2801 */ "G_FMAXIMUM\000"
1469 /* 2812 */ "G_ATOMICRMW_FMAXIMUM\000"
1470 /* 2833 */ "G_FMINIMUMNUM\000"
1471 /* 2847 */ "G_FMAXIMUMNUM\000"
1472 /* 2861 */ "G_FMINNUM\000"
1473 /* 2871 */ "G_FMAXNUM\000"
1474 /* 2881 */ "G_FATAN\000"
1475 /* 2889 */ "G_FTAN\000"
1476 /* 2896 */ "G_INTRINSIC_ROUNDEVEN\000"
1477 /* 2918 */ "G_ASSERT_ALIGN\000"
1478 /* 2933 */ "G_FCOPYSIGN\000"
1479 /* 2945 */ "G_VECREDUCE_FMIN\000"
1480 /* 2962 */ "G_ATOMICRMW_FMIN\000"
1481 /* 2979 */ "G_VECREDUCE_SMIN\000"
1482 /* 2996 */ "G_SMIN\000"
1483 /* 3003 */ "G_VECREDUCE_UMIN\000"
1484 /* 3020 */ "G_UMIN\000"
1485 /* 3027 */ "G_ATOMICRMW_UMIN\000"
1486 /* 3044 */ "G_ATOMICRMW_MIN\000"
1487 /* 3060 */ "G_FASIN\000"
1488 /* 3068 */ "G_FSIN\000"
1489 /* 3075 */ "CFI_INSTRUCTION\000"
1490 /* 3091 */ "ADJCALLSTACKDOWN\000"
1491 /* 3108 */ "G_SSUBO\000"
1492 /* 3116 */ "G_USUBO\000"
1493 /* 3124 */ "G_SADDO\000"
1494 /* 3132 */ "G_UADDO\000"
1495 /* 3140 */ "JUMP_TABLE_DEBUG_INFO\000"
1496 /* 3162 */ "G_SMULO\000"
1497 /* 3170 */ "G_UMULO\000"
1498 /* 3178 */ "G_BZERO\000"
1499 /* 3186 */ "STACKMAP\000"
1500 /* 3195 */ "G_DEBUGTRAP\000"
1501 /* 3207 */ "G_UBSANTRAP\000"
1502 /* 3219 */ "G_TRAP\000"
1503 /* 3226 */ "G_ATOMICRMW_UDEC_WRAP\000"
1504 /* 3248 */ "G_ATOMICRMW_UINC_WRAP\000"
1505 /* 3270 */ "G_BSWAP\000"
1506 /* 3278 */ "G_SITOFP\000"
1507 /* 3287 */ "G_UITOFP\000"
1508 /* 3296 */ "G_FCMP\000"
1509 /* 3303 */ "G_ICMP\000"
1510 /* 3310 */ "G_SCMP\000"
1511 /* 3317 */ "G_UCMP\000"
1512 /* 3324 */ "JMP\000"
1513 /* 3328 */ "NOP\000"
1514 /* 3332 */ "CONVERGENCECTRL_LOOP\000"
1515 /* 3353 */ "G_CTPOP\000"
1516 /* 3361 */ "PATCHABLE_OP\000"
1517 /* 3374 */ "FAULTING_OP\000"
1518 /* 3386 */ "ADJCALLSTACKUP\000"
1519 /* 3401 */ "PREALLOCATED_SETUP\000"
1520 /* 3420 */ "G_FLDEXP\000"
1521 /* 3429 */ "G_STRICT_FLDEXP\000"
1522 /* 3445 */ "G_FEXP\000"
1523 /* 3452 */ "G_FFREXP\000"
1524 /* 3461 */ "LDDACQ\000"
1525 /* 3468 */ "G_BR\000"
1526 /* 3473 */ "INLINEASM_BR\000"
1527 /* 3486 */ "G_BLOCK_ADDR\000"
1528 /* 3499 */ "MEMBARRIER\000"
1529 /* 3510 */ "G_CONSTANT_FOLD_BARRIER\000"
1530 /* 3534 */ "PATCHABLE_FUNCTION_ENTER\000"
1531 /* 3559 */ "G_READCYCLECOUNTER\000"
1532 /* 3578 */ "G_READSTEADYCOUNTER\000"
1533 /* 3598 */ "G_READ_REGISTER\000"
1534 /* 3614 */ "G_WRITE_REGISTER\000"
1535 /* 3631 */ "G_ASHR\000"
1536 /* 3638 */ "G_FSHR\000"
1537 /* 3645 */ "G_LSHR\000"
1538 /* 3652 */ "CONVERGENCECTRL_ANCHOR\000"
1539 /* 3675 */ "G_FFLOOR\000"
1540 /* 3684 */ "G_SAVGFLOOR\000"
1541 /* 3696 */ "G_UAVGFLOOR\000"
1542 /* 3708 */ "G_EXTRACT_SUBVECTOR\000"
1543 /* 3728 */ "G_INSERT_SUBVECTOR\000"
1544 /* 3747 */ "G_BUILD_VECTOR\000"
1545 /* 3762 */ "G_SHUFFLE_VECTOR\000"
1546 /* 3779 */ "G_STEP_VECTOR\000"
1547 /* 3793 */ "G_SPLAT_VECTOR\000"
1548 /* 3808 */ "G_VECREDUCE_XOR\000"
1549 /* 3824 */ "G_XOR\000"
1550 /* 3830 */ "G_ATOMICRMW_XOR\000"
1551 /* 3846 */ "G_VECREDUCE_OR\000"
1552 /* 3861 */ "G_OR\000"
1553 /* 3866 */ "G_ATOMICRMW_OR\000"
1554 /* 3881 */ "G_ROTR\000"
1555 /* 3888 */ "G_INTTOPTR\000"
1556 /* 3899 */ "G_FABS\000"
1557 /* 3906 */ "G_ABS\000"
1558 /* 3912 */ "G_ABDS\000"
1559 /* 3919 */ "G_UNMERGE_VALUES\000"
1560 /* 3936 */ "G_MERGE_VALUES\000"
1561 /* 3951 */ "G_CTLS\000"
1562 /* 3958 */ "G_FACOS\000"
1563 /* 3966 */ "G_FCOS\000"
1564 /* 3973 */ "G_FSINCOS\000"
1565 /* 3983 */ "G_CONCAT_VECTORS\000"
1566 /* 4000 */ "COPY_TO_REGCLASS\000"
1567 /* 4017 */ "G_IS_FPCLASS\000"
1568 /* 4030 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1569 /* 4060 */ "G_VECTOR_COMPRESS\000"
1570 /* 4078 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1571 /* 4105 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1572 /* 4143 */ "G_TRUNC_SSAT_S\000"
1573 /* 4158 */ "G_SSUBSAT\000"
1574 /* 4168 */ "G_USUBSAT\000"
1575 /* 4178 */ "G_SADDSAT\000"
1576 /* 4188 */ "G_UADDSAT\000"
1577 /* 4198 */ "G_SSHLSAT\000"
1578 /* 4208 */ "G_USHLSAT\000"
1579 /* 4218 */ "G_SMULFIXSAT\000"
1580 /* 4231 */ "G_UMULFIXSAT\000"
1581 /* 4244 */ "G_SDIVFIXSAT\000"
1582 /* 4257 */ "G_UDIVFIXSAT\000"
1583 /* 4270 */ "G_ATOMICRMW_USUB_SAT\000"
1584 /* 4291 */ "G_FPTOSI_SAT\000"
1585 /* 4304 */ "G_FPTOUI_SAT\000"
1586 /* 4317 */ "G_EXTRACT\000"
1587 /* 4327 */ "G_SELECT\000"
1588 /* 4336 */ "G_BRINDIRECT\000"
1589 /* 4349 */ "PATCHABLE_RET\000"
1590 /* 4363 */ "G_MEMSET\000"
1591 /* 4372 */ "CORE_SHIFT\000"
1592 /* 4383 */ "PATCHABLE_FUNCTION_EXIT\000"
1593 /* 4407 */ "G_BRJT\000"
1594 /* 4414 */ "G_EXTRACT_VECTOR_ELT\000"
1595 /* 4435 */ "G_INSERT_VECTOR_ELT\000"
1596 /* 4455 */ "G_FCONSTANT\000"
1597 /* 4467 */ "G_CONSTANT\000"
1598 /* 4478 */ "G_INTRINSIC_CONVERGENT\000"
1599 /* 4501 */ "STATEPOINT\000"
1600 /* 4512 */ "PATCHPOINT\000"
1601 /* 4523 */ "G_PTRTOINT\000"
1602 /* 4534 */ "G_FRINT\000"
1603 /* 4542 */ "G_INTRINSIC_LLRINT\000"
1604 /* 4561 */ "G_INTRINSIC_LRINT\000"
1605 /* 4579 */ "G_FNEARBYINT\000"
1606 /* 4592 */ "G_VASTART\000"
1607 /* 4602 */ "LIFETIME_START\000"
1608 /* 4617 */ "G_INVOKE_REGION_START\000"
1609 /* 4639 */ "G_INSERT\000"
1610 /* 4648 */ "G_FSQRT\000"
1611 /* 4656 */ "G_STRICT_FSQRT\000"
1612 /* 4671 */ "G_BITCAST\000"
1613 /* 4681 */ "G_ADDRSPACE_CAST\000"
1614 /* 4698 */ "ADDR_SPACE_CAST\000"
1615 /* 4714 */ "DBG_VALUE_LIST\000"
1616 /* 4729 */ "CORE_ST\000"
1617 /* 4737 */ "G_FPEXT\000"
1618 /* 4745 */ "G_SEXT\000"
1619 /* 4752 */ "G_ASSERT_SEXT\000"
1620 /* 4766 */ "G_ANYEXT\000"
1621 /* 4775 */ "G_ZEXT\000"
1622 /* 4782 */ "G_ASSERT_ZEXT\000"
1623 /* 4796 */ "G_ABDU\000"
1624 /* 4803 */ "G_TRUNC_SSAT_U\000"
1625 /* 4818 */ "G_TRUNC_USAT_U\000"
1626 /* 4833 */ "G_FDIV\000"
1627 /* 4840 */ "G_STRICT_FDIV\000"
1628 /* 4854 */ "G_SDIV\000"
1629 /* 4861 */ "G_UDIV\000"
1630 /* 4868 */ "G_GET_FPENV\000"
1631 /* 4880 */ "G_RESET_FPENV\000"
1632 /* 4894 */ "G_SET_FPENV\000"
1633 /* 4906 */ "XADDW\000"
1634 /* 4912 */ "LDW\000"
1635 /* 4916 */ "G_FPOW\000"
1636 /* 4923 */ "STW\000"
1637 /* 4927 */ "LD_IND_W\000"
1638 /* 4936 */ "LD_ABS_W\000"
1639 /* 4945 */ "G_VECREDUCE_FMAX\000"
1640 /* 4962 */ "G_ATOMICRMW_FMAX\000"
1641 /* 4979 */ "G_VECREDUCE_SMAX\000"
1642 /* 4996 */ "G_SMAX\000"
1643 /* 5003 */ "G_VECREDUCE_UMAX\000"
1644 /* 5020 */ "G_UMAX\000"
1645 /* 5027 */ "G_ATOMICRMW_UMAX\000"
1646 /* 5044 */ "G_ATOMICRMW_MAX\000"
1647 /* 5060 */ "G_FRAME_INDEX\000"
1648 /* 5074 */ "G_SBFX\000"
1649 /* 5081 */ "G_UBFX\000"
1650 /* 5088 */ "G_SMULFIX\000"
1651 /* 5098 */ "G_UMULFIX\000"
1652 /* 5108 */ "G_SDIVFIX\000"
1653 /* 5118 */ "G_UDIVFIX\000"
1654 /* 5128 */ "JX\000"
1655 /* 5131 */ "JALX\000"
1656 /* 5136 */ "LDBSX\000"
1657 /* 5142 */ "LDHSX\000"
1658 /* 5148 */ "LDWSX\000"
1659 /* 5154 */ "G_MEMCPY\000"
1660 /* 5163 */ "COPY\000"
1661 /* 5168 */ "CONVERGENCECTRL_ENTRY\000"
1662 /* 5190 */ "G_CTLZ\000"
1663 /* 5197 */ "G_CTTZ\000"
1664 /* 5204 */ "Select_Ri\000"
1665 /* 5214 */ "SRA_ri\000"
1666 /* 5221 */ "SUB_ri\000"
1667 /* 5228 */ "ADD_ri\000"
1668 /* 5235 */ "AND_ri\000"
1669 /* 5242 */ "SMOD_ri\000"
1670 /* 5250 */ "JSGE_ri\000"
1671 /* 5258 */ "JUGE_ri\000"
1672 /* 5266 */ "JSLE_ri\000"
1673 /* 5274 */ "JULE_ri\000"
1674 /* 5282 */ "JNE_ri\000"
1675 /* 5289 */ "FI_ri\000"
1676 /* 5295 */ "SLL_ri\000"
1677 /* 5302 */ "SRL_ri\000"
1678 /* 5309 */ "MUL_ri\000"
1679 /* 5316 */ "JEQ_ri\000"
1680 /* 5323 */ "XOR_ri\000"
1681 /* 5330 */ "JSET_ri\000"
1682 /* 5338 */ "JSGT_ri\000"
1683 /* 5346 */ "JUGT_ri\000"
1684 /* 5354 */ "JSLT_ri\000"
1685 /* 5362 */ "JULT_ri\000"
1686 /* 5370 */ "SDIV_ri\000"
1687 /* 5378 */ "MOV_ri\000"
1688 /* 5385 */ "STB_imm\000"
1689 /* 5393 */ "STD_imm\000"
1690 /* 5401 */ "STH_imm\000"
1691 /* 5409 */ "STW_imm\000"
1692 /* 5417 */ "LD_pseudo\000"
1693 /* 5427 */ "SRA_rr\000"
1694 /* 5434 */ "SUB_rr\000"
1695 /* 5441 */ "ADD_rr\000"
1696 /* 5448 */ "AND_rr\000"
1697 /* 5455 */ "SMOD_rr\000"
1698 /* 5463 */ "JSGE_rr\000"
1699 /* 5471 */ "JUGE_rr\000"
1700 /* 5479 */ "JSLE_rr\000"
1701 /* 5487 */ "JULE_rr\000"
1702 /* 5495 */ "JNE_rr\000"
1703 /* 5502 */ "SLL_rr\000"
1704 /* 5509 */ "SRL_rr\000"
1705 /* 5516 */ "MUL_rr\000"
1706 /* 5523 */ "JEQ_rr\000"
1707 /* 5530 */ "XOR_rr\000"
1708 /* 5537 */ "JSET_rr\000"
1709 /* 5545 */ "JSGT_rr\000"
1710 /* 5553 */ "JUGT_rr\000"
1711 /* 5561 */ "JSLT_rr\000"
1712 /* 5569 */ "JULT_rr\000"
1713 /* 5577 */ "SDIV_rr\000"
1714 /* 5585 */ "MOV_rr\000"
1715 /* 5592 */ "Select\000"
1716};
1717#ifdef __GNUC__
1718#pragma GCC diagnostic pop
1719#endif
1720
1721extern const unsigned BPFInstrNameIndices[] = {
1722 2295U, 2717U, 3473U, 3075U, 2372U, 2353U, 2381U, 2548U,
1723 2062U, 2077U, 2028U, 2015U, 2104U, 4000U, 1855U, 4714U,
1724 2041U, 2291U, 2362U, 1625U, 5163U, 2325U, 1747U, 4602U,
1725 1423U, 1576U, 1613U, 3186U, 2536U, 4512U, 1536U, 3401U,
1726 2197U, 4501U, 1781U, 3374U, 3361U, 3534U, 4349U, 4383U,
1727 2468U, 2515U, 2488U, 2398U, 1846U, 3499U, 3140U, 1770U,
1728 5168U, 3652U, 3332U, 1903U, 4752U, 4782U, 2918U, 1297U,
1729 990U, 2656U, 4854U, 4861U, 2683U, 2690U, 2697U, 2707U,
1730 1401U, 3861U, 3824U, 3912U, 4796U, 3696U, 2457U, 3684U,
1731 2446U, 2026U, 2293U, 5060U, 1865U, 1880U, 2553U, 4317U,
1732 3919U, 4639U, 3936U, 3747U, 1078U, 3983U, 4523U, 3888U,
1733 4671U, 1946U, 3510U, 1510U, 1052U, 1492U, 4561U, 4542U,
1734 2896U, 3559U, 3578U, 1198U, 1142U, 1172U, 1183U, 1123U,
1735 1153U, 1825U, 1809U, 4030U, 2118U, 2135U, 1313U, 996U,
1736 1407U, 1368U, 3866U, 3830U, 5044U, 3044U, 5027U, 3027U,
1737 1264U, 973U, 4962U, 2962U, 2812U, 2759U, 3248U, 3226U,
1738 1451U, 4270U, 1605U, 2214U, 1442U, 4336U, 4617U, 1030U,
1739 4078U, 4478U, 4105U, 4766U, 1070U, 4143U, 4803U, 4818U,
1740 4467U, 4455U, 4592U, 2189U, 4745U, 2091U, 4775U, 2432U,
1741 3645U, 3631U, 2425U, 3638U, 3881U, 2574U, 3303U, 3296U,
1742 3310U, 3317U, 4327U, 3132U, 1646U, 3116U, 1597U, 3124U,
1743 1638U, 3108U, 1589U, 3170U, 3162U, 2237U, 2229U, 4188U,
1744 4178U, 4168U, 4158U, 4208U, 4198U, 5088U, 5098U, 4218U,
1745 4231U, 5108U, 5118U, 4244U, 4257U, 1222U, 952U, 2598U,
1746 925U, 1116U, 4833U, 2662U, 1971U, 4916U, 2317U, 3445U,
1747 756U, 9U, 2182U, 739U, 0U, 3420U, 3452U, 2055U,
1748 4737U, 1042U, 2299U, 2308U, 3278U, 3287U, 4291U, 4304U,
1749 3899U, 2933U, 4017U, 1955U, 2861U, 2871U, 1695U, 1710U,
1750 2748U, 2801U, 2833U, 2847U, 4868U, 4894U, 4880U, 1654U,
1751 1682U, 1667U, 2152U, 2167U, 1303U, 2339U, 2996U, 4996U,
1752 3020U, 5020U, 3906U, 1483U, 1473U, 3468U, 4407U, 1725U,
1753 3728U, 3708U, 4435U, 4414U, 3762U, 3793U, 3779U, 4060U,
1754 5197U, 1997U, 5190U, 1979U, 3951U, 3353U, 3270U, 1833U,
1755 2438U, 3966U, 3068U, 3973U, 2889U, 3958U, 3060U, 2881U,
1756 747U, 2261U, 2253U, 2245U, 4648U, 3675U, 4534U, 4579U,
1757 4681U, 3486U, 1734U, 1099U, 1924U, 1794U, 1250U, 959U,
1758 2626U, 4840U, 2669U, 931U, 4656U, 3429U, 3598U, 3614U,
1759 5154U, 1754U, 1936U, 4363U, 3178U, 3219U, 3195U, 3207U,
1760 1229U, 2605U, 1205U, 2581U, 4945U, 2945U, 2780U, 2727U,
1761 1281U, 2640U, 1385U, 3846U, 3808U, 4979U, 2979U, 5003U,
1762 3003U, 5074U, 5081U, 3091U, 3386U, 5289U, 784U, 5156U,
1763 5592U, 729U, 826U, 222U, 5204U, 242U, 810U, 206U,
1764 4698U, 5228U, 275U, 5441U, 506U, 5235U, 285U, 5448U,
1765 516U, 855U, 40U, 774U, 865U, 89U, 792U, 1359U,
1766 164U, 30U, 764U, 4372U, 4729U, 5371U, 466U, 5578U,
1767 697U, 2349U, 5131U, 1436U, 5316U, 390U, 5523U, 621U,
1768 3324U, 2569U, 5282U, 350U, 5495U, 581U, 5330U, 410U,
1769 5537U, 641U, 5250U, 306U, 5463U, 537U, 5338U, 421U,
1770 5545U, 652U, 5266U, 328U, 5479U, 559U, 5354U, 443U,
1771 5561U, 674U, 5258U, 317U, 5471U, 548U, 5346U, 432U,
1772 5553U, 663U, 5274U, 339U, 5487U, 570U, 5362U, 454U,
1773 5569U, 685U, 5128U, 944U, 18U, 97U, 5136U, 1342U,
1774 3461U, 2225U, 50U, 106U, 5142U, 4912U, 141U, 115U,
1775 5148U, 1021U, 2282U, 4936U, 1012U, 2273U, 4927U, 846U,
1776 5417U, 860U, 45U, 779U, 5243U, 296U, 5456U, 527U,
1777 888U, 717U, 873U, 900U, 914U, 800U, 5378U, 476U,
1778 5585U, 707U, 5309U, 380U, 5516U, 611U, 235U, 839U,
1779 3328U, 5324U, 401U, 5531U, 632U, 4359U, 5370U, 465U,
1780 5577U, 696U, 5295U, 360U, 5502U, 591U, 5242U, 295U,
1781 5455U, 526U, 5214U, 255U, 5427U, 486U, 5302U, 370U,
1782 5509U, 601U, 948U, 24U, 62U, 5385U, 1572U, 2418U,
1783 5393U, 2269U, 56U, 71U, 5401U, 4923U, 200U, 80U,
1784 5409U, 5221U, 265U, 5434U, 496U, 1336U, 4906U, 133U,
1785 1353U, 156U, 1362U, 167U, 1329U, 124U, 1346U, 147U,
1786 1553U, 175U, 1559U, 183U, 1561U, 185U, 5323U, 400U,
1787 5530U, 631U, 1566U, 192U,
1788};
1789
1790static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
1791 II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 524, nullptr, 0);
1792}
1793
1794
1795} // namespace llvm
1796
1797#endif // GET_INSTRINFO_MC_DESC
1798
1799#ifdef GET_INSTRINFO_HEADER
1800#undef GET_INSTRINFO_HEADER
1801
1802namespace llvm {
1803
1804struct BPFGenInstrInfo : public TargetInstrInfo {
1805 explicit BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1806 ~BPFGenInstrInfo() override = default;
1807};
1808
1809} // namespace llvm
1810
1811namespace llvm::BPF {
1812
1813
1814} // namespace llvm::BPF
1815
1816#endif // GET_INSTRINFO_HEADER
1817
1818#ifdef GET_INSTRINFO_HELPER_DECLS
1819#undef GET_INSTRINFO_HELPER_DECLS
1820
1821
1822#endif // GET_INSTRINFO_HELPER_DECLS
1823
1824#ifdef GET_INSTRINFO_HELPERS
1825#undef GET_INSTRINFO_HELPERS
1826
1827
1828#endif // GET_INSTRINFO_HELPERS
1829
1830#ifdef GET_INSTRINFO_CTOR_DTOR
1831#undef GET_INSTRINFO_CTOR_DTOR
1832
1833namespace llvm {
1834
1835extern const BPFInstrTable BPFDescs;
1836extern const unsigned BPFInstrNameIndices[];
1837extern const char BPFInstrNameData[];
1838BPFGenInstrInfo::BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1839 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1840 InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 524);
1841}
1842
1843} // namespace llvm
1844
1845#endif // GET_INSTRINFO_CTOR_DTOR
1846
1847#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1848#undef GET_INSTRINFO_MC_HELPER_DECLS
1849
1850namespace llvm {
1851
1852class MCInst;
1853class FeatureBitset;
1854
1855namespace BPF_MC {
1856
1857void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1858
1859} // namespace BPF_MC
1860
1861} // namespace llvm
1862
1863#endif // GET_INSTRINFO_MC_HELPER_DECLS
1864
1865#ifdef GET_INSTRINFO_MC_HELPERS
1866#undef GET_INSTRINFO_MC_HELPERS
1867
1868namespace llvm::BPF_MC {
1869
1870
1871} // namespace llvm::BPF_MC
1872
1873#endif // GET_INSTRINFO_MC_HELPERS
1874
1875#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1876 defined(GET_AVAILABLE_OPCODE_CHECKER)
1877#define GET_COMPUTE_FEATURES
1878#endif
1879#ifdef GET_COMPUTE_FEATURES
1880#undef GET_COMPUTE_FEATURES
1881
1882namespace llvm::BPF_MC {
1883
1884// Bits for subtarget features that participate in instruction matching.
1885enum SubtargetFeatureBits : uint8_t {
1886};
1887
1888inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1889 FeatureBitset Features;
1890 return Features;
1891}
1892
1893inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1894 enum : uint8_t {
1895 CEFBS_None,
1896 };
1897
1898 static constexpr FeatureBitset FeatureBitsets[] = {
1899 {}, // CEFBS_None
1900 };
1901 static constexpr uint8_t RequiredFeaturesRefs[] = {
1902 CEFBS_None, // PHI
1903 CEFBS_None, // INLINEASM
1904 CEFBS_None, // INLINEASM_BR
1905 CEFBS_None, // CFI_INSTRUCTION
1906 CEFBS_None, // EH_LABEL
1907 CEFBS_None, // GC_LABEL
1908 CEFBS_None, // ANNOTATION_LABEL
1909 CEFBS_None, // KILL
1910 CEFBS_None, // EXTRACT_SUBREG
1911 CEFBS_None, // INSERT_SUBREG
1912 CEFBS_None, // IMPLICIT_DEF
1913 CEFBS_None, // INIT_UNDEF
1914 CEFBS_None, // SUBREG_TO_REG
1915 CEFBS_None, // COPY_TO_REGCLASS
1916 CEFBS_None, // DBG_VALUE
1917 CEFBS_None, // DBG_VALUE_LIST
1918 CEFBS_None, // DBG_INSTR_REF
1919 CEFBS_None, // DBG_PHI
1920 CEFBS_None, // DBG_LABEL
1921 CEFBS_None, // REG_SEQUENCE
1922 CEFBS_None, // COPY
1923 CEFBS_None, // COPY_LANEMASK
1924 CEFBS_None, // BUNDLE
1925 CEFBS_None, // LIFETIME_START
1926 CEFBS_None, // LIFETIME_END
1927 CEFBS_None, // PSEUDO_PROBE
1928 CEFBS_None, // ARITH_FENCE
1929 CEFBS_None, // STACKMAP
1930 CEFBS_None, // FENTRY_CALL
1931 CEFBS_None, // PATCHPOINT
1932 CEFBS_None, // LOAD_STACK_GUARD
1933 CEFBS_None, // PREALLOCATED_SETUP
1934 CEFBS_None, // PREALLOCATED_ARG
1935 CEFBS_None, // STATEPOINT
1936 CEFBS_None, // LOCAL_ESCAPE
1937 CEFBS_None, // FAULTING_OP
1938 CEFBS_None, // PATCHABLE_OP
1939 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1940 CEFBS_None, // PATCHABLE_RET
1941 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1942 CEFBS_None, // PATCHABLE_TAIL_CALL
1943 CEFBS_None, // PATCHABLE_EVENT_CALL
1944 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1945 CEFBS_None, // ICALL_BRANCH_FUNNEL
1946 CEFBS_None, // FAKE_USE
1947 CEFBS_None, // MEMBARRIER
1948 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1949 CEFBS_None, // RELOC_NONE
1950 CEFBS_None, // CONVERGENCECTRL_ENTRY
1951 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1952 CEFBS_None, // CONVERGENCECTRL_LOOP
1953 CEFBS_None, // CONVERGENCECTRL_GLUE
1954 CEFBS_None, // G_ASSERT_SEXT
1955 CEFBS_None, // G_ASSERT_ZEXT
1956 CEFBS_None, // G_ASSERT_ALIGN
1957 CEFBS_None, // G_ADD
1958 CEFBS_None, // G_SUB
1959 CEFBS_None, // G_MUL
1960 CEFBS_None, // G_SDIV
1961 CEFBS_None, // G_UDIV
1962 CEFBS_None, // G_SREM
1963 CEFBS_None, // G_UREM
1964 CEFBS_None, // G_SDIVREM
1965 CEFBS_None, // G_UDIVREM
1966 CEFBS_None, // G_AND
1967 CEFBS_None, // G_OR
1968 CEFBS_None, // G_XOR
1969 CEFBS_None, // G_ABDS
1970 CEFBS_None, // G_ABDU
1971 CEFBS_None, // G_UAVGFLOOR
1972 CEFBS_None, // G_UAVGCEIL
1973 CEFBS_None, // G_SAVGFLOOR
1974 CEFBS_None, // G_SAVGCEIL
1975 CEFBS_None, // G_IMPLICIT_DEF
1976 CEFBS_None, // G_PHI
1977 CEFBS_None, // G_FRAME_INDEX
1978 CEFBS_None, // G_GLOBAL_VALUE
1979 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
1980 CEFBS_None, // G_CONSTANT_POOL
1981 CEFBS_None, // G_EXTRACT
1982 CEFBS_None, // G_UNMERGE_VALUES
1983 CEFBS_None, // G_INSERT
1984 CEFBS_None, // G_MERGE_VALUES
1985 CEFBS_None, // G_BUILD_VECTOR
1986 CEFBS_None, // G_BUILD_VECTOR_TRUNC
1987 CEFBS_None, // G_CONCAT_VECTORS
1988 CEFBS_None, // G_PTRTOINT
1989 CEFBS_None, // G_INTTOPTR
1990 CEFBS_None, // G_BITCAST
1991 CEFBS_None, // G_FREEZE
1992 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
1993 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
1994 CEFBS_None, // G_INTRINSIC_TRUNC
1995 CEFBS_None, // G_INTRINSIC_ROUND
1996 CEFBS_None, // G_INTRINSIC_LRINT
1997 CEFBS_None, // G_INTRINSIC_LLRINT
1998 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
1999 CEFBS_None, // G_READCYCLECOUNTER
2000 CEFBS_None, // G_READSTEADYCOUNTER
2001 CEFBS_None, // G_LOAD
2002 CEFBS_None, // G_SEXTLOAD
2003 CEFBS_None, // G_ZEXTLOAD
2004 CEFBS_None, // G_INDEXED_LOAD
2005 CEFBS_None, // G_INDEXED_SEXTLOAD
2006 CEFBS_None, // G_INDEXED_ZEXTLOAD
2007 CEFBS_None, // G_STORE
2008 CEFBS_None, // G_INDEXED_STORE
2009 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2010 CEFBS_None, // G_ATOMIC_CMPXCHG
2011 CEFBS_None, // G_ATOMICRMW_XCHG
2012 CEFBS_None, // G_ATOMICRMW_ADD
2013 CEFBS_None, // G_ATOMICRMW_SUB
2014 CEFBS_None, // G_ATOMICRMW_AND
2015 CEFBS_None, // G_ATOMICRMW_NAND
2016 CEFBS_None, // G_ATOMICRMW_OR
2017 CEFBS_None, // G_ATOMICRMW_XOR
2018 CEFBS_None, // G_ATOMICRMW_MAX
2019 CEFBS_None, // G_ATOMICRMW_MIN
2020 CEFBS_None, // G_ATOMICRMW_UMAX
2021 CEFBS_None, // G_ATOMICRMW_UMIN
2022 CEFBS_None, // G_ATOMICRMW_FADD
2023 CEFBS_None, // G_ATOMICRMW_FSUB
2024 CEFBS_None, // G_ATOMICRMW_FMAX
2025 CEFBS_None, // G_ATOMICRMW_FMIN
2026 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2027 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2028 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2029 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2030 CEFBS_None, // G_ATOMICRMW_USUB_COND
2031 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2032 CEFBS_None, // G_FENCE
2033 CEFBS_None, // G_PREFETCH
2034 CEFBS_None, // G_BRCOND
2035 CEFBS_None, // G_BRINDIRECT
2036 CEFBS_None, // G_INVOKE_REGION_START
2037 CEFBS_None, // G_INTRINSIC
2038 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2039 CEFBS_None, // G_INTRINSIC_CONVERGENT
2040 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2041 CEFBS_None, // G_ANYEXT
2042 CEFBS_None, // G_TRUNC
2043 CEFBS_None, // G_TRUNC_SSAT_S
2044 CEFBS_None, // G_TRUNC_SSAT_U
2045 CEFBS_None, // G_TRUNC_USAT_U
2046 CEFBS_None, // G_CONSTANT
2047 CEFBS_None, // G_FCONSTANT
2048 CEFBS_None, // G_VASTART
2049 CEFBS_None, // G_VAARG
2050 CEFBS_None, // G_SEXT
2051 CEFBS_None, // G_SEXT_INREG
2052 CEFBS_None, // G_ZEXT
2053 CEFBS_None, // G_SHL
2054 CEFBS_None, // G_LSHR
2055 CEFBS_None, // G_ASHR
2056 CEFBS_None, // G_FSHL
2057 CEFBS_None, // G_FSHR
2058 CEFBS_None, // G_ROTR
2059 CEFBS_None, // G_ROTL
2060 CEFBS_None, // G_ICMP
2061 CEFBS_None, // G_FCMP
2062 CEFBS_None, // G_SCMP
2063 CEFBS_None, // G_UCMP
2064 CEFBS_None, // G_SELECT
2065 CEFBS_None, // G_UADDO
2066 CEFBS_None, // G_UADDE
2067 CEFBS_None, // G_USUBO
2068 CEFBS_None, // G_USUBE
2069 CEFBS_None, // G_SADDO
2070 CEFBS_None, // G_SADDE
2071 CEFBS_None, // G_SSUBO
2072 CEFBS_None, // G_SSUBE
2073 CEFBS_None, // G_UMULO
2074 CEFBS_None, // G_SMULO
2075 CEFBS_None, // G_UMULH
2076 CEFBS_None, // G_SMULH
2077 CEFBS_None, // G_UADDSAT
2078 CEFBS_None, // G_SADDSAT
2079 CEFBS_None, // G_USUBSAT
2080 CEFBS_None, // G_SSUBSAT
2081 CEFBS_None, // G_USHLSAT
2082 CEFBS_None, // G_SSHLSAT
2083 CEFBS_None, // G_SMULFIX
2084 CEFBS_None, // G_UMULFIX
2085 CEFBS_None, // G_SMULFIXSAT
2086 CEFBS_None, // G_UMULFIXSAT
2087 CEFBS_None, // G_SDIVFIX
2088 CEFBS_None, // G_UDIVFIX
2089 CEFBS_None, // G_SDIVFIXSAT
2090 CEFBS_None, // G_UDIVFIXSAT
2091 CEFBS_None, // G_FADD
2092 CEFBS_None, // G_FSUB
2093 CEFBS_None, // G_FMUL
2094 CEFBS_None, // G_FMA
2095 CEFBS_None, // G_FMAD
2096 CEFBS_None, // G_FDIV
2097 CEFBS_None, // G_FREM
2098 CEFBS_None, // G_FMODF
2099 CEFBS_None, // G_FPOW
2100 CEFBS_None, // G_FPOWI
2101 CEFBS_None, // G_FEXP
2102 CEFBS_None, // G_FEXP2
2103 CEFBS_None, // G_FEXP10
2104 CEFBS_None, // G_FLOG
2105 CEFBS_None, // G_FLOG2
2106 CEFBS_None, // G_FLOG10
2107 CEFBS_None, // G_FLDEXP
2108 CEFBS_None, // G_FFREXP
2109 CEFBS_None, // G_FNEG
2110 CEFBS_None, // G_FPEXT
2111 CEFBS_None, // G_FPTRUNC
2112 CEFBS_None, // G_FPTOSI
2113 CEFBS_None, // G_FPTOUI
2114 CEFBS_None, // G_SITOFP
2115 CEFBS_None, // G_UITOFP
2116 CEFBS_None, // G_FPTOSI_SAT
2117 CEFBS_None, // G_FPTOUI_SAT
2118 CEFBS_None, // G_FABS
2119 CEFBS_None, // G_FCOPYSIGN
2120 CEFBS_None, // G_IS_FPCLASS
2121 CEFBS_None, // G_FCANONICALIZE
2122 CEFBS_None, // G_FMINNUM
2123 CEFBS_None, // G_FMAXNUM
2124 CEFBS_None, // G_FMINNUM_IEEE
2125 CEFBS_None, // G_FMAXNUM_IEEE
2126 CEFBS_None, // G_FMINIMUM
2127 CEFBS_None, // G_FMAXIMUM
2128 CEFBS_None, // G_FMINIMUMNUM
2129 CEFBS_None, // G_FMAXIMUMNUM
2130 CEFBS_None, // G_GET_FPENV
2131 CEFBS_None, // G_SET_FPENV
2132 CEFBS_None, // G_RESET_FPENV
2133 CEFBS_None, // G_GET_FPMODE
2134 CEFBS_None, // G_SET_FPMODE
2135 CEFBS_None, // G_RESET_FPMODE
2136 CEFBS_None, // G_GET_ROUNDING
2137 CEFBS_None, // G_SET_ROUNDING
2138 CEFBS_None, // G_PTR_ADD
2139 CEFBS_None, // G_PTRMASK
2140 CEFBS_None, // G_SMIN
2141 CEFBS_None, // G_SMAX
2142 CEFBS_None, // G_UMIN
2143 CEFBS_None, // G_UMAX
2144 CEFBS_None, // G_ABS
2145 CEFBS_None, // G_LROUND
2146 CEFBS_None, // G_LLROUND
2147 CEFBS_None, // G_BR
2148 CEFBS_None, // G_BRJT
2149 CEFBS_None, // G_VSCALE
2150 CEFBS_None, // G_INSERT_SUBVECTOR
2151 CEFBS_None, // G_EXTRACT_SUBVECTOR
2152 CEFBS_None, // G_INSERT_VECTOR_ELT
2153 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2154 CEFBS_None, // G_SHUFFLE_VECTOR
2155 CEFBS_None, // G_SPLAT_VECTOR
2156 CEFBS_None, // G_STEP_VECTOR
2157 CEFBS_None, // G_VECTOR_COMPRESS
2158 CEFBS_None, // G_CTTZ
2159 CEFBS_None, // G_CTTZ_ZERO_UNDEF
2160 CEFBS_None, // G_CTLZ
2161 CEFBS_None, // G_CTLZ_ZERO_UNDEF
2162 CEFBS_None, // G_CTLS
2163 CEFBS_None, // G_CTPOP
2164 CEFBS_None, // G_BSWAP
2165 CEFBS_None, // G_BITREVERSE
2166 CEFBS_None, // G_FCEIL
2167 CEFBS_None, // G_FCOS
2168 CEFBS_None, // G_FSIN
2169 CEFBS_None, // G_FSINCOS
2170 CEFBS_None, // G_FTAN
2171 CEFBS_None, // G_FACOS
2172 CEFBS_None, // G_FASIN
2173 CEFBS_None, // G_FATAN
2174 CEFBS_None, // G_FATAN2
2175 CEFBS_None, // G_FCOSH
2176 CEFBS_None, // G_FSINH
2177 CEFBS_None, // G_FTANH
2178 CEFBS_None, // G_FSQRT
2179 CEFBS_None, // G_FFLOOR
2180 CEFBS_None, // G_FRINT
2181 CEFBS_None, // G_FNEARBYINT
2182 CEFBS_None, // G_ADDRSPACE_CAST
2183 CEFBS_None, // G_BLOCK_ADDR
2184 CEFBS_None, // G_JUMP_TABLE
2185 CEFBS_None, // G_DYN_STACKALLOC
2186 CEFBS_None, // G_STACKSAVE
2187 CEFBS_None, // G_STACKRESTORE
2188 CEFBS_None, // G_STRICT_FADD
2189 CEFBS_None, // G_STRICT_FSUB
2190 CEFBS_None, // G_STRICT_FMUL
2191 CEFBS_None, // G_STRICT_FDIV
2192 CEFBS_None, // G_STRICT_FREM
2193 CEFBS_None, // G_STRICT_FMA
2194 CEFBS_None, // G_STRICT_FSQRT
2195 CEFBS_None, // G_STRICT_FLDEXP
2196 CEFBS_None, // G_READ_REGISTER
2197 CEFBS_None, // G_WRITE_REGISTER
2198 CEFBS_None, // G_MEMCPY
2199 CEFBS_None, // G_MEMCPY_INLINE
2200 CEFBS_None, // G_MEMMOVE
2201 CEFBS_None, // G_MEMSET
2202 CEFBS_None, // G_BZERO
2203 CEFBS_None, // G_TRAP
2204 CEFBS_None, // G_DEBUGTRAP
2205 CEFBS_None, // G_UBSANTRAP
2206 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2207 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2208 CEFBS_None, // G_VECREDUCE_FADD
2209 CEFBS_None, // G_VECREDUCE_FMUL
2210 CEFBS_None, // G_VECREDUCE_FMAX
2211 CEFBS_None, // G_VECREDUCE_FMIN
2212 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2213 CEFBS_None, // G_VECREDUCE_FMINIMUM
2214 CEFBS_None, // G_VECREDUCE_ADD
2215 CEFBS_None, // G_VECREDUCE_MUL
2216 CEFBS_None, // G_VECREDUCE_AND
2217 CEFBS_None, // G_VECREDUCE_OR
2218 CEFBS_None, // G_VECREDUCE_XOR
2219 CEFBS_None, // G_VECREDUCE_SMAX
2220 CEFBS_None, // G_VECREDUCE_SMIN
2221 CEFBS_None, // G_VECREDUCE_UMAX
2222 CEFBS_None, // G_VECREDUCE_UMIN
2223 CEFBS_None, // G_SBFX
2224 CEFBS_None, // G_UBFX
2225 CEFBS_None, // ADJCALLSTACKDOWN
2226 CEFBS_None, // ADJCALLSTACKUP
2227 CEFBS_None, // FI_ri
2228 CEFBS_None, // LDIMM64
2229 CEFBS_None, // MEMCPY
2230 CEFBS_None, // Select
2231 CEFBS_None, // Select_32
2232 CEFBS_None, // Select_32_64
2233 CEFBS_None, // Select_64_32
2234 CEFBS_None, // Select_Ri
2235 CEFBS_None, // Select_Ri_32
2236 CEFBS_None, // Select_Ri_32_64
2237 CEFBS_None, // Select_Ri_64_32
2238 CEFBS_None, // ADDR_SPACE_CAST
2239 CEFBS_None, // ADD_ri
2240 CEFBS_None, // ADD_ri_32
2241 CEFBS_None, // ADD_rr
2242 CEFBS_None, // ADD_rr_32
2243 CEFBS_None, // AND_ri
2244 CEFBS_None, // AND_ri_32
2245 CEFBS_None, // AND_rr
2246 CEFBS_None, // AND_rr_32
2247 CEFBS_None, // BE16
2248 CEFBS_None, // BE32
2249 CEFBS_None, // BE64
2250 CEFBS_None, // BSWAP16
2251 CEFBS_None, // BSWAP32
2252 CEFBS_None, // BSWAP64
2253 CEFBS_None, // CMPXCHGD
2254 CEFBS_None, // CMPXCHGW32
2255 CEFBS_None, // CORE_LD32
2256 CEFBS_None, // CORE_LD64
2257 CEFBS_None, // CORE_SHIFT
2258 CEFBS_None, // CORE_ST
2259 CEFBS_None, // DIV_ri
2260 CEFBS_None, // DIV_ri_32
2261 CEFBS_None, // DIV_rr
2262 CEFBS_None, // DIV_rr_32
2263 CEFBS_None, // JAL
2264 CEFBS_None, // JALX
2265 CEFBS_None, // JCOND
2266 CEFBS_None, // JEQ_ri
2267 CEFBS_None, // JEQ_ri_32
2268 CEFBS_None, // JEQ_rr
2269 CEFBS_None, // JEQ_rr_32
2270 CEFBS_None, // JMP
2271 CEFBS_None, // JMPL
2272 CEFBS_None, // JNE_ri
2273 CEFBS_None, // JNE_ri_32
2274 CEFBS_None, // JNE_rr
2275 CEFBS_None, // JNE_rr_32
2276 CEFBS_None, // JSET_ri
2277 CEFBS_None, // JSET_ri_32
2278 CEFBS_None, // JSET_rr
2279 CEFBS_None, // JSET_rr_32
2280 CEFBS_None, // JSGE_ri
2281 CEFBS_None, // JSGE_ri_32
2282 CEFBS_None, // JSGE_rr
2283 CEFBS_None, // JSGE_rr_32
2284 CEFBS_None, // JSGT_ri
2285 CEFBS_None, // JSGT_ri_32
2286 CEFBS_None, // JSGT_rr
2287 CEFBS_None, // JSGT_rr_32
2288 CEFBS_None, // JSLE_ri
2289 CEFBS_None, // JSLE_ri_32
2290 CEFBS_None, // JSLE_rr
2291 CEFBS_None, // JSLE_rr_32
2292 CEFBS_None, // JSLT_ri
2293 CEFBS_None, // JSLT_ri_32
2294 CEFBS_None, // JSLT_rr
2295 CEFBS_None, // JSLT_rr_32
2296 CEFBS_None, // JUGE_ri
2297 CEFBS_None, // JUGE_ri_32
2298 CEFBS_None, // JUGE_rr
2299 CEFBS_None, // JUGE_rr_32
2300 CEFBS_None, // JUGT_ri
2301 CEFBS_None, // JUGT_ri_32
2302 CEFBS_None, // JUGT_rr
2303 CEFBS_None, // JUGT_rr_32
2304 CEFBS_None, // JULE_ri
2305 CEFBS_None, // JULE_ri_32
2306 CEFBS_None, // JULE_rr
2307 CEFBS_None, // JULE_rr_32
2308 CEFBS_None, // JULT_ri
2309 CEFBS_None, // JULT_ri_32
2310 CEFBS_None, // JULT_rr
2311 CEFBS_None, // JULT_rr_32
2312 CEFBS_None, // JX
2313 CEFBS_None, // LDB
2314 CEFBS_None, // LDB32
2315 CEFBS_None, // LDBACQ32
2316 CEFBS_None, // LDBSX
2317 CEFBS_None, // LDD
2318 CEFBS_None, // LDDACQ
2319 CEFBS_None, // LDH
2320 CEFBS_None, // LDH32
2321 CEFBS_None, // LDHACQ32
2322 CEFBS_None, // LDHSX
2323 CEFBS_None, // LDW
2324 CEFBS_None, // LDW32
2325 CEFBS_None, // LDWACQ32
2326 CEFBS_None, // LDWSX
2327 CEFBS_None, // LD_ABS_B
2328 CEFBS_None, // LD_ABS_H
2329 CEFBS_None, // LD_ABS_W
2330 CEFBS_None, // LD_IND_B
2331 CEFBS_None, // LD_IND_H
2332 CEFBS_None, // LD_IND_W
2333 CEFBS_None, // LD_imm64
2334 CEFBS_None, // LD_pseudo
2335 CEFBS_None, // LE16
2336 CEFBS_None, // LE32
2337 CEFBS_None, // LE64
2338 CEFBS_None, // MOD_ri
2339 CEFBS_None, // MOD_ri_32
2340 CEFBS_None, // MOD_rr
2341 CEFBS_None, // MOD_rr_32
2342 CEFBS_None, // MOVSX_rr_16
2343 CEFBS_None, // MOVSX_rr_32
2344 CEFBS_None, // MOVSX_rr_32_16
2345 CEFBS_None, // MOVSX_rr_32_8
2346 CEFBS_None, // MOVSX_rr_8
2347 CEFBS_None, // MOV_32_64
2348 CEFBS_None, // MOV_ri
2349 CEFBS_None, // MOV_ri_32
2350 CEFBS_None, // MOV_rr
2351 CEFBS_None, // MOV_rr_32
2352 CEFBS_None, // MUL_ri
2353 CEFBS_None, // MUL_ri_32
2354 CEFBS_None, // MUL_rr
2355 CEFBS_None, // MUL_rr_32
2356 CEFBS_None, // NEG_32
2357 CEFBS_None, // NEG_64
2358 CEFBS_None, // NOP
2359 CEFBS_None, // OR_ri
2360 CEFBS_None, // OR_ri_32
2361 CEFBS_None, // OR_rr
2362 CEFBS_None, // OR_rr_32
2363 CEFBS_None, // RET
2364 CEFBS_None, // SDIV_ri
2365 CEFBS_None, // SDIV_ri_32
2366 CEFBS_None, // SDIV_rr
2367 CEFBS_None, // SDIV_rr_32
2368 CEFBS_None, // SLL_ri
2369 CEFBS_None, // SLL_ri_32
2370 CEFBS_None, // SLL_rr
2371 CEFBS_None, // SLL_rr_32
2372 CEFBS_None, // SMOD_ri
2373 CEFBS_None, // SMOD_ri_32
2374 CEFBS_None, // SMOD_rr
2375 CEFBS_None, // SMOD_rr_32
2376 CEFBS_None, // SRA_ri
2377 CEFBS_None, // SRA_ri_32
2378 CEFBS_None, // SRA_rr
2379 CEFBS_None, // SRA_rr_32
2380 CEFBS_None, // SRL_ri
2381 CEFBS_None, // SRL_ri_32
2382 CEFBS_None, // SRL_rr
2383 CEFBS_None, // SRL_rr_32
2384 CEFBS_None, // STB
2385 CEFBS_None, // STB32
2386 CEFBS_None, // STBREL32
2387 CEFBS_None, // STB_imm
2388 CEFBS_None, // STD
2389 CEFBS_None, // STDREL
2390 CEFBS_None, // STD_imm
2391 CEFBS_None, // STH
2392 CEFBS_None, // STH32
2393 CEFBS_None, // STHREL32
2394 CEFBS_None, // STH_imm
2395 CEFBS_None, // STW
2396 CEFBS_None, // STW32
2397 CEFBS_None, // STWREL32
2398 CEFBS_None, // STW_imm
2399 CEFBS_None, // SUB_ri
2400 CEFBS_None, // SUB_ri_32
2401 CEFBS_None, // SUB_rr
2402 CEFBS_None, // SUB_rr_32
2403 CEFBS_None, // XADDD
2404 CEFBS_None, // XADDW
2405 CEFBS_None, // XADDW32
2406 CEFBS_None, // XANDD
2407 CEFBS_None, // XANDW32
2408 CEFBS_None, // XCHGD
2409 CEFBS_None, // XCHGW32
2410 CEFBS_None, // XFADDD
2411 CEFBS_None, // XFADDW32
2412 CEFBS_None, // XFANDD
2413 CEFBS_None, // XFANDW32
2414 CEFBS_None, // XFORD
2415 CEFBS_None, // XFORW32
2416 CEFBS_None, // XFXORD
2417 CEFBS_None, // XFXORW32
2418 CEFBS_None, // XORD
2419 CEFBS_None, // XORW32
2420 CEFBS_None, // XOR_ri
2421 CEFBS_None, // XOR_ri_32
2422 CEFBS_None, // XOR_rr
2423 CEFBS_None, // XOR_rr_32
2424 CEFBS_None, // XXORD
2425 CEFBS_None, // XXORW32
2426 };
2427
2428 assert(Opcode < 524);
2429 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2430}
2431
2432
2433} // namespace llvm::BPF_MC
2434
2435#endif // GET_COMPUTE_FEATURES
2436
2437#ifdef GET_AVAILABLE_OPCODE_CHECKER
2438#undef GET_AVAILABLE_OPCODE_CHECKER
2439
2440namespace llvm::BPF_MC {
2441
2442bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2443 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2444 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2445 FeatureBitset MissingFeatures =
2446 (AvailableFeatures & RequiredFeatures) ^
2447 RequiredFeatures;
2448 return !MissingFeatures.any();
2449}
2450
2451} // namespace llvm::BPF_MC
2452
2453#endif // GET_AVAILABLE_OPCODE_CHECKER
2454
2455#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2456#undef ENABLE_INSTR_PREDICATE_VERIFIER
2457
2458#include <sstream>
2459
2460namespace llvm::BPF_MC {
2461
2462#ifndef NDEBUG
2463static const char *SubtargetFeatureNames[] = {
2464 nullptr
2465};
2466
2467#endif // NDEBUG
2468
2469void verifyInstructionPredicates(
2470 unsigned Opcode, const FeatureBitset &Features) {
2471#ifndef NDEBUG
2472 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2473 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2474 FeatureBitset MissingFeatures =
2475 (AvailableFeatures & RequiredFeatures) ^
2476 RequiredFeatures;
2477 if (MissingFeatures.any()) {
2478 std::ostringstream Msg;
2479 Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
2480 << " instruction but the ";
2481 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2482 if (MissingFeatures.test(i))
2483 Msg << SubtargetFeatureNames[i] << " ";
2484 Msg << "predicate(s) are not met";
2485 report_fatal_error(Msg.str().c_str());
2486 }
2487#endif // NDEBUG
2488}
2489
2490} // namespace llvm::BPF_MC
2491
2492#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2493
2494