1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::BPF {
13
14 enum {
15 PHI = 0, // Target.td:1329
16 INLINEASM = 1, // Target.td:1335
17 INLINEASM_BR = 2, // Target.td:1341
18 CFI_INSTRUCTION = 3, // Target.td:1350
19 EH_LABEL = 4, // Target.td:1359
20 GC_LABEL = 5, // Target.td:1368
21 ANNOTATION_LABEL = 6, // Target.td:1377
22 KILL = 7, // Target.td:1385
23 EXTRACT_SUBREG = 8, // Target.td:1392
24 INSERT_SUBREG = 9, // Target.td:1398
25 IMPLICIT_DEF = 10, // Target.td:1405
26 INIT_UNDEF = 11, // Target.td:1414
27 SUBREG_TO_REG = 12, // Target.td:1421
28 COPY_TO_REGCLASS = 13, // Target.td:1427
29 DBG_VALUE = 14, // Target.td:1434
30 DBG_VALUE_LIST = 15, // Target.td:1441
31 DBG_INSTR_REF = 16, // Target.td:1448
32 DBG_PHI = 17, // Target.td:1455
33 DBG_LABEL = 18, // Target.td:1462
34 REG_SEQUENCE = 19, // Target.td:1469
35 COPY = 20, // Target.td:1476
36 COPY_LANEMASK = 21, // Target.td:1484
37 BUNDLE = 22, // Target.td:1491
38 LIFETIME_START = 23, // Target.td:1497
39 LIFETIME_END = 24, // Target.td:1504
40 PSEUDO_PROBE = 25, // Target.td:1511
41 ARITH_FENCE = 26, // Target.td:1518
42 STACKMAP = 27, // Target.td:1527
43 FENTRY_CALL = 28, // Target.td:1662
44 PATCHPOINT = 29, // Target.td:1535
45 LOAD_STACK_GUARD = 30, // Target.td:1553
46 PREALLOCATED_SETUP = 31, // Target.td:1561
47 PREALLOCATED_ARG = 32, // Target.td:1567
48 STATEPOINT = 33, // Target.td:1544
49 LOCAL_ESCAPE = 34, // Target.td:1573
50 FAULTING_OP = 35, // Target.td:1582
51 PATCHABLE_OP = 36, // Target.td:1602
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1610
53 PATCHABLE_RET = 38, // Target.td:1617
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1626
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1634
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1642
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1652
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1672
59 FAKE_USE = 44, // Target.td:1592
60 MEMBARRIER = 45, // Target.td:1678
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1686
62 RELOC_NONE = 47, // Target.td:1694
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1706
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1702
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1710
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1714
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1937
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1929
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1944
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1522
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1535
96 G_INSERT = 81, // GenericOpcodes.td:1544
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1554
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1574
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1584
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1591
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1951
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1280
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1286
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1292
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1298
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1304
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1310
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1316
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1322
114 G_LOAD = 99, // GenericOpcodes.td:1349
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1358
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1366
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1375
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1385
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1394
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1402
121 G_STORE = 106, // GenericOpcodes.td:1410
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1420
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1428
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1439
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1450
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1470
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1471
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1472
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1473
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1474
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1475
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1476
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1477
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1478
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1479
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1480
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1491
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1492
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1493
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1494
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1495
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1496
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1497
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1498
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1481
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1482
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1483
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1484
149 G_FENCE = 134, // GenericOpcodes.td:1500
150 G_PREFETCH = 135, // GenericOpcodes.td:1507
151 G_BRCOND = 136, // GenericOpcodes.td:1647
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1656
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1679
154 G_INTRINSIC = 139, // GenericOpcodes.td:1599
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1606
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1615
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1623
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:601
183 G_UADDE = 168, // GenericOpcodes.td:609
184 G_USUBO = 169, // GenericOpcodes.td:631
185 G_USUBE = 170, // GenericOpcodes.td:637
186 G_SADDO = 171, // GenericOpcodes.td:616
187 G_SADDE = 172, // GenericOpcodes.td:624
188 G_SSUBO = 173, // GenericOpcodes.td:644
189 G_SSUBE = 174, // GenericOpcodes.td:651
190 G_UMULO = 175, // GenericOpcodes.td:658
191 G_SMULO = 176, // GenericOpcodes.td:666
192 G_UMULH = 177, // GenericOpcodes.td:675
193 G_SMULH = 178, // GenericOpcodes.td:684
194 G_UADDSAT = 179, // GenericOpcodes.td:696
195 G_SADDSAT = 180, // GenericOpcodes.td:704
196 G_USUBSAT = 181, // GenericOpcodes.td:712
197 G_SSUBSAT = 182, // GenericOpcodes.td:720
198 G_USHLSAT = 183, // GenericOpcodes.td:728
199 G_SSHLSAT = 184, // GenericOpcodes.td:736
200 G_SMULFIX = 185, // GenericOpcodes.td:748
201 G_UMULFIX = 186, // GenericOpcodes.td:755
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:765
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:772
204 G_SDIVFIX = 189, // GenericOpcodes.td:783
205 G_UDIVFIX = 190, // GenericOpcodes.td:790
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:800
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:807
208 G_FADD = 193, // GenericOpcodes.td:980
209 G_FSUB = 194, // GenericOpcodes.td:988
210 G_FMUL = 195, // GenericOpcodes.td:996
211 G_FMA = 196, // GenericOpcodes.td:1005
212 G_FMAD = 197, // GenericOpcodes.td:1014
213 G_FDIV = 198, // GenericOpcodes.td:1022
214 G_FREM = 199, // GenericOpcodes.td:1029
215 G_FMODF = 200, // GenericOpcodes.td:1036
216 G_FPOW = 201, // GenericOpcodes.td:1043
217 G_FPOWI = 202, // GenericOpcodes.td:1050
218 G_FEXP = 203, // GenericOpcodes.td:1057
219 G_FEXP2 = 204, // GenericOpcodes.td:1064
220 G_FEXP10 = 205, // GenericOpcodes.td:1071
221 G_FLOG = 206, // GenericOpcodes.td:1078
222 G_FLOG2 = 207, // GenericOpcodes.td:1085
223 G_FLOG10 = 208, // GenericOpcodes.td:1092
224 G_FLDEXP = 209, // GenericOpcodes.td:1099
225 G_FFREXP = 210, // GenericOpcodes.td:1106
226 G_FNEG = 211, // GenericOpcodes.td:818
227 G_FPEXT = 212, // GenericOpcodes.td:824
228 G_FPTRUNC = 213, // GenericOpcodes.td:830
229 G_FPTOSI = 214, // GenericOpcodes.td:836
230 G_FPTOUI = 215, // GenericOpcodes.td:842
231 G_SITOFP = 216, // GenericOpcodes.td:848
232 G_UITOFP = 217, // GenericOpcodes.td:854
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:860
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:866
235 G_FABS = 220, // GenericOpcodes.td:872
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:878
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:891
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:884
239 G_FMINNUM = 224, // GenericOpcodes.td:904
240 G_FMAXNUM = 225, // GenericOpcodes.td:911
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:929
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:936
243 G_FMINIMUM = 228, // GenericOpcodes.td:946
244 G_FMAXIMUM = 229, // GenericOpcodes.td:953
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:961
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:968
247 G_GET_FPENV = 232, // GenericOpcodes.td:1236
248 G_SET_FPENV = 233, // GenericOpcodes.td:1243
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1250
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1257
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1264
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1271
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1328
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1334
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1637
265 G_BRJT = 250, // GenericOpcodes.td:1667
266 G_VSCALE = 251, // GenericOpcodes.td:1565
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1711
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1719
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1727
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1735
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1746
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1754
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1762
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1769
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_FCEIL = 269, // GenericOpcodes.td:1113
285 G_FCOS = 270, // GenericOpcodes.td:1120
286 G_FSIN = 271, // GenericOpcodes.td:1127
287 G_FSINCOS = 272, // GenericOpcodes.td:1134
288 G_FTAN = 273, // GenericOpcodes.td:1141
289 G_FACOS = 274, // GenericOpcodes.td:1148
290 G_FASIN = 275, // GenericOpcodes.td:1155
291 G_FATAN = 276, // GenericOpcodes.td:1162
292 G_FATAN2 = 277, // GenericOpcodes.td:1169
293 G_FCOSH = 278, // GenericOpcodes.td:1176
294 G_FSINH = 279, // GenericOpcodes.td:1183
295 G_FTANH = 280, // GenericOpcodes.td:1190
296 G_FSQRT = 281, // GenericOpcodes.td:1200
297 G_FFLOOR = 282, // GenericOpcodes.td:1207
298 G_FRINT = 283, // GenericOpcodes.td:1214
299 G_FNEARBYINT = 284, // GenericOpcodes.td:1221
300 G_ADDRSPACE_CAST = 285, // GenericOpcodes.td:248
301 G_BLOCK_ADDR = 286, // GenericOpcodes.td:254
302 G_JUMP_TABLE = 287, // GenericOpcodes.td:260
303 G_DYN_STACKALLOC = 288, // GenericOpcodes.td:266
304 G_STACKSAVE = 289, // GenericOpcodes.td:272
305 G_STACKRESTORE = 290, // GenericOpcodes.td:278
306 G_STRICT_FADD = 291, // GenericOpcodes.td:1821
307 G_STRICT_FSUB = 292, // GenericOpcodes.td:1822
308 G_STRICT_FMUL = 293, // GenericOpcodes.td:1823
309 G_STRICT_FDIV = 294, // GenericOpcodes.td:1824
310 G_STRICT_FREM = 295, // GenericOpcodes.td:1825
311 G_STRICT_FMA = 296, // GenericOpcodes.td:1826
312 G_STRICT_FSQRT = 297, // GenericOpcodes.td:1827
313 G_STRICT_FLDEXP = 298, // GenericOpcodes.td:1828
314 G_STRICT_FCMP = 299, // GenericOpcodes.td:1829
315 G_STRICT_FCMPS = 300, // GenericOpcodes.td:1830
316 G_READ_REGISTER = 301, // GenericOpcodes.td:1686
317 G_WRITE_REGISTER = 302, // GenericOpcodes.td:1696
318 G_MEMCPY = 303, // GenericOpcodes.td:1836
319 G_MEMCPY_INLINE = 304, // GenericOpcodes.td:1844
320 G_MEMMOVE = 305, // GenericOpcodes.td:1852
321 G_MEMSET = 306, // GenericOpcodes.td:1860
322 G_BZERO = 307, // GenericOpcodes.td:1867
323 G_MEMSET_INLINE = 308, // GenericOpcodes.td:1874
324 G_TRAP = 309, // GenericOpcodes.td:1884
325 G_DEBUGTRAP = 310, // GenericOpcodes.td:1891
326 G_UBSANTRAP = 311, // GenericOpcodes.td:1897
327 G_VECREDUCE_SEQ_FADD = 312, // GenericOpcodes.td:1785
328 G_VECREDUCE_SEQ_FMUL = 313, // GenericOpcodes.td:1791
329 G_VECREDUCE_FADD = 314, // GenericOpcodes.td:1797
330 G_VECREDUCE_FMUL = 315, // GenericOpcodes.td:1798
331 G_VECREDUCE_FMAX = 316, // GenericOpcodes.td:1800
332 G_VECREDUCE_FMIN = 317, // GenericOpcodes.td:1801
333 G_VECREDUCE_FMAXIMUM = 318, // GenericOpcodes.td:1802
334 G_VECREDUCE_FMINIMUM = 319, // GenericOpcodes.td:1803
335 G_VECREDUCE_FMAXIMUMNUM = 320, // GenericOpcodes.td:1804
336 G_VECREDUCE_FMINIMUMNUM = 321, // GenericOpcodes.td:1805
337 G_VECREDUCE_ADD = 322, // GenericOpcodes.td:1807
338 G_VECREDUCE_MUL = 323, // GenericOpcodes.td:1808
339 G_VECREDUCE_AND = 324, // GenericOpcodes.td:1809
340 G_VECREDUCE_OR = 325, // GenericOpcodes.td:1810
341 G_VECREDUCE_XOR = 326, // GenericOpcodes.td:1811
342 G_VECREDUCE_SMAX = 327, // GenericOpcodes.td:1812
343 G_VECREDUCE_SMIN = 328, // GenericOpcodes.td:1813
344 G_VECREDUCE_UMAX = 329, // GenericOpcodes.td:1814
345 G_VECREDUCE_UMIN = 330, // GenericOpcodes.td:1815
346 G_SBFX = 331, // GenericOpcodes.td:1909
347 G_UBFX = 332, // GenericOpcodes.td:1917
348 ADJCALLSTACKDOWN = 333, // BPFInstrInfo.td:849
349 ADJCALLSTACKUP = 334, // BPFInstrInfo.td:852
350 FI_ri = 335, // BPFInstrInfo.td:515
351 LDIMM64 = 336, // BPFInstrInfo.td:1425
352 LOAD_STACK_ARG_PSEUDO = 337, // BPFInstrInfo.td:320
353 MEMCPY = 338, // BPFInstrInfo.td:1416
354 STORE_STACK_ARG_IMM_PSEUDO = 339, // BPFInstrInfo.td:330
355 STORE_STACK_ARG_PSEUDO = 340, // BPFInstrInfo.td:326
356 Select = 341, // BPFInstrInfo.td:858
357 Select_32 = 342, // BPFInstrInfo.td:878
358 Select_32_64 = 343, // BPFInstrInfo.td:888
359 Select_64_32 = 344, // BPFInstrInfo.td:868
360 Select_Ri = 345, // BPFInstrInfo.td:863
361 Select_Ri_32 = 346, // BPFInstrInfo.td:883
362 Select_Ri_32_64 = 347, // BPFInstrInfo.td:893
363 Select_Ri_64_32 = 348, // BPFInstrInfo.td:873
364 ADDR_SPACE_CAST = 349, // BPFInstrInfo.td:486
365 ADD_ri = 350, // BPFInstrInfo.td:366
366 ADD_ri_32 = 351, // BPFInstrInfo.td:376
367 ADD_rr = 352, // BPFInstrInfo.td:361
368 ADD_rr_32 = 353, // BPFInstrInfo.td:371
369 AND_ri = 354, // BPFInstrInfo.td:366
370 AND_ri_32 = 355, // BPFInstrInfo.td:376
371 AND_rr = 356, // BPFInstrInfo.td:361
372 AND_rr_32 = 357, // BPFInstrInfo.td:371
373 BE16 = 358, // BPFInstrInfo.td:1225
374 BE32 = 359, // BPFInstrInfo.td:1226
375 BE64 = 360, // BPFInstrInfo.td:1227
376 BSWAP16 = 361, // BPFInstrInfo.td:1218
377 BSWAP32 = 362, // BPFInstrInfo.td:1219
378 BSWAP64 = 363, // BPFInstrInfo.td:1220
379 CMPXCHGD = 364, // BPFInstrInfo.td:1198
380 CMPXCHGW32 = 365, // BPFInstrInfo.td:1194
381 CORE_LD32 = 366, // BPFInstrInfo.td:687
382 CORE_LD64 = 367, // BPFInstrInfo.td:686
383 CORE_SHIFT = 368, // BPFInstrInfo.td:694
384 CORE_ST = 369, // BPFInstrInfo.td:688
385 DIV_ri = 370, // BPFInstrInfo.td:366
386 DIV_ri_32 = 371, // BPFInstrInfo.td:376
387 DIV_rr = 372, // BPFInstrInfo.td:361
388 DIV_rr_32 = 373, // BPFInstrInfo.td:371
389 JAL = 374, // BPFInstrInfo.td:813
390 JALX = 375, // BPFInstrInfo.td:814
391 JCOND = 376, // BPFInstrInfo.td:310
392 JEQ_ri = 377, // BPFInstrInfo.td:292
393 JEQ_ri_32 = 378, // BPFInstrInfo.td:294
394 JEQ_rr = 379, // BPFInstrInfo.td:291
395 JEQ_rr_32 = 380, // BPFInstrInfo.td:293
396 JMP = 381, // BPFInstrInfo.td:807
397 JMPL = 382, // BPFInstrInfo.td:808
398 JNE_ri = 383, // BPFInstrInfo.td:292
399 JNE_ri_32 = 384, // BPFInstrInfo.td:294
400 JNE_rr = 385, // BPFInstrInfo.td:291
401 JNE_rr_32 = 386, // BPFInstrInfo.td:293
402 JSET_ri = 387, // BPFInstrInfo.td:292
403 JSET_ri_32 = 388, // BPFInstrInfo.td:294
404 JSET_rr = 389, // BPFInstrInfo.td:291
405 JSET_rr_32 = 390, // BPFInstrInfo.td:293
406 JSGE_ri = 391, // BPFInstrInfo.td:292
407 JSGE_ri_32 = 392, // BPFInstrInfo.td:294
408 JSGE_rr = 393, // BPFInstrInfo.td:291
409 JSGE_rr_32 = 394, // BPFInstrInfo.td:293
410 JSGT_ri = 395, // BPFInstrInfo.td:292
411 JSGT_ri_32 = 396, // BPFInstrInfo.td:294
412 JSGT_rr = 397, // BPFInstrInfo.td:291
413 JSGT_rr_32 = 398, // BPFInstrInfo.td:293
414 JSLE_ri = 399, // BPFInstrInfo.td:292
415 JSLE_ri_32 = 400, // BPFInstrInfo.td:294
416 JSLE_rr = 401, // BPFInstrInfo.td:291
417 JSLE_rr_32 = 402, // BPFInstrInfo.td:293
418 JSLT_ri = 403, // BPFInstrInfo.td:292
419 JSLT_ri_32 = 404, // BPFInstrInfo.td:294
420 JSLT_rr = 405, // BPFInstrInfo.td:291
421 JSLT_rr_32 = 406, // BPFInstrInfo.td:293
422 JUGE_ri = 407, // BPFInstrInfo.td:292
423 JUGE_ri_32 = 408, // BPFInstrInfo.td:294
424 JUGE_rr = 409, // BPFInstrInfo.td:291
425 JUGE_rr_32 = 410, // BPFInstrInfo.td:293
426 JUGT_ri = 411, // BPFInstrInfo.td:292
427 JUGT_ri_32 = 412, // BPFInstrInfo.td:294
428 JUGT_rr = 413, // BPFInstrInfo.td:291
429 JUGT_rr_32 = 414, // BPFInstrInfo.td:293
430 JULE_ri = 415, // BPFInstrInfo.td:292
431 JULE_ri_32 = 416, // BPFInstrInfo.td:294
432 JULE_rr = 417, // BPFInstrInfo.td:291
433 JULE_rr_32 = 418, // BPFInstrInfo.td:293
434 JULT_ri = 419, // BPFInstrInfo.td:292
435 JULT_ri_32 = 420, // BPFInstrInfo.td:294
436 JULT_rr = 421, // BPFInstrInfo.td:291
437 JULT_rr_32 = 422, // BPFInstrInfo.td:293
438 JX = 423, // BPFInstrInfo.td:314
439 LDB = 424, // BPFInstrInfo.td:705
440 LDB32 = 425, // BPFInstrInfo.td:1353
441 LDBACQ32 = 426, // BPFInstrInfo.td:1358
442 LDBSX = 427, // BPFInstrInfo.td:711
443 LDD = 428, // BPFInstrInfo.td:714
444 LDDACQ = 429, // BPFInstrInfo.td:748
445 LDH = 430, // BPFInstrInfo.td:704
446 LDH32 = 431, // BPFInstrInfo.td:1352
447 LDHACQ32 = 432, // BPFInstrInfo.td:1357
448 LDHSX = 433, // BPFInstrInfo.td:710
449 LDW = 434, // BPFInstrInfo.td:703
450 LDW32 = 435, // BPFInstrInfo.td:1351
451 LDWACQ32 = 436, // BPFInstrInfo.td:1356
452 LDWSX = 437, // BPFInstrInfo.td:709
453 LD_ABS_B = 438, // BPFInstrInfo.td:1262
454 LD_ABS_H = 439, // BPFInstrInfo.td:1263
455 LD_ABS_W = 440, // BPFInstrInfo.td:1264
456 LD_IND_B = 441, // BPFInstrInfo.td:1266
457 LD_IND_H = 442, // BPFInstrInfo.td:1267
458 LD_IND_W = 443, // BPFInstrInfo.td:1268
459 LD_imm64 = 444, // BPFInstrInfo.td:440
460 LD_pseudo = 445, // BPFInstrInfo.td:531
461 LE16 = 446, // BPFInstrInfo.td:1230
462 LE32 = 447, // BPFInstrInfo.td:1231
463 LE64 = 448, // BPFInstrInfo.td:1232
464 MOD_ri = 449, // BPFInstrInfo.td:366
465 MOD_ri_32 = 450, // BPFInstrInfo.td:376
466 MOD_rr = 451, // BPFInstrInfo.td:361
467 MOD_rr_32 = 452, // BPFInstrInfo.td:371
468 MOVSX_rr_16 = 453, // BPFInstrInfo.td:467
469 MOVSX_rr_32 = 454, // BPFInstrInfo.td:471
470 MOVSX_rr_32_16 = 455, // BPFInstrInfo.td:479
471 MOVSX_rr_32_8 = 456, // BPFInstrInfo.td:475
472 MOVSX_rr_8 = 457, // BPFInstrInfo.td:463
473 MOV_32_64 = 458, // BPFInstrInfo.td:1271
474 MOV_ri = 459, // BPFInstrInfo.td:446
475 MOV_ri_32 = 460, // BPFInstrInfo.td:456
476 MOV_rr = 461, // BPFInstrInfo.td:441
477 MOV_rr_32 = 462, // BPFInstrInfo.td:451
478 MUL_ri = 463, // BPFInstrInfo.td:366
479 MUL_ri_32 = 464, // BPFInstrInfo.td:376
480 MUL_rr = 465, // BPFInstrInfo.td:361
481 MUL_rr_32 = 466, // BPFInstrInfo.td:371
482 NEG_32 = 467, // BPFInstrInfo.td:417
483 NEG_64 = 468, // BPFInstrInfo.td:414
484 NOP = 469, // BPFInstrInfo.td:830
485 OR_ri = 470, // BPFInstrInfo.td:366
486 OR_ri_32 = 471, // BPFInstrInfo.td:376
487 OR_rr = 472, // BPFInstrInfo.td:361
488 OR_rr_32 = 473, // BPFInstrInfo.td:371
489 RET = 474, // BPFInstrInfo.td:844
490 SDIV_ri = 475, // BPFInstrInfo.td:366
491 SDIV_ri_32 = 476, // BPFInstrInfo.td:376
492 SDIV_rr = 477, // BPFInstrInfo.td:361
493 SDIV_rr_32 = 478, // BPFInstrInfo.td:371
494 SLL_ri = 479, // BPFInstrInfo.td:366
495 SLL_ri_32 = 480, // BPFInstrInfo.td:376
496 SLL_rr = 481, // BPFInstrInfo.td:361
497 SLL_rr_32 = 482, // BPFInstrInfo.td:371
498 SMOD_ri = 483, // BPFInstrInfo.td:366
499 SMOD_ri_32 = 484, // BPFInstrInfo.td:376
500 SMOD_rr = 485, // BPFInstrInfo.td:361
501 SMOD_rr_32 = 486, // BPFInstrInfo.td:371
502 SRA_ri = 487, // BPFInstrInfo.td:366
503 SRA_ri_32 = 488, // BPFInstrInfo.td:376
504 SRA_rr = 489, // BPFInstrInfo.td:361
505 SRA_rr_32 = 490, // BPFInstrInfo.td:371
506 SRL_ri = 491, // BPFInstrInfo.td:366
507 SRL_ri_32 = 492, // BPFInstrInfo.td:376
508 SRL_rr = 493, // BPFInstrInfo.td:361
509 SRL_rr_32 = 494, // BPFInstrInfo.td:371
510 STB = 495, // BPFInstrInfo.td:571
511 STB32 = 496, // BPFInstrInfo.td:1320
512 STBREL32 = 497, // BPFInstrInfo.td:1325
513 STB_imm = 498, // BPFInstrInfo.td:607
514 STD = 499, // BPFInstrInfo.td:573
515 STDREL = 500, // BPFInstrInfo.td:651
516 STD_imm = 501, // BPFInstrInfo.td:604
517 STH = 502, // BPFInstrInfo.td:570
518 STH32 = 503, // BPFInstrInfo.td:1319
519 STHREL32 = 504, // BPFInstrInfo.td:1324
520 STH_imm = 505, // BPFInstrInfo.td:606
521 STW = 506, // BPFInstrInfo.td:569
522 STW32 = 507, // BPFInstrInfo.td:1318
523 STWREL32 = 508, // BPFInstrInfo.td:1323
524 STW_imm = 509, // BPFInstrInfo.td:605
525 SUB_ri = 510, // BPFInstrInfo.td:366
526 SUB_ri_32 = 511, // BPFInstrInfo.td:376
527 SUB_rr = 512, // BPFInstrInfo.td:361
528 SUB_rr_32 = 513, // BPFInstrInfo.td:371
529 XADDD = 514, // BPFInstrInfo.td:947
530 XADDW = 515, // BPFInstrInfo.td:946
531 XADDW32 = 516, // BPFInstrInfo.td:941
532 XANDD = 517, // BPFInstrInfo.td:948
533 XANDW32 = 518, // BPFInstrInfo.td:942
534 XCHGD = 519, // BPFInstrInfo.td:1154
535 XCHGW32 = 520, // BPFInstrInfo.td:1151
536 XFADDD = 521, // BPFInstrInfo.td:1004
537 XFADDW32 = 522, // BPFInstrInfo.td:997
538 XFANDD = 523, // BPFInstrInfo.td:1006
539 XFANDW32 = 524, // BPFInstrInfo.td:998
540 XFORD = 525, // BPFInstrInfo.td:1007
541 XFORW32 = 526, // BPFInstrInfo.td:999
542 XFXORD = 527, // BPFInstrInfo.td:1008
543 XFXORW32 = 528, // BPFInstrInfo.td:1000
544 XORD = 529, // BPFInstrInfo.td:949
545 XORW32 = 530, // BPFInstrInfo.td:943
546 XOR_ri = 531, // BPFInstrInfo.td:366
547 XOR_ri_32 = 532, // BPFInstrInfo.td:376
548 XOR_rr = 533, // BPFInstrInfo.td:361
549 XOR_rr_32 = 534, // BPFInstrInfo.td:371
550 XXORD = 535, // BPFInstrInfo.td:950
551 XXORW32 = 536, // BPFInstrInfo.td:944
552 INSTRUCTION_LIST_END = 537
553 };
554
555} // namespace llvm::BPF
556
557#endif // GET_INSTRINFO_ENUM
558
559#ifdef GET_INSTRINFO_SCHED_ENUM
560#undef GET_INSTRINFO_SCHED_ENUM
561
562namespace llvm::BPF::Sched {
563
564 enum {
565 NoInstrModel = 0,
566 SCHED_LIST_END = 1
567 };
568
569} // namespace llvm::BPF::Sched
570
571#endif // GET_INSTRINFO_SCHED_ENUM
572
573#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
574
575namespace llvm {
576
577struct BPFInstrTable {
578 MCInstrDesc Insts[537];
579 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
580 MCPhysReg ImplicitOps[14];
581 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
582 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
583 MCOperandInfo OperandInfo[282];
584};
585} // namespace llvm
586
587#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
588
589#ifdef GET_INSTRINFO_MC_DESC
590#undef GET_INSTRINFO_MC_DESC
591
592namespace llvm {
593
594static_assert((sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
595static constexpr unsigned BPFOpInfoBase = (sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) / sizeof(MCOperandInfo);
596
597extern const BPFInstrTable BPFDescs = {
598 {
599 { 536, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORW32
600 { 535, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORD
601 { 534, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr_32
602 { 533, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr
603 { 532, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri_32
604 { 531, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri
605 { 530, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORW32
606 { 529, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORD
607 { 528, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORW32
608 { 527, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORD
609 { 526, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORW32
610 { 525, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORD
611 { 524, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDW32
612 { 523, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDD
613 { 522, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDW32
614 { 521, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDD
615 { 520, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGW32
616 { 519, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGD
617 { 518, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDW32
618 { 517, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDD
619 { 516, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW32
620 { 515, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW
621 { 514, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDD
622 { 513, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr_32
623 { 512, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr
624 { 511, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri_32
625 { 510, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri
626 { 509, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_imm
627 { 508, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWREL32
628 { 507, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW32
629 { 506, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW
630 { 505, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_imm
631 { 504, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STHREL32
632 { 503, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH32
633 { 502, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH
634 { 501, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD_imm
635 { 500, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDREL
636 { 499, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD
637 { 498, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_imm
638 { 497, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STBREL32
639 { 496, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB32
640 { 495, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB
641 { 494, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr_32
642 { 493, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr
643 { 492, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri_32
644 { 491, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri
645 { 490, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr_32
646 { 489, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr
647 { 488, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri_32
648 { 487, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri
649 { 486, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr_32
650 { 485, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr
651 { 484, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri_32
652 { 483, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri
653 { 482, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr_32
654 { 481, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr
655 { 480, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri_32
656 { 479, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri
657 { 478, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr_32
658 { 477, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr
659 { 476, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri_32
660 { 475, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri
661 { 474, 0, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
662 { 473, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr_32
663 { 472, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr
664 { 471, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri_32
665 { 470, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri
666 { 469, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
667 { 468, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_64
668 { 467, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 269, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_32
669 { 466, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr_32
670 { 465, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr
671 { 464, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri_32
672 { 463, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri
673 { 462, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr_32
674 { 461, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr
675 { 460, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 267, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri_32
676 { 459, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri
677 { 458, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 265, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_32_64
678 { 457, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_8
679 { 456, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_8
680 { 455, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_16
681 { 454, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32
682 { 453, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_16
683 { 452, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr_32
684 { 451, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr
685 { 450, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri_32
686 { 449, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri
687 { 448, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE64
688 { 447, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE32
689 { 446, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE16
690 { 445, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_pseudo
691 { 444, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_imm64
692 { 443, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_W
693 { 442, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_H
694 { 441, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_B
695 { 440, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_W
696 { 439, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_H
697 { 438, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_B
698 { 437, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSX
699 { 436, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWACQ32
700 { 435, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW32
701 { 434, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW
702 { 433, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHSX
703 { 432, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHACQ32
704 { 431, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH32
705 { 430, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH
706 { 429, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDDACQ
707 { 428, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDD
708 { 427, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBSX
709 { 426, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBACQ32
710 { 425, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB32
711 { 424, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB
712 { 423, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JX
713 { 422, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr_32
714 { 421, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr
715 { 420, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri_32
716 { 419, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri
717 { 418, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr_32
718 { 417, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr
719 { 416, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri_32
720 { 415, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri
721 { 414, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr_32
722 { 413, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr
723 { 412, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri_32
724 { 411, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri
725 { 410, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr_32
726 { 409, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr
727 { 408, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri_32
728 { 407, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri
729 { 406, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr_32
730 { 405, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr
731 { 404, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri_32
732 { 403, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri
733 { 402, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr_32
734 { 401, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr
735 { 400, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri_32
736 { 399, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri
737 { 398, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr_32
738 { 397, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr
739 { 396, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri_32
740 { 395, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri
741 { 394, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr_32
742 { 393, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr
743 { 392, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri_32
744 { 391, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri
745 { 390, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr_32
746 { 389, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr
747 { 388, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri_32
748 { 387, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri
749 { 386, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr_32
750 { 385, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr
751 { 384, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri_32
752 { 383, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri
753 { 382, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMPL
754 { 381, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
755 { 380, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr_32
756 { 379, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr
757 { 378, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri_32
758 { 377, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri
759 { 376, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCOND
760 { 375, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 28, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JALX
761 { 374, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 0, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JAL
762 { 373, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr_32
763 { 372, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr
764 { 371, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri_32
765 { 370, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri
766 { 369, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 242, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_ST
767 { 368, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 238, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_SHIFT
768 { 367, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 234, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD64
769 { 366, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 230, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD32
770 { 365, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 227, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGW32
771 { 364, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 224, 2, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGD
772 { 363, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP64
773 { 362, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP32
774 { 361, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP16
775 { 360, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE64
776 { 359, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE32
777 { 358, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE16
778 { 357, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr_32
779 { 356, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr
780 { 355, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri_32
781 { 354, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri
782 { 353, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr_32
783 { 352, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr
784 { 351, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri_32
785 { 350, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri
786 { 349, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDR_SPACE_CAST
787 { 348, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 204, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_64_32
788 { 347, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 198, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32_64
789 { 346, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 192, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32
790 { 345, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri
791 { 344, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_64_32
792 { 343, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 174, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32_64
793 { 342, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 168, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32
794 { 341, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select
795 { 340, 2, 0, 8, 0, 0, 0, BPFOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_STACK_ARG_PSEUDO
796 { 339, 2, 0, 8, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_STACK_ARG_IMM_PSEUDO
797 { 338, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY
798 { 337, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_STACK_ARG_PSEUDO
799 { 336, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIMM64
800 { 335, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FI_ri
801 { 334, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
802 { 333, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
803 { 332, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
804 { 331, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
805 { 330, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
806 { 329, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
807 { 328, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
808 { 327, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
809 { 326, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
810 { 325, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
811 { 324, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
812 { 323, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
813 { 322, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
814 { 321, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
815 { 320, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
816 { 319, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
817 { 318, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
818 { 317, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
819 { 316, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
820 { 315, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
821 { 314, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
822 { 313, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
823 { 312, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
824 { 311, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
825 { 310, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
826 { 309, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
827 { 308, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
828 { 307, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
829 { 306, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
830 { 305, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
831 { 304, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
832 { 303, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
833 { 302, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
834 { 301, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
835 { 300, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
836 { 299, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
837 { 298, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
838 { 297, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
839 { 296, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
840 { 295, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
841 { 294, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
842 { 293, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
843 { 292, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
844 { 291, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
845 { 290, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
846 { 289, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
847 { 288, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
848 { 287, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
849 { 286, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
850 { 285, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
851 { 284, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
852 { 283, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
853 { 282, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
854 { 281, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
855 { 280, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
856 { 279, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
857 { 278, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
858 { 277, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
859 { 276, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
860 { 275, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
861 { 274, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
862 { 273, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
863 { 272, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
864 { 271, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
865 { 270, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
866 { 269, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
867 { 268, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
868 { 267, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
869 { 266, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
870 { 265, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
871 { 264, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
872 { 263, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
873 { 262, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
874 { 261, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
875 { 260, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
876 { 259, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
877 { 258, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
878 { 257, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
879 { 256, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
880 { 255, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
881 { 254, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
882 { 253, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
883 { 252, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
884 { 251, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
885 { 250, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
886 { 249, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
887 { 248, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
888 { 247, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
889 { 246, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
890 { 245, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
891 { 244, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
892 { 243, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
893 { 242, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
894 { 241, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
895 { 240, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
896 { 239, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
897 { 238, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
898 { 237, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
899 { 236, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
900 { 235, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
901 { 234, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
902 { 233, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
903 { 232, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
904 { 231, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
905 { 230, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
906 { 229, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
907 { 228, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
908 { 227, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
909 { 226, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
910 { 225, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
911 { 224, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
912 { 223, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
913 { 222, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
914 { 221, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
915 { 220, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
916 { 219, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
917 { 218, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
918 { 217, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
919 { 216, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
920 { 215, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
921 { 214, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
922 { 213, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
923 { 212, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
924 { 211, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
925 { 210, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
926 { 209, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
927 { 208, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
928 { 207, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
929 { 206, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
930 { 205, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
931 { 204, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
932 { 203, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
933 { 202, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
934 { 201, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
935 { 200, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
936 { 199, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
937 { 198, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
938 { 197, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
939 { 196, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
940 { 195, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
941 { 194, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
942 { 193, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
943 { 192, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
944 { 191, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
945 { 190, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
946 { 189, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
947 { 188, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
948 { 187, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
949 { 186, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
950 { 185, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
951 { 184, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
952 { 183, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
953 { 182, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
954 { 181, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
955 { 180, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
956 { 179, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
957 { 178, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
958 { 177, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
959 { 176, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
960 { 175, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
961 { 174, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
962 { 173, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
963 { 172, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
964 { 171, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
965 { 170, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
966 { 169, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
967 { 168, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
968 { 167, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
969 { 166, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
970 { 165, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
971 { 164, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
972 { 163, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
973 { 162, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
974 { 161, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
975 { 160, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
976 { 159, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
977 { 158, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
978 { 157, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
979 { 156, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
980 { 155, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
981 { 154, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
982 { 153, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
983 { 152, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
984 { 151, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
985 { 150, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
986 { 149, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
987 { 148, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
988 { 147, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
989 { 146, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
990 { 145, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
991 { 144, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
992 { 143, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
993 { 142, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
994 { 141, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
995 { 140, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
996 { 139, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
997 { 138, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
998 { 137, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
999 { 136, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1000 { 135, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1001 { 134, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1002 { 133, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1003 { 132, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1004 { 131, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1005 { 130, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1006 { 129, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1007 { 128, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1008 { 127, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1009 { 126, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1010 { 125, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1011 { 124, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1012 { 123, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1013 { 122, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1014 { 121, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1015 { 120, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1016 { 119, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1017 { 118, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1018 { 117, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1019 { 116, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1020 { 115, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1021 { 114, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1022 { 113, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1023 { 112, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1024 { 111, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1025 { 110, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1026 { 109, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1027 { 108, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1028 { 107, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1029 { 106, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1030 { 105, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1031 { 104, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1032 { 103, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1033 { 102, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1034 { 101, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1035 { 100, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1036 { 99, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1037 { 98, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1038 { 97, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1039 { 96, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1040 { 95, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1041 { 94, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1042 { 93, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1043 { 92, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1044 { 91, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1045 { 90, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1046 { 89, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1047 { 88, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1048 { 87, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1049 { 86, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1050 { 85, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1051 { 84, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1052 { 83, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1053 { 82, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1054 { 81, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1055 { 80, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1056 { 79, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1057 { 78, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1058 { 77, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1059 { 76, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1060 { 75, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1061 { 74, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1062 { 73, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1063 { 72, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1064 { 71, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1065 { 70, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1066 { 69, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1067 { 68, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1068 { 67, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1069 { 66, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1070 { 65, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1071 { 64, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1072 { 63, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1073 { 62, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1074 { 61, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1075 { 60, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1076 { 59, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1077 { 58, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1078 { 57, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1079 { 56, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1080 { 55, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1081 { 54, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1082 { 53, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1083 { 52, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1084 { 51, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1085 { 50, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1086 { 49, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1087 { 48, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1088 { 47, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1089 { 46, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1090 { 45, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1091 { 44, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1092 { 43, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1093 { 42, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14400
1094 { 41, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14399
1095 { 40, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1096 { 39, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1097 { 38, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1098 { 37, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1099 { 36, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1100 { 35, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1101 { 34, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1102 { 33, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1103 { 32, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14398
1104 { 31, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1105 { 30, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_13978
1106 { 29, 6, 1, 0, 0, 0, 0, BPFOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1107 { 28, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1108 { 27, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1109 { 26, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1110 { 25, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1111 { 24, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1112 { 23, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1113 { 22, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1114 { 21, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1115 { 20, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1116 { 19, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1117 { 18, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1118 { 17, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1119 { 16, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1120 { 15, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1121 { 14, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1122 { 13, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1123 { 12, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1124 { 11, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1125 { 10, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1126 { 9, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1127 { 8, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1128 { 7, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1129 { 6, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1130 { 5, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1131 { 4, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1132 { 3, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1133 { 2, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1134 { 1, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1135 { 0, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1136 }, {
1137 /* 0 */
1138 /* 0 */ BPF::R11, BPF::R11,
1139 /* 2 */ BPF::R0, BPF::R0,
1140 /* 4 */ BPF::W0, BPF::W0,
1141 /* 6 */ BPF::R11,
1142 /* 7 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1143 }, {
1144 0
1145 }, {
1146 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1147 /* 1 */
1148 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1149 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1150 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1151 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1152 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1153 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1154 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1155 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1156 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1157 /* 28 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1158 /* 29 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1159 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1160 /* 34 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1161 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1162 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1163 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1164 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1165 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1166 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1167 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1168 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1169 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1170 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1171 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1172 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1173 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1174 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1175 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1176 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1177 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1178 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1179 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1180 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1181 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1182 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1183 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1184 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1185 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1186 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1187 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1188 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1189 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1190 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1191 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1192 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1193 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1194 /* 151 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1195 /* 154 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1196 /* 156 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1197 /* 160 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1198 /* 162 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1199 /* 168 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1200 /* 174 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1201 /* 180 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1202 /* 186 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1203 /* 192 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1204 /* 198 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1205 /* 204 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1206 /* 210 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1207 /* 213 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1208 /* 216 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1209 /* 219 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1210 /* 222 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1211 /* 224 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1212 /* 227 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1213 /* 230 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1214 /* 234 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1215 /* 238 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1216 /* 242 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1217 /* 246 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1218 /* 249 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1219 /* 252 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1220 /* 255 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1221 /* 258 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1222 /* 261 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1223 /* 263 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1224 /* 265 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1225 /* 267 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1226 /* 269 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1227 /* 271 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1228 /* 274 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1229 /* 278 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1230 }
1231};
1232
1233
1234#ifdef __GNUC__
1235#pragma GCC diagnostic push
1236#pragma GCC diagnostic ignored "-Woverlength-strings"
1237#endif
1238extern const char BPFInstrNameData[] = {
1239 /* 0 */ "G_FLOG10\000"
1240 /* 9 */ "G_FEXP10\000"
1241 /* 18 */ "LDB32\000"
1242 /* 24 */ "STB32\000"
1243 /* 30 */ "CORE_LD32\000"
1244 /* 40 */ "BE32\000"
1245 /* 45 */ "LE32\000"
1246 /* 50 */ "LDH32\000"
1247 /* 56 */ "STH32\000"
1248 /* 62 */ "STBREL32\000"
1249 /* 71 */ "STHREL32\000"
1250 /* 80 */ "STWREL32\000"
1251 /* 89 */ "BSWAP32\000"
1252 /* 97 */ "LDBACQ32\000"
1253 /* 106 */ "LDHACQ32\000"
1254 /* 115 */ "LDWACQ32\000"
1255 /* 124 */ "XFADDW32\000"
1256 /* 133 */ "XADDW32\000"
1257 /* 141 */ "LDW32\000"
1258 /* 147 */ "XFANDW32\000"
1259 /* 156 */ "XANDW32\000"
1260 /* 164 */ "CMPXCHGW32\000"
1261 /* 175 */ "XFORW32\000"
1262 /* 183 */ "XFXORW32\000"
1263 /* 192 */ "XXORW32\000"
1264 /* 200 */ "STW32\000"
1265 /* 206 */ "Select_Ri_64_32\000"
1266 /* 222 */ "Select_64_32\000"
1267 /* 235 */ "NEG_32\000"
1268 /* 242 */ "Select_Ri_32\000"
1269 /* 255 */ "SRA_ri_32\000"
1270 /* 265 */ "SUB_ri_32\000"
1271 /* 275 */ "ADD_ri_32\000"
1272 /* 285 */ "AND_ri_32\000"
1273 /* 295 */ "SMOD_ri_32\000"
1274 /* 306 */ "JSGE_ri_32\000"
1275 /* 317 */ "JUGE_ri_32\000"
1276 /* 328 */ "JSLE_ri_32\000"
1277 /* 339 */ "JULE_ri_32\000"
1278 /* 350 */ "JNE_ri_32\000"
1279 /* 360 */ "SLL_ri_32\000"
1280 /* 370 */ "SRL_ri_32\000"
1281 /* 380 */ "MUL_ri_32\000"
1282 /* 390 */ "JEQ_ri_32\000"
1283 /* 400 */ "XOR_ri_32\000"
1284 /* 410 */ "JSET_ri_32\000"
1285 /* 421 */ "JSGT_ri_32\000"
1286 /* 432 */ "JUGT_ri_32\000"
1287 /* 443 */ "JSLT_ri_32\000"
1288 /* 454 */ "JULT_ri_32\000"
1289 /* 465 */ "SDIV_ri_32\000"
1290 /* 476 */ "MOV_ri_32\000"
1291 /* 486 */ "SRA_rr_32\000"
1292 /* 496 */ "SUB_rr_32\000"
1293 /* 506 */ "ADD_rr_32\000"
1294 /* 516 */ "AND_rr_32\000"
1295 /* 526 */ "SMOD_rr_32\000"
1296 /* 537 */ "JSGE_rr_32\000"
1297 /* 548 */ "JUGE_rr_32\000"
1298 /* 559 */ "JSLE_rr_32\000"
1299 /* 570 */ "JULE_rr_32\000"
1300 /* 581 */ "JNE_rr_32\000"
1301 /* 591 */ "SLL_rr_32\000"
1302 /* 601 */ "SRL_rr_32\000"
1303 /* 611 */ "MUL_rr_32\000"
1304 /* 621 */ "JEQ_rr_32\000"
1305 /* 631 */ "XOR_rr_32\000"
1306 /* 641 */ "JSET_rr_32\000"
1307 /* 652 */ "JSGT_rr_32\000"
1308 /* 663 */ "JUGT_rr_32\000"
1309 /* 674 */ "JSLT_rr_32\000"
1310 /* 685 */ "JULT_rr_32\000"
1311 /* 696 */ "SDIV_rr_32\000"
1312 /* 707 */ "MOV_rr_32\000"
1313 /* 717 */ "MOVSX_rr_32\000"
1314 /* 729 */ "Select_32\000"
1315 /* 739 */ "G_FLOG2\000"
1316 /* 747 */ "G_FATAN2\000"
1317 /* 756 */ "G_FEXP2\000"
1318 /* 764 */ "CORE_LD64\000"
1319 /* 774 */ "BE64\000"
1320 /* 779 */ "LE64\000"
1321 /* 784 */ "LDIMM64\000"
1322 /* 792 */ "BSWAP64\000"
1323 /* 800 */ "MOV_32_64\000"
1324 /* 810 */ "Select_Ri_32_64\000"
1325 /* 826 */ "Select_32_64\000"
1326 /* 839 */ "NEG_64\000"
1327 /* 846 */ "LD_imm64\000"
1328 /* 855 */ "BE16\000"
1329 /* 860 */ "LE16\000"
1330 /* 865 */ "BSWAP16\000"
1331 /* 873 */ "MOVSX_rr_32_16\000"
1332 /* 888 */ "MOVSX_rr_16\000"
1333 /* 900 */ "MOVSX_rr_32_8\000"
1334 /* 914 */ "MOVSX_rr_8\000"
1335 /* 925 */ "G_FMA\000"
1336 /* 931 */ "G_STRICT_FMA\000"
1337 /* 944 */ "LDB\000"
1338 /* 948 */ "STB\000"
1339 /* 952 */ "G_FSUB\000"
1340 /* 959 */ "G_STRICT_FSUB\000"
1341 /* 973 */ "G_ATOMICRMW_FSUB\000"
1342 /* 990 */ "G_SUB\000"
1343 /* 996 */ "G_ATOMICRMW_SUB\000"
1344 /* 1012 */ "LD_IND_B\000"
1345 /* 1021 */ "LD_ABS_B\000"
1346 /* 1030 */ "G_INTRINSIC\000"
1347 /* 1042 */ "G_FPTRUNC\000"
1348 /* 1052 */ "G_INTRINSIC_TRUNC\000"
1349 /* 1070 */ "G_TRUNC\000"
1350 /* 1078 */ "G_BUILD_VECTOR_TRUNC\000"
1351 /* 1099 */ "G_DYN_STACKALLOC\000"
1352 /* 1116 */ "G_FMAD\000"
1353 /* 1123 */ "G_FPEXTLOAD\000"
1354 /* 1135 */ "G_INDEXED_SEXTLOAD\000"
1355 /* 1154 */ "G_SEXTLOAD\000"
1356 /* 1165 */ "G_INDEXED_ZEXTLOAD\000"
1357 /* 1184 */ "G_ZEXTLOAD\000"
1358 /* 1195 */ "G_INDEXED_LOAD\000"
1359 /* 1210 */ "G_LOAD\000"
1360 /* 1217 */ "G_VECREDUCE_FADD\000"
1361 /* 1234 */ "G_FADD\000"
1362 /* 1241 */ "G_VECREDUCE_SEQ_FADD\000"
1363 /* 1262 */ "G_STRICT_FADD\000"
1364 /* 1276 */ "G_ATOMICRMW_FADD\000"
1365 /* 1293 */ "G_VECREDUCE_ADD\000"
1366 /* 1309 */ "G_ADD\000"
1367 /* 1315 */ "G_PTR_ADD\000"
1368 /* 1325 */ "G_ATOMICRMW_ADD\000"
1369 /* 1341 */ "XFADDD\000"
1370 /* 1348 */ "XADDD\000"
1371 /* 1354 */ "LDD\000"
1372 /* 1358 */ "XFANDD\000"
1373 /* 1365 */ "XANDD\000"
1374 /* 1371 */ "CMPXCHGD\000"
1375 /* 1380 */ "G_ATOMICRMW_NAND\000"
1376 /* 1397 */ "G_VECREDUCE_AND\000"
1377 /* 1413 */ "G_AND\000"
1378 /* 1419 */ "G_ATOMICRMW_AND\000"
1379 /* 1435 */ "LIFETIME_END\000"
1380 /* 1448 */ "JCOND\000"
1381 /* 1454 */ "G_BRCOND\000"
1382 /* 1463 */ "G_ATOMICRMW_USUB_COND\000"
1383 /* 1485 */ "G_LLROUND\000"
1384 /* 1495 */ "G_LROUND\000"
1385 /* 1504 */ "G_INTRINSIC_ROUND\000"
1386 /* 1522 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1387 /* 1548 */ "LOAD_STACK_GUARD\000"
1388 /* 1565 */ "XFORD\000"
1389 /* 1571 */ "XFXORD\000"
1390 /* 1578 */ "XXORD\000"
1391 /* 1584 */ "STD\000"
1392 /* 1588 */ "PSEUDO_PROBE\000"
1393 /* 1601 */ "G_SSUBE\000"
1394 /* 1609 */ "G_USUBE\000"
1395 /* 1617 */ "G_FENCE\000"
1396 /* 1625 */ "ARITH_FENCE\000"
1397 /* 1637 */ "REG_SEQUENCE\000"
1398 /* 1650 */ "G_SADDE\000"
1399 /* 1658 */ "G_UADDE\000"
1400 /* 1666 */ "G_GET_FPMODE\000"
1401 /* 1679 */ "G_RESET_FPMODE\000"
1402 /* 1694 */ "G_SET_FPMODE\000"
1403 /* 1707 */ "G_FMINNUM_IEEE\000"
1404 /* 1722 */ "G_FMAXNUM_IEEE\000"
1405 /* 1737 */ "G_VSCALE\000"
1406 /* 1746 */ "G_JUMP_TABLE\000"
1407 /* 1759 */ "BUNDLE\000"
1408 /* 1766 */ "G_MEMSET_INLINE\000"
1409 /* 1782 */ "G_MEMCPY_INLINE\000"
1410 /* 1798 */ "RELOC_NONE\000"
1411 /* 1809 */ "LOCAL_ESCAPE\000"
1412 /* 1822 */ "G_FPTRUNCSTORE\000"
1413 /* 1837 */ "G_STACKRESTORE\000"
1414 /* 1852 */ "G_INDEXED_STORE\000"
1415 /* 1868 */ "G_STORE\000"
1416 /* 1876 */ "G_BITREVERSE\000"
1417 /* 1889 */ "FAKE_USE\000"
1418 /* 1898 */ "DBG_VALUE\000"
1419 /* 1908 */ "G_GLOBAL_VALUE\000"
1420 /* 1923 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1421 /* 1946 */ "CONVERGENCECTRL_GLUE\000"
1422 /* 1967 */ "G_STACKSAVE\000"
1423 /* 1979 */ "G_MEMMOVE\000"
1424 /* 1989 */ "G_FREEZE\000"
1425 /* 1998 */ "G_FCANONICALIZE\000"
1426 /* 2014 */ "G_FMODF\000"
1427 /* 2022 */ "INIT_UNDEF\000"
1428 /* 2033 */ "G_IMPLICIT_DEF\000"
1429 /* 2048 */ "DBG_INSTR_REF\000"
1430 /* 2062 */ "G_FNEG\000"
1431 /* 2069 */ "EXTRACT_SUBREG\000"
1432 /* 2084 */ "INSERT_SUBREG\000"
1433 /* 2098 */ "G_SEXT_INREG\000"
1434 /* 2111 */ "SUBREG_TO_REG\000"
1435 /* 2125 */ "G_ATOMIC_CMPXCHG\000"
1436 /* 2142 */ "G_ATOMICRMW_XCHG\000"
1437 /* 2159 */ "G_GET_ROUNDING\000"
1438 /* 2174 */ "G_SET_ROUNDING\000"
1439 /* 2189 */ "G_FLOG\000"
1440 /* 2196 */ "G_VAARG\000"
1441 /* 2204 */ "PREALLOCATED_ARG\000"
1442 /* 2221 */ "G_PREFETCH\000"
1443 /* 2232 */ "LDH\000"
1444 /* 2236 */ "G_SMULH\000"
1445 /* 2244 */ "G_UMULH\000"
1446 /* 2252 */ "G_FTANH\000"
1447 /* 2260 */ "G_FSINH\000"
1448 /* 2268 */ "G_FCOSH\000"
1449 /* 2276 */ "STH\000"
1450 /* 2280 */ "LD_IND_H\000"
1451 /* 2289 */ "LD_ABS_H\000"
1452 /* 2298 */ "DBG_PHI\000"
1453 /* 2306 */ "G_FPTOSI\000"
1454 /* 2315 */ "G_FPTOUI\000"
1455 /* 2324 */ "G_FPOWI\000"
1456 /* 2332 */ "COPY_LANEMASK\000"
1457 /* 2346 */ "G_PTRMASK\000"
1458 /* 2356 */ "JAL\000"
1459 /* 2360 */ "GC_LABEL\000"
1460 /* 2369 */ "DBG_LABEL\000"
1461 /* 2379 */ "EH_LABEL\000"
1462 /* 2388 */ "ANNOTATION_LABEL\000"
1463 /* 2405 */ "ICALL_BRANCH_FUNNEL\000"
1464 /* 2425 */ "STDREL\000"
1465 /* 2432 */ "G_FSHL\000"
1466 /* 2439 */ "G_SHL\000"
1467 /* 2445 */ "G_FCEIL\000"
1468 /* 2453 */ "G_SAVGCEIL\000"
1469 /* 2464 */ "G_UAVGCEIL\000"
1470 /* 2475 */ "PATCHABLE_TAIL_CALL\000"
1471 /* 2495 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1472 /* 2522 */ "PATCHABLE_EVENT_CALL\000"
1473 /* 2543 */ "FENTRY_CALL\000"
1474 /* 2555 */ "KILL\000"
1475 /* 2560 */ "G_CONSTANT_POOL\000"
1476 /* 2576 */ "JMPL\000"
1477 /* 2581 */ "G_ROTL\000"
1478 /* 2588 */ "G_VECREDUCE_FMUL\000"
1479 /* 2605 */ "G_FMUL\000"
1480 /* 2612 */ "G_VECREDUCE_SEQ_FMUL\000"
1481 /* 2633 */ "G_STRICT_FMUL\000"
1482 /* 2647 */ "G_CLMUL\000"
1483 /* 2655 */ "G_VECREDUCE_MUL\000"
1484 /* 2671 */ "G_MUL\000"
1485 /* 2677 */ "G_FREM\000"
1486 /* 2684 */ "G_STRICT_FREM\000"
1487 /* 2698 */ "G_SREM\000"
1488 /* 2705 */ "G_UREM\000"
1489 /* 2712 */ "G_SDIVREM\000"
1490 /* 2722 */ "G_UDIVREM\000"
1491 /* 2732 */ "INLINEASM\000"
1492 /* 2742 */ "G_VECREDUCE_FMINIMUM\000"
1493 /* 2763 */ "G_FMINIMUM\000"
1494 /* 2774 */ "G_ATOMICRMW_FMINIMUM\000"
1495 /* 2795 */ "G_VECREDUCE_FMAXIMUM\000"
1496 /* 2816 */ "G_FMAXIMUM\000"
1497 /* 2827 */ "G_ATOMICRMW_FMAXIMUM\000"
1498 /* 2848 */ "G_VECREDUCE_FMINIMUMNUM\000"
1499 /* 2872 */ "G_FMINIMUMNUM\000"
1500 /* 2886 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1501 /* 2910 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1502 /* 2934 */ "G_FMAXIMUMNUM\000"
1503 /* 2948 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1504 /* 2972 */ "G_FMINNUM\000"
1505 /* 2982 */ "G_FMAXNUM\000"
1506 /* 2992 */ "G_FATAN\000"
1507 /* 3000 */ "G_FTAN\000"
1508 /* 3007 */ "G_INTRINSIC_ROUNDEVEN\000"
1509 /* 3029 */ "G_ASSERT_ALIGN\000"
1510 /* 3044 */ "G_FCOPYSIGN\000"
1511 /* 3056 */ "G_VECREDUCE_FMIN\000"
1512 /* 3073 */ "G_ATOMICRMW_FMIN\000"
1513 /* 3090 */ "G_VECREDUCE_SMIN\000"
1514 /* 3107 */ "G_SMIN\000"
1515 /* 3114 */ "G_VECREDUCE_UMIN\000"
1516 /* 3131 */ "G_UMIN\000"
1517 /* 3138 */ "G_ATOMICRMW_UMIN\000"
1518 /* 3155 */ "G_ATOMICRMW_MIN\000"
1519 /* 3171 */ "G_FASIN\000"
1520 /* 3179 */ "G_FSIN\000"
1521 /* 3186 */ "CFI_INSTRUCTION\000"
1522 /* 3202 */ "G_CTLZ_ZERO_POISON\000"
1523 /* 3221 */ "G_CTTZ_ZERO_POISON\000"
1524 /* 3240 */ "ADJCALLSTACKDOWN\000"
1525 /* 3257 */ "G_SSUBO\000"
1526 /* 3265 */ "G_USUBO\000"
1527 /* 3273 */ "G_SADDO\000"
1528 /* 3281 */ "G_UADDO\000"
1529 /* 3289 */ "LOAD_STACK_ARG_PSEUDO\000"
1530 /* 3311 */ "STORE_STACK_ARG_PSEUDO\000"
1531 /* 3334 */ "STORE_STACK_ARG_IMM_PSEUDO\000"
1532 /* 3361 */ "JUMP_TABLE_DEBUG_INFO\000"
1533 /* 3383 */ "G_SMULO\000"
1534 /* 3391 */ "G_UMULO\000"
1535 /* 3399 */ "G_BZERO\000"
1536 /* 3407 */ "STACKMAP\000"
1537 /* 3416 */ "G_DEBUGTRAP\000"
1538 /* 3428 */ "G_UBSANTRAP\000"
1539 /* 3440 */ "G_TRAP\000"
1540 /* 3447 */ "G_ATOMICRMW_UDEC_WRAP\000"
1541 /* 3469 */ "G_ATOMICRMW_UINC_WRAP\000"
1542 /* 3491 */ "G_BSWAP\000"
1543 /* 3499 */ "G_SITOFP\000"
1544 /* 3508 */ "G_UITOFP\000"
1545 /* 3517 */ "G_FCMP\000"
1546 /* 3524 */ "G_STRICT_FCMP\000"
1547 /* 3538 */ "G_ICMP\000"
1548 /* 3545 */ "G_SCMP\000"
1549 /* 3552 */ "G_UCMP\000"
1550 /* 3559 */ "JMP\000"
1551 /* 3563 */ "NOP\000"
1552 /* 3567 */ "CONVERGENCECTRL_LOOP\000"
1553 /* 3588 */ "G_CTPOP\000"
1554 /* 3596 */ "PATCHABLE_OP\000"
1555 /* 3609 */ "FAULTING_OP\000"
1556 /* 3621 */ "ADJCALLSTACKUP\000"
1557 /* 3636 */ "PREALLOCATED_SETUP\000"
1558 /* 3655 */ "G_FLDEXP\000"
1559 /* 3664 */ "G_STRICT_FLDEXP\000"
1560 /* 3680 */ "G_FEXP\000"
1561 /* 3687 */ "G_FFREXP\000"
1562 /* 3696 */ "LDDACQ\000"
1563 /* 3703 */ "G_BR\000"
1564 /* 3708 */ "INLINEASM_BR\000"
1565 /* 3721 */ "G_BLOCK_ADDR\000"
1566 /* 3734 */ "MEMBARRIER\000"
1567 /* 3745 */ "G_CONSTANT_FOLD_BARRIER\000"
1568 /* 3769 */ "PATCHABLE_FUNCTION_ENTER\000"
1569 /* 3794 */ "G_READCYCLECOUNTER\000"
1570 /* 3813 */ "G_READSTEADYCOUNTER\000"
1571 /* 3833 */ "G_READ_REGISTER\000"
1572 /* 3849 */ "G_WRITE_REGISTER\000"
1573 /* 3866 */ "G_ASHR\000"
1574 /* 3873 */ "G_FSHR\000"
1575 /* 3880 */ "G_LSHR\000"
1576 /* 3887 */ "CONVERGENCECTRL_ANCHOR\000"
1577 /* 3910 */ "G_FFLOOR\000"
1578 /* 3919 */ "G_SAVGFLOOR\000"
1579 /* 3931 */ "G_UAVGFLOOR\000"
1580 /* 3943 */ "G_EXTRACT_SUBVECTOR\000"
1581 /* 3963 */ "G_INSERT_SUBVECTOR\000"
1582 /* 3982 */ "G_BUILD_VECTOR\000"
1583 /* 3997 */ "G_SHUFFLE_VECTOR\000"
1584 /* 4014 */ "G_STEP_VECTOR\000"
1585 /* 4028 */ "G_SPLAT_VECTOR\000"
1586 /* 4043 */ "G_VECREDUCE_XOR\000"
1587 /* 4059 */ "G_XOR\000"
1588 /* 4065 */ "G_ATOMICRMW_XOR\000"
1589 /* 4081 */ "G_VECREDUCE_OR\000"
1590 /* 4096 */ "G_OR\000"
1591 /* 4101 */ "G_ATOMICRMW_OR\000"
1592 /* 4116 */ "G_ROTR\000"
1593 /* 4123 */ "G_INTTOPTR\000"
1594 /* 4134 */ "G_FABS\000"
1595 /* 4141 */ "G_ABS\000"
1596 /* 4147 */ "G_ABDS\000"
1597 /* 4154 */ "G_UNMERGE_VALUES\000"
1598 /* 4171 */ "G_MERGE_VALUES\000"
1599 /* 4186 */ "G_CTLS\000"
1600 /* 4193 */ "G_FACOS\000"
1601 /* 4201 */ "G_FCOS\000"
1602 /* 4208 */ "G_FSINCOS\000"
1603 /* 4218 */ "G_STRICT_FCMPS\000"
1604 /* 4233 */ "G_CONCAT_VECTORS\000"
1605 /* 4250 */ "COPY_TO_REGCLASS\000"
1606 /* 4267 */ "G_IS_FPCLASS\000"
1607 /* 4280 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1608 /* 4310 */ "G_VECTOR_COMPRESS\000"
1609 /* 4328 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1610 /* 4355 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1611 /* 4393 */ "G_TRUNC_SSAT_S\000"
1612 /* 4408 */ "G_SSUBSAT\000"
1613 /* 4418 */ "G_USUBSAT\000"
1614 /* 4428 */ "G_SADDSAT\000"
1615 /* 4438 */ "G_UADDSAT\000"
1616 /* 4448 */ "G_SSHLSAT\000"
1617 /* 4458 */ "G_USHLSAT\000"
1618 /* 4468 */ "G_SMULFIXSAT\000"
1619 /* 4481 */ "G_UMULFIXSAT\000"
1620 /* 4494 */ "G_SDIVFIXSAT\000"
1621 /* 4507 */ "G_UDIVFIXSAT\000"
1622 /* 4520 */ "G_ATOMICRMW_USUB_SAT\000"
1623 /* 4541 */ "G_FPTOSI_SAT\000"
1624 /* 4554 */ "G_FPTOUI_SAT\000"
1625 /* 4567 */ "G_EXTRACT\000"
1626 /* 4577 */ "G_SELECT\000"
1627 /* 4586 */ "G_BRINDIRECT\000"
1628 /* 4599 */ "PATCHABLE_RET\000"
1629 /* 4613 */ "G_MEMSET\000"
1630 /* 4622 */ "CORE_SHIFT\000"
1631 /* 4633 */ "PATCHABLE_FUNCTION_EXIT\000"
1632 /* 4657 */ "G_BRJT\000"
1633 /* 4664 */ "G_EXTRACT_VECTOR_ELT\000"
1634 /* 4685 */ "G_INSERT_VECTOR_ELT\000"
1635 /* 4705 */ "G_FCONSTANT\000"
1636 /* 4717 */ "G_CONSTANT\000"
1637 /* 4728 */ "G_INTRINSIC_CONVERGENT\000"
1638 /* 4751 */ "STATEPOINT\000"
1639 /* 4762 */ "PATCHPOINT\000"
1640 /* 4773 */ "G_PTRTOINT\000"
1641 /* 4784 */ "G_FRINT\000"
1642 /* 4792 */ "G_INTRINSIC_LLRINT\000"
1643 /* 4811 */ "G_INTRINSIC_LRINT\000"
1644 /* 4829 */ "G_FNEARBYINT\000"
1645 /* 4842 */ "G_VASTART\000"
1646 /* 4852 */ "LIFETIME_START\000"
1647 /* 4867 */ "G_INVOKE_REGION_START\000"
1648 /* 4889 */ "G_INSERT\000"
1649 /* 4898 */ "G_FSQRT\000"
1650 /* 4906 */ "G_STRICT_FSQRT\000"
1651 /* 4921 */ "G_BITCAST\000"
1652 /* 4931 */ "G_ADDRSPACE_CAST\000"
1653 /* 4948 */ "ADDR_SPACE_CAST\000"
1654 /* 4964 */ "DBG_VALUE_LIST\000"
1655 /* 4979 */ "CORE_ST\000"
1656 /* 4987 */ "G_FPEXT\000"
1657 /* 4995 */ "G_SEXT\000"
1658 /* 5002 */ "G_ASSERT_SEXT\000"
1659 /* 5016 */ "G_ANYEXT\000"
1660 /* 5025 */ "G_ZEXT\000"
1661 /* 5032 */ "G_ASSERT_ZEXT\000"
1662 /* 5046 */ "G_ABDU\000"
1663 /* 5053 */ "G_TRUNC_SSAT_U\000"
1664 /* 5068 */ "G_TRUNC_USAT_U\000"
1665 /* 5083 */ "G_FDIV\000"
1666 /* 5090 */ "G_STRICT_FDIV\000"
1667 /* 5104 */ "G_SDIV\000"
1668 /* 5111 */ "G_UDIV\000"
1669 /* 5118 */ "G_GET_FPENV\000"
1670 /* 5130 */ "G_RESET_FPENV\000"
1671 /* 5144 */ "G_SET_FPENV\000"
1672 /* 5156 */ "XADDW\000"
1673 /* 5162 */ "LDW\000"
1674 /* 5166 */ "G_FPOW\000"
1675 /* 5173 */ "STW\000"
1676 /* 5177 */ "LD_IND_W\000"
1677 /* 5186 */ "LD_ABS_W\000"
1678 /* 5195 */ "G_VECREDUCE_FMAX\000"
1679 /* 5212 */ "G_ATOMICRMW_FMAX\000"
1680 /* 5229 */ "G_VECREDUCE_SMAX\000"
1681 /* 5246 */ "G_SMAX\000"
1682 /* 5253 */ "G_VECREDUCE_UMAX\000"
1683 /* 5270 */ "G_UMAX\000"
1684 /* 5277 */ "G_ATOMICRMW_UMAX\000"
1685 /* 5294 */ "G_ATOMICRMW_MAX\000"
1686 /* 5310 */ "G_FRAME_INDEX\000"
1687 /* 5324 */ "G_SBFX\000"
1688 /* 5331 */ "G_UBFX\000"
1689 /* 5338 */ "G_SMULFIX\000"
1690 /* 5348 */ "G_UMULFIX\000"
1691 /* 5358 */ "G_SDIVFIX\000"
1692 /* 5368 */ "G_UDIVFIX\000"
1693 /* 5378 */ "JX\000"
1694 /* 5381 */ "JALX\000"
1695 /* 5386 */ "LDBSX\000"
1696 /* 5392 */ "LDHSX\000"
1697 /* 5398 */ "LDWSX\000"
1698 /* 5404 */ "G_MEMCPY\000"
1699 /* 5413 */ "COPY\000"
1700 /* 5418 */ "CONVERGENCECTRL_ENTRY\000"
1701 /* 5440 */ "G_CTLZ\000"
1702 /* 5447 */ "G_CTTZ\000"
1703 /* 5454 */ "Select_Ri\000"
1704 /* 5464 */ "SRA_ri\000"
1705 /* 5471 */ "SUB_ri\000"
1706 /* 5478 */ "ADD_ri\000"
1707 /* 5485 */ "AND_ri\000"
1708 /* 5492 */ "SMOD_ri\000"
1709 /* 5500 */ "JSGE_ri\000"
1710 /* 5508 */ "JUGE_ri\000"
1711 /* 5516 */ "JSLE_ri\000"
1712 /* 5524 */ "JULE_ri\000"
1713 /* 5532 */ "JNE_ri\000"
1714 /* 5539 */ "FI_ri\000"
1715 /* 5545 */ "SLL_ri\000"
1716 /* 5552 */ "SRL_ri\000"
1717 /* 5559 */ "MUL_ri\000"
1718 /* 5566 */ "JEQ_ri\000"
1719 /* 5573 */ "XOR_ri\000"
1720 /* 5580 */ "JSET_ri\000"
1721 /* 5588 */ "JSGT_ri\000"
1722 /* 5596 */ "JUGT_ri\000"
1723 /* 5604 */ "JSLT_ri\000"
1724 /* 5612 */ "JULT_ri\000"
1725 /* 5620 */ "SDIV_ri\000"
1726 /* 5628 */ "MOV_ri\000"
1727 /* 5635 */ "STB_imm\000"
1728 /* 5643 */ "STD_imm\000"
1729 /* 5651 */ "STH_imm\000"
1730 /* 5659 */ "STW_imm\000"
1731 /* 5667 */ "LD_pseudo\000"
1732 /* 5677 */ "SRA_rr\000"
1733 /* 5684 */ "SUB_rr\000"
1734 /* 5691 */ "ADD_rr\000"
1735 /* 5698 */ "AND_rr\000"
1736 /* 5705 */ "SMOD_rr\000"
1737 /* 5713 */ "JSGE_rr\000"
1738 /* 5721 */ "JUGE_rr\000"
1739 /* 5729 */ "JSLE_rr\000"
1740 /* 5737 */ "JULE_rr\000"
1741 /* 5745 */ "JNE_rr\000"
1742 /* 5752 */ "SLL_rr\000"
1743 /* 5759 */ "SRL_rr\000"
1744 /* 5766 */ "MUL_rr\000"
1745 /* 5773 */ "JEQ_rr\000"
1746 /* 5780 */ "XOR_rr\000"
1747 /* 5787 */ "JSET_rr\000"
1748 /* 5795 */ "JSGT_rr\000"
1749 /* 5803 */ "JUGT_rr\000"
1750 /* 5811 */ "JSLT_rr\000"
1751 /* 5819 */ "JULT_rr\000"
1752 /* 5827 */ "SDIV_rr\000"
1753 /* 5835 */ "MOV_rr\000"
1754 /* 5842 */ "Select\000"
1755};
1756#ifdef __GNUC__
1757#pragma GCC diagnostic pop
1758#endif
1759
1760extern const unsigned BPFInstrNameIndices[] = {
1761 2302U, 2732U, 3708U, 3186U, 2379U, 2360U, 2388U, 2555U,
1762 2069U, 2084U, 2035U, 2022U, 2111U, 4250U, 1898U, 4964U,
1763 2048U, 2298U, 2369U, 1637U, 5413U, 2332U, 1759U, 4852U,
1764 1435U, 1588U, 1625U, 3407U, 2543U, 4762U, 1548U, 3636U,
1765 2204U, 4751U, 1809U, 3609U, 3596U, 3769U, 4599U, 4633U,
1766 2475U, 2522U, 2495U, 2405U, 1889U, 3734U, 3361U, 1798U,
1767 5418U, 3887U, 3567U, 1946U, 5002U, 5032U, 3029U, 1309U,
1768 990U, 2671U, 5104U, 5111U, 2698U, 2705U, 2712U, 2722U,
1769 1413U, 4096U, 4059U, 4147U, 5046U, 3931U, 2464U, 3919U,
1770 2453U, 2033U, 2300U, 5310U, 1908U, 1923U, 2560U, 4567U,
1771 4154U, 4889U, 4171U, 3982U, 1078U, 4233U, 4773U, 4123U,
1772 4921U, 1989U, 3745U, 1522U, 1052U, 1504U, 4811U, 4792U,
1773 3007U, 3794U, 3813U, 1210U, 1154U, 1184U, 1123U, 1195U,
1774 1135U, 1165U, 1868U, 1822U, 1852U, 4280U, 2125U, 2142U,
1775 1325U, 996U, 1419U, 1380U, 4101U, 4065U, 5294U, 3155U,
1776 5277U, 3138U, 1276U, 973U, 5212U, 3073U, 2827U, 2774U,
1777 2948U, 2886U, 3469U, 3447U, 1463U, 4520U, 1617U, 2221U,
1778 1454U, 4586U, 4867U, 1030U, 4328U, 4728U, 4355U, 5016U,
1779 1070U, 4393U, 5053U, 5068U, 4717U, 4705U, 4842U, 2196U,
1780 4995U, 2098U, 5025U, 2439U, 3880U, 3866U, 2432U, 3873U,
1781 4116U, 2581U, 3538U, 3517U, 3545U, 3552U, 4577U, 3281U,
1782 1658U, 3265U, 1609U, 3273U, 1650U, 3257U, 1601U, 3391U,
1783 3383U, 2244U, 2236U, 4438U, 4428U, 4418U, 4408U, 4458U,
1784 4448U, 5338U, 5348U, 4468U, 4481U, 5358U, 5368U, 4494U,
1785 4507U, 1234U, 952U, 2605U, 925U, 1116U, 5083U, 2677U,
1786 2014U, 5166U, 2324U, 3680U, 756U, 9U, 2189U, 739U,
1787 0U, 3655U, 3687U, 2062U, 4987U, 1042U, 2306U, 2315U,
1788 3499U, 3508U, 4541U, 4554U, 4134U, 3044U, 4267U, 1998U,
1789 2972U, 2982U, 1707U, 1722U, 2763U, 2816U, 2872U, 2934U,
1790 5118U, 5144U, 5130U, 1666U, 1694U, 1679U, 2159U, 2174U,
1791 1315U, 2346U, 3107U, 5246U, 3131U, 5270U, 4141U, 1495U,
1792 1485U, 3703U, 4657U, 1737U, 3963U, 3943U, 4685U, 4664U,
1793 3997U, 4028U, 4014U, 4310U, 5447U, 3221U, 5440U, 3202U,
1794 4186U, 3588U, 3491U, 1876U, 2647U, 2445U, 4201U, 3179U,
1795 4208U, 3000U, 4193U, 3171U, 2992U, 747U, 2268U, 2260U,
1796 2252U, 4898U, 3910U, 4784U, 4829U, 4931U, 3721U, 1746U,
1797 1099U, 1967U, 1837U, 1262U, 959U, 2633U, 5090U, 2684U,
1798 931U, 4906U, 3664U, 3524U, 4218U, 3833U, 3849U, 5404U,
1799 1782U, 1979U, 4613U, 3399U, 1766U, 3440U, 3416U, 3428U,
1800 1241U, 2612U, 1217U, 2588U, 5195U, 3056U, 2795U, 2742U,
1801 2910U, 2848U, 1293U, 2655U, 1397U, 4081U, 4043U, 5229U,
1802 3090U, 5253U, 3114U, 5324U, 5331U, 3240U, 3621U, 5539U,
1803 784U, 3289U, 5406U, 3334U, 3311U, 5842U, 729U, 826U,
1804 222U, 5454U, 242U, 810U, 206U, 4948U, 5478U, 275U,
1805 5691U, 506U, 5485U, 285U, 5698U, 516U, 855U, 40U,
1806 774U, 865U, 89U, 792U, 1371U, 164U, 30U, 764U,
1807 4622U, 4979U, 5621U, 466U, 5828U, 697U, 2356U, 5381U,
1808 1448U, 5566U, 390U, 5773U, 621U, 3559U, 2576U, 5532U,
1809 350U, 5745U, 581U, 5580U, 410U, 5787U, 641U, 5500U,
1810 306U, 5713U, 537U, 5588U, 421U, 5795U, 652U, 5516U,
1811 328U, 5729U, 559U, 5604U, 443U, 5811U, 674U, 5508U,
1812 317U, 5721U, 548U, 5596U, 432U, 5803U, 663U, 5524U,
1813 339U, 5737U, 570U, 5612U, 454U, 5819U, 685U, 5378U,
1814 944U, 18U, 97U, 5386U, 1354U, 3696U, 2232U, 50U,
1815 106U, 5392U, 5162U, 141U, 115U, 5398U, 1021U, 2289U,
1816 5186U, 1012U, 2280U, 5177U, 846U, 5667U, 860U, 45U,
1817 779U, 5493U, 296U, 5706U, 527U, 888U, 717U, 873U,
1818 900U, 914U, 800U, 5628U, 476U, 5835U, 707U, 5559U,
1819 380U, 5766U, 611U, 235U, 839U, 3563U, 5574U, 401U,
1820 5781U, 632U, 4609U, 5620U, 465U, 5827U, 696U, 5545U,
1821 360U, 5752U, 591U, 5492U, 295U, 5705U, 526U, 5464U,
1822 255U, 5677U, 486U, 5552U, 370U, 5759U, 601U, 948U,
1823 24U, 62U, 5635U, 1584U, 2425U, 5643U, 2276U, 56U,
1824 71U, 5651U, 5173U, 200U, 80U, 5659U, 5471U, 265U,
1825 5684U, 496U, 1348U, 5156U, 133U, 1365U, 156U, 1374U,
1826 167U, 1341U, 124U, 1358U, 147U, 1565U, 175U, 1571U,
1827 183U, 1573U, 185U, 5573U, 400U, 5780U, 631U, 1578U,
1828 192U,
1829};
1830
1831static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
1832 II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 537, nullptr, 0);
1833}
1834
1835
1836} // namespace llvm
1837
1838#endif // GET_INSTRINFO_MC_DESC
1839
1840#ifdef GET_INSTRINFO_HEADER
1841#undef GET_INSTRINFO_HEADER
1842
1843namespace llvm {
1844
1845struct BPFGenInstrInfo : public TargetInstrInfo {
1846 explicit BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1847 ~BPFGenInstrInfo() override = default;
1848};
1849
1850} // namespace llvm
1851
1852namespace llvm::BPF {
1853
1854
1855} // namespace llvm::BPF
1856
1857#endif // GET_INSTRINFO_HEADER
1858
1859#ifdef GET_INSTRINFO_HELPER_DECLS
1860#undef GET_INSTRINFO_HELPER_DECLS
1861
1862
1863#endif // GET_INSTRINFO_HELPER_DECLS
1864
1865#ifdef GET_INSTRINFO_HELPERS
1866#undef GET_INSTRINFO_HELPERS
1867
1868
1869#endif // GET_INSTRINFO_HELPERS
1870
1871#ifdef GET_INSTRINFO_CTOR_DTOR
1872#undef GET_INSTRINFO_CTOR_DTOR
1873
1874namespace llvm {
1875
1876extern const BPFInstrTable BPFDescs;
1877extern const unsigned BPFInstrNameIndices[];
1878extern const char BPFInstrNameData[];
1879BPFGenInstrInfo::BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1880 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1881 InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 537);
1882}
1883
1884} // namespace llvm
1885
1886#endif // GET_INSTRINFO_CTOR_DTOR
1887
1888#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1889#undef GET_INSTRINFO_MC_HELPER_DECLS
1890
1891namespace llvm {
1892
1893class MCInst;
1894class FeatureBitset;
1895
1896namespace BPF_MC {
1897
1898void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1899
1900} // namespace BPF_MC
1901
1902} // namespace llvm
1903
1904#endif // GET_INSTRINFO_MC_HELPER_DECLS
1905
1906#ifdef GET_INSTRINFO_MC_HELPERS
1907#undef GET_INSTRINFO_MC_HELPERS
1908
1909namespace llvm::BPF_MC {
1910
1911
1912} // namespace llvm::BPF_MC
1913
1914#endif // GET_INSTRINFO_MC_HELPERS
1915
1916#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1917 defined(GET_AVAILABLE_OPCODE_CHECKER)
1918#define GET_COMPUTE_FEATURES
1919#endif
1920#ifdef GET_COMPUTE_FEATURES
1921#undef GET_COMPUTE_FEATURES
1922
1923namespace llvm::BPF_MC {
1924
1925// Bits for subtarget features that participate in instruction matching.
1926enum SubtargetFeatureBits : uint8_t {
1927};
1928
1929inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1930 FeatureBitset Features;
1931 return Features;
1932}
1933
1934inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1935 enum : uint8_t {
1936 CEFBS_None,
1937 };
1938
1939 static constexpr FeatureBitset FeatureBitsets[] = {
1940 {}, // CEFBS_None
1941 };
1942 static constexpr uint8_t RequiredFeaturesRefs[] = {
1943 CEFBS_None, // PHI
1944 CEFBS_None, // INLINEASM
1945 CEFBS_None, // INLINEASM_BR
1946 CEFBS_None, // CFI_INSTRUCTION
1947 CEFBS_None, // EH_LABEL
1948 CEFBS_None, // GC_LABEL
1949 CEFBS_None, // ANNOTATION_LABEL
1950 CEFBS_None, // KILL
1951 CEFBS_None, // EXTRACT_SUBREG
1952 CEFBS_None, // INSERT_SUBREG
1953 CEFBS_None, // IMPLICIT_DEF
1954 CEFBS_None, // INIT_UNDEF
1955 CEFBS_None, // SUBREG_TO_REG
1956 CEFBS_None, // COPY_TO_REGCLASS
1957 CEFBS_None, // DBG_VALUE
1958 CEFBS_None, // DBG_VALUE_LIST
1959 CEFBS_None, // DBG_INSTR_REF
1960 CEFBS_None, // DBG_PHI
1961 CEFBS_None, // DBG_LABEL
1962 CEFBS_None, // REG_SEQUENCE
1963 CEFBS_None, // COPY
1964 CEFBS_None, // COPY_LANEMASK
1965 CEFBS_None, // BUNDLE
1966 CEFBS_None, // LIFETIME_START
1967 CEFBS_None, // LIFETIME_END
1968 CEFBS_None, // PSEUDO_PROBE
1969 CEFBS_None, // ARITH_FENCE
1970 CEFBS_None, // STACKMAP
1971 CEFBS_None, // FENTRY_CALL
1972 CEFBS_None, // PATCHPOINT
1973 CEFBS_None, // LOAD_STACK_GUARD
1974 CEFBS_None, // PREALLOCATED_SETUP
1975 CEFBS_None, // PREALLOCATED_ARG
1976 CEFBS_None, // STATEPOINT
1977 CEFBS_None, // LOCAL_ESCAPE
1978 CEFBS_None, // FAULTING_OP
1979 CEFBS_None, // PATCHABLE_OP
1980 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1981 CEFBS_None, // PATCHABLE_RET
1982 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1983 CEFBS_None, // PATCHABLE_TAIL_CALL
1984 CEFBS_None, // PATCHABLE_EVENT_CALL
1985 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1986 CEFBS_None, // ICALL_BRANCH_FUNNEL
1987 CEFBS_None, // FAKE_USE
1988 CEFBS_None, // MEMBARRIER
1989 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1990 CEFBS_None, // RELOC_NONE
1991 CEFBS_None, // CONVERGENCECTRL_ENTRY
1992 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1993 CEFBS_None, // CONVERGENCECTRL_LOOP
1994 CEFBS_None, // CONVERGENCECTRL_GLUE
1995 CEFBS_None, // G_ASSERT_SEXT
1996 CEFBS_None, // G_ASSERT_ZEXT
1997 CEFBS_None, // G_ASSERT_ALIGN
1998 CEFBS_None, // G_ADD
1999 CEFBS_None, // G_SUB
2000 CEFBS_None, // G_MUL
2001 CEFBS_None, // G_SDIV
2002 CEFBS_None, // G_UDIV
2003 CEFBS_None, // G_SREM
2004 CEFBS_None, // G_UREM
2005 CEFBS_None, // G_SDIVREM
2006 CEFBS_None, // G_UDIVREM
2007 CEFBS_None, // G_AND
2008 CEFBS_None, // G_OR
2009 CEFBS_None, // G_XOR
2010 CEFBS_None, // G_ABDS
2011 CEFBS_None, // G_ABDU
2012 CEFBS_None, // G_UAVGFLOOR
2013 CEFBS_None, // G_UAVGCEIL
2014 CEFBS_None, // G_SAVGFLOOR
2015 CEFBS_None, // G_SAVGCEIL
2016 CEFBS_None, // G_IMPLICIT_DEF
2017 CEFBS_None, // G_PHI
2018 CEFBS_None, // G_FRAME_INDEX
2019 CEFBS_None, // G_GLOBAL_VALUE
2020 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2021 CEFBS_None, // G_CONSTANT_POOL
2022 CEFBS_None, // G_EXTRACT
2023 CEFBS_None, // G_UNMERGE_VALUES
2024 CEFBS_None, // G_INSERT
2025 CEFBS_None, // G_MERGE_VALUES
2026 CEFBS_None, // G_BUILD_VECTOR
2027 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2028 CEFBS_None, // G_CONCAT_VECTORS
2029 CEFBS_None, // G_PTRTOINT
2030 CEFBS_None, // G_INTTOPTR
2031 CEFBS_None, // G_BITCAST
2032 CEFBS_None, // G_FREEZE
2033 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2034 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2035 CEFBS_None, // G_INTRINSIC_TRUNC
2036 CEFBS_None, // G_INTRINSIC_ROUND
2037 CEFBS_None, // G_INTRINSIC_LRINT
2038 CEFBS_None, // G_INTRINSIC_LLRINT
2039 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2040 CEFBS_None, // G_READCYCLECOUNTER
2041 CEFBS_None, // G_READSTEADYCOUNTER
2042 CEFBS_None, // G_LOAD
2043 CEFBS_None, // G_SEXTLOAD
2044 CEFBS_None, // G_ZEXTLOAD
2045 CEFBS_None, // G_FPEXTLOAD
2046 CEFBS_None, // G_INDEXED_LOAD
2047 CEFBS_None, // G_INDEXED_SEXTLOAD
2048 CEFBS_None, // G_INDEXED_ZEXTLOAD
2049 CEFBS_None, // G_STORE
2050 CEFBS_None, // G_FPTRUNCSTORE
2051 CEFBS_None, // G_INDEXED_STORE
2052 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2053 CEFBS_None, // G_ATOMIC_CMPXCHG
2054 CEFBS_None, // G_ATOMICRMW_XCHG
2055 CEFBS_None, // G_ATOMICRMW_ADD
2056 CEFBS_None, // G_ATOMICRMW_SUB
2057 CEFBS_None, // G_ATOMICRMW_AND
2058 CEFBS_None, // G_ATOMICRMW_NAND
2059 CEFBS_None, // G_ATOMICRMW_OR
2060 CEFBS_None, // G_ATOMICRMW_XOR
2061 CEFBS_None, // G_ATOMICRMW_MAX
2062 CEFBS_None, // G_ATOMICRMW_MIN
2063 CEFBS_None, // G_ATOMICRMW_UMAX
2064 CEFBS_None, // G_ATOMICRMW_UMIN
2065 CEFBS_None, // G_ATOMICRMW_FADD
2066 CEFBS_None, // G_ATOMICRMW_FSUB
2067 CEFBS_None, // G_ATOMICRMW_FMAX
2068 CEFBS_None, // G_ATOMICRMW_FMIN
2069 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2070 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2071 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2072 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2073 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2074 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2075 CEFBS_None, // G_ATOMICRMW_USUB_COND
2076 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2077 CEFBS_None, // G_FENCE
2078 CEFBS_None, // G_PREFETCH
2079 CEFBS_None, // G_BRCOND
2080 CEFBS_None, // G_BRINDIRECT
2081 CEFBS_None, // G_INVOKE_REGION_START
2082 CEFBS_None, // G_INTRINSIC
2083 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2084 CEFBS_None, // G_INTRINSIC_CONVERGENT
2085 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2086 CEFBS_None, // G_ANYEXT
2087 CEFBS_None, // G_TRUNC
2088 CEFBS_None, // G_TRUNC_SSAT_S
2089 CEFBS_None, // G_TRUNC_SSAT_U
2090 CEFBS_None, // G_TRUNC_USAT_U
2091 CEFBS_None, // G_CONSTANT
2092 CEFBS_None, // G_FCONSTANT
2093 CEFBS_None, // G_VASTART
2094 CEFBS_None, // G_VAARG
2095 CEFBS_None, // G_SEXT
2096 CEFBS_None, // G_SEXT_INREG
2097 CEFBS_None, // G_ZEXT
2098 CEFBS_None, // G_SHL
2099 CEFBS_None, // G_LSHR
2100 CEFBS_None, // G_ASHR
2101 CEFBS_None, // G_FSHL
2102 CEFBS_None, // G_FSHR
2103 CEFBS_None, // G_ROTR
2104 CEFBS_None, // G_ROTL
2105 CEFBS_None, // G_ICMP
2106 CEFBS_None, // G_FCMP
2107 CEFBS_None, // G_SCMP
2108 CEFBS_None, // G_UCMP
2109 CEFBS_None, // G_SELECT
2110 CEFBS_None, // G_UADDO
2111 CEFBS_None, // G_UADDE
2112 CEFBS_None, // G_USUBO
2113 CEFBS_None, // G_USUBE
2114 CEFBS_None, // G_SADDO
2115 CEFBS_None, // G_SADDE
2116 CEFBS_None, // G_SSUBO
2117 CEFBS_None, // G_SSUBE
2118 CEFBS_None, // G_UMULO
2119 CEFBS_None, // G_SMULO
2120 CEFBS_None, // G_UMULH
2121 CEFBS_None, // G_SMULH
2122 CEFBS_None, // G_UADDSAT
2123 CEFBS_None, // G_SADDSAT
2124 CEFBS_None, // G_USUBSAT
2125 CEFBS_None, // G_SSUBSAT
2126 CEFBS_None, // G_USHLSAT
2127 CEFBS_None, // G_SSHLSAT
2128 CEFBS_None, // G_SMULFIX
2129 CEFBS_None, // G_UMULFIX
2130 CEFBS_None, // G_SMULFIXSAT
2131 CEFBS_None, // G_UMULFIXSAT
2132 CEFBS_None, // G_SDIVFIX
2133 CEFBS_None, // G_UDIVFIX
2134 CEFBS_None, // G_SDIVFIXSAT
2135 CEFBS_None, // G_UDIVFIXSAT
2136 CEFBS_None, // G_FADD
2137 CEFBS_None, // G_FSUB
2138 CEFBS_None, // G_FMUL
2139 CEFBS_None, // G_FMA
2140 CEFBS_None, // G_FMAD
2141 CEFBS_None, // G_FDIV
2142 CEFBS_None, // G_FREM
2143 CEFBS_None, // G_FMODF
2144 CEFBS_None, // G_FPOW
2145 CEFBS_None, // G_FPOWI
2146 CEFBS_None, // G_FEXP
2147 CEFBS_None, // G_FEXP2
2148 CEFBS_None, // G_FEXP10
2149 CEFBS_None, // G_FLOG
2150 CEFBS_None, // G_FLOG2
2151 CEFBS_None, // G_FLOG10
2152 CEFBS_None, // G_FLDEXP
2153 CEFBS_None, // G_FFREXP
2154 CEFBS_None, // G_FNEG
2155 CEFBS_None, // G_FPEXT
2156 CEFBS_None, // G_FPTRUNC
2157 CEFBS_None, // G_FPTOSI
2158 CEFBS_None, // G_FPTOUI
2159 CEFBS_None, // G_SITOFP
2160 CEFBS_None, // G_UITOFP
2161 CEFBS_None, // G_FPTOSI_SAT
2162 CEFBS_None, // G_FPTOUI_SAT
2163 CEFBS_None, // G_FABS
2164 CEFBS_None, // G_FCOPYSIGN
2165 CEFBS_None, // G_IS_FPCLASS
2166 CEFBS_None, // G_FCANONICALIZE
2167 CEFBS_None, // G_FMINNUM
2168 CEFBS_None, // G_FMAXNUM
2169 CEFBS_None, // G_FMINNUM_IEEE
2170 CEFBS_None, // G_FMAXNUM_IEEE
2171 CEFBS_None, // G_FMINIMUM
2172 CEFBS_None, // G_FMAXIMUM
2173 CEFBS_None, // G_FMINIMUMNUM
2174 CEFBS_None, // G_FMAXIMUMNUM
2175 CEFBS_None, // G_GET_FPENV
2176 CEFBS_None, // G_SET_FPENV
2177 CEFBS_None, // G_RESET_FPENV
2178 CEFBS_None, // G_GET_FPMODE
2179 CEFBS_None, // G_SET_FPMODE
2180 CEFBS_None, // G_RESET_FPMODE
2181 CEFBS_None, // G_GET_ROUNDING
2182 CEFBS_None, // G_SET_ROUNDING
2183 CEFBS_None, // G_PTR_ADD
2184 CEFBS_None, // G_PTRMASK
2185 CEFBS_None, // G_SMIN
2186 CEFBS_None, // G_SMAX
2187 CEFBS_None, // G_UMIN
2188 CEFBS_None, // G_UMAX
2189 CEFBS_None, // G_ABS
2190 CEFBS_None, // G_LROUND
2191 CEFBS_None, // G_LLROUND
2192 CEFBS_None, // G_BR
2193 CEFBS_None, // G_BRJT
2194 CEFBS_None, // G_VSCALE
2195 CEFBS_None, // G_INSERT_SUBVECTOR
2196 CEFBS_None, // G_EXTRACT_SUBVECTOR
2197 CEFBS_None, // G_INSERT_VECTOR_ELT
2198 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2199 CEFBS_None, // G_SHUFFLE_VECTOR
2200 CEFBS_None, // G_SPLAT_VECTOR
2201 CEFBS_None, // G_STEP_VECTOR
2202 CEFBS_None, // G_VECTOR_COMPRESS
2203 CEFBS_None, // G_CTTZ
2204 CEFBS_None, // G_CTTZ_ZERO_POISON
2205 CEFBS_None, // G_CTLZ
2206 CEFBS_None, // G_CTLZ_ZERO_POISON
2207 CEFBS_None, // G_CTLS
2208 CEFBS_None, // G_CTPOP
2209 CEFBS_None, // G_BSWAP
2210 CEFBS_None, // G_BITREVERSE
2211 CEFBS_None, // G_CLMUL
2212 CEFBS_None, // G_FCEIL
2213 CEFBS_None, // G_FCOS
2214 CEFBS_None, // G_FSIN
2215 CEFBS_None, // G_FSINCOS
2216 CEFBS_None, // G_FTAN
2217 CEFBS_None, // G_FACOS
2218 CEFBS_None, // G_FASIN
2219 CEFBS_None, // G_FATAN
2220 CEFBS_None, // G_FATAN2
2221 CEFBS_None, // G_FCOSH
2222 CEFBS_None, // G_FSINH
2223 CEFBS_None, // G_FTANH
2224 CEFBS_None, // G_FSQRT
2225 CEFBS_None, // G_FFLOOR
2226 CEFBS_None, // G_FRINT
2227 CEFBS_None, // G_FNEARBYINT
2228 CEFBS_None, // G_ADDRSPACE_CAST
2229 CEFBS_None, // G_BLOCK_ADDR
2230 CEFBS_None, // G_JUMP_TABLE
2231 CEFBS_None, // G_DYN_STACKALLOC
2232 CEFBS_None, // G_STACKSAVE
2233 CEFBS_None, // G_STACKRESTORE
2234 CEFBS_None, // G_STRICT_FADD
2235 CEFBS_None, // G_STRICT_FSUB
2236 CEFBS_None, // G_STRICT_FMUL
2237 CEFBS_None, // G_STRICT_FDIV
2238 CEFBS_None, // G_STRICT_FREM
2239 CEFBS_None, // G_STRICT_FMA
2240 CEFBS_None, // G_STRICT_FSQRT
2241 CEFBS_None, // G_STRICT_FLDEXP
2242 CEFBS_None, // G_STRICT_FCMP
2243 CEFBS_None, // G_STRICT_FCMPS
2244 CEFBS_None, // G_READ_REGISTER
2245 CEFBS_None, // G_WRITE_REGISTER
2246 CEFBS_None, // G_MEMCPY
2247 CEFBS_None, // G_MEMCPY_INLINE
2248 CEFBS_None, // G_MEMMOVE
2249 CEFBS_None, // G_MEMSET
2250 CEFBS_None, // G_BZERO
2251 CEFBS_None, // G_MEMSET_INLINE
2252 CEFBS_None, // G_TRAP
2253 CEFBS_None, // G_DEBUGTRAP
2254 CEFBS_None, // G_UBSANTRAP
2255 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2256 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2257 CEFBS_None, // G_VECREDUCE_FADD
2258 CEFBS_None, // G_VECREDUCE_FMUL
2259 CEFBS_None, // G_VECREDUCE_FMAX
2260 CEFBS_None, // G_VECREDUCE_FMIN
2261 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2262 CEFBS_None, // G_VECREDUCE_FMINIMUM
2263 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2264 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2265 CEFBS_None, // G_VECREDUCE_ADD
2266 CEFBS_None, // G_VECREDUCE_MUL
2267 CEFBS_None, // G_VECREDUCE_AND
2268 CEFBS_None, // G_VECREDUCE_OR
2269 CEFBS_None, // G_VECREDUCE_XOR
2270 CEFBS_None, // G_VECREDUCE_SMAX
2271 CEFBS_None, // G_VECREDUCE_SMIN
2272 CEFBS_None, // G_VECREDUCE_UMAX
2273 CEFBS_None, // G_VECREDUCE_UMIN
2274 CEFBS_None, // G_SBFX
2275 CEFBS_None, // G_UBFX
2276 CEFBS_None, // ADJCALLSTACKDOWN
2277 CEFBS_None, // ADJCALLSTACKUP
2278 CEFBS_None, // FI_ri
2279 CEFBS_None, // LDIMM64
2280 CEFBS_None, // LOAD_STACK_ARG_PSEUDO
2281 CEFBS_None, // MEMCPY
2282 CEFBS_None, // STORE_STACK_ARG_IMM_PSEUDO
2283 CEFBS_None, // STORE_STACK_ARG_PSEUDO
2284 CEFBS_None, // Select
2285 CEFBS_None, // Select_32
2286 CEFBS_None, // Select_32_64
2287 CEFBS_None, // Select_64_32
2288 CEFBS_None, // Select_Ri
2289 CEFBS_None, // Select_Ri_32
2290 CEFBS_None, // Select_Ri_32_64
2291 CEFBS_None, // Select_Ri_64_32
2292 CEFBS_None, // ADDR_SPACE_CAST
2293 CEFBS_None, // ADD_ri
2294 CEFBS_None, // ADD_ri_32
2295 CEFBS_None, // ADD_rr
2296 CEFBS_None, // ADD_rr_32
2297 CEFBS_None, // AND_ri
2298 CEFBS_None, // AND_ri_32
2299 CEFBS_None, // AND_rr
2300 CEFBS_None, // AND_rr_32
2301 CEFBS_None, // BE16
2302 CEFBS_None, // BE32
2303 CEFBS_None, // BE64
2304 CEFBS_None, // BSWAP16
2305 CEFBS_None, // BSWAP32
2306 CEFBS_None, // BSWAP64
2307 CEFBS_None, // CMPXCHGD
2308 CEFBS_None, // CMPXCHGW32
2309 CEFBS_None, // CORE_LD32
2310 CEFBS_None, // CORE_LD64
2311 CEFBS_None, // CORE_SHIFT
2312 CEFBS_None, // CORE_ST
2313 CEFBS_None, // DIV_ri
2314 CEFBS_None, // DIV_ri_32
2315 CEFBS_None, // DIV_rr
2316 CEFBS_None, // DIV_rr_32
2317 CEFBS_None, // JAL
2318 CEFBS_None, // JALX
2319 CEFBS_None, // JCOND
2320 CEFBS_None, // JEQ_ri
2321 CEFBS_None, // JEQ_ri_32
2322 CEFBS_None, // JEQ_rr
2323 CEFBS_None, // JEQ_rr_32
2324 CEFBS_None, // JMP
2325 CEFBS_None, // JMPL
2326 CEFBS_None, // JNE_ri
2327 CEFBS_None, // JNE_ri_32
2328 CEFBS_None, // JNE_rr
2329 CEFBS_None, // JNE_rr_32
2330 CEFBS_None, // JSET_ri
2331 CEFBS_None, // JSET_ri_32
2332 CEFBS_None, // JSET_rr
2333 CEFBS_None, // JSET_rr_32
2334 CEFBS_None, // JSGE_ri
2335 CEFBS_None, // JSGE_ri_32
2336 CEFBS_None, // JSGE_rr
2337 CEFBS_None, // JSGE_rr_32
2338 CEFBS_None, // JSGT_ri
2339 CEFBS_None, // JSGT_ri_32
2340 CEFBS_None, // JSGT_rr
2341 CEFBS_None, // JSGT_rr_32
2342 CEFBS_None, // JSLE_ri
2343 CEFBS_None, // JSLE_ri_32
2344 CEFBS_None, // JSLE_rr
2345 CEFBS_None, // JSLE_rr_32
2346 CEFBS_None, // JSLT_ri
2347 CEFBS_None, // JSLT_ri_32
2348 CEFBS_None, // JSLT_rr
2349 CEFBS_None, // JSLT_rr_32
2350 CEFBS_None, // JUGE_ri
2351 CEFBS_None, // JUGE_ri_32
2352 CEFBS_None, // JUGE_rr
2353 CEFBS_None, // JUGE_rr_32
2354 CEFBS_None, // JUGT_ri
2355 CEFBS_None, // JUGT_ri_32
2356 CEFBS_None, // JUGT_rr
2357 CEFBS_None, // JUGT_rr_32
2358 CEFBS_None, // JULE_ri
2359 CEFBS_None, // JULE_ri_32
2360 CEFBS_None, // JULE_rr
2361 CEFBS_None, // JULE_rr_32
2362 CEFBS_None, // JULT_ri
2363 CEFBS_None, // JULT_ri_32
2364 CEFBS_None, // JULT_rr
2365 CEFBS_None, // JULT_rr_32
2366 CEFBS_None, // JX
2367 CEFBS_None, // LDB
2368 CEFBS_None, // LDB32
2369 CEFBS_None, // LDBACQ32
2370 CEFBS_None, // LDBSX
2371 CEFBS_None, // LDD
2372 CEFBS_None, // LDDACQ
2373 CEFBS_None, // LDH
2374 CEFBS_None, // LDH32
2375 CEFBS_None, // LDHACQ32
2376 CEFBS_None, // LDHSX
2377 CEFBS_None, // LDW
2378 CEFBS_None, // LDW32
2379 CEFBS_None, // LDWACQ32
2380 CEFBS_None, // LDWSX
2381 CEFBS_None, // LD_ABS_B
2382 CEFBS_None, // LD_ABS_H
2383 CEFBS_None, // LD_ABS_W
2384 CEFBS_None, // LD_IND_B
2385 CEFBS_None, // LD_IND_H
2386 CEFBS_None, // LD_IND_W
2387 CEFBS_None, // LD_imm64
2388 CEFBS_None, // LD_pseudo
2389 CEFBS_None, // LE16
2390 CEFBS_None, // LE32
2391 CEFBS_None, // LE64
2392 CEFBS_None, // MOD_ri
2393 CEFBS_None, // MOD_ri_32
2394 CEFBS_None, // MOD_rr
2395 CEFBS_None, // MOD_rr_32
2396 CEFBS_None, // MOVSX_rr_16
2397 CEFBS_None, // MOVSX_rr_32
2398 CEFBS_None, // MOVSX_rr_32_16
2399 CEFBS_None, // MOVSX_rr_32_8
2400 CEFBS_None, // MOVSX_rr_8
2401 CEFBS_None, // MOV_32_64
2402 CEFBS_None, // MOV_ri
2403 CEFBS_None, // MOV_ri_32
2404 CEFBS_None, // MOV_rr
2405 CEFBS_None, // MOV_rr_32
2406 CEFBS_None, // MUL_ri
2407 CEFBS_None, // MUL_ri_32
2408 CEFBS_None, // MUL_rr
2409 CEFBS_None, // MUL_rr_32
2410 CEFBS_None, // NEG_32
2411 CEFBS_None, // NEG_64
2412 CEFBS_None, // NOP
2413 CEFBS_None, // OR_ri
2414 CEFBS_None, // OR_ri_32
2415 CEFBS_None, // OR_rr
2416 CEFBS_None, // OR_rr_32
2417 CEFBS_None, // RET
2418 CEFBS_None, // SDIV_ri
2419 CEFBS_None, // SDIV_ri_32
2420 CEFBS_None, // SDIV_rr
2421 CEFBS_None, // SDIV_rr_32
2422 CEFBS_None, // SLL_ri
2423 CEFBS_None, // SLL_ri_32
2424 CEFBS_None, // SLL_rr
2425 CEFBS_None, // SLL_rr_32
2426 CEFBS_None, // SMOD_ri
2427 CEFBS_None, // SMOD_ri_32
2428 CEFBS_None, // SMOD_rr
2429 CEFBS_None, // SMOD_rr_32
2430 CEFBS_None, // SRA_ri
2431 CEFBS_None, // SRA_ri_32
2432 CEFBS_None, // SRA_rr
2433 CEFBS_None, // SRA_rr_32
2434 CEFBS_None, // SRL_ri
2435 CEFBS_None, // SRL_ri_32
2436 CEFBS_None, // SRL_rr
2437 CEFBS_None, // SRL_rr_32
2438 CEFBS_None, // STB
2439 CEFBS_None, // STB32
2440 CEFBS_None, // STBREL32
2441 CEFBS_None, // STB_imm
2442 CEFBS_None, // STD
2443 CEFBS_None, // STDREL
2444 CEFBS_None, // STD_imm
2445 CEFBS_None, // STH
2446 CEFBS_None, // STH32
2447 CEFBS_None, // STHREL32
2448 CEFBS_None, // STH_imm
2449 CEFBS_None, // STW
2450 CEFBS_None, // STW32
2451 CEFBS_None, // STWREL32
2452 CEFBS_None, // STW_imm
2453 CEFBS_None, // SUB_ri
2454 CEFBS_None, // SUB_ri_32
2455 CEFBS_None, // SUB_rr
2456 CEFBS_None, // SUB_rr_32
2457 CEFBS_None, // XADDD
2458 CEFBS_None, // XADDW
2459 CEFBS_None, // XADDW32
2460 CEFBS_None, // XANDD
2461 CEFBS_None, // XANDW32
2462 CEFBS_None, // XCHGD
2463 CEFBS_None, // XCHGW32
2464 CEFBS_None, // XFADDD
2465 CEFBS_None, // XFADDW32
2466 CEFBS_None, // XFANDD
2467 CEFBS_None, // XFANDW32
2468 CEFBS_None, // XFORD
2469 CEFBS_None, // XFORW32
2470 CEFBS_None, // XFXORD
2471 CEFBS_None, // XFXORW32
2472 CEFBS_None, // XORD
2473 CEFBS_None, // XORW32
2474 CEFBS_None, // XOR_ri
2475 CEFBS_None, // XOR_ri_32
2476 CEFBS_None, // XOR_rr
2477 CEFBS_None, // XOR_rr_32
2478 CEFBS_None, // XXORD
2479 CEFBS_None, // XXORW32
2480 };
2481
2482 assert(Opcode < 537);
2483 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2484}
2485
2486
2487} // namespace llvm::BPF_MC
2488
2489#endif // GET_COMPUTE_FEATURES
2490
2491#ifdef GET_AVAILABLE_OPCODE_CHECKER
2492#undef GET_AVAILABLE_OPCODE_CHECKER
2493
2494namespace llvm::BPF_MC {
2495
2496bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2497 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2498 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2499 FeatureBitset MissingFeatures =
2500 (AvailableFeatures & RequiredFeatures) ^
2501 RequiredFeatures;
2502 return !MissingFeatures.any();
2503}
2504
2505} // namespace llvm::BPF_MC
2506
2507#endif // GET_AVAILABLE_OPCODE_CHECKER
2508
2509#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2510#undef ENABLE_INSTR_PREDICATE_VERIFIER
2511
2512#include <sstream>
2513
2514namespace llvm::BPF_MC {
2515
2516#ifndef NDEBUG
2517static const char *SubtargetFeatureNames[] = {
2518 nullptr
2519};
2520
2521#endif // NDEBUG
2522
2523void verifyInstructionPredicates(
2524 unsigned Opcode, const FeatureBitset &Features) {
2525#ifndef NDEBUG
2526 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2527 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2528 FeatureBitset MissingFeatures =
2529 (AvailableFeatures & RequiredFeatures) ^
2530 RequiredFeatures;
2531 if (MissingFeatures.any()) {
2532 std::ostringstream Msg;
2533 Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
2534 << " instruction but the ";
2535 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2536 if (MissingFeatures.test(i))
2537 Msg << SubtargetFeatureNames[i] << " ";
2538 Msg << "predicate(s) are not met";
2539 report_fatal_error(Msg.str().c_str());
2540 }
2541#endif // NDEBUG
2542}
2543
2544} // namespace llvm::BPF_MC
2545
2546#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2547
2548