1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::BPF {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1540
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553
96 G_INSERT = 81, // GenericOpcodes.td:1562
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1572
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340
114 G_LOAD = 99, // GenericOpcodes.td:1367
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1376
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1384
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1393
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420
121 G_STORE = 106, // GenericOpcodes.td:1428
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1446
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502
149 G_FENCE = 134, // GenericOpcodes.td:1518
150 G_PREFETCH = 135, // GenericOpcodes.td:1525
151 G_BRCOND = 136, // GenericOpcodes.td:1665
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1674
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697
154 G_INTRINSIC = 139, // GenericOpcodes.td:1617
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:619
183 G_UADDE = 168, // GenericOpcodes.td:627
184 G_USUBO = 169, // GenericOpcodes.td:649
185 G_USUBE = 170, // GenericOpcodes.td:655
186 G_SADDO = 171, // GenericOpcodes.td:634
187 G_SADDE = 172, // GenericOpcodes.td:642
188 G_SSUBO = 173, // GenericOpcodes.td:662
189 G_SSUBE = 174, // GenericOpcodes.td:669
190 G_UMULO = 175, // GenericOpcodes.td:676
191 G_SMULO = 176, // GenericOpcodes.td:684
192 G_UMULH = 177, // GenericOpcodes.td:693
193 G_SMULH = 178, // GenericOpcodes.td:702
194 G_UADDSAT = 179, // GenericOpcodes.td:714
195 G_SADDSAT = 180, // GenericOpcodes.td:722
196 G_USUBSAT = 181, // GenericOpcodes.td:730
197 G_SSUBSAT = 182, // GenericOpcodes.td:738
198 G_USHLSAT = 183, // GenericOpcodes.td:746
199 G_SSHLSAT = 184, // GenericOpcodes.td:754
200 G_SMULFIX = 185, // GenericOpcodes.td:766
201 G_UMULFIX = 186, // GenericOpcodes.td:773
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:783
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:790
204 G_SDIVFIX = 189, // GenericOpcodes.td:801
205 G_UDIVFIX = 190, // GenericOpcodes.td:808
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:818
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:825
208 G_FADD = 193, // GenericOpcodes.td:998
209 G_FSUB = 194, // GenericOpcodes.td:1006
210 G_FMUL = 195, // GenericOpcodes.td:1014
211 G_FMA = 196, // GenericOpcodes.td:1023
212 G_FMAD = 197, // GenericOpcodes.td:1032
213 G_FDIV = 198, // GenericOpcodes.td:1040
214 G_FREM = 199, // GenericOpcodes.td:1047
215 G_FMODF = 200, // GenericOpcodes.td:1054
216 G_FPOW = 201, // GenericOpcodes.td:1061
217 G_FPOWI = 202, // GenericOpcodes.td:1068
218 G_FEXP = 203, // GenericOpcodes.td:1075
219 G_FEXP2 = 204, // GenericOpcodes.td:1082
220 G_FEXP10 = 205, // GenericOpcodes.td:1089
221 G_FLOG = 206, // GenericOpcodes.td:1096
222 G_FLOG2 = 207, // GenericOpcodes.td:1103
223 G_FLOG10 = 208, // GenericOpcodes.td:1110
224 G_FLDEXP = 209, // GenericOpcodes.td:1117
225 G_FFREXP = 210, // GenericOpcodes.td:1124
226 G_FNEG = 211, // GenericOpcodes.td:836
227 G_FPEXT = 212, // GenericOpcodes.td:842
228 G_FPTRUNC = 213, // GenericOpcodes.td:848
229 G_FPTOSI = 214, // GenericOpcodes.td:854
230 G_FPTOUI = 215, // GenericOpcodes.td:860
231 G_SITOFP = 216, // GenericOpcodes.td:866
232 G_UITOFP = 217, // GenericOpcodes.td:872
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:878
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:884
235 G_FABS = 220, // GenericOpcodes.td:890
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:896
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:909
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:902
239 G_FMINNUM = 224, // GenericOpcodes.td:922
240 G_FMAXNUM = 225, // GenericOpcodes.td:929
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954
243 G_FMINIMUM = 228, // GenericOpcodes.td:964
244 G_FMAXIMUM = 229, // GenericOpcodes.td:971
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:979
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986
247 G_GET_FPENV = 232, // GenericOpcodes.td:1254
248 G_SET_FPENV = 233, // GenericOpcodes.td:1261
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1268
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1275
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1282
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1289
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1346
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1352
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1655
265 G_BRJT = 250, // GenericOpcodes.td:1685
266 G_VSCALE = 251, // GenericOpcodes.td:1583
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1780
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_CLMULR = 270, // GenericOpcodes.td:606
286 G_FCEIL = 271, // GenericOpcodes.td:1131
287 G_FCOS = 272, // GenericOpcodes.td:1138
288 G_FSIN = 273, // GenericOpcodes.td:1145
289 G_FSINCOS = 274, // GenericOpcodes.td:1152
290 G_FTAN = 275, // GenericOpcodes.td:1159
291 G_FACOS = 276, // GenericOpcodes.td:1166
292 G_FASIN = 277, // GenericOpcodes.td:1173
293 G_FATAN = 278, // GenericOpcodes.td:1180
294 G_FATAN2 = 279, // GenericOpcodes.td:1187
295 G_FCOSH = 280, // GenericOpcodes.td:1194
296 G_FSINH = 281, // GenericOpcodes.td:1201
297 G_FTANH = 282, // GenericOpcodes.td:1208
298 G_FSQRT = 283, // GenericOpcodes.td:1218
299 G_FFLOOR = 284, // GenericOpcodes.td:1225
300 G_FRINT = 285, // GenericOpcodes.td:1232
301 G_FNEARBYINT = 286, // GenericOpcodes.td:1239
302 G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248
303 G_BLOCK_ADDR = 288, // GenericOpcodes.td:254
304 G_JUMP_TABLE = 289, // GenericOpcodes.td:260
305 G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266
306 G_STACKSAVE = 291, // GenericOpcodes.td:272
307 G_STACKRESTORE = 292, // GenericOpcodes.td:278
308 G_STRICT_FADD = 293, // GenericOpcodes.td:1839
309 G_STRICT_FSUB = 294, // GenericOpcodes.td:1840
310 G_STRICT_FMUL = 295, // GenericOpcodes.td:1841
311 G_STRICT_FDIV = 296, // GenericOpcodes.td:1842
312 G_STRICT_FREM = 297, // GenericOpcodes.td:1843
313 G_STRICT_FMA = 298, // GenericOpcodes.td:1844
314 G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845
315 G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846
316 G_STRICT_FCMP = 301, // GenericOpcodes.td:1847
317 G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848
318 G_READ_REGISTER = 303, // GenericOpcodes.td:1704
319 G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714
320 G_MEMCPY = 305, // GenericOpcodes.td:1854
321 G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862
322 G_MEMMOVE = 307, // GenericOpcodes.td:1870
323 G_MEMSET = 308, // GenericOpcodes.td:1878
324 G_BZERO = 309, // GenericOpcodes.td:1885
325 G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892
326 G_TRAP = 311, // GenericOpcodes.td:1902
327 G_DEBUGTRAP = 312, // GenericOpcodes.td:1909
328 G_UBSANTRAP = 313, // GenericOpcodes.td:1915
329 G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803
330 G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809
331 G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815
332 G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816
333 G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818
334 G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819
335 G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820
336 G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821
337 G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822
338 G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823
339 G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825
340 G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826
341 G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827
342 G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828
343 G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829
344 G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830
345 G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831
346 G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832
347 G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833
348 G_SBFX = 333, // GenericOpcodes.td:1927
349 G_UBFX = 334, // GenericOpcodes.td:1935
350 ADJCALLSTACKDOWN = 335, // BPFInstrInfo.td:849
351 ADJCALLSTACKUP = 336, // BPFInstrInfo.td:852
352 FI_ri = 337, // BPFInstrInfo.td:515
353 LDIMM64 = 338, // BPFInstrInfo.td:1425
354 LOAD_STACK_ARG_PSEUDO = 339, // BPFInstrInfo.td:320
355 MEMCPY = 340, // BPFInstrInfo.td:1416
356 STORE_STACK_ARG_IMM_PSEUDO = 341, // BPFInstrInfo.td:330
357 STORE_STACK_ARG_PSEUDO = 342, // BPFInstrInfo.td:326
358 Select = 343, // BPFInstrInfo.td:858
359 Select_32 = 344, // BPFInstrInfo.td:878
360 Select_32_64 = 345, // BPFInstrInfo.td:888
361 Select_64_32 = 346, // BPFInstrInfo.td:868
362 Select_Ri = 347, // BPFInstrInfo.td:863
363 Select_Ri_32 = 348, // BPFInstrInfo.td:883
364 Select_Ri_32_64 = 349, // BPFInstrInfo.td:893
365 Select_Ri_64_32 = 350, // BPFInstrInfo.td:873
366 ADDR_SPACE_CAST = 351, // BPFInstrInfo.td:486
367 ADD_ri = 352, // BPFInstrInfo.td:366
368 ADD_ri_32 = 353, // BPFInstrInfo.td:376
369 ADD_rr = 354, // BPFInstrInfo.td:361
370 ADD_rr_32 = 355, // BPFInstrInfo.td:371
371 AND_ri = 356, // BPFInstrInfo.td:366
372 AND_ri_32 = 357, // BPFInstrInfo.td:376
373 AND_rr = 358, // BPFInstrInfo.td:361
374 AND_rr_32 = 359, // BPFInstrInfo.td:371
375 BE16 = 360, // BPFInstrInfo.td:1225
376 BE32 = 361, // BPFInstrInfo.td:1226
377 BE64 = 362, // BPFInstrInfo.td:1227
378 BSWAP16 = 363, // BPFInstrInfo.td:1218
379 BSWAP32 = 364, // BPFInstrInfo.td:1219
380 BSWAP64 = 365, // BPFInstrInfo.td:1220
381 CMPXCHGD = 366, // BPFInstrInfo.td:1198
382 CMPXCHGW32 = 367, // BPFInstrInfo.td:1194
383 CORE_LD32 = 368, // BPFInstrInfo.td:687
384 CORE_LD64 = 369, // BPFInstrInfo.td:686
385 CORE_SHIFT = 370, // BPFInstrInfo.td:694
386 CORE_ST = 371, // BPFInstrInfo.td:688
387 DIV_ri = 372, // BPFInstrInfo.td:366
388 DIV_ri_32 = 373, // BPFInstrInfo.td:376
389 DIV_rr = 374, // BPFInstrInfo.td:361
390 DIV_rr_32 = 375, // BPFInstrInfo.td:371
391 JAL = 376, // BPFInstrInfo.td:813
392 JALX = 377, // BPFInstrInfo.td:814
393 JCOND = 378, // BPFInstrInfo.td:310
394 JEQ_ri = 379, // BPFInstrInfo.td:292
395 JEQ_ri_32 = 380, // BPFInstrInfo.td:294
396 JEQ_rr = 381, // BPFInstrInfo.td:291
397 JEQ_rr_32 = 382, // BPFInstrInfo.td:293
398 JMP = 383, // BPFInstrInfo.td:807
399 JMPL = 384, // BPFInstrInfo.td:808
400 JNE_ri = 385, // BPFInstrInfo.td:292
401 JNE_ri_32 = 386, // BPFInstrInfo.td:294
402 JNE_rr = 387, // BPFInstrInfo.td:291
403 JNE_rr_32 = 388, // BPFInstrInfo.td:293
404 JSET_ri = 389, // BPFInstrInfo.td:292
405 JSET_ri_32 = 390, // BPFInstrInfo.td:294
406 JSET_rr = 391, // BPFInstrInfo.td:291
407 JSET_rr_32 = 392, // BPFInstrInfo.td:293
408 JSGE_ri = 393, // BPFInstrInfo.td:292
409 JSGE_ri_32 = 394, // BPFInstrInfo.td:294
410 JSGE_rr = 395, // BPFInstrInfo.td:291
411 JSGE_rr_32 = 396, // BPFInstrInfo.td:293
412 JSGT_ri = 397, // BPFInstrInfo.td:292
413 JSGT_ri_32 = 398, // BPFInstrInfo.td:294
414 JSGT_rr = 399, // BPFInstrInfo.td:291
415 JSGT_rr_32 = 400, // BPFInstrInfo.td:293
416 JSLE_ri = 401, // BPFInstrInfo.td:292
417 JSLE_ri_32 = 402, // BPFInstrInfo.td:294
418 JSLE_rr = 403, // BPFInstrInfo.td:291
419 JSLE_rr_32 = 404, // BPFInstrInfo.td:293
420 JSLT_ri = 405, // BPFInstrInfo.td:292
421 JSLT_ri_32 = 406, // BPFInstrInfo.td:294
422 JSLT_rr = 407, // BPFInstrInfo.td:291
423 JSLT_rr_32 = 408, // BPFInstrInfo.td:293
424 JUGE_ri = 409, // BPFInstrInfo.td:292
425 JUGE_ri_32 = 410, // BPFInstrInfo.td:294
426 JUGE_rr = 411, // BPFInstrInfo.td:291
427 JUGE_rr_32 = 412, // BPFInstrInfo.td:293
428 JUGT_ri = 413, // BPFInstrInfo.td:292
429 JUGT_ri_32 = 414, // BPFInstrInfo.td:294
430 JUGT_rr = 415, // BPFInstrInfo.td:291
431 JUGT_rr_32 = 416, // BPFInstrInfo.td:293
432 JULE_ri = 417, // BPFInstrInfo.td:292
433 JULE_ri_32 = 418, // BPFInstrInfo.td:294
434 JULE_rr = 419, // BPFInstrInfo.td:291
435 JULE_rr_32 = 420, // BPFInstrInfo.td:293
436 JULT_ri = 421, // BPFInstrInfo.td:292
437 JULT_ri_32 = 422, // BPFInstrInfo.td:294
438 JULT_rr = 423, // BPFInstrInfo.td:291
439 JULT_rr_32 = 424, // BPFInstrInfo.td:293
440 JX = 425, // BPFInstrInfo.td:314
441 LDB = 426, // BPFInstrInfo.td:705
442 LDB32 = 427, // BPFInstrInfo.td:1353
443 LDBACQ32 = 428, // BPFInstrInfo.td:1358
444 LDBSX = 429, // BPFInstrInfo.td:711
445 LDD = 430, // BPFInstrInfo.td:714
446 LDDACQ = 431, // BPFInstrInfo.td:748
447 LDH = 432, // BPFInstrInfo.td:704
448 LDH32 = 433, // BPFInstrInfo.td:1352
449 LDHACQ32 = 434, // BPFInstrInfo.td:1357
450 LDHSX = 435, // BPFInstrInfo.td:710
451 LDW = 436, // BPFInstrInfo.td:703
452 LDW32 = 437, // BPFInstrInfo.td:1351
453 LDWACQ32 = 438, // BPFInstrInfo.td:1356
454 LDWSX = 439, // BPFInstrInfo.td:709
455 LD_ABS_B = 440, // BPFInstrInfo.td:1262
456 LD_ABS_H = 441, // BPFInstrInfo.td:1263
457 LD_ABS_W = 442, // BPFInstrInfo.td:1264
458 LD_IND_B = 443, // BPFInstrInfo.td:1266
459 LD_IND_H = 444, // BPFInstrInfo.td:1267
460 LD_IND_W = 445, // BPFInstrInfo.td:1268
461 LD_imm64 = 446, // BPFInstrInfo.td:440
462 LD_pseudo = 447, // BPFInstrInfo.td:531
463 LE16 = 448, // BPFInstrInfo.td:1230
464 LE32 = 449, // BPFInstrInfo.td:1231
465 LE64 = 450, // BPFInstrInfo.td:1232
466 MOD_ri = 451, // BPFInstrInfo.td:366
467 MOD_ri_32 = 452, // BPFInstrInfo.td:376
468 MOD_rr = 453, // BPFInstrInfo.td:361
469 MOD_rr_32 = 454, // BPFInstrInfo.td:371
470 MOVSX_rr_16 = 455, // BPFInstrInfo.td:467
471 MOVSX_rr_32 = 456, // BPFInstrInfo.td:471
472 MOVSX_rr_32_16 = 457, // BPFInstrInfo.td:479
473 MOVSX_rr_32_8 = 458, // BPFInstrInfo.td:475
474 MOVSX_rr_8 = 459, // BPFInstrInfo.td:463
475 MOV_32_64 = 460, // BPFInstrInfo.td:1271
476 MOV_ri = 461, // BPFInstrInfo.td:446
477 MOV_ri_32 = 462, // BPFInstrInfo.td:456
478 MOV_rr = 463, // BPFInstrInfo.td:441
479 MOV_rr_32 = 464, // BPFInstrInfo.td:451
480 MUL_ri = 465, // BPFInstrInfo.td:366
481 MUL_ri_32 = 466, // BPFInstrInfo.td:376
482 MUL_rr = 467, // BPFInstrInfo.td:361
483 MUL_rr_32 = 468, // BPFInstrInfo.td:371
484 NEG_32 = 469, // BPFInstrInfo.td:417
485 NEG_64 = 470, // BPFInstrInfo.td:414
486 NOP = 471, // BPFInstrInfo.td:830
487 OR_ri = 472, // BPFInstrInfo.td:366
488 OR_ri_32 = 473, // BPFInstrInfo.td:376
489 OR_rr = 474, // BPFInstrInfo.td:361
490 OR_rr_32 = 475, // BPFInstrInfo.td:371
491 RET = 476, // BPFInstrInfo.td:844
492 SDIV_ri = 477, // BPFInstrInfo.td:366
493 SDIV_ri_32 = 478, // BPFInstrInfo.td:376
494 SDIV_rr = 479, // BPFInstrInfo.td:361
495 SDIV_rr_32 = 480, // BPFInstrInfo.td:371
496 SLL_ri = 481, // BPFInstrInfo.td:366
497 SLL_ri_32 = 482, // BPFInstrInfo.td:376
498 SLL_rr = 483, // BPFInstrInfo.td:361
499 SLL_rr_32 = 484, // BPFInstrInfo.td:371
500 SMOD_ri = 485, // BPFInstrInfo.td:366
501 SMOD_ri_32 = 486, // BPFInstrInfo.td:376
502 SMOD_rr = 487, // BPFInstrInfo.td:361
503 SMOD_rr_32 = 488, // BPFInstrInfo.td:371
504 SRA_ri = 489, // BPFInstrInfo.td:366
505 SRA_ri_32 = 490, // BPFInstrInfo.td:376
506 SRA_rr = 491, // BPFInstrInfo.td:361
507 SRA_rr_32 = 492, // BPFInstrInfo.td:371
508 SRL_ri = 493, // BPFInstrInfo.td:366
509 SRL_ri_32 = 494, // BPFInstrInfo.td:376
510 SRL_rr = 495, // BPFInstrInfo.td:361
511 SRL_rr_32 = 496, // BPFInstrInfo.td:371
512 STB = 497, // BPFInstrInfo.td:571
513 STB32 = 498, // BPFInstrInfo.td:1320
514 STBREL32 = 499, // BPFInstrInfo.td:1325
515 STB_imm = 500, // BPFInstrInfo.td:607
516 STD = 501, // BPFInstrInfo.td:573
517 STDREL = 502, // BPFInstrInfo.td:651
518 STD_imm = 503, // BPFInstrInfo.td:604
519 STH = 504, // BPFInstrInfo.td:570
520 STH32 = 505, // BPFInstrInfo.td:1319
521 STHREL32 = 506, // BPFInstrInfo.td:1324
522 STH_imm = 507, // BPFInstrInfo.td:606
523 STW = 508, // BPFInstrInfo.td:569
524 STW32 = 509, // BPFInstrInfo.td:1318
525 STWREL32 = 510, // BPFInstrInfo.td:1323
526 STW_imm = 511, // BPFInstrInfo.td:605
527 SUB_ri = 512, // BPFInstrInfo.td:366
528 SUB_ri_32 = 513, // BPFInstrInfo.td:376
529 SUB_rr = 514, // BPFInstrInfo.td:361
530 SUB_rr_32 = 515, // BPFInstrInfo.td:371
531 XADDD = 516, // BPFInstrInfo.td:947
532 XADDW = 517, // BPFInstrInfo.td:946
533 XADDW32 = 518, // BPFInstrInfo.td:941
534 XANDD = 519, // BPFInstrInfo.td:948
535 XANDW32 = 520, // BPFInstrInfo.td:942
536 XCHGD = 521, // BPFInstrInfo.td:1154
537 XCHGW32 = 522, // BPFInstrInfo.td:1151
538 XFADDD = 523, // BPFInstrInfo.td:1004
539 XFADDW32 = 524, // BPFInstrInfo.td:997
540 XFANDD = 525, // BPFInstrInfo.td:1006
541 XFANDW32 = 526, // BPFInstrInfo.td:998
542 XFORD = 527, // BPFInstrInfo.td:1007
543 XFORW32 = 528, // BPFInstrInfo.td:999
544 XFXORD = 529, // BPFInstrInfo.td:1008
545 XFXORW32 = 530, // BPFInstrInfo.td:1000
546 XORD = 531, // BPFInstrInfo.td:949
547 XORW32 = 532, // BPFInstrInfo.td:943
548 XOR_ri = 533, // BPFInstrInfo.td:366
549 XOR_ri_32 = 534, // BPFInstrInfo.td:376
550 XOR_rr = 535, // BPFInstrInfo.td:361
551 XOR_rr_32 = 536, // BPFInstrInfo.td:371
552 XXORD = 537, // BPFInstrInfo.td:950
553 XXORW32 = 538, // BPFInstrInfo.td:944
554 INSTRUCTION_LIST_END = 539
555 };
556
557} // namespace llvm::BPF
558
559#endif // GET_INSTRINFO_ENUM
560
561#ifdef GET_INSTRINFO_SCHED_ENUM
562#undef GET_INSTRINFO_SCHED_ENUM
563
564namespace llvm::BPF::Sched {
565
566 enum {
567 NoInstrModel = 0,
568 SCHED_LIST_END = 1
569 };
570
571} // namespace llvm::BPF::Sched
572
573#endif // GET_INSTRINFO_SCHED_ENUM
574
575#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
576
577namespace llvm {
578
579struct BPFInstrTable {
580 MCInstrDesc Insts[539];
581 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
582 MCPhysReg ImplicitOps[14];
583 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
584 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
585 MCOperandInfo OperandInfo[282];
586};
587} // namespace llvm
588
589#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
590
591#ifdef GET_INSTRINFO_MC_DESC
592#undef GET_INSTRINFO_MC_DESC
593
594namespace llvm {
595
596static_assert((sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
597static constexpr unsigned BPFOpInfoBase = (sizeof BPFInstrTable::ImplicitOps + sizeof BPFInstrTable::Padding) / sizeof(MCOperandInfo);
598
599extern const BPFInstrTable BPFDescs = {
600 {
601 { 538, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORW32
602 { 537, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XXORD
603 { 536, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr_32
604 { 535, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_rr
605 { 534, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri_32
606 { 533, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XOR_ri
607 { 532, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORW32
608 { 531, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XORD
609 { 530, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORW32
610 { 529, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFXORD
611 { 528, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORW32
612 { 527, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFORD
613 { 526, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDW32
614 { 525, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFANDD
615 { 524, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDW32
616 { 523, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XFADDD
617 { 522, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGW32
618 { 521, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XCHGD
619 { 520, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDW32
620 { 519, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XANDD
621 { 518, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 278, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW32
622 { 517, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDW
623 { 516, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 274, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // XADDD
624 { 515, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr_32
625 { 514, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_rr
626 { 513, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri_32
627 { 512, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUB_ri
628 { 511, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW_imm
629 { 510, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STWREL32
630 { 509, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW32
631 { 508, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STW
632 { 507, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH_imm
633 { 506, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STHREL32
634 { 505, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH32
635 { 504, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STH
636 { 503, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD_imm
637 { 502, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STDREL
638 { 501, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STD
639 { 500, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 271, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB_imm
640 { 499, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STBREL32
641 { 498, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB32
642 { 497, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STB
643 { 496, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr_32
644 { 495, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_rr
645 { 494, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri_32
646 { 493, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRL_ri
647 { 492, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr_32
648 { 491, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_rr
649 { 490, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri_32
650 { 489, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SRA_ri
651 { 488, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr_32
652 { 487, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_rr
653 { 486, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri_32
654 { 485, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SMOD_ri
655 { 484, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr_32
656 { 483, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_rr
657 { 482, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri_32
658 { 481, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SLL_ri
659 { 480, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr_32
660 { 479, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_rr
661 { 478, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri_32
662 { 477, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SDIV_ri
663 { 476, 0, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RET
664 { 475, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr_32
665 { 474, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_rr
666 { 473, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri_32
667 { 472, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // OR_ri
668 { 471, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NOP
669 { 470, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_64
670 { 469, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 269, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // NEG_32
671 { 468, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr_32
672 { 467, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_rr
673 { 466, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri_32
674 { 465, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MUL_ri
675 { 464, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr_32
676 { 463, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_rr
677 { 462, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 267, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri_32
678 { 461, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_ri
679 { 460, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 265, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOV_32_64
680 { 459, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_8
681 { 458, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_8
682 { 457, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 263, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32_16
683 { 456, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_32
684 { 455, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 261, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOVSX_rr_16
685 { 454, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr_32
686 { 453, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_rr
687 { 452, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri_32
688 { 451, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MOD_ri
689 { 450, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE64
690 { 449, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE32
691 { 448, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LE16
692 { 447, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_pseudo
693 { 446, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_imm64
694 { 445, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_W
695 { 444, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_H
696 { 443, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 28, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_IND_B
697 { 442, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_W
698 { 441, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_H
699 { 440, 1, 0, 8, 0, 1, 6, BPFOpInfoBase + 1, 7, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LD_ABS_B
700 { 439, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWSX
701 { 438, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDWACQ32
702 { 437, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW32
703 { 436, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDW
704 { 435, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHSX
705 { 434, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDHACQ32
706 { 433, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH32
707 { 432, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDH
708 { 431, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDDACQ
709 { 430, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDD
710 { 429, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBSX
711 { 428, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDBACQ32
712 { 427, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 258, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB32
713 { 426, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDB
714 { 425, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JX
715 { 424, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr_32
716 { 423, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_rr
717 { 422, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri_32
718 { 421, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULT_ri
719 { 420, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr_32
720 { 419, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_rr
721 { 418, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri_32
722 { 417, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JULE_ri
723 { 416, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr_32
724 { 415, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_rr
725 { 414, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri_32
726 { 413, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGT_ri
727 { 412, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr_32
728 { 411, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_rr
729 { 410, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri_32
730 { 409, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUGE_ri
731 { 408, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr_32
732 { 407, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_rr
733 { 406, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri_32
734 { 405, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLT_ri
735 { 404, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr_32
736 { 403, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_rr
737 { 402, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri_32
738 { 401, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSLE_ri
739 { 400, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr_32
740 { 399, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_rr
741 { 398, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri_32
742 { 397, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGT_ri
743 { 396, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr_32
744 { 395, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_rr
745 { 394, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri_32
746 { 393, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSGE_ri
747 { 392, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr_32
748 { 391, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_rr
749 { 390, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri_32
750 { 389, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JSET_ri
751 { 388, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr_32
752 { 387, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_rr
753 { 386, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri_32
754 { 385, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JNE_ri
755 { 384, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMPL
756 { 383, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JMP
757 { 382, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 255, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr_32
758 { 381, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 252, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_rr
759 { 380, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 249, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri_32
760 { 379, 3, 0, 8, 0, 0, 0, BPFOpInfoBase + 246, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JEQ_ri
761 { 378, 1, 0, 8, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JCOND
762 { 377, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 28, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JALX
763 { 376, 1, 0, 8, 0, 1, 0, BPFOpInfoBase + 0, 6, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JAL
764 { 375, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr_32
765 { 374, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_rr
766 { 373, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri_32
767 { 372, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DIV_ri
768 { 371, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 242, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_ST
769 { 370, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 238, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_SHIFT
770 { 369, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 234, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD64
771 { 368, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 230, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CORE_LD32
772 { 367, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 227, 4, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGW32
773 { 366, 3, 0, 8, 0, 1, 1, BPFOpInfoBase + 224, 2, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CMPXCHGD
774 { 365, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP64
775 { 364, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP32
776 { 363, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BSWAP16
777 { 362, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE64
778 { 361, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE32
779 { 360, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 222, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BE16
780 { 359, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr_32
781 { 358, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_rr
782 { 357, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri_32
783 { 356, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // AND_ri
784 { 355, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 219, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr_32
785 { 354, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 216, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_rr
786 { 353, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 213, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri_32
787 { 352, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 210, 0, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADD_ri
788 { 351, 4, 1, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADDR_SPACE_CAST
789 { 350, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 204, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_64_32
790 { 349, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 198, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32_64
791 { 348, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 192, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri_32
792 { 347, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 186, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_Ri
793 { 346, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 180, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_64_32
794 { 345, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 174, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32_64
795 { 344, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 168, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select_32
796 { 343, 6, 1, 8, 0, 0, 0, BPFOpInfoBase + 162, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Select
797 { 342, 2, 0, 8, 0, 0, 0, BPFOpInfoBase + 160, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_STACK_ARG_PSEUDO
798 { 341, 2, 0, 8, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STORE_STACK_ARG_IMM_PSEUDO
799 { 340, 4, 0, 8, 0, 0, 0, BPFOpInfoBase + 156, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMCPY
800 { 339, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOAD_STACK_ARG_PSEUDO
801 { 338, 2, 1, 8, 0, 0, 0, BPFOpInfoBase + 154, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LDIMM64
802 { 337, 3, 1, 8, 0, 0, 0, BPFOpInfoBase + 151, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FI_ri
803 { 336, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKUP
804 { 335, 2, 0, 8, 0, 1, 1, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ADJCALLSTACKDOWN
805 { 334, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
806 { 333, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
807 { 332, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
808 { 331, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
809 { 330, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
810 { 329, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
811 { 328, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
812 { 327, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
813 { 326, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
814 { 325, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
815 { 324, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
816 { 323, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
817 { 322, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
818 { 321, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
819 { 320, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
820 { 319, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
821 { 318, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
822 { 317, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
823 { 316, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
824 { 315, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
825 { 314, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
826 { 313, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
827 { 312, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
828 { 311, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
829 { 310, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
830 { 309, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
831 { 308, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
832 { 307, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
833 { 306, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
834 { 305, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
835 { 304, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
836 { 303, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
837 { 302, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
838 { 301, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
839 { 300, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
840 { 299, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
841 { 298, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
842 { 297, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
843 { 296, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
844 { 295, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
845 { 294, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
846 { 293, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
847 { 292, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
848 { 291, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
849 { 290, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
850 { 289, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
851 { 288, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
852 { 287, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
853 { 286, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
854 { 285, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
855 { 284, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
856 { 283, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
857 { 282, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
858 { 281, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
859 { 280, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
860 { 279, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
861 { 278, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
862 { 277, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
863 { 276, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
864 { 275, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
865 { 274, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
866 { 273, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
867 { 272, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
868 { 271, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
869 { 270, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULR
870 { 269, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
871 { 268, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
872 { 267, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
873 { 266, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
874 { 265, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
875 { 264, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
876 { 263, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
877 { 262, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
878 { 261, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
879 { 260, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
880 { 259, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
881 { 258, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
882 { 257, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
883 { 256, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
884 { 255, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
885 { 254, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
886 { 253, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
887 { 252, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
888 { 251, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
889 { 250, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
890 { 249, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
891 { 248, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
892 { 247, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
893 { 246, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
894 { 245, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
895 { 244, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
896 { 243, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
897 { 242, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
898 { 241, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
899 { 240, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
900 { 239, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
901 { 238, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
902 { 237, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
903 { 236, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
904 { 235, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
905 { 234, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
906 { 233, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
907 { 232, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
908 { 231, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
909 { 230, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
910 { 229, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
911 { 228, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
912 { 227, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
913 { 226, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
914 { 225, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
915 { 224, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
916 { 223, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
917 { 222, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
918 { 221, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
919 { 220, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
920 { 219, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
921 { 218, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
922 { 217, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
923 { 216, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
924 { 215, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
925 { 214, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
926 { 213, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
927 { 212, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
928 { 211, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
929 { 210, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
930 { 209, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
931 { 208, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
932 { 207, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
933 { 206, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
934 { 205, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
935 { 204, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
936 { 203, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
937 { 202, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
938 { 201, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
939 { 200, 3, 2, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
940 { 199, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
941 { 198, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
942 { 197, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
943 { 196, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
944 { 195, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
945 { 194, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
946 { 193, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
947 { 192, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
948 { 191, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
949 { 190, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
950 { 189, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
951 { 188, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
952 { 187, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
953 { 186, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
954 { 185, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
955 { 184, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
956 { 183, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
957 { 182, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
958 { 181, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
959 { 180, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
960 { 179, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
961 { 178, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
962 { 177, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
963 { 176, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
964 { 175, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
965 { 174, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
966 { 173, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
967 { 172, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
968 { 171, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
969 { 170, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
970 { 169, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
971 { 168, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
972 { 167, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
973 { 166, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
974 { 165, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
975 { 164, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
976 { 163, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
977 { 162, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
978 { 161, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
979 { 160, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
980 { 159, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
981 { 158, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
982 { 157, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
983 { 156, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
984 { 155, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
985 { 154, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
986 { 153, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
987 { 152, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
988 { 151, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
989 { 150, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
990 { 149, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
991 { 148, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
992 { 147, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
993 { 146, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
994 { 145, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
995 { 144, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
996 { 143, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
997 { 142, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
998 { 141, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
999 { 140, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
1000 { 139, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
1001 { 138, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
1002 { 137, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
1003 { 136, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
1004 { 135, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
1005 { 134, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
1006 { 133, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
1007 { 132, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
1008 { 131, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
1009 { 130, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
1010 { 129, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
1011 { 128, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
1012 { 127, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
1013 { 126, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
1014 { 125, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
1015 { 124, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
1016 { 123, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
1017 { 122, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
1018 { 121, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
1019 { 120, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
1020 { 119, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
1021 { 118, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
1022 { 117, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
1023 { 116, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
1024 { 115, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
1025 { 114, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
1026 { 113, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
1027 { 112, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
1028 { 111, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
1029 { 110, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
1030 { 109, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1031 { 108, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
1032 { 107, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
1033 { 106, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
1034 { 105, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
1035 { 104, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
1036 { 103, 5, 2, 0, 0, 0, 0, BPFOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
1037 { 102, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
1038 { 101, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
1039 { 100, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
1040 { 99, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
1041 { 98, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
1042 { 97, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
1043 { 96, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
1044 { 95, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
1045 { 94, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
1046 { 93, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
1047 { 92, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
1048 { 91, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
1049 { 90, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
1050 { 89, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
1051 { 88, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
1052 { 87, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
1053 { 86, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
1054 { 85, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
1055 { 84, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
1056 { 83, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
1057 { 82, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
1058 { 81, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
1059 { 80, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
1060 { 79, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
1061 { 78, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
1062 { 77, 5, 1, 0, 0, 0, 0, BPFOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
1063 { 76, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
1064 { 75, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
1065 { 74, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
1066 { 73, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
1067 { 72, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
1068 { 71, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
1069 { 70, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
1070 { 69, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
1071 { 68, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
1072 { 67, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
1073 { 66, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
1074 { 65, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
1075 { 64, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
1076 { 63, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
1077 { 62, 4, 2, 0, 0, 0, 0, BPFOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
1078 { 61, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
1079 { 60, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
1080 { 59, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
1081 { 58, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
1082 { 57, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
1083 { 56, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
1084 { 55, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
1085 { 54, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
1086 { 53, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
1087 { 52, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
1088 { 51, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
1089 { 50, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
1090 { 49, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
1091 { 48, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
1092 { 47, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
1093 { 46, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
1094 { 45, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
1095 { 44, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
1096 { 43, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
1097 { 42, 3, 0, 0, 0, 0, 0, BPFOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14843
1098 { 41, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14842
1099 { 40, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
1100 { 39, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
1101 { 38, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
1102 { 37, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
1103 { 36, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
1104 { 35, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
1105 { 34, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
1106 { 33, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
1107 { 32, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14841
1108 { 31, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
1109 { 30, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14418
1110 { 29, 6, 1, 0, 0, 0, 0, BPFOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
1111 { 28, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
1112 { 27, 2, 0, 0, 0, 0, 0, BPFOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
1113 { 26, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
1114 { 25, 4, 0, 0, 0, 0, 0, BPFOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
1115 { 24, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
1116 { 23, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
1117 { 22, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
1118 { 21, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
1119 { 20, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
1120 { 19, 2, 1, 0, 0, 0, 0, BPFOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
1121 { 18, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
1122 { 17, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
1123 { 16, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
1124 { 15, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
1125 { 14, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
1126 { 13, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
1127 { 12, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
1128 { 11, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
1129 { 10, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
1130 { 9, 4, 1, 0, 0, 0, 0, BPFOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
1131 { 8, 3, 1, 0, 0, 0, 0, BPFOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
1132 { 7, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
1133 { 6, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
1134 { 5, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
1135 { 4, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
1136 { 3, 1, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
1137 { 2, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
1138 { 1, 0, 0, 0, 0, 0, 0, BPFOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
1139 { 0, 1, 1, 0, 0, 0, 0, BPFOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
1140 }, {
1141 /* 0 */
1142 /* 0 */ BPF::R11, BPF::R11,
1143 /* 2 */ BPF::R0, BPF::R0,
1144 /* 4 */ BPF::W0, BPF::W0,
1145 /* 6 */ BPF::R11,
1146 /* 7 */ BPF::R6, BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5,
1147 }, {
1148 0
1149 }, {
1150 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1151 /* 1 */
1152 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1153 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1154 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1155 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1156 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1157 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1158 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1159 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1160 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1161 /* 28 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1162 /* 29 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1163 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1164 /* 34 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1165 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1166 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1167 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1168 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1169 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1170 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1171 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1172 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1173 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1174 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1175 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1176 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1177 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1178 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1179 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1180 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1181 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1182 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
1183 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1184 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1185 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1186 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1187 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1188 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1189 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1190 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1191 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1192 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1193 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1194 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1195 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1196 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1197 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1198 /* 151 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1199 /* 154 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1200 /* 156 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1201 /* 160 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1202 /* 162 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1203 /* 168 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1204 /* 174 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1205 /* 180 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1206 /* 186 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1207 /* 192 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1208 /* 198 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1209 /* 204 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1210 /* 210 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1211 /* 213 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1212 /* 216 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1213 /* 219 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1214 /* 222 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1215 /* 224 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1216 /* 227 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1217 /* 230 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1218 /* 234 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1219 /* 238 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1220 /* 242 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1221 /* 246 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1222 /* 249 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1223 /* 252 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1224 /* 255 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1225 /* 258 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1226 /* 261 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1227 /* 263 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1228 /* 265 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1229 /* 267 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1230 /* 269 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1231 /* 271 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1232 /* 274 */ { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1233 /* 278 */ { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { BPF::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { BPF::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1234 }
1235};
1236
1237
1238#ifdef __GNUC__
1239#pragma GCC diagnostic push
1240#pragma GCC diagnostic ignored "-Woverlength-strings"
1241#endif
1242extern const char BPFInstrNameData[] = {
1243 /* 0 */ "G_FLOG10\000"
1244 /* 9 */ "G_FEXP10\000"
1245 /* 18 */ "LDB32\000"
1246 /* 24 */ "STB32\000"
1247 /* 30 */ "CORE_LD32\000"
1248 /* 40 */ "BE32\000"
1249 /* 45 */ "LE32\000"
1250 /* 50 */ "LDH32\000"
1251 /* 56 */ "STH32\000"
1252 /* 62 */ "STBREL32\000"
1253 /* 71 */ "STHREL32\000"
1254 /* 80 */ "STWREL32\000"
1255 /* 89 */ "BSWAP32\000"
1256 /* 97 */ "LDBACQ32\000"
1257 /* 106 */ "LDHACQ32\000"
1258 /* 115 */ "LDWACQ32\000"
1259 /* 124 */ "XFADDW32\000"
1260 /* 133 */ "XADDW32\000"
1261 /* 141 */ "LDW32\000"
1262 /* 147 */ "XFANDW32\000"
1263 /* 156 */ "XANDW32\000"
1264 /* 164 */ "CMPXCHGW32\000"
1265 /* 175 */ "XFORW32\000"
1266 /* 183 */ "XFXORW32\000"
1267 /* 192 */ "XXORW32\000"
1268 /* 200 */ "STW32\000"
1269 /* 206 */ "Select_Ri_64_32\000"
1270 /* 222 */ "Select_64_32\000"
1271 /* 235 */ "NEG_32\000"
1272 /* 242 */ "Select_Ri_32\000"
1273 /* 255 */ "SRA_ri_32\000"
1274 /* 265 */ "SUB_ri_32\000"
1275 /* 275 */ "ADD_ri_32\000"
1276 /* 285 */ "AND_ri_32\000"
1277 /* 295 */ "SMOD_ri_32\000"
1278 /* 306 */ "JSGE_ri_32\000"
1279 /* 317 */ "JUGE_ri_32\000"
1280 /* 328 */ "JSLE_ri_32\000"
1281 /* 339 */ "JULE_ri_32\000"
1282 /* 350 */ "JNE_ri_32\000"
1283 /* 360 */ "SLL_ri_32\000"
1284 /* 370 */ "SRL_ri_32\000"
1285 /* 380 */ "MUL_ri_32\000"
1286 /* 390 */ "JEQ_ri_32\000"
1287 /* 400 */ "XOR_ri_32\000"
1288 /* 410 */ "JSET_ri_32\000"
1289 /* 421 */ "JSGT_ri_32\000"
1290 /* 432 */ "JUGT_ri_32\000"
1291 /* 443 */ "JSLT_ri_32\000"
1292 /* 454 */ "JULT_ri_32\000"
1293 /* 465 */ "SDIV_ri_32\000"
1294 /* 476 */ "MOV_ri_32\000"
1295 /* 486 */ "SRA_rr_32\000"
1296 /* 496 */ "SUB_rr_32\000"
1297 /* 506 */ "ADD_rr_32\000"
1298 /* 516 */ "AND_rr_32\000"
1299 /* 526 */ "SMOD_rr_32\000"
1300 /* 537 */ "JSGE_rr_32\000"
1301 /* 548 */ "JUGE_rr_32\000"
1302 /* 559 */ "JSLE_rr_32\000"
1303 /* 570 */ "JULE_rr_32\000"
1304 /* 581 */ "JNE_rr_32\000"
1305 /* 591 */ "SLL_rr_32\000"
1306 /* 601 */ "SRL_rr_32\000"
1307 /* 611 */ "MUL_rr_32\000"
1308 /* 621 */ "JEQ_rr_32\000"
1309 /* 631 */ "XOR_rr_32\000"
1310 /* 641 */ "JSET_rr_32\000"
1311 /* 652 */ "JSGT_rr_32\000"
1312 /* 663 */ "JUGT_rr_32\000"
1313 /* 674 */ "JSLT_rr_32\000"
1314 /* 685 */ "JULT_rr_32\000"
1315 /* 696 */ "SDIV_rr_32\000"
1316 /* 707 */ "MOV_rr_32\000"
1317 /* 717 */ "MOVSX_rr_32\000"
1318 /* 729 */ "Select_32\000"
1319 /* 739 */ "G_FLOG2\000"
1320 /* 747 */ "G_FATAN2\000"
1321 /* 756 */ "G_FEXP2\000"
1322 /* 764 */ "CORE_LD64\000"
1323 /* 774 */ "BE64\000"
1324 /* 779 */ "LE64\000"
1325 /* 784 */ "LDIMM64\000"
1326 /* 792 */ "BSWAP64\000"
1327 /* 800 */ "MOV_32_64\000"
1328 /* 810 */ "Select_Ri_32_64\000"
1329 /* 826 */ "Select_32_64\000"
1330 /* 839 */ "NEG_64\000"
1331 /* 846 */ "LD_imm64\000"
1332 /* 855 */ "BE16\000"
1333 /* 860 */ "LE16\000"
1334 /* 865 */ "BSWAP16\000"
1335 /* 873 */ "MOVSX_rr_32_16\000"
1336 /* 888 */ "MOVSX_rr_16\000"
1337 /* 900 */ "MOVSX_rr_32_8\000"
1338 /* 914 */ "MOVSX_rr_8\000"
1339 /* 925 */ "G_FMA\000"
1340 /* 931 */ "G_STRICT_FMA\000"
1341 /* 944 */ "LDB\000"
1342 /* 948 */ "STB\000"
1343 /* 952 */ "G_FSUB\000"
1344 /* 959 */ "G_STRICT_FSUB\000"
1345 /* 973 */ "G_ATOMICRMW_FSUB\000"
1346 /* 990 */ "G_SUB\000"
1347 /* 996 */ "G_ATOMICRMW_SUB\000"
1348 /* 1012 */ "LD_IND_B\000"
1349 /* 1021 */ "LD_ABS_B\000"
1350 /* 1030 */ "G_INTRINSIC\000"
1351 /* 1042 */ "G_FPTRUNC\000"
1352 /* 1052 */ "G_INTRINSIC_TRUNC\000"
1353 /* 1070 */ "G_TRUNC\000"
1354 /* 1078 */ "G_BUILD_VECTOR_TRUNC\000"
1355 /* 1099 */ "G_DYN_STACKALLOC\000"
1356 /* 1116 */ "G_FMAD\000"
1357 /* 1123 */ "G_FPEXTLOAD\000"
1358 /* 1135 */ "G_INDEXED_SEXTLOAD\000"
1359 /* 1154 */ "G_SEXTLOAD\000"
1360 /* 1165 */ "G_INDEXED_ZEXTLOAD\000"
1361 /* 1184 */ "G_ZEXTLOAD\000"
1362 /* 1195 */ "G_INDEXED_LOAD\000"
1363 /* 1210 */ "G_LOAD\000"
1364 /* 1217 */ "G_VECREDUCE_FADD\000"
1365 /* 1234 */ "G_FADD\000"
1366 /* 1241 */ "G_VECREDUCE_SEQ_FADD\000"
1367 /* 1262 */ "G_STRICT_FADD\000"
1368 /* 1276 */ "G_ATOMICRMW_FADD\000"
1369 /* 1293 */ "G_VECREDUCE_ADD\000"
1370 /* 1309 */ "G_ADD\000"
1371 /* 1315 */ "G_PTR_ADD\000"
1372 /* 1325 */ "G_ATOMICRMW_ADD\000"
1373 /* 1341 */ "XFADDD\000"
1374 /* 1348 */ "XADDD\000"
1375 /* 1354 */ "LDD\000"
1376 /* 1358 */ "XFANDD\000"
1377 /* 1365 */ "XANDD\000"
1378 /* 1371 */ "CMPXCHGD\000"
1379 /* 1380 */ "G_ATOMICRMW_NAND\000"
1380 /* 1397 */ "G_VECREDUCE_AND\000"
1381 /* 1413 */ "G_AND\000"
1382 /* 1419 */ "G_ATOMICRMW_AND\000"
1383 /* 1435 */ "LIFETIME_END\000"
1384 /* 1448 */ "JCOND\000"
1385 /* 1454 */ "G_BRCOND\000"
1386 /* 1463 */ "G_ATOMICRMW_USUB_COND\000"
1387 /* 1485 */ "G_LLROUND\000"
1388 /* 1495 */ "G_LROUND\000"
1389 /* 1504 */ "G_INTRINSIC_ROUND\000"
1390 /* 1522 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
1391 /* 1548 */ "LOAD_STACK_GUARD\000"
1392 /* 1565 */ "XFORD\000"
1393 /* 1571 */ "XFXORD\000"
1394 /* 1578 */ "XXORD\000"
1395 /* 1584 */ "STD\000"
1396 /* 1588 */ "PSEUDO_PROBE\000"
1397 /* 1601 */ "G_SSUBE\000"
1398 /* 1609 */ "G_USUBE\000"
1399 /* 1617 */ "G_FENCE\000"
1400 /* 1625 */ "ARITH_FENCE\000"
1401 /* 1637 */ "REG_SEQUENCE\000"
1402 /* 1650 */ "G_SADDE\000"
1403 /* 1658 */ "G_UADDE\000"
1404 /* 1666 */ "G_GET_FPMODE\000"
1405 /* 1679 */ "G_RESET_FPMODE\000"
1406 /* 1694 */ "G_SET_FPMODE\000"
1407 /* 1707 */ "G_FMINNUM_IEEE\000"
1408 /* 1722 */ "G_FMAXNUM_IEEE\000"
1409 /* 1737 */ "G_VSCALE\000"
1410 /* 1746 */ "G_JUMP_TABLE\000"
1411 /* 1759 */ "BUNDLE\000"
1412 /* 1766 */ "G_MEMSET_INLINE\000"
1413 /* 1782 */ "G_MEMCPY_INLINE\000"
1414 /* 1798 */ "RELOC_NONE\000"
1415 /* 1809 */ "LOCAL_ESCAPE\000"
1416 /* 1822 */ "G_FPTRUNCSTORE\000"
1417 /* 1837 */ "G_STACKRESTORE\000"
1418 /* 1852 */ "G_INDEXED_STORE\000"
1419 /* 1868 */ "G_STORE\000"
1420 /* 1876 */ "G_BITREVERSE\000"
1421 /* 1889 */ "FAKE_USE\000"
1422 /* 1898 */ "DBG_VALUE\000"
1423 /* 1908 */ "G_GLOBAL_VALUE\000"
1424 /* 1923 */ "G_PTRAUTH_GLOBAL_VALUE\000"
1425 /* 1946 */ "CONVERGENCECTRL_GLUE\000"
1426 /* 1967 */ "G_STACKSAVE\000"
1427 /* 1979 */ "G_MEMMOVE\000"
1428 /* 1989 */ "G_FREEZE\000"
1429 /* 1998 */ "G_FCANONICALIZE\000"
1430 /* 2014 */ "G_FMODF\000"
1431 /* 2022 */ "INIT_UNDEF\000"
1432 /* 2033 */ "G_IMPLICIT_DEF\000"
1433 /* 2048 */ "DBG_INSTR_REF\000"
1434 /* 2062 */ "G_FNEG\000"
1435 /* 2069 */ "EXTRACT_SUBREG\000"
1436 /* 2084 */ "INSERT_SUBREG\000"
1437 /* 2098 */ "G_SEXT_INREG\000"
1438 /* 2111 */ "SUBREG_TO_REG\000"
1439 /* 2125 */ "G_ATOMIC_CMPXCHG\000"
1440 /* 2142 */ "G_ATOMICRMW_XCHG\000"
1441 /* 2159 */ "G_GET_ROUNDING\000"
1442 /* 2174 */ "G_SET_ROUNDING\000"
1443 /* 2189 */ "G_FLOG\000"
1444 /* 2196 */ "G_VAARG\000"
1445 /* 2204 */ "PREALLOCATED_ARG\000"
1446 /* 2221 */ "G_PREFETCH\000"
1447 /* 2232 */ "LDH\000"
1448 /* 2236 */ "G_CLMULH\000"
1449 /* 2245 */ "G_SMULH\000"
1450 /* 2253 */ "G_UMULH\000"
1451 /* 2261 */ "G_FTANH\000"
1452 /* 2269 */ "G_FSINH\000"
1453 /* 2277 */ "G_FCOSH\000"
1454 /* 2285 */ "STH\000"
1455 /* 2289 */ "LD_IND_H\000"
1456 /* 2298 */ "LD_ABS_H\000"
1457 /* 2307 */ "DBG_PHI\000"
1458 /* 2315 */ "G_FPTOSI\000"
1459 /* 2324 */ "G_FPTOUI\000"
1460 /* 2333 */ "G_FPOWI\000"
1461 /* 2341 */ "COPY_LANEMASK\000"
1462 /* 2355 */ "G_PTRMASK\000"
1463 /* 2365 */ "JAL\000"
1464 /* 2369 */ "GC_LABEL\000"
1465 /* 2378 */ "DBG_LABEL\000"
1466 /* 2388 */ "EH_LABEL\000"
1467 /* 2397 */ "ANNOTATION_LABEL\000"
1468 /* 2414 */ "ICALL_BRANCH_FUNNEL\000"
1469 /* 2434 */ "STDREL\000"
1470 /* 2441 */ "G_FSHL\000"
1471 /* 2448 */ "G_SHL\000"
1472 /* 2454 */ "G_FCEIL\000"
1473 /* 2462 */ "G_SAVGCEIL\000"
1474 /* 2473 */ "G_UAVGCEIL\000"
1475 /* 2484 */ "PATCHABLE_TAIL_CALL\000"
1476 /* 2504 */ "PATCHABLE_TYPED_EVENT_CALL\000"
1477 /* 2531 */ "PATCHABLE_EVENT_CALL\000"
1478 /* 2552 */ "FENTRY_CALL\000"
1479 /* 2564 */ "KILL\000"
1480 /* 2569 */ "G_CONSTANT_POOL\000"
1481 /* 2585 */ "JMPL\000"
1482 /* 2590 */ "G_ROTL\000"
1483 /* 2597 */ "G_VECREDUCE_FMUL\000"
1484 /* 2614 */ "G_FMUL\000"
1485 /* 2621 */ "G_VECREDUCE_SEQ_FMUL\000"
1486 /* 2642 */ "G_STRICT_FMUL\000"
1487 /* 2656 */ "G_CLMUL\000"
1488 /* 2664 */ "G_VECREDUCE_MUL\000"
1489 /* 2680 */ "G_MUL\000"
1490 /* 2686 */ "G_FREM\000"
1491 /* 2693 */ "G_STRICT_FREM\000"
1492 /* 2707 */ "G_SREM\000"
1493 /* 2714 */ "G_UREM\000"
1494 /* 2721 */ "G_SDIVREM\000"
1495 /* 2731 */ "G_UDIVREM\000"
1496 /* 2741 */ "INLINEASM\000"
1497 /* 2751 */ "G_VECREDUCE_FMINIMUM\000"
1498 /* 2772 */ "G_FMINIMUM\000"
1499 /* 2783 */ "G_ATOMICRMW_FMINIMUM\000"
1500 /* 2804 */ "G_VECREDUCE_FMAXIMUM\000"
1501 /* 2825 */ "G_FMAXIMUM\000"
1502 /* 2836 */ "G_ATOMICRMW_FMAXIMUM\000"
1503 /* 2857 */ "G_VECREDUCE_FMINIMUMNUM\000"
1504 /* 2881 */ "G_FMINIMUMNUM\000"
1505 /* 2895 */ "G_ATOMICRMW_FMINIMUMNUM\000"
1506 /* 2919 */ "G_VECREDUCE_FMAXIMUMNUM\000"
1507 /* 2943 */ "G_FMAXIMUMNUM\000"
1508 /* 2957 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
1509 /* 2981 */ "G_FMINNUM\000"
1510 /* 2991 */ "G_FMAXNUM\000"
1511 /* 3001 */ "G_FATAN\000"
1512 /* 3009 */ "G_FTAN\000"
1513 /* 3016 */ "G_INTRINSIC_ROUNDEVEN\000"
1514 /* 3038 */ "G_ASSERT_ALIGN\000"
1515 /* 3053 */ "G_FCOPYSIGN\000"
1516 /* 3065 */ "G_VECREDUCE_FMIN\000"
1517 /* 3082 */ "G_ATOMICRMW_FMIN\000"
1518 /* 3099 */ "G_VECREDUCE_SMIN\000"
1519 /* 3116 */ "G_SMIN\000"
1520 /* 3123 */ "G_VECREDUCE_UMIN\000"
1521 /* 3140 */ "G_UMIN\000"
1522 /* 3147 */ "G_ATOMICRMW_UMIN\000"
1523 /* 3164 */ "G_ATOMICRMW_MIN\000"
1524 /* 3180 */ "G_FASIN\000"
1525 /* 3188 */ "G_FSIN\000"
1526 /* 3195 */ "CFI_INSTRUCTION\000"
1527 /* 3211 */ "G_CTLZ_ZERO_POISON\000"
1528 /* 3230 */ "G_CTTZ_ZERO_POISON\000"
1529 /* 3249 */ "ADJCALLSTACKDOWN\000"
1530 /* 3266 */ "G_SSUBO\000"
1531 /* 3274 */ "G_USUBO\000"
1532 /* 3282 */ "G_SADDO\000"
1533 /* 3290 */ "G_UADDO\000"
1534 /* 3298 */ "LOAD_STACK_ARG_PSEUDO\000"
1535 /* 3320 */ "STORE_STACK_ARG_PSEUDO\000"
1536 /* 3343 */ "STORE_STACK_ARG_IMM_PSEUDO\000"
1537 /* 3370 */ "JUMP_TABLE_DEBUG_INFO\000"
1538 /* 3392 */ "G_SMULO\000"
1539 /* 3400 */ "G_UMULO\000"
1540 /* 3408 */ "G_BZERO\000"
1541 /* 3416 */ "STACKMAP\000"
1542 /* 3425 */ "G_DEBUGTRAP\000"
1543 /* 3437 */ "G_UBSANTRAP\000"
1544 /* 3449 */ "G_TRAP\000"
1545 /* 3456 */ "G_ATOMICRMW_UDEC_WRAP\000"
1546 /* 3478 */ "G_ATOMICRMW_UINC_WRAP\000"
1547 /* 3500 */ "G_BSWAP\000"
1548 /* 3508 */ "G_SITOFP\000"
1549 /* 3517 */ "G_UITOFP\000"
1550 /* 3526 */ "G_FCMP\000"
1551 /* 3533 */ "G_STRICT_FCMP\000"
1552 /* 3547 */ "G_ICMP\000"
1553 /* 3554 */ "G_SCMP\000"
1554 /* 3561 */ "G_UCMP\000"
1555 /* 3568 */ "JMP\000"
1556 /* 3572 */ "NOP\000"
1557 /* 3576 */ "CONVERGENCECTRL_LOOP\000"
1558 /* 3597 */ "G_CTPOP\000"
1559 /* 3605 */ "PATCHABLE_OP\000"
1560 /* 3618 */ "FAULTING_OP\000"
1561 /* 3630 */ "ADJCALLSTACKUP\000"
1562 /* 3645 */ "PREALLOCATED_SETUP\000"
1563 /* 3664 */ "G_FLDEXP\000"
1564 /* 3673 */ "G_STRICT_FLDEXP\000"
1565 /* 3689 */ "G_FEXP\000"
1566 /* 3696 */ "G_FFREXP\000"
1567 /* 3705 */ "LDDACQ\000"
1568 /* 3712 */ "G_BR\000"
1569 /* 3717 */ "INLINEASM_BR\000"
1570 /* 3730 */ "G_BLOCK_ADDR\000"
1571 /* 3743 */ "MEMBARRIER\000"
1572 /* 3754 */ "G_CONSTANT_FOLD_BARRIER\000"
1573 /* 3778 */ "PATCHABLE_FUNCTION_ENTER\000"
1574 /* 3803 */ "G_READCYCLECOUNTER\000"
1575 /* 3822 */ "G_READSTEADYCOUNTER\000"
1576 /* 3842 */ "G_READ_REGISTER\000"
1577 /* 3858 */ "G_WRITE_REGISTER\000"
1578 /* 3875 */ "G_ASHR\000"
1579 /* 3882 */ "G_FSHR\000"
1580 /* 3889 */ "G_LSHR\000"
1581 /* 3896 */ "G_CLMULR\000"
1582 /* 3905 */ "CONVERGENCECTRL_ANCHOR\000"
1583 /* 3928 */ "G_FFLOOR\000"
1584 /* 3937 */ "G_SAVGFLOOR\000"
1585 /* 3949 */ "G_UAVGFLOOR\000"
1586 /* 3961 */ "G_EXTRACT_SUBVECTOR\000"
1587 /* 3981 */ "G_INSERT_SUBVECTOR\000"
1588 /* 4000 */ "G_BUILD_VECTOR\000"
1589 /* 4015 */ "G_SHUFFLE_VECTOR\000"
1590 /* 4032 */ "G_STEP_VECTOR\000"
1591 /* 4046 */ "G_SPLAT_VECTOR\000"
1592 /* 4061 */ "G_VECREDUCE_XOR\000"
1593 /* 4077 */ "G_XOR\000"
1594 /* 4083 */ "G_ATOMICRMW_XOR\000"
1595 /* 4099 */ "G_VECREDUCE_OR\000"
1596 /* 4114 */ "G_OR\000"
1597 /* 4119 */ "G_ATOMICRMW_OR\000"
1598 /* 4134 */ "G_ROTR\000"
1599 /* 4141 */ "G_INTTOPTR\000"
1600 /* 4152 */ "G_FABS\000"
1601 /* 4159 */ "G_ABS\000"
1602 /* 4165 */ "G_ABDS\000"
1603 /* 4172 */ "G_UNMERGE_VALUES\000"
1604 /* 4189 */ "G_MERGE_VALUES\000"
1605 /* 4204 */ "G_CTLS\000"
1606 /* 4211 */ "G_FACOS\000"
1607 /* 4219 */ "G_FCOS\000"
1608 /* 4226 */ "G_FSINCOS\000"
1609 /* 4236 */ "G_STRICT_FCMPS\000"
1610 /* 4251 */ "G_CONCAT_VECTORS\000"
1611 /* 4268 */ "COPY_TO_REGCLASS\000"
1612 /* 4285 */ "G_IS_FPCLASS\000"
1613 /* 4298 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1614 /* 4328 */ "G_VECTOR_COMPRESS\000"
1615 /* 4346 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1616 /* 4373 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1617 /* 4411 */ "G_TRUNC_SSAT_S\000"
1618 /* 4426 */ "G_SSUBSAT\000"
1619 /* 4436 */ "G_USUBSAT\000"
1620 /* 4446 */ "G_SADDSAT\000"
1621 /* 4456 */ "G_UADDSAT\000"
1622 /* 4466 */ "G_SSHLSAT\000"
1623 /* 4476 */ "G_USHLSAT\000"
1624 /* 4486 */ "G_SMULFIXSAT\000"
1625 /* 4499 */ "G_UMULFIXSAT\000"
1626 /* 4512 */ "G_SDIVFIXSAT\000"
1627 /* 4525 */ "G_UDIVFIXSAT\000"
1628 /* 4538 */ "G_ATOMICRMW_USUB_SAT\000"
1629 /* 4559 */ "G_FPTOSI_SAT\000"
1630 /* 4572 */ "G_FPTOUI_SAT\000"
1631 /* 4585 */ "G_EXTRACT\000"
1632 /* 4595 */ "G_SELECT\000"
1633 /* 4604 */ "G_BRINDIRECT\000"
1634 /* 4617 */ "PATCHABLE_RET\000"
1635 /* 4631 */ "G_MEMSET\000"
1636 /* 4640 */ "CORE_SHIFT\000"
1637 /* 4651 */ "PATCHABLE_FUNCTION_EXIT\000"
1638 /* 4675 */ "G_BRJT\000"
1639 /* 4682 */ "G_EXTRACT_VECTOR_ELT\000"
1640 /* 4703 */ "G_INSERT_VECTOR_ELT\000"
1641 /* 4723 */ "G_FCONSTANT\000"
1642 /* 4735 */ "G_CONSTANT\000"
1643 /* 4746 */ "G_INTRINSIC_CONVERGENT\000"
1644 /* 4769 */ "STATEPOINT\000"
1645 /* 4780 */ "PATCHPOINT\000"
1646 /* 4791 */ "G_PTRTOINT\000"
1647 /* 4802 */ "G_FRINT\000"
1648 /* 4810 */ "G_INTRINSIC_LLRINT\000"
1649 /* 4829 */ "G_INTRINSIC_LRINT\000"
1650 /* 4847 */ "G_FNEARBYINT\000"
1651 /* 4860 */ "G_VASTART\000"
1652 /* 4870 */ "LIFETIME_START\000"
1653 /* 4885 */ "G_INVOKE_REGION_START\000"
1654 /* 4907 */ "G_INSERT\000"
1655 /* 4916 */ "G_FSQRT\000"
1656 /* 4924 */ "G_STRICT_FSQRT\000"
1657 /* 4939 */ "G_BITCAST\000"
1658 /* 4949 */ "G_ADDRSPACE_CAST\000"
1659 /* 4966 */ "ADDR_SPACE_CAST\000"
1660 /* 4982 */ "DBG_VALUE_LIST\000"
1661 /* 4997 */ "CORE_ST\000"
1662 /* 5005 */ "G_FPEXT\000"
1663 /* 5013 */ "G_SEXT\000"
1664 /* 5020 */ "G_ASSERT_SEXT\000"
1665 /* 5034 */ "G_ANYEXT\000"
1666 /* 5043 */ "G_ZEXT\000"
1667 /* 5050 */ "G_ASSERT_ZEXT\000"
1668 /* 5064 */ "G_ABDU\000"
1669 /* 5071 */ "G_TRUNC_SSAT_U\000"
1670 /* 5086 */ "G_TRUNC_USAT_U\000"
1671 /* 5101 */ "G_FDIV\000"
1672 /* 5108 */ "G_STRICT_FDIV\000"
1673 /* 5122 */ "G_SDIV\000"
1674 /* 5129 */ "G_UDIV\000"
1675 /* 5136 */ "G_GET_FPENV\000"
1676 /* 5148 */ "G_RESET_FPENV\000"
1677 /* 5162 */ "G_SET_FPENV\000"
1678 /* 5174 */ "XADDW\000"
1679 /* 5180 */ "LDW\000"
1680 /* 5184 */ "G_FPOW\000"
1681 /* 5191 */ "STW\000"
1682 /* 5195 */ "LD_IND_W\000"
1683 /* 5204 */ "LD_ABS_W\000"
1684 /* 5213 */ "G_VECREDUCE_FMAX\000"
1685 /* 5230 */ "G_ATOMICRMW_FMAX\000"
1686 /* 5247 */ "G_VECREDUCE_SMAX\000"
1687 /* 5264 */ "G_SMAX\000"
1688 /* 5271 */ "G_VECREDUCE_UMAX\000"
1689 /* 5288 */ "G_UMAX\000"
1690 /* 5295 */ "G_ATOMICRMW_UMAX\000"
1691 /* 5312 */ "G_ATOMICRMW_MAX\000"
1692 /* 5328 */ "G_FRAME_INDEX\000"
1693 /* 5342 */ "G_SBFX\000"
1694 /* 5349 */ "G_UBFX\000"
1695 /* 5356 */ "G_SMULFIX\000"
1696 /* 5366 */ "G_UMULFIX\000"
1697 /* 5376 */ "G_SDIVFIX\000"
1698 /* 5386 */ "G_UDIVFIX\000"
1699 /* 5396 */ "JX\000"
1700 /* 5399 */ "JALX\000"
1701 /* 5404 */ "LDBSX\000"
1702 /* 5410 */ "LDHSX\000"
1703 /* 5416 */ "LDWSX\000"
1704 /* 5422 */ "G_MEMCPY\000"
1705 /* 5431 */ "COPY\000"
1706 /* 5436 */ "CONVERGENCECTRL_ENTRY\000"
1707 /* 5458 */ "G_CTLZ\000"
1708 /* 5465 */ "G_CTTZ\000"
1709 /* 5472 */ "Select_Ri\000"
1710 /* 5482 */ "SRA_ri\000"
1711 /* 5489 */ "SUB_ri\000"
1712 /* 5496 */ "ADD_ri\000"
1713 /* 5503 */ "AND_ri\000"
1714 /* 5510 */ "SMOD_ri\000"
1715 /* 5518 */ "JSGE_ri\000"
1716 /* 5526 */ "JUGE_ri\000"
1717 /* 5534 */ "JSLE_ri\000"
1718 /* 5542 */ "JULE_ri\000"
1719 /* 5550 */ "JNE_ri\000"
1720 /* 5557 */ "FI_ri\000"
1721 /* 5563 */ "SLL_ri\000"
1722 /* 5570 */ "SRL_ri\000"
1723 /* 5577 */ "MUL_ri\000"
1724 /* 5584 */ "JEQ_ri\000"
1725 /* 5591 */ "XOR_ri\000"
1726 /* 5598 */ "JSET_ri\000"
1727 /* 5606 */ "JSGT_ri\000"
1728 /* 5614 */ "JUGT_ri\000"
1729 /* 5622 */ "JSLT_ri\000"
1730 /* 5630 */ "JULT_ri\000"
1731 /* 5638 */ "SDIV_ri\000"
1732 /* 5646 */ "MOV_ri\000"
1733 /* 5653 */ "STB_imm\000"
1734 /* 5661 */ "STD_imm\000"
1735 /* 5669 */ "STH_imm\000"
1736 /* 5677 */ "STW_imm\000"
1737 /* 5685 */ "LD_pseudo\000"
1738 /* 5695 */ "SRA_rr\000"
1739 /* 5702 */ "SUB_rr\000"
1740 /* 5709 */ "ADD_rr\000"
1741 /* 5716 */ "AND_rr\000"
1742 /* 5723 */ "SMOD_rr\000"
1743 /* 5731 */ "JSGE_rr\000"
1744 /* 5739 */ "JUGE_rr\000"
1745 /* 5747 */ "JSLE_rr\000"
1746 /* 5755 */ "JULE_rr\000"
1747 /* 5763 */ "JNE_rr\000"
1748 /* 5770 */ "SLL_rr\000"
1749 /* 5777 */ "SRL_rr\000"
1750 /* 5784 */ "MUL_rr\000"
1751 /* 5791 */ "JEQ_rr\000"
1752 /* 5798 */ "XOR_rr\000"
1753 /* 5805 */ "JSET_rr\000"
1754 /* 5813 */ "JSGT_rr\000"
1755 /* 5821 */ "JUGT_rr\000"
1756 /* 5829 */ "JSLT_rr\000"
1757 /* 5837 */ "JULT_rr\000"
1758 /* 5845 */ "SDIV_rr\000"
1759 /* 5853 */ "MOV_rr\000"
1760 /* 5860 */ "Select\000"
1761};
1762#ifdef __GNUC__
1763#pragma GCC diagnostic pop
1764#endif
1765
1766extern const unsigned BPFInstrNameIndices[] = {
1767 2311U, 2741U, 3717U, 3195U, 2388U, 2369U, 2397U, 2564U,
1768 2069U, 2084U, 2035U, 2022U, 2111U, 4268U, 1898U, 4982U,
1769 2048U, 2307U, 2378U, 1637U, 5431U, 2341U, 1759U, 4870U,
1770 1435U, 1588U, 1625U, 3416U, 2552U, 4780U, 1548U, 3645U,
1771 2204U, 4769U, 1809U, 3618U, 3605U, 3778U, 4617U, 4651U,
1772 2484U, 2531U, 2504U, 2414U, 1889U, 3743U, 3370U, 1798U,
1773 5436U, 3905U, 3576U, 1946U, 5020U, 5050U, 3038U, 1309U,
1774 990U, 2680U, 5122U, 5129U, 2707U, 2714U, 2721U, 2731U,
1775 1413U, 4114U, 4077U, 4165U, 5064U, 3949U, 2473U, 3937U,
1776 2462U, 2033U, 2309U, 5328U, 1908U, 1923U, 2569U, 4585U,
1777 4172U, 4907U, 4189U, 4000U, 1078U, 4251U, 4791U, 4141U,
1778 4939U, 1989U, 3754U, 1522U, 1052U, 1504U, 4829U, 4810U,
1779 3016U, 3803U, 3822U, 1210U, 1154U, 1184U, 1123U, 1195U,
1780 1135U, 1165U, 1868U, 1822U, 1852U, 4298U, 2125U, 2142U,
1781 1325U, 996U, 1419U, 1380U, 4119U, 4083U, 5312U, 3164U,
1782 5295U, 3147U, 1276U, 973U, 5230U, 3082U, 2836U, 2783U,
1783 2957U, 2895U, 3478U, 3456U, 1463U, 4538U, 1617U, 2221U,
1784 1454U, 4604U, 4885U, 1030U, 4346U, 4746U, 4373U, 5034U,
1785 1070U, 4411U, 5071U, 5086U, 4735U, 4723U, 4860U, 2196U,
1786 5013U, 2098U, 5043U, 2448U, 3889U, 3875U, 2441U, 3882U,
1787 4134U, 2590U, 3547U, 3526U, 3554U, 3561U, 4595U, 3290U,
1788 1658U, 3274U, 1609U, 3282U, 1650U, 3266U, 1601U, 3400U,
1789 3392U, 2253U, 2245U, 4456U, 4446U, 4436U, 4426U, 4476U,
1790 4466U, 5356U, 5366U, 4486U, 4499U, 5376U, 5386U, 4512U,
1791 4525U, 1234U, 952U, 2614U, 925U, 1116U, 5101U, 2686U,
1792 2014U, 5184U, 2333U, 3689U, 756U, 9U, 2189U, 739U,
1793 0U, 3664U, 3696U, 2062U, 5005U, 1042U, 2315U, 2324U,
1794 3508U, 3517U, 4559U, 4572U, 4152U, 3053U, 4285U, 1998U,
1795 2981U, 2991U, 1707U, 1722U, 2772U, 2825U, 2881U, 2943U,
1796 5136U, 5162U, 5148U, 1666U, 1694U, 1679U, 2159U, 2174U,
1797 1315U, 2355U, 3116U, 5264U, 3140U, 5288U, 4159U, 1495U,
1798 1485U, 3712U, 4675U, 1737U, 3981U, 3961U, 4703U, 4682U,
1799 4015U, 4046U, 4032U, 4328U, 5465U, 3230U, 5458U, 3211U,
1800 4204U, 3597U, 3500U, 1876U, 2656U, 2236U, 3896U, 2454U,
1801 4219U, 3188U, 4226U, 3009U, 4211U, 3180U, 3001U, 747U,
1802 2277U, 2269U, 2261U, 4916U, 3928U, 4802U, 4847U, 4949U,
1803 3730U, 1746U, 1099U, 1967U, 1837U, 1262U, 959U, 2642U,
1804 5108U, 2693U, 931U, 4924U, 3673U, 3533U, 4236U, 3842U,
1805 3858U, 5422U, 1782U, 1979U, 4631U, 3408U, 1766U, 3449U,
1806 3425U, 3437U, 1241U, 2621U, 1217U, 2597U, 5213U, 3065U,
1807 2804U, 2751U, 2919U, 2857U, 1293U, 2664U, 1397U, 4099U,
1808 4061U, 5247U, 3099U, 5271U, 3123U, 5342U, 5349U, 3249U,
1809 3630U, 5557U, 784U, 3298U, 5424U, 3343U, 3320U, 5860U,
1810 729U, 826U, 222U, 5472U, 242U, 810U, 206U, 4966U,
1811 5496U, 275U, 5709U, 506U, 5503U, 285U, 5716U, 516U,
1812 855U, 40U, 774U, 865U, 89U, 792U, 1371U, 164U,
1813 30U, 764U, 4640U, 4997U, 5639U, 466U, 5846U, 697U,
1814 2365U, 5399U, 1448U, 5584U, 390U, 5791U, 621U, 3568U,
1815 2585U, 5550U, 350U, 5763U, 581U, 5598U, 410U, 5805U,
1816 641U, 5518U, 306U, 5731U, 537U, 5606U, 421U, 5813U,
1817 652U, 5534U, 328U, 5747U, 559U, 5622U, 443U, 5829U,
1818 674U, 5526U, 317U, 5739U, 548U, 5614U, 432U, 5821U,
1819 663U, 5542U, 339U, 5755U, 570U, 5630U, 454U, 5837U,
1820 685U, 5396U, 944U, 18U, 97U, 5404U, 1354U, 3705U,
1821 2232U, 50U, 106U, 5410U, 5180U, 141U, 115U, 5416U,
1822 1021U, 2298U, 5204U, 1012U, 2289U, 5195U, 846U, 5685U,
1823 860U, 45U, 779U, 5511U, 296U, 5724U, 527U, 888U,
1824 717U, 873U, 900U, 914U, 800U, 5646U, 476U, 5853U,
1825 707U, 5577U, 380U, 5784U, 611U, 235U, 839U, 3572U,
1826 5592U, 401U, 5799U, 632U, 4627U, 5638U, 465U, 5845U,
1827 696U, 5563U, 360U, 5770U, 591U, 5510U, 295U, 5723U,
1828 526U, 5482U, 255U, 5695U, 486U, 5570U, 370U, 5777U,
1829 601U, 948U, 24U, 62U, 5653U, 1584U, 2434U, 5661U,
1830 2285U, 56U, 71U, 5669U, 5191U, 200U, 80U, 5677U,
1831 5489U, 265U, 5702U, 496U, 1348U, 5174U, 133U, 1365U,
1832 156U, 1374U, 167U, 1341U, 124U, 1358U, 147U, 1565U,
1833 175U, 1571U, 183U, 1573U, 185U, 5591U, 400U, 5798U,
1834 631U, 1578U, 192U,
1835};
1836
1837static inline void InitBPFMCInstrInfo(MCInstrInfo *II) {
1838 II->InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 539, nullptr, 0);
1839}
1840
1841
1842} // namespace llvm
1843
1844#endif // GET_INSTRINFO_MC_DESC
1845
1846#ifdef GET_INSTRINFO_HEADER
1847#undef GET_INSTRINFO_HEADER
1848
1849namespace llvm {
1850
1851struct BPFGenInstrInfo : public TargetInstrInfo {
1852 explicit BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1853 ~BPFGenInstrInfo() override = default;
1854};
1855
1856} // namespace llvm
1857
1858namespace llvm::BPF {
1859
1860
1861} // namespace llvm::BPF
1862
1863#endif // GET_INSTRINFO_HEADER
1864
1865#ifdef GET_INSTRINFO_HELPER_DECLS
1866#undef GET_INSTRINFO_HELPER_DECLS
1867
1868
1869#endif // GET_INSTRINFO_HELPER_DECLS
1870
1871#ifdef GET_INSTRINFO_HELPERS
1872#undef GET_INSTRINFO_HELPERS
1873
1874
1875#endif // GET_INSTRINFO_HELPERS
1876
1877#ifdef GET_INSTRINFO_CTOR_DTOR
1878#undef GET_INSTRINFO_CTOR_DTOR
1879
1880namespace llvm {
1881
1882extern const BPFInstrTable BPFDescs;
1883extern const unsigned BPFInstrNameIndices[];
1884extern const char BPFInstrNameData[];
1885BPFGenInstrInfo::BPFGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1886 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1887 InitMCInstrInfo(BPFDescs.Insts, BPFInstrNameIndices, BPFInstrNameData, nullptr, nullptr, 539);
1888}
1889
1890} // namespace llvm
1891
1892#endif // GET_INSTRINFO_CTOR_DTOR
1893
1894#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1895#undef GET_INSTRINFO_MC_HELPER_DECLS
1896
1897namespace llvm {
1898
1899class MCInst;
1900class FeatureBitset;
1901
1902namespace BPF_MC {
1903
1904void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1905
1906} // namespace BPF_MC
1907
1908} // namespace llvm
1909
1910#endif // GET_INSTRINFO_MC_HELPER_DECLS
1911
1912#ifdef GET_INSTRINFO_MC_HELPERS
1913#undef GET_INSTRINFO_MC_HELPERS
1914
1915namespace llvm::BPF_MC {
1916
1917
1918} // namespace llvm::BPF_MC
1919
1920#endif // GET_INSTRINFO_MC_HELPERS
1921
1922#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1923 defined(GET_AVAILABLE_OPCODE_CHECKER)
1924#define GET_COMPUTE_FEATURES
1925#endif
1926#ifdef GET_COMPUTE_FEATURES
1927#undef GET_COMPUTE_FEATURES
1928
1929namespace llvm::BPF_MC {
1930
1931// Bits for subtarget features that participate in instruction matching.
1932enum SubtargetFeatureBits : uint8_t {
1933};
1934
1935inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1936 FeatureBitset Features;
1937 return Features;
1938}
1939
1940inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1941 enum : uint8_t {
1942 CEFBS_None,
1943 };
1944
1945 static constexpr FeatureBitset FeatureBitsets[] = {
1946 {}, // CEFBS_None
1947 };
1948 static constexpr uint8_t RequiredFeaturesRefs[] = {
1949 CEFBS_None, // PHI
1950 CEFBS_None, // INLINEASM
1951 CEFBS_None, // INLINEASM_BR
1952 CEFBS_None, // CFI_INSTRUCTION
1953 CEFBS_None, // EH_LABEL
1954 CEFBS_None, // GC_LABEL
1955 CEFBS_None, // ANNOTATION_LABEL
1956 CEFBS_None, // KILL
1957 CEFBS_None, // EXTRACT_SUBREG
1958 CEFBS_None, // INSERT_SUBREG
1959 CEFBS_None, // IMPLICIT_DEF
1960 CEFBS_None, // INIT_UNDEF
1961 CEFBS_None, // SUBREG_TO_REG
1962 CEFBS_None, // COPY_TO_REGCLASS
1963 CEFBS_None, // DBG_VALUE
1964 CEFBS_None, // DBG_VALUE_LIST
1965 CEFBS_None, // DBG_INSTR_REF
1966 CEFBS_None, // DBG_PHI
1967 CEFBS_None, // DBG_LABEL
1968 CEFBS_None, // REG_SEQUENCE
1969 CEFBS_None, // COPY
1970 CEFBS_None, // COPY_LANEMASK
1971 CEFBS_None, // BUNDLE
1972 CEFBS_None, // LIFETIME_START
1973 CEFBS_None, // LIFETIME_END
1974 CEFBS_None, // PSEUDO_PROBE
1975 CEFBS_None, // ARITH_FENCE
1976 CEFBS_None, // STACKMAP
1977 CEFBS_None, // FENTRY_CALL
1978 CEFBS_None, // PATCHPOINT
1979 CEFBS_None, // LOAD_STACK_GUARD
1980 CEFBS_None, // PREALLOCATED_SETUP
1981 CEFBS_None, // PREALLOCATED_ARG
1982 CEFBS_None, // STATEPOINT
1983 CEFBS_None, // LOCAL_ESCAPE
1984 CEFBS_None, // FAULTING_OP
1985 CEFBS_None, // PATCHABLE_OP
1986 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1987 CEFBS_None, // PATCHABLE_RET
1988 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1989 CEFBS_None, // PATCHABLE_TAIL_CALL
1990 CEFBS_None, // PATCHABLE_EVENT_CALL
1991 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1992 CEFBS_None, // ICALL_BRANCH_FUNNEL
1993 CEFBS_None, // FAKE_USE
1994 CEFBS_None, // MEMBARRIER
1995 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1996 CEFBS_None, // RELOC_NONE
1997 CEFBS_None, // CONVERGENCECTRL_ENTRY
1998 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1999 CEFBS_None, // CONVERGENCECTRL_LOOP
2000 CEFBS_None, // CONVERGENCECTRL_GLUE
2001 CEFBS_None, // G_ASSERT_SEXT
2002 CEFBS_None, // G_ASSERT_ZEXT
2003 CEFBS_None, // G_ASSERT_ALIGN
2004 CEFBS_None, // G_ADD
2005 CEFBS_None, // G_SUB
2006 CEFBS_None, // G_MUL
2007 CEFBS_None, // G_SDIV
2008 CEFBS_None, // G_UDIV
2009 CEFBS_None, // G_SREM
2010 CEFBS_None, // G_UREM
2011 CEFBS_None, // G_SDIVREM
2012 CEFBS_None, // G_UDIVREM
2013 CEFBS_None, // G_AND
2014 CEFBS_None, // G_OR
2015 CEFBS_None, // G_XOR
2016 CEFBS_None, // G_ABDS
2017 CEFBS_None, // G_ABDU
2018 CEFBS_None, // G_UAVGFLOOR
2019 CEFBS_None, // G_UAVGCEIL
2020 CEFBS_None, // G_SAVGFLOOR
2021 CEFBS_None, // G_SAVGCEIL
2022 CEFBS_None, // G_IMPLICIT_DEF
2023 CEFBS_None, // G_PHI
2024 CEFBS_None, // G_FRAME_INDEX
2025 CEFBS_None, // G_GLOBAL_VALUE
2026 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
2027 CEFBS_None, // G_CONSTANT_POOL
2028 CEFBS_None, // G_EXTRACT
2029 CEFBS_None, // G_UNMERGE_VALUES
2030 CEFBS_None, // G_INSERT
2031 CEFBS_None, // G_MERGE_VALUES
2032 CEFBS_None, // G_BUILD_VECTOR
2033 CEFBS_None, // G_BUILD_VECTOR_TRUNC
2034 CEFBS_None, // G_CONCAT_VECTORS
2035 CEFBS_None, // G_PTRTOINT
2036 CEFBS_None, // G_INTTOPTR
2037 CEFBS_None, // G_BITCAST
2038 CEFBS_None, // G_FREEZE
2039 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
2040 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
2041 CEFBS_None, // G_INTRINSIC_TRUNC
2042 CEFBS_None, // G_INTRINSIC_ROUND
2043 CEFBS_None, // G_INTRINSIC_LRINT
2044 CEFBS_None, // G_INTRINSIC_LLRINT
2045 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
2046 CEFBS_None, // G_READCYCLECOUNTER
2047 CEFBS_None, // G_READSTEADYCOUNTER
2048 CEFBS_None, // G_LOAD
2049 CEFBS_None, // G_SEXTLOAD
2050 CEFBS_None, // G_ZEXTLOAD
2051 CEFBS_None, // G_FPEXTLOAD
2052 CEFBS_None, // G_INDEXED_LOAD
2053 CEFBS_None, // G_INDEXED_SEXTLOAD
2054 CEFBS_None, // G_INDEXED_ZEXTLOAD
2055 CEFBS_None, // G_STORE
2056 CEFBS_None, // G_FPTRUNCSTORE
2057 CEFBS_None, // G_INDEXED_STORE
2058 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
2059 CEFBS_None, // G_ATOMIC_CMPXCHG
2060 CEFBS_None, // G_ATOMICRMW_XCHG
2061 CEFBS_None, // G_ATOMICRMW_ADD
2062 CEFBS_None, // G_ATOMICRMW_SUB
2063 CEFBS_None, // G_ATOMICRMW_AND
2064 CEFBS_None, // G_ATOMICRMW_NAND
2065 CEFBS_None, // G_ATOMICRMW_OR
2066 CEFBS_None, // G_ATOMICRMW_XOR
2067 CEFBS_None, // G_ATOMICRMW_MAX
2068 CEFBS_None, // G_ATOMICRMW_MIN
2069 CEFBS_None, // G_ATOMICRMW_UMAX
2070 CEFBS_None, // G_ATOMICRMW_UMIN
2071 CEFBS_None, // G_ATOMICRMW_FADD
2072 CEFBS_None, // G_ATOMICRMW_FSUB
2073 CEFBS_None, // G_ATOMICRMW_FMAX
2074 CEFBS_None, // G_ATOMICRMW_FMIN
2075 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
2076 CEFBS_None, // G_ATOMICRMW_FMINIMUM
2077 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
2078 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
2079 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
2080 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
2081 CEFBS_None, // G_ATOMICRMW_USUB_COND
2082 CEFBS_None, // G_ATOMICRMW_USUB_SAT
2083 CEFBS_None, // G_FENCE
2084 CEFBS_None, // G_PREFETCH
2085 CEFBS_None, // G_BRCOND
2086 CEFBS_None, // G_BRINDIRECT
2087 CEFBS_None, // G_INVOKE_REGION_START
2088 CEFBS_None, // G_INTRINSIC
2089 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
2090 CEFBS_None, // G_INTRINSIC_CONVERGENT
2091 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
2092 CEFBS_None, // G_ANYEXT
2093 CEFBS_None, // G_TRUNC
2094 CEFBS_None, // G_TRUNC_SSAT_S
2095 CEFBS_None, // G_TRUNC_SSAT_U
2096 CEFBS_None, // G_TRUNC_USAT_U
2097 CEFBS_None, // G_CONSTANT
2098 CEFBS_None, // G_FCONSTANT
2099 CEFBS_None, // G_VASTART
2100 CEFBS_None, // G_VAARG
2101 CEFBS_None, // G_SEXT
2102 CEFBS_None, // G_SEXT_INREG
2103 CEFBS_None, // G_ZEXT
2104 CEFBS_None, // G_SHL
2105 CEFBS_None, // G_LSHR
2106 CEFBS_None, // G_ASHR
2107 CEFBS_None, // G_FSHL
2108 CEFBS_None, // G_FSHR
2109 CEFBS_None, // G_ROTR
2110 CEFBS_None, // G_ROTL
2111 CEFBS_None, // G_ICMP
2112 CEFBS_None, // G_FCMP
2113 CEFBS_None, // G_SCMP
2114 CEFBS_None, // G_UCMP
2115 CEFBS_None, // G_SELECT
2116 CEFBS_None, // G_UADDO
2117 CEFBS_None, // G_UADDE
2118 CEFBS_None, // G_USUBO
2119 CEFBS_None, // G_USUBE
2120 CEFBS_None, // G_SADDO
2121 CEFBS_None, // G_SADDE
2122 CEFBS_None, // G_SSUBO
2123 CEFBS_None, // G_SSUBE
2124 CEFBS_None, // G_UMULO
2125 CEFBS_None, // G_SMULO
2126 CEFBS_None, // G_UMULH
2127 CEFBS_None, // G_SMULH
2128 CEFBS_None, // G_UADDSAT
2129 CEFBS_None, // G_SADDSAT
2130 CEFBS_None, // G_USUBSAT
2131 CEFBS_None, // G_SSUBSAT
2132 CEFBS_None, // G_USHLSAT
2133 CEFBS_None, // G_SSHLSAT
2134 CEFBS_None, // G_SMULFIX
2135 CEFBS_None, // G_UMULFIX
2136 CEFBS_None, // G_SMULFIXSAT
2137 CEFBS_None, // G_UMULFIXSAT
2138 CEFBS_None, // G_SDIVFIX
2139 CEFBS_None, // G_UDIVFIX
2140 CEFBS_None, // G_SDIVFIXSAT
2141 CEFBS_None, // G_UDIVFIXSAT
2142 CEFBS_None, // G_FADD
2143 CEFBS_None, // G_FSUB
2144 CEFBS_None, // G_FMUL
2145 CEFBS_None, // G_FMA
2146 CEFBS_None, // G_FMAD
2147 CEFBS_None, // G_FDIV
2148 CEFBS_None, // G_FREM
2149 CEFBS_None, // G_FMODF
2150 CEFBS_None, // G_FPOW
2151 CEFBS_None, // G_FPOWI
2152 CEFBS_None, // G_FEXP
2153 CEFBS_None, // G_FEXP2
2154 CEFBS_None, // G_FEXP10
2155 CEFBS_None, // G_FLOG
2156 CEFBS_None, // G_FLOG2
2157 CEFBS_None, // G_FLOG10
2158 CEFBS_None, // G_FLDEXP
2159 CEFBS_None, // G_FFREXP
2160 CEFBS_None, // G_FNEG
2161 CEFBS_None, // G_FPEXT
2162 CEFBS_None, // G_FPTRUNC
2163 CEFBS_None, // G_FPTOSI
2164 CEFBS_None, // G_FPTOUI
2165 CEFBS_None, // G_SITOFP
2166 CEFBS_None, // G_UITOFP
2167 CEFBS_None, // G_FPTOSI_SAT
2168 CEFBS_None, // G_FPTOUI_SAT
2169 CEFBS_None, // G_FABS
2170 CEFBS_None, // G_FCOPYSIGN
2171 CEFBS_None, // G_IS_FPCLASS
2172 CEFBS_None, // G_FCANONICALIZE
2173 CEFBS_None, // G_FMINNUM
2174 CEFBS_None, // G_FMAXNUM
2175 CEFBS_None, // G_FMINNUM_IEEE
2176 CEFBS_None, // G_FMAXNUM_IEEE
2177 CEFBS_None, // G_FMINIMUM
2178 CEFBS_None, // G_FMAXIMUM
2179 CEFBS_None, // G_FMINIMUMNUM
2180 CEFBS_None, // G_FMAXIMUMNUM
2181 CEFBS_None, // G_GET_FPENV
2182 CEFBS_None, // G_SET_FPENV
2183 CEFBS_None, // G_RESET_FPENV
2184 CEFBS_None, // G_GET_FPMODE
2185 CEFBS_None, // G_SET_FPMODE
2186 CEFBS_None, // G_RESET_FPMODE
2187 CEFBS_None, // G_GET_ROUNDING
2188 CEFBS_None, // G_SET_ROUNDING
2189 CEFBS_None, // G_PTR_ADD
2190 CEFBS_None, // G_PTRMASK
2191 CEFBS_None, // G_SMIN
2192 CEFBS_None, // G_SMAX
2193 CEFBS_None, // G_UMIN
2194 CEFBS_None, // G_UMAX
2195 CEFBS_None, // G_ABS
2196 CEFBS_None, // G_LROUND
2197 CEFBS_None, // G_LLROUND
2198 CEFBS_None, // G_BR
2199 CEFBS_None, // G_BRJT
2200 CEFBS_None, // G_VSCALE
2201 CEFBS_None, // G_INSERT_SUBVECTOR
2202 CEFBS_None, // G_EXTRACT_SUBVECTOR
2203 CEFBS_None, // G_INSERT_VECTOR_ELT
2204 CEFBS_None, // G_EXTRACT_VECTOR_ELT
2205 CEFBS_None, // G_SHUFFLE_VECTOR
2206 CEFBS_None, // G_SPLAT_VECTOR
2207 CEFBS_None, // G_STEP_VECTOR
2208 CEFBS_None, // G_VECTOR_COMPRESS
2209 CEFBS_None, // G_CTTZ
2210 CEFBS_None, // G_CTTZ_ZERO_POISON
2211 CEFBS_None, // G_CTLZ
2212 CEFBS_None, // G_CTLZ_ZERO_POISON
2213 CEFBS_None, // G_CTLS
2214 CEFBS_None, // G_CTPOP
2215 CEFBS_None, // G_BSWAP
2216 CEFBS_None, // G_BITREVERSE
2217 CEFBS_None, // G_CLMUL
2218 CEFBS_None, // G_CLMULH
2219 CEFBS_None, // G_CLMULR
2220 CEFBS_None, // G_FCEIL
2221 CEFBS_None, // G_FCOS
2222 CEFBS_None, // G_FSIN
2223 CEFBS_None, // G_FSINCOS
2224 CEFBS_None, // G_FTAN
2225 CEFBS_None, // G_FACOS
2226 CEFBS_None, // G_FASIN
2227 CEFBS_None, // G_FATAN
2228 CEFBS_None, // G_FATAN2
2229 CEFBS_None, // G_FCOSH
2230 CEFBS_None, // G_FSINH
2231 CEFBS_None, // G_FTANH
2232 CEFBS_None, // G_FSQRT
2233 CEFBS_None, // G_FFLOOR
2234 CEFBS_None, // G_FRINT
2235 CEFBS_None, // G_FNEARBYINT
2236 CEFBS_None, // G_ADDRSPACE_CAST
2237 CEFBS_None, // G_BLOCK_ADDR
2238 CEFBS_None, // G_JUMP_TABLE
2239 CEFBS_None, // G_DYN_STACKALLOC
2240 CEFBS_None, // G_STACKSAVE
2241 CEFBS_None, // G_STACKRESTORE
2242 CEFBS_None, // G_STRICT_FADD
2243 CEFBS_None, // G_STRICT_FSUB
2244 CEFBS_None, // G_STRICT_FMUL
2245 CEFBS_None, // G_STRICT_FDIV
2246 CEFBS_None, // G_STRICT_FREM
2247 CEFBS_None, // G_STRICT_FMA
2248 CEFBS_None, // G_STRICT_FSQRT
2249 CEFBS_None, // G_STRICT_FLDEXP
2250 CEFBS_None, // G_STRICT_FCMP
2251 CEFBS_None, // G_STRICT_FCMPS
2252 CEFBS_None, // G_READ_REGISTER
2253 CEFBS_None, // G_WRITE_REGISTER
2254 CEFBS_None, // G_MEMCPY
2255 CEFBS_None, // G_MEMCPY_INLINE
2256 CEFBS_None, // G_MEMMOVE
2257 CEFBS_None, // G_MEMSET
2258 CEFBS_None, // G_BZERO
2259 CEFBS_None, // G_MEMSET_INLINE
2260 CEFBS_None, // G_TRAP
2261 CEFBS_None, // G_DEBUGTRAP
2262 CEFBS_None, // G_UBSANTRAP
2263 CEFBS_None, // G_VECREDUCE_SEQ_FADD
2264 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
2265 CEFBS_None, // G_VECREDUCE_FADD
2266 CEFBS_None, // G_VECREDUCE_FMUL
2267 CEFBS_None, // G_VECREDUCE_FMAX
2268 CEFBS_None, // G_VECREDUCE_FMIN
2269 CEFBS_None, // G_VECREDUCE_FMAXIMUM
2270 CEFBS_None, // G_VECREDUCE_FMINIMUM
2271 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
2272 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
2273 CEFBS_None, // G_VECREDUCE_ADD
2274 CEFBS_None, // G_VECREDUCE_MUL
2275 CEFBS_None, // G_VECREDUCE_AND
2276 CEFBS_None, // G_VECREDUCE_OR
2277 CEFBS_None, // G_VECREDUCE_XOR
2278 CEFBS_None, // G_VECREDUCE_SMAX
2279 CEFBS_None, // G_VECREDUCE_SMIN
2280 CEFBS_None, // G_VECREDUCE_UMAX
2281 CEFBS_None, // G_VECREDUCE_UMIN
2282 CEFBS_None, // G_SBFX
2283 CEFBS_None, // G_UBFX
2284 CEFBS_None, // ADJCALLSTACKDOWN
2285 CEFBS_None, // ADJCALLSTACKUP
2286 CEFBS_None, // FI_ri
2287 CEFBS_None, // LDIMM64
2288 CEFBS_None, // LOAD_STACK_ARG_PSEUDO
2289 CEFBS_None, // MEMCPY
2290 CEFBS_None, // STORE_STACK_ARG_IMM_PSEUDO
2291 CEFBS_None, // STORE_STACK_ARG_PSEUDO
2292 CEFBS_None, // Select
2293 CEFBS_None, // Select_32
2294 CEFBS_None, // Select_32_64
2295 CEFBS_None, // Select_64_32
2296 CEFBS_None, // Select_Ri
2297 CEFBS_None, // Select_Ri_32
2298 CEFBS_None, // Select_Ri_32_64
2299 CEFBS_None, // Select_Ri_64_32
2300 CEFBS_None, // ADDR_SPACE_CAST
2301 CEFBS_None, // ADD_ri
2302 CEFBS_None, // ADD_ri_32
2303 CEFBS_None, // ADD_rr
2304 CEFBS_None, // ADD_rr_32
2305 CEFBS_None, // AND_ri
2306 CEFBS_None, // AND_ri_32
2307 CEFBS_None, // AND_rr
2308 CEFBS_None, // AND_rr_32
2309 CEFBS_None, // BE16
2310 CEFBS_None, // BE32
2311 CEFBS_None, // BE64
2312 CEFBS_None, // BSWAP16
2313 CEFBS_None, // BSWAP32
2314 CEFBS_None, // BSWAP64
2315 CEFBS_None, // CMPXCHGD
2316 CEFBS_None, // CMPXCHGW32
2317 CEFBS_None, // CORE_LD32
2318 CEFBS_None, // CORE_LD64
2319 CEFBS_None, // CORE_SHIFT
2320 CEFBS_None, // CORE_ST
2321 CEFBS_None, // DIV_ri
2322 CEFBS_None, // DIV_ri_32
2323 CEFBS_None, // DIV_rr
2324 CEFBS_None, // DIV_rr_32
2325 CEFBS_None, // JAL
2326 CEFBS_None, // JALX
2327 CEFBS_None, // JCOND
2328 CEFBS_None, // JEQ_ri
2329 CEFBS_None, // JEQ_ri_32
2330 CEFBS_None, // JEQ_rr
2331 CEFBS_None, // JEQ_rr_32
2332 CEFBS_None, // JMP
2333 CEFBS_None, // JMPL
2334 CEFBS_None, // JNE_ri
2335 CEFBS_None, // JNE_ri_32
2336 CEFBS_None, // JNE_rr
2337 CEFBS_None, // JNE_rr_32
2338 CEFBS_None, // JSET_ri
2339 CEFBS_None, // JSET_ri_32
2340 CEFBS_None, // JSET_rr
2341 CEFBS_None, // JSET_rr_32
2342 CEFBS_None, // JSGE_ri
2343 CEFBS_None, // JSGE_ri_32
2344 CEFBS_None, // JSGE_rr
2345 CEFBS_None, // JSGE_rr_32
2346 CEFBS_None, // JSGT_ri
2347 CEFBS_None, // JSGT_ri_32
2348 CEFBS_None, // JSGT_rr
2349 CEFBS_None, // JSGT_rr_32
2350 CEFBS_None, // JSLE_ri
2351 CEFBS_None, // JSLE_ri_32
2352 CEFBS_None, // JSLE_rr
2353 CEFBS_None, // JSLE_rr_32
2354 CEFBS_None, // JSLT_ri
2355 CEFBS_None, // JSLT_ri_32
2356 CEFBS_None, // JSLT_rr
2357 CEFBS_None, // JSLT_rr_32
2358 CEFBS_None, // JUGE_ri
2359 CEFBS_None, // JUGE_ri_32
2360 CEFBS_None, // JUGE_rr
2361 CEFBS_None, // JUGE_rr_32
2362 CEFBS_None, // JUGT_ri
2363 CEFBS_None, // JUGT_ri_32
2364 CEFBS_None, // JUGT_rr
2365 CEFBS_None, // JUGT_rr_32
2366 CEFBS_None, // JULE_ri
2367 CEFBS_None, // JULE_ri_32
2368 CEFBS_None, // JULE_rr
2369 CEFBS_None, // JULE_rr_32
2370 CEFBS_None, // JULT_ri
2371 CEFBS_None, // JULT_ri_32
2372 CEFBS_None, // JULT_rr
2373 CEFBS_None, // JULT_rr_32
2374 CEFBS_None, // JX
2375 CEFBS_None, // LDB
2376 CEFBS_None, // LDB32
2377 CEFBS_None, // LDBACQ32
2378 CEFBS_None, // LDBSX
2379 CEFBS_None, // LDD
2380 CEFBS_None, // LDDACQ
2381 CEFBS_None, // LDH
2382 CEFBS_None, // LDH32
2383 CEFBS_None, // LDHACQ32
2384 CEFBS_None, // LDHSX
2385 CEFBS_None, // LDW
2386 CEFBS_None, // LDW32
2387 CEFBS_None, // LDWACQ32
2388 CEFBS_None, // LDWSX
2389 CEFBS_None, // LD_ABS_B
2390 CEFBS_None, // LD_ABS_H
2391 CEFBS_None, // LD_ABS_W
2392 CEFBS_None, // LD_IND_B
2393 CEFBS_None, // LD_IND_H
2394 CEFBS_None, // LD_IND_W
2395 CEFBS_None, // LD_imm64
2396 CEFBS_None, // LD_pseudo
2397 CEFBS_None, // LE16
2398 CEFBS_None, // LE32
2399 CEFBS_None, // LE64
2400 CEFBS_None, // MOD_ri
2401 CEFBS_None, // MOD_ri_32
2402 CEFBS_None, // MOD_rr
2403 CEFBS_None, // MOD_rr_32
2404 CEFBS_None, // MOVSX_rr_16
2405 CEFBS_None, // MOVSX_rr_32
2406 CEFBS_None, // MOVSX_rr_32_16
2407 CEFBS_None, // MOVSX_rr_32_8
2408 CEFBS_None, // MOVSX_rr_8
2409 CEFBS_None, // MOV_32_64
2410 CEFBS_None, // MOV_ri
2411 CEFBS_None, // MOV_ri_32
2412 CEFBS_None, // MOV_rr
2413 CEFBS_None, // MOV_rr_32
2414 CEFBS_None, // MUL_ri
2415 CEFBS_None, // MUL_ri_32
2416 CEFBS_None, // MUL_rr
2417 CEFBS_None, // MUL_rr_32
2418 CEFBS_None, // NEG_32
2419 CEFBS_None, // NEG_64
2420 CEFBS_None, // NOP
2421 CEFBS_None, // OR_ri
2422 CEFBS_None, // OR_ri_32
2423 CEFBS_None, // OR_rr
2424 CEFBS_None, // OR_rr_32
2425 CEFBS_None, // RET
2426 CEFBS_None, // SDIV_ri
2427 CEFBS_None, // SDIV_ri_32
2428 CEFBS_None, // SDIV_rr
2429 CEFBS_None, // SDIV_rr_32
2430 CEFBS_None, // SLL_ri
2431 CEFBS_None, // SLL_ri_32
2432 CEFBS_None, // SLL_rr
2433 CEFBS_None, // SLL_rr_32
2434 CEFBS_None, // SMOD_ri
2435 CEFBS_None, // SMOD_ri_32
2436 CEFBS_None, // SMOD_rr
2437 CEFBS_None, // SMOD_rr_32
2438 CEFBS_None, // SRA_ri
2439 CEFBS_None, // SRA_ri_32
2440 CEFBS_None, // SRA_rr
2441 CEFBS_None, // SRA_rr_32
2442 CEFBS_None, // SRL_ri
2443 CEFBS_None, // SRL_ri_32
2444 CEFBS_None, // SRL_rr
2445 CEFBS_None, // SRL_rr_32
2446 CEFBS_None, // STB
2447 CEFBS_None, // STB32
2448 CEFBS_None, // STBREL32
2449 CEFBS_None, // STB_imm
2450 CEFBS_None, // STD
2451 CEFBS_None, // STDREL
2452 CEFBS_None, // STD_imm
2453 CEFBS_None, // STH
2454 CEFBS_None, // STH32
2455 CEFBS_None, // STHREL32
2456 CEFBS_None, // STH_imm
2457 CEFBS_None, // STW
2458 CEFBS_None, // STW32
2459 CEFBS_None, // STWREL32
2460 CEFBS_None, // STW_imm
2461 CEFBS_None, // SUB_ri
2462 CEFBS_None, // SUB_ri_32
2463 CEFBS_None, // SUB_rr
2464 CEFBS_None, // SUB_rr_32
2465 CEFBS_None, // XADDD
2466 CEFBS_None, // XADDW
2467 CEFBS_None, // XADDW32
2468 CEFBS_None, // XANDD
2469 CEFBS_None, // XANDW32
2470 CEFBS_None, // XCHGD
2471 CEFBS_None, // XCHGW32
2472 CEFBS_None, // XFADDD
2473 CEFBS_None, // XFADDW32
2474 CEFBS_None, // XFANDD
2475 CEFBS_None, // XFANDW32
2476 CEFBS_None, // XFORD
2477 CEFBS_None, // XFORW32
2478 CEFBS_None, // XFXORD
2479 CEFBS_None, // XFXORW32
2480 CEFBS_None, // XORD
2481 CEFBS_None, // XORW32
2482 CEFBS_None, // XOR_ri
2483 CEFBS_None, // XOR_ri_32
2484 CEFBS_None, // XOR_rr
2485 CEFBS_None, // XOR_rr_32
2486 CEFBS_None, // XXORD
2487 CEFBS_None, // XXORW32
2488 };
2489
2490 assert(Opcode < 539);
2491 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
2492}
2493
2494
2495} // namespace llvm::BPF_MC
2496
2497#endif // GET_COMPUTE_FEATURES
2498
2499#ifdef GET_AVAILABLE_OPCODE_CHECKER
2500#undef GET_AVAILABLE_OPCODE_CHECKER
2501
2502namespace llvm::BPF_MC {
2503
2504bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
2505 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2506 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2507 FeatureBitset MissingFeatures =
2508 (AvailableFeatures & RequiredFeatures) ^
2509 RequiredFeatures;
2510 return !MissingFeatures.any();
2511}
2512
2513} // namespace llvm::BPF_MC
2514
2515#endif // GET_AVAILABLE_OPCODE_CHECKER
2516
2517#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
2518#undef ENABLE_INSTR_PREDICATE_VERIFIER
2519
2520#include <sstream>
2521
2522namespace llvm::BPF_MC {
2523
2524#ifndef NDEBUG
2525static const char *SubtargetFeatureNames[] = {
2526 nullptr
2527};
2528
2529#endif // NDEBUG
2530
2531void verifyInstructionPredicates(
2532 unsigned Opcode, const FeatureBitset &Features) {
2533#ifndef NDEBUG
2534 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
2535 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
2536 FeatureBitset MissingFeatures =
2537 (AvailableFeatures & RequiredFeatures) ^
2538 RequiredFeatures;
2539 if (MissingFeatures.any()) {
2540 std::ostringstream Msg;
2541 Msg << "Attempting to emit " << &BPFInstrNameData[BPFInstrNameIndices[Opcode]]
2542 << " instruction but the ";
2543 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
2544 if (MissingFeatures.test(i))
2545 Msg << SubtargetFeatureNames[i] << " ";
2546 Msg << "predicate(s) are not met";
2547 report_fatal_error(Msg.str().c_str());
2548 }
2549#endif // NDEBUG
2550}
2551
2552} // namespace llvm::BPF_MC
2553
2554#endif // ENABLE_INSTR_PREDICATE_VERIFIER
2555
2556