1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t BPFRegDiffLists[] = {
12 /* 0 */ -12, 0,
13 /* 2 */ 12, 0,
14};
15
16extern const LaneBitmask BPFLaneMaskLists[] = {
17 /* 0 */ LaneBitmask(0x0000000000000001),
18 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
19};
20
21extern const uint16_t BPFSubRegIdxLists[] = {
22 /* 0 */ 1,
23};
24
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30extern const char BPFRegStrings[] = {
31 /* 0 */ "R10\000"
32 /* 4 */ "W10\000"
33 /* 8 */ "R0\000"
34 /* 11 */ "W0\000"
35 /* 14 */ "R11\000"
36 /* 18 */ "W11\000"
37 /* 22 */ "R1\000"
38 /* 25 */ "W1\000"
39 /* 28 */ "R2\000"
40 /* 31 */ "W2\000"
41 /* 34 */ "R3\000"
42 /* 37 */ "W3\000"
43 /* 40 */ "R4\000"
44 /* 43 */ "W4\000"
45 /* 46 */ "R5\000"
46 /* 49 */ "W5\000"
47 /* 52 */ "R6\000"
48 /* 55 */ "W6\000"
49 /* 58 */ "R7\000"
50 /* 61 */ "W7\000"
51 /* 64 */ "R8\000"
52 /* 67 */ "W8\000"
53 /* 70 */ "R9\000"
54 /* 73 */ "W9\000"
55};
56#ifdef __GNUC__
57#pragma GCC diagnostic pop
58#endif
59
60extern const MCRegisterDesc BPFRegDesc[] = { // Descriptors
61 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
62 { .Name: 8, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4096, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
63 { .Name: 22, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4097, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
64 { .Name: 28, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4098, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
65 { .Name: 34, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4099, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
66 { .Name: 40, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4100, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
67 { .Name: 46, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4101, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
68 { .Name: 52, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4102, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
69 { .Name: 58, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4103, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
70 { .Name: 64, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4104, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
71 { .Name: 70, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4105, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
72 { .Name: 0, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4106, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
73 { .Name: 14, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4107, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
74 { .Name: 11, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4096, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
75 { .Name: 25, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4097, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
76 { .Name: 31, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4098, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
77 { .Name: 37, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4099, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
78 { .Name: 43, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4100, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
79 { .Name: 49, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4101, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
80 { .Name: 55, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4102, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
81 { .Name: 61, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4103, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
82 { .Name: 67, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4104, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
83 { .Name: 73, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4105, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
84 { .Name: 4, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4106, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
85 { .Name: 18, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4107, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
86};
87
88extern const MCPhysReg BPFRegUnitRoots[][2] = {
89 { BPF::W0 },
90 { BPF::W1 },
91 { BPF::W2 },
92 { BPF::W3 },
93 { BPF::W4 },
94 { BPF::W5 },
95 { BPF::W6 },
96 { BPF::W7 },
97 { BPF::W8 },
98 { BPF::W9 },
99 { BPF::W10 },
100 { BPF::W11 },
101};
102
103namespace { // Register classes...
104 // GPR32 Register Class...
105 const MCPhysReg GPR32[] = {
106 BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W0, BPF::W11, BPF::W10,
107 };
108
109 // GPR32 Bit set.
110 const uint8_t GPR32Bits[] = {
111 0x00, 0xe0, 0xff, 0x01,
112 };
113
114 // GPR Register Class...
115 const MCPhysReg GPR[] = {
116 BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R0, BPF::R11, BPF::R10,
117 };
118
119 // GPR Bit set.
120 const uint8_t GPRBits[] = {
121 0xfe, 0x1f,
122 };
123
124} // end anonymous namespace
125
126
127#ifdef __GNUC__
128#pragma GCC diagnostic push
129#pragma GCC diagnostic ignored "-Woverlength-strings"
130#endif
131extern const char BPFRegClassStrings[] = {
132 /* 0 */ "GPR32\000"
133 /* 6 */ "GPR\000"
134};
135#ifdef __GNUC__
136#pragma GCC diagnostic pop
137#endif
138
139extern const MCRegisterClass BPFMCRegisterClasses[] = {
140 { .RegsBegin: GPR32, .RegSet: GPR32Bits, .NameIdx: 0, .RegsSize: 12, .RegSetSize: sizeof(GPR32Bits), .ID: BPF::GPR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
141 { .RegsBegin: GPR, .RegSet: GPRBits, .NameIdx: 6, .RegsSize: 12, .RegSetSize: sizeof(GPRBits), .ID: BPF::GPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
142};
143
144// BPF Dwarf<->LLVM register mappings.
145extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[] = {
146 { .FromReg: 0U, .ToReg: BPF::W0 },
147 { .FromReg: 1U, .ToReg: BPF::W1 },
148 { .FromReg: 2U, .ToReg: BPF::W2 },
149 { .FromReg: 3U, .ToReg: BPF::W3 },
150 { .FromReg: 4U, .ToReg: BPF::W4 },
151 { .FromReg: 5U, .ToReg: BPF::W5 },
152 { .FromReg: 6U, .ToReg: BPF::W6 },
153 { .FromReg: 7U, .ToReg: BPF::W7 },
154 { .FromReg: 8U, .ToReg: BPF::W8 },
155 { .FromReg: 9U, .ToReg: BPF::W9 },
156 { .FromReg: 10U, .ToReg: BPF::W10 },
157 { .FromReg: 11U, .ToReg: BPF::W11 },
158};
159extern const unsigned BPFDwarfFlavour0Dwarf2LSize = std::size(BPFDwarfFlavour0Dwarf2L);
160
161extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[] = {
162 { .FromReg: 0U, .ToReg: BPF::W0 },
163 { .FromReg: 1U, .ToReg: BPF::W1 },
164 { .FromReg: 2U, .ToReg: BPF::W2 },
165 { .FromReg: 3U, .ToReg: BPF::W3 },
166 { .FromReg: 4U, .ToReg: BPF::W4 },
167 { .FromReg: 5U, .ToReg: BPF::W5 },
168 { .FromReg: 6U, .ToReg: BPF::W6 },
169 { .FromReg: 7U, .ToReg: BPF::W7 },
170 { .FromReg: 8U, .ToReg: BPF::W8 },
171 { .FromReg: 9U, .ToReg: BPF::W9 },
172 { .FromReg: 10U, .ToReg: BPF::W10 },
173 { .FromReg: 11U, .ToReg: BPF::W11 },
174};
175extern const unsigned BPFEHFlavour0Dwarf2LSize = std::size(BPFEHFlavour0Dwarf2L);
176
177extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[] = {
178 { .FromReg: BPF::R0, .ToReg: 0U },
179 { .FromReg: BPF::R1, .ToReg: 1U },
180 { .FromReg: BPF::R2, .ToReg: 2U },
181 { .FromReg: BPF::R3, .ToReg: 3U },
182 { .FromReg: BPF::R4, .ToReg: 4U },
183 { .FromReg: BPF::R5, .ToReg: 5U },
184 { .FromReg: BPF::R6, .ToReg: 6U },
185 { .FromReg: BPF::R7, .ToReg: 7U },
186 { .FromReg: BPF::R8, .ToReg: 8U },
187 { .FromReg: BPF::R9, .ToReg: 9U },
188 { .FromReg: BPF::R10, .ToReg: 10U },
189 { .FromReg: BPF::R11, .ToReg: 11U },
190 { .FromReg: BPF::W0, .ToReg: 0U },
191 { .FromReg: BPF::W1, .ToReg: 1U },
192 { .FromReg: BPF::W2, .ToReg: 2U },
193 { .FromReg: BPF::W3, .ToReg: 3U },
194 { .FromReg: BPF::W4, .ToReg: 4U },
195 { .FromReg: BPF::W5, .ToReg: 5U },
196 { .FromReg: BPF::W6, .ToReg: 6U },
197 { .FromReg: BPF::W7, .ToReg: 7U },
198 { .FromReg: BPF::W8, .ToReg: 8U },
199 { .FromReg: BPF::W9, .ToReg: 9U },
200 { .FromReg: BPF::W10, .ToReg: 10U },
201 { .FromReg: BPF::W11, .ToReg: 11U },
202};
203extern const unsigned BPFDwarfFlavour0L2DwarfSize = std::size(BPFDwarfFlavour0L2Dwarf);
204
205extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[] = {
206 { .FromReg: BPF::R0, .ToReg: 0U },
207 { .FromReg: BPF::R1, .ToReg: 1U },
208 { .FromReg: BPF::R2, .ToReg: 2U },
209 { .FromReg: BPF::R3, .ToReg: 3U },
210 { .FromReg: BPF::R4, .ToReg: 4U },
211 { .FromReg: BPF::R5, .ToReg: 5U },
212 { .FromReg: BPF::R6, .ToReg: 6U },
213 { .FromReg: BPF::R7, .ToReg: 7U },
214 { .FromReg: BPF::R8, .ToReg: 8U },
215 { .FromReg: BPF::R9, .ToReg: 9U },
216 { .FromReg: BPF::R10, .ToReg: 10U },
217 { .FromReg: BPF::R11, .ToReg: 11U },
218 { .FromReg: BPF::W0, .ToReg: 0U },
219 { .FromReg: BPF::W1, .ToReg: 1U },
220 { .FromReg: BPF::W2, .ToReg: 2U },
221 { .FromReg: BPF::W3, .ToReg: 3U },
222 { .FromReg: BPF::W4, .ToReg: 4U },
223 { .FromReg: BPF::W5, .ToReg: 5U },
224 { .FromReg: BPF::W6, .ToReg: 6U },
225 { .FromReg: BPF::W7, .ToReg: 7U },
226 { .FromReg: BPF::W8, .ToReg: 8U },
227 { .FromReg: BPF::W9, .ToReg: 9U },
228 { .FromReg: BPF::W10, .ToReg: 10U },
229 { .FromReg: BPF::W11, .ToReg: 11U },
230};
231extern const unsigned BPFEHFlavour0L2DwarfSize = std::size(BPFEHFlavour0L2Dwarf);
232
233extern const uint16_t BPFRegEncodingTable[] = {
234 0,
235 0,
236 1,
237 2,
238 3,
239 4,
240 5,
241 6,
242 7,
243 8,
244 9,
245 10,
246 11,
247 0,
248 1,
249 2,
250 3,
251 4,
252 5,
253 6,
254 7,
255 8,
256 9,
257 10,
258 11,
259};
260static inline void InitBPFMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
261 RI->InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC, C: BPFMCRegisterClasses, NC: 2, RURoots: BPFRegUnitRoots, NRU: 12, DL: BPFRegDiffLists, RUMS: BPFLaneMaskLists, Strings: BPFRegStrings, ClassStrings: BPFRegClassStrings, SubIndices: BPFSubRegIdxLists, NumIndices: 2,
262RET: BPFRegEncodingTable);
263
264 switch (DwarfFlavour) {
265 default:
266 llvm_unreachable("Unknown DWARF flavour");
267 case 0:
268 RI->mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
269 break;
270 }
271 switch (EHFlavour) {
272 default:
273 llvm_unreachable("Unknown DWARF flavour");
274 case 0:
275 RI->mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
276 break;
277 }
278 switch (DwarfFlavour) {
279 default:
280 llvm_unreachable("Unknown DWARF flavour");
281 case 0:
282 RI->mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
283 break;
284 }
285 switch (EHFlavour) {
286 default:
287 llvm_unreachable("Unknown DWARF flavour");
288 case 0:
289 RI->mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
290 break;
291 }
292}
293
294} // end namespace llvm
295
296