1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t BPFRegDiffLists[] = {
12 /* 0 */ -12, 0,
13 /* 2 */ 12, 0,
14};
15
16extern const LaneBitmask BPFLaneMaskLists[] = {
17 /* 0 */ LaneBitmask(0x0000000000000001),
18 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
19};
20
21extern const uint16_t BPFSubRegIdxLists[] = {
22 /* 0 */ 1,
23};
24
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30extern const char BPFRegStrings[] = {
31 /* 0 */ "R10\000"
32 /* 4 */ "W10\000"
33 /* 8 */ "R0\000"
34 /* 11 */ "W0\000"
35 /* 14 */ "R11\000"
36 /* 18 */ "W11\000"
37 /* 22 */ "R1\000"
38 /* 25 */ "W1\000"
39 /* 28 */ "R2\000"
40 /* 31 */ "W2\000"
41 /* 34 */ "R3\000"
42 /* 37 */ "W3\000"
43 /* 40 */ "R4\000"
44 /* 43 */ "W4\000"
45 /* 46 */ "R5\000"
46 /* 49 */ "W5\000"
47 /* 52 */ "R6\000"
48 /* 55 */ "W6\000"
49 /* 58 */ "R7\000"
50 /* 61 */ "W7\000"
51 /* 64 */ "R8\000"
52 /* 67 */ "W8\000"
53 /* 70 */ "R9\000"
54 /* 73 */ "W9\000"
55};
56#ifdef __GNUC__
57#pragma GCC diagnostic pop
58#endif
59
60extern const MCRegisterDesc BPFRegDesc[] = { // Descriptors
61 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
62 { .Name: 8, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4096, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
63 { .Name: 22, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4097, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
64 { .Name: 28, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4098, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
65 { .Name: 34, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4099, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
66 { .Name: 40, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4100, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
67 { .Name: 46, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4101, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
68 { .Name: 52, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4102, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
69 { .Name: 58, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4103, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
70 { .Name: 64, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4104, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
71 { .Name: 70, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4105, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
72 { .Name: 0, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4106, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
73 { .Name: 14, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4107, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
74 { .Name: 11, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4096, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
75 { .Name: 25, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4097, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
76 { .Name: 31, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4098, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
77 { .Name: 37, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4099, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
78 { .Name: 43, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4100, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
79 { .Name: 49, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4101, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
80 { .Name: 55, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4102, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
81 { .Name: 61, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4103, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
82 { .Name: 67, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4104, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
83 { .Name: 73, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4105, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
84 { .Name: 4, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4106, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
85 { .Name: 18, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4107, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
86};
87
88extern const MCPhysReg BPFRegUnitRoots[][2] = {
89 { BPF::W0 },
90 { BPF::W1 },
91 { BPF::W2 },
92 { BPF::W3 },
93 { BPF::W4 },
94 { BPF::W5 },
95 { BPF::W6 },
96 { BPF::W7 },
97 { BPF::W8 },
98 { BPF::W9 },
99 { BPF::W10 },
100 { BPF::W11 },
101};
102
103namespace {
104
105// Register classes...
106 // GPR32 Register Class...
107 const MCPhysReg GPR32[] = {
108 BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W0, BPF::W11, BPF::W10,
109 };
110
111 // GPR32 Bit set.
112 const uint8_t GPR32Bits[] = {
113 0x00, 0xe0, 0xff, 0x01,
114 };
115
116 // GPR Register Class...
117 const MCPhysReg GPR[] = {
118 BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R0, BPF::R11, BPF::R10,
119 };
120
121 // GPR Bit set.
122 const uint8_t GPRBits[] = {
123 0xfe, 0x1f,
124 };
125
126} // namespace
127
128#ifdef __GNUC__
129#pragma GCC diagnostic push
130#pragma GCC diagnostic ignored "-Woverlength-strings"
131#endif
132extern const char BPFRegClassStrings[] = {
133 /* 0 */ "GPR32\000"
134 /* 6 */ "GPR\000"
135};
136#ifdef __GNUC__
137#pragma GCC diagnostic pop
138#endif
139
140extern const MCRegisterClass BPFMCRegisterClasses[] = {
141 { .RegsBegin: GPR32, .RegSet: GPR32Bits, .NameIdx: 0, .RegsSize: 12, .RegSetSize: sizeof(GPR32Bits), .ID: BPF::GPR32RegClassID, .RegSizeInBits: 32, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
142 { .RegsBegin: GPR, .RegSet: GPRBits, .NameIdx: 6, .RegsSize: 12, .RegSetSize: sizeof(GPRBits), .ID: BPF::GPRRegClassID, .RegSizeInBits: 64, .CopyCost: 1, .Allocatable: true, .BaseClass: false },
143};
144
145// BPF Dwarf<->LLVM register mappings.
146extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[] = {
147 { .FromReg: 0U, .ToReg: BPF::W0 },
148 { .FromReg: 1U, .ToReg: BPF::W1 },
149 { .FromReg: 2U, .ToReg: BPF::W2 },
150 { .FromReg: 3U, .ToReg: BPF::W3 },
151 { .FromReg: 4U, .ToReg: BPF::W4 },
152 { .FromReg: 5U, .ToReg: BPF::W5 },
153 { .FromReg: 6U, .ToReg: BPF::W6 },
154 { .FromReg: 7U, .ToReg: BPF::W7 },
155 { .FromReg: 8U, .ToReg: BPF::W8 },
156 { .FromReg: 9U, .ToReg: BPF::W9 },
157 { .FromReg: 10U, .ToReg: BPF::W10 },
158 { .FromReg: 11U, .ToReg: BPF::W11 },
159};
160extern const unsigned BPFDwarfFlavour0Dwarf2LSize = std::size(BPFDwarfFlavour0Dwarf2L);
161
162extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[] = {
163 { .FromReg: 0U, .ToReg: BPF::W0 },
164 { .FromReg: 1U, .ToReg: BPF::W1 },
165 { .FromReg: 2U, .ToReg: BPF::W2 },
166 { .FromReg: 3U, .ToReg: BPF::W3 },
167 { .FromReg: 4U, .ToReg: BPF::W4 },
168 { .FromReg: 5U, .ToReg: BPF::W5 },
169 { .FromReg: 6U, .ToReg: BPF::W6 },
170 { .FromReg: 7U, .ToReg: BPF::W7 },
171 { .FromReg: 8U, .ToReg: BPF::W8 },
172 { .FromReg: 9U, .ToReg: BPF::W9 },
173 { .FromReg: 10U, .ToReg: BPF::W10 },
174 { .FromReg: 11U, .ToReg: BPF::W11 },
175};
176extern const unsigned BPFEHFlavour0Dwarf2LSize = std::size(BPFEHFlavour0Dwarf2L);
177
178extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[] = {
179 { .FromReg: BPF::R0, .ToReg: 0U },
180 { .FromReg: BPF::R1, .ToReg: 1U },
181 { .FromReg: BPF::R2, .ToReg: 2U },
182 { .FromReg: BPF::R3, .ToReg: 3U },
183 { .FromReg: BPF::R4, .ToReg: 4U },
184 { .FromReg: BPF::R5, .ToReg: 5U },
185 { .FromReg: BPF::R6, .ToReg: 6U },
186 { .FromReg: BPF::R7, .ToReg: 7U },
187 { .FromReg: BPF::R8, .ToReg: 8U },
188 { .FromReg: BPF::R9, .ToReg: 9U },
189 { .FromReg: BPF::R10, .ToReg: 10U },
190 { .FromReg: BPF::R11, .ToReg: 11U },
191 { .FromReg: BPF::W0, .ToReg: 0U },
192 { .FromReg: BPF::W1, .ToReg: 1U },
193 { .FromReg: BPF::W2, .ToReg: 2U },
194 { .FromReg: BPF::W3, .ToReg: 3U },
195 { .FromReg: BPF::W4, .ToReg: 4U },
196 { .FromReg: BPF::W5, .ToReg: 5U },
197 { .FromReg: BPF::W6, .ToReg: 6U },
198 { .FromReg: BPF::W7, .ToReg: 7U },
199 { .FromReg: BPF::W8, .ToReg: 8U },
200 { .FromReg: BPF::W9, .ToReg: 9U },
201 { .FromReg: BPF::W10, .ToReg: 10U },
202 { .FromReg: BPF::W11, .ToReg: 11U },
203};
204extern const unsigned BPFDwarfFlavour0L2DwarfSize = std::size(BPFDwarfFlavour0L2Dwarf);
205
206extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[] = {
207 { .FromReg: BPF::R0, .ToReg: 0U },
208 { .FromReg: BPF::R1, .ToReg: 1U },
209 { .FromReg: BPF::R2, .ToReg: 2U },
210 { .FromReg: BPF::R3, .ToReg: 3U },
211 { .FromReg: BPF::R4, .ToReg: 4U },
212 { .FromReg: BPF::R5, .ToReg: 5U },
213 { .FromReg: BPF::R6, .ToReg: 6U },
214 { .FromReg: BPF::R7, .ToReg: 7U },
215 { .FromReg: BPF::R8, .ToReg: 8U },
216 { .FromReg: BPF::R9, .ToReg: 9U },
217 { .FromReg: BPF::R10, .ToReg: 10U },
218 { .FromReg: BPF::R11, .ToReg: 11U },
219 { .FromReg: BPF::W0, .ToReg: 0U },
220 { .FromReg: BPF::W1, .ToReg: 1U },
221 { .FromReg: BPF::W2, .ToReg: 2U },
222 { .FromReg: BPF::W3, .ToReg: 3U },
223 { .FromReg: BPF::W4, .ToReg: 4U },
224 { .FromReg: BPF::W5, .ToReg: 5U },
225 { .FromReg: BPF::W6, .ToReg: 6U },
226 { .FromReg: BPF::W7, .ToReg: 7U },
227 { .FromReg: BPF::W8, .ToReg: 8U },
228 { .FromReg: BPF::W9, .ToReg: 9U },
229 { .FromReg: BPF::W10, .ToReg: 10U },
230 { .FromReg: BPF::W11, .ToReg: 11U },
231};
232extern const unsigned BPFEHFlavour0L2DwarfSize = std::size(BPFEHFlavour0L2Dwarf);
233
234extern const uint16_t BPFRegEncodingTable[] = {
235 0,
236 0,
237 1,
238 2,
239 3,
240 4,
241 5,
242 6,
243 7,
244 8,
245 9,
246 10,
247 11,
248 0,
249 1,
250 2,
251 3,
252 4,
253 5,
254 6,
255 7,
256 8,
257 9,
258 10,
259 11,
260};
261static inline void InitBPFMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
262 RI->InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC, C: BPFMCRegisterClasses, NC: 2, RURoots: BPFRegUnitRoots, NRU: 12, DL: BPFRegDiffLists, RUMS: BPFLaneMaskLists, Strings: BPFRegStrings, ClassStrings: BPFRegClassStrings, SubIndices: BPFSubRegIdxLists, NumIndices: 2,
263RET: BPFRegEncodingTable, RUI: nullptr);
264
265 switch (DwarfFlavour) {
266 default:
267 llvm_unreachable("Unknown DWARF flavour");
268 case 0:
269 RI->mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
270 break;
271 }
272 switch (EHFlavour) {
273 default:
274 llvm_unreachable("Unknown DWARF flavour");
275 case 0:
276 RI->mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
277 break;
278 }
279 switch (DwarfFlavour) {
280 default:
281 llvm_unreachable("Unknown DWARF flavour");
282 case 0:
283 RI->mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
284 break;
285 }
286 switch (EHFlavour) {
287 default:
288 llvm_unreachable("Unknown DWARF flavour");
289 case 0:
290 RI->mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
291 break;
292 }
293}
294
295
296} // namespace llvm
297