1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t BPFRegDiffLists[] = {
12 /* 0 */ -12, 0,
13 /* 2 */ 12, 0,
14};
15
16extern const LaneBitmask BPFLaneMaskLists[] = {
17 /* 0 */ LaneBitmask(0x0000000000000001),
18 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
19};
20
21extern const uint16_t BPFSubRegIdxLists[] = {
22 /* 0 */ 1,
23};
24
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30extern const char BPFRegStrings[] = {
31 /* 0 */ "R10\000"
32 /* 4 */ "W10\000"
33 /* 8 */ "R0\000"
34 /* 11 */ "W0\000"
35 /* 14 */ "R11\000"
36 /* 18 */ "W11\000"
37 /* 22 */ "R1\000"
38 /* 25 */ "W1\000"
39 /* 28 */ "R2\000"
40 /* 31 */ "W2\000"
41 /* 34 */ "R3\000"
42 /* 37 */ "W3\000"
43 /* 40 */ "R4\000"
44 /* 43 */ "W4\000"
45 /* 46 */ "R5\000"
46 /* 49 */ "W5\000"
47 /* 52 */ "R6\000"
48 /* 55 */ "W6\000"
49 /* 58 */ "R7\000"
50 /* 61 */ "W7\000"
51 /* 64 */ "R8\000"
52 /* 67 */ "W8\000"
53 /* 70 */ "R9\000"
54 /* 73 */ "W9\000"
55};
56#ifdef __GNUC__
57#pragma GCC diagnostic pop
58#endif
59
60extern const MCRegisterDesc BPFRegDesc[] = { // Descriptors
61 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
62 { .Name: 8, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4096, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
63 { .Name: 22, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4097, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
64 { .Name: 28, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4098, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
65 { .Name: 34, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4099, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
66 { .Name: 40, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4100, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
67 { .Name: 46, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4101, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
68 { .Name: 52, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4102, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
69 { .Name: 58, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4103, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
70 { .Name: 64, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4104, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
71 { .Name: 70, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4105, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
72 { .Name: 0, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4106, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
73 { .Name: 14, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4107, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
74 { .Name: 11, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4096, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
75 { .Name: 25, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4097, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
76 { .Name: 31, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4098, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
77 { .Name: 37, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4099, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
78 { .Name: 43, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4100, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
79 { .Name: 49, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4101, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
80 { .Name: 55, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4102, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
81 { .Name: 61, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4103, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
82 { .Name: 67, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4104, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
83 { .Name: 73, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4105, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
84 { .Name: 4, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4106, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
85 { .Name: 18, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4107, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
86};
87
88extern const MCPhysReg BPFRegUnitRoots[][2] = {
89 { BPF::W0 },
90 { BPF::W1 },
91 { BPF::W2 },
92 { BPF::W3 },
93 { BPF::W4 },
94 { BPF::W5 },
95 { BPF::W6 },
96 { BPF::W7 },
97 { BPF::W8 },
98 { BPF::W9 },
99 { BPF::W10 },
100 { BPF::W11 },
101};
102
103// Register classes...
104
105#ifdef __GNUC__
106#pragma GCC diagnostic push
107#pragma GCC diagnostic ignored "-Woverlength-strings"
108#endif
109extern const char BPFRegClassStrings[] = {
110 /* 0 */ "GPR32\000"
111 /* 6 */ "GPR\000"
112};
113#ifdef __GNUC__
114#pragma GCC diagnostic pop
115#endif
116
117using BPFRegisterClassStorage = MCRegisterClassStorage<2, 24, 6, 3, 2, 0>;
118extern const MCRegisterClassStorage<2, 24, 6, 3, 2, 0> BPFMCRegisterClassStorage = {
119 .Classes: {
120 {
121 offsetof(BPFRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
122 offsetof(BPFRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
123 .NameIdx: 0,
124 .RegSizeInBits: 32,
125 .RegsSize: 12,
126 .RegSetSize: 4,
127 .ID: BPF::GPR32RegClassID,
128 .CopyCost: 1, /* CopyCost */
129 .Allocatable: true, /* Allocatable */
130 .BaseClass: false,
131 offsetof(BPFRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
132 offsetof(BPFRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
133 .LaneMask: LaneBitmask(0x0000000000000001),
134 .AllocationPriority: 0,
135 .GlobalPriority: false,
136 .TSFlags: 0x00, /* TSFlags */
137 .SpillStackID: 0, /* SpillStackID */
138 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
139 .CoveredBySubRegs: false, /* CoveredBySubRegs */
140 offsetof(BPFRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
141 .SuperClassesSize: 0
142 },
143 {
144 offsetof(BPFRegisterClassStorage, Regs[12]) - 1 * sizeof(MCRegisterClass),
145 offsetof(BPFRegisterClassStorage, BitSets[4]) - 1 * sizeof(MCRegisterClass),
146 .NameIdx: 6,
147 .RegSizeInBits: 64,
148 .RegsSize: 12,
149 .RegSetSize: 2,
150 .ID: BPF::GPRRegClassID,
151 .CopyCost: 1, /* CopyCost */
152 .Allocatable: true, /* Allocatable */
153 .BaseClass: false,
154 offsetof(BPFRegisterClassStorage, SubClassMasks[2]) - 1 * sizeof(MCRegisterClass),
155 offsetof(BPFRegisterClassStorage, SuperRegIdxSeqs[1]) - 1 * sizeof(MCRegisterClass),
156 .LaneMask: LaneBitmask(0x0000000000000001),
157 .AllocationPriority: 0,
158 .GlobalPriority: false,
159 .TSFlags: 0x00, /* TSFlags */
160 .SpillStackID: 0, /* SpillStackID */
161 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
162 .CoveredBySubRegs: false, /* CoveredBySubRegs */
163 offsetof(BPFRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
164 .SuperClassesSize: 0
165 },
166 },
167 .Regs: {
168 /* 0 */ BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W0, BPF::W11, BPF::W10,
169 /* 12 */ BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R0, BPF::R11, BPF::R10,
170 },
171 .BitSets: {
172 /* 0 */ 0x00, 0xe0, 0xff, 0x01,
173 /* 4 */ 0xfe, 0x1f,
174 },
175 .SubClassMasks: {
176 // 0 GPR32
177 0x00000001,
178 0x00000002, // sub_32
179 // 2 GPR
180 0x00000002,
181 },
182 .SuperRegIdxSeqs: {
183 /* 0 */ 1, 0,
184 },
185 .SuperClasses: {
186 /* 0 GPR32 */
187 /* 0 GPR */
188 }
189};
190
191const MCRegisterClass &getBPFMCRegisterClass(unsigned RC) {
192 return BPFMCRegisterClassStorage.Classes[RC];
193}
194
195// BPF Dwarf<->LLVM register mappings.
196extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[] = {
197 { .FromReg: 0U, .ToReg: BPF::W0 },
198 { .FromReg: 1U, .ToReg: BPF::W1 },
199 { .FromReg: 2U, .ToReg: BPF::W2 },
200 { .FromReg: 3U, .ToReg: BPF::W3 },
201 { .FromReg: 4U, .ToReg: BPF::W4 },
202 { .FromReg: 5U, .ToReg: BPF::W5 },
203 { .FromReg: 6U, .ToReg: BPF::W6 },
204 { .FromReg: 7U, .ToReg: BPF::W7 },
205 { .FromReg: 8U, .ToReg: BPF::W8 },
206 { .FromReg: 9U, .ToReg: BPF::W9 },
207 { .FromReg: 10U, .ToReg: BPF::W10 },
208 { .FromReg: 11U, .ToReg: BPF::W11 },
209};
210extern const unsigned BPFDwarfFlavour0Dwarf2LSize = std::size(BPFDwarfFlavour0Dwarf2L);
211
212extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[] = {
213 { .FromReg: 0U, .ToReg: BPF::W0 },
214 { .FromReg: 1U, .ToReg: BPF::W1 },
215 { .FromReg: 2U, .ToReg: BPF::W2 },
216 { .FromReg: 3U, .ToReg: BPF::W3 },
217 { .FromReg: 4U, .ToReg: BPF::W4 },
218 { .FromReg: 5U, .ToReg: BPF::W5 },
219 { .FromReg: 6U, .ToReg: BPF::W6 },
220 { .FromReg: 7U, .ToReg: BPF::W7 },
221 { .FromReg: 8U, .ToReg: BPF::W8 },
222 { .FromReg: 9U, .ToReg: BPF::W9 },
223 { .FromReg: 10U, .ToReg: BPF::W10 },
224 { .FromReg: 11U, .ToReg: BPF::W11 },
225};
226extern const unsigned BPFEHFlavour0Dwarf2LSize = std::size(BPFEHFlavour0Dwarf2L);
227
228extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[] = {
229 { .FromReg: BPF::R0, .ToReg: 0U },
230 { .FromReg: BPF::R1, .ToReg: 1U },
231 { .FromReg: BPF::R2, .ToReg: 2U },
232 { .FromReg: BPF::R3, .ToReg: 3U },
233 { .FromReg: BPF::R4, .ToReg: 4U },
234 { .FromReg: BPF::R5, .ToReg: 5U },
235 { .FromReg: BPF::R6, .ToReg: 6U },
236 { .FromReg: BPF::R7, .ToReg: 7U },
237 { .FromReg: BPF::R8, .ToReg: 8U },
238 { .FromReg: BPF::R9, .ToReg: 9U },
239 { .FromReg: BPF::R10, .ToReg: 10U },
240 { .FromReg: BPF::R11, .ToReg: 11U },
241 { .FromReg: BPF::W0, .ToReg: 0U },
242 { .FromReg: BPF::W1, .ToReg: 1U },
243 { .FromReg: BPF::W2, .ToReg: 2U },
244 { .FromReg: BPF::W3, .ToReg: 3U },
245 { .FromReg: BPF::W4, .ToReg: 4U },
246 { .FromReg: BPF::W5, .ToReg: 5U },
247 { .FromReg: BPF::W6, .ToReg: 6U },
248 { .FromReg: BPF::W7, .ToReg: 7U },
249 { .FromReg: BPF::W8, .ToReg: 8U },
250 { .FromReg: BPF::W9, .ToReg: 9U },
251 { .FromReg: BPF::W10, .ToReg: 10U },
252 { .FromReg: BPF::W11, .ToReg: 11U },
253};
254extern const unsigned BPFDwarfFlavour0L2DwarfSize = std::size(BPFDwarfFlavour0L2Dwarf);
255
256extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[] = {
257 { .FromReg: BPF::R0, .ToReg: 0U },
258 { .FromReg: BPF::R1, .ToReg: 1U },
259 { .FromReg: BPF::R2, .ToReg: 2U },
260 { .FromReg: BPF::R3, .ToReg: 3U },
261 { .FromReg: BPF::R4, .ToReg: 4U },
262 { .FromReg: BPF::R5, .ToReg: 5U },
263 { .FromReg: BPF::R6, .ToReg: 6U },
264 { .FromReg: BPF::R7, .ToReg: 7U },
265 { .FromReg: BPF::R8, .ToReg: 8U },
266 { .FromReg: BPF::R9, .ToReg: 9U },
267 { .FromReg: BPF::R10, .ToReg: 10U },
268 { .FromReg: BPF::R11, .ToReg: 11U },
269 { .FromReg: BPF::W0, .ToReg: 0U },
270 { .FromReg: BPF::W1, .ToReg: 1U },
271 { .FromReg: BPF::W2, .ToReg: 2U },
272 { .FromReg: BPF::W3, .ToReg: 3U },
273 { .FromReg: BPF::W4, .ToReg: 4U },
274 { .FromReg: BPF::W5, .ToReg: 5U },
275 { .FromReg: BPF::W6, .ToReg: 6U },
276 { .FromReg: BPF::W7, .ToReg: 7U },
277 { .FromReg: BPF::W8, .ToReg: 8U },
278 { .FromReg: BPF::W9, .ToReg: 9U },
279 { .FromReg: BPF::W10, .ToReg: 10U },
280 { .FromReg: BPF::W11, .ToReg: 11U },
281};
282extern const unsigned BPFEHFlavour0L2DwarfSize = std::size(BPFEHFlavour0L2Dwarf);
283
284extern const uint16_t BPFRegEncodingTable[] = {
285 0,
286 0,
287 1,
288 2,
289 3,
290 4,
291 5,
292 6,
293 7,
294 8,
295 9,
296 10,
297 11,
298 0,
299 1,
300 2,
301 3,
302 4,
303 5,
304 6,
305 7,
306 8,
307 9,
308 10,
309 11,
310};
311static inline void InitBPFMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
312 RI->InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC, C: BPFMCRegisterClassStorage.Classes, NC: 2, RURoots: BPFRegUnitRoots, NRU: 12, DL: BPFRegDiffLists, RUMS: BPFLaneMaskLists, Strings: BPFRegStrings, ClassStrings: BPFRegClassStrings, SubIndices: BPFSubRegIdxLists, NumIndices: 2,
313RET: BPFRegEncodingTable, RUI: nullptr);
314
315 switch (DwarfFlavour) {
316 default:
317 llvm_unreachable("Unknown DWARF flavour");
318 case 0:
319 RI->mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
320 break;
321 }
322 switch (EHFlavour) {
323 default:
324 llvm_unreachable("Unknown DWARF flavour");
325 case 0:
326 RI->mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
327 break;
328 }
329 switch (DwarfFlavour) {
330 default:
331 llvm_unreachable("Unknown DWARF flavour");
332 case 0:
333 RI->mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
334 break;
335 }
336 switch (EHFlavour) {
337 default:
338 llvm_unreachable("Unknown DWARF flavour");
339 case 0:
340 RI->mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
341 break;
342 }
343}
344
345
346} // namespace llvm
347