1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* MC Register Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const int16_t BPFRegDiffLists[] = {
12 /* 0 */ -12, 0,
13 /* 2 */ 12, 0,
14};
15
16extern const LaneBitmask BPFLaneMaskLists[] = {
17 /* 0 */ LaneBitmask(0x0000000000000001),
18 /* 1 */ LaneBitmask(0xFFFFFFFFFFFFFFFF),
19};
20
21extern const uint16_t BPFSubRegIdxLists[] = {
22 /* 0 */ 1,
23};
24
25
26#ifdef __GNUC__
27#pragma GCC diagnostic push
28#pragma GCC diagnostic ignored "-Woverlength-strings"
29#endif
30extern const char BPFRegStrings[] = {
31 /* 0 */ "R10\000"
32 /* 4 */ "W10\000"
33 /* 8 */ "R0\000"
34 /* 11 */ "W0\000"
35 /* 14 */ "R11\000"
36 /* 18 */ "W11\000"
37 /* 22 */ "R1\000"
38 /* 25 */ "W1\000"
39 /* 28 */ "R2\000"
40 /* 31 */ "W2\000"
41 /* 34 */ "R3\000"
42 /* 37 */ "W3\000"
43 /* 40 */ "R4\000"
44 /* 43 */ "W4\000"
45 /* 46 */ "R5\000"
46 /* 49 */ "W5\000"
47 /* 52 */ "R6\000"
48 /* 55 */ "W6\000"
49 /* 58 */ "R7\000"
50 /* 61 */ "W7\000"
51 /* 64 */ "R8\000"
52 /* 67 */ "W8\000"
53 /* 70 */ "R9\000"
54 /* 73 */ "W9\000"
55};
56#ifdef __GNUC__
57#pragma GCC diagnostic pop
58#endif
59
60extern const MCRegisterDesc BPFRegDesc[] = { // Descriptors
61 { .Name: 3, .SubRegs: 0, .SuperRegs: 0, .SubRegIndices: 0, .RegUnits: 0, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
62 { .Name: 8, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4096, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
63 { .Name: 22, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4097, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
64 { .Name: 28, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4098, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
65 { .Name: 34, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4099, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
66 { .Name: 40, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4100, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
67 { .Name: 46, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4101, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
68 { .Name: 52, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4102, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
69 { .Name: 58, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4103, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
70 { .Name: 64, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4104, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
71 { .Name: 70, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4105, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
72 { .Name: 0, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4106, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
73 { .Name: 14, .SubRegs: 2, .SuperRegs: 1, .SubRegIndices: 0, .RegUnits: 4107, .RegUnitLaneMasks: 0, .IsConstant: 0, .IsArtificial: 0 },
74 { .Name: 11, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4096, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
75 { .Name: 25, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4097, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
76 { .Name: 31, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4098, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
77 { .Name: 37, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4099, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
78 { .Name: 43, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4100, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
79 { .Name: 49, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4101, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
80 { .Name: 55, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4102, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
81 { .Name: 61, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4103, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
82 { .Name: 67, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4104, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
83 { .Name: 73, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4105, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
84 { .Name: 4, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4106, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
85 { .Name: 18, .SubRegs: 1, .SuperRegs: 0, .SubRegIndices: 1, .RegUnits: 4107, .RegUnitLaneMasks: 1, .IsConstant: 0, .IsArtificial: 0 },
86};
87
88extern const MCPhysReg BPFRegUnitRoots[][2] = {
89 { BPF::W0 },
90 { BPF::W1 },
91 { BPF::W2 },
92 { BPF::W3 },
93 { BPF::W4 },
94 { BPF::W5 },
95 { BPF::W6 },
96 { BPF::W7 },
97 { BPF::W8 },
98 { BPF::W9 },
99 { BPF::W10 },
100 { BPF::W11 },
101};
102
103// Register classes...
104
105#ifdef __GNUC__
106#pragma GCC diagnostic push
107#pragma GCC diagnostic ignored "-Woverlength-strings"
108#endif
109extern const char BPFRegClassStrings[] = {
110 /* 0 */ "GPR32\000"
111 /* 6 */ "GPR\000"
112};
113#ifdef __GNUC__
114#pragma GCC diagnostic pop
115#endif
116
117using BPFRegisterClassStorage = MCRegisterClassStorage<2, 24, 4, 3, 2, 0>;
118extern const MCRegisterClassStorage<2, 24, 4, 3, 2, 0> BPFMCRegisterClassStorage = {
119 .Classes: {
120 {
121 offsetof(BPFRegisterClassStorage, Regs[0]) - 0 * sizeof(MCRegisterClass),
122 offsetof(BPFRegisterClassStorage, BitSets[0]) - 0 * sizeof(MCRegisterClass),
123 .NameIdx: 0,
124 .RegSizeInBits: 32,
125 .RegsSize: 12,
126 .RegSetBegin: 13, /* MinRegVal */
127 .RegSetSize: 12, /* RegSetSize */
128 .ID: BPF::GPR32RegClassID,
129 .CopyCost: 1, /* CopyCost */
130 .Allocatable: true, /* Allocatable */
131 .BaseClass: false,
132 offsetof(BPFRegisterClassStorage, SubClassMasks[0]) - 0 * sizeof(MCRegisterClass),
133 offsetof(BPFRegisterClassStorage, SuperRegIdxSeqs[0]) - 0 * sizeof(MCRegisterClass),
134 .LaneMask: LaneBitmask(0x0000000000000001),
135 .AllocationPriority: 0,
136 .GlobalPriority: false,
137 .TSFlags: 0x00, /* TSFlags */
138 .SpillStackID: 0, /* SpillStackID */
139 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
140 .CoveredBySubRegs: false, /* CoveredBySubRegs */
141 offsetof(BPFRegisterClassStorage, SuperClasses[0]) - 0 * sizeof(MCRegisterClass),
142 .SuperClassesSize: 0
143 },
144 {
145 offsetof(BPFRegisterClassStorage, Regs[12]) - 1 * sizeof(MCRegisterClass),
146 offsetof(BPFRegisterClassStorage, BitSets[2]) - 1 * sizeof(MCRegisterClass),
147 .NameIdx: 6,
148 .RegSizeInBits: 64,
149 .RegsSize: 12,
150 .RegSetBegin: 1, /* MinRegVal */
151 .RegSetSize: 12, /* RegSetSize */
152 .ID: BPF::GPRRegClassID,
153 .CopyCost: 1, /* CopyCost */
154 .Allocatable: true, /* Allocatable */
155 .BaseClass: false,
156 offsetof(BPFRegisterClassStorage, SubClassMasks[2]) - 1 * sizeof(MCRegisterClass),
157 offsetof(BPFRegisterClassStorage, SuperRegIdxSeqs[1]) - 1 * sizeof(MCRegisterClass),
158 .LaneMask: LaneBitmask(0x0000000000000001),
159 .AllocationPriority: 0,
160 .GlobalPriority: false,
161 .TSFlags: 0x00, /* TSFlags */
162 .SpillStackID: 0, /* SpillStackID */
163 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
164 .CoveredBySubRegs: false, /* CoveredBySubRegs */
165 offsetof(BPFRegisterClassStorage, SuperClasses[0]) - 1 * sizeof(MCRegisterClass),
166 .SuperClassesSize: 0
167 },
168 },
169 .Regs: {
170 /* 0 */ BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5, BPF::W6, BPF::W7, BPF::W8, BPF::W9, BPF::W0, BPF::W11, BPF::W10,
171 /* 12 */ BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R0, BPF::R11, BPF::R10,
172 },
173 .BitSets: {
174 /* 0 */ 0xff, 0x0f,
175 /* 2 */ 0xff, 0x0f,
176 },
177 .SubClassMasks: {
178 // 0 GPR32
179 0x00000001,
180 0x00000002, // sub_32
181 // 2 GPR
182 0x00000002,
183 },
184 .SuperRegIdxSeqs: {
185 /* 0 */ 1, 0,
186 },
187 .SuperClasses: {
188 /* 0 GPR32 */
189 /* 0 GPR */
190 }
191};
192
193const MCRegisterClass &getBPFMCRegisterClass(unsigned RC) {
194 return BPFMCRegisterClassStorage.Classes[RC];
195}
196
197// BPF Dwarf<->LLVM register mappings.
198extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[] = {
199 { .FromReg: 0U, .ToReg: BPF::W0 },
200 { .FromReg: 1U, .ToReg: BPF::W1 },
201 { .FromReg: 2U, .ToReg: BPF::W2 },
202 { .FromReg: 3U, .ToReg: BPF::W3 },
203 { .FromReg: 4U, .ToReg: BPF::W4 },
204 { .FromReg: 5U, .ToReg: BPF::W5 },
205 { .FromReg: 6U, .ToReg: BPF::W6 },
206 { .FromReg: 7U, .ToReg: BPF::W7 },
207 { .FromReg: 8U, .ToReg: BPF::W8 },
208 { .FromReg: 9U, .ToReg: BPF::W9 },
209 { .FromReg: 10U, .ToReg: BPF::W10 },
210 { .FromReg: 11U, .ToReg: BPF::W11 },
211};
212extern const unsigned BPFDwarfFlavour0Dwarf2LSize = std::size(BPFDwarfFlavour0Dwarf2L);
213
214extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[] = {
215 { .FromReg: 0U, .ToReg: BPF::W0 },
216 { .FromReg: 1U, .ToReg: BPF::W1 },
217 { .FromReg: 2U, .ToReg: BPF::W2 },
218 { .FromReg: 3U, .ToReg: BPF::W3 },
219 { .FromReg: 4U, .ToReg: BPF::W4 },
220 { .FromReg: 5U, .ToReg: BPF::W5 },
221 { .FromReg: 6U, .ToReg: BPF::W6 },
222 { .FromReg: 7U, .ToReg: BPF::W7 },
223 { .FromReg: 8U, .ToReg: BPF::W8 },
224 { .FromReg: 9U, .ToReg: BPF::W9 },
225 { .FromReg: 10U, .ToReg: BPF::W10 },
226 { .FromReg: 11U, .ToReg: BPF::W11 },
227};
228extern const unsigned BPFEHFlavour0Dwarf2LSize = std::size(BPFEHFlavour0Dwarf2L);
229
230extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[] = {
231 { .FromReg: BPF::R0, .ToReg: 0U },
232 { .FromReg: BPF::R1, .ToReg: 1U },
233 { .FromReg: BPF::R2, .ToReg: 2U },
234 { .FromReg: BPF::R3, .ToReg: 3U },
235 { .FromReg: BPF::R4, .ToReg: 4U },
236 { .FromReg: BPF::R5, .ToReg: 5U },
237 { .FromReg: BPF::R6, .ToReg: 6U },
238 { .FromReg: BPF::R7, .ToReg: 7U },
239 { .FromReg: BPF::R8, .ToReg: 8U },
240 { .FromReg: BPF::R9, .ToReg: 9U },
241 { .FromReg: BPF::R10, .ToReg: 10U },
242 { .FromReg: BPF::R11, .ToReg: 11U },
243 { .FromReg: BPF::W0, .ToReg: 0U },
244 { .FromReg: BPF::W1, .ToReg: 1U },
245 { .FromReg: BPF::W2, .ToReg: 2U },
246 { .FromReg: BPF::W3, .ToReg: 3U },
247 { .FromReg: BPF::W4, .ToReg: 4U },
248 { .FromReg: BPF::W5, .ToReg: 5U },
249 { .FromReg: BPF::W6, .ToReg: 6U },
250 { .FromReg: BPF::W7, .ToReg: 7U },
251 { .FromReg: BPF::W8, .ToReg: 8U },
252 { .FromReg: BPF::W9, .ToReg: 9U },
253 { .FromReg: BPF::W10, .ToReg: 10U },
254 { .FromReg: BPF::W11, .ToReg: 11U },
255};
256extern const unsigned BPFDwarfFlavour0L2DwarfSize = std::size(BPFDwarfFlavour0L2Dwarf);
257
258extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[] = {
259 { .FromReg: BPF::R0, .ToReg: 0U },
260 { .FromReg: BPF::R1, .ToReg: 1U },
261 { .FromReg: BPF::R2, .ToReg: 2U },
262 { .FromReg: BPF::R3, .ToReg: 3U },
263 { .FromReg: BPF::R4, .ToReg: 4U },
264 { .FromReg: BPF::R5, .ToReg: 5U },
265 { .FromReg: BPF::R6, .ToReg: 6U },
266 { .FromReg: BPF::R7, .ToReg: 7U },
267 { .FromReg: BPF::R8, .ToReg: 8U },
268 { .FromReg: BPF::R9, .ToReg: 9U },
269 { .FromReg: BPF::R10, .ToReg: 10U },
270 { .FromReg: BPF::R11, .ToReg: 11U },
271 { .FromReg: BPF::W0, .ToReg: 0U },
272 { .FromReg: BPF::W1, .ToReg: 1U },
273 { .FromReg: BPF::W2, .ToReg: 2U },
274 { .FromReg: BPF::W3, .ToReg: 3U },
275 { .FromReg: BPF::W4, .ToReg: 4U },
276 { .FromReg: BPF::W5, .ToReg: 5U },
277 { .FromReg: BPF::W6, .ToReg: 6U },
278 { .FromReg: BPF::W7, .ToReg: 7U },
279 { .FromReg: BPF::W8, .ToReg: 8U },
280 { .FromReg: BPF::W9, .ToReg: 9U },
281 { .FromReg: BPF::W10, .ToReg: 10U },
282 { .FromReg: BPF::W11, .ToReg: 11U },
283};
284extern const unsigned BPFEHFlavour0L2DwarfSize = std::size(BPFEHFlavour0L2Dwarf);
285
286extern const uint16_t BPFRegEncodingTable[] = {
287 0,
288 0,
289 1,
290 2,
291 3,
292 4,
293 5,
294 6,
295 7,
296 8,
297 9,
298 10,
299 11,
300 0,
301 1,
302 2,
303 3,
304 4,
305 5,
306 6,
307 7,
308 8,
309 9,
310 10,
311 11,
312};
313static inline void InitBPFMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
314 RI->InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC, C: BPFMCRegisterClassStorage.Classes, NC: 2, RURoots: BPFRegUnitRoots, NRU: 12, DL: BPFRegDiffLists, RUMS: BPFLaneMaskLists, Strings: BPFRegStrings, ClassStrings: BPFRegClassStrings, SubIndices: BPFSubRegIdxLists, NumIndices: 2,
315RET: BPFRegEncodingTable, RUI: nullptr);
316
317 switch (DwarfFlavour) {
318 default:
319 llvm_unreachable("Unknown DWARF flavour");
320 case 0:
321 RI->mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
322 break;
323 }
324 switch (EHFlavour) {
325 default:
326 llvm_unreachable("Unknown DWARF flavour");
327 case 0:
328 RI->mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
329 break;
330 }
331 switch (DwarfFlavour) {
332 default:
333 llvm_unreachable("Unknown DWARF flavour");
334 case 0:
335 RI->mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
336 break;
337 }
338 switch (EHFlavour) {
339 default:
340 llvm_unreachable("Unknown DWARF flavour");
341 case 0:
342 RI->mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
343 break;
344 }
345}
346
347
348} // namespace llvm
349