1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass BPFMCRegisterClasses[];
12
13static const MVT::SimpleValueType BPFVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char BPFSubRegIndexStrings[] = {
23 /* 0 */ "sub_32\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t BPFSubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits BPFSubRegIdxRangeTable[] = {
35 { .Offset: 65535, .Size: 65535 },
36 { .Offset: 0, .Size: 32 }, // sub_32
37};
38
39
40static const LaneBitmask BPFSubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // sub_32
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo BPFRegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*BPFVTLists+*/.VTListOffset: 0 }, // GPR32
50 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*BPFVTLists+*/.VTListOffset: 2 }, // GPR
51};
52static const uint32_t GPR32SubClassMask[] = {
53 0x00000001,
54 0x00000002, // sub_32
55};
56
57static const uint32_t GPRSubClassMask[] = {
58 0x00000002,
59};
60
61static const uint16_t SuperRegIdxSeqs[] = {
62 /* 0 */ 1, 0,
63};
64
65namespace BPF {
66
67// Register class instances.
68 extern const TargetRegisterClass GPR32RegClass = {
69 .MC: &BPFMCRegisterClasses[GPR32RegClassID],
70 .SubClassMask: GPR32SubClassMask,
71 .SuperRegIndices: SuperRegIdxSeqs + 0,
72 .LaneMask: LaneBitmask(0x0000000000000001),
73 .AllocationPriority: 0,
74 .GlobalPriority: false,
75 .TSFlags: 0x00, /* TSFlags */
76 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
77 .CoveredBySubRegs: false, /* CoveredBySubRegs */
78 .SuperClasses: nullptr, .SuperClassesSize: 0,
79 .OrderFunc: nullptr
80 };
81
82 extern const TargetRegisterClass GPRRegClass = {
83 .MC: &BPFMCRegisterClasses[GPRRegClassID],
84 .SubClassMask: GPRSubClassMask,
85 .SuperRegIndices: SuperRegIdxSeqs + 1,
86 .LaneMask: LaneBitmask(0x0000000000000001),
87 .AllocationPriority: 0,
88 .GlobalPriority: false,
89 .TSFlags: 0x00, /* TSFlags */
90 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
91 .CoveredBySubRegs: false, /* CoveredBySubRegs */
92 .SuperClasses: nullptr, .SuperClassesSize: 0,
93 .OrderFunc: nullptr
94 };
95
96
97} // namespace BPF
98static const TargetRegisterClass *const BPFRegisterClasses[] = {
99 &BPF::GPR32RegClass,
100 &BPF::GPRRegClass,
101 };
102
103static const uint8_t BPFCostPerUseTable[] = {
1040, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
105
106
107static const bool BPFInAllocatableClassTable[] = {
108false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
109
110
111static const TargetRegisterInfoDesc BPFRegInfoDesc = { // Extra Descriptors
112.CostPerUse: BPFCostPerUseTable, .NumCosts: 1, .InAllocatableClass: BPFInAllocatableClassTable};
113
114unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
115 static const uint8_t Rows[1][1] = {
116 { 0, },
117 };
118
119 --IdxA; assert(IdxA < 1); (void) IdxA;
120 --IdxB; assert(IdxB < 1);
121 return Rows[0][IdxB];
122}
123
124unsigned BPFGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
125 static const uint8_t Table[1][1] = {
126 { 0, },
127 };
128
129 --IdxA; assert(IdxA < 1);
130 --IdxB; assert(IdxB < 1);
131 return Table[IdxA][IdxB];
132 }
133
134 struct MaskRolOp {
135 LaneBitmask Mask;
136 uint8_t RotateLeft;
137 };
138 static const MaskRolOp LaneMaskComposeSequences[] = {
139 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
140 };
141 static const uint8_t CompositeSequences[] = {
142 0 // to sub_32
143 };
144
145LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
146 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
147 LaneBitmask Result;
148 for (const MaskRolOp *Ops =
149 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
150 Ops->Mask.any(); ++Ops) {
151 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
152 if (unsigned S = Ops->RotateLeft)
153 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
154 else
155 Result |= LaneBitmask(M);
156 }
157 return Result;
158}
159
160LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
161 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
162 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
163 LaneBitmask Result;
164 for (const MaskRolOp *Ops =
165 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
166 Ops->Mask.any(); ++Ops) {
167 LaneBitmask::Type M = LaneMask.getAsInteger();
168 if (unsigned S = Ops->RotateLeft)
169 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
170 else
171 Result |= LaneBitmask(M);
172 }
173 return Result;
174}
175
176const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
177 static constexpr uint8_t Table[2][1] = {
178 { // GPR32
179 0, // sub_32
180 },
181 { // GPR
182 2, // sub_32 -> GPR
183 },
184
185 };
186 assert(RC && "Missing regclass");
187 if (!Idx) return RC;
188 --Idx;
189 assert(Idx < 1 && "Bad subreg");
190 unsigned TV = Table[RC->getID()][Idx];
191 return TV ? getRegClass(i: TV - 1) : nullptr;
192}const TargetRegisterClass *BPFGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
193 static constexpr uint8_t Table[2][1] = {
194 { // GPR32
195 0, // GPR32:sub_32
196 },
197 { // GPR
198 1, // GPR:sub_32 -> GPR32
199 },
200
201 };
202 assert(RC && "Missing regclass");
203 if (!Idx) return RC;
204 --Idx;
205 assert(Idx < 1 && "Bad subreg");
206 unsigned TV = Table[RC->getID()][Idx];
207 return TV ? getRegClass(i: TV - 1) : nullptr;
208}/// Get the weight in units of pressure for this register class.
209const RegClassWeight &BPFGenRegisterInfo::
210getRegClassWeight(const TargetRegisterClass *RC) const {
211 static const RegClassWeight RCWeightTable[] = {
212 {.RegWeight: 1, .WeightLimit: 12}, // GPR32
213 {.RegWeight: 1, .WeightLimit: 12}, // GPR
214 };
215 return RCWeightTable[RC->getID()];
216}
217
218/// Get the weight in units of pressure for this register unit.
219unsigned BPFGenRegisterInfo::
220getRegUnitWeight(MCRegUnit RegUnit) const {
221 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
222 // All register units have unit weight.
223 return 1;
224}
225
226
227// Get the number of dimensions of register pressure.
228unsigned BPFGenRegisterInfo::getNumRegPressureSets() const {
229 return 1;
230}
231
232// Get the name of this register unit pressure set.
233const char *BPFGenRegisterInfo::
234getRegPressureSetName(unsigned Idx) const {
235 static const char *PressureNameTable[] = {
236 "GPR32",
237 };
238 return PressureNameTable[Idx];
239}
240
241// Get the register unit pressure limit for this dimension.
242// This limit must be adjusted dynamically for reserved registers.
243unsigned BPFGenRegisterInfo::
244getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
245 static const uint8_t PressureLimitTable[] = {
246 12, // 0: GPR32
247 };
248 return PressureLimitTable[Idx];
249}
250
251/// Table of pressure sets per register class or unit.
252static const int RCSetsTable[] = {
253 /* 0 */ 0, -1,
254};
255
256/// Get the dimensions of register pressure impacted by this register class.
257/// Returns a -1 terminated array of pressure set IDs
258const int *BPFGenRegisterInfo::
259getRegClassPressureSets(const TargetRegisterClass *RC) const {
260 static const uint8_t RCSetStartTable[] = {
261 0,0,};
262 return &RCSetsTable[RCSetStartTable[RC->getID()]];
263}
264
265/// Get the dimensions of register pressure impacted by this register unit.
266/// Returns a -1 terminated array of pressure set IDs
267const int *BPFGenRegisterInfo::
268getRegUnitPressureSets(MCRegUnit RegUnit) const {
269 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
270 static const uint8_t RUSetStartTable[] = {
271 0,0,0,0,0,0,0,0,0,0,0,0,};
272 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
273}
274
275extern const MCRegisterDesc BPFRegDesc[];
276extern const int16_t BPFRegDiffLists[];
277extern const LaneBitmask BPFLaneMaskLists[];
278extern const char BPFRegStrings[];
279extern const char BPFRegClassStrings[];
280extern const MCPhysReg BPFRegUnitRoots[][2];
281extern const uint16_t BPFSubRegIdxLists[];
282extern const uint16_t BPFRegEncodingTable[];
283// BPF Dwarf<->LLVM register mappings.
284extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
285extern const unsigned BPFDwarfFlavour0Dwarf2LSize;
286
287extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
288extern const unsigned BPFEHFlavour0Dwarf2LSize;
289
290extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
291extern const unsigned BPFDwarfFlavour0L2DwarfSize;
292
293extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
294extern const unsigned BPFEHFlavour0L2DwarfSize;
295
296
297BPFGenRegisterInfo::
298BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
299 unsigned PC, unsigned HwMode)
300 : TargetRegisterInfo(&BPFRegInfoDesc, BPFRegisterClasses,
301 BPFSubRegIndexStrings, BPFSubRegIndexNameOffsets,
302 BPFSubRegIdxRangeTable, BPFSubRegIndexLaneMaskTable,
303
304 LaneBitmask(0xFFFFFFFFFFFFFFFE), BPFRegClassInfos, BPFVTLists, HwMode) {
305 InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC,
306 C: BPFMCRegisterClasses, NC: 2, RURoots: BPFRegUnitRoots, NRU: 12, DL: BPFRegDiffLists,
307 RUMS: BPFLaneMaskLists, Strings: BPFRegStrings, ClassStrings: BPFRegClassStrings, SubIndices: BPFSubRegIdxLists, NumIndices: 2,
308 RET: BPFRegEncodingTable, RUI: nullptr);
309
310 switch (DwarfFlavour) {
311 default:
312 llvm_unreachable("Unknown DWARF flavour");
313 case 0:
314 mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
315 break;
316 }
317 switch (EHFlavour) {
318 default:
319 llvm_unreachable("Unknown DWARF flavour");
320 case 0:
321 mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
322 break;
323 }
324 switch (DwarfFlavour) {
325 default:
326 llvm_unreachable("Unknown DWARF flavour");
327 case 0:
328 mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
329 break;
330 }
331 switch (EHFlavour) {
332 default:
333 llvm_unreachable("Unknown DWARF flavour");
334 case 0:
335 mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
336 break;
337 }
338}
339
340static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
341static const uint32_t CSR_RegMask[] = { 0x00f80f80, };
342static const MCPhysReg CSR_PreserveAll_SaveList[] = { BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
343static const uint32_t CSR_PreserveAll_RegMask[] = { 0x00ffeffe, };
344
345
346ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const {
347 static const uint32_t *const Masks[] = {
348 CSR_RegMask,
349 CSR_PreserveAll_RegMask,
350 };
351 return ArrayRef(Masks);
352}
353
354bool BPFGenRegisterInfo::
355isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
356 return
357 false;
358}
359
360bool BPFGenRegisterInfo::
361isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
362 return
363 false;
364}
365
366bool BPFGenRegisterInfo::
367isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
368 return
369 false;
370}
371
372bool BPFGenRegisterInfo::
373isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
374 return
375 false;
376}
377
378bool BPFGenRegisterInfo::
379isConstantPhysReg(MCRegister PhysReg) const {
380 return
381 false;
382}
383
384ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const {
385 static const char *Names[] = {
386 "CSR",
387 "CSR_PreserveAll",
388 };
389 return ArrayRef(Names);
390}
391
392const BPFFrameLowering *
393BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
394 return static_cast<const BPFFrameLowering *>(
395 MF.getSubtarget().getFrameLowering());
396}
397
398
399} // namespace llvm
400