1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass BPFMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16};
17
18static const char *SubRegIndexNameTable[] = { "sub_32", "" };
19
20static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
21 { .Offset: 65535, .Size: 65535 },
22 { .Offset: 0, .Size: 32 }, // sub_32
23};
24
25
26static const LaneBitmask SubRegIndexLaneMaskTable[] = {
27 LaneBitmask::getAll(),
28 LaneBitmask(0x0000000000000001), // sub_32
29 };
30
31
32
33static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
34 // Mode = 0 (Default)
35 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 0 }, // GPR32
36 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // GPR
37};
38static const uint32_t GPR32SubClassMask[] = {
39 0x00000001,
40 0x00000002, // sub_32
41};
42
43static const uint32_t GPRSubClassMask[] = {
44 0x00000002,
45};
46
47static const uint16_t SuperRegIdxSeqs[] = {
48 /* 0 */ 1, 0,
49};
50
51
52namespace BPF { // Register class instances
53 extern const TargetRegisterClass GPR32RegClass = {
54 .MC: &BPFMCRegisterClasses[GPR32RegClassID],
55 .SubClassMask: GPR32SubClassMask,
56 .SuperRegIndices: SuperRegIdxSeqs + 0,
57 .LaneMask: LaneBitmask(0x0000000000000001),
58 .AllocationPriority: 0,
59 .GlobalPriority: false,
60 .TSFlags: 0x00, /* TSFlags */
61 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
62 .CoveredBySubRegs: false, /* CoveredBySubRegs */
63 .SuperClasses: nullptr, .SuperClassesSize: 0,
64 .OrderFunc: nullptr
65 };
66
67 extern const TargetRegisterClass GPRRegClass = {
68 .MC: &BPFMCRegisterClasses[GPRRegClassID],
69 .SubClassMask: GPRSubClassMask,
70 .SuperRegIndices: SuperRegIdxSeqs + 1,
71 .LaneMask: LaneBitmask(0x0000000000000001),
72 .AllocationPriority: 0,
73 .GlobalPriority: false,
74 .TSFlags: 0x00, /* TSFlags */
75 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
76 .CoveredBySubRegs: false, /* CoveredBySubRegs */
77 .SuperClasses: nullptr, .SuperClassesSize: 0,
78 .OrderFunc: nullptr
79 };
80
81} // end namespace BPF
82
83namespace {
84 const TargetRegisterClass *const RegisterClasses[] = {
85 &BPF::GPR32RegClass,
86 &BPF::GPRRegClass,
87 };
88} // end anonymous namespace
89
90static const uint8_t CostPerUseTable[] = {
910, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
92
93
94static const bool InAllocatableClassTable[] = {
95false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
96
97
98static const TargetRegisterInfoDesc BPFRegInfoDesc = { // Extra Descriptors
99.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
100
101unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
102 static const uint8_t Rows[1][1] = {
103 { 0, },
104 };
105
106 --IdxA; assert(IdxA < 1); (void) IdxA;
107 --IdxB; assert(IdxB < 1);
108 return Rows[0][IdxB];
109}
110
111unsigned BPFGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
112 static const uint8_t Table[1][1] = {
113 { 0, },
114 };
115
116 --IdxA; assert(IdxA < 1);
117 --IdxB; assert(IdxB < 1);
118 return Table[IdxA][IdxB];
119 }
120
121 struct MaskRolOp {
122 LaneBitmask Mask;
123 uint8_t RotateLeft;
124 };
125 static const MaskRolOp LaneMaskComposeSequences[] = {
126 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
127 };
128 static const uint8_t CompositeSequences[] = {
129 0 // to sub_32
130 };
131
132LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
133 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
134 LaneBitmask Result;
135 for (const MaskRolOp *Ops =
136 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
137 Ops->Mask.any(); ++Ops) {
138 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
139 if (unsigned S = Ops->RotateLeft)
140 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
141 else
142 Result |= LaneBitmask(M);
143 }
144 return Result;
145}
146
147LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
148 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
149 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
150 LaneBitmask Result;
151 for (const MaskRolOp *Ops =
152 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
153 Ops->Mask.any(); ++Ops) {
154 LaneBitmask::Type M = LaneMask.getAsInteger();
155 if (unsigned S = Ops->RotateLeft)
156 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
157 else
158 Result |= LaneBitmask(M);
159 }
160 return Result;
161}
162
163const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
164 static const uint8_t Table[2][1] = {
165 { // GPR32
166 0, // sub_32
167 },
168 { // GPR
169 2, // sub_32 -> GPR
170 },
171 };
172 assert(RC && "Missing regclass");
173 if (!Idx) return RC;
174 --Idx;
175 assert(Idx < 1 && "Bad subreg");
176 unsigned TV = Table[RC->getID()][Idx];
177 return TV ? getRegClass(i: TV - 1) : nullptr;
178}
179
180const TargetRegisterClass *BPFGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
181 static const uint8_t Table[2][1] = {
182 { // GPR32
183 0, // GPR32:sub_32
184 },
185 { // GPR
186 1, // GPR:sub_32 -> GPR32
187 },
188 };
189 assert(RC && "Missing regclass");
190 if (!Idx) return RC;
191 --Idx;
192 assert(Idx < 1 && "Bad subreg");
193 unsigned TV = Table[RC->getID()][Idx];
194 return TV ? getRegClass(i: TV - 1) : nullptr;
195}
196
197/// Get the weight in units of pressure for this register class.
198const RegClassWeight &BPFGenRegisterInfo::
199getRegClassWeight(const TargetRegisterClass *RC) const {
200 static const RegClassWeight RCWeightTable[] = {
201 {.RegWeight: 1, .WeightLimit: 12}, // GPR32
202 {.RegWeight: 1, .WeightLimit: 12}, // GPR
203 };
204 return RCWeightTable[RC->getID()];
205}
206
207/// Get the weight in units of pressure for this register unit.
208unsigned BPFGenRegisterInfo::
209getRegUnitWeight(MCRegUnit RegUnit) const {
210 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
211 // All register units have unit weight.
212 return 1;
213}
214
215
216// Get the number of dimensions of register pressure.
217unsigned BPFGenRegisterInfo::getNumRegPressureSets() const {
218 return 1;
219}
220
221// Get the name of this register unit pressure set.
222const char *BPFGenRegisterInfo::
223getRegPressureSetName(unsigned Idx) const {
224 static const char *PressureNameTable[] = {
225 "GPR32",
226 };
227 return PressureNameTable[Idx];
228}
229
230// Get the register unit pressure limit for this dimension.
231// This limit must be adjusted dynamically for reserved registers.
232unsigned BPFGenRegisterInfo::
233getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
234 static const uint8_t PressureLimitTable[] = {
235 12, // 0: GPR32
236 };
237 return PressureLimitTable[Idx];
238}
239
240/// Table of pressure sets per register class or unit.
241static const int RCSetsTable[] = {
242 /* 0 */ 0, -1,
243};
244
245/// Get the dimensions of register pressure impacted by this register class.
246/// Returns a -1 terminated array of pressure set IDs
247const int *BPFGenRegisterInfo::
248getRegClassPressureSets(const TargetRegisterClass *RC) const {
249 static const uint8_t RCSetStartTable[] = {
250 0,0,};
251 return &RCSetsTable[RCSetStartTable[RC->getID()]];
252}
253
254/// Get the dimensions of register pressure impacted by this register unit.
255/// Returns a -1 terminated array of pressure set IDs
256const int *BPFGenRegisterInfo::
257getRegUnitPressureSets(MCRegUnit RegUnit) const {
258 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
259 static const uint8_t RUSetStartTable[] = {
260 0,0,0,0,0,0,0,0,0,0,0,0,};
261 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
262}
263
264extern const MCRegisterDesc BPFRegDesc[];
265extern const int16_t BPFRegDiffLists[];
266extern const LaneBitmask BPFLaneMaskLists[];
267extern const char BPFRegStrings[];
268extern const char BPFRegClassStrings[];
269extern const MCPhysReg BPFRegUnitRoots[][2];
270extern const uint16_t BPFSubRegIdxLists[];
271extern const uint16_t BPFRegEncodingTable[];
272// BPF Dwarf<->LLVM register mappings.
273extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
274extern const unsigned BPFDwarfFlavour0Dwarf2LSize;
275
276extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
277extern const unsigned BPFEHFlavour0Dwarf2LSize;
278
279extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
280extern const unsigned BPFDwarfFlavour0L2DwarfSize;
281
282extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
283extern const unsigned BPFEHFlavour0L2DwarfSize;
284
285BPFGenRegisterInfo::
286BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
287 unsigned PC, unsigned HwMode)
288 : TargetRegisterInfo(&BPFRegInfoDesc, RegisterClasses, RegisterClasses+2,
289 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
290 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
291 InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC,
292 C: BPFMCRegisterClasses, NC: 2,
293 RURoots: BPFRegUnitRoots,
294 NRU: 12,
295 DL: BPFRegDiffLists,
296 RUMS: BPFLaneMaskLists,
297 Strings: BPFRegStrings,
298 ClassStrings: BPFRegClassStrings,
299 SubIndices: BPFSubRegIdxLists,
300 NumIndices: 2,
301 RET: BPFRegEncodingTable);
302
303 switch (DwarfFlavour) {
304 default:
305 llvm_unreachable("Unknown DWARF flavour");
306 case 0:
307 mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
308 break;
309 }
310 switch (EHFlavour) {
311 default:
312 llvm_unreachable("Unknown DWARF flavour");
313 case 0:
314 mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
315 break;
316 }
317 switch (DwarfFlavour) {
318 default:
319 llvm_unreachable("Unknown DWARF flavour");
320 case 0:
321 mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
322 break;
323 }
324 switch (EHFlavour) {
325 default:
326 llvm_unreachable("Unknown DWARF flavour");
327 case 0:
328 mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
329 break;
330 }
331}
332
333static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
334static const uint32_t CSR_RegMask[] = { 0x00f80f80, };
335static const MCPhysReg CSR_PreserveAll_SaveList[] = { BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
336static const uint32_t CSR_PreserveAll_RegMask[] = { 0x00ffeffe, };
337
338
339ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const {
340 static const uint32_t *const Masks[] = {
341 CSR_RegMask,
342 CSR_PreserveAll_RegMask,
343 };
344 return ArrayRef(Masks);
345}
346
347bool BPFGenRegisterInfo::
348isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
349 return
350 false;
351}
352
353bool BPFGenRegisterInfo::
354isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
355 return
356 false;
357}
358
359bool BPFGenRegisterInfo::
360isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
361 return
362 false;
363}
364
365bool BPFGenRegisterInfo::
366isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
367 return
368 false;
369}
370
371bool BPFGenRegisterInfo::
372isConstantPhysReg(MCRegister PhysReg) const {
373 return
374 false;
375}
376
377ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const {
378 static const char *Names[] = {
379 "CSR",
380 "CSR_PreserveAll",
381 };
382 return ArrayRef(Names);
383}
384
385const BPFFrameLowering *
386BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
387 return static_cast<const BPFFrameLowering *>(
388 MF.getSubtarget().getFrameLowering());
389}
390
391} // end namespace llvm
392
393