1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<2, 24, 6, 3, 2, 0> BPFMCRegisterClassStorage;
12
13static const MVT::SimpleValueType BPFVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char BPFSubRegIndexStrings[] = {
23 /* 0 */ "sub_32\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t BPFSubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits BPFSubRegIdxRangeTable[] = {
35 { .Offset: 4294967295, .Size: 4294967295 },
36 { .Offset: 0, .Size: 32 }, // sub_32
37};
38
39
40static const LaneBitmask BPFSubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // sub_32
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo BPFRegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*BPFVTLists+*/.VTListOffset: 0 }, // GPR32
50 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*BPFVTLists+*/.VTListOffset: 2 }, // GPR
51};
52
53static const uint8_t BPFCostPerUseTable[] = {
540, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
55
56
57static const bool BPFInAllocatableClassTable[] = {
58false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
59
60
61static const TargetRegisterInfoDesc BPFRegInfoDesc = { // Extra Descriptors
62.CostPerUse: BPFCostPerUseTable, .NumCosts: 1, .InAllocatableClass: BPFInAllocatableClassTable};
63
64unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
65 static const uint8_t Rows[1][1] = {
66 { 0, },
67 };
68
69 --IdxA; assert(IdxA < 1); (void) IdxA;
70 --IdxB; assert(IdxB < 1);
71 return Rows[0][IdxB];
72}
73
74unsigned BPFGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
75 static const uint8_t Table[1][1] = {
76 { 0, },
77 };
78
79 --IdxA; assert(IdxA < 1);
80 --IdxB; assert(IdxB < 1);
81 return Table[IdxA][IdxB];
82 }
83
84 struct MaskRolOp {
85 LaneBitmask Mask;
86 uint8_t RotateLeft;
87 };
88 static const MaskRolOp LaneMaskComposeSequences[] = {
89 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
90 };
91 static const uint8_t CompositeSequences[] = {
92 0 // to sub_32
93 };
94
95LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
96 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
97 LaneBitmask Result;
98 for (const MaskRolOp *Ops =
99 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
100 Ops->Mask.any(); ++Ops) {
101 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
102 if (unsigned S = Ops->RotateLeft)
103 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
104 else
105 Result |= LaneBitmask(M);
106 }
107 return Result;
108}
109
110LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
111 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
112 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
113 LaneBitmask Result;
114 for (const MaskRolOp *Ops =
115 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
116 Ops->Mask.any(); ++Ops) {
117 LaneBitmask::Type M = LaneMask.getAsInteger();
118 if (unsigned S = Ops->RotateLeft)
119 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
120 else
121 Result |= LaneBitmask(M);
122 }
123 return Result;
124}
125
126const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
127 static constexpr uint8_t Table[2][1] = {
128 { // GPR32
129 0, // sub_32
130 },
131 { // GPR
132 2, // sub_32 -> GPR
133 },
134
135 };
136 assert(RC && "Missing regclass");
137 if (!Idx) return RC;
138 --Idx;
139 assert(Idx < 1 && "Bad subreg");
140 unsigned TV = Table[RC->getID()][Idx];
141 return TV ? getRegClass(i: TV - 1) : nullptr;
142}const TargetRegisterClass *BPFGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
143 static constexpr uint8_t Table[2][1] = {
144 { // GPR32
145 0, // GPR32:sub_32
146 },
147 { // GPR
148 1, // GPR:sub_32 -> GPR32
149 },
150
151 };
152 assert(RC && "Missing regclass");
153 if (!Idx) return RC;
154 --Idx;
155 assert(Idx < 1 && "Bad subreg");
156 unsigned TV = Table[RC->getID()][Idx];
157 return TV ? getRegClass(i: TV - 1) : nullptr;
158}/// Get the weight in units of pressure for this register class.
159const RegClassWeight &BPFGenRegisterInfo::
160getRegClassWeight(const TargetRegisterClass *RC) const {
161 static const RegClassWeight RCWeightTable[] = {
162 {.RegWeight: 1, .WeightLimit: 12}, // GPR32
163 {.RegWeight: 1, .WeightLimit: 12}, // GPR
164 };
165 return RCWeightTable[RC->getID()];
166}
167
168/// Get the weight in units of pressure for this register unit.
169unsigned BPFGenRegisterInfo::
170getRegUnitWeight(MCRegUnit RegUnit) const {
171 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
172 // All register units have unit weight.
173 return 1;
174}
175
176
177// Get the number of dimensions of register pressure.
178unsigned BPFGenRegisterInfo::getNumRegPressureSets() const {
179 return 1;
180}
181
182// Get the name of this register unit pressure set.
183const char *BPFGenRegisterInfo::
184getRegPressureSetName(unsigned Idx) const {
185 static const char *PressureNameTable[] = {
186 "GPR32",
187 };
188 return PressureNameTable[Idx];
189}
190
191// Get the register unit pressure limit for this dimension.
192// This limit must be adjusted dynamically for reserved registers.
193unsigned BPFGenRegisterInfo::
194getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
195 static const uint8_t PressureLimitTable[] = {
196 12, // 0: GPR32
197 };
198 return PressureLimitTable[Idx];
199}
200
201/// Table of pressure sets per register class or unit.
202static const int RCSetsTable[] = {
203 /* 0 */ 0, -1,
204};
205
206/// Get the dimensions of register pressure impacted by this register class.
207/// Returns a -1 terminated array of pressure set IDs
208const int *BPFGenRegisterInfo::
209getRegClassPressureSets(const TargetRegisterClass *RC) const {
210 static const uint8_t RCSetStartTable[] = {
211 0,0,};
212 return &RCSetsTable[RCSetStartTable[RC->getID()]];
213}
214
215/// Get the dimensions of register pressure impacted by this register unit.
216/// Returns a -1 terminated array of pressure set IDs
217const int *BPFGenRegisterInfo::
218getRegUnitPressureSets(MCRegUnit RegUnit) const {
219 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
220 static const uint8_t RUSetStartTable[] = {
221 0,0,0,0,0,0,0,0,0,0,0,0,};
222 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
223}
224
225
226// Register to minimal register class mapping
227
228const TargetRegisterClass *BPFGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
229 static const uint16_t InvalidRegClassID = UINT16_MAX;
230
231 static const uint16_t Mapping[25] = {
232 InvalidRegClassID, // NoRegister
233 BPF::GPRRegClassID, // R0
234 BPF::GPRRegClassID, // R1
235 BPF::GPRRegClassID, // R2
236 BPF::GPRRegClassID, // R3
237 BPF::GPRRegClassID, // R4
238 BPF::GPRRegClassID, // R5
239 BPF::GPRRegClassID, // R6
240 BPF::GPRRegClassID, // R7
241 BPF::GPRRegClassID, // R8
242 BPF::GPRRegClassID, // R9
243 BPF::GPRRegClassID, // R10
244 BPF::GPRRegClassID, // R11
245 BPF::GPR32RegClassID, // W0
246 BPF::GPR32RegClassID, // W1
247 BPF::GPR32RegClassID, // W2
248 BPF::GPR32RegClassID, // W3
249 BPF::GPR32RegClassID, // W4
250 BPF::GPR32RegClassID, // W5
251 BPF::GPR32RegClassID, // W6
252 BPF::GPR32RegClassID, // W7
253 BPF::GPR32RegClassID, // W8
254 BPF::GPR32RegClassID, // W9
255 BPF::GPR32RegClassID, // W10
256 BPF::GPR32RegClassID, // W11
257 };
258
259 assert(Reg < ArrayRef(Mapping).size());
260 unsigned RCID = Mapping[Reg.id()];
261 if (RCID == InvalidRegClassID)
262 return nullptr;
263 return &BPFMCRegisterClassStorage.Classes[RCID];
264}
265extern const MCRegisterDesc BPFRegDesc[];
266extern const int16_t BPFRegDiffLists[];
267extern const LaneBitmask BPFLaneMaskLists[];
268extern const char BPFRegStrings[];
269extern const char BPFRegClassStrings[];
270extern const MCPhysReg BPFRegUnitRoots[][2];
271extern const uint16_t BPFSubRegIdxLists[];
272extern const uint16_t BPFRegEncodingTable[];
273// BPF Dwarf<->LLVM register mappings.
274extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
275extern const unsigned BPFDwarfFlavour0Dwarf2LSize;
276
277extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
278extern const unsigned BPFEHFlavour0Dwarf2LSize;
279
280extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
281extern const unsigned BPFDwarfFlavour0L2DwarfSize;
282
283extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
284extern const unsigned BPFEHFlavour0L2DwarfSize;
285
286
287BPFGenRegisterInfo::
288BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
289 unsigned PC, unsigned HwMode)
290 : TargetRegisterInfo(&BPFRegInfoDesc,
291 BPFSubRegIndexStrings, BPFSubRegIndexNameOffsets,
292 BPFSubRegIdxRangeTable, BPFSubRegIndexLaneMaskTable,
293
294 LaneBitmask(0xFFFFFFFFFFFFFFFE), BPFRegClassInfos, BPFVTLists, HwMode) {
295 InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC,
296 C: &getBPFMCRegisterClass(RC: 0), NC: 2, RURoots: BPFRegUnitRoots, NRU: 12, DL: BPFRegDiffLists,
297 RUMS: BPFLaneMaskLists, Strings: BPFRegStrings, ClassStrings: BPFRegClassStrings, SubIndices: BPFSubRegIdxLists, NumIndices: 2,
298 RET: BPFRegEncodingTable, RUI: nullptr);
299
300 switch (DwarfFlavour) {
301 default:
302 llvm_unreachable("Unknown DWARF flavour");
303 case 0:
304 mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
305 break;
306 }
307 switch (EHFlavour) {
308 default:
309 llvm_unreachable("Unknown DWARF flavour");
310 case 0:
311 mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
312 break;
313 }
314 switch (DwarfFlavour) {
315 default:
316 llvm_unreachable("Unknown DWARF flavour");
317 case 0:
318 mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
319 break;
320 }
321 switch (EHFlavour) {
322 default:
323 llvm_unreachable("Unknown DWARF flavour");
324 case 0:
325 mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
326 break;
327 }
328}
329
330static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
331static const uint32_t CSR_RegMask[] = { 0x00f80f80, };
332static const MCPhysReg CSR_PreserveAll_SaveList[] = { BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
333static const uint32_t CSR_PreserveAll_RegMask[] = { 0x00ffeffe, };
334
335
336ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const {
337 static const uint32_t *const Masks[] = {
338 CSR_RegMask,
339 CSR_PreserveAll_RegMask,
340 };
341 return ArrayRef(Masks);
342}
343
344bool BPFGenRegisterInfo::
345isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
346 return
347 false;
348}
349
350bool BPFGenRegisterInfo::
351isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
352 return
353 false;
354}
355
356bool BPFGenRegisterInfo::
357isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
358 return
359 false;
360}
361
362bool BPFGenRegisterInfo::
363isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
364 return
365 false;
366}
367
368bool BPFGenRegisterInfo::
369isConstantPhysReg(MCRegister PhysReg) const {
370 return
371 false;
372}
373
374ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const {
375 static const char *Names[] = {
376 "CSR",
377 "CSR_PreserveAll",
378 };
379 return ArrayRef(Names);
380}
381
382const BPFFrameLowering *
383BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
384 return static_cast<const BPFFrameLowering *>(
385 MF.getSubtarget().getFrameLowering());
386}
387
388
389} // namespace llvm
390