1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass BPFMCRegisterClasses[];
12
13static const MVT::SimpleValueType BPFVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char BPFSubRegIndexStrings[] = {
23 /* 0 */ "sub_32\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t BPFSubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits BPFSubRegIdxRangeTable[] = {
35 { .Offset: 4294967295, .Size: 4294967295 },
36 { .Offset: 0, .Size: 32 }, // sub_32
37};
38
39
40static const LaneBitmask BPFSubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // sub_32
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo BPFRegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*BPFVTLists+*/.VTListOffset: 0 }, // GPR32
50 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*BPFVTLists+*/.VTListOffset: 2 }, // GPR
51};
52static const uint32_t GPR32SubClassMask[] = {
53 0x00000001,
54 0x00000002, // sub_32
55};
56
57static const uint32_t GPRSubClassMask[] = {
58 0x00000002,
59};
60
61static const uint16_t SuperRegIdxSeqs[] = {
62 /* 0 */ 1, 0,
63};
64
65namespace BPF {
66
67// Register class instances.
68 extern const TargetRegisterClass GPR32RegClass = {
69 .MC: &BPFMCRegisterClasses[GPR32RegClassID],
70 .SubClassMask: GPR32SubClassMask,
71 .SuperRegIndices: SuperRegIdxSeqs + 0,
72 .LaneMask: LaneBitmask(0x0000000000000001),
73 .AllocationPriority: 0,
74 .GlobalPriority: false,
75 .TSFlags: 0x00, /* TSFlags */
76 .SpillStackID: 0, /* SpillStackID */
77 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
78 .CoveredBySubRegs: false, /* CoveredBySubRegs */
79 .SuperClasses: nullptr, .SuperClassesSize: 0,
80 .OrderFunc: nullptr
81 };
82
83 extern const TargetRegisterClass GPRRegClass = {
84 .MC: &BPFMCRegisterClasses[GPRRegClassID],
85 .SubClassMask: GPRSubClassMask,
86 .SuperRegIndices: SuperRegIdxSeqs + 1,
87 .LaneMask: LaneBitmask(0x0000000000000001),
88 .AllocationPriority: 0,
89 .GlobalPriority: false,
90 .TSFlags: 0x00, /* TSFlags */
91 .SpillStackID: 0, /* SpillStackID */
92 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
93 .CoveredBySubRegs: false, /* CoveredBySubRegs */
94 .SuperClasses: nullptr, .SuperClassesSize: 0,
95 .OrderFunc: nullptr
96 };
97
98
99} // namespace BPF
100static const TargetRegisterClass *const BPFRegisterClasses[] = {
101 &BPF::GPR32RegClass,
102 &BPF::GPRRegClass,
103 };
104
105static const uint8_t BPFCostPerUseTable[] = {
1060, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
107
108
109static const bool BPFInAllocatableClassTable[] = {
110false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
111
112
113static const TargetRegisterInfoDesc BPFRegInfoDesc = { // Extra Descriptors
114.CostPerUse: BPFCostPerUseTable, .NumCosts: 1, .InAllocatableClass: BPFInAllocatableClassTable};
115
116unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
117 static const uint8_t Rows[1][1] = {
118 { 0, },
119 };
120
121 --IdxA; assert(IdxA < 1); (void) IdxA;
122 --IdxB; assert(IdxB < 1);
123 return Rows[0][IdxB];
124}
125
126unsigned BPFGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
127 static const uint8_t Table[1][1] = {
128 { 0, },
129 };
130
131 --IdxA; assert(IdxA < 1);
132 --IdxB; assert(IdxB < 1);
133 return Table[IdxA][IdxB];
134 }
135
136 struct MaskRolOp {
137 LaneBitmask Mask;
138 uint8_t RotateLeft;
139 };
140 static const MaskRolOp LaneMaskComposeSequences[] = {
141 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
142 };
143 static const uint8_t CompositeSequences[] = {
144 0 // to sub_32
145 };
146
147LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
148 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
149 LaneBitmask Result;
150 for (const MaskRolOp *Ops =
151 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
152 Ops->Mask.any(); ++Ops) {
153 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
154 if (unsigned S = Ops->RotateLeft)
155 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
156 else
157 Result |= LaneBitmask(M);
158 }
159 return Result;
160}
161
162LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
163 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
164 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
165 LaneBitmask Result;
166 for (const MaskRolOp *Ops =
167 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
168 Ops->Mask.any(); ++Ops) {
169 LaneBitmask::Type M = LaneMask.getAsInteger();
170 if (unsigned S = Ops->RotateLeft)
171 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
172 else
173 Result |= LaneBitmask(M);
174 }
175 return Result;
176}
177
178const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
179 static constexpr uint8_t Table[2][1] = {
180 { // GPR32
181 0, // sub_32
182 },
183 { // GPR
184 2, // sub_32 -> GPR
185 },
186
187 };
188 assert(RC && "Missing regclass");
189 if (!Idx) return RC;
190 --Idx;
191 assert(Idx < 1 && "Bad subreg");
192 unsigned TV = Table[RC->getID()][Idx];
193 return TV ? getRegClass(i: TV - 1) : nullptr;
194}const TargetRegisterClass *BPFGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
195 static constexpr uint8_t Table[2][1] = {
196 { // GPR32
197 0, // GPR32:sub_32
198 },
199 { // GPR
200 1, // GPR:sub_32 -> GPR32
201 },
202
203 };
204 assert(RC && "Missing regclass");
205 if (!Idx) return RC;
206 --Idx;
207 assert(Idx < 1 && "Bad subreg");
208 unsigned TV = Table[RC->getID()][Idx];
209 return TV ? getRegClass(i: TV - 1) : nullptr;
210}/// Get the weight in units of pressure for this register class.
211const RegClassWeight &BPFGenRegisterInfo::
212getRegClassWeight(const TargetRegisterClass *RC) const {
213 static const RegClassWeight RCWeightTable[] = {
214 {.RegWeight: 1, .WeightLimit: 12}, // GPR32
215 {.RegWeight: 1, .WeightLimit: 12}, // GPR
216 };
217 return RCWeightTable[RC->getID()];
218}
219
220/// Get the weight in units of pressure for this register unit.
221unsigned BPFGenRegisterInfo::
222getRegUnitWeight(MCRegUnit RegUnit) const {
223 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
224 // All register units have unit weight.
225 return 1;
226}
227
228
229// Get the number of dimensions of register pressure.
230unsigned BPFGenRegisterInfo::getNumRegPressureSets() const {
231 return 1;
232}
233
234// Get the name of this register unit pressure set.
235const char *BPFGenRegisterInfo::
236getRegPressureSetName(unsigned Idx) const {
237 static const char *PressureNameTable[] = {
238 "GPR32",
239 };
240 return PressureNameTable[Idx];
241}
242
243// Get the register unit pressure limit for this dimension.
244// This limit must be adjusted dynamically for reserved registers.
245unsigned BPFGenRegisterInfo::
246getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
247 static const uint8_t PressureLimitTable[] = {
248 12, // 0: GPR32
249 };
250 return PressureLimitTable[Idx];
251}
252
253/// Table of pressure sets per register class or unit.
254static const int RCSetsTable[] = {
255 /* 0 */ 0, -1,
256};
257
258/// Get the dimensions of register pressure impacted by this register class.
259/// Returns a -1 terminated array of pressure set IDs
260const int *BPFGenRegisterInfo::
261getRegClassPressureSets(const TargetRegisterClass *RC) const {
262 static const uint8_t RCSetStartTable[] = {
263 0,0,};
264 return &RCSetsTable[RCSetStartTable[RC->getID()]];
265}
266
267/// Get the dimensions of register pressure impacted by this register unit.
268/// Returns a -1 terminated array of pressure set IDs
269const int *BPFGenRegisterInfo::
270getRegUnitPressureSets(MCRegUnit RegUnit) const {
271 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
272 static const uint8_t RUSetStartTable[] = {
273 0,0,0,0,0,0,0,0,0,0,0,0,};
274 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
275}
276
277
278// Register to minimal register class mapping
279
280const TargetRegisterClass *BPFGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
281 static const uint16_t InvalidRegClassID = UINT16_MAX;
282
283 static const uint16_t Mapping[25] = {
284 InvalidRegClassID, // NoRegister
285 BPF::GPRRegClassID, // R0
286 BPF::GPRRegClassID, // R1
287 BPF::GPRRegClassID, // R2
288 BPF::GPRRegClassID, // R3
289 BPF::GPRRegClassID, // R4
290 BPF::GPRRegClassID, // R5
291 BPF::GPRRegClassID, // R6
292 BPF::GPRRegClassID, // R7
293 BPF::GPRRegClassID, // R8
294 BPF::GPRRegClassID, // R9
295 BPF::GPRRegClassID, // R10
296 BPF::GPRRegClassID, // R11
297 BPF::GPR32RegClassID, // W0
298 BPF::GPR32RegClassID, // W1
299 BPF::GPR32RegClassID, // W2
300 BPF::GPR32RegClassID, // W3
301 BPF::GPR32RegClassID, // W4
302 BPF::GPR32RegClassID, // W5
303 BPF::GPR32RegClassID, // W6
304 BPF::GPR32RegClassID, // W7
305 BPF::GPR32RegClassID, // W8
306 BPF::GPR32RegClassID, // W9
307 BPF::GPR32RegClassID, // W10
308 BPF::GPR32RegClassID, // W11
309 };
310
311 assert(Reg < ArrayRef(Mapping).size());
312 unsigned RCID = Mapping[Reg.id()];
313 if (RCID == InvalidRegClassID)
314 return nullptr;
315 return BPFRegisterClasses[RCID];
316}
317extern const MCRegisterDesc BPFRegDesc[];
318extern const int16_t BPFRegDiffLists[];
319extern const LaneBitmask BPFLaneMaskLists[];
320extern const char BPFRegStrings[];
321extern const char BPFRegClassStrings[];
322extern const MCPhysReg BPFRegUnitRoots[][2];
323extern const uint16_t BPFSubRegIdxLists[];
324extern const uint16_t BPFRegEncodingTable[];
325// BPF Dwarf<->LLVM register mappings.
326extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
327extern const unsigned BPFDwarfFlavour0Dwarf2LSize;
328
329extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
330extern const unsigned BPFEHFlavour0Dwarf2LSize;
331
332extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
333extern const unsigned BPFDwarfFlavour0L2DwarfSize;
334
335extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
336extern const unsigned BPFEHFlavour0L2DwarfSize;
337
338
339BPFGenRegisterInfo::
340BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
341 unsigned PC, unsigned HwMode)
342 : TargetRegisterInfo(&BPFRegInfoDesc, BPFRegisterClasses,
343 BPFSubRegIndexStrings, BPFSubRegIndexNameOffsets,
344 BPFSubRegIdxRangeTable, BPFSubRegIndexLaneMaskTable,
345
346 LaneBitmask(0xFFFFFFFFFFFFFFFE), BPFRegClassInfos, BPFVTLists, HwMode) {
347 InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC,
348 C: BPFMCRegisterClasses, NC: 2, RURoots: BPFRegUnitRoots, NRU: 12, DL: BPFRegDiffLists,
349 RUMS: BPFLaneMaskLists, Strings: BPFRegStrings, ClassStrings: BPFRegClassStrings, SubIndices: BPFSubRegIdxLists, NumIndices: 2,
350 RET: BPFRegEncodingTable, RUI: nullptr);
351
352 switch (DwarfFlavour) {
353 default:
354 llvm_unreachable("Unknown DWARF flavour");
355 case 0:
356 mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
357 break;
358 }
359 switch (EHFlavour) {
360 default:
361 llvm_unreachable("Unknown DWARF flavour");
362 case 0:
363 mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
364 break;
365 }
366 switch (DwarfFlavour) {
367 default:
368 llvm_unreachable("Unknown DWARF flavour");
369 case 0:
370 mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
371 break;
372 }
373 switch (EHFlavour) {
374 default:
375 llvm_unreachable("Unknown DWARF flavour");
376 case 0:
377 mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
378 break;
379 }
380}
381
382static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
383static const uint32_t CSR_RegMask[] = { 0x00f80f80, };
384static const MCPhysReg CSR_PreserveAll_SaveList[] = { BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
385static const uint32_t CSR_PreserveAll_RegMask[] = { 0x00ffeffe, };
386
387
388ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const {
389 static const uint32_t *const Masks[] = {
390 CSR_RegMask,
391 CSR_PreserveAll_RegMask,
392 };
393 return ArrayRef(Masks);
394}
395
396bool BPFGenRegisterInfo::
397isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
398 return
399 false;
400}
401
402bool BPFGenRegisterInfo::
403isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
404 return
405 false;
406}
407
408bool BPFGenRegisterInfo::
409isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
410 return
411 false;
412}
413
414bool BPFGenRegisterInfo::
415isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
416 return
417 false;
418}
419
420bool BPFGenRegisterInfo::
421isConstantPhysReg(MCRegister PhysReg) const {
422 return
423 false;
424}
425
426ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const {
427 static const char *Names[] = {
428 "CSR",
429 "CSR_PreserveAll",
430 };
431 return ArrayRef(Names);
432}
433
434const BPFFrameLowering *
435BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
436 return static_cast<const BPFFrameLowering *>(
437 MF.getSubtarget().getFrameLowering());
438}
439
440
441} // namespace llvm
442