1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClass BPFMCRegisterClasses[];
12
13static const MVT::SimpleValueType VTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char BPFSubRegIndexStrings[] = {
23 /* 0 */ "sub_32\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t BPFSubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
35 { .Offset: 65535, .Size: 65535 },
36 { .Offset: 0, .Size: 32 }, // sub_32
37};
38
39
40static const LaneBitmask SubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // sub_32
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 0 }, // GPR32
50 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*VTLists+*/.VTListOffset: 2 }, // GPR
51};
52static const uint32_t GPR32SubClassMask[] = {
53 0x00000001,
54 0x00000002, // sub_32
55};
56
57static const uint32_t GPRSubClassMask[] = {
58 0x00000002,
59};
60
61static const uint16_t SuperRegIdxSeqs[] = {
62 /* 0 */ 1, 0,
63};
64
65namespace BPF {
66
67// Register class instances
68 extern const TargetRegisterClass GPR32RegClass = {
69 .MC: &BPFMCRegisterClasses[GPR32RegClassID],
70 .SubClassMask: GPR32SubClassMask,
71 .SuperRegIndices: SuperRegIdxSeqs + 0,
72 .LaneMask: LaneBitmask(0x0000000000000001),
73 .AllocationPriority: 0,
74 .GlobalPriority: false,
75 .TSFlags: 0x00, /* TSFlags */
76 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
77 .CoveredBySubRegs: false, /* CoveredBySubRegs */
78 .SuperClasses: nullptr, .SuperClassesSize: 0,
79 .OrderFunc: nullptr
80 };
81
82 extern const TargetRegisterClass GPRRegClass = {
83 .MC: &BPFMCRegisterClasses[GPRRegClassID],
84 .SubClassMask: GPRSubClassMask,
85 .SuperRegIndices: SuperRegIdxSeqs + 1,
86 .LaneMask: LaneBitmask(0x0000000000000001),
87 .AllocationPriority: 0,
88 .GlobalPriority: false,
89 .TSFlags: 0x00, /* TSFlags */
90 .HasDisjunctSubRegs: false, /* HasDisjunctSubRegs */
91 .CoveredBySubRegs: false, /* CoveredBySubRegs */
92 .SuperClasses: nullptr, .SuperClassesSize: 0,
93 .OrderFunc: nullptr
94 };
95
96
97} // namespace BPF
98namespace {
99
100 const TargetRegisterClass *const RegisterClasses[] = {
101 &BPF::GPR32RegClass,
102 &BPF::GPRRegClass,
103 };
104} // namespace
105
106static const uint8_t CostPerUseTable[] = {
1070, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
108
109
110static const bool InAllocatableClassTable[] = {
111false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
112
113
114static const TargetRegisterInfoDesc BPFRegInfoDesc = { // Extra Descriptors
115.CostPerUse: CostPerUseTable, .NumCosts: 1, .InAllocatableClass: InAllocatableClassTable};
116
117unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
118 static const uint8_t Rows[1][1] = {
119 { 0, },
120 };
121
122 --IdxA; assert(IdxA < 1); (void) IdxA;
123 --IdxB; assert(IdxB < 1);
124 return Rows[0][IdxB];
125}
126
127unsigned BPFGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
128 static const uint8_t Table[1][1] = {
129 { 0, },
130 };
131
132 --IdxA; assert(IdxA < 1);
133 --IdxB; assert(IdxB < 1);
134 return Table[IdxA][IdxB];
135 }
136
137 struct MaskRolOp {
138 LaneBitmask Mask;
139 uint8_t RotateLeft;
140 };
141 static const MaskRolOp LaneMaskComposeSequences[] = {
142 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
143 };
144 static const uint8_t CompositeSequences[] = {
145 0 // to sub_32
146 };
147
148LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
149 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
150 LaneBitmask Result;
151 for (const MaskRolOp *Ops =
152 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
153 Ops->Mask.any(); ++Ops) {
154 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
155 if (unsigned S = Ops->RotateLeft)
156 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
157 else
158 Result |= LaneBitmask(M);
159 }
160 return Result;
161}
162
163LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
164 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
165 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
166 LaneBitmask Result;
167 for (const MaskRolOp *Ops =
168 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
169 Ops->Mask.any(); ++Ops) {
170 LaneBitmask::Type M = LaneMask.getAsInteger();
171 if (unsigned S = Ops->RotateLeft)
172 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
173 else
174 Result |= LaneBitmask(M);
175 }
176 return Result;
177}
178
179const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
180 static constexpr uint8_t Table[2][1] = {
181 { // GPR32
182 0, // sub_32
183 },
184 { // GPR
185 2, // sub_32 -> GPR
186 },
187
188 };
189 assert(RC && "Missing regclass");
190 if (!Idx) return RC;
191 --Idx;
192 assert(Idx < 1 && "Bad subreg");
193 unsigned TV = Table[RC->getID()][Idx];
194 return TV ? getRegClass(i: TV - 1) : nullptr;
195}const TargetRegisterClass *BPFGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
196 static constexpr uint8_t Table[2][1] = {
197 { // GPR32
198 0, // GPR32:sub_32
199 },
200 { // GPR
201 1, // GPR:sub_32 -> GPR32
202 },
203
204 };
205 assert(RC && "Missing regclass");
206 if (!Idx) return RC;
207 --Idx;
208 assert(Idx < 1 && "Bad subreg");
209 unsigned TV = Table[RC->getID()][Idx];
210 return TV ? getRegClass(i: TV - 1) : nullptr;
211}/// Get the weight in units of pressure for this register class.
212const RegClassWeight &BPFGenRegisterInfo::
213getRegClassWeight(const TargetRegisterClass *RC) const {
214 static const RegClassWeight RCWeightTable[] = {
215 {.RegWeight: 1, .WeightLimit: 12}, // GPR32
216 {.RegWeight: 1, .WeightLimit: 12}, // GPR
217 };
218 return RCWeightTable[RC->getID()];
219}
220
221/// Get the weight in units of pressure for this register unit.
222unsigned BPFGenRegisterInfo::
223getRegUnitWeight(MCRegUnit RegUnit) const {
224 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
225 // All register units have unit weight.
226 return 1;
227}
228
229
230// Get the number of dimensions of register pressure.
231unsigned BPFGenRegisterInfo::getNumRegPressureSets() const {
232 return 1;
233}
234
235// Get the name of this register unit pressure set.
236const char *BPFGenRegisterInfo::
237getRegPressureSetName(unsigned Idx) const {
238 static const char *PressureNameTable[] = {
239 "GPR32",
240 };
241 return PressureNameTable[Idx];
242}
243
244// Get the register unit pressure limit for this dimension.
245// This limit must be adjusted dynamically for reserved registers.
246unsigned BPFGenRegisterInfo::
247getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
248 static const uint8_t PressureLimitTable[] = {
249 12, // 0: GPR32
250 };
251 return PressureLimitTable[Idx];
252}
253
254/// Table of pressure sets per register class or unit.
255static const int RCSetsTable[] = {
256 /* 0 */ 0, -1,
257};
258
259/// Get the dimensions of register pressure impacted by this register class.
260/// Returns a -1 terminated array of pressure set IDs
261const int *BPFGenRegisterInfo::
262getRegClassPressureSets(const TargetRegisterClass *RC) const {
263 static const uint8_t RCSetStartTable[] = {
264 0,0,};
265 return &RCSetsTable[RCSetStartTable[RC->getID()]];
266}
267
268/// Get the dimensions of register pressure impacted by this register unit.
269/// Returns a -1 terminated array of pressure set IDs
270const int *BPFGenRegisterInfo::
271getRegUnitPressureSets(MCRegUnit RegUnit) const {
272 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
273 static const uint8_t RUSetStartTable[] = {
274 0,0,0,0,0,0,0,0,0,0,0,0,};
275 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
276}
277
278extern const MCRegisterDesc BPFRegDesc[];
279extern const int16_t BPFRegDiffLists[];
280extern const LaneBitmask BPFLaneMaskLists[];
281extern const char BPFRegStrings[];
282extern const char BPFRegClassStrings[];
283extern const MCPhysReg BPFRegUnitRoots[][2];
284extern const uint16_t BPFSubRegIdxLists[];
285extern const uint16_t BPFRegEncodingTable[];
286// BPF Dwarf<->LLVM register mappings.
287extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
288extern const unsigned BPFDwarfFlavour0Dwarf2LSize;
289
290extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
291extern const unsigned BPFEHFlavour0Dwarf2LSize;
292
293extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
294extern const unsigned BPFDwarfFlavour0L2DwarfSize;
295
296extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
297extern const unsigned BPFEHFlavour0L2DwarfSize;
298
299
300BPFGenRegisterInfo::
301BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
302 unsigned PC, unsigned HwMode)
303 : TargetRegisterInfo(&BPFRegInfoDesc, RegisterClasses, RegisterClasses+2,
304 BPFSubRegIndexStrings, BPFSubRegIndexNameOffsets,
305 SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
306
307 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
308 InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC,
309 C: BPFMCRegisterClasses, NC: 2,
310 RURoots: BPFRegUnitRoots,
311 NRU: 12,
312 DL: BPFRegDiffLists,
313 RUMS: BPFLaneMaskLists,
314 Strings: BPFRegStrings,
315 ClassStrings: BPFRegClassStrings,
316 SubIndices: BPFSubRegIdxLists,
317 NumIndices: 2,
318 RET: BPFRegEncodingTable,
319 RUI: nullptr);
320
321 switch (DwarfFlavour) {
322 default:
323 llvm_unreachable("Unknown DWARF flavour");
324 case 0:
325 mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
326 break;
327 }
328 switch (EHFlavour) {
329 default:
330 llvm_unreachable("Unknown DWARF flavour");
331 case 0:
332 mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
333 break;
334 }
335 switch (DwarfFlavour) {
336 default:
337 llvm_unreachable("Unknown DWARF flavour");
338 case 0:
339 mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
340 break;
341 }
342 switch (EHFlavour) {
343 default:
344 llvm_unreachable("Unknown DWARF flavour");
345 case 0:
346 mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
347 break;
348 }
349}
350
351static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
352static const uint32_t CSR_RegMask[] = { 0x00f80f80, };
353static const MCPhysReg CSR_PreserveAll_SaveList[] = { BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
354static const uint32_t CSR_PreserveAll_RegMask[] = { 0x00ffeffe, };
355
356
357ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const {
358 static const uint32_t *const Masks[] = {
359 CSR_RegMask,
360 CSR_PreserveAll_RegMask,
361 };
362 return ArrayRef(Masks);
363}
364
365bool BPFGenRegisterInfo::
366isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
367 return
368 false;
369}
370
371bool BPFGenRegisterInfo::
372isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
373 return
374 false;
375}
376
377bool BPFGenRegisterInfo::
378isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
379 return
380 false;
381}
382
383bool BPFGenRegisterInfo::
384isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
385 return
386 false;
387}
388
389bool BPFGenRegisterInfo::
390isConstantPhysReg(MCRegister PhysReg) const {
391 return
392 false;
393}
394
395ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const {
396 static const char *Names[] = {
397 "CSR",
398 "CSR_PreserveAll",
399 };
400 return ArrayRef(Names);
401}
402
403const BPFFrameLowering *
404BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
405 return static_cast<const BPFFrameLowering *>(
406 MF.getSubtarget().getFrameLowering());
407}
408
409
410} // namespace llvm
411