1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register and Register Classes Information *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10
11extern const MCRegisterClassStorage<2, 24, 4, 3, 2, 0> BPFMCRegisterClassStorage;
12
13static const MVT::SimpleValueType BPFVTLists[] = {
14 /* 0 */ MVT::i32, MVT::Other,
15 /* 2 */ MVT::i64, MVT::Other,
16};
17
18#ifdef __GNUC__
19#pragma GCC diagnostic push
20#pragma GCC diagnostic ignored "-Woverlength-strings"
21#endif
22static constexpr char BPFSubRegIndexStrings[] = {
23 /* 0 */ "sub_32\000"
24};
25#ifdef __GNUC__
26#pragma GCC diagnostic pop
27#endif
28
29
30static constexpr uint32_t BPFSubRegIndexNameOffsets[] = {
31 0,
32};
33
34static const TargetRegisterInfo::SubRegCoveredBits BPFSubRegIdxRangeTable[] = {
35 { .Offset: 4294967295, .Size: 4294967295 },
36 { .Offset: 0, .Size: 32 }, // sub_32
37};
38
39
40static const LaneBitmask BPFSubRegIndexLaneMaskTable[] = {
41 LaneBitmask::getAll(),
42 LaneBitmask(0x0000000000000001), // sub_32
43 };
44
45
46
47static const TargetRegisterInfo::RegClassInfo BPFRegClassInfos[] = {
48 // Mode = 0 (DefaultMode)
49 { .RegSize: 32, .SpillSize: 32, .SpillAlignment: 64, /*BPFVTLists+*/.VTListOffset: 0 }, // GPR32
50 { .RegSize: 64, .SpillSize: 64, .SpillAlignment: 64, /*BPFVTLists+*/.VTListOffset: 2 }, // GPR
51};
52
53static const uint8_t BPFCostPerUseTable[] = {
540, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
55
56
57static const bool BPFInAllocatableClassTable[] = {
58false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
59
60
61static const TargetRegisterInfoDesc BPFRegInfoDesc = { // Extra Descriptors
62.CostPerUse: BPFCostPerUseTable, .NumCosts: 1, .InAllocatableClass: BPFInAllocatableClassTable};
63
64unsigned BPFGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
65 static const uint8_t Rows[1][1] = {
66 { 0, },
67 };
68
69 --IdxA; assert(IdxA < 1); (void) IdxA;
70 --IdxB; assert(IdxB < 1);
71 return Rows[0][IdxB];
72}
73
74unsigned BPFGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
75 static const uint8_t Table[1][1] = {
76 { 0, },
77 };
78
79 --IdxA; assert(IdxA < 1);
80 --IdxB; assert(IdxB < 1);
81 return Table[IdxA][IdxB];
82 }
83
84 struct MaskRolOp {
85 LaneBitmask Mask;
86 uint8_t RotateLeft;
87 };
88 static const MaskRolOp LaneMaskComposeSequences[] = {
89 { .Mask: LaneBitmask(0xFFFFFFFFFFFFFFFF), .RotateLeft: 0 }, { .Mask: LaneBitmask::getNone(), .RotateLeft: 0 } // Sequence 0
90 };
91 static const uint8_t CompositeSequences[] = {
92 0 // to sub_32
93 };
94
95LaneBitmask BPFGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
96 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
97 LaneBitmask Result;
98 for (const MaskRolOp *Ops =
99 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
100 Ops->Mask.any(); ++Ops) {
101 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
102 if (unsigned S = Ops->RotateLeft)
103 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
104 else
105 Result |= LaneBitmask(M);
106 }
107 return Result;
108}
109
110LaneBitmask BPFGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
111 LaneMask &= getSubRegIndexLaneMask(SubIdx: IdxA);
112 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
113 LaneBitmask Result;
114 for (const MaskRolOp *Ops =
115 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
116 Ops->Mask.any(); ++Ops) {
117 LaneBitmask::Type M = LaneMask.getAsInteger();
118 if (unsigned S = Ops->RotateLeft)
119 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
120 else
121 Result |= LaneBitmask(M);
122 }
123 return Result;
124}
125
126const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
127 static constexpr uint8_t Table[2][1] = {
128 { // GPR32
129 0, // sub_32
130 },
131 { // GPR
132 2, // sub_32 -> GPR
133 },
134
135 };
136 assert(RC && "Missing regclass");
137 if (!Idx) return RC;
138 --Idx;
139 assert(Idx < 1 && "Bad subreg");
140 unsigned TV = Table[RC->getID()][Idx];
141 return TV ? getRegClass(i: TV - 1) : nullptr;
142}const TargetRegisterClass *BPFGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
143 static constexpr uint8_t Table[2][1] = {
144 { // GPR32
145 0, // GPR32:sub_32
146 },
147 { // GPR
148 1, // GPR:sub_32 -> GPR32
149 },
150
151 };
152 assert(RC && "Missing regclass");
153 if (!Idx) return RC;
154 --Idx;
155 assert(Idx < 1 && "Bad subreg");
156 unsigned TV = Table[RC->getID()][Idx];
157 return TV ? getRegClass(i: TV - 1) : nullptr;
158}/// Get the weight in units of pressure for this register class.
159const RegClassWeight &BPFGenRegisterInfo::
160getRegClassWeight(const TargetRegisterClass *RC) const {
161 static const RegClassWeight RCWeightTable[] = {
162 {.RegWeight: 1, .WeightLimit: 12}, // GPR32
163 {.RegWeight: 1, .WeightLimit: 12}, // GPR
164 };
165 return RCWeightTable[RC->getID()];
166}
167
168/// Get the weight in units of pressure for this register unit.
169unsigned BPFGenRegisterInfo::
170getRegUnitWeight(MCRegUnit RegUnit) const {
171 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
172 // All register units have unit weight.
173 return 1;
174}
175
176
177// Get the number of dimensions of register pressure.
178unsigned BPFGenRegisterInfo::getNumRegPressureSets() const {
179 return 1;
180}
181
182// Get the name of this register unit pressure set.
183const char *BPFGenRegisterInfo::
184getRegPressureSetName(unsigned Idx) const {
185 static const char *PressureNameTable[] = {
186 "GPR32",
187 };
188 return PressureNameTable[Idx];
189}
190
191// Get the register unit pressure limit for this dimension.
192// This limit must be adjusted dynamically for reserved registers.
193unsigned BPFGenRegisterInfo::
194getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
195 static const uint8_t PressureLimitTable[] = {
196 12, // 0: GPR32
197 };
198 return PressureLimitTable[Idx];
199}
200
201/// Get the register class for this pressure set with the largest
202/// `RegClassWeight::WeightLimit`.
203const TargetRegisterClass *BPFGenRegisterInfo::
204getLargestRegClassForRegPressureSet(unsigned Idx) const {
205 static const uint8_t PSetRegClassTable[] = {
206 BPF::GPR32RegClassID, // 0: GPR32
207 };
208 return getRegClass(i: PSetRegClassTable[Idx]);
209}
210
211/// Table of pressure sets per register class or unit.
212static const int RCSetsTable[] = {
213 /* 0 */ 0, -1,
214};
215
216/// Get the dimensions of register pressure impacted by this register class.
217/// Returns a -1 terminated array of pressure set IDs
218const int *BPFGenRegisterInfo::
219getRegClassPressureSets(const TargetRegisterClass *RC) const {
220 static const uint8_t RCSetStartTable[] = {
221 0,0,};
222 return &RCSetsTable[RCSetStartTable[RC->getID()]];
223}
224
225/// Get the dimensions of register pressure impacted by this register unit.
226/// Returns a -1 terminated array of pressure set IDs
227const int *BPFGenRegisterInfo::
228getRegUnitPressureSets(MCRegUnit RegUnit) const {
229 assert(static_cast<unsigned>(RegUnit) < 12 && "invalid register unit");
230 static const uint8_t RUSetStartTable[] = {
231 0,0,0,0,0,0,0,0,0,0,0,0,};
232 return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
233}
234
235
236// Register to minimal register class mapping
237
238const TargetRegisterClass *BPFGenRegisterInfo::getMinimalPhysRegClass(MCRegister Reg) const {
239 static const uint16_t InvalidRegClassID = UINT16_MAX;
240
241 static const uint16_t Mapping[25] = {
242 InvalidRegClassID, // NoRegister
243 BPF::GPRRegClassID, // R0
244 BPF::GPRRegClassID, // R1
245 BPF::GPRRegClassID, // R2
246 BPF::GPRRegClassID, // R3
247 BPF::GPRRegClassID, // R4
248 BPF::GPRRegClassID, // R5
249 BPF::GPRRegClassID, // R6
250 BPF::GPRRegClassID, // R7
251 BPF::GPRRegClassID, // R8
252 BPF::GPRRegClassID, // R9
253 BPF::GPRRegClassID, // R10
254 BPF::GPRRegClassID, // R11
255 BPF::GPR32RegClassID, // W0
256 BPF::GPR32RegClassID, // W1
257 BPF::GPR32RegClassID, // W2
258 BPF::GPR32RegClassID, // W3
259 BPF::GPR32RegClassID, // W4
260 BPF::GPR32RegClassID, // W5
261 BPF::GPR32RegClassID, // W6
262 BPF::GPR32RegClassID, // W7
263 BPF::GPR32RegClassID, // W8
264 BPF::GPR32RegClassID, // W9
265 BPF::GPR32RegClassID, // W10
266 BPF::GPR32RegClassID, // W11
267 };
268
269 assert(Reg < ArrayRef(Mapping).size());
270 unsigned RCID = Mapping[Reg.id()];
271 if (RCID == InvalidRegClassID)
272 return nullptr;
273 return &BPFMCRegisterClassStorage.Classes[RCID];
274}
275extern const MCRegisterDesc BPFRegDesc[];
276extern const int16_t BPFRegDiffLists[];
277extern const LaneBitmask BPFLaneMaskLists[];
278extern const char BPFRegStrings[];
279extern const char BPFRegClassStrings[];
280extern const MCPhysReg BPFRegUnitRoots[][2];
281extern const uint16_t BPFSubRegIdxLists[];
282extern const uint16_t BPFRegEncodingTable[];
283// BPF Dwarf<->LLVM register mappings.
284extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0Dwarf2L[];
285extern const unsigned BPFDwarfFlavour0Dwarf2LSize;
286
287extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0Dwarf2L[];
288extern const unsigned BPFEHFlavour0Dwarf2LSize;
289
290extern const MCRegisterInfo::DwarfLLVMRegPair BPFDwarfFlavour0L2Dwarf[];
291extern const unsigned BPFDwarfFlavour0L2DwarfSize;
292
293extern const MCRegisterInfo::DwarfLLVMRegPair BPFEHFlavour0L2Dwarf[];
294extern const unsigned BPFEHFlavour0L2DwarfSize;
295
296
297BPFGenRegisterInfo::
298BPFGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
299 unsigned PC, unsigned HwMode)
300 : TargetRegisterInfo(&BPFRegInfoDesc,
301 BPFSubRegIndexStrings, BPFSubRegIndexNameOffsets,
302 BPFSubRegIdxRangeTable, BPFSubRegIndexLaneMaskTable,
303
304 LaneBitmask(0xFFFFFFFFFFFFFFFE), BPFRegClassInfos, BPFVTLists, HwMode) {
305 InitMCRegisterInfo(D: BPFRegDesc, NR: 25, RA, PC,
306 C: &getBPFMCRegisterClass(RC: 0), NC: 2, RURoots: BPFRegUnitRoots, NRU: 12, DL: BPFRegDiffLists,
307 RUMS: BPFLaneMaskLists, Strings: BPFRegStrings, ClassStrings: BPFRegClassStrings, SubIndices: BPFSubRegIdxLists, NumIndices: 2,
308 RET: BPFRegEncodingTable, RUI: nullptr);
309
310 switch (DwarfFlavour) {
311 default:
312 llvm_unreachable("Unknown DWARF flavour");
313 case 0:
314 mapDwarfRegsToLLVMRegs(Map: BPFDwarfFlavour0Dwarf2L, Size: BPFDwarfFlavour0Dwarf2LSize, isEH: false);
315 break;
316 }
317 switch (EHFlavour) {
318 default:
319 llvm_unreachable("Unknown DWARF flavour");
320 case 0:
321 mapDwarfRegsToLLVMRegs(Map: BPFEHFlavour0Dwarf2L, Size: BPFEHFlavour0Dwarf2LSize, isEH: true);
322 break;
323 }
324 switch (DwarfFlavour) {
325 default:
326 llvm_unreachable("Unknown DWARF flavour");
327 case 0:
328 mapLLVMRegsToDwarfRegs(Map: BPFDwarfFlavour0L2Dwarf, Size: BPFDwarfFlavour0L2DwarfSize, isEH: false);
329 break;
330 }
331 switch (EHFlavour) {
332 default:
333 llvm_unreachable("Unknown DWARF flavour");
334 case 0:
335 mapLLVMRegsToDwarfRegs(Map: BPFEHFlavour0L2Dwarf, Size: BPFEHFlavour0L2DwarfSize, isEH: true);
336 break;
337 }
338}
339
340static const MCPhysReg CSR_SaveList[] = { BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
341static const uint32_t CSR_RegMask[] = { 0x00f80f80, };
342static const MCPhysReg CSR_PreserveAll_SaveList[] = { BPF::R0, BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5, BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, 0 };
343static const uint32_t CSR_PreserveAll_RegMask[] = { 0x00ffeffe, };
344
345
346ArrayRef<const uint32_t *> BPFGenRegisterInfo::getRegMasks() const {
347 static const uint32_t *const Masks[] = {
348 CSR_RegMask,
349 CSR_PreserveAll_RegMask,
350 };
351 return ArrayRef(Masks);
352}
353
354bool BPFGenRegisterInfo::
355isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
356 return
357 false;
358}
359
360bool BPFGenRegisterInfo::
361isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
362 return
363 false;
364}
365
366bool BPFGenRegisterInfo::
367isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
368 return
369 false;
370}
371
372bool BPFGenRegisterInfo::
373isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
374 return
375 false;
376}
377
378bool BPFGenRegisterInfo::
379isConstantPhysReg(MCRegister PhysReg) const {
380 return
381 false;
382}
383
384ArrayRef<const char *> BPFGenRegisterInfo::getRegMaskNames() const {
385 static const char *Names[] = {
386 "CSR",
387 "CSR_PreserveAll",
388 };
389 return ArrayRef(Names);
390}
391
392const BPFFrameLowering *
393BPFGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
394 return static_cast<const BPFFrameLowering *>(
395 MF.getSubtarget().getFrameLowering());
396}
397
398
399} // namespace llvm
400