1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace BPF {
15
16enum {
17 ALU32 = 0,
18 DummyFeature = 1,
19 DwarfRIS = 2,
20 MisalignedMemAccess = 3,
21 NumSubtargetFeatures = 4
22};
23
24} // namespace BPF
25
26} // namespace llvm
27
28#endif // GET_SUBTARGETINFO_ENUM
29
30#ifdef GET_SUBTARGETINFO_MACRO
31
32GET_SUBTARGETINFO_MACRO(AllowsMisalignedMemAccess, false, allowsMisalignedMemAccess)
33GET_SUBTARGETINFO_MACRO(HasAlu32, false, hasAlu32)
34GET_SUBTARGETINFO_MACRO(UseDwarfRIS, false, useDwarfRIS)
35GET_SUBTARGETINFO_MACRO(isDummyMode, false, isDummyMode)
36
37#undef GET_SUBTARGETINFO_MACRO
38#endif // GET_SUBTARGETINFO_MACRO
39
40#ifdef GET_SUBTARGETINFO_MC_DESC
41#undef GET_SUBTARGETINFO_MC_DESC
42
43namespace llvm {
44
45// Sorted (by key) array of values for CPU features.
46extern const llvm::SubtargetFeatureKVStorage< 4, 178> BPFFeatureKVStorage = {
47 {
48 { sizeof(SubtargetFeatureKV) * 4 + 1, sizeof(SubtargetFeatureKV) * 4 + 30, BPF::MisalignedMemAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
49 { sizeof(SubtargetFeatureKV) * 3 + 62, sizeof(SubtargetFeatureKV) * 3 + 68, BPF::ALU32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
50 { sizeof(SubtargetFeatureKV) * 2 + 94, sizeof(SubtargetFeatureKV) * 2 + 100, BPF::DummyFeature, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
51 { sizeof(SubtargetFeatureKV) * 1 + 115, sizeof(SubtargetFeatureKV) * 1 + 124, BPF::DwarfRIS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
52 },
53 "\000allows-misaligned-mem-access\000Allows misaligned memory access\000"
54 "alu32\000Enable ALU32 instructions\000dummy\000unused feature\000dwarfr"
55 "is\000Disable MCAsmInfo DwarfUsesRelocationsAcrossSections\000"};
56
57#ifdef DBGFIELD
58#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
59#endif
60#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
61#define DBGFIELD(x) x,
62#define DBGVAL_OR_NULLPTR(x) x
63#else
64#define DBGFIELD(x)
65#define DBGVAL_OR_NULLPTR(x) nullptr
66#endif
67
68// ===============================================================
69// Data tables for the new per-operand machine model.
70
71static_assert(0 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t");
72static_assert(0 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t");
73
74// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
75extern const llvm::MCWriteProcResEntry BPFWriteProcResTable[] = {
76 { 0, 0, 0 }, // Invalid
77}; // BPFWriteProcResTable
78
79// {Cycles, WriteResourceID}
80extern const llvm::MCWriteLatencyEntry BPFWriteLatencyTable[] = {
81 { 0, 0}, // Invalid
82}; // BPFWriteLatencyTable
83
84// {UseIdx, WriteResourceID, Cycles}
85extern const llvm::MCReadAdvanceEntry BPFReadAdvanceTable[] = {
86 {0, 0, 0}, // Invalid
87}; // BPFReadAdvanceTable
88
89#ifdef __GNUC__
90#pragma GCC diagnostic push
91#pragma GCC diagnostic ignored "-Woverlength-strings"
92#endif
93static constexpr char BPFSchedClassNamesStorage[] =
94 "\0"
95 "InvalidSchedClass\0"
96 ;
97#ifdef __GNUC__
98#pragma GCC diagnostic pop
99#endif
100
101static constexpr llvm::StringTable
102BPFSchedClassNames = BPFSchedClassNamesStorage;
103
104extern const llvm::MCSchedModel BPFSchedModels[] = {
105{ // NoSchedModel
106 MCSchedModel::DefaultIssueWidth,
107 MCSchedModel::DefaultMicroOpBufferSize,
108 MCSchedModel::DefaultLoopMicroOpBufferSize,
109 MCSchedModel::DefaultLoadLatency,
110 MCSchedModel::DefaultHighLatency,
111 MCSchedModel::DefaultMispredictPenalty,
112 false, // PostRAScheduler
113 false, // CompleteModel
114 false, // EnableIntervals
115 0, // Processor ID
116 nullptr, nullptr, 0, 0, // No instruction-level machine model.
117 DBGVAL_OR_NULLPTR(&BPFSchedClassNames), // SchedClassNames
118 nullptr, // No Itinerary
119 nullptr // No extra processor descriptor
120 },
121};
122
123#undef DBGFIELD
124
125#undef DBGVAL_OR_NULLPTR
126
127// Sorted (by key) array of values for CPU subtype.
128extern const llvm::SubtargetSubTypeKVStorage< 6, 28> BPFSubTypeKVStorage = {
129 {
130 { sizeof(SubtargetSubTypeKV) * 6 + 1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
131 { sizeof(SubtargetSubTypeKV) * 5 + 9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
132 { sizeof(SubtargetSubTypeKV) * 4 + 15, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
133 { sizeof(SubtargetSubTypeKV) * 3 + 18, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
134 { sizeof(SubtargetSubTypeKV) * 2 + 21, { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
135 { sizeof(SubtargetSubTypeKV) * 1 + 24, { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 },
136 },
137 "\000generic\000probe\000v1\000v2\000v3\000v4\000"};
138
139namespace BPF_MC {
140
141unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
142 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
143 // Don't know how to resolve this scheduling class.
144 return 0;
145}
146
147} // namespace BPF_MC
148struct BPFGenMCSubtargetInfo : public MCSubtargetInfo {
149 BPFGenMCSubtargetInfo(const Triple &TT,
150 StringRef CPU, StringRef TuneCPU, StringRef FS,
151 StringTable PN,
152 ArrayRef<SubtargetFeatureKV> PF,
153 ArrayRef<SubtargetSubTypeKV> PD,
154 const MCSchedModel *PSM,
155 const MCWriteProcResEntry *WPR,
156 const MCWriteLatencyEntry *WL,
157 const MCReadAdvanceEntry *RA, const InstrStage *IS,
158 const unsigned *OC, const unsigned *FP) :
159 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PSM,
160 WPR, WL, RA, IS, OC, FP) { }
161
162 unsigned resolveVariantSchedClass(unsigned SchedClass,
163 const MCInst *MI, const MCInstrInfo *MCII,
164 unsigned CPUID) const final {
165 return BPF_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
166 }
167};
168
169static inline MCSubtargetInfo *createBPFMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
170 return new BPFGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(BPFSubTypeKVStorage.Strings), BPFFeatureKVStorage.Features, BPFSubTypeKVStorage.SubTypes, BPFSchedModels,
171 BPFWriteProcResTable, BPFWriteLatencyTable, BPFReadAdvanceTable,
172 nullptr, nullptr, nullptr);
173}
174
175
176} // namespace llvm
177
178#endif // GET_SUBTARGETINFO_MC_DESC
179
180#ifdef GET_SUBTARGETINFO_TARGET_DESC
181#undef GET_SUBTARGETINFO_TARGET_DESC
182
183#include "llvm/ADT/BitmaskEnum.h"
184#include "llvm/Support/Debug.h"
185#include "llvm/Support/raw_ostream.h"
186
187// ParseSubtargetFeatures - Parses features string setting specified
188// subtarget options.
189void llvm::BPFSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
190 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
191 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
192 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
193 InitMCProcessorInfo(CPU, TuneCPU, FS);
194 const FeatureBitset &Bits = getFeatureBits();
195 if (Bits[BPF::ALU32]) HasAlu32 = true;
196 if (Bits[BPF::DummyFeature]) isDummyMode = true;
197 if (Bits[BPF::DwarfRIS]) UseDwarfRIS = true;
198 if (Bits[BPF::MisalignedMemAccess]) AllowsMisalignedMemAccess = true;
199}
200
201#endif // GET_SUBTARGETINFO_TARGET_DESC
202
203#ifdef GET_SUBTARGETINFO_HEADER
204#undef GET_SUBTARGETINFO_HEADER
205
206namespace llvm {
207
208class DFAPacketizer;
209namespace BPF_MC {
210
211unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
212
213} // namespace BPF_MC
214struct BPFGenSubtargetInfo : public TargetSubtargetInfo {
215 explicit BPFGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
216public:
217 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
218 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
219 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
220 const FeatureBitset &getInlineIgnoreFeatures() const override;
221 const FeatureBitset &getInlineInverseFeatures() const override;
222 const FeatureBitset &getInlineMustMatchFeatures() const override;
223};
224
225} // namespace llvm
226
227#endif // GET_SUBTARGETINFO_HEADER
228
229#ifdef GET_SUBTARGETINFO_CTOR
230#undef GET_SUBTARGETINFO_CTOR
231
232#include "llvm/CodeGen/TargetSchedule.h"
233
234namespace llvm {
235
236extern const llvm::StringRef BPFNames[];
237extern const llvm::SubtargetFeatureKVStorage<4, 178> BPFFeatureKVStorage;
238extern const llvm::SubtargetSubTypeKVStorage<6, 28> BPFSubTypeKVStorage;
239extern const llvm::MCSchedModel BPFSchedModels[];
240extern const llvm::MCWriteProcResEntry BPFWriteProcResTable[];
241extern const llvm::MCWriteLatencyEntry BPFWriteLatencyTable[];
242extern const llvm::MCReadAdvanceEntry BPFReadAdvanceTable[];
243BPFGenSubtargetInfo::BPFGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
244 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(BPFSubTypeKVStorage.Strings), ArrayRef(BPFFeatureKVStorage.Features), ArrayRef(BPFSubTypeKVStorage.SubTypes), BPFSchedModels,
245 BPFWriteProcResTable, BPFWriteLatencyTable, BPFReadAdvanceTable,
246 nullptr, nullptr, nullptr) {}
247
248unsigned BPFGenSubtargetInfo
249::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
250 report_fatal_error("Expected a variant SchedClass");
251} // BPFGenSubtargetInfo::resolveSchedClass
252
253unsigned BPFGenSubtargetInfo
254::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
255 return BPF_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
256} // BPFGenSubtargetInfo::resolveVariantSchedClass
257
258const FeatureBitset &BPFGenSubtargetInfo::getInlineIgnoreFeatures() const {
259 static constexpr FeatureBitset Features = {
260 };
261 return Features;
262}
263
264const FeatureBitset &BPFGenSubtargetInfo::getInlineInverseFeatures() const {
265 static constexpr FeatureBitset Features = {
266 };
267 return Features;
268}
269
270const FeatureBitset &BPFGenSubtargetInfo::getInlineMustMatchFeatures() const {
271 static constexpr FeatureBitset Features = {
272 };
273 return Features;
274}
275
276
277} // namespace llvm
278
279#endif // GET_SUBTARGETINFO_CTOR
280
281#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
282#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
283
284
285#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
286
287#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
288#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
289
290
291#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
292
293