1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_SUBTARGETINFO_ENUM
10#undef GET_SUBTARGETINFO_ENUM
11
12namespace llvm {
13
14namespace BPF {
15
16enum {
17 ALU32 = 0,
18 DummyFeature = 1,
19 DwarfRIS = 2,
20 MisalignedMemAccess = 3,
21 NumSubtargetFeatures = 4
22};
23
24} // namespace BPF
25
26} // namespace llvm
27
28#endif // GET_SUBTARGETINFO_ENUM
29
30#ifdef GET_SUBTARGETINFO_MACRO
31
32GET_SUBTARGETINFO_MACRO(AllowsMisalignedMemAccess, false, allowsMisalignedMemAccess)
33GET_SUBTARGETINFO_MACRO(HasAlu32, false, hasAlu32)
34GET_SUBTARGETINFO_MACRO(UseDwarfRIS, false, useDwarfRIS)
35GET_SUBTARGETINFO_MACRO(isDummyMode, false, isDummyMode)
36
37#undef GET_SUBTARGETINFO_MACRO
38#endif // GET_SUBTARGETINFO_MACRO
39
40#ifdef GET_SUBTARGETINFO_MC_DESC
41#undef GET_SUBTARGETINFO_MC_DESC
42
43namespace llvm {
44
45// Sorted (by key) array of values for CPU features.
46extern const llvm::SubtargetFeatureKV BPFFeatureKV[] = {
47 { "allows-misaligned-mem-access", "Allows misaligned memory access", BPF::MisalignedMemAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
48 { "alu32", "Enable ALU32 instructions", BPF::ALU32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
49 { "dummy", "unused feature", BPF::DummyFeature, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
50 { "dwarfris", "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections", BPF::DwarfRIS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
51};
52
53#ifdef DBGFIELD
54#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
55#endif
56#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
57#define DBGFIELD(x) x,
58#define DBGVAL_OR_NULLPTR(x) x
59#else
60#define DBGFIELD(x)
61#define DBGVAL_OR_NULLPTR(x) nullptr
62#endif
63
64// ===============================================================
65// Data tables for the new per-operand machine model.
66
67// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
68extern const llvm::MCWriteProcResEntry BPFWriteProcResTable[] = {
69 { 0, 0, 0 }, // Invalid
70}; // BPFWriteProcResTable
71
72// {Cycles, WriteResourceID}
73extern const llvm::MCWriteLatencyEntry BPFWriteLatencyTable[] = {
74 { 0, 0}, // Invalid
75}; // BPFWriteLatencyTable
76
77// {UseIdx, WriteResourceID, Cycles}
78extern const llvm::MCReadAdvanceEntry BPFReadAdvanceTable[] = {
79 {0, 0, 0}, // Invalid
80}; // BPFReadAdvanceTable
81
82#ifdef __GNUC__
83#pragma GCC diagnostic push
84#pragma GCC diagnostic ignored "-Woverlength-strings"
85#endif
86static constexpr char BPFSchedClassNamesStorage[] =
87 "\0"
88 "InvalidSchedClass\0"
89 ;
90#ifdef __GNUC__
91#pragma GCC diagnostic pop
92#endif
93
94static constexpr llvm::StringTable
95BPFSchedClassNames = BPFSchedClassNamesStorage;
96
97static const llvm::MCSchedModel NoSchedModel = {
98 MCSchedModel::DefaultIssueWidth,
99 MCSchedModel::DefaultMicroOpBufferSize,
100 MCSchedModel::DefaultLoopMicroOpBufferSize,
101 MCSchedModel::DefaultLoadLatency,
102 MCSchedModel::DefaultHighLatency,
103 MCSchedModel::DefaultMispredictPenalty,
104 false, // PostRAScheduler
105 false, // CompleteModel
106 false, // EnableIntervals
107 0, // Processor ID
108 nullptr, nullptr, 0, 0, // No instruction-level machine model.
109 DBGVAL_OR_NULLPTR(&BPFSchedClassNames), // SchedClassNames
110 nullptr, // No Itinerary
111 nullptr // No extra processor descriptor
112};
113
114#undef DBGFIELD
115
116#undef DBGVAL_OR_NULLPTR
117
118// Sorted (by key) array of values for CPU subtype.
119extern const llvm::SubtargetSubTypeKV BPFSubTypeKV[] = {
120 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
121 { "probe", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
122 { "v1", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
123 { "v2", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
124 { "v3", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
125 { "v4", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
126};
127
128// Sorted array of names of CPU subtypes, including aliases.
129extern const llvm::StringRef BPFNames[] = {
130"generic",
131"probe",
132"v1",
133"v2",
134"v3",
135"v4"};
136
137namespace BPF_MC {
138
139unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
140 const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) {
141 // Don't know how to resolve this scheduling class.
142 return 0;
143}
144
145} // namespace BPF_MC
146struct BPFGenMCSubtargetInfo : public MCSubtargetInfo {
147 BPFGenMCSubtargetInfo(const Triple &TT,
148 StringRef CPU, StringRef TuneCPU, StringRef FS,
149 ArrayRef<StringRef> PN,
150 ArrayRef<SubtargetFeatureKV> PF,
151 ArrayRef<SubtargetSubTypeKV> PD,
152 const MCWriteProcResEntry *WPR,
153 const MCWriteLatencyEntry *WL,
154 const MCReadAdvanceEntry *RA, const InstrStage *IS,
155 const unsigned *OC, const unsigned *FP) :
156 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD,
157 WPR, WL, RA, IS, OC, FP) { }
158
159 unsigned resolveVariantSchedClass(unsigned SchedClass,
160 const MCInst *MI, const MCInstrInfo *MCII,
161 unsigned CPUID) const final {
162 return BPF_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
163 }
164};
165
166static inline MCSubtargetInfo *createBPFMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
167 return new BPFGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, BPFNames, BPFFeatureKV, BPFSubTypeKV,
168 BPFWriteProcResTable, BPFWriteLatencyTable, BPFReadAdvanceTable,
169 nullptr, nullptr, nullptr);
170}
171
172
173} // namespace llvm
174
175#endif // GET_SUBTARGETINFO_MC_DESC
176
177#ifdef GET_SUBTARGETINFO_TARGET_DESC
178#undef GET_SUBTARGETINFO_TARGET_DESC
179
180#include "llvm/ADT/BitmaskEnum.h"
181#include "llvm/Support/Debug.h"
182#include "llvm/Support/raw_ostream.h"
183
184// ParseSubtargetFeatures - Parses features string setting specified
185// subtarget options.
186void llvm::BPFSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
187 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
188 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
189 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
190 InitMCProcessorInfo(CPU, TuneCPU, FS);
191 const FeatureBitset &Bits = getFeatureBits();
192 if (Bits[BPF::ALU32]) HasAlu32 = true;
193 if (Bits[BPF::DummyFeature]) isDummyMode = true;
194 if (Bits[BPF::DwarfRIS]) UseDwarfRIS = true;
195 if (Bits[BPF::MisalignedMemAccess]) AllowsMisalignedMemAccess = true;
196}
197
198#endif // GET_SUBTARGETINFO_TARGET_DESC
199
200#ifdef GET_SUBTARGETINFO_HEADER
201#undef GET_SUBTARGETINFO_HEADER
202
203namespace llvm {
204
205class DFAPacketizer;
206namespace BPF_MC {
207
208unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID);
209
210} // namespace BPF_MC
211struct BPFGenSubtargetInfo : public TargetSubtargetInfo {
212 explicit BPFGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
213public:
214 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final;
215 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final;
216 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
217};
218
219} // namespace llvm
220
221#endif // GET_SUBTARGETINFO_HEADER
222
223#ifdef GET_SUBTARGETINFO_CTOR
224#undef GET_SUBTARGETINFO_CTOR
225
226#include "llvm/CodeGen/TargetSchedule.h"
227
228namespace llvm {
229
230extern const llvm::StringRef BPFNames[];
231extern const llvm::SubtargetFeatureKV BPFFeatureKV[];
232extern const llvm::SubtargetSubTypeKV BPFSubTypeKV[];
233extern const llvm::MCWriteProcResEntry BPFWriteProcResTable[];
234extern const llvm::MCWriteLatencyEntry BPFWriteLatencyTable[];
235extern const llvm::MCReadAdvanceEntry BPFReadAdvanceTable[];
236BPFGenSubtargetInfo::BPFGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
237 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(BPFNames, 6), ArrayRef(BPFFeatureKV, 4), ArrayRef(BPFSubTypeKV, 6),
238 BPFWriteProcResTable, BPFWriteLatencyTable, BPFReadAdvanceTable,
239 nullptr, nullptr, nullptr) {}
240
241unsigned BPFGenSubtargetInfo
242::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
243 report_fatal_error("Expected a variant SchedClass");
244} // BPFGenSubtargetInfo::resolveSchedClass
245
246unsigned BPFGenSubtargetInfo
247::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
248 return BPF_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
249} // BPFGenSubtargetInfo::resolveVariantSchedClass
250
251
252} // namespace llvm
253
254#endif // GET_SUBTARGETINFO_CTOR
255
256#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
257#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
258
259
260#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
261
262#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
263#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
264
265
266#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
267
268