1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::dxil {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1945
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1937
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1952
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1530
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1543
96 G_INSERT = 81, // GenericOpcodes.td:1552
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1562
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1582
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1592
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1599
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1959
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1288
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1294
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1300
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1306
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1312
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1318
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1324
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1330
114 G_LOAD = 99, // GenericOpcodes.td:1357
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1366
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1374
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1383
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1393
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1402
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1410
121 G_STORE = 106, // GenericOpcodes.td:1418
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1428
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1436
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1447
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1458
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1478
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1479
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1480
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1481
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1482
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1483
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1484
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1485
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1486
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1487
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1488
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1499
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1500
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1501
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1502
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1503
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1504
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1505
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1506
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1489
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1490
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1491
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1492
149 G_FENCE = 134, // GenericOpcodes.td:1508
150 G_PREFETCH = 135, // GenericOpcodes.td:1515
151 G_BRCOND = 136, // GenericOpcodes.td:1655
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1664
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1687
154 G_INTRINSIC = 139, // GenericOpcodes.td:1607
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1614
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1623
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1631
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:609
183 G_UADDE = 168, // GenericOpcodes.td:617
184 G_USUBO = 169, // GenericOpcodes.td:639
185 G_USUBE = 170, // GenericOpcodes.td:645
186 G_SADDO = 171, // GenericOpcodes.td:624
187 G_SADDE = 172, // GenericOpcodes.td:632
188 G_SSUBO = 173, // GenericOpcodes.td:652
189 G_SSUBE = 174, // GenericOpcodes.td:659
190 G_UMULO = 175, // GenericOpcodes.td:666
191 G_SMULO = 176, // GenericOpcodes.td:674
192 G_UMULH = 177, // GenericOpcodes.td:683
193 G_SMULH = 178, // GenericOpcodes.td:692
194 G_UADDSAT = 179, // GenericOpcodes.td:704
195 G_SADDSAT = 180, // GenericOpcodes.td:712
196 G_USUBSAT = 181, // GenericOpcodes.td:720
197 G_SSUBSAT = 182, // GenericOpcodes.td:728
198 G_USHLSAT = 183, // GenericOpcodes.td:736
199 G_SSHLSAT = 184, // GenericOpcodes.td:744
200 G_SMULFIX = 185, // GenericOpcodes.td:756
201 G_UMULFIX = 186, // GenericOpcodes.td:763
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:773
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:780
204 G_SDIVFIX = 189, // GenericOpcodes.td:791
205 G_UDIVFIX = 190, // GenericOpcodes.td:798
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:808
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:815
208 G_FADD = 193, // GenericOpcodes.td:988
209 G_FSUB = 194, // GenericOpcodes.td:996
210 G_FMUL = 195, // GenericOpcodes.td:1004
211 G_FMA = 196, // GenericOpcodes.td:1013
212 G_FMAD = 197, // GenericOpcodes.td:1022
213 G_FDIV = 198, // GenericOpcodes.td:1030
214 G_FREM = 199, // GenericOpcodes.td:1037
215 G_FMODF = 200, // GenericOpcodes.td:1044
216 G_FPOW = 201, // GenericOpcodes.td:1051
217 G_FPOWI = 202, // GenericOpcodes.td:1058
218 G_FEXP = 203, // GenericOpcodes.td:1065
219 G_FEXP2 = 204, // GenericOpcodes.td:1072
220 G_FEXP10 = 205, // GenericOpcodes.td:1079
221 G_FLOG = 206, // GenericOpcodes.td:1086
222 G_FLOG2 = 207, // GenericOpcodes.td:1093
223 G_FLOG10 = 208, // GenericOpcodes.td:1100
224 G_FLDEXP = 209, // GenericOpcodes.td:1107
225 G_FFREXP = 210, // GenericOpcodes.td:1114
226 G_FNEG = 211, // GenericOpcodes.td:826
227 G_FPEXT = 212, // GenericOpcodes.td:832
228 G_FPTRUNC = 213, // GenericOpcodes.td:838
229 G_FPTOSI = 214, // GenericOpcodes.td:844
230 G_FPTOUI = 215, // GenericOpcodes.td:850
231 G_SITOFP = 216, // GenericOpcodes.td:856
232 G_UITOFP = 217, // GenericOpcodes.td:862
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:868
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:874
235 G_FABS = 220, // GenericOpcodes.td:880
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:886
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:899
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:892
239 G_FMINNUM = 224, // GenericOpcodes.td:912
240 G_FMAXNUM = 225, // GenericOpcodes.td:919
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:937
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:944
243 G_FMINIMUM = 228, // GenericOpcodes.td:954
244 G_FMAXIMUM = 229, // GenericOpcodes.td:961
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:969
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:976
247 G_GET_FPENV = 232, // GenericOpcodes.td:1244
248 G_SET_FPENV = 233, // GenericOpcodes.td:1251
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1258
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1265
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1272
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1279
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1336
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1342
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1645
265 G_BRJT = 250, // GenericOpcodes.td:1675
266 G_VSCALE = 251, // GenericOpcodes.td:1573
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1719
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1727
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1735
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1743
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1754
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1762
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1770
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1777
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_FCEIL = 270, // GenericOpcodes.td:1121
286 G_FCOS = 271, // GenericOpcodes.td:1128
287 G_FSIN = 272, // GenericOpcodes.td:1135
288 G_FSINCOS = 273, // GenericOpcodes.td:1142
289 G_FTAN = 274, // GenericOpcodes.td:1149
290 G_FACOS = 275, // GenericOpcodes.td:1156
291 G_FASIN = 276, // GenericOpcodes.td:1163
292 G_FATAN = 277, // GenericOpcodes.td:1170
293 G_FATAN2 = 278, // GenericOpcodes.td:1177
294 G_FCOSH = 279, // GenericOpcodes.td:1184
295 G_FSINH = 280, // GenericOpcodes.td:1191
296 G_FTANH = 281, // GenericOpcodes.td:1198
297 G_FSQRT = 282, // GenericOpcodes.td:1208
298 G_FFLOOR = 283, // GenericOpcodes.td:1215
299 G_FRINT = 284, // GenericOpcodes.td:1222
300 G_FNEARBYINT = 285, // GenericOpcodes.td:1229
301 G_ADDRSPACE_CAST = 286, // GenericOpcodes.td:248
302 G_BLOCK_ADDR = 287, // GenericOpcodes.td:254
303 G_JUMP_TABLE = 288, // GenericOpcodes.td:260
304 G_DYN_STACKALLOC = 289, // GenericOpcodes.td:266
305 G_STACKSAVE = 290, // GenericOpcodes.td:272
306 G_STACKRESTORE = 291, // GenericOpcodes.td:278
307 G_STRICT_FADD = 292, // GenericOpcodes.td:1829
308 G_STRICT_FSUB = 293, // GenericOpcodes.td:1830
309 G_STRICT_FMUL = 294, // GenericOpcodes.td:1831
310 G_STRICT_FDIV = 295, // GenericOpcodes.td:1832
311 G_STRICT_FREM = 296, // GenericOpcodes.td:1833
312 G_STRICT_FMA = 297, // GenericOpcodes.td:1834
313 G_STRICT_FSQRT = 298, // GenericOpcodes.td:1835
314 G_STRICT_FLDEXP = 299, // GenericOpcodes.td:1836
315 G_STRICT_FCMP = 300, // GenericOpcodes.td:1837
316 G_STRICT_FCMPS = 301, // GenericOpcodes.td:1838
317 G_READ_REGISTER = 302, // GenericOpcodes.td:1694
318 G_WRITE_REGISTER = 303, // GenericOpcodes.td:1704
319 G_MEMCPY = 304, // GenericOpcodes.td:1844
320 G_MEMCPY_INLINE = 305, // GenericOpcodes.td:1852
321 G_MEMMOVE = 306, // GenericOpcodes.td:1860
322 G_MEMSET = 307, // GenericOpcodes.td:1868
323 G_BZERO = 308, // GenericOpcodes.td:1875
324 G_MEMSET_INLINE = 309, // GenericOpcodes.td:1882
325 G_TRAP = 310, // GenericOpcodes.td:1892
326 G_DEBUGTRAP = 311, // GenericOpcodes.td:1899
327 G_UBSANTRAP = 312, // GenericOpcodes.td:1905
328 G_VECREDUCE_SEQ_FADD = 313, // GenericOpcodes.td:1793
329 G_VECREDUCE_SEQ_FMUL = 314, // GenericOpcodes.td:1799
330 G_VECREDUCE_FADD = 315, // GenericOpcodes.td:1805
331 G_VECREDUCE_FMUL = 316, // GenericOpcodes.td:1806
332 G_VECREDUCE_FMAX = 317, // GenericOpcodes.td:1808
333 G_VECREDUCE_FMIN = 318, // GenericOpcodes.td:1809
334 G_VECREDUCE_FMAXIMUM = 319, // GenericOpcodes.td:1810
335 G_VECREDUCE_FMINIMUM = 320, // GenericOpcodes.td:1811
336 G_VECREDUCE_FMAXIMUMNUM = 321, // GenericOpcodes.td:1812
337 G_VECREDUCE_FMINIMUMNUM = 322, // GenericOpcodes.td:1813
338 G_VECREDUCE_ADD = 323, // GenericOpcodes.td:1815
339 G_VECREDUCE_MUL = 324, // GenericOpcodes.td:1816
340 G_VECREDUCE_AND = 325, // GenericOpcodes.td:1817
341 G_VECREDUCE_OR = 326, // GenericOpcodes.td:1818
342 G_VECREDUCE_XOR = 327, // GenericOpcodes.td:1819
343 G_VECREDUCE_SMAX = 328, // GenericOpcodes.td:1820
344 G_VECREDUCE_SMIN = 329, // GenericOpcodes.td:1821
345 G_VECREDUCE_UMAX = 330, // GenericOpcodes.td:1822
346 G_VECREDUCE_UMIN = 331, // GenericOpcodes.td:1823
347 G_SBFX = 332, // GenericOpcodes.td:1917
348 G_UBFX = 333, // GenericOpcodes.td:1925
349 DummyInst = 334, // DXILStubs.td:18
350 INSTRUCTION_LIST_END = 335
351 };
352
353} // namespace llvm::dxil
354
355#endif // GET_INSTRINFO_ENUM
356
357#ifdef GET_INSTRINFO_SCHED_ENUM
358#undef GET_INSTRINFO_SCHED_ENUM
359
360namespace llvm::dxil::Sched {
361
362 enum {
363 NoInstrModel = 0,
364 SCHED_LIST_END = 1
365 };
366
367} // namespace llvm::dxil::Sched
368
369#endif // GET_INSTRINFO_SCHED_ENUM
370
371#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
372
373namespace llvm {
374
375struct DirectXInstrTable {
376 MCInstrDesc Insts[335];
377 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
378 MCPhysReg ImplicitOps[1];
379 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
380 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
381 MCOperandInfo OperandInfo[151];
382};
383} // namespace llvm
384
385#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
386
387#ifdef GET_INSTRINFO_MC_DESC
388#undef GET_INSTRINFO_MC_DESC
389
390namespace llvm {
391
392static_assert((sizeof DirectXInstrTable::ImplicitOps + sizeof DirectXInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
393static constexpr unsigned DirectXOpInfoBase = (sizeof DirectXInstrTable::ImplicitOps + sizeof DirectXInstrTable::Padding) / sizeof(MCOperandInfo);
394
395extern const DirectXInstrTable DirectXDescs = {
396 {
397 { 334, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DummyInst
398 { 333, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
399 { 332, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
400 { 331, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
401 { 330, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
402 { 329, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
403 { 328, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
404 { 327, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
405 { 326, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
406 { 325, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
407 { 324, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
408 { 323, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
409 { 322, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
410 { 321, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
411 { 320, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
412 { 319, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
413 { 318, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
414 { 317, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
415 { 316, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
416 { 315, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
417 { 314, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
418 { 313, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
419 { 312, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
420 { 311, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
421 { 310, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
422 { 309, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
423 { 308, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
424 { 307, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
425 { 306, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
426 { 305, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
427 { 304, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
428 { 303, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
429 { 302, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
430 { 301, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
431 { 300, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
432 { 299, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
433 { 298, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
434 { 297, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
435 { 296, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
436 { 295, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
437 { 294, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
438 { 293, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
439 { 292, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
440 { 291, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
441 { 290, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
442 { 289, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
443 { 288, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
444 { 287, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
445 { 286, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
446 { 285, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
447 { 284, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
448 { 283, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
449 { 282, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
450 { 281, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
451 { 280, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
452 { 279, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
453 { 278, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
454 { 277, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
455 { 276, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
456 { 275, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
457 { 274, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
458 { 273, 3, 2, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
459 { 272, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
460 { 271, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
461 { 270, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
462 { 269, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
463 { 268, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
464 { 267, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
465 { 266, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
466 { 265, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
467 { 264, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
468 { 263, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
469 { 262, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
470 { 261, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
471 { 260, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
472 { 259, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
473 { 258, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
474 { 257, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
475 { 256, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
476 { 255, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
477 { 254, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
478 { 253, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
479 { 252, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
480 { 251, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
481 { 250, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
482 { 249, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
483 { 248, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
484 { 247, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
485 { 246, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
486 { 245, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
487 { 244, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
488 { 243, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
489 { 242, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
490 { 241, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
491 { 240, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
492 { 239, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
493 { 238, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
494 { 237, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
495 { 236, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
496 { 235, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
497 { 234, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
498 { 233, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
499 { 232, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
500 { 231, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
501 { 230, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
502 { 229, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
503 { 228, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
504 { 227, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
505 { 226, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
506 { 225, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
507 { 224, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
508 { 223, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
509 { 222, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
510 { 221, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
511 { 220, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
512 { 219, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
513 { 218, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
514 { 217, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
515 { 216, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
516 { 215, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
517 { 214, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
518 { 213, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
519 { 212, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
520 { 211, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
521 { 210, 3, 2, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
522 { 209, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
523 { 208, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
524 { 207, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
525 { 206, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
526 { 205, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
527 { 204, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
528 { 203, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
529 { 202, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
530 { 201, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
531 { 200, 3, 2, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
532 { 199, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
533 { 198, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
534 { 197, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
535 { 196, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
536 { 195, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
537 { 194, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
538 { 193, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
539 { 192, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
540 { 191, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
541 { 190, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
542 { 189, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
543 { 188, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
544 { 187, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
545 { 186, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
546 { 185, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
547 { 184, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
548 { 183, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
549 { 182, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
550 { 181, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
551 { 180, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
552 { 179, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
553 { 178, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
554 { 177, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
555 { 176, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
556 { 175, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
557 { 174, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
558 { 173, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
559 { 172, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
560 { 171, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
561 { 170, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
562 { 169, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
563 { 168, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
564 { 167, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
565 { 166, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
566 { 165, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
567 { 164, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
568 { 163, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
569 { 162, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
570 { 161, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
571 { 160, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
572 { 159, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
573 { 158, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
574 { 157, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
575 { 156, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
576 { 155, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
577 { 154, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
578 { 153, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
579 { 152, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
580 { 151, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
581 { 150, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
582 { 149, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
583 { 148, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
584 { 147, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
585 { 146, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
586 { 145, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
587 { 144, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
588 { 143, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
589 { 142, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
590 { 141, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
591 { 140, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
592 { 139, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
593 { 138, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
594 { 137, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
595 { 136, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
596 { 135, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
597 { 134, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
598 { 133, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
599 { 132, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
600 { 131, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
601 { 130, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
602 { 129, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
603 { 128, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
604 { 127, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
605 { 126, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
606 { 125, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
607 { 124, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
608 { 123, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
609 { 122, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
610 { 121, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
611 { 120, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
612 { 119, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
613 { 118, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
614 { 117, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
615 { 116, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
616 { 115, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
617 { 114, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
618 { 113, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
619 { 112, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
620 { 111, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
621 { 110, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
622 { 109, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
623 { 108, 5, 1, 0, 0, 0, 0, DirectXOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
624 { 107, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
625 { 106, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
626 { 105, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
627 { 104, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
628 { 103, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
629 { 102, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
630 { 101, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
631 { 100, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
632 { 99, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
633 { 98, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
634 { 97, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
635 { 96, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
636 { 95, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
637 { 94, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
638 { 93, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
639 { 92, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
640 { 91, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
641 { 90, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
642 { 89, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
643 { 88, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
644 { 87, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
645 { 86, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
646 { 85, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
647 { 84, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
648 { 83, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
649 { 82, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
650 { 81, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
651 { 80, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
652 { 79, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
653 { 78, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
654 { 77, 5, 1, 0, 0, 0, 0, DirectXOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
655 { 76, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
656 { 75, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
657 { 74, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
658 { 73, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
659 { 72, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
660 { 71, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
661 { 70, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
662 { 69, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
663 { 68, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
664 { 67, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
665 { 66, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
666 { 65, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
667 { 64, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
668 { 63, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
669 { 62, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
670 { 61, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
671 { 60, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
672 { 59, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
673 { 58, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
674 { 57, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
675 { 56, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
676 { 55, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
677 { 54, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
678 { 53, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
679 { 52, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
680 { 51, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
681 { 50, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
682 { 49, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
683 { 48, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
684 { 47, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
685 { 46, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
686 { 45, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
687 { 44, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
688 { 43, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
689 { 42, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14629
690 { 41, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14628
691 { 40, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
692 { 39, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
693 { 38, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
694 { 37, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
695 { 36, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
696 { 35, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
697 { 34, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
698 { 33, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
699 { 32, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14627
700 { 31, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
701 { 30, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14348
702 { 29, 6, 1, 0, 0, 0, 0, DirectXOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
703 { 28, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
704 { 27, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
705 { 26, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
706 { 25, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
707 { 24, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
708 { 23, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
709 { 22, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
710 { 21, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
711 { 20, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
712 { 19, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
713 { 18, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
714 { 17, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
715 { 16, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
716 { 15, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
717 { 14, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
718 { 13, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
719 { 12, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
720 { 11, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
721 { 10, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
722 { 9, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
723 { 8, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
724 { 7, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
725 { 6, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
726 { 5, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
727 { 4, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
728 { 3, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
729 { 2, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
730 { 1, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
731 { 0, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
732 }, {
733 /* 0 */
734 }, {
735 0
736 }, {
737 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
738 /* 1 */
739 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
740 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
741 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
742 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
743 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
744 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
745 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
746 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
747 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
748 /* 28 */ { dxil::DXILClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
749 /* 29 */ { dxil::DXILClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
750 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
751 /* 34 */ { dxil::DXILClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
752 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { dxil::DXILClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
753 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
754 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
755 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
756 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
757 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
758 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
759 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
760 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
761 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
762 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
763 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
764 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
765 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
766 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
767 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
768 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
769 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
770 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
771 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
772 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
773 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
774 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
775 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
776 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
777 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
778 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
779 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
780 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
781 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
782 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
783 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
784 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
785 }
786};
787
788
789#ifdef __GNUC__
790#pragma GCC diagnostic push
791#pragma GCC diagnostic ignored "-Woverlength-strings"
792#endif
793extern const char DirectXInstrNameData[] = {
794 /* 0 */ "G_FLOG10\000"
795 /* 9 */ "G_FEXP10\000"
796 /* 18 */ "G_FLOG2\000"
797 /* 26 */ "G_FATAN2\000"
798 /* 35 */ "G_FEXP2\000"
799 /* 43 */ "G_FMA\000"
800 /* 49 */ "G_STRICT_FMA\000"
801 /* 62 */ "G_FSUB\000"
802 /* 69 */ "G_STRICT_FSUB\000"
803 /* 83 */ "G_ATOMICRMW_FSUB\000"
804 /* 100 */ "G_SUB\000"
805 /* 106 */ "G_ATOMICRMW_SUB\000"
806 /* 122 */ "G_INTRINSIC\000"
807 /* 134 */ "G_FPTRUNC\000"
808 /* 144 */ "G_INTRINSIC_TRUNC\000"
809 /* 162 */ "G_TRUNC\000"
810 /* 170 */ "G_BUILD_VECTOR_TRUNC\000"
811 /* 191 */ "G_DYN_STACKALLOC\000"
812 /* 208 */ "G_FMAD\000"
813 /* 215 */ "G_FPEXTLOAD\000"
814 /* 227 */ "G_INDEXED_SEXTLOAD\000"
815 /* 246 */ "G_SEXTLOAD\000"
816 /* 257 */ "G_INDEXED_ZEXTLOAD\000"
817 /* 276 */ "G_ZEXTLOAD\000"
818 /* 287 */ "G_INDEXED_LOAD\000"
819 /* 302 */ "G_LOAD\000"
820 /* 309 */ "G_VECREDUCE_FADD\000"
821 /* 326 */ "G_FADD\000"
822 /* 333 */ "G_VECREDUCE_SEQ_FADD\000"
823 /* 354 */ "G_STRICT_FADD\000"
824 /* 368 */ "G_ATOMICRMW_FADD\000"
825 /* 385 */ "G_VECREDUCE_ADD\000"
826 /* 401 */ "G_ADD\000"
827 /* 407 */ "G_PTR_ADD\000"
828 /* 417 */ "G_ATOMICRMW_ADD\000"
829 /* 433 */ "G_ATOMICRMW_NAND\000"
830 /* 450 */ "G_VECREDUCE_AND\000"
831 /* 466 */ "G_AND\000"
832 /* 472 */ "G_ATOMICRMW_AND\000"
833 /* 488 */ "LIFETIME_END\000"
834 /* 501 */ "G_BRCOND\000"
835 /* 510 */ "G_ATOMICRMW_USUB_COND\000"
836 /* 532 */ "G_LLROUND\000"
837 /* 542 */ "G_LROUND\000"
838 /* 551 */ "G_INTRINSIC_ROUND\000"
839 /* 569 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
840 /* 595 */ "LOAD_STACK_GUARD\000"
841 /* 612 */ "PSEUDO_PROBE\000"
842 /* 625 */ "G_SSUBE\000"
843 /* 633 */ "G_USUBE\000"
844 /* 641 */ "G_FENCE\000"
845 /* 649 */ "ARITH_FENCE\000"
846 /* 661 */ "REG_SEQUENCE\000"
847 /* 674 */ "G_SADDE\000"
848 /* 682 */ "G_UADDE\000"
849 /* 690 */ "G_GET_FPMODE\000"
850 /* 703 */ "G_RESET_FPMODE\000"
851 /* 718 */ "G_SET_FPMODE\000"
852 /* 731 */ "G_FMINNUM_IEEE\000"
853 /* 746 */ "G_FMAXNUM_IEEE\000"
854 /* 761 */ "G_VSCALE\000"
855 /* 770 */ "G_JUMP_TABLE\000"
856 /* 783 */ "BUNDLE\000"
857 /* 790 */ "G_MEMSET_INLINE\000"
858 /* 806 */ "G_MEMCPY_INLINE\000"
859 /* 822 */ "RELOC_NONE\000"
860 /* 833 */ "LOCAL_ESCAPE\000"
861 /* 846 */ "G_FPTRUNCSTORE\000"
862 /* 861 */ "G_STACKRESTORE\000"
863 /* 876 */ "G_INDEXED_STORE\000"
864 /* 892 */ "G_STORE\000"
865 /* 900 */ "G_BITREVERSE\000"
866 /* 913 */ "FAKE_USE\000"
867 /* 922 */ "DBG_VALUE\000"
868 /* 932 */ "G_GLOBAL_VALUE\000"
869 /* 947 */ "G_PTRAUTH_GLOBAL_VALUE\000"
870 /* 970 */ "CONVERGENCECTRL_GLUE\000"
871 /* 991 */ "G_STACKSAVE\000"
872 /* 1003 */ "G_MEMMOVE\000"
873 /* 1013 */ "G_FREEZE\000"
874 /* 1022 */ "G_FCANONICALIZE\000"
875 /* 1038 */ "G_FMODF\000"
876 /* 1046 */ "INIT_UNDEF\000"
877 /* 1057 */ "G_IMPLICIT_DEF\000"
878 /* 1072 */ "DBG_INSTR_REF\000"
879 /* 1086 */ "G_FNEG\000"
880 /* 1093 */ "EXTRACT_SUBREG\000"
881 /* 1108 */ "INSERT_SUBREG\000"
882 /* 1122 */ "G_SEXT_INREG\000"
883 /* 1135 */ "SUBREG_TO_REG\000"
884 /* 1149 */ "G_ATOMIC_CMPXCHG\000"
885 /* 1166 */ "G_ATOMICRMW_XCHG\000"
886 /* 1183 */ "G_GET_ROUNDING\000"
887 /* 1198 */ "G_SET_ROUNDING\000"
888 /* 1213 */ "G_FLOG\000"
889 /* 1220 */ "G_VAARG\000"
890 /* 1228 */ "PREALLOCATED_ARG\000"
891 /* 1245 */ "G_PREFETCH\000"
892 /* 1256 */ "G_CLMULH\000"
893 /* 1265 */ "G_SMULH\000"
894 /* 1273 */ "G_UMULH\000"
895 /* 1281 */ "G_FTANH\000"
896 /* 1289 */ "G_FSINH\000"
897 /* 1297 */ "G_FCOSH\000"
898 /* 1305 */ "DBG_PHI\000"
899 /* 1313 */ "G_FPTOSI\000"
900 /* 1322 */ "G_FPTOUI\000"
901 /* 1331 */ "G_FPOWI\000"
902 /* 1339 */ "COPY_LANEMASK\000"
903 /* 1353 */ "G_PTRMASK\000"
904 /* 1363 */ "GC_LABEL\000"
905 /* 1372 */ "DBG_LABEL\000"
906 /* 1382 */ "EH_LABEL\000"
907 /* 1391 */ "ANNOTATION_LABEL\000"
908 /* 1408 */ "ICALL_BRANCH_FUNNEL\000"
909 /* 1428 */ "G_FSHL\000"
910 /* 1435 */ "G_SHL\000"
911 /* 1441 */ "G_FCEIL\000"
912 /* 1449 */ "G_SAVGCEIL\000"
913 /* 1460 */ "G_UAVGCEIL\000"
914 /* 1471 */ "PATCHABLE_TAIL_CALL\000"
915 /* 1491 */ "PATCHABLE_TYPED_EVENT_CALL\000"
916 /* 1518 */ "PATCHABLE_EVENT_CALL\000"
917 /* 1539 */ "FENTRY_CALL\000"
918 /* 1551 */ "KILL\000"
919 /* 1556 */ "G_CONSTANT_POOL\000"
920 /* 1572 */ "G_ROTL\000"
921 /* 1579 */ "G_VECREDUCE_FMUL\000"
922 /* 1596 */ "G_FMUL\000"
923 /* 1603 */ "G_VECREDUCE_SEQ_FMUL\000"
924 /* 1624 */ "G_STRICT_FMUL\000"
925 /* 1638 */ "G_CLMUL\000"
926 /* 1646 */ "G_VECREDUCE_MUL\000"
927 /* 1662 */ "G_MUL\000"
928 /* 1668 */ "G_FREM\000"
929 /* 1675 */ "G_STRICT_FREM\000"
930 /* 1689 */ "G_SREM\000"
931 /* 1696 */ "G_UREM\000"
932 /* 1703 */ "G_SDIVREM\000"
933 /* 1713 */ "G_UDIVREM\000"
934 /* 1723 */ "INLINEASM\000"
935 /* 1733 */ "G_VECREDUCE_FMINIMUM\000"
936 /* 1754 */ "G_FMINIMUM\000"
937 /* 1765 */ "G_ATOMICRMW_FMINIMUM\000"
938 /* 1786 */ "G_VECREDUCE_FMAXIMUM\000"
939 /* 1807 */ "G_FMAXIMUM\000"
940 /* 1818 */ "G_ATOMICRMW_FMAXIMUM\000"
941 /* 1839 */ "G_VECREDUCE_FMINIMUMNUM\000"
942 /* 1863 */ "G_FMINIMUMNUM\000"
943 /* 1877 */ "G_ATOMICRMW_FMINIMUMNUM\000"
944 /* 1901 */ "G_VECREDUCE_FMAXIMUMNUM\000"
945 /* 1925 */ "G_FMAXIMUMNUM\000"
946 /* 1939 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
947 /* 1963 */ "G_FMINNUM\000"
948 /* 1973 */ "G_FMAXNUM\000"
949 /* 1983 */ "G_FATAN\000"
950 /* 1991 */ "G_FTAN\000"
951 /* 1998 */ "G_INTRINSIC_ROUNDEVEN\000"
952 /* 2020 */ "G_ASSERT_ALIGN\000"
953 /* 2035 */ "G_FCOPYSIGN\000"
954 /* 2047 */ "G_VECREDUCE_FMIN\000"
955 /* 2064 */ "G_ATOMICRMW_FMIN\000"
956 /* 2081 */ "G_VECREDUCE_SMIN\000"
957 /* 2098 */ "G_SMIN\000"
958 /* 2105 */ "G_VECREDUCE_UMIN\000"
959 /* 2122 */ "G_UMIN\000"
960 /* 2129 */ "G_ATOMICRMW_UMIN\000"
961 /* 2146 */ "G_ATOMICRMW_MIN\000"
962 /* 2162 */ "G_FASIN\000"
963 /* 2170 */ "G_FSIN\000"
964 /* 2177 */ "CFI_INSTRUCTION\000"
965 /* 2193 */ "G_CTLZ_ZERO_POISON\000"
966 /* 2212 */ "G_CTTZ_ZERO_POISON\000"
967 /* 2231 */ "G_SSUBO\000"
968 /* 2239 */ "G_USUBO\000"
969 /* 2247 */ "G_SADDO\000"
970 /* 2255 */ "G_UADDO\000"
971 /* 2263 */ "JUMP_TABLE_DEBUG_INFO\000"
972 /* 2285 */ "G_SMULO\000"
973 /* 2293 */ "G_UMULO\000"
974 /* 2301 */ "G_BZERO\000"
975 /* 2309 */ "STACKMAP\000"
976 /* 2318 */ "G_DEBUGTRAP\000"
977 /* 2330 */ "G_UBSANTRAP\000"
978 /* 2342 */ "G_TRAP\000"
979 /* 2349 */ "G_ATOMICRMW_UDEC_WRAP\000"
980 /* 2371 */ "G_ATOMICRMW_UINC_WRAP\000"
981 /* 2393 */ "G_BSWAP\000"
982 /* 2401 */ "G_SITOFP\000"
983 /* 2410 */ "G_UITOFP\000"
984 /* 2419 */ "G_FCMP\000"
985 /* 2426 */ "G_STRICT_FCMP\000"
986 /* 2440 */ "G_ICMP\000"
987 /* 2447 */ "G_SCMP\000"
988 /* 2454 */ "G_UCMP\000"
989 /* 2461 */ "CONVERGENCECTRL_LOOP\000"
990 /* 2482 */ "G_CTPOP\000"
991 /* 2490 */ "PATCHABLE_OP\000"
992 /* 2503 */ "FAULTING_OP\000"
993 /* 2515 */ "PREALLOCATED_SETUP\000"
994 /* 2534 */ "G_FLDEXP\000"
995 /* 2543 */ "G_STRICT_FLDEXP\000"
996 /* 2559 */ "G_FEXP\000"
997 /* 2566 */ "G_FFREXP\000"
998 /* 2575 */ "G_BR\000"
999 /* 2580 */ "INLINEASM_BR\000"
1000 /* 2593 */ "G_BLOCK_ADDR\000"
1001 /* 2606 */ "MEMBARRIER\000"
1002 /* 2617 */ "G_CONSTANT_FOLD_BARRIER\000"
1003 /* 2641 */ "PATCHABLE_FUNCTION_ENTER\000"
1004 /* 2666 */ "G_READCYCLECOUNTER\000"
1005 /* 2685 */ "G_READSTEADYCOUNTER\000"
1006 /* 2705 */ "G_READ_REGISTER\000"
1007 /* 2721 */ "G_WRITE_REGISTER\000"
1008 /* 2738 */ "G_ASHR\000"
1009 /* 2745 */ "G_FSHR\000"
1010 /* 2752 */ "G_LSHR\000"
1011 /* 2759 */ "CONVERGENCECTRL_ANCHOR\000"
1012 /* 2782 */ "G_FFLOOR\000"
1013 /* 2791 */ "G_SAVGFLOOR\000"
1014 /* 2803 */ "G_UAVGFLOOR\000"
1015 /* 2815 */ "G_EXTRACT_SUBVECTOR\000"
1016 /* 2835 */ "G_INSERT_SUBVECTOR\000"
1017 /* 2854 */ "G_BUILD_VECTOR\000"
1018 /* 2869 */ "G_SHUFFLE_VECTOR\000"
1019 /* 2886 */ "G_STEP_VECTOR\000"
1020 /* 2900 */ "G_SPLAT_VECTOR\000"
1021 /* 2915 */ "G_VECREDUCE_XOR\000"
1022 /* 2931 */ "G_XOR\000"
1023 /* 2937 */ "G_ATOMICRMW_XOR\000"
1024 /* 2953 */ "G_VECREDUCE_OR\000"
1025 /* 2968 */ "G_OR\000"
1026 /* 2973 */ "G_ATOMICRMW_OR\000"
1027 /* 2988 */ "G_ROTR\000"
1028 /* 2995 */ "G_INTTOPTR\000"
1029 /* 3006 */ "G_FABS\000"
1030 /* 3013 */ "G_ABS\000"
1031 /* 3019 */ "G_ABDS\000"
1032 /* 3026 */ "G_UNMERGE_VALUES\000"
1033 /* 3043 */ "G_MERGE_VALUES\000"
1034 /* 3058 */ "G_CTLS\000"
1035 /* 3065 */ "G_FACOS\000"
1036 /* 3073 */ "G_FCOS\000"
1037 /* 3080 */ "G_FSINCOS\000"
1038 /* 3090 */ "G_STRICT_FCMPS\000"
1039 /* 3105 */ "G_CONCAT_VECTORS\000"
1040 /* 3122 */ "COPY_TO_REGCLASS\000"
1041 /* 3139 */ "G_IS_FPCLASS\000"
1042 /* 3152 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1043 /* 3182 */ "G_VECTOR_COMPRESS\000"
1044 /* 3200 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1045 /* 3227 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1046 /* 3265 */ "G_TRUNC_SSAT_S\000"
1047 /* 3280 */ "G_SSUBSAT\000"
1048 /* 3290 */ "G_USUBSAT\000"
1049 /* 3300 */ "G_SADDSAT\000"
1050 /* 3310 */ "G_UADDSAT\000"
1051 /* 3320 */ "G_SSHLSAT\000"
1052 /* 3330 */ "G_USHLSAT\000"
1053 /* 3340 */ "G_SMULFIXSAT\000"
1054 /* 3353 */ "G_UMULFIXSAT\000"
1055 /* 3366 */ "G_SDIVFIXSAT\000"
1056 /* 3379 */ "G_UDIVFIXSAT\000"
1057 /* 3392 */ "G_ATOMICRMW_USUB_SAT\000"
1058 /* 3413 */ "G_FPTOSI_SAT\000"
1059 /* 3426 */ "G_FPTOUI_SAT\000"
1060 /* 3439 */ "G_EXTRACT\000"
1061 /* 3449 */ "G_SELECT\000"
1062 /* 3458 */ "G_BRINDIRECT\000"
1063 /* 3471 */ "PATCHABLE_RET\000"
1064 /* 3485 */ "G_MEMSET\000"
1065 /* 3494 */ "PATCHABLE_FUNCTION_EXIT\000"
1066 /* 3518 */ "G_BRJT\000"
1067 /* 3525 */ "G_EXTRACT_VECTOR_ELT\000"
1068 /* 3546 */ "G_INSERT_VECTOR_ELT\000"
1069 /* 3566 */ "G_FCONSTANT\000"
1070 /* 3578 */ "G_CONSTANT\000"
1071 /* 3589 */ "G_INTRINSIC_CONVERGENT\000"
1072 /* 3612 */ "STATEPOINT\000"
1073 /* 3623 */ "PATCHPOINT\000"
1074 /* 3634 */ "G_PTRTOINT\000"
1075 /* 3645 */ "G_FRINT\000"
1076 /* 3653 */ "G_INTRINSIC_LLRINT\000"
1077 /* 3672 */ "G_INTRINSIC_LRINT\000"
1078 /* 3690 */ "G_FNEARBYINT\000"
1079 /* 3703 */ "G_VASTART\000"
1080 /* 3713 */ "LIFETIME_START\000"
1081 /* 3728 */ "G_INVOKE_REGION_START\000"
1082 /* 3750 */ "G_INSERT\000"
1083 /* 3759 */ "G_FSQRT\000"
1084 /* 3767 */ "G_STRICT_FSQRT\000"
1085 /* 3782 */ "G_BITCAST\000"
1086 /* 3792 */ "G_ADDRSPACE_CAST\000"
1087 /* 3809 */ "DBG_VALUE_LIST\000"
1088 /* 3824 */ "G_FPEXT\000"
1089 /* 3832 */ "G_SEXT\000"
1090 /* 3839 */ "G_ASSERT_SEXT\000"
1091 /* 3853 */ "G_ANYEXT\000"
1092 /* 3862 */ "G_ZEXT\000"
1093 /* 3869 */ "G_ASSERT_ZEXT\000"
1094 /* 3883 */ "G_ABDU\000"
1095 /* 3890 */ "G_TRUNC_SSAT_U\000"
1096 /* 3905 */ "G_TRUNC_USAT_U\000"
1097 /* 3920 */ "G_FDIV\000"
1098 /* 3927 */ "G_STRICT_FDIV\000"
1099 /* 3941 */ "G_SDIV\000"
1100 /* 3948 */ "G_UDIV\000"
1101 /* 3955 */ "G_GET_FPENV\000"
1102 /* 3967 */ "G_RESET_FPENV\000"
1103 /* 3981 */ "G_SET_FPENV\000"
1104 /* 3993 */ "G_FPOW\000"
1105 /* 4000 */ "G_VECREDUCE_FMAX\000"
1106 /* 4017 */ "G_ATOMICRMW_FMAX\000"
1107 /* 4034 */ "G_VECREDUCE_SMAX\000"
1108 /* 4051 */ "G_SMAX\000"
1109 /* 4058 */ "G_VECREDUCE_UMAX\000"
1110 /* 4075 */ "G_UMAX\000"
1111 /* 4082 */ "G_ATOMICRMW_UMAX\000"
1112 /* 4099 */ "G_ATOMICRMW_MAX\000"
1113 /* 4115 */ "G_FRAME_INDEX\000"
1114 /* 4129 */ "G_SBFX\000"
1115 /* 4136 */ "G_UBFX\000"
1116 /* 4143 */ "G_SMULFIX\000"
1117 /* 4153 */ "G_UMULFIX\000"
1118 /* 4163 */ "G_SDIVFIX\000"
1119 /* 4173 */ "G_UDIVFIX\000"
1120 /* 4183 */ "G_MEMCPY\000"
1121 /* 4192 */ "COPY\000"
1122 /* 4197 */ "CONVERGENCECTRL_ENTRY\000"
1123 /* 4219 */ "G_CTLZ\000"
1124 /* 4226 */ "G_CTTZ\000"
1125 /* 4233 */ "DummyInst\000"
1126};
1127#ifdef __GNUC__
1128#pragma GCC diagnostic pop
1129#endif
1130
1131extern const unsigned DirectXInstrNameIndices[] = {
1132 1309U, 1723U, 2580U, 2177U, 1382U, 1363U, 1391U, 1551U,
1133 1093U, 1108U, 1059U, 1046U, 1135U, 3122U, 922U, 3809U,
1134 1072U, 1305U, 1372U, 661U, 4192U, 1339U, 783U, 3713U,
1135 488U, 612U, 649U, 2309U, 1539U, 3623U, 595U, 2515U,
1136 1228U, 3612U, 833U, 2503U, 2490U, 2641U, 3471U, 3494U,
1137 1471U, 1518U, 1491U, 1408U, 913U, 2606U, 2263U, 822U,
1138 4197U, 2759U, 2461U, 970U, 3839U, 3869U, 2020U, 401U,
1139 100U, 1662U, 3941U, 3948U, 1689U, 1696U, 1703U, 1713U,
1140 466U, 2968U, 2931U, 3019U, 3883U, 2803U, 1460U, 2791U,
1141 1449U, 1057U, 1307U, 4115U, 932U, 947U, 1556U, 3439U,
1142 3026U, 3750U, 3043U, 2854U, 170U, 3105U, 3634U, 2995U,
1143 3782U, 1013U, 2617U, 569U, 144U, 551U, 3672U, 3653U,
1144 1998U, 2666U, 2685U, 302U, 246U, 276U, 215U, 287U,
1145 227U, 257U, 892U, 846U, 876U, 3152U, 1149U, 1166U,
1146 417U, 106U, 472U, 433U, 2973U, 2937U, 4099U, 2146U,
1147 4082U, 2129U, 368U, 83U, 4017U, 2064U, 1818U, 1765U,
1148 1939U, 1877U, 2371U, 2349U, 510U, 3392U, 641U, 1245U,
1149 501U, 3458U, 3728U, 122U, 3200U, 3589U, 3227U, 3853U,
1150 162U, 3265U, 3890U, 3905U, 3578U, 3566U, 3703U, 1220U,
1151 3832U, 1122U, 3862U, 1435U, 2752U, 2738U, 1428U, 2745U,
1152 2988U, 1572U, 2440U, 2419U, 2447U, 2454U, 3449U, 2255U,
1153 682U, 2239U, 633U, 2247U, 674U, 2231U, 625U, 2293U,
1154 2285U, 1273U, 1265U, 3310U, 3300U, 3290U, 3280U, 3330U,
1155 3320U, 4143U, 4153U, 3340U, 3353U, 4163U, 4173U, 3366U,
1156 3379U, 326U, 62U, 1596U, 43U, 208U, 3920U, 1668U,
1157 1038U, 3993U, 1331U, 2559U, 35U, 9U, 1213U, 18U,
1158 0U, 2534U, 2566U, 1086U, 3824U, 134U, 1313U, 1322U,
1159 2401U, 2410U, 3413U, 3426U, 3006U, 2035U, 3139U, 1022U,
1160 1963U, 1973U, 731U, 746U, 1754U, 1807U, 1863U, 1925U,
1161 3955U, 3981U, 3967U, 690U, 718U, 703U, 1183U, 1198U,
1162 407U, 1353U, 2098U, 4051U, 2122U, 4075U, 3013U, 542U,
1163 532U, 2575U, 3518U, 761U, 2835U, 2815U, 3546U, 3525U,
1164 2869U, 2900U, 2886U, 3182U, 4226U, 2212U, 4219U, 2193U,
1165 3058U, 2482U, 2393U, 900U, 1638U, 1256U, 1441U, 3073U,
1166 2170U, 3080U, 1991U, 3065U, 2162U, 1983U, 26U, 1297U,
1167 1289U, 1281U, 3759U, 2782U, 3645U, 3690U, 3792U, 2593U,
1168 770U, 191U, 991U, 861U, 354U, 69U, 1624U, 3927U,
1169 1675U, 49U, 3767U, 2543U, 2426U, 3090U, 2705U, 2721U,
1170 4183U, 806U, 1003U, 3485U, 2301U, 790U, 2342U, 2318U,
1171 2330U, 333U, 1603U, 309U, 1579U, 4000U, 2047U, 1786U,
1172 1733U, 1901U, 1839U, 385U, 1646U, 450U, 2953U, 2915U,
1173 4034U, 2081U, 4058U, 2105U, 4129U, 4136U, 4233U,
1174};
1175
1176static inline void InitDirectXMCInstrInfo(MCInstrInfo *II) {
1177 II->InitMCInstrInfo(DirectXDescs.Insts, DirectXInstrNameIndices, DirectXInstrNameData, nullptr, nullptr, 335, nullptr, 0);
1178}
1179
1180
1181} // namespace llvm
1182
1183#endif // GET_INSTRINFO_MC_DESC
1184
1185#ifdef GET_INSTRINFO_HEADER
1186#undef GET_INSTRINFO_HEADER
1187
1188namespace llvm {
1189
1190struct DirectXGenInstrInfo : public TargetInstrInfo {
1191 explicit DirectXGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1192 ~DirectXGenInstrInfo() override = default;
1193};
1194
1195} // namespace llvm
1196
1197namespace llvm::dxil {
1198
1199
1200} // namespace llvm::dxil
1201
1202#endif // GET_INSTRINFO_HEADER
1203
1204#ifdef GET_INSTRINFO_HELPER_DECLS
1205#undef GET_INSTRINFO_HELPER_DECLS
1206
1207
1208#endif // GET_INSTRINFO_HELPER_DECLS
1209
1210#ifdef GET_INSTRINFO_HELPERS
1211#undef GET_INSTRINFO_HELPERS
1212
1213
1214#endif // GET_INSTRINFO_HELPERS
1215
1216#ifdef GET_INSTRINFO_CTOR_DTOR
1217#undef GET_INSTRINFO_CTOR_DTOR
1218
1219namespace llvm {
1220
1221extern const DirectXInstrTable DirectXDescs;
1222extern const unsigned DirectXInstrNameIndices[];
1223extern const char DirectXInstrNameData[];
1224DirectXGenInstrInfo::DirectXGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1225 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1226 InitMCInstrInfo(DirectXDescs.Insts, DirectXInstrNameIndices, DirectXInstrNameData, nullptr, nullptr, 335);
1227}
1228
1229} // namespace llvm
1230
1231#endif // GET_INSTRINFO_CTOR_DTOR
1232
1233#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1234#undef GET_INSTRINFO_MC_HELPER_DECLS
1235
1236namespace llvm {
1237
1238class MCInst;
1239class FeatureBitset;
1240
1241namespace DirectX_MC {
1242
1243void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1244
1245} // namespace DirectX_MC
1246
1247} // namespace llvm
1248
1249#endif // GET_INSTRINFO_MC_HELPER_DECLS
1250
1251#ifdef GET_INSTRINFO_MC_HELPERS
1252#undef GET_INSTRINFO_MC_HELPERS
1253
1254namespace llvm::DirectX_MC {
1255
1256
1257} // namespace llvm::DirectX_MC
1258
1259#endif // GET_INSTRINFO_MC_HELPERS
1260
1261#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1262 defined(GET_AVAILABLE_OPCODE_CHECKER)
1263#define GET_COMPUTE_FEATURES
1264#endif
1265#ifdef GET_COMPUTE_FEATURES
1266#undef GET_COMPUTE_FEATURES
1267
1268namespace llvm::DirectX_MC {
1269
1270// Bits for subtarget features that participate in instruction matching.
1271enum SubtargetFeatureBits : uint8_t {
1272};
1273
1274inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1275 FeatureBitset Features;
1276 return Features;
1277}
1278
1279inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1280 enum : uint8_t {
1281 CEFBS_None,
1282 };
1283
1284 static constexpr FeatureBitset FeatureBitsets[] = {
1285 {}, // CEFBS_None
1286 };
1287 static constexpr uint8_t RequiredFeaturesRefs[] = {
1288 CEFBS_None, // PHI
1289 CEFBS_None, // INLINEASM
1290 CEFBS_None, // INLINEASM_BR
1291 CEFBS_None, // CFI_INSTRUCTION
1292 CEFBS_None, // EH_LABEL
1293 CEFBS_None, // GC_LABEL
1294 CEFBS_None, // ANNOTATION_LABEL
1295 CEFBS_None, // KILL
1296 CEFBS_None, // EXTRACT_SUBREG
1297 CEFBS_None, // INSERT_SUBREG
1298 CEFBS_None, // IMPLICIT_DEF
1299 CEFBS_None, // INIT_UNDEF
1300 CEFBS_None, // SUBREG_TO_REG
1301 CEFBS_None, // COPY_TO_REGCLASS
1302 CEFBS_None, // DBG_VALUE
1303 CEFBS_None, // DBG_VALUE_LIST
1304 CEFBS_None, // DBG_INSTR_REF
1305 CEFBS_None, // DBG_PHI
1306 CEFBS_None, // DBG_LABEL
1307 CEFBS_None, // REG_SEQUENCE
1308 CEFBS_None, // COPY
1309 CEFBS_None, // COPY_LANEMASK
1310 CEFBS_None, // BUNDLE
1311 CEFBS_None, // LIFETIME_START
1312 CEFBS_None, // LIFETIME_END
1313 CEFBS_None, // PSEUDO_PROBE
1314 CEFBS_None, // ARITH_FENCE
1315 CEFBS_None, // STACKMAP
1316 CEFBS_None, // FENTRY_CALL
1317 CEFBS_None, // PATCHPOINT
1318 CEFBS_None, // LOAD_STACK_GUARD
1319 CEFBS_None, // PREALLOCATED_SETUP
1320 CEFBS_None, // PREALLOCATED_ARG
1321 CEFBS_None, // STATEPOINT
1322 CEFBS_None, // LOCAL_ESCAPE
1323 CEFBS_None, // FAULTING_OP
1324 CEFBS_None, // PATCHABLE_OP
1325 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1326 CEFBS_None, // PATCHABLE_RET
1327 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1328 CEFBS_None, // PATCHABLE_TAIL_CALL
1329 CEFBS_None, // PATCHABLE_EVENT_CALL
1330 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1331 CEFBS_None, // ICALL_BRANCH_FUNNEL
1332 CEFBS_None, // FAKE_USE
1333 CEFBS_None, // MEMBARRIER
1334 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1335 CEFBS_None, // RELOC_NONE
1336 CEFBS_None, // CONVERGENCECTRL_ENTRY
1337 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1338 CEFBS_None, // CONVERGENCECTRL_LOOP
1339 CEFBS_None, // CONVERGENCECTRL_GLUE
1340 CEFBS_None, // G_ASSERT_SEXT
1341 CEFBS_None, // G_ASSERT_ZEXT
1342 CEFBS_None, // G_ASSERT_ALIGN
1343 CEFBS_None, // G_ADD
1344 CEFBS_None, // G_SUB
1345 CEFBS_None, // G_MUL
1346 CEFBS_None, // G_SDIV
1347 CEFBS_None, // G_UDIV
1348 CEFBS_None, // G_SREM
1349 CEFBS_None, // G_UREM
1350 CEFBS_None, // G_SDIVREM
1351 CEFBS_None, // G_UDIVREM
1352 CEFBS_None, // G_AND
1353 CEFBS_None, // G_OR
1354 CEFBS_None, // G_XOR
1355 CEFBS_None, // G_ABDS
1356 CEFBS_None, // G_ABDU
1357 CEFBS_None, // G_UAVGFLOOR
1358 CEFBS_None, // G_UAVGCEIL
1359 CEFBS_None, // G_SAVGFLOOR
1360 CEFBS_None, // G_SAVGCEIL
1361 CEFBS_None, // G_IMPLICIT_DEF
1362 CEFBS_None, // G_PHI
1363 CEFBS_None, // G_FRAME_INDEX
1364 CEFBS_None, // G_GLOBAL_VALUE
1365 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
1366 CEFBS_None, // G_CONSTANT_POOL
1367 CEFBS_None, // G_EXTRACT
1368 CEFBS_None, // G_UNMERGE_VALUES
1369 CEFBS_None, // G_INSERT
1370 CEFBS_None, // G_MERGE_VALUES
1371 CEFBS_None, // G_BUILD_VECTOR
1372 CEFBS_None, // G_BUILD_VECTOR_TRUNC
1373 CEFBS_None, // G_CONCAT_VECTORS
1374 CEFBS_None, // G_PTRTOINT
1375 CEFBS_None, // G_INTTOPTR
1376 CEFBS_None, // G_BITCAST
1377 CEFBS_None, // G_FREEZE
1378 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
1379 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
1380 CEFBS_None, // G_INTRINSIC_TRUNC
1381 CEFBS_None, // G_INTRINSIC_ROUND
1382 CEFBS_None, // G_INTRINSIC_LRINT
1383 CEFBS_None, // G_INTRINSIC_LLRINT
1384 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
1385 CEFBS_None, // G_READCYCLECOUNTER
1386 CEFBS_None, // G_READSTEADYCOUNTER
1387 CEFBS_None, // G_LOAD
1388 CEFBS_None, // G_SEXTLOAD
1389 CEFBS_None, // G_ZEXTLOAD
1390 CEFBS_None, // G_FPEXTLOAD
1391 CEFBS_None, // G_INDEXED_LOAD
1392 CEFBS_None, // G_INDEXED_SEXTLOAD
1393 CEFBS_None, // G_INDEXED_ZEXTLOAD
1394 CEFBS_None, // G_STORE
1395 CEFBS_None, // G_FPTRUNCSTORE
1396 CEFBS_None, // G_INDEXED_STORE
1397 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1398 CEFBS_None, // G_ATOMIC_CMPXCHG
1399 CEFBS_None, // G_ATOMICRMW_XCHG
1400 CEFBS_None, // G_ATOMICRMW_ADD
1401 CEFBS_None, // G_ATOMICRMW_SUB
1402 CEFBS_None, // G_ATOMICRMW_AND
1403 CEFBS_None, // G_ATOMICRMW_NAND
1404 CEFBS_None, // G_ATOMICRMW_OR
1405 CEFBS_None, // G_ATOMICRMW_XOR
1406 CEFBS_None, // G_ATOMICRMW_MAX
1407 CEFBS_None, // G_ATOMICRMW_MIN
1408 CEFBS_None, // G_ATOMICRMW_UMAX
1409 CEFBS_None, // G_ATOMICRMW_UMIN
1410 CEFBS_None, // G_ATOMICRMW_FADD
1411 CEFBS_None, // G_ATOMICRMW_FSUB
1412 CEFBS_None, // G_ATOMICRMW_FMAX
1413 CEFBS_None, // G_ATOMICRMW_FMIN
1414 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
1415 CEFBS_None, // G_ATOMICRMW_FMINIMUM
1416 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
1417 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
1418 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
1419 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
1420 CEFBS_None, // G_ATOMICRMW_USUB_COND
1421 CEFBS_None, // G_ATOMICRMW_USUB_SAT
1422 CEFBS_None, // G_FENCE
1423 CEFBS_None, // G_PREFETCH
1424 CEFBS_None, // G_BRCOND
1425 CEFBS_None, // G_BRINDIRECT
1426 CEFBS_None, // G_INVOKE_REGION_START
1427 CEFBS_None, // G_INTRINSIC
1428 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
1429 CEFBS_None, // G_INTRINSIC_CONVERGENT
1430 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1431 CEFBS_None, // G_ANYEXT
1432 CEFBS_None, // G_TRUNC
1433 CEFBS_None, // G_TRUNC_SSAT_S
1434 CEFBS_None, // G_TRUNC_SSAT_U
1435 CEFBS_None, // G_TRUNC_USAT_U
1436 CEFBS_None, // G_CONSTANT
1437 CEFBS_None, // G_FCONSTANT
1438 CEFBS_None, // G_VASTART
1439 CEFBS_None, // G_VAARG
1440 CEFBS_None, // G_SEXT
1441 CEFBS_None, // G_SEXT_INREG
1442 CEFBS_None, // G_ZEXT
1443 CEFBS_None, // G_SHL
1444 CEFBS_None, // G_LSHR
1445 CEFBS_None, // G_ASHR
1446 CEFBS_None, // G_FSHL
1447 CEFBS_None, // G_FSHR
1448 CEFBS_None, // G_ROTR
1449 CEFBS_None, // G_ROTL
1450 CEFBS_None, // G_ICMP
1451 CEFBS_None, // G_FCMP
1452 CEFBS_None, // G_SCMP
1453 CEFBS_None, // G_UCMP
1454 CEFBS_None, // G_SELECT
1455 CEFBS_None, // G_UADDO
1456 CEFBS_None, // G_UADDE
1457 CEFBS_None, // G_USUBO
1458 CEFBS_None, // G_USUBE
1459 CEFBS_None, // G_SADDO
1460 CEFBS_None, // G_SADDE
1461 CEFBS_None, // G_SSUBO
1462 CEFBS_None, // G_SSUBE
1463 CEFBS_None, // G_UMULO
1464 CEFBS_None, // G_SMULO
1465 CEFBS_None, // G_UMULH
1466 CEFBS_None, // G_SMULH
1467 CEFBS_None, // G_UADDSAT
1468 CEFBS_None, // G_SADDSAT
1469 CEFBS_None, // G_USUBSAT
1470 CEFBS_None, // G_SSUBSAT
1471 CEFBS_None, // G_USHLSAT
1472 CEFBS_None, // G_SSHLSAT
1473 CEFBS_None, // G_SMULFIX
1474 CEFBS_None, // G_UMULFIX
1475 CEFBS_None, // G_SMULFIXSAT
1476 CEFBS_None, // G_UMULFIXSAT
1477 CEFBS_None, // G_SDIVFIX
1478 CEFBS_None, // G_UDIVFIX
1479 CEFBS_None, // G_SDIVFIXSAT
1480 CEFBS_None, // G_UDIVFIXSAT
1481 CEFBS_None, // G_FADD
1482 CEFBS_None, // G_FSUB
1483 CEFBS_None, // G_FMUL
1484 CEFBS_None, // G_FMA
1485 CEFBS_None, // G_FMAD
1486 CEFBS_None, // G_FDIV
1487 CEFBS_None, // G_FREM
1488 CEFBS_None, // G_FMODF
1489 CEFBS_None, // G_FPOW
1490 CEFBS_None, // G_FPOWI
1491 CEFBS_None, // G_FEXP
1492 CEFBS_None, // G_FEXP2
1493 CEFBS_None, // G_FEXP10
1494 CEFBS_None, // G_FLOG
1495 CEFBS_None, // G_FLOG2
1496 CEFBS_None, // G_FLOG10
1497 CEFBS_None, // G_FLDEXP
1498 CEFBS_None, // G_FFREXP
1499 CEFBS_None, // G_FNEG
1500 CEFBS_None, // G_FPEXT
1501 CEFBS_None, // G_FPTRUNC
1502 CEFBS_None, // G_FPTOSI
1503 CEFBS_None, // G_FPTOUI
1504 CEFBS_None, // G_SITOFP
1505 CEFBS_None, // G_UITOFP
1506 CEFBS_None, // G_FPTOSI_SAT
1507 CEFBS_None, // G_FPTOUI_SAT
1508 CEFBS_None, // G_FABS
1509 CEFBS_None, // G_FCOPYSIGN
1510 CEFBS_None, // G_IS_FPCLASS
1511 CEFBS_None, // G_FCANONICALIZE
1512 CEFBS_None, // G_FMINNUM
1513 CEFBS_None, // G_FMAXNUM
1514 CEFBS_None, // G_FMINNUM_IEEE
1515 CEFBS_None, // G_FMAXNUM_IEEE
1516 CEFBS_None, // G_FMINIMUM
1517 CEFBS_None, // G_FMAXIMUM
1518 CEFBS_None, // G_FMINIMUMNUM
1519 CEFBS_None, // G_FMAXIMUMNUM
1520 CEFBS_None, // G_GET_FPENV
1521 CEFBS_None, // G_SET_FPENV
1522 CEFBS_None, // G_RESET_FPENV
1523 CEFBS_None, // G_GET_FPMODE
1524 CEFBS_None, // G_SET_FPMODE
1525 CEFBS_None, // G_RESET_FPMODE
1526 CEFBS_None, // G_GET_ROUNDING
1527 CEFBS_None, // G_SET_ROUNDING
1528 CEFBS_None, // G_PTR_ADD
1529 CEFBS_None, // G_PTRMASK
1530 CEFBS_None, // G_SMIN
1531 CEFBS_None, // G_SMAX
1532 CEFBS_None, // G_UMIN
1533 CEFBS_None, // G_UMAX
1534 CEFBS_None, // G_ABS
1535 CEFBS_None, // G_LROUND
1536 CEFBS_None, // G_LLROUND
1537 CEFBS_None, // G_BR
1538 CEFBS_None, // G_BRJT
1539 CEFBS_None, // G_VSCALE
1540 CEFBS_None, // G_INSERT_SUBVECTOR
1541 CEFBS_None, // G_EXTRACT_SUBVECTOR
1542 CEFBS_None, // G_INSERT_VECTOR_ELT
1543 CEFBS_None, // G_EXTRACT_VECTOR_ELT
1544 CEFBS_None, // G_SHUFFLE_VECTOR
1545 CEFBS_None, // G_SPLAT_VECTOR
1546 CEFBS_None, // G_STEP_VECTOR
1547 CEFBS_None, // G_VECTOR_COMPRESS
1548 CEFBS_None, // G_CTTZ
1549 CEFBS_None, // G_CTTZ_ZERO_POISON
1550 CEFBS_None, // G_CTLZ
1551 CEFBS_None, // G_CTLZ_ZERO_POISON
1552 CEFBS_None, // G_CTLS
1553 CEFBS_None, // G_CTPOP
1554 CEFBS_None, // G_BSWAP
1555 CEFBS_None, // G_BITREVERSE
1556 CEFBS_None, // G_CLMUL
1557 CEFBS_None, // G_CLMULH
1558 CEFBS_None, // G_FCEIL
1559 CEFBS_None, // G_FCOS
1560 CEFBS_None, // G_FSIN
1561 CEFBS_None, // G_FSINCOS
1562 CEFBS_None, // G_FTAN
1563 CEFBS_None, // G_FACOS
1564 CEFBS_None, // G_FASIN
1565 CEFBS_None, // G_FATAN
1566 CEFBS_None, // G_FATAN2
1567 CEFBS_None, // G_FCOSH
1568 CEFBS_None, // G_FSINH
1569 CEFBS_None, // G_FTANH
1570 CEFBS_None, // G_FSQRT
1571 CEFBS_None, // G_FFLOOR
1572 CEFBS_None, // G_FRINT
1573 CEFBS_None, // G_FNEARBYINT
1574 CEFBS_None, // G_ADDRSPACE_CAST
1575 CEFBS_None, // G_BLOCK_ADDR
1576 CEFBS_None, // G_JUMP_TABLE
1577 CEFBS_None, // G_DYN_STACKALLOC
1578 CEFBS_None, // G_STACKSAVE
1579 CEFBS_None, // G_STACKRESTORE
1580 CEFBS_None, // G_STRICT_FADD
1581 CEFBS_None, // G_STRICT_FSUB
1582 CEFBS_None, // G_STRICT_FMUL
1583 CEFBS_None, // G_STRICT_FDIV
1584 CEFBS_None, // G_STRICT_FREM
1585 CEFBS_None, // G_STRICT_FMA
1586 CEFBS_None, // G_STRICT_FSQRT
1587 CEFBS_None, // G_STRICT_FLDEXP
1588 CEFBS_None, // G_STRICT_FCMP
1589 CEFBS_None, // G_STRICT_FCMPS
1590 CEFBS_None, // G_READ_REGISTER
1591 CEFBS_None, // G_WRITE_REGISTER
1592 CEFBS_None, // G_MEMCPY
1593 CEFBS_None, // G_MEMCPY_INLINE
1594 CEFBS_None, // G_MEMMOVE
1595 CEFBS_None, // G_MEMSET
1596 CEFBS_None, // G_BZERO
1597 CEFBS_None, // G_MEMSET_INLINE
1598 CEFBS_None, // G_TRAP
1599 CEFBS_None, // G_DEBUGTRAP
1600 CEFBS_None, // G_UBSANTRAP
1601 CEFBS_None, // G_VECREDUCE_SEQ_FADD
1602 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
1603 CEFBS_None, // G_VECREDUCE_FADD
1604 CEFBS_None, // G_VECREDUCE_FMUL
1605 CEFBS_None, // G_VECREDUCE_FMAX
1606 CEFBS_None, // G_VECREDUCE_FMIN
1607 CEFBS_None, // G_VECREDUCE_FMAXIMUM
1608 CEFBS_None, // G_VECREDUCE_FMINIMUM
1609 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
1610 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
1611 CEFBS_None, // G_VECREDUCE_ADD
1612 CEFBS_None, // G_VECREDUCE_MUL
1613 CEFBS_None, // G_VECREDUCE_AND
1614 CEFBS_None, // G_VECREDUCE_OR
1615 CEFBS_None, // G_VECREDUCE_XOR
1616 CEFBS_None, // G_VECREDUCE_SMAX
1617 CEFBS_None, // G_VECREDUCE_SMIN
1618 CEFBS_None, // G_VECREDUCE_UMAX
1619 CEFBS_None, // G_VECREDUCE_UMIN
1620 CEFBS_None, // G_SBFX
1621 CEFBS_None, // G_UBFX
1622 CEFBS_None, // DummyInst
1623 };
1624
1625 assert(Opcode < 335);
1626 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
1627}
1628
1629
1630} // namespace llvm::DirectX_MC
1631
1632#endif // GET_COMPUTE_FEATURES
1633
1634#ifdef GET_AVAILABLE_OPCODE_CHECKER
1635#undef GET_AVAILABLE_OPCODE_CHECKER
1636
1637namespace llvm::DirectX_MC {
1638
1639bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
1640 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
1641 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
1642 FeatureBitset MissingFeatures =
1643 (AvailableFeatures & RequiredFeatures) ^
1644 RequiredFeatures;
1645 return !MissingFeatures.any();
1646}
1647
1648} // namespace llvm::DirectX_MC
1649
1650#endif // GET_AVAILABLE_OPCODE_CHECKER
1651
1652#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
1653#undef ENABLE_INSTR_PREDICATE_VERIFIER
1654
1655#include <sstream>
1656
1657namespace llvm::DirectX_MC {
1658
1659#ifndef NDEBUG
1660static const char *SubtargetFeatureNames[] = {
1661 nullptr
1662};
1663
1664#endif // NDEBUG
1665
1666void verifyInstructionPredicates(
1667 unsigned Opcode, const FeatureBitset &Features) {
1668#ifndef NDEBUG
1669 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
1670 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
1671 FeatureBitset MissingFeatures =
1672 (AvailableFeatures & RequiredFeatures) ^
1673 RequiredFeatures;
1674 if (MissingFeatures.any()) {
1675 std::ostringstream Msg;
1676 Msg << "Attempting to emit " << &DirectXInstrNameData[DirectXInstrNameIndices[Opcode]]
1677 << " instruction but the ";
1678 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
1679 if (MissingFeatures.test(i))
1680 Msg << SubtargetFeatureNames[i] << " ";
1681 Msg << "predicate(s) are not met";
1682 report_fatal_error(Msg.str().c_str());
1683 }
1684#endif // NDEBUG
1685}
1686
1687} // namespace llvm::DirectX_MC
1688
1689#endif // ENABLE_INSTR_PREDICATE_VERIFIER
1690
1691