1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11
12namespace llvm::dxil {
13
14 enum {
15 PHI = 0, // Target.td:1314
16 INLINEASM = 1, // Target.td:1320
17 INLINEASM_BR = 2, // Target.td:1326
18 CFI_INSTRUCTION = 3, // Target.td:1335
19 EH_LABEL = 4, // Target.td:1344
20 GC_LABEL = 5, // Target.td:1353
21 ANNOTATION_LABEL = 6, // Target.td:1362
22 KILL = 7, // Target.td:1370
23 EXTRACT_SUBREG = 8, // Target.td:1377
24 INSERT_SUBREG = 9, // Target.td:1383
25 IMPLICIT_DEF = 10, // Target.td:1390
26 INIT_UNDEF = 11, // Target.td:1399
27 SUBREG_TO_REG = 12, // Target.td:1406
28 COPY_TO_REGCLASS = 13, // Target.td:1412
29 DBG_VALUE = 14, // Target.td:1419
30 DBG_VALUE_LIST = 15, // Target.td:1426
31 DBG_INSTR_REF = 16, // Target.td:1433
32 DBG_PHI = 17, // Target.td:1440
33 DBG_LABEL = 18, // Target.td:1447
34 REG_SEQUENCE = 19, // Target.td:1454
35 COPY = 20, // Target.td:1461
36 COPY_LANEMASK = 21, // Target.td:1469
37 BUNDLE = 22, // Target.td:1476
38 LIFETIME_START = 23, // Target.td:1482
39 LIFETIME_END = 24, // Target.td:1489
40 PSEUDO_PROBE = 25, // Target.td:1496
41 ARITH_FENCE = 26, // Target.td:1503
42 STACKMAP = 27, // Target.td:1512
43 FENTRY_CALL = 28, // Target.td:1647
44 PATCHPOINT = 29, // Target.td:1520
45 LOAD_STACK_GUARD = 30, // Target.td:1538
46 PREALLOCATED_SETUP = 31, // Target.td:1546
47 PREALLOCATED_ARG = 32, // Target.td:1552
48 STATEPOINT = 33, // Target.td:1529
49 LOCAL_ESCAPE = 34, // Target.td:1558
50 FAULTING_OP = 35, // Target.td:1567
51 PATCHABLE_OP = 36, // Target.td:1587
52 PATCHABLE_FUNCTION_ENTER = 37, // Target.td:1595
53 PATCHABLE_RET = 38, // Target.td:1602
54 PATCHABLE_FUNCTION_EXIT = 39, // Target.td:1611
55 PATCHABLE_TAIL_CALL = 40, // Target.td:1619
56 PATCHABLE_EVENT_CALL = 41, // Target.td:1627
57 PATCHABLE_TYPED_EVENT_CALL = 42, // Target.td:1637
58 ICALL_BRANCH_FUNNEL = 43, // Target.td:1657
59 FAKE_USE = 44, // Target.td:1577
60 MEMBARRIER = 45, // Target.td:1663
61 JUMP_TABLE_DEBUG_INFO = 46, // Target.td:1671
62 RELOC_NONE = 47, // Target.td:1679
63 CONVERGENCECTRL_ENTRY = 48, // Target.td:1691
64 CONVERGENCECTRL_ANCHOR = 49, // Target.td:1687
65 CONVERGENCECTRL_LOOP = 50, // Target.td:1695
66 CONVERGENCECTRL_GLUE = 51, // Target.td:1699
67 G_ASSERT_SEXT = 52, // GenericOpcodes.td:1955
68 G_ASSERT_ZEXT = 53, // GenericOpcodes.td:1947
69 G_ASSERT_ALIGN = 54, // GenericOpcodes.td:1962
70 G_ADD = 55, // GenericOpcodes.td:308
71 G_SUB = 56, // GenericOpcodes.td:316
72 G_MUL = 57, // GenericOpcodes.td:324
73 G_SDIV = 58, // GenericOpcodes.td:332
74 G_UDIV = 59, // GenericOpcodes.td:340
75 G_SREM = 60, // GenericOpcodes.td:348
76 G_UREM = 61, // GenericOpcodes.td:356
77 G_SDIVREM = 62, // GenericOpcodes.td:364
78 G_UDIVREM = 63, // GenericOpcodes.td:372
79 G_AND = 64, // GenericOpcodes.td:380
80 G_OR = 65, // GenericOpcodes.td:388
81 G_XOR = 66, // GenericOpcodes.td:396
82 G_ABDS = 67, // GenericOpcodes.td:425
83 G_ABDU = 68, // GenericOpcodes.td:433
84 G_UAVGFLOOR = 69, // GenericOpcodes.td:441
85 G_UAVGCEIL = 70, // GenericOpcodes.td:448
86 G_SAVGFLOOR = 71, // GenericOpcodes.td:455
87 G_SAVGCEIL = 72, // GenericOpcodes.td:462
88 G_IMPLICIT_DEF = 73, // GenericOpcodes.td:111
89 G_PHI = 74, // GenericOpcodes.td:118
90 G_FRAME_INDEX = 75, // GenericOpcodes.td:125
91 G_GLOBAL_VALUE = 76, // GenericOpcodes.td:131
92 G_PTRAUTH_GLOBAL_VALUE = 77, // GenericOpcodes.td:137
93 G_CONSTANT_POOL = 78, // GenericOpcodes.td:143
94 G_EXTRACT = 79, // GenericOpcodes.td:1540
95 G_UNMERGE_VALUES = 80, // GenericOpcodes.td:1553
96 G_INSERT = 81, // GenericOpcodes.td:1562
97 G_MERGE_VALUES = 82, // GenericOpcodes.td:1572
98 G_BUILD_VECTOR = 83, // GenericOpcodes.td:1592
99 G_BUILD_VECTOR_TRUNC = 84, // GenericOpcodes.td:1602
100 G_CONCAT_VECTORS = 85, // GenericOpcodes.td:1609
101 G_PTRTOINT = 86, // GenericOpcodes.td:155
102 G_INTTOPTR = 87, // GenericOpcodes.td:149
103 G_BITCAST = 88, // GenericOpcodes.td:161
104 G_FREEZE = 89, // GenericOpcodes.td:284
105 G_CONSTANT_FOLD_BARRIER = 90, // GenericOpcodes.td:1969
106 G_INTRINSIC_FPTRUNC_ROUND = 91, // GenericOpcodes.td:1298
107 G_INTRINSIC_TRUNC = 92, // GenericOpcodes.td:1304
108 G_INTRINSIC_ROUND = 93, // GenericOpcodes.td:1310
109 G_INTRINSIC_LRINT = 94, // GenericOpcodes.td:1316
110 G_INTRINSIC_LLRINT = 95, // GenericOpcodes.td:1322
111 G_INTRINSIC_ROUNDEVEN = 96, // GenericOpcodes.td:1328
112 G_READCYCLECOUNTER = 97, // GenericOpcodes.td:1334
113 G_READSTEADYCOUNTER = 98, // GenericOpcodes.td:1340
114 G_LOAD = 99, // GenericOpcodes.td:1367
115 G_SEXTLOAD = 100, // GenericOpcodes.td:1376
116 G_ZEXTLOAD = 101, // GenericOpcodes.td:1384
117 G_FPEXTLOAD = 102, // GenericOpcodes.td:1393
118 G_INDEXED_LOAD = 103, // GenericOpcodes.td:1403
119 G_INDEXED_SEXTLOAD = 104, // GenericOpcodes.td:1412
120 G_INDEXED_ZEXTLOAD = 105, // GenericOpcodes.td:1420
121 G_STORE = 106, // GenericOpcodes.td:1428
122 G_FPTRUNCSTORE = 107, // GenericOpcodes.td:1438
123 G_INDEXED_STORE = 108, // GenericOpcodes.td:1446
124 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 109, // GenericOpcodes.td:1457
125 G_ATOMIC_CMPXCHG = 110, // GenericOpcodes.td:1468
126 G_ATOMICRMW_XCHG = 111, // GenericOpcodes.td:1488
127 G_ATOMICRMW_ADD = 112, // GenericOpcodes.td:1489
128 G_ATOMICRMW_SUB = 113, // GenericOpcodes.td:1490
129 G_ATOMICRMW_AND = 114, // GenericOpcodes.td:1491
130 G_ATOMICRMW_NAND = 115, // GenericOpcodes.td:1492
131 G_ATOMICRMW_OR = 116, // GenericOpcodes.td:1493
132 G_ATOMICRMW_XOR = 117, // GenericOpcodes.td:1494
133 G_ATOMICRMW_MAX = 118, // GenericOpcodes.td:1495
134 G_ATOMICRMW_MIN = 119, // GenericOpcodes.td:1496
135 G_ATOMICRMW_UMAX = 120, // GenericOpcodes.td:1497
136 G_ATOMICRMW_UMIN = 121, // GenericOpcodes.td:1498
137 G_ATOMICRMW_FADD = 122, // GenericOpcodes.td:1509
138 G_ATOMICRMW_FSUB = 123, // GenericOpcodes.td:1510
139 G_ATOMICRMW_FMAX = 124, // GenericOpcodes.td:1511
140 G_ATOMICRMW_FMIN = 125, // GenericOpcodes.td:1512
141 G_ATOMICRMW_FMAXIMUM = 126, // GenericOpcodes.td:1513
142 G_ATOMICRMW_FMINIMUM = 127, // GenericOpcodes.td:1514
143 G_ATOMICRMW_FMAXIMUMNUM = 128, // GenericOpcodes.td:1515
144 G_ATOMICRMW_FMINIMUMNUM = 129, // GenericOpcodes.td:1516
145 G_ATOMICRMW_UINC_WRAP = 130, // GenericOpcodes.td:1499
146 G_ATOMICRMW_UDEC_WRAP = 131, // GenericOpcodes.td:1500
147 G_ATOMICRMW_USUB_COND = 132, // GenericOpcodes.td:1501
148 G_ATOMICRMW_USUB_SAT = 133, // GenericOpcodes.td:1502
149 G_FENCE = 134, // GenericOpcodes.td:1518
150 G_PREFETCH = 135, // GenericOpcodes.td:1525
151 G_BRCOND = 136, // GenericOpcodes.td:1665
152 G_BRINDIRECT = 137, // GenericOpcodes.td:1674
153 G_INVOKE_REGION_START = 138, // GenericOpcodes.td:1697
154 G_INTRINSIC = 139, // GenericOpcodes.td:1617
155 G_INTRINSIC_W_SIDE_EFFECTS = 140, // GenericOpcodes.td:1624
156 G_INTRINSIC_CONVERGENT = 141, // GenericOpcodes.td:1633
157 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 142, // GenericOpcodes.td:1641
158 G_ANYEXT = 143, // GenericOpcodes.td:44
159 G_TRUNC = 144, // GenericOpcodes.td:83
160 G_TRUNC_SSAT_S = 145, // GenericOpcodes.td:91
161 G_TRUNC_SSAT_U = 146, // GenericOpcodes.td:98
162 G_TRUNC_USAT_U = 147, // GenericOpcodes.td:105
163 G_CONSTANT = 148, // GenericOpcodes.td:169
164 G_FCONSTANT = 149, // GenericOpcodes.td:177
165 G_VASTART = 150, // GenericOpcodes.td:184
166 G_VAARG = 151, // GenericOpcodes.td:191
167 G_SEXT = 152, // GenericOpcodes.td:52
168 G_SEXT_INREG = 153, // GenericOpcodes.td:66
169 G_ZEXT = 154, // GenericOpcodes.td:74
170 G_SHL = 155, // GenericOpcodes.td:404
171 G_LSHR = 156, // GenericOpcodes.td:411
172 G_ASHR = 157, // GenericOpcodes.td:418
173 G_FSHL = 158, // GenericOpcodes.td:470
174 G_FSHR = 159, // GenericOpcodes.td:478
175 G_ROTR = 160, // GenericOpcodes.td:485
176 G_ROTL = 161, // GenericOpcodes.td:492
177 G_ICMP = 162, // GenericOpcodes.td:499
178 G_FCMP = 163, // GenericOpcodes.td:506
179 G_SCMP = 164, // GenericOpcodes.td:513
180 G_UCMP = 165, // GenericOpcodes.td:520
181 G_SELECT = 166, // GenericOpcodes.td:527
182 G_UADDO = 167, // GenericOpcodes.td:619
183 G_UADDE = 168, // GenericOpcodes.td:627
184 G_USUBO = 169, // GenericOpcodes.td:649
185 G_USUBE = 170, // GenericOpcodes.td:655
186 G_SADDO = 171, // GenericOpcodes.td:634
187 G_SADDE = 172, // GenericOpcodes.td:642
188 G_SSUBO = 173, // GenericOpcodes.td:662
189 G_SSUBE = 174, // GenericOpcodes.td:669
190 G_UMULO = 175, // GenericOpcodes.td:676
191 G_SMULO = 176, // GenericOpcodes.td:684
192 G_UMULH = 177, // GenericOpcodes.td:693
193 G_SMULH = 178, // GenericOpcodes.td:702
194 G_UADDSAT = 179, // GenericOpcodes.td:714
195 G_SADDSAT = 180, // GenericOpcodes.td:722
196 G_USUBSAT = 181, // GenericOpcodes.td:730
197 G_SSUBSAT = 182, // GenericOpcodes.td:738
198 G_USHLSAT = 183, // GenericOpcodes.td:746
199 G_SSHLSAT = 184, // GenericOpcodes.td:754
200 G_SMULFIX = 185, // GenericOpcodes.td:766
201 G_UMULFIX = 186, // GenericOpcodes.td:773
202 G_SMULFIXSAT = 187, // GenericOpcodes.td:783
203 G_UMULFIXSAT = 188, // GenericOpcodes.td:790
204 G_SDIVFIX = 189, // GenericOpcodes.td:801
205 G_UDIVFIX = 190, // GenericOpcodes.td:808
206 G_SDIVFIXSAT = 191, // GenericOpcodes.td:818
207 G_UDIVFIXSAT = 192, // GenericOpcodes.td:825
208 G_FADD = 193, // GenericOpcodes.td:998
209 G_FSUB = 194, // GenericOpcodes.td:1006
210 G_FMUL = 195, // GenericOpcodes.td:1014
211 G_FMA = 196, // GenericOpcodes.td:1023
212 G_FMAD = 197, // GenericOpcodes.td:1032
213 G_FDIV = 198, // GenericOpcodes.td:1040
214 G_FREM = 199, // GenericOpcodes.td:1047
215 G_FMODF = 200, // GenericOpcodes.td:1054
216 G_FPOW = 201, // GenericOpcodes.td:1061
217 G_FPOWI = 202, // GenericOpcodes.td:1068
218 G_FEXP = 203, // GenericOpcodes.td:1075
219 G_FEXP2 = 204, // GenericOpcodes.td:1082
220 G_FEXP10 = 205, // GenericOpcodes.td:1089
221 G_FLOG = 206, // GenericOpcodes.td:1096
222 G_FLOG2 = 207, // GenericOpcodes.td:1103
223 G_FLOG10 = 208, // GenericOpcodes.td:1110
224 G_FLDEXP = 209, // GenericOpcodes.td:1117
225 G_FFREXP = 210, // GenericOpcodes.td:1124
226 G_FNEG = 211, // GenericOpcodes.td:836
227 G_FPEXT = 212, // GenericOpcodes.td:842
228 G_FPTRUNC = 213, // GenericOpcodes.td:848
229 G_FPTOSI = 214, // GenericOpcodes.td:854
230 G_FPTOUI = 215, // GenericOpcodes.td:860
231 G_SITOFP = 216, // GenericOpcodes.td:866
232 G_UITOFP = 217, // GenericOpcodes.td:872
233 G_FPTOSI_SAT = 218, // GenericOpcodes.td:878
234 G_FPTOUI_SAT = 219, // GenericOpcodes.td:884
235 G_FABS = 220, // GenericOpcodes.td:890
236 G_FCOPYSIGN = 221, // GenericOpcodes.td:896
237 G_IS_FPCLASS = 222, // GenericOpcodes.td:909
238 G_FCANONICALIZE = 223, // GenericOpcodes.td:902
239 G_FMINNUM = 224, // GenericOpcodes.td:922
240 G_FMAXNUM = 225, // GenericOpcodes.td:929
241 G_FMINNUM_IEEE = 226, // GenericOpcodes.td:947
242 G_FMAXNUM_IEEE = 227, // GenericOpcodes.td:954
243 G_FMINIMUM = 228, // GenericOpcodes.td:964
244 G_FMAXIMUM = 229, // GenericOpcodes.td:971
245 G_FMINIMUMNUM = 230, // GenericOpcodes.td:979
246 G_FMAXIMUMNUM = 231, // GenericOpcodes.td:986
247 G_GET_FPENV = 232, // GenericOpcodes.td:1254
248 G_SET_FPENV = 233, // GenericOpcodes.td:1261
249 G_RESET_FPENV = 234, // GenericOpcodes.td:1268
250 G_GET_FPMODE = 235, // GenericOpcodes.td:1275
251 G_SET_FPMODE = 236, // GenericOpcodes.td:1282
252 G_RESET_FPMODE = 237, // GenericOpcodes.td:1289
253 G_GET_ROUNDING = 238, // GenericOpcodes.td:1346
254 G_SET_ROUNDING = 239, // GenericOpcodes.td:1352
255 G_PTR_ADD = 240, // GenericOpcodes.td:534
256 G_PTRMASK = 241, // GenericOpcodes.td:542
257 G_SMIN = 242, // GenericOpcodes.td:549
258 G_SMAX = 243, // GenericOpcodes.td:557
259 G_UMIN = 244, // GenericOpcodes.td:565
260 G_UMAX = 245, // GenericOpcodes.td:573
261 G_ABS = 246, // GenericOpcodes.td:581
262 G_LROUND = 247, // GenericOpcodes.td:291
263 G_LLROUND = 248, // GenericOpcodes.td:297
264 G_BR = 249, // GenericOpcodes.td:1655
265 G_BRJT = 250, // GenericOpcodes.td:1685
266 G_VSCALE = 251, // GenericOpcodes.td:1583
267 G_INSERT_SUBVECTOR = 252, // GenericOpcodes.td:1729
268 G_EXTRACT_SUBVECTOR = 253, // GenericOpcodes.td:1737
269 G_INSERT_VECTOR_ELT = 254, // GenericOpcodes.td:1745
270 G_EXTRACT_VECTOR_ELT = 255, // GenericOpcodes.td:1753
271 G_SHUFFLE_VECTOR = 256, // GenericOpcodes.td:1764
272 G_SPLAT_VECTOR = 257, // GenericOpcodes.td:1772
273 G_STEP_VECTOR = 258, // GenericOpcodes.td:1780
274 G_VECTOR_COMPRESS = 259, // GenericOpcodes.td:1787
275 G_CTTZ = 260, // GenericOpcodes.td:211
276 G_CTTZ_ZERO_POISON = 261, // GenericOpcodes.td:217
277 G_CTLZ = 262, // GenericOpcodes.td:199
278 G_CTLZ_ZERO_POISON = 263, // GenericOpcodes.td:205
279 G_CTLS = 264, // GenericOpcodes.td:223
280 G_CTPOP = 265, // GenericOpcodes.td:229
281 G_BSWAP = 266, // GenericOpcodes.td:235
282 G_BITREVERSE = 267, // GenericOpcodes.td:242
283 G_CLMUL = 268, // GenericOpcodes.td:588
284 G_CLMULH = 269, // GenericOpcodes.td:596
285 G_CLMULR = 270, // GenericOpcodes.td:606
286 G_FCEIL = 271, // GenericOpcodes.td:1131
287 G_FCOS = 272, // GenericOpcodes.td:1138
288 G_FSIN = 273, // GenericOpcodes.td:1145
289 G_FSINCOS = 274, // GenericOpcodes.td:1152
290 G_FTAN = 275, // GenericOpcodes.td:1159
291 G_FACOS = 276, // GenericOpcodes.td:1166
292 G_FASIN = 277, // GenericOpcodes.td:1173
293 G_FATAN = 278, // GenericOpcodes.td:1180
294 G_FATAN2 = 279, // GenericOpcodes.td:1187
295 G_FCOSH = 280, // GenericOpcodes.td:1194
296 G_FSINH = 281, // GenericOpcodes.td:1201
297 G_FTANH = 282, // GenericOpcodes.td:1208
298 G_FSQRT = 283, // GenericOpcodes.td:1218
299 G_FFLOOR = 284, // GenericOpcodes.td:1225
300 G_FRINT = 285, // GenericOpcodes.td:1232
301 G_FNEARBYINT = 286, // GenericOpcodes.td:1239
302 G_ADDRSPACE_CAST = 287, // GenericOpcodes.td:248
303 G_BLOCK_ADDR = 288, // GenericOpcodes.td:254
304 G_JUMP_TABLE = 289, // GenericOpcodes.td:260
305 G_DYN_STACKALLOC = 290, // GenericOpcodes.td:266
306 G_STACKSAVE = 291, // GenericOpcodes.td:272
307 G_STACKRESTORE = 292, // GenericOpcodes.td:278
308 G_STRICT_FADD = 293, // GenericOpcodes.td:1839
309 G_STRICT_FSUB = 294, // GenericOpcodes.td:1840
310 G_STRICT_FMUL = 295, // GenericOpcodes.td:1841
311 G_STRICT_FDIV = 296, // GenericOpcodes.td:1842
312 G_STRICT_FREM = 297, // GenericOpcodes.td:1843
313 G_STRICT_FMA = 298, // GenericOpcodes.td:1844
314 G_STRICT_FSQRT = 299, // GenericOpcodes.td:1845
315 G_STRICT_FLDEXP = 300, // GenericOpcodes.td:1846
316 G_STRICT_FCMP = 301, // GenericOpcodes.td:1847
317 G_STRICT_FCMPS = 302, // GenericOpcodes.td:1848
318 G_READ_REGISTER = 303, // GenericOpcodes.td:1704
319 G_WRITE_REGISTER = 304, // GenericOpcodes.td:1714
320 G_MEMCPY = 305, // GenericOpcodes.td:1854
321 G_MEMCPY_INLINE = 306, // GenericOpcodes.td:1862
322 G_MEMMOVE = 307, // GenericOpcodes.td:1870
323 G_MEMSET = 308, // GenericOpcodes.td:1878
324 G_BZERO = 309, // GenericOpcodes.td:1885
325 G_MEMSET_INLINE = 310, // GenericOpcodes.td:1892
326 G_TRAP = 311, // GenericOpcodes.td:1902
327 G_DEBUGTRAP = 312, // GenericOpcodes.td:1909
328 G_UBSANTRAP = 313, // GenericOpcodes.td:1915
329 G_VECREDUCE_SEQ_FADD = 314, // GenericOpcodes.td:1803
330 G_VECREDUCE_SEQ_FMUL = 315, // GenericOpcodes.td:1809
331 G_VECREDUCE_FADD = 316, // GenericOpcodes.td:1815
332 G_VECREDUCE_FMUL = 317, // GenericOpcodes.td:1816
333 G_VECREDUCE_FMAX = 318, // GenericOpcodes.td:1818
334 G_VECREDUCE_FMIN = 319, // GenericOpcodes.td:1819
335 G_VECREDUCE_FMAXIMUM = 320, // GenericOpcodes.td:1820
336 G_VECREDUCE_FMINIMUM = 321, // GenericOpcodes.td:1821
337 G_VECREDUCE_FMAXIMUMNUM = 322, // GenericOpcodes.td:1822
338 G_VECREDUCE_FMINIMUMNUM = 323, // GenericOpcodes.td:1823
339 G_VECREDUCE_ADD = 324, // GenericOpcodes.td:1825
340 G_VECREDUCE_MUL = 325, // GenericOpcodes.td:1826
341 G_VECREDUCE_AND = 326, // GenericOpcodes.td:1827
342 G_VECREDUCE_OR = 327, // GenericOpcodes.td:1828
343 G_VECREDUCE_XOR = 328, // GenericOpcodes.td:1829
344 G_VECREDUCE_SMAX = 329, // GenericOpcodes.td:1830
345 G_VECREDUCE_SMIN = 330, // GenericOpcodes.td:1831
346 G_VECREDUCE_UMAX = 331, // GenericOpcodes.td:1832
347 G_VECREDUCE_UMIN = 332, // GenericOpcodes.td:1833
348 G_SBFX = 333, // GenericOpcodes.td:1927
349 G_UBFX = 334, // GenericOpcodes.td:1935
350 DummyInst = 335, // DXILStubs.td:18
351 INSTRUCTION_LIST_END = 336
352 };
353
354} // namespace llvm::dxil
355
356#endif // GET_INSTRINFO_ENUM
357
358#ifdef GET_INSTRINFO_SCHED_ENUM
359#undef GET_INSTRINFO_SCHED_ENUM
360
361namespace llvm::dxil::Sched {
362
363 enum {
364 NoInstrModel = 0,
365 SCHED_LIST_END = 1
366 };
367
368} // namespace llvm::dxil::Sched
369
370#endif // GET_INSTRINFO_SCHED_ENUM
371
372#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
373
374namespace llvm {
375
376struct DirectXInstrTable {
377 MCInstrDesc Insts[336];
378 static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
379 MCPhysReg ImplicitOps[1];
380 char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
381 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
382 MCOperandInfo OperandInfo[151];
383};
384} // namespace llvm
385
386#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
387
388#ifdef GET_INSTRINFO_MC_DESC
389#undef GET_INSTRINFO_MC_DESC
390
391namespace llvm {
392
393static_assert((sizeof DirectXInstrTable::ImplicitOps + sizeof DirectXInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
394static constexpr unsigned DirectXOpInfoBase = (sizeof DirectXInstrTable::ImplicitOps + sizeof DirectXInstrTable::Padding) / sizeof(MCOperandInfo);
395
396extern const DirectXInstrTable DirectXDescs = {
397 {
398 { 335, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DummyInst
399 { 334, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
400 { 333, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 147, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SBFX
401 { 332, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMIN
402 { 331, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_UMAX
403 { 330, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMIN
404 { 329, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SMAX
405 { 328, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_XOR
406 { 327, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_OR
407 { 326, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_AND
408 { 325, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_MUL
409 { 324, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_ADD
410 { 323, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUMNUM
411 { 322, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUMNUM
412 { 321, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMINIMUM
413 { 320, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAXIMUM
414 { 319, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMIN
415 { 318, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMAX
416 { 317, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FMUL
417 { 316, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_FADD
418 { 315, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FMUL
419 { 314, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECREDUCE_SEQ_FADD
420 { 313, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBSANTRAP
421 { 312, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DEBUGTRAP
422 { 311, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRAP
423 { 310, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET_INLINE
424 { 309, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BZERO
425 { 308, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMSET
426 { 307, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMMOVE
427 { 306, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY_INLINE
428 { 305, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 143, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MEMCPY
429 { 304, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 141, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_WRITE_REGISTER
430 { 303, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_READ_REGISTER
431 { 302, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMPS
432 { 301, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FCMP
433 { 300, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FLDEXP
434 { 299, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSQRT
435 { 298, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMA
436 { 297, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FREM
437 { 296, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FDIV
438 { 295, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FMUL
439 { 294, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FSUB
440 { 293, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STRICT_FADD
441 { 292, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKRESTORE
442 { 291, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STACKSAVE
443 { 290, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_DYN_STACKALLOC
444 { 289, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_JUMP_TABLE
445 { 288, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BLOCK_ADDR
446 { 287, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADDRSPACE_CAST
447 { 286, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEARBYINT
448 { 285, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRINT
449 { 284, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFLOOR
450 { 283, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSQRT
451 { 282, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTANH
452 { 281, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINH
453 { 280, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOSH
454 { 279, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN2
455 { 278, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FATAN
456 { 277, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FASIN
457 { 276, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FACOS
458 { 275, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FTAN
459 { 274, 3, 2, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSINCOS
460 { 273, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSIN
461 { 272, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOS
462 { 271, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCEIL
463 { 270, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULR
464 { 269, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMULH
465 { 268, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CLMUL
466 { 267, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITREVERSE
467 { 266, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BSWAP
468 { 265, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTPOP
469 { 264, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLS
470 { 263, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ_ZERO_POISON
471 { 262, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTLZ
472 { 261, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ_ZERO_POISON
473 { 260, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CTTZ
474 { 259, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 137, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VECTOR_COMPRESS
475 { 258, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STEP_VECTOR
476 { 257, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SPLAT_VECTOR
477 { 256, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 133, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHUFFLE_VECTOR
478 { 255, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 130, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_VECTOR_ELT
479 { 254, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 126, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_VECTOR_ELT
480 { 253, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT_SUBVECTOR
481 { 252, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT_SUBVECTOR
482 { 251, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VSCALE
483 { 250, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 123, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRJT
484 { 249, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BR
485 { 248, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LLROUND
486 { 247, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LROUND
487 { 246, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABS
488 { 245, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMAX
489 { 244, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMIN
490 { 243, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMAX
491 { 242, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMIN
492 { 241, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRMASK
493 { 240, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTR_ADD
494 { 239, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_ROUNDING
495 { 238, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_ROUNDING
496 { 237, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPMODE
497 { 236, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPMODE
498 { 235, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPMODE
499 { 234, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_RESET_FPENV
500 { 233, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SET_FPENV
501 { 232, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GET_FPENV
502 { 231, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUMNUM
503 { 230, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUMNUM
504 { 229, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXIMUM
505 { 228, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINIMUM
506 { 227, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM_IEEE
507 { 226, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM_IEEE
508 { 225, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAXNUM
509 { 224, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMINNUM
510 { 223, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCANONICALIZE
511 { 222, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IS_FPCLASS
512 { 221, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCOPYSIGN
513 { 220, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FABS
514 { 219, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI_SAT
515 { 218, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI_SAT
516 { 217, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UITOFP
517 { 216, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SITOFP
518 { 215, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOUI
519 { 214, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTOSI
520 { 213, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNC
521 { 212, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXT
522 { 211, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FNEG
523 { 210, 3, 2, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FFREXP
524 { 209, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLDEXP
525 { 208, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG10
526 { 207, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG2
527 { 206, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FLOG
528 { 205, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP10
529 { 204, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP2
530 { 203, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FEXP
531 { 202, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOWI
532 { 201, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPOW
533 { 200, 3, 2, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMODF
534 { 199, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREM
535 { 198, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FDIV
536 { 197, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMAD
537 { 196, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMA
538 { 195, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FMUL
539 { 194, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSUB
540 { 193, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FADD
541 { 192, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIXSAT
542 { 191, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIXSAT
543 { 190, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVFIX
544 { 189, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVFIX
545 { 188, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIXSAT
546 { 187, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIXSAT
547 { 186, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULFIX
548 { 185, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 119, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULFIX
549 { 184, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSHLSAT
550 { 183, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USHLSAT
551 { 182, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBSAT
552 { 181, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBSAT
553 { 180, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDSAT
554 { 179, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDSAT
555 { 178, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULH
556 { 177, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULH
557 { 176, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SMULO
558 { 175, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UMULO
559 { 174, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBE
560 { 173, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SSUBO
561 { 172, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDE
562 { 171, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SADDO
563 { 170, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBE
564 { 169, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_USUBO
565 { 168, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 114, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDE
566 { 167, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UADDO
567 { 166, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SELECT
568 { 165, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UCMP
569 { 164, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 111, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SCMP
570 { 163, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCMP
571 { 162, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 107, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ICMP
572 { 161, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTL
573 { 160, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ROTR
574 { 159, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHR
575 { 158, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 103, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FSHL
576 { 157, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASHR
577 { 156, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LSHR
578 { 155, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 100, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SHL
579 { 154, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXT
580 { 153, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT_INREG
581 { 152, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXT
582 { 151, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 97, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VAARG
583 { 150, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_VASTART
584 { 149, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FCONSTANT
585 { 148, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT
586 { 147, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_USAT_U
587 { 146, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_U
588 { 145, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC_SSAT_S
589 { 144, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_TRUNC
590 { 143, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ANYEXT
591 { 142, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
592 { 141, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // G_INTRINSIC_CONVERGENT
593 { 140, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_W_SIDE_EFFECTS
594 { 139, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC
595 { 138, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INVOKE_REGION_START
596 { 137, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRINDIRECT
597 { 136, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BRCOND
598 { 135, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 93, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PREFETCH
599 { 134, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 20, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FENCE
600 { 133, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_SAT
601 { 132, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_USUB_COND
602 { 131, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UDEC_WRAP
603 { 130, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UINC_WRAP
604 { 129, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUMNUM
605 { 128, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUMNUM
606 { 127, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMINIMUM
607 { 126, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAXIMUM
608 { 125, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMIN
609 { 124, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FMAX
610 { 123, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FSUB
611 { 122, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_FADD
612 { 121, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMIN
613 { 120, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_UMAX
614 { 119, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MIN
615 { 118, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_MAX
616 { 117, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XOR
617 { 116, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_OR
618 { 115, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_NAND
619 { 114, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_AND
620 { 113, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_SUB
621 { 112, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_ADD
622 { 111, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 90, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMICRMW_XCHG
623 { 110, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 86, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG
624 { 109, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 81, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
625 { 108, 5, 1, 0, 0, 0, 0, DirectXOpInfoBase + 76, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_STORE
626 { 107, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPTRUNCSTORE
627 { 106, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_STORE
628 { 105, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_ZEXTLOAD
629 { 104, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_SEXTLOAD
630 { 103, 5, 2, 0, 0, 0, 0, DirectXOpInfoBase + 71, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INDEXED_LOAD
631 { 102, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FPEXTLOAD
632 { 101, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ZEXTLOAD
633 { 100, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SEXTLOAD
634 { 99, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_LOAD
635 { 98, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READSTEADYCOUNTER
636 { 97, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_READCYCLECOUNTER
637 { 96, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUNDEVEN
638 { 95, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LLRINT
639 { 94, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_LRINT
640 { 93, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_ROUND
641 { 92, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_TRUNC
642 { 91, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 68, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTRINSIC_FPTRUNC_ROUND
643 { 90, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_FOLD_BARRIER
644 { 89, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 66, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FREEZE
645 { 88, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BITCAST
646 { 87, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INTTOPTR
647 { 86, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRTOINT
648 { 85, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONCAT_VECTORS
649 { 84, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR_TRUNC
650 { 83, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_BUILD_VECTOR
651 { 82, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MERGE_VALUES
652 { 81, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 62, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_INSERT
653 { 80, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 60, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UNMERGE_VALUES
654 { 79, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 57, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_EXTRACT
655 { 78, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_CONSTANT_POOL
656 { 77, 5, 1, 0, 0, 0, 0, DirectXOpInfoBase + 52, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PTRAUTH_GLOBAL_VALUE
657 { 76, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_GLOBAL_VALUE
658 { 75, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 50, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_FRAME_INDEX
659 { 74, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_PHI
660 { 73, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 49, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_IMPLICIT_DEF
661 { 72, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGCEIL
662 { 71, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SAVGFLOOR
663 { 70, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGCEIL
664 { 69, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UAVGFLOOR
665 { 68, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDU
666 { 67, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ABDS
667 { 66, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_XOR
668 { 65, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_OR
669 { 64, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_AND
670 { 63, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIVREM
671 { 62, 4, 2, 0, 0, 0, 0, DirectXOpInfoBase + 45, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIVREM
672 { 61, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UREM
673 { 60, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SREM
674 { 59, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UDIV
675 { 58, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SDIV
676 { 57, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_MUL
677 { 56, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_SUB
678 { 55, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 42, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ADD
679 { 54, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ALIGN
680 { 53, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_ZEXT
681 { 52, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 39, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_ASSERT_SEXT
682 { 51, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_GLUE
683 { 50, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_LOOP
684 { 49, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ANCHOR
685 { 48, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // CONVERGENCECTRL_ENTRY
686 { 47, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // RELOC_NONE
687 { 46, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // JUMP_TABLE_DEBUG_INFO
688 { 45, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MEMBARRIER
689 { 44, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAKE_USE
690 { 43, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ICALL_BRANCH_FUNNEL
691 { 42, 3, 0, 0, 0, 0, 0, DirectXOpInfoBase + 36, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14701
692 { 41, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 34, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14700
693 { 40, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_TAIL_CALL
694 { 39, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_EXIT
695 { 38, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_RET
696 { 37, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_FUNCTION_ENTER
697 { 36, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHABLE_OP
698 { 35, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FAULTING_OP
699 { 34, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 32, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LOCAL_ESCAPE
700 { 33, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STATEPOINT
701 { 32, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 29, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14699
702 { 31, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PREALLOCATED_SETUP
703 { 30, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 28, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_14418
704 { 29, 6, 1, 0, 0, 0, 0, DirectXOpInfoBase + 22, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PATCHPOINT
705 { 28, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // FENTRY_CALL
706 { 27, 2, 0, 0, 0, 0, 0, DirectXOpInfoBase + 20, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // STACKMAP
707 { 26, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 18, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ARITH_FENCE
708 { 25, 4, 0, 0, 0, 0, 0, DirectXOpInfoBase + 14, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PSEUDO_PROBE
709 { 24, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_END
710 { 23, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // LIFETIME_START
711 { 22, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // BUNDLE
712 { 21, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 11, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_LANEMASK
713 { 20, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY
714 { 19, 2, 1, 0, 0, 0, 0, DirectXOpInfoBase + 9, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // REG_SEQUENCE
715 { 18, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_LABEL
716 { 17, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_PHI
717 { 16, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_INSTR_REF
718 { 15, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE_LIST
719 { 14, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // DBG_VALUE
720 { 13, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // COPY_TO_REGCLASS
721 { 12, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // SUBREG_TO_REG
722 { 11, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INIT_UNDEF
723 { 10, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // IMPLICIT_DEF
724 { 9, 4, 1, 0, 0, 0, 0, DirectXOpInfoBase + 5, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INSERT_SUBREG
725 { 8, 3, 1, 0, 0, 0, 0, DirectXOpInfoBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EXTRACT_SUBREG
726 { 7, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // KILL
727 { 6, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // ANNOTATION_LABEL
728 { 5, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // GC_LABEL
729 { 4, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // EH_LABEL
730 { 3, 1, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // CFI_INSTRUCTION
731 { 2, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM_BR
732 { 1, 0, 0, 0, 0, 0, 0, DirectXOpInfoBase + 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // INLINEASM
733 { 0, 1, 1, 0, 0, 0, 0, DirectXOpInfoBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // PHI
734 }, {
735 /* 0 */
736 }, {
737 0
738 }, {
739 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
740 /* 1 */
741 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
742 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
743 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
744 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
745 /* 11 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
746 /* 14 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
747 /* 18 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
748 /* 20 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
749 /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
750 /* 28 */ { dxil::DXILClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
751 /* 29 */ { dxil::DXILClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
752 /* 32 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
753 /* 34 */ { dxil::DXILClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
754 /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { dxil::DXILClassRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
755 /* 39 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
756 /* 42 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
757 /* 45 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
758 /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
759 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
760 /* 52 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
761 /* 57 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
762 /* 60 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
763 /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
764 /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
765 /* 68 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
766 /* 71 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
767 /* 76 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
768 /* 81 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
769 /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
770 /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
771 /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_2, 0 },
772 /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
773 /* 100 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
774 /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
775 /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
776 /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
777 /* 114 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
778 /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
779 /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
780 /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
781 /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
782 /* 133 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
783 /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
784 /* 141 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
785 /* 143 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
786 /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
787 }
788};
789
790
791#ifdef __GNUC__
792#pragma GCC diagnostic push
793#pragma GCC diagnostic ignored "-Woverlength-strings"
794#endif
795extern const char DirectXInstrNameData[] = {
796 /* 0 */ "G_FLOG10\000"
797 /* 9 */ "G_FEXP10\000"
798 /* 18 */ "G_FLOG2\000"
799 /* 26 */ "G_FATAN2\000"
800 /* 35 */ "G_FEXP2\000"
801 /* 43 */ "G_FMA\000"
802 /* 49 */ "G_STRICT_FMA\000"
803 /* 62 */ "G_FSUB\000"
804 /* 69 */ "G_STRICT_FSUB\000"
805 /* 83 */ "G_ATOMICRMW_FSUB\000"
806 /* 100 */ "G_SUB\000"
807 /* 106 */ "G_ATOMICRMW_SUB\000"
808 /* 122 */ "G_INTRINSIC\000"
809 /* 134 */ "G_FPTRUNC\000"
810 /* 144 */ "G_INTRINSIC_TRUNC\000"
811 /* 162 */ "G_TRUNC\000"
812 /* 170 */ "G_BUILD_VECTOR_TRUNC\000"
813 /* 191 */ "G_DYN_STACKALLOC\000"
814 /* 208 */ "G_FMAD\000"
815 /* 215 */ "G_FPEXTLOAD\000"
816 /* 227 */ "G_INDEXED_SEXTLOAD\000"
817 /* 246 */ "G_SEXTLOAD\000"
818 /* 257 */ "G_INDEXED_ZEXTLOAD\000"
819 /* 276 */ "G_ZEXTLOAD\000"
820 /* 287 */ "G_INDEXED_LOAD\000"
821 /* 302 */ "G_LOAD\000"
822 /* 309 */ "G_VECREDUCE_FADD\000"
823 /* 326 */ "G_FADD\000"
824 /* 333 */ "G_VECREDUCE_SEQ_FADD\000"
825 /* 354 */ "G_STRICT_FADD\000"
826 /* 368 */ "G_ATOMICRMW_FADD\000"
827 /* 385 */ "G_VECREDUCE_ADD\000"
828 /* 401 */ "G_ADD\000"
829 /* 407 */ "G_PTR_ADD\000"
830 /* 417 */ "G_ATOMICRMW_ADD\000"
831 /* 433 */ "G_ATOMICRMW_NAND\000"
832 /* 450 */ "G_VECREDUCE_AND\000"
833 /* 466 */ "G_AND\000"
834 /* 472 */ "G_ATOMICRMW_AND\000"
835 /* 488 */ "LIFETIME_END\000"
836 /* 501 */ "G_BRCOND\000"
837 /* 510 */ "G_ATOMICRMW_USUB_COND\000"
838 /* 532 */ "G_LLROUND\000"
839 /* 542 */ "G_LROUND\000"
840 /* 551 */ "G_INTRINSIC_ROUND\000"
841 /* 569 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
842 /* 595 */ "LOAD_STACK_GUARD\000"
843 /* 612 */ "PSEUDO_PROBE\000"
844 /* 625 */ "G_SSUBE\000"
845 /* 633 */ "G_USUBE\000"
846 /* 641 */ "G_FENCE\000"
847 /* 649 */ "ARITH_FENCE\000"
848 /* 661 */ "REG_SEQUENCE\000"
849 /* 674 */ "G_SADDE\000"
850 /* 682 */ "G_UADDE\000"
851 /* 690 */ "G_GET_FPMODE\000"
852 /* 703 */ "G_RESET_FPMODE\000"
853 /* 718 */ "G_SET_FPMODE\000"
854 /* 731 */ "G_FMINNUM_IEEE\000"
855 /* 746 */ "G_FMAXNUM_IEEE\000"
856 /* 761 */ "G_VSCALE\000"
857 /* 770 */ "G_JUMP_TABLE\000"
858 /* 783 */ "BUNDLE\000"
859 /* 790 */ "G_MEMSET_INLINE\000"
860 /* 806 */ "G_MEMCPY_INLINE\000"
861 /* 822 */ "RELOC_NONE\000"
862 /* 833 */ "LOCAL_ESCAPE\000"
863 /* 846 */ "G_FPTRUNCSTORE\000"
864 /* 861 */ "G_STACKRESTORE\000"
865 /* 876 */ "G_INDEXED_STORE\000"
866 /* 892 */ "G_STORE\000"
867 /* 900 */ "G_BITREVERSE\000"
868 /* 913 */ "FAKE_USE\000"
869 /* 922 */ "DBG_VALUE\000"
870 /* 932 */ "G_GLOBAL_VALUE\000"
871 /* 947 */ "G_PTRAUTH_GLOBAL_VALUE\000"
872 /* 970 */ "CONVERGENCECTRL_GLUE\000"
873 /* 991 */ "G_STACKSAVE\000"
874 /* 1003 */ "G_MEMMOVE\000"
875 /* 1013 */ "G_FREEZE\000"
876 /* 1022 */ "G_FCANONICALIZE\000"
877 /* 1038 */ "G_FMODF\000"
878 /* 1046 */ "INIT_UNDEF\000"
879 /* 1057 */ "G_IMPLICIT_DEF\000"
880 /* 1072 */ "DBG_INSTR_REF\000"
881 /* 1086 */ "G_FNEG\000"
882 /* 1093 */ "EXTRACT_SUBREG\000"
883 /* 1108 */ "INSERT_SUBREG\000"
884 /* 1122 */ "G_SEXT_INREG\000"
885 /* 1135 */ "SUBREG_TO_REG\000"
886 /* 1149 */ "G_ATOMIC_CMPXCHG\000"
887 /* 1166 */ "G_ATOMICRMW_XCHG\000"
888 /* 1183 */ "G_GET_ROUNDING\000"
889 /* 1198 */ "G_SET_ROUNDING\000"
890 /* 1213 */ "G_FLOG\000"
891 /* 1220 */ "G_VAARG\000"
892 /* 1228 */ "PREALLOCATED_ARG\000"
893 /* 1245 */ "G_PREFETCH\000"
894 /* 1256 */ "G_CLMULH\000"
895 /* 1265 */ "G_SMULH\000"
896 /* 1273 */ "G_UMULH\000"
897 /* 1281 */ "G_FTANH\000"
898 /* 1289 */ "G_FSINH\000"
899 /* 1297 */ "G_FCOSH\000"
900 /* 1305 */ "DBG_PHI\000"
901 /* 1313 */ "G_FPTOSI\000"
902 /* 1322 */ "G_FPTOUI\000"
903 /* 1331 */ "G_FPOWI\000"
904 /* 1339 */ "COPY_LANEMASK\000"
905 /* 1353 */ "G_PTRMASK\000"
906 /* 1363 */ "GC_LABEL\000"
907 /* 1372 */ "DBG_LABEL\000"
908 /* 1382 */ "EH_LABEL\000"
909 /* 1391 */ "ANNOTATION_LABEL\000"
910 /* 1408 */ "ICALL_BRANCH_FUNNEL\000"
911 /* 1428 */ "G_FSHL\000"
912 /* 1435 */ "G_SHL\000"
913 /* 1441 */ "G_FCEIL\000"
914 /* 1449 */ "G_SAVGCEIL\000"
915 /* 1460 */ "G_UAVGCEIL\000"
916 /* 1471 */ "PATCHABLE_TAIL_CALL\000"
917 /* 1491 */ "PATCHABLE_TYPED_EVENT_CALL\000"
918 /* 1518 */ "PATCHABLE_EVENT_CALL\000"
919 /* 1539 */ "FENTRY_CALL\000"
920 /* 1551 */ "KILL\000"
921 /* 1556 */ "G_CONSTANT_POOL\000"
922 /* 1572 */ "G_ROTL\000"
923 /* 1579 */ "G_VECREDUCE_FMUL\000"
924 /* 1596 */ "G_FMUL\000"
925 /* 1603 */ "G_VECREDUCE_SEQ_FMUL\000"
926 /* 1624 */ "G_STRICT_FMUL\000"
927 /* 1638 */ "G_CLMUL\000"
928 /* 1646 */ "G_VECREDUCE_MUL\000"
929 /* 1662 */ "G_MUL\000"
930 /* 1668 */ "G_FREM\000"
931 /* 1675 */ "G_STRICT_FREM\000"
932 /* 1689 */ "G_SREM\000"
933 /* 1696 */ "G_UREM\000"
934 /* 1703 */ "G_SDIVREM\000"
935 /* 1713 */ "G_UDIVREM\000"
936 /* 1723 */ "INLINEASM\000"
937 /* 1733 */ "G_VECREDUCE_FMINIMUM\000"
938 /* 1754 */ "G_FMINIMUM\000"
939 /* 1765 */ "G_ATOMICRMW_FMINIMUM\000"
940 /* 1786 */ "G_VECREDUCE_FMAXIMUM\000"
941 /* 1807 */ "G_FMAXIMUM\000"
942 /* 1818 */ "G_ATOMICRMW_FMAXIMUM\000"
943 /* 1839 */ "G_VECREDUCE_FMINIMUMNUM\000"
944 /* 1863 */ "G_FMINIMUMNUM\000"
945 /* 1877 */ "G_ATOMICRMW_FMINIMUMNUM\000"
946 /* 1901 */ "G_VECREDUCE_FMAXIMUMNUM\000"
947 /* 1925 */ "G_FMAXIMUMNUM\000"
948 /* 1939 */ "G_ATOMICRMW_FMAXIMUMNUM\000"
949 /* 1963 */ "G_FMINNUM\000"
950 /* 1973 */ "G_FMAXNUM\000"
951 /* 1983 */ "G_FATAN\000"
952 /* 1991 */ "G_FTAN\000"
953 /* 1998 */ "G_INTRINSIC_ROUNDEVEN\000"
954 /* 2020 */ "G_ASSERT_ALIGN\000"
955 /* 2035 */ "G_FCOPYSIGN\000"
956 /* 2047 */ "G_VECREDUCE_FMIN\000"
957 /* 2064 */ "G_ATOMICRMW_FMIN\000"
958 /* 2081 */ "G_VECREDUCE_SMIN\000"
959 /* 2098 */ "G_SMIN\000"
960 /* 2105 */ "G_VECREDUCE_UMIN\000"
961 /* 2122 */ "G_UMIN\000"
962 /* 2129 */ "G_ATOMICRMW_UMIN\000"
963 /* 2146 */ "G_ATOMICRMW_MIN\000"
964 /* 2162 */ "G_FASIN\000"
965 /* 2170 */ "G_FSIN\000"
966 /* 2177 */ "CFI_INSTRUCTION\000"
967 /* 2193 */ "G_CTLZ_ZERO_POISON\000"
968 /* 2212 */ "G_CTTZ_ZERO_POISON\000"
969 /* 2231 */ "G_SSUBO\000"
970 /* 2239 */ "G_USUBO\000"
971 /* 2247 */ "G_SADDO\000"
972 /* 2255 */ "G_UADDO\000"
973 /* 2263 */ "JUMP_TABLE_DEBUG_INFO\000"
974 /* 2285 */ "G_SMULO\000"
975 /* 2293 */ "G_UMULO\000"
976 /* 2301 */ "G_BZERO\000"
977 /* 2309 */ "STACKMAP\000"
978 /* 2318 */ "G_DEBUGTRAP\000"
979 /* 2330 */ "G_UBSANTRAP\000"
980 /* 2342 */ "G_TRAP\000"
981 /* 2349 */ "G_ATOMICRMW_UDEC_WRAP\000"
982 /* 2371 */ "G_ATOMICRMW_UINC_WRAP\000"
983 /* 2393 */ "G_BSWAP\000"
984 /* 2401 */ "G_SITOFP\000"
985 /* 2410 */ "G_UITOFP\000"
986 /* 2419 */ "G_FCMP\000"
987 /* 2426 */ "G_STRICT_FCMP\000"
988 /* 2440 */ "G_ICMP\000"
989 /* 2447 */ "G_SCMP\000"
990 /* 2454 */ "G_UCMP\000"
991 /* 2461 */ "CONVERGENCECTRL_LOOP\000"
992 /* 2482 */ "G_CTPOP\000"
993 /* 2490 */ "PATCHABLE_OP\000"
994 /* 2503 */ "FAULTING_OP\000"
995 /* 2515 */ "PREALLOCATED_SETUP\000"
996 /* 2534 */ "G_FLDEXP\000"
997 /* 2543 */ "G_STRICT_FLDEXP\000"
998 /* 2559 */ "G_FEXP\000"
999 /* 2566 */ "G_FFREXP\000"
1000 /* 2575 */ "G_BR\000"
1001 /* 2580 */ "INLINEASM_BR\000"
1002 /* 2593 */ "G_BLOCK_ADDR\000"
1003 /* 2606 */ "MEMBARRIER\000"
1004 /* 2617 */ "G_CONSTANT_FOLD_BARRIER\000"
1005 /* 2641 */ "PATCHABLE_FUNCTION_ENTER\000"
1006 /* 2666 */ "G_READCYCLECOUNTER\000"
1007 /* 2685 */ "G_READSTEADYCOUNTER\000"
1008 /* 2705 */ "G_READ_REGISTER\000"
1009 /* 2721 */ "G_WRITE_REGISTER\000"
1010 /* 2738 */ "G_ASHR\000"
1011 /* 2745 */ "G_FSHR\000"
1012 /* 2752 */ "G_LSHR\000"
1013 /* 2759 */ "G_CLMULR\000"
1014 /* 2768 */ "CONVERGENCECTRL_ANCHOR\000"
1015 /* 2791 */ "G_FFLOOR\000"
1016 /* 2800 */ "G_SAVGFLOOR\000"
1017 /* 2812 */ "G_UAVGFLOOR\000"
1018 /* 2824 */ "G_EXTRACT_SUBVECTOR\000"
1019 /* 2844 */ "G_INSERT_SUBVECTOR\000"
1020 /* 2863 */ "G_BUILD_VECTOR\000"
1021 /* 2878 */ "G_SHUFFLE_VECTOR\000"
1022 /* 2895 */ "G_STEP_VECTOR\000"
1023 /* 2909 */ "G_SPLAT_VECTOR\000"
1024 /* 2924 */ "G_VECREDUCE_XOR\000"
1025 /* 2940 */ "G_XOR\000"
1026 /* 2946 */ "G_ATOMICRMW_XOR\000"
1027 /* 2962 */ "G_VECREDUCE_OR\000"
1028 /* 2977 */ "G_OR\000"
1029 /* 2982 */ "G_ATOMICRMW_OR\000"
1030 /* 2997 */ "G_ROTR\000"
1031 /* 3004 */ "G_INTTOPTR\000"
1032 /* 3015 */ "G_FABS\000"
1033 /* 3022 */ "G_ABS\000"
1034 /* 3028 */ "G_ABDS\000"
1035 /* 3035 */ "G_UNMERGE_VALUES\000"
1036 /* 3052 */ "G_MERGE_VALUES\000"
1037 /* 3067 */ "G_CTLS\000"
1038 /* 3074 */ "G_FACOS\000"
1039 /* 3082 */ "G_FCOS\000"
1040 /* 3089 */ "G_FSINCOS\000"
1041 /* 3099 */ "G_STRICT_FCMPS\000"
1042 /* 3114 */ "G_CONCAT_VECTORS\000"
1043 /* 3131 */ "COPY_TO_REGCLASS\000"
1044 /* 3148 */ "G_IS_FPCLASS\000"
1045 /* 3161 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
1046 /* 3191 */ "G_VECTOR_COMPRESS\000"
1047 /* 3209 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
1048 /* 3236 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
1049 /* 3274 */ "G_TRUNC_SSAT_S\000"
1050 /* 3289 */ "G_SSUBSAT\000"
1051 /* 3299 */ "G_USUBSAT\000"
1052 /* 3309 */ "G_SADDSAT\000"
1053 /* 3319 */ "G_UADDSAT\000"
1054 /* 3329 */ "G_SSHLSAT\000"
1055 /* 3339 */ "G_USHLSAT\000"
1056 /* 3349 */ "G_SMULFIXSAT\000"
1057 /* 3362 */ "G_UMULFIXSAT\000"
1058 /* 3375 */ "G_SDIVFIXSAT\000"
1059 /* 3388 */ "G_UDIVFIXSAT\000"
1060 /* 3401 */ "G_ATOMICRMW_USUB_SAT\000"
1061 /* 3422 */ "G_FPTOSI_SAT\000"
1062 /* 3435 */ "G_FPTOUI_SAT\000"
1063 /* 3448 */ "G_EXTRACT\000"
1064 /* 3458 */ "G_SELECT\000"
1065 /* 3467 */ "G_BRINDIRECT\000"
1066 /* 3480 */ "PATCHABLE_RET\000"
1067 /* 3494 */ "G_MEMSET\000"
1068 /* 3503 */ "PATCHABLE_FUNCTION_EXIT\000"
1069 /* 3527 */ "G_BRJT\000"
1070 /* 3534 */ "G_EXTRACT_VECTOR_ELT\000"
1071 /* 3555 */ "G_INSERT_VECTOR_ELT\000"
1072 /* 3575 */ "G_FCONSTANT\000"
1073 /* 3587 */ "G_CONSTANT\000"
1074 /* 3598 */ "G_INTRINSIC_CONVERGENT\000"
1075 /* 3621 */ "STATEPOINT\000"
1076 /* 3632 */ "PATCHPOINT\000"
1077 /* 3643 */ "G_PTRTOINT\000"
1078 /* 3654 */ "G_FRINT\000"
1079 /* 3662 */ "G_INTRINSIC_LLRINT\000"
1080 /* 3681 */ "G_INTRINSIC_LRINT\000"
1081 /* 3699 */ "G_FNEARBYINT\000"
1082 /* 3712 */ "G_VASTART\000"
1083 /* 3722 */ "LIFETIME_START\000"
1084 /* 3737 */ "G_INVOKE_REGION_START\000"
1085 /* 3759 */ "G_INSERT\000"
1086 /* 3768 */ "G_FSQRT\000"
1087 /* 3776 */ "G_STRICT_FSQRT\000"
1088 /* 3791 */ "G_BITCAST\000"
1089 /* 3801 */ "G_ADDRSPACE_CAST\000"
1090 /* 3818 */ "DBG_VALUE_LIST\000"
1091 /* 3833 */ "G_FPEXT\000"
1092 /* 3841 */ "G_SEXT\000"
1093 /* 3848 */ "G_ASSERT_SEXT\000"
1094 /* 3862 */ "G_ANYEXT\000"
1095 /* 3871 */ "G_ZEXT\000"
1096 /* 3878 */ "G_ASSERT_ZEXT\000"
1097 /* 3892 */ "G_ABDU\000"
1098 /* 3899 */ "G_TRUNC_SSAT_U\000"
1099 /* 3914 */ "G_TRUNC_USAT_U\000"
1100 /* 3929 */ "G_FDIV\000"
1101 /* 3936 */ "G_STRICT_FDIV\000"
1102 /* 3950 */ "G_SDIV\000"
1103 /* 3957 */ "G_UDIV\000"
1104 /* 3964 */ "G_GET_FPENV\000"
1105 /* 3976 */ "G_RESET_FPENV\000"
1106 /* 3990 */ "G_SET_FPENV\000"
1107 /* 4002 */ "G_FPOW\000"
1108 /* 4009 */ "G_VECREDUCE_FMAX\000"
1109 /* 4026 */ "G_ATOMICRMW_FMAX\000"
1110 /* 4043 */ "G_VECREDUCE_SMAX\000"
1111 /* 4060 */ "G_SMAX\000"
1112 /* 4067 */ "G_VECREDUCE_UMAX\000"
1113 /* 4084 */ "G_UMAX\000"
1114 /* 4091 */ "G_ATOMICRMW_UMAX\000"
1115 /* 4108 */ "G_ATOMICRMW_MAX\000"
1116 /* 4124 */ "G_FRAME_INDEX\000"
1117 /* 4138 */ "G_SBFX\000"
1118 /* 4145 */ "G_UBFX\000"
1119 /* 4152 */ "G_SMULFIX\000"
1120 /* 4162 */ "G_UMULFIX\000"
1121 /* 4172 */ "G_SDIVFIX\000"
1122 /* 4182 */ "G_UDIVFIX\000"
1123 /* 4192 */ "G_MEMCPY\000"
1124 /* 4201 */ "COPY\000"
1125 /* 4206 */ "CONVERGENCECTRL_ENTRY\000"
1126 /* 4228 */ "G_CTLZ\000"
1127 /* 4235 */ "G_CTTZ\000"
1128 /* 4242 */ "DummyInst\000"
1129};
1130#ifdef __GNUC__
1131#pragma GCC diagnostic pop
1132#endif
1133
1134extern const unsigned DirectXInstrNameIndices[] = {
1135 1309U, 1723U, 2580U, 2177U, 1382U, 1363U, 1391U, 1551U,
1136 1093U, 1108U, 1059U, 1046U, 1135U, 3131U, 922U, 3818U,
1137 1072U, 1305U, 1372U, 661U, 4201U, 1339U, 783U, 3722U,
1138 488U, 612U, 649U, 2309U, 1539U, 3632U, 595U, 2515U,
1139 1228U, 3621U, 833U, 2503U, 2490U, 2641U, 3480U, 3503U,
1140 1471U, 1518U, 1491U, 1408U, 913U, 2606U, 2263U, 822U,
1141 4206U, 2768U, 2461U, 970U, 3848U, 3878U, 2020U, 401U,
1142 100U, 1662U, 3950U, 3957U, 1689U, 1696U, 1703U, 1713U,
1143 466U, 2977U, 2940U, 3028U, 3892U, 2812U, 1460U, 2800U,
1144 1449U, 1057U, 1307U, 4124U, 932U, 947U, 1556U, 3448U,
1145 3035U, 3759U, 3052U, 2863U, 170U, 3114U, 3643U, 3004U,
1146 3791U, 1013U, 2617U, 569U, 144U, 551U, 3681U, 3662U,
1147 1998U, 2666U, 2685U, 302U, 246U, 276U, 215U, 287U,
1148 227U, 257U, 892U, 846U, 876U, 3161U, 1149U, 1166U,
1149 417U, 106U, 472U, 433U, 2982U, 2946U, 4108U, 2146U,
1150 4091U, 2129U, 368U, 83U, 4026U, 2064U, 1818U, 1765U,
1151 1939U, 1877U, 2371U, 2349U, 510U, 3401U, 641U, 1245U,
1152 501U, 3467U, 3737U, 122U, 3209U, 3598U, 3236U, 3862U,
1153 162U, 3274U, 3899U, 3914U, 3587U, 3575U, 3712U, 1220U,
1154 3841U, 1122U, 3871U, 1435U, 2752U, 2738U, 1428U, 2745U,
1155 2997U, 1572U, 2440U, 2419U, 2447U, 2454U, 3458U, 2255U,
1156 682U, 2239U, 633U, 2247U, 674U, 2231U, 625U, 2293U,
1157 2285U, 1273U, 1265U, 3319U, 3309U, 3299U, 3289U, 3339U,
1158 3329U, 4152U, 4162U, 3349U, 3362U, 4172U, 4182U, 3375U,
1159 3388U, 326U, 62U, 1596U, 43U, 208U, 3929U, 1668U,
1160 1038U, 4002U, 1331U, 2559U, 35U, 9U, 1213U, 18U,
1161 0U, 2534U, 2566U, 1086U, 3833U, 134U, 1313U, 1322U,
1162 2401U, 2410U, 3422U, 3435U, 3015U, 2035U, 3148U, 1022U,
1163 1963U, 1973U, 731U, 746U, 1754U, 1807U, 1863U, 1925U,
1164 3964U, 3990U, 3976U, 690U, 718U, 703U, 1183U, 1198U,
1165 407U, 1353U, 2098U, 4060U, 2122U, 4084U, 3022U, 542U,
1166 532U, 2575U, 3527U, 761U, 2844U, 2824U, 3555U, 3534U,
1167 2878U, 2909U, 2895U, 3191U, 4235U, 2212U, 4228U, 2193U,
1168 3067U, 2482U, 2393U, 900U, 1638U, 1256U, 2759U, 1441U,
1169 3082U, 2170U, 3089U, 1991U, 3074U, 2162U, 1983U, 26U,
1170 1297U, 1289U, 1281U, 3768U, 2791U, 3654U, 3699U, 3801U,
1171 2593U, 770U, 191U, 991U, 861U, 354U, 69U, 1624U,
1172 3936U, 1675U, 49U, 3776U, 2543U, 2426U, 3099U, 2705U,
1173 2721U, 4192U, 806U, 1003U, 3494U, 2301U, 790U, 2342U,
1174 2318U, 2330U, 333U, 1603U, 309U, 1579U, 4009U, 2047U,
1175 1786U, 1733U, 1901U, 1839U, 385U, 1646U, 450U, 2962U,
1176 2924U, 4043U, 2081U, 4067U, 2105U, 4138U, 4145U, 4242U,
1177};
1178
1179static inline void InitDirectXMCInstrInfo(MCInstrInfo *II) {
1180 II->InitMCInstrInfo(DirectXDescs.Insts, DirectXInstrNameIndices, DirectXInstrNameData, nullptr, nullptr, 336, nullptr, 0);
1181}
1182
1183
1184} // namespace llvm
1185
1186#endif // GET_INSTRINFO_MC_DESC
1187
1188#ifdef GET_INSTRINFO_HEADER
1189#undef GET_INSTRINFO_HEADER
1190
1191namespace llvm {
1192
1193struct DirectXGenInstrInfo : public TargetInstrInfo {
1194 explicit DirectXGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1195 ~DirectXGenInstrInfo() override = default;
1196};
1197
1198} // namespace llvm
1199
1200namespace llvm::dxil {
1201
1202
1203} // namespace llvm::dxil
1204
1205#endif // GET_INSTRINFO_HEADER
1206
1207#ifdef GET_INSTRINFO_HELPER_DECLS
1208#undef GET_INSTRINFO_HELPER_DECLS
1209
1210
1211#endif // GET_INSTRINFO_HELPER_DECLS
1212
1213#ifdef GET_INSTRINFO_HELPERS
1214#undef GET_INSTRINFO_HELPERS
1215
1216
1217#endif // GET_INSTRINFO_HELPERS
1218
1219#ifdef GET_INSTRINFO_CTOR_DTOR
1220#undef GET_INSTRINFO_CTOR_DTOR
1221
1222namespace llvm {
1223
1224extern const DirectXInstrTable DirectXDescs;
1225extern const unsigned DirectXInstrNameIndices[];
1226extern const char DirectXInstrNameData[];
1227DirectXGenInstrInfo::DirectXGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1228 : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1229 InitMCInstrInfo(DirectXDescs.Insts, DirectXInstrNameIndices, DirectXInstrNameData, nullptr, nullptr, 336);
1230}
1231
1232} // namespace llvm
1233
1234#endif // GET_INSTRINFO_CTOR_DTOR
1235
1236#ifdef GET_INSTRINFO_MC_HELPER_DECLS
1237#undef GET_INSTRINFO_MC_HELPER_DECLS
1238
1239namespace llvm {
1240
1241class MCInst;
1242class FeatureBitset;
1243
1244namespace DirectX_MC {
1245
1246void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
1247
1248} // namespace DirectX_MC
1249
1250} // namespace llvm
1251
1252#endif // GET_INSTRINFO_MC_HELPER_DECLS
1253
1254#ifdef GET_INSTRINFO_MC_HELPERS
1255#undef GET_INSTRINFO_MC_HELPERS
1256
1257namespace llvm::DirectX_MC {
1258
1259
1260} // namespace llvm::DirectX_MC
1261
1262#endif // GET_INSTRINFO_MC_HELPERS
1263
1264#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
1265 defined(GET_AVAILABLE_OPCODE_CHECKER)
1266#define GET_COMPUTE_FEATURES
1267#endif
1268#ifdef GET_COMPUTE_FEATURES
1269#undef GET_COMPUTE_FEATURES
1270
1271namespace llvm::DirectX_MC {
1272
1273// Bits for subtarget features that participate in instruction matching.
1274enum SubtargetFeatureBits : uint8_t {
1275};
1276
1277inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
1278 FeatureBitset Features;
1279 return Features;
1280}
1281
1282inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
1283 enum : uint8_t {
1284 CEFBS_None,
1285 };
1286
1287 static constexpr FeatureBitset FeatureBitsets[] = {
1288 {}, // CEFBS_None
1289 };
1290 static constexpr uint8_t RequiredFeaturesRefs[] = {
1291 CEFBS_None, // PHI
1292 CEFBS_None, // INLINEASM
1293 CEFBS_None, // INLINEASM_BR
1294 CEFBS_None, // CFI_INSTRUCTION
1295 CEFBS_None, // EH_LABEL
1296 CEFBS_None, // GC_LABEL
1297 CEFBS_None, // ANNOTATION_LABEL
1298 CEFBS_None, // KILL
1299 CEFBS_None, // EXTRACT_SUBREG
1300 CEFBS_None, // INSERT_SUBREG
1301 CEFBS_None, // IMPLICIT_DEF
1302 CEFBS_None, // INIT_UNDEF
1303 CEFBS_None, // SUBREG_TO_REG
1304 CEFBS_None, // COPY_TO_REGCLASS
1305 CEFBS_None, // DBG_VALUE
1306 CEFBS_None, // DBG_VALUE_LIST
1307 CEFBS_None, // DBG_INSTR_REF
1308 CEFBS_None, // DBG_PHI
1309 CEFBS_None, // DBG_LABEL
1310 CEFBS_None, // REG_SEQUENCE
1311 CEFBS_None, // COPY
1312 CEFBS_None, // COPY_LANEMASK
1313 CEFBS_None, // BUNDLE
1314 CEFBS_None, // LIFETIME_START
1315 CEFBS_None, // LIFETIME_END
1316 CEFBS_None, // PSEUDO_PROBE
1317 CEFBS_None, // ARITH_FENCE
1318 CEFBS_None, // STACKMAP
1319 CEFBS_None, // FENTRY_CALL
1320 CEFBS_None, // PATCHPOINT
1321 CEFBS_None, // LOAD_STACK_GUARD
1322 CEFBS_None, // PREALLOCATED_SETUP
1323 CEFBS_None, // PREALLOCATED_ARG
1324 CEFBS_None, // STATEPOINT
1325 CEFBS_None, // LOCAL_ESCAPE
1326 CEFBS_None, // FAULTING_OP
1327 CEFBS_None, // PATCHABLE_OP
1328 CEFBS_None, // PATCHABLE_FUNCTION_ENTER
1329 CEFBS_None, // PATCHABLE_RET
1330 CEFBS_None, // PATCHABLE_FUNCTION_EXIT
1331 CEFBS_None, // PATCHABLE_TAIL_CALL
1332 CEFBS_None, // PATCHABLE_EVENT_CALL
1333 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
1334 CEFBS_None, // ICALL_BRANCH_FUNNEL
1335 CEFBS_None, // FAKE_USE
1336 CEFBS_None, // MEMBARRIER
1337 CEFBS_None, // JUMP_TABLE_DEBUG_INFO
1338 CEFBS_None, // RELOC_NONE
1339 CEFBS_None, // CONVERGENCECTRL_ENTRY
1340 CEFBS_None, // CONVERGENCECTRL_ANCHOR
1341 CEFBS_None, // CONVERGENCECTRL_LOOP
1342 CEFBS_None, // CONVERGENCECTRL_GLUE
1343 CEFBS_None, // G_ASSERT_SEXT
1344 CEFBS_None, // G_ASSERT_ZEXT
1345 CEFBS_None, // G_ASSERT_ALIGN
1346 CEFBS_None, // G_ADD
1347 CEFBS_None, // G_SUB
1348 CEFBS_None, // G_MUL
1349 CEFBS_None, // G_SDIV
1350 CEFBS_None, // G_UDIV
1351 CEFBS_None, // G_SREM
1352 CEFBS_None, // G_UREM
1353 CEFBS_None, // G_SDIVREM
1354 CEFBS_None, // G_UDIVREM
1355 CEFBS_None, // G_AND
1356 CEFBS_None, // G_OR
1357 CEFBS_None, // G_XOR
1358 CEFBS_None, // G_ABDS
1359 CEFBS_None, // G_ABDU
1360 CEFBS_None, // G_UAVGFLOOR
1361 CEFBS_None, // G_UAVGCEIL
1362 CEFBS_None, // G_SAVGFLOOR
1363 CEFBS_None, // G_SAVGCEIL
1364 CEFBS_None, // G_IMPLICIT_DEF
1365 CEFBS_None, // G_PHI
1366 CEFBS_None, // G_FRAME_INDEX
1367 CEFBS_None, // G_GLOBAL_VALUE
1368 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
1369 CEFBS_None, // G_CONSTANT_POOL
1370 CEFBS_None, // G_EXTRACT
1371 CEFBS_None, // G_UNMERGE_VALUES
1372 CEFBS_None, // G_INSERT
1373 CEFBS_None, // G_MERGE_VALUES
1374 CEFBS_None, // G_BUILD_VECTOR
1375 CEFBS_None, // G_BUILD_VECTOR_TRUNC
1376 CEFBS_None, // G_CONCAT_VECTORS
1377 CEFBS_None, // G_PTRTOINT
1378 CEFBS_None, // G_INTTOPTR
1379 CEFBS_None, // G_BITCAST
1380 CEFBS_None, // G_FREEZE
1381 CEFBS_None, // G_CONSTANT_FOLD_BARRIER
1382 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
1383 CEFBS_None, // G_INTRINSIC_TRUNC
1384 CEFBS_None, // G_INTRINSIC_ROUND
1385 CEFBS_None, // G_INTRINSIC_LRINT
1386 CEFBS_None, // G_INTRINSIC_LLRINT
1387 CEFBS_None, // G_INTRINSIC_ROUNDEVEN
1388 CEFBS_None, // G_READCYCLECOUNTER
1389 CEFBS_None, // G_READSTEADYCOUNTER
1390 CEFBS_None, // G_LOAD
1391 CEFBS_None, // G_SEXTLOAD
1392 CEFBS_None, // G_ZEXTLOAD
1393 CEFBS_None, // G_FPEXTLOAD
1394 CEFBS_None, // G_INDEXED_LOAD
1395 CEFBS_None, // G_INDEXED_SEXTLOAD
1396 CEFBS_None, // G_INDEXED_ZEXTLOAD
1397 CEFBS_None, // G_STORE
1398 CEFBS_None, // G_FPTRUNCSTORE
1399 CEFBS_None, // G_INDEXED_STORE
1400 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1401 CEFBS_None, // G_ATOMIC_CMPXCHG
1402 CEFBS_None, // G_ATOMICRMW_XCHG
1403 CEFBS_None, // G_ATOMICRMW_ADD
1404 CEFBS_None, // G_ATOMICRMW_SUB
1405 CEFBS_None, // G_ATOMICRMW_AND
1406 CEFBS_None, // G_ATOMICRMW_NAND
1407 CEFBS_None, // G_ATOMICRMW_OR
1408 CEFBS_None, // G_ATOMICRMW_XOR
1409 CEFBS_None, // G_ATOMICRMW_MAX
1410 CEFBS_None, // G_ATOMICRMW_MIN
1411 CEFBS_None, // G_ATOMICRMW_UMAX
1412 CEFBS_None, // G_ATOMICRMW_UMIN
1413 CEFBS_None, // G_ATOMICRMW_FADD
1414 CEFBS_None, // G_ATOMICRMW_FSUB
1415 CEFBS_None, // G_ATOMICRMW_FMAX
1416 CEFBS_None, // G_ATOMICRMW_FMIN
1417 CEFBS_None, // G_ATOMICRMW_FMAXIMUM
1418 CEFBS_None, // G_ATOMICRMW_FMINIMUM
1419 CEFBS_None, // G_ATOMICRMW_FMAXIMUMNUM
1420 CEFBS_None, // G_ATOMICRMW_FMINIMUMNUM
1421 CEFBS_None, // G_ATOMICRMW_UINC_WRAP
1422 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
1423 CEFBS_None, // G_ATOMICRMW_USUB_COND
1424 CEFBS_None, // G_ATOMICRMW_USUB_SAT
1425 CEFBS_None, // G_FENCE
1426 CEFBS_None, // G_PREFETCH
1427 CEFBS_None, // G_BRCOND
1428 CEFBS_None, // G_BRINDIRECT
1429 CEFBS_None, // G_INVOKE_REGION_START
1430 CEFBS_None, // G_INTRINSIC
1431 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
1432 CEFBS_None, // G_INTRINSIC_CONVERGENT
1433 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1434 CEFBS_None, // G_ANYEXT
1435 CEFBS_None, // G_TRUNC
1436 CEFBS_None, // G_TRUNC_SSAT_S
1437 CEFBS_None, // G_TRUNC_SSAT_U
1438 CEFBS_None, // G_TRUNC_USAT_U
1439 CEFBS_None, // G_CONSTANT
1440 CEFBS_None, // G_FCONSTANT
1441 CEFBS_None, // G_VASTART
1442 CEFBS_None, // G_VAARG
1443 CEFBS_None, // G_SEXT
1444 CEFBS_None, // G_SEXT_INREG
1445 CEFBS_None, // G_ZEXT
1446 CEFBS_None, // G_SHL
1447 CEFBS_None, // G_LSHR
1448 CEFBS_None, // G_ASHR
1449 CEFBS_None, // G_FSHL
1450 CEFBS_None, // G_FSHR
1451 CEFBS_None, // G_ROTR
1452 CEFBS_None, // G_ROTL
1453 CEFBS_None, // G_ICMP
1454 CEFBS_None, // G_FCMP
1455 CEFBS_None, // G_SCMP
1456 CEFBS_None, // G_UCMP
1457 CEFBS_None, // G_SELECT
1458 CEFBS_None, // G_UADDO
1459 CEFBS_None, // G_UADDE
1460 CEFBS_None, // G_USUBO
1461 CEFBS_None, // G_USUBE
1462 CEFBS_None, // G_SADDO
1463 CEFBS_None, // G_SADDE
1464 CEFBS_None, // G_SSUBO
1465 CEFBS_None, // G_SSUBE
1466 CEFBS_None, // G_UMULO
1467 CEFBS_None, // G_SMULO
1468 CEFBS_None, // G_UMULH
1469 CEFBS_None, // G_SMULH
1470 CEFBS_None, // G_UADDSAT
1471 CEFBS_None, // G_SADDSAT
1472 CEFBS_None, // G_USUBSAT
1473 CEFBS_None, // G_SSUBSAT
1474 CEFBS_None, // G_USHLSAT
1475 CEFBS_None, // G_SSHLSAT
1476 CEFBS_None, // G_SMULFIX
1477 CEFBS_None, // G_UMULFIX
1478 CEFBS_None, // G_SMULFIXSAT
1479 CEFBS_None, // G_UMULFIXSAT
1480 CEFBS_None, // G_SDIVFIX
1481 CEFBS_None, // G_UDIVFIX
1482 CEFBS_None, // G_SDIVFIXSAT
1483 CEFBS_None, // G_UDIVFIXSAT
1484 CEFBS_None, // G_FADD
1485 CEFBS_None, // G_FSUB
1486 CEFBS_None, // G_FMUL
1487 CEFBS_None, // G_FMA
1488 CEFBS_None, // G_FMAD
1489 CEFBS_None, // G_FDIV
1490 CEFBS_None, // G_FREM
1491 CEFBS_None, // G_FMODF
1492 CEFBS_None, // G_FPOW
1493 CEFBS_None, // G_FPOWI
1494 CEFBS_None, // G_FEXP
1495 CEFBS_None, // G_FEXP2
1496 CEFBS_None, // G_FEXP10
1497 CEFBS_None, // G_FLOG
1498 CEFBS_None, // G_FLOG2
1499 CEFBS_None, // G_FLOG10
1500 CEFBS_None, // G_FLDEXP
1501 CEFBS_None, // G_FFREXP
1502 CEFBS_None, // G_FNEG
1503 CEFBS_None, // G_FPEXT
1504 CEFBS_None, // G_FPTRUNC
1505 CEFBS_None, // G_FPTOSI
1506 CEFBS_None, // G_FPTOUI
1507 CEFBS_None, // G_SITOFP
1508 CEFBS_None, // G_UITOFP
1509 CEFBS_None, // G_FPTOSI_SAT
1510 CEFBS_None, // G_FPTOUI_SAT
1511 CEFBS_None, // G_FABS
1512 CEFBS_None, // G_FCOPYSIGN
1513 CEFBS_None, // G_IS_FPCLASS
1514 CEFBS_None, // G_FCANONICALIZE
1515 CEFBS_None, // G_FMINNUM
1516 CEFBS_None, // G_FMAXNUM
1517 CEFBS_None, // G_FMINNUM_IEEE
1518 CEFBS_None, // G_FMAXNUM_IEEE
1519 CEFBS_None, // G_FMINIMUM
1520 CEFBS_None, // G_FMAXIMUM
1521 CEFBS_None, // G_FMINIMUMNUM
1522 CEFBS_None, // G_FMAXIMUMNUM
1523 CEFBS_None, // G_GET_FPENV
1524 CEFBS_None, // G_SET_FPENV
1525 CEFBS_None, // G_RESET_FPENV
1526 CEFBS_None, // G_GET_FPMODE
1527 CEFBS_None, // G_SET_FPMODE
1528 CEFBS_None, // G_RESET_FPMODE
1529 CEFBS_None, // G_GET_ROUNDING
1530 CEFBS_None, // G_SET_ROUNDING
1531 CEFBS_None, // G_PTR_ADD
1532 CEFBS_None, // G_PTRMASK
1533 CEFBS_None, // G_SMIN
1534 CEFBS_None, // G_SMAX
1535 CEFBS_None, // G_UMIN
1536 CEFBS_None, // G_UMAX
1537 CEFBS_None, // G_ABS
1538 CEFBS_None, // G_LROUND
1539 CEFBS_None, // G_LLROUND
1540 CEFBS_None, // G_BR
1541 CEFBS_None, // G_BRJT
1542 CEFBS_None, // G_VSCALE
1543 CEFBS_None, // G_INSERT_SUBVECTOR
1544 CEFBS_None, // G_EXTRACT_SUBVECTOR
1545 CEFBS_None, // G_INSERT_VECTOR_ELT
1546 CEFBS_None, // G_EXTRACT_VECTOR_ELT
1547 CEFBS_None, // G_SHUFFLE_VECTOR
1548 CEFBS_None, // G_SPLAT_VECTOR
1549 CEFBS_None, // G_STEP_VECTOR
1550 CEFBS_None, // G_VECTOR_COMPRESS
1551 CEFBS_None, // G_CTTZ
1552 CEFBS_None, // G_CTTZ_ZERO_POISON
1553 CEFBS_None, // G_CTLZ
1554 CEFBS_None, // G_CTLZ_ZERO_POISON
1555 CEFBS_None, // G_CTLS
1556 CEFBS_None, // G_CTPOP
1557 CEFBS_None, // G_BSWAP
1558 CEFBS_None, // G_BITREVERSE
1559 CEFBS_None, // G_CLMUL
1560 CEFBS_None, // G_CLMULH
1561 CEFBS_None, // G_CLMULR
1562 CEFBS_None, // G_FCEIL
1563 CEFBS_None, // G_FCOS
1564 CEFBS_None, // G_FSIN
1565 CEFBS_None, // G_FSINCOS
1566 CEFBS_None, // G_FTAN
1567 CEFBS_None, // G_FACOS
1568 CEFBS_None, // G_FASIN
1569 CEFBS_None, // G_FATAN
1570 CEFBS_None, // G_FATAN2
1571 CEFBS_None, // G_FCOSH
1572 CEFBS_None, // G_FSINH
1573 CEFBS_None, // G_FTANH
1574 CEFBS_None, // G_FSQRT
1575 CEFBS_None, // G_FFLOOR
1576 CEFBS_None, // G_FRINT
1577 CEFBS_None, // G_FNEARBYINT
1578 CEFBS_None, // G_ADDRSPACE_CAST
1579 CEFBS_None, // G_BLOCK_ADDR
1580 CEFBS_None, // G_JUMP_TABLE
1581 CEFBS_None, // G_DYN_STACKALLOC
1582 CEFBS_None, // G_STACKSAVE
1583 CEFBS_None, // G_STACKRESTORE
1584 CEFBS_None, // G_STRICT_FADD
1585 CEFBS_None, // G_STRICT_FSUB
1586 CEFBS_None, // G_STRICT_FMUL
1587 CEFBS_None, // G_STRICT_FDIV
1588 CEFBS_None, // G_STRICT_FREM
1589 CEFBS_None, // G_STRICT_FMA
1590 CEFBS_None, // G_STRICT_FSQRT
1591 CEFBS_None, // G_STRICT_FLDEXP
1592 CEFBS_None, // G_STRICT_FCMP
1593 CEFBS_None, // G_STRICT_FCMPS
1594 CEFBS_None, // G_READ_REGISTER
1595 CEFBS_None, // G_WRITE_REGISTER
1596 CEFBS_None, // G_MEMCPY
1597 CEFBS_None, // G_MEMCPY_INLINE
1598 CEFBS_None, // G_MEMMOVE
1599 CEFBS_None, // G_MEMSET
1600 CEFBS_None, // G_BZERO
1601 CEFBS_None, // G_MEMSET_INLINE
1602 CEFBS_None, // G_TRAP
1603 CEFBS_None, // G_DEBUGTRAP
1604 CEFBS_None, // G_UBSANTRAP
1605 CEFBS_None, // G_VECREDUCE_SEQ_FADD
1606 CEFBS_None, // G_VECREDUCE_SEQ_FMUL
1607 CEFBS_None, // G_VECREDUCE_FADD
1608 CEFBS_None, // G_VECREDUCE_FMUL
1609 CEFBS_None, // G_VECREDUCE_FMAX
1610 CEFBS_None, // G_VECREDUCE_FMIN
1611 CEFBS_None, // G_VECREDUCE_FMAXIMUM
1612 CEFBS_None, // G_VECREDUCE_FMINIMUM
1613 CEFBS_None, // G_VECREDUCE_FMAXIMUMNUM
1614 CEFBS_None, // G_VECREDUCE_FMINIMUMNUM
1615 CEFBS_None, // G_VECREDUCE_ADD
1616 CEFBS_None, // G_VECREDUCE_MUL
1617 CEFBS_None, // G_VECREDUCE_AND
1618 CEFBS_None, // G_VECREDUCE_OR
1619 CEFBS_None, // G_VECREDUCE_XOR
1620 CEFBS_None, // G_VECREDUCE_SMAX
1621 CEFBS_None, // G_VECREDUCE_SMIN
1622 CEFBS_None, // G_VECREDUCE_UMAX
1623 CEFBS_None, // G_VECREDUCE_UMIN
1624 CEFBS_None, // G_SBFX
1625 CEFBS_None, // G_UBFX
1626 CEFBS_None, // DummyInst
1627 };
1628
1629 assert(Opcode < 336);
1630 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
1631}
1632
1633
1634} // namespace llvm::DirectX_MC
1635
1636#endif // GET_COMPUTE_FEATURES
1637
1638#ifdef GET_AVAILABLE_OPCODE_CHECKER
1639#undef GET_AVAILABLE_OPCODE_CHECKER
1640
1641namespace llvm::DirectX_MC {
1642
1643bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
1644 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
1645 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
1646 FeatureBitset MissingFeatures =
1647 (AvailableFeatures & RequiredFeatures) ^
1648 RequiredFeatures;
1649 return !MissingFeatures.any();
1650}
1651
1652} // namespace llvm::DirectX_MC
1653
1654#endif // GET_AVAILABLE_OPCODE_CHECKER
1655
1656#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
1657#undef ENABLE_INSTR_PREDICATE_VERIFIER
1658
1659#include <sstream>
1660
1661namespace llvm::DirectX_MC {
1662
1663#ifndef NDEBUG
1664static const char *SubtargetFeatureNames[] = {
1665 nullptr
1666};
1667
1668#endif // NDEBUG
1669
1670void verifyInstructionPredicates(
1671 unsigned Opcode, const FeatureBitset &Features) {
1672#ifndef NDEBUG
1673 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
1674 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
1675 FeatureBitset MissingFeatures =
1676 (AvailableFeatures & RequiredFeatures) ^
1677 RequiredFeatures;
1678 if (MissingFeatures.any()) {
1679 std::ostringstream Msg;
1680 Msg << "Attempting to emit " << &DirectXInstrNameData[DirectXInstrNameIndices[Opcode]]
1681 << " instruction but the ";
1682 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
1683 if (MissingFeatures.test(i))
1684 Msg << SubtargetFeatureNames[i] << " ";
1685 Msg << "predicate(s) are not met";
1686 report_fatal_error(Msg.str().c_str());
1687 }
1688#endif // NDEBUG
1689}
1690
1691} // namespace llvm::DirectX_MC
1692
1693#endif // ENABLE_INSTR_PREDICATE_VERIFIER
1694
1695