| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* Target Register Enum Values *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | namespace llvm { |
| 10 | |
| 11 | class MCRegisterClass; |
| 12 | const MCRegisterClass &getDirectXMCRegisterClass(unsigned RC); |
| 13 | namespace dxil { |
| 14 | |
| 15 | enum : unsigned { |
| 16 | NoRegister, |
| 17 | DXIL = 1, |
| 18 | NUM_TARGET_REGS // 2 |
| 19 | }; |
| 20 | |
| 21 | } // namespace dxil |
| 22 | |
| 23 | // Register classes |
| 24 | |
| 25 | namespace dxil { |
| 26 | |
| 27 | enum { |
| 28 | DXILClassRegClassID = 0, |
| 29 | |
| 30 | }; |
| 31 | |
| 32 | } // namespace dxil |
| 33 | // Register pressure sets enum. |
| 34 | namespace dxil { |
| 35 | |
| 36 | enum RegisterPressureSets { |
| 37 | DXILClass = 0, |
| 38 | }; |
| 39 | |
| 40 | } // namespace dxil |
| 41 | |
| 42 | } // namespace llvm |
| 43 | |