| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* * Hexagon Disassembler *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | |
| 10 | #include "llvm/MC/MCInst.h" |
| 11 | #include "llvm/MC/MCSubtargetInfo.h" |
| 12 | #include "llvm/Support/DataTypes.h" |
| 13 | #include "llvm/Support/Debug.h" |
| 14 | #include "llvm/Support/LEB128.h" |
| 15 | #include "llvm/Support/raw_ostream.h" |
| 16 | #include "llvm/TargetParser/SubtargetFeature.h" |
| 17 | #include <assert.h> |
| 18 | |
| 19 | namespace { |
| 20 | |
| 21 | // InsnBitWidth is essentially a type trait used by the decoder emitter to query |
| 22 | // the supported bitwidth for a given type. But default, the value is 0, making |
| 23 | // it an invalid type for use as `InsnType` when instantiating the decoder. |
| 24 | // Individual targets are expected to provide specializations for these based |
| 25 | // on their usage. |
| 26 | template <typename T> constexpr uint32_t InsnBitWidth = 0; |
| 27 | |
| 28 | static const uint8_t DecoderTable32[19322] = { |
| 29 | OPC_SwitchField, 28, 4, // 0: switch Inst[31:28] { |
| 30 | 0, 4, // 3: case 0x0: { |
| 31 | OPC_Decode, 236, 8, 0, // 5: decode to A4_ext using decoder 0 |
| 32 | // 5: } |
| 33 | 1, 217, 6, // 9: case 0x1: { |
| 34 | OPC_SwitchField, 22, 6, // 12: switch Inst[27:22] { |
| 35 | 0, 23, // 15: case 0x0: { |
| 36 | OPC_SwitchField, 13, 1, // 17: switch Inst[13] { |
| 37 | 0, 8, // 20: case 0x0: { |
| 38 | OPC_CheckField, 0, 1, 0, // 22: check Inst[0] == 0x0 |
| 39 | OPC_Decode, 137, 11, 1, // 26: decode to J4_cmpeqi_tp0_jump_nt using decoder 1 |
| 40 | // 26: } |
| 41 | 1, 0, // 30: case 0x1: { |
| 42 | OPC_CheckField, 0, 1, 0, // 32: check Inst[0] == 0x0 |
| 43 | OPC_Decode, 138, 11, 1, // 36: decode to J4_cmpeqi_tp0_jump_t using decoder 1 |
| 44 | // 36: } |
| 45 | // 36: } // switch Inst[13] |
| 46 | // 36: } |
| 47 | 1, 23, // 40: case 0x1: { |
| 48 | OPC_SwitchField, 13, 1, // 42: switch Inst[13] { |
| 49 | 0, 8, // 45: case 0x0: { |
| 50 | OPC_CheckField, 0, 1, 0, // 47: check Inst[0] == 0x0 |
| 51 | OPC_Decode, 131, 11, 1, // 51: decode to J4_cmpeqi_fp0_jump_nt using decoder 1 |
| 52 | // 51: } |
| 53 | 1, 0, // 55: case 0x1: { |
| 54 | OPC_CheckField, 0, 1, 0, // 57: check Inst[0] == 0x0 |
| 55 | OPC_Decode, 132, 11, 1, // 61: decode to J4_cmpeqi_fp0_jump_t using decoder 1 |
| 56 | // 61: } |
| 57 | // 61: } // switch Inst[13] |
| 58 | // 61: } |
| 59 | 2, 23, // 65: case 0x2: { |
| 60 | OPC_SwitchField, 13, 1, // 67: switch Inst[13] { |
| 61 | 0, 8, // 70: case 0x0: { |
| 62 | OPC_CheckField, 0, 1, 0, // 72: check Inst[0] == 0x0 |
| 63 | OPC_Decode, 173, 11, 1, // 76: decode to J4_cmpgti_tp0_jump_nt using decoder 1 |
| 64 | // 76: } |
| 65 | 1, 0, // 80: case 0x1: { |
| 66 | OPC_CheckField, 0, 1, 0, // 82: check Inst[0] == 0x0 |
| 67 | OPC_Decode, 174, 11, 1, // 86: decode to J4_cmpgti_tp0_jump_t using decoder 1 |
| 68 | // 86: } |
| 69 | // 86: } // switch Inst[13] |
| 70 | // 86: } |
| 71 | 3, 23, // 90: case 0x3: { |
| 72 | OPC_SwitchField, 13, 1, // 92: switch Inst[13] { |
| 73 | 0, 8, // 95: case 0x0: { |
| 74 | OPC_CheckField, 0, 1, 0, // 97: check Inst[0] == 0x0 |
| 75 | OPC_Decode, 167, 11, 1, // 101: decode to J4_cmpgti_fp0_jump_nt using decoder 1 |
| 76 | // 101: } |
| 77 | 1, 0, // 105: case 0x1: { |
| 78 | OPC_CheckField, 0, 1, 0, // 107: check Inst[0] == 0x0 |
| 79 | OPC_Decode, 168, 11, 1, // 111: decode to J4_cmpgti_fp0_jump_t using decoder 1 |
| 80 | // 111: } |
| 81 | // 111: } // switch Inst[13] |
| 82 | // 111: } |
| 83 | 4, 23, // 115: case 0x4: { |
| 84 | OPC_SwitchField, 13, 1, // 117: switch Inst[13] { |
| 85 | 0, 8, // 120: case 0x0: { |
| 86 | OPC_CheckField, 0, 1, 0, // 122: check Inst[0] == 0x0 |
| 87 | OPC_Decode, 209, 11, 1, // 126: decode to J4_cmpgtui_tp0_jump_nt using decoder 1 |
| 88 | // 126: } |
| 89 | 1, 0, // 130: case 0x1: { |
| 90 | OPC_CheckField, 0, 1, 0, // 132: check Inst[0] == 0x0 |
| 91 | OPC_Decode, 210, 11, 1, // 136: decode to J4_cmpgtui_tp0_jump_t using decoder 1 |
| 92 | // 136: } |
| 93 | // 136: } // switch Inst[13] |
| 94 | // 136: } |
| 95 | 5, 23, // 140: case 0x5: { |
| 96 | OPC_SwitchField, 13, 1, // 142: switch Inst[13] { |
| 97 | 0, 8, // 145: case 0x0: { |
| 98 | OPC_CheckField, 0, 1, 0, // 147: check Inst[0] == 0x0 |
| 99 | OPC_Decode, 203, 11, 1, // 151: decode to J4_cmpgtui_fp0_jump_nt using decoder 1 |
| 100 | // 151: } |
| 101 | 1, 0, // 155: case 0x1: { |
| 102 | OPC_CheckField, 0, 1, 0, // 157: check Inst[0] == 0x0 |
| 103 | OPC_Decode, 204, 11, 1, // 161: decode to J4_cmpgtui_fp0_jump_t using decoder 1 |
| 104 | // 161: } |
| 105 | // 161: } // switch Inst[13] |
| 106 | // 161: } |
| 107 | 6, 63, // 165: case 0x6: { |
| 108 | OPC_SwitchField, 8, 6, // 167: switch Inst[13:8] { |
| 109 | 0, 8, // 170: case 0x0: { |
| 110 | OPC_CheckField, 0, 1, 0, // 172: check Inst[0] == 0x0 |
| 111 | OPC_Decode, 149, 11, 2, // 176: decode to J4_cmpeqn1_tp0_jump_nt using decoder 2 |
| 112 | // 176: } |
| 113 | 1, 8, // 180: case 0x1: { |
| 114 | OPC_CheckField, 0, 1, 0, // 182: check Inst[0] == 0x0 |
| 115 | OPC_Decode, 185, 11, 2, // 186: decode to J4_cmpgtn1_tp0_jump_nt using decoder 2 |
| 116 | // 186: } |
| 117 | 3, 8, // 190: case 0x3: { |
| 118 | OPC_CheckField, 0, 1, 0, // 192: check Inst[0] == 0x0 |
| 119 | OPC_Decode, 232, 11, 3, // 196: decode to J4_tstbit0_tp0_jump_nt using decoder 3 |
| 120 | // 196: } |
| 121 | 32, 8, // 200: case 0x20: { |
| 122 | OPC_CheckField, 0, 1, 0, // 202: check Inst[0] == 0x0 |
| 123 | OPC_Decode, 150, 11, 2, // 206: decode to J4_cmpeqn1_tp0_jump_t using decoder 2 |
| 124 | // 206: } |
| 125 | 33, 8, // 210: case 0x21: { |
| 126 | OPC_CheckField, 0, 1, 0, // 212: check Inst[0] == 0x0 |
| 127 | OPC_Decode, 186, 11, 2, // 216: decode to J4_cmpgtn1_tp0_jump_t using decoder 2 |
| 128 | // 216: } |
| 129 | 35, 0, // 220: case 0x23: { |
| 130 | OPC_CheckField, 0, 1, 0, // 222: check Inst[0] == 0x0 |
| 131 | OPC_Decode, 233, 11, 3, // 226: decode to J4_tstbit0_tp0_jump_t using decoder 3 |
| 132 | // 226: } |
| 133 | // 226: } // switch Inst[13:8] |
| 134 | // 226: } |
| 135 | 7, 63, // 230: case 0x7: { |
| 136 | OPC_SwitchField, 8, 6, // 232: switch Inst[13:8] { |
| 137 | 0, 8, // 235: case 0x0: { |
| 138 | OPC_CheckField, 0, 1, 0, // 237: check Inst[0] == 0x0 |
| 139 | OPC_Decode, 143, 11, 2, // 241: decode to J4_cmpeqn1_fp0_jump_nt using decoder 2 |
| 140 | // 241: } |
| 141 | 1, 8, // 245: case 0x1: { |
| 142 | OPC_CheckField, 0, 1, 0, // 247: check Inst[0] == 0x0 |
| 143 | OPC_Decode, 179, 11, 2, // 251: decode to J4_cmpgtn1_fp0_jump_nt using decoder 2 |
| 144 | // 251: } |
| 145 | 3, 8, // 255: case 0x3: { |
| 146 | OPC_CheckField, 0, 1, 0, // 257: check Inst[0] == 0x0 |
| 147 | OPC_Decode, 226, 11, 3, // 261: decode to J4_tstbit0_fp0_jump_nt using decoder 3 |
| 148 | // 261: } |
| 149 | 32, 8, // 265: case 0x20: { |
| 150 | OPC_CheckField, 0, 1, 0, // 267: check Inst[0] == 0x0 |
| 151 | OPC_Decode, 144, 11, 2, // 271: decode to J4_cmpeqn1_fp0_jump_t using decoder 2 |
| 152 | // 271: } |
| 153 | 33, 8, // 275: case 0x21: { |
| 154 | OPC_CheckField, 0, 1, 0, // 277: check Inst[0] == 0x0 |
| 155 | OPC_Decode, 180, 11, 2, // 281: decode to J4_cmpgtn1_fp0_jump_t using decoder 2 |
| 156 | // 281: } |
| 157 | 35, 0, // 285: case 0x23: { |
| 158 | OPC_CheckField, 0, 1, 0, // 287: check Inst[0] == 0x0 |
| 159 | OPC_Decode, 227, 11, 3, // 291: decode to J4_tstbit0_fp0_jump_t using decoder 3 |
| 160 | // 291: } |
| 161 | // 291: } // switch Inst[13:8] |
| 162 | // 291: } |
| 163 | 8, 23, // 295: case 0x8: { |
| 164 | OPC_SwitchField, 13, 1, // 297: switch Inst[13] { |
| 165 | 0, 8, // 300: case 0x0: { |
| 166 | OPC_CheckField, 0, 1, 0, // 302: check Inst[0] == 0x0 |
| 167 | OPC_Decode, 139, 11, 1, // 306: decode to J4_cmpeqi_tp1_jump_nt using decoder 1 |
| 168 | // 306: } |
| 169 | 1, 0, // 310: case 0x1: { |
| 170 | OPC_CheckField, 0, 1, 0, // 312: check Inst[0] == 0x0 |
| 171 | OPC_Decode, 140, 11, 1, // 316: decode to J4_cmpeqi_tp1_jump_t using decoder 1 |
| 172 | // 316: } |
| 173 | // 316: } // switch Inst[13] |
| 174 | // 316: } |
| 175 | 9, 23, // 320: case 0x9: { |
| 176 | OPC_SwitchField, 13, 1, // 322: switch Inst[13] { |
| 177 | 0, 8, // 325: case 0x0: { |
| 178 | OPC_CheckField, 0, 1, 0, // 327: check Inst[0] == 0x0 |
| 179 | OPC_Decode, 133, 11, 1, // 331: decode to J4_cmpeqi_fp1_jump_nt using decoder 1 |
| 180 | // 331: } |
| 181 | 1, 0, // 335: case 0x1: { |
| 182 | OPC_CheckField, 0, 1, 0, // 337: check Inst[0] == 0x0 |
| 183 | OPC_Decode, 134, 11, 1, // 341: decode to J4_cmpeqi_fp1_jump_t using decoder 1 |
| 184 | // 341: } |
| 185 | // 341: } // switch Inst[13] |
| 186 | // 341: } |
| 187 | 10, 23, // 345: case 0xa: { |
| 188 | OPC_SwitchField, 13, 1, // 347: switch Inst[13] { |
| 189 | 0, 8, // 350: case 0x0: { |
| 190 | OPC_CheckField, 0, 1, 0, // 352: check Inst[0] == 0x0 |
| 191 | OPC_Decode, 175, 11, 1, // 356: decode to J4_cmpgti_tp1_jump_nt using decoder 1 |
| 192 | // 356: } |
| 193 | 1, 0, // 360: case 0x1: { |
| 194 | OPC_CheckField, 0, 1, 0, // 362: check Inst[0] == 0x0 |
| 195 | OPC_Decode, 176, 11, 1, // 366: decode to J4_cmpgti_tp1_jump_t using decoder 1 |
| 196 | // 366: } |
| 197 | // 366: } // switch Inst[13] |
| 198 | // 366: } |
| 199 | 11, 23, // 370: case 0xb: { |
| 200 | OPC_SwitchField, 13, 1, // 372: switch Inst[13] { |
| 201 | 0, 8, // 375: case 0x0: { |
| 202 | OPC_CheckField, 0, 1, 0, // 377: check Inst[0] == 0x0 |
| 203 | OPC_Decode, 169, 11, 1, // 381: decode to J4_cmpgti_fp1_jump_nt using decoder 1 |
| 204 | // 381: } |
| 205 | 1, 0, // 385: case 0x1: { |
| 206 | OPC_CheckField, 0, 1, 0, // 387: check Inst[0] == 0x0 |
| 207 | OPC_Decode, 170, 11, 1, // 391: decode to J4_cmpgti_fp1_jump_t using decoder 1 |
| 208 | // 391: } |
| 209 | // 391: } // switch Inst[13] |
| 210 | // 391: } |
| 211 | 12, 23, // 395: case 0xc: { |
| 212 | OPC_SwitchField, 13, 1, // 397: switch Inst[13] { |
| 213 | 0, 8, // 400: case 0x0: { |
| 214 | OPC_CheckField, 0, 1, 0, // 402: check Inst[0] == 0x0 |
| 215 | OPC_Decode, 211, 11, 1, // 406: decode to J4_cmpgtui_tp1_jump_nt using decoder 1 |
| 216 | // 406: } |
| 217 | 1, 0, // 410: case 0x1: { |
| 218 | OPC_CheckField, 0, 1, 0, // 412: check Inst[0] == 0x0 |
| 219 | OPC_Decode, 212, 11, 1, // 416: decode to J4_cmpgtui_tp1_jump_t using decoder 1 |
| 220 | // 416: } |
| 221 | // 416: } // switch Inst[13] |
| 222 | // 416: } |
| 223 | 13, 23, // 420: case 0xd: { |
| 224 | OPC_SwitchField, 13, 1, // 422: switch Inst[13] { |
| 225 | 0, 8, // 425: case 0x0: { |
| 226 | OPC_CheckField, 0, 1, 0, // 427: check Inst[0] == 0x0 |
| 227 | OPC_Decode, 205, 11, 1, // 431: decode to J4_cmpgtui_fp1_jump_nt using decoder 1 |
| 228 | // 431: } |
| 229 | 1, 0, // 435: case 0x1: { |
| 230 | OPC_CheckField, 0, 1, 0, // 437: check Inst[0] == 0x0 |
| 231 | OPC_Decode, 206, 11, 1, // 441: decode to J4_cmpgtui_fp1_jump_t using decoder 1 |
| 232 | // 441: } |
| 233 | // 441: } // switch Inst[13] |
| 234 | // 441: } |
| 235 | 14, 63, // 445: case 0xe: { |
| 236 | OPC_SwitchField, 8, 6, // 447: switch Inst[13:8] { |
| 237 | 0, 8, // 450: case 0x0: { |
| 238 | OPC_CheckField, 0, 1, 0, // 452: check Inst[0] == 0x0 |
| 239 | OPC_Decode, 151, 11, 2, // 456: decode to J4_cmpeqn1_tp1_jump_nt using decoder 2 |
| 240 | // 456: } |
| 241 | 1, 8, // 460: case 0x1: { |
| 242 | OPC_CheckField, 0, 1, 0, // 462: check Inst[0] == 0x0 |
| 243 | OPC_Decode, 187, 11, 2, // 466: decode to J4_cmpgtn1_tp1_jump_nt using decoder 2 |
| 244 | // 466: } |
| 245 | 3, 8, // 470: case 0x3: { |
| 246 | OPC_CheckField, 0, 1, 0, // 472: check Inst[0] == 0x0 |
| 247 | OPC_Decode, 234, 11, 3, // 476: decode to J4_tstbit0_tp1_jump_nt using decoder 3 |
| 248 | // 476: } |
| 249 | 32, 8, // 480: case 0x20: { |
| 250 | OPC_CheckField, 0, 1, 0, // 482: check Inst[0] == 0x0 |
| 251 | OPC_Decode, 152, 11, 2, // 486: decode to J4_cmpeqn1_tp1_jump_t using decoder 2 |
| 252 | // 486: } |
| 253 | 33, 8, // 490: case 0x21: { |
| 254 | OPC_CheckField, 0, 1, 0, // 492: check Inst[0] == 0x0 |
| 255 | OPC_Decode, 188, 11, 2, // 496: decode to J4_cmpgtn1_tp1_jump_t using decoder 2 |
| 256 | // 496: } |
| 257 | 35, 0, // 500: case 0x23: { |
| 258 | OPC_CheckField, 0, 1, 0, // 502: check Inst[0] == 0x0 |
| 259 | OPC_Decode, 235, 11, 3, // 506: decode to J4_tstbit0_tp1_jump_t using decoder 3 |
| 260 | // 506: } |
| 261 | // 506: } // switch Inst[13:8] |
| 262 | // 506: } |
| 263 | 15, 63, // 510: case 0xf: { |
| 264 | OPC_SwitchField, 8, 6, // 512: switch Inst[13:8] { |
| 265 | 0, 8, // 515: case 0x0: { |
| 266 | OPC_CheckField, 0, 1, 0, // 517: check Inst[0] == 0x0 |
| 267 | OPC_Decode, 145, 11, 2, // 521: decode to J4_cmpeqn1_fp1_jump_nt using decoder 2 |
| 268 | // 521: } |
| 269 | 1, 8, // 525: case 0x1: { |
| 270 | OPC_CheckField, 0, 1, 0, // 527: check Inst[0] == 0x0 |
| 271 | OPC_Decode, 181, 11, 2, // 531: decode to J4_cmpgtn1_fp1_jump_nt using decoder 2 |
| 272 | // 531: } |
| 273 | 3, 8, // 535: case 0x3: { |
| 274 | OPC_CheckField, 0, 1, 0, // 537: check Inst[0] == 0x0 |
| 275 | OPC_Decode, 228, 11, 3, // 541: decode to J4_tstbit0_fp1_jump_nt using decoder 3 |
| 276 | // 541: } |
| 277 | 32, 8, // 545: case 0x20: { |
| 278 | OPC_CheckField, 0, 1, 0, // 547: check Inst[0] == 0x0 |
| 279 | OPC_Decode, 146, 11, 2, // 551: decode to J4_cmpeqn1_fp1_jump_t using decoder 2 |
| 280 | // 551: } |
| 281 | 33, 8, // 555: case 0x21: { |
| 282 | OPC_CheckField, 0, 1, 0, // 557: check Inst[0] == 0x0 |
| 283 | OPC_Decode, 182, 11, 2, // 561: decode to J4_cmpgtn1_fp1_jump_t using decoder 2 |
| 284 | // 561: } |
| 285 | 35, 0, // 565: case 0x23: { |
| 286 | OPC_CheckField, 0, 1, 0, // 567: check Inst[0] == 0x0 |
| 287 | OPC_Decode, 229, 11, 3, // 571: decode to J4_tstbit0_fp1_jump_t using decoder 3 |
| 288 | // 571: } |
| 289 | // 571: } // switch Inst[13:8] |
| 290 | // 571: } |
| 291 | 16, 43, // 575: case 0x10: { |
| 292 | OPC_SwitchField, 12, 2, // 577: switch Inst[13:12] { |
| 293 | 0, 8, // 580: case 0x0: { |
| 294 | OPC_CheckField, 0, 1, 0, // 582: check Inst[0] == 0x0 |
| 295 | OPC_Decode, 253, 10, 4, // 586: decode to J4_cmpeq_tp0_jump_nt using decoder 4 |
| 296 | // 586: } |
| 297 | 1, 8, // 590: case 0x1: { |
| 298 | OPC_CheckField, 0, 1, 0, // 592: check Inst[0] == 0x0 |
| 299 | OPC_Decode, 255, 10, 4, // 596: decode to J4_cmpeq_tp1_jump_nt using decoder 4 |
| 300 | // 596: } |
| 301 | 2, 8, // 600: case 0x2: { |
| 302 | OPC_CheckField, 0, 1, 0, // 602: check Inst[0] == 0x0 |
| 303 | OPC_Decode, 254, 10, 4, // 606: decode to J4_cmpeq_tp0_jump_t using decoder 4 |
| 304 | // 606: } |
| 305 | 3, 0, // 610: case 0x3: { |
| 306 | OPC_CheckField, 0, 1, 0, // 612: check Inst[0] == 0x0 |
| 307 | OPC_Decode, 128, 11, 4, // 616: decode to J4_cmpeq_tp1_jump_t using decoder 4 |
| 308 | // 616: } |
| 309 | // 616: } // switch Inst[13:12] |
| 310 | // 616: } |
| 311 | 17, 43, // 620: case 0x11: { |
| 312 | OPC_SwitchField, 12, 2, // 622: switch Inst[13:12] { |
| 313 | 0, 8, // 625: case 0x0: { |
| 314 | OPC_CheckField, 0, 1, 0, // 627: check Inst[0] == 0x0 |
| 315 | OPC_Decode, 247, 10, 4, // 631: decode to J4_cmpeq_fp0_jump_nt using decoder 4 |
| 316 | // 631: } |
| 317 | 1, 8, // 635: case 0x1: { |
| 318 | OPC_CheckField, 0, 1, 0, // 637: check Inst[0] == 0x0 |
| 319 | OPC_Decode, 249, 10, 4, // 641: decode to J4_cmpeq_fp1_jump_nt using decoder 4 |
| 320 | // 641: } |
| 321 | 2, 8, // 645: case 0x2: { |
| 322 | OPC_CheckField, 0, 1, 0, // 647: check Inst[0] == 0x0 |
| 323 | OPC_Decode, 248, 10, 4, // 651: decode to J4_cmpeq_fp0_jump_t using decoder 4 |
| 324 | // 651: } |
| 325 | 3, 0, // 655: case 0x3: { |
| 326 | OPC_CheckField, 0, 1, 0, // 657: check Inst[0] == 0x0 |
| 327 | OPC_Decode, 250, 10, 4, // 661: decode to J4_cmpeq_fp1_jump_t using decoder 4 |
| 328 | // 661: } |
| 329 | // 661: } // switch Inst[13:12] |
| 330 | // 661: } |
| 331 | 18, 43, // 665: case 0x12: { |
| 332 | OPC_SwitchField, 12, 2, // 667: switch Inst[13:12] { |
| 333 | 0, 8, // 670: case 0x0: { |
| 334 | OPC_CheckField, 0, 1, 0, // 672: check Inst[0] == 0x0 |
| 335 | OPC_Decode, 161, 11, 4, // 676: decode to J4_cmpgt_tp0_jump_nt using decoder 4 |
| 336 | // 676: } |
| 337 | 1, 8, // 680: case 0x1: { |
| 338 | OPC_CheckField, 0, 1, 0, // 682: check Inst[0] == 0x0 |
| 339 | OPC_Decode, 163, 11, 4, // 686: decode to J4_cmpgt_tp1_jump_nt using decoder 4 |
| 340 | // 686: } |
| 341 | 2, 8, // 690: case 0x2: { |
| 342 | OPC_CheckField, 0, 1, 0, // 692: check Inst[0] == 0x0 |
| 343 | OPC_Decode, 162, 11, 4, // 696: decode to J4_cmpgt_tp0_jump_t using decoder 4 |
| 344 | // 696: } |
| 345 | 3, 0, // 700: case 0x3: { |
| 346 | OPC_CheckField, 0, 1, 0, // 702: check Inst[0] == 0x0 |
| 347 | OPC_Decode, 164, 11, 4, // 706: decode to J4_cmpgt_tp1_jump_t using decoder 4 |
| 348 | // 706: } |
| 349 | // 706: } // switch Inst[13:12] |
| 350 | // 706: } |
| 351 | 19, 43, // 710: case 0x13: { |
| 352 | OPC_SwitchField, 12, 2, // 712: switch Inst[13:12] { |
| 353 | 0, 8, // 715: case 0x0: { |
| 354 | OPC_CheckField, 0, 1, 0, // 717: check Inst[0] == 0x0 |
| 355 | OPC_Decode, 155, 11, 4, // 721: decode to J4_cmpgt_fp0_jump_nt using decoder 4 |
| 356 | // 721: } |
| 357 | 1, 8, // 725: case 0x1: { |
| 358 | OPC_CheckField, 0, 1, 0, // 727: check Inst[0] == 0x0 |
| 359 | OPC_Decode, 157, 11, 4, // 731: decode to J4_cmpgt_fp1_jump_nt using decoder 4 |
| 360 | // 731: } |
| 361 | 2, 8, // 735: case 0x2: { |
| 362 | OPC_CheckField, 0, 1, 0, // 737: check Inst[0] == 0x0 |
| 363 | OPC_Decode, 156, 11, 4, // 741: decode to J4_cmpgt_fp0_jump_t using decoder 4 |
| 364 | // 741: } |
| 365 | 3, 0, // 745: case 0x3: { |
| 366 | OPC_CheckField, 0, 1, 0, // 747: check Inst[0] == 0x0 |
| 367 | OPC_Decode, 158, 11, 4, // 751: decode to J4_cmpgt_fp1_jump_t using decoder 4 |
| 368 | // 751: } |
| 369 | // 751: } // switch Inst[13:12] |
| 370 | // 751: } |
| 371 | 20, 43, // 755: case 0x14: { |
| 372 | OPC_SwitchField, 12, 2, // 757: switch Inst[13:12] { |
| 373 | 0, 8, // 760: case 0x0: { |
| 374 | OPC_CheckField, 0, 1, 0, // 762: check Inst[0] == 0x0 |
| 375 | OPC_Decode, 197, 11, 4, // 766: decode to J4_cmpgtu_tp0_jump_nt using decoder 4 |
| 376 | // 766: } |
| 377 | 1, 8, // 770: case 0x1: { |
| 378 | OPC_CheckField, 0, 1, 0, // 772: check Inst[0] == 0x0 |
| 379 | OPC_Decode, 199, 11, 4, // 776: decode to J4_cmpgtu_tp1_jump_nt using decoder 4 |
| 380 | // 776: } |
| 381 | 2, 8, // 780: case 0x2: { |
| 382 | OPC_CheckField, 0, 1, 0, // 782: check Inst[0] == 0x0 |
| 383 | OPC_Decode, 198, 11, 4, // 786: decode to J4_cmpgtu_tp0_jump_t using decoder 4 |
| 384 | // 786: } |
| 385 | 3, 0, // 790: case 0x3: { |
| 386 | OPC_CheckField, 0, 1, 0, // 792: check Inst[0] == 0x0 |
| 387 | OPC_Decode, 200, 11, 4, // 796: decode to J4_cmpgtu_tp1_jump_t using decoder 4 |
| 388 | // 796: } |
| 389 | // 796: } // switch Inst[13:12] |
| 390 | // 796: } |
| 391 | 21, 43, // 800: case 0x15: { |
| 392 | OPC_SwitchField, 12, 2, // 802: switch Inst[13:12] { |
| 393 | 0, 8, // 805: case 0x0: { |
| 394 | OPC_CheckField, 0, 1, 0, // 807: check Inst[0] == 0x0 |
| 395 | OPC_Decode, 191, 11, 4, // 811: decode to J4_cmpgtu_fp0_jump_nt using decoder 4 |
| 396 | // 811: } |
| 397 | 1, 8, // 815: case 0x1: { |
| 398 | OPC_CheckField, 0, 1, 0, // 817: check Inst[0] == 0x0 |
| 399 | OPC_Decode, 193, 11, 4, // 821: decode to J4_cmpgtu_fp1_jump_nt using decoder 4 |
| 400 | // 821: } |
| 401 | 2, 8, // 825: case 0x2: { |
| 402 | OPC_CheckField, 0, 1, 0, // 827: check Inst[0] == 0x0 |
| 403 | OPC_Decode, 192, 11, 4, // 831: decode to J4_cmpgtu_fp0_jump_t using decoder 4 |
| 404 | // 831: } |
| 405 | 3, 0, // 835: case 0x3: { |
| 406 | OPC_CheckField, 0, 1, 0, // 837: check Inst[0] == 0x0 |
| 407 | OPC_Decode, 194, 11, 4, // 841: decode to J4_cmpgtu_fp1_jump_t using decoder 4 |
| 408 | // 841: } |
| 409 | // 841: } // switch Inst[13:12] |
| 410 | // 841: } |
| 411 | 24, 8, // 845: case 0x18: { |
| 412 | OPC_CheckField, 0, 1, 0, // 847: check Inst[0] == 0x0 |
| 413 | OPC_Decode, 222, 11, 5, // 851: decode to J4_jumpseti using decoder 5 |
| 414 | // 851: } |
| 415 | 28, 0, // 855: case 0x1c: { |
| 416 | OPC_CheckField, 12, 2, 0, // 857: check Inst[13:12] == 0x0 |
| 417 | OPC_CheckField, 0, 1, 0, // 861: check Inst[0] == 0x0 |
| 418 | OPC_Decode, 223, 11, 6, // 865: decode to J4_jumpsetr using decoder 6 |
| 419 | // 865: } |
| 420 | // 865: } // switch Inst[27:22] |
| 421 | // 865: } |
| 422 | 2, 217, 5, // 869: case 0x2: { |
| 423 | OPC_SwitchField, 22, 6, // 872: switch Inst[27:22] { |
| 424 | 0, 31, // 875: case 0x0: { |
| 425 | OPC_SwitchField, 13, 1, // 877: switch Inst[13] { |
| 426 | 0, 12, // 880: case 0x0: { |
| 427 | OPC_CheckField, 19, 1, 0, // 882: check Inst[19] == 0x0 |
| 428 | OPC_CheckField, 0, 1, 0, // 886: check Inst[0] == 0x0 |
| 429 | OPC_Decode, 251, 10, 7, // 890: decode to J4_cmpeq_t_jumpnv_nt using decoder 7 |
| 430 | // 890: } |
| 431 | 1, 0, // 894: case 0x1: { |
| 432 | OPC_CheckField, 19, 1, 0, // 896: check Inst[19] == 0x0 |
| 433 | OPC_CheckField, 0, 1, 0, // 900: check Inst[0] == 0x0 |
| 434 | OPC_Decode, 252, 10, 7, // 904: decode to J4_cmpeq_t_jumpnv_t using decoder 7 |
| 435 | // 904: } |
| 436 | // 904: } // switch Inst[13] |
| 437 | // 904: } |
| 438 | 1, 31, // 908: case 0x1: { |
| 439 | OPC_SwitchField, 13, 1, // 910: switch Inst[13] { |
| 440 | 0, 12, // 913: case 0x0: { |
| 441 | OPC_CheckField, 19, 1, 0, // 915: check Inst[19] == 0x0 |
| 442 | OPC_CheckField, 0, 1, 0, // 919: check Inst[0] == 0x0 |
| 443 | OPC_Decode, 245, 10, 7, // 923: decode to J4_cmpeq_f_jumpnv_nt using decoder 7 |
| 444 | // 923: } |
| 445 | 1, 0, // 927: case 0x1: { |
| 446 | OPC_CheckField, 19, 1, 0, // 929: check Inst[19] == 0x0 |
| 447 | OPC_CheckField, 0, 1, 0, // 933: check Inst[0] == 0x0 |
| 448 | OPC_Decode, 246, 10, 7, // 937: decode to J4_cmpeq_f_jumpnv_t using decoder 7 |
| 449 | // 937: } |
| 450 | // 937: } // switch Inst[13] |
| 451 | // 937: } |
| 452 | 2, 31, // 941: case 0x2: { |
| 453 | OPC_SwitchField, 13, 1, // 943: switch Inst[13] { |
| 454 | 0, 12, // 946: case 0x0: { |
| 455 | OPC_CheckField, 19, 1, 0, // 948: check Inst[19] == 0x0 |
| 456 | OPC_CheckField, 0, 1, 0, // 952: check Inst[0] == 0x0 |
| 457 | OPC_Decode, 159, 11, 7, // 956: decode to J4_cmpgt_t_jumpnv_nt using decoder 7 |
| 458 | // 956: } |
| 459 | 1, 0, // 960: case 0x1: { |
| 460 | OPC_CheckField, 19, 1, 0, // 962: check Inst[19] == 0x0 |
| 461 | OPC_CheckField, 0, 1, 0, // 966: check Inst[0] == 0x0 |
| 462 | OPC_Decode, 160, 11, 7, // 970: decode to J4_cmpgt_t_jumpnv_t using decoder 7 |
| 463 | // 970: } |
| 464 | // 970: } // switch Inst[13] |
| 465 | // 970: } |
| 466 | 3, 31, // 974: case 0x3: { |
| 467 | OPC_SwitchField, 13, 1, // 976: switch Inst[13] { |
| 468 | 0, 12, // 979: case 0x0: { |
| 469 | OPC_CheckField, 19, 1, 0, // 981: check Inst[19] == 0x0 |
| 470 | OPC_CheckField, 0, 1, 0, // 985: check Inst[0] == 0x0 |
| 471 | OPC_Decode, 153, 11, 7, // 989: decode to J4_cmpgt_f_jumpnv_nt using decoder 7 |
| 472 | // 989: } |
| 473 | 1, 0, // 993: case 0x1: { |
| 474 | OPC_CheckField, 19, 1, 0, // 995: check Inst[19] == 0x0 |
| 475 | OPC_CheckField, 0, 1, 0, // 999: check Inst[0] == 0x0 |
| 476 | OPC_Decode, 154, 11, 7, // 1003: decode to J4_cmpgt_f_jumpnv_t using decoder 7 |
| 477 | // 1003: } |
| 478 | // 1003: } // switch Inst[13] |
| 479 | // 1003: } |
| 480 | 4, 31, // 1007: case 0x4: { |
| 481 | OPC_SwitchField, 13, 1, // 1009: switch Inst[13] { |
| 482 | 0, 12, // 1012: case 0x0: { |
| 483 | OPC_CheckField, 19, 1, 0, // 1014: check Inst[19] == 0x0 |
| 484 | OPC_CheckField, 0, 1, 0, // 1018: check Inst[0] == 0x0 |
| 485 | OPC_Decode, 195, 11, 7, // 1022: decode to J4_cmpgtu_t_jumpnv_nt using decoder 7 |
| 486 | // 1022: } |
| 487 | 1, 0, // 1026: case 0x1: { |
| 488 | OPC_CheckField, 19, 1, 0, // 1028: check Inst[19] == 0x0 |
| 489 | OPC_CheckField, 0, 1, 0, // 1032: check Inst[0] == 0x0 |
| 490 | OPC_Decode, 196, 11, 7, // 1036: decode to J4_cmpgtu_t_jumpnv_t using decoder 7 |
| 491 | // 1036: } |
| 492 | // 1036: } // switch Inst[13] |
| 493 | // 1036: } |
| 494 | 5, 31, // 1040: case 0x5: { |
| 495 | OPC_SwitchField, 13, 1, // 1042: switch Inst[13] { |
| 496 | 0, 12, // 1045: case 0x0: { |
| 497 | OPC_CheckField, 19, 1, 0, // 1047: check Inst[19] == 0x0 |
| 498 | OPC_CheckField, 0, 1, 0, // 1051: check Inst[0] == 0x0 |
| 499 | OPC_Decode, 189, 11, 7, // 1055: decode to J4_cmpgtu_f_jumpnv_nt using decoder 7 |
| 500 | // 1055: } |
| 501 | 1, 0, // 1059: case 0x1: { |
| 502 | OPC_CheckField, 19, 1, 0, // 1061: check Inst[19] == 0x0 |
| 503 | OPC_CheckField, 0, 1, 0, // 1065: check Inst[0] == 0x0 |
| 504 | OPC_Decode, 190, 11, 7, // 1069: decode to J4_cmpgtu_f_jumpnv_t using decoder 7 |
| 505 | // 1069: } |
| 506 | // 1069: } // switch Inst[13] |
| 507 | // 1069: } |
| 508 | 6, 31, // 1073: case 0x6: { |
| 509 | OPC_SwitchField, 13, 1, // 1075: switch Inst[13] { |
| 510 | 0, 12, // 1078: case 0x0: { |
| 511 | OPC_CheckField, 19, 1, 0, // 1080: check Inst[19] == 0x0 |
| 512 | OPC_CheckField, 0, 1, 0, // 1084: check Inst[0] == 0x0 |
| 513 | OPC_Decode, 215, 11, 8, // 1088: decode to J4_cmplt_t_jumpnv_nt using decoder 8 |
| 514 | // 1088: } |
| 515 | 1, 0, // 1092: case 0x1: { |
| 516 | OPC_CheckField, 19, 1, 0, // 1094: check Inst[19] == 0x0 |
| 517 | OPC_CheckField, 0, 1, 0, // 1098: check Inst[0] == 0x0 |
| 518 | OPC_Decode, 216, 11, 8, // 1102: decode to J4_cmplt_t_jumpnv_t using decoder 8 |
| 519 | // 1102: } |
| 520 | // 1102: } // switch Inst[13] |
| 521 | // 1102: } |
| 522 | 7, 31, // 1106: case 0x7: { |
| 523 | OPC_SwitchField, 13, 1, // 1108: switch Inst[13] { |
| 524 | 0, 12, // 1111: case 0x0: { |
| 525 | OPC_CheckField, 19, 1, 0, // 1113: check Inst[19] == 0x0 |
| 526 | OPC_CheckField, 0, 1, 0, // 1117: check Inst[0] == 0x0 |
| 527 | OPC_Decode, 213, 11, 8, // 1121: decode to J4_cmplt_f_jumpnv_nt using decoder 8 |
| 528 | // 1121: } |
| 529 | 1, 0, // 1125: case 0x1: { |
| 530 | OPC_CheckField, 19, 1, 0, // 1127: check Inst[19] == 0x0 |
| 531 | OPC_CheckField, 0, 1, 0, // 1131: check Inst[0] == 0x0 |
| 532 | OPC_Decode, 214, 11, 8, // 1135: decode to J4_cmplt_f_jumpnv_t using decoder 8 |
| 533 | // 1135: } |
| 534 | // 1135: } // switch Inst[13] |
| 535 | // 1135: } |
| 536 | 8, 31, // 1139: case 0x8: { |
| 537 | OPC_SwitchField, 13, 1, // 1141: switch Inst[13] { |
| 538 | 0, 12, // 1144: case 0x0: { |
| 539 | OPC_CheckField, 19, 1, 0, // 1146: check Inst[19] == 0x0 |
| 540 | OPC_CheckField, 0, 1, 0, // 1150: check Inst[0] == 0x0 |
| 541 | OPC_Decode, 219, 11, 8, // 1154: decode to J4_cmpltu_t_jumpnv_nt using decoder 8 |
| 542 | // 1154: } |
| 543 | 1, 0, // 1158: case 0x1: { |
| 544 | OPC_CheckField, 19, 1, 0, // 1160: check Inst[19] == 0x0 |
| 545 | OPC_CheckField, 0, 1, 0, // 1164: check Inst[0] == 0x0 |
| 546 | OPC_Decode, 220, 11, 8, // 1168: decode to J4_cmpltu_t_jumpnv_t using decoder 8 |
| 547 | // 1168: } |
| 548 | // 1168: } // switch Inst[13] |
| 549 | // 1168: } |
| 550 | 9, 31, // 1172: case 0x9: { |
| 551 | OPC_SwitchField, 13, 1, // 1174: switch Inst[13] { |
| 552 | 0, 12, // 1177: case 0x0: { |
| 553 | OPC_CheckField, 19, 1, 0, // 1179: check Inst[19] == 0x0 |
| 554 | OPC_CheckField, 0, 1, 0, // 1183: check Inst[0] == 0x0 |
| 555 | OPC_Decode, 217, 11, 8, // 1187: decode to J4_cmpltu_f_jumpnv_nt using decoder 8 |
| 556 | // 1187: } |
| 557 | 1, 0, // 1191: case 0x1: { |
| 558 | OPC_CheckField, 19, 1, 0, // 1193: check Inst[19] == 0x0 |
| 559 | OPC_CheckField, 0, 1, 0, // 1197: check Inst[0] == 0x0 |
| 560 | OPC_Decode, 218, 11, 8, // 1201: decode to J4_cmpltu_f_jumpnv_t using decoder 8 |
| 561 | // 1201: } |
| 562 | // 1201: } // switch Inst[13] |
| 563 | // 1201: } |
| 564 | 16, 31, // 1205: case 0x10: { |
| 565 | OPC_SwitchField, 13, 1, // 1207: switch Inst[13] { |
| 566 | 0, 12, // 1210: case 0x0: { |
| 567 | OPC_CheckField, 19, 1, 0, // 1212: check Inst[19] == 0x0 |
| 568 | OPC_CheckField, 0, 1, 0, // 1216: check Inst[0] == 0x0 |
| 569 | OPC_Decode, 135, 11, 9, // 1220: decode to J4_cmpeqi_t_jumpnv_nt using decoder 9 |
| 570 | // 1220: } |
| 571 | 1, 0, // 1224: case 0x1: { |
| 572 | OPC_CheckField, 19, 1, 0, // 1226: check Inst[19] == 0x0 |
| 573 | OPC_CheckField, 0, 1, 0, // 1230: check Inst[0] == 0x0 |
| 574 | OPC_Decode, 136, 11, 9, // 1234: decode to J4_cmpeqi_t_jumpnv_t using decoder 9 |
| 575 | // 1234: } |
| 576 | // 1234: } // switch Inst[13] |
| 577 | // 1234: } |
| 578 | 17, 31, // 1238: case 0x11: { |
| 579 | OPC_SwitchField, 13, 1, // 1240: switch Inst[13] { |
| 580 | 0, 12, // 1243: case 0x0: { |
| 581 | OPC_CheckField, 19, 1, 0, // 1245: check Inst[19] == 0x0 |
| 582 | OPC_CheckField, 0, 1, 0, // 1249: check Inst[0] == 0x0 |
| 583 | OPC_Decode, 129, 11, 9, // 1253: decode to J4_cmpeqi_f_jumpnv_nt using decoder 9 |
| 584 | // 1253: } |
| 585 | 1, 0, // 1257: case 0x1: { |
| 586 | OPC_CheckField, 19, 1, 0, // 1259: check Inst[19] == 0x0 |
| 587 | OPC_CheckField, 0, 1, 0, // 1263: check Inst[0] == 0x0 |
| 588 | OPC_Decode, 130, 11, 9, // 1267: decode to J4_cmpeqi_f_jumpnv_t using decoder 9 |
| 589 | // 1267: } |
| 590 | // 1267: } // switch Inst[13] |
| 591 | // 1267: } |
| 592 | 18, 31, // 1271: case 0x12: { |
| 593 | OPC_SwitchField, 13, 1, // 1273: switch Inst[13] { |
| 594 | 0, 12, // 1276: case 0x0: { |
| 595 | OPC_CheckField, 19, 1, 0, // 1278: check Inst[19] == 0x0 |
| 596 | OPC_CheckField, 0, 1, 0, // 1282: check Inst[0] == 0x0 |
| 597 | OPC_Decode, 171, 11, 9, // 1286: decode to J4_cmpgti_t_jumpnv_nt using decoder 9 |
| 598 | // 1286: } |
| 599 | 1, 0, // 1290: case 0x1: { |
| 600 | OPC_CheckField, 19, 1, 0, // 1292: check Inst[19] == 0x0 |
| 601 | OPC_CheckField, 0, 1, 0, // 1296: check Inst[0] == 0x0 |
| 602 | OPC_Decode, 172, 11, 9, // 1300: decode to J4_cmpgti_t_jumpnv_t using decoder 9 |
| 603 | // 1300: } |
| 604 | // 1300: } // switch Inst[13] |
| 605 | // 1300: } |
| 606 | 19, 31, // 1304: case 0x13: { |
| 607 | OPC_SwitchField, 13, 1, // 1306: switch Inst[13] { |
| 608 | 0, 12, // 1309: case 0x0: { |
| 609 | OPC_CheckField, 19, 1, 0, // 1311: check Inst[19] == 0x0 |
| 610 | OPC_CheckField, 0, 1, 0, // 1315: check Inst[0] == 0x0 |
| 611 | OPC_Decode, 165, 11, 9, // 1319: decode to J4_cmpgti_f_jumpnv_nt using decoder 9 |
| 612 | // 1319: } |
| 613 | 1, 0, // 1323: case 0x1: { |
| 614 | OPC_CheckField, 19, 1, 0, // 1325: check Inst[19] == 0x0 |
| 615 | OPC_CheckField, 0, 1, 0, // 1329: check Inst[0] == 0x0 |
| 616 | OPC_Decode, 166, 11, 9, // 1333: decode to J4_cmpgti_f_jumpnv_t using decoder 9 |
| 617 | // 1333: } |
| 618 | // 1333: } // switch Inst[13] |
| 619 | // 1333: } |
| 620 | 20, 31, // 1337: case 0x14: { |
| 621 | OPC_SwitchField, 13, 1, // 1339: switch Inst[13] { |
| 622 | 0, 12, // 1342: case 0x0: { |
| 623 | OPC_CheckField, 19, 1, 0, // 1344: check Inst[19] == 0x0 |
| 624 | OPC_CheckField, 0, 1, 0, // 1348: check Inst[0] == 0x0 |
| 625 | OPC_Decode, 207, 11, 9, // 1352: decode to J4_cmpgtui_t_jumpnv_nt using decoder 9 |
| 626 | // 1352: } |
| 627 | 1, 0, // 1356: case 0x1: { |
| 628 | OPC_CheckField, 19, 1, 0, // 1358: check Inst[19] == 0x0 |
| 629 | OPC_CheckField, 0, 1, 0, // 1362: check Inst[0] == 0x0 |
| 630 | OPC_Decode, 208, 11, 9, // 1366: decode to J4_cmpgtui_t_jumpnv_t using decoder 9 |
| 631 | // 1366: } |
| 632 | // 1366: } // switch Inst[13] |
| 633 | // 1366: } |
| 634 | 21, 31, // 1370: case 0x15: { |
| 635 | OPC_SwitchField, 13, 1, // 1372: switch Inst[13] { |
| 636 | 0, 12, // 1375: case 0x0: { |
| 637 | OPC_CheckField, 19, 1, 0, // 1377: check Inst[19] == 0x0 |
| 638 | OPC_CheckField, 0, 1, 0, // 1381: check Inst[0] == 0x0 |
| 639 | OPC_Decode, 201, 11, 9, // 1385: decode to J4_cmpgtui_f_jumpnv_nt using decoder 9 |
| 640 | // 1385: } |
| 641 | 1, 0, // 1389: case 0x1: { |
| 642 | OPC_CheckField, 19, 1, 0, // 1391: check Inst[19] == 0x0 |
| 643 | OPC_CheckField, 0, 1, 0, // 1395: check Inst[0] == 0x0 |
| 644 | OPC_Decode, 202, 11, 9, // 1399: decode to J4_cmpgtui_f_jumpnv_t using decoder 9 |
| 645 | // 1399: } |
| 646 | // 1399: } // switch Inst[13] |
| 647 | // 1399: } |
| 648 | 22, 31, // 1403: case 0x16: { |
| 649 | OPC_SwitchField, 8, 6, // 1405: switch Inst[13:8] { |
| 650 | 0, 12, // 1408: case 0x0: { |
| 651 | OPC_CheckField, 19, 1, 0, // 1410: check Inst[19] == 0x0 |
| 652 | OPC_CheckField, 0, 1, 0, // 1414: check Inst[0] == 0x0 |
| 653 | OPC_Decode, 230, 11, 10, // 1418: decode to J4_tstbit0_t_jumpnv_nt using decoder 10 |
| 654 | // 1418: } |
| 655 | 32, 0, // 1422: case 0x20: { |
| 656 | OPC_CheckField, 19, 1, 0, // 1424: check Inst[19] == 0x0 |
| 657 | OPC_CheckField, 0, 1, 0, // 1428: check Inst[0] == 0x0 |
| 658 | OPC_Decode, 231, 11, 10, // 1432: decode to J4_tstbit0_t_jumpnv_t using decoder 10 |
| 659 | // 1432: } |
| 660 | // 1432: } // switch Inst[13:8] |
| 661 | // 1432: } |
| 662 | 23, 31, // 1436: case 0x17: { |
| 663 | OPC_SwitchField, 8, 6, // 1438: switch Inst[13:8] { |
| 664 | 0, 12, // 1441: case 0x0: { |
| 665 | OPC_CheckField, 19, 1, 0, // 1443: check Inst[19] == 0x0 |
| 666 | OPC_CheckField, 0, 1, 0, // 1447: check Inst[0] == 0x0 |
| 667 | OPC_Decode, 224, 11, 10, // 1451: decode to J4_tstbit0_f_jumpnv_nt using decoder 10 |
| 668 | // 1451: } |
| 669 | 32, 0, // 1455: case 0x20: { |
| 670 | OPC_CheckField, 19, 1, 0, // 1457: check Inst[19] == 0x0 |
| 671 | OPC_CheckField, 0, 1, 0, // 1461: check Inst[0] == 0x0 |
| 672 | OPC_Decode, 225, 11, 10, // 1465: decode to J4_tstbit0_f_jumpnv_t using decoder 10 |
| 673 | // 1465: } |
| 674 | // 1465: } // switch Inst[13:8] |
| 675 | // 1465: } |
| 676 | 24, 31, // 1469: case 0x18: { |
| 677 | OPC_SwitchField, 8, 6, // 1471: switch Inst[13:8] { |
| 678 | 0, 12, // 1474: case 0x0: { |
| 679 | OPC_CheckField, 19, 1, 0, // 1476: check Inst[19] == 0x0 |
| 680 | OPC_CheckField, 0, 1, 0, // 1480: check Inst[0] == 0x0 |
| 681 | OPC_Decode, 147, 11, 11, // 1484: decode to J4_cmpeqn1_t_jumpnv_nt using decoder 11 |
| 682 | // 1484: } |
| 683 | 32, 0, // 1488: case 0x20: { |
| 684 | OPC_CheckField, 19, 1, 0, // 1490: check Inst[19] == 0x0 |
| 685 | OPC_CheckField, 0, 1, 0, // 1494: check Inst[0] == 0x0 |
| 686 | OPC_Decode, 148, 11, 11, // 1498: decode to J4_cmpeqn1_t_jumpnv_t using decoder 11 |
| 687 | // 1498: } |
| 688 | // 1498: } // switch Inst[13:8] |
| 689 | // 1498: } |
| 690 | 25, 31, // 1502: case 0x19: { |
| 691 | OPC_SwitchField, 8, 6, // 1504: switch Inst[13:8] { |
| 692 | 0, 12, // 1507: case 0x0: { |
| 693 | OPC_CheckField, 19, 1, 0, // 1509: check Inst[19] == 0x0 |
| 694 | OPC_CheckField, 0, 1, 0, // 1513: check Inst[0] == 0x0 |
| 695 | OPC_Decode, 141, 11, 11, // 1517: decode to J4_cmpeqn1_f_jumpnv_nt using decoder 11 |
| 696 | // 1517: } |
| 697 | 32, 0, // 1521: case 0x20: { |
| 698 | OPC_CheckField, 19, 1, 0, // 1523: check Inst[19] == 0x0 |
| 699 | OPC_CheckField, 0, 1, 0, // 1527: check Inst[0] == 0x0 |
| 700 | OPC_Decode, 142, 11, 11, // 1531: decode to J4_cmpeqn1_f_jumpnv_t using decoder 11 |
| 701 | // 1531: } |
| 702 | // 1531: } // switch Inst[13:8] |
| 703 | // 1531: } |
| 704 | 26, 31, // 1535: case 0x1a: { |
| 705 | OPC_SwitchField, 8, 6, // 1537: switch Inst[13:8] { |
| 706 | 0, 12, // 1540: case 0x0: { |
| 707 | OPC_CheckField, 19, 1, 0, // 1542: check Inst[19] == 0x0 |
| 708 | OPC_CheckField, 0, 1, 0, // 1546: check Inst[0] == 0x0 |
| 709 | OPC_Decode, 183, 11, 11, // 1550: decode to J4_cmpgtn1_t_jumpnv_nt using decoder 11 |
| 710 | // 1550: } |
| 711 | 32, 0, // 1554: case 0x20: { |
| 712 | OPC_CheckField, 19, 1, 0, // 1556: check Inst[19] == 0x0 |
| 713 | OPC_CheckField, 0, 1, 0, // 1560: check Inst[0] == 0x0 |
| 714 | OPC_Decode, 184, 11, 11, // 1564: decode to J4_cmpgtn1_t_jumpnv_t using decoder 11 |
| 715 | // 1564: } |
| 716 | // 1564: } // switch Inst[13:8] |
| 717 | // 1564: } |
| 718 | 27, 0, // 1568: case 0x1b: { |
| 719 | OPC_SwitchField, 8, 6, // 1570: switch Inst[13:8] { |
| 720 | 0, 12, // 1573: case 0x0: { |
| 721 | OPC_CheckField, 19, 1, 0, // 1575: check Inst[19] == 0x0 |
| 722 | OPC_CheckField, 0, 1, 0, // 1579: check Inst[0] == 0x0 |
| 723 | OPC_Decode, 177, 11, 11, // 1583: decode to J4_cmpgtn1_f_jumpnv_nt using decoder 11 |
| 724 | // 1583: } |
| 725 | 32, 0, // 1587: case 0x20: { |
| 726 | OPC_CheckField, 19, 1, 0, // 1589: check Inst[19] == 0x0 |
| 727 | OPC_CheckField, 0, 1, 0, // 1593: check Inst[0] == 0x0 |
| 728 | OPC_Decode, 178, 11, 11, // 1597: decode to J4_cmpgtn1_f_jumpnv_t using decoder 11 |
| 729 | // 1597: } |
| 730 | // 1597: } // switch Inst[13:8] |
| 731 | // 1597: } |
| 732 | // 1597: } // switch Inst[27:22] |
| 733 | // 1597: } |
| 734 | 3, 212, 6, // 1601: case 0x3: { |
| 735 | OPC_SwitchField, 21, 7, // 1604: switch Inst[27:21] { |
| 736 | 0, 4, // 1607: case 0x0: { |
| 737 | OPC_Decode, 168, 13, 12, // 1609: decode to L4_ploadrbt_rr using decoder 12 |
| 738 | // 1609: } |
| 739 | 1, 4, // 1613: case 0x1: { |
| 740 | OPC_Decode, 200, 13, 12, // 1615: decode to L4_ploadrubt_rr using decoder 12 |
| 741 | // 1615: } |
| 742 | 2, 4, // 1619: case 0x2: { |
| 743 | OPC_Decode, 184, 13, 12, // 1621: decode to L4_ploadrht_rr using decoder 12 |
| 744 | // 1621: } |
| 745 | 3, 4, // 1625: case 0x3: { |
| 746 | OPC_Decode, 208, 13, 12, // 1627: decode to L4_ploadruht_rr using decoder 12 |
| 747 | // 1627: } |
| 748 | 4, 4, // 1631: case 0x4: { |
| 749 | OPC_Decode, 192, 13, 12, // 1633: decode to L4_ploadrit_rr using decoder 12 |
| 750 | // 1633: } |
| 751 | 6, 4, // 1637: case 0x6: { |
| 752 | OPC_Decode, 176, 13, 13, // 1639: decode to L4_ploadrdt_rr using decoder 13 |
| 753 | // 1639: } |
| 754 | 8, 4, // 1643: case 0x8: { |
| 755 | OPC_Decode, 164, 13, 12, // 1645: decode to L4_ploadrbf_rr using decoder 12 |
| 756 | // 1645: } |
| 757 | 9, 4, // 1649: case 0x9: { |
| 758 | OPC_Decode, 196, 13, 12, // 1651: decode to L4_ploadrubf_rr using decoder 12 |
| 759 | // 1651: } |
| 760 | 10, 4, // 1655: case 0xa: { |
| 761 | OPC_Decode, 180, 13, 12, // 1657: decode to L4_ploadrhf_rr using decoder 12 |
| 762 | // 1657: } |
| 763 | 11, 4, // 1661: case 0xb: { |
| 764 | OPC_Decode, 204, 13, 12, // 1663: decode to L4_ploadruhf_rr using decoder 12 |
| 765 | // 1663: } |
| 766 | 12, 4, // 1667: case 0xc: { |
| 767 | OPC_Decode, 188, 13, 12, // 1669: decode to L4_ploadrif_rr using decoder 12 |
| 768 | // 1669: } |
| 769 | 14, 4, // 1673: case 0xe: { |
| 770 | OPC_Decode, 172, 13, 13, // 1675: decode to L4_ploadrdf_rr using decoder 13 |
| 771 | // 1675: } |
| 772 | 16, 4, // 1679: case 0x10: { |
| 773 | OPC_Decode, 170, 13, 12, // 1681: decode to L4_ploadrbtnew_rr using decoder 12 |
| 774 | // 1681: } |
| 775 | 17, 4, // 1685: case 0x11: { |
| 776 | OPC_Decode, 202, 13, 12, // 1687: decode to L4_ploadrubtnew_rr using decoder 12 |
| 777 | // 1687: } |
| 778 | 18, 4, // 1691: case 0x12: { |
| 779 | OPC_Decode, 186, 13, 12, // 1693: decode to L4_ploadrhtnew_rr using decoder 12 |
| 780 | // 1693: } |
| 781 | 19, 4, // 1697: case 0x13: { |
| 782 | OPC_Decode, 210, 13, 12, // 1699: decode to L4_ploadruhtnew_rr using decoder 12 |
| 783 | // 1699: } |
| 784 | 20, 4, // 1703: case 0x14: { |
| 785 | OPC_Decode, 194, 13, 12, // 1705: decode to L4_ploadritnew_rr using decoder 12 |
| 786 | // 1705: } |
| 787 | 22, 4, // 1709: case 0x16: { |
| 788 | OPC_Decode, 178, 13, 13, // 1711: decode to L4_ploadrdtnew_rr using decoder 13 |
| 789 | // 1711: } |
| 790 | 24, 4, // 1715: case 0x18: { |
| 791 | OPC_Decode, 166, 13, 12, // 1717: decode to L4_ploadrbfnew_rr using decoder 12 |
| 792 | // 1717: } |
| 793 | 25, 4, // 1721: case 0x19: { |
| 794 | OPC_Decode, 198, 13, 12, // 1723: decode to L4_ploadrubfnew_rr using decoder 12 |
| 795 | // 1723: } |
| 796 | 26, 4, // 1727: case 0x1a: { |
| 797 | OPC_Decode, 182, 13, 12, // 1729: decode to L4_ploadrhfnew_rr using decoder 12 |
| 798 | // 1729: } |
| 799 | 27, 4, // 1733: case 0x1b: { |
| 800 | OPC_Decode, 206, 13, 12, // 1735: decode to L4_ploadruhfnew_rr using decoder 12 |
| 801 | // 1735: } |
| 802 | 28, 4, // 1739: case 0x1c: { |
| 803 | OPC_Decode, 190, 13, 12, // 1741: decode to L4_ploadrifnew_rr using decoder 12 |
| 804 | // 1741: } |
| 805 | 30, 4, // 1745: case 0x1e: { |
| 806 | OPC_Decode, 174, 13, 13, // 1747: decode to L4_ploadrdfnew_rr using decoder 13 |
| 807 | // 1747: } |
| 808 | 32, 4, // 1751: case 0x20: { |
| 809 | OPC_Decode, 143, 19, 14, // 1753: decode to S4_pstorerbt_rr using decoder 14 |
| 810 | // 1753: } |
| 811 | 34, 4, // 1757: case 0x22: { |
| 812 | OPC_Decode, 183, 19, 14, // 1759: decode to S4_pstorerht_rr using decoder 14 |
| 813 | // 1759: } |
| 814 | 35, 4, // 1763: case 0x23: { |
| 815 | OPC_Decode, 163, 19, 14, // 1765: decode to S4_pstorerft_rr using decoder 14 |
| 816 | // 1765: } |
| 817 | 36, 4, // 1769: case 0x24: { |
| 818 | OPC_Decode, 203, 19, 14, // 1771: decode to S4_pstorerit_rr using decoder 14 |
| 819 | // 1771: } |
| 820 | 37, 21, // 1775: case 0x25: { |
| 821 | OPC_SwitchField, 3, 2, // 1777: switch Inst[4:3] { |
| 822 | 0, 4, // 1780: case 0x0: { |
| 823 | OPC_Decode, 138, 19, 15, // 1782: decode to S4_pstorerbnewt_rr using decoder 15 |
| 824 | // 1782: } |
| 825 | 1, 4, // 1786: case 0x1: { |
| 826 | OPC_Decode, 178, 19, 15, // 1788: decode to S4_pstorerhnewt_rr using decoder 15 |
| 827 | // 1788: } |
| 828 | 2, 0, // 1792: case 0x2: { |
| 829 | OPC_Decode, 198, 19, 15, // 1794: decode to S4_pstorerinewt_rr using decoder 15 |
| 830 | // 1794: } |
| 831 | // 1794: } // switch Inst[4:3] |
| 832 | // 1794: } |
| 833 | 38, 4, // 1798: case 0x26: { |
| 834 | OPC_Decode, 153, 19, 16, // 1800: decode to S4_pstorerdt_rr using decoder 16 |
| 835 | // 1800: } |
| 836 | 40, 4, // 1804: case 0x28: { |
| 837 | OPC_Decode, 128, 19, 14, // 1806: decode to S4_pstorerbf_rr using decoder 14 |
| 838 | // 1806: } |
| 839 | 42, 4, // 1810: case 0x2a: { |
| 840 | OPC_Decode, 168, 19, 14, // 1812: decode to S4_pstorerhf_rr using decoder 14 |
| 841 | // 1812: } |
| 842 | 43, 4, // 1816: case 0x2b: { |
| 843 | OPC_Decode, 158, 19, 14, // 1818: decode to S4_pstorerff_rr using decoder 14 |
| 844 | // 1818: } |
| 845 | 44, 4, // 1822: case 0x2c: { |
| 846 | OPC_Decode, 188, 19, 14, // 1824: decode to S4_pstorerif_rr using decoder 14 |
| 847 | // 1824: } |
| 848 | 45, 21, // 1828: case 0x2d: { |
| 849 | OPC_SwitchField, 3, 2, // 1830: switch Inst[4:3] { |
| 850 | 0, 4, // 1833: case 0x0: { |
| 851 | OPC_Decode, 133, 19, 15, // 1835: decode to S4_pstorerbnewf_rr using decoder 15 |
| 852 | // 1835: } |
| 853 | 1, 4, // 1839: case 0x1: { |
| 854 | OPC_Decode, 173, 19, 15, // 1841: decode to S4_pstorerhnewf_rr using decoder 15 |
| 855 | // 1841: } |
| 856 | 2, 0, // 1845: case 0x2: { |
| 857 | OPC_Decode, 193, 19, 15, // 1847: decode to S4_pstorerinewf_rr using decoder 15 |
| 858 | // 1847: } |
| 859 | // 1847: } // switch Inst[4:3] |
| 860 | // 1847: } |
| 861 | 46, 4, // 1851: case 0x2e: { |
| 862 | OPC_Decode, 148, 19, 16, // 1853: decode to S4_pstorerdf_rr using decoder 16 |
| 863 | // 1853: } |
| 864 | 48, 4, // 1857: case 0x30: { |
| 865 | OPC_Decode, 146, 19, 14, // 1859: decode to S4_pstorerbtnew_rr using decoder 14 |
| 866 | // 1859: } |
| 867 | 50, 4, // 1863: case 0x32: { |
| 868 | OPC_Decode, 186, 19, 14, // 1865: decode to S4_pstorerhtnew_rr using decoder 14 |
| 869 | // 1865: } |
| 870 | 51, 4, // 1869: case 0x33: { |
| 871 | OPC_Decode, 166, 19, 14, // 1871: decode to S4_pstorerftnew_rr using decoder 14 |
| 872 | // 1871: } |
| 873 | 52, 4, // 1875: case 0x34: { |
| 874 | OPC_Decode, 206, 19, 14, // 1877: decode to S4_pstoreritnew_rr using decoder 14 |
| 875 | // 1877: } |
| 876 | 53, 21, // 1881: case 0x35: { |
| 877 | OPC_SwitchField, 3, 2, // 1883: switch Inst[4:3] { |
| 878 | 0, 4, // 1886: case 0x0: { |
| 879 | OPC_Decode, 141, 19, 15, // 1888: decode to S4_pstorerbnewtnew_rr using decoder 15 |
| 880 | // 1888: } |
| 881 | 1, 4, // 1892: case 0x1: { |
| 882 | OPC_Decode, 181, 19, 15, // 1894: decode to S4_pstorerhnewtnew_rr using decoder 15 |
| 883 | // 1894: } |
| 884 | 2, 0, // 1898: case 0x2: { |
| 885 | OPC_Decode, 201, 19, 15, // 1900: decode to S4_pstorerinewtnew_rr using decoder 15 |
| 886 | // 1900: } |
| 887 | // 1900: } // switch Inst[4:3] |
| 888 | // 1900: } |
| 889 | 54, 4, // 1904: case 0x36: { |
| 890 | OPC_Decode, 156, 19, 16, // 1906: decode to S4_pstorerdtnew_rr using decoder 16 |
| 891 | // 1906: } |
| 892 | 56, 4, // 1910: case 0x38: { |
| 893 | OPC_Decode, 131, 19, 14, // 1912: decode to S4_pstorerbfnew_rr using decoder 14 |
| 894 | // 1912: } |
| 895 | 58, 4, // 1916: case 0x3a: { |
| 896 | OPC_Decode, 171, 19, 14, // 1918: decode to S4_pstorerhfnew_rr using decoder 14 |
| 897 | // 1918: } |
| 898 | 59, 4, // 1922: case 0x3b: { |
| 899 | OPC_Decode, 161, 19, 14, // 1924: decode to S4_pstorerffnew_rr using decoder 14 |
| 900 | // 1924: } |
| 901 | 60, 4, // 1928: case 0x3c: { |
| 902 | OPC_Decode, 191, 19, 14, // 1930: decode to S4_pstorerifnew_rr using decoder 14 |
| 903 | // 1930: } |
| 904 | 61, 21, // 1934: case 0x3d: { |
| 905 | OPC_SwitchField, 3, 2, // 1936: switch Inst[4:3] { |
| 906 | 0, 4, // 1939: case 0x0: { |
| 907 | OPC_Decode, 136, 19, 15, // 1941: decode to S4_pstorerbnewfnew_rr using decoder 15 |
| 908 | // 1941: } |
| 909 | 1, 4, // 1945: case 0x1: { |
| 910 | OPC_Decode, 176, 19, 15, // 1947: decode to S4_pstorerhnewfnew_rr using decoder 15 |
| 911 | // 1947: } |
| 912 | 2, 0, // 1951: case 0x2: { |
| 913 | OPC_Decode, 196, 19, 15, // 1953: decode to S4_pstorerinewfnew_rr using decoder 15 |
| 914 | // 1953: } |
| 915 | // 1953: } // switch Inst[4:3] |
| 916 | // 1953: } |
| 917 | 62, 4, // 1957: case 0x3e: { |
| 918 | OPC_Decode, 151, 19, 16, // 1959: decode to S4_pstorerdfnew_rr using decoder 16 |
| 919 | // 1959: } |
| 920 | 64, 4, // 1963: case 0x40: { |
| 921 | OPC_Decode, 213, 19, 17, // 1965: decode to S4_storeirbt_io using decoder 17 |
| 922 | // 1965: } |
| 923 | 65, 4, // 1969: case 0x41: { |
| 924 | OPC_Decode, 218, 19, 18, // 1971: decode to S4_storeirht_io using decoder 18 |
| 925 | // 1971: } |
| 926 | 66, 4, // 1975: case 0x42: { |
| 927 | OPC_Decode, 223, 19, 19, // 1977: decode to S4_storeirit_io using decoder 19 |
| 928 | // 1977: } |
| 929 | 68, 4, // 1981: case 0x44: { |
| 930 | OPC_Decode, 211, 19, 17, // 1983: decode to S4_storeirbf_io using decoder 17 |
| 931 | // 1983: } |
| 932 | 69, 4, // 1987: case 0x45: { |
| 933 | OPC_Decode, 216, 19, 18, // 1989: decode to S4_storeirhf_io using decoder 18 |
| 934 | // 1989: } |
| 935 | 70, 4, // 1993: case 0x46: { |
| 936 | OPC_Decode, 221, 19, 19, // 1995: decode to S4_storeirif_io using decoder 19 |
| 937 | // 1995: } |
| 938 | 72, 4, // 1999: case 0x48: { |
| 939 | OPC_Decode, 214, 19, 17, // 2001: decode to S4_storeirbtnew_io using decoder 17 |
| 940 | // 2001: } |
| 941 | 73, 4, // 2005: case 0x49: { |
| 942 | OPC_Decode, 219, 19, 18, // 2007: decode to S4_storeirhtnew_io using decoder 18 |
| 943 | // 2007: } |
| 944 | 74, 4, // 2011: case 0x4a: { |
| 945 | OPC_Decode, 224, 19, 19, // 2013: decode to S4_storeiritnew_io using decoder 19 |
| 946 | // 2013: } |
| 947 | 76, 4, // 2017: case 0x4c: { |
| 948 | OPC_Decode, 212, 19, 17, // 2019: decode to S4_storeirbfnew_io using decoder 17 |
| 949 | // 2019: } |
| 950 | 77, 4, // 2023: case 0x4d: { |
| 951 | OPC_Decode, 217, 19, 18, // 2025: decode to S4_storeirhfnew_io using decoder 18 |
| 952 | // 2025: } |
| 953 | 78, 4, // 2029: case 0x4e: { |
| 954 | OPC_Decode, 222, 19, 19, // 2031: decode to S4_storeirifnew_io using decoder 19 |
| 955 | // 2031: } |
| 956 | 80, 8, // 2035: case 0x50: { |
| 957 | OPC_CheckField, 5, 2, 0, // 2037: check Inst[6:5] == 0x0 |
| 958 | OPC_Decode, 142, 13, 20, // 2041: decode to L4_loadrb_rr using decoder 20 |
| 959 | // 2041: } |
| 960 | 81, 8, // 2045: case 0x51: { |
| 961 | OPC_CheckField, 5, 2, 0, // 2047: check Inst[6:5] == 0x0 |
| 962 | OPC_Decode, 154, 13, 20, // 2051: decode to L4_loadrub_rr using decoder 20 |
| 963 | // 2051: } |
| 964 | 82, 8, // 2055: case 0x52: { |
| 965 | OPC_CheckField, 5, 2, 0, // 2057: check Inst[6:5] == 0x0 |
| 966 | OPC_Decode, 148, 13, 20, // 2061: decode to L4_loadrh_rr using decoder 20 |
| 967 | // 2061: } |
| 968 | 83, 8, // 2065: case 0x53: { |
| 969 | OPC_CheckField, 5, 2, 0, // 2067: check Inst[6:5] == 0x0 |
| 970 | OPC_Decode, 157, 13, 20, // 2071: decode to L4_loadruh_rr using decoder 20 |
| 971 | // 2071: } |
| 972 | 84, 8, // 2075: case 0x54: { |
| 973 | OPC_CheckField, 5, 2, 0, // 2077: check Inst[6:5] == 0x0 |
| 974 | OPC_Decode, 151, 13, 20, // 2081: decode to L4_loadri_rr using decoder 20 |
| 975 | // 2081: } |
| 976 | 86, 8, // 2085: case 0x56: { |
| 977 | OPC_CheckField, 5, 2, 0, // 2087: check Inst[6:5] == 0x0 |
| 978 | OPC_Decode, 145, 13, 21, // 2091: decode to L4_loadrd_rr using decoder 21 |
| 979 | // 2091: } |
| 980 | 88, 8, // 2095: case 0x58: { |
| 981 | OPC_CheckField, 5, 2, 0, // 2097: check Inst[6:5] == 0x0 |
| 982 | OPC_Decode, 226, 19, 22, // 2101: decode to S4_storerb_rr using decoder 22 |
| 983 | // 2101: } |
| 984 | 90, 8, // 2105: case 0x5a: { |
| 985 | OPC_CheckField, 5, 2, 0, // 2107: check Inst[6:5] == 0x0 |
| 986 | OPC_Decode, 238, 19, 22, // 2111: decode to S4_storerh_rr using decoder 22 |
| 987 | // 2111: } |
| 988 | 91, 8, // 2115: case 0x5b: { |
| 989 | OPC_CheckField, 5, 2, 0, // 2117: check Inst[6:5] == 0x0 |
| 990 | OPC_Decode, 235, 19, 22, // 2121: decode to S4_storerf_rr using decoder 22 |
| 991 | // 2121: } |
| 992 | 92, 8, // 2125: case 0x5c: { |
| 993 | OPC_CheckField, 5, 2, 0, // 2127: check Inst[6:5] == 0x0 |
| 994 | OPC_Decode, 244, 19, 22, // 2131: decode to S4_storeri_rr using decoder 22 |
| 995 | // 2131: } |
| 996 | 93, 21, // 2135: case 0x5d: { |
| 997 | OPC_SwitchField, 3, 4, // 2137: switch Inst[6:3] { |
| 998 | 0, 4, // 2140: case 0x0: { |
| 999 | OPC_Decode, 229, 19, 23, // 2142: decode to S4_storerbnew_rr using decoder 23 |
| 1000 | // 2142: } |
| 1001 | 1, 4, // 2146: case 0x1: { |
| 1002 | OPC_Decode, 241, 19, 23, // 2148: decode to S4_storerhnew_rr using decoder 23 |
| 1003 | // 2148: } |
| 1004 | 2, 0, // 2152: case 0x2: { |
| 1005 | OPC_Decode, 247, 19, 23, // 2154: decode to S4_storerinew_rr using decoder 23 |
| 1006 | // 2154: } |
| 1007 | // 2154: } // switch Inst[6:3] |
| 1008 | // 2154: } |
| 1009 | 94, 8, // 2158: case 0x5e: { |
| 1010 | OPC_CheckField, 5, 2, 0, // 2160: check Inst[6:5] == 0x0 |
| 1011 | OPC_Decode, 232, 19, 24, // 2164: decode to S4_storerd_rr using decoder 24 |
| 1012 | // 2164: } |
| 1013 | 96, 4, // 2168: case 0x60: { |
| 1014 | OPC_Decode, 210, 19, 25, // 2170: decode to S4_storeirb_io using decoder 25 |
| 1015 | // 2170: } |
| 1016 | 97, 4, // 2174: case 0x61: { |
| 1017 | OPC_Decode, 215, 19, 26, // 2176: decode to S4_storeirh_io using decoder 26 |
| 1018 | // 2176: } |
| 1019 | 98, 4, // 2180: case 0x62: { |
| 1020 | OPC_Decode, 220, 19, 27, // 2182: decode to S4_storeiri_io using decoder 27 |
| 1021 | // 2182: } |
| 1022 | 112, 43, // 2186: case 0x70: { |
| 1023 | OPC_SwitchField, 5, 2, // 2188: switch Inst[6:5] { |
| 1024 | 0, 8, // 2191: case 0x0: { |
| 1025 | OPC_CheckField, 13, 1, 0, // 2193: check Inst[13] == 0x0 |
| 1026 | OPC_Decode, 237, 12, 28, // 2197: decode to L4_add_memopb_io using decoder 28 |
| 1027 | // 2197: } |
| 1028 | 1, 8, // 2201: case 0x1: { |
| 1029 | OPC_CheckField, 13, 1, 0, // 2203: check Inst[13] == 0x0 |
| 1030 | OPC_Decode, 218, 13, 28, // 2207: decode to L4_sub_memopb_io using decoder 28 |
| 1031 | // 2207: } |
| 1032 | 2, 8, // 2211: case 0x2: { |
| 1033 | OPC_CheckField, 13, 1, 0, // 2213: check Inst[13] == 0x0 |
| 1034 | OPC_Decode, 240, 12, 28, // 2217: decode to L4_and_memopb_io using decoder 28 |
| 1035 | // 2217: } |
| 1036 | 3, 0, // 2221: case 0x3: { |
| 1037 | OPC_CheckField, 13, 1, 0, // 2223: check Inst[13] == 0x0 |
| 1038 | OPC_Decode, 160, 13, 28, // 2227: decode to L4_or_memopb_io using decoder 28 |
| 1039 | // 2227: } |
| 1040 | // 2227: } // switch Inst[6:5] |
| 1041 | // 2227: } |
| 1042 | 113, 43, // 2231: case 0x71: { |
| 1043 | OPC_SwitchField, 5, 2, // 2233: switch Inst[6:5] { |
| 1044 | 0, 8, // 2236: case 0x0: { |
| 1045 | OPC_CheckField, 13, 1, 0, // 2238: check Inst[13] == 0x0 |
| 1046 | OPC_Decode, 238, 12, 29, // 2242: decode to L4_add_memoph_io using decoder 29 |
| 1047 | // 2242: } |
| 1048 | 1, 8, // 2246: case 0x1: { |
| 1049 | OPC_CheckField, 13, 1, 0, // 2248: check Inst[13] == 0x0 |
| 1050 | OPC_Decode, 219, 13, 29, // 2252: decode to L4_sub_memoph_io using decoder 29 |
| 1051 | // 2252: } |
| 1052 | 2, 8, // 2256: case 0x2: { |
| 1053 | OPC_CheckField, 13, 1, 0, // 2258: check Inst[13] == 0x0 |
| 1054 | OPC_Decode, 241, 12, 29, // 2262: decode to L4_and_memoph_io using decoder 29 |
| 1055 | // 2262: } |
| 1056 | 3, 0, // 2266: case 0x3: { |
| 1057 | OPC_CheckField, 13, 1, 0, // 2268: check Inst[13] == 0x0 |
| 1058 | OPC_Decode, 161, 13, 29, // 2272: decode to L4_or_memoph_io using decoder 29 |
| 1059 | // 2272: } |
| 1060 | // 2272: } // switch Inst[6:5] |
| 1061 | // 2272: } |
| 1062 | 114, 43, // 2276: case 0x72: { |
| 1063 | OPC_SwitchField, 5, 2, // 2278: switch Inst[6:5] { |
| 1064 | 0, 8, // 2281: case 0x0: { |
| 1065 | OPC_CheckField, 13, 1, 0, // 2283: check Inst[13] == 0x0 |
| 1066 | OPC_Decode, 239, 12, 30, // 2287: decode to L4_add_memopw_io using decoder 30 |
| 1067 | // 2287: } |
| 1068 | 1, 8, // 2291: case 0x1: { |
| 1069 | OPC_CheckField, 13, 1, 0, // 2293: check Inst[13] == 0x0 |
| 1070 | OPC_Decode, 220, 13, 30, // 2297: decode to L4_sub_memopw_io using decoder 30 |
| 1071 | // 2297: } |
| 1072 | 2, 8, // 2301: case 0x2: { |
| 1073 | OPC_CheckField, 13, 1, 0, // 2303: check Inst[13] == 0x0 |
| 1074 | OPC_Decode, 242, 12, 30, // 2307: decode to L4_and_memopw_io using decoder 30 |
| 1075 | // 2307: } |
| 1076 | 3, 0, // 2311: case 0x3: { |
| 1077 | OPC_CheckField, 13, 1, 0, // 2313: check Inst[13] == 0x0 |
| 1078 | OPC_Decode, 162, 13, 30, // 2317: decode to L4_or_memopw_io using decoder 30 |
| 1079 | // 2317: } |
| 1080 | // 2317: } // switch Inst[6:5] |
| 1081 | // 2317: } |
| 1082 | 120, 43, // 2321: case 0x78: { |
| 1083 | OPC_SwitchField, 5, 2, // 2323: switch Inst[6:5] { |
| 1084 | 0, 8, // 2326: case 0x0: { |
| 1085 | OPC_CheckField, 13, 1, 0, // 2328: check Inst[13] == 0x0 |
| 1086 | OPC_Decode, 243, 12, 31, // 2332: decode to L4_iadd_memopb_io using decoder 31 |
| 1087 | // 2332: } |
| 1088 | 1, 8, // 2336: case 0x1: { |
| 1089 | OPC_CheckField, 13, 1, 0, // 2338: check Inst[13] == 0x0 |
| 1090 | OPC_Decode, 252, 12, 31, // 2342: decode to L4_isub_memopb_io using decoder 31 |
| 1091 | // 2342: } |
| 1092 | 2, 8, // 2346: case 0x2: { |
| 1093 | OPC_CheckField, 13, 1, 0, // 2348: check Inst[13] == 0x0 |
| 1094 | OPC_Decode, 246, 12, 31, // 2352: decode to L4_iand_memopb_io using decoder 31 |
| 1095 | // 2352: } |
| 1096 | 3, 0, // 2356: case 0x3: { |
| 1097 | OPC_CheckField, 13, 1, 0, // 2358: check Inst[13] == 0x0 |
| 1098 | OPC_Decode, 249, 12, 31, // 2362: decode to L4_ior_memopb_io using decoder 31 |
| 1099 | // 2362: } |
| 1100 | // 2362: } // switch Inst[6:5] |
| 1101 | // 2362: } |
| 1102 | 121, 43, // 2366: case 0x79: { |
| 1103 | OPC_SwitchField, 5, 2, // 2368: switch Inst[6:5] { |
| 1104 | 0, 8, // 2371: case 0x0: { |
| 1105 | OPC_CheckField, 13, 1, 0, // 2373: check Inst[13] == 0x0 |
| 1106 | OPC_Decode, 244, 12, 32, // 2377: decode to L4_iadd_memoph_io using decoder 32 |
| 1107 | // 2377: } |
| 1108 | 1, 8, // 2381: case 0x1: { |
| 1109 | OPC_CheckField, 13, 1, 0, // 2383: check Inst[13] == 0x0 |
| 1110 | OPC_Decode, 253, 12, 32, // 2387: decode to L4_isub_memoph_io using decoder 32 |
| 1111 | // 2387: } |
| 1112 | 2, 8, // 2391: case 0x2: { |
| 1113 | OPC_CheckField, 13, 1, 0, // 2393: check Inst[13] == 0x0 |
| 1114 | OPC_Decode, 247, 12, 32, // 2397: decode to L4_iand_memoph_io using decoder 32 |
| 1115 | // 2397: } |
| 1116 | 3, 0, // 2401: case 0x3: { |
| 1117 | OPC_CheckField, 13, 1, 0, // 2403: check Inst[13] == 0x0 |
| 1118 | OPC_Decode, 250, 12, 32, // 2407: decode to L4_ior_memoph_io using decoder 32 |
| 1119 | // 2407: } |
| 1120 | // 2407: } // switch Inst[6:5] |
| 1121 | // 2407: } |
| 1122 | 122, 0, // 2411: case 0x7a: { |
| 1123 | OPC_SwitchField, 5, 2, // 2413: switch Inst[6:5] { |
| 1124 | 0, 8, // 2416: case 0x0: { |
| 1125 | OPC_CheckField, 13, 1, 0, // 2418: check Inst[13] == 0x0 |
| 1126 | OPC_Decode, 245, 12, 33, // 2422: decode to L4_iadd_memopw_io using decoder 33 |
| 1127 | // 2422: } |
| 1128 | 1, 8, // 2426: case 0x1: { |
| 1129 | OPC_CheckField, 13, 1, 0, // 2428: check Inst[13] == 0x0 |
| 1130 | OPC_Decode, 254, 12, 33, // 2432: decode to L4_isub_memopw_io using decoder 33 |
| 1131 | // 2432: } |
| 1132 | 2, 8, // 2436: case 0x2: { |
| 1133 | OPC_CheckField, 13, 1, 0, // 2438: check Inst[13] == 0x0 |
| 1134 | OPC_Decode, 248, 12, 33, // 2442: decode to L4_iand_memopw_io using decoder 33 |
| 1135 | // 2442: } |
| 1136 | 3, 0, // 2446: case 0x3: { |
| 1137 | OPC_CheckField, 13, 1, 0, // 2448: check Inst[13] == 0x0 |
| 1138 | OPC_Decode, 251, 12, 33, // 2452: decode to L4_ior_memopw_io using decoder 33 |
| 1139 | // 2452: } |
| 1140 | // 2452: } // switch Inst[6:5] |
| 1141 | // 2452: } |
| 1142 | // 2452: } // switch Inst[27:21] |
| 1143 | // 2452: } |
| 1144 | 4, 153, 6, // 2456: case 0x4: { |
| 1145 | OPC_SwitchField, 21, 4, // 2459: switch Inst[24:21] { |
| 1146 | 0, 54, // 2462: case 0x0: { |
| 1147 | OPC_SwitchField, 27, 1, // 2464: switch Inst[27] { |
| 1148 | 0, 43, // 2467: case 0x0: { |
| 1149 | OPC_SwitchField, 25, 2, // 2469: switch Inst[26:25] { |
| 1150 | 0, 8, // 2472: case 0x0: { |
| 1151 | OPC_CheckField, 2, 1, 0, // 2474: check Inst[2] == 0x0 |
| 1152 | OPC_Decode, 221, 17, 34, // 2478: decode to S2_pstorerbt_io using decoder 34 |
| 1153 | // 2478: } |
| 1154 | 1, 8, // 2482: case 0x1: { |
| 1155 | OPC_CheckField, 2, 1, 0, // 2484: check Inst[2] == 0x0 |
| 1156 | OPC_Decode, 145, 19, 34, // 2488: decode to S4_pstorerbtnew_io using decoder 34 |
| 1157 | // 2488: } |
| 1158 | 2, 8, // 2492: case 0x2: { |
| 1159 | OPC_CheckField, 2, 1, 0, // 2494: check Inst[2] == 0x0 |
| 1160 | OPC_Decode, 212, 17, 34, // 2498: decode to S2_pstorerbf_io using decoder 34 |
| 1161 | // 2498: } |
| 1162 | 3, 0, // 2502: case 0x3: { |
| 1163 | OPC_CheckField, 2, 1, 0, // 2504: check Inst[2] == 0x0 |
| 1164 | OPC_Decode, 130, 19, 34, // 2508: decode to S4_pstorerbfnew_io using decoder 34 |
| 1165 | // 2508: } |
| 1166 | // 2508: } // switch Inst[26:25] |
| 1167 | // 2508: } |
| 1168 | 1, 0, // 2512: case 0x1: { |
| 1169 | OPC_Decode, 144, 18, 35, // 2514: decode to S2_storerbgp using decoder 35 |
| 1170 | // 2514: } |
| 1171 | // 2514: } // switch Inst[27] |
| 1172 | // 2514: } |
| 1173 | 2, 54, // 2518: case 0x2: { |
| 1174 | OPC_SwitchField, 27, 1, // 2520: switch Inst[27] { |
| 1175 | 0, 43, // 2523: case 0x0: { |
| 1176 | OPC_SwitchField, 25, 2, // 2525: switch Inst[26:25] { |
| 1177 | 0, 8, // 2528: case 0x0: { |
| 1178 | OPC_CheckField, 2, 1, 0, // 2530: check Inst[2] == 0x0 |
| 1179 | OPC_Decode, 245, 17, 36, // 2534: decode to S2_pstorerht_io using decoder 36 |
| 1180 | // 2534: } |
| 1181 | 1, 8, // 2538: case 0x1: { |
| 1182 | OPC_CheckField, 2, 1, 0, // 2540: check Inst[2] == 0x0 |
| 1183 | OPC_Decode, 185, 19, 36, // 2544: decode to S4_pstorerhtnew_io using decoder 36 |
| 1184 | // 2544: } |
| 1185 | 2, 8, // 2548: case 0x2: { |
| 1186 | OPC_CheckField, 2, 1, 0, // 2550: check Inst[2] == 0x0 |
| 1187 | OPC_Decode, 236, 17, 36, // 2554: decode to S2_pstorerhf_io using decoder 36 |
| 1188 | // 2554: } |
| 1189 | 3, 0, // 2558: case 0x3: { |
| 1190 | OPC_CheckField, 2, 1, 0, // 2560: check Inst[2] == 0x0 |
| 1191 | OPC_Decode, 170, 19, 36, // 2564: decode to S4_pstorerhfnew_io using decoder 36 |
| 1192 | // 2564: } |
| 1193 | // 2564: } // switch Inst[26:25] |
| 1194 | // 2564: } |
| 1195 | 1, 0, // 2568: case 0x1: { |
| 1196 | OPC_Decode, 172, 18, 37, // 2570: decode to S2_storerhgp using decoder 37 |
| 1197 | // 2570: } |
| 1198 | // 2570: } // switch Inst[27] |
| 1199 | // 2570: } |
| 1200 | 3, 54, // 2574: case 0x3: { |
| 1201 | OPC_SwitchField, 27, 1, // 2576: switch Inst[27] { |
| 1202 | 0, 43, // 2579: case 0x0: { |
| 1203 | OPC_SwitchField, 25, 2, // 2581: switch Inst[26:25] { |
| 1204 | 0, 8, // 2584: case 0x0: { |
| 1205 | OPC_CheckField, 2, 1, 0, // 2586: check Inst[2] == 0x0 |
| 1206 | OPC_Decode, 233, 17, 36, // 2590: decode to S2_pstorerft_io using decoder 36 |
| 1207 | // 2590: } |
| 1208 | 1, 8, // 2594: case 0x1: { |
| 1209 | OPC_CheckField, 2, 1, 0, // 2596: check Inst[2] == 0x0 |
| 1210 | OPC_Decode, 165, 19, 36, // 2600: decode to S4_pstorerftnew_io using decoder 36 |
| 1211 | // 2600: } |
| 1212 | 2, 8, // 2604: case 0x2: { |
| 1213 | OPC_CheckField, 2, 1, 0, // 2606: check Inst[2] == 0x0 |
| 1214 | OPC_Decode, 230, 17, 36, // 2610: decode to S2_pstorerff_io using decoder 36 |
| 1215 | // 2610: } |
| 1216 | 3, 0, // 2614: case 0x3: { |
| 1217 | OPC_CheckField, 2, 1, 0, // 2616: check Inst[2] == 0x0 |
| 1218 | OPC_Decode, 160, 19, 36, // 2620: decode to S4_pstorerffnew_io using decoder 36 |
| 1219 | // 2620: } |
| 1220 | // 2620: } // switch Inst[26:25] |
| 1221 | // 2620: } |
| 1222 | 1, 0, // 2624: case 0x1: { |
| 1223 | OPC_Decode, 165, 18, 37, // 2626: decode to S2_storerfgp using decoder 37 |
| 1224 | // 2626: } |
| 1225 | // 2626: } // switch Inst[27] |
| 1226 | // 2626: } |
| 1227 | 4, 54, // 2630: case 0x4: { |
| 1228 | OPC_SwitchField, 27, 1, // 2632: switch Inst[27] { |
| 1229 | 0, 43, // 2635: case 0x0: { |
| 1230 | OPC_SwitchField, 25, 2, // 2637: switch Inst[26:25] { |
| 1231 | 0, 8, // 2640: case 0x0: { |
| 1232 | OPC_CheckField, 2, 1, 0, // 2642: check Inst[2] == 0x0 |
| 1233 | OPC_Decode, 129, 18, 38, // 2646: decode to S2_pstorerit_io using decoder 38 |
| 1234 | // 2646: } |
| 1235 | 1, 8, // 2650: case 0x1: { |
| 1236 | OPC_CheckField, 2, 1, 0, // 2652: check Inst[2] == 0x0 |
| 1237 | OPC_Decode, 205, 19, 38, // 2656: decode to S4_pstoreritnew_io using decoder 38 |
| 1238 | // 2656: } |
| 1239 | 2, 8, // 2660: case 0x2: { |
| 1240 | OPC_CheckField, 2, 1, 0, // 2662: check Inst[2] == 0x0 |
| 1241 | OPC_Decode, 248, 17, 38, // 2666: decode to S2_pstorerif_io using decoder 38 |
| 1242 | // 2666: } |
| 1243 | 3, 0, // 2670: case 0x3: { |
| 1244 | OPC_CheckField, 2, 1, 0, // 2672: check Inst[2] == 0x0 |
| 1245 | OPC_Decode, 190, 19, 38, // 2676: decode to S4_pstorerifnew_io using decoder 38 |
| 1246 | // 2676: } |
| 1247 | // 2676: } // switch Inst[26:25] |
| 1248 | // 2676: } |
| 1249 | 1, 0, // 2680: case 0x1: { |
| 1250 | OPC_Decode, 186, 18, 39, // 2682: decode to S2_storerigp using decoder 39 |
| 1251 | // 2682: } |
| 1252 | // 2682: } // switch Inst[27] |
| 1253 | // 2682: } |
| 1254 | 5, 171, 1, // 2686: case 0x5: { |
| 1255 | OPC_SwitchField, 11, 2, // 2689: switch Inst[12:11] { |
| 1256 | 0, 54, // 2692: case 0x0: { |
| 1257 | OPC_SwitchField, 27, 1, // 2694: switch Inst[27] { |
| 1258 | 0, 43, // 2697: case 0x0: { |
| 1259 | OPC_SwitchField, 25, 2, // 2699: switch Inst[26:25] { |
| 1260 | 0, 8, // 2702: case 0x0: { |
| 1261 | OPC_CheckField, 2, 1, 0, // 2704: check Inst[2] == 0x0 |
| 1262 | OPC_Decode, 218, 17, 40, // 2708: decode to S2_pstorerbnewt_io using decoder 40 |
| 1263 | // 2708: } |
| 1264 | 1, 8, // 2712: case 0x1: { |
| 1265 | OPC_CheckField, 2, 1, 0, // 2714: check Inst[2] == 0x0 |
| 1266 | OPC_Decode, 140, 19, 40, // 2718: decode to S4_pstorerbnewtnew_io using decoder 40 |
| 1267 | // 2718: } |
| 1268 | 2, 8, // 2722: case 0x2: { |
| 1269 | OPC_CheckField, 2, 1, 0, // 2724: check Inst[2] == 0x0 |
| 1270 | OPC_Decode, 215, 17, 40, // 2728: decode to S2_pstorerbnewf_io using decoder 40 |
| 1271 | // 2728: } |
| 1272 | 3, 0, // 2732: case 0x3: { |
| 1273 | OPC_CheckField, 2, 1, 0, // 2734: check Inst[2] == 0x0 |
| 1274 | OPC_Decode, 135, 19, 40, // 2738: decode to S4_pstorerbnewfnew_io using decoder 40 |
| 1275 | // 2738: } |
| 1276 | // 2738: } // switch Inst[26:25] |
| 1277 | // 2738: } |
| 1278 | 1, 0, // 2742: case 0x1: { |
| 1279 | OPC_Decode, 151, 18, 41, // 2744: decode to S2_storerbnewgp using decoder 41 |
| 1280 | // 2744: } |
| 1281 | // 2744: } // switch Inst[27] |
| 1282 | // 2744: } |
| 1283 | 1, 54, // 2748: case 0x1: { |
| 1284 | OPC_SwitchField, 27, 1, // 2750: switch Inst[27] { |
| 1285 | 0, 43, // 2753: case 0x0: { |
| 1286 | OPC_SwitchField, 25, 2, // 2755: switch Inst[26:25] { |
| 1287 | 0, 8, // 2758: case 0x0: { |
| 1288 | OPC_CheckField, 2, 1, 0, // 2760: check Inst[2] == 0x0 |
| 1289 | OPC_Decode, 242, 17, 42, // 2764: decode to S2_pstorerhnewt_io using decoder 42 |
| 1290 | // 2764: } |
| 1291 | 1, 8, // 2768: case 0x1: { |
| 1292 | OPC_CheckField, 2, 1, 0, // 2770: check Inst[2] == 0x0 |
| 1293 | OPC_Decode, 180, 19, 42, // 2774: decode to S4_pstorerhnewtnew_io using decoder 42 |
| 1294 | // 2774: } |
| 1295 | 2, 8, // 2778: case 0x2: { |
| 1296 | OPC_CheckField, 2, 1, 0, // 2780: check Inst[2] == 0x0 |
| 1297 | OPC_Decode, 239, 17, 42, // 2784: decode to S2_pstorerhnewf_io using decoder 42 |
| 1298 | // 2784: } |
| 1299 | 3, 0, // 2788: case 0x3: { |
| 1300 | OPC_CheckField, 2, 1, 0, // 2790: check Inst[2] == 0x0 |
| 1301 | OPC_Decode, 175, 19, 42, // 2794: decode to S4_pstorerhnewfnew_io using decoder 42 |
| 1302 | // 2794: } |
| 1303 | // 2794: } // switch Inst[26:25] |
| 1304 | // 2794: } |
| 1305 | 1, 0, // 2798: case 0x1: { |
| 1306 | OPC_Decode, 179, 18, 43, // 2800: decode to S2_storerhnewgp using decoder 43 |
| 1307 | // 2800: } |
| 1308 | // 2800: } // switch Inst[27] |
| 1309 | // 2800: } |
| 1310 | 2, 0, // 2804: case 0x2: { |
| 1311 | OPC_SwitchField, 27, 1, // 2806: switch Inst[27] { |
| 1312 | 0, 43, // 2809: case 0x0: { |
| 1313 | OPC_SwitchField, 25, 2, // 2811: switch Inst[26:25] { |
| 1314 | 0, 8, // 2814: case 0x0: { |
| 1315 | OPC_CheckField, 2, 1, 0, // 2816: check Inst[2] == 0x0 |
| 1316 | OPC_Decode, 254, 17, 44, // 2820: decode to S2_pstorerinewt_io using decoder 44 |
| 1317 | // 2820: } |
| 1318 | 1, 8, // 2824: case 0x1: { |
| 1319 | OPC_CheckField, 2, 1, 0, // 2826: check Inst[2] == 0x0 |
| 1320 | OPC_Decode, 200, 19, 44, // 2830: decode to S4_pstorerinewtnew_io using decoder 44 |
| 1321 | // 2830: } |
| 1322 | 2, 8, // 2834: case 0x2: { |
| 1323 | OPC_CheckField, 2, 1, 0, // 2836: check Inst[2] == 0x0 |
| 1324 | OPC_Decode, 251, 17, 44, // 2840: decode to S2_pstorerinewf_io using decoder 44 |
| 1325 | // 2840: } |
| 1326 | 3, 0, // 2844: case 0x3: { |
| 1327 | OPC_CheckField, 2, 1, 0, // 2846: check Inst[2] == 0x0 |
| 1328 | OPC_Decode, 195, 19, 44, // 2850: decode to S4_pstorerinewfnew_io using decoder 44 |
| 1329 | // 2850: } |
| 1330 | // 2850: } // switch Inst[26:25] |
| 1331 | // 2850: } |
| 1332 | 1, 0, // 2854: case 0x1: { |
| 1333 | OPC_Decode, 193, 18, 45, // 2856: decode to S2_storerinewgp using decoder 45 |
| 1334 | // 2856: } |
| 1335 | // 2856: } // switch Inst[27] |
| 1336 | // 2856: } |
| 1337 | // 2856: } // switch Inst[12:11] |
| 1338 | // 2856: } |
| 1339 | 6, 54, // 2860: case 0x6: { |
| 1340 | OPC_SwitchField, 27, 1, // 2862: switch Inst[27] { |
| 1341 | 0, 43, // 2865: case 0x0: { |
| 1342 | OPC_SwitchField, 25, 2, // 2867: switch Inst[26:25] { |
| 1343 | 0, 8, // 2870: case 0x0: { |
| 1344 | OPC_CheckField, 2, 1, 0, // 2872: check Inst[2] == 0x0 |
| 1345 | OPC_Decode, 227, 17, 46, // 2876: decode to S2_pstorerdt_io using decoder 46 |
| 1346 | // 2876: } |
| 1347 | 1, 8, // 2880: case 0x1: { |
| 1348 | OPC_CheckField, 2, 1, 0, // 2882: check Inst[2] == 0x0 |
| 1349 | OPC_Decode, 155, 19, 46, // 2886: decode to S4_pstorerdtnew_io using decoder 46 |
| 1350 | // 2886: } |
| 1351 | 2, 8, // 2890: case 0x2: { |
| 1352 | OPC_CheckField, 2, 1, 0, // 2892: check Inst[2] == 0x0 |
| 1353 | OPC_Decode, 224, 17, 46, // 2896: decode to S2_pstorerdf_io using decoder 46 |
| 1354 | // 2896: } |
| 1355 | 3, 0, // 2900: case 0x3: { |
| 1356 | OPC_CheckField, 2, 1, 0, // 2902: check Inst[2] == 0x0 |
| 1357 | OPC_Decode, 150, 19, 46, // 2906: decode to S4_pstorerdfnew_io using decoder 46 |
| 1358 | // 2906: } |
| 1359 | // 2906: } // switch Inst[26:25] |
| 1360 | // 2906: } |
| 1361 | 1, 0, // 2910: case 0x1: { |
| 1362 | OPC_Decode, 158, 18, 47, // 2912: decode to S2_storerdgp using decoder 47 |
| 1363 | // 2912: } |
| 1364 | // 2912: } // switch Inst[27] |
| 1365 | // 2912: } |
| 1366 | 8, 54, // 2916: case 0x8: { |
| 1367 | OPC_SwitchField, 27, 1, // 2918: switch Inst[27] { |
| 1368 | 0, 43, // 2921: case 0x0: { |
| 1369 | OPC_SwitchField, 25, 2, // 2923: switch Inst[26:25] { |
| 1370 | 0, 8, // 2926: case 0x0: { |
| 1371 | OPC_CheckField, 13, 1, 0, // 2928: check Inst[13] == 0x0 |
| 1372 | OPC_Decode, 193, 12, 48, // 2932: decode to L2_ploadrbt_io using decoder 48 |
| 1373 | // 2932: } |
| 1374 | 1, 8, // 2936: case 0x1: { |
| 1375 | OPC_CheckField, 13, 1, 0, // 2938: check Inst[13] == 0x0 |
| 1376 | OPC_Decode, 195, 12, 48, // 2942: decode to L2_ploadrbtnew_io using decoder 48 |
| 1377 | // 2942: } |
| 1378 | 2, 8, // 2946: case 0x2: { |
| 1379 | OPC_CheckField, 13, 1, 0, // 2948: check Inst[13] == 0x0 |
| 1380 | OPC_Decode, 189, 12, 48, // 2952: decode to L2_ploadrbf_io using decoder 48 |
| 1381 | // 2952: } |
| 1382 | 3, 0, // 2956: case 0x3: { |
| 1383 | OPC_CheckField, 13, 1, 0, // 2958: check Inst[13] == 0x0 |
| 1384 | OPC_Decode, 191, 12, 48, // 2962: decode to L2_ploadrbfnew_io using decoder 48 |
| 1385 | // 2962: } |
| 1386 | // 2962: } // switch Inst[26:25] |
| 1387 | // 2962: } |
| 1388 | 1, 0, // 2966: case 0x1: { |
| 1389 | OPC_Decode, 151, 12, 49, // 2968: decode to L2_loadrbgp using decoder 49 |
| 1390 | // 2968: } |
| 1391 | // 2968: } // switch Inst[27] |
| 1392 | // 2968: } |
| 1393 | 9, 54, // 2972: case 0x9: { |
| 1394 | OPC_SwitchField, 27, 1, // 2974: switch Inst[27] { |
| 1395 | 0, 43, // 2977: case 0x0: { |
| 1396 | OPC_SwitchField, 25, 2, // 2979: switch Inst[26:25] { |
| 1397 | 0, 8, // 2982: case 0x0: { |
| 1398 | OPC_CheckField, 13, 1, 0, // 2984: check Inst[13] == 0x0 |
| 1399 | OPC_Decode, 225, 12, 48, // 2988: decode to L2_ploadrubt_io using decoder 48 |
| 1400 | // 2988: } |
| 1401 | 1, 8, // 2992: case 0x1: { |
| 1402 | OPC_CheckField, 13, 1, 0, // 2994: check Inst[13] == 0x0 |
| 1403 | OPC_Decode, 227, 12, 48, // 2998: decode to L2_ploadrubtnew_io using decoder 48 |
| 1404 | // 2998: } |
| 1405 | 2, 8, // 3002: case 0x2: { |
| 1406 | OPC_CheckField, 13, 1, 0, // 3004: check Inst[13] == 0x0 |
| 1407 | OPC_Decode, 221, 12, 48, // 3008: decode to L2_ploadrubf_io using decoder 48 |
| 1408 | // 3008: } |
| 1409 | 3, 0, // 3012: case 0x3: { |
| 1410 | OPC_CheckField, 13, 1, 0, // 3014: check Inst[13] == 0x0 |
| 1411 | OPC_Decode, 223, 12, 48, // 3018: decode to L2_ploadrubfnew_io using decoder 48 |
| 1412 | // 3018: } |
| 1413 | // 3018: } // switch Inst[26:25] |
| 1414 | // 3018: } |
| 1415 | 1, 0, // 3022: case 0x1: { |
| 1416 | OPC_Decode, 179, 12, 49, // 3024: decode to L2_loadrubgp using decoder 49 |
| 1417 | // 3024: } |
| 1418 | // 3024: } // switch Inst[27] |
| 1419 | // 3024: } |
| 1420 | 10, 54, // 3028: case 0xa: { |
| 1421 | OPC_SwitchField, 27, 1, // 3030: switch Inst[27] { |
| 1422 | 0, 43, // 3033: case 0x0: { |
| 1423 | OPC_SwitchField, 25, 2, // 3035: switch Inst[26:25] { |
| 1424 | 0, 8, // 3038: case 0x0: { |
| 1425 | OPC_CheckField, 13, 1, 0, // 3040: check Inst[13] == 0x0 |
| 1426 | OPC_Decode, 209, 12, 50, // 3044: decode to L2_ploadrht_io using decoder 50 |
| 1427 | // 3044: } |
| 1428 | 1, 8, // 3048: case 0x1: { |
| 1429 | OPC_CheckField, 13, 1, 0, // 3050: check Inst[13] == 0x0 |
| 1430 | OPC_Decode, 211, 12, 50, // 3054: decode to L2_ploadrhtnew_io using decoder 50 |
| 1431 | // 3054: } |
| 1432 | 2, 8, // 3058: case 0x2: { |
| 1433 | OPC_CheckField, 13, 1, 0, // 3060: check Inst[13] == 0x0 |
| 1434 | OPC_Decode, 205, 12, 50, // 3064: decode to L2_ploadrhf_io using decoder 50 |
| 1435 | // 3064: } |
| 1436 | 3, 0, // 3068: case 0x3: { |
| 1437 | OPC_CheckField, 13, 1, 0, // 3070: check Inst[13] == 0x0 |
| 1438 | OPC_Decode, 207, 12, 50, // 3074: decode to L2_ploadrhfnew_io using decoder 50 |
| 1439 | // 3074: } |
| 1440 | // 3074: } // switch Inst[26:25] |
| 1441 | // 3074: } |
| 1442 | 1, 0, // 3078: case 0x1: { |
| 1443 | OPC_Decode, 165, 12, 51, // 3080: decode to L2_loadrhgp using decoder 51 |
| 1444 | // 3080: } |
| 1445 | // 3080: } // switch Inst[27] |
| 1446 | // 3080: } |
| 1447 | 11, 54, // 3084: case 0xb: { |
| 1448 | OPC_SwitchField, 27, 1, // 3086: switch Inst[27] { |
| 1449 | 0, 43, // 3089: case 0x0: { |
| 1450 | OPC_SwitchField, 25, 2, // 3091: switch Inst[26:25] { |
| 1451 | 0, 8, // 3094: case 0x0: { |
| 1452 | OPC_CheckField, 13, 1, 0, // 3096: check Inst[13] == 0x0 |
| 1453 | OPC_Decode, 233, 12, 50, // 3100: decode to L2_ploadruht_io using decoder 50 |
| 1454 | // 3100: } |
| 1455 | 1, 8, // 3104: case 0x1: { |
| 1456 | OPC_CheckField, 13, 1, 0, // 3106: check Inst[13] == 0x0 |
| 1457 | OPC_Decode, 235, 12, 50, // 3110: decode to L2_ploadruhtnew_io using decoder 50 |
| 1458 | // 3110: } |
| 1459 | 2, 8, // 3114: case 0x2: { |
| 1460 | OPC_CheckField, 13, 1, 0, // 3116: check Inst[13] == 0x0 |
| 1461 | OPC_Decode, 229, 12, 50, // 3120: decode to L2_ploadruhf_io using decoder 50 |
| 1462 | // 3120: } |
| 1463 | 3, 0, // 3124: case 0x3: { |
| 1464 | OPC_CheckField, 13, 1, 0, // 3126: check Inst[13] == 0x0 |
| 1465 | OPC_Decode, 231, 12, 50, // 3130: decode to L2_ploadruhfnew_io using decoder 50 |
| 1466 | // 3130: } |
| 1467 | // 3130: } // switch Inst[26:25] |
| 1468 | // 3130: } |
| 1469 | 1, 0, // 3134: case 0x1: { |
| 1470 | OPC_Decode, 186, 12, 51, // 3136: decode to L2_loadruhgp using decoder 51 |
| 1471 | // 3136: } |
| 1472 | // 3136: } // switch Inst[27] |
| 1473 | // 3136: } |
| 1474 | 12, 54, // 3140: case 0xc: { |
| 1475 | OPC_SwitchField, 27, 1, // 3142: switch Inst[27] { |
| 1476 | 0, 43, // 3145: case 0x0: { |
| 1477 | OPC_SwitchField, 25, 2, // 3147: switch Inst[26:25] { |
| 1478 | 0, 8, // 3150: case 0x0: { |
| 1479 | OPC_CheckField, 13, 1, 0, // 3152: check Inst[13] == 0x0 |
| 1480 | OPC_Decode, 217, 12, 52, // 3156: decode to L2_ploadrit_io using decoder 52 |
| 1481 | // 3156: } |
| 1482 | 1, 8, // 3160: case 0x1: { |
| 1483 | OPC_CheckField, 13, 1, 0, // 3162: check Inst[13] == 0x0 |
| 1484 | OPC_Decode, 219, 12, 52, // 3166: decode to L2_ploadritnew_io using decoder 52 |
| 1485 | // 3166: } |
| 1486 | 2, 8, // 3170: case 0x2: { |
| 1487 | OPC_CheckField, 13, 1, 0, // 3172: check Inst[13] == 0x0 |
| 1488 | OPC_Decode, 213, 12, 52, // 3176: decode to L2_ploadrif_io using decoder 52 |
| 1489 | // 3176: } |
| 1490 | 3, 0, // 3180: case 0x3: { |
| 1491 | OPC_CheckField, 13, 1, 0, // 3182: check Inst[13] == 0x0 |
| 1492 | OPC_Decode, 215, 12, 52, // 3186: decode to L2_ploadrifnew_io using decoder 52 |
| 1493 | // 3186: } |
| 1494 | // 3186: } // switch Inst[26:25] |
| 1495 | // 3186: } |
| 1496 | 1, 0, // 3190: case 0x1: { |
| 1497 | OPC_Decode, 172, 12, 53, // 3192: decode to L2_loadrigp using decoder 53 |
| 1498 | // 3192: } |
| 1499 | // 3192: } // switch Inst[27] |
| 1500 | // 3192: } |
| 1501 | 14, 0, // 3196: case 0xe: { |
| 1502 | OPC_SwitchField, 27, 1, // 3198: switch Inst[27] { |
| 1503 | 0, 43, // 3201: case 0x0: { |
| 1504 | OPC_SwitchField, 25, 2, // 3203: switch Inst[26:25] { |
| 1505 | 0, 8, // 3206: case 0x0: { |
| 1506 | OPC_CheckField, 13, 1, 0, // 3208: check Inst[13] == 0x0 |
| 1507 | OPC_Decode, 201, 12, 54, // 3212: decode to L2_ploadrdt_io using decoder 54 |
| 1508 | // 3212: } |
| 1509 | 1, 8, // 3216: case 0x1: { |
| 1510 | OPC_CheckField, 13, 1, 0, // 3218: check Inst[13] == 0x0 |
| 1511 | OPC_Decode, 203, 12, 54, // 3222: decode to L2_ploadrdtnew_io using decoder 54 |
| 1512 | // 3222: } |
| 1513 | 2, 8, // 3226: case 0x2: { |
| 1514 | OPC_CheckField, 13, 1, 0, // 3228: check Inst[13] == 0x0 |
| 1515 | OPC_Decode, 197, 12, 54, // 3232: decode to L2_ploadrdf_io using decoder 54 |
| 1516 | // 3232: } |
| 1517 | 3, 0, // 3236: case 0x3: { |
| 1518 | OPC_CheckField, 13, 1, 0, // 3238: check Inst[13] == 0x0 |
| 1519 | OPC_Decode, 199, 12, 54, // 3242: decode to L2_ploadrdfnew_io using decoder 54 |
| 1520 | // 3242: } |
| 1521 | // 3242: } // switch Inst[26:25] |
| 1522 | // 3242: } |
| 1523 | 1, 0, // 3246: case 0x1: { |
| 1524 | OPC_Decode, 158, 12, 55, // 3248: decode to L2_loadrdgp using decoder 55 |
| 1525 | // 3248: } |
| 1526 | // 3248: } // switch Inst[27] |
| 1527 | // 3248: } |
| 1528 | // 3248: } // switch Inst[24:21] |
| 1529 | // 3248: } |
| 1530 | 5, 187, 4, // 3252: case 0x5: { |
| 1531 | OPC_SwitchField, 25, 3, // 3255: switch Inst[27:25] { |
| 1532 | 0, 53, // 3258: case 0x0: { |
| 1533 | OPC_SwitchField, 21, 4, // 3260: switch Inst[24:21] { |
| 1534 | 5, 8, // 3263: case 0x5: { |
| 1535 | OPC_CheckField, 0, 14, 0, // 3265: check Inst[13:0] == 0x0 |
| 1536 | OPC_Decode, 194, 10, 56, // 3269: decode to J2_callr using decoder 56 |
| 1537 | // 3269: } |
| 1538 | 6, 10, // 3273: case 0x6: { |
| 1539 | OPC_CheckPredicate, 0, // 3275: check predicate 0 |
| 1540 | OPC_CheckField, 0, 14, 0, // 3277: check Inst[13:0] == 0x0 |
| 1541 | OPC_Decode, 196, 10, 56, // 3281: decode to J2_callrh using decoder 56 |
| 1542 | // 3281: } |
| 1543 | 8, 12, // 3285: case 0x8: { |
| 1544 | OPC_CheckField, 10, 4, 0, // 3287: check Inst[13:10] == 0x0 |
| 1545 | OPC_CheckField, 0, 8, 0, // 3291: check Inst[7:0] == 0x0 |
| 1546 | OPC_Decode, 197, 10, 57, // 3295: decode to J2_callrt using decoder 57 |
| 1547 | // 3295: } |
| 1548 | 9, 0, // 3299: case 0x9: { |
| 1549 | OPC_CheckField, 10, 4, 0, // 3301: check Inst[13:10] == 0x0 |
| 1550 | OPC_CheckField, 0, 8, 0, // 3305: check Inst[7:0] == 0x0 |
| 1551 | OPC_Decode, 195, 10, 57, // 3309: decode to J2_callrf using decoder 57 |
| 1552 | // 3309: } |
| 1553 | // 3309: } // switch Inst[24:21] |
| 1554 | // 3309: } |
| 1555 | 1, 129, 1, // 3313: case 0x1: { |
| 1556 | OPC_SwitchField, 21, 4, // 3316: switch Inst[24:21] { |
| 1557 | 4, 8, // 3319: case 0x4: { |
| 1558 | OPC_CheckField, 0, 14, 0, // 3321: check Inst[13:0] == 0x0 |
| 1559 | OPC_Decode, 204, 10, 56, // 3325: decode to J2_jumpr using decoder 56 |
| 1560 | // 3325: } |
| 1561 | 5, 8, // 3329: case 0x5: { |
| 1562 | OPC_CheckField, 0, 14, 0, // 3331: check Inst[13:0] == 0x0 |
| 1563 | OPC_Decode, 221, 11, 56, // 3335: decode to J4_hintjumpr using decoder 56 |
| 1564 | // 3335: } |
| 1565 | 6, 10, // 3339: case 0x6: { |
| 1566 | OPC_CheckPredicate, 0, // 3341: check predicate 0 |
| 1567 | OPC_CheckField, 0, 14, 0, // 3343: check Inst[13:0] == 0x0 |
| 1568 | OPC_Decode, 211, 10, 56, // 3347: decode to J2_jumprh using decoder 56 |
| 1569 | // 3347: } |
| 1570 | 10, 45, // 3351: case 0xa: { |
| 1571 | OPC_SwitchField, 10, 4, // 3353: switch Inst[13:10] { |
| 1572 | 0, 8, // 3356: case 0x0: { |
| 1573 | OPC_CheckField, 0, 8, 0, // 3358: check Inst[7:0] == 0x0 |
| 1574 | OPC_Decode, 216, 10, 57, // 3362: decode to J2_jumprt using decoder 57 |
| 1575 | // 3362: } |
| 1576 | 2, 8, // 3366: case 0x2: { |
| 1577 | OPC_CheckField, 0, 8, 0, // 3368: check Inst[7:0] == 0x0 |
| 1578 | OPC_Decode, 217, 10, 57, // 3372: decode to J2_jumprtnew using decoder 57 |
| 1579 | // 3372: } |
| 1580 | 4, 10, // 3376: case 0x4: { |
| 1581 | OPC_CheckPredicate, 1, // 3378: check predicate 1 |
| 1582 | OPC_CheckField, 0, 8, 0, // 3380: check Inst[7:0] == 0x0 |
| 1583 | OPC_Decode, 219, 10, 57, // 3384: decode to J2_jumprtpt using decoder 57 |
| 1584 | // 3384: } |
| 1585 | 6, 0, // 3388: case 0x6: { |
| 1586 | OPC_CheckField, 0, 8, 0, // 3390: check Inst[7:0] == 0x0 |
| 1587 | OPC_Decode, 218, 10, 57, // 3394: decode to J2_jumprtnewpt using decoder 57 |
| 1588 | // 3394: } |
| 1589 | // 3394: } // switch Inst[13:10] |
| 1590 | // 3394: } |
| 1591 | 11, 0, // 3398: case 0xb: { |
| 1592 | OPC_SwitchField, 10, 4, // 3400: switch Inst[13:10] { |
| 1593 | 0, 8, // 3403: case 0x0: { |
| 1594 | OPC_CheckField, 0, 8, 0, // 3405: check Inst[7:0] == 0x0 |
| 1595 | OPC_Decode, 205, 10, 57, // 3409: decode to J2_jumprf using decoder 57 |
| 1596 | // 3409: } |
| 1597 | 2, 8, // 3413: case 0x2: { |
| 1598 | OPC_CheckField, 0, 8, 0, // 3415: check Inst[7:0] == 0x0 |
| 1599 | OPC_Decode, 206, 10, 57, // 3419: decode to J2_jumprfnew using decoder 57 |
| 1600 | // 3419: } |
| 1601 | 4, 10, // 3423: case 0x4: { |
| 1602 | OPC_CheckPredicate, 1, // 3425: check predicate 1 |
| 1603 | OPC_CheckField, 0, 8, 0, // 3427: check Inst[7:0] == 0x0 |
| 1604 | OPC_Decode, 208, 10, 57, // 3431: decode to J2_jumprfpt using decoder 57 |
| 1605 | // 3431: } |
| 1606 | 6, 0, // 3435: case 0x6: { |
| 1607 | OPC_CheckField, 0, 8, 0, // 3437: check Inst[7:0] == 0x0 |
| 1608 | OPC_Decode, 207, 10, 57, // 3441: decode to J2_jumprfnewpt using decoder 57 |
| 1609 | // 3441: } |
| 1610 | // 3441: } // switch Inst[13:10] |
| 1611 | // 3441: } |
| 1612 | // 3441: } // switch Inst[24:21] |
| 1613 | // 3441: } |
| 1614 | 2, 126, // 3445: case 0x2: { |
| 1615 | OPC_SwitchField, 21, 4, // 3447: switch Inst[24:21] { |
| 1616 | 0, 20, // 3450: case 0x0: { |
| 1617 | OPC_CheckField, 16, 5, 0, // 3452: check Inst[20:16] == 0x0 |
| 1618 | OPC_CheckField, 13, 1, 0, // 3456: check Inst[13] == 0x0 |
| 1619 | OPC_CheckField, 5, 3, 0, // 3460: check Inst[7:5] == 0x0 |
| 1620 | OPC_CheckField, 0, 2, 0, // 3464: check Inst[1:0] == 0x0 |
| 1621 | OPC_Decode, 242, 10, 58, // 3468: decode to J2_trap0 using decoder 58 |
| 1622 | // 3468: } |
| 1623 | 2, 20, // 3472: case 0x2: { |
| 1624 | OPC_CheckField, 18, 3, 0, // 3474: check Inst[20:18] == 0x0 |
| 1625 | OPC_CheckField, 13, 1, 0, // 3478: check Inst[13] == 0x0 |
| 1626 | OPC_CheckField, 5, 3, 0, // 3482: check Inst[7:5] == 0x0 |
| 1627 | OPC_CheckField, 0, 2, 0, // 3486: check Inst[1:0] == 0x0 |
| 1628 | OPC_Decode, 234, 10, 59, // 3490: decode to J2_pause using decoder 59 |
| 1629 | // 3490: } |
| 1630 | 4, 30, // 3494: case 0x4: { |
| 1631 | OPC_CheckField, 0, 2, 0, // 3496: check Inst[1:0] == 0x0 |
| 1632 | OPC_CheckField, 5, 3, 0, // 3500: check Inst[7:5] == 0x0 |
| 1633 | OPC_CheckField, 13, 1, 0, // 3504: check Inst[13] == 0x0 |
| 1634 | OPC_Scope, 10, // 3508: try { |
| 1635 | OPC_CheckField, 16, 5, 0, // 3510: check Inst[20:16] == 0x0 |
| 1636 | OPC_CheckPredicate, 2, // 3514: check predicate 2 |
| 1637 | OPC_Decode, 198, 16, 58, // 3516: decode to PS_trap1 using decoder 58 |
| 1638 | // 3516: } else try { |
| 1639 | OPC_CheckPredicate, 3, // 3520: check predicate 3 |
| 1640 | OPC_Decode, 243, 10, 60, // 3522: decode to J2_trap1 using decoder 60 |
| 1641 | // 3522: } |
| 1642 | // 3522: } |
| 1643 | 13, 8, // 3526: case 0xd: { |
| 1644 | OPC_CheckField, 5, 9, 0, // 3528: check Inst[13:5] == 0x0 |
| 1645 | OPC_Decode, 159, 26, 61, // 3532: decode to Y2_icdatar using decoder 61 |
| 1646 | // 3532: } |
| 1647 | 14, 25, // 3536: case 0xe: { |
| 1648 | OPC_SwitchField, 13, 1, // 3538: switch Inst[13] { |
| 1649 | 0, 8, // 3541: case 0x0: { |
| 1650 | OPC_CheckField, 0, 8, 0, // 3543: check Inst[7:0] == 0x0 |
| 1651 | OPC_Decode, 165, 26, 62, // 3547: decode to Y2_ictagw using decoder 62 |
| 1652 | // 3547: } |
| 1653 | 1, 0, // 3551: case 0x1: { |
| 1654 | OPC_CheckPredicate, 4, // 3553: check predicate 4 |
| 1655 | OPC_CheckField, 0, 8, 0, // 3555: check Inst[7:0] == 0x0 |
| 1656 | OPC_Decode, 160, 26, 62, // 3559: decode to Y2_icdataw using decoder 62 |
| 1657 | // 3559: } |
| 1658 | // 3559: } // switch Inst[13] |
| 1659 | // 3559: } |
| 1660 | 15, 0, // 3563: case 0xf: { |
| 1661 | OPC_CheckField, 5, 9, 0, // 3565: check Inst[13:5] == 0x0 |
| 1662 | OPC_Decode, 164, 26, 61, // 3569: decode to Y2_ictagr using decoder 61 |
| 1663 | // 3569: } |
| 1664 | // 3569: } // switch Inst[24:21] |
| 1665 | // 3569: } |
| 1666 | 3, 68, // 3573: case 0x3: { |
| 1667 | OPC_SwitchField, 0, 14, // 3575: switch Inst[13:0] { |
| 1668 | 0, 19, // 3578: case 0x0: { |
| 1669 | OPC_SwitchField, 21, 4, // 3580: switch Inst[24:21] { |
| 1670 | 6, 4, // 3583: case 0x6: { |
| 1671 | OPC_Decode, 161, 26, 56, // 3585: decode to Y2_icinva using decoder 56 |
| 1672 | // 3585: } |
| 1673 | 15, 0, // 3589: case 0xf: { |
| 1674 | OPC_CheckField, 16, 5, 0, // 3591: check Inst[20:16] == 0x0 |
| 1675 | OPC_Decode, 241, 10, 63, // 3595: decode to J2_rte using decoder 63 |
| 1676 | // 3595: } |
| 1677 | // 3595: } // switch Inst[24:21] |
| 1678 | // 3595: } |
| 1679 | 2, 9, // 3599: case 0x2: { |
| 1680 | OPC_CheckField, 16, 9, 192, 3, // 3601: check Inst[24:16] == 0x1c0 |
| 1681 | OPC_Decode, 166, 26, 63, // 3606: decode to Y2_isync using decoder 63 |
| 1682 | // 3606: } |
| 1683 | 128, 16, 8, // 3610: case 0x800: { |
| 1684 | OPC_CheckField, 21, 4, 6, // 3613: check Inst[24:21] == 0x6 |
| 1685 | OPC_Decode, 162, 26, 56, // 3617: decode to Y2_icinvidx using decoder 56 |
| 1686 | // 3617: } |
| 1687 | 128, 32, 0, // 3621: case 0x1000: { |
| 1688 | OPC_SwitchField, 16, 9, // 3624: switch Inst[24:16] { |
| 1689 | 192, 1, 4, // 3627: case 0xc0: { |
| 1690 | OPC_Decode, 163, 26, 63, // 3630: decode to Y2_ickill using decoder 63 |
| 1691 | // 3630: } |
| 1692 | 224, 3, 0, // 3634: case 0x1e0: { |
| 1693 | OPC_CheckPredicate, 0, // 3637: check predicate 0 |
| 1694 | OPC_Decode, 244, 10, 63, // 3639: decode to J2_unpause using decoder 63 |
| 1695 | // 3639: } |
| 1696 | // 3639: } // switch Inst[24:16] |
| 1697 | // 3639: } |
| 1698 | // 3639: } // switch Inst[13:0] |
| 1699 | // 3639: } |
| 1700 | 4, 8, // 3643: case 0x4: { |
| 1701 | OPC_CheckField, 0, 1, 0, // 3645: check Inst[0] == 0x0 |
| 1702 | OPC_Decode, 199, 10, 64, // 3649: decode to J2_jump using decoder 64 |
| 1703 | // 3649: } |
| 1704 | 5, 8, // 3653: case 0x5: { |
| 1705 | OPC_CheckField, 0, 1, 0, // 3655: check Inst[0] == 0x0 |
| 1706 | OPC_Decode, 192, 10, 64, // 3659: decode to J2_call using decoder 64 |
| 1707 | // 3659: } |
| 1708 | 6, 0, // 3663: case 0x6: { |
| 1709 | OPC_SwitchField, 10, 3, // 3665: switch Inst[12:10] { |
| 1710 | 0, 53, // 3668: case 0x0: { |
| 1711 | OPC_SwitchField, 21, 1, // 3670: switch Inst[21] { |
| 1712 | 0, 23, // 3673: case 0x0: { |
| 1713 | OPC_SwitchField, 24, 1, // 3675: switch Inst[24] { |
| 1714 | 0, 8, // 3678: case 0x0: { |
| 1715 | OPC_CheckField, 0, 1, 0, // 3680: check Inst[0] == 0x0 |
| 1716 | OPC_Decode, 222, 10, 65, // 3684: decode to J2_jumpt using decoder 65 |
| 1717 | // 3684: } |
| 1718 | 1, 0, // 3688: case 0x1: { |
| 1719 | OPC_CheckField, 0, 1, 0, // 3690: check Inst[0] == 0x0 |
| 1720 | OPC_Decode, 198, 10, 65, // 3694: decode to J2_callt using decoder 65 |
| 1721 | // 3694: } |
| 1722 | // 3694: } // switch Inst[24] |
| 1723 | // 3694: } |
| 1724 | 1, 0, // 3698: case 0x1: { |
| 1725 | OPC_SwitchField, 24, 1, // 3700: switch Inst[24] { |
| 1726 | 0, 8, // 3703: case 0x0: { |
| 1727 | OPC_CheckField, 0, 1, 0, // 3705: check Inst[0] == 0x0 |
| 1728 | OPC_Decode, 200, 10, 65, // 3709: decode to J2_jumpf using decoder 65 |
| 1729 | // 3709: } |
| 1730 | 1, 0, // 3713: case 0x1: { |
| 1731 | OPC_CheckField, 0, 1, 0, // 3715: check Inst[0] == 0x0 |
| 1732 | OPC_Decode, 193, 10, 65, // 3719: decode to J2_callf using decoder 65 |
| 1733 | // 3719: } |
| 1734 | // 3719: } // switch Inst[24] |
| 1735 | // 3719: } |
| 1736 | // 3719: } // switch Inst[21] |
| 1737 | // 3719: } |
| 1738 | 2, 31, // 3723: case 0x2: { |
| 1739 | OPC_SwitchField, 21, 1, // 3725: switch Inst[21] { |
| 1740 | 0, 12, // 3728: case 0x0: { |
| 1741 | OPC_CheckField, 24, 1, 0, // 3730: check Inst[24] == 0x0 |
| 1742 | OPC_CheckField, 0, 1, 0, // 3734: check Inst[0] == 0x0 |
| 1743 | OPC_Decode, 223, 10, 65, // 3738: decode to J2_jumptnew using decoder 65 |
| 1744 | // 3738: } |
| 1745 | 1, 0, // 3742: case 0x1: { |
| 1746 | OPC_CheckField, 24, 1, 0, // 3744: check Inst[24] == 0x0 |
| 1747 | OPC_CheckField, 0, 1, 0, // 3748: check Inst[0] == 0x0 |
| 1748 | OPC_Decode, 201, 10, 65, // 3752: decode to J2_jumpfnew using decoder 65 |
| 1749 | // 3752: } |
| 1750 | // 3752: } // switch Inst[21] |
| 1751 | // 3752: } |
| 1752 | 4, 35, // 3756: case 0x4: { |
| 1753 | OPC_SwitchField, 21, 1, // 3758: switch Inst[21] { |
| 1754 | 0, 14, // 3761: case 0x0: { |
| 1755 | OPC_CheckPredicate, 1, // 3763: check predicate 1 |
| 1756 | OPC_CheckField, 24, 1, 0, // 3765: check Inst[24] == 0x0 |
| 1757 | OPC_CheckField, 0, 1, 0, // 3769: check Inst[0] == 0x0 |
| 1758 | OPC_Decode, 225, 10, 65, // 3773: decode to J2_jumptpt using decoder 65 |
| 1759 | // 3773: } |
| 1760 | 1, 0, // 3777: case 0x1: { |
| 1761 | OPC_CheckPredicate, 1, // 3779: check predicate 1 |
| 1762 | OPC_CheckField, 24, 1, 0, // 3781: check Inst[24] == 0x0 |
| 1763 | OPC_CheckField, 0, 1, 0, // 3785: check Inst[0] == 0x0 |
| 1764 | OPC_Decode, 203, 10, 65, // 3789: decode to J2_jumpfpt using decoder 65 |
| 1765 | // 3789: } |
| 1766 | // 3789: } // switch Inst[21] |
| 1767 | // 3789: } |
| 1768 | 6, 0, // 3793: case 0x6: { |
| 1769 | OPC_SwitchField, 21, 1, // 3795: switch Inst[21] { |
| 1770 | 0, 12, // 3798: case 0x0: { |
| 1771 | OPC_CheckField, 24, 1, 0, // 3800: check Inst[24] == 0x0 |
| 1772 | OPC_CheckField, 0, 1, 0, // 3804: check Inst[0] == 0x0 |
| 1773 | OPC_Decode, 224, 10, 65, // 3808: decode to J2_jumptnewpt using decoder 65 |
| 1774 | // 3808: } |
| 1775 | 1, 0, // 3812: case 0x1: { |
| 1776 | OPC_CheckField, 24, 1, 0, // 3814: check Inst[24] == 0x0 |
| 1777 | OPC_CheckField, 0, 1, 0, // 3818: check Inst[0] == 0x0 |
| 1778 | OPC_Decode, 202, 10, 65, // 3822: decode to J2_jumpfnewpt using decoder 65 |
| 1779 | // 3822: } |
| 1780 | // 3822: } // switch Inst[21] |
| 1781 | // 3822: } |
| 1782 | // 3822: } // switch Inst[12:10] |
| 1783 | // 3822: } |
| 1784 | // 3822: } // switch Inst[27:25] |
| 1785 | // 3822: } |
| 1786 | 6, 142, 9, // 3826: case 0x6: { |
| 1787 | OPC_SwitchField, 23, 5, // 3829: switch Inst[27:23] { |
| 1788 | 0, 39, // 3832: case 0x0: { |
| 1789 | OPC_SwitchField, 21, 2, // 3834: switch Inst[22:21] { |
| 1790 | 0, 16, // 3837: case 0x0: { |
| 1791 | OPC_CheckField, 13, 1, 0, // 3839: check Inst[13] == 0x0 |
| 1792 | OPC_CheckField, 5, 3, 0, // 3843: check Inst[7:5] == 0x0 |
| 1793 | OPC_CheckField, 0, 3, 0, // 3847: check Inst[2:0] == 0x0 |
| 1794 | OPC_Decode, 228, 10, 66, // 3851: decode to J2_loop0r using decoder 66 |
| 1795 | // 3851: } |
| 1796 | 1, 0, // 3855: case 0x1: { |
| 1797 | OPC_CheckField, 13, 1, 0, // 3857: check Inst[13] == 0x0 |
| 1798 | OPC_CheckField, 5, 3, 0, // 3861: check Inst[7:5] == 0x0 |
| 1799 | OPC_CheckField, 0, 3, 0, // 3865: check Inst[2:0] == 0x0 |
| 1800 | OPC_Decode, 232, 10, 66, // 3869: decode to J2_loop1r using decoder 66 |
| 1801 | // 3869: } |
| 1802 | // 3869: } // switch Inst[22:21] |
| 1803 | // 3869: } |
| 1804 | 1, 57, // 3873: case 0x1: { |
| 1805 | OPC_SwitchField, 21, 2, // 3875: switch Inst[22:21] { |
| 1806 | 1, 16, // 3878: case 0x1: { |
| 1807 | OPC_CheckField, 13, 1, 0, // 3880: check Inst[13] == 0x0 |
| 1808 | OPC_CheckField, 5, 3, 0, // 3884: check Inst[7:5] == 0x0 |
| 1809 | OPC_CheckField, 0, 3, 0, // 3888: check Inst[2:0] == 0x0 |
| 1810 | OPC_Decode, 236, 10, 66, // 3892: decode to J2_ploop1sr using decoder 66 |
| 1811 | // 3892: } |
| 1812 | 2, 16, // 3896: case 0x2: { |
| 1813 | OPC_CheckField, 13, 1, 0, // 3898: check Inst[13] == 0x0 |
| 1814 | OPC_CheckField, 5, 3, 0, // 3902: check Inst[7:5] == 0x0 |
| 1815 | OPC_CheckField, 0, 3, 0, // 3906: check Inst[2:0] == 0x0 |
| 1816 | OPC_Decode, 238, 10, 66, // 3910: decode to J2_ploop2sr using decoder 66 |
| 1817 | // 3910: } |
| 1818 | 3, 0, // 3914: case 0x3: { |
| 1819 | OPC_CheckField, 13, 1, 0, // 3916: check Inst[13] == 0x0 |
| 1820 | OPC_CheckField, 5, 3, 0, // 3920: check Inst[7:5] == 0x0 |
| 1821 | OPC_CheckField, 0, 3, 0, // 3924: check Inst[2:0] == 0x0 |
| 1822 | OPC_Decode, 240, 10, 66, // 3928: decode to J2_ploop3sr using decoder 66 |
| 1823 | // 3928: } |
| 1824 | // 3928: } // switch Inst[22:21] |
| 1825 | // 3928: } |
| 1826 | 2, 53, // 3932: case 0x2: { |
| 1827 | OPC_SwitchField, 12, 1, // 3934: switch Inst[12] { |
| 1828 | 0, 23, // 3937: case 0x0: { |
| 1829 | OPC_SwitchField, 22, 1, // 3939: switch Inst[22] { |
| 1830 | 0, 8, // 3942: case 0x0: { |
| 1831 | OPC_CheckField, 0, 1, 0, // 3944: check Inst[0] == 0x0 |
| 1832 | OPC_Decode, 220, 10, 67, // 3948: decode to J2_jumprz using decoder 67 |
| 1833 | // 3948: } |
| 1834 | 1, 0, // 3952: case 0x1: { |
| 1835 | OPC_CheckField, 0, 1, 0, // 3954: check Inst[0] == 0x0 |
| 1836 | OPC_Decode, 209, 10, 67, // 3958: decode to J2_jumprgtez using decoder 67 |
| 1837 | // 3958: } |
| 1838 | // 3958: } // switch Inst[22] |
| 1839 | // 3958: } |
| 1840 | 1, 0, // 3962: case 0x1: { |
| 1841 | OPC_SwitchField, 22, 1, // 3964: switch Inst[22] { |
| 1842 | 0, 8, // 3967: case 0x0: { |
| 1843 | OPC_CheckField, 0, 1, 0, // 3969: check Inst[0] == 0x0 |
| 1844 | OPC_Decode, 221, 10, 67, // 3973: decode to J2_jumprzpt using decoder 67 |
| 1845 | // 3973: } |
| 1846 | 1, 0, // 3977: case 0x1: { |
| 1847 | OPC_CheckField, 0, 1, 0, // 3979: check Inst[0] == 0x0 |
| 1848 | OPC_Decode, 210, 10, 67, // 3983: decode to J2_jumprgtezpt using decoder 67 |
| 1849 | // 3983: } |
| 1850 | // 3983: } // switch Inst[22] |
| 1851 | // 3983: } |
| 1852 | // 3983: } // switch Inst[12] |
| 1853 | // 3983: } |
| 1854 | 3, 53, // 3987: case 0x3: { |
| 1855 | OPC_SwitchField, 12, 1, // 3989: switch Inst[12] { |
| 1856 | 0, 23, // 3992: case 0x0: { |
| 1857 | OPC_SwitchField, 22, 1, // 3994: switch Inst[22] { |
| 1858 | 0, 8, // 3997: case 0x0: { |
| 1859 | OPC_CheckField, 0, 1, 0, // 3999: check Inst[0] == 0x0 |
| 1860 | OPC_Decode, 214, 10, 67, // 4003: decode to J2_jumprnz using decoder 67 |
| 1861 | // 4003: } |
| 1862 | 1, 0, // 4007: case 0x1: { |
| 1863 | OPC_CheckField, 0, 1, 0, // 4009: check Inst[0] == 0x0 |
| 1864 | OPC_Decode, 212, 10, 67, // 4013: decode to J2_jumprltez using decoder 67 |
| 1865 | // 4013: } |
| 1866 | // 4013: } // switch Inst[22] |
| 1867 | // 4013: } |
| 1868 | 1, 0, // 4017: case 0x1: { |
| 1869 | OPC_SwitchField, 22, 1, // 4019: switch Inst[22] { |
| 1870 | 0, 8, // 4022: case 0x0: { |
| 1871 | OPC_CheckField, 0, 1, 0, // 4024: check Inst[0] == 0x0 |
| 1872 | OPC_Decode, 215, 10, 67, // 4028: decode to J2_jumprnzpt using decoder 67 |
| 1873 | // 4028: } |
| 1874 | 1, 0, // 4032: case 0x1: { |
| 1875 | OPC_CheckField, 0, 1, 0, // 4034: check Inst[0] == 0x0 |
| 1876 | OPC_Decode, 213, 10, 67, // 4038: decode to J2_jumprltezpt using decoder 67 |
| 1877 | // 4038: } |
| 1878 | // 4038: } // switch Inst[22] |
| 1879 | // 4038: } |
| 1880 | // 4038: } // switch Inst[12] |
| 1881 | // 4038: } |
| 1882 | 4, 102, // 4042: case 0x4: { |
| 1883 | OPC_SwitchField, 5, 3, // 4044: switch Inst[7:5] { |
| 1884 | 0, 37, // 4047: case 0x0: { |
| 1885 | OPC_SwitchField, 21, 2, // 4049: switch Inst[22:21] { |
| 1886 | 0, 8, // 4052: case 0x0: { |
| 1887 | OPC_CheckField, 8, 6, 0, // 4054: check Inst[13:8] == 0x0 |
| 1888 | OPC_Decode, 190, 10, 68, // 4058: decode to G4_tfrgrcr using decoder 68 |
| 1889 | // 4058: } |
| 1890 | 1, 8, // 4062: case 0x1: { |
| 1891 | OPC_CheckField, 8, 6, 0, // 4064: check Inst[13:8] == 0x0 |
| 1892 | OPC_Decode, 146, 8, 69, // 4068: decode to A2_tfrrcr using decoder 69 |
| 1893 | // 4068: } |
| 1894 | 2, 0, // 4072: case 0x2: { |
| 1895 | OPC_CheckField, 8, 6, 0, // 4074: check Inst[13:8] == 0x0 |
| 1896 | OPC_CheckField, 0, 5, 0, // 4078: check Inst[4:0] == 0x0 |
| 1897 | OPC_Decode, 196, 26, 56, // 4082: decode to Y4_trace using decoder 56 |
| 1898 | // 4082: } |
| 1899 | // 4082: } // switch Inst[22:21] |
| 1900 | // 4082: } |
| 1901 | 1, 18, // 4086: case 0x1: { |
| 1902 | OPC_CheckPredicate, 5, // 4088: check predicate 5 |
| 1903 | OPC_CheckField, 21, 2, 2, // 4090: check Inst[22:21] == 0x2 |
| 1904 | OPC_CheckField, 8, 6, 0, // 4094: check Inst[13:8] == 0x0 |
| 1905 | OPC_CheckField, 0, 5, 0, // 4098: check Inst[4:0] == 0x0 |
| 1906 | OPC_Decode, 208, 26, 56, // 4102: decode to Y6_diag using decoder 56 |
| 1907 | // 4102: } |
| 1908 | 2, 18, // 4106: case 0x2: { |
| 1909 | OPC_CheckPredicate, 5, // 4108: check predicate 5 |
| 1910 | OPC_CheckField, 21, 2, 2, // 4110: check Inst[22:21] == 0x2 |
| 1911 | OPC_CheckField, 13, 1, 0, // 4114: check Inst[13] == 0x0 |
| 1912 | OPC_CheckField, 0, 5, 0, // 4118: check Inst[4:0] == 0x0 |
| 1913 | OPC_Decode, 209, 26, 70, // 4122: decode to Y6_diag0 using decoder 70 |
| 1914 | // 4122: } |
| 1915 | 3, 0, // 4126: case 0x3: { |
| 1916 | OPC_CheckPredicate, 5, // 4128: check predicate 5 |
| 1917 | OPC_CheckField, 21, 2, 2, // 4130: check Inst[22:21] == 0x2 |
| 1918 | OPC_CheckField, 13, 1, 0, // 4134: check Inst[13] == 0x0 |
| 1919 | OPC_CheckField, 0, 5, 0, // 4138: check Inst[4:0] == 0x0 |
| 1920 | OPC_Decode, 210, 26, 70, // 4142: decode to Y6_diag1 using decoder 70 |
| 1921 | // 4142: } |
| 1922 | // 4142: } // switch Inst[7:5] |
| 1923 | // 4142: } |
| 1924 | 6, 23, // 4146: case 0x6: { |
| 1925 | OPC_SwitchField, 21, 2, // 4148: switch Inst[22:21] { |
| 1926 | 0, 8, // 4151: case 0x0: { |
| 1927 | OPC_CheckField, 5, 9, 0, // 4153: check Inst[13:5] == 0x0 |
| 1928 | OPC_Decode, 189, 10, 71, // 4157: decode to G4_tfrgpcp using decoder 71 |
| 1929 | // 4157: } |
| 1930 | 1, 0, // 4161: case 0x1: { |
| 1931 | OPC_CheckField, 5, 9, 0, // 4163: check Inst[13:5] == 0x0 |
| 1932 | OPC_Decode, 146, 9, 72, // 4167: decode to A4_tfrpcp using decoder 72 |
| 1933 | // 4167: } |
| 1934 | // 4167: } // switch Inst[22:21] |
| 1935 | // 4167: } |
| 1936 | 8, 78, // 4171: case 0x8: { |
| 1937 | OPC_SwitchField, 0, 14, // 4173: switch Inst[13:0] { |
| 1938 | 0, 23, // 4176: case 0x0: { |
| 1939 | OPC_SwitchField, 21, 2, // 4178: switch Inst[22:21] { |
| 1940 | 0, 4, // 4181: case 0x0: { |
| 1941 | OPC_Decode, 176, 26, 56, // 4183: decode to Y2_swi using decoder 56 |
| 1942 | // 4183: } |
| 1943 | 2, 6, // 4187: case 0x2: { |
| 1944 | OPC_CheckPredicate, 3, // 4189: check predicate 3 |
| 1945 | OPC_Decode, 186, 26, 56, // 4191: decode to Y2_wait using decoder 56 |
| 1946 | // 4191: } |
| 1947 | 3, 0, // 4195: case 0x3: { |
| 1948 | OPC_Decode, 175, 26, 56, // 4197: decode to Y2_stop using decoder 56 |
| 1949 | // 4197: } |
| 1950 | // 4197: } // switch Inst[22:21] |
| 1951 | // 4197: } |
| 1952 | 32, 21, // 4201: case 0x20: { |
| 1953 | OPC_SwitchField, 21, 2, // 4203: switch Inst[22:21] { |
| 1954 | 0, 4, // 4206: case 0x0: { |
| 1955 | OPC_Decode, 144, 26, 56, // 4208: decode to Y2_cswi using decoder 56 |
| 1956 | // 4208: } |
| 1957 | 2, 4, // 4212: case 0x2: { |
| 1958 | OPC_Decode, 171, 26, 56, // 4214: decode to Y2_resume using decoder 56 |
| 1959 | // 4214: } |
| 1960 | 3, 0, // 4218: case 0x3: { |
| 1961 | OPC_Decode, 174, 26, 56, // 4220: decode to Y2_start using decoder 56 |
| 1962 | // 4220: } |
| 1963 | // 4220: } // switch Inst[22:21] |
| 1964 | // 4220: } |
| 1965 | 64, 15, // 4224: case 0x40: { |
| 1966 | OPC_SwitchField, 21, 2, // 4226: switch Inst[22:21] { |
| 1967 | 0, 4, // 4229: case 0x0: { |
| 1968 | OPC_Decode, 158, 26, 56, // 4231: decode to Y2_iassignw using decoder 56 |
| 1969 | // 4231: } |
| 1970 | 3, 0, // 4235: case 0x3: { |
| 1971 | OPC_Decode, 192, 26, 56, // 4237: decode to Y4_nmi using decoder 56 |
| 1972 | // 4237: } |
| 1973 | // 4237: } // switch Inst[22:21] |
| 1974 | // 4237: } |
| 1975 | 96, 0, // 4241: case 0x60: { |
| 1976 | OPC_CheckField, 21, 2, 0, // 4243: check Inst[22:21] == 0x0 |
| 1977 | OPC_Decode, 142, 26, 56, // 4247: decode to Y2_ciad using decoder 56 |
| 1978 | // 4247: } |
| 1979 | // 4247: } // switch Inst[13:0] |
| 1980 | // 4247: } |
| 1981 | 9, 47, // 4251: case 0x9: { |
| 1982 | OPC_SwitchField, 0, 8, // 4253: switch Inst[7:0] { |
| 1983 | 0, 12, // 4256: case 0x0: { |
| 1984 | OPC_CheckField, 21, 2, 0, // 4258: check Inst[22:21] == 0x0 |
| 1985 | OPC_CheckField, 10, 4, 0, // 4262: check Inst[13:10] == 0x0 |
| 1986 | OPC_Decode, 172, 26, 57, // 4266: decode to Y2_setimask using decoder 57 |
| 1987 | // 4266: } |
| 1988 | 32, 14, // 4270: case 0x20: { |
| 1989 | OPC_CheckPredicate, 4, // 4272: check predicate 4 |
| 1990 | OPC_CheckField, 21, 2, 0, // 4274: check Inst[22:21] == 0x0 |
| 1991 | OPC_CheckField, 10, 4, 0, // 4278: check Inst[13:10] == 0x0 |
| 1992 | OPC_Decode, 173, 26, 57, // 4282: decode to Y2_setprio using decoder 57 |
| 1993 | // 4282: } |
| 1994 | 96, 0, // 4286: case 0x60: { |
| 1995 | OPC_CheckField, 21, 2, 0, // 4288: check Inst[22:21] == 0x0 |
| 1996 | OPC_CheckField, 8, 6, 0, // 4292: check Inst[13:8] == 0x0 |
| 1997 | OPC_Decode, 193, 26, 56, // 4296: decode to Y4_siad using decoder 56 |
| 1998 | // 4296: } |
| 1999 | // 4296: } // switch Inst[7:0] |
| 2000 | // 4296: } |
| 2001 | 10, 23, // 4300: case 0xa: { |
| 2002 | OPC_SwitchField, 21, 2, // 4302: switch Inst[22:21] { |
| 2003 | 0, 8, // 4305: case 0x0: { |
| 2004 | OPC_CheckField, 0, 14, 0, // 4307: check Inst[13:0] == 0x0 |
| 2005 | OPC_Decode, 143, 26, 73, // 4311: decode to Y2_crswap0 using decoder 73 |
| 2006 | // 4311: } |
| 2007 | 1, 0, // 4315: case 0x1: { |
| 2008 | OPC_CheckField, 0, 14, 0, // 4317: check Inst[13:0] == 0x0 |
| 2009 | OPC_Decode, 187, 26, 73, // 4321: decode to Y4_crswap1 using decoder 73 |
| 2010 | // 4321: } |
| 2011 | // 4321: } // switch Inst[22:21] |
| 2012 | // 4321: } |
| 2013 | 12, 23, // 4325: case 0xc: { |
| 2014 | OPC_SwitchField, 21, 2, // 4327: switch Inst[22:21] { |
| 2015 | 0, 8, // 4330: case 0x0: { |
| 2016 | OPC_CheckField, 5, 9, 0, // 4332: check Inst[13:5] == 0x0 |
| 2017 | OPC_Decode, 156, 26, 61, // 4336: decode to Y2_getimask using decoder 61 |
| 2018 | // 4336: } |
| 2019 | 3, 0, // 4340: case 0x3: { |
| 2020 | OPC_CheckField, 5, 9, 0, // 4342: check Inst[13:5] == 0x0 |
| 2021 | OPC_Decode, 157, 26, 61, // 4346: decode to Y2_iassignr using decoder 61 |
| 2022 | // 4346: } |
| 2023 | // 4346: } // switch Inst[22:21] |
| 2024 | // 4346: } |
| 2025 | 14, 12, // 4350: case 0xe: { |
| 2026 | OPC_CheckField, 21, 2, 0, // 4352: check Inst[22:21] == 0x0 |
| 2027 | OPC_CheckField, 7, 7, 0, // 4356: check Inst[13:7] == 0x0 |
| 2028 | OPC_Decode, 179, 26, 74, // 4360: decode to Y2_tfrsrcr using decoder 74 |
| 2029 | // 4360: } |
| 2030 | 16, 23, // 4364: case 0x10: { |
| 2031 | OPC_SwitchField, 21, 2, // 4366: switch Inst[22:21] { |
| 2032 | 0, 8, // 4369: case 0x0: { |
| 2033 | OPC_CheckField, 5, 9, 0, // 4371: check Inst[13:5] == 0x0 |
| 2034 | OPC_Decode, 145, 9, 75, // 4375: decode to A4_tfrcpp using decoder 75 |
| 2035 | // 4375: } |
| 2036 | 1, 0, // 4379: case 0x1: { |
| 2037 | OPC_CheckField, 5, 9, 0, // 4381: check Inst[13:5] == 0x0 |
| 2038 | OPC_Decode, 187, 10, 76, // 4385: decode to G4_tfrgcpp using decoder 76 |
| 2039 | // 4385: } |
| 2040 | // 4385: } // switch Inst[22:21] |
| 2041 | // 4385: } |
| 2042 | 18, 31, // 4389: case 0x12: { |
| 2043 | OPC_SwitchField, 21, 2, // 4391: switch Inst[22:21] { |
| 2044 | 0, 12, // 4394: case 0x0: { |
| 2045 | OPC_CheckField, 13, 1, 0, // 4396: check Inst[13] == 0x0 |
| 2046 | OPC_CheckField, 2, 1, 0, // 4400: check Inst[2] == 0x0 |
| 2047 | OPC_Decode, 226, 10, 77, // 4404: decode to J2_loop0i using decoder 77 |
| 2048 | // 4404: } |
| 2049 | 1, 0, // 4408: case 0x1: { |
| 2050 | OPC_CheckField, 13, 1, 0, // 4410: check Inst[13] == 0x0 |
| 2051 | OPC_CheckField, 2, 1, 0, // 4414: check Inst[2] == 0x0 |
| 2052 | OPC_Decode, 230, 10, 77, // 4418: decode to J2_loop1i using decoder 77 |
| 2053 | // 4418: } |
| 2054 | // 4418: } // switch Inst[22:21] |
| 2055 | // 4418: } |
| 2056 | 19, 45, // 4422: case 0x13: { |
| 2057 | OPC_SwitchField, 21, 2, // 4424: switch Inst[22:21] { |
| 2058 | 1, 12, // 4427: case 0x1: { |
| 2059 | OPC_CheckField, 13, 1, 0, // 4429: check Inst[13] == 0x0 |
| 2060 | OPC_CheckField, 2, 1, 0, // 4433: check Inst[2] == 0x0 |
| 2061 | OPC_Decode, 235, 10, 77, // 4437: decode to J2_ploop1si using decoder 77 |
| 2062 | // 4437: } |
| 2063 | 2, 12, // 4441: case 0x2: { |
| 2064 | OPC_CheckField, 13, 1, 0, // 4443: check Inst[13] == 0x0 |
| 2065 | OPC_CheckField, 2, 1, 0, // 4447: check Inst[2] == 0x0 |
| 2066 | OPC_Decode, 237, 10, 77, // 4451: decode to J2_ploop2si using decoder 77 |
| 2067 | // 4451: } |
| 2068 | 3, 0, // 4455: case 0x3: { |
| 2069 | OPC_CheckField, 13, 1, 0, // 4457: check Inst[13] == 0x0 |
| 2070 | OPC_CheckField, 2, 1, 0, // 4461: check Inst[2] == 0x0 |
| 2071 | OPC_Decode, 239, 10, 77, // 4465: decode to J2_ploop3si using decoder 77 |
| 2072 | // 4465: } |
| 2073 | // 4465: } // switch Inst[22:21] |
| 2074 | // 4465: } |
| 2075 | 20, 41, // 4469: case 0x14: { |
| 2076 | OPC_SwitchField, 21, 2, // 4471: switch Inst[22:21] { |
| 2077 | 0, 8, // 4474: case 0x0: { |
| 2078 | OPC_CheckField, 5, 9, 0, // 4476: check Inst[13:5] == 0x0 |
| 2079 | OPC_Decode, 143, 8, 78, // 4480: decode to A2_tfrcrr using decoder 78 |
| 2080 | // 4480: } |
| 2081 | 1, 8, // 4484: case 0x1: { |
| 2082 | OPC_CheckField, 5, 9, 0, // 4486: check Inst[13:5] == 0x0 |
| 2083 | OPC_Decode, 188, 10, 79, // 4490: decode to G4_tfrgcrr using decoder 79 |
| 2084 | // 4490: } |
| 2085 | 2, 0, // 4494: case 0x2: { |
| 2086 | OPC_CheckField, 16, 5, 9, // 4496: check Inst[20:16] == 0x9 |
| 2087 | OPC_CheckField, 13, 1, 0, // 4500: check Inst[13] == 0x0 |
| 2088 | OPC_CheckField, 5, 2, 0, // 4504: check Inst[6:5] == 0x0 |
| 2089 | OPC_Decode, 212, 9, 80, // 4508: decode to C4_addipc using decoder 80 |
| 2090 | // 4508: } |
| 2091 | // 4508: } // switch Inst[22:21] |
| 2092 | // 4508: } |
| 2093 | 22, 141, 1, // 4512: case 0x16: { |
| 2094 | OPC_SwitchField, 18, 5, // 4515: switch Inst[22:18] { |
| 2095 | 0, 23, // 4518: case 0x0: { |
| 2096 | OPC_SwitchField, 2, 6, // 4520: switch Inst[7:2] { |
| 2097 | 0, 8, // 4523: case 0x0: { |
| 2098 | OPC_CheckField, 10, 4, 0, // 4525: check Inst[13:10] == 0x0 |
| 2099 | OPC_Decode, 176, 9, 81, // 4529: decode to C2_and using decoder 81 |
| 2100 | // 4529: } |
| 2101 | 36, 0, // 4533: case 0x24: { |
| 2102 | OPC_CheckField, 10, 4, 8, // 4535: check Inst[13:10] == 0x8 |
| 2103 | OPC_Decode, 223, 9, 82, // 4539: decode to C4_fastcorner9 using decoder 82 |
| 2104 | // 4539: } |
| 2105 | // 4539: } // switch Inst[7:2] |
| 2106 | // 4539: } |
| 2107 | 4, 27, // 4543: case 0x4: { |
| 2108 | OPC_SwitchField, 2, 4, // 4545: switch Inst[5:2] { |
| 2109 | 0, 8, // 4548: case 0x0: { |
| 2110 | OPC_CheckField, 10, 4, 0, // 4550: check Inst[13:10] == 0x0 |
| 2111 | OPC_Decode, 213, 9, 83, // 4554: decode to C4_and_and using decoder 83 |
| 2112 | // 4554: } |
| 2113 | 4, 0, // 4558: case 0x4: { |
| 2114 | OPC_CheckField, 10, 4, 8, // 4560: check Inst[13:10] == 0x8 |
| 2115 | OPC_CheckField, 6, 2, 2, // 4564: check Inst[7:6] == 0x2 |
| 2116 | OPC_Decode, 224, 9, 82, // 4568: decode to C4_fastcorner9_not using decoder 82 |
| 2117 | // 4568: } |
| 2118 | // 4568: } // switch Inst[5:2] |
| 2119 | // 4568: } |
| 2120 | 8, 12, // 4572: case 0x8: { |
| 2121 | OPC_CheckField, 10, 4, 0, // 4574: check Inst[13:10] == 0x0 |
| 2122 | OPC_CheckField, 2, 6, 0, // 4578: check Inst[7:2] == 0x0 |
| 2123 | OPC_Decode, 205, 9, 81, // 4582: decode to C2_or using decoder 81 |
| 2124 | // 4582: } |
| 2125 | 12, 12, // 4586: case 0xc: { |
| 2126 | OPC_CheckField, 10, 4, 0, // 4588: check Inst[13:10] == 0x0 |
| 2127 | OPC_CheckField, 2, 4, 0, // 4592: check Inst[5:2] == 0x0 |
| 2128 | OPC_Decode, 215, 9, 83, // 4596: decode to C4_and_or using decoder 83 |
| 2129 | // 4596: } |
| 2130 | 16, 12, // 4600: case 0x10: { |
| 2131 | OPC_CheckField, 10, 4, 0, // 4602: check Inst[13:10] == 0x0 |
| 2132 | OPC_CheckField, 2, 6, 0, // 4606: check Inst[7:2] == 0x0 |
| 2133 | OPC_Decode, 211, 9, 82, // 4610: decode to C2_xor using decoder 82 |
| 2134 | // 4610: } |
| 2135 | 20, 12, // 4614: case 0x14: { |
| 2136 | OPC_CheckField, 10, 4, 0, // 4616: check Inst[13:10] == 0x0 |
| 2137 | OPC_CheckField, 2, 4, 0, // 4620: check Inst[5:2] == 0x0 |
| 2138 | OPC_Decode, 228, 9, 83, // 4624: decode to C4_or_and using decoder 83 |
| 2139 | // 4624: } |
| 2140 | 24, 12, // 4628: case 0x18: { |
| 2141 | OPC_CheckField, 10, 4, 0, // 4630: check Inst[13:10] == 0x0 |
| 2142 | OPC_CheckField, 2, 6, 0, // 4634: check Inst[7:2] == 0x0 |
| 2143 | OPC_Decode, 177, 9, 81, // 4638: decode to C2_andn using decoder 81 |
| 2144 | // 4638: } |
| 2145 | 28, 0, // 4642: case 0x1c: { |
| 2146 | OPC_CheckField, 10, 4, 0, // 4644: check Inst[13:10] == 0x0 |
| 2147 | OPC_CheckField, 2, 4, 0, // 4648: check Inst[5:2] == 0x0 |
| 2148 | OPC_Decode, 230, 9, 83, // 4652: decode to C4_or_or using decoder 83 |
| 2149 | // 4652: } |
| 2150 | // 4652: } // switch Inst[22:18] |
| 2151 | // 4652: } |
| 2152 | 23, 103, // 4656: case 0x17: { |
| 2153 | OPC_SwitchField, 18, 5, // 4658: switch Inst[22:18] { |
| 2154 | 0, 8, // 4661: case 0x0: { |
| 2155 | OPC_CheckField, 2, 12, 0, // 4663: check Inst[13:2] == 0x0 |
| 2156 | OPC_Decode, 178, 9, 84, // 4667: decode to C2_any8 using decoder 84 |
| 2157 | // 4667: } |
| 2158 | 4, 12, // 4671: case 0x4: { |
| 2159 | OPC_CheckField, 10, 4, 0, // 4673: check Inst[13:10] == 0x0 |
| 2160 | OPC_CheckField, 2, 4, 0, // 4677: check Inst[5:2] == 0x0 |
| 2161 | OPC_Decode, 214, 9, 83, // 4681: decode to C4_and_andn using decoder 83 |
| 2162 | // 4681: } |
| 2163 | 8, 8, // 4685: case 0x8: { |
| 2164 | OPC_CheckField, 2, 12, 0, // 4687: check Inst[13:2] == 0x0 |
| 2165 | OPC_Decode, 175, 9, 84, // 4691: decode to C2_all8 using decoder 84 |
| 2166 | // 4691: } |
| 2167 | 12, 12, // 4695: case 0xc: { |
| 2168 | OPC_CheckField, 10, 4, 0, // 4697: check Inst[13:10] == 0x0 |
| 2169 | OPC_CheckField, 2, 4, 0, // 4701: check Inst[5:2] == 0x0 |
| 2170 | OPC_Decode, 216, 9, 83, // 4705: decode to C4_and_orn using decoder 83 |
| 2171 | // 4705: } |
| 2172 | 16, 8, // 4709: case 0x10: { |
| 2173 | OPC_CheckField, 2, 12, 0, // 4711: check Inst[13:2] == 0x0 |
| 2174 | OPC_Decode, 204, 9, 84, // 4715: decode to C2_not using decoder 84 |
| 2175 | // 4715: } |
| 2176 | 20, 12, // 4719: case 0x14: { |
| 2177 | OPC_CheckField, 10, 4, 0, // 4721: check Inst[13:10] == 0x0 |
| 2178 | OPC_CheckField, 2, 4, 0, // 4725: check Inst[5:2] == 0x0 |
| 2179 | OPC_Decode, 229, 9, 83, // 4729: decode to C4_or_andn using decoder 83 |
| 2180 | // 4729: } |
| 2181 | 24, 12, // 4733: case 0x18: { |
| 2182 | OPC_CheckField, 10, 4, 0, // 4735: check Inst[13:10] == 0x0 |
| 2183 | OPC_CheckField, 2, 6, 0, // 4739: check Inst[7:2] == 0x0 |
| 2184 | OPC_Decode, 206, 9, 81, // 4743: decode to C2_orn using decoder 81 |
| 2185 | // 4743: } |
| 2186 | 28, 0, // 4747: case 0x1c: { |
| 2187 | OPC_CheckField, 10, 4, 0, // 4749: check Inst[13:10] == 0x0 |
| 2188 | OPC_CheckField, 2, 4, 0, // 4753: check Inst[5:2] == 0x0 |
| 2189 | OPC_Decode, 231, 9, 83, // 4757: decode to C4_or_orn using decoder 83 |
| 2190 | // 4757: } |
| 2191 | // 4757: } // switch Inst[22:18] |
| 2192 | // 4757: } |
| 2193 | 24, 134, 1, // 4761: case 0x18: { |
| 2194 | OPC_SwitchField, 5, 3, // 4764: switch Inst[7:5] { |
| 2195 | 0, 57, // 4767: case 0x0: { |
| 2196 | OPC_SwitchField, 21, 2, // 4769: switch Inst[22:21] { |
| 2197 | 0, 12, // 4772: case 0x0: { |
| 2198 | OPC_CheckField, 13, 1, 0, // 4774: check Inst[13] == 0x0 |
| 2199 | OPC_CheckField, 0, 5, 0, // 4778: check Inst[4:0] == 0x0 |
| 2200 | OPC_Decode, 185, 26, 85, // 4782: decode to Y2_tlbw using decoder 85 |
| 2201 | // 4782: } |
| 2202 | 1, 16, // 4786: case 0x1: { |
| 2203 | OPC_CheckField, 16, 5, 0, // 4788: check Inst[20:16] == 0x0 |
| 2204 | OPC_CheckField, 8, 6, 0, // 4792: check Inst[13:8] == 0x0 |
| 2205 | OPC_CheckField, 0, 5, 0, // 4796: check Inst[4:0] == 0x0 |
| 2206 | OPC_Decode, 141, 26, 63, // 4800: decode to Y2_break using decoder 63 |
| 2207 | // 4800: } |
| 2208 | 2, 8, // 4804: case 0x2: { |
| 2209 | OPC_CheckField, 8, 6, 0, // 4806: check Inst[13:8] == 0x0 |
| 2210 | OPC_Decode, 183, 26, 86, // 4810: decode to Y2_tlbr using decoder 86 |
| 2211 | // 4810: } |
| 2212 | 3, 0, // 4814: case 0x3: { |
| 2213 | OPC_CheckPredicate, 6, // 4816: check predicate 6 |
| 2214 | OPC_CheckField, 8, 6, 0, // 4818: check Inst[13:8] == 0x0 |
| 2215 | OPC_Decode, 182, 26, 87, // 4822: decode to Y2_tlbpp using decoder 87 |
| 2216 | // 4822: } |
| 2217 | // 4822: } // switch Inst[22:21] |
| 2218 | // 4822: } |
| 2219 | 1, 16, // 4826: case 0x1: { |
| 2220 | OPC_CheckField, 16, 7, 32, // 4828: check Inst[22:16] == 0x20 |
| 2221 | OPC_CheckField, 8, 6, 0, // 4832: check Inst[13:8] == 0x0 |
| 2222 | OPC_CheckField, 0, 5, 0, // 4836: check Inst[4:0] == 0x0 |
| 2223 | OPC_Decode, 180, 26, 63, // 4840: decode to Y2_tlblock using decoder 63 |
| 2224 | // 4840: } |
| 2225 | 2, 16, // 4844: case 0x2: { |
| 2226 | OPC_CheckField, 16, 7, 32, // 4846: check Inst[22:16] == 0x20 |
| 2227 | OPC_CheckField, 8, 6, 0, // 4850: check Inst[13:8] == 0x0 |
| 2228 | OPC_CheckField, 0, 5, 0, // 4854: check Inst[4:0] == 0x0 |
| 2229 | OPC_Decode, 184, 26, 63, // 4858: decode to Y2_tlbunlock using decoder 63 |
| 2230 | // 4858: } |
| 2231 | 3, 16, // 4862: case 0x3: { |
| 2232 | OPC_CheckField, 16, 7, 32, // 4864: check Inst[22:16] == 0x20 |
| 2233 | OPC_CheckField, 8, 6, 0, // 4868: check Inst[13:8] == 0x0 |
| 2234 | OPC_CheckField, 0, 5, 0, // 4872: check Inst[4:0] == 0x0 |
| 2235 | OPC_Decode, 167, 26, 63, // 4876: decode to Y2_k0lock using decoder 63 |
| 2236 | // 4876: } |
| 2237 | 4, 0, // 4880: case 0x4: { |
| 2238 | OPC_CheckField, 16, 7, 32, // 4882: check Inst[22:16] == 0x20 |
| 2239 | OPC_CheckField, 8, 6, 0, // 4886: check Inst[13:8] == 0x0 |
| 2240 | OPC_CheckField, 0, 5, 0, // 4890: check Inst[4:0] == 0x0 |
| 2241 | OPC_Decode, 168, 26, 63, // 4894: decode to Y2_k0unlock using decoder 63 |
| 2242 | // 4894: } |
| 2243 | // 4894: } // switch Inst[7:5] |
| 2244 | // 4894: } |
| 2245 | 25, 47, // 4898: case 0x19: { |
| 2246 | OPC_SwitchField, 21, 2, // 4900: switch Inst[22:21] { |
| 2247 | 0, 8, // 4903: case 0x0: { |
| 2248 | OPC_CheckField, 5, 9, 0, // 4905: check Inst[13:5] == 0x0 |
| 2249 | OPC_Decode, 181, 26, 61, // 4909: decode to Y2_tlbp using decoder 61 |
| 2250 | // 4909: } |
| 2251 | 1, 8, // 4913: case 0x1: { |
| 2252 | OPC_CheckField, 0, 14, 0, // 4915: check Inst[13:0] == 0x0 |
| 2253 | OPC_Decode, 206, 26, 56, // 4919: decode to Y5_tlbasidi using decoder 56 |
| 2254 | // 4919: } |
| 2255 | 2, 12, // 4923: case 0x2: { |
| 2256 | OPC_CheckField, 13, 1, 0, // 4925: check Inst[13] == 0x0 |
| 2257 | OPC_CheckField, 5, 3, 0, // 4929: check Inst[7:5] == 0x0 |
| 2258 | OPC_Decode, 197, 26, 88, // 4933: decode to Y5_ctlbw using decoder 88 |
| 2259 | // 4933: } |
| 2260 | 3, 0, // 4937: case 0x3: { |
| 2261 | OPC_CheckField, 5, 9, 0, // 4939: check Inst[13:5] == 0x0 |
| 2262 | OPC_Decode, 207, 26, 87, // 4943: decode to Y5_tlboc using decoder 87 |
| 2263 | // 4943: } |
| 2264 | // 4943: } // switch Inst[22:21] |
| 2265 | // 4943: } |
| 2266 | 26, 12, // 4947: case 0x1a: { |
| 2267 | OPC_CheckField, 21, 2, 0, // 4949: check Inst[22:21] == 0x0 |
| 2268 | OPC_CheckField, 7, 7, 0, // 4953: check Inst[13:7] == 0x0 |
| 2269 | OPC_Decode, 195, 26, 89, // 4957: decode to Y4_tfrspcp using decoder 89 |
| 2270 | // 4957: } |
| 2271 | 27, 12, // 4961: case 0x1b: { |
| 2272 | OPC_CheckField, 21, 2, 0, // 4963: check Inst[22:21] == 0x0 |
| 2273 | OPC_CheckField, 0, 14, 0, // 4967: check Inst[13:0] == 0x0 |
| 2274 | OPC_Decode, 188, 26, 90, // 4971: decode to Y4_crswap10 using decoder 90 |
| 2275 | // 4971: } |
| 2276 | 29, 8, // 4975: case 0x1d: { |
| 2277 | OPC_CheckField, 5, 9, 0, // 4977: check Inst[13:5] == 0x0 |
| 2278 | OPC_Decode, 178, 26, 91, // 4981: decode to Y2_tfrscrr using decoder 91 |
| 2279 | // 4981: } |
| 2280 | 30, 0, // 4985: case 0x1e: { |
| 2281 | OPC_CheckField, 5, 9, 0, // 4987: check Inst[13:5] == 0x0 |
| 2282 | OPC_Decode, 194, 26, 92, // 4991: decode to Y4_tfrscpp using decoder 92 |
| 2283 | // 4991: } |
| 2284 | // 4991: } // switch Inst[27:23] |
| 2285 | // 4991: } |
| 2286 | 7, 172, 5, // 4995: case 0x7: { |
| 2287 | OPC_SwitchField, 25, 3, // 4998: switch Inst[27:25] { |
| 2288 | 0, 248, 2, // 5001: case 0x0: { |
| 2289 | OPC_SwitchField, 21, 1, // 5004: switch Inst[21] { |
| 2290 | 0, 168, 1, // 5007: case 0x0: { |
| 2291 | OPC_SwitchField, 10, 4, // 5010: switch Inst[13:10] { |
| 2292 | 0, 23, // 5013: case 0x0: { |
| 2293 | OPC_SwitchField, 22, 3, // 5015: switch Inst[24:22] { |
| 2294 | 0, 8, // 5018: case 0x0: { |
| 2295 | OPC_CheckField, 5, 5, 0, // 5020: check Inst[9:5] == 0x0 |
| 2296 | OPC_Decode, 188, 7, 61, // 5024: decode to A2_aslh using decoder 61 |
| 2297 | // 5024: } |
| 2298 | 3, 0, // 5028: case 0x3: { |
| 2299 | OPC_CheckField, 5, 5, 0, // 5030: check Inst[9:5] == 0x0 |
| 2300 | OPC_Decode, 211, 8, 61, // 5034: decode to A2_zxth using decoder 61 |
| 2301 | // 5034: } |
| 2302 | // 5034: } // switch Inst[24:22] |
| 2303 | // 5034: } |
| 2304 | 8, 33, // 5038: case 0x8: { |
| 2305 | OPC_SwitchField, 22, 3, // 5040: switch Inst[24:22] { |
| 2306 | 0, 8, // 5043: case 0x0: { |
| 2307 | OPC_CheckField, 5, 3, 0, // 5045: check Inst[7:5] == 0x0 |
| 2308 | OPC_Decode, 242, 8, 93, // 5049: decode to A4_paslht using decoder 93 |
| 2309 | // 5049: } |
| 2310 | 2, 8, // 5053: case 0x2: { |
| 2311 | OPC_CheckField, 5, 3, 0, // 5055: check Inst[7:5] == 0x0 |
| 2312 | OPC_Decode, 130, 9, 93, // 5059: decode to A4_pzxtbt using decoder 93 |
| 2313 | // 5059: } |
| 2314 | 3, 0, // 5063: case 0x3: { |
| 2315 | OPC_CheckField, 5, 3, 0, // 5065: check Inst[7:5] == 0x0 |
| 2316 | OPC_Decode, 134, 9, 93, // 5069: decode to A4_pzxtht using decoder 93 |
| 2317 | // 5069: } |
| 2318 | // 5069: } // switch Inst[24:22] |
| 2319 | // 5069: } |
| 2320 | 9, 33, // 5073: case 0x9: { |
| 2321 | OPC_SwitchField, 22, 3, // 5075: switch Inst[24:22] { |
| 2322 | 0, 8, // 5078: case 0x0: { |
| 2323 | OPC_CheckField, 5, 3, 0, // 5080: check Inst[7:5] == 0x0 |
| 2324 | OPC_Decode, 243, 8, 93, // 5084: decode to A4_paslhtnew using decoder 93 |
| 2325 | // 5084: } |
| 2326 | 2, 8, // 5088: case 0x2: { |
| 2327 | OPC_CheckField, 5, 3, 0, // 5090: check Inst[7:5] == 0x0 |
| 2328 | OPC_Decode, 131, 9, 93, // 5094: decode to A4_pzxtbtnew using decoder 93 |
| 2329 | // 5094: } |
| 2330 | 3, 0, // 5098: case 0x3: { |
| 2331 | OPC_CheckField, 5, 3, 0, // 5100: check Inst[7:5] == 0x0 |
| 2332 | OPC_Decode, 135, 9, 93, // 5104: decode to A4_pzxthtnew using decoder 93 |
| 2333 | // 5104: } |
| 2334 | // 5104: } // switch Inst[24:22] |
| 2335 | // 5104: } |
| 2336 | 10, 33, // 5108: case 0xa: { |
| 2337 | OPC_SwitchField, 22, 3, // 5110: switch Inst[24:22] { |
| 2338 | 0, 8, // 5113: case 0x0: { |
| 2339 | OPC_CheckField, 5, 3, 0, // 5115: check Inst[7:5] == 0x0 |
| 2340 | OPC_Decode, 240, 8, 93, // 5119: decode to A4_paslhf using decoder 93 |
| 2341 | // 5119: } |
| 2342 | 2, 8, // 5123: case 0x2: { |
| 2343 | OPC_CheckField, 5, 3, 0, // 5125: check Inst[7:5] == 0x0 |
| 2344 | OPC_Decode, 128, 9, 93, // 5129: decode to A4_pzxtbf using decoder 93 |
| 2345 | // 5129: } |
| 2346 | 3, 0, // 5133: case 0x3: { |
| 2347 | OPC_CheckField, 5, 3, 0, // 5135: check Inst[7:5] == 0x0 |
| 2348 | OPC_Decode, 132, 9, 93, // 5139: decode to A4_pzxthf using decoder 93 |
| 2349 | // 5139: } |
| 2350 | // 5139: } // switch Inst[24:22] |
| 2351 | // 5139: } |
| 2352 | 11, 0, // 5143: case 0xb: { |
| 2353 | OPC_SwitchField, 22, 3, // 5145: switch Inst[24:22] { |
| 2354 | 0, 8, // 5148: case 0x0: { |
| 2355 | OPC_CheckField, 5, 3, 0, // 5150: check Inst[7:5] == 0x0 |
| 2356 | OPC_Decode, 241, 8, 93, // 5154: decode to A4_paslhfnew using decoder 93 |
| 2357 | // 5154: } |
| 2358 | 2, 8, // 5158: case 0x2: { |
| 2359 | OPC_CheckField, 5, 3, 0, // 5160: check Inst[7:5] == 0x0 |
| 2360 | OPC_Decode, 129, 9, 93, // 5164: decode to A4_pzxtbfnew using decoder 93 |
| 2361 | // 5164: } |
| 2362 | 3, 0, // 5168: case 0x3: { |
| 2363 | OPC_CheckField, 5, 3, 0, // 5170: check Inst[7:5] == 0x0 |
| 2364 | OPC_Decode, 133, 9, 93, // 5174: decode to A4_pzxthfnew using decoder 93 |
| 2365 | // 5174: } |
| 2366 | // 5174: } // switch Inst[24:22] |
| 2367 | // 5174: } |
| 2368 | // 5174: } // switch Inst[13:10] |
| 2369 | // 5174: } |
| 2370 | 1, 0, // 5178: case 0x1: { |
| 2371 | OPC_SwitchField, 24, 1, // 5180: switch Inst[24] { |
| 2372 | 0, 188, 1, // 5183: case 0x0: { |
| 2373 | OPC_SwitchField, 10, 4, // 5186: switch Inst[13:10] { |
| 2374 | 0, 43, // 5189: case 0x0: { |
| 2375 | OPC_SwitchField, 22, 2, // 5191: switch Inst[23:22] { |
| 2376 | 0, 8, // 5194: case 0x0: { |
| 2377 | OPC_CheckField, 5, 5, 0, // 5196: check Inst[9:5] == 0x0 |
| 2378 | OPC_Decode, 189, 7, 61, // 5200: decode to A2_asrh using decoder 61 |
| 2379 | // 5200: } |
| 2380 | 1, 8, // 5204: case 0x1: { |
| 2381 | OPC_CheckField, 5, 5, 0, // 5206: check Inst[9:5] == 0x0 |
| 2382 | OPC_Decode, 142, 8, 61, // 5210: decode to A2_tfr using decoder 61 |
| 2383 | // 5210: } |
| 2384 | 2, 8, // 5214: case 0x2: { |
| 2385 | OPC_CheckField, 5, 5, 0, // 5216: check Inst[9:5] == 0x0 |
| 2386 | OPC_Decode, 139, 8, 61, // 5220: decode to A2_sxtb using decoder 61 |
| 2387 | // 5220: } |
| 2388 | 3, 0, // 5224: case 0x3: { |
| 2389 | OPC_CheckField, 5, 5, 0, // 5226: check Inst[9:5] == 0x0 |
| 2390 | OPC_Decode, 140, 8, 61, // 5230: decode to A2_sxth using decoder 61 |
| 2391 | // 5230: } |
| 2392 | // 5230: } // switch Inst[23:22] |
| 2393 | // 5230: } |
| 2394 | 8, 33, // 5234: case 0x8: { |
| 2395 | OPC_SwitchField, 22, 2, // 5236: switch Inst[23:22] { |
| 2396 | 0, 8, // 5239: case 0x0: { |
| 2397 | OPC_CheckField, 5, 3, 0, // 5241: check Inst[7:5] == 0x0 |
| 2398 | OPC_Decode, 246, 8, 93, // 5245: decode to A4_pasrht using decoder 93 |
| 2399 | // 5245: } |
| 2400 | 2, 8, // 5249: case 0x2: { |
| 2401 | OPC_CheckField, 5, 3, 0, // 5251: check Inst[7:5] == 0x0 |
| 2402 | OPC_Decode, 250, 8, 93, // 5255: decode to A4_psxtbt using decoder 93 |
| 2403 | // 5255: } |
| 2404 | 3, 0, // 5259: case 0x3: { |
| 2405 | OPC_CheckField, 5, 3, 0, // 5261: check Inst[7:5] == 0x0 |
| 2406 | OPC_Decode, 254, 8, 93, // 5265: decode to A4_psxtht using decoder 93 |
| 2407 | // 5265: } |
| 2408 | // 5265: } // switch Inst[23:22] |
| 2409 | // 5265: } |
| 2410 | 9, 33, // 5269: case 0x9: { |
| 2411 | OPC_SwitchField, 22, 2, // 5271: switch Inst[23:22] { |
| 2412 | 0, 8, // 5274: case 0x0: { |
| 2413 | OPC_CheckField, 5, 3, 0, // 5276: check Inst[7:5] == 0x0 |
| 2414 | OPC_Decode, 247, 8, 93, // 5280: decode to A4_pasrhtnew using decoder 93 |
| 2415 | // 5280: } |
| 2416 | 2, 8, // 5284: case 0x2: { |
| 2417 | OPC_CheckField, 5, 3, 0, // 5286: check Inst[7:5] == 0x0 |
| 2418 | OPC_Decode, 251, 8, 93, // 5290: decode to A4_psxtbtnew using decoder 93 |
| 2419 | // 5290: } |
| 2420 | 3, 0, // 5294: case 0x3: { |
| 2421 | OPC_CheckField, 5, 3, 0, // 5296: check Inst[7:5] == 0x0 |
| 2422 | OPC_Decode, 255, 8, 93, // 5300: decode to A4_psxthtnew using decoder 93 |
| 2423 | // 5300: } |
| 2424 | // 5300: } // switch Inst[23:22] |
| 2425 | // 5300: } |
| 2426 | 10, 33, // 5304: case 0xa: { |
| 2427 | OPC_SwitchField, 22, 2, // 5306: switch Inst[23:22] { |
| 2428 | 0, 8, // 5309: case 0x0: { |
| 2429 | OPC_CheckField, 5, 3, 0, // 5311: check Inst[7:5] == 0x0 |
| 2430 | OPC_Decode, 244, 8, 93, // 5315: decode to A4_pasrhf using decoder 93 |
| 2431 | // 5315: } |
| 2432 | 2, 8, // 5319: case 0x2: { |
| 2433 | OPC_CheckField, 5, 3, 0, // 5321: check Inst[7:5] == 0x0 |
| 2434 | OPC_Decode, 248, 8, 93, // 5325: decode to A4_psxtbf using decoder 93 |
| 2435 | // 5325: } |
| 2436 | 3, 0, // 5329: case 0x3: { |
| 2437 | OPC_CheckField, 5, 3, 0, // 5331: check Inst[7:5] == 0x0 |
| 2438 | OPC_Decode, 252, 8, 93, // 5335: decode to A4_psxthf using decoder 93 |
| 2439 | // 5335: } |
| 2440 | // 5335: } // switch Inst[23:22] |
| 2441 | // 5335: } |
| 2442 | 11, 0, // 5339: case 0xb: { |
| 2443 | OPC_SwitchField, 22, 2, // 5341: switch Inst[23:22] { |
| 2444 | 0, 8, // 5344: case 0x0: { |
| 2445 | OPC_CheckField, 5, 3, 0, // 5346: check Inst[7:5] == 0x0 |
| 2446 | OPC_Decode, 245, 8, 93, // 5350: decode to A4_pasrhfnew using decoder 93 |
| 2447 | // 5350: } |
| 2448 | 2, 8, // 5354: case 0x2: { |
| 2449 | OPC_CheckField, 5, 3, 0, // 5356: check Inst[7:5] == 0x0 |
| 2450 | OPC_Decode, 249, 8, 93, // 5360: decode to A4_psxtbfnew using decoder 93 |
| 2451 | // 5360: } |
| 2452 | 3, 0, // 5364: case 0x3: { |
| 2453 | OPC_CheckField, 5, 3, 0, // 5366: check Inst[7:5] == 0x0 |
| 2454 | OPC_Decode, 253, 8, 93, // 5370: decode to A4_psxthfnew using decoder 93 |
| 2455 | // 5370: } |
| 2456 | // 5370: } // switch Inst[23:22] |
| 2457 | // 5370: } |
| 2458 | // 5370: } // switch Inst[13:10] |
| 2459 | // 5370: } |
| 2460 | 1, 0, // 5374: case 0x1: { |
| 2461 | OPC_Decode, 145, 8, 94, // 5376: decode to A2_tfril using decoder 94 |
| 2462 | // 5376: } |
| 2463 | // 5376: } // switch Inst[24] |
| 2464 | // 5376: } |
| 2465 | // 5376: } // switch Inst[21] |
| 2466 | // 5376: } |
| 2467 | 1, 64, // 5380: case 0x1: { |
| 2468 | OPC_SwitchField, 24, 1, // 5382: switch Inst[24] { |
| 2469 | 0, 8, // 5385: case 0x0: { |
| 2470 | OPC_CheckField, 21, 1, 1, // 5387: check Inst[21] == 0x1 |
| 2471 | OPC_Decode, 144, 8, 94, // 5391: decode to A2_tfrih using decoder 94 |
| 2472 | // 5391: } |
| 2473 | 1, 0, // 5395: case 0x1: { |
| 2474 | OPC_SwitchField, 13, 1, // 5397: switch Inst[13] { |
| 2475 | 0, 15, // 5400: case 0x0: { |
| 2476 | OPC_SwitchField, 23, 1, // 5402: switch Inst[23] { |
| 2477 | 0, 4, // 5405: case 0x0: { |
| 2478 | OPC_Decode, 202, 9, 95, // 5407: decode to C2_muxir using decoder 95 |
| 2479 | // 5407: } |
| 2480 | 1, 0, // 5411: case 0x1: { |
| 2481 | OPC_Decode, 203, 9, 96, // 5413: decode to C2_muxri using decoder 96 |
| 2482 | // 5413: } |
| 2483 | // 5413: } // switch Inst[23] |
| 2484 | // 5413: } |
| 2485 | 1, 0, // 5417: case 0x1: { |
| 2486 | OPC_SwitchField, 21, 3, // 5419: switch Inst[23:21] { |
| 2487 | 0, 4, // 5422: case 0x0: { |
| 2488 | OPC_Decode, 233, 8, 97, // 5424: decode to A4_combineri using decoder 97 |
| 2489 | // 5424: } |
| 2490 | 1, 4, // 5428: case 0x1: { |
| 2491 | OPC_Decode, 232, 8, 98, // 5430: decode to A4_combineir using decoder 98 |
| 2492 | // 5430: } |
| 2493 | 2, 4, // 5434: case 0x2: { |
| 2494 | OPC_Decode, 137, 9, 99, // 5436: decode to A4_rcmpeqi using decoder 99 |
| 2495 | // 5436: } |
| 2496 | 3, 0, // 5440: case 0x3: { |
| 2497 | OPC_Decode, 139, 9, 99, // 5442: decode to A4_rcmpneqi using decoder 99 |
| 2498 | // 5442: } |
| 2499 | // 5442: } // switch Inst[23:21] |
| 2500 | // 5442: } |
| 2501 | // 5442: } // switch Inst[13] |
| 2502 | // 5442: } |
| 2503 | // 5442: } // switch Inst[24] |
| 2504 | // 5442: } |
| 2505 | 2, 101, // 5446: case 0x2: { |
| 2506 | OPC_SwitchField, 23, 2, // 5448: switch Inst[24:23] { |
| 2507 | 0, 15, // 5451: case 0x0: { |
| 2508 | OPC_SwitchField, 13, 1, // 5453: switch Inst[13] { |
| 2509 | 0, 4, // 5456: case 0x0: { |
| 2510 | OPC_Decode, 215, 7, 95, // 5458: decode to A2_paddit using decoder 95 |
| 2511 | // 5458: } |
| 2512 | 1, 0, // 5462: case 0x1: { |
| 2513 | OPC_Decode, 216, 7, 95, // 5464: decode to A2_padditnew using decoder 95 |
| 2514 | // 5464: } |
| 2515 | // 5464: } // switch Inst[13] |
| 2516 | // 5464: } |
| 2517 | 1, 15, // 5468: case 0x1: { |
| 2518 | OPC_SwitchField, 13, 1, // 5470: switch Inst[13] { |
| 2519 | 0, 4, // 5473: case 0x0: { |
| 2520 | OPC_Decode, 213, 7, 95, // 5475: decode to A2_paddif using decoder 95 |
| 2521 | // 5475: } |
| 2522 | 1, 0, // 5479: case 0x1: { |
| 2523 | OPC_Decode, 214, 7, 95, // 5481: decode to A2_paddifnew using decoder 95 |
| 2524 | // 5481: } |
| 2525 | // 5481: } // switch Inst[13] |
| 2526 | // 5481: } |
| 2527 | 2, 37, // 5485: case 0x2: { |
| 2528 | OPC_SwitchField, 2, 3, // 5487: switch Inst[4:2] { |
| 2529 | 0, 15, // 5490: case 0x0: { |
| 2530 | OPC_SwitchField, 22, 1, // 5492: switch Inst[22] { |
| 2531 | 0, 4, // 5495: case 0x0: { |
| 2532 | OPC_Decode, 191, 9, 100, // 5497: decode to C2_cmpeqi using decoder 100 |
| 2533 | // 5497: } |
| 2534 | 1, 0, // 5501: case 0x1: { |
| 2535 | OPC_Decode, 194, 9, 100, // 5503: decode to C2_cmpgti using decoder 100 |
| 2536 | // 5503: } |
| 2537 | // 5503: } // switch Inst[22] |
| 2538 | // 5503: } |
| 2539 | 4, 0, // 5507: case 0x4: { |
| 2540 | OPC_SwitchField, 22, 1, // 5509: switch Inst[22] { |
| 2541 | 0, 4, // 5512: case 0x0: { |
| 2542 | OPC_Decode, 222, 9, 100, // 5514: decode to C4_cmpneqi using decoder 100 |
| 2543 | // 5514: } |
| 2544 | 1, 0, // 5518: case 0x1: { |
| 2545 | OPC_Decode, 218, 9, 100, // 5520: decode to C4_cmpltei using decoder 100 |
| 2546 | // 5520: } |
| 2547 | // 5520: } // switch Inst[22] |
| 2548 | // 5520: } |
| 2549 | // 5520: } // switch Inst[4:2] |
| 2550 | // 5520: } |
| 2551 | 3, 0, // 5524: case 0x3: { |
| 2552 | OPC_SwitchField, 2, 3, // 5526: switch Inst[4:2] { |
| 2553 | 0, 8, // 5529: case 0x0: { |
| 2554 | OPC_CheckField, 21, 2, 0, // 5531: check Inst[22:21] == 0x0 |
| 2555 | OPC_Decode, 197, 9, 101, // 5535: decode to C2_cmpgtui using decoder 101 |
| 2556 | // 5535: } |
| 2557 | 4, 0, // 5539: case 0x4: { |
| 2558 | OPC_CheckField, 21, 2, 0, // 5541: check Inst[22:21] == 0x0 |
| 2559 | OPC_Decode, 220, 9, 101, // 5545: decode to C4_cmplteui using decoder 101 |
| 2560 | // 5545: } |
| 2561 | // 5545: } // switch Inst[4:2] |
| 2562 | // 5545: } |
| 2563 | // 5545: } // switch Inst[24:23] |
| 2564 | // 5545: } |
| 2565 | 3, 21, // 5549: case 0x3: { |
| 2566 | OPC_SwitchField, 22, 3, // 5551: switch Inst[24:22] { |
| 2567 | 0, 4, // 5554: case 0x0: { |
| 2568 | OPC_Decode, 186, 7, 102, // 5556: decode to A2_andir using decoder 102 |
| 2569 | // 5556: } |
| 2570 | 1, 4, // 5560: case 0x1: { |
| 2571 | OPC_Decode, 255, 7, 103, // 5562: decode to A2_subri using decoder 103 |
| 2572 | // 5562: } |
| 2573 | 2, 0, // 5566: case 0x2: { |
| 2574 | OPC_Decode, 209, 7, 102, // 5568: decode to A2_orir using decoder 102 |
| 2575 | // 5568: } |
| 2576 | // 5568: } // switch Inst[24:22] |
| 2577 | // 5568: } |
| 2578 | 4, 12, // 5572: case 0x4: { |
| 2579 | OPC_CheckField, 24, 1, 0, // 5574: check Inst[24] == 0x0 |
| 2580 | OPC_CheckField, 21, 1, 0, // 5578: check Inst[21] == 0x0 |
| 2581 | OPC_Decode, 147, 8, 104, // 5582: decode to A2_tfrsi using decoder 104 |
| 2582 | // 5582: } |
| 2583 | 5, 4, // 5586: case 0x5: { |
| 2584 | OPC_Decode, 201, 9, 105, // 5588: decode to C2_muxii using decoder 105 |
| 2585 | // 5588: } |
| 2586 | 6, 19, // 5592: case 0x6: { |
| 2587 | OPC_SwitchField, 23, 2, // 5594: switch Inst[24:23] { |
| 2588 | 0, 4, // 5597: case 0x0: { |
| 2589 | OPC_Decode, 194, 7, 106, // 5599: decode to A2_combineii using decoder 106 |
| 2590 | // 5599: } |
| 2591 | 1, 0, // 5603: case 0x1: { |
| 2592 | OPC_CheckField, 21, 2, 0, // 5605: check Inst[22:21] == 0x0 |
| 2593 | OPC_Decode, 231, 8, 107, // 5609: decode to A4_combineii using decoder 107 |
| 2594 | // 5609: } |
| 2595 | // 5609: } // switch Inst[24:23] |
| 2596 | // 5609: } |
| 2597 | 7, 0, // 5613: case 0x7: { |
| 2598 | OPC_SwitchField, 23, 2, // 5615: switch Inst[24:23] { |
| 2599 | 0, 23, // 5618: case 0x0: { |
| 2600 | OPC_SwitchField, 13, 1, // 5620: switch Inst[13] { |
| 2601 | 0, 8, // 5623: case 0x0: { |
| 2602 | OPC_CheckField, 20, 1, 0, // 5625: check Inst[20] == 0x0 |
| 2603 | OPC_Decode, 187, 9, 108, // 5629: decode to C2_cmoveit using decoder 108 |
| 2604 | // 5629: } |
| 2605 | 1, 0, // 5633: case 0x1: { |
| 2606 | OPC_CheckField, 20, 1, 0, // 5635: check Inst[20] == 0x0 |
| 2607 | OPC_Decode, 189, 9, 108, // 5639: decode to C2_cmovenewit using decoder 108 |
| 2608 | // 5639: } |
| 2609 | // 5639: } // switch Inst[13] |
| 2610 | // 5639: } |
| 2611 | 1, 23, // 5643: case 0x1: { |
| 2612 | OPC_SwitchField, 13, 1, // 5645: switch Inst[13] { |
| 2613 | 0, 8, // 5648: case 0x0: { |
| 2614 | OPC_CheckField, 20, 1, 0, // 5650: check Inst[20] == 0x0 |
| 2615 | OPC_Decode, 186, 9, 108, // 5654: decode to C2_cmoveif using decoder 108 |
| 2616 | // 5654: } |
| 2617 | 1, 0, // 5658: case 0x1: { |
| 2618 | OPC_CheckField, 20, 1, 0, // 5660: check Inst[20] == 0x0 |
| 2619 | OPC_Decode, 188, 9, 108, // 5664: decode to C2_cmovenewif using decoder 108 |
| 2620 | // 5664: } |
| 2621 | // 5664: } // switch Inst[13] |
| 2622 | // 5664: } |
| 2623 | 2, 0, // 5668: case 0x2: { |
| 2624 | OPC_CheckField, 16, 7, 0, // 5670: check Inst[22:16] == 0x0 |
| 2625 | OPC_CheckField, 0, 14, 0, // 5674: check Inst[13:0] == 0x0 |
| 2626 | OPC_Decode, 206, 7, 63, // 5678: decode to A2_nop using decoder 63 |
| 2627 | // 5678: } |
| 2628 | // 5678: } // switch Inst[24:23] |
| 2629 | // 5678: } |
| 2630 | // 5678: } // switch Inst[27:25] |
| 2631 | // 5678: } |
| 2632 | 8, 202, 14, // 5682: case 0x8: { |
| 2633 | OPC_SwitchField, 24, 4, // 5685: switch Inst[27:24] { |
| 2634 | 0, 227, 2, // 5688: case 0x0: { |
| 2635 | OPC_SwitchField, 5, 3, // 5691: switch Inst[7:5] { |
| 2636 | 0, 49, // 5694: case 0x0: { |
| 2637 | OPC_SwitchField, 21, 3, // 5696: switch Inst[23:21] { |
| 2638 | 0, 4, // 5699: case 0x0: { |
| 2639 | OPC_Decode, 240, 16, 109, // 5701: decode to S2_asr_i_p using decoder 109 |
| 2640 | // 5701: } |
| 2641 | 1, 8, // 5705: case 0x1: { |
| 2642 | OPC_CheckField, 12, 2, 0, // 5707: check Inst[13:12] == 0x0 |
| 2643 | OPC_Decode, 135, 20, 110, // 5711: decode to S5_vasrhrnd using decoder 110 |
| 2644 | // 5711: } |
| 2645 | 2, 8, // 5715: case 0x2: { |
| 2646 | OPC_CheckField, 13, 1, 0, // 5717: check Inst[13] == 0x0 |
| 2647 | OPC_Decode, 254, 16, 111, // 5721: decode to S2_asr_i_vw using decoder 111 |
| 2648 | // 5721: } |
| 2649 | 4, 8, // 5725: case 0x4: { |
| 2650 | OPC_CheckField, 12, 2, 0, // 5727: check Inst[13:12] == 0x0 |
| 2651 | OPC_Decode, 253, 16, 110, // 5731: decode to S2_asr_i_vh using decoder 110 |
| 2652 | // 5731: } |
| 2653 | 7, 0, // 5735: case 0x7: { |
| 2654 | OPC_CheckField, 8, 6, 0, // 5737: check Inst[13:8] == 0x0 |
| 2655 | OPC_Decode, 254, 9, 112, // 5741: decode to F2_conv_df2d using decoder 112 |
| 2656 | // 5741: } |
| 2657 | // 5741: } // switch Inst[23:21] |
| 2658 | // 5741: } |
| 2659 | 1, 39, // 5745: case 0x1: { |
| 2660 | OPC_SwitchField, 21, 3, // 5747: switch Inst[23:21] { |
| 2661 | 0, 4, // 5750: case 0x0: { |
| 2662 | OPC_Decode, 182, 17, 109, // 5752: decode to S2_lsr_i_p using decoder 109 |
| 2663 | // 5752: } |
| 2664 | 2, 8, // 5756: case 0x2: { |
| 2665 | OPC_CheckField, 13, 1, 0, // 5758: check Inst[13] == 0x0 |
| 2666 | OPC_Decode, 195, 17, 111, // 5762: decode to S2_lsr_i_vw using decoder 111 |
| 2667 | // 5762: } |
| 2668 | 4, 8, // 5766: case 0x4: { |
| 2669 | OPC_CheckField, 12, 2, 0, // 5768: check Inst[13:12] == 0x0 |
| 2670 | OPC_Decode, 194, 17, 110, // 5772: decode to S2_lsr_i_vh using decoder 110 |
| 2671 | // 5772: } |
| 2672 | 7, 0, // 5776: case 0x7: { |
| 2673 | OPC_CheckField, 8, 6, 0, // 5778: check Inst[13:8] == 0x0 |
| 2674 | OPC_Decode, 129, 10, 112, // 5782: decode to F2_conv_df2ud using decoder 112 |
| 2675 | // 5782: } |
| 2676 | // 5782: } // switch Inst[23:21] |
| 2677 | // 5782: } |
| 2678 | 2, 39, // 5786: case 0x2: { |
| 2679 | OPC_SwitchField, 21, 3, // 5788: switch Inst[23:21] { |
| 2680 | 0, 4, // 5791: case 0x0: { |
| 2681 | OPC_Decode, 211, 16, 109, // 5793: decode to S2_asl_i_p using decoder 109 |
| 2682 | // 5793: } |
| 2683 | 2, 8, // 5797: case 0x2: { |
| 2684 | OPC_CheckField, 13, 1, 0, // 5799: check Inst[13] == 0x0 |
| 2685 | OPC_Decode, 225, 16, 111, // 5803: decode to S2_asl_i_vw using decoder 111 |
| 2686 | // 5803: } |
| 2687 | 4, 8, // 5807: case 0x4: { |
| 2688 | OPC_CheckField, 12, 2, 0, // 5809: check Inst[13:12] == 0x0 |
| 2689 | OPC_Decode, 224, 16, 110, // 5813: decode to S2_asl_i_vh using decoder 110 |
| 2690 | // 5813: } |
| 2691 | 7, 0, // 5817: case 0x7: { |
| 2692 | OPC_CheckField, 8, 6, 0, // 5819: check Inst[13:8] == 0x0 |
| 2693 | OPC_Decode, 144, 10, 112, // 5823: decode to F2_conv_ud2df using decoder 112 |
| 2694 | // 5823: } |
| 2695 | // 5823: } // switch Inst[23:21] |
| 2696 | // 5823: } |
| 2697 | 3, 21, // 5827: case 0x3: { |
| 2698 | OPC_SwitchField, 21, 3, // 5829: switch Inst[23:21] { |
| 2699 | 0, 6, // 5832: case 0x0: { |
| 2700 | OPC_CheckPredicate, 1, // 5834: check predicate 1 |
| 2701 | OPC_Decode, 136, 20, 109, // 5836: decode to S6_rol_i_p using decoder 109 |
| 2702 | // 5836: } |
| 2703 | 7, 0, // 5840: case 0x7: { |
| 2704 | OPC_CheckField, 8, 6, 0, // 5842: check Inst[13:8] == 0x0 |
| 2705 | OPC_Decode, 252, 9, 112, // 5846: decode to F2_conv_d2df using decoder 112 |
| 2706 | // 5846: } |
| 2707 | // 5846: } // switch Inst[23:21] |
| 2708 | // 5846: } |
| 2709 | 4, 43, // 5850: case 0x4: { |
| 2710 | OPC_SwitchField, 21, 3, // 5852: switch Inst[23:21] { |
| 2711 | 0, 8, // 5855: case 0x0: { |
| 2712 | OPC_CheckField, 8, 6, 0, // 5857: check Inst[13:8] == 0x0 |
| 2713 | OPC_Decode, 217, 18, 112, // 5861: decode to S2_vsathub_nopack using decoder 112 |
| 2714 | // 5861: } |
| 2715 | 2, 8, // 5865: case 0x2: { |
| 2716 | OPC_CheckField, 8, 6, 0, // 5867: check Inst[13:8] == 0x0 |
| 2717 | OPC_Decode, 148, 8, 112, // 5871: decode to A2_vabsh using decoder 112 |
| 2718 | // 5871: } |
| 2719 | 4, 8, // 5875: case 0x4: { |
| 2720 | OPC_CheckField, 8, 6, 0, // 5877: check Inst[13:8] == 0x0 |
| 2721 | OPC_Decode, 207, 7, 112, // 5881: decode to A2_notp using decoder 112 |
| 2722 | // 5881: } |
| 2723 | 6, 0, // 5885: case 0x6: { |
| 2724 | OPC_CheckField, 8, 6, 0, // 5887: check Inst[13:8] == 0x0 |
| 2725 | OPC_Decode, 158, 17, 112, // 5891: decode to S2_deinterleave using decoder 112 |
| 2726 | // 5891: } |
| 2727 | // 5891: } // switch Inst[23:21] |
| 2728 | // 5891: } |
| 2729 | 5, 43, // 5895: case 0x5: { |
| 2730 | OPC_SwitchField, 21, 3, // 5897: switch Inst[23:21] { |
| 2731 | 0, 8, // 5900: case 0x0: { |
| 2732 | OPC_CheckField, 8, 6, 0, // 5902: check Inst[13:8] == 0x0 |
| 2733 | OPC_Decode, 221, 18, 112, // 5906: decode to S2_vsatwuh_nopack using decoder 112 |
| 2734 | // 5906: } |
| 2735 | 2, 8, // 5910: case 0x2: { |
| 2736 | OPC_CheckField, 8, 6, 0, // 5912: check Inst[13:8] == 0x0 |
| 2737 | OPC_Decode, 149, 8, 112, // 5916: decode to A2_vabshsat using decoder 112 |
| 2738 | // 5916: } |
| 2739 | 4, 8, // 5920: case 0x4: { |
| 2740 | OPC_CheckField, 8, 6, 0, // 5922: check Inst[13:8] == 0x0 |
| 2741 | OPC_Decode, 204, 7, 112, // 5926: decode to A2_negp using decoder 112 |
| 2742 | // 5926: } |
| 2743 | 6, 0, // 5930: case 0x6: { |
| 2744 | OPC_CheckField, 8, 6, 0, // 5932: check Inst[13:8] == 0x0 |
| 2745 | OPC_Decode, 167, 17, 112, // 5936: decode to S2_interleave using decoder 112 |
| 2746 | // 5936: } |
| 2747 | // 5936: } // switch Inst[23:21] |
| 2748 | // 5936: } |
| 2749 | 6, 53, // 5940: case 0x6: { |
| 2750 | OPC_SwitchField, 21, 3, // 5942: switch Inst[23:21] { |
| 2751 | 0, 8, // 5945: case 0x0: { |
| 2752 | OPC_CheckField, 8, 6, 0, // 5947: check Inst[13:8] == 0x0 |
| 2753 | OPC_Decode, 219, 18, 112, // 5951: decode to S2_vsatwh_nopack using decoder 112 |
| 2754 | // 5951: } |
| 2755 | 2, 8, // 5955: case 0x2: { |
| 2756 | OPC_CheckField, 8, 6, 0, // 5957: check Inst[13:8] == 0x0 |
| 2757 | OPC_Decode, 150, 8, 112, // 5961: decode to A2_vabsw using decoder 112 |
| 2758 | // 5961: } |
| 2759 | 4, 8, // 5965: case 0x4: { |
| 2760 | OPC_CheckField, 8, 6, 0, // 5967: check Inst[13:8] == 0x0 |
| 2761 | OPC_Decode, 164, 7, 112, // 5971: decode to A2_absp using decoder 112 |
| 2762 | // 5971: } |
| 2763 | 6, 8, // 5975: case 0x6: { |
| 2764 | OPC_CheckField, 8, 6, 0, // 5977: check Inst[13:8] == 0x0 |
| 2765 | OPC_Decode, 143, 17, 112, // 5981: decode to S2_brevp using decoder 112 |
| 2766 | // 5981: } |
| 2767 | 7, 0, // 5985: case 0x7: { |
| 2768 | OPC_CheckField, 8, 6, 0, // 5987: check Inst[13:8] == 0x0 |
| 2769 | OPC_Decode, 255, 9, 112, // 5991: decode to F2_conv_df2d_chop using decoder 112 |
| 2770 | // 5991: } |
| 2771 | // 5991: } // switch Inst[23:21] |
| 2772 | // 5991: } |
| 2773 | 7, 0, // 5995: case 0x7: { |
| 2774 | OPC_SwitchField, 21, 3, // 5997: switch Inst[23:21] { |
| 2775 | 0, 8, // 6000: case 0x0: { |
| 2776 | OPC_CheckField, 8, 6, 0, // 6002: check Inst[13:8] == 0x0 |
| 2777 | OPC_Decode, 215, 18, 112, // 6006: decode to S2_vsathb_nopack using decoder 112 |
| 2778 | // 6006: } |
| 2779 | 2, 8, // 6010: case 0x2: { |
| 2780 | OPC_CheckField, 8, 6, 0, // 6012: check Inst[13:8] == 0x0 |
| 2781 | OPC_Decode, 151, 8, 112, // 6016: decode to A2_vabswsat using decoder 112 |
| 2782 | // 6016: } |
| 2783 | 4, 8, // 6020: case 0x4: { |
| 2784 | OPC_CheckField, 8, 6, 0, // 6022: check Inst[13:8] == 0x0 |
| 2785 | OPC_Decode, 179, 8, 112, // 6026: decode to A2_vconj using decoder 112 |
| 2786 | // 6026: } |
| 2787 | 6, 4, // 6030: case 0x6: { |
| 2788 | OPC_Decode, 245, 16, 109, // 6032: decode to S2_asr_i_p_rnd using decoder 109 |
| 2789 | // 6032: } |
| 2790 | 7, 0, // 6036: case 0x7: { |
| 2791 | OPC_CheckField, 8, 6, 0, // 6038: check Inst[13:8] == 0x0 |
| 2792 | OPC_Decode, 130, 10, 112, // 6042: decode to F2_conv_df2ud_chop using decoder 112 |
| 2793 | // 6042: } |
| 2794 | // 6042: } // switch Inst[23:21] |
| 2795 | // 6042: } |
| 2796 | // 6042: } // switch Inst[7:5] |
| 2797 | // 6042: } |
| 2798 | 1, 4, // 6046: case 0x1: { |
| 2799 | OPC_Decode, 161, 17, 113, // 6048: decode to S2_extractup using decoder 113 |
| 2800 | // 6048: } |
| 2801 | 2, 167, 1, // 6052: case 0x2: { |
| 2802 | OPC_SwitchField, 5, 3, // 6055: switch Inst[7:5] { |
| 2803 | 0, 15, // 6058: case 0x0: { |
| 2804 | OPC_SwitchField, 21, 3, // 6060: switch Inst[23:21] { |
| 2805 | 0, 4, // 6063: case 0x0: { |
| 2806 | OPC_Decode, 243, 16, 114, // 6065: decode to S2_asr_i_p_nac using decoder 114 |
| 2807 | // 6065: } |
| 2808 | 2, 0, // 6069: case 0x2: { |
| 2809 | OPC_Decode, 242, 16, 114, // 6071: decode to S2_asr_i_p_and using decoder 114 |
| 2810 | // 6071: } |
| 2811 | // 6071: } // switch Inst[23:21] |
| 2812 | // 6071: } |
| 2813 | 1, 21, // 6075: case 0x1: { |
| 2814 | OPC_SwitchField, 21, 3, // 6077: switch Inst[23:21] { |
| 2815 | 0, 4, // 6080: case 0x0: { |
| 2816 | OPC_Decode, 185, 17, 114, // 6082: decode to S2_lsr_i_p_nac using decoder 114 |
| 2817 | // 6082: } |
| 2818 | 2, 4, // 6086: case 0x2: { |
| 2819 | OPC_Decode, 184, 17, 114, // 6088: decode to S2_lsr_i_p_and using decoder 114 |
| 2820 | // 6088: } |
| 2821 | 4, 0, // 6092: case 0x4: { |
| 2822 | OPC_Decode, 187, 17, 114, // 6094: decode to S2_lsr_i_p_xacc using decoder 114 |
| 2823 | // 6094: } |
| 2824 | // 6094: } // switch Inst[23:21] |
| 2825 | // 6094: } |
| 2826 | 2, 21, // 6098: case 0x2: { |
| 2827 | OPC_SwitchField, 21, 3, // 6100: switch Inst[23:21] { |
| 2828 | 0, 4, // 6103: case 0x0: { |
| 2829 | OPC_Decode, 214, 16, 114, // 6105: decode to S2_asl_i_p_nac using decoder 114 |
| 2830 | // 6105: } |
| 2831 | 2, 4, // 6109: case 0x2: { |
| 2832 | OPC_Decode, 213, 16, 114, // 6111: decode to S2_asl_i_p_and using decoder 114 |
| 2833 | // 6111: } |
| 2834 | 4, 0, // 6115: case 0x4: { |
| 2835 | OPC_Decode, 216, 16, 114, // 6117: decode to S2_asl_i_p_xacc using decoder 114 |
| 2836 | // 6117: } |
| 2837 | // 6117: } // switch Inst[23:21] |
| 2838 | // 6117: } |
| 2839 | 3, 27, // 6121: case 0x3: { |
| 2840 | OPC_SwitchField, 21, 3, // 6123: switch Inst[23:21] { |
| 2841 | 0, 6, // 6126: case 0x0: { |
| 2842 | OPC_CheckPredicate, 1, // 6128: check predicate 1 |
| 2843 | OPC_Decode, 139, 20, 114, // 6130: decode to S6_rol_i_p_nac using decoder 114 |
| 2844 | // 6130: } |
| 2845 | 2, 6, // 6134: case 0x2: { |
| 2846 | OPC_CheckPredicate, 1, // 6136: check predicate 1 |
| 2847 | OPC_Decode, 138, 20, 114, // 6138: decode to S6_rol_i_p_and using decoder 114 |
| 2848 | // 6138: } |
| 2849 | 4, 0, // 6142: case 0x4: { |
| 2850 | OPC_CheckPredicate, 1, // 6144: check predicate 1 |
| 2851 | OPC_Decode, 141, 20, 114, // 6146: decode to S6_rol_i_p_xacc using decoder 114 |
| 2852 | // 6146: } |
| 2853 | // 6146: } // switch Inst[23:21] |
| 2854 | // 6146: } |
| 2855 | 4, 15, // 6150: case 0x4: { |
| 2856 | OPC_SwitchField, 21, 3, // 6152: switch Inst[23:21] { |
| 2857 | 0, 4, // 6155: case 0x0: { |
| 2858 | OPC_Decode, 241, 16, 114, // 6157: decode to S2_asr_i_p_acc using decoder 114 |
| 2859 | // 6157: } |
| 2860 | 2, 0, // 6161: case 0x2: { |
| 2861 | OPC_Decode, 244, 16, 114, // 6163: decode to S2_asr_i_p_or using decoder 114 |
| 2862 | // 6163: } |
| 2863 | // 6163: } // switch Inst[23:21] |
| 2864 | // 6163: } |
| 2865 | 5, 15, // 6167: case 0x5: { |
| 2866 | OPC_SwitchField, 21, 3, // 6169: switch Inst[23:21] { |
| 2867 | 0, 4, // 6172: case 0x0: { |
| 2868 | OPC_Decode, 183, 17, 114, // 6174: decode to S2_lsr_i_p_acc using decoder 114 |
| 2869 | // 6174: } |
| 2870 | 2, 0, // 6178: case 0x2: { |
| 2871 | OPC_Decode, 186, 17, 114, // 6180: decode to S2_lsr_i_p_or using decoder 114 |
| 2872 | // 6180: } |
| 2873 | // 6180: } // switch Inst[23:21] |
| 2874 | // 6180: } |
| 2875 | 6, 15, // 6184: case 0x6: { |
| 2876 | OPC_SwitchField, 21, 3, // 6186: switch Inst[23:21] { |
| 2877 | 0, 4, // 6189: case 0x0: { |
| 2878 | OPC_Decode, 212, 16, 114, // 6191: decode to S2_asl_i_p_acc using decoder 114 |
| 2879 | // 6191: } |
| 2880 | 2, 0, // 6195: case 0x2: { |
| 2881 | OPC_Decode, 215, 16, 114, // 6197: decode to S2_asl_i_p_or using decoder 114 |
| 2882 | // 6197: } |
| 2883 | // 6197: } // switch Inst[23:21] |
| 2884 | // 6197: } |
| 2885 | 7, 0, // 6201: case 0x7: { |
| 2886 | OPC_SwitchField, 21, 3, // 6203: switch Inst[23:21] { |
| 2887 | 0, 6, // 6206: case 0x0: { |
| 2888 | OPC_CheckPredicate, 1, // 6208: check predicate 1 |
| 2889 | OPC_Decode, 137, 20, 114, // 6210: decode to S6_rol_i_p_acc using decoder 114 |
| 2890 | // 6210: } |
| 2891 | 2, 0, // 6214: case 0x2: { |
| 2892 | OPC_CheckPredicate, 1, // 6216: check predicate 1 |
| 2893 | OPC_Decode, 140, 20, 114, // 6218: decode to S6_rol_i_p_or using decoder 114 |
| 2894 | // 6218: } |
| 2895 | // 6218: } // switch Inst[23:21] |
| 2896 | // 6218: } |
| 2897 | // 6218: } // switch Inst[7:5] |
| 2898 | // 6218: } |
| 2899 | 3, 4, // 6222: case 0x3: { |
| 2900 | OPC_Decode, 165, 17, 115, // 6224: decode to S2_insertp using decoder 115 |
| 2901 | // 6224: } |
| 2902 | 4, 121, // 6228: case 0x4: { |
| 2903 | OPC_SwitchField, 5, 9, // 6230: switch Inst[13:5] { |
| 2904 | 0, 21, // 6233: case 0x0: { |
| 2905 | OPC_SwitchField, 21, 3, // 6235: switch Inst[23:21] { |
| 2906 | 0, 4, // 6238: case 0x0: { |
| 2907 | OPC_Decode, 226, 18, 86, // 6240: decode to S2_vsxtbh using decoder 86 |
| 2908 | // 6240: } |
| 2909 | 2, 4, // 6244: case 0x2: { |
| 2910 | OPC_Decode, 141, 8, 86, // 6246: decode to A2_sxtw using decoder 86 |
| 2911 | // 6246: } |
| 2912 | 4, 0, // 6250: case 0x4: { |
| 2913 | OPC_Decode, 137, 10, 86, // 6252: decode to F2_conv_sf2df using decoder 86 |
| 2914 | // 6252: } |
| 2915 | // 6252: } // switch Inst[23:21] |
| 2916 | // 6252: } |
| 2917 | 1, 8, // 6256: case 0x1: { |
| 2918 | OPC_CheckField, 21, 3, 4, // 6258: check Inst[23:21] == 0x4 |
| 2919 | OPC_Decode, 146, 10, 86, // 6262: decode to F2_conv_uw2df using decoder 86 |
| 2920 | // 6262: } |
| 2921 | 2, 21, // 6266: case 0x2: { |
| 2922 | OPC_SwitchField, 21, 3, // 6268: switch Inst[23:21] { |
| 2923 | 0, 4, // 6271: case 0x0: { |
| 2924 | OPC_Decode, 232, 18, 86, // 6273: decode to S2_vzxtbh using decoder 86 |
| 2925 | // 6273: } |
| 2926 | 2, 4, // 6277: case 0x2: { |
| 2927 | OPC_Decode, 223, 18, 86, // 6279: decode to S2_vsplatrh using decoder 86 |
| 2928 | // 6279: } |
| 2929 | 4, 0, // 6283: case 0x4: { |
| 2930 | OPC_Decode, 148, 10, 86, // 6285: decode to F2_conv_w2df using decoder 86 |
| 2931 | // 6285: } |
| 2932 | // 6285: } // switch Inst[23:21] |
| 2933 | // 6285: } |
| 2934 | 3, 8, // 6289: case 0x3: { |
| 2935 | OPC_CheckField, 21, 3, 4, // 6291: check Inst[23:21] == 0x4 |
| 2936 | OPC_Decode, 138, 10, 86, // 6295: decode to F2_conv_sf2ud using decoder 86 |
| 2937 | // 6295: } |
| 2938 | 4, 23, // 6299: case 0x4: { |
| 2939 | OPC_SwitchField, 21, 3, // 6301: switch Inst[23:21] { |
| 2940 | 0, 4, // 6304: case 0x0: { |
| 2941 | OPC_Decode, 227, 18, 86, // 6306: decode to S2_vsxthw using decoder 86 |
| 2942 | // 6306: } |
| 2943 | 2, 6, // 6310: case 0x2: { |
| 2944 | OPC_CheckPredicate, 7, // 6312: check predicate 7 |
| 2945 | OPC_Decode, 148, 20, 86, // 6314: decode to S6_vsplatrbp using decoder 86 |
| 2946 | // 6314: } |
| 2947 | 4, 0, // 6318: case 0x4: { |
| 2948 | OPC_Decode, 135, 10, 86, // 6320: decode to F2_conv_sf2d using decoder 86 |
| 2949 | // 6320: } |
| 2950 | // 6320: } // switch Inst[23:21] |
| 2951 | // 6320: } |
| 2952 | 5, 8, // 6324: case 0x5: { |
| 2953 | OPC_CheckField, 21, 3, 4, // 6326: check Inst[23:21] == 0x4 |
| 2954 | OPC_Decode, 139, 10, 86, // 6330: decode to F2_conv_sf2ud_chop using decoder 86 |
| 2955 | // 6330: } |
| 2956 | 6, 0, // 6334: case 0x6: { |
| 2957 | OPC_SwitchField, 21, 3, // 6336: switch Inst[23:21] { |
| 2958 | 0, 4, // 6339: case 0x0: { |
| 2959 | OPC_Decode, 233, 18, 86, // 6341: decode to S2_vzxthw using decoder 86 |
| 2960 | // 6341: } |
| 2961 | 4, 0, // 6345: case 0x4: { |
| 2962 | OPC_Decode, 136, 10, 86, // 6347: decode to F2_conv_sf2d_chop using decoder 86 |
| 2963 | // 6347: } |
| 2964 | // 6347: } // switch Inst[23:21] |
| 2965 | // 6347: } |
| 2966 | // 6347: } // switch Inst[13:5] |
| 2967 | // 6347: } |
| 2968 | 5, 75, // 6351: case 0x5: { |
| 2969 | OPC_SwitchField, 21, 3, // 6353: switch Inst[23:21] { |
| 2970 | 0, 12, // 6356: case 0x0: { |
| 2971 | OPC_CheckField, 13, 1, 0, // 6358: check Inst[13] == 0x0 |
| 2972 | OPC_CheckField, 2, 6, 0, // 6362: check Inst[7:2] == 0x0 |
| 2973 | OPC_Decode, 205, 18, 116, // 6366: decode to S2_tstbit_i using decoder 116 |
| 2974 | // 6366: } |
| 2975 | 1, 12, // 6370: case 0x1: { |
| 2976 | OPC_CheckField, 13, 1, 0, // 6372: check Inst[13] == 0x0 |
| 2977 | OPC_CheckField, 2, 6, 0, // 6376: check Inst[7:2] == 0x0 |
| 2978 | OPC_Decode, 247, 18, 116, // 6380: decode to S4_ntstbit_i using decoder 116 |
| 2979 | // 6380: } |
| 2980 | 2, 8, // 6384: case 0x2: { |
| 2981 | OPC_CheckField, 2, 12, 0, // 6386: check Inst[13:2] == 0x0 |
| 2982 | OPC_Decode, 208, 9, 117, // 6390: decode to C2_tfrrp using decoder 117 |
| 2983 | // 6390: } |
| 2984 | 4, 8, // 6394: case 0x4: { |
| 2985 | OPC_CheckField, 2, 6, 0, // 6396: check Inst[7:2] == 0x0 |
| 2986 | OPC_Decode, 180, 9, 118, // 6400: decode to C2_bitsclri using decoder 118 |
| 2987 | // 6400: } |
| 2988 | 5, 8, // 6404: case 0x5: { |
| 2989 | OPC_CheckField, 2, 6, 0, // 6406: check Inst[7:2] == 0x0 |
| 2990 | OPC_Decode, 226, 9, 118, // 6410: decode to C4_nbitsclri using decoder 118 |
| 2991 | // 6410: } |
| 2992 | 7, 0, // 6414: case 0x7: { |
| 2993 | OPC_CheckField, 13, 1, 0, // 6416: check Inst[13] == 0x0 |
| 2994 | OPC_CheckField, 2, 6, 0, // 6420: check Inst[7:2] == 0x0 |
| 2995 | OPC_Decode, 166, 10, 116, // 6424: decode to F2_sfclass using decoder 116 |
| 2996 | // 6424: } |
| 2997 | // 6424: } // switch Inst[23:21] |
| 2998 | // 6424: } |
| 2999 | 6, 16, // 6428: case 0x6: { |
| 3000 | OPC_CheckField, 16, 8, 0, // 6430: check Inst[23:16] == 0x0 |
| 3001 | OPC_CheckField, 10, 4, 0, // 6434: check Inst[13:10] == 0x0 |
| 3002 | OPC_CheckField, 5, 3, 0, // 6438: check Inst[7:5] == 0x0 |
| 3003 | OPC_Decode, 199, 9, 119, // 6442: decode to C2_mask using decoder 119 |
| 3004 | // 6442: } |
| 3005 | 7, 27, // 6446: case 0x7: { |
| 3006 | OPC_SwitchField, 22, 2, // 6448: switch Inst[23:22] { |
| 3007 | 0, 4, // 6451: case 0x0: { |
| 3008 | OPC_Decode, 199, 18, 120, // 6453: decode to S2_tableidxb using decoder 120 |
| 3009 | // 6453: } |
| 3010 | 1, 4, // 6457: case 0x1: { |
| 3011 | OPC_Decode, 201, 18, 120, // 6459: decode to S2_tableidxh using decoder 120 |
| 3012 | // 6459: } |
| 3013 | 2, 4, // 6463: case 0x2: { |
| 3014 | OPC_Decode, 202, 18, 120, // 6465: decode to S2_tableidxw using decoder 120 |
| 3015 | // 6465: } |
| 3016 | 3, 0, // 6469: case 0x3: { |
| 3017 | OPC_Decode, 200, 18, 120, // 6471: decode to S2_tableidxd using decoder 120 |
| 3018 | // 6471: } |
| 3019 | // 6471: } // switch Inst[23:22] |
| 3020 | // 6471: } |
| 3021 | 8, 147, 2, // 6475: case 0x8: { |
| 3022 | OPC_SwitchField, 21, 3, // 6478: switch Inst[23:21] { |
| 3023 | 0, 33, // 6481: case 0x0: { |
| 3024 | OPC_SwitchField, 5, 9, // 6483: switch Inst[13:5] { |
| 3025 | 0, 4, // 6486: case 0x0: { |
| 3026 | OPC_Decode, 216, 18, 87, // 6488: decode to S2_vsathub using decoder 87 |
| 3027 | // 6488: } |
| 3028 | 1, 4, // 6492: case 0x1: { |
| 3029 | OPC_Decode, 128, 10, 87, // 6494: decode to F2_conv_df2sf using decoder 87 |
| 3030 | // 6494: } |
| 3031 | 2, 4, // 6498: case 0x2: { |
| 3032 | OPC_Decode, 218, 18, 87, // 6500: decode to S2_vsatwh using decoder 87 |
| 3033 | // 6500: } |
| 3034 | 4, 4, // 6504: case 0x4: { |
| 3035 | OPC_Decode, 220, 18, 87, // 6506: decode to S2_vsatwuh using decoder 87 |
| 3036 | // 6506: } |
| 3037 | 6, 0, // 6510: case 0x6: { |
| 3038 | OPC_Decode, 214, 18, 87, // 6512: decode to S2_vsathb using decoder 87 |
| 3039 | // 6512: } |
| 3040 | // 6512: } // switch Inst[13:5] |
| 3041 | // 6512: } |
| 3042 | 1, 8, // 6516: case 0x1: { |
| 3043 | OPC_CheckField, 5, 9, 1, // 6518: check Inst[13:5] == 0x1 |
| 3044 | OPC_Decode, 145, 10, 87, // 6522: decode to F2_conv_ud2sf using decoder 87 |
| 3045 | // 6522: } |
| 3046 | 2, 27, // 6526: case 0x2: { |
| 3047 | OPC_SwitchField, 5, 9, // 6528: switch Inst[13:5] { |
| 3048 | 0, 4, // 6531: case 0x0: { |
| 3049 | OPC_Decode, 151, 17, 87, // 6533: decode to S2_clbp using decoder 87 |
| 3050 | // 6533: } |
| 3051 | 1, 4, // 6537: case 0x1: { |
| 3052 | OPC_Decode, 253, 9, 87, // 6539: decode to F2_conv_d2sf using decoder 87 |
| 3053 | // 6539: } |
| 3054 | 2, 4, // 6543: case 0x2: { |
| 3055 | OPC_Decode, 146, 17, 87, // 6545: decode to S2_cl0p using decoder 87 |
| 3056 | // 6545: } |
| 3057 | 4, 0, // 6549: case 0x4: { |
| 3058 | OPC_Decode, 148, 17, 87, // 6551: decode to S2_cl1p using decoder 87 |
| 3059 | // 6551: } |
| 3060 | // 6551: } // switch Inst[13:5] |
| 3061 | // 6551: } |
| 3062 | 3, 59, // 6555: case 0x3: { |
| 3063 | OPC_SwitchField, 5, 3, // 6557: switch Inst[7:5] { |
| 3064 | 0, 8, // 6560: case 0x0: { |
| 3065 | OPC_CheckField, 8, 6, 0, // 6562: check Inst[13:8] == 0x0 |
| 3066 | OPC_Decode, 241, 18, 87, // 6566: decode to S4_clbpnorm using decoder 87 |
| 3067 | // 6566: } |
| 3068 | 1, 8, // 6570: case 0x1: { |
| 3069 | OPC_CheckField, 8, 6, 0, // 6572: check Inst[13:8] == 0x0 |
| 3070 | OPC_Decode, 131, 10, 87, // 6576: decode to F2_conv_df2uw using decoder 87 |
| 3071 | // 6576: } |
| 3072 | 2, 4, // 6580: case 0x2: { |
| 3073 | OPC_Decode, 240, 18, 121, // 6582: decode to S4_clbpaddi using decoder 121 |
| 3074 | // 6582: } |
| 3075 | 3, 8, // 6586: case 0x3: { |
| 3076 | OPC_CheckField, 8, 6, 0, // 6588: check Inst[13:8] == 0x0 |
| 3077 | OPC_Decode, 134, 20, 87, // 6592: decode to S5_popcountp using decoder 87 |
| 3078 | // 6592: } |
| 3079 | 4, 8, // 6596: case 0x4: { |
| 3080 | OPC_CheckField, 12, 2, 0, // 6598: check Inst[13:12] == 0x0 |
| 3081 | OPC_Decode, 132, 20, 122, // 6602: decode to S5_asrhub_rnd_sat using decoder 122 |
| 3082 | // 6602: } |
| 3083 | 5, 0, // 6606: case 0x5: { |
| 3084 | OPC_CheckField, 12, 2, 0, // 6608: check Inst[13:12] == 0x0 |
| 3085 | OPC_Decode, 133, 20, 122, // 6612: decode to S5_asrhub_sat using decoder 122 |
| 3086 | // 6612: } |
| 3087 | // 6612: } // switch Inst[7:5] |
| 3088 | // 6612: } |
| 3089 | 4, 33, // 6616: case 0x4: { |
| 3090 | OPC_SwitchField, 5, 9, // 6618: switch Inst[13:5] { |
| 3091 | 0, 4, // 6621: case 0x0: { |
| 3092 | OPC_Decode, 230, 18, 87, // 6623: decode to S2_vtrunohb using decoder 87 |
| 3093 | // 6623: } |
| 3094 | 1, 4, // 6627: case 0x1: { |
| 3095 | OPC_Decode, 133, 10, 87, // 6629: decode to F2_conv_df2w using decoder 87 |
| 3096 | // 6629: } |
| 3097 | 2, 4, // 6633: case 0x2: { |
| 3098 | OPC_Decode, 228, 18, 87, // 6635: decode to S2_vtrunehb using decoder 87 |
| 3099 | // 6635: } |
| 3100 | 4, 4, // 6639: case 0x4: { |
| 3101 | OPC_Decode, 212, 18, 87, // 6641: decode to S2_vrndpackwh using decoder 87 |
| 3102 | // 6641: } |
| 3103 | 6, 0, // 6645: case 0x6: { |
| 3104 | OPC_Decode, 213, 18, 87, // 6647: decode to S2_vrndpackwhs using decoder 87 |
| 3105 | // 6647: } |
| 3106 | // 6647: } // switch Inst[13:5] |
| 3107 | // 6647: } |
| 3108 | 5, 8, // 6651: case 0x5: { |
| 3109 | OPC_CheckField, 5, 9, 1, // 6653: check Inst[13:5] == 0x1 |
| 3110 | OPC_Decode, 132, 10, 87, // 6657: decode to F2_conv_df2uw_chop using decoder 87 |
| 3111 | // 6657: } |
| 3112 | 6, 67, // 6661: case 0x6: { |
| 3113 | OPC_SwitchField, 5, 3, // 6663: switch Inst[7:5] { |
| 3114 | 0, 8, // 6666: case 0x0: { |
| 3115 | OPC_CheckField, 8, 6, 0, // 6668: check Inst[13:8] == 0x0 |
| 3116 | OPC_Decode, 236, 7, 87, // 6672: decode to A2_sat using decoder 87 |
| 3117 | // 6672: } |
| 3118 | 1, 8, // 6676: case 0x1: { |
| 3119 | OPC_CheckField, 8, 6, 0, // 6678: check Inst[13:8] == 0x0 |
| 3120 | OPC_Decode, 235, 7, 87, // 6682: decode to A2_roundsat using decoder 87 |
| 3121 | // 6682: } |
| 3122 | 2, 8, // 6686: case 0x2: { |
| 3123 | OPC_CheckField, 13, 1, 0, // 6688: check Inst[13] == 0x0 |
| 3124 | OPC_Decode, 252, 16, 123, // 6692: decode to S2_asr_i_svw_trun using decoder 123 |
| 3125 | // 6692: } |
| 3126 | 4, 8, // 6696: case 0x4: { |
| 3127 | OPC_CheckField, 13, 1, 0, // 6698: check Inst[13] == 0x0 |
| 3128 | OPC_Decode, 216, 8, 124, // 6702: decode to A4_bitspliti using decoder 124 |
| 3129 | // 6702: } |
| 3130 | 5, 10, // 6706: case 0x5: { |
| 3131 | OPC_CheckPredicate, 8, // 6708: check predicate 8 |
| 3132 | OPC_CheckField, 13, 1, 0, // 6710: check Inst[13] == 0x0 |
| 3133 | OPC_Decode, 171, 9, 125, // 6714: decode to A7_clip using decoder 125 |
| 3134 | // 6714: } |
| 3135 | 6, 0, // 6718: case 0x6: { |
| 3136 | OPC_CheckPredicate, 8, // 6720: check predicate 8 |
| 3137 | OPC_CheckField, 13, 1, 0, // 6722: check Inst[13] == 0x0 |
| 3138 | OPC_Decode, 174, 9, 111, // 6726: decode to A7_vclip using decoder 111 |
| 3139 | // 6726: } |
| 3140 | // 6726: } // switch Inst[7:5] |
| 3141 | // 6726: } |
| 3142 | 7, 0, // 6730: case 0x7: { |
| 3143 | OPC_SwitchField, 5, 9, // 6732: switch Inst[13:5] { |
| 3144 | 1, 4, // 6735: case 0x1: { |
| 3145 | OPC_Decode, 134, 10, 87, // 6737: decode to F2_conv_df2w_chop using decoder 87 |
| 3146 | // 6737: } |
| 3147 | 2, 4, // 6741: case 0x2: { |
| 3148 | OPC_Decode, 155, 17, 87, // 6743: decode to S2_ct0p using decoder 87 |
| 3149 | // 6743: } |
| 3150 | 4, 0, // 6747: case 0x4: { |
| 3151 | OPC_Decode, 157, 17, 87, // 6749: decode to S2_ct1p using decoder 87 |
| 3152 | // 6749: } |
| 3153 | // 6749: } // switch Inst[13:5] |
| 3154 | // 6749: } |
| 3155 | // 6749: } // switch Inst[23:21] |
| 3156 | // 6749: } |
| 3157 | 9, 27, // 6753: case 0x9: { |
| 3158 | OPC_SwitchField, 18, 6, // 6755: switch Inst[23:18] { |
| 3159 | 0, 12, // 6758: case 0x0: { |
| 3160 | OPC_CheckField, 10, 4, 0, // 6760: check Inst[13:10] == 0x0 |
| 3161 | OPC_CheckField, 5, 3, 0, // 6764: check Inst[7:5] == 0x0 |
| 3162 | OPC_Decode, 209, 9, 126, // 6768: decode to C2_vitpack using decoder 126 |
| 3163 | // 6768: } |
| 3164 | 16, 0, // 6772: case 0x10: { |
| 3165 | OPC_CheckField, 5, 9, 0, // 6774: check Inst[13:5] == 0x0 |
| 3166 | OPC_Decode, 207, 9, 127, // 6778: decode to C2_tfrpr using decoder 127 |
| 3167 | // 6778: } |
| 3168 | // 6778: } // switch Inst[23:18] |
| 3169 | // 6778: } |
| 3170 | 10, 4, // 6782: case 0xa: { |
| 3171 | OPC_Decode, 244, 18, 113, // 6784: decode to S4_extractp using decoder 113 |
| 3172 | // 6784: } |
| 3173 | 11, 78, // 6788: case 0xb: { |
| 3174 | OPC_SwitchField, 21, 3, // 6790: switch Inst[23:21] { |
| 3175 | 1, 8, // 6793: case 0x1: { |
| 3176 | OPC_CheckField, 5, 9, 0, // 6795: check Inst[13:5] == 0x0 |
| 3177 | OPC_Decode, 147, 10, 61, // 6799: decode to F2_conv_uw2sf using decoder 61 |
| 3178 | // 6799: } |
| 3179 | 2, 8, // 6803: case 0x2: { |
| 3180 | OPC_CheckField, 5, 9, 0, // 6805: check Inst[13:5] == 0x0 |
| 3181 | OPC_Decode, 149, 10, 61, // 6809: decode to F2_conv_w2sf using decoder 61 |
| 3182 | // 6809: } |
| 3183 | 3, 15, // 6813: case 0x3: { |
| 3184 | OPC_SwitchField, 5, 9, // 6815: switch Inst[13:5] { |
| 3185 | 0, 4, // 6818: case 0x0: { |
| 3186 | OPC_Decode, 140, 10, 61, // 6820: decode to F2_conv_sf2uw using decoder 61 |
| 3187 | // 6820: } |
| 3188 | 1, 0, // 6824: case 0x1: { |
| 3189 | OPC_Decode, 141, 10, 61, // 6826: decode to F2_conv_sf2uw_chop using decoder 61 |
| 3190 | // 6826: } |
| 3191 | // 6826: } // switch Inst[13:5] |
| 3192 | // 6826: } |
| 3193 | 4, 15, // 6830: case 0x4: { |
| 3194 | OPC_SwitchField, 5, 9, // 6832: switch Inst[13:5] { |
| 3195 | 0, 4, // 6835: case 0x0: { |
| 3196 | OPC_Decode, 142, 10, 61, // 6837: decode to F2_conv_sf2w using decoder 61 |
| 3197 | // 6837: } |
| 3198 | 1, 0, // 6841: case 0x1: { |
| 3199 | OPC_Decode, 143, 10, 61, // 6843: decode to F2_conv_sf2w_chop using decoder 61 |
| 3200 | // 6843: } |
| 3201 | // 6843: } // switch Inst[13:5] |
| 3202 | // 6843: } |
| 3203 | 5, 8, // 6847: case 0x5: { |
| 3204 | OPC_CheckField, 5, 9, 0, // 6849: check Inst[13:5] == 0x0 |
| 3205 | OPC_Decode, 173, 10, 61, // 6853: decode to F2_sffixupr using decoder 61 |
| 3206 | // 6853: } |
| 3207 | 7, 0, // 6857: case 0x7: { |
| 3208 | OPC_CheckField, 7, 7, 0, // 6859: check Inst[13:7] == 0x0 |
| 3209 | OPC_Decode, 181, 10, 128, 1, // 6863: decode to F2_sfinvsqrta using decoder 128 |
| 3210 | // 6863: } |
| 3211 | // 6863: } // switch Inst[23:21] |
| 3212 | // 6863: } |
| 3213 | 12, 231, 2, // 6868: case 0xc: { |
| 3214 | OPC_SwitchField, 5, 3, // 6871: switch Inst[7:5] { |
| 3215 | 0, 60, // 6874: case 0x0: { |
| 3216 | OPC_SwitchField, 21, 3, // 6876: switch Inst[23:21] { |
| 3217 | 0, 8, // 6879: case 0x0: { |
| 3218 | OPC_CheckField, 13, 1, 0, // 6881: check Inst[13] == 0x0 |
| 3219 | OPC_Decode, 246, 16, 125, // 6885: decode to S2_asr_i_r using decoder 125 |
| 3220 | // 6885: } |
| 3221 | 1, 5, // 6889: case 0x1: { |
| 3222 | OPC_Decode, 239, 18, 129, 1, // 6891: decode to S4_clbaddi using decoder 129 |
| 3223 | // 6891: } |
| 3224 | 2, 8, // 6896: case 0x2: { |
| 3225 | OPC_CheckField, 13, 1, 0, // 6898: check Inst[13] == 0x0 |
| 3226 | OPC_Decode, 251, 16, 125, // 6902: decode to S2_asr_i_r_rnd using decoder 125 |
| 3227 | // 6902: } |
| 3228 | 4, 8, // 6906: case 0x4: { |
| 3229 | OPC_CheckField, 8, 6, 0, // 6908: check Inst[13:8] == 0x0 |
| 3230 | OPC_Decode, 197, 18, 61, // 6912: decode to S2_svsathb using decoder 61 |
| 3231 | // 6912: } |
| 3232 | 6, 8, // 6916: case 0x6: { |
| 3233 | OPC_CheckField, 13, 1, 0, // 6918: check Inst[13] == 0x0 |
| 3234 | OPC_Decode, 132, 18, 125, // 6922: decode to S2_setbit_i using decoder 125 |
| 3235 | // 6922: } |
| 3236 | 7, 0, // 6926: case 0x7: { |
| 3237 | OPC_CheckField, 13, 1, 0, // 6928: check Inst[13] == 0x0 |
| 3238 | OPC_Decode, 234, 8, 125, // 6932: decode to A4_cround_ri using decoder 125 |
| 3239 | // 6932: } |
| 3240 | // 6932: } // switch Inst[23:21] |
| 3241 | // 6932: } |
| 3242 | 1, 23, // 6936: case 0x1: { |
| 3243 | OPC_SwitchField, 21, 3, // 6938: switch Inst[23:21] { |
| 3244 | 0, 8, // 6941: case 0x0: { |
| 3245 | OPC_CheckField, 13, 1, 0, // 6943: check Inst[13] == 0x0 |
| 3246 | OPC_Decode, 188, 17, 125, // 6947: decode to S2_lsr_i_r using decoder 125 |
| 3247 | // 6947: } |
| 3248 | 6, 0, // 6951: case 0x6: { |
| 3249 | OPC_CheckField, 13, 1, 0, // 6953: check Inst[13] == 0x0 |
| 3250 | OPC_Decode, 152, 17, 125, // 6957: decode to S2_clrbit_i using decoder 125 |
| 3251 | // 6957: } |
| 3252 | // 6957: } // switch Inst[23:21] |
| 3253 | // 6957: } |
| 3254 | 2, 51, // 6961: case 0x2: { |
| 3255 | OPC_SwitchField, 21, 3, // 6963: switch Inst[23:21] { |
| 3256 | 0, 8, // 6966: case 0x0: { |
| 3257 | OPC_CheckField, 13, 1, 0, // 6968: check Inst[13] == 0x0 |
| 3258 | OPC_Decode, 217, 16, 125, // 6972: decode to S2_asl_i_r using decoder 125 |
| 3259 | // 6972: } |
| 3260 | 2, 8, // 6976: case 0x2: { |
| 3261 | OPC_CheckField, 13, 1, 0, // 6978: check Inst[13] == 0x0 |
| 3262 | OPC_Decode, 222, 16, 125, // 6982: decode to S2_asl_i_r_sat using decoder 125 |
| 3263 | // 6982: } |
| 3264 | 4, 8, // 6986: case 0x4: { |
| 3265 | OPC_CheckField, 8, 6, 0, // 6988: check Inst[13:8] == 0x0 |
| 3266 | OPC_Decode, 198, 18, 61, // 6992: decode to S2_svsathub using decoder 61 |
| 3267 | // 6992: } |
| 3268 | 6, 8, // 6996: case 0x6: { |
| 3269 | OPC_CheckField, 13, 1, 0, // 6998: check Inst[13] == 0x0 |
| 3270 | OPC_Decode, 203, 18, 125, // 7002: decode to S2_togglebit_i using decoder 125 |
| 3271 | // 7002: } |
| 3272 | 7, 0, // 7006: case 0x7: { |
| 3273 | OPC_CheckPredicate, 8, // 7008: check predicate 8 |
| 3274 | OPC_Decode, 172, 9, 109, // 7010: decode to A7_croundd_ri using decoder 109 |
| 3275 | // 7010: } |
| 3276 | // 7010: } // switch Inst[23:21] |
| 3277 | // 7010: } |
| 3278 | 3, 14, // 7014: case 0x3: { |
| 3279 | OPC_CheckPredicate, 1, // 7016: check predicate 1 |
| 3280 | OPC_CheckField, 21, 3, 0, // 7018: check Inst[23:21] == 0x0 |
| 3281 | OPC_CheckField, 13, 1, 0, // 7022: check Inst[13] == 0x0 |
| 3282 | OPC_Decode, 142, 20, 125, // 7026: decode to S6_rol_i_r using decoder 125 |
| 3283 | // 7026: } |
| 3284 | 4, 53, // 7030: case 0x4: { |
| 3285 | OPC_SwitchField, 21, 3, // 7032: switch Inst[23:21] { |
| 3286 | 0, 8, // 7035: case 0x0: { |
| 3287 | OPC_CheckField, 8, 6, 0, // 7037: check Inst[13:8] == 0x0 |
| 3288 | OPC_Decode, 149, 17, 61, // 7041: decode to S2_clb using decoder 61 |
| 3289 | // 7041: } |
| 3290 | 2, 8, // 7045: case 0x2: { |
| 3291 | OPC_CheckField, 8, 6, 0, // 7047: check Inst[13:8] == 0x0 |
| 3292 | OPC_Decode, 154, 17, 61, // 7051: decode to S2_ct0 using decoder 61 |
| 3293 | // 7051: } |
| 3294 | 4, 8, // 7055: case 0x4: { |
| 3295 | OPC_CheckField, 8, 6, 0, // 7057: check Inst[13:8] == 0x0 |
| 3296 | OPC_Decode, 163, 7, 61, // 7061: decode to A2_abs using decoder 61 |
| 3297 | // 7061: } |
| 3298 | 6, 8, // 7065: case 0x6: { |
| 3299 | OPC_CheckField, 8, 6, 0, // 7067: check Inst[13:8] == 0x0 |
| 3300 | OPC_Decode, 238, 7, 61, // 7071: decode to A2_sath using decoder 61 |
| 3301 | // 7071: } |
| 3302 | 7, 0, // 7075: case 0x7: { |
| 3303 | OPC_CheckField, 13, 1, 0, // 7077: check Inst[13] == 0x0 |
| 3304 | OPC_Decode, 140, 9, 125, // 7081: decode to A4_round_ri using decoder 125 |
| 3305 | // 7081: } |
| 3306 | // 7081: } // switch Inst[23:21] |
| 3307 | // 7081: } |
| 3308 | 5, 43, // 7085: case 0x5: { |
| 3309 | OPC_SwitchField, 21, 3, // 7087: switch Inst[23:21] { |
| 3310 | 0, 8, // 7090: case 0x0: { |
| 3311 | OPC_CheckField, 8, 6, 0, // 7092: check Inst[13:8] == 0x0 |
| 3312 | OPC_Decode, 145, 17, 61, // 7096: decode to S2_cl0 using decoder 61 |
| 3313 | // 7096: } |
| 3314 | 2, 8, // 7100: case 0x2: { |
| 3315 | OPC_CheckField, 8, 6, 0, // 7102: check Inst[13:8] == 0x0 |
| 3316 | OPC_Decode, 156, 17, 61, // 7106: decode to S2_ct1 using decoder 61 |
| 3317 | // 7106: } |
| 3318 | 4, 8, // 7110: case 0x4: { |
| 3319 | OPC_CheckField, 8, 6, 0, // 7112: check Inst[13:8] == 0x0 |
| 3320 | OPC_Decode, 165, 7, 61, // 7116: decode to A2_abssat using decoder 61 |
| 3321 | // 7116: } |
| 3322 | 6, 0, // 7120: case 0x6: { |
| 3323 | OPC_CheckField, 8, 6, 0, // 7122: check Inst[13:8] == 0x0 |
| 3324 | OPC_Decode, 240, 7, 61, // 7126: decode to A2_satuh using decoder 61 |
| 3325 | // 7126: } |
| 3326 | // 7126: } // switch Inst[23:21] |
| 3327 | // 7126: } |
| 3328 | 6, 53, // 7130: case 0x6: { |
| 3329 | OPC_SwitchField, 21, 3, // 7132: switch Inst[23:21] { |
| 3330 | 0, 8, // 7135: case 0x0: { |
| 3331 | OPC_CheckField, 8, 6, 0, // 7137: check Inst[13:8] == 0x0 |
| 3332 | OPC_Decode, 147, 17, 61, // 7141: decode to S2_cl1 using decoder 61 |
| 3333 | // 7141: } |
| 3334 | 2, 8, // 7145: case 0x2: { |
| 3335 | OPC_CheckField, 8, 6, 0, // 7147: check Inst[13:8] == 0x0 |
| 3336 | OPC_Decode, 142, 17, 61, // 7151: decode to S2_brev using decoder 61 |
| 3337 | // 7151: } |
| 3338 | 4, 8, // 7155: case 0x4: { |
| 3339 | OPC_CheckField, 8, 6, 0, // 7157: check Inst[13:8] == 0x0 |
| 3340 | OPC_Decode, 205, 7, 61, // 7161: decode to A2_negsat using decoder 61 |
| 3341 | // 7161: } |
| 3342 | 6, 8, // 7165: case 0x6: { |
| 3343 | OPC_CheckField, 8, 6, 0, // 7167: check Inst[13:8] == 0x0 |
| 3344 | OPC_Decode, 239, 7, 61, // 7171: decode to A2_satub using decoder 61 |
| 3345 | // 7171: } |
| 3346 | 7, 0, // 7175: case 0x7: { |
| 3347 | OPC_CheckField, 13, 1, 0, // 7177: check Inst[13] == 0x0 |
| 3348 | OPC_Decode, 141, 9, 125, // 7181: decode to A4_round_ri_sat using decoder 125 |
| 3349 | // 7181: } |
| 3350 | // 7181: } // switch Inst[23:21] |
| 3351 | // 7181: } |
| 3352 | 7, 0, // 7185: case 0x7: { |
| 3353 | OPC_SwitchField, 21, 3, // 7187: switch Inst[23:21] { |
| 3354 | 0, 8, // 7190: case 0x0: { |
| 3355 | OPC_CheckField, 8, 6, 0, // 7192: check Inst[13:8] == 0x0 |
| 3356 | OPC_Decode, 150, 17, 61, // 7196: decode to S2_clbnorm using decoder 61 |
| 3357 | // 7196: } |
| 3358 | 2, 8, // 7200: case 0x2: { |
| 3359 | OPC_CheckField, 8, 6, 0, // 7202: check Inst[13:8] == 0x0 |
| 3360 | OPC_Decode, 222, 18, 61, // 7206: decode to S2_vsplatrb using decoder 61 |
| 3361 | // 7206: } |
| 3362 | 4, 8, // 7210: case 0x4: { |
| 3363 | OPC_CheckField, 8, 6, 0, // 7212: check Inst[13:8] == 0x0 |
| 3364 | OPC_Decode, 138, 8, 61, // 7216: decode to A2_swiz using decoder 61 |
| 3365 | // 7216: } |
| 3366 | 6, 0, // 7220: case 0x6: { |
| 3367 | OPC_CheckField, 8, 6, 0, // 7222: check Inst[13:8] == 0x0 |
| 3368 | OPC_Decode, 237, 7, 61, // 7226: decode to A2_satb using decoder 61 |
| 3369 | // 7226: } |
| 3370 | // 7226: } // switch Inst[23:21] |
| 3371 | // 7226: } |
| 3372 | // 7226: } // switch Inst[7:5] |
| 3373 | // 7226: } |
| 3374 | 13, 39, // 7230: case 0xd: { |
| 3375 | OPC_SwitchField, 13, 1, // 7232: switch Inst[13] { |
| 3376 | 0, 17, // 7235: case 0x0: { |
| 3377 | OPC_SwitchField, 23, 1, // 7237: switch Inst[23] { |
| 3378 | 0, 5, // 7240: case 0x0: { |
| 3379 | OPC_Decode, 159, 17, 130, 1, // 7242: decode to S2_extractu using decoder 130 |
| 3380 | // 7242: } |
| 3381 | 1, 0, // 7247: case 0x1: { |
| 3382 | OPC_Decode, 242, 18, 130, 1, // 7249: decode to S4_extract using decoder 130 |
| 3383 | // 7249: } |
| 3384 | // 7249: } // switch Inst[23] |
| 3385 | // 7249: } |
| 3386 | 1, 0, // 7254: case 0x1: { |
| 3387 | OPC_CheckPredicate, 4, // 7256: check predicate 4 |
| 3388 | OPC_CheckField, 23, 1, 0, // 7258: check Inst[23] == 0x0 |
| 3389 | OPC_CheckField, 16, 5, 0, // 7262: check Inst[20:16] == 0x0 |
| 3390 | OPC_Decode, 209, 17, 131, 1, // 7266: decode to S2_mask using decoder 131 |
| 3391 | // 7266: } |
| 3392 | // 7266: } // switch Inst[13] |
| 3393 | // 7266: } |
| 3394 | 14, 134, 2, // 7271: case 0xe: { |
| 3395 | OPC_SwitchField, 5, 3, // 7274: switch Inst[7:5] { |
| 3396 | 0, 25, // 7277: case 0x0: { |
| 3397 | OPC_SwitchField, 21, 3, // 7279: switch Inst[23:21] { |
| 3398 | 0, 9, // 7282: case 0x0: { |
| 3399 | OPC_CheckField, 13, 1, 0, // 7284: check Inst[13] == 0x0 |
| 3400 | OPC_Decode, 249, 16, 132, 1, // 7288: decode to S2_asr_i_r_nac using decoder 132 |
| 3401 | // 7288: } |
| 3402 | 2, 0, // 7293: case 0x2: { |
| 3403 | OPC_CheckField, 13, 1, 0, // 7295: check Inst[13] == 0x0 |
| 3404 | OPC_Decode, 248, 16, 132, 1, // 7299: decode to S2_asr_i_r_and using decoder 132 |
| 3405 | // 7299: } |
| 3406 | // 7299: } // switch Inst[23:21] |
| 3407 | // 7299: } |
| 3408 | 1, 36, // 7304: case 0x1: { |
| 3409 | OPC_SwitchField, 21, 3, // 7306: switch Inst[23:21] { |
| 3410 | 0, 9, // 7309: case 0x0: { |
| 3411 | OPC_CheckField, 13, 1, 0, // 7311: check Inst[13] == 0x0 |
| 3412 | OPC_Decode, 191, 17, 132, 1, // 7315: decode to S2_lsr_i_r_nac using decoder 132 |
| 3413 | // 7315: } |
| 3414 | 2, 9, // 7320: case 0x2: { |
| 3415 | OPC_CheckField, 13, 1, 0, // 7322: check Inst[13] == 0x0 |
| 3416 | OPC_Decode, 190, 17, 132, 1, // 7326: decode to S2_lsr_i_r_and using decoder 132 |
| 3417 | // 7326: } |
| 3418 | 4, 0, // 7331: case 0x4: { |
| 3419 | OPC_CheckField, 13, 1, 0, // 7333: check Inst[13] == 0x0 |
| 3420 | OPC_Decode, 193, 17, 132, 1, // 7337: decode to S2_lsr_i_r_xacc using decoder 132 |
| 3421 | // 7337: } |
| 3422 | // 7337: } // switch Inst[23:21] |
| 3423 | // 7337: } |
| 3424 | 2, 36, // 7342: case 0x2: { |
| 3425 | OPC_SwitchField, 21, 3, // 7344: switch Inst[23:21] { |
| 3426 | 0, 9, // 7347: case 0x0: { |
| 3427 | OPC_CheckField, 13, 1, 0, // 7349: check Inst[13] == 0x0 |
| 3428 | OPC_Decode, 220, 16, 132, 1, // 7353: decode to S2_asl_i_r_nac using decoder 132 |
| 3429 | // 7353: } |
| 3430 | 2, 9, // 7358: case 0x2: { |
| 3431 | OPC_CheckField, 13, 1, 0, // 7360: check Inst[13] == 0x0 |
| 3432 | OPC_Decode, 219, 16, 132, 1, // 7364: decode to S2_asl_i_r_and using decoder 132 |
| 3433 | // 7364: } |
| 3434 | 4, 0, // 7369: case 0x4: { |
| 3435 | OPC_CheckField, 13, 1, 0, // 7371: check Inst[13] == 0x0 |
| 3436 | OPC_Decode, 223, 16, 132, 1, // 7375: decode to S2_asl_i_r_xacc using decoder 132 |
| 3437 | // 7375: } |
| 3438 | // 7375: } // switch Inst[23:21] |
| 3439 | // 7375: } |
| 3440 | 3, 42, // 7380: case 0x3: { |
| 3441 | OPC_SwitchField, 21, 3, // 7382: switch Inst[23:21] { |
| 3442 | 0, 11, // 7385: case 0x0: { |
| 3443 | OPC_CheckPredicate, 1, // 7387: check predicate 1 |
| 3444 | OPC_CheckField, 13, 1, 0, // 7389: check Inst[13] == 0x0 |
| 3445 | OPC_Decode, 145, 20, 132, 1, // 7393: decode to S6_rol_i_r_nac using decoder 132 |
| 3446 | // 7393: } |
| 3447 | 2, 11, // 7398: case 0x2: { |
| 3448 | OPC_CheckPredicate, 1, // 7400: check predicate 1 |
| 3449 | OPC_CheckField, 13, 1, 0, // 7402: check Inst[13] == 0x0 |
| 3450 | OPC_Decode, 144, 20, 132, 1, // 7406: decode to S6_rol_i_r_and using decoder 132 |
| 3451 | // 7406: } |
| 3452 | 4, 0, // 7411: case 0x4: { |
| 3453 | OPC_CheckPredicate, 1, // 7413: check predicate 1 |
| 3454 | OPC_CheckField, 13, 1, 0, // 7415: check Inst[13] == 0x0 |
| 3455 | OPC_Decode, 147, 20, 132, 1, // 7419: decode to S6_rol_i_r_xacc using decoder 132 |
| 3456 | // 7419: } |
| 3457 | // 7419: } // switch Inst[23:21] |
| 3458 | // 7419: } |
| 3459 | 4, 25, // 7424: case 0x4: { |
| 3460 | OPC_SwitchField, 21, 3, // 7426: switch Inst[23:21] { |
| 3461 | 0, 9, // 7429: case 0x0: { |
| 3462 | OPC_CheckField, 13, 1, 0, // 7431: check Inst[13] == 0x0 |
| 3463 | OPC_Decode, 247, 16, 132, 1, // 7435: decode to S2_asr_i_r_acc using decoder 132 |
| 3464 | // 7435: } |
| 3465 | 2, 0, // 7440: case 0x2: { |
| 3466 | OPC_CheckField, 13, 1, 0, // 7442: check Inst[13] == 0x0 |
| 3467 | OPC_Decode, 250, 16, 132, 1, // 7446: decode to S2_asr_i_r_or using decoder 132 |
| 3468 | // 7446: } |
| 3469 | // 7446: } // switch Inst[23:21] |
| 3470 | // 7446: } |
| 3471 | 5, 25, // 7451: case 0x5: { |
| 3472 | OPC_SwitchField, 21, 3, // 7453: switch Inst[23:21] { |
| 3473 | 0, 9, // 7456: case 0x0: { |
| 3474 | OPC_CheckField, 13, 1, 0, // 7458: check Inst[13] == 0x0 |
| 3475 | OPC_Decode, 189, 17, 132, 1, // 7462: decode to S2_lsr_i_r_acc using decoder 132 |
| 3476 | // 7462: } |
| 3477 | 2, 0, // 7467: case 0x2: { |
| 3478 | OPC_CheckField, 13, 1, 0, // 7469: check Inst[13] == 0x0 |
| 3479 | OPC_Decode, 192, 17, 132, 1, // 7473: decode to S2_lsr_i_r_or using decoder 132 |
| 3480 | // 7473: } |
| 3481 | // 7473: } // switch Inst[23:21] |
| 3482 | // 7473: } |
| 3483 | 6, 25, // 7478: case 0x6: { |
| 3484 | OPC_SwitchField, 21, 3, // 7480: switch Inst[23:21] { |
| 3485 | 0, 9, // 7483: case 0x0: { |
| 3486 | OPC_CheckField, 13, 1, 0, // 7485: check Inst[13] == 0x0 |
| 3487 | OPC_Decode, 218, 16, 132, 1, // 7489: decode to S2_asl_i_r_acc using decoder 132 |
| 3488 | // 7489: } |
| 3489 | 2, 0, // 7494: case 0x2: { |
| 3490 | OPC_CheckField, 13, 1, 0, // 7496: check Inst[13] == 0x0 |
| 3491 | OPC_Decode, 221, 16, 132, 1, // 7500: decode to S2_asl_i_r_or using decoder 132 |
| 3492 | // 7500: } |
| 3493 | // 7500: } // switch Inst[23:21] |
| 3494 | // 7500: } |
| 3495 | 7, 0, // 7505: case 0x7: { |
| 3496 | OPC_SwitchField, 21, 3, // 7507: switch Inst[23:21] { |
| 3497 | 0, 11, // 7510: case 0x0: { |
| 3498 | OPC_CheckPredicate, 1, // 7512: check predicate 1 |
| 3499 | OPC_CheckField, 13, 1, 0, // 7514: check Inst[13] == 0x0 |
| 3500 | OPC_Decode, 143, 20, 132, 1, // 7518: decode to S6_rol_i_r_acc using decoder 132 |
| 3501 | // 7518: } |
| 3502 | 2, 0, // 7523: case 0x2: { |
| 3503 | OPC_CheckPredicate, 1, // 7525: check predicate 1 |
| 3504 | OPC_CheckField, 13, 1, 0, // 7527: check Inst[13] == 0x0 |
| 3505 | OPC_Decode, 146, 20, 132, 1, // 7531: decode to S6_rol_i_r_or using decoder 132 |
| 3506 | // 7531: } |
| 3507 | // 7531: } // switch Inst[23:21] |
| 3508 | // 7531: } |
| 3509 | // 7531: } // switch Inst[7:5] |
| 3510 | // 7531: } |
| 3511 | 15, 0, // 7536: case 0xf: { |
| 3512 | OPC_CheckField, 23, 1, 0, // 7538: check Inst[23] == 0x0 |
| 3513 | OPC_CheckField, 13, 1, 0, // 7542: check Inst[13] == 0x0 |
| 3514 | OPC_Decode, 163, 17, 133, 1, // 7546: decode to S2_insert using decoder 133 |
| 3515 | // 7546: } |
| 3516 | // 7546: } // switch Inst[27:24] |
| 3517 | // 7546: } |
| 3518 | 9, 147, 11, // 7551: case 0x9: { |
| 3519 | OPC_SwitchField, 21, 4, // 7554: switch Inst[24:21] { |
| 3520 | 0, 168, 1, // 7557: case 0x0: { |
| 3521 | OPC_SwitchField, 25, 3, // 7560: switch Inst[27:25] { |
| 3522 | 0, 8, // 7563: case 0x0: { |
| 3523 | OPC_CheckField, 5, 9, 0, // 7565: check Inst[13:5] == 0x0 |
| 3524 | OPC_Decode, 236, 11, 86, // 7569: decode to L2_deallocframe using decoder 86 |
| 3525 | // 7569: } |
| 3526 | 1, 61, // 7573: case 0x1: { |
| 3527 | OPC_SwitchField, 5, 3, // 7575: switch Inst[7:5] { |
| 3528 | 0, 43, // 7578: case 0x0: { |
| 3529 | OPC_SwitchField, 13, 1, // 7580: switch Inst[13] { |
| 3530 | 0, 31, // 7583: case 0x0: { |
| 3531 | OPC_SwitchField, 8, 5, // 7585: switch Inst[12:8] { |
| 3532 | 0, 4, // 7588: case 0x0: { |
| 3533 | OPC_Decode, 188, 12, 61, // 7590: decode to L2_loadw_locked using decoder 61 |
| 3534 | // 7590: } |
| 3535 | 8, 6, // 7594: case 0x8: { |
| 3536 | OPC_CheckPredicate, 9, // 7596: check predicate 9 |
| 3537 | OPC_Decode, 187, 12, 61, // 7598: decode to L2_loadw_aq using decoder 61 |
| 3538 | // 7598: } |
| 3539 | 16, 4, // 7602: case 0x10: { |
| 3540 | OPC_Decode, 140, 13, 86, // 7604: decode to L4_loadd_locked using decoder 86 |
| 3541 | // 7604: } |
| 3542 | 24, 0, // 7608: case 0x18: { |
| 3543 | OPC_CheckPredicate, 9, // 7610: check predicate 9 |
| 3544 | OPC_Decode, 139, 13, 86, // 7612: decode to L4_loadd_aq using decoder 86 |
| 3545 | // 7612: } |
| 3546 | // 7612: } // switch Inst[12:8] |
| 3547 | // 7612: } |
| 3548 | 1, 0, // 7616: case 0x1: { |
| 3549 | OPC_Decode, 159, 13, 134, 1, // 7618: decode to L4_loadw_phys using decoder 134 |
| 3550 | // 7618: } |
| 3551 | // 7618: } // switch Inst[13] |
| 3552 | // 7618: } |
| 3553 | 2, 0, // 7623: case 0x2: { |
| 3554 | OPC_CheckPredicate, 4, // 7625: check predicate 4 |
| 3555 | OPC_CheckField, 0, 5, 0, // 7627: check Inst[4:0] == 0x0 |
| 3556 | OPC_Decode, 221, 13, 135, 1, // 7631: decode to L6_memcpy using decoder 135 |
| 3557 | // 7631: } |
| 3558 | // 7631: } // switch Inst[7:5] |
| 3559 | // 7631: } |
| 3560 | 2, 9, // 7636: case 0x2: { |
| 3561 | OPC_CheckField, 11, 3, 0, // 7638: check Inst[13:11] == 0x0 |
| 3562 | OPC_Decode, 149, 26, 136, 1, // 7642: decode to Y2_dcfetchbo using decoder 136 |
| 3563 | // 7642: } |
| 3564 | 3, 0, // 7647: case 0x3: { |
| 3565 | OPC_SwitchField, 10, 4, // 7649: switch Inst[13:10] { |
| 3566 | 0, 8, // 7652: case 0x0: { |
| 3567 | OPC_CheckField, 5, 5, 0, // 7654: check Inst[9:5] == 0x0 |
| 3568 | OPC_Decode, 211, 13, 86, // 7658: decode to L4_return using decoder 86 |
| 3569 | // 7658: } |
| 3570 | 2, 9, // 7662: case 0x2: { |
| 3571 | OPC_CheckField, 5, 3, 0, // 7664: check Inst[7:5] == 0x0 |
| 3572 | OPC_Decode, 216, 13, 137, 1, // 7668: decode to L4_return_tnew_pnt using decoder 137 |
| 3573 | // 7668: } |
| 3574 | 4, 9, // 7673: case 0x4: { |
| 3575 | OPC_CheckField, 5, 3, 0, // 7675: check Inst[7:5] == 0x0 |
| 3576 | OPC_Decode, 215, 13, 137, 1, // 7679: decode to L4_return_t using decoder 137 |
| 3577 | // 7679: } |
| 3578 | 6, 9, // 7684: case 0x6: { |
| 3579 | OPC_CheckField, 5, 3, 0, // 7686: check Inst[7:5] == 0x0 |
| 3580 | OPC_Decode, 217, 13, 137, 1, // 7690: decode to L4_return_tnew_pt using decoder 137 |
| 3581 | // 7690: } |
| 3582 | 10, 9, // 7695: case 0xa: { |
| 3583 | OPC_CheckField, 5, 3, 0, // 7697: check Inst[7:5] == 0x0 |
| 3584 | OPC_Decode, 213, 13, 137, 1, // 7701: decode to L4_return_fnew_pnt using decoder 137 |
| 3585 | // 7701: } |
| 3586 | 12, 9, // 7706: case 0xc: { |
| 3587 | OPC_CheckField, 5, 3, 0, // 7708: check Inst[7:5] == 0x0 |
| 3588 | OPC_Decode, 212, 13, 137, 1, // 7712: decode to L4_return_f using decoder 137 |
| 3589 | // 7712: } |
| 3590 | 14, 0, // 7717: case 0xe: { |
| 3591 | OPC_CheckField, 5, 3, 0, // 7719: check Inst[7:5] == 0x0 |
| 3592 | OPC_Decode, 214, 13, 137, 1, // 7723: decode to L4_return_fnew_pt using decoder 137 |
| 3593 | // 7723: } |
| 3594 | // 7723: } // switch Inst[13:10] |
| 3595 | // 7723: } |
| 3596 | // 7723: } // switch Inst[27:25] |
| 3597 | // 7723: } |
| 3598 | 1, 71, // 7728: case 0x1: { |
| 3599 | OPC_SwitchField, 27, 1, // 7730: switch Inst[27] { |
| 3600 | 0, 5, // 7733: case 0x0: { |
| 3601 | OPC_Decode, 249, 11, 138, 1, // 7735: decode to L2_loadbsw2_io using decoder 138 |
| 3602 | // 7735: } |
| 3603 | 1, 0, // 7740: case 0x1: { |
| 3604 | OPC_SwitchField, 25, 2, // 7742: switch Inst[26:25] { |
| 3605 | 0, 21, // 7745: case 0x0: { |
| 3606 | OPC_SwitchField, 9, 4, // 7747: switch Inst[12:9] { |
| 3607 | 0, 5, // 7750: case 0x0: { |
| 3608 | OPC_Decode, 251, 11, 139, 1, // 7752: decode to L2_loadbsw2_pci using decoder 139 |
| 3609 | // 7752: } |
| 3610 | 1, 0, // 7757: case 0x1: { |
| 3611 | OPC_CheckField, 5, 4, 0, // 7759: check Inst[8:5] == 0x0 |
| 3612 | OPC_Decode, 252, 11, 140, 1, // 7763: decode to L2_loadbsw2_pcr using decoder 140 |
| 3613 | // 7763: } |
| 3614 | // 7763: } // switch Inst[12:9] |
| 3615 | // 7763: } |
| 3616 | 1, 9, // 7768: case 0x1: { |
| 3617 | OPC_CheckField, 9, 5, 0, // 7770: check Inst[13:9] == 0x0 |
| 3618 | OPC_Decode, 253, 11, 141, 1, // 7774: decode to L2_loadbsw2_pi using decoder 141 |
| 3619 | // 7774: } |
| 3620 | 2, 9, // 7779: case 0x2: { |
| 3621 | OPC_CheckField, 5, 8, 0, // 7781: check Inst[12:5] == 0x0 |
| 3622 | OPC_Decode, 254, 11, 140, 1, // 7785: decode to L2_loadbsw2_pr using decoder 140 |
| 3623 | // 7785: } |
| 3624 | 3, 0, // 7790: case 0x3: { |
| 3625 | OPC_CheckField, 5, 8, 0, // 7792: check Inst[12:5] == 0x0 |
| 3626 | OPC_Decode, 250, 11, 140, 1, // 7796: decode to L2_loadbsw2_pbr using decoder 140 |
| 3627 | // 7796: } |
| 3628 | // 7796: } // switch Inst[26:25] |
| 3629 | // 7796: } |
| 3630 | // 7796: } // switch Inst[27] |
| 3631 | // 7796: } |
| 3632 | 2, 71, // 7801: case 0x2: { |
| 3633 | OPC_SwitchField, 27, 1, // 7803: switch Inst[27] { |
| 3634 | 0, 5, // 7806: case 0x0: { |
| 3635 | OPC_Decode, 243, 11, 142, 1, // 7808: decode to L2_loadalignh_io using decoder 142 |
| 3636 | // 7808: } |
| 3637 | 1, 0, // 7813: case 0x1: { |
| 3638 | OPC_SwitchField, 25, 2, // 7815: switch Inst[26:25] { |
| 3639 | 0, 21, // 7818: case 0x0: { |
| 3640 | OPC_SwitchField, 9, 4, // 7820: switch Inst[12:9] { |
| 3641 | 0, 5, // 7823: case 0x0: { |
| 3642 | OPC_Decode, 245, 11, 143, 1, // 7825: decode to L2_loadalignh_pci using decoder 143 |
| 3643 | // 7825: } |
| 3644 | 1, 0, // 7830: case 0x1: { |
| 3645 | OPC_CheckField, 5, 4, 0, // 7832: check Inst[8:5] == 0x0 |
| 3646 | OPC_Decode, 246, 11, 144, 1, // 7836: decode to L2_loadalignh_pcr using decoder 144 |
| 3647 | // 7836: } |
| 3648 | // 7836: } // switch Inst[12:9] |
| 3649 | // 7836: } |
| 3650 | 1, 9, // 7841: case 0x1: { |
| 3651 | OPC_CheckField, 9, 5, 0, // 7843: check Inst[13:9] == 0x0 |
| 3652 | OPC_Decode, 247, 11, 145, 1, // 7847: decode to L2_loadalignh_pi using decoder 145 |
| 3653 | // 7847: } |
| 3654 | 2, 9, // 7852: case 0x2: { |
| 3655 | OPC_CheckField, 5, 8, 0, // 7854: check Inst[12:5] == 0x0 |
| 3656 | OPC_Decode, 248, 11, 144, 1, // 7858: decode to L2_loadalignh_pr using decoder 144 |
| 3657 | // 7858: } |
| 3658 | 3, 0, // 7863: case 0x3: { |
| 3659 | OPC_CheckField, 5, 8, 0, // 7865: check Inst[12:5] == 0x0 |
| 3660 | OPC_Decode, 244, 11, 144, 1, // 7869: decode to L2_loadalignh_pbr using decoder 144 |
| 3661 | // 7869: } |
| 3662 | // 7869: } // switch Inst[26:25] |
| 3663 | // 7869: } |
| 3664 | // 7869: } // switch Inst[27] |
| 3665 | // 7869: } |
| 3666 | 3, 71, // 7874: case 0x3: { |
| 3667 | OPC_SwitchField, 27, 1, // 7876: switch Inst[27] { |
| 3668 | 0, 5, // 7879: case 0x0: { |
| 3669 | OPC_Decode, 133, 12, 138, 1, // 7881: decode to L2_loadbzw2_io using decoder 138 |
| 3670 | // 7881: } |
| 3671 | 1, 0, // 7886: case 0x1: { |
| 3672 | OPC_SwitchField, 25, 2, // 7888: switch Inst[26:25] { |
| 3673 | 0, 21, // 7891: case 0x0: { |
| 3674 | OPC_SwitchField, 9, 4, // 7893: switch Inst[12:9] { |
| 3675 | 0, 5, // 7896: case 0x0: { |
| 3676 | OPC_Decode, 135, 12, 139, 1, // 7898: decode to L2_loadbzw2_pci using decoder 139 |
| 3677 | // 7898: } |
| 3678 | 1, 0, // 7903: case 0x1: { |
| 3679 | OPC_CheckField, 5, 4, 0, // 7905: check Inst[8:5] == 0x0 |
| 3680 | OPC_Decode, 136, 12, 140, 1, // 7909: decode to L2_loadbzw2_pcr using decoder 140 |
| 3681 | // 7909: } |
| 3682 | // 7909: } // switch Inst[12:9] |
| 3683 | // 7909: } |
| 3684 | 1, 9, // 7914: case 0x1: { |
| 3685 | OPC_CheckField, 9, 5, 0, // 7916: check Inst[13:9] == 0x0 |
| 3686 | OPC_Decode, 137, 12, 141, 1, // 7920: decode to L2_loadbzw2_pi using decoder 141 |
| 3687 | // 7920: } |
| 3688 | 2, 9, // 7925: case 0x2: { |
| 3689 | OPC_CheckField, 5, 8, 0, // 7927: check Inst[12:5] == 0x0 |
| 3690 | OPC_Decode, 138, 12, 140, 1, // 7931: decode to L2_loadbzw2_pr using decoder 140 |
| 3691 | // 7931: } |
| 3692 | 3, 0, // 7936: case 0x3: { |
| 3693 | OPC_CheckField, 5, 8, 0, // 7938: check Inst[12:5] == 0x0 |
| 3694 | OPC_Decode, 134, 12, 140, 1, // 7942: decode to L2_loadbzw2_pbr using decoder 140 |
| 3695 | // 7942: } |
| 3696 | // 7942: } // switch Inst[26:25] |
| 3697 | // 7942: } |
| 3698 | // 7942: } // switch Inst[27] |
| 3699 | // 7942: } |
| 3700 | 4, 71, // 7947: case 0x4: { |
| 3701 | OPC_SwitchField, 27, 1, // 7949: switch Inst[27] { |
| 3702 | 0, 5, // 7952: case 0x0: { |
| 3703 | OPC_Decode, 237, 11, 146, 1, // 7954: decode to L2_loadalignb_io using decoder 146 |
| 3704 | // 7954: } |
| 3705 | 1, 0, // 7959: case 0x1: { |
| 3706 | OPC_SwitchField, 25, 2, // 7961: switch Inst[26:25] { |
| 3707 | 0, 21, // 7964: case 0x0: { |
| 3708 | OPC_SwitchField, 9, 4, // 7966: switch Inst[12:9] { |
| 3709 | 0, 5, // 7969: case 0x0: { |
| 3710 | OPC_Decode, 239, 11, 147, 1, // 7971: decode to L2_loadalignb_pci using decoder 147 |
| 3711 | // 7971: } |
| 3712 | 1, 0, // 7976: case 0x1: { |
| 3713 | OPC_CheckField, 5, 4, 0, // 7978: check Inst[8:5] == 0x0 |
| 3714 | OPC_Decode, 240, 11, 144, 1, // 7982: decode to L2_loadalignb_pcr using decoder 144 |
| 3715 | // 7982: } |
| 3716 | // 7982: } // switch Inst[12:9] |
| 3717 | // 7982: } |
| 3718 | 1, 9, // 7987: case 0x1: { |
| 3719 | OPC_CheckField, 9, 5, 0, // 7989: check Inst[13:9] == 0x0 |
| 3720 | OPC_Decode, 241, 11, 148, 1, // 7993: decode to L2_loadalignb_pi using decoder 148 |
| 3721 | // 7993: } |
| 3722 | 2, 9, // 7998: case 0x2: { |
| 3723 | OPC_CheckField, 5, 8, 0, // 8000: check Inst[12:5] == 0x0 |
| 3724 | OPC_Decode, 242, 11, 144, 1, // 8004: decode to L2_loadalignb_pr using decoder 144 |
| 3725 | // 8004: } |
| 3726 | 3, 0, // 8009: case 0x3: { |
| 3727 | OPC_CheckField, 5, 8, 0, // 8011: check Inst[12:5] == 0x0 |
| 3728 | OPC_Decode, 238, 11, 144, 1, // 8015: decode to L2_loadalignb_pbr using decoder 144 |
| 3729 | // 8015: } |
| 3730 | // 8015: } // switch Inst[26:25] |
| 3731 | // 8015: } |
| 3732 | // 8015: } // switch Inst[27] |
| 3733 | // 8015: } |
| 3734 | 5, 71, // 8020: case 0x5: { |
| 3735 | OPC_SwitchField, 27, 1, // 8022: switch Inst[27] { |
| 3736 | 0, 5, // 8025: case 0x0: { |
| 3737 | OPC_Decode, 139, 12, 149, 1, // 8027: decode to L2_loadbzw4_io using decoder 149 |
| 3738 | // 8027: } |
| 3739 | 1, 0, // 8032: case 0x1: { |
| 3740 | OPC_SwitchField, 25, 2, // 8034: switch Inst[26:25] { |
| 3741 | 0, 21, // 8037: case 0x0: { |
| 3742 | OPC_SwitchField, 9, 4, // 8039: switch Inst[12:9] { |
| 3743 | 0, 5, // 8042: case 0x0: { |
| 3744 | OPC_Decode, 141, 12, 150, 1, // 8044: decode to L2_loadbzw4_pci using decoder 150 |
| 3745 | // 8044: } |
| 3746 | 1, 0, // 8049: case 0x1: { |
| 3747 | OPC_CheckField, 5, 4, 0, // 8051: check Inst[8:5] == 0x0 |
| 3748 | OPC_Decode, 142, 12, 151, 1, // 8055: decode to L2_loadbzw4_pcr using decoder 151 |
| 3749 | // 8055: } |
| 3750 | // 8055: } // switch Inst[12:9] |
| 3751 | // 8055: } |
| 3752 | 1, 9, // 8060: case 0x1: { |
| 3753 | OPC_CheckField, 9, 5, 0, // 8062: check Inst[13:9] == 0x0 |
| 3754 | OPC_Decode, 143, 12, 152, 1, // 8066: decode to L2_loadbzw4_pi using decoder 152 |
| 3755 | // 8066: } |
| 3756 | 2, 9, // 8071: case 0x2: { |
| 3757 | OPC_CheckField, 5, 8, 0, // 8073: check Inst[12:5] == 0x0 |
| 3758 | OPC_Decode, 144, 12, 151, 1, // 8077: decode to L2_loadbzw4_pr using decoder 151 |
| 3759 | // 8077: } |
| 3760 | 3, 0, // 8082: case 0x3: { |
| 3761 | OPC_CheckField, 5, 8, 0, // 8084: check Inst[12:5] == 0x0 |
| 3762 | OPC_Decode, 140, 12, 151, 1, // 8088: decode to L2_loadbzw4_pbr using decoder 151 |
| 3763 | // 8088: } |
| 3764 | // 8088: } // switch Inst[26:25] |
| 3765 | // 8088: } |
| 3766 | // 8088: } // switch Inst[27] |
| 3767 | // 8088: } |
| 3768 | 7, 71, // 8093: case 0x7: { |
| 3769 | OPC_SwitchField, 27, 1, // 8095: switch Inst[27] { |
| 3770 | 0, 5, // 8098: case 0x0: { |
| 3771 | OPC_Decode, 255, 11, 149, 1, // 8100: decode to L2_loadbsw4_io using decoder 149 |
| 3772 | // 8100: } |
| 3773 | 1, 0, // 8105: case 0x1: { |
| 3774 | OPC_SwitchField, 25, 2, // 8107: switch Inst[26:25] { |
| 3775 | 0, 21, // 8110: case 0x0: { |
| 3776 | OPC_SwitchField, 9, 4, // 8112: switch Inst[12:9] { |
| 3777 | 0, 5, // 8115: case 0x0: { |
| 3778 | OPC_Decode, 129, 12, 150, 1, // 8117: decode to L2_loadbsw4_pci using decoder 150 |
| 3779 | // 8117: } |
| 3780 | 1, 0, // 8122: case 0x1: { |
| 3781 | OPC_CheckField, 5, 4, 0, // 8124: check Inst[8:5] == 0x0 |
| 3782 | OPC_Decode, 130, 12, 151, 1, // 8128: decode to L2_loadbsw4_pcr using decoder 151 |
| 3783 | // 8128: } |
| 3784 | // 8128: } // switch Inst[12:9] |
| 3785 | // 8128: } |
| 3786 | 1, 9, // 8133: case 0x1: { |
| 3787 | OPC_CheckField, 9, 5, 0, // 8135: check Inst[13:9] == 0x0 |
| 3788 | OPC_Decode, 131, 12, 152, 1, // 8139: decode to L2_loadbsw4_pi using decoder 152 |
| 3789 | // 8139: } |
| 3790 | 2, 9, // 8144: case 0x2: { |
| 3791 | OPC_CheckField, 5, 8, 0, // 8146: check Inst[12:5] == 0x0 |
| 3792 | OPC_Decode, 132, 12, 151, 1, // 8150: decode to L2_loadbsw4_pr using decoder 151 |
| 3793 | // 8150: } |
| 3794 | 3, 0, // 8155: case 0x3: { |
| 3795 | OPC_CheckField, 5, 8, 0, // 8157: check Inst[12:5] == 0x0 |
| 3796 | OPC_Decode, 128, 12, 151, 1, // 8161: decode to L2_loadbsw4_pbr using decoder 151 |
| 3797 | // 8161: } |
| 3798 | // 8161: } // switch Inst[26:25] |
| 3799 | // 8161: } |
| 3800 | // 8161: } // switch Inst[27] |
| 3801 | // 8161: } |
| 3802 | 8, 133, 1, // 8166: case 0x8: { |
| 3803 | OPC_SwitchField, 27, 1, // 8169: switch Inst[27] { |
| 3804 | 0, 5, // 8172: case 0x0: { |
| 3805 | OPC_Decode, 145, 12, 153, 1, // 8174: decode to L2_loadrb_io using decoder 153 |
| 3806 | // 8174: } |
| 3807 | 1, 0, // 8179: case 0x1: { |
| 3808 | OPC_SwitchField, 11, 2, // 8181: switch Inst[12:11] { |
| 3809 | 0, 71, // 8184: case 0x0: { |
| 3810 | OPC_SwitchField, 25, 2, // 8186: switch Inst[26:25] { |
| 3811 | 0, 21, // 8189: case 0x0: { |
| 3812 | OPC_SwitchField, 9, 2, // 8191: switch Inst[10:9] { |
| 3813 | 0, 5, // 8194: case 0x0: { |
| 3814 | OPC_Decode, 147, 12, 154, 1, // 8196: decode to L2_loadrb_pci using decoder 154 |
| 3815 | // 8196: } |
| 3816 | 1, 0, // 8201: case 0x1: { |
| 3817 | OPC_CheckField, 5, 4, 0, // 8203: check Inst[8:5] == 0x0 |
| 3818 | OPC_Decode, 148, 12, 140, 1, // 8207: decode to L2_loadrb_pcr using decoder 140 |
| 3819 | // 8207: } |
| 3820 | // 8207: } // switch Inst[10:9] |
| 3821 | // 8207: } |
| 3822 | 1, 21, // 8212: case 0x1: { |
| 3823 | OPC_SwitchField, 13, 1, // 8214: switch Inst[13] { |
| 3824 | 0, 9, // 8217: case 0x0: { |
| 3825 | OPC_CheckField, 9, 2, 0, // 8219: check Inst[10:9] == 0x0 |
| 3826 | OPC_Decode, 149, 12, 155, 1, // 8223: decode to L2_loadrb_pi using decoder 155 |
| 3827 | // 8223: } |
| 3828 | 1, 0, // 8228: case 0x1: { |
| 3829 | OPC_Decode, 194, 12, 156, 1, // 8230: decode to L2_ploadrbt_pi using decoder 156 |
| 3830 | // 8230: } |
| 3831 | // 8230: } // switch Inst[13] |
| 3832 | // 8230: } |
| 3833 | 2, 9, // 8235: case 0x2: { |
| 3834 | OPC_CheckField, 5, 6, 0, // 8237: check Inst[10:5] == 0x0 |
| 3835 | OPC_Decode, 150, 12, 140, 1, // 8241: decode to L2_loadrb_pr using decoder 140 |
| 3836 | // 8241: } |
| 3837 | 3, 0, // 8246: case 0x3: { |
| 3838 | OPC_CheckField, 5, 6, 0, // 8248: check Inst[10:5] == 0x0 |
| 3839 | OPC_Decode, 146, 12, 140, 1, // 8252: decode to L2_loadrb_pbr using decoder 140 |
| 3840 | // 8252: } |
| 3841 | // 8252: } // switch Inst[26:25] |
| 3842 | // 8252: } |
| 3843 | 1, 13, // 8257: case 0x1: { |
| 3844 | OPC_CheckField, 25, 2, 1, // 8259: check Inst[26:25] == 0x1 |
| 3845 | OPC_CheckField, 13, 1, 1, // 8263: check Inst[13] == 0x1 |
| 3846 | OPC_Decode, 190, 12, 156, 1, // 8267: decode to L2_ploadrbf_pi using decoder 156 |
| 3847 | // 8267: } |
| 3848 | 2, 13, // 8272: case 0x2: { |
| 3849 | OPC_CheckField, 25, 2, 1, // 8274: check Inst[26:25] == 0x1 |
| 3850 | OPC_CheckField, 13, 1, 1, // 8278: check Inst[13] == 0x1 |
| 3851 | OPC_Decode, 196, 12, 156, 1, // 8282: decode to L2_ploadrbtnew_pi using decoder 156 |
| 3852 | // 8282: } |
| 3853 | 3, 0, // 8287: case 0x3: { |
| 3854 | OPC_CheckField, 25, 2, 1, // 8289: check Inst[26:25] == 0x1 |
| 3855 | OPC_CheckField, 13, 1, 1, // 8293: check Inst[13] == 0x1 |
| 3856 | OPC_Decode, 192, 12, 156, 1, // 8297: decode to L2_ploadrbfnew_pi using decoder 156 |
| 3857 | // 8297: } |
| 3858 | // 8297: } // switch Inst[12:11] |
| 3859 | // 8297: } |
| 3860 | // 8297: } // switch Inst[27] |
| 3861 | // 8297: } |
| 3862 | 9, 133, 1, // 8302: case 0x9: { |
| 3863 | OPC_SwitchField, 27, 1, // 8305: switch Inst[27] { |
| 3864 | 0, 5, // 8308: case 0x0: { |
| 3865 | OPC_Decode, 173, 12, 153, 1, // 8310: decode to L2_loadrub_io using decoder 153 |
| 3866 | // 8310: } |
| 3867 | 1, 0, // 8315: case 0x1: { |
| 3868 | OPC_SwitchField, 11, 2, // 8317: switch Inst[12:11] { |
| 3869 | 0, 71, // 8320: case 0x0: { |
| 3870 | OPC_SwitchField, 25, 2, // 8322: switch Inst[26:25] { |
| 3871 | 0, 21, // 8325: case 0x0: { |
| 3872 | OPC_SwitchField, 9, 2, // 8327: switch Inst[10:9] { |
| 3873 | 0, 5, // 8330: case 0x0: { |
| 3874 | OPC_Decode, 175, 12, 154, 1, // 8332: decode to L2_loadrub_pci using decoder 154 |
| 3875 | // 8332: } |
| 3876 | 1, 0, // 8337: case 0x1: { |
| 3877 | OPC_CheckField, 5, 4, 0, // 8339: check Inst[8:5] == 0x0 |
| 3878 | OPC_Decode, 176, 12, 140, 1, // 8343: decode to L2_loadrub_pcr using decoder 140 |
| 3879 | // 8343: } |
| 3880 | // 8343: } // switch Inst[10:9] |
| 3881 | // 8343: } |
| 3882 | 1, 21, // 8348: case 0x1: { |
| 3883 | OPC_SwitchField, 13, 1, // 8350: switch Inst[13] { |
| 3884 | 0, 9, // 8353: case 0x0: { |
| 3885 | OPC_CheckField, 9, 2, 0, // 8355: check Inst[10:9] == 0x0 |
| 3886 | OPC_Decode, 177, 12, 155, 1, // 8359: decode to L2_loadrub_pi using decoder 155 |
| 3887 | // 8359: } |
| 3888 | 1, 0, // 8364: case 0x1: { |
| 3889 | OPC_Decode, 226, 12, 156, 1, // 8366: decode to L2_ploadrubt_pi using decoder 156 |
| 3890 | // 8366: } |
| 3891 | // 8366: } // switch Inst[13] |
| 3892 | // 8366: } |
| 3893 | 2, 9, // 8371: case 0x2: { |
| 3894 | OPC_CheckField, 5, 6, 0, // 8373: check Inst[10:5] == 0x0 |
| 3895 | OPC_Decode, 178, 12, 140, 1, // 8377: decode to L2_loadrub_pr using decoder 140 |
| 3896 | // 8377: } |
| 3897 | 3, 0, // 8382: case 0x3: { |
| 3898 | OPC_CheckField, 5, 6, 0, // 8384: check Inst[10:5] == 0x0 |
| 3899 | OPC_Decode, 174, 12, 140, 1, // 8388: decode to L2_loadrub_pbr using decoder 140 |
| 3900 | // 8388: } |
| 3901 | // 8388: } // switch Inst[26:25] |
| 3902 | // 8388: } |
| 3903 | 1, 13, // 8393: case 0x1: { |
| 3904 | OPC_CheckField, 25, 2, 1, // 8395: check Inst[26:25] == 0x1 |
| 3905 | OPC_CheckField, 13, 1, 1, // 8399: check Inst[13] == 0x1 |
| 3906 | OPC_Decode, 222, 12, 156, 1, // 8403: decode to L2_ploadrubf_pi using decoder 156 |
| 3907 | // 8403: } |
| 3908 | 2, 13, // 8408: case 0x2: { |
| 3909 | OPC_CheckField, 25, 2, 1, // 8410: check Inst[26:25] == 0x1 |
| 3910 | OPC_CheckField, 13, 1, 1, // 8414: check Inst[13] == 0x1 |
| 3911 | OPC_Decode, 228, 12, 156, 1, // 8418: decode to L2_ploadrubtnew_pi using decoder 156 |
| 3912 | // 8418: } |
| 3913 | 3, 0, // 8423: case 0x3: { |
| 3914 | OPC_CheckField, 25, 2, 1, // 8425: check Inst[26:25] == 0x1 |
| 3915 | OPC_CheckField, 13, 1, 1, // 8429: check Inst[13] == 0x1 |
| 3916 | OPC_Decode, 224, 12, 156, 1, // 8433: decode to L2_ploadrubfnew_pi using decoder 156 |
| 3917 | // 8433: } |
| 3918 | // 8433: } // switch Inst[12:11] |
| 3919 | // 8433: } |
| 3920 | // 8433: } // switch Inst[27] |
| 3921 | // 8433: } |
| 3922 | 10, 133, 1, // 8438: case 0xa: { |
| 3923 | OPC_SwitchField, 27, 1, // 8441: switch Inst[27] { |
| 3924 | 0, 5, // 8444: case 0x0: { |
| 3925 | OPC_Decode, 159, 12, 138, 1, // 8446: decode to L2_loadrh_io using decoder 138 |
| 3926 | // 8446: } |
| 3927 | 1, 0, // 8451: case 0x1: { |
| 3928 | OPC_SwitchField, 11, 2, // 8453: switch Inst[12:11] { |
| 3929 | 0, 71, // 8456: case 0x0: { |
| 3930 | OPC_SwitchField, 25, 2, // 8458: switch Inst[26:25] { |
| 3931 | 0, 21, // 8461: case 0x0: { |
| 3932 | OPC_SwitchField, 9, 2, // 8463: switch Inst[10:9] { |
| 3933 | 0, 5, // 8466: case 0x0: { |
| 3934 | OPC_Decode, 161, 12, 139, 1, // 8468: decode to L2_loadrh_pci using decoder 139 |
| 3935 | // 8468: } |
| 3936 | 1, 0, // 8473: case 0x1: { |
| 3937 | OPC_CheckField, 5, 4, 0, // 8475: check Inst[8:5] == 0x0 |
| 3938 | OPC_Decode, 162, 12, 140, 1, // 8479: decode to L2_loadrh_pcr using decoder 140 |
| 3939 | // 8479: } |
| 3940 | // 8479: } // switch Inst[10:9] |
| 3941 | // 8479: } |
| 3942 | 1, 21, // 8484: case 0x1: { |
| 3943 | OPC_SwitchField, 13, 1, // 8486: switch Inst[13] { |
| 3944 | 0, 9, // 8489: case 0x0: { |
| 3945 | OPC_CheckField, 9, 2, 0, // 8491: check Inst[10:9] == 0x0 |
| 3946 | OPC_Decode, 163, 12, 141, 1, // 8495: decode to L2_loadrh_pi using decoder 141 |
| 3947 | // 8495: } |
| 3948 | 1, 0, // 8500: case 0x1: { |
| 3949 | OPC_Decode, 210, 12, 157, 1, // 8502: decode to L2_ploadrht_pi using decoder 157 |
| 3950 | // 8502: } |
| 3951 | // 8502: } // switch Inst[13] |
| 3952 | // 8502: } |
| 3953 | 2, 9, // 8507: case 0x2: { |
| 3954 | OPC_CheckField, 5, 6, 0, // 8509: check Inst[10:5] == 0x0 |
| 3955 | OPC_Decode, 164, 12, 140, 1, // 8513: decode to L2_loadrh_pr using decoder 140 |
| 3956 | // 8513: } |
| 3957 | 3, 0, // 8518: case 0x3: { |
| 3958 | OPC_CheckField, 5, 6, 0, // 8520: check Inst[10:5] == 0x0 |
| 3959 | OPC_Decode, 160, 12, 140, 1, // 8524: decode to L2_loadrh_pbr using decoder 140 |
| 3960 | // 8524: } |
| 3961 | // 8524: } // switch Inst[26:25] |
| 3962 | // 8524: } |
| 3963 | 1, 13, // 8529: case 0x1: { |
| 3964 | OPC_CheckField, 25, 2, 1, // 8531: check Inst[26:25] == 0x1 |
| 3965 | OPC_CheckField, 13, 1, 1, // 8535: check Inst[13] == 0x1 |
| 3966 | OPC_Decode, 206, 12, 157, 1, // 8539: decode to L2_ploadrhf_pi using decoder 157 |
| 3967 | // 8539: } |
| 3968 | 2, 13, // 8544: case 0x2: { |
| 3969 | OPC_CheckField, 25, 2, 1, // 8546: check Inst[26:25] == 0x1 |
| 3970 | OPC_CheckField, 13, 1, 1, // 8550: check Inst[13] == 0x1 |
| 3971 | OPC_Decode, 212, 12, 157, 1, // 8554: decode to L2_ploadrhtnew_pi using decoder 157 |
| 3972 | // 8554: } |
| 3973 | 3, 0, // 8559: case 0x3: { |
| 3974 | OPC_CheckField, 25, 2, 1, // 8561: check Inst[26:25] == 0x1 |
| 3975 | OPC_CheckField, 13, 1, 1, // 8565: check Inst[13] == 0x1 |
| 3976 | OPC_Decode, 208, 12, 157, 1, // 8569: decode to L2_ploadrhfnew_pi using decoder 157 |
| 3977 | // 8569: } |
| 3978 | // 8569: } // switch Inst[12:11] |
| 3979 | // 8569: } |
| 3980 | // 8569: } // switch Inst[27] |
| 3981 | // 8569: } |
| 3982 | 11, 133, 1, // 8574: case 0xb: { |
| 3983 | OPC_SwitchField, 27, 1, // 8577: switch Inst[27] { |
| 3984 | 0, 5, // 8580: case 0x0: { |
| 3985 | OPC_Decode, 180, 12, 138, 1, // 8582: decode to L2_loadruh_io using decoder 138 |
| 3986 | // 8582: } |
| 3987 | 1, 0, // 8587: case 0x1: { |
| 3988 | OPC_SwitchField, 11, 2, // 8589: switch Inst[12:11] { |
| 3989 | 0, 71, // 8592: case 0x0: { |
| 3990 | OPC_SwitchField, 25, 2, // 8594: switch Inst[26:25] { |
| 3991 | 0, 21, // 8597: case 0x0: { |
| 3992 | OPC_SwitchField, 9, 2, // 8599: switch Inst[10:9] { |
| 3993 | 0, 5, // 8602: case 0x0: { |
| 3994 | OPC_Decode, 182, 12, 139, 1, // 8604: decode to L2_loadruh_pci using decoder 139 |
| 3995 | // 8604: } |
| 3996 | 1, 0, // 8609: case 0x1: { |
| 3997 | OPC_CheckField, 5, 4, 0, // 8611: check Inst[8:5] == 0x0 |
| 3998 | OPC_Decode, 183, 12, 140, 1, // 8615: decode to L2_loadruh_pcr using decoder 140 |
| 3999 | // 8615: } |
| 4000 | // 8615: } // switch Inst[10:9] |
| 4001 | // 8615: } |
| 4002 | 1, 21, // 8620: case 0x1: { |
| 4003 | OPC_SwitchField, 13, 1, // 8622: switch Inst[13] { |
| 4004 | 0, 9, // 8625: case 0x0: { |
| 4005 | OPC_CheckField, 9, 2, 0, // 8627: check Inst[10:9] == 0x0 |
| 4006 | OPC_Decode, 184, 12, 141, 1, // 8631: decode to L2_loadruh_pi using decoder 141 |
| 4007 | // 8631: } |
| 4008 | 1, 0, // 8636: case 0x1: { |
| 4009 | OPC_Decode, 234, 12, 157, 1, // 8638: decode to L2_ploadruht_pi using decoder 157 |
| 4010 | // 8638: } |
| 4011 | // 8638: } // switch Inst[13] |
| 4012 | // 8638: } |
| 4013 | 2, 9, // 8643: case 0x2: { |
| 4014 | OPC_CheckField, 5, 6, 0, // 8645: check Inst[10:5] == 0x0 |
| 4015 | OPC_Decode, 185, 12, 140, 1, // 8649: decode to L2_loadruh_pr using decoder 140 |
| 4016 | // 8649: } |
| 4017 | 3, 0, // 8654: case 0x3: { |
| 4018 | OPC_CheckField, 5, 6, 0, // 8656: check Inst[10:5] == 0x0 |
| 4019 | OPC_Decode, 181, 12, 140, 1, // 8660: decode to L2_loadruh_pbr using decoder 140 |
| 4020 | // 8660: } |
| 4021 | // 8660: } // switch Inst[26:25] |
| 4022 | // 8660: } |
| 4023 | 1, 13, // 8665: case 0x1: { |
| 4024 | OPC_CheckField, 25, 2, 1, // 8667: check Inst[26:25] == 0x1 |
| 4025 | OPC_CheckField, 13, 1, 1, // 8671: check Inst[13] == 0x1 |
| 4026 | OPC_Decode, 230, 12, 157, 1, // 8675: decode to L2_ploadruhf_pi using decoder 157 |
| 4027 | // 8675: } |
| 4028 | 2, 13, // 8680: case 0x2: { |
| 4029 | OPC_CheckField, 25, 2, 1, // 8682: check Inst[26:25] == 0x1 |
| 4030 | OPC_CheckField, 13, 1, 1, // 8686: check Inst[13] == 0x1 |
| 4031 | OPC_Decode, 236, 12, 157, 1, // 8690: decode to L2_ploadruhtnew_pi using decoder 157 |
| 4032 | // 8690: } |
| 4033 | 3, 0, // 8695: case 0x3: { |
| 4034 | OPC_CheckField, 25, 2, 1, // 8697: check Inst[26:25] == 0x1 |
| 4035 | OPC_CheckField, 13, 1, 1, // 8701: check Inst[13] == 0x1 |
| 4036 | OPC_Decode, 232, 12, 157, 1, // 8705: decode to L2_ploadruhfnew_pi using decoder 157 |
| 4037 | // 8705: } |
| 4038 | // 8705: } // switch Inst[12:11] |
| 4039 | // 8705: } |
| 4040 | // 8705: } // switch Inst[27] |
| 4041 | // 8705: } |
| 4042 | 12, 133, 1, // 8710: case 0xc: { |
| 4043 | OPC_SwitchField, 27, 1, // 8713: switch Inst[27] { |
| 4044 | 0, 5, // 8716: case 0x0: { |
| 4045 | OPC_Decode, 166, 12, 158, 1, // 8718: decode to L2_loadri_io using decoder 158 |
| 4046 | // 8718: } |
| 4047 | 1, 0, // 8723: case 0x1: { |
| 4048 | OPC_SwitchField, 11, 2, // 8725: switch Inst[12:11] { |
| 4049 | 0, 71, // 8728: case 0x0: { |
| 4050 | OPC_SwitchField, 25, 2, // 8730: switch Inst[26:25] { |
| 4051 | 0, 21, // 8733: case 0x0: { |
| 4052 | OPC_SwitchField, 9, 2, // 8735: switch Inst[10:9] { |
| 4053 | 0, 5, // 8738: case 0x0: { |
| 4054 | OPC_Decode, 168, 12, 159, 1, // 8740: decode to L2_loadri_pci using decoder 159 |
| 4055 | // 8740: } |
| 4056 | 1, 0, // 8745: case 0x1: { |
| 4057 | OPC_CheckField, 5, 4, 0, // 8747: check Inst[8:5] == 0x0 |
| 4058 | OPC_Decode, 169, 12, 140, 1, // 8751: decode to L2_loadri_pcr using decoder 140 |
| 4059 | // 8751: } |
| 4060 | // 8751: } // switch Inst[10:9] |
| 4061 | // 8751: } |
| 4062 | 1, 21, // 8756: case 0x1: { |
| 4063 | OPC_SwitchField, 13, 1, // 8758: switch Inst[13] { |
| 4064 | 0, 9, // 8761: case 0x0: { |
| 4065 | OPC_CheckField, 9, 2, 0, // 8763: check Inst[10:9] == 0x0 |
| 4066 | OPC_Decode, 170, 12, 160, 1, // 8767: decode to L2_loadri_pi using decoder 160 |
| 4067 | // 8767: } |
| 4068 | 1, 0, // 8772: case 0x1: { |
| 4069 | OPC_Decode, 218, 12, 161, 1, // 8774: decode to L2_ploadrit_pi using decoder 161 |
| 4070 | // 8774: } |
| 4071 | // 8774: } // switch Inst[13] |
| 4072 | // 8774: } |
| 4073 | 2, 9, // 8779: case 0x2: { |
| 4074 | OPC_CheckField, 5, 6, 0, // 8781: check Inst[10:5] == 0x0 |
| 4075 | OPC_Decode, 171, 12, 140, 1, // 8785: decode to L2_loadri_pr using decoder 140 |
| 4076 | // 8785: } |
| 4077 | 3, 0, // 8790: case 0x3: { |
| 4078 | OPC_CheckField, 5, 6, 0, // 8792: check Inst[10:5] == 0x0 |
| 4079 | OPC_Decode, 167, 12, 140, 1, // 8796: decode to L2_loadri_pbr using decoder 140 |
| 4080 | // 8796: } |
| 4081 | // 8796: } // switch Inst[26:25] |
| 4082 | // 8796: } |
| 4083 | 1, 13, // 8801: case 0x1: { |
| 4084 | OPC_CheckField, 25, 2, 1, // 8803: check Inst[26:25] == 0x1 |
| 4085 | OPC_CheckField, 13, 1, 1, // 8807: check Inst[13] == 0x1 |
| 4086 | OPC_Decode, 214, 12, 161, 1, // 8811: decode to L2_ploadrif_pi using decoder 161 |
| 4087 | // 8811: } |
| 4088 | 2, 13, // 8816: case 0x2: { |
| 4089 | OPC_CheckField, 25, 2, 1, // 8818: check Inst[26:25] == 0x1 |
| 4090 | OPC_CheckField, 13, 1, 1, // 8822: check Inst[13] == 0x1 |
| 4091 | OPC_Decode, 220, 12, 161, 1, // 8826: decode to L2_ploadritnew_pi using decoder 161 |
| 4092 | // 8826: } |
| 4093 | 3, 0, // 8831: case 0x3: { |
| 4094 | OPC_CheckField, 25, 2, 1, // 8833: check Inst[26:25] == 0x1 |
| 4095 | OPC_CheckField, 13, 1, 1, // 8837: check Inst[13] == 0x1 |
| 4096 | OPC_Decode, 216, 12, 161, 1, // 8841: decode to L2_ploadrifnew_pi using decoder 161 |
| 4097 | // 8841: } |
| 4098 | // 8841: } // switch Inst[12:11] |
| 4099 | // 8841: } |
| 4100 | // 8841: } // switch Inst[27] |
| 4101 | // 8841: } |
| 4102 | 14, 0, // 8846: case 0xe: { |
| 4103 | OPC_SwitchField, 27, 1, // 8848: switch Inst[27] { |
| 4104 | 0, 5, // 8851: case 0x0: { |
| 4105 | OPC_Decode, 152, 12, 162, 1, // 8853: decode to L2_loadrd_io using decoder 162 |
| 4106 | // 8853: } |
| 4107 | 1, 0, // 8858: case 0x1: { |
| 4108 | OPC_SwitchField, 11, 2, // 8860: switch Inst[12:11] { |
| 4109 | 0, 71, // 8863: case 0x0: { |
| 4110 | OPC_SwitchField, 25, 2, // 8865: switch Inst[26:25] { |
| 4111 | 0, 21, // 8868: case 0x0: { |
| 4112 | OPC_SwitchField, 9, 2, // 8870: switch Inst[10:9] { |
| 4113 | 0, 5, // 8873: case 0x0: { |
| 4114 | OPC_Decode, 154, 12, 163, 1, // 8875: decode to L2_loadrd_pci using decoder 163 |
| 4115 | // 8875: } |
| 4116 | 1, 0, // 8880: case 0x1: { |
| 4117 | OPC_CheckField, 5, 4, 0, // 8882: check Inst[8:5] == 0x0 |
| 4118 | OPC_Decode, 155, 12, 151, 1, // 8886: decode to L2_loadrd_pcr using decoder 151 |
| 4119 | // 8886: } |
| 4120 | // 8886: } // switch Inst[10:9] |
| 4121 | // 8886: } |
| 4122 | 1, 21, // 8891: case 0x1: { |
| 4123 | OPC_SwitchField, 13, 1, // 8893: switch Inst[13] { |
| 4124 | 0, 9, // 8896: case 0x0: { |
| 4125 | OPC_CheckField, 9, 2, 0, // 8898: check Inst[10:9] == 0x0 |
| 4126 | OPC_Decode, 156, 12, 164, 1, // 8902: decode to L2_loadrd_pi using decoder 164 |
| 4127 | // 8902: } |
| 4128 | 1, 0, // 8907: case 0x1: { |
| 4129 | OPC_Decode, 202, 12, 165, 1, // 8909: decode to L2_ploadrdt_pi using decoder 165 |
| 4130 | // 8909: } |
| 4131 | // 8909: } // switch Inst[13] |
| 4132 | // 8909: } |
| 4133 | 2, 9, // 8914: case 0x2: { |
| 4134 | OPC_CheckField, 5, 6, 0, // 8916: check Inst[10:5] == 0x0 |
| 4135 | OPC_Decode, 157, 12, 151, 1, // 8920: decode to L2_loadrd_pr using decoder 151 |
| 4136 | // 8920: } |
| 4137 | 3, 0, // 8925: case 0x3: { |
| 4138 | OPC_CheckField, 5, 6, 0, // 8927: check Inst[10:5] == 0x0 |
| 4139 | OPC_Decode, 153, 12, 151, 1, // 8931: decode to L2_loadrd_pbr using decoder 151 |
| 4140 | // 8931: } |
| 4141 | // 8931: } // switch Inst[26:25] |
| 4142 | // 8931: } |
| 4143 | 1, 13, // 8936: case 0x1: { |
| 4144 | OPC_CheckField, 25, 2, 1, // 8938: check Inst[26:25] == 0x1 |
| 4145 | OPC_CheckField, 13, 1, 1, // 8942: check Inst[13] == 0x1 |
| 4146 | OPC_Decode, 198, 12, 165, 1, // 8946: decode to L2_ploadrdf_pi using decoder 165 |
| 4147 | // 8946: } |
| 4148 | 2, 13, // 8951: case 0x2: { |
| 4149 | OPC_CheckField, 25, 2, 1, // 8953: check Inst[26:25] == 0x1 |
| 4150 | OPC_CheckField, 13, 1, 1, // 8957: check Inst[13] == 0x1 |
| 4151 | OPC_Decode, 204, 12, 165, 1, // 8961: decode to L2_ploadrdtnew_pi using decoder 165 |
| 4152 | // 8961: } |
| 4153 | 3, 0, // 8966: case 0x3: { |
| 4154 | OPC_CheckField, 25, 2, 1, // 8968: check Inst[26:25] == 0x1 |
| 4155 | OPC_CheckField, 13, 1, 1, // 8972: check Inst[13] == 0x1 |
| 4156 | OPC_Decode, 200, 12, 165, 1, // 8976: decode to L2_ploadrdfnew_pi using decoder 165 |
| 4157 | // 8976: } |
| 4158 | // 8976: } // switch Inst[12:11] |
| 4159 | // 8976: } |
| 4160 | // 8976: } // switch Inst[27] |
| 4161 | // 8976: } |
| 4162 | // 8976: } // switch Inst[24:21] |
| 4163 | // 8976: } |
| 4164 | 10, 220, 13, // 8981: case 0xa: { |
| 4165 | OPC_SwitchField, 21, 4, // 8984: switch Inst[24:21] { |
| 4166 | 0, 203, 1, // 8987: case 0x0: { |
| 4167 | OPC_SwitchField, 5, 3, // 8990: switch Inst[7:5] { |
| 4168 | 0, 81, // 8993: case 0x0: { |
| 4169 | OPC_SwitchField, 25, 3, // 8995: switch Inst[27:25] { |
| 4170 | 0, 12, // 8998: case 0x0: { |
| 4171 | OPC_CheckField, 8, 6, 0, // 9000: check Inst[13:8] == 0x0 |
| 4172 | OPC_CheckField, 0, 5, 0, // 9004: check Inst[4:0] == 0x0 |
| 4173 | OPC_Decode, 145, 26, 56, // 9008: decode to Y2_dccleana using decoder 56 |
| 4174 | // 9008: } |
| 4175 | 1, 16, // 9012: case 0x1: { |
| 4176 | OPC_CheckField, 16, 5, 0, // 9014: check Inst[20:16] == 0x0 |
| 4177 | OPC_CheckField, 8, 6, 0, // 9018: check Inst[13:8] == 0x0 |
| 4178 | OPC_CheckField, 0, 5, 0, // 9022: check Inst[4:0] == 0x0 |
| 4179 | OPC_Decode, 152, 26, 63, // 9026: decode to Y2_dckill using decoder 63 |
| 4180 | // 9026: } |
| 4181 | 2, 12, // 9030: case 0x2: { |
| 4182 | OPC_CheckField, 13, 1, 0, // 9032: check Inst[13] == 0x0 |
| 4183 | OPC_CheckField, 0, 5, 0, // 9036: check Inst[4:0] == 0x0 |
| 4184 | OPC_Decode, 154, 26, 62, // 9040: decode to Y2_dctagw using decoder 62 |
| 4185 | // 9040: } |
| 4186 | 3, 12, // 9044: case 0x3: { |
| 4187 | OPC_CheckField, 13, 1, 0, // 9046: check Inst[13] == 0x0 |
| 4188 | OPC_CheckField, 0, 5, 0, // 9050: check Inst[4:0] == 0x0 |
| 4189 | OPC_Decode, 189, 26, 62, // 9054: decode to Y4_l2fetch using decoder 62 |
| 4190 | // 9054: } |
| 4191 | 4, 0, // 9058: case 0x4: { |
| 4192 | OPC_CheckField, 16, 5, 0, // 9060: check Inst[20:16] == 0x0 |
| 4193 | OPC_CheckField, 8, 6, 0, // 9064: check Inst[13:8] == 0x0 |
| 4194 | OPC_CheckField, 0, 5, 0, // 9068: check Inst[4:0] == 0x0 |
| 4195 | OPC_Decode, 140, 26, 63, // 9072: decode to Y2_barrier using decoder 63 |
| 4196 | // 9072: } |
| 4197 | // 9072: } // switch Inst[27:25] |
| 4198 | // 9072: } |
| 4199 | 1, 36, // 9076: case 0x1: { |
| 4200 | OPC_SwitchField, 25, 3, // 9078: switch Inst[27:25] { |
| 4201 | 3, 14, // 9081: case 0x3: { |
| 4202 | OPC_CheckPredicate, 9, // 9083: check predicate 9 |
| 4203 | OPC_CheckField, 8, 6, 0, // 9085: check Inst[13:8] == 0x0 |
| 4204 | OPC_CheckField, 0, 5, 0, // 9089: check Inst[4:0] == 0x0 |
| 4205 | OPC_Decode, 215, 26, 56, // 9093: decode to Y6_dmstart using decoder 56 |
| 4206 | // 9093: } |
| 4207 | 4, 0, // 9097: case 0x4: { |
| 4208 | OPC_CheckPredicate, 9, // 9099: check predicate 9 |
| 4209 | OPC_CheckField, 16, 5, 0, // 9101: check Inst[20:16] == 0x0 |
| 4210 | OPC_CheckField, 8, 6, 0, // 9105: check Inst[13:8] == 0x0 |
| 4211 | OPC_Decode, 216, 26, 166, 1, // 9109: decode to Y6_dmwait using decoder 166 |
| 4212 | // 9109: } |
| 4213 | // 9109: } // switch Inst[27:25] |
| 4214 | // 9109: } |
| 4215 | 2, 36, // 9114: case 0x2: { |
| 4216 | OPC_SwitchField, 25, 3, // 9116: switch Inst[27:25] { |
| 4217 | 3, 14, // 9119: case 0x3: { |
| 4218 | OPC_CheckPredicate, 9, // 9121: check predicate 9 |
| 4219 | OPC_CheckField, 13, 1, 0, // 9123: check Inst[13] == 0x0 |
| 4220 | OPC_CheckField, 0, 5, 0, // 9127: check Inst[4:0] == 0x0 |
| 4221 | OPC_Decode, 211, 26, 62, // 9131: decode to Y6_dmlink using decoder 62 |
| 4222 | // 9131: } |
| 4223 | 4, 0, // 9135: case 0x4: { |
| 4224 | OPC_CheckPredicate, 9, // 9137: check predicate 9 |
| 4225 | OPC_CheckField, 16, 5, 0, // 9139: check Inst[20:16] == 0x0 |
| 4226 | OPC_CheckField, 8, 6, 0, // 9143: check Inst[13:8] == 0x0 |
| 4227 | OPC_Decode, 213, 26, 166, 1, // 9147: decode to Y6_dmpoll using decoder 166 |
| 4228 | // 9147: } |
| 4229 | // 9147: } // switch Inst[27:25] |
| 4230 | // 9147: } |
| 4231 | 3, 19, // 9152: case 0x3: { |
| 4232 | OPC_CheckPredicate, 9, // 9154: check predicate 9 |
| 4233 | OPC_CheckField, 25, 3, 4, // 9156: check Inst[27:25] == 0x4 |
| 4234 | OPC_CheckField, 16, 5, 0, // 9160: check Inst[20:16] == 0x0 |
| 4235 | OPC_CheckField, 8, 6, 0, // 9164: check Inst[13:8] == 0x0 |
| 4236 | OPC_Decode, 212, 26, 166, 1, // 9168: decode to Y6_dmpause using decoder 166 |
| 4237 | // 9168: } |
| 4238 | 4, 0, // 9173: case 0x4: { |
| 4239 | OPC_CheckPredicate, 9, // 9175: check predicate 9 |
| 4240 | OPC_CheckField, 25, 3, 3, // 9177: check Inst[27:25] == 0x3 |
| 4241 | OPC_CheckField, 8, 6, 0, // 9181: check Inst[13:8] == 0x0 |
| 4242 | OPC_CheckField, 0, 5, 0, // 9185: check Inst[4:0] == 0x0 |
| 4243 | OPC_Decode, 214, 26, 56, // 9189: decode to Y6_dmresume using decoder 56 |
| 4244 | // 9189: } |
| 4245 | // 9189: } // switch Inst[7:5] |
| 4246 | // 9189: } |
| 4247 | 1, 91, // 9193: case 0x1: { |
| 4248 | OPC_SwitchField, 25, 3, // 9195: switch Inst[27:25] { |
| 4249 | 0, 8, // 9198: case 0x0: { |
| 4250 | OPC_CheckField, 0, 14, 0, // 9200: check Inst[13:0] == 0x0 |
| 4251 | OPC_Decode, 150, 26, 56, // 9204: decode to Y2_dcinva using decoder 56 |
| 4252 | // 9204: } |
| 4253 | 1, 8, // 9208: case 0x1: { |
| 4254 | OPC_CheckField, 0, 14, 0, // 9210: check Inst[13:0] == 0x0 |
| 4255 | OPC_Decode, 146, 26, 56, // 9214: decode to Y2_dccleanidx using decoder 56 |
| 4256 | // 9214: } |
| 4257 | 2, 8, // 9218: case 0x2: { |
| 4258 | OPC_CheckField, 5, 9, 0, // 9220: check Inst[13:5] == 0x0 |
| 4259 | OPC_Decode, 153, 26, 61, // 9224: decode to Y2_dctagr using decoder 61 |
| 4260 | // 9224: } |
| 4261 | 3, 8, // 9228: case 0x3: { |
| 4262 | OPC_CheckField, 0, 14, 0, // 9230: check Inst[13:0] == 0x0 |
| 4263 | OPC_Decode, 198, 26, 56, // 9234: decode to Y5_l2cleanidx using decoder 56 |
| 4264 | // 9234: } |
| 4265 | 4, 0, // 9238: case 0x4: { |
| 4266 | OPC_SwitchField, 0, 14, // 9240: switch Inst[13:0] { |
| 4267 | 0, 8, // 9243: case 0x0: { |
| 4268 | OPC_CheckField, 16, 5, 0, // 9245: check Inst[20:16] == 0x0 |
| 4269 | OPC_Decode, 170, 26, 63, // 9249: decode to Y2_l2kill using decoder 63 |
| 4270 | // 9249: } |
| 4271 | 128, 16, 8, // 9253: case 0x800: { |
| 4272 | OPC_CheckField, 16, 5, 0, // 9256: check Inst[20:16] == 0x0 |
| 4273 | OPC_Decode, 202, 26, 63, // 9260: decode to Y5_l2gunlock using decoder 63 |
| 4274 | // 9260: } |
| 4275 | 128, 32, 8, // 9264: case 0x1000: { |
| 4276 | OPC_CheckField, 16, 5, 0, // 9267: check Inst[20:16] == 0x0 |
| 4277 | OPC_Decode, 200, 26, 63, // 9271: decode to Y5_l2gclean using decoder 63 |
| 4278 | // 9271: } |
| 4279 | 128, 48, 0, // 9275: case 0x1800: { |
| 4280 | OPC_CheckField, 16, 5, 0, // 9278: check Inst[20:16] == 0x0 |
| 4281 | OPC_Decode, 201, 26, 63, // 9282: decode to Y5_l2gcleaninv using decoder 63 |
| 4282 | // 9282: } |
| 4283 | // 9282: } // switch Inst[13:0] |
| 4284 | // 9282: } |
| 4285 | // 9282: } // switch Inst[27:25] |
| 4286 | // 9282: } |
| 4287 | 2, 61, // 9286: case 0x2: { |
| 4288 | OPC_SwitchField, 25, 3, // 9288: switch Inst[27:25] { |
| 4289 | 0, 8, // 9291: case 0x0: { |
| 4290 | OPC_CheckField, 0, 14, 0, // 9293: check Inst[13:0] == 0x0 |
| 4291 | OPC_Decode, 147, 26, 56, // 9297: decode to Y2_dccleaninva using decoder 56 |
| 4292 | // 9297: } |
| 4293 | 1, 8, // 9301: case 0x1: { |
| 4294 | OPC_CheckField, 0, 14, 0, // 9303: check Inst[13:0] == 0x0 |
| 4295 | OPC_Decode, 151, 26, 56, // 9307: decode to Y2_dcinvidx using decoder 56 |
| 4296 | // 9307: } |
| 4297 | 2, 12, // 9311: case 0x2: { |
| 4298 | OPC_CheckField, 13, 1, 0, // 9313: check Inst[13] == 0x0 |
| 4299 | OPC_CheckField, 0, 8, 0, // 9317: check Inst[7:0] == 0x0 |
| 4300 | OPC_Decode, 191, 26, 62, // 9321: decode to Y4_l2tagw using decoder 62 |
| 4301 | // 9321: } |
| 4302 | 3, 8, // 9325: case 0x3: { |
| 4303 | OPC_CheckField, 0, 14, 0, // 9327: check Inst[13:0] == 0x0 |
| 4304 | OPC_Decode, 203, 26, 56, // 9331: decode to Y5_l2invidx using decoder 56 |
| 4305 | // 9331: } |
| 4306 | 4, 0, // 9335: case 0x4: { |
| 4307 | OPC_CheckField, 16, 5, 0, // 9337: check Inst[20:16] == 0x0 |
| 4308 | OPC_CheckField, 0, 14, 0, // 9341: check Inst[13:0] == 0x0 |
| 4309 | OPC_Decode, 177, 26, 63, // 9345: decode to Y2_syncht using decoder 63 |
| 4310 | // 9345: } |
| 4311 | // 9345: } // switch Inst[27:25] |
| 4312 | // 9345: } |
| 4313 | 3, 43, // 9349: case 0x3: { |
| 4314 | OPC_SwitchField, 25, 3, // 9351: switch Inst[27:25] { |
| 4315 | 1, 8, // 9354: case 0x1: { |
| 4316 | OPC_CheckField, 0, 14, 0, // 9356: check Inst[13:0] == 0x0 |
| 4317 | OPC_Decode, 148, 26, 56, // 9360: decode to Y2_dccleaninvidx using decoder 56 |
| 4318 | // 9360: } |
| 4319 | 2, 8, // 9364: case 0x2: { |
| 4320 | OPC_CheckField, 5, 9, 0, // 9366: check Inst[13:5] == 0x0 |
| 4321 | OPC_Decode, 190, 26, 61, // 9370: decode to Y4_l2tagr using decoder 61 |
| 4322 | // 9370: } |
| 4323 | 3, 8, // 9374: case 0x3: { |
| 4324 | OPC_CheckField, 0, 14, 0, // 9376: check Inst[13:0] == 0x0 |
| 4325 | OPC_Decode, 205, 26, 56, // 9380: decode to Y5_l2unlocka using decoder 56 |
| 4326 | // 9380: } |
| 4327 | 4, 0, // 9384: case 0x4: { |
| 4328 | OPC_CheckField, 0, 14, 0, // 9386: check Inst[13:0] == 0x0 |
| 4329 | OPC_Decode, 169, 26, 56, // 9390: decode to Y2_l2cleaninvidx using decoder 56 |
| 4330 | // 9390: } |
| 4331 | // 9390: } // switch Inst[27:25] |
| 4332 | // 9390: } |
| 4333 | 4, 29, // 9394: case 0x4: { |
| 4334 | OPC_SwitchField, 25, 3, // 9396: switch Inst[27:25] { |
| 4335 | 0, 9, // 9399: case 0x0: { |
| 4336 | OPC_CheckField, 11, 3, 0, // 9401: check Inst[13:11] == 0x0 |
| 4337 | OPC_Decode, 210, 16, 167, 1, // 9405: decode to S2_allocframe using decoder 167 |
| 4338 | // 9405: } |
| 4339 | 3, 0, // 9410: case 0x3: { |
| 4340 | OPC_CheckField, 13, 1, 0, // 9412: check Inst[13] == 0x0 |
| 4341 | OPC_CheckField, 0, 8, 0, // 9416: check Inst[7:0] == 0x0 |
| 4342 | OPC_Decode, 199, 26, 168, 1, // 9420: decode to Y5_l2fetch using decoder 168 |
| 4343 | // 9420: } |
| 4344 | // 9420: } // switch Inst[27:25] |
| 4345 | // 9420: } |
| 4346 | 5, 70, // 9425: case 0x5: { |
| 4347 | OPC_SwitchField, 2, 6, // 9427: switch Inst[7:2] { |
| 4348 | 0, 33, // 9430: case 0x0: { |
| 4349 | OPC_SwitchField, 25, 3, // 9432: switch Inst[27:25] { |
| 4350 | 0, 9, // 9435: case 0x0: { |
| 4351 | OPC_CheckField, 13, 1, 0, // 9437: check Inst[13] == 0x0 |
| 4352 | OPC_Decode, 194, 18, 169, 1, // 9441: decode to S2_storew_locked using decoder 169 |
| 4353 | // 9441: } |
| 4354 | 3, 0, // 9446: case 0x3: { |
| 4355 | OPC_CheckField, 16, 5, 0, // 9448: check Inst[20:16] == 0x0 |
| 4356 | OPC_CheckField, 13, 1, 0, // 9452: check Inst[13] == 0x0 |
| 4357 | OPC_CheckField, 0, 2, 0, // 9456: check Inst[1:0] == 0x0 |
| 4358 | OPC_Decode, 218, 26, 170, 1, // 9460: decode to Y6_l2gcleanpa using decoder 170 |
| 4359 | // 9460: } |
| 4360 | // 9460: } // switch Inst[27:25] |
| 4361 | // 9460: } |
| 4362 | 2, 14, // 9465: case 0x2: { |
| 4363 | OPC_CheckPredicate, 9, // 9467: check predicate 9 |
| 4364 | OPC_CheckField, 25, 3, 0, // 9469: check Inst[27:25] == 0x0 |
| 4365 | OPC_CheckField, 13, 1, 0, // 9473: check Inst[13] == 0x0 |
| 4366 | OPC_Decode, 195, 18, 62, // 9477: decode to S2_storew_rl_at_vi using decoder 62 |
| 4367 | // 9477: } |
| 4368 | 10, 0, // 9481: case 0xa: { |
| 4369 | OPC_CheckPredicate, 9, // 9483: check predicate 9 |
| 4370 | OPC_CheckField, 25, 3, 0, // 9485: check Inst[27:25] == 0x0 |
| 4371 | OPC_CheckField, 13, 1, 0, // 9489: check Inst[13] == 0x0 |
| 4372 | OPC_Decode, 196, 18, 62, // 9493: decode to S2_storew_rl_st_vi using decoder 62 |
| 4373 | // 9493: } |
| 4374 | // 9493: } // switch Inst[7:2] |
| 4375 | // 9493: } |
| 4376 | 6, 32, // 9497: case 0x6: { |
| 4377 | OPC_SwitchField, 25, 3, // 9499: switch Inst[27:25] { |
| 4378 | 0, 8, // 9502: case 0x0: { |
| 4379 | OPC_CheckField, 0, 14, 0, // 9504: check Inst[13:0] == 0x0 |
| 4380 | OPC_Decode, 155, 26, 56, // 9508: decode to Y2_dczeroa using decoder 56 |
| 4381 | // 9508: } |
| 4382 | 3, 0, // 9512: case 0x3: { |
| 4383 | OPC_CheckField, 16, 5, 0, // 9514: check Inst[20:16] == 0x0 |
| 4384 | OPC_CheckField, 13, 1, 0, // 9518: check Inst[13] == 0x0 |
| 4385 | OPC_CheckField, 0, 8, 0, // 9522: check Inst[7:0] == 0x0 |
| 4386 | OPC_Decode, 217, 26, 170, 1, // 9526: decode to Y6_l2gcleaninvpa using decoder 170 |
| 4387 | // 9526: } |
| 4388 | // 9526: } // switch Inst[27:25] |
| 4389 | // 9526: } |
| 4390 | 7, 99, // 9531: case 0x7: { |
| 4391 | OPC_SwitchField, 2, 6, // 9533: switch Inst[7:2] { |
| 4392 | 0, 28, // 9536: case 0x0: { |
| 4393 | OPC_SwitchField, 13, 1, // 9538: switch Inst[13] { |
| 4394 | 0, 9, // 9541: case 0x0: { |
| 4395 | OPC_CheckField, 25, 3, 0, // 9543: check Inst[27:25] == 0x0 |
| 4396 | OPC_Decode, 207, 19, 171, 1, // 9547: decode to S4_stored_locked using decoder 171 |
| 4397 | // 9547: } |
| 4398 | 1, 0, // 9552: case 0x1: { |
| 4399 | OPC_CheckField, 25, 3, 0, // 9554: check Inst[27:25] == 0x0 |
| 4400 | OPC_CheckField, 8, 5, 0, // 9558: check Inst[12:8] == 0x0 |
| 4401 | OPC_Decode, 204, 26, 117, // 9562: decode to Y5_l2locka using decoder 117 |
| 4402 | // 9562: } |
| 4403 | // 9562: } // switch Inst[13] |
| 4404 | // 9562: } |
| 4405 | 2, 15, // 9566: case 0x2: { |
| 4406 | OPC_CheckPredicate, 9, // 9568: check predicate 9 |
| 4407 | OPC_CheckField, 25, 3, 0, // 9570: check Inst[27:25] == 0x0 |
| 4408 | OPC_CheckField, 13, 1, 0, // 9574: check Inst[13] == 0x0 |
| 4409 | OPC_Decode, 208, 19, 168, 1, // 9578: decode to S4_stored_rl_at_vi using decoder 168 |
| 4410 | // 9578: } |
| 4411 | 3, 14, // 9583: case 0x3: { |
| 4412 | OPC_CheckPredicate, 9, // 9585: check predicate 9 |
| 4413 | OPC_CheckField, 25, 3, 0, // 9587: check Inst[27:25] == 0x0 |
| 4414 | OPC_CheckField, 13, 1, 0, // 9591: check Inst[13] == 0x0 |
| 4415 | OPC_Decode, 199, 16, 56, // 9595: decode to R6_release_at_vi using decoder 56 |
| 4416 | // 9595: } |
| 4417 | 10, 15, // 9599: case 0xa: { |
| 4418 | OPC_CheckPredicate, 9, // 9601: check predicate 9 |
| 4419 | OPC_CheckField, 25, 3, 0, // 9603: check Inst[27:25] == 0x0 |
| 4420 | OPC_CheckField, 13, 1, 0, // 9607: check Inst[13] == 0x0 |
| 4421 | OPC_Decode, 209, 19, 168, 1, // 9611: decode to S4_stored_rl_st_vi using decoder 168 |
| 4422 | // 9611: } |
| 4423 | 11, 0, // 9616: case 0xb: { |
| 4424 | OPC_CheckPredicate, 9, // 9618: check predicate 9 |
| 4425 | OPC_CheckField, 25, 3, 0, // 9620: check Inst[27:25] == 0x0 |
| 4426 | OPC_CheckField, 13, 1, 0, // 9624: check Inst[13] == 0x0 |
| 4427 | OPC_Decode, 200, 16, 56, // 9628: decode to R6_release_st_vi using decoder 56 |
| 4428 | // 9628: } |
| 4429 | // 9628: } // switch Inst[7:2] |
| 4430 | // 9628: } |
| 4431 | 8, 135, 1, // 9632: case 0x8: { |
| 4432 | OPC_SwitchField, 27, 1, // 9635: switch Inst[27] { |
| 4433 | 0, 5, // 9638: case 0x0: { |
| 4434 | OPC_Decode, 138, 18, 172, 1, // 9640: decode to S2_storerb_io using decoder 172 |
| 4435 | // 9640: } |
| 4436 | 1, 0, // 9645: case 0x1: { |
| 4437 | OPC_SwitchField, 25, 2, // 9647: switch Inst[26:25] { |
| 4438 | 0, 25, // 9650: case 0x0: { |
| 4439 | OPC_SwitchField, 0, 3, // 9652: switch Inst[2:0] { |
| 4440 | 0, 9, // 9655: case 0x0: { |
| 4441 | OPC_CheckField, 7, 1, 0, // 9657: check Inst[7] == 0x0 |
| 4442 | OPC_Decode, 140, 18, 173, 1, // 9661: decode to S2_storerb_pci using decoder 173 |
| 4443 | // 9661: } |
| 4444 | 2, 0, // 9666: case 0x2: { |
| 4445 | OPC_CheckField, 3, 5, 0, // 9668: check Inst[7:3] == 0x0 |
| 4446 | OPC_Decode, 141, 18, 174, 1, // 9672: decode to S2_storerb_pcr using decoder 174 |
| 4447 | // 9672: } |
| 4448 | // 9672: } // switch Inst[2:0] |
| 4449 | // 9672: } |
| 4450 | 1, 69, // 9677: case 0x1: { |
| 4451 | OPC_SwitchField, 2, 1, // 9679: switch Inst[2] { |
| 4452 | 0, 37, // 9682: case 0x0: { |
| 4453 | OPC_SwitchField, 7, 1, // 9684: switch Inst[7] { |
| 4454 | 0, 21, // 9687: case 0x0: { |
| 4455 | OPC_SwitchField, 13, 1, // 9689: switch Inst[13] { |
| 4456 | 0, 9, // 9692: case 0x0: { |
| 4457 | OPC_CheckField, 0, 2, 0, // 9694: check Inst[1:0] == 0x0 |
| 4458 | OPC_Decode, 142, 18, 175, 1, // 9698: decode to S2_storerb_pi using decoder 175 |
| 4459 | // 9698: } |
| 4460 | 1, 0, // 9703: case 0x1: { |
| 4461 | OPC_Decode, 222, 17, 176, 1, // 9705: decode to S2_pstorerbt_pi using decoder 176 |
| 4462 | // 9705: } |
| 4463 | // 9705: } // switch Inst[13] |
| 4464 | // 9705: } |
| 4465 | 1, 0, // 9710: case 0x1: { |
| 4466 | OPC_CheckField, 13, 1, 1, // 9712: check Inst[13] == 0x1 |
| 4467 | OPC_Decode, 223, 17, 176, 1, // 9716: decode to S2_pstorerbtnew_pi using decoder 176 |
| 4468 | // 9716: } |
| 4469 | // 9716: } // switch Inst[7] |
| 4470 | // 9716: } |
| 4471 | 1, 0, // 9721: case 0x1: { |
| 4472 | OPC_SwitchField, 7, 1, // 9723: switch Inst[7] { |
| 4473 | 0, 9, // 9726: case 0x0: { |
| 4474 | OPC_CheckField, 13, 1, 1, // 9728: check Inst[13] == 0x1 |
| 4475 | OPC_Decode, 213, 17, 176, 1, // 9732: decode to S2_pstorerbf_pi using decoder 176 |
| 4476 | // 9732: } |
| 4477 | 1, 0, // 9737: case 0x1: { |
| 4478 | OPC_CheckField, 13, 1, 1, // 9739: check Inst[13] == 0x1 |
| 4479 | OPC_Decode, 214, 17, 176, 1, // 9743: decode to S2_pstorerbfnew_pi using decoder 176 |
| 4480 | // 9743: } |
| 4481 | // 9743: } // switch Inst[7] |
| 4482 | // 9743: } |
| 4483 | // 9743: } // switch Inst[2] |
| 4484 | // 9743: } |
| 4485 | 2, 9, // 9748: case 0x2: { |
| 4486 | OPC_CheckField, 0, 8, 0, // 9750: check Inst[7:0] == 0x0 |
| 4487 | OPC_Decode, 143, 18, 174, 1, // 9754: decode to S2_storerb_pr using decoder 174 |
| 4488 | // 9754: } |
| 4489 | 3, 0, // 9759: case 0x3: { |
| 4490 | OPC_CheckField, 0, 8, 0, // 9761: check Inst[7:0] == 0x0 |
| 4491 | OPC_Decode, 139, 18, 174, 1, // 9765: decode to S2_storerb_pbr using decoder 174 |
| 4492 | // 9765: } |
| 4493 | // 9765: } // switch Inst[26:25] |
| 4494 | // 9765: } |
| 4495 | // 9765: } // switch Inst[27] |
| 4496 | // 9765: } |
| 4497 | 10, 135, 1, // 9770: case 0xa: { |
| 4498 | OPC_SwitchField, 27, 1, // 9773: switch Inst[27] { |
| 4499 | 0, 5, // 9776: case 0x0: { |
| 4500 | OPC_Decode, 166, 18, 177, 1, // 9778: decode to S2_storerh_io using decoder 177 |
| 4501 | // 9778: } |
| 4502 | 1, 0, // 9783: case 0x1: { |
| 4503 | OPC_SwitchField, 25, 2, // 9785: switch Inst[26:25] { |
| 4504 | 0, 25, // 9788: case 0x0: { |
| 4505 | OPC_SwitchField, 0, 3, // 9790: switch Inst[2:0] { |
| 4506 | 0, 9, // 9793: case 0x0: { |
| 4507 | OPC_CheckField, 7, 1, 0, // 9795: check Inst[7] == 0x0 |
| 4508 | OPC_Decode, 168, 18, 178, 1, // 9799: decode to S2_storerh_pci using decoder 178 |
| 4509 | // 9799: } |
| 4510 | 2, 0, // 9804: case 0x2: { |
| 4511 | OPC_CheckField, 3, 5, 0, // 9806: check Inst[7:3] == 0x0 |
| 4512 | OPC_Decode, 169, 18, 174, 1, // 9810: decode to S2_storerh_pcr using decoder 174 |
| 4513 | // 9810: } |
| 4514 | // 9810: } // switch Inst[2:0] |
| 4515 | // 9810: } |
| 4516 | 1, 69, // 9815: case 0x1: { |
| 4517 | OPC_SwitchField, 2, 1, // 9817: switch Inst[2] { |
| 4518 | 0, 37, // 9820: case 0x0: { |
| 4519 | OPC_SwitchField, 7, 1, // 9822: switch Inst[7] { |
| 4520 | 0, 21, // 9825: case 0x0: { |
| 4521 | OPC_SwitchField, 13, 1, // 9827: switch Inst[13] { |
| 4522 | 0, 9, // 9830: case 0x0: { |
| 4523 | OPC_CheckField, 0, 2, 0, // 9832: check Inst[1:0] == 0x0 |
| 4524 | OPC_Decode, 170, 18, 179, 1, // 9836: decode to S2_storerh_pi using decoder 179 |
| 4525 | // 9836: } |
| 4526 | 1, 0, // 9841: case 0x1: { |
| 4527 | OPC_Decode, 246, 17, 180, 1, // 9843: decode to S2_pstorerht_pi using decoder 180 |
| 4528 | // 9843: } |
| 4529 | // 9843: } // switch Inst[13] |
| 4530 | // 9843: } |
| 4531 | 1, 0, // 9848: case 0x1: { |
| 4532 | OPC_CheckField, 13, 1, 1, // 9850: check Inst[13] == 0x1 |
| 4533 | OPC_Decode, 247, 17, 180, 1, // 9854: decode to S2_pstorerhtnew_pi using decoder 180 |
| 4534 | // 9854: } |
| 4535 | // 9854: } // switch Inst[7] |
| 4536 | // 9854: } |
| 4537 | 1, 0, // 9859: case 0x1: { |
| 4538 | OPC_SwitchField, 7, 1, // 9861: switch Inst[7] { |
| 4539 | 0, 9, // 9864: case 0x0: { |
| 4540 | OPC_CheckField, 13, 1, 1, // 9866: check Inst[13] == 0x1 |
| 4541 | OPC_Decode, 237, 17, 180, 1, // 9870: decode to S2_pstorerhf_pi using decoder 180 |
| 4542 | // 9870: } |
| 4543 | 1, 0, // 9875: case 0x1: { |
| 4544 | OPC_CheckField, 13, 1, 1, // 9877: check Inst[13] == 0x1 |
| 4545 | OPC_Decode, 238, 17, 180, 1, // 9881: decode to S2_pstorerhfnew_pi using decoder 180 |
| 4546 | // 9881: } |
| 4547 | // 9881: } // switch Inst[7] |
| 4548 | // 9881: } |
| 4549 | // 9881: } // switch Inst[2] |
| 4550 | // 9881: } |
| 4551 | 2, 9, // 9886: case 0x2: { |
| 4552 | OPC_CheckField, 0, 8, 0, // 9888: check Inst[7:0] == 0x0 |
| 4553 | OPC_Decode, 171, 18, 174, 1, // 9892: decode to S2_storerh_pr using decoder 174 |
| 4554 | // 9892: } |
| 4555 | 3, 0, // 9897: case 0x3: { |
| 4556 | OPC_CheckField, 0, 8, 0, // 9899: check Inst[7:0] == 0x0 |
| 4557 | OPC_Decode, 167, 18, 174, 1, // 9903: decode to S2_storerh_pbr using decoder 174 |
| 4558 | // 9903: } |
| 4559 | // 9903: } // switch Inst[26:25] |
| 4560 | // 9903: } |
| 4561 | // 9903: } // switch Inst[27] |
| 4562 | // 9903: } |
| 4563 | 11, 135, 1, // 9908: case 0xb: { |
| 4564 | OPC_SwitchField, 27, 1, // 9911: switch Inst[27] { |
| 4565 | 0, 5, // 9914: case 0x0: { |
| 4566 | OPC_Decode, 159, 18, 177, 1, // 9916: decode to S2_storerf_io using decoder 177 |
| 4567 | // 9916: } |
| 4568 | 1, 0, // 9921: case 0x1: { |
| 4569 | OPC_SwitchField, 25, 2, // 9923: switch Inst[26:25] { |
| 4570 | 0, 25, // 9926: case 0x0: { |
| 4571 | OPC_SwitchField, 0, 3, // 9928: switch Inst[2:0] { |
| 4572 | 0, 9, // 9931: case 0x0: { |
| 4573 | OPC_CheckField, 7, 1, 0, // 9933: check Inst[7] == 0x0 |
| 4574 | OPC_Decode, 161, 18, 178, 1, // 9937: decode to S2_storerf_pci using decoder 178 |
| 4575 | // 9937: } |
| 4576 | 2, 0, // 9942: case 0x2: { |
| 4577 | OPC_CheckField, 3, 5, 0, // 9944: check Inst[7:3] == 0x0 |
| 4578 | OPC_Decode, 162, 18, 174, 1, // 9948: decode to S2_storerf_pcr using decoder 174 |
| 4579 | // 9948: } |
| 4580 | // 9948: } // switch Inst[2:0] |
| 4581 | // 9948: } |
| 4582 | 1, 69, // 9953: case 0x1: { |
| 4583 | OPC_SwitchField, 2, 1, // 9955: switch Inst[2] { |
| 4584 | 0, 37, // 9958: case 0x0: { |
| 4585 | OPC_SwitchField, 7, 1, // 9960: switch Inst[7] { |
| 4586 | 0, 21, // 9963: case 0x0: { |
| 4587 | OPC_SwitchField, 13, 1, // 9965: switch Inst[13] { |
| 4588 | 0, 9, // 9968: case 0x0: { |
| 4589 | OPC_CheckField, 0, 2, 0, // 9970: check Inst[1:0] == 0x0 |
| 4590 | OPC_Decode, 163, 18, 179, 1, // 9974: decode to S2_storerf_pi using decoder 179 |
| 4591 | // 9974: } |
| 4592 | 1, 0, // 9979: case 0x1: { |
| 4593 | OPC_Decode, 234, 17, 180, 1, // 9981: decode to S2_pstorerft_pi using decoder 180 |
| 4594 | // 9981: } |
| 4595 | // 9981: } // switch Inst[13] |
| 4596 | // 9981: } |
| 4597 | 1, 0, // 9986: case 0x1: { |
| 4598 | OPC_CheckField, 13, 1, 1, // 9988: check Inst[13] == 0x1 |
| 4599 | OPC_Decode, 235, 17, 180, 1, // 9992: decode to S2_pstorerftnew_pi using decoder 180 |
| 4600 | // 9992: } |
| 4601 | // 9992: } // switch Inst[7] |
| 4602 | // 9992: } |
| 4603 | 1, 0, // 9997: case 0x1: { |
| 4604 | OPC_SwitchField, 7, 1, // 9999: switch Inst[7] { |
| 4605 | 0, 9, // 10002: case 0x0: { |
| 4606 | OPC_CheckField, 13, 1, 1, // 10004: check Inst[13] == 0x1 |
| 4607 | OPC_Decode, 231, 17, 180, 1, // 10008: decode to S2_pstorerff_pi using decoder 180 |
| 4608 | // 10008: } |
| 4609 | 1, 0, // 10013: case 0x1: { |
| 4610 | OPC_CheckField, 13, 1, 1, // 10015: check Inst[13] == 0x1 |
| 4611 | OPC_Decode, 232, 17, 180, 1, // 10019: decode to S2_pstorerffnew_pi using decoder 180 |
| 4612 | // 10019: } |
| 4613 | // 10019: } // switch Inst[7] |
| 4614 | // 10019: } |
| 4615 | // 10019: } // switch Inst[2] |
| 4616 | // 10019: } |
| 4617 | 2, 9, // 10024: case 0x2: { |
| 4618 | OPC_CheckField, 0, 8, 0, // 10026: check Inst[7:0] == 0x0 |
| 4619 | OPC_Decode, 164, 18, 174, 1, // 10030: decode to S2_storerf_pr using decoder 174 |
| 4620 | // 10030: } |
| 4621 | 3, 0, // 10035: case 0x3: { |
| 4622 | OPC_CheckField, 0, 8, 0, // 10037: check Inst[7:0] == 0x0 |
| 4623 | OPC_Decode, 160, 18, 174, 1, // 10041: decode to S2_storerf_pbr using decoder 174 |
| 4624 | // 10041: } |
| 4625 | // 10041: } // switch Inst[26:25] |
| 4626 | // 10041: } |
| 4627 | // 10041: } // switch Inst[27] |
| 4628 | // 10041: } |
| 4629 | 12, 135, 1, // 10046: case 0xc: { |
| 4630 | OPC_SwitchField, 27, 1, // 10049: switch Inst[27] { |
| 4631 | 0, 5, // 10052: case 0x0: { |
| 4632 | OPC_Decode, 180, 18, 181, 1, // 10054: decode to S2_storeri_io using decoder 181 |
| 4633 | // 10054: } |
| 4634 | 1, 0, // 10059: case 0x1: { |
| 4635 | OPC_SwitchField, 25, 2, // 10061: switch Inst[26:25] { |
| 4636 | 0, 25, // 10064: case 0x0: { |
| 4637 | OPC_SwitchField, 0, 3, // 10066: switch Inst[2:0] { |
| 4638 | 0, 9, // 10069: case 0x0: { |
| 4639 | OPC_CheckField, 7, 1, 0, // 10071: check Inst[7] == 0x0 |
| 4640 | OPC_Decode, 182, 18, 182, 1, // 10075: decode to S2_storeri_pci using decoder 182 |
| 4641 | // 10075: } |
| 4642 | 2, 0, // 10080: case 0x2: { |
| 4643 | OPC_CheckField, 3, 5, 0, // 10082: check Inst[7:3] == 0x0 |
| 4644 | OPC_Decode, 183, 18, 174, 1, // 10086: decode to S2_storeri_pcr using decoder 174 |
| 4645 | // 10086: } |
| 4646 | // 10086: } // switch Inst[2:0] |
| 4647 | // 10086: } |
| 4648 | 1, 69, // 10091: case 0x1: { |
| 4649 | OPC_SwitchField, 2, 1, // 10093: switch Inst[2] { |
| 4650 | 0, 37, // 10096: case 0x0: { |
| 4651 | OPC_SwitchField, 7, 1, // 10098: switch Inst[7] { |
| 4652 | 0, 21, // 10101: case 0x0: { |
| 4653 | OPC_SwitchField, 13, 1, // 10103: switch Inst[13] { |
| 4654 | 0, 9, // 10106: case 0x0: { |
| 4655 | OPC_CheckField, 0, 2, 0, // 10108: check Inst[1:0] == 0x0 |
| 4656 | OPC_Decode, 184, 18, 183, 1, // 10112: decode to S2_storeri_pi using decoder 183 |
| 4657 | // 10112: } |
| 4658 | 1, 0, // 10117: case 0x1: { |
| 4659 | OPC_Decode, 130, 18, 184, 1, // 10119: decode to S2_pstorerit_pi using decoder 184 |
| 4660 | // 10119: } |
| 4661 | // 10119: } // switch Inst[13] |
| 4662 | // 10119: } |
| 4663 | 1, 0, // 10124: case 0x1: { |
| 4664 | OPC_CheckField, 13, 1, 1, // 10126: check Inst[13] == 0x1 |
| 4665 | OPC_Decode, 131, 18, 184, 1, // 10130: decode to S2_pstoreritnew_pi using decoder 184 |
| 4666 | // 10130: } |
| 4667 | // 10130: } // switch Inst[7] |
| 4668 | // 10130: } |
| 4669 | 1, 0, // 10135: case 0x1: { |
| 4670 | OPC_SwitchField, 7, 1, // 10137: switch Inst[7] { |
| 4671 | 0, 9, // 10140: case 0x0: { |
| 4672 | OPC_CheckField, 13, 1, 1, // 10142: check Inst[13] == 0x1 |
| 4673 | OPC_Decode, 249, 17, 184, 1, // 10146: decode to S2_pstorerif_pi using decoder 184 |
| 4674 | // 10146: } |
| 4675 | 1, 0, // 10151: case 0x1: { |
| 4676 | OPC_CheckField, 13, 1, 1, // 10153: check Inst[13] == 0x1 |
| 4677 | OPC_Decode, 250, 17, 184, 1, // 10157: decode to S2_pstorerifnew_pi using decoder 184 |
| 4678 | // 10157: } |
| 4679 | // 10157: } // switch Inst[7] |
| 4680 | // 10157: } |
| 4681 | // 10157: } // switch Inst[2] |
| 4682 | // 10157: } |
| 4683 | 2, 9, // 10162: case 0x2: { |
| 4684 | OPC_CheckField, 0, 8, 0, // 10164: check Inst[7:0] == 0x0 |
| 4685 | OPC_Decode, 185, 18, 174, 1, // 10168: decode to S2_storeri_pr using decoder 174 |
| 4686 | // 10168: } |
| 4687 | 3, 0, // 10173: case 0x3: { |
| 4688 | OPC_CheckField, 0, 8, 0, // 10175: check Inst[7:0] == 0x0 |
| 4689 | OPC_Decode, 181, 18, 174, 1, // 10179: decode to S2_storeri_pbr using decoder 174 |
| 4690 | // 10179: } |
| 4691 | // 10179: } // switch Inst[26:25] |
| 4692 | // 10179: } |
| 4693 | // 10179: } // switch Inst[27] |
| 4694 | // 10179: } |
| 4695 | 13, 160, 3, // 10184: case 0xd: { |
| 4696 | OPC_SwitchField, 11, 2, // 10187: switch Inst[12:11] { |
| 4697 | 0, 135, 1, // 10190: case 0x0: { |
| 4698 | OPC_SwitchField, 27, 1, // 10193: switch Inst[27] { |
| 4699 | 0, 5, // 10196: case 0x0: { |
| 4700 | OPC_Decode, 145, 18, 185, 1, // 10198: decode to S2_storerbnew_io using decoder 185 |
| 4701 | // 10198: } |
| 4702 | 1, 0, // 10203: case 0x1: { |
| 4703 | OPC_SwitchField, 25, 2, // 10205: switch Inst[26:25] { |
| 4704 | 0, 25, // 10208: case 0x0: { |
| 4705 | OPC_SwitchField, 0, 3, // 10210: switch Inst[2:0] { |
| 4706 | 0, 9, // 10213: case 0x0: { |
| 4707 | OPC_CheckField, 7, 1, 0, // 10215: check Inst[7] == 0x0 |
| 4708 | OPC_Decode, 147, 18, 186, 1, // 10219: decode to S2_storerbnew_pci using decoder 186 |
| 4709 | // 10219: } |
| 4710 | 2, 0, // 10224: case 0x2: { |
| 4711 | OPC_CheckField, 3, 5, 0, // 10226: check Inst[7:3] == 0x0 |
| 4712 | OPC_Decode, 148, 18, 187, 1, // 10230: decode to S2_storerbnew_pcr using decoder 187 |
| 4713 | // 10230: } |
| 4714 | // 10230: } // switch Inst[2:0] |
| 4715 | // 10230: } |
| 4716 | 1, 69, // 10235: case 0x1: { |
| 4717 | OPC_SwitchField, 2, 1, // 10237: switch Inst[2] { |
| 4718 | 0, 37, // 10240: case 0x0: { |
| 4719 | OPC_SwitchField, 7, 1, // 10242: switch Inst[7] { |
| 4720 | 0, 21, // 10245: case 0x0: { |
| 4721 | OPC_SwitchField, 13, 1, // 10247: switch Inst[13] { |
| 4722 | 0, 9, // 10250: case 0x0: { |
| 4723 | OPC_CheckField, 0, 2, 0, // 10252: check Inst[1:0] == 0x0 |
| 4724 | OPC_Decode, 149, 18, 188, 1, // 10256: decode to S2_storerbnew_pi using decoder 188 |
| 4725 | // 10256: } |
| 4726 | 1, 0, // 10261: case 0x1: { |
| 4727 | OPC_Decode, 219, 17, 189, 1, // 10263: decode to S2_pstorerbnewt_pi using decoder 189 |
| 4728 | // 10263: } |
| 4729 | // 10263: } // switch Inst[13] |
| 4730 | // 10263: } |
| 4731 | 1, 0, // 10268: case 0x1: { |
| 4732 | OPC_CheckField, 13, 1, 1, // 10270: check Inst[13] == 0x1 |
| 4733 | OPC_Decode, 220, 17, 189, 1, // 10274: decode to S2_pstorerbnewtnew_pi using decoder 189 |
| 4734 | // 10274: } |
| 4735 | // 10274: } // switch Inst[7] |
| 4736 | // 10274: } |
| 4737 | 1, 0, // 10279: case 0x1: { |
| 4738 | OPC_SwitchField, 7, 1, // 10281: switch Inst[7] { |
| 4739 | 0, 9, // 10284: case 0x0: { |
| 4740 | OPC_CheckField, 13, 1, 1, // 10286: check Inst[13] == 0x1 |
| 4741 | OPC_Decode, 216, 17, 189, 1, // 10290: decode to S2_pstorerbnewf_pi using decoder 189 |
| 4742 | // 10290: } |
| 4743 | 1, 0, // 10295: case 0x1: { |
| 4744 | OPC_CheckField, 13, 1, 1, // 10297: check Inst[13] == 0x1 |
| 4745 | OPC_Decode, 217, 17, 189, 1, // 10301: decode to S2_pstorerbnewfnew_pi using decoder 189 |
| 4746 | // 10301: } |
| 4747 | // 10301: } // switch Inst[7] |
| 4748 | // 10301: } |
| 4749 | // 10301: } // switch Inst[2] |
| 4750 | // 10301: } |
| 4751 | 2, 9, // 10306: case 0x2: { |
| 4752 | OPC_CheckField, 0, 8, 0, // 10308: check Inst[7:0] == 0x0 |
| 4753 | OPC_Decode, 150, 18, 187, 1, // 10312: decode to S2_storerbnew_pr using decoder 187 |
| 4754 | // 10312: } |
| 4755 | 3, 0, // 10317: case 0x3: { |
| 4756 | OPC_CheckField, 0, 8, 0, // 10319: check Inst[7:0] == 0x0 |
| 4757 | OPC_Decode, 146, 18, 187, 1, // 10323: decode to S2_storerbnew_pbr using decoder 187 |
| 4758 | // 10323: } |
| 4759 | // 10323: } // switch Inst[26:25] |
| 4760 | // 10323: } |
| 4761 | // 10323: } // switch Inst[27] |
| 4762 | // 10323: } |
| 4763 | 1, 135, 1, // 10328: case 0x1: { |
| 4764 | OPC_SwitchField, 27, 1, // 10331: switch Inst[27] { |
| 4765 | 0, 5, // 10334: case 0x0: { |
| 4766 | OPC_Decode, 173, 18, 190, 1, // 10336: decode to S2_storerhnew_io using decoder 190 |
| 4767 | // 10336: } |
| 4768 | 1, 0, // 10341: case 0x1: { |
| 4769 | OPC_SwitchField, 25, 2, // 10343: switch Inst[26:25] { |
| 4770 | 0, 25, // 10346: case 0x0: { |
| 4771 | OPC_SwitchField, 0, 3, // 10348: switch Inst[2:0] { |
| 4772 | 0, 9, // 10351: case 0x0: { |
| 4773 | OPC_CheckField, 7, 1, 0, // 10353: check Inst[7] == 0x0 |
| 4774 | OPC_Decode, 175, 18, 191, 1, // 10357: decode to S2_storerhnew_pci using decoder 191 |
| 4775 | // 10357: } |
| 4776 | 2, 0, // 10362: case 0x2: { |
| 4777 | OPC_CheckField, 3, 5, 0, // 10364: check Inst[7:3] == 0x0 |
| 4778 | OPC_Decode, 176, 18, 187, 1, // 10368: decode to S2_storerhnew_pcr using decoder 187 |
| 4779 | // 10368: } |
| 4780 | // 10368: } // switch Inst[2:0] |
| 4781 | // 10368: } |
| 4782 | 1, 69, // 10373: case 0x1: { |
| 4783 | OPC_SwitchField, 2, 1, // 10375: switch Inst[2] { |
| 4784 | 0, 37, // 10378: case 0x0: { |
| 4785 | OPC_SwitchField, 7, 1, // 10380: switch Inst[7] { |
| 4786 | 0, 21, // 10383: case 0x0: { |
| 4787 | OPC_SwitchField, 13, 1, // 10385: switch Inst[13] { |
| 4788 | 0, 9, // 10388: case 0x0: { |
| 4789 | OPC_CheckField, 0, 2, 0, // 10390: check Inst[1:0] == 0x0 |
| 4790 | OPC_Decode, 177, 18, 192, 1, // 10394: decode to S2_storerhnew_pi using decoder 192 |
| 4791 | // 10394: } |
| 4792 | 1, 0, // 10399: case 0x1: { |
| 4793 | OPC_Decode, 243, 17, 193, 1, // 10401: decode to S2_pstorerhnewt_pi using decoder 193 |
| 4794 | // 10401: } |
| 4795 | // 10401: } // switch Inst[13] |
| 4796 | // 10401: } |
| 4797 | 1, 0, // 10406: case 0x1: { |
| 4798 | OPC_CheckField, 13, 1, 1, // 10408: check Inst[13] == 0x1 |
| 4799 | OPC_Decode, 244, 17, 193, 1, // 10412: decode to S2_pstorerhnewtnew_pi using decoder 193 |
| 4800 | // 10412: } |
| 4801 | // 10412: } // switch Inst[7] |
| 4802 | // 10412: } |
| 4803 | 1, 0, // 10417: case 0x1: { |
| 4804 | OPC_SwitchField, 7, 1, // 10419: switch Inst[7] { |
| 4805 | 0, 9, // 10422: case 0x0: { |
| 4806 | OPC_CheckField, 13, 1, 1, // 10424: check Inst[13] == 0x1 |
| 4807 | OPC_Decode, 240, 17, 193, 1, // 10428: decode to S2_pstorerhnewf_pi using decoder 193 |
| 4808 | // 10428: } |
| 4809 | 1, 0, // 10433: case 0x1: { |
| 4810 | OPC_CheckField, 13, 1, 1, // 10435: check Inst[13] == 0x1 |
| 4811 | OPC_Decode, 241, 17, 193, 1, // 10439: decode to S2_pstorerhnewfnew_pi using decoder 193 |
| 4812 | // 10439: } |
| 4813 | // 10439: } // switch Inst[7] |
| 4814 | // 10439: } |
| 4815 | // 10439: } // switch Inst[2] |
| 4816 | // 10439: } |
| 4817 | 2, 9, // 10444: case 0x2: { |
| 4818 | OPC_CheckField, 0, 8, 0, // 10446: check Inst[7:0] == 0x0 |
| 4819 | OPC_Decode, 178, 18, 187, 1, // 10450: decode to S2_storerhnew_pr using decoder 187 |
| 4820 | // 10450: } |
| 4821 | 3, 0, // 10455: case 0x3: { |
| 4822 | OPC_CheckField, 0, 8, 0, // 10457: check Inst[7:0] == 0x0 |
| 4823 | OPC_Decode, 174, 18, 187, 1, // 10461: decode to S2_storerhnew_pbr using decoder 187 |
| 4824 | // 10461: } |
| 4825 | // 10461: } // switch Inst[26:25] |
| 4826 | // 10461: } |
| 4827 | // 10461: } // switch Inst[27] |
| 4828 | // 10461: } |
| 4829 | 2, 0, // 10466: case 0x2: { |
| 4830 | OPC_SwitchField, 27, 1, // 10468: switch Inst[27] { |
| 4831 | 0, 5, // 10471: case 0x0: { |
| 4832 | OPC_Decode, 187, 18, 194, 1, // 10473: decode to S2_storerinew_io using decoder 194 |
| 4833 | // 10473: } |
| 4834 | 1, 0, // 10478: case 0x1: { |
| 4835 | OPC_SwitchField, 25, 2, // 10480: switch Inst[26:25] { |
| 4836 | 0, 25, // 10483: case 0x0: { |
| 4837 | OPC_SwitchField, 0, 3, // 10485: switch Inst[2:0] { |
| 4838 | 0, 9, // 10488: case 0x0: { |
| 4839 | OPC_CheckField, 7, 1, 0, // 10490: check Inst[7] == 0x0 |
| 4840 | OPC_Decode, 189, 18, 195, 1, // 10494: decode to S2_storerinew_pci using decoder 195 |
| 4841 | // 10494: } |
| 4842 | 2, 0, // 10499: case 0x2: { |
| 4843 | OPC_CheckField, 3, 5, 0, // 10501: check Inst[7:3] == 0x0 |
| 4844 | OPC_Decode, 190, 18, 187, 1, // 10505: decode to S2_storerinew_pcr using decoder 187 |
| 4845 | // 10505: } |
| 4846 | // 10505: } // switch Inst[2:0] |
| 4847 | // 10505: } |
| 4848 | 1, 69, // 10510: case 0x1: { |
| 4849 | OPC_SwitchField, 2, 1, // 10512: switch Inst[2] { |
| 4850 | 0, 37, // 10515: case 0x0: { |
| 4851 | OPC_SwitchField, 7, 1, // 10517: switch Inst[7] { |
| 4852 | 0, 21, // 10520: case 0x0: { |
| 4853 | OPC_SwitchField, 13, 1, // 10522: switch Inst[13] { |
| 4854 | 0, 9, // 10525: case 0x0: { |
| 4855 | OPC_CheckField, 0, 2, 0, // 10527: check Inst[1:0] == 0x0 |
| 4856 | OPC_Decode, 191, 18, 196, 1, // 10531: decode to S2_storerinew_pi using decoder 196 |
| 4857 | // 10531: } |
| 4858 | 1, 0, // 10536: case 0x1: { |
| 4859 | OPC_Decode, 255, 17, 197, 1, // 10538: decode to S2_pstorerinewt_pi using decoder 197 |
| 4860 | // 10538: } |
| 4861 | // 10538: } // switch Inst[13] |
| 4862 | // 10538: } |
| 4863 | 1, 0, // 10543: case 0x1: { |
| 4864 | OPC_CheckField, 13, 1, 1, // 10545: check Inst[13] == 0x1 |
| 4865 | OPC_Decode, 128, 18, 197, 1, // 10549: decode to S2_pstorerinewtnew_pi using decoder 197 |
| 4866 | // 10549: } |
| 4867 | // 10549: } // switch Inst[7] |
| 4868 | // 10549: } |
| 4869 | 1, 0, // 10554: case 0x1: { |
| 4870 | OPC_SwitchField, 7, 1, // 10556: switch Inst[7] { |
| 4871 | 0, 9, // 10559: case 0x0: { |
| 4872 | OPC_CheckField, 13, 1, 1, // 10561: check Inst[13] == 0x1 |
| 4873 | OPC_Decode, 252, 17, 197, 1, // 10565: decode to S2_pstorerinewf_pi using decoder 197 |
| 4874 | // 10565: } |
| 4875 | 1, 0, // 10570: case 0x1: { |
| 4876 | OPC_CheckField, 13, 1, 1, // 10572: check Inst[13] == 0x1 |
| 4877 | OPC_Decode, 253, 17, 197, 1, // 10576: decode to S2_pstorerinewfnew_pi using decoder 197 |
| 4878 | // 10576: } |
| 4879 | // 10576: } // switch Inst[7] |
| 4880 | // 10576: } |
| 4881 | // 10576: } // switch Inst[2] |
| 4882 | // 10576: } |
| 4883 | 2, 9, // 10581: case 0x2: { |
| 4884 | OPC_CheckField, 0, 8, 0, // 10583: check Inst[7:0] == 0x0 |
| 4885 | OPC_Decode, 192, 18, 187, 1, // 10587: decode to S2_storerinew_pr using decoder 187 |
| 4886 | // 10587: } |
| 4887 | 3, 0, // 10592: case 0x3: { |
| 4888 | OPC_CheckField, 0, 8, 0, // 10594: check Inst[7:0] == 0x0 |
| 4889 | OPC_Decode, 188, 18, 187, 1, // 10598: decode to S2_storerinew_pbr using decoder 187 |
| 4890 | // 10598: } |
| 4891 | // 10598: } // switch Inst[26:25] |
| 4892 | // 10598: } |
| 4893 | // 10598: } // switch Inst[27] |
| 4894 | // 10598: } |
| 4895 | // 10598: } // switch Inst[12:11] |
| 4896 | // 10598: } |
| 4897 | 14, 0, // 10603: case 0xe: { |
| 4898 | OPC_SwitchField, 27, 1, // 10605: switch Inst[27] { |
| 4899 | 0, 5, // 10608: case 0x0: { |
| 4900 | OPC_Decode, 152, 18, 198, 1, // 10610: decode to S2_storerd_io using decoder 198 |
| 4901 | // 10610: } |
| 4902 | 1, 0, // 10615: case 0x1: { |
| 4903 | OPC_SwitchField, 25, 2, // 10617: switch Inst[26:25] { |
| 4904 | 0, 25, // 10620: case 0x0: { |
| 4905 | OPC_SwitchField, 0, 3, // 10622: switch Inst[2:0] { |
| 4906 | 0, 9, // 10625: case 0x0: { |
| 4907 | OPC_CheckField, 7, 1, 0, // 10627: check Inst[7] == 0x0 |
| 4908 | OPC_Decode, 154, 18, 199, 1, // 10631: decode to S2_storerd_pci using decoder 199 |
| 4909 | // 10631: } |
| 4910 | 2, 0, // 10636: case 0x2: { |
| 4911 | OPC_CheckField, 3, 5, 0, // 10638: check Inst[7:3] == 0x0 |
| 4912 | OPC_Decode, 155, 18, 200, 1, // 10642: decode to S2_storerd_pcr using decoder 200 |
| 4913 | // 10642: } |
| 4914 | // 10642: } // switch Inst[2:0] |
| 4915 | // 10642: } |
| 4916 | 1, 69, // 10647: case 0x1: { |
| 4917 | OPC_SwitchField, 2, 1, // 10649: switch Inst[2] { |
| 4918 | 0, 37, // 10652: case 0x0: { |
| 4919 | OPC_SwitchField, 7, 1, // 10654: switch Inst[7] { |
| 4920 | 0, 21, // 10657: case 0x0: { |
| 4921 | OPC_SwitchField, 13, 1, // 10659: switch Inst[13] { |
| 4922 | 0, 9, // 10662: case 0x0: { |
| 4923 | OPC_CheckField, 0, 2, 0, // 10664: check Inst[1:0] == 0x0 |
| 4924 | OPC_Decode, 156, 18, 201, 1, // 10668: decode to S2_storerd_pi using decoder 201 |
| 4925 | // 10668: } |
| 4926 | 1, 0, // 10673: case 0x1: { |
| 4927 | OPC_Decode, 228, 17, 202, 1, // 10675: decode to S2_pstorerdt_pi using decoder 202 |
| 4928 | // 10675: } |
| 4929 | // 10675: } // switch Inst[13] |
| 4930 | // 10675: } |
| 4931 | 1, 0, // 10680: case 0x1: { |
| 4932 | OPC_CheckField, 13, 1, 1, // 10682: check Inst[13] == 0x1 |
| 4933 | OPC_Decode, 229, 17, 202, 1, // 10686: decode to S2_pstorerdtnew_pi using decoder 202 |
| 4934 | // 10686: } |
| 4935 | // 10686: } // switch Inst[7] |
| 4936 | // 10686: } |
| 4937 | 1, 0, // 10691: case 0x1: { |
| 4938 | OPC_SwitchField, 7, 1, // 10693: switch Inst[7] { |
| 4939 | 0, 9, // 10696: case 0x0: { |
| 4940 | OPC_CheckField, 13, 1, 1, // 10698: check Inst[13] == 0x1 |
| 4941 | OPC_Decode, 225, 17, 202, 1, // 10702: decode to S2_pstorerdf_pi using decoder 202 |
| 4942 | // 10702: } |
| 4943 | 1, 0, // 10707: case 0x1: { |
| 4944 | OPC_CheckField, 13, 1, 1, // 10709: check Inst[13] == 0x1 |
| 4945 | OPC_Decode, 226, 17, 202, 1, // 10713: decode to S2_pstorerdfnew_pi using decoder 202 |
| 4946 | // 10713: } |
| 4947 | // 10713: } // switch Inst[7] |
| 4948 | // 10713: } |
| 4949 | // 10713: } // switch Inst[2] |
| 4950 | // 10713: } |
| 4951 | 2, 9, // 10718: case 0x2: { |
| 4952 | OPC_CheckField, 0, 8, 0, // 10720: check Inst[7:0] == 0x0 |
| 4953 | OPC_Decode, 157, 18, 200, 1, // 10724: decode to S2_storerd_pr using decoder 200 |
| 4954 | // 10724: } |
| 4955 | 3, 0, // 10729: case 0x3: { |
| 4956 | OPC_CheckField, 0, 8, 0, // 10731: check Inst[7:0] == 0x0 |
| 4957 | OPC_Decode, 153, 18, 200, 1, // 10735: decode to S2_storerd_pbr using decoder 200 |
| 4958 | // 10735: } |
| 4959 | // 10735: } // switch Inst[26:25] |
| 4960 | // 10735: } |
| 4961 | // 10735: } // switch Inst[27] |
| 4962 | // 10735: } |
| 4963 | // 10735: } // switch Inst[24:21] |
| 4964 | // 10735: } |
| 4965 | 11, 5, // 10740: case 0xb: { |
| 4966 | OPC_Decode, 179, 7, 203, 1, // 10742: decode to A2_addi using decoder 203 |
| 4967 | // 10742: } |
| 4968 | 12, 181, 12, // 10747: case 0xc: { |
| 4969 | OPC_SwitchField, 21, 7, // 10750: switch Inst[27:21] { |
| 4970 | 0, 9, // 10753: case 0x0: { |
| 4971 | OPC_CheckField, 13, 1, 0, // 10755: check Inst[13] == 0x0 |
| 4972 | OPC_Decode, 207, 18, 204, 1, // 10759: decode to S2_valignib using decoder 204 |
| 4973 | // 10759: } |
| 4974 | 4, 9, // 10764: case 0x4: { |
| 4975 | OPC_CheckField, 13, 1, 0, // 10766: check Inst[13] == 0x0 |
| 4976 | OPC_Decode, 224, 18, 205, 1, // 10770: decode to S2_vspliceib using decoder 205 |
| 4977 | // 10770: } |
| 4978 | 8, 47, // 10775: case 0x8: { |
| 4979 | OPC_SwitchField, 5, 3, // 10777: switch Inst[7:5] { |
| 4980 | 0, 9, // 10780: case 0x0: { |
| 4981 | OPC_CheckField, 13, 1, 0, // 10782: check Inst[13] == 0x0 |
| 4982 | OPC_Decode, 162, 17, 206, 1, // 10786: decode to S2_extractup_rp using decoder 206 |
| 4983 | // 10786: } |
| 4984 | 2, 9, // 10791: case 0x2: { |
| 4985 | OPC_CheckField, 13, 1, 0, // 10793: check Inst[13] == 0x0 |
| 4986 | OPC_Decode, 134, 18, 206, 1, // 10797: decode to S2_shuffeb using decoder 206 |
| 4987 | // 10797: } |
| 4988 | 4, 9, // 10802: case 0x4: { |
| 4989 | OPC_CheckField, 13, 1, 0, // 10804: check Inst[13] == 0x0 |
| 4990 | OPC_Decode, 136, 18, 207, 1, // 10808: decode to S2_shuffob using decoder 207 |
| 4991 | // 10808: } |
| 4992 | 6, 0, // 10813: case 0x6: { |
| 4993 | OPC_CheckField, 13, 1, 0, // 10815: check Inst[13] == 0x0 |
| 4994 | OPC_Decode, 135, 18, 206, 1, // 10819: decode to S2_shuffeh using decoder 206 |
| 4995 | // 10819: } |
| 4996 | // 10819: } // switch Inst[7:5] |
| 4997 | // 10819: } |
| 4998 | 10, 58, // 10824: case 0xa: { |
| 4999 | OPC_SwitchField, 5, 3, // 10826: switch Inst[7:5] { |
| 5000 | 0, 9, // 10829: case 0x0: { |
| 5001 | OPC_CheckField, 13, 1, 0, // 10831: check Inst[13] == 0x0 |
| 5002 | OPC_Decode, 128, 20, 206, 1, // 10835: decode to S4_vxaddsubw using decoder 206 |
| 5003 | // 10835: } |
| 5004 | 1, 9, // 10840: case 0x1: { |
| 5005 | OPC_CheckField, 13, 1, 0, // 10842: check Inst[13] == 0x0 |
| 5006 | OPC_Decode, 168, 9, 208, 1, // 10846: decode to A5_vaddhubs using decoder 208 |
| 5007 | // 10846: } |
| 5008 | 2, 9, // 10851: case 0x2: { |
| 5009 | OPC_CheckField, 13, 1, 0, // 10853: check Inst[13] == 0x0 |
| 5010 | OPC_Decode, 131, 20, 206, 1, // 10857: decode to S4_vxsubaddw using decoder 206 |
| 5011 | // 10857: } |
| 5012 | 4, 9, // 10862: case 0x4: { |
| 5013 | OPC_CheckField, 13, 1, 0, // 10864: check Inst[13] == 0x0 |
| 5014 | OPC_Decode, 254, 19, 206, 1, // 10868: decode to S4_vxaddsubh using decoder 206 |
| 5015 | // 10868: } |
| 5016 | 6, 0, // 10873: case 0x6: { |
| 5017 | OPC_CheckField, 13, 1, 0, // 10875: check Inst[13] == 0x0 |
| 5018 | OPC_Decode, 129, 20, 206, 1, // 10879: decode to S4_vxsubaddh using decoder 206 |
| 5019 | // 10879: } |
| 5020 | // 10879: } // switch Inst[7:5] |
| 5021 | // 10879: } |
| 5022 | 12, 73, // 10884: case 0xc: { |
| 5023 | OPC_SwitchField, 5, 3, // 10886: switch Inst[7:5] { |
| 5024 | 0, 9, // 10889: case 0x0: { |
| 5025 | OPC_CheckField, 13, 1, 0, // 10891: check Inst[13] == 0x0 |
| 5026 | OPC_Decode, 137, 18, 207, 1, // 10895: decode to S2_shuffoh using decoder 207 |
| 5027 | // 10895: } |
| 5028 | 2, 9, // 10900: case 0x2: { |
| 5029 | OPC_CheckField, 13, 1, 0, // 10902: check Inst[13] == 0x0 |
| 5030 | OPC_Decode, 229, 18, 206, 1, // 10906: decode to S2_vtrunewh using decoder 206 |
| 5031 | // 10906: } |
| 5032 | 3, 11, // 10911: case 0x3: { |
| 5033 | OPC_CheckPredicate, 7, // 10913: check predicate 7 |
| 5034 | OPC_CheckField, 13, 1, 0, // 10915: check Inst[13] == 0x0 |
| 5035 | OPC_Decode, 149, 20, 206, 1, // 10919: decode to S6_vtrunehb_ppp using decoder 206 |
| 5036 | // 10919: } |
| 5037 | 4, 9, // 10924: case 0x4: { |
| 5038 | OPC_CheckField, 13, 1, 0, // 10926: check Inst[13] == 0x0 |
| 5039 | OPC_Decode, 231, 18, 206, 1, // 10930: decode to S2_vtrunowh using decoder 206 |
| 5040 | // 10930: } |
| 5041 | 5, 11, // 10935: case 0x5: { |
| 5042 | OPC_CheckPredicate, 7, // 10937: check predicate 7 |
| 5043 | OPC_CheckField, 13, 1, 0, // 10939: check Inst[13] == 0x0 |
| 5044 | OPC_Decode, 150, 20, 206, 1, // 10943: decode to S6_vtrunohb_ppp using decoder 206 |
| 5045 | // 10943: } |
| 5046 | 6, 0, // 10948: case 0x6: { |
| 5047 | OPC_CheckField, 13, 1, 0, // 10950: check Inst[13] == 0x0 |
| 5048 | OPC_Decode, 168, 17, 206, 1, // 10954: decode to S2_lfsp using decoder 206 |
| 5049 | // 10954: } |
| 5050 | // 10954: } // switch Inst[7:5] |
| 5051 | // 10954: } |
| 5052 | 14, 49, // 10959: case 0xe: { |
| 5053 | OPC_SwitchField, 5, 3, // 10961: switch Inst[7:5] { |
| 5054 | 0, 9, // 10964: case 0x0: { |
| 5055 | OPC_CheckField, 13, 1, 0, // 10966: check Inst[13] == 0x0 |
| 5056 | OPC_Decode, 255, 19, 206, 1, // 10970: decode to S4_vxaddsubhr using decoder 206 |
| 5057 | // 10970: } |
| 5058 | 2, 9, // 10975: case 0x2: { |
| 5059 | OPC_CheckField, 13, 1, 0, // 10977: check Inst[13] == 0x0 |
| 5060 | OPC_Decode, 130, 20, 206, 1, // 10981: decode to S4_vxsubaddhr using decoder 206 |
| 5061 | // 10981: } |
| 5062 | 4, 9, // 10986: case 0x4: { |
| 5063 | OPC_CheckField, 13, 1, 0, // 10988: check Inst[13] == 0x0 |
| 5064 | OPC_Decode, 245, 18, 206, 1, // 10992: decode to S4_extractp_rp using decoder 206 |
| 5065 | // 10992: } |
| 5066 | 6, 0, // 10997: case 0x6: { |
| 5067 | OPC_CheckPredicate, 10, // 10999: check predicate 10 |
| 5068 | OPC_CheckField, 13, 1, 0, // 11001: check Inst[13] == 0x0 |
| 5069 | OPC_Decode, 144, 17, 206, 1, // 11005: decode to S2_cabacdecbin using decoder 206 |
| 5070 | // 11005: } |
| 5071 | // 11005: } // switch Inst[7:5] |
| 5072 | // 11005: } |
| 5073 | 16, 13, // 11010: case 0x10: { |
| 5074 | OPC_CheckField, 13, 1, 0, // 11012: check Inst[13] == 0x0 |
| 5075 | OPC_CheckField, 7, 1, 0, // 11016: check Inst[7] == 0x0 |
| 5076 | OPC_Decode, 208, 18, 209, 1, // 11020: decode to S2_valignrb using decoder 209 |
| 5077 | // 11020: } |
| 5078 | 20, 13, // 11025: case 0x14: { |
| 5079 | OPC_CheckField, 13, 1, 0, // 11027: check Inst[13] == 0x0 |
| 5080 | OPC_CheckField, 7, 1, 0, // 11031: check Inst[7] == 0x0 |
| 5081 | OPC_Decode, 225, 18, 210, 1, // 11035: decode to S2_vsplicerb using decoder 210 |
| 5082 | // 11035: } |
| 5083 | 22, 13, // 11040: case 0x16: { |
| 5084 | OPC_CheckField, 13, 1, 0, // 11042: check Inst[13] == 0x0 |
| 5085 | OPC_CheckField, 7, 1, 0, // 11046: check Inst[7] == 0x0 |
| 5086 | OPC_Decode, 212, 8, 211, 1, // 11050: decode to A4_addp_c using decoder 211 |
| 5087 | // 11050: } |
| 5088 | 23, 13, // 11055: case 0x17: { |
| 5089 | OPC_CheckField, 13, 1, 0, // 11057: check Inst[13] == 0x0 |
| 5090 | OPC_CheckField, 7, 1, 0, // 11061: check Inst[7] == 0x0 |
| 5091 | OPC_Decode, 144, 9, 211, 1, // 11065: decode to A4_subp_c using decoder 211 |
| 5092 | // 11065: } |
| 5093 | 24, 47, // 11070: case 0x18: { |
| 5094 | OPC_SwitchField, 5, 3, // 11072: switch Inst[7:5] { |
| 5095 | 0, 9, // 11075: case 0x0: { |
| 5096 | OPC_CheckField, 13, 1, 0, // 11077: check Inst[13] == 0x0 |
| 5097 | OPC_Decode, 141, 17, 212, 1, // 11081: decode to S2_asr_r_vw using decoder 212 |
| 5098 | // 11081: } |
| 5099 | 2, 9, // 11086: case 0x2: { |
| 5100 | OPC_CheckField, 13, 1, 0, // 11088: check Inst[13] == 0x0 |
| 5101 | OPC_Decode, 208, 17, 212, 1, // 11092: decode to S2_lsr_r_vw using decoder 212 |
| 5102 | // 11092: } |
| 5103 | 4, 9, // 11097: case 0x4: { |
| 5104 | OPC_CheckField, 13, 1, 0, // 11099: check Inst[13] == 0x0 |
| 5105 | OPC_Decode, 239, 16, 212, 1, // 11103: decode to S2_asl_r_vw using decoder 212 |
| 5106 | // 11103: } |
| 5107 | 6, 0, // 11108: case 0x6: { |
| 5108 | OPC_CheckField, 13, 1, 0, // 11110: check Inst[13] == 0x0 |
| 5109 | OPC_Decode, 181, 17, 212, 1, // 11114: decode to S2_lsl_r_vw using decoder 212 |
| 5110 | // 11114: } |
| 5111 | // 11114: } // switch Inst[7:5] |
| 5112 | // 11114: } |
| 5113 | 26, 47, // 11119: case 0x1a: { |
| 5114 | OPC_SwitchField, 5, 3, // 11121: switch Inst[7:5] { |
| 5115 | 0, 9, // 11124: case 0x0: { |
| 5116 | OPC_CheckField, 13, 1, 0, // 11126: check Inst[13] == 0x0 |
| 5117 | OPC_Decode, 140, 17, 212, 1, // 11130: decode to S2_asr_r_vh using decoder 212 |
| 5118 | // 11130: } |
| 5119 | 2, 9, // 11135: case 0x2: { |
| 5120 | OPC_CheckField, 13, 1, 0, // 11137: check Inst[13] == 0x0 |
| 5121 | OPC_Decode, 207, 17, 212, 1, // 11141: decode to S2_lsr_r_vh using decoder 212 |
| 5122 | // 11141: } |
| 5123 | 4, 9, // 11146: case 0x4: { |
| 5124 | OPC_CheckField, 13, 1, 0, // 11148: check Inst[13] == 0x0 |
| 5125 | OPC_Decode, 238, 16, 212, 1, // 11152: decode to S2_asl_r_vh using decoder 212 |
| 5126 | // 11152: } |
| 5127 | 6, 0, // 11157: case 0x6: { |
| 5128 | OPC_CheckField, 13, 1, 0, // 11159: check Inst[13] == 0x0 |
| 5129 | OPC_Decode, 180, 17, 212, 1, // 11163: decode to S2_lsl_r_vh using decoder 212 |
| 5130 | // 11163: } |
| 5131 | // 11163: } // switch Inst[7:5] |
| 5132 | // 11163: } |
| 5133 | 28, 47, // 11168: case 0x1c: { |
| 5134 | OPC_SwitchField, 5, 3, // 11170: switch Inst[7:5] { |
| 5135 | 0, 9, // 11173: case 0x0: { |
| 5136 | OPC_CheckField, 13, 1, 0, // 11175: check Inst[13] == 0x0 |
| 5137 | OPC_Decode, 255, 16, 212, 1, // 11179: decode to S2_asr_r_p using decoder 212 |
| 5138 | // 11179: } |
| 5139 | 2, 9, // 11184: case 0x2: { |
| 5140 | OPC_CheckField, 13, 1, 0, // 11186: check Inst[13] == 0x0 |
| 5141 | OPC_Decode, 196, 17, 212, 1, // 11190: decode to S2_lsr_r_p using decoder 212 |
| 5142 | // 11190: } |
| 5143 | 4, 9, // 11195: case 0x4: { |
| 5144 | OPC_CheckField, 13, 1, 0, // 11197: check Inst[13] == 0x0 |
| 5145 | OPC_Decode, 226, 16, 212, 1, // 11201: decode to S2_asl_r_p using decoder 212 |
| 5146 | // 11201: } |
| 5147 | 6, 0, // 11206: case 0x6: { |
| 5148 | OPC_CheckField, 13, 1, 0, // 11208: check Inst[13] == 0x0 |
| 5149 | OPC_Decode, 169, 17, 212, 1, // 11212: decode to S2_lsl_r_p using decoder 212 |
| 5150 | // 11212: } |
| 5151 | // 11212: } // switch Inst[7:5] |
| 5152 | // 11212: } |
| 5153 | 30, 40, // 11217: case 0x1e: { |
| 5154 | OPC_SwitchField, 6, 2, // 11219: switch Inst[7:6] { |
| 5155 | 0, 13, // 11222: case 0x0: { |
| 5156 | OPC_CheckField, 13, 1, 0, // 11224: check Inst[13] == 0x0 |
| 5157 | OPC_CheckField, 5, 1, 0, // 11228: check Inst[5] == 0x0 |
| 5158 | OPC_Decode, 210, 18, 212, 1, // 11232: decode to S2_vcrotate using decoder 212 |
| 5159 | // 11232: } |
| 5160 | 1, 13, // 11237: case 0x1: { |
| 5161 | OPC_CheckField, 13, 1, 0, // 11239: check Inst[13] == 0x0 |
| 5162 | OPC_CheckField, 5, 1, 0, // 11243: check Inst[5] == 0x0 |
| 5163 | OPC_Decode, 209, 18, 212, 1, // 11247: decode to S2_vcnegh using decoder 212 |
| 5164 | // 11247: } |
| 5165 | 3, 0, // 11252: case 0x3: { |
| 5166 | OPC_Decode, 252, 19, 213, 1, // 11254: decode to S4_vrcrotate using decoder 213 |
| 5167 | // 11254: } |
| 5168 | // 11254: } // switch Inst[7:6] |
| 5169 | // 11254: } |
| 5170 | 32, 9, // 11259: case 0x20: { |
| 5171 | OPC_CheckField, 13, 1, 0, // 11261: check Inst[13] == 0x0 |
| 5172 | OPC_Decode, 209, 16, 214, 1, // 11265: decode to S2_addasl_rrri using decoder 214 |
| 5173 | // 11265: } |
| 5174 | 40, 53, // 11270: case 0x28: { |
| 5175 | OPC_SwitchField, 5, 3, // 11272: switch Inst[7:5] { |
| 5176 | 2, 8, // 11275: case 0x2: { |
| 5177 | OPC_CheckField, 13, 1, 0, // 11277: check Inst[13] == 0x0 |
| 5178 | OPC_Decode, 139, 17, 88, // 11281: decode to S2_asr_r_svw_trun using decoder 88 |
| 5179 | // 11281: } |
| 5180 | 4, 8, // 11285: case 0x4: { |
| 5181 | OPC_CheckField, 13, 1, 0, // 11287: check Inst[13] == 0x0 |
| 5182 | OPC_Decode, 244, 15, 88, // 11291: decode to M4_cmpyi_wh using decoder 88 |
| 5183 | // 11291: } |
| 5184 | 5, 8, // 11295: case 0x5: { |
| 5185 | OPC_CheckField, 13, 1, 0, // 11297: check Inst[13] == 0x0 |
| 5186 | OPC_Decode, 245, 15, 88, // 11301: decode to M4_cmpyi_whc using decoder 88 |
| 5187 | // 11301: } |
| 5188 | 6, 8, // 11305: case 0x6: { |
| 5189 | OPC_CheckField, 13, 1, 0, // 11307: check Inst[13] == 0x0 |
| 5190 | OPC_Decode, 246, 15, 88, // 11311: decode to M4_cmpyr_wh using decoder 88 |
| 5191 | // 11311: } |
| 5192 | 7, 0, // 11315: case 0x7: { |
| 5193 | OPC_CheckField, 13, 1, 0, // 11317: check Inst[13] == 0x0 |
| 5194 | OPC_Decode, 247, 15, 88, // 11321: decode to M4_cmpyr_whc using decoder 88 |
| 5195 | // 11321: } |
| 5196 | // 11321: } // switch Inst[7:5] |
| 5197 | // 11321: } |
| 5198 | 48, 25, // 11325: case 0x30: { |
| 5199 | OPC_SwitchField, 5, 3, // 11327: switch Inst[7:5] { |
| 5200 | 0, 9, // 11330: case 0x0: { |
| 5201 | OPC_CheckField, 13, 1, 0, // 11332: check Inst[13] == 0x0 |
| 5202 | OPC_Decode, 138, 17, 134, 1, // 11336: decode to S2_asr_r_r_sat using decoder 134 |
| 5203 | // 11336: } |
| 5204 | 4, 0, // 11341: case 0x4: { |
| 5205 | OPC_CheckField, 13, 1, 0, // 11343: check Inst[13] == 0x0 |
| 5206 | OPC_Decode, 237, 16, 134, 1, // 11347: decode to S2_asl_r_r_sat using decoder 134 |
| 5207 | // 11347: } |
| 5208 | // 11347: } // switch Inst[7:5] |
| 5209 | // 11347: } |
| 5210 | 50, 47, // 11352: case 0x32: { |
| 5211 | OPC_SwitchField, 5, 3, // 11354: switch Inst[7:5] { |
| 5212 | 0, 9, // 11357: case 0x0: { |
| 5213 | OPC_CheckField, 13, 1, 0, // 11359: check Inst[13] == 0x0 |
| 5214 | OPC_Decode, 133, 17, 134, 1, // 11363: decode to S2_asr_r_r using decoder 134 |
| 5215 | // 11363: } |
| 5216 | 2, 9, // 11368: case 0x2: { |
| 5217 | OPC_CheckField, 13, 1, 0, // 11370: check Inst[13] == 0x0 |
| 5218 | OPC_Decode, 202, 17, 134, 1, // 11374: decode to S2_lsr_r_r using decoder 134 |
| 5219 | // 11374: } |
| 5220 | 4, 9, // 11379: case 0x4: { |
| 5221 | OPC_CheckField, 13, 1, 0, // 11381: check Inst[13] == 0x0 |
| 5222 | OPC_Decode, 232, 16, 134, 1, // 11385: decode to S2_asl_r_r using decoder 134 |
| 5223 | // 11385: } |
| 5224 | 6, 0, // 11390: case 0x6: { |
| 5225 | OPC_CheckField, 13, 1, 0, // 11392: check Inst[13] == 0x0 |
| 5226 | OPC_Decode, 175, 17, 134, 1, // 11396: decode to S2_lsl_r_r using decoder 134 |
| 5227 | // 11396: } |
| 5228 | // 11396: } // switch Inst[7:5] |
| 5229 | // 11396: } |
| 5230 | 52, 59, // 11401: case 0x34: { |
| 5231 | OPC_SwitchField, 6, 2, // 11403: switch Inst[7:6] { |
| 5232 | 0, 13, // 11406: case 0x0: { |
| 5233 | OPC_CheckField, 13, 1, 0, // 11408: check Inst[13] == 0x0 |
| 5234 | OPC_CheckField, 5, 1, 0, // 11412: check Inst[5] == 0x0 |
| 5235 | OPC_Decode, 133, 18, 134, 1, // 11416: decode to S2_setbit_r using decoder 134 |
| 5236 | // 11416: } |
| 5237 | 1, 13, // 11421: case 0x1: { |
| 5238 | OPC_CheckField, 13, 1, 0, // 11423: check Inst[13] == 0x0 |
| 5239 | OPC_CheckField, 5, 1, 0, // 11427: check Inst[5] == 0x0 |
| 5240 | OPC_Decode, 153, 17, 134, 1, // 11431: decode to S2_clrbit_r using decoder 134 |
| 5241 | // 11431: } |
| 5242 | 2, 13, // 11436: case 0x2: { |
| 5243 | OPC_CheckField, 13, 1, 0, // 11438: check Inst[13] == 0x0 |
| 5244 | OPC_CheckField, 5, 1, 0, // 11442: check Inst[5] == 0x0 |
| 5245 | OPC_Decode, 204, 18, 134, 1, // 11446: decode to S2_togglebit_r using decoder 134 |
| 5246 | // 11446: } |
| 5247 | 3, 0, // 11451: case 0x3: { |
| 5248 | OPC_CheckField, 13, 1, 0, // 11453: check Inst[13] == 0x0 |
| 5249 | OPC_Decode, 246, 18, 215, 1, // 11457: decode to S4_lsli using decoder 215 |
| 5250 | // 11457: } |
| 5251 | // 11457: } // switch Inst[7:6] |
| 5252 | // 11457: } |
| 5253 | 54, 49, // 11462: case 0x36: { |
| 5254 | OPC_SwitchField, 5, 3, // 11464: switch Inst[7:5] { |
| 5255 | 0, 9, // 11467: case 0x0: { |
| 5256 | OPC_CheckField, 13, 1, 0, // 11469: check Inst[13] == 0x0 |
| 5257 | OPC_Decode, 235, 8, 134, 1, // 11473: decode to A4_cround_rr using decoder 134 |
| 5258 | // 11473: } |
| 5259 | 2, 11, // 11478: case 0x2: { |
| 5260 | OPC_CheckPredicate, 8, // 11480: check predicate 8 |
| 5261 | OPC_CheckField, 13, 1, 0, // 11482: check Inst[13] == 0x0 |
| 5262 | OPC_Decode, 173, 9, 212, 1, // 11486: decode to A7_croundd_rr using decoder 212 |
| 5263 | // 11486: } |
| 5264 | 4, 9, // 11491: case 0x4: { |
| 5265 | OPC_CheckField, 13, 1, 0, // 11493: check Inst[13] == 0x0 |
| 5266 | OPC_Decode, 142, 9, 134, 1, // 11497: decode to A4_round_rr using decoder 134 |
| 5267 | // 11497: } |
| 5268 | 6, 0, // 11502: case 0x6: { |
| 5269 | OPC_CheckField, 13, 1, 0, // 11504: check Inst[13] == 0x0 |
| 5270 | OPC_Decode, 143, 9, 134, 1, // 11508: decode to A4_round_rr_sat using decoder 134 |
| 5271 | // 11508: } |
| 5272 | // 11508: } // switch Inst[7:5] |
| 5273 | // 11508: } |
| 5274 | 56, 13, // 11513: case 0x38: { |
| 5275 | OPC_CheckField, 13, 1, 0, // 11515: check Inst[13] == 0x0 |
| 5276 | OPC_CheckField, 2, 6, 0, // 11519: check Inst[7:2] == 0x0 |
| 5277 | OPC_Decode, 206, 18, 169, 1, // 11523: decode to S2_tstbit_r using decoder 169 |
| 5278 | // 11523: } |
| 5279 | 57, 13, // 11528: case 0x39: { |
| 5280 | OPC_CheckField, 13, 1, 0, // 11530: check Inst[13] == 0x0 |
| 5281 | OPC_CheckField, 2, 6, 0, // 11534: check Inst[7:2] == 0x0 |
| 5282 | OPC_Decode, 248, 18, 169, 1, // 11538: decode to S4_ntstbit_r using decoder 169 |
| 5283 | // 11538: } |
| 5284 | 58, 13, // 11543: case 0x3a: { |
| 5285 | OPC_CheckField, 13, 1, 0, // 11545: check Inst[13] == 0x0 |
| 5286 | OPC_CheckField, 2, 6, 0, // 11549: check Inst[7:2] == 0x0 |
| 5287 | OPC_Decode, 181, 9, 169, 1, // 11553: decode to C2_bitsset using decoder 169 |
| 5288 | // 11553: } |
| 5289 | 59, 13, // 11558: case 0x3b: { |
| 5290 | OPC_CheckField, 13, 1, 0, // 11560: check Inst[13] == 0x0 |
| 5291 | OPC_CheckField, 2, 6, 0, // 11564: check Inst[7:2] == 0x0 |
| 5292 | OPC_Decode, 227, 9, 169, 1, // 11568: decode to C4_nbitsset using decoder 169 |
| 5293 | // 11568: } |
| 5294 | 60, 13, // 11573: case 0x3c: { |
| 5295 | OPC_CheckField, 13, 1, 0, // 11575: check Inst[13] == 0x0 |
| 5296 | OPC_CheckField, 2, 6, 0, // 11579: check Inst[7:2] == 0x0 |
| 5297 | OPC_Decode, 179, 9, 169, 1, // 11583: decode to C2_bitsclr using decoder 169 |
| 5298 | // 11583: } |
| 5299 | 61, 13, // 11588: case 0x3d: { |
| 5300 | OPC_CheckField, 13, 1, 0, // 11590: check Inst[13] == 0x0 |
| 5301 | OPC_CheckField, 2, 6, 0, // 11594: check Inst[7:2] == 0x0 |
| 5302 | OPC_Decode, 225, 9, 169, 1, // 11598: decode to C4_nbitsclr using decoder 169 |
| 5303 | // 11598: } |
| 5304 | 62, 69, // 11603: case 0x3e: { |
| 5305 | OPC_SwitchField, 2, 6, // 11605: switch Inst[7:2] { |
| 5306 | 16, 9, // 11608: case 0x10: { |
| 5307 | OPC_CheckField, 13, 1, 0, // 11610: check Inst[13] == 0x0 |
| 5308 | OPC_Decode, 221, 8, 169, 1, // 11614: decode to A4_cmpbgt using decoder 169 |
| 5309 | // 11614: } |
| 5310 | 24, 9, // 11619: case 0x18: { |
| 5311 | OPC_CheckField, 13, 1, 0, // 11621: check Inst[13] == 0x0 |
| 5312 | OPC_Decode, 225, 8, 169, 1, // 11625: decode to A4_cmpheq using decoder 169 |
| 5313 | // 11625: } |
| 5314 | 32, 9, // 11630: case 0x20: { |
| 5315 | OPC_CheckField, 13, 1, 0, // 11632: check Inst[13] == 0x0 |
| 5316 | OPC_Decode, 227, 8, 169, 1, // 11636: decode to A4_cmphgt using decoder 169 |
| 5317 | // 11636: } |
| 5318 | 40, 9, // 11641: case 0x28: { |
| 5319 | OPC_CheckField, 13, 1, 0, // 11643: check Inst[13] == 0x0 |
| 5320 | OPC_Decode, 229, 8, 169, 1, // 11647: decode to A4_cmphgtu using decoder 169 |
| 5321 | // 11647: } |
| 5322 | 48, 9, // 11652: case 0x30: { |
| 5323 | OPC_CheckField, 13, 1, 0, // 11654: check Inst[13] == 0x0 |
| 5324 | OPC_Decode, 219, 8, 169, 1, // 11658: decode to A4_cmpbeq using decoder 169 |
| 5325 | // 11658: } |
| 5326 | 56, 0, // 11663: case 0x38: { |
| 5327 | OPC_CheckField, 13, 1, 0, // 11665: check Inst[13] == 0x0 |
| 5328 | OPC_Decode, 223, 8, 169, 1, // 11669: decode to A4_cmpbgtu using decoder 169 |
| 5329 | // 11669: } |
| 5330 | // 11669: } // switch Inst[7:2] |
| 5331 | // 11669: } |
| 5332 | 63, 47, // 11674: case 0x3f: { |
| 5333 | OPC_SwitchField, 2, 6, // 11676: switch Inst[7:2] { |
| 5334 | 0, 9, // 11679: case 0x0: { |
| 5335 | OPC_CheckField, 13, 1, 0, // 11681: check Inst[13] == 0x0 |
| 5336 | OPC_Decode, 168, 10, 169, 1, // 11685: decode to F2_sfcmpge using decoder 169 |
| 5337 | // 11685: } |
| 5338 | 8, 9, // 11690: case 0x8: { |
| 5339 | OPC_CheckField, 13, 1, 0, // 11692: check Inst[13] == 0x0 |
| 5340 | OPC_Decode, 170, 10, 169, 1, // 11696: decode to F2_sfcmpuo using decoder 169 |
| 5341 | // 11696: } |
| 5342 | 24, 9, // 11701: case 0x18: { |
| 5343 | OPC_CheckField, 13, 1, 0, // 11703: check Inst[13] == 0x0 |
| 5344 | OPC_Decode, 167, 10, 169, 1, // 11707: decode to F2_sfcmpeq using decoder 169 |
| 5345 | // 11707: } |
| 5346 | 32, 0, // 11712: case 0x20: { |
| 5347 | OPC_CheckField, 13, 1, 0, // 11714: check Inst[13] == 0x0 |
| 5348 | OPC_Decode, 169, 10, 169, 1, // 11718: decode to F2_sfcmpgt using decoder 169 |
| 5349 | // 11718: } |
| 5350 | // 11718: } // switch Inst[7:2] |
| 5351 | // 11718: } |
| 5352 | 64, 13, // 11723: case 0x40: { |
| 5353 | OPC_CheckField, 13, 1, 0, // 11725: check Inst[13] == 0x0 |
| 5354 | OPC_CheckField, 5, 3, 0, // 11729: check Inst[7:5] == 0x0 |
| 5355 | OPC_Decode, 164, 17, 216, 1, // 11733: decode to S2_insert_rp using decoder 216 |
| 5356 | // 11733: } |
| 5357 | 72, 25, // 11738: case 0x48: { |
| 5358 | OPC_SwitchField, 5, 3, // 11740: switch Inst[7:5] { |
| 5359 | 0, 9, // 11743: case 0x0: { |
| 5360 | OPC_CheckField, 13, 1, 0, // 11745: check Inst[13] == 0x0 |
| 5361 | OPC_Decode, 160, 17, 217, 1, // 11749: decode to S2_extractu_rp using decoder 217 |
| 5362 | // 11749: } |
| 5363 | 2, 0, // 11754: case 0x2: { |
| 5364 | OPC_CheckField, 13, 1, 0, // 11756: check Inst[13] == 0x0 |
| 5365 | OPC_Decode, 243, 18, 217, 1, // 11760: decode to S4_extract_rp using decoder 217 |
| 5366 | // 11760: } |
| 5367 | // 11760: } // switch Inst[7:5] |
| 5368 | // 11760: } |
| 5369 | 80, 13, // 11765: case 0x50: { |
| 5370 | OPC_CheckField, 13, 1, 0, // 11767: check Inst[13] == 0x0 |
| 5371 | OPC_CheckField, 5, 3, 0, // 11771: check Inst[7:5] == 0x0 |
| 5372 | OPC_Decode, 166, 17, 218, 1, // 11775: decode to S2_insertp_rp using decoder 218 |
| 5373 | // 11775: } |
| 5374 | 84, 13, // 11780: case 0x54: { |
| 5375 | OPC_CheckField, 13, 1, 0, // 11782: check Inst[13] == 0x0 |
| 5376 | OPC_CheckField, 5, 3, 0, // 11786: check Inst[7:5] == 0x0 |
| 5377 | OPC_Decode, 146, 16, 218, 1, // 11790: decode to M4_xor_xacc using decoder 218 |
| 5378 | // 11790: } |
| 5379 | 88, 47, // 11795: case 0x58: { |
| 5380 | OPC_SwitchField, 5, 3, // 11797: switch Inst[7:5] { |
| 5381 | 0, 9, // 11800: case 0x0: { |
| 5382 | OPC_CheckField, 13, 1, 0, // 11802: check Inst[13] == 0x0 |
| 5383 | OPC_Decode, 131, 17, 219, 1, // 11806: decode to S2_asr_r_p_or using decoder 219 |
| 5384 | // 11806: } |
| 5385 | 2, 9, // 11811: case 0x2: { |
| 5386 | OPC_CheckField, 13, 1, 0, // 11813: check Inst[13] == 0x0 |
| 5387 | OPC_Decode, 200, 17, 219, 1, // 11817: decode to S2_lsr_r_p_or using decoder 219 |
| 5388 | // 11817: } |
| 5389 | 4, 9, // 11822: case 0x4: { |
| 5390 | OPC_CheckField, 13, 1, 0, // 11824: check Inst[13] == 0x0 |
| 5391 | OPC_Decode, 230, 16, 219, 1, // 11828: decode to S2_asl_r_p_or using decoder 219 |
| 5392 | // 11828: } |
| 5393 | 6, 0, // 11833: case 0x6: { |
| 5394 | OPC_CheckField, 13, 1, 0, // 11835: check Inst[13] == 0x0 |
| 5395 | OPC_Decode, 173, 17, 219, 1, // 11839: decode to S2_lsl_r_p_or using decoder 219 |
| 5396 | // 11839: } |
| 5397 | // 11839: } // switch Inst[7:5] |
| 5398 | // 11839: } |
| 5399 | 89, 90, // 11844: case 0x59: { |
| 5400 | OPC_SwitchField, 5, 3, // 11846: switch Inst[7:5] { |
| 5401 | 1, 17, // 11849: case 0x1: { |
| 5402 | OPC_SwitchField, 13, 1, // 11851: switch Inst[13] { |
| 5403 | 0, 5, // 11854: case 0x0: { |
| 5404 | OPC_Decode, 159, 9, 220, 1, // 11856: decode to A4_vrmaxh using decoder 220 |
| 5405 | // 11856: } |
| 5406 | 1, 0, // 11861: case 0x1: { |
| 5407 | OPC_Decode, 160, 9, 220, 1, // 11863: decode to A4_vrmaxuh using decoder 220 |
| 5408 | // 11863: } |
| 5409 | // 11863: } // switch Inst[13] |
| 5410 | // 11863: } |
| 5411 | 2, 17, // 11868: case 0x2: { |
| 5412 | OPC_SwitchField, 13, 1, // 11870: switch Inst[13] { |
| 5413 | 0, 5, // 11873: case 0x0: { |
| 5414 | OPC_Decode, 162, 9, 220, 1, // 11875: decode to A4_vrmaxw using decoder 220 |
| 5415 | // 11875: } |
| 5416 | 1, 0, // 11880: case 0x1: { |
| 5417 | OPC_Decode, 161, 9, 220, 1, // 11882: decode to A4_vrmaxuw using decoder 220 |
| 5418 | // 11882: } |
| 5419 | // 11882: } // switch Inst[13] |
| 5420 | // 11882: } |
| 5421 | 5, 17, // 11887: case 0x5: { |
| 5422 | OPC_SwitchField, 13, 1, // 11889: switch Inst[13] { |
| 5423 | 0, 5, // 11892: case 0x0: { |
| 5424 | OPC_Decode, 163, 9, 220, 1, // 11894: decode to A4_vrminh using decoder 220 |
| 5425 | // 11894: } |
| 5426 | 1, 0, // 11899: case 0x1: { |
| 5427 | OPC_Decode, 164, 9, 220, 1, // 11901: decode to A4_vrminuh using decoder 220 |
| 5428 | // 11901: } |
| 5429 | // 11901: } // switch Inst[13] |
| 5430 | // 11901: } |
| 5431 | 6, 17, // 11906: case 0x6: { |
| 5432 | OPC_SwitchField, 13, 1, // 11908: switch Inst[13] { |
| 5433 | 0, 5, // 11911: case 0x0: { |
| 5434 | OPC_Decode, 166, 9, 220, 1, // 11913: decode to A4_vrminw using decoder 220 |
| 5435 | // 11913: } |
| 5436 | 1, 0, // 11918: case 0x1: { |
| 5437 | OPC_Decode, 165, 9, 220, 1, // 11920: decode to A4_vrminuw using decoder 220 |
| 5438 | // 11920: } |
| 5439 | // 11920: } // switch Inst[13] |
| 5440 | // 11920: } |
| 5441 | 7, 0, // 11925: case 0x7: { |
| 5442 | OPC_CheckField, 13, 1, 1, // 11927: check Inst[13] == 0x1 |
| 5443 | OPC_Decode, 211, 18, 219, 1, // 11931: decode to S2_vrcnegh using decoder 219 |
| 5444 | // 11931: } |
| 5445 | // 11931: } // switch Inst[7:5] |
| 5446 | // 11931: } |
| 5447 | 90, 47, // 11936: case 0x5a: { |
| 5448 | OPC_SwitchField, 5, 3, // 11938: switch Inst[7:5] { |
| 5449 | 0, 9, // 11941: case 0x0: { |
| 5450 | OPC_CheckField, 13, 1, 0, // 11943: check Inst[13] == 0x0 |
| 5451 | OPC_Decode, 129, 17, 219, 1, // 11947: decode to S2_asr_r_p_and using decoder 219 |
| 5452 | // 11947: } |
| 5453 | 2, 9, // 11952: case 0x2: { |
| 5454 | OPC_CheckField, 13, 1, 0, // 11954: check Inst[13] == 0x0 |
| 5455 | OPC_Decode, 198, 17, 219, 1, // 11958: decode to S2_lsr_r_p_and using decoder 219 |
| 5456 | // 11958: } |
| 5457 | 4, 9, // 11963: case 0x4: { |
| 5458 | OPC_CheckField, 13, 1, 0, // 11965: check Inst[13] == 0x0 |
| 5459 | OPC_Decode, 228, 16, 219, 1, // 11969: decode to S2_asl_r_p_and using decoder 219 |
| 5460 | // 11969: } |
| 5461 | 6, 0, // 11974: case 0x6: { |
| 5462 | OPC_CheckField, 13, 1, 0, // 11976: check Inst[13] == 0x0 |
| 5463 | OPC_Decode, 171, 17, 219, 1, // 11980: decode to S2_lsl_r_p_and using decoder 219 |
| 5464 | // 11980: } |
| 5465 | // 11980: } // switch Inst[7:5] |
| 5466 | // 11980: } |
| 5467 | 91, 47, // 11985: case 0x5b: { |
| 5468 | OPC_SwitchField, 5, 3, // 11987: switch Inst[7:5] { |
| 5469 | 0, 9, // 11990: case 0x0: { |
| 5470 | OPC_CheckField, 13, 1, 0, // 11992: check Inst[13] == 0x0 |
| 5471 | OPC_Decode, 132, 17, 219, 1, // 11996: decode to S2_asr_r_p_xor using decoder 219 |
| 5472 | // 11996: } |
| 5473 | 2, 9, // 12001: case 0x2: { |
| 5474 | OPC_CheckField, 13, 1, 0, // 12003: check Inst[13] == 0x0 |
| 5475 | OPC_Decode, 201, 17, 219, 1, // 12007: decode to S2_lsr_r_p_xor using decoder 219 |
| 5476 | // 12007: } |
| 5477 | 4, 9, // 12012: case 0x4: { |
| 5478 | OPC_CheckField, 13, 1, 0, // 12014: check Inst[13] == 0x0 |
| 5479 | OPC_Decode, 231, 16, 219, 1, // 12018: decode to S2_asl_r_p_xor using decoder 219 |
| 5480 | // 12018: } |
| 5481 | 6, 0, // 12023: case 0x6: { |
| 5482 | OPC_CheckField, 13, 1, 0, // 12025: check Inst[13] == 0x0 |
| 5483 | OPC_Decode, 174, 17, 219, 1, // 12029: decode to S2_lsl_r_p_xor using decoder 219 |
| 5484 | // 12029: } |
| 5485 | // 12029: } // switch Inst[7:5] |
| 5486 | // 12029: } |
| 5487 | 92, 47, // 12034: case 0x5c: { |
| 5488 | OPC_SwitchField, 5, 3, // 12036: switch Inst[7:5] { |
| 5489 | 0, 9, // 12039: case 0x0: { |
| 5490 | OPC_CheckField, 13, 1, 0, // 12041: check Inst[13] == 0x0 |
| 5491 | OPC_Decode, 130, 17, 219, 1, // 12045: decode to S2_asr_r_p_nac using decoder 219 |
| 5492 | // 12045: } |
| 5493 | 2, 9, // 12050: case 0x2: { |
| 5494 | OPC_CheckField, 13, 1, 0, // 12052: check Inst[13] == 0x0 |
| 5495 | OPC_Decode, 199, 17, 219, 1, // 12056: decode to S2_lsr_r_p_nac using decoder 219 |
| 5496 | // 12056: } |
| 5497 | 4, 9, // 12061: case 0x4: { |
| 5498 | OPC_CheckField, 13, 1, 0, // 12063: check Inst[13] == 0x0 |
| 5499 | OPC_Decode, 229, 16, 219, 1, // 12067: decode to S2_asl_r_p_nac using decoder 219 |
| 5500 | // 12067: } |
| 5501 | 6, 0, // 12072: case 0x6: { |
| 5502 | OPC_CheckField, 13, 1, 0, // 12074: check Inst[13] == 0x0 |
| 5503 | OPC_Decode, 172, 17, 219, 1, // 12078: decode to S2_lsl_r_p_nac using decoder 219 |
| 5504 | // 12078: } |
| 5505 | // 12078: } // switch Inst[7:5] |
| 5506 | // 12078: } |
| 5507 | 93, 9, // 12083: case 0x5d: { |
| 5508 | OPC_CheckField, 6, 2, 0, // 12085: check Inst[7:6] == 0x0 |
| 5509 | OPC_Decode, 253, 19, 221, 1, // 12089: decode to S4_vrcrotate_acc using decoder 221 |
| 5510 | // 12089: } |
| 5511 | 94, 47, // 12094: case 0x5e: { |
| 5512 | OPC_SwitchField, 5, 3, // 12096: switch Inst[7:5] { |
| 5513 | 0, 9, // 12099: case 0x0: { |
| 5514 | OPC_CheckField, 13, 1, 0, // 12101: check Inst[13] == 0x0 |
| 5515 | OPC_Decode, 128, 17, 219, 1, // 12105: decode to S2_asr_r_p_acc using decoder 219 |
| 5516 | // 12105: } |
| 5517 | 2, 9, // 12110: case 0x2: { |
| 5518 | OPC_CheckField, 13, 1, 0, // 12112: check Inst[13] == 0x0 |
| 5519 | OPC_Decode, 197, 17, 219, 1, // 12116: decode to S2_lsr_r_p_acc using decoder 219 |
| 5520 | // 12116: } |
| 5521 | 4, 9, // 12121: case 0x4: { |
| 5522 | OPC_CheckField, 13, 1, 0, // 12123: check Inst[13] == 0x0 |
| 5523 | OPC_Decode, 227, 16, 219, 1, // 12127: decode to S2_asl_r_p_acc using decoder 219 |
| 5524 | // 12127: } |
| 5525 | 6, 0, // 12132: case 0x6: { |
| 5526 | OPC_CheckField, 13, 1, 0, // 12134: check Inst[13] == 0x0 |
| 5527 | OPC_Decode, 170, 17, 219, 1, // 12138: decode to S2_lsl_r_p_acc using decoder 219 |
| 5528 | // 12138: } |
| 5529 | // 12138: } // switch Inst[7:5] |
| 5530 | // 12138: } |
| 5531 | 96, 47, // 12143: case 0x60: { |
| 5532 | OPC_SwitchField, 5, 3, // 12145: switch Inst[7:5] { |
| 5533 | 0, 9, // 12148: case 0x0: { |
| 5534 | OPC_CheckField, 13, 1, 0, // 12150: check Inst[13] == 0x0 |
| 5535 | OPC_Decode, 137, 17, 222, 1, // 12154: decode to S2_asr_r_r_or using decoder 222 |
| 5536 | // 12154: } |
| 5537 | 2, 9, // 12159: case 0x2: { |
| 5538 | OPC_CheckField, 13, 1, 0, // 12161: check Inst[13] == 0x0 |
| 5539 | OPC_Decode, 206, 17, 222, 1, // 12165: decode to S2_lsr_r_r_or using decoder 222 |
| 5540 | // 12165: } |
| 5541 | 4, 9, // 12170: case 0x4: { |
| 5542 | OPC_CheckField, 13, 1, 0, // 12172: check Inst[13] == 0x0 |
| 5543 | OPC_Decode, 236, 16, 222, 1, // 12176: decode to S2_asl_r_r_or using decoder 222 |
| 5544 | // 12176: } |
| 5545 | 6, 0, // 12181: case 0x6: { |
| 5546 | OPC_CheckField, 13, 1, 0, // 12183: check Inst[13] == 0x0 |
| 5547 | OPC_Decode, 179, 17, 222, 1, // 12187: decode to S2_lsl_r_r_or using decoder 222 |
| 5548 | // 12187: } |
| 5549 | // 12187: } // switch Inst[7:5] |
| 5550 | // 12187: } |
| 5551 | 98, 47, // 12192: case 0x62: { |
| 5552 | OPC_SwitchField, 5, 3, // 12194: switch Inst[7:5] { |
| 5553 | 0, 9, // 12197: case 0x0: { |
| 5554 | OPC_CheckField, 13, 1, 0, // 12199: check Inst[13] == 0x0 |
| 5555 | OPC_Decode, 135, 17, 222, 1, // 12203: decode to S2_asr_r_r_and using decoder 222 |
| 5556 | // 12203: } |
| 5557 | 2, 9, // 12208: case 0x2: { |
| 5558 | OPC_CheckField, 13, 1, 0, // 12210: check Inst[13] == 0x0 |
| 5559 | OPC_Decode, 204, 17, 222, 1, // 12214: decode to S2_lsr_r_r_and using decoder 222 |
| 5560 | // 12214: } |
| 5561 | 4, 9, // 12219: case 0x4: { |
| 5562 | OPC_CheckField, 13, 1, 0, // 12221: check Inst[13] == 0x0 |
| 5563 | OPC_Decode, 234, 16, 222, 1, // 12225: decode to S2_asl_r_r_and using decoder 222 |
| 5564 | // 12225: } |
| 5565 | 6, 0, // 12230: case 0x6: { |
| 5566 | OPC_CheckField, 13, 1, 0, // 12232: check Inst[13] == 0x0 |
| 5567 | OPC_Decode, 177, 17, 222, 1, // 12236: decode to S2_lsl_r_r_and using decoder 222 |
| 5568 | // 12236: } |
| 5569 | // 12236: } // switch Inst[7:5] |
| 5570 | // 12236: } |
| 5571 | 100, 47, // 12241: case 0x64: { |
| 5572 | OPC_SwitchField, 5, 3, // 12243: switch Inst[7:5] { |
| 5573 | 0, 9, // 12246: case 0x0: { |
| 5574 | OPC_CheckField, 13, 1, 0, // 12248: check Inst[13] == 0x0 |
| 5575 | OPC_Decode, 136, 17, 222, 1, // 12252: decode to S2_asr_r_r_nac using decoder 222 |
| 5576 | // 12252: } |
| 5577 | 2, 9, // 12257: case 0x2: { |
| 5578 | OPC_CheckField, 13, 1, 0, // 12259: check Inst[13] == 0x0 |
| 5579 | OPC_Decode, 205, 17, 222, 1, // 12263: decode to S2_lsr_r_r_nac using decoder 222 |
| 5580 | // 12263: } |
| 5581 | 4, 9, // 12268: case 0x4: { |
| 5582 | OPC_CheckField, 13, 1, 0, // 12270: check Inst[13] == 0x0 |
| 5583 | OPC_Decode, 235, 16, 222, 1, // 12274: decode to S2_asl_r_r_nac using decoder 222 |
| 5584 | // 12274: } |
| 5585 | 6, 0, // 12279: case 0x6: { |
| 5586 | OPC_CheckField, 13, 1, 0, // 12281: check Inst[13] == 0x0 |
| 5587 | OPC_Decode, 178, 17, 222, 1, // 12285: decode to S2_lsl_r_r_nac using decoder 222 |
| 5588 | // 12285: } |
| 5589 | // 12285: } // switch Inst[7:5] |
| 5590 | // 12285: } |
| 5591 | 102, 0, // 12290: case 0x66: { |
| 5592 | OPC_SwitchField, 5, 3, // 12292: switch Inst[7:5] { |
| 5593 | 0, 9, // 12295: case 0x0: { |
| 5594 | OPC_CheckField, 13, 1, 0, // 12297: check Inst[13] == 0x0 |
| 5595 | OPC_Decode, 134, 17, 222, 1, // 12301: decode to S2_asr_r_r_acc using decoder 222 |
| 5596 | // 12301: } |
| 5597 | 2, 9, // 12306: case 0x2: { |
| 5598 | OPC_CheckField, 13, 1, 0, // 12308: check Inst[13] == 0x0 |
| 5599 | OPC_Decode, 203, 17, 222, 1, // 12312: decode to S2_lsr_r_r_acc using decoder 222 |
| 5600 | // 12312: } |
| 5601 | 4, 9, // 12317: case 0x4: { |
| 5602 | OPC_CheckField, 13, 1, 0, // 12319: check Inst[13] == 0x0 |
| 5603 | OPC_Decode, 233, 16, 222, 1, // 12323: decode to S2_asl_r_r_acc using decoder 222 |
| 5604 | // 12323: } |
| 5605 | 6, 0, // 12328: case 0x6: { |
| 5606 | OPC_CheckField, 13, 1, 0, // 12330: check Inst[13] == 0x0 |
| 5607 | OPC_Decode, 176, 17, 222, 1, // 12334: decode to S2_lsl_r_r_acc using decoder 222 |
| 5608 | // 12334: } |
| 5609 | // 12334: } // switch Inst[7:5] |
| 5610 | // 12334: } |
| 5611 | // 12334: } // switch Inst[27:21] |
| 5612 | // 12334: } |
| 5613 | 13, 194, 14, // 12339: case 0xd: { |
| 5614 | OPC_SwitchField, 24, 4, // 12342: switch Inst[27:24] { |
| 5615 | 0, 17, // 12345: case 0x0: { |
| 5616 | OPC_CheckField, 21, 3, 0, // 12347: check Inst[23:21] == 0x0 |
| 5617 | OPC_CheckField, 13, 1, 0, // 12351: check Inst[13] == 0x0 |
| 5618 | OPC_CheckField, 5, 3, 0, // 12355: check Inst[7:5] == 0x0 |
| 5619 | OPC_Decode, 211, 17, 208, 1, // 12359: decode to S2_parityp using decoder 208 |
| 5620 | // 12359: } |
| 5621 | 1, 17, // 12364: case 0x1: { |
| 5622 | OPC_CheckField, 21, 3, 0, // 12366: check Inst[23:21] == 0x0 |
| 5623 | OPC_CheckField, 13, 1, 0, // 12370: check Inst[13] == 0x0 |
| 5624 | OPC_CheckField, 7, 1, 0, // 12374: check Inst[7] == 0x0 |
| 5625 | OPC_Decode, 210, 9, 223, 1, // 12378: decode to C2_vmux using decoder 223 |
| 5626 | // 12378: } |
| 5627 | 2, 131, 2, // 12383: case 0x2: { |
| 5628 | OPC_SwitchField, 2, 6, // 12386: switch Inst[7:2] { |
| 5629 | 0, 44, // 12389: case 0x0: { |
| 5630 | OPC_SwitchField, 21, 3, // 12391: switch Inst[23:21] { |
| 5631 | 0, 17, // 12394: case 0x0: { |
| 5632 | OPC_SwitchField, 13, 1, // 12396: switch Inst[13] { |
| 5633 | 0, 5, // 12399: case 0x0: { |
| 5634 | OPC_Decode, 176, 8, 224, 1, // 12401: decode to A2_vcmpweq using decoder 224 |
| 5635 | // 12401: } |
| 5636 | 1, 0, // 12406: case 0x1: { |
| 5637 | OPC_Decode, 148, 9, 224, 1, // 12408: decode to A4_vcmpbeq_any using decoder 224 |
| 5638 | // 12408: } |
| 5639 | // 12408: } // switch Inst[13] |
| 5640 | // 12408: } |
| 5641 | 4, 9, // 12413: case 0x4: { |
| 5642 | OPC_CheckField, 13, 1, 0, // 12415: check Inst[13] == 0x0 |
| 5643 | OPC_Decode, 192, 9, 224, 1, // 12419: decode to C2_cmpeqp using decoder 224 |
| 5644 | // 12419: } |
| 5645 | 7, 0, // 12424: case 0x7: { |
| 5646 | OPC_CheckField, 13, 1, 0, // 12426: check Inst[13] == 0x0 |
| 5647 | OPC_Decode, 152, 10, 224, 1, // 12430: decode to F2_dfcmpeq using decoder 224 |
| 5648 | // 12430: } |
| 5649 | // 12430: } // switch Inst[23:21] |
| 5650 | // 12430: } |
| 5651 | 8, 35, // 12435: case 0x8: { |
| 5652 | OPC_SwitchField, 13, 1, // 12437: switch Inst[13] { |
| 5653 | 0, 17, // 12440: case 0x0: { |
| 5654 | OPC_SwitchField, 21, 3, // 12442: switch Inst[23:21] { |
| 5655 | 0, 5, // 12445: case 0x0: { |
| 5656 | OPC_Decode, 177, 8, 224, 1, // 12447: decode to A2_vcmpwgt using decoder 224 |
| 5657 | // 12447: } |
| 5658 | 7, 0, // 12452: case 0x7: { |
| 5659 | OPC_Decode, 154, 10, 224, 1, // 12454: decode to F2_dfcmpgt using decoder 224 |
| 5660 | // 12454: } |
| 5661 | // 12454: } // switch Inst[23:21] |
| 5662 | // 12454: } |
| 5663 | 1, 0, // 12459: case 0x1: { |
| 5664 | OPC_CheckPredicate, 3, // 12461: check predicate 3 |
| 5665 | OPC_CheckField, 21, 3, 0, // 12463: check Inst[23:21] == 0x0 |
| 5666 | OPC_Decode, 169, 9, 224, 1, // 12467: decode to A6_vcmpbeq_notany using decoder 224 |
| 5667 | // 12467: } |
| 5668 | // 12467: } // switch Inst[13] |
| 5669 | // 12467: } |
| 5670 | 16, 44, // 12472: case 0x10: { |
| 5671 | OPC_SwitchField, 21, 3, // 12474: switch Inst[23:21] { |
| 5672 | 0, 17, // 12477: case 0x0: { |
| 5673 | OPC_SwitchField, 13, 1, // 12479: switch Inst[13] { |
| 5674 | 0, 5, // 12482: case 0x0: { |
| 5675 | OPC_Decode, 178, 8, 224, 1, // 12484: decode to A2_vcmpwgtu using decoder 224 |
| 5676 | // 12484: } |
| 5677 | 1, 0, // 12489: case 0x1: { |
| 5678 | OPC_Decode, 150, 9, 224, 1, // 12491: decode to A4_vcmpbgt using decoder 224 |
| 5679 | // 12491: } |
| 5680 | // 12491: } // switch Inst[13] |
| 5681 | // 12491: } |
| 5682 | 4, 9, // 12496: case 0x4: { |
| 5683 | OPC_CheckField, 13, 1, 0, // 12498: check Inst[13] == 0x0 |
| 5684 | OPC_Decode, 195, 9, 224, 1, // 12502: decode to C2_cmpgtp using decoder 224 |
| 5685 | // 12502: } |
| 5686 | 7, 0, // 12507: case 0x7: { |
| 5687 | OPC_CheckField, 13, 1, 0, // 12509: check Inst[13] == 0x0 |
| 5688 | OPC_Decode, 153, 10, 224, 1, // 12513: decode to F2_dfcmpge using decoder 224 |
| 5689 | // 12513: } |
| 5690 | // 12513: } // switch Inst[23:21] |
| 5691 | // 12513: } |
| 5692 | 24, 33, // 12518: case 0x18: { |
| 5693 | OPC_SwitchField, 13, 1, // 12520: switch Inst[13] { |
| 5694 | 0, 17, // 12523: case 0x0: { |
| 5695 | OPC_SwitchField, 21, 3, // 12525: switch Inst[23:21] { |
| 5696 | 0, 5, // 12528: case 0x0: { |
| 5697 | OPC_Decode, 173, 8, 224, 1, // 12530: decode to A2_vcmpheq using decoder 224 |
| 5698 | // 12530: } |
| 5699 | 7, 0, // 12535: case 0x7: { |
| 5700 | OPC_Decode, 155, 10, 224, 1, // 12537: decode to F2_dfcmpuo using decoder 224 |
| 5701 | // 12537: } |
| 5702 | // 12537: } // switch Inst[23:21] |
| 5703 | // 12537: } |
| 5704 | 1, 0, // 12542: case 0x1: { |
| 5705 | OPC_CheckField, 21, 3, 0, // 12544: check Inst[23:21] == 0x0 |
| 5706 | OPC_Decode, 147, 9, 225, 1, // 12548: decode to A4_tlbmatch using decoder 225 |
| 5707 | // 12548: } |
| 5708 | // 12548: } // switch Inst[13] |
| 5709 | // 12548: } |
| 5710 | 32, 33, // 12553: case 0x20: { |
| 5711 | OPC_SwitchField, 13, 1, // 12555: switch Inst[13] { |
| 5712 | 0, 17, // 12558: case 0x0: { |
| 5713 | OPC_SwitchField, 21, 3, // 12560: switch Inst[23:21] { |
| 5714 | 0, 5, // 12563: case 0x0: { |
| 5715 | OPC_Decode, 174, 8, 224, 1, // 12565: decode to A2_vcmphgt using decoder 224 |
| 5716 | // 12565: } |
| 5717 | 4, 0, // 12570: case 0x4: { |
| 5718 | OPC_Decode, 198, 9, 224, 1, // 12572: decode to C2_cmpgtup using decoder 224 |
| 5719 | // 12572: } |
| 5720 | // 12572: } // switch Inst[23:21] |
| 5721 | // 12572: } |
| 5722 | 1, 0, // 12577: case 0x1: { |
| 5723 | OPC_CheckField, 21, 3, 0, // 12579: check Inst[23:21] == 0x0 |
| 5724 | OPC_Decode, 218, 8, 224, 1, // 12583: decode to A4_boundscheck_lo using decoder 224 |
| 5725 | // 12583: } |
| 5726 | // 12583: } // switch Inst[13] |
| 5727 | // 12583: } |
| 5728 | 40, 25, // 12588: case 0x28: { |
| 5729 | OPC_SwitchField, 13, 1, // 12590: switch Inst[13] { |
| 5730 | 0, 9, // 12593: case 0x0: { |
| 5731 | OPC_CheckField, 21, 3, 0, // 12595: check Inst[23:21] == 0x0 |
| 5732 | OPC_Decode, 175, 8, 224, 1, // 12599: decode to A2_vcmphgtu using decoder 224 |
| 5733 | // 12599: } |
| 5734 | 1, 0, // 12604: case 0x1: { |
| 5735 | OPC_CheckField, 21, 3, 0, // 12606: check Inst[23:21] == 0x0 |
| 5736 | OPC_Decode, 217, 8, 224, 1, // 12610: decode to A4_boundscheck_hi using decoder 224 |
| 5737 | // 12610: } |
| 5738 | // 12610: } // switch Inst[13] |
| 5739 | // 12610: } |
| 5740 | 48, 13, // 12615: case 0x30: { |
| 5741 | OPC_CheckField, 21, 3, 0, // 12617: check Inst[23:21] == 0x0 |
| 5742 | OPC_CheckField, 13, 1, 0, // 12621: check Inst[13] == 0x0 |
| 5743 | OPC_Decode, 171, 8, 224, 1, // 12625: decode to A2_vcmpbeq using decoder 224 |
| 5744 | // 12625: } |
| 5745 | 56, 0, // 12630: case 0x38: { |
| 5746 | OPC_CheckField, 21, 3, 0, // 12632: check Inst[23:21] == 0x0 |
| 5747 | OPC_CheckField, 13, 1, 0, // 12636: check Inst[13] == 0x0 |
| 5748 | OPC_Decode, 172, 8, 224, 1, // 12640: decode to A2_vcmpbgtu using decoder 224 |
| 5749 | // 12640: } |
| 5750 | // 12640: } // switch Inst[7:2] |
| 5751 | // 12640: } |
| 5752 | 3, 180, 5, // 12645: case 0x3: { |
| 5753 | OPC_SwitchField, 5, 3, // 12648: switch Inst[7:5] { |
| 5754 | 0, 91, // 12651: case 0x0: { |
| 5755 | OPC_SwitchField, 21, 3, // 12653: switch Inst[23:21] { |
| 5756 | 0, 9, // 12656: case 0x0: { |
| 5757 | OPC_CheckField, 13, 1, 0, // 12658: check Inst[13] == 0x0 |
| 5758 | OPC_Decode, 154, 8, 206, 1, // 12662: decode to A2_vaddub using decoder 206 |
| 5759 | // 12662: } |
| 5760 | 1, 9, // 12667: case 0x1: { |
| 5761 | OPC_CheckField, 13, 1, 0, // 12669: check Inst[13] == 0x0 |
| 5762 | OPC_Decode, 204, 8, 207, 1, // 12673: decode to A2_vsubub using decoder 207 |
| 5763 | // 12673: } |
| 5764 | 2, 9, // 12678: case 0x2: { |
| 5765 | OPC_CheckField, 13, 1, 0, // 12680: check Inst[13] == 0x0 |
| 5766 | OPC_Decode, 162, 8, 206, 1, // 12684: decode to A2_vavgub using decoder 206 |
| 5767 | // 12684: } |
| 5768 | 3, 9, // 12689: case 0x3: { |
| 5769 | OPC_CheckField, 13, 1, 0, // 12691: check Inst[13] == 0x0 |
| 5770 | OPC_Decode, 168, 8, 206, 1, // 12695: decode to A2_vavgw using decoder 206 |
| 5771 | // 12695: } |
| 5772 | 4, 9, // 12700: case 0x4: { |
| 5773 | OPC_CheckField, 13, 1, 0, // 12702: check Inst[13] == 0x0 |
| 5774 | OPC_Decode, 192, 8, 207, 1, // 12706: decode to A2_vnavgh using decoder 207 |
| 5775 | // 12706: } |
| 5776 | 5, 9, // 12711: case 0x5: { |
| 5777 | OPC_CheckField, 13, 1, 0, // 12713: check Inst[13] == 0x0 |
| 5778 | OPC_Decode, 188, 8, 207, 1, // 12717: decode to A2_vminub using decoder 207 |
| 5779 | // 12717: } |
| 5780 | 6, 9, // 12722: case 0x6: { |
| 5781 | OPC_CheckField, 13, 1, 0, // 12724: check Inst[13] == 0x0 |
| 5782 | OPC_Decode, 182, 8, 207, 1, // 12728: decode to A2_vmaxub using decoder 207 |
| 5783 | // 12728: } |
| 5784 | 7, 0, // 12733: case 0x7: { |
| 5785 | OPC_CheckField, 13, 1, 0, // 12735: check Inst[13] == 0x0 |
| 5786 | OPC_Decode, 187, 7, 206, 1, // 12739: decode to A2_andp using decoder 206 |
| 5787 | // 12739: } |
| 5788 | // 12739: } // switch Inst[23:21] |
| 5789 | // 12739: } |
| 5790 | 1, 91, // 12744: case 0x1: { |
| 5791 | OPC_SwitchField, 21, 3, // 12746: switch Inst[23:21] { |
| 5792 | 0, 9, // 12749: case 0x0: { |
| 5793 | OPC_CheckField, 13, 1, 0, // 12751: check Inst[13] == 0x0 |
| 5794 | OPC_Decode, 155, 8, 206, 1, // 12755: decode to A2_vaddubs using decoder 206 |
| 5795 | // 12755: } |
| 5796 | 1, 9, // 12760: case 0x1: { |
| 5797 | OPC_CheckField, 13, 1, 0, // 12762: check Inst[13] == 0x0 |
| 5798 | OPC_Decode, 205, 8, 207, 1, // 12766: decode to A2_vsububs using decoder 207 |
| 5799 | // 12766: } |
| 5800 | 2, 9, // 12771: case 0x2: { |
| 5801 | OPC_CheckField, 13, 1, 0, // 12773: check Inst[13] == 0x0 |
| 5802 | OPC_Decode, 163, 8, 206, 1, // 12777: decode to A2_vavgubr using decoder 206 |
| 5803 | // 12777: } |
| 5804 | 3, 9, // 12782: case 0x3: { |
| 5805 | OPC_CheckField, 13, 1, 0, // 12784: check Inst[13] == 0x0 |
| 5806 | OPC_Decode, 170, 8, 206, 1, // 12788: decode to A2_vavgwr using decoder 206 |
| 5807 | // 12788: } |
| 5808 | 4, 9, // 12793: case 0x4: { |
| 5809 | OPC_CheckField, 13, 1, 0, // 12795: check Inst[13] == 0x0 |
| 5810 | OPC_Decode, 194, 8, 207, 1, // 12799: decode to A2_vnavghr using decoder 207 |
| 5811 | // 12799: } |
| 5812 | 5, 9, // 12804: case 0x5: { |
| 5813 | OPC_CheckField, 13, 1, 0, // 12806: check Inst[13] == 0x0 |
| 5814 | OPC_Decode, 187, 8, 207, 1, // 12810: decode to A2_vminh using decoder 207 |
| 5815 | // 12810: } |
| 5816 | 6, 9, // 12815: case 0x6: { |
| 5817 | OPC_CheckField, 13, 1, 0, // 12817: check Inst[13] == 0x0 |
| 5818 | OPC_Decode, 181, 8, 207, 1, // 12821: decode to A2_vmaxh using decoder 207 |
| 5819 | // 12821: } |
| 5820 | 7, 0, // 12826: case 0x7: { |
| 5821 | OPC_CheckField, 13, 1, 0, // 12828: check Inst[13] == 0x0 |
| 5822 | OPC_Decode, 214, 8, 207, 1, // 12832: decode to A4_andnp using decoder 207 |
| 5823 | // 12832: } |
| 5824 | // 12832: } // switch Inst[23:21] |
| 5825 | // 12832: } |
| 5826 | 2, 91, // 12837: case 0x2: { |
| 5827 | OPC_SwitchField, 21, 3, // 12839: switch Inst[23:21] { |
| 5828 | 0, 9, // 12842: case 0x0: { |
| 5829 | OPC_CheckField, 13, 1, 0, // 12844: check Inst[13] == 0x0 |
| 5830 | OPC_Decode, 152, 8, 206, 1, // 12848: decode to A2_vaddh using decoder 206 |
| 5831 | // 12848: } |
| 5832 | 1, 9, // 12853: case 0x1: { |
| 5833 | OPC_CheckField, 13, 1, 0, // 12855: check Inst[13] == 0x0 |
| 5834 | OPC_Decode, 202, 8, 207, 1, // 12859: decode to A2_vsubh using decoder 207 |
| 5835 | // 12859: } |
| 5836 | 2, 9, // 12864: case 0x2: { |
| 5837 | OPC_CheckField, 13, 1, 0, // 12866: check Inst[13] == 0x0 |
| 5838 | OPC_Decode, 159, 8, 206, 1, // 12870: decode to A2_vavgh using decoder 206 |
| 5839 | // 12870: } |
| 5840 | 3, 9, // 12875: case 0x3: { |
| 5841 | OPC_CheckField, 13, 1, 0, // 12877: check Inst[13] == 0x0 |
| 5842 | OPC_Decode, 169, 8, 206, 1, // 12881: decode to A2_vavgwcr using decoder 206 |
| 5843 | // 12881: } |
| 5844 | 4, 9, // 12886: case 0x4: { |
| 5845 | OPC_CheckField, 13, 1, 0, // 12888: check Inst[13] == 0x0 |
| 5846 | OPC_Decode, 193, 8, 207, 1, // 12892: decode to A2_vnavghcr using decoder 207 |
| 5847 | // 12892: } |
| 5848 | 5, 9, // 12897: case 0x5: { |
| 5849 | OPC_CheckField, 13, 1, 0, // 12899: check Inst[13] == 0x0 |
| 5850 | OPC_Decode, 189, 8, 207, 1, // 12903: decode to A2_vminuh using decoder 207 |
| 5851 | // 12903: } |
| 5852 | 6, 9, // 12908: case 0x6: { |
| 5853 | OPC_CheckField, 13, 1, 0, // 12910: check Inst[13] == 0x0 |
| 5854 | OPC_Decode, 183, 8, 207, 1, // 12914: decode to A2_vmaxuh using decoder 207 |
| 5855 | // 12914: } |
| 5856 | 7, 0, // 12919: case 0x7: { |
| 5857 | OPC_CheckField, 13, 1, 0, // 12921: check Inst[13] == 0x0 |
| 5858 | OPC_Decode, 210, 7, 206, 1, // 12925: decode to A2_orp using decoder 206 |
| 5859 | // 12925: } |
| 5860 | // 12925: } // switch Inst[23:21] |
| 5861 | // 12925: } |
| 5862 | 3, 91, // 12930: case 0x3: { |
| 5863 | OPC_SwitchField, 21, 3, // 12932: switch Inst[23:21] { |
| 5864 | 0, 9, // 12935: case 0x0: { |
| 5865 | OPC_CheckField, 13, 1, 0, // 12937: check Inst[13] == 0x0 |
| 5866 | OPC_Decode, 153, 8, 206, 1, // 12941: decode to A2_vaddhs using decoder 206 |
| 5867 | // 12941: } |
| 5868 | 1, 9, // 12946: case 0x1: { |
| 5869 | OPC_CheckField, 13, 1, 0, // 12948: check Inst[13] == 0x0 |
| 5870 | OPC_Decode, 203, 8, 207, 1, // 12952: decode to A2_vsubhs using decoder 207 |
| 5871 | // 12952: } |
| 5872 | 2, 9, // 12957: case 0x2: { |
| 5873 | OPC_CheckField, 13, 1, 0, // 12959: check Inst[13] == 0x0 |
| 5874 | OPC_Decode, 161, 8, 206, 1, // 12963: decode to A2_vavghr using decoder 206 |
| 5875 | // 12963: } |
| 5876 | 3, 9, // 12968: case 0x3: { |
| 5877 | OPC_CheckField, 13, 1, 0, // 12970: check Inst[13] == 0x0 |
| 5878 | OPC_Decode, 166, 8, 206, 1, // 12974: decode to A2_vavguw using decoder 206 |
| 5879 | // 12974: } |
| 5880 | 4, 9, // 12979: case 0x4: { |
| 5881 | OPC_CheckField, 13, 1, 0, // 12981: check Inst[13] == 0x0 |
| 5882 | OPC_Decode, 195, 8, 207, 1, // 12985: decode to A2_vnavgw using decoder 207 |
| 5883 | // 12985: } |
| 5884 | 5, 9, // 12990: case 0x5: { |
| 5885 | OPC_CheckField, 13, 1, 0, // 12992: check Inst[13] == 0x0 |
| 5886 | OPC_Decode, 191, 8, 207, 1, // 12996: decode to A2_vminw using decoder 207 |
| 5887 | // 12996: } |
| 5888 | 6, 9, // 13001: case 0x6: { |
| 5889 | OPC_CheckField, 13, 1, 0, // 13003: check Inst[13] == 0x0 |
| 5890 | OPC_Decode, 185, 8, 207, 1, // 13007: decode to A2_vmaxw using decoder 207 |
| 5891 | // 13007: } |
| 5892 | 7, 0, // 13012: case 0x7: { |
| 5893 | OPC_CheckField, 13, 1, 0, // 13014: check Inst[13] == 0x0 |
| 5894 | OPC_Decode, 239, 8, 207, 1, // 13018: decode to A4_ornp using decoder 207 |
| 5895 | // 13018: } |
| 5896 | // 13018: } // switch Inst[23:21] |
| 5897 | // 13018: } |
| 5898 | 4, 91, // 13023: case 0x4: { |
| 5899 | OPC_SwitchField, 21, 3, // 13025: switch Inst[23:21] { |
| 5900 | 0, 9, // 13028: case 0x0: { |
| 5901 | OPC_CheckField, 13, 1, 0, // 13030: check Inst[13] == 0x0 |
| 5902 | OPC_Decode, 156, 8, 206, 1, // 13034: decode to A2_vadduhs using decoder 206 |
| 5903 | // 13034: } |
| 5904 | 1, 9, // 13039: case 0x1: { |
| 5905 | OPC_CheckField, 13, 1, 0, // 13041: check Inst[13] == 0x0 |
| 5906 | OPC_Decode, 206, 8, 207, 1, // 13045: decode to A2_vsubuhs using decoder 207 |
| 5907 | // 13045: } |
| 5908 | 2, 9, // 13050: case 0x2: { |
| 5909 | OPC_CheckField, 13, 1, 0, // 13052: check Inst[13] == 0x0 |
| 5910 | OPC_Decode, 160, 8, 206, 1, // 13056: decode to A2_vavghcr using decoder 206 |
| 5911 | // 13056: } |
| 5912 | 3, 9, // 13061: case 0x3: { |
| 5913 | OPC_CheckField, 13, 1, 0, // 13063: check Inst[13] == 0x0 |
| 5914 | OPC_Decode, 167, 8, 206, 1, // 13067: decode to A2_vavguwr using decoder 206 |
| 5915 | // 13067: } |
| 5916 | 4, 9, // 13072: case 0x4: { |
| 5917 | OPC_CheckField, 13, 1, 0, // 13074: check Inst[13] == 0x0 |
| 5918 | OPC_Decode, 197, 8, 207, 1, // 13078: decode to A2_vnavgwr using decoder 207 |
| 5919 | // 13078: } |
| 5920 | 5, 9, // 13083: case 0x5: { |
| 5921 | OPC_CheckField, 13, 1, 0, // 13085: check Inst[13] == 0x0 |
| 5922 | OPC_Decode, 190, 8, 207, 1, // 13089: decode to A2_vminuw using decoder 207 |
| 5923 | // 13089: } |
| 5924 | 6, 9, // 13094: case 0x6: { |
| 5925 | OPC_CheckField, 13, 1, 0, // 13096: check Inst[13] == 0x0 |
| 5926 | OPC_Decode, 197, 7, 206, 1, // 13100: decode to A2_maxp using decoder 206 |
| 5927 | // 13100: } |
| 5928 | 7, 0, // 13105: case 0x7: { |
| 5929 | OPC_CheckField, 13, 1, 0, // 13107: check Inst[13] == 0x0 |
| 5930 | OPC_Decode, 210, 8, 206, 1, // 13111: decode to A2_xorp using decoder 206 |
| 5931 | // 13111: } |
| 5932 | // 13111: } // switch Inst[23:21] |
| 5933 | // 13111: } |
| 5934 | 5, 69, // 13116: case 0x5: { |
| 5935 | OPC_SwitchField, 21, 3, // 13118: switch Inst[23:21] { |
| 5936 | 0, 9, // 13121: case 0x0: { |
| 5937 | OPC_CheckField, 13, 1, 0, // 13123: check Inst[13] == 0x0 |
| 5938 | OPC_Decode, 157, 8, 206, 1, // 13127: decode to A2_vaddw using decoder 206 |
| 5939 | // 13127: } |
| 5940 | 1, 9, // 13132: case 0x1: { |
| 5941 | OPC_CheckField, 13, 1, 0, // 13134: check Inst[13] == 0x0 |
| 5942 | OPC_Decode, 207, 8, 207, 1, // 13138: decode to A2_vsubw using decoder 207 |
| 5943 | // 13138: } |
| 5944 | 2, 9, // 13143: case 0x2: { |
| 5945 | OPC_CheckField, 13, 1, 0, // 13145: check Inst[13] == 0x0 |
| 5946 | OPC_Decode, 164, 8, 206, 1, // 13149: decode to A2_vavguh using decoder 206 |
| 5947 | // 13149: } |
| 5948 | 3, 9, // 13154: case 0x3: { |
| 5949 | OPC_CheckField, 13, 1, 0, // 13156: check Inst[13] == 0x0 |
| 5950 | OPC_Decode, 181, 7, 206, 1, // 13160: decode to A2_addpsat using decoder 206 |
| 5951 | // 13160: } |
| 5952 | 5, 9, // 13165: case 0x5: { |
| 5953 | OPC_CheckField, 13, 1, 0, // 13167: check Inst[13] == 0x0 |
| 5954 | OPC_Decode, 184, 8, 207, 1, // 13171: decode to A2_vmaxuw using decoder 207 |
| 5955 | // 13171: } |
| 5956 | 6, 0, // 13176: case 0x6: { |
| 5957 | OPC_CheckField, 13, 1, 0, // 13178: check Inst[13] == 0x0 |
| 5958 | OPC_Decode, 199, 7, 206, 1, // 13182: decode to A2_maxup using decoder 206 |
| 5959 | // 13182: } |
| 5960 | // 13182: } // switch Inst[23:21] |
| 5961 | // 13182: } |
| 5962 | 6, 80, // 13187: case 0x6: { |
| 5963 | OPC_SwitchField, 21, 3, // 13189: switch Inst[23:21] { |
| 5964 | 0, 9, // 13192: case 0x0: { |
| 5965 | OPC_CheckField, 13, 1, 0, // 13194: check Inst[13] == 0x0 |
| 5966 | OPC_Decode, 158, 8, 206, 1, // 13198: decode to A2_vaddws using decoder 206 |
| 5967 | // 13198: } |
| 5968 | 1, 9, // 13203: case 0x1: { |
| 5969 | OPC_CheckField, 13, 1, 0, // 13205: check Inst[13] == 0x0 |
| 5970 | OPC_Decode, 208, 8, 207, 1, // 13209: decode to A2_vsubws using decoder 207 |
| 5971 | // 13209: } |
| 5972 | 2, 9, // 13214: case 0x2: { |
| 5973 | OPC_CheckField, 13, 1, 0, // 13216: check Inst[13] == 0x0 |
| 5974 | OPC_Decode, 165, 8, 206, 1, // 13220: decode to A2_vavguhr using decoder 206 |
| 5975 | // 13220: } |
| 5976 | 3, 9, // 13225: case 0x3: { |
| 5977 | OPC_CheckField, 13, 1, 0, // 13227: check Inst[13] == 0x0 |
| 5978 | OPC_Decode, 184, 7, 206, 1, // 13231: decode to A2_addspl using decoder 206 |
| 5979 | // 13231: } |
| 5980 | 4, 9, // 13236: case 0x4: { |
| 5981 | OPC_CheckField, 13, 1, 0, // 13238: check Inst[13] == 0x0 |
| 5982 | OPC_Decode, 196, 8, 207, 1, // 13242: decode to A2_vnavgwcr using decoder 207 |
| 5983 | // 13242: } |
| 5984 | 5, 9, // 13247: case 0x5: { |
| 5985 | OPC_CheckField, 13, 1, 0, // 13249: check Inst[13] == 0x0 |
| 5986 | OPC_Decode, 201, 7, 207, 1, // 13253: decode to A2_minp using decoder 207 |
| 5987 | // 13253: } |
| 5988 | 6, 0, // 13258: case 0x6: { |
| 5989 | OPC_CheckField, 13, 1, 0, // 13260: check Inst[13] == 0x0 |
| 5990 | OPC_Decode, 180, 8, 207, 1, // 13264: decode to A2_vmaxb using decoder 207 |
| 5991 | // 13264: } |
| 5992 | // 13264: } // switch Inst[23:21] |
| 5993 | // 13264: } |
| 5994 | 7, 0, // 13269: case 0x7: { |
| 5995 | OPC_SwitchField, 21, 3, // 13271: switch Inst[23:21] { |
| 5996 | 0, 9, // 13274: case 0x0: { |
| 5997 | OPC_CheckField, 13, 1, 0, // 13276: check Inst[13] == 0x0 |
| 5998 | OPC_Decode, 180, 7, 206, 1, // 13280: decode to A2_addp using decoder 206 |
| 5999 | // 13280: } |
| 6000 | 1, 9, // 13285: case 0x1: { |
| 6001 | OPC_CheckField, 13, 1, 0, // 13287: check Inst[13] == 0x0 |
| 6002 | OPC_Decode, 254, 7, 207, 1, // 13291: decode to A2_subp using decoder 207 |
| 6003 | // 13291: } |
| 6004 | 3, 9, // 13296: case 0x3: { |
| 6005 | OPC_CheckField, 13, 1, 0, // 13298: check Inst[13] == 0x0 |
| 6006 | OPC_Decode, 183, 7, 206, 1, // 13302: decode to A2_addsph using decoder 206 |
| 6007 | // 13302: } |
| 6008 | 5, 9, // 13307: case 0x5: { |
| 6009 | OPC_CheckField, 13, 1, 0, // 13309: check Inst[13] == 0x0 |
| 6010 | OPC_Decode, 203, 7, 207, 1, // 13313: decode to A2_minup using decoder 207 |
| 6011 | // 13313: } |
| 6012 | 6, 9, // 13318: case 0x6: { |
| 6013 | OPC_CheckField, 13, 1, 0, // 13320: check Inst[13] == 0x0 |
| 6014 | OPC_Decode, 186, 8, 207, 1, // 13324: decode to A2_vminb using decoder 207 |
| 6015 | // 13324: } |
| 6016 | 7, 0, // 13329: case 0x7: { |
| 6017 | OPC_CheckField, 13, 1, 0, // 13331: check Inst[13] == 0x0 |
| 6018 | OPC_Decode, 237, 8, 134, 1, // 13335: decode to A4_modwrapu using decoder 134 |
| 6019 | // 13335: } |
| 6020 | // 13335: } // switch Inst[23:21] |
| 6021 | // 13335: } |
| 6022 | // 13335: } // switch Inst[7:5] |
| 6023 | // 13335: } |
| 6024 | 4, 33, // 13340: case 0x4: { |
| 6025 | OPC_SwitchField, 21, 3, // 13342: switch Inst[23:21] { |
| 6026 | 0, 13, // 13345: case 0x0: { |
| 6027 | OPC_CheckField, 13, 1, 0, // 13347: check Inst[13] == 0x0 |
| 6028 | OPC_CheckField, 5, 3, 0, // 13351: check Inst[7:5] == 0x0 |
| 6029 | OPC_Decode, 221, 26, 226, 1, // 13355: decode to dep_S2_packhl using decoder 226 |
| 6030 | // 13355: } |
| 6031 | 1, 0, // 13360: case 0x1: { |
| 6032 | OPC_CheckField, 13, 1, 0, // 13362: check Inst[13] == 0x0 |
| 6033 | OPC_CheckField, 5, 3, 0, // 13366: check Inst[7:5] == 0x0 |
| 6034 | OPC_Decode, 215, 8, 226, 1, // 13370: decode to A4_bitsplit using decoder 226 |
| 6035 | // 13370: } |
| 6036 | // 13370: } // switch Inst[23:21] |
| 6037 | // 13370: } |
| 6038 | 5, 128, 3, // 13375: case 0x5: { |
| 6039 | OPC_SwitchField, 5, 3, // 13378: switch Inst[7:5] { |
| 6040 | 0, 91, // 13381: case 0x0: { |
| 6041 | OPC_SwitchField, 21, 3, // 13383: switch Inst[23:21] { |
| 6042 | 0, 9, // 13386: case 0x0: { |
| 6043 | OPC_CheckField, 13, 1, 0, // 13388: check Inst[13] == 0x0 |
| 6044 | OPC_Decode, 176, 7, 227, 1, // 13392: decode to A2_addh_l16_ll using decoder 227 |
| 6045 | // 13392: } |
| 6046 | 1, 9, // 13397: case 0x1: { |
| 6047 | OPC_CheckField, 13, 1, 0, // 13399: check Inst[13] == 0x0 |
| 6048 | OPC_Decode, 251, 7, 227, 1, // 13403: decode to A2_subh_l16_ll using decoder 227 |
| 6049 | // 13403: } |
| 6050 | 2, 9, // 13408: case 0x2: { |
| 6051 | OPC_CheckField, 13, 1, 0, // 13410: check Inst[13] == 0x0 |
| 6052 | OPC_Decode, 170, 7, 227, 1, // 13414: decode to A2_addh_h16_ll using decoder 227 |
| 6053 | // 13414: } |
| 6054 | 3, 9, // 13419: case 0x3: { |
| 6055 | OPC_CheckField, 13, 1, 0, // 13421: check Inst[13] == 0x0 |
| 6056 | OPC_Decode, 245, 7, 227, 1, // 13425: decode to A2_subh_h16_ll using decoder 227 |
| 6057 | // 13425: } |
| 6058 | 4, 9, // 13430: case 0x4: { |
| 6059 | OPC_CheckField, 13, 1, 0, // 13432: check Inst[13] == 0x0 |
| 6060 | OPC_Decode, 219, 26, 134, 1, // 13436: decode to dep_A2_addsat using decoder 134 |
| 6061 | // 13436: } |
| 6062 | 5, 9, // 13441: case 0x5: { |
| 6063 | OPC_CheckField, 13, 1, 0, // 13443: check Inst[13] == 0x0 |
| 6064 | OPC_Decode, 200, 7, 227, 1, // 13447: decode to A2_min using decoder 227 |
| 6065 | // 13447: } |
| 6066 | 6, 9, // 13452: case 0x6: { |
| 6067 | OPC_CheckField, 13, 1, 0, // 13454: check Inst[13] == 0x0 |
| 6068 | OPC_Decode, 196, 7, 134, 1, // 13458: decode to A2_max using decoder 134 |
| 6069 | // 13458: } |
| 6070 | 7, 0, // 13463: case 0x7: { |
| 6071 | OPC_CheckField, 13, 1, 0, // 13465: check Inst[13] == 0x0 |
| 6072 | OPC_Decode, 254, 18, 134, 1, // 13469: decode to S4_parity using decoder 134 |
| 6073 | // 13469: } |
| 6074 | // 13469: } // switch Inst[23:21] |
| 6075 | // 13469: } |
| 6076 | 1, 25, // 13474: case 0x1: { |
| 6077 | OPC_SwitchField, 21, 3, // 13476: switch Inst[23:21] { |
| 6078 | 2, 9, // 13479: case 0x2: { |
| 6079 | OPC_CheckField, 13, 1, 0, // 13481: check Inst[13] == 0x0 |
| 6080 | OPC_Decode, 169, 7, 227, 1, // 13485: decode to A2_addh_h16_lh using decoder 227 |
| 6081 | // 13485: } |
| 6082 | 3, 0, // 13490: case 0x3: { |
| 6083 | OPC_CheckField, 13, 1, 0, // 13492: check Inst[13] == 0x0 |
| 6084 | OPC_Decode, 244, 7, 227, 1, // 13496: decode to A2_subh_h16_lh using decoder 227 |
| 6085 | // 13496: } |
| 6086 | // 13496: } // switch Inst[23:21] |
| 6087 | // 13496: } |
| 6088 | 2, 47, // 13501: case 0x2: { |
| 6089 | OPC_SwitchField, 21, 3, // 13503: switch Inst[23:21] { |
| 6090 | 0, 9, // 13506: case 0x0: { |
| 6091 | OPC_CheckField, 13, 1, 0, // 13508: check Inst[13] == 0x0 |
| 6092 | OPC_Decode, 175, 7, 227, 1, // 13512: decode to A2_addh_l16_hl using decoder 227 |
| 6093 | // 13512: } |
| 6094 | 1, 9, // 13517: case 0x1: { |
| 6095 | OPC_CheckField, 13, 1, 0, // 13519: check Inst[13] == 0x0 |
| 6096 | OPC_Decode, 250, 7, 227, 1, // 13523: decode to A2_subh_l16_hl using decoder 227 |
| 6097 | // 13523: } |
| 6098 | 2, 9, // 13528: case 0x2: { |
| 6099 | OPC_CheckField, 13, 1, 0, // 13530: check Inst[13] == 0x0 |
| 6100 | OPC_Decode, 168, 7, 227, 1, // 13534: decode to A2_addh_h16_hl using decoder 227 |
| 6101 | // 13534: } |
| 6102 | 3, 0, // 13539: case 0x3: { |
| 6103 | OPC_CheckField, 13, 1, 0, // 13541: check Inst[13] == 0x0 |
| 6104 | OPC_Decode, 243, 7, 227, 1, // 13545: decode to A2_subh_h16_hl using decoder 227 |
| 6105 | // 13545: } |
| 6106 | // 13545: } // switch Inst[23:21] |
| 6107 | // 13545: } |
| 6108 | 3, 25, // 13550: case 0x3: { |
| 6109 | OPC_SwitchField, 21, 3, // 13552: switch Inst[23:21] { |
| 6110 | 2, 9, // 13555: case 0x2: { |
| 6111 | OPC_CheckField, 13, 1, 0, // 13557: check Inst[13] == 0x0 |
| 6112 | OPC_Decode, 167, 7, 227, 1, // 13561: decode to A2_addh_h16_hh using decoder 227 |
| 6113 | // 13561: } |
| 6114 | 3, 0, // 13566: case 0x3: { |
| 6115 | OPC_CheckField, 13, 1, 0, // 13568: check Inst[13] == 0x0 |
| 6116 | OPC_Decode, 242, 7, 227, 1, // 13572: decode to A2_subh_h16_hh using decoder 227 |
| 6117 | // 13572: } |
| 6118 | // 13572: } // switch Inst[23:21] |
| 6119 | // 13572: } |
| 6120 | 4, 80, // 13577: case 0x4: { |
| 6121 | OPC_SwitchField, 21, 3, // 13579: switch Inst[23:21] { |
| 6122 | 0, 9, // 13582: case 0x0: { |
| 6123 | OPC_CheckField, 13, 1, 0, // 13584: check Inst[13] == 0x0 |
| 6124 | OPC_Decode, 178, 7, 227, 1, // 13588: decode to A2_addh_l16_sat_ll using decoder 227 |
| 6125 | // 13588: } |
| 6126 | 1, 9, // 13593: case 0x1: { |
| 6127 | OPC_CheckField, 13, 1, 0, // 13595: check Inst[13] == 0x0 |
| 6128 | OPC_Decode, 253, 7, 227, 1, // 13599: decode to A2_subh_l16_sat_ll using decoder 227 |
| 6129 | // 13599: } |
| 6130 | 2, 9, // 13604: case 0x2: { |
| 6131 | OPC_CheckField, 13, 1, 0, // 13606: check Inst[13] == 0x0 |
| 6132 | OPC_Decode, 174, 7, 227, 1, // 13610: decode to A2_addh_h16_sat_ll using decoder 227 |
| 6133 | // 13610: } |
| 6134 | 3, 9, // 13615: case 0x3: { |
| 6135 | OPC_CheckField, 13, 1, 0, // 13617: check Inst[13] == 0x0 |
| 6136 | OPC_Decode, 249, 7, 227, 1, // 13621: decode to A2_subh_h16_sat_ll using decoder 227 |
| 6137 | // 13621: } |
| 6138 | 4, 9, // 13626: case 0x4: { |
| 6139 | OPC_CheckField, 13, 1, 0, // 13628: check Inst[13] == 0x0 |
| 6140 | OPC_Decode, 220, 26, 227, 1, // 13632: decode to dep_A2_subsat using decoder 227 |
| 6141 | // 13632: } |
| 6142 | 5, 9, // 13637: case 0x5: { |
| 6143 | OPC_CheckField, 13, 1, 0, // 13639: check Inst[13] == 0x0 |
| 6144 | OPC_Decode, 202, 7, 227, 1, // 13643: decode to A2_minu using decoder 227 |
| 6145 | // 13643: } |
| 6146 | 6, 0, // 13648: case 0x6: { |
| 6147 | OPC_CheckField, 13, 1, 0, // 13650: check Inst[13] == 0x0 |
| 6148 | OPC_Decode, 198, 7, 134, 1, // 13654: decode to A2_maxu using decoder 134 |
| 6149 | // 13654: } |
| 6150 | // 13654: } // switch Inst[23:21] |
| 6151 | // 13654: } |
| 6152 | 5, 25, // 13659: case 0x5: { |
| 6153 | OPC_SwitchField, 21, 3, // 13661: switch Inst[23:21] { |
| 6154 | 2, 9, // 13664: case 0x2: { |
| 6155 | OPC_CheckField, 13, 1, 0, // 13666: check Inst[13] == 0x0 |
| 6156 | OPC_Decode, 173, 7, 227, 1, // 13670: decode to A2_addh_h16_sat_lh using decoder 227 |
| 6157 | // 13670: } |
| 6158 | 3, 0, // 13675: case 0x3: { |
| 6159 | OPC_CheckField, 13, 1, 0, // 13677: check Inst[13] == 0x0 |
| 6160 | OPC_Decode, 248, 7, 227, 1, // 13681: decode to A2_subh_h16_sat_lh using decoder 227 |
| 6161 | // 13681: } |
| 6162 | // 13681: } // switch Inst[23:21] |
| 6163 | // 13681: } |
| 6164 | 6, 47, // 13686: case 0x6: { |
| 6165 | OPC_SwitchField, 21, 3, // 13688: switch Inst[23:21] { |
| 6166 | 0, 9, // 13691: case 0x0: { |
| 6167 | OPC_CheckField, 13, 1, 0, // 13693: check Inst[13] == 0x0 |
| 6168 | OPC_Decode, 177, 7, 227, 1, // 13697: decode to A2_addh_l16_sat_hl using decoder 227 |
| 6169 | // 13697: } |
| 6170 | 1, 9, // 13702: case 0x1: { |
| 6171 | OPC_CheckField, 13, 1, 0, // 13704: check Inst[13] == 0x0 |
| 6172 | OPC_Decode, 252, 7, 227, 1, // 13708: decode to A2_subh_l16_sat_hl using decoder 227 |
| 6173 | // 13708: } |
| 6174 | 2, 9, // 13713: case 0x2: { |
| 6175 | OPC_CheckField, 13, 1, 0, // 13715: check Inst[13] == 0x0 |
| 6176 | OPC_Decode, 172, 7, 227, 1, // 13719: decode to A2_addh_h16_sat_hl using decoder 227 |
| 6177 | // 13719: } |
| 6178 | 3, 0, // 13724: case 0x3: { |
| 6179 | OPC_CheckField, 13, 1, 0, // 13726: check Inst[13] == 0x0 |
| 6180 | OPC_Decode, 247, 7, 227, 1, // 13730: decode to A2_subh_h16_sat_hl using decoder 227 |
| 6181 | // 13730: } |
| 6182 | // 13730: } // switch Inst[23:21] |
| 6183 | // 13730: } |
| 6184 | 7, 0, // 13735: case 0x7: { |
| 6185 | OPC_SwitchField, 21, 3, // 13737: switch Inst[23:21] { |
| 6186 | 2, 9, // 13740: case 0x2: { |
| 6187 | OPC_CheckField, 13, 1, 0, // 13742: check Inst[13] == 0x0 |
| 6188 | OPC_Decode, 171, 7, 227, 1, // 13746: decode to A2_addh_h16_sat_hh using decoder 227 |
| 6189 | // 13746: } |
| 6190 | 3, 0, // 13751: case 0x3: { |
| 6191 | OPC_CheckField, 13, 1, 0, // 13753: check Inst[13] == 0x0 |
| 6192 | OPC_Decode, 246, 7, 227, 1, // 13757: decode to A2_subh_h16_sat_hh using decoder 227 |
| 6193 | // 13757: } |
| 6194 | // 13757: } // switch Inst[23:21] |
| 6195 | // 13757: } |
| 6196 | // 13757: } // switch Inst[7:5] |
| 6197 | // 13757: } |
| 6198 | 6, 25, // 13762: case 0x6: { |
| 6199 | OPC_SwitchField, 22, 2, // 13764: switch Inst[23:22] { |
| 6200 | 0, 9, // 13767: case 0x0: { |
| 6201 | OPC_CheckField, 16, 5, 0, // 13769: check Inst[20:16] == 0x0 |
| 6202 | OPC_Decode, 180, 10, 228, 1, // 13773: decode to F2_sfimm_p using decoder 228 |
| 6203 | // 13773: } |
| 6204 | 1, 0, // 13778: case 0x1: { |
| 6205 | OPC_CheckField, 16, 5, 0, // 13780: check Inst[20:16] == 0x0 |
| 6206 | OPC_Decode, 179, 10, 228, 1, // 13784: decode to F2_sfimm_n using decoder 228 |
| 6207 | // 13784: } |
| 6208 | // 13784: } // switch Inst[23:22] |
| 6209 | // 13784: } |
| 6210 | 7, 9, // 13789: case 0x7: { |
| 6211 | OPC_CheckField, 23, 1, 0, // 13791: check Inst[23] == 0x0 |
| 6212 | OPC_Decode, 252, 15, 229, 1, // 13795: decode to M4_mpyrr_addi using decoder 229 |
| 6213 | // 13795: } |
| 6214 | 8, 5, // 13800: case 0x8: { |
| 6215 | OPC_Decode, 249, 15, 230, 1, // 13802: decode to M4_mpyri_addi using decoder 230 |
| 6216 | // 13802: } |
| 6217 | 9, 25, // 13807: case 0x9: { |
| 6218 | OPC_SwitchField, 22, 2, // 13809: switch Inst[23:22] { |
| 6219 | 0, 9, // 13812: case 0x0: { |
| 6220 | OPC_CheckField, 16, 5, 0, // 13814: check Inst[20:16] == 0x0 |
| 6221 | OPC_Decode, 157, 10, 231, 1, // 13818: decode to F2_dfimm_p using decoder 231 |
| 6222 | // 13818: } |
| 6223 | 1, 0, // 13823: case 0x1: { |
| 6224 | OPC_CheckField, 16, 5, 0, // 13825: check Inst[20:16] == 0x0 |
| 6225 | OPC_Decode, 156, 10, 231, 1, // 13829: decode to F2_dfimm_n using decoder 231 |
| 6226 | // 13829: } |
| 6227 | // 13829: } // switch Inst[23:22] |
| 6228 | // 13829: } |
| 6229 | 10, 24, // 13834: case 0xa: { |
| 6230 | OPC_SwitchField, 22, 2, // 13836: switch Inst[23:22] { |
| 6231 | 0, 5, // 13839: case 0x0: { |
| 6232 | OPC_Decode, 249, 18, 232, 1, // 13841: decode to S4_or_andi using decoder 232 |
| 6233 | // 13841: } |
| 6234 | 1, 5, // 13846: case 0x1: { |
| 6235 | OPC_Decode, 250, 18, 233, 1, // 13848: decode to S4_or_andix using decoder 233 |
| 6236 | // 13848: } |
| 6237 | 2, 0, // 13853: case 0x2: { |
| 6238 | OPC_Decode, 251, 18, 232, 1, // 13855: decode to S4_or_ori using decoder 232 |
| 6239 | // 13855: } |
| 6240 | // 13855: } // switch Inst[23:22] |
| 6241 | // 13855: } |
| 6242 | 11, 17, // 13860: case 0xb: { |
| 6243 | OPC_SwitchField, 23, 1, // 13862: switch Inst[23] { |
| 6244 | 0, 5, // 13865: case 0x0: { |
| 6245 | OPC_Decode, 234, 18, 234, 1, // 13867: decode to S4_addaddi using decoder 234 |
| 6246 | // 13867: } |
| 6247 | 1, 0, // 13872: case 0x1: { |
| 6248 | OPC_Decode, 249, 19, 235, 1, // 13874: decode to S4_subaddi using decoder 235 |
| 6249 | // 13874: } |
| 6250 | // 13874: } // switch Inst[23] |
| 6251 | // 13874: } |
| 6252 | 12, 132, 1, // 13879: case 0xc: { |
| 6253 | OPC_SwitchField, 21, 3, // 13882: switch Inst[23:21] { |
| 6254 | 0, 36, // 13885: case 0x0: { |
| 6255 | OPC_SwitchField, 2, 3, // 13887: switch Inst[4:2] { |
| 6256 | 0, 9, // 13890: case 0x0: { |
| 6257 | OPC_CheckField, 13, 1, 0, // 13892: check Inst[13] == 0x0 |
| 6258 | OPC_Decode, 149, 9, 236, 1, // 13896: decode to A4_vcmpbeqi using decoder 236 |
| 6259 | // 13896: } |
| 6260 | 2, 9, // 13901: case 0x2: { |
| 6261 | OPC_CheckField, 13, 1, 0, // 13903: check Inst[13] == 0x0 |
| 6262 | OPC_Decode, 153, 9, 237, 1, // 13907: decode to A4_vcmpheqi using decoder 237 |
| 6263 | // 13907: } |
| 6264 | 4, 0, // 13912: case 0x4: { |
| 6265 | OPC_CheckField, 13, 1, 0, // 13914: check Inst[13] == 0x0 |
| 6266 | OPC_Decode, 156, 9, 237, 1, // 13918: decode to A4_vcmpweqi using decoder 237 |
| 6267 | // 13918: } |
| 6268 | // 13918: } // switch Inst[4:2] |
| 6269 | // 13918: } |
| 6270 | 1, 36, // 13923: case 0x1: { |
| 6271 | OPC_SwitchField, 2, 3, // 13925: switch Inst[4:2] { |
| 6272 | 0, 9, // 13928: case 0x0: { |
| 6273 | OPC_CheckField, 13, 1, 0, // 13930: check Inst[13] == 0x0 |
| 6274 | OPC_Decode, 151, 9, 237, 1, // 13934: decode to A4_vcmpbgti using decoder 237 |
| 6275 | // 13934: } |
| 6276 | 2, 9, // 13939: case 0x2: { |
| 6277 | OPC_CheckField, 13, 1, 0, // 13941: check Inst[13] == 0x0 |
| 6278 | OPC_Decode, 154, 9, 237, 1, // 13945: decode to A4_vcmphgti using decoder 237 |
| 6279 | // 13945: } |
| 6280 | 4, 0, // 13950: case 0x4: { |
| 6281 | OPC_CheckField, 13, 1, 0, // 13952: check Inst[13] == 0x0 |
| 6282 | OPC_Decode, 157, 9, 237, 1, // 13956: decode to A4_vcmpwgti using decoder 237 |
| 6283 | // 13956: } |
| 6284 | // 13956: } // switch Inst[4:2] |
| 6285 | // 13956: } |
| 6286 | 2, 36, // 13961: case 0x2: { |
| 6287 | OPC_SwitchField, 2, 3, // 13963: switch Inst[4:2] { |
| 6288 | 0, 9, // 13966: case 0x0: { |
| 6289 | OPC_CheckField, 12, 2, 0, // 13968: check Inst[13:12] == 0x0 |
| 6290 | OPC_Decode, 152, 9, 238, 1, // 13972: decode to A4_vcmpbgtui using decoder 238 |
| 6291 | // 13972: } |
| 6292 | 2, 9, // 13977: case 0x2: { |
| 6293 | OPC_CheckField, 12, 2, 0, // 13979: check Inst[13:12] == 0x0 |
| 6294 | OPC_Decode, 155, 9, 238, 1, // 13983: decode to A4_vcmphgtui using decoder 238 |
| 6295 | // 13983: } |
| 6296 | 4, 0, // 13988: case 0x4: { |
| 6297 | OPC_CheckField, 12, 2, 0, // 13990: check Inst[13:12] == 0x0 |
| 6298 | OPC_Decode, 158, 9, 238, 1, // 13994: decode to A4_vcmpwgtui using decoder 238 |
| 6299 | // 13994: } |
| 6300 | // 13994: } // switch Inst[4:2] |
| 6301 | // 13994: } |
| 6302 | 4, 0, // 13999: case 0x4: { |
| 6303 | OPC_CheckField, 10, 4, 0, // 14001: check Inst[13:10] == 0x0 |
| 6304 | OPC_CheckField, 2, 3, 4, // 14005: check Inst[4:2] == 0x4 |
| 6305 | OPC_Decode, 151, 10, 239, 1, // 14009: decode to F2_dfclass using decoder 239 |
| 6306 | // 14009: } |
| 6307 | // 14009: } // switch Inst[23:21] |
| 6308 | // 14009: } |
| 6309 | 13, 84, // 14014: case 0xd: { |
| 6310 | OPC_SwitchField, 21, 3, // 14016: switch Inst[23:21] { |
| 6311 | 0, 25, // 14019: case 0x0: { |
| 6312 | OPC_SwitchField, 2, 3, // 14021: switch Inst[4:2] { |
| 6313 | 0, 9, // 14024: case 0x0: { |
| 6314 | OPC_CheckField, 13, 1, 0, // 14026: check Inst[13] == 0x0 |
| 6315 | OPC_Decode, 220, 8, 240, 1, // 14030: decode to A4_cmpbeqi using decoder 240 |
| 6316 | // 14030: } |
| 6317 | 2, 0, // 14035: case 0x2: { |
| 6318 | OPC_CheckField, 13, 1, 0, // 14037: check Inst[13] == 0x0 |
| 6319 | OPC_Decode, 226, 8, 241, 1, // 14041: decode to A4_cmpheqi using decoder 241 |
| 6320 | // 14041: } |
| 6321 | // 14041: } // switch Inst[4:2] |
| 6322 | // 14041: } |
| 6323 | 1, 25, // 14046: case 0x1: { |
| 6324 | OPC_SwitchField, 2, 3, // 14048: switch Inst[4:2] { |
| 6325 | 0, 9, // 14051: case 0x0: { |
| 6326 | OPC_CheckField, 13, 1, 0, // 14053: check Inst[13] == 0x0 |
| 6327 | OPC_Decode, 222, 8, 242, 1, // 14057: decode to A4_cmpbgti using decoder 242 |
| 6328 | // 14057: } |
| 6329 | 2, 0, // 14062: case 0x2: { |
| 6330 | OPC_CheckField, 13, 1, 0, // 14064: check Inst[13] == 0x0 |
| 6331 | OPC_Decode, 228, 8, 241, 1, // 14068: decode to A4_cmphgti using decoder 241 |
| 6332 | // 14068: } |
| 6333 | // 14068: } // switch Inst[4:2] |
| 6334 | // 14068: } |
| 6335 | 2, 0, // 14073: case 0x2: { |
| 6336 | OPC_SwitchField, 2, 3, // 14075: switch Inst[4:2] { |
| 6337 | 0, 9, // 14078: case 0x0: { |
| 6338 | OPC_CheckField, 12, 2, 0, // 14080: check Inst[13:12] == 0x0 |
| 6339 | OPC_Decode, 224, 8, 243, 1, // 14084: decode to A4_cmpbgtui using decoder 243 |
| 6340 | // 14084: } |
| 6341 | 2, 0, // 14089: case 0x2: { |
| 6342 | OPC_CheckField, 12, 2, 0, // 14091: check Inst[13:12] == 0x0 |
| 6343 | OPC_Decode, 230, 8, 243, 1, // 14095: decode to A4_cmphgtui using decoder 243 |
| 6344 | // 14095: } |
| 6345 | // 14095: } // switch Inst[4:2] |
| 6346 | // 14095: } |
| 6347 | // 14095: } // switch Inst[23:21] |
| 6348 | // 14095: } |
| 6349 | 14, 79, // 14100: case 0xe: { |
| 6350 | OPC_SwitchField, 0, 3, // 14102: switch Inst[2:0] { |
| 6351 | 0, 17, // 14105: case 0x0: { |
| 6352 | OPC_SwitchField, 4, 1, // 14107: switch Inst[4] { |
| 6353 | 0, 5, // 14110: case 0x0: { |
| 6354 | OPC_Decode, 237, 18, 244, 1, // 14112: decode to S4_andi_asl_ri using decoder 244 |
| 6355 | // 14112: } |
| 6356 | 1, 0, // 14117: case 0x1: { |
| 6357 | OPC_Decode, 238, 18, 244, 1, // 14119: decode to S4_andi_lsr_ri using decoder 244 |
| 6358 | // 14119: } |
| 6359 | // 14119: } // switch Inst[4] |
| 6360 | // 14119: } |
| 6361 | 2, 17, // 14124: case 0x2: { |
| 6362 | OPC_SwitchField, 4, 1, // 14126: switch Inst[4] { |
| 6363 | 0, 5, // 14129: case 0x0: { |
| 6364 | OPC_Decode, 252, 18, 244, 1, // 14131: decode to S4_ori_asl_ri using decoder 244 |
| 6365 | // 14131: } |
| 6366 | 1, 0, // 14136: case 0x1: { |
| 6367 | OPC_Decode, 253, 18, 244, 1, // 14138: decode to S4_ori_lsr_ri using decoder 244 |
| 6368 | // 14138: } |
| 6369 | // 14138: } // switch Inst[4] |
| 6370 | // 14138: } |
| 6371 | 4, 17, // 14143: case 0x4: { |
| 6372 | OPC_SwitchField, 4, 1, // 14145: switch Inst[4] { |
| 6373 | 0, 5, // 14148: case 0x0: { |
| 6374 | OPC_Decode, 235, 18, 244, 1, // 14150: decode to S4_addi_asl_ri using decoder 244 |
| 6375 | // 14150: } |
| 6376 | 1, 0, // 14155: case 0x1: { |
| 6377 | OPC_Decode, 236, 18, 244, 1, // 14157: decode to S4_addi_lsr_ri using decoder 244 |
| 6378 | // 14157: } |
| 6379 | // 14157: } // switch Inst[4] |
| 6380 | // 14157: } |
| 6381 | 6, 0, // 14162: case 0x6: { |
| 6382 | OPC_SwitchField, 4, 1, // 14164: switch Inst[4] { |
| 6383 | 0, 5, // 14167: case 0x0: { |
| 6384 | OPC_Decode, 250, 19, 244, 1, // 14169: decode to S4_subi_asl_ri using decoder 244 |
| 6385 | // 14169: } |
| 6386 | 1, 0, // 14174: case 0x1: { |
| 6387 | OPC_Decode, 251, 19, 244, 1, // 14176: decode to S4_subi_lsr_ri using decoder 244 |
| 6388 | // 14176: } |
| 6389 | // 14176: } // switch Inst[4] |
| 6390 | // 14176: } |
| 6391 | // 14176: } // switch Inst[2:0] |
| 6392 | // 14176: } |
| 6393 | 15, 0, // 14181: case 0xf: { |
| 6394 | OPC_SwitchField, 23, 1, // 14183: switch Inst[23] { |
| 6395 | 0, 5, // 14186: case 0x0: { |
| 6396 | OPC_Decode, 251, 15, 245, 1, // 14188: decode to M4_mpyri_addr_u2 using decoder 245 |
| 6397 | // 14188: } |
| 6398 | 1, 0, // 14193: case 0x1: { |
| 6399 | OPC_Decode, 250, 15, 246, 1, // 14195: decode to M4_mpyri_addr using decoder 246 |
| 6400 | // 14195: } |
| 6401 | // 14195: } // switch Inst[23] |
| 6402 | // 14195: } |
| 6403 | // 14195: } // switch Inst[27:24] |
| 6404 | // 14195: } |
| 6405 | 14, 146, 34, // 14200: case 0xe: { |
| 6406 | OPC_SwitchField, 21, 7, // 14203: switch Inst[27:21] { |
| 6407 | 0, 9, // 14206: case 0x0: { |
| 6408 | OPC_CheckField, 13, 1, 0, // 14208: check Inst[13] == 0x0 |
| 6409 | OPC_Decode, 137, 15, 247, 1, // 14212: decode to M2_mpysip using decoder 247 |
| 6410 | // 14212: } |
| 6411 | 4, 9, // 14217: case 0x4: { |
| 6412 | OPC_CheckField, 13, 1, 0, // 14219: check Inst[13] == 0x0 |
| 6413 | OPC_Decode, 136, 15, 247, 1, // 14223: decode to M2_mpysin using decoder 247 |
| 6414 | // 14223: } |
| 6415 | 8, 9, // 14228: case 0x8: { |
| 6416 | OPC_CheckField, 13, 1, 0, // 14230: check Inst[13] == 0x0 |
| 6417 | OPC_Decode, 130, 14, 248, 1, // 14234: decode to M2_macsip using decoder 248 |
| 6418 | // 14234: } |
| 6419 | 12, 9, // 14239: case 0xc: { |
| 6420 | OPC_CheckField, 13, 1, 0, // 14241: check Inst[13] == 0x0 |
| 6421 | OPC_Decode, 129, 14, 248, 1, // 14245: decode to M2_macsin using decoder 248 |
| 6422 | // 14245: } |
| 6423 | 16, 9, // 14250: case 0x10: { |
| 6424 | OPC_CheckField, 13, 1, 0, // 14252: check Inst[13] == 0x0 |
| 6425 | OPC_Decode, 224, 13, 249, 1, // 14256: decode to M2_accii using decoder 249 |
| 6426 | // 14256: } |
| 6427 | 20, 9, // 14261: case 0x14: { |
| 6428 | OPC_CheckField, 13, 1, 0, // 14263: check Inst[13] == 0x0 |
| 6429 | OPC_Decode, 189, 15, 249, 1, // 14267: decode to M2_naccii using decoder 249 |
| 6430 | // 14267: } |
| 6431 | 24, 13, // 14272: case 0x18: { |
| 6432 | OPC_CheckField, 13, 1, 0, // 14274: check Inst[13] == 0x0 |
| 6433 | OPC_CheckField, 5, 3, 0, // 14278: check Inst[7:5] == 0x0 |
| 6434 | OPC_Decode, 253, 15, 250, 1, // 14282: decode to M4_mpyrr_addr using decoder 250 |
| 6435 | // 14282: } |
| 6436 | 32, 47, // 14287: case 0x20: { |
| 6437 | OPC_SwitchField, 5, 3, // 14289: switch Inst[7:5] { |
| 6438 | 0, 9, // 14292: case 0x0: { |
| 6439 | OPC_CheckField, 13, 1, 0, // 14294: check Inst[13] == 0x0 |
| 6440 | OPC_Decode, 245, 14, 226, 1, // 14298: decode to M2_mpyd_ll_s0 using decoder 226 |
| 6441 | // 14298: } |
| 6442 | 1, 9, // 14303: case 0x1: { |
| 6443 | OPC_CheckField, 13, 1, 0, // 14305: check Inst[13] == 0x0 |
| 6444 | OPC_Decode, 243, 14, 226, 1, // 14309: decode to M2_mpyd_lh_s0 using decoder 226 |
| 6445 | // 14309: } |
| 6446 | 2, 9, // 14314: case 0x2: { |
| 6447 | OPC_CheckField, 13, 1, 0, // 14316: check Inst[13] == 0x0 |
| 6448 | OPC_Decode, 241, 14, 226, 1, // 14320: decode to M2_mpyd_hl_s0 using decoder 226 |
| 6449 | // 14320: } |
| 6450 | 3, 0, // 14325: case 0x3: { |
| 6451 | OPC_CheckField, 13, 1, 0, // 14327: check Inst[13] == 0x0 |
| 6452 | OPC_Decode, 239, 14, 226, 1, // 14331: decode to M2_mpyd_hh_s0 using decoder 226 |
| 6453 | // 14331: } |
| 6454 | // 14331: } // switch Inst[7:5] |
| 6455 | // 14331: } |
| 6456 | 33, 47, // 14336: case 0x21: { |
| 6457 | OPC_SwitchField, 5, 3, // 14338: switch Inst[7:5] { |
| 6458 | 0, 9, // 14341: case 0x0: { |
| 6459 | OPC_CheckField, 13, 1, 0, // 14343: check Inst[13] == 0x0 |
| 6460 | OPC_Decode, 133, 15, 226, 1, // 14347: decode to M2_mpyd_rnd_ll_s0 using decoder 226 |
| 6461 | // 14347: } |
| 6462 | 1, 9, // 14352: case 0x1: { |
| 6463 | OPC_CheckField, 13, 1, 0, // 14354: check Inst[13] == 0x0 |
| 6464 | OPC_Decode, 131, 15, 226, 1, // 14358: decode to M2_mpyd_rnd_lh_s0 using decoder 226 |
| 6465 | // 14358: } |
| 6466 | 2, 9, // 14363: case 0x2: { |
| 6467 | OPC_CheckField, 13, 1, 0, // 14365: check Inst[13] == 0x0 |
| 6468 | OPC_Decode, 129, 15, 226, 1, // 14369: decode to M2_mpyd_rnd_hl_s0 using decoder 226 |
| 6469 | // 14369: } |
| 6470 | 3, 0, // 14374: case 0x3: { |
| 6471 | OPC_CheckField, 13, 1, 0, // 14376: check Inst[13] == 0x0 |
| 6472 | OPC_Decode, 255, 14, 226, 1, // 14380: decode to M2_mpyd_rnd_hh_s0 using decoder 226 |
| 6473 | // 14380: } |
| 6474 | // 14380: } // switch Inst[7:5] |
| 6475 | // 14380: } |
| 6476 | 34, 47, // 14385: case 0x22: { |
| 6477 | OPC_SwitchField, 5, 3, // 14387: switch Inst[7:5] { |
| 6478 | 0, 9, // 14390: case 0x0: { |
| 6479 | OPC_CheckField, 13, 1, 0, // 14392: check Inst[13] == 0x0 |
| 6480 | OPC_Decode, 178, 15, 226, 1, // 14396: decode to M2_mpyud_ll_s0 using decoder 226 |
| 6481 | // 14396: } |
| 6482 | 1, 9, // 14401: case 0x1: { |
| 6483 | OPC_CheckField, 13, 1, 0, // 14403: check Inst[13] == 0x0 |
| 6484 | OPC_Decode, 176, 15, 226, 1, // 14407: decode to M2_mpyud_lh_s0 using decoder 226 |
| 6485 | // 14407: } |
| 6486 | 2, 9, // 14412: case 0x2: { |
| 6487 | OPC_CheckField, 13, 1, 0, // 14414: check Inst[13] == 0x0 |
| 6488 | OPC_Decode, 174, 15, 226, 1, // 14418: decode to M2_mpyud_hl_s0 using decoder 226 |
| 6489 | // 14418: } |
| 6490 | 3, 0, // 14423: case 0x3: { |
| 6491 | OPC_CheckField, 13, 1, 0, // 14425: check Inst[13] == 0x0 |
| 6492 | OPC_Decode, 172, 15, 226, 1, // 14429: decode to M2_mpyud_hh_s0 using decoder 226 |
| 6493 | // 14429: } |
| 6494 | // 14429: } // switch Inst[7:5] |
| 6495 | // 14429: } |
| 6496 | 36, 47, // 14434: case 0x24: { |
| 6497 | OPC_SwitchField, 5, 3, // 14436: switch Inst[7:5] { |
| 6498 | 0, 9, // 14439: case 0x0: { |
| 6499 | OPC_CheckField, 13, 1, 0, // 14441: check Inst[13] == 0x0 |
| 6500 | OPC_Decode, 246, 14, 226, 1, // 14445: decode to M2_mpyd_ll_s1 using decoder 226 |
| 6501 | // 14445: } |
| 6502 | 1, 9, // 14450: case 0x1: { |
| 6503 | OPC_CheckField, 13, 1, 0, // 14452: check Inst[13] == 0x0 |
| 6504 | OPC_Decode, 244, 14, 226, 1, // 14456: decode to M2_mpyd_lh_s1 using decoder 226 |
| 6505 | // 14456: } |
| 6506 | 2, 9, // 14461: case 0x2: { |
| 6507 | OPC_CheckField, 13, 1, 0, // 14463: check Inst[13] == 0x0 |
| 6508 | OPC_Decode, 242, 14, 226, 1, // 14467: decode to M2_mpyd_hl_s1 using decoder 226 |
| 6509 | // 14467: } |
| 6510 | 3, 0, // 14472: case 0x3: { |
| 6511 | OPC_CheckField, 13, 1, 0, // 14474: check Inst[13] == 0x0 |
| 6512 | OPC_Decode, 240, 14, 226, 1, // 14478: decode to M2_mpyd_hh_s1 using decoder 226 |
| 6513 | // 14478: } |
| 6514 | // 14478: } // switch Inst[7:5] |
| 6515 | // 14478: } |
| 6516 | 37, 47, // 14483: case 0x25: { |
| 6517 | OPC_SwitchField, 5, 3, // 14485: switch Inst[7:5] { |
| 6518 | 0, 9, // 14488: case 0x0: { |
| 6519 | OPC_CheckField, 13, 1, 0, // 14490: check Inst[13] == 0x0 |
| 6520 | OPC_Decode, 134, 15, 226, 1, // 14494: decode to M2_mpyd_rnd_ll_s1 using decoder 226 |
| 6521 | // 14494: } |
| 6522 | 1, 9, // 14499: case 0x1: { |
| 6523 | OPC_CheckField, 13, 1, 0, // 14501: check Inst[13] == 0x0 |
| 6524 | OPC_Decode, 132, 15, 226, 1, // 14505: decode to M2_mpyd_rnd_lh_s1 using decoder 226 |
| 6525 | // 14505: } |
| 6526 | 2, 9, // 14510: case 0x2: { |
| 6527 | OPC_CheckField, 13, 1, 0, // 14512: check Inst[13] == 0x0 |
| 6528 | OPC_Decode, 130, 15, 226, 1, // 14516: decode to M2_mpyd_rnd_hl_s1 using decoder 226 |
| 6529 | // 14516: } |
| 6530 | 3, 0, // 14521: case 0x3: { |
| 6531 | OPC_CheckField, 13, 1, 0, // 14523: check Inst[13] == 0x0 |
| 6532 | OPC_Decode, 128, 15, 226, 1, // 14527: decode to M2_mpyd_rnd_hh_s1 using decoder 226 |
| 6533 | // 14527: } |
| 6534 | // 14527: } // switch Inst[7:5] |
| 6535 | // 14527: } |
| 6536 | 38, 47, // 14532: case 0x26: { |
| 6537 | OPC_SwitchField, 5, 3, // 14534: switch Inst[7:5] { |
| 6538 | 0, 9, // 14537: case 0x0: { |
| 6539 | OPC_CheckField, 13, 1, 0, // 14539: check Inst[13] == 0x0 |
| 6540 | OPC_Decode, 179, 15, 226, 1, // 14543: decode to M2_mpyud_ll_s1 using decoder 226 |
| 6541 | // 14543: } |
| 6542 | 1, 9, // 14548: case 0x1: { |
| 6543 | OPC_CheckField, 13, 1, 0, // 14550: check Inst[13] == 0x0 |
| 6544 | OPC_Decode, 177, 15, 226, 1, // 14554: decode to M2_mpyud_lh_s1 using decoder 226 |
| 6545 | // 14554: } |
| 6546 | 2, 9, // 14559: case 0x2: { |
| 6547 | OPC_CheckField, 13, 1, 0, // 14561: check Inst[13] == 0x0 |
| 6548 | OPC_Decode, 175, 15, 226, 1, // 14565: decode to M2_mpyud_hl_s1 using decoder 226 |
| 6549 | // 14565: } |
| 6550 | 3, 0, // 14570: case 0x3: { |
| 6551 | OPC_CheckField, 13, 1, 0, // 14572: check Inst[13] == 0x0 |
| 6552 | OPC_Decode, 173, 15, 226, 1, // 14576: decode to M2_mpyud_hh_s1 using decoder 226 |
| 6553 | // 14576: } |
| 6554 | // 14576: } // switch Inst[7:5] |
| 6555 | // 14576: } |
| 6556 | 40, 69, // 14581: case 0x28: { |
| 6557 | OPC_SwitchField, 5, 3, // 14583: switch Inst[7:5] { |
| 6558 | 0, 9, // 14586: case 0x0: { |
| 6559 | OPC_CheckField, 13, 1, 0, // 14588: check Inst[13] == 0x0 |
| 6560 | OPC_Decode, 248, 13, 226, 1, // 14592: decode to M2_dpmpyss_s0 using decoder 226 |
| 6561 | // 14592: } |
| 6562 | 1, 9, // 14597: case 0x1: { |
| 6563 | OPC_CheckField, 13, 1, 0, // 14599: check Inst[13] == 0x0 |
| 6564 | OPC_Decode, 231, 13, 226, 1, // 14603: decode to M2_cmpyi_s0 using decoder 226 |
| 6565 | // 14603: } |
| 6566 | 2, 9, // 14608: case 0x2: { |
| 6567 | OPC_CheckField, 13, 1, 0, // 14610: check Inst[13] == 0x0 |
| 6568 | OPC_Decode, 232, 13, 226, 1, // 14614: decode to M2_cmpyr_s0 using decoder 226 |
| 6569 | // 14614: } |
| 6570 | 5, 9, // 14619: case 0x5: { |
| 6571 | OPC_CheckField, 13, 1, 0, // 14621: check Inst[13] == 0x0 |
| 6572 | OPC_Decode, 215, 15, 226, 1, // 14625: decode to M2_vmpy2s_s0 using decoder 226 |
| 6573 | // 14625: } |
| 6574 | 6, 9, // 14630: case 0x6: { |
| 6575 | OPC_CheckField, 13, 1, 0, // 14632: check Inst[13] == 0x0 |
| 6576 | OPC_Decode, 237, 13, 226, 1, // 14636: decode to M2_cmpys_s0 using decoder 226 |
| 6577 | // 14636: } |
| 6578 | 7, 0, // 14641: case 0x7: { |
| 6579 | OPC_CheckField, 13, 1, 0, // 14643: check Inst[13] == 0x0 |
| 6580 | OPC_Decode, 219, 15, 226, 1, // 14647: decode to M2_vmpy2su_s0 using decoder 226 |
| 6581 | // 14647: } |
| 6582 | // 14647: } // switch Inst[7:5] |
| 6583 | // 14647: } |
| 6584 | 42, 47, // 14652: case 0x2a: { |
| 6585 | OPC_SwitchField, 5, 3, // 14654: switch Inst[7:5] { |
| 6586 | 0, 9, // 14657: case 0x0: { |
| 6587 | OPC_CheckField, 13, 1, 0, // 14659: check Inst[13] == 0x0 |
| 6588 | OPC_Decode, 251, 13, 226, 1, // 14663: decode to M2_dpmpyuu_s0 using decoder 226 |
| 6589 | // 14663: } |
| 6590 | 1, 9, // 14668: case 0x1: { |
| 6591 | OPC_CheckField, 13, 1, 0, // 14670: check Inst[13] == 0x0 |
| 6592 | OPC_Decode, 151, 16, 226, 1, // 14674: decode to M5_vmpybsu using decoder 226 |
| 6593 | // 14674: } |
| 6594 | 6, 9, // 14679: case 0x6: { |
| 6595 | OPC_CheckField, 13, 1, 0, // 14681: check Inst[13] == 0x0 |
| 6596 | OPC_Decode, 239, 13, 226, 1, // 14685: decode to M2_cmpysc_s0 using decoder 226 |
| 6597 | // 14685: } |
| 6598 | 7, 0, // 14690: case 0x7: { |
| 6599 | OPC_CheckField, 13, 1, 0, // 14692: check Inst[13] == 0x0 |
| 6600 | OPC_Decode, 131, 16, 226, 1, // 14696: decode to M4_pmpyw using decoder 226 |
| 6601 | // 14696: } |
| 6602 | // 14696: } // switch Inst[7:5] |
| 6603 | // 14696: } |
| 6604 | 44, 47, // 14701: case 0x2c: { |
| 6605 | OPC_SwitchField, 5, 3, // 14703: switch Inst[7:5] { |
| 6606 | 1, 9, // 14706: case 0x1: { |
| 6607 | OPC_CheckField, 13, 1, 0, // 14708: check Inst[13] == 0x0 |
| 6608 | OPC_Decode, 152, 16, 226, 1, // 14712: decode to M5_vmpybuu using decoder 226 |
| 6609 | // 14712: } |
| 6610 | 5, 9, // 14717: case 0x5: { |
| 6611 | OPC_CheckField, 13, 1, 0, // 14719: check Inst[13] == 0x0 |
| 6612 | OPC_Decode, 217, 15, 226, 1, // 14723: decode to M2_vmpy2s_s1 using decoder 226 |
| 6613 | // 14723: } |
| 6614 | 6, 9, // 14728: case 0x6: { |
| 6615 | OPC_CheckField, 13, 1, 0, // 14730: check Inst[13] == 0x0 |
| 6616 | OPC_Decode, 238, 13, 226, 1, // 14734: decode to M2_cmpys_s1 using decoder 226 |
| 6617 | // 14734: } |
| 6618 | 7, 0, // 14739: case 0x7: { |
| 6619 | OPC_CheckField, 13, 1, 0, // 14741: check Inst[13] == 0x0 |
| 6620 | OPC_Decode, 220, 15, 226, 1, // 14745: decode to M2_vmpy2su_s1 using decoder 226 |
| 6621 | // 14745: } |
| 6622 | // 14745: } // switch Inst[7:5] |
| 6623 | // 14745: } |
| 6624 | 46, 25, // 14750: case 0x2e: { |
| 6625 | OPC_SwitchField, 5, 3, // 14752: switch Inst[7:5] { |
| 6626 | 6, 9, // 14755: case 0x6: { |
| 6627 | OPC_CheckField, 13, 1, 0, // 14757: check Inst[13] == 0x0 |
| 6628 | OPC_Decode, 240, 13, 226, 1, // 14761: decode to M2_cmpysc_s1 using decoder 226 |
| 6629 | // 14761: } |
| 6630 | 7, 0, // 14766: case 0x7: { |
| 6631 | OPC_CheckField, 13, 1, 0, // 14768: check Inst[13] == 0x0 |
| 6632 | OPC_Decode, 133, 16, 226, 1, // 14772: decode to M4_vpmpyh using decoder 226 |
| 6633 | // 14772: } |
| 6634 | // 14772: } // switch Inst[7:5] |
| 6635 | // 14772: } |
| 6636 | 48, 47, // 14777: case 0x30: { |
| 6637 | OPC_SwitchField, 5, 3, // 14779: switch Inst[7:5] { |
| 6638 | 0, 9, // 14782: case 0x0: { |
| 6639 | OPC_CheckField, 13, 1, 0, // 14784: check Inst[13] == 0x0 |
| 6640 | OPC_Decode, 237, 14, 251, 1, // 14788: decode to M2_mpyd_acc_ll_s0 using decoder 251 |
| 6641 | // 14788: } |
| 6642 | 1, 9, // 14793: case 0x1: { |
| 6643 | OPC_CheckField, 13, 1, 0, // 14795: check Inst[13] == 0x0 |
| 6644 | OPC_Decode, 235, 14, 251, 1, // 14799: decode to M2_mpyd_acc_lh_s0 using decoder 251 |
| 6645 | // 14799: } |
| 6646 | 2, 9, // 14804: case 0x2: { |
| 6647 | OPC_CheckField, 13, 1, 0, // 14806: check Inst[13] == 0x0 |
| 6648 | OPC_Decode, 233, 14, 251, 1, // 14810: decode to M2_mpyd_acc_hl_s0 using decoder 251 |
| 6649 | // 14810: } |
| 6650 | 3, 0, // 14815: case 0x3: { |
| 6651 | OPC_CheckField, 13, 1, 0, // 14817: check Inst[13] == 0x0 |
| 6652 | OPC_Decode, 231, 14, 251, 1, // 14821: decode to M2_mpyd_acc_hh_s0 using decoder 251 |
| 6653 | // 14821: } |
| 6654 | // 14821: } // switch Inst[7:5] |
| 6655 | // 14821: } |
| 6656 | 49, 47, // 14826: case 0x31: { |
| 6657 | OPC_SwitchField, 5, 3, // 14828: switch Inst[7:5] { |
| 6658 | 0, 9, // 14831: case 0x0: { |
| 6659 | OPC_CheckField, 13, 1, 0, // 14833: check Inst[13] == 0x0 |
| 6660 | OPC_Decode, 253, 14, 251, 1, // 14837: decode to M2_mpyd_nac_ll_s0 using decoder 251 |
| 6661 | // 14837: } |
| 6662 | 1, 9, // 14842: case 0x1: { |
| 6663 | OPC_CheckField, 13, 1, 0, // 14844: check Inst[13] == 0x0 |
| 6664 | OPC_Decode, 251, 14, 251, 1, // 14848: decode to M2_mpyd_nac_lh_s0 using decoder 251 |
| 6665 | // 14848: } |
| 6666 | 2, 9, // 14853: case 0x2: { |
| 6667 | OPC_CheckField, 13, 1, 0, // 14855: check Inst[13] == 0x0 |
| 6668 | OPC_Decode, 249, 14, 251, 1, // 14859: decode to M2_mpyd_nac_hl_s0 using decoder 251 |
| 6669 | // 14859: } |
| 6670 | 3, 0, // 14864: case 0x3: { |
| 6671 | OPC_CheckField, 13, 1, 0, // 14866: check Inst[13] == 0x0 |
| 6672 | OPC_Decode, 247, 14, 251, 1, // 14870: decode to M2_mpyd_nac_hh_s0 using decoder 251 |
| 6673 | // 14870: } |
| 6674 | // 14870: } // switch Inst[7:5] |
| 6675 | // 14870: } |
| 6676 | 50, 47, // 14875: case 0x32: { |
| 6677 | OPC_SwitchField, 5, 3, // 14877: switch Inst[7:5] { |
| 6678 | 0, 9, // 14880: case 0x0: { |
| 6679 | OPC_CheckField, 13, 1, 0, // 14882: check Inst[13] == 0x0 |
| 6680 | OPC_Decode, 170, 15, 251, 1, // 14886: decode to M2_mpyud_acc_ll_s0 using decoder 251 |
| 6681 | // 14886: } |
| 6682 | 1, 9, // 14891: case 0x1: { |
| 6683 | OPC_CheckField, 13, 1, 0, // 14893: check Inst[13] == 0x0 |
| 6684 | OPC_Decode, 168, 15, 251, 1, // 14897: decode to M2_mpyud_acc_lh_s0 using decoder 251 |
| 6685 | // 14897: } |
| 6686 | 2, 9, // 14902: case 0x2: { |
| 6687 | OPC_CheckField, 13, 1, 0, // 14904: check Inst[13] == 0x0 |
| 6688 | OPC_Decode, 166, 15, 251, 1, // 14908: decode to M2_mpyud_acc_hl_s0 using decoder 251 |
| 6689 | // 14908: } |
| 6690 | 3, 0, // 14913: case 0x3: { |
| 6691 | OPC_CheckField, 13, 1, 0, // 14915: check Inst[13] == 0x0 |
| 6692 | OPC_Decode, 164, 15, 251, 1, // 14919: decode to M2_mpyud_acc_hh_s0 using decoder 251 |
| 6693 | // 14919: } |
| 6694 | // 14919: } // switch Inst[7:5] |
| 6695 | // 14919: } |
| 6696 | 51, 47, // 14924: case 0x33: { |
| 6697 | OPC_SwitchField, 5, 3, // 14926: switch Inst[7:5] { |
| 6698 | 0, 9, // 14929: case 0x0: { |
| 6699 | OPC_CheckField, 13, 1, 0, // 14931: check Inst[13] == 0x0 |
| 6700 | OPC_Decode, 186, 15, 251, 1, // 14935: decode to M2_mpyud_nac_ll_s0 using decoder 251 |
| 6701 | // 14935: } |
| 6702 | 1, 9, // 14940: case 0x1: { |
| 6703 | OPC_CheckField, 13, 1, 0, // 14942: check Inst[13] == 0x0 |
| 6704 | OPC_Decode, 184, 15, 251, 1, // 14946: decode to M2_mpyud_nac_lh_s0 using decoder 251 |
| 6705 | // 14946: } |
| 6706 | 2, 9, // 14951: case 0x2: { |
| 6707 | OPC_CheckField, 13, 1, 0, // 14953: check Inst[13] == 0x0 |
| 6708 | OPC_Decode, 182, 15, 251, 1, // 14957: decode to M2_mpyud_nac_hl_s0 using decoder 251 |
| 6709 | // 14957: } |
| 6710 | 3, 0, // 14962: case 0x3: { |
| 6711 | OPC_CheckField, 13, 1, 0, // 14964: check Inst[13] == 0x0 |
| 6712 | OPC_Decode, 180, 15, 251, 1, // 14968: decode to M2_mpyud_nac_hh_s0 using decoder 251 |
| 6713 | // 14968: } |
| 6714 | // 14968: } // switch Inst[7:5] |
| 6715 | // 14968: } |
| 6716 | 52, 47, // 14973: case 0x34: { |
| 6717 | OPC_SwitchField, 5, 3, // 14975: switch Inst[7:5] { |
| 6718 | 0, 9, // 14978: case 0x0: { |
| 6719 | OPC_CheckField, 13, 1, 0, // 14980: check Inst[13] == 0x0 |
| 6720 | OPC_Decode, 238, 14, 251, 1, // 14984: decode to M2_mpyd_acc_ll_s1 using decoder 251 |
| 6721 | // 14984: } |
| 6722 | 1, 9, // 14989: case 0x1: { |
| 6723 | OPC_CheckField, 13, 1, 0, // 14991: check Inst[13] == 0x0 |
| 6724 | OPC_Decode, 236, 14, 251, 1, // 14995: decode to M2_mpyd_acc_lh_s1 using decoder 251 |
| 6725 | // 14995: } |
| 6726 | 2, 9, // 15000: case 0x2: { |
| 6727 | OPC_CheckField, 13, 1, 0, // 15002: check Inst[13] == 0x0 |
| 6728 | OPC_Decode, 234, 14, 251, 1, // 15006: decode to M2_mpyd_acc_hl_s1 using decoder 251 |
| 6729 | // 15006: } |
| 6730 | 3, 0, // 15011: case 0x3: { |
| 6731 | OPC_CheckField, 13, 1, 0, // 15013: check Inst[13] == 0x0 |
| 6732 | OPC_Decode, 232, 14, 251, 1, // 15017: decode to M2_mpyd_acc_hh_s1 using decoder 251 |
| 6733 | // 15017: } |
| 6734 | // 15017: } // switch Inst[7:5] |
| 6735 | // 15017: } |
| 6736 | 53, 47, // 15022: case 0x35: { |
| 6737 | OPC_SwitchField, 5, 3, // 15024: switch Inst[7:5] { |
| 6738 | 0, 9, // 15027: case 0x0: { |
| 6739 | OPC_CheckField, 13, 1, 0, // 15029: check Inst[13] == 0x0 |
| 6740 | OPC_Decode, 254, 14, 251, 1, // 15033: decode to M2_mpyd_nac_ll_s1 using decoder 251 |
| 6741 | // 15033: } |
| 6742 | 1, 9, // 15038: case 0x1: { |
| 6743 | OPC_CheckField, 13, 1, 0, // 15040: check Inst[13] == 0x0 |
| 6744 | OPC_Decode, 252, 14, 251, 1, // 15044: decode to M2_mpyd_nac_lh_s1 using decoder 251 |
| 6745 | // 15044: } |
| 6746 | 2, 9, // 15049: case 0x2: { |
| 6747 | OPC_CheckField, 13, 1, 0, // 15051: check Inst[13] == 0x0 |
| 6748 | OPC_Decode, 250, 14, 251, 1, // 15055: decode to M2_mpyd_nac_hl_s1 using decoder 251 |
| 6749 | // 15055: } |
| 6750 | 3, 0, // 15060: case 0x3: { |
| 6751 | OPC_CheckField, 13, 1, 0, // 15062: check Inst[13] == 0x0 |
| 6752 | OPC_Decode, 248, 14, 251, 1, // 15066: decode to M2_mpyd_nac_hh_s1 using decoder 251 |
| 6753 | // 15066: } |
| 6754 | // 15066: } // switch Inst[7:5] |
| 6755 | // 15066: } |
| 6756 | 54, 47, // 15071: case 0x36: { |
| 6757 | OPC_SwitchField, 5, 3, // 15073: switch Inst[7:5] { |
| 6758 | 0, 9, // 15076: case 0x0: { |
| 6759 | OPC_CheckField, 13, 1, 0, // 15078: check Inst[13] == 0x0 |
| 6760 | OPC_Decode, 171, 15, 251, 1, // 15082: decode to M2_mpyud_acc_ll_s1 using decoder 251 |
| 6761 | // 15082: } |
| 6762 | 1, 9, // 15087: case 0x1: { |
| 6763 | OPC_CheckField, 13, 1, 0, // 15089: check Inst[13] == 0x0 |
| 6764 | OPC_Decode, 169, 15, 251, 1, // 15093: decode to M2_mpyud_acc_lh_s1 using decoder 251 |
| 6765 | // 15093: } |
| 6766 | 2, 9, // 15098: case 0x2: { |
| 6767 | OPC_CheckField, 13, 1, 0, // 15100: check Inst[13] == 0x0 |
| 6768 | OPC_Decode, 167, 15, 251, 1, // 15104: decode to M2_mpyud_acc_hl_s1 using decoder 251 |
| 6769 | // 15104: } |
| 6770 | 3, 0, // 15109: case 0x3: { |
| 6771 | OPC_CheckField, 13, 1, 0, // 15111: check Inst[13] == 0x0 |
| 6772 | OPC_Decode, 165, 15, 251, 1, // 15115: decode to M2_mpyud_acc_hh_s1 using decoder 251 |
| 6773 | // 15115: } |
| 6774 | // 15115: } // switch Inst[7:5] |
| 6775 | // 15115: } |
| 6776 | 55, 47, // 15120: case 0x37: { |
| 6777 | OPC_SwitchField, 5, 3, // 15122: switch Inst[7:5] { |
| 6778 | 0, 9, // 15125: case 0x0: { |
| 6779 | OPC_CheckField, 13, 1, 0, // 15127: check Inst[13] == 0x0 |
| 6780 | OPC_Decode, 187, 15, 251, 1, // 15131: decode to M2_mpyud_nac_ll_s1 using decoder 251 |
| 6781 | // 15131: } |
| 6782 | 1, 9, // 15136: case 0x1: { |
| 6783 | OPC_CheckField, 13, 1, 0, // 15138: check Inst[13] == 0x0 |
| 6784 | OPC_Decode, 185, 15, 251, 1, // 15142: decode to M2_mpyud_nac_lh_s1 using decoder 251 |
| 6785 | // 15142: } |
| 6786 | 2, 9, // 15147: case 0x2: { |
| 6787 | OPC_CheckField, 13, 1, 0, // 15149: check Inst[13] == 0x0 |
| 6788 | OPC_Decode, 183, 15, 251, 1, // 15153: decode to M2_mpyud_nac_hl_s1 using decoder 251 |
| 6789 | // 15153: } |
| 6790 | 3, 0, // 15158: case 0x3: { |
| 6791 | OPC_CheckField, 13, 1, 0, // 15160: check Inst[13] == 0x0 |
| 6792 | OPC_Decode, 181, 15, 251, 1, // 15164: decode to M2_mpyud_nac_hh_s1 using decoder 251 |
| 6793 | // 15164: } |
| 6794 | // 15164: } // switch Inst[7:5] |
| 6795 | // 15164: } |
| 6796 | 56, 69, // 15169: case 0x38: { |
| 6797 | OPC_SwitchField, 5, 3, // 15171: switch Inst[7:5] { |
| 6798 | 0, 9, // 15174: case 0x0: { |
| 6799 | OPC_CheckField, 13, 1, 0, // 15176: check Inst[13] == 0x0 |
| 6800 | OPC_Decode, 245, 13, 251, 1, // 15180: decode to M2_dpmpyss_acc_s0 using decoder 251 |
| 6801 | // 15180: } |
| 6802 | 1, 9, // 15185: case 0x1: { |
| 6803 | OPC_CheckField, 13, 1, 0, // 15187: check Inst[13] == 0x0 |
| 6804 | OPC_Decode, 225, 13, 251, 1, // 15191: decode to M2_cmaci_s0 using decoder 251 |
| 6805 | // 15191: } |
| 6806 | 2, 9, // 15196: case 0x2: { |
| 6807 | OPC_CheckField, 13, 1, 0, // 15198: check Inst[13] == 0x0 |
| 6808 | OPC_Decode, 226, 13, 251, 1, // 15202: decode to M2_cmacr_s0 using decoder 251 |
| 6809 | // 15202: } |
| 6810 | 5, 9, // 15207: case 0x5: { |
| 6811 | OPC_CheckField, 13, 1, 0, // 15209: check Inst[13] == 0x0 |
| 6812 | OPC_Decode, 209, 15, 251, 1, // 15213: decode to M2_vmac2s_s0 using decoder 251 |
| 6813 | // 15213: } |
| 6814 | 6, 9, // 15218: case 0x6: { |
| 6815 | OPC_CheckField, 13, 1, 0, // 15220: check Inst[13] == 0x0 |
| 6816 | OPC_Decode, 227, 13, 251, 1, // 15224: decode to M2_cmacs_s0 using decoder 251 |
| 6817 | // 15224: } |
| 6818 | 7, 0, // 15229: case 0x7: { |
| 6819 | OPC_CheckField, 13, 1, 0, // 15231: check Inst[13] == 0x0 |
| 6820 | OPC_Decode, 241, 13, 251, 1, // 15235: decode to M2_cnacs_s0 using decoder 251 |
| 6821 | // 15235: } |
| 6822 | // 15235: } // switch Inst[7:5] |
| 6823 | // 15235: } |
| 6824 | 57, 36, // 15240: case 0x39: { |
| 6825 | OPC_SwitchField, 5, 3, // 15242: switch Inst[7:5] { |
| 6826 | 0, 9, // 15245: case 0x0: { |
| 6827 | OPC_CheckField, 13, 1, 0, // 15247: check Inst[13] == 0x0 |
| 6828 | OPC_Decode, 246, 13, 251, 1, // 15251: decode to M2_dpmpyss_nac_s0 using decoder 251 |
| 6829 | // 15251: } |
| 6830 | 1, 9, // 15256: case 0x1: { |
| 6831 | OPC_CheckField, 13, 1, 0, // 15258: check Inst[13] == 0x0 |
| 6832 | OPC_Decode, 205, 15, 251, 1, // 15262: decode to M2_vmac2 using decoder 251 |
| 6833 | // 15262: } |
| 6834 | 7, 0, // 15267: case 0x7: { |
| 6835 | OPC_CheckField, 13, 1, 0, // 15269: check Inst[13] == 0x0 |
| 6836 | OPC_Decode, 132, 16, 251, 1, // 15273: decode to M4_pmpyw_acc using decoder 251 |
| 6837 | // 15273: } |
| 6838 | // 15273: } // switch Inst[7:5] |
| 6839 | // 15273: } |
| 6840 | 58, 36, // 15278: case 0x3a: { |
| 6841 | OPC_SwitchField, 5, 3, // 15280: switch Inst[7:5] { |
| 6842 | 0, 9, // 15283: case 0x0: { |
| 6843 | OPC_CheckField, 13, 1, 0, // 15285: check Inst[13] == 0x0 |
| 6844 | OPC_Decode, 249, 13, 251, 1, // 15289: decode to M2_dpmpyuu_acc_s0 using decoder 251 |
| 6845 | // 15289: } |
| 6846 | 6, 9, // 15294: case 0x6: { |
| 6847 | OPC_CheckField, 13, 1, 0, // 15296: check Inst[13] == 0x0 |
| 6848 | OPC_Decode, 229, 13, 251, 1, // 15300: decode to M2_cmacsc_s0 using decoder 251 |
| 6849 | // 15300: } |
| 6850 | 7, 0, // 15305: case 0x7: { |
| 6851 | OPC_CheckField, 13, 1, 0, // 15307: check Inst[13] == 0x0 |
| 6852 | OPC_Decode, 243, 13, 251, 1, // 15311: decode to M2_cnacsc_s0 using decoder 251 |
| 6853 | // 15311: } |
| 6854 | // 15311: } // switch Inst[7:5] |
| 6855 | // 15311: } |
| 6856 | 59, 25, // 15316: case 0x3b: { |
| 6857 | OPC_SwitchField, 5, 3, // 15318: switch Inst[7:5] { |
| 6858 | 0, 9, // 15321: case 0x0: { |
| 6859 | OPC_CheckField, 13, 1, 0, // 15323: check Inst[13] == 0x0 |
| 6860 | OPC_Decode, 250, 13, 251, 1, // 15327: decode to M2_dpmpyuu_nac_s0 using decoder 251 |
| 6861 | // 15327: } |
| 6862 | 5, 0, // 15332: case 0x5: { |
| 6863 | OPC_CheckField, 13, 1, 0, // 15334: check Inst[13] == 0x0 |
| 6864 | OPC_Decode, 211, 15, 251, 1, // 15338: decode to M2_vmac2su_s0 using decoder 251 |
| 6865 | // 15338: } |
| 6866 | // 15338: } // switch Inst[7:5] |
| 6867 | // 15338: } |
| 6868 | 60, 47, // 15343: case 0x3c: { |
| 6869 | OPC_SwitchField, 5, 3, // 15345: switch Inst[7:5] { |
| 6870 | 1, 9, // 15348: case 0x1: { |
| 6871 | OPC_CheckField, 13, 1, 0, // 15350: check Inst[13] == 0x0 |
| 6872 | OPC_Decode, 150, 16, 251, 1, // 15354: decode to M5_vmacbuu using decoder 251 |
| 6873 | // 15354: } |
| 6874 | 5, 9, // 15359: case 0x5: { |
| 6875 | OPC_CheckField, 13, 1, 0, // 15361: check Inst[13] == 0x0 |
| 6876 | OPC_Decode, 210, 15, 251, 1, // 15365: decode to M2_vmac2s_s1 using decoder 251 |
| 6877 | // 15365: } |
| 6878 | 6, 9, // 15370: case 0x6: { |
| 6879 | OPC_CheckField, 13, 1, 0, // 15372: check Inst[13] == 0x0 |
| 6880 | OPC_Decode, 228, 13, 251, 1, // 15376: decode to M2_cmacs_s1 using decoder 251 |
| 6881 | // 15376: } |
| 6882 | 7, 0, // 15381: case 0x7: { |
| 6883 | OPC_CheckField, 13, 1, 0, // 15383: check Inst[13] == 0x0 |
| 6884 | OPC_Decode, 242, 13, 251, 1, // 15387: decode to M2_cnacs_s1 using decoder 251 |
| 6885 | // 15387: } |
| 6886 | // 15387: } // switch Inst[7:5] |
| 6887 | // 15387: } |
| 6888 | 61, 13, // 15392: case 0x3d: { |
| 6889 | OPC_CheckField, 13, 1, 0, // 15394: check Inst[13] == 0x0 |
| 6890 | OPC_CheckField, 5, 3, 7, // 15398: check Inst[7:5] == 0x7 |
| 6891 | OPC_Decode, 134, 16, 251, 1, // 15402: decode to M4_vpmpyh_acc using decoder 251 |
| 6892 | // 15402: } |
| 6893 | 62, 36, // 15407: case 0x3e: { |
| 6894 | OPC_SwitchField, 5, 3, // 15409: switch Inst[7:5] { |
| 6895 | 1, 9, // 15412: case 0x1: { |
| 6896 | OPC_CheckField, 13, 1, 0, // 15414: check Inst[13] == 0x0 |
| 6897 | OPC_Decode, 149, 16, 251, 1, // 15418: decode to M5_vmacbsu using decoder 251 |
| 6898 | // 15418: } |
| 6899 | 6, 9, // 15423: case 0x6: { |
| 6900 | OPC_CheckField, 13, 1, 0, // 15425: check Inst[13] == 0x0 |
| 6901 | OPC_Decode, 230, 13, 251, 1, // 15429: decode to M2_cmacsc_s1 using decoder 251 |
| 6902 | // 15429: } |
| 6903 | 7, 0, // 15434: case 0x7: { |
| 6904 | OPC_CheckField, 13, 1, 0, // 15436: check Inst[13] == 0x0 |
| 6905 | OPC_Decode, 244, 13, 251, 1, // 15440: decode to M2_cnacsc_s1 using decoder 251 |
| 6906 | // 15440: } |
| 6907 | // 15440: } // switch Inst[7:5] |
| 6908 | // 15440: } |
| 6909 | 63, 13, // 15445: case 0x3f: { |
| 6910 | OPC_CheckField, 13, 1, 0, // 15447: check Inst[13] == 0x0 |
| 6911 | OPC_CheckField, 5, 3, 5, // 15451: check Inst[7:5] == 0x5 |
| 6912 | OPC_Decode, 212, 15, 251, 1, // 15455: decode to M2_vmac2su_s1 using decoder 251 |
| 6913 | // 15455: } |
| 6914 | 64, 93, // 15460: case 0x40: { |
| 6915 | OPC_SwitchField, 5, 3, // 15462: switch Inst[7:5] { |
| 6916 | 0, 9, // 15465: case 0x0: { |
| 6917 | OPC_CheckField, 13, 1, 0, // 15467: check Inst[13] == 0x0 |
| 6918 | OPC_Decode, 227, 15, 206, 1, // 15471: decode to M2_vrcmpyi_s0 using decoder 206 |
| 6919 | // 15471: } |
| 6920 | 1, 9, // 15476: case 0x1: { |
| 6921 | OPC_CheckField, 13, 1, 0, // 15478: check Inst[13] == 0x0 |
| 6922 | OPC_Decode, 229, 15, 206, 1, // 15482: decode to M2_vrcmpyr_s0 using decoder 206 |
| 6923 | // 15482: } |
| 6924 | 2, 9, // 15487: case 0x2: { |
| 6925 | OPC_CheckField, 13, 1, 0, // 15489: check Inst[13] == 0x0 |
| 6926 | OPC_Decode, 238, 15, 206, 1, // 15493: decode to M2_vrmpy_s0 using decoder 206 |
| 6927 | // 15493: } |
| 6928 | 3, 11, // 15498: case 0x3: { |
| 6929 | OPC_CheckPredicate, 4, // 15500: check predicate 4 |
| 6930 | OPC_CheckField, 13, 1, 0, // 15502: check Inst[13] == 0x0 |
| 6931 | OPC_Decode, 150, 10, 206, 1, // 15506: decode to F2_dfadd using decoder 206 |
| 6932 | // 15506: } |
| 6933 | 4, 9, // 15511: case 0x4: { |
| 6934 | OPC_CheckField, 13, 1, 0, // 15513: check Inst[13] == 0x0 |
| 6935 | OPC_Decode, 203, 15, 206, 1, // 15517: decode to M2_vdmpys_s0 using decoder 206 |
| 6936 | // 15517: } |
| 6937 | 5, 9, // 15522: case 0x5: { |
| 6938 | OPC_CheckField, 13, 1, 0, // 15524: check Inst[13] == 0x0 |
| 6939 | OPC_Decode, 153, 14, 206, 1, // 15528: decode to M2_mmpyl_s0 using decoder 206 |
| 6940 | // 15528: } |
| 6941 | 6, 9, // 15533: case 0x6: { |
| 6942 | OPC_CheckField, 13, 1, 0, // 15535: check Inst[13] == 0x0 |
| 6943 | OPC_Decode, 213, 15, 206, 1, // 15539: decode to M2_vmpy2es_s0 using decoder 206 |
| 6944 | // 15539: } |
| 6945 | 7, 0, // 15544: case 0x7: { |
| 6946 | OPC_CheckField, 13, 1, 0, // 15546: check Inst[13] == 0x0 |
| 6947 | OPC_Decode, 149, 14, 206, 1, // 15550: decode to M2_mmpyh_s0 using decoder 206 |
| 6948 | // 15550: } |
| 6949 | // 15550: } // switch Inst[7:5] |
| 6950 | // 15550: } |
| 6951 | 65, 71, // 15555: case 0x41: { |
| 6952 | OPC_SwitchField, 5, 3, // 15557: switch Inst[7:5] { |
| 6953 | 0, 9, // 15560: case 0x0: { |
| 6954 | OPC_CheckField, 13, 1, 0, // 15562: check Inst[13] == 0x0 |
| 6955 | OPC_Decode, 192, 15, 207, 1, // 15566: decode to M2_vabsdiffw using decoder 207 |
| 6956 | // 15566: } |
| 6957 | 2, 9, // 15571: case 0x2: { |
| 6958 | OPC_CheckField, 13, 1, 0, // 15573: check Inst[13] == 0x0 |
| 6959 | OPC_Decode, 141, 16, 206, 1, // 15577: decode to M4_vrmpyoh_s0 using decoder 206 |
| 6960 | // 15577: } |
| 6961 | 3, 11, // 15582: case 0x3: { |
| 6962 | OPC_CheckPredicate, 5, // 15584: check predicate 5 |
| 6963 | OPC_CheckField, 13, 1, 0, // 15586: check Inst[13] == 0x0 |
| 6964 | OPC_Decode, 158, 10, 206, 1, // 15590: decode to F2_dfmax using decoder 206 |
| 6965 | // 15590: } |
| 6966 | 5, 9, // 15595: case 0x5: { |
| 6967 | OPC_CheckField, 13, 1, 0, // 15597: check Inst[13] == 0x0 |
| 6968 | OPC_Decode, 151, 14, 206, 1, // 15601: decode to M2_mmpyl_rs0 using decoder 206 |
| 6969 | // 15601: } |
| 6970 | 6, 9, // 15606: case 0x6: { |
| 6971 | OPC_CheckField, 13, 1, 0, // 15608: check Inst[13] == 0x0 |
| 6972 | OPC_Decode, 196, 15, 206, 1, // 15612: decode to M2_vcmpy_s0_sat_r using decoder 206 |
| 6973 | // 15612: } |
| 6974 | 7, 0, // 15617: case 0x7: { |
| 6975 | OPC_CheckField, 13, 1, 0, // 15619: check Inst[13] == 0x0 |
| 6976 | OPC_Decode, 147, 14, 206, 1, // 15623: decode to M2_mmpyh_rs0 using decoder 206 |
| 6977 | // 15623: } |
| 6978 | // 15623: } // switch Inst[7:5] |
| 6979 | // 15623: } |
| 6980 | 66, 93, // 15628: case 0x42: { |
| 6981 | OPC_SwitchField, 5, 3, // 15630: switch Inst[7:5] { |
| 6982 | 0, 9, // 15633: case 0x0: { |
| 6983 | OPC_CheckField, 13, 1, 0, // 15635: check Inst[13] == 0x0 |
| 6984 | OPC_Decode, 228, 15, 206, 1, // 15639: decode to M2_vrcmpyi_s0c using decoder 206 |
| 6985 | // 15639: } |
| 6986 | 1, 9, // 15644: case 0x1: { |
| 6987 | OPC_CheckField, 13, 1, 0, // 15646: check Inst[13] == 0x0 |
| 6988 | OPC_Decode, 198, 8, 206, 1, // 15650: decode to A2_vraddub using decoder 206 |
| 6989 | // 15650: } |
| 6990 | 2, 9, // 15655: case 0x2: { |
| 6991 | OPC_CheckField, 13, 1, 0, // 15657: check Inst[13] == 0x0 |
| 6992 | OPC_Decode, 200, 8, 206, 1, // 15661: decode to A2_vrsadub using decoder 206 |
| 6993 | // 15661: } |
| 6994 | 3, 11, // 15666: case 0x3: { |
| 6995 | OPC_CheckPredicate, 5, // 15668: check predicate 5 |
| 6996 | OPC_CheckField, 13, 1, 0, // 15670: check Inst[13] == 0x0 |
| 6997 | OPC_Decode, 160, 10, 206, 1, // 15674: decode to F2_dfmpyfix using decoder 206 |
| 6998 | // 15674: } |
| 6999 | 4, 9, // 15679: case 0x4: { |
| 7000 | OPC_CheckField, 13, 1, 0, // 15681: check Inst[13] == 0x0 |
| 7001 | OPC_Decode, 137, 16, 206, 1, // 15685: decode to M4_vrmpyeh_s0 using decoder 206 |
| 7002 | // 15685: } |
| 7003 | 5, 9, // 15690: case 0x5: { |
| 7004 | OPC_CheckField, 13, 1, 0, // 15692: check Inst[13] == 0x0 |
| 7005 | OPC_Decode, 161, 14, 206, 1, // 15696: decode to M2_mmpyul_s0 using decoder 206 |
| 7006 | // 15696: } |
| 7007 | 6, 9, // 15701: case 0x6: { |
| 7008 | OPC_CheckField, 13, 1, 0, // 15703: check Inst[13] == 0x0 |
| 7009 | OPC_Decode, 195, 15, 206, 1, // 15707: decode to M2_vcmpy_s0_sat_i using decoder 206 |
| 7010 | // 15707: } |
| 7011 | 7, 0, // 15712: case 0x7: { |
| 7012 | OPC_CheckField, 13, 1, 0, // 15714: check Inst[13] == 0x0 |
| 7013 | OPC_Decode, 157, 14, 206, 1, // 15718: decode to M2_mmpyuh_s0 using decoder 206 |
| 7014 | // 15718: } |
| 7015 | // 15718: } // switch Inst[7:5] |
| 7016 | // 15718: } |
| 7017 | 67, 60, // 15723: case 0x43: { |
| 7018 | OPC_SwitchField, 5, 3, // 15725: switch Inst[7:5] { |
| 7019 | 0, 9, // 15728: case 0x0: { |
| 7020 | OPC_CheckField, 13, 1, 0, // 15730: check Inst[13] == 0x0 |
| 7021 | OPC_Decode, 191, 15, 207, 1, // 15734: decode to M2_vabsdiffh using decoder 207 |
| 7022 | // 15734: } |
| 7023 | 1, 9, // 15739: case 0x1: { |
| 7024 | OPC_CheckField, 13, 1, 0, // 15741: check Inst[13] == 0x0 |
| 7025 | OPC_Decode, 230, 15, 206, 1, // 15745: decode to M2_vrcmpyr_s0c using decoder 206 |
| 7026 | // 15745: } |
| 7027 | 2, 11, // 15750: case 0x2: { |
| 7028 | OPC_CheckPredicate, 8, // 15752: check predicate 8 |
| 7029 | OPC_CheckField, 13, 1, 0, // 15754: check Inst[13] == 0x0 |
| 7030 | OPC_Decode, 159, 16, 206, 1, // 15758: decode to M7_dcmpyiw using decoder 206 |
| 7031 | // 15758: } |
| 7032 | 5, 9, // 15763: case 0x5: { |
| 7033 | OPC_CheckField, 13, 1, 0, // 15765: check Inst[13] == 0x0 |
| 7034 | OPC_Decode, 159, 14, 206, 1, // 15769: decode to M2_mmpyul_rs0 using decoder 206 |
| 7035 | // 15769: } |
| 7036 | 7, 0, // 15774: case 0x7: { |
| 7037 | OPC_CheckField, 13, 1, 0, // 15776: check Inst[13] == 0x0 |
| 7038 | OPC_Decode, 155, 14, 206, 1, // 15780: decode to M2_mmpyuh_rs0 using decoder 206 |
| 7039 | // 15780: } |
| 7040 | // 15780: } // switch Inst[7:5] |
| 7041 | // 15780: } |
| 7042 | 68, 84, // 15785: case 0x44: { |
| 7043 | OPC_SwitchField, 5, 3, // 15787: switch Inst[7:5] { |
| 7044 | 1, 9, // 15790: case 0x1: { |
| 7045 | OPC_CheckField, 13, 1, 0, // 15792: check Inst[13] == 0x0 |
| 7046 | OPC_Decode, 156, 16, 206, 1, // 15796: decode to M5_vrmpybuu using decoder 206 |
| 7047 | // 15796: } |
| 7048 | 2, 11, // 15801: case 0x2: { |
| 7049 | OPC_CheckPredicate, 8, // 15803: check predicate 8 |
| 7050 | OPC_CheckField, 13, 1, 0, // 15805: check Inst[13] == 0x0 |
| 7051 | OPC_Decode, 163, 16, 206, 1, // 15809: decode to M7_dcmpyrw using decoder 206 |
| 7052 | // 15809: } |
| 7053 | 3, 11, // 15814: case 0x3: { |
| 7054 | OPC_CheckPredicate, 4, // 15816: check predicate 4 |
| 7055 | OPC_CheckField, 13, 1, 0, // 15818: check Inst[13] == 0x0 |
| 7056 | OPC_Decode, 164, 10, 206, 1, // 15822: decode to F2_dfsub using decoder 206 |
| 7057 | // 15822: } |
| 7058 | 4, 9, // 15827: case 0x4: { |
| 7059 | OPC_CheckField, 13, 1, 0, // 15829: check Inst[13] == 0x0 |
| 7060 | OPC_Decode, 204, 15, 206, 1, // 15833: decode to M2_vdmpys_s1 using decoder 206 |
| 7061 | // 15833: } |
| 7062 | 5, 9, // 15838: case 0x5: { |
| 7063 | OPC_CheckField, 13, 1, 0, // 15840: check Inst[13] == 0x0 |
| 7064 | OPC_Decode, 154, 14, 206, 1, // 15844: decode to M2_mmpyl_s1 using decoder 206 |
| 7065 | // 15844: } |
| 7066 | 6, 9, // 15849: case 0x6: { |
| 7067 | OPC_CheckField, 13, 1, 0, // 15851: check Inst[13] == 0x0 |
| 7068 | OPC_Decode, 214, 15, 206, 1, // 15855: decode to M2_vmpy2es_s1 using decoder 206 |
| 7069 | // 15855: } |
| 7070 | 7, 0, // 15860: case 0x7: { |
| 7071 | OPC_CheckField, 13, 1, 0, // 15862: check Inst[13] == 0x0 |
| 7072 | OPC_Decode, 150, 14, 206, 1, // 15866: decode to M2_mmpyh_s1 using decoder 206 |
| 7073 | // 15866: } |
| 7074 | // 15866: } // switch Inst[7:5] |
| 7075 | // 15866: } |
| 7076 | 69, 95, // 15871: case 0x45: { |
| 7077 | OPC_SwitchField, 5, 3, // 15873: switch Inst[7:5] { |
| 7078 | 0, 11, // 15876: case 0x0: { |
| 7079 | OPC_CheckPredicate, 7, // 15878: check predicate 7 |
| 7080 | OPC_CheckField, 13, 1, 0, // 15880: check Inst[13] == 0x0 |
| 7081 | OPC_Decode, 158, 16, 207, 1, // 15884: decode to M6_vabsdiffub using decoder 207 |
| 7082 | // 15884: } |
| 7083 | 1, 9, // 15889: case 0x1: { |
| 7084 | OPC_CheckField, 13, 1, 0, // 15891: check Inst[13] == 0x0 |
| 7085 | OPC_Decode, 148, 16, 206, 1, // 15895: decode to M5_vdmpybsu using decoder 206 |
| 7086 | // 15895: } |
| 7087 | 2, 9, // 15900: case 0x2: { |
| 7088 | OPC_CheckField, 13, 1, 0, // 15902: check Inst[13] == 0x0 |
| 7089 | OPC_Decode, 142, 16, 206, 1, // 15906: decode to M4_vrmpyoh_s1 using decoder 206 |
| 7090 | // 15906: } |
| 7091 | 3, 11, // 15911: case 0x3: { |
| 7092 | OPC_CheckPredicate, 5, // 15913: check predicate 5 |
| 7093 | OPC_CheckField, 13, 1, 0, // 15915: check Inst[13] == 0x0 |
| 7094 | OPC_Decode, 163, 10, 206, 1, // 15919: decode to F2_dfmpyll using decoder 206 |
| 7095 | // 15919: } |
| 7096 | 4, 9, // 15924: case 0x4: { |
| 7097 | OPC_CheckField, 13, 1, 0, // 15926: check Inst[13] == 0x0 |
| 7098 | OPC_Decode, 233, 15, 206, 1, // 15930: decode to M2_vrcmpys_s1_h using decoder 206 |
| 7099 | // 15930: } |
| 7100 | 5, 9, // 15935: case 0x5: { |
| 7101 | OPC_CheckField, 13, 1, 0, // 15937: check Inst[13] == 0x0 |
| 7102 | OPC_Decode, 152, 14, 206, 1, // 15941: decode to M2_mmpyl_rs1 using decoder 206 |
| 7103 | // 15941: } |
| 7104 | 6, 9, // 15946: case 0x6: { |
| 7105 | OPC_CheckField, 13, 1, 0, // 15948: check Inst[13] == 0x0 |
| 7106 | OPC_Decode, 198, 15, 206, 1, // 15952: decode to M2_vcmpy_s1_sat_r using decoder 206 |
| 7107 | // 15952: } |
| 7108 | 7, 0, // 15957: case 0x7: { |
| 7109 | OPC_CheckField, 13, 1, 0, // 15959: check Inst[13] == 0x0 |
| 7110 | OPC_Decode, 148, 14, 206, 1, // 15963: decode to M2_mmpyh_rs1 using decoder 206 |
| 7111 | // 15963: } |
| 7112 | // 15963: } // switch Inst[7:5] |
| 7113 | // 15963: } |
| 7114 | 70, 84, // 15968: case 0x46: { |
| 7115 | OPC_SwitchField, 5, 3, // 15970: switch Inst[7:5] { |
| 7116 | 1, 9, // 15973: case 0x1: { |
| 7117 | OPC_CheckField, 13, 1, 0, // 15975: check Inst[13] == 0x0 |
| 7118 | OPC_Decode, 155, 16, 206, 1, // 15979: decode to M5_vrmpybsu using decoder 206 |
| 7119 | // 15979: } |
| 7120 | 2, 11, // 15984: case 0x2: { |
| 7121 | OPC_CheckPredicate, 8, // 15986: check predicate 8 |
| 7122 | OPC_CheckField, 13, 1, 0, // 15988: check Inst[13] == 0x0 |
| 7123 | OPC_Decode, 165, 16, 206, 1, // 15992: decode to M7_dcmpyrwc using decoder 206 |
| 7124 | // 15992: } |
| 7125 | 3, 11, // 15997: case 0x3: { |
| 7126 | OPC_CheckPredicate, 5, // 15999: check predicate 5 |
| 7127 | OPC_CheckField, 13, 1, 0, // 16001: check Inst[13] == 0x0 |
| 7128 | OPC_Decode, 159, 10, 206, 1, // 16005: decode to F2_dfmin using decoder 206 |
| 7129 | // 16005: } |
| 7130 | 4, 9, // 16010: case 0x4: { |
| 7131 | OPC_CheckField, 13, 1, 0, // 16012: check Inst[13] == 0x0 |
| 7132 | OPC_Decode, 138, 16, 206, 1, // 16016: decode to M4_vrmpyeh_s1 using decoder 206 |
| 7133 | // 16016: } |
| 7134 | 5, 9, // 16021: case 0x5: { |
| 7135 | OPC_CheckField, 13, 1, 0, // 16023: check Inst[13] == 0x0 |
| 7136 | OPC_Decode, 162, 14, 206, 1, // 16027: decode to M2_mmpyul_s1 using decoder 206 |
| 7137 | // 16027: } |
| 7138 | 6, 9, // 16032: case 0x6: { |
| 7139 | OPC_CheckField, 13, 1, 0, // 16034: check Inst[13] == 0x0 |
| 7140 | OPC_Decode, 197, 15, 206, 1, // 16038: decode to M2_vcmpy_s1_sat_i using decoder 206 |
| 7141 | // 16038: } |
| 7142 | 7, 0, // 16043: case 0x7: { |
| 7143 | OPC_CheckField, 13, 1, 0, // 16045: check Inst[13] == 0x0 |
| 7144 | OPC_Decode, 158, 14, 206, 1, // 16049: decode to M2_mmpyuh_s1 using decoder 206 |
| 7145 | // 16049: } |
| 7146 | // 16049: } // switch Inst[7:5] |
| 7147 | // 16049: } |
| 7148 | 71, 62, // 16054: case 0x47: { |
| 7149 | OPC_SwitchField, 5, 3, // 16056: switch Inst[7:5] { |
| 7150 | 0, 11, // 16059: case 0x0: { |
| 7151 | OPC_CheckPredicate, 7, // 16061: check predicate 7 |
| 7152 | OPC_CheckField, 13, 1, 0, // 16063: check Inst[13] == 0x0 |
| 7153 | OPC_Decode, 157, 16, 207, 1, // 16067: decode to M6_vabsdiffb using decoder 207 |
| 7154 | // 16067: } |
| 7155 | 2, 11, // 16072: case 0x2: { |
| 7156 | OPC_CheckPredicate, 8, // 16074: check predicate 8 |
| 7157 | OPC_CheckField, 13, 1, 0, // 16076: check Inst[13] == 0x0 |
| 7158 | OPC_Decode, 161, 16, 206, 1, // 16080: decode to M7_dcmpyiwc using decoder 206 |
| 7159 | // 16080: } |
| 7160 | 4, 9, // 16085: case 0x4: { |
| 7161 | OPC_CheckField, 13, 1, 0, // 16087: check Inst[13] == 0x0 |
| 7162 | OPC_Decode, 234, 15, 206, 1, // 16091: decode to M2_vrcmpys_s1_l using decoder 206 |
| 7163 | // 16091: } |
| 7164 | 5, 9, // 16096: case 0x5: { |
| 7165 | OPC_CheckField, 13, 1, 0, // 16098: check Inst[13] == 0x0 |
| 7166 | OPC_Decode, 160, 14, 206, 1, // 16102: decode to M2_mmpyul_rs1 using decoder 206 |
| 7167 | // 16102: } |
| 7168 | 7, 0, // 16107: case 0x7: { |
| 7169 | OPC_CheckField, 13, 1, 0, // 16109: check Inst[13] == 0x0 |
| 7170 | OPC_Decode, 156, 14, 206, 1, // 16113: decode to M2_mmpyuh_rs1 using decoder 206 |
| 7171 | // 16113: } |
| 7172 | // 16113: } // switch Inst[7:5] |
| 7173 | // 16113: } |
| 7174 | 72, 38, // 16118: case 0x48: { |
| 7175 | OPC_SwitchField, 5, 3, // 16120: switch Inst[7:5] { |
| 7176 | 0, 9, // 16123: case 0x0: { |
| 7177 | OPC_CheckField, 13, 1, 0, // 16125: check Inst[13] == 0x0 |
| 7178 | OPC_Decode, 201, 15, 208, 1, // 16129: decode to M2_vdmpyrs_s0 using decoder 208 |
| 7179 | // 16129: } |
| 7180 | 1, 9, // 16134: case 0x1: { |
| 7181 | OPC_CheckField, 13, 1, 0, // 16136: check Inst[13] == 0x0 |
| 7182 | OPC_Decode, 222, 15, 208, 1, // 16140: decode to M2_vradduh using decoder 208 |
| 7183 | // 16140: } |
| 7184 | 4, 0, // 16145: case 0x4: { |
| 7185 | OPC_CheckPredicate, 8, // 16147: check predicate 8 |
| 7186 | OPC_CheckField, 13, 1, 0, // 16149: check Inst[13] == 0x0 |
| 7187 | OPC_Decode, 169, 16, 208, 1, // 16153: decode to M7_wcmpyiwc using decoder 208 |
| 7188 | // 16153: } |
| 7189 | // 16153: } // switch Inst[7:5] |
| 7190 | // 16153: } |
| 7191 | 73, 27, // 16158: case 0x49: { |
| 7192 | OPC_SwitchField, 5, 3, // 16160: switch Inst[7:5] { |
| 7193 | 0, 11, // 16163: case 0x0: { |
| 7194 | OPC_CheckPredicate, 8, // 16165: check predicate 8 |
| 7195 | OPC_CheckField, 13, 1, 0, // 16167: check Inst[13] == 0x0 |
| 7196 | OPC_Decode, 167, 16, 208, 1, // 16171: decode to M7_wcmpyiw using decoder 208 |
| 7197 | // 16171: } |
| 7198 | 7, 0, // 16176: case 0x7: { |
| 7199 | OPC_CheckField, 13, 1, 0, // 16178: check Inst[13] == 0x0 |
| 7200 | OPC_Decode, 221, 15, 208, 1, // 16182: decode to M2_vraddh using decoder 208 |
| 7201 | // 16182: } |
| 7202 | // 16182: } // switch Inst[7:5] |
| 7203 | // 16182: } |
| 7204 | 74, 15, // 16187: case 0x4a: { |
| 7205 | OPC_CheckPredicate, 8, // 16189: check predicate 8 |
| 7206 | OPC_CheckField, 13, 1, 0, // 16191: check Inst[13] == 0x0 |
| 7207 | OPC_CheckField, 5, 3, 0, // 16195: check Inst[7:5] == 0x0 |
| 7208 | OPC_Decode, 171, 16, 208, 1, // 16199: decode to M7_wcmpyrw using decoder 208 |
| 7209 | // 16199: } |
| 7210 | 75, 15, // 16204: case 0x4b: { |
| 7211 | OPC_CheckPredicate, 8, // 16206: check predicate 8 |
| 7212 | OPC_CheckField, 13, 1, 0, // 16208: check Inst[13] == 0x0 |
| 7213 | OPC_CheckField, 5, 3, 0, // 16212: check Inst[7:5] == 0x0 |
| 7214 | OPC_Decode, 173, 16, 208, 1, // 16216: decode to M7_wcmpyrwc using decoder 208 |
| 7215 | // 16216: } |
| 7216 | 76, 27, // 16221: case 0x4c: { |
| 7217 | OPC_SwitchField, 5, 3, // 16223: switch Inst[7:5] { |
| 7218 | 0, 9, // 16226: case 0x0: { |
| 7219 | OPC_CheckField, 13, 1, 0, // 16228: check Inst[13] == 0x0 |
| 7220 | OPC_Decode, 202, 15, 208, 1, // 16232: decode to M2_vdmpyrs_s1 using decoder 208 |
| 7221 | // 16232: } |
| 7222 | 4, 0, // 16237: case 0x4: { |
| 7223 | OPC_CheckPredicate, 8, // 16239: check predicate 8 |
| 7224 | OPC_CheckField, 13, 1, 0, // 16241: check Inst[13] == 0x0 |
| 7225 | OPC_Decode, 170, 16, 208, 1, // 16245: decode to M7_wcmpyiwc_rnd using decoder 208 |
| 7226 | // 16245: } |
| 7227 | // 16245: } // switch Inst[7:5] |
| 7228 | // 16245: } |
| 7229 | 77, 38, // 16250: case 0x4d: { |
| 7230 | OPC_SwitchField, 5, 3, // 16252: switch Inst[7:5] { |
| 7231 | 0, 11, // 16255: case 0x0: { |
| 7232 | OPC_CheckPredicate, 8, // 16257: check predicate 8 |
| 7233 | OPC_CheckField, 13, 1, 0, // 16259: check Inst[13] == 0x0 |
| 7234 | OPC_Decode, 168, 16, 208, 1, // 16263: decode to M7_wcmpyiw_rnd using decoder 208 |
| 7235 | // 16263: } |
| 7236 | 6, 9, // 16268: case 0x6: { |
| 7237 | OPC_CheckField, 13, 1, 0, // 16270: check Inst[13] == 0x0 |
| 7238 | OPC_Decode, 235, 15, 208, 1, // 16274: decode to M2_vrcmpys_s1rp_h using decoder 208 |
| 7239 | // 16274: } |
| 7240 | 7, 0, // 16279: case 0x7: { |
| 7241 | OPC_CheckField, 13, 1, 0, // 16281: check Inst[13] == 0x0 |
| 7242 | OPC_Decode, 236, 15, 208, 1, // 16285: decode to M2_vrcmpys_s1rp_l using decoder 208 |
| 7243 | // 16285: } |
| 7244 | // 16285: } // switch Inst[7:5] |
| 7245 | // 16285: } |
| 7246 | 78, 15, // 16290: case 0x4e: { |
| 7247 | OPC_CheckPredicate, 8, // 16292: check predicate 8 |
| 7248 | OPC_CheckField, 13, 1, 0, // 16294: check Inst[13] == 0x0 |
| 7249 | OPC_CheckField, 5, 3, 0, // 16298: check Inst[7:5] == 0x0 |
| 7250 | OPC_Decode, 172, 16, 208, 1, // 16302: decode to M7_wcmpyrw_rnd using decoder 208 |
| 7251 | // 16302: } |
| 7252 | 79, 15, // 16307: case 0x4f: { |
| 7253 | OPC_CheckPredicate, 8, // 16309: check predicate 8 |
| 7254 | OPC_CheckField, 13, 1, 0, // 16311: check Inst[13] == 0x0 |
| 7255 | OPC_CheckField, 5, 3, 0, // 16315: check Inst[7:5] == 0x0 |
| 7256 | OPC_Decode, 174, 16, 208, 1, // 16319: decode to M7_wcmpyrwc_rnd using decoder 208 |
| 7257 | // 16319: } |
| 7258 | 80, 93, // 16324: case 0x50: { |
| 7259 | OPC_SwitchField, 5, 3, // 16326: switch Inst[7:5] { |
| 7260 | 0, 9, // 16329: case 0x0: { |
| 7261 | OPC_CheckField, 13, 1, 0, // 16331: check Inst[13] == 0x0 |
| 7262 | OPC_Decode, 223, 15, 218, 1, // 16335: decode to M2_vrcmaci_s0 using decoder 218 |
| 7263 | // 16335: } |
| 7264 | 1, 9, // 16340: case 0x1: { |
| 7265 | OPC_CheckField, 13, 1, 0, // 16342: check Inst[13] == 0x0 |
| 7266 | OPC_Decode, 225, 15, 218, 1, // 16346: decode to M2_vrcmacr_s0 using decoder 218 |
| 7267 | // 16346: } |
| 7268 | 2, 9, // 16351: case 0x2: { |
| 7269 | OPC_CheckField, 13, 1, 0, // 16353: check Inst[13] == 0x0 |
| 7270 | OPC_Decode, 237, 15, 218, 1, // 16357: decode to M2_vrmac_s0 using decoder 218 |
| 7271 | // 16357: } |
| 7272 | 3, 11, // 16362: case 0x3: { |
| 7273 | OPC_CheckPredicate, 5, // 16364: check predicate 5 |
| 7274 | OPC_CheckField, 13, 1, 0, // 16366: check Inst[13] == 0x0 |
| 7275 | OPC_Decode, 162, 10, 218, 1, // 16370: decode to F2_dfmpylh using decoder 218 |
| 7276 | // 16370: } |
| 7277 | 4, 9, // 16375: case 0x4: { |
| 7278 | OPC_CheckField, 13, 1, 0, // 16377: check Inst[13] == 0x0 |
| 7279 | OPC_Decode, 199, 15, 218, 1, // 16381: decode to M2_vdmacs_s0 using decoder 218 |
| 7280 | // 16381: } |
| 7281 | 5, 9, // 16386: case 0x5: { |
| 7282 | OPC_CheckField, 13, 1, 0, // 16388: check Inst[13] == 0x0 |
| 7283 | OPC_Decode, 137, 14, 218, 1, // 16392: decode to M2_mmacls_s0 using decoder 218 |
| 7284 | // 16392: } |
| 7285 | 6, 9, // 16397: case 0x6: { |
| 7286 | OPC_CheckField, 13, 1, 0, // 16399: check Inst[13] == 0x0 |
| 7287 | OPC_Decode, 207, 15, 218, 1, // 16403: decode to M2_vmac2es_s0 using decoder 218 |
| 7288 | // 16403: } |
| 7289 | 7, 0, // 16408: case 0x7: { |
| 7290 | OPC_CheckField, 13, 1, 0, // 16410: check Inst[13] == 0x0 |
| 7291 | OPC_Decode, 133, 14, 218, 1, // 16414: decode to M2_mmachs_s0 using decoder 218 |
| 7292 | // 16414: } |
| 7293 | // 16414: } // switch Inst[7:5] |
| 7294 | // 16414: } |
| 7295 | 81, 69, // 16419: case 0x51: { |
| 7296 | OPC_SwitchField, 5, 3, // 16421: switch Inst[7:5] { |
| 7297 | 1, 9, // 16424: case 0x1: { |
| 7298 | OPC_CheckField, 13, 1, 0, // 16426: check Inst[13] == 0x0 |
| 7299 | OPC_Decode, 147, 16, 218, 1, // 16430: decode to M5_vdmacbsu using decoder 218 |
| 7300 | // 16430: } |
| 7301 | 2, 9, // 16435: case 0x2: { |
| 7302 | OPC_CheckField, 13, 1, 0, // 16437: check Inst[13] == 0x0 |
| 7303 | OPC_Decode, 206, 15, 218, 1, // 16441: decode to M2_vmac2es using decoder 218 |
| 7304 | // 16441: } |
| 7305 | 4, 9, // 16446: case 0x4: { |
| 7306 | OPC_CheckField, 13, 1, 0, // 16448: check Inst[13] == 0x0 |
| 7307 | OPC_Decode, 194, 15, 218, 1, // 16452: decode to M2_vcmac_s0_sat_r using decoder 218 |
| 7308 | // 16452: } |
| 7309 | 5, 9, // 16457: case 0x5: { |
| 7310 | OPC_CheckField, 13, 1, 0, // 16459: check Inst[13] == 0x0 |
| 7311 | OPC_Decode, 135, 14, 218, 1, // 16463: decode to M2_mmacls_rs0 using decoder 218 |
| 7312 | // 16463: } |
| 7313 | 6, 9, // 16468: case 0x6: { |
| 7314 | OPC_CheckField, 13, 1, 0, // 16470: check Inst[13] == 0x0 |
| 7315 | OPC_Decode, 135, 16, 218, 1, // 16474: decode to M4_vrmpyeh_acc_s0 using decoder 218 |
| 7316 | // 16474: } |
| 7317 | 7, 0, // 16479: case 0x7: { |
| 7318 | OPC_CheckField, 13, 1, 0, // 16481: check Inst[13] == 0x0 |
| 7319 | OPC_Decode, 131, 14, 218, 1, // 16485: decode to M2_mmachs_rs0 using decoder 218 |
| 7320 | // 16485: } |
| 7321 | // 16485: } // switch Inst[7:5] |
| 7322 | // 16485: } |
| 7323 | 82, 82, // 16490: case 0x52: { |
| 7324 | OPC_SwitchField, 5, 3, // 16492: switch Inst[7:5] { |
| 7325 | 0, 9, // 16495: case 0x0: { |
| 7326 | OPC_CheckField, 13, 1, 0, // 16497: check Inst[13] == 0x0 |
| 7327 | OPC_Decode, 224, 15, 218, 1, // 16501: decode to M2_vrcmaci_s0c using decoder 218 |
| 7328 | // 16501: } |
| 7329 | 1, 9, // 16506: case 0x1: { |
| 7330 | OPC_CheckField, 13, 1, 0, // 16508: check Inst[13] == 0x0 |
| 7331 | OPC_Decode, 199, 8, 218, 1, // 16512: decode to A2_vraddub_acc using decoder 218 |
| 7332 | // 16512: } |
| 7333 | 2, 9, // 16517: case 0x2: { |
| 7334 | OPC_CheckField, 13, 1, 0, // 16519: check Inst[13] == 0x0 |
| 7335 | OPC_Decode, 201, 8, 218, 1, // 16523: decode to A2_vrsadub_acc using decoder 218 |
| 7336 | // 16523: } |
| 7337 | 4, 9, // 16528: case 0x4: { |
| 7338 | OPC_CheckField, 13, 1, 0, // 16530: check Inst[13] == 0x0 |
| 7339 | OPC_Decode, 193, 15, 218, 1, // 16534: decode to M2_vcmac_s0_sat_i using decoder 218 |
| 7340 | // 16534: } |
| 7341 | 5, 9, // 16539: case 0x5: { |
| 7342 | OPC_CheckField, 13, 1, 0, // 16541: check Inst[13] == 0x0 |
| 7343 | OPC_Decode, 145, 14, 218, 1, // 16545: decode to M2_mmaculs_s0 using decoder 218 |
| 7344 | // 16545: } |
| 7345 | 6, 11, // 16550: case 0x6: { |
| 7346 | OPC_CheckPredicate, 8, // 16552: check predicate 8 |
| 7347 | OPC_CheckField, 13, 1, 0, // 16554: check Inst[13] == 0x0 |
| 7348 | OPC_Decode, 162, 16, 218, 1, // 16558: decode to M7_dcmpyiwc_acc using decoder 218 |
| 7349 | // 16558: } |
| 7350 | 7, 0, // 16563: case 0x7: { |
| 7351 | OPC_CheckField, 13, 1, 0, // 16565: check Inst[13] == 0x0 |
| 7352 | OPC_Decode, 141, 14, 218, 1, // 16569: decode to M2_mmacuhs_s0 using decoder 218 |
| 7353 | // 16569: } |
| 7354 | // 16569: } // switch Inst[7:5] |
| 7355 | // 16569: } |
| 7356 | 83, 60, // 16574: case 0x53: { |
| 7357 | OPC_SwitchField, 5, 3, // 16576: switch Inst[7:5] { |
| 7358 | 1, 9, // 16579: case 0x1: { |
| 7359 | OPC_CheckField, 13, 1, 0, // 16581: check Inst[13] == 0x0 |
| 7360 | OPC_Decode, 226, 15, 218, 1, // 16585: decode to M2_vrcmacr_s0c using decoder 218 |
| 7361 | // 16585: } |
| 7362 | 2, 11, // 16590: case 0x2: { |
| 7363 | OPC_CheckPredicate, 8, // 16592: check predicate 8 |
| 7364 | OPC_CheckField, 13, 1, 0, // 16594: check Inst[13] == 0x0 |
| 7365 | OPC_Decode, 160, 16, 218, 1, // 16598: decode to M7_dcmpyiw_acc using decoder 218 |
| 7366 | // 16598: } |
| 7367 | 5, 9, // 16603: case 0x5: { |
| 7368 | OPC_CheckField, 13, 1, 0, // 16605: check Inst[13] == 0x0 |
| 7369 | OPC_Decode, 143, 14, 218, 1, // 16609: decode to M2_mmaculs_rs0 using decoder 218 |
| 7370 | // 16609: } |
| 7371 | 6, 9, // 16614: case 0x6: { |
| 7372 | OPC_CheckField, 13, 1, 0, // 16616: check Inst[13] == 0x0 |
| 7373 | OPC_Decode, 139, 16, 218, 1, // 16620: decode to M4_vrmpyoh_acc_s0 using decoder 218 |
| 7374 | // 16620: } |
| 7375 | 7, 0, // 16625: case 0x7: { |
| 7376 | OPC_CheckField, 13, 1, 0, // 16627: check Inst[13] == 0x0 |
| 7377 | OPC_Decode, 139, 14, 218, 1, // 16631: decode to M2_mmacuhs_rs0 using decoder 218 |
| 7378 | // 16631: } |
| 7379 | // 16631: } // switch Inst[7:5] |
| 7380 | // 16631: } |
| 7381 | 84, 84, // 16636: case 0x54: { |
| 7382 | OPC_SwitchField, 5, 3, // 16638: switch Inst[7:5] { |
| 7383 | 1, 9, // 16641: case 0x1: { |
| 7384 | OPC_CheckField, 13, 1, 0, // 16643: check Inst[13] == 0x0 |
| 7385 | OPC_Decode, 154, 16, 218, 1, // 16647: decode to M5_vrmacbuu using decoder 218 |
| 7386 | // 16647: } |
| 7387 | 2, 11, // 16652: case 0x2: { |
| 7388 | OPC_CheckPredicate, 8, // 16654: check predicate 8 |
| 7389 | OPC_CheckField, 13, 1, 0, // 16656: check Inst[13] == 0x0 |
| 7390 | OPC_Decode, 164, 16, 218, 1, // 16660: decode to M7_dcmpyrw_acc using decoder 218 |
| 7391 | // 16660: } |
| 7392 | 3, 11, // 16665: case 0x3: { |
| 7393 | OPC_CheckPredicate, 5, // 16667: check predicate 5 |
| 7394 | OPC_CheckField, 13, 1, 0, // 16669: check Inst[13] == 0x0 |
| 7395 | OPC_Decode, 161, 10, 218, 1, // 16673: decode to F2_dfmpyhh using decoder 218 |
| 7396 | // 16673: } |
| 7397 | 4, 9, // 16678: case 0x4: { |
| 7398 | OPC_CheckField, 13, 1, 0, // 16680: check Inst[13] == 0x0 |
| 7399 | OPC_Decode, 200, 15, 218, 1, // 16684: decode to M2_vdmacs_s1 using decoder 218 |
| 7400 | // 16684: } |
| 7401 | 5, 9, // 16689: case 0x5: { |
| 7402 | OPC_CheckField, 13, 1, 0, // 16691: check Inst[13] == 0x0 |
| 7403 | OPC_Decode, 138, 14, 218, 1, // 16695: decode to M2_mmacls_s1 using decoder 218 |
| 7404 | // 16695: } |
| 7405 | 6, 9, // 16700: case 0x6: { |
| 7406 | OPC_CheckField, 13, 1, 0, // 16702: check Inst[13] == 0x0 |
| 7407 | OPC_Decode, 208, 15, 218, 1, // 16706: decode to M2_vmac2es_s1 using decoder 218 |
| 7408 | // 16706: } |
| 7409 | 7, 0, // 16711: case 0x7: { |
| 7410 | OPC_CheckField, 13, 1, 0, // 16713: check Inst[13] == 0x0 |
| 7411 | OPC_Decode, 134, 14, 218, 1, // 16717: decode to M2_mmachs_s1 using decoder 218 |
| 7412 | // 16717: } |
| 7413 | // 16717: } // switch Inst[7:5] |
| 7414 | // 16717: } |
| 7415 | 85, 65, // 16722: case 0x55: { |
| 7416 | OPC_SwitchField, 7, 1, // 16724: switch Inst[7] { |
| 7417 | 0, 11, // 16727: case 0x0: { |
| 7418 | OPC_CheckPredicate, 11, // 16729: check predicate 11 |
| 7419 | OPC_CheckField, 13, 1, 0, // 16731: check Inst[13] == 0x0 |
| 7420 | OPC_Decode, 167, 9, 252, 1, // 16735: decode to A5_ACS using decoder 252 |
| 7421 | // 16735: } |
| 7422 | 1, 0, // 16740: case 0x1: { |
| 7423 | OPC_SwitchField, 5, 2, // 16742: switch Inst[6:5] { |
| 7424 | 0, 9, // 16745: case 0x0: { |
| 7425 | OPC_CheckField, 13, 1, 0, // 16747: check Inst[13] == 0x0 |
| 7426 | OPC_Decode, 231, 15, 218, 1, // 16751: decode to M2_vrcmpys_acc_s1_h using decoder 218 |
| 7427 | // 16751: } |
| 7428 | 1, 9, // 16756: case 0x1: { |
| 7429 | OPC_CheckField, 13, 1, 0, // 16758: check Inst[13] == 0x0 |
| 7430 | OPC_Decode, 136, 14, 218, 1, // 16762: decode to M2_mmacls_rs1 using decoder 218 |
| 7431 | // 16762: } |
| 7432 | 2, 9, // 16767: case 0x2: { |
| 7433 | OPC_CheckField, 13, 1, 0, // 16769: check Inst[13] == 0x0 |
| 7434 | OPC_Decode, 136, 16, 218, 1, // 16773: decode to M4_vrmpyeh_acc_s1 using decoder 218 |
| 7435 | // 16773: } |
| 7436 | 3, 0, // 16778: case 0x3: { |
| 7437 | OPC_CheckField, 13, 1, 0, // 16780: check Inst[13] == 0x0 |
| 7438 | OPC_Decode, 132, 14, 218, 1, // 16784: decode to M2_mmachs_rs1 using decoder 218 |
| 7439 | // 16784: } |
| 7440 | // 16784: } // switch Inst[6:5] |
| 7441 | // 16784: } |
| 7442 | // 16784: } // switch Inst[7] |
| 7443 | // 16784: } |
| 7444 | 86, 49, // 16789: case 0x56: { |
| 7445 | OPC_SwitchField, 5, 3, // 16791: switch Inst[7:5] { |
| 7446 | 1, 9, // 16794: case 0x1: { |
| 7447 | OPC_CheckField, 13, 1, 0, // 16796: check Inst[13] == 0x0 |
| 7448 | OPC_Decode, 153, 16, 218, 1, // 16800: decode to M5_vrmacbsu using decoder 218 |
| 7449 | // 16800: } |
| 7450 | 2, 11, // 16805: case 0x2: { |
| 7451 | OPC_CheckPredicate, 8, // 16807: check predicate 8 |
| 7452 | OPC_CheckField, 13, 1, 0, // 16809: check Inst[13] == 0x0 |
| 7453 | OPC_Decode, 166, 16, 218, 1, // 16813: decode to M7_dcmpyrwc_acc using decoder 218 |
| 7454 | // 16813: } |
| 7455 | 5, 9, // 16818: case 0x5: { |
| 7456 | OPC_CheckField, 13, 1, 0, // 16820: check Inst[13] == 0x0 |
| 7457 | OPC_Decode, 146, 14, 218, 1, // 16824: decode to M2_mmaculs_s1 using decoder 218 |
| 7458 | // 16824: } |
| 7459 | 7, 0, // 16829: case 0x7: { |
| 7460 | OPC_CheckField, 13, 1, 0, // 16831: check Inst[13] == 0x0 |
| 7461 | OPC_Decode, 142, 14, 218, 1, // 16835: decode to M2_mmacuhs_s1 using decoder 218 |
| 7462 | // 16835: } |
| 7463 | // 16835: } // switch Inst[7:5] |
| 7464 | // 16835: } |
| 7465 | 87, 65, // 16840: case 0x57: { |
| 7466 | OPC_SwitchField, 7, 1, // 16842: switch Inst[7] { |
| 7467 | 0, 11, // 16845: case 0x0: { |
| 7468 | OPC_CheckPredicate, 7, // 16847: check predicate 7 |
| 7469 | OPC_CheckField, 13, 1, 0, // 16849: check Inst[13] == 0x0 |
| 7470 | OPC_Decode, 170, 9, 253, 1, // 16853: decode to A6_vminub_RdP using decoder 253 |
| 7471 | // 16853: } |
| 7472 | 1, 0, // 16858: case 0x1: { |
| 7473 | OPC_SwitchField, 5, 2, // 16860: switch Inst[6:5] { |
| 7474 | 0, 9, // 16863: case 0x0: { |
| 7475 | OPC_CheckField, 13, 1, 0, // 16865: check Inst[13] == 0x0 |
| 7476 | OPC_Decode, 232, 15, 218, 1, // 16869: decode to M2_vrcmpys_acc_s1_l using decoder 218 |
| 7477 | // 16869: } |
| 7478 | 1, 9, // 16874: case 0x1: { |
| 7479 | OPC_CheckField, 13, 1, 0, // 16876: check Inst[13] == 0x0 |
| 7480 | OPC_Decode, 144, 14, 218, 1, // 16880: decode to M2_mmaculs_rs1 using decoder 218 |
| 7481 | // 16880: } |
| 7482 | 2, 9, // 16885: case 0x2: { |
| 7483 | OPC_CheckField, 13, 1, 0, // 16887: check Inst[13] == 0x0 |
| 7484 | OPC_Decode, 140, 16, 218, 1, // 16891: decode to M4_vrmpyoh_acc_s1 using decoder 218 |
| 7485 | // 16891: } |
| 7486 | 3, 0, // 16896: case 0x3: { |
| 7487 | OPC_CheckField, 13, 1, 0, // 16898: check Inst[13] == 0x0 |
| 7488 | OPC_Decode, 140, 14, 218, 1, // 16902: decode to M2_mmacuhs_rs1 using decoder 218 |
| 7489 | // 16902: } |
| 7490 | // 16902: } // switch Inst[6:5] |
| 7491 | // 16902: } |
| 7492 | // 16902: } // switch Inst[7] |
| 7493 | // 16902: } |
| 7494 | 88, 25, // 16907: case 0x58: { |
| 7495 | OPC_SwitchField, 5, 3, // 16909: switch Inst[7:5] { |
| 7496 | 0, 9, // 16912: case 0x0: { |
| 7497 | OPC_CheckField, 13, 1, 0, // 16914: check Inst[13] == 0x0 |
| 7498 | OPC_Decode, 165, 10, 134, 1, // 16918: decode to F2_sfadd using decoder 134 |
| 7499 | // 16918: } |
| 7500 | 1, 0, // 16923: case 0x1: { |
| 7501 | OPC_CheckField, 13, 1, 0, // 16925: check Inst[13] == 0x0 |
| 7502 | OPC_Decode, 186, 10, 134, 1, // 16929: decode to F2_sfsub using decoder 134 |
| 7503 | // 16929: } |
| 7504 | // 16929: } // switch Inst[7:5] |
| 7505 | // 16929: } |
| 7506 | 90, 13, // 16934: case 0x5a: { |
| 7507 | OPC_CheckField, 13, 1, 0, // 16936: check Inst[13] == 0x0 |
| 7508 | OPC_CheckField, 5, 3, 0, // 16940: check Inst[7:5] == 0x0 |
| 7509 | OPC_Decode, 184, 10, 134, 1, // 16944: decode to F2_sfmpy using decoder 134 |
| 7510 | // 16944: } |
| 7511 | 92, 25, // 16949: case 0x5c: { |
| 7512 | OPC_SwitchField, 5, 3, // 16951: switch Inst[7:5] { |
| 7513 | 0, 9, // 16954: case 0x0: { |
| 7514 | OPC_CheckField, 13, 1, 0, // 16956: check Inst[13] == 0x0 |
| 7515 | OPC_Decode, 182, 10, 134, 1, // 16960: decode to F2_sfmax using decoder 134 |
| 7516 | // 16960: } |
| 7517 | 1, 0, // 16965: case 0x1: { |
| 7518 | OPC_CheckField, 13, 1, 0, // 16967: check Inst[13] == 0x0 |
| 7519 | OPC_Decode, 183, 10, 134, 1, // 16971: decode to F2_sfmin using decoder 134 |
| 7520 | // 16971: } |
| 7521 | // 16971: } // switch Inst[7:5] |
| 7522 | // 16971: } |
| 7523 | 94, 25, // 16976: case 0x5e: { |
| 7524 | OPC_SwitchField, 5, 3, // 16978: switch Inst[7:5] { |
| 7525 | 0, 9, // 16981: case 0x0: { |
| 7526 | OPC_CheckField, 13, 1, 0, // 16983: check Inst[13] == 0x0 |
| 7527 | OPC_Decode, 172, 10, 134, 1, // 16987: decode to F2_sffixupn using decoder 134 |
| 7528 | // 16987: } |
| 7529 | 1, 0, // 16992: case 0x1: { |
| 7530 | OPC_CheckField, 13, 1, 0, // 16994: check Inst[13] == 0x0 |
| 7531 | OPC_Decode, 171, 10, 134, 1, // 16998: decode to F2_sffixupd using decoder 134 |
| 7532 | // 16998: } |
| 7533 | // 16998: } // switch Inst[7:5] |
| 7534 | // 16998: } |
| 7535 | 95, 13, // 17003: case 0x5f: { |
| 7536 | OPC_CheckField, 13, 1, 0, // 17005: check Inst[13] == 0x0 |
| 7537 | OPC_CheckField, 7, 1, 1, // 17009: check Inst[7] == 0x1 |
| 7538 | OPC_Decode, 185, 10, 254, 1, // 17013: decode to F2_sfrecipa using decoder 254 |
| 7539 | // 17013: } |
| 7540 | 96, 91, // 17018: case 0x60: { |
| 7541 | OPC_SwitchField, 5, 3, // 17020: switch Inst[7:5] { |
| 7542 | 0, 9, // 17023: case 0x0: { |
| 7543 | OPC_CheckField, 13, 1, 0, // 17025: check Inst[13] == 0x0 |
| 7544 | OPC_Decode, 186, 14, 134, 1, // 17029: decode to M2_mpy_ll_s0 using decoder 134 |
| 7545 | // 17029: } |
| 7546 | 1, 9, // 17034: case 0x1: { |
| 7547 | OPC_CheckField, 13, 1, 0, // 17036: check Inst[13] == 0x0 |
| 7548 | OPC_Decode, 184, 14, 134, 1, // 17040: decode to M2_mpy_lh_s0 using decoder 134 |
| 7549 | // 17040: } |
| 7550 | 2, 9, // 17045: case 0x2: { |
| 7551 | OPC_CheckField, 13, 1, 0, // 17047: check Inst[13] == 0x0 |
| 7552 | OPC_Decode, 182, 14, 134, 1, // 17051: decode to M2_mpy_hl_s0 using decoder 134 |
| 7553 | // 17051: } |
| 7554 | 3, 9, // 17056: case 0x3: { |
| 7555 | OPC_CheckField, 13, 1, 0, // 17058: check Inst[13] == 0x0 |
| 7556 | OPC_Decode, 180, 14, 134, 1, // 17062: decode to M2_mpy_hh_s0 using decoder 134 |
| 7557 | // 17062: } |
| 7558 | 4, 9, // 17067: case 0x4: { |
| 7559 | OPC_CheckField, 13, 1, 0, // 17069: check Inst[13] == 0x0 |
| 7560 | OPC_Decode, 218, 14, 134, 1, // 17073: decode to M2_mpy_sat_ll_s0 using decoder 134 |
| 7561 | // 17073: } |
| 7562 | 5, 9, // 17078: case 0x5: { |
| 7563 | OPC_CheckField, 13, 1, 0, // 17080: check Inst[13] == 0x0 |
| 7564 | OPC_Decode, 216, 14, 134, 1, // 17084: decode to M2_mpy_sat_lh_s0 using decoder 134 |
| 7565 | // 17084: } |
| 7566 | 6, 9, // 17089: case 0x6: { |
| 7567 | OPC_CheckField, 13, 1, 0, // 17091: check Inst[13] == 0x0 |
| 7568 | OPC_Decode, 214, 14, 134, 1, // 17095: decode to M2_mpy_sat_hl_s0 using decoder 134 |
| 7569 | // 17095: } |
| 7570 | 7, 0, // 17100: case 0x7: { |
| 7571 | OPC_CheckField, 13, 1, 0, // 17102: check Inst[13] == 0x0 |
| 7572 | OPC_Decode, 212, 14, 134, 1, // 17106: decode to M2_mpy_sat_hh_s0 using decoder 134 |
| 7573 | // 17106: } |
| 7574 | // 17106: } // switch Inst[7:5] |
| 7575 | // 17106: } |
| 7576 | 97, 91, // 17111: case 0x61: { |
| 7577 | OPC_SwitchField, 5, 3, // 17113: switch Inst[7:5] { |
| 7578 | 0, 9, // 17116: case 0x0: { |
| 7579 | OPC_CheckField, 13, 1, 0, // 17118: check Inst[13] == 0x0 |
| 7580 | OPC_Decode, 210, 14, 134, 1, // 17122: decode to M2_mpy_rnd_ll_s0 using decoder 134 |
| 7581 | // 17122: } |
| 7582 | 1, 9, // 17127: case 0x1: { |
| 7583 | OPC_CheckField, 13, 1, 0, // 17129: check Inst[13] == 0x0 |
| 7584 | OPC_Decode, 208, 14, 134, 1, // 17133: decode to M2_mpy_rnd_lh_s0 using decoder 134 |
| 7585 | // 17133: } |
| 7586 | 2, 9, // 17138: case 0x2: { |
| 7587 | OPC_CheckField, 13, 1, 0, // 17140: check Inst[13] == 0x0 |
| 7588 | OPC_Decode, 206, 14, 134, 1, // 17144: decode to M2_mpy_rnd_hl_s0 using decoder 134 |
| 7589 | // 17144: } |
| 7590 | 3, 9, // 17149: case 0x3: { |
| 7591 | OPC_CheckField, 13, 1, 0, // 17151: check Inst[13] == 0x0 |
| 7592 | OPC_Decode, 204, 14, 134, 1, // 17155: decode to M2_mpy_rnd_hh_s0 using decoder 134 |
| 7593 | // 17155: } |
| 7594 | 4, 9, // 17160: case 0x4: { |
| 7595 | OPC_CheckField, 13, 1, 0, // 17162: check Inst[13] == 0x0 |
| 7596 | OPC_Decode, 226, 14, 134, 1, // 17166: decode to M2_mpy_sat_rnd_ll_s0 using decoder 134 |
| 7597 | // 17166: } |
| 7598 | 5, 9, // 17171: case 0x5: { |
| 7599 | OPC_CheckField, 13, 1, 0, // 17173: check Inst[13] == 0x0 |
| 7600 | OPC_Decode, 224, 14, 134, 1, // 17177: decode to M2_mpy_sat_rnd_lh_s0 using decoder 134 |
| 7601 | // 17177: } |
| 7602 | 6, 9, // 17182: case 0x6: { |
| 7603 | OPC_CheckField, 13, 1, 0, // 17184: check Inst[13] == 0x0 |
| 7604 | OPC_Decode, 222, 14, 134, 1, // 17188: decode to M2_mpy_sat_rnd_hl_s0 using decoder 134 |
| 7605 | // 17188: } |
| 7606 | 7, 0, // 17193: case 0x7: { |
| 7607 | OPC_CheckField, 13, 1, 0, // 17195: check Inst[13] == 0x0 |
| 7608 | OPC_Decode, 220, 14, 134, 1, // 17199: decode to M2_mpy_sat_rnd_hh_s0 using decoder 134 |
| 7609 | // 17199: } |
| 7610 | // 17199: } // switch Inst[7:5] |
| 7611 | // 17199: } |
| 7612 | 98, 47, // 17204: case 0x62: { |
| 7613 | OPC_SwitchField, 5, 3, // 17206: switch Inst[7:5] { |
| 7614 | 0, 9, // 17209: case 0x0: { |
| 7615 | OPC_CheckField, 13, 1, 0, // 17211: check Inst[13] == 0x0 |
| 7616 | OPC_Decode, 153, 15, 134, 1, // 17215: decode to M2_mpyu_ll_s0 using decoder 134 |
| 7617 | // 17215: } |
| 7618 | 1, 9, // 17220: case 0x1: { |
| 7619 | OPC_CheckField, 13, 1, 0, // 17222: check Inst[13] == 0x0 |
| 7620 | OPC_Decode, 151, 15, 134, 1, // 17226: decode to M2_mpyu_lh_s0 using decoder 134 |
| 7621 | // 17226: } |
| 7622 | 2, 9, // 17231: case 0x2: { |
| 7623 | OPC_CheckField, 13, 1, 0, // 17233: check Inst[13] == 0x0 |
| 7624 | OPC_Decode, 149, 15, 134, 1, // 17237: decode to M2_mpyu_hl_s0 using decoder 134 |
| 7625 | // 17237: } |
| 7626 | 3, 0, // 17242: case 0x3: { |
| 7627 | OPC_CheckField, 13, 1, 0, // 17244: check Inst[13] == 0x0 |
| 7628 | OPC_Decode, 147, 15, 134, 1, // 17248: decode to M2_mpyu_hh_s0 using decoder 134 |
| 7629 | // 17248: } |
| 7630 | // 17248: } // switch Inst[7:5] |
| 7631 | // 17248: } |
| 7632 | 100, 91, // 17253: case 0x64: { |
| 7633 | OPC_SwitchField, 5, 3, // 17255: switch Inst[7:5] { |
| 7634 | 0, 9, // 17258: case 0x0: { |
| 7635 | OPC_CheckField, 13, 1, 0, // 17260: check Inst[13] == 0x0 |
| 7636 | OPC_Decode, 187, 14, 134, 1, // 17264: decode to M2_mpy_ll_s1 using decoder 134 |
| 7637 | // 17264: } |
| 7638 | 1, 9, // 17269: case 0x1: { |
| 7639 | OPC_CheckField, 13, 1, 0, // 17271: check Inst[13] == 0x0 |
| 7640 | OPC_Decode, 185, 14, 134, 1, // 17275: decode to M2_mpy_lh_s1 using decoder 134 |
| 7641 | // 17275: } |
| 7642 | 2, 9, // 17280: case 0x2: { |
| 7643 | OPC_CheckField, 13, 1, 0, // 17282: check Inst[13] == 0x0 |
| 7644 | OPC_Decode, 183, 14, 134, 1, // 17286: decode to M2_mpy_hl_s1 using decoder 134 |
| 7645 | // 17286: } |
| 7646 | 3, 9, // 17291: case 0x3: { |
| 7647 | OPC_CheckField, 13, 1, 0, // 17293: check Inst[13] == 0x0 |
| 7648 | OPC_Decode, 181, 14, 134, 1, // 17297: decode to M2_mpy_hh_s1 using decoder 134 |
| 7649 | // 17297: } |
| 7650 | 4, 9, // 17302: case 0x4: { |
| 7651 | OPC_CheckField, 13, 1, 0, // 17304: check Inst[13] == 0x0 |
| 7652 | OPC_Decode, 219, 14, 134, 1, // 17308: decode to M2_mpy_sat_ll_s1 using decoder 134 |
| 7653 | // 17308: } |
| 7654 | 5, 9, // 17313: case 0x5: { |
| 7655 | OPC_CheckField, 13, 1, 0, // 17315: check Inst[13] == 0x0 |
| 7656 | OPC_Decode, 217, 14, 134, 1, // 17319: decode to M2_mpy_sat_lh_s1 using decoder 134 |
| 7657 | // 17319: } |
| 7658 | 6, 9, // 17324: case 0x6: { |
| 7659 | OPC_CheckField, 13, 1, 0, // 17326: check Inst[13] == 0x0 |
| 7660 | OPC_Decode, 215, 14, 134, 1, // 17330: decode to M2_mpy_sat_hl_s1 using decoder 134 |
| 7661 | // 17330: } |
| 7662 | 7, 0, // 17335: case 0x7: { |
| 7663 | OPC_CheckField, 13, 1, 0, // 17337: check Inst[13] == 0x0 |
| 7664 | OPC_Decode, 213, 14, 134, 1, // 17341: decode to M2_mpy_sat_hh_s1 using decoder 134 |
| 7665 | // 17341: } |
| 7666 | // 17341: } // switch Inst[7:5] |
| 7667 | // 17341: } |
| 7668 | 101, 91, // 17346: case 0x65: { |
| 7669 | OPC_SwitchField, 5, 3, // 17348: switch Inst[7:5] { |
| 7670 | 0, 9, // 17351: case 0x0: { |
| 7671 | OPC_CheckField, 13, 1, 0, // 17353: check Inst[13] == 0x0 |
| 7672 | OPC_Decode, 211, 14, 134, 1, // 17357: decode to M2_mpy_rnd_ll_s1 using decoder 134 |
| 7673 | // 17357: } |
| 7674 | 1, 9, // 17362: case 0x1: { |
| 7675 | OPC_CheckField, 13, 1, 0, // 17364: check Inst[13] == 0x0 |
| 7676 | OPC_Decode, 209, 14, 134, 1, // 17368: decode to M2_mpy_rnd_lh_s1 using decoder 134 |
| 7677 | // 17368: } |
| 7678 | 2, 9, // 17373: case 0x2: { |
| 7679 | OPC_CheckField, 13, 1, 0, // 17375: check Inst[13] == 0x0 |
| 7680 | OPC_Decode, 207, 14, 134, 1, // 17379: decode to M2_mpy_rnd_hl_s1 using decoder 134 |
| 7681 | // 17379: } |
| 7682 | 3, 9, // 17384: case 0x3: { |
| 7683 | OPC_CheckField, 13, 1, 0, // 17386: check Inst[13] == 0x0 |
| 7684 | OPC_Decode, 205, 14, 134, 1, // 17390: decode to M2_mpy_rnd_hh_s1 using decoder 134 |
| 7685 | // 17390: } |
| 7686 | 4, 9, // 17395: case 0x4: { |
| 7687 | OPC_CheckField, 13, 1, 0, // 17397: check Inst[13] == 0x0 |
| 7688 | OPC_Decode, 227, 14, 134, 1, // 17401: decode to M2_mpy_sat_rnd_ll_s1 using decoder 134 |
| 7689 | // 17401: } |
| 7690 | 5, 9, // 17406: case 0x5: { |
| 7691 | OPC_CheckField, 13, 1, 0, // 17408: check Inst[13] == 0x0 |
| 7692 | OPC_Decode, 225, 14, 134, 1, // 17412: decode to M2_mpy_sat_rnd_lh_s1 using decoder 134 |
| 7693 | // 17412: } |
| 7694 | 6, 9, // 17417: case 0x6: { |
| 7695 | OPC_CheckField, 13, 1, 0, // 17419: check Inst[13] == 0x0 |
| 7696 | OPC_Decode, 223, 14, 134, 1, // 17423: decode to M2_mpy_sat_rnd_hl_s1 using decoder 134 |
| 7697 | // 17423: } |
| 7698 | 7, 0, // 17428: case 0x7: { |
| 7699 | OPC_CheckField, 13, 1, 0, // 17430: check Inst[13] == 0x0 |
| 7700 | OPC_Decode, 221, 14, 134, 1, // 17434: decode to M2_mpy_sat_rnd_hh_s1 using decoder 134 |
| 7701 | // 17434: } |
| 7702 | // 17434: } // switch Inst[7:5] |
| 7703 | // 17434: } |
| 7704 | 102, 47, // 17439: case 0x66: { |
| 7705 | OPC_SwitchField, 5, 3, // 17441: switch Inst[7:5] { |
| 7706 | 0, 9, // 17444: case 0x0: { |
| 7707 | OPC_CheckField, 13, 1, 0, // 17446: check Inst[13] == 0x0 |
| 7708 | OPC_Decode, 154, 15, 134, 1, // 17450: decode to M2_mpyu_ll_s1 using decoder 134 |
| 7709 | // 17450: } |
| 7710 | 1, 9, // 17455: case 0x1: { |
| 7711 | OPC_CheckField, 13, 1, 0, // 17457: check Inst[13] == 0x0 |
| 7712 | OPC_Decode, 152, 15, 134, 1, // 17461: decode to M2_mpyu_lh_s1 using decoder 134 |
| 7713 | // 17461: } |
| 7714 | 2, 9, // 17466: case 0x2: { |
| 7715 | OPC_CheckField, 13, 1, 0, // 17468: check Inst[13] == 0x0 |
| 7716 | OPC_Decode, 150, 15, 134, 1, // 17472: decode to M2_mpyu_hl_s1 using decoder 134 |
| 7717 | // 17472: } |
| 7718 | 3, 0, // 17477: case 0x3: { |
| 7719 | OPC_CheckField, 13, 1, 0, // 17479: check Inst[13] == 0x0 |
| 7720 | OPC_Decode, 148, 15, 134, 1, // 17483: decode to M2_mpyu_hh_s1 using decoder 134 |
| 7721 | // 17483: } |
| 7722 | // 17483: } // switch Inst[7:5] |
| 7723 | // 17483: } |
| 7724 | 104, 25, // 17488: case 0x68: { |
| 7725 | OPC_SwitchField, 5, 3, // 17490: switch Inst[7:5] { |
| 7726 | 0, 9, // 17493: case 0x0: { |
| 7727 | OPC_CheckField, 13, 1, 0, // 17495: check Inst[13] == 0x0 |
| 7728 | OPC_Decode, 135, 15, 134, 1, // 17499: decode to M2_mpyi using decoder 134 |
| 7729 | // 17499: } |
| 7730 | 1, 0, // 17504: case 0x1: { |
| 7731 | OPC_CheckField, 13, 1, 0, // 17506: check Inst[13] == 0x0 |
| 7732 | OPC_Decode, 228, 14, 134, 1, // 17510: decode to M2_mpy_up using decoder 134 |
| 7733 | // 17510: } |
| 7734 | // 17510: } // switch Inst[7:5] |
| 7735 | // 17510: } |
| 7736 | 105, 36, // 17515: case 0x69: { |
| 7737 | OPC_SwitchField, 5, 3, // 17517: switch Inst[7:5] { |
| 7738 | 1, 9, // 17520: case 0x1: { |
| 7739 | OPC_CheckField, 13, 1, 0, // 17522: check Inst[13] == 0x0 |
| 7740 | OPC_Decode, 247, 13, 134, 1, // 17526: decode to M2_dpmpyss_rnd_s0 using decoder 134 |
| 7741 | // 17526: } |
| 7742 | 6, 9, // 17531: case 0x6: { |
| 7743 | OPC_CheckField, 13, 1, 0, // 17533: check Inst[13] == 0x0 |
| 7744 | OPC_Decode, 233, 13, 134, 1, // 17537: decode to M2_cmpyrs_s0 using decoder 134 |
| 7745 | // 17537: } |
| 7746 | 7, 0, // 17542: case 0x7: { |
| 7747 | OPC_CheckField, 13, 1, 0, // 17544: check Inst[13] == 0x0 |
| 7748 | OPC_Decode, 216, 15, 134, 1, // 17548: decode to M2_vmpy2s_s0pack using decoder 134 |
| 7749 | // 17548: } |
| 7750 | // 17548: } // switch Inst[7:5] |
| 7751 | // 17548: } |
| 7752 | 106, 13, // 17553: case 0x6a: { |
| 7753 | OPC_CheckField, 13, 1, 0, // 17555: check Inst[13] == 0x0 |
| 7754 | OPC_CheckField, 5, 3, 1, // 17559: check Inst[7:5] == 0x1 |
| 7755 | OPC_Decode, 163, 15, 134, 1, // 17563: decode to M2_mpyu_up using decoder 134 |
| 7756 | // 17563: } |
| 7757 | 107, 25, // 17568: case 0x6b: { |
| 7758 | OPC_SwitchField, 5, 3, // 17570: switch Inst[7:5] { |
| 7759 | 1, 9, // 17573: case 0x1: { |
| 7760 | OPC_CheckField, 13, 1, 0, // 17575: check Inst[13] == 0x0 |
| 7761 | OPC_Decode, 138, 15, 134, 1, // 17579: decode to M2_mpysu_up using decoder 134 |
| 7762 | // 17579: } |
| 7763 | 6, 0, // 17584: case 0x6: { |
| 7764 | OPC_CheckField, 13, 1, 0, // 17586: check Inst[13] == 0x0 |
| 7765 | OPC_Decode, 235, 13, 134, 1, // 17590: decode to M2_cmpyrsc_s0 using decoder 134 |
| 7766 | // 17590: } |
| 7767 | // 17590: } // switch Inst[7:5] |
| 7768 | // 17590: } |
| 7769 | 109, 69, // 17595: case 0x6d: { |
| 7770 | OPC_SwitchField, 5, 3, // 17597: switch Inst[7:5] { |
| 7771 | 0, 9, // 17600: case 0x0: { |
| 7772 | OPC_CheckField, 13, 1, 0, // 17602: check Inst[13] == 0x0 |
| 7773 | OPC_Decode, 253, 13, 134, 1, // 17606: decode to M2_hmmpyh_s1 using decoder 134 |
| 7774 | // 17606: } |
| 7775 | 1, 9, // 17611: case 0x1: { |
| 7776 | OPC_CheckField, 13, 1, 0, // 17613: check Inst[13] == 0x0 |
| 7777 | OPC_Decode, 255, 13, 134, 1, // 17617: decode to M2_hmmpyl_s1 using decoder 134 |
| 7778 | // 17617: } |
| 7779 | 2, 9, // 17622: case 0x2: { |
| 7780 | OPC_CheckField, 13, 1, 0, // 17624: check Inst[13] == 0x0 |
| 7781 | OPC_Decode, 229, 14, 134, 1, // 17628: decode to M2_mpy_up_s1 using decoder 134 |
| 7782 | // 17628: } |
| 7783 | 4, 9, // 17633: case 0x4: { |
| 7784 | OPC_CheckField, 13, 1, 0, // 17635: check Inst[13] == 0x0 |
| 7785 | OPC_Decode, 252, 13, 134, 1, // 17639: decode to M2_hmmpyh_rs1 using decoder 134 |
| 7786 | // 17639: } |
| 7787 | 6, 9, // 17644: case 0x6: { |
| 7788 | OPC_CheckField, 13, 1, 0, // 17646: check Inst[13] == 0x0 |
| 7789 | OPC_Decode, 234, 13, 134, 1, // 17650: decode to M2_cmpyrs_s1 using decoder 134 |
| 7790 | // 17650: } |
| 7791 | 7, 0, // 17655: case 0x7: { |
| 7792 | OPC_CheckField, 13, 1, 0, // 17657: check Inst[13] == 0x0 |
| 7793 | OPC_Decode, 218, 15, 134, 1, // 17661: decode to M2_vmpy2s_s1pack using decoder 134 |
| 7794 | // 17661: } |
| 7795 | // 17661: } // switch Inst[7:5] |
| 7796 | // 17661: } |
| 7797 | 111, 36, // 17666: case 0x6f: { |
| 7798 | OPC_SwitchField, 5, 3, // 17668: switch Inst[7:5] { |
| 7799 | 0, 9, // 17671: case 0x0: { |
| 7800 | OPC_CheckField, 13, 1, 0, // 17673: check Inst[13] == 0x0 |
| 7801 | OPC_Decode, 230, 14, 134, 1, // 17677: decode to M2_mpy_up_s1_sat using decoder 134 |
| 7802 | // 17677: } |
| 7803 | 4, 9, // 17682: case 0x4: { |
| 7804 | OPC_CheckField, 13, 1, 0, // 17684: check Inst[13] == 0x0 |
| 7805 | OPC_Decode, 254, 13, 134, 1, // 17688: decode to M2_hmmpyl_rs1 using decoder 134 |
| 7806 | // 17688: } |
| 7807 | 6, 0, // 17693: case 0x6: { |
| 7808 | OPC_CheckField, 13, 1, 0, // 17695: check Inst[13] == 0x0 |
| 7809 | OPC_Decode, 236, 13, 134, 1, // 17699: decode to M2_cmpyrsc_s1 using decoder 134 |
| 7810 | // 17699: } |
| 7811 | // 17699: } // switch Inst[7:5] |
| 7812 | // 17699: } |
| 7813 | 112, 91, // 17704: case 0x70: { |
| 7814 | OPC_SwitchField, 5, 3, // 17706: switch Inst[7:5] { |
| 7815 | 0, 9, // 17709: case 0x0: { |
| 7816 | OPC_CheckField, 13, 1, 0, // 17711: check Inst[13] == 0x0 |
| 7817 | OPC_Decode, 170, 14, 222, 1, // 17715: decode to M2_mpy_acc_ll_s0 using decoder 222 |
| 7818 | // 17715: } |
| 7819 | 1, 9, // 17720: case 0x1: { |
| 7820 | OPC_CheckField, 13, 1, 0, // 17722: check Inst[13] == 0x0 |
| 7821 | OPC_Decode, 168, 14, 222, 1, // 17726: decode to M2_mpy_acc_lh_s0 using decoder 222 |
| 7822 | // 17726: } |
| 7823 | 2, 9, // 17731: case 0x2: { |
| 7824 | OPC_CheckField, 13, 1, 0, // 17733: check Inst[13] == 0x0 |
| 7825 | OPC_Decode, 166, 14, 222, 1, // 17737: decode to M2_mpy_acc_hl_s0 using decoder 222 |
| 7826 | // 17737: } |
| 7827 | 3, 9, // 17742: case 0x3: { |
| 7828 | OPC_CheckField, 13, 1, 0, // 17744: check Inst[13] == 0x0 |
| 7829 | OPC_Decode, 164, 14, 222, 1, // 17748: decode to M2_mpy_acc_hh_s0 using decoder 222 |
| 7830 | // 17748: } |
| 7831 | 4, 9, // 17753: case 0x4: { |
| 7832 | OPC_CheckField, 13, 1, 0, // 17755: check Inst[13] == 0x0 |
| 7833 | OPC_Decode, 178, 14, 222, 1, // 17759: decode to M2_mpy_acc_sat_ll_s0 using decoder 222 |
| 7834 | // 17759: } |
| 7835 | 5, 9, // 17764: case 0x5: { |
| 7836 | OPC_CheckField, 13, 1, 0, // 17766: check Inst[13] == 0x0 |
| 7837 | OPC_Decode, 176, 14, 222, 1, // 17770: decode to M2_mpy_acc_sat_lh_s0 using decoder 222 |
| 7838 | // 17770: } |
| 7839 | 6, 9, // 17775: case 0x6: { |
| 7840 | OPC_CheckField, 13, 1, 0, // 17777: check Inst[13] == 0x0 |
| 7841 | OPC_Decode, 174, 14, 222, 1, // 17781: decode to M2_mpy_acc_sat_hl_s0 using decoder 222 |
| 7842 | // 17781: } |
| 7843 | 7, 0, // 17786: case 0x7: { |
| 7844 | OPC_CheckField, 13, 1, 0, // 17788: check Inst[13] == 0x0 |
| 7845 | OPC_Decode, 172, 14, 222, 1, // 17792: decode to M2_mpy_acc_sat_hh_s0 using decoder 222 |
| 7846 | // 17792: } |
| 7847 | // 17792: } // switch Inst[7:5] |
| 7848 | // 17792: } |
| 7849 | 113, 91, // 17797: case 0x71: { |
| 7850 | OPC_SwitchField, 5, 3, // 17799: switch Inst[7:5] { |
| 7851 | 0, 9, // 17802: case 0x0: { |
| 7852 | OPC_CheckField, 13, 1, 0, // 17804: check Inst[13] == 0x0 |
| 7853 | OPC_Decode, 194, 14, 222, 1, // 17808: decode to M2_mpy_nac_ll_s0 using decoder 222 |
| 7854 | // 17808: } |
| 7855 | 1, 9, // 17813: case 0x1: { |
| 7856 | OPC_CheckField, 13, 1, 0, // 17815: check Inst[13] == 0x0 |
| 7857 | OPC_Decode, 192, 14, 222, 1, // 17819: decode to M2_mpy_nac_lh_s0 using decoder 222 |
| 7858 | // 17819: } |
| 7859 | 2, 9, // 17824: case 0x2: { |
| 7860 | OPC_CheckField, 13, 1, 0, // 17826: check Inst[13] == 0x0 |
| 7861 | OPC_Decode, 190, 14, 222, 1, // 17830: decode to M2_mpy_nac_hl_s0 using decoder 222 |
| 7862 | // 17830: } |
| 7863 | 3, 9, // 17835: case 0x3: { |
| 7864 | OPC_CheckField, 13, 1, 0, // 17837: check Inst[13] == 0x0 |
| 7865 | OPC_Decode, 188, 14, 222, 1, // 17841: decode to M2_mpy_nac_hh_s0 using decoder 222 |
| 7866 | // 17841: } |
| 7867 | 4, 9, // 17846: case 0x4: { |
| 7868 | OPC_CheckField, 13, 1, 0, // 17848: check Inst[13] == 0x0 |
| 7869 | OPC_Decode, 202, 14, 222, 1, // 17852: decode to M2_mpy_nac_sat_ll_s0 using decoder 222 |
| 7870 | // 17852: } |
| 7871 | 5, 9, // 17857: case 0x5: { |
| 7872 | OPC_CheckField, 13, 1, 0, // 17859: check Inst[13] == 0x0 |
| 7873 | OPC_Decode, 200, 14, 222, 1, // 17863: decode to M2_mpy_nac_sat_lh_s0 using decoder 222 |
| 7874 | // 17863: } |
| 7875 | 6, 9, // 17868: case 0x6: { |
| 7876 | OPC_CheckField, 13, 1, 0, // 17870: check Inst[13] == 0x0 |
| 7877 | OPC_Decode, 198, 14, 222, 1, // 17874: decode to M2_mpy_nac_sat_hl_s0 using decoder 222 |
| 7878 | // 17874: } |
| 7879 | 7, 0, // 17879: case 0x7: { |
| 7880 | OPC_CheckField, 13, 1, 0, // 17881: check Inst[13] == 0x0 |
| 7881 | OPC_Decode, 196, 14, 222, 1, // 17885: decode to M2_mpy_nac_sat_hh_s0 using decoder 222 |
| 7882 | // 17885: } |
| 7883 | // 17885: } // switch Inst[7:5] |
| 7884 | // 17885: } |
| 7885 | 114, 47, // 17890: case 0x72: { |
| 7886 | OPC_SwitchField, 5, 3, // 17892: switch Inst[7:5] { |
| 7887 | 0, 9, // 17895: case 0x0: { |
| 7888 | OPC_CheckField, 13, 1, 0, // 17897: check Inst[13] == 0x0 |
| 7889 | OPC_Decode, 145, 15, 222, 1, // 17901: decode to M2_mpyu_acc_ll_s0 using decoder 222 |
| 7890 | // 17901: } |
| 7891 | 1, 9, // 17906: case 0x1: { |
| 7892 | OPC_CheckField, 13, 1, 0, // 17908: check Inst[13] == 0x0 |
| 7893 | OPC_Decode, 143, 15, 222, 1, // 17912: decode to M2_mpyu_acc_lh_s0 using decoder 222 |
| 7894 | // 17912: } |
| 7895 | 2, 9, // 17917: case 0x2: { |
| 7896 | OPC_CheckField, 13, 1, 0, // 17919: check Inst[13] == 0x0 |
| 7897 | OPC_Decode, 141, 15, 222, 1, // 17923: decode to M2_mpyu_acc_hl_s0 using decoder 222 |
| 7898 | // 17923: } |
| 7899 | 3, 0, // 17928: case 0x3: { |
| 7900 | OPC_CheckField, 13, 1, 0, // 17930: check Inst[13] == 0x0 |
| 7901 | OPC_Decode, 139, 15, 222, 1, // 17934: decode to M2_mpyu_acc_hh_s0 using decoder 222 |
| 7902 | // 17934: } |
| 7903 | // 17934: } // switch Inst[7:5] |
| 7904 | // 17934: } |
| 7905 | 115, 47, // 17939: case 0x73: { |
| 7906 | OPC_SwitchField, 5, 3, // 17941: switch Inst[7:5] { |
| 7907 | 0, 9, // 17944: case 0x0: { |
| 7908 | OPC_CheckField, 13, 1, 0, // 17946: check Inst[13] == 0x0 |
| 7909 | OPC_Decode, 161, 15, 222, 1, // 17950: decode to M2_mpyu_nac_ll_s0 using decoder 222 |
| 7910 | // 17950: } |
| 7911 | 1, 9, // 17955: case 0x1: { |
| 7912 | OPC_CheckField, 13, 1, 0, // 17957: check Inst[13] == 0x0 |
| 7913 | OPC_Decode, 159, 15, 222, 1, // 17961: decode to M2_mpyu_nac_lh_s0 using decoder 222 |
| 7914 | // 17961: } |
| 7915 | 2, 9, // 17966: case 0x2: { |
| 7916 | OPC_CheckField, 13, 1, 0, // 17968: check Inst[13] == 0x0 |
| 7917 | OPC_Decode, 157, 15, 222, 1, // 17972: decode to M2_mpyu_nac_hl_s0 using decoder 222 |
| 7918 | // 17972: } |
| 7919 | 3, 0, // 17977: case 0x3: { |
| 7920 | OPC_CheckField, 13, 1, 0, // 17979: check Inst[13] == 0x0 |
| 7921 | OPC_Decode, 155, 15, 222, 1, // 17983: decode to M2_mpyu_nac_hh_s0 using decoder 222 |
| 7922 | // 17983: } |
| 7923 | // 17983: } // switch Inst[7:5] |
| 7924 | // 17983: } |
| 7925 | 116, 91, // 17988: case 0x74: { |
| 7926 | OPC_SwitchField, 5, 3, // 17990: switch Inst[7:5] { |
| 7927 | 0, 9, // 17993: case 0x0: { |
| 7928 | OPC_CheckField, 13, 1, 0, // 17995: check Inst[13] == 0x0 |
| 7929 | OPC_Decode, 171, 14, 222, 1, // 17999: decode to M2_mpy_acc_ll_s1 using decoder 222 |
| 7930 | // 17999: } |
| 7931 | 1, 9, // 18004: case 0x1: { |
| 7932 | OPC_CheckField, 13, 1, 0, // 18006: check Inst[13] == 0x0 |
| 7933 | OPC_Decode, 169, 14, 222, 1, // 18010: decode to M2_mpy_acc_lh_s1 using decoder 222 |
| 7934 | // 18010: } |
| 7935 | 2, 9, // 18015: case 0x2: { |
| 7936 | OPC_CheckField, 13, 1, 0, // 18017: check Inst[13] == 0x0 |
| 7937 | OPC_Decode, 167, 14, 222, 1, // 18021: decode to M2_mpy_acc_hl_s1 using decoder 222 |
| 7938 | // 18021: } |
| 7939 | 3, 9, // 18026: case 0x3: { |
| 7940 | OPC_CheckField, 13, 1, 0, // 18028: check Inst[13] == 0x0 |
| 7941 | OPC_Decode, 165, 14, 222, 1, // 18032: decode to M2_mpy_acc_hh_s1 using decoder 222 |
| 7942 | // 18032: } |
| 7943 | 4, 9, // 18037: case 0x4: { |
| 7944 | OPC_CheckField, 13, 1, 0, // 18039: check Inst[13] == 0x0 |
| 7945 | OPC_Decode, 179, 14, 222, 1, // 18043: decode to M2_mpy_acc_sat_ll_s1 using decoder 222 |
| 7946 | // 18043: } |
| 7947 | 5, 9, // 18048: case 0x5: { |
| 7948 | OPC_CheckField, 13, 1, 0, // 18050: check Inst[13] == 0x0 |
| 7949 | OPC_Decode, 177, 14, 222, 1, // 18054: decode to M2_mpy_acc_sat_lh_s1 using decoder 222 |
| 7950 | // 18054: } |
| 7951 | 6, 9, // 18059: case 0x6: { |
| 7952 | OPC_CheckField, 13, 1, 0, // 18061: check Inst[13] == 0x0 |
| 7953 | OPC_Decode, 175, 14, 222, 1, // 18065: decode to M2_mpy_acc_sat_hl_s1 using decoder 222 |
| 7954 | // 18065: } |
| 7955 | 7, 0, // 18070: case 0x7: { |
| 7956 | OPC_CheckField, 13, 1, 0, // 18072: check Inst[13] == 0x0 |
| 7957 | OPC_Decode, 173, 14, 222, 1, // 18076: decode to M2_mpy_acc_sat_hh_s1 using decoder 222 |
| 7958 | // 18076: } |
| 7959 | // 18076: } // switch Inst[7:5] |
| 7960 | // 18076: } |
| 7961 | 117, 91, // 18081: case 0x75: { |
| 7962 | OPC_SwitchField, 5, 3, // 18083: switch Inst[7:5] { |
| 7963 | 0, 9, // 18086: case 0x0: { |
| 7964 | OPC_CheckField, 13, 1, 0, // 18088: check Inst[13] == 0x0 |
| 7965 | OPC_Decode, 195, 14, 222, 1, // 18092: decode to M2_mpy_nac_ll_s1 using decoder 222 |
| 7966 | // 18092: } |
| 7967 | 1, 9, // 18097: case 0x1: { |
| 7968 | OPC_CheckField, 13, 1, 0, // 18099: check Inst[13] == 0x0 |
| 7969 | OPC_Decode, 193, 14, 222, 1, // 18103: decode to M2_mpy_nac_lh_s1 using decoder 222 |
| 7970 | // 18103: } |
| 7971 | 2, 9, // 18108: case 0x2: { |
| 7972 | OPC_CheckField, 13, 1, 0, // 18110: check Inst[13] == 0x0 |
| 7973 | OPC_Decode, 191, 14, 222, 1, // 18114: decode to M2_mpy_nac_hl_s1 using decoder 222 |
| 7974 | // 18114: } |
| 7975 | 3, 9, // 18119: case 0x3: { |
| 7976 | OPC_CheckField, 13, 1, 0, // 18121: check Inst[13] == 0x0 |
| 7977 | OPC_Decode, 189, 14, 222, 1, // 18125: decode to M2_mpy_nac_hh_s1 using decoder 222 |
| 7978 | // 18125: } |
| 7979 | 4, 9, // 18130: case 0x4: { |
| 7980 | OPC_CheckField, 13, 1, 0, // 18132: check Inst[13] == 0x0 |
| 7981 | OPC_Decode, 203, 14, 222, 1, // 18136: decode to M2_mpy_nac_sat_ll_s1 using decoder 222 |
| 7982 | // 18136: } |
| 7983 | 5, 9, // 18141: case 0x5: { |
| 7984 | OPC_CheckField, 13, 1, 0, // 18143: check Inst[13] == 0x0 |
| 7985 | OPC_Decode, 201, 14, 222, 1, // 18147: decode to M2_mpy_nac_sat_lh_s1 using decoder 222 |
| 7986 | // 18147: } |
| 7987 | 6, 9, // 18152: case 0x6: { |
| 7988 | OPC_CheckField, 13, 1, 0, // 18154: check Inst[13] == 0x0 |
| 7989 | OPC_Decode, 199, 14, 222, 1, // 18158: decode to M2_mpy_nac_sat_hl_s1 using decoder 222 |
| 7990 | // 18158: } |
| 7991 | 7, 0, // 18163: case 0x7: { |
| 7992 | OPC_CheckField, 13, 1, 0, // 18165: check Inst[13] == 0x0 |
| 7993 | OPC_Decode, 197, 14, 222, 1, // 18169: decode to M2_mpy_nac_sat_hh_s1 using decoder 222 |
| 7994 | // 18169: } |
| 7995 | // 18169: } // switch Inst[7:5] |
| 7996 | // 18169: } |
| 7997 | 118, 47, // 18174: case 0x76: { |
| 7998 | OPC_SwitchField, 5, 3, // 18176: switch Inst[7:5] { |
| 7999 | 0, 9, // 18179: case 0x0: { |
| 8000 | OPC_CheckField, 13, 1, 0, // 18181: check Inst[13] == 0x0 |
| 8001 | OPC_Decode, 146, 15, 222, 1, // 18185: decode to M2_mpyu_acc_ll_s1 using decoder 222 |
| 8002 | // 18185: } |
| 8003 | 1, 9, // 18190: case 0x1: { |
| 8004 | OPC_CheckField, 13, 1, 0, // 18192: check Inst[13] == 0x0 |
| 8005 | OPC_Decode, 144, 15, 222, 1, // 18196: decode to M2_mpyu_acc_lh_s1 using decoder 222 |
| 8006 | // 18196: } |
| 8007 | 2, 9, // 18201: case 0x2: { |
| 8008 | OPC_CheckField, 13, 1, 0, // 18203: check Inst[13] == 0x0 |
| 8009 | OPC_Decode, 142, 15, 222, 1, // 18207: decode to M2_mpyu_acc_hl_s1 using decoder 222 |
| 8010 | // 18207: } |
| 8011 | 3, 0, // 18212: case 0x3: { |
| 8012 | OPC_CheckField, 13, 1, 0, // 18214: check Inst[13] == 0x0 |
| 8013 | OPC_Decode, 140, 15, 222, 1, // 18218: decode to M2_mpyu_acc_hh_s1 using decoder 222 |
| 8014 | // 18218: } |
| 8015 | // 18218: } // switch Inst[7:5] |
| 8016 | // 18218: } |
| 8017 | 119, 47, // 18223: case 0x77: { |
| 8018 | OPC_SwitchField, 5, 3, // 18225: switch Inst[7:5] { |
| 8019 | 0, 9, // 18228: case 0x0: { |
| 8020 | OPC_CheckField, 13, 1, 0, // 18230: check Inst[13] == 0x0 |
| 8021 | OPC_Decode, 162, 15, 222, 1, // 18234: decode to M2_mpyu_nac_ll_s1 using decoder 222 |
| 8022 | // 18234: } |
| 8023 | 1, 9, // 18239: case 0x1: { |
| 8024 | OPC_CheckField, 13, 1, 0, // 18241: check Inst[13] == 0x0 |
| 8025 | OPC_Decode, 160, 15, 222, 1, // 18245: decode to M2_mpyu_nac_lh_s1 using decoder 222 |
| 8026 | // 18245: } |
| 8027 | 2, 9, // 18250: case 0x2: { |
| 8028 | OPC_CheckField, 13, 1, 0, // 18252: check Inst[13] == 0x0 |
| 8029 | OPC_Decode, 158, 15, 222, 1, // 18256: decode to M2_mpyu_nac_hl_s1 using decoder 222 |
| 8030 | // 18256: } |
| 8031 | 3, 0, // 18261: case 0x3: { |
| 8032 | OPC_CheckField, 13, 1, 0, // 18263: check Inst[13] == 0x0 |
| 8033 | OPC_Decode, 156, 15, 222, 1, // 18267: decode to M2_mpyu_nac_hh_s1 using decoder 222 |
| 8034 | // 18267: } |
| 8035 | // 18267: } // switch Inst[7:5] |
| 8036 | // 18267: } |
| 8037 | 120, 80, // 18272: case 0x78: { |
| 8038 | OPC_SwitchField, 5, 3, // 18274: switch Inst[7:5] { |
| 8039 | 0, 9, // 18277: case 0x0: { |
| 8040 | OPC_CheckField, 13, 1, 0, // 18279: check Inst[13] == 0x0 |
| 8041 | OPC_Decode, 128, 14, 222, 1, // 18283: decode to M2_maci using decoder 222 |
| 8042 | // 18283: } |
| 8043 | 1, 9, // 18288: case 0x1: { |
| 8044 | OPC_CheckField, 13, 1, 0, // 18290: check Inst[13] == 0x0 |
| 8045 | OPC_Decode, 223, 13, 222, 1, // 18294: decode to M2_acci using decoder 222 |
| 8046 | // 18294: } |
| 8047 | 3, 9, // 18299: case 0x3: { |
| 8048 | OPC_CheckField, 13, 1, 0, // 18301: check Inst[13] == 0x0 |
| 8049 | OPC_Decode, 190, 15, 255, 1, // 18305: decode to M2_subacc using decoder 255 |
| 8050 | // 18305: } |
| 8051 | 4, 9, // 18310: case 0x4: { |
| 8052 | OPC_CheckField, 13, 1, 0, // 18312: check Inst[13] == 0x0 |
| 8053 | OPC_Decode, 174, 10, 222, 1, // 18316: decode to F2_sffma using decoder 222 |
| 8054 | // 18316: } |
| 8055 | 5, 9, // 18321: case 0x5: { |
| 8056 | OPC_CheckField, 13, 1, 0, // 18323: check Inst[13] == 0x0 |
| 8057 | OPC_Decode, 177, 10, 222, 1, // 18327: decode to F2_sffms using decoder 222 |
| 8058 | // 18327: } |
| 8059 | 6, 9, // 18332: case 0x6: { |
| 8060 | OPC_CheckField, 13, 1, 0, // 18334: check Inst[13] == 0x0 |
| 8061 | OPC_Decode, 175, 10, 222, 1, // 18338: decode to F2_sffma_lib using decoder 222 |
| 8062 | // 18338: } |
| 8063 | 7, 0, // 18343: case 0x7: { |
| 8064 | OPC_CheckField, 13, 1, 0, // 18345: check Inst[13] == 0x0 |
| 8065 | OPC_Decode, 178, 10, 222, 1, // 18349: decode to F2_sffms_lib using decoder 222 |
| 8066 | // 18349: } |
| 8067 | // 18349: } // switch Inst[7:5] |
| 8068 | // 18349: } |
| 8069 | 121, 36, // 18354: case 0x79: { |
| 8070 | OPC_SwitchField, 5, 3, // 18356: switch Inst[7:5] { |
| 8071 | 0, 9, // 18359: case 0x0: { |
| 8072 | OPC_CheckField, 13, 1, 0, // 18361: check Inst[13] == 0x0 |
| 8073 | OPC_Decode, 128, 16, 222, 1, // 18365: decode to M4_or_andn using decoder 222 |
| 8074 | // 18365: } |
| 8075 | 1, 9, // 18370: case 0x1: { |
| 8076 | OPC_CheckField, 13, 1, 0, // 18372: check Inst[13] == 0x0 |
| 8077 | OPC_Decode, 241, 15, 222, 1, // 18376: decode to M4_and_andn using decoder 222 |
| 8078 | // 18376: } |
| 8079 | 2, 0, // 18381: case 0x2: { |
| 8080 | OPC_CheckField, 13, 1, 0, // 18383: check Inst[13] == 0x0 |
| 8081 | OPC_Decode, 144, 16, 222, 1, // 18387: decode to M4_xor_andn using decoder 222 |
| 8082 | // 18387: } |
| 8083 | // 18387: } // switch Inst[7:5] |
| 8084 | // 18387: } |
| 8085 | 122, 47, // 18392: case 0x7a: { |
| 8086 | OPC_SwitchField, 5, 3, // 18394: switch Inst[7:5] { |
| 8087 | 0, 9, // 18397: case 0x0: { |
| 8088 | OPC_CheckField, 13, 1, 0, // 18399: check Inst[13] == 0x0 |
| 8089 | OPC_Decode, 240, 15, 222, 1, // 18403: decode to M4_and_and using decoder 222 |
| 8090 | // 18403: } |
| 8091 | 1, 9, // 18408: case 0x1: { |
| 8092 | OPC_CheckField, 13, 1, 0, // 18410: check Inst[13] == 0x0 |
| 8093 | OPC_Decode, 242, 15, 222, 1, // 18414: decode to M4_and_or using decoder 222 |
| 8094 | // 18414: } |
| 8095 | 2, 9, // 18419: case 0x2: { |
| 8096 | OPC_CheckField, 13, 1, 0, // 18421: check Inst[13] == 0x0 |
| 8097 | OPC_Decode, 243, 15, 222, 1, // 18425: decode to M4_and_xor using decoder 222 |
| 8098 | // 18425: } |
| 8099 | 3, 0, // 18430: case 0x3: { |
| 8100 | OPC_CheckField, 13, 1, 0, // 18432: check Inst[13] == 0x0 |
| 8101 | OPC_Decode, 255, 15, 222, 1, // 18436: decode to M4_or_and using decoder 222 |
| 8102 | // 18436: } |
| 8103 | // 18436: } // switch Inst[7:5] |
| 8104 | // 18436: } |
| 8105 | 123, 41, // 18441: case 0x7b: { |
| 8106 | OPC_SwitchField, 7, 1, // 18443: switch Inst[7] { |
| 8107 | 0, 25, // 18446: case 0x0: { |
| 8108 | OPC_SwitchField, 5, 2, // 18448: switch Inst[6:5] { |
| 8109 | 0, 9, // 18451: case 0x0: { |
| 8110 | OPC_CheckField, 13, 1, 0, // 18453: check Inst[13] == 0x0 |
| 8111 | OPC_Decode, 248, 15, 222, 1, // 18457: decode to M4_mac_up_s1_sat using decoder 222 |
| 8112 | // 18457: } |
| 8113 | 1, 0, // 18462: case 0x1: { |
| 8114 | OPC_CheckField, 13, 1, 0, // 18464: check Inst[13] == 0x0 |
| 8115 | OPC_Decode, 254, 15, 222, 1, // 18468: decode to M4_nac_up_s1_sat using decoder 222 |
| 8116 | // 18468: } |
| 8117 | // 18468: } // switch Inst[6:5] |
| 8118 | // 18468: } |
| 8119 | 1, 0, // 18473: case 0x1: { |
| 8120 | OPC_CheckField, 13, 1, 0, // 18475: check Inst[13] == 0x0 |
| 8121 | OPC_Decode, 176, 10, 128, 2, // 18479: decode to F2_sffma_sc using decoder 256 |
| 8122 | // 18479: } |
| 8123 | // 18479: } // switch Inst[7] |
| 8124 | // 18479: } |
| 8125 | 124, 38, // 18484: case 0x7c: { |
| 8126 | OPC_SwitchField, 5, 3, // 18486: switch Inst[7:5] { |
| 8127 | 0, 11, // 18489: case 0x0: { |
| 8128 | OPC_CheckPredicate, 4, // 18491: check predicate 4 |
| 8129 | OPC_CheckField, 13, 1, 0, // 18493: check Inst[13] == 0x0 |
| 8130 | OPC_Decode, 163, 14, 222, 1, // 18497: decode to M2_mnaci using decoder 222 |
| 8131 | // 18497: } |
| 8132 | 1, 9, // 18502: case 0x1: { |
| 8133 | OPC_CheckField, 13, 1, 0, // 18504: check Inst[13] == 0x0 |
| 8134 | OPC_Decode, 188, 15, 222, 1, // 18508: decode to M2_nacci using decoder 222 |
| 8135 | // 18508: } |
| 8136 | 3, 0, // 18513: case 0x3: { |
| 8137 | OPC_CheckField, 13, 1, 0, // 18515: check Inst[13] == 0x0 |
| 8138 | OPC_Decode, 239, 15, 222, 1, // 18519: decode to M2_xor_xacc using decoder 222 |
| 8139 | // 18519: } |
| 8140 | // 18519: } // switch Inst[7:5] |
| 8141 | // 18519: } |
| 8142 | 126, 0, // 18524: case 0x7e: { |
| 8143 | OPC_SwitchField, 5, 3, // 18526: switch Inst[7:5] { |
| 8144 | 0, 9, // 18529: case 0x0: { |
| 8145 | OPC_CheckField, 13, 1, 0, // 18531: check Inst[13] == 0x0 |
| 8146 | OPC_Decode, 129, 16, 222, 1, // 18535: decode to M4_or_or using decoder 222 |
| 8147 | // 18535: } |
| 8148 | 1, 9, // 18540: case 0x1: { |
| 8149 | OPC_CheckField, 13, 1, 0, // 18542: check Inst[13] == 0x0 |
| 8150 | OPC_Decode, 130, 16, 222, 1, // 18546: decode to M4_or_xor using decoder 222 |
| 8151 | // 18546: } |
| 8152 | 2, 9, // 18551: case 0x2: { |
| 8153 | OPC_CheckField, 13, 1, 0, // 18553: check Inst[13] == 0x0 |
| 8154 | OPC_Decode, 143, 16, 222, 1, // 18557: decode to M4_xor_and using decoder 222 |
| 8155 | // 18557: } |
| 8156 | 3, 0, // 18562: case 0x3: { |
| 8157 | OPC_CheckField, 13, 1, 0, // 18564: check Inst[13] == 0x0 |
| 8158 | OPC_Decode, 145, 16, 222, 1, // 18568: decode to M4_xor_or using decoder 222 |
| 8159 | // 18568: } |
| 8160 | // 18568: } // switch Inst[7:5] |
| 8161 | // 18568: } |
| 8162 | // 18568: } // switch Inst[27:21] |
| 8163 | // 18568: } |
| 8164 | 15, 0, // 18573: case 0xf: { |
| 8165 | OPC_SwitchField, 21, 7, // 18575: switch Inst[27:21] { |
| 8166 | 8, 13, // 18578: case 0x8: { |
| 8167 | OPC_CheckField, 13, 1, 0, // 18580: check Inst[13] == 0x0 |
| 8168 | OPC_CheckField, 5, 3, 0, // 18584: check Inst[7:5] == 0x0 |
| 8169 | OPC_Decode, 185, 7, 134, 1, // 18588: decode to A2_and using decoder 134 |
| 8170 | // 18588: } |
| 8171 | 9, 13, // 18593: case 0x9: { |
| 8172 | OPC_CheckField, 13, 1, 0, // 18595: check Inst[13] == 0x0 |
| 8173 | OPC_CheckField, 5, 3, 0, // 18599: check Inst[7:5] == 0x0 |
| 8174 | OPC_Decode, 208, 7, 134, 1, // 18603: decode to A2_or using decoder 134 |
| 8175 | // 18603: } |
| 8176 | 11, 13, // 18608: case 0xb: { |
| 8177 | OPC_CheckField, 13, 1, 0, // 18610: check Inst[13] == 0x0 |
| 8178 | OPC_CheckField, 5, 3, 0, // 18614: check Inst[7:5] == 0x0 |
| 8179 | OPC_Decode, 209, 8, 134, 1, // 18618: decode to A2_xor using decoder 134 |
| 8180 | // 18618: } |
| 8181 | 12, 13, // 18623: case 0xc: { |
| 8182 | OPC_CheckField, 13, 1, 0, // 18625: check Inst[13] == 0x0 |
| 8183 | OPC_CheckField, 5, 3, 0, // 18629: check Inst[7:5] == 0x0 |
| 8184 | OPC_Decode, 213, 8, 227, 1, // 18633: decode to A4_andn using decoder 227 |
| 8185 | // 18633: } |
| 8186 | 13, 13, // 18638: case 0xd: { |
| 8187 | OPC_CheckField, 13, 1, 0, // 18640: check Inst[13] == 0x0 |
| 8188 | OPC_CheckField, 5, 3, 0, // 18644: check Inst[7:5] == 0x0 |
| 8189 | OPC_Decode, 238, 8, 227, 1, // 18648: decode to A4_orn using decoder 227 |
| 8190 | // 18648: } |
| 8191 | 16, 25, // 18653: case 0x10: { |
| 8192 | OPC_SwitchField, 2, 6, // 18655: switch Inst[7:2] { |
| 8193 | 0, 9, // 18658: case 0x0: { |
| 8194 | OPC_CheckField, 13, 1, 0, // 18660: check Inst[13] == 0x0 |
| 8195 | OPC_Decode, 190, 9, 169, 1, // 18664: decode to C2_cmpeq using decoder 169 |
| 8196 | // 18664: } |
| 8197 | 4, 0, // 18669: case 0x4: { |
| 8198 | OPC_CheckField, 13, 1, 0, // 18671: check Inst[13] == 0x0 |
| 8199 | OPC_Decode, 221, 9, 169, 1, // 18675: decode to C4_cmpneq using decoder 169 |
| 8200 | // 18675: } |
| 8201 | // 18675: } // switch Inst[7:2] |
| 8202 | // 18675: } |
| 8203 | 18, 25, // 18680: case 0x12: { |
| 8204 | OPC_SwitchField, 2, 6, // 18682: switch Inst[7:2] { |
| 8205 | 0, 9, // 18685: case 0x0: { |
| 8206 | OPC_CheckField, 13, 1, 0, // 18687: check Inst[13] == 0x0 |
| 8207 | OPC_Decode, 193, 9, 169, 1, // 18691: decode to C2_cmpgt using decoder 169 |
| 8208 | // 18691: } |
| 8209 | 4, 0, // 18696: case 0x4: { |
| 8210 | OPC_CheckField, 13, 1, 0, // 18698: check Inst[13] == 0x0 |
| 8211 | OPC_Decode, 217, 9, 169, 1, // 18702: decode to C4_cmplte using decoder 169 |
| 8212 | // 18702: } |
| 8213 | // 18702: } // switch Inst[7:2] |
| 8214 | // 18702: } |
| 8215 | 19, 25, // 18707: case 0x13: { |
| 8216 | OPC_SwitchField, 2, 6, // 18709: switch Inst[7:2] { |
| 8217 | 0, 9, // 18712: case 0x0: { |
| 8218 | OPC_CheckField, 13, 1, 0, // 18714: check Inst[13] == 0x0 |
| 8219 | OPC_Decode, 196, 9, 169, 1, // 18718: decode to C2_cmpgtu using decoder 169 |
| 8220 | // 18718: } |
| 8221 | 4, 0, // 18723: case 0x4: { |
| 8222 | OPC_CheckField, 13, 1, 0, // 18725: check Inst[13] == 0x0 |
| 8223 | OPC_Decode, 219, 9, 169, 1, // 18729: decode to C4_cmplteu using decoder 169 |
| 8224 | // 18729: } |
| 8225 | // 18729: } // switch Inst[7:2] |
| 8226 | // 18729: } |
| 8227 | 24, 13, // 18734: case 0x18: { |
| 8228 | OPC_CheckField, 13, 1, 0, // 18736: check Inst[13] == 0x0 |
| 8229 | OPC_CheckField, 5, 3, 0, // 18740: check Inst[7:5] == 0x0 |
| 8230 | OPC_Decode, 166, 7, 134, 1, // 18744: decode to A2_add using decoder 134 |
| 8231 | // 18744: } |
| 8232 | 25, 13, // 18749: case 0x19: { |
| 8233 | OPC_CheckField, 13, 1, 0, // 18751: check Inst[13] == 0x0 |
| 8234 | OPC_CheckField, 5, 3, 0, // 18755: check Inst[7:5] == 0x0 |
| 8235 | OPC_Decode, 241, 7, 227, 1, // 18759: decode to A2_sub using decoder 227 |
| 8236 | // 18759: } |
| 8237 | 26, 13, // 18764: case 0x1a: { |
| 8238 | OPC_CheckField, 13, 1, 0, // 18766: check Inst[13] == 0x0 |
| 8239 | OPC_CheckField, 5, 3, 0, // 18770: check Inst[7:5] == 0x0 |
| 8240 | OPC_Decode, 136, 9, 134, 1, // 18774: decode to A4_rcmpeq using decoder 134 |
| 8241 | // 18774: } |
| 8242 | 27, 13, // 18779: case 0x1b: { |
| 8243 | OPC_CheckField, 13, 1, 0, // 18781: check Inst[13] == 0x0 |
| 8244 | OPC_CheckField, 5, 3, 0, // 18785: check Inst[7:5] == 0x0 |
| 8245 | OPC_Decode, 138, 9, 134, 1, // 18789: decode to A4_rcmpneq using decoder 134 |
| 8246 | // 18789: } |
| 8247 | 28, 13, // 18794: case 0x1c: { |
| 8248 | OPC_CheckField, 13, 1, 0, // 18796: check Inst[13] == 0x0 |
| 8249 | OPC_CheckField, 5, 3, 0, // 18800: check Inst[7:5] == 0x0 |
| 8250 | OPC_Decode, 190, 7, 227, 1, // 18804: decode to A2_combine_hh using decoder 227 |
| 8251 | // 18804: } |
| 8252 | 29, 13, // 18809: case 0x1d: { |
| 8253 | OPC_CheckField, 13, 1, 0, // 18811: check Inst[13] == 0x0 |
| 8254 | OPC_CheckField, 5, 3, 0, // 18815: check Inst[7:5] == 0x0 |
| 8255 | OPC_Decode, 191, 7, 227, 1, // 18819: decode to A2_combine_hl using decoder 227 |
| 8256 | // 18819: } |
| 8257 | 30, 13, // 18824: case 0x1e: { |
| 8258 | OPC_CheckField, 13, 1, 0, // 18826: check Inst[13] == 0x0 |
| 8259 | OPC_CheckField, 5, 3, 0, // 18830: check Inst[7:5] == 0x0 |
| 8260 | OPC_Decode, 192, 7, 227, 1, // 18834: decode to A2_combine_lh using decoder 227 |
| 8261 | // 18834: } |
| 8262 | 31, 13, // 18839: case 0x1f: { |
| 8263 | OPC_CheckField, 13, 1, 0, // 18841: check Inst[13] == 0x0 |
| 8264 | OPC_CheckField, 5, 3, 0, // 18845: check Inst[7:5] == 0x0 |
| 8265 | OPC_Decode, 193, 7, 227, 1, // 18849: decode to A2_combine_ll using decoder 227 |
| 8266 | // 18849: } |
| 8267 | 32, 13, // 18854: case 0x20: { |
| 8268 | OPC_CheckField, 13, 1, 0, // 18856: check Inst[13] == 0x0 |
| 8269 | OPC_CheckField, 7, 1, 0, // 18860: check Inst[7] == 0x0 |
| 8270 | OPC_Decode, 200, 9, 254, 1, // 18864: decode to C2_mux using decoder 254 |
| 8271 | // 18864: } |
| 8272 | 40, 13, // 18869: case 0x28: { |
| 8273 | OPC_CheckField, 13, 1, 0, // 18871: check Inst[13] == 0x0 |
| 8274 | OPC_CheckField, 5, 3, 0, // 18875: check Inst[7:5] == 0x0 |
| 8275 | OPC_Decode, 195, 7, 226, 1, // 18879: decode to A2_combinew using decoder 226 |
| 8276 | // 18879: } |
| 8277 | 44, 13, // 18884: case 0x2c: { |
| 8278 | OPC_CheckField, 13, 1, 0, // 18886: check Inst[13] == 0x0 |
| 8279 | OPC_CheckField, 5, 3, 0, // 18890: check Inst[7:5] == 0x0 |
| 8280 | OPC_Decode, 210, 17, 226, 1, // 18894: decode to S2_packhl using decoder 226 |
| 8281 | // 18894: } |
| 8282 | 48, 13, // 18899: case 0x30: { |
| 8283 | OPC_CheckField, 13, 1, 0, // 18901: check Inst[13] == 0x0 |
| 8284 | OPC_CheckField, 5, 3, 0, // 18905: check Inst[7:5] == 0x0 |
| 8285 | OPC_Decode, 129, 8, 134, 1, // 18909: decode to A2_svaddh using decoder 134 |
| 8286 | // 18909: } |
| 8287 | 49, 13, // 18914: case 0x31: { |
| 8288 | OPC_CheckField, 13, 1, 0, // 18916: check Inst[13] == 0x0 |
| 8289 | OPC_CheckField, 5, 3, 0, // 18920: check Inst[7:5] == 0x0 |
| 8290 | OPC_Decode, 130, 8, 134, 1, // 18924: decode to A2_svaddhs using decoder 134 |
| 8291 | // 18924: } |
| 8292 | 50, 13, // 18929: case 0x32: { |
| 8293 | OPC_CheckField, 13, 1, 0, // 18931: check Inst[13] == 0x0 |
| 8294 | OPC_CheckField, 5, 3, 0, // 18935: check Inst[7:5] == 0x0 |
| 8295 | OPC_Decode, 182, 7, 134, 1, // 18939: decode to A2_addsat using decoder 134 |
| 8296 | // 18939: } |
| 8297 | 51, 13, // 18944: case 0x33: { |
| 8298 | OPC_CheckField, 13, 1, 0, // 18946: check Inst[13] == 0x0 |
| 8299 | OPC_CheckField, 5, 3, 0, // 18950: check Inst[7:5] == 0x0 |
| 8300 | OPC_Decode, 131, 8, 134, 1, // 18954: decode to A2_svadduhs using decoder 134 |
| 8301 | // 18954: } |
| 8302 | 52, 13, // 18959: case 0x34: { |
| 8303 | OPC_CheckField, 13, 1, 0, // 18961: check Inst[13] == 0x0 |
| 8304 | OPC_CheckField, 5, 3, 0, // 18965: check Inst[7:5] == 0x0 |
| 8305 | OPC_Decode, 135, 8, 227, 1, // 18969: decode to A2_svsubh using decoder 227 |
| 8306 | // 18969: } |
| 8307 | 53, 13, // 18974: case 0x35: { |
| 8308 | OPC_CheckField, 13, 1, 0, // 18976: check Inst[13] == 0x0 |
| 8309 | OPC_CheckField, 5, 3, 0, // 18980: check Inst[7:5] == 0x0 |
| 8310 | OPC_Decode, 136, 8, 227, 1, // 18984: decode to A2_svsubhs using decoder 227 |
| 8311 | // 18984: } |
| 8312 | 54, 13, // 18989: case 0x36: { |
| 8313 | OPC_CheckField, 13, 1, 0, // 18991: check Inst[13] == 0x0 |
| 8314 | OPC_CheckField, 5, 3, 0, // 18995: check Inst[7:5] == 0x0 |
| 8315 | OPC_Decode, 128, 8, 227, 1, // 18999: decode to A2_subsat using decoder 227 |
| 8316 | // 18999: } |
| 8317 | 55, 13, // 19004: case 0x37: { |
| 8318 | OPC_CheckField, 13, 1, 0, // 19006: check Inst[13] == 0x0 |
| 8319 | OPC_CheckField, 5, 3, 0, // 19010: check Inst[7:5] == 0x0 |
| 8320 | OPC_Decode, 137, 8, 227, 1, // 19014: decode to A2_svsubuhs using decoder 227 |
| 8321 | // 19014: } |
| 8322 | 56, 13, // 19019: case 0x38: { |
| 8323 | OPC_CheckField, 13, 1, 0, // 19021: check Inst[13] == 0x0 |
| 8324 | OPC_CheckField, 5, 3, 0, // 19025: check Inst[7:5] == 0x0 |
| 8325 | OPC_Decode, 132, 8, 134, 1, // 19029: decode to A2_svavgh using decoder 134 |
| 8326 | // 19029: } |
| 8327 | 57, 13, // 19034: case 0x39: { |
| 8328 | OPC_CheckField, 13, 1, 0, // 19036: check Inst[13] == 0x0 |
| 8329 | OPC_CheckField, 5, 3, 0, // 19040: check Inst[7:5] == 0x0 |
| 8330 | OPC_Decode, 133, 8, 134, 1, // 19044: decode to A2_svavghs using decoder 134 |
| 8331 | // 19044: } |
| 8332 | 59, 13, // 19049: case 0x3b: { |
| 8333 | OPC_CheckField, 13, 1, 0, // 19051: check Inst[13] == 0x0 |
| 8334 | OPC_CheckField, 5, 3, 0, // 19055: check Inst[7:5] == 0x0 |
| 8335 | OPC_Decode, 134, 8, 227, 1, // 19059: decode to A2_svnavgh using decoder 227 |
| 8336 | // 19059: } |
| 8337 | 72, 41, // 19064: case 0x48: { |
| 8338 | OPC_SwitchField, 7, 1, // 19066: switch Inst[7] { |
| 8339 | 0, 17, // 19069: case 0x0: { |
| 8340 | OPC_SwitchField, 13, 1, // 19071: switch Inst[13] { |
| 8341 | 0, 5, // 19074: case 0x0: { |
| 8342 | OPC_Decode, 221, 7, 254, 1, // 19076: decode to A2_pandt using decoder 254 |
| 8343 | // 19076: } |
| 8344 | 1, 0, // 19081: case 0x1: { |
| 8345 | OPC_Decode, 222, 7, 254, 1, // 19083: decode to A2_pandtnew using decoder 254 |
| 8346 | // 19083: } |
| 8347 | // 19083: } // switch Inst[13] |
| 8348 | // 19083: } |
| 8349 | 1, 0, // 19088: case 0x1: { |
| 8350 | OPC_SwitchField, 13, 1, // 19090: switch Inst[13] { |
| 8351 | 0, 5, // 19093: case 0x0: { |
| 8352 | OPC_Decode, 219, 7, 254, 1, // 19095: decode to A2_pandf using decoder 254 |
| 8353 | // 19095: } |
| 8354 | 1, 0, // 19100: case 0x1: { |
| 8355 | OPC_Decode, 220, 7, 254, 1, // 19102: decode to A2_pandfnew using decoder 254 |
| 8356 | // 19102: } |
| 8357 | // 19102: } // switch Inst[13] |
| 8358 | // 19102: } |
| 8359 | // 19102: } // switch Inst[7] |
| 8360 | // 19102: } |
| 8361 | 73, 41, // 19107: case 0x49: { |
| 8362 | OPC_SwitchField, 7, 1, // 19109: switch Inst[7] { |
| 8363 | 0, 17, // 19112: case 0x0: { |
| 8364 | OPC_SwitchField, 13, 1, // 19114: switch Inst[13] { |
| 8365 | 0, 5, // 19117: case 0x0: { |
| 8366 | OPC_Decode, 225, 7, 254, 1, // 19119: decode to A2_port using decoder 254 |
| 8367 | // 19119: } |
| 8368 | 1, 0, // 19124: case 0x1: { |
| 8369 | OPC_Decode, 226, 7, 254, 1, // 19126: decode to A2_portnew using decoder 254 |
| 8370 | // 19126: } |
| 8371 | // 19126: } // switch Inst[13] |
| 8372 | // 19126: } |
| 8373 | 1, 0, // 19131: case 0x1: { |
| 8374 | OPC_SwitchField, 13, 1, // 19133: switch Inst[13] { |
| 8375 | 0, 5, // 19136: case 0x0: { |
| 8376 | OPC_Decode, 223, 7, 254, 1, // 19138: decode to A2_porf using decoder 254 |
| 8377 | // 19138: } |
| 8378 | 1, 0, // 19143: case 0x1: { |
| 8379 | OPC_Decode, 224, 7, 254, 1, // 19145: decode to A2_porfnew using decoder 254 |
| 8380 | // 19145: } |
| 8381 | // 19145: } // switch Inst[13] |
| 8382 | // 19145: } |
| 8383 | // 19145: } // switch Inst[7] |
| 8384 | // 19145: } |
| 8385 | 75, 41, // 19150: case 0x4b: { |
| 8386 | OPC_SwitchField, 7, 1, // 19152: switch Inst[7] { |
| 8387 | 0, 17, // 19155: case 0x0: { |
| 8388 | OPC_SwitchField, 13, 1, // 19157: switch Inst[13] { |
| 8389 | 0, 5, // 19160: case 0x0: { |
| 8390 | OPC_Decode, 233, 7, 254, 1, // 19162: decode to A2_pxort using decoder 254 |
| 8391 | // 19162: } |
| 8392 | 1, 0, // 19167: case 0x1: { |
| 8393 | OPC_Decode, 234, 7, 254, 1, // 19169: decode to A2_pxortnew using decoder 254 |
| 8394 | // 19169: } |
| 8395 | // 19169: } // switch Inst[13] |
| 8396 | // 19169: } |
| 8397 | 1, 0, // 19174: case 0x1: { |
| 8398 | OPC_SwitchField, 13, 1, // 19176: switch Inst[13] { |
| 8399 | 0, 5, // 19179: case 0x0: { |
| 8400 | OPC_Decode, 231, 7, 254, 1, // 19181: decode to A2_pxorf using decoder 254 |
| 8401 | // 19181: } |
| 8402 | 1, 0, // 19186: case 0x1: { |
| 8403 | OPC_Decode, 232, 7, 254, 1, // 19188: decode to A2_pxorfnew using decoder 254 |
| 8404 | // 19188: } |
| 8405 | // 19188: } // switch Inst[13] |
| 8406 | // 19188: } |
| 8407 | // 19188: } // switch Inst[7] |
| 8408 | // 19188: } |
| 8409 | 88, 41, // 19193: case 0x58: { |
| 8410 | OPC_SwitchField, 7, 1, // 19195: switch Inst[7] { |
| 8411 | 0, 17, // 19198: case 0x0: { |
| 8412 | OPC_SwitchField, 13, 1, // 19200: switch Inst[13] { |
| 8413 | 0, 5, // 19203: case 0x0: { |
| 8414 | OPC_Decode, 217, 7, 254, 1, // 19205: decode to A2_paddt using decoder 254 |
| 8415 | // 19205: } |
| 8416 | 1, 0, // 19210: case 0x1: { |
| 8417 | OPC_Decode, 218, 7, 254, 1, // 19212: decode to A2_paddtnew using decoder 254 |
| 8418 | // 19212: } |
| 8419 | // 19212: } // switch Inst[13] |
| 8420 | // 19212: } |
| 8421 | 1, 0, // 19217: case 0x1: { |
| 8422 | OPC_SwitchField, 13, 1, // 19219: switch Inst[13] { |
| 8423 | 0, 5, // 19222: case 0x0: { |
| 8424 | OPC_Decode, 211, 7, 254, 1, // 19224: decode to A2_paddf using decoder 254 |
| 8425 | // 19224: } |
| 8426 | 1, 0, // 19229: case 0x1: { |
| 8427 | OPC_Decode, 212, 7, 254, 1, // 19231: decode to A2_paddfnew using decoder 254 |
| 8428 | // 19231: } |
| 8429 | // 19231: } // switch Inst[13] |
| 8430 | // 19231: } |
| 8431 | // 19231: } // switch Inst[7] |
| 8432 | // 19231: } |
| 8433 | 89, 41, // 19236: case 0x59: { |
| 8434 | OPC_SwitchField, 7, 1, // 19238: switch Inst[7] { |
| 8435 | 0, 17, // 19241: case 0x0: { |
| 8436 | OPC_SwitchField, 13, 1, // 19243: switch Inst[13] { |
| 8437 | 0, 5, // 19246: case 0x0: { |
| 8438 | OPC_Decode, 229, 7, 129, 2, // 19248: decode to A2_psubt using decoder 257 |
| 8439 | // 19248: } |
| 8440 | 1, 0, // 19253: case 0x1: { |
| 8441 | OPC_Decode, 230, 7, 129, 2, // 19255: decode to A2_psubtnew using decoder 257 |
| 8442 | // 19255: } |
| 8443 | // 19255: } // switch Inst[13] |
| 8444 | // 19255: } |
| 8445 | 1, 0, // 19260: case 0x1: { |
| 8446 | OPC_SwitchField, 13, 1, // 19262: switch Inst[13] { |
| 8447 | 0, 5, // 19265: case 0x0: { |
| 8448 | OPC_Decode, 227, 7, 129, 2, // 19267: decode to A2_psubf using decoder 257 |
| 8449 | // 19267: } |
| 8450 | 1, 0, // 19272: case 0x1: { |
| 8451 | OPC_Decode, 228, 7, 129, 2, // 19274: decode to A2_psubfnew using decoder 257 |
| 8452 | // 19274: } |
| 8453 | // 19274: } // switch Inst[13] |
| 8454 | // 19274: } |
| 8455 | // 19274: } // switch Inst[7] |
| 8456 | // 19274: } |
| 8457 | 104, 0, // 19279: case 0x68: { |
| 8458 | OPC_SwitchField, 7, 1, // 19281: switch Inst[7] { |
| 8459 | 0, 17, // 19284: case 0x0: { |
| 8460 | OPC_SwitchField, 13, 1, // 19286: switch Inst[13] { |
| 8461 | 0, 5, // 19289: case 0x0: { |
| 8462 | OPC_Decode, 185, 9, 130, 2, // 19291: decode to C2_ccombinewt using decoder 258 |
| 8463 | // 19291: } |
| 8464 | 1, 0, // 19296: case 0x1: { |
| 8465 | OPC_Decode, 184, 9, 130, 2, // 19298: decode to C2_ccombinewnewt using decoder 258 |
| 8466 | // 19298: } |
| 8467 | // 19298: } // switch Inst[13] |
| 8468 | // 19298: } |
| 8469 | 1, 0, // 19303: case 0x1: { |
| 8470 | OPC_SwitchField, 13, 1, // 19305: switch Inst[13] { |
| 8471 | 0, 5, // 19308: case 0x0: { |
| 8472 | OPC_Decode, 182, 9, 130, 2, // 19310: decode to C2_ccombinewf using decoder 258 |
| 8473 | // 19310: } |
| 8474 | 1, 0, // 19315: case 0x1: { |
| 8475 | OPC_Decode, 183, 9, 130, 2, // 19317: decode to C2_ccombinewnewf using decoder 258 |
| 8476 | // 19317: } |
| 8477 | // 19317: } // switch Inst[13] |
| 8478 | // 19317: } |
| 8479 | // 19317: } // switch Inst[7] |
| 8480 | // 19317: } |
| 8481 | // 19317: } // switch Inst[27:21] |
| 8482 | // 19317: } |
| 8483 | // 19317: } // switch Inst[31:28] |
| 8484 | }; |
| 8485 | static const uint8_t DecoderTableEXT_mmvec32[8767] = { |
| 8486 | OPC_SwitchField, 24, 8, // 0: switch Inst[31:24] { |
| 8487 | 24, 114, // 3: case 0x18: { |
| 8488 | OPC_SwitchField, 5, 3, // 5: switch Inst[7:5] { |
| 8489 | 0, 11, // 8: case 0x0: { |
| 8490 | OPC_CheckPredicate, 12, // 10: check predicate 12 |
| 8491 | OPC_CheckField, 13, 1, 0, // 12: check Inst[13] == 0x0 |
| 8492 | OPC_Decode, 181, 22, 131, 2, // 16: decode to V6_vasrhbsat using decoder 259 |
| 8493 | // 16: } |
| 8494 | 1, 11, // 21: case 0x1: { |
| 8495 | OPC_CheckPredicate, 12, // 23: check predicate 12 |
| 8496 | OPC_CheckField, 13, 1, 0, // 25: check Inst[13] == 0x0 |
| 8497 | OPC_Decode, 187, 22, 131, 2, // 29: decode to V6_vasruwuhrndsat using decoder 259 |
| 8498 | // 29: } |
| 8499 | 2, 11, // 34: case 0x2: { |
| 8500 | OPC_CheckPredicate, 12, // 36: check predicate 12 |
| 8501 | OPC_CheckField, 13, 1, 0, // 38: check Inst[13] == 0x0 |
| 8502 | OPC_Decode, 198, 22, 131, 2, // 42: decode to V6_vasrwuhrndsat using decoder 259 |
| 8503 | // 42: } |
| 8504 | 3, 11, // 47: case 0x3: { |
| 8505 | OPC_CheckPredicate, 12, // 49: check predicate 12 |
| 8506 | OPC_CheckField, 13, 1, 0, // 51: check Inst[13] == 0x0 |
| 8507 | OPC_Decode, 241, 23, 131, 2, // 55: decode to V6_vlutvvb_nm using decoder 259 |
| 8508 | // 55: } |
| 8509 | 4, 21, // 60: case 0x4: { |
| 8510 | OPC_SwitchField, 13, 1, // 62: switch Inst[13] { |
| 8511 | 0, 7, // 65: case 0x0: { |
| 8512 | OPC_CheckPredicate, 12, // 67: check predicate 12 |
| 8513 | OPC_Decode, 246, 23, 132, 2, // 69: decode to V6_vlutvwh_nm using decoder 260 |
| 8514 | // 69: } |
| 8515 | 1, 0, // 74: case 0x1: { |
| 8516 | OPC_CheckPredicate, 13, // 76: check predicate 13 |
| 8517 | OPC_Decode, 188, 22, 131, 2, // 78: decode to V6_vasruwuhsat using decoder 259 |
| 8518 | // 78: } |
| 8519 | // 78: } // switch Inst[13] |
| 8520 | // 78: } |
| 8521 | 5, 21, // 83: case 0x5: { |
| 8522 | OPC_SwitchField, 13, 1, // 85: switch Inst[13] { |
| 8523 | 0, 7, // 88: case 0x0: { |
| 8524 | OPC_CheckPredicate, 14, // 90: check predicate 14 |
| 8525 | OPC_Decode, 159, 22, 131, 2, // 92: decode to V6_valign4 using decoder 259 |
| 8526 | // 92: } |
| 8527 | 1, 0, // 97: case 0x1: { |
| 8528 | OPC_CheckPredicate, 13, // 99: check predicate 13 |
| 8529 | OPC_Decode, 186, 22, 131, 2, // 101: decode to V6_vasruhubsat using decoder 259 |
| 8530 | // 101: } |
| 8531 | // 101: } // switch Inst[13] |
| 8532 | // 101: } |
| 8533 | 7, 0, // 106: case 0x7: { |
| 8534 | OPC_CheckPredicate, 13, // 108: check predicate 13 |
| 8535 | OPC_CheckField, 13, 1, 0, // 110: check Inst[13] == 0x0 |
| 8536 | OPC_Decode, 185, 22, 131, 2, // 114: decode to V6_vasruhubrndsat using decoder 259 |
| 8537 | // 114: } |
| 8538 | // 114: } // switch Inst[7:5] |
| 8539 | // 114: } |
| 8540 | 25, 243, 11, // 119: case 0x19: { |
| 8541 | OPC_SwitchField, 21, 3, // 122: switch Inst[23:21] { |
| 8542 | 0, 187, 1, // 125: case 0x0: { |
| 8543 | OPC_SwitchField, 5, 3, // 128: switch Inst[7:5] { |
| 8544 | 0, 21, // 131: case 0x0: { |
| 8545 | OPC_SwitchField, 13, 1, // 133: switch Inst[13] { |
| 8546 | 0, 7, // 136: case 0x0: { |
| 8547 | OPC_CheckPredicate, 15, // 138: check predicate 15 |
| 8548 | OPC_Decode, 238, 25, 133, 2, // 140: decode to V6_vtmpyb using decoder 261 |
| 8549 | // 140: } |
| 8550 | 1, 0, // 145: case 0x1: { |
| 8551 | OPC_CheckPredicate, 15, // 147: check predicate 15 |
| 8552 | OPC_Decode, 239, 25, 134, 2, // 149: decode to V6_vtmpyb_acc using decoder 262 |
| 8553 | // 149: } |
| 8554 | // 149: } // switch Inst[13] |
| 8555 | // 149: } |
| 8556 | 1, 21, // 154: case 0x1: { |
| 8557 | OPC_SwitchField, 13, 1, // 156: switch Inst[13] { |
| 8558 | 0, 7, // 159: case 0x0: { |
| 8559 | OPC_CheckPredicate, 15, // 161: check predicate 15 |
| 8560 | OPC_Decode, 240, 25, 133, 2, // 163: decode to V6_vtmpybus using decoder 261 |
| 8561 | // 163: } |
| 8562 | 1, 0, // 168: case 0x1: { |
| 8563 | OPC_CheckPredicate, 15, // 170: check predicate 15 |
| 8564 | OPC_Decode, 241, 25, 134, 2, // 172: decode to V6_vtmpybus_acc using decoder 262 |
| 8565 | // 172: } |
| 8566 | // 172: } // switch Inst[13] |
| 8567 | // 172: } |
| 8568 | 2, 21, // 177: case 0x2: { |
| 8569 | OPC_SwitchField, 13, 1, // 179: switch Inst[13] { |
| 8570 | 0, 7, // 182: case 0x0: { |
| 8571 | OPC_CheckPredicate, 15, // 184: check predicate 15 |
| 8572 | OPC_Decode, 138, 23, 135, 2, // 186: decode to V6_vdmpyhb using decoder 263 |
| 8573 | // 186: } |
| 8574 | 1, 0, // 191: case 0x1: { |
| 8575 | OPC_CheckPredicate, 15, // 193: check predicate 15 |
| 8576 | OPC_Decode, 243, 25, 134, 2, // 195: decode to V6_vtmpyhb_acc using decoder 262 |
| 8577 | // 195: } |
| 8578 | // 195: } // switch Inst[13] |
| 8579 | // 195: } |
| 8580 | 3, 21, // 200: case 0x3: { |
| 8581 | OPC_SwitchField, 13, 1, // 202: switch Inst[13] { |
| 8582 | 0, 7, // 205: case 0x0: { |
| 8583 | OPC_CheckPredicate, 15, // 207: check predicate 15 |
| 8584 | OPC_Decode, 131, 25, 135, 2, // 209: decode to V6_vrmpyub using decoder 263 |
| 8585 | // 209: } |
| 8586 | 1, 0, // 214: case 0x1: { |
| 8587 | OPC_CheckPredicate, 15, // 216: check predicate 15 |
| 8588 | OPC_Decode, 139, 23, 136, 2, // 218: decode to V6_vdmpyhb_acc using decoder 264 |
| 8589 | // 218: } |
| 8590 | // 218: } // switch Inst[13] |
| 8591 | // 218: } |
| 8592 | 4, 21, // 223: case 0x4: { |
| 8593 | OPC_SwitchField, 13, 1, // 225: switch Inst[13] { |
| 8594 | 0, 7, // 228: case 0x0: { |
| 8595 | OPC_CheckPredicate, 15, // 230: check predicate 15 |
| 8596 | OPC_Decode, 251, 24, 135, 2, // 232: decode to V6_vrmpybus using decoder 263 |
| 8597 | // 232: } |
| 8598 | 1, 0, // 237: case 0x1: { |
| 8599 | OPC_CheckPredicate, 15, // 239: check predicate 15 |
| 8600 | OPC_Decode, 132, 25, 136, 2, // 241: decode to V6_vrmpyub_acc using decoder 264 |
| 8601 | // 241: } |
| 8602 | // 241: } // switch Inst[13] |
| 8603 | // 241: } |
| 8604 | 5, 21, // 246: case 0x5: { |
| 8605 | OPC_SwitchField, 13, 1, // 248: switch Inst[13] { |
| 8606 | 0, 7, // 251: case 0x0: { |
| 8607 | OPC_CheckPredicate, 15, // 253: check predicate 15 |
| 8608 | OPC_Decode, 152, 23, 133, 2, // 255: decode to V6_vdsaduh using decoder 261 |
| 8609 | // 255: } |
| 8610 | 1, 0, // 260: case 0x1: { |
| 8611 | OPC_CheckPredicate, 15, // 262: check predicate 15 |
| 8612 | OPC_Decode, 252, 24, 136, 2, // 264: decode to V6_vrmpybus_acc using decoder 264 |
| 8613 | // 264: } |
| 8614 | // 264: } // switch Inst[13] |
| 8615 | // 264: } |
| 8616 | 6, 21, // 269: case 0x6: { |
| 8617 | OPC_SwitchField, 13, 1, // 271: switch Inst[13] { |
| 8618 | 0, 7, // 274: case 0x0: { |
| 8619 | OPC_CheckPredicate, 15, // 276: check predicate 15 |
| 8620 | OPC_Decode, 134, 23, 135, 2, // 278: decode to V6_vdmpybus using decoder 263 |
| 8621 | // 278: } |
| 8622 | 1, 0, // 283: case 0x1: { |
| 8623 | OPC_CheckPredicate, 15, // 285: check predicate 15 |
| 8624 | OPC_Decode, 135, 23, 136, 2, // 287: decode to V6_vdmpybus_acc using decoder 264 |
| 8625 | // 287: } |
| 8626 | // 287: } // switch Inst[13] |
| 8627 | // 287: } |
| 8628 | 7, 0, // 292: case 0x7: { |
| 8629 | OPC_SwitchField, 13, 1, // 294: switch Inst[13] { |
| 8630 | 0, 7, // 297: case 0x0: { |
| 8631 | OPC_CheckPredicate, 15, // 299: check predicate 15 |
| 8632 | OPC_Decode, 136, 23, 133, 2, // 301: decode to V6_vdmpybus_dv using decoder 261 |
| 8633 | // 301: } |
| 8634 | 1, 0, // 306: case 0x1: { |
| 8635 | OPC_CheckPredicate, 15, // 308: check predicate 15 |
| 8636 | OPC_Decode, 137, 23, 134, 2, // 310: decode to V6_vdmpybus_dv_acc using decoder 262 |
| 8637 | // 310: } |
| 8638 | // 310: } // switch Inst[13] |
| 8639 | // 310: } |
| 8640 | // 310: } // switch Inst[7:5] |
| 8641 | // 310: } |
| 8642 | 1, 187, 1, // 315: case 0x1: { |
| 8643 | OPC_SwitchField, 5, 3, // 318: switch Inst[7:5] { |
| 8644 | 0, 21, // 321: case 0x0: { |
| 8645 | OPC_SwitchField, 13, 1, // 323: switch Inst[13] { |
| 8646 | 0, 7, // 326: case 0x0: { |
| 8647 | OPC_CheckPredicate, 15, // 328: check predicate 15 |
| 8648 | OPC_Decode, 148, 23, 135, 2, // 330: decode to V6_vdmpyhsusat using decoder 263 |
| 8649 | // 330: } |
| 8650 | 1, 0, // 335: case 0x1: { |
| 8651 | OPC_CheckPredicate, 15, // 337: check predicate 15 |
| 8652 | OPC_Decode, 149, 23, 136, 2, // 339: decode to V6_vdmpyhsusat_acc using decoder 264 |
| 8653 | // 339: } |
| 8654 | // 339: } // switch Inst[13] |
| 8655 | // 339: } |
| 8656 | 1, 21, // 344: case 0x1: { |
| 8657 | OPC_SwitchField, 13, 1, // 346: switch Inst[13] { |
| 8658 | 0, 7, // 349: case 0x0: { |
| 8659 | OPC_CheckPredicate, 15, // 351: check predicate 15 |
| 8660 | OPC_Decode, 146, 23, 137, 2, // 353: decode to V6_vdmpyhsuisat using decoder 265 |
| 8661 | // 353: } |
| 8662 | 1, 0, // 358: case 0x1: { |
| 8663 | OPC_CheckPredicate, 15, // 360: check predicate 15 |
| 8664 | OPC_Decode, 147, 23, 138, 2, // 362: decode to V6_vdmpyhsuisat_acc using decoder 266 |
| 8665 | // 362: } |
| 8666 | // 362: } // switch Inst[13] |
| 8667 | // 362: } |
| 8668 | 2, 21, // 367: case 0x2: { |
| 8669 | OPC_SwitchField, 13, 1, // 369: switch Inst[13] { |
| 8670 | 0, 7, // 372: case 0x0: { |
| 8671 | OPC_CheckPredicate, 15, // 374: check predicate 15 |
| 8672 | OPC_Decode, 144, 23, 135, 2, // 376: decode to V6_vdmpyhsat using decoder 263 |
| 8673 | // 376: } |
| 8674 | 1, 0, // 381: case 0x1: { |
| 8675 | OPC_CheckPredicate, 15, // 383: check predicate 15 |
| 8676 | OPC_Decode, 143, 23, 138, 2, // 385: decode to V6_vdmpyhisat_acc using decoder 266 |
| 8677 | // 385: } |
| 8678 | // 385: } // switch Inst[13] |
| 8679 | // 385: } |
| 8680 | 3, 21, // 390: case 0x3: { |
| 8681 | OPC_SwitchField, 13, 1, // 392: switch Inst[13] { |
| 8682 | 0, 7, // 395: case 0x0: { |
| 8683 | OPC_CheckPredicate, 15, // 397: check predicate 15 |
| 8684 | OPC_Decode, 142, 23, 137, 2, // 399: decode to V6_vdmpyhisat using decoder 265 |
| 8685 | // 399: } |
| 8686 | 1, 0, // 404: case 0x1: { |
| 8687 | OPC_CheckPredicate, 15, // 406: check predicate 15 |
| 8688 | OPC_Decode, 145, 23, 136, 2, // 408: decode to V6_vdmpyhsat_acc using decoder 264 |
| 8689 | // 408: } |
| 8690 | // 408: } // switch Inst[13] |
| 8691 | // 408: } |
| 8692 | 4, 21, // 413: case 0x4: { |
| 8693 | OPC_SwitchField, 13, 1, // 415: switch Inst[13] { |
| 8694 | 0, 7, // 418: case 0x0: { |
| 8695 | OPC_CheckPredicate, 15, // 420: check predicate 15 |
| 8696 | OPC_Decode, 140, 23, 133, 2, // 422: decode to V6_vdmpyhb_dv using decoder 261 |
| 8697 | // 422: } |
| 8698 | 1, 0, // 427: case 0x1: { |
| 8699 | OPC_CheckPredicate, 15, // 429: check predicate 15 |
| 8700 | OPC_Decode, 141, 23, 134, 2, // 431: decode to V6_vdmpyhb_dv_acc using decoder 262 |
| 8701 | // 431: } |
| 8702 | // 431: } // switch Inst[13] |
| 8703 | // 431: } |
| 8704 | 5, 21, // 436: case 0x5: { |
| 8705 | OPC_SwitchField, 13, 1, // 438: switch Inst[13] { |
| 8706 | 0, 7, // 441: case 0x0: { |
| 8707 | OPC_CheckPredicate, 15, // 443: check predicate 15 |
| 8708 | OPC_Decode, 172, 24, 139, 2, // 445: decode to V6_vmpybus using decoder 267 |
| 8709 | // 445: } |
| 8710 | 1, 0, // 450: case 0x1: { |
| 8711 | OPC_CheckPredicate, 15, // 452: check predicate 15 |
| 8712 | OPC_Decode, 173, 24, 140, 2, // 454: decode to V6_vmpybus_acc using decoder 268 |
| 8713 | // 454: } |
| 8714 | // 454: } // switch Inst[13] |
| 8715 | // 454: } |
| 8716 | 6, 21, // 459: case 0x6: { |
| 8717 | OPC_SwitchField, 13, 1, // 461: switch Inst[13] { |
| 8718 | 0, 7, // 464: case 0x0: { |
| 8719 | OPC_CheckPredicate, 15, // 466: check predicate 15 |
| 8720 | OPC_Decode, 139, 24, 133, 2, // 468: decode to V6_vmpabus using decoder 261 |
| 8721 | // 468: } |
| 8722 | 1, 0, // 473: case 0x1: { |
| 8723 | OPC_CheckPredicate, 15, // 475: check predicate 15 |
| 8724 | OPC_Decode, 140, 24, 134, 2, // 477: decode to V6_vmpabus_acc using decoder 262 |
| 8725 | // 477: } |
| 8726 | // 477: } // switch Inst[13] |
| 8727 | // 477: } |
| 8728 | 7, 0, // 482: case 0x7: { |
| 8729 | OPC_SwitchField, 13, 1, // 484: switch Inst[13] { |
| 8730 | 0, 7, // 487: case 0x0: { |
| 8731 | OPC_CheckPredicate, 15, // 489: check predicate 15 |
| 8732 | OPC_Decode, 145, 24, 133, 2, // 491: decode to V6_vmpahb using decoder 261 |
| 8733 | // 491: } |
| 8734 | 1, 0, // 496: case 0x1: { |
| 8735 | OPC_CheckPredicate, 15, // 498: check predicate 15 |
| 8736 | OPC_Decode, 146, 24, 134, 2, // 500: decode to V6_vmpahb_acc using decoder 262 |
| 8737 | // 500: } |
| 8738 | // 500: } // switch Inst[13] |
| 8739 | // 500: } |
| 8740 | // 500: } // switch Inst[7:5] |
| 8741 | // 500: } |
| 8742 | 2, 151, 1, // 505: case 0x2: { |
| 8743 | OPC_SwitchField, 6, 2, // 508: switch Inst[7:6] { |
| 8744 | 0, 49, // 511: case 0x0: { |
| 8745 | OPC_SwitchField, 5, 1, // 513: switch Inst[5] { |
| 8746 | 0, 21, // 516: case 0x0: { |
| 8747 | OPC_SwitchField, 13, 1, // 518: switch Inst[13] { |
| 8748 | 0, 7, // 521: case 0x0: { |
| 8749 | OPC_CheckPredicate, 15, // 523: check predicate 15 |
| 8750 | OPC_Decode, 180, 24, 139, 2, // 525: decode to V6_vmpyh using decoder 267 |
| 8751 | // 525: } |
| 8752 | 1, 0, // 530: case 0x1: { |
| 8753 | OPC_CheckPredicate, 15, // 532: check predicate 15 |
| 8754 | OPC_Decode, 182, 24, 140, 2, // 534: decode to V6_vmpyhsat_acc using decoder 268 |
| 8755 | // 534: } |
| 8756 | // 534: } // switch Inst[13] |
| 8757 | // 534: } |
| 8758 | 1, 0, // 539: case 0x1: { |
| 8759 | OPC_SwitchField, 13, 1, // 541: switch Inst[13] { |
| 8760 | 0, 7, // 544: case 0x0: { |
| 8761 | OPC_CheckPredicate, 15, // 546: check predicate 15 |
| 8762 | OPC_Decode, 184, 24, 135, 2, // 548: decode to V6_vmpyhss using decoder 263 |
| 8763 | // 548: } |
| 8764 | 1, 0, // 553: case 0x1: { |
| 8765 | OPC_CheckPredicate, 15, // 555: check predicate 15 |
| 8766 | OPC_Decode, 215, 24, 140, 2, // 557: decode to V6_vmpyuh_acc using decoder 268 |
| 8767 | // 557: } |
| 8768 | // 557: } // switch Inst[13] |
| 8769 | // 557: } |
| 8770 | // 557: } // switch Inst[5] |
| 8771 | // 557: } |
| 8772 | 1, 49, // 562: case 0x1: { |
| 8773 | OPC_SwitchField, 5, 1, // 564: switch Inst[5] { |
| 8774 | 0, 21, // 567: case 0x0: { |
| 8775 | OPC_SwitchField, 13, 1, // 569: switch Inst[13] { |
| 8776 | 0, 7, // 572: case 0x0: { |
| 8777 | OPC_CheckPredicate, 15, // 574: check predicate 15 |
| 8778 | OPC_Decode, 183, 24, 135, 2, // 576: decode to V6_vmpyhsrs using decoder 263 |
| 8779 | // 576: } |
| 8780 | 1, 0, // 581: case 0x1: { |
| 8781 | OPC_CheckPredicate, 15, // 583: check predicate 15 |
| 8782 | OPC_Decode, 200, 24, 136, 2, // 585: decode to V6_vmpyiwb_acc using decoder 264 |
| 8783 | // 585: } |
| 8784 | // 585: } // switch Inst[13] |
| 8785 | // 585: } |
| 8786 | 1, 0, // 590: case 0x1: { |
| 8787 | OPC_SwitchField, 13, 1, // 592: switch Inst[13] { |
| 8788 | 0, 7, // 595: case 0x0: { |
| 8789 | OPC_CheckPredicate, 15, // 597: check predicate 15 |
| 8790 | OPC_Decode, 214, 24, 139, 2, // 599: decode to V6_vmpyuh using decoder 267 |
| 8791 | // 599: } |
| 8792 | 1, 0, // 604: case 0x1: { |
| 8793 | OPC_CheckPredicate, 15, // 606: check predicate 15 |
| 8794 | OPC_Decode, 202, 24, 136, 2, // 608: decode to V6_vmpyiwh_acc using decoder 264 |
| 8795 | // 608: } |
| 8796 | // 608: } // switch Inst[13] |
| 8797 | // 608: } |
| 8798 | // 608: } // switch Inst[5] |
| 8799 | // 608: } |
| 8800 | 2, 21, // 613: case 0x2: { |
| 8801 | OPC_SwitchField, 13, 1, // 615: switch Inst[13] { |
| 8802 | 0, 7, // 618: case 0x0: { |
| 8803 | OPC_CheckPredicate, 15, // 620: check predicate 15 |
| 8804 | OPC_Decode, 253, 24, 141, 2, // 622: decode to V6_vrmpybusi using decoder 269 |
| 8805 | // 622: } |
| 8806 | 1, 0, // 627: case 0x1: { |
| 8807 | OPC_CheckPredicate, 15, // 629: check predicate 15 |
| 8808 | OPC_Decode, 254, 24, 142, 2, // 631: decode to V6_vrmpybusi_acc using decoder 270 |
| 8809 | // 631: } |
| 8810 | // 631: } // switch Inst[13] |
| 8811 | // 631: } |
| 8812 | 3, 0, // 636: case 0x3: { |
| 8813 | OPC_SwitchField, 13, 1, // 638: switch Inst[13] { |
| 8814 | 0, 7, // 641: case 0x0: { |
| 8815 | OPC_CheckPredicate, 15, // 643: check predicate 15 |
| 8816 | OPC_Decode, 167, 25, 141, 2, // 645: decode to V6_vrsadubi using decoder 269 |
| 8817 | // 645: } |
| 8818 | 1, 0, // 650: case 0x1: { |
| 8819 | OPC_CheckPredicate, 15, // 652: check predicate 15 |
| 8820 | OPC_Decode, 168, 25, 142, 2, // 654: decode to V6_vrsadubi_acc using decoder 270 |
| 8821 | // 654: } |
| 8822 | // 654: } // switch Inst[13] |
| 8823 | // 654: } |
| 8824 | // 654: } // switch Inst[7:6] |
| 8825 | // 654: } |
| 8826 | 3, 211, 1, // 659: case 0x3: { |
| 8827 | OPC_SwitchField, 6, 2, // 662: switch Inst[7:6] { |
| 8828 | 0, 49, // 665: case 0x0: { |
| 8829 | OPC_SwitchField, 5, 1, // 667: switch Inst[5] { |
| 8830 | 0, 21, // 670: case 0x0: { |
| 8831 | OPC_SwitchField, 13, 1, // 672: switch Inst[13] { |
| 8832 | 0, 7, // 675: case 0x0: { |
| 8833 | OPC_CheckPredicate, 15, // 677: check predicate 15 |
| 8834 | OPC_Decode, 196, 24, 135, 2, // 679: decode to V6_vmpyihb using decoder 263 |
| 8835 | // 679: } |
| 8836 | 1, 0, // 684: case 0x1: { |
| 8837 | OPC_CheckPredicate, 15, // 686: check predicate 15 |
| 8838 | OPC_Decode, 153, 23, 134, 2, // 688: decode to V6_vdsaduh_acc using decoder 262 |
| 8839 | // 688: } |
| 8840 | // 688: } // switch Inst[13] |
| 8841 | // 688: } |
| 8842 | 1, 0, // 693: case 0x1: { |
| 8843 | OPC_SwitchField, 13, 1, // 695: switch Inst[13] { |
| 8844 | 0, 7, // 698: case 0x0: { |
| 8845 | OPC_CheckPredicate, 15, // 700: check predicate 15 |
| 8846 | OPC_Decode, 159, 25, 135, 2, // 702: decode to V6_vror using decoder 263 |
| 8847 | // 702: } |
| 8848 | 1, 0, // 707: case 0x1: { |
| 8849 | OPC_CheckPredicate, 15, // 709: check predicate 15 |
| 8850 | OPC_Decode, 197, 24, 136, 2, // 711: decode to V6_vmpyihb_acc using decoder 264 |
| 8851 | // 711: } |
| 8852 | // 711: } // switch Inst[13] |
| 8853 | // 711: } |
| 8854 | // 711: } // switch Inst[5] |
| 8855 | // 711: } |
| 8856 | 1, 63, // 716: case 0x1: { |
| 8857 | OPC_SwitchField, 5, 1, // 718: switch Inst[5] { |
| 8858 | 0, 21, // 721: case 0x0: { |
| 8859 | OPC_SwitchField, 13, 1, // 723: switch Inst[13] { |
| 8860 | 0, 7, // 726: case 0x0: { |
| 8861 | OPC_CheckPredicate, 13, // 728: check predicate 13 |
| 8862 | OPC_Decode, 216, 24, 135, 2, // 730: decode to V6_vmpyuhe using decoder 263 |
| 8863 | // 730: } |
| 8864 | 1, 0, // 735: case 0x1: { |
| 8865 | OPC_CheckPredicate, 15, // 737: check predicate 15 |
| 8866 | OPC_Decode, 175, 22, 136, 2, // 739: decode to V6_vaslw_acc using decoder 264 |
| 8867 | // 739: } |
| 8868 | // 739: } // switch Inst[13] |
| 8869 | // 739: } |
| 8870 | 1, 0, // 744: case 0x1: { |
| 8871 | OPC_SwitchField, 13, 1, // 746: switch Inst[13] { |
| 8872 | 0, 7, // 749: case 0x0: { |
| 8873 | OPC_CheckPredicate, 13, // 751: check predicate 13 |
| 8874 | OPC_Decode, 142, 24, 133, 2, // 753: decode to V6_vmpabuu using decoder 261 |
| 8875 | // 753: } |
| 8876 | 1, 0, // 758: case 0x1: { |
| 8877 | OPC_SwitchField, 10, 3, // 760: switch Inst[12:10] { |
| 8878 | 0, 7, // 763: case 0x0: { |
| 8879 | OPC_CheckPredicate, 15, // 765: check predicate 15 |
| 8880 | OPC_Decode, 166, 22, 143, 2, // 767: decode to V6_vandqrt_acc using decoder 271 |
| 8881 | // 767: } |
| 8882 | 1, 0, // 772: case 0x1: { |
| 8883 | OPC_CheckPredicate, 12, // 774: check predicate 12 |
| 8884 | OPC_Decode, 164, 22, 143, 2, // 776: decode to V6_vandnqrt_acc using decoder 271 |
| 8885 | // 776: } |
| 8886 | // 776: } // switch Inst[12:10] |
| 8887 | // 776: } |
| 8888 | // 776: } // switch Inst[13] |
| 8889 | // 776: } |
| 8890 | // 776: } // switch Inst[5] |
| 8891 | // 776: } |
| 8892 | 2, 53, // 781: case 0x2: { |
| 8893 | OPC_SwitchField, 5, 1, // 783: switch Inst[5] { |
| 8894 | 0, 25, // 786: case 0x0: { |
| 8895 | OPC_SwitchField, 13, 1, // 788: switch Inst[13] { |
| 8896 | 0, 7, // 791: case 0x0: { |
| 8897 | OPC_CheckPredicate, 13, // 793: check predicate 13 |
| 8898 | OPC_Decode, 239, 23, 144, 2, // 795: decode to V6_vlut4 using decoder 272 |
| 8899 | // 795: } |
| 8900 | 1, 0, // 800: case 0x1: { |
| 8901 | OPC_CheckPredicate, 15, // 802: check predicate 15 |
| 8902 | OPC_CheckField, 2, 3, 0, // 804: check Inst[4:2] == 0x0 |
| 8903 | OPC_Decode, 170, 22, 145, 2, // 808: decode to V6_vandvrt_acc using decoder 273 |
| 8904 | // 808: } |
| 8905 | // 808: } // switch Inst[13] |
| 8906 | // 808: } |
| 8907 | 1, 0, // 813: case 0x1: { |
| 8908 | OPC_SwitchField, 13, 1, // 815: switch Inst[13] { |
| 8909 | 0, 7, // 818: case 0x0: { |
| 8910 | OPC_CheckPredicate, 15, // 820: check predicate 15 |
| 8911 | OPC_Decode, 193, 22, 135, 2, // 822: decode to V6_vasrw using decoder 263 |
| 8912 | // 822: } |
| 8913 | 1, 0, // 827: case 0x1: { |
| 8914 | OPC_CheckPredicate, 15, // 829: check predicate 15 |
| 8915 | OPC_Decode, 194, 22, 136, 2, // 831: decode to V6_vasrw_acc using decoder 264 |
| 8916 | // 831: } |
| 8917 | // 831: } // switch Inst[13] |
| 8918 | // 831: } |
| 8919 | // 831: } // switch Inst[5] |
| 8920 | // 831: } |
| 8921 | 3, 0, // 836: case 0x3: { |
| 8922 | OPC_SwitchField, 13, 1, // 838: switch Inst[13] { |
| 8923 | 0, 21, // 841: case 0x0: { |
| 8924 | OPC_SwitchField, 5, 1, // 843: switch Inst[5] { |
| 8925 | 0, 7, // 846: case 0x0: { |
| 8926 | OPC_CheckPredicate, 15, // 848: check predicate 15 |
| 8927 | OPC_Decode, 178, 22, 135, 2, // 850: decode to V6_vasrh using decoder 263 |
| 8928 | // 850: } |
| 8929 | 1, 0, // 855: case 0x1: { |
| 8930 | OPC_CheckPredicate, 15, // 857: check predicate 15 |
| 8931 | OPC_Decode, 174, 22, 135, 2, // 859: decode to V6_vaslw using decoder 263 |
| 8932 | // 859: } |
| 8933 | // 859: } // switch Inst[5] |
| 8934 | // 859: } |
| 8935 | 1, 0, // 864: case 0x1: { |
| 8936 | OPC_CheckPredicate, 15, // 866: check predicate 15 |
| 8937 | OPC_Decode, 136, 25, 142, 2, // 868: decode to V6_vrmpyubi_acc using decoder 270 |
| 8938 | // 868: } |
| 8939 | // 868: } // switch Inst[13] |
| 8940 | // 868: } |
| 8941 | // 868: } // switch Inst[7:6] |
| 8942 | // 868: } |
| 8943 | 4, 177, 1, // 873: case 0x4: { |
| 8944 | OPC_SwitchField, 5, 3, // 876: switch Inst[7:5] { |
| 8945 | 0, 21, // 879: case 0x0: { |
| 8946 | OPC_SwitchField, 13, 1, // 881: switch Inst[13] { |
| 8947 | 0, 7, // 884: case 0x0: { |
| 8948 | OPC_CheckPredicate, 15, // 886: check predicate 15 |
| 8949 | OPC_Decode, 171, 22, 135, 2, // 888: decode to V6_vaslh using decoder 263 |
| 8950 | // 888: } |
| 8951 | 1, 0, // 893: case 0x1: { |
| 8952 | OPC_CheckPredicate, 15, // 895: check predicate 15 |
| 8953 | OPC_Decode, 211, 24, 140, 2, // 897: decode to V6_vmpyub_acc using decoder 268 |
| 8954 | // 897: } |
| 8955 | // 897: } // switch Inst[13] |
| 8956 | // 897: } |
| 8957 | 1, 21, // 902: case 0x1: { |
| 8958 | OPC_SwitchField, 13, 1, // 904: switch Inst[13] { |
| 8959 | 0, 7, // 907: case 0x0: { |
| 8960 | OPC_CheckPredicate, 15, // 909: check predicate 15 |
| 8961 | OPC_Decode, 237, 23, 135, 2, // 911: decode to V6_vlsrw using decoder 263 |
| 8962 | // 911: } |
| 8963 | 1, 0, // 916: case 0x1: { |
| 8964 | OPC_CheckPredicate, 12, // 918: check predicate 12 |
| 8965 | OPC_Decode, 204, 24, 136, 2, // 920: decode to V6_vmpyiwub_acc using decoder 264 |
| 8966 | // 920: } |
| 8967 | // 920: } // switch Inst[13] |
| 8968 | // 920: } |
| 8969 | 2, 21, // 925: case 0x2: { |
| 8970 | OPC_SwitchField, 13, 1, // 927: switch Inst[13] { |
| 8971 | 0, 7, // 930: case 0x0: { |
| 8972 | OPC_CheckPredicate, 15, // 932: check predicate 15 |
| 8973 | OPC_Decode, 235, 23, 135, 2, // 934: decode to V6_vlsrh using decoder 263 |
| 8974 | // 934: } |
| 8975 | 1, 0, // 939: case 0x1: { |
| 8976 | OPC_CheckPredicate, 12, // 941: check predicate 12 |
| 8977 | OPC_Decode, 149, 24, 134, 2, // 943: decode to V6_vmpauhb_acc using decoder 262 |
| 8978 | // 943: } |
| 8979 | // 943: } // switch Inst[13] |
| 8980 | // 943: } |
| 8981 | 3, 21, // 948: case 0x3: { |
| 8982 | OPC_SwitchField, 13, 1, // 950: switch Inst[13] { |
| 8983 | 0, 7, // 953: case 0x0: { |
| 8984 | OPC_CheckPredicate, 12, // 955: check predicate 12 |
| 8985 | OPC_Decode, 234, 23, 135, 2, // 957: decode to V6_vlsrb using decoder 263 |
| 8986 | // 957: } |
| 8987 | 1, 0, // 962: case 0x1: { |
| 8988 | OPC_CheckPredicate, 13, // 964: check predicate 13 |
| 8989 | OPC_Decode, 217, 24, 136, 2, // 966: decode to V6_vmpyuhe_acc using decoder 264 |
| 8990 | // 966: } |
| 8991 | // 966: } // switch Inst[13] |
| 8992 | // 966: } |
| 8993 | 4, 11, // 971: case 0x4: { |
| 8994 | OPC_CheckPredicate, 13, // 973: check predicate 13 |
| 8995 | OPC_CheckField, 13, 1, 1, // 975: check Inst[13] == 0x1 |
| 8996 | OPC_Decode, 147, 24, 146, 2, // 979: decode to V6_vmpahhsat using decoder 274 |
| 8997 | // 979: } |
| 8998 | 5, 21, // 984: case 0x5: { |
| 8999 | OPC_SwitchField, 13, 1, // 986: switch Inst[13] { |
| 9000 | 0, 7, // 989: case 0x0: { |
| 9001 | OPC_CheckPredicate, 12, // 991: check predicate 12 |
| 9002 | OPC_Decode, 148, 24, 133, 2, // 993: decode to V6_vmpauhb using decoder 261 |
| 9003 | // 993: } |
| 9004 | 1, 0, // 998: case 0x1: { |
| 9005 | OPC_CheckPredicate, 13, // 1000: check predicate 13 |
| 9006 | OPC_Decode, 150, 24, 146, 2, // 1002: decode to V6_vmpauhuhsat using decoder 274 |
| 9007 | // 1002: } |
| 9008 | // 1002: } // switch Inst[13] |
| 9009 | // 1002: } |
| 9010 | 6, 21, // 1007: case 0x6: { |
| 9011 | OPC_SwitchField, 13, 1, // 1009: switch Inst[13] { |
| 9012 | 0, 7, // 1012: case 0x0: { |
| 9013 | OPC_CheckPredicate, 12, // 1014: check predicate 12 |
| 9014 | OPC_Decode, 203, 24, 135, 2, // 1016: decode to V6_vmpyiwub using decoder 263 |
| 9015 | // 1016: } |
| 9016 | 1, 0, // 1021: case 0x1: { |
| 9017 | OPC_CheckPredicate, 13, // 1023: check predicate 13 |
| 9018 | OPC_Decode, 151, 24, 146, 2, // 1025: decode to V6_vmpsuhuhsat using decoder 274 |
| 9019 | // 1025: } |
| 9020 | // 1025: } // switch Inst[13] |
| 9021 | // 1025: } |
| 9022 | 7, 0, // 1030: case 0x7: { |
| 9023 | OPC_SwitchField, 13, 1, // 1032: switch Inst[13] { |
| 9024 | 0, 7, // 1035: case 0x0: { |
| 9025 | OPC_CheckPredicate, 15, // 1037: check predicate 15 |
| 9026 | OPC_Decode, 201, 24, 135, 2, // 1039: decode to V6_vmpyiwh using decoder 263 |
| 9027 | // 1039: } |
| 9028 | 1, 0, // 1044: case 0x1: { |
| 9029 | OPC_CheckPredicate, 13, // 1046: check predicate 13 |
| 9030 | OPC_Decode, 179, 22, 136, 2, // 1048: decode to V6_vasrh_acc using decoder 264 |
| 9031 | // 1048: } |
| 9032 | // 1048: } // switch Inst[13] |
| 9033 | // 1048: } |
| 9034 | // 1048: } // switch Inst[7:5] |
| 9035 | // 1048: } |
| 9036 | 5, 209, 1, // 1053: case 0x5: { |
| 9037 | OPC_SwitchField, 6, 2, // 1056: switch Inst[7:6] { |
| 9038 | 0, 58, // 1059: case 0x0: { |
| 9039 | OPC_SwitchField, 5, 1, // 1061: switch Inst[5] { |
| 9040 | 0, 21, // 1064: case 0x0: { |
| 9041 | OPC_SwitchField, 13, 1, // 1066: switch Inst[13] { |
| 9042 | 0, 7, // 1069: case 0x0: { |
| 9043 | OPC_CheckPredicate, 15, // 1071: check predicate 15 |
| 9044 | OPC_Decode, 199, 24, 135, 2, // 1073: decode to V6_vmpyiwb using decoder 263 |
| 9045 | // 1073: } |
| 9046 | 1, 0, // 1078: case 0x1: { |
| 9047 | OPC_CheckPredicate, 13, // 1080: check predicate 13 |
| 9048 | OPC_Decode, 250, 24, 147, 2, // 1082: decode to V6_vrmpybub_rtt_acc using decoder 275 |
| 9049 | // 1082: } |
| 9050 | // 1082: } // switch Inst[13] |
| 9051 | // 1082: } |
| 9052 | 1, 0, // 1087: case 0x1: { |
| 9053 | OPC_SwitchField, 8, 6, // 1089: switch Inst[13:8] { |
| 9054 | 0, 7, // 1092: case 0x0: { |
| 9055 | OPC_CheckPredicate, 15, // 1094: check predicate 15 |
| 9056 | OPC_Decode, 218, 20, 148, 2, // 1096: decode to V6_lvsplatw using decoder 276 |
| 9057 | // 1096: } |
| 9058 | 1, 7, // 1101: case 0x1: { |
| 9059 | OPC_CheckPredicate, 16, // 1103: check predicate 16 |
| 9060 | OPC_Decode, 139, 26, 148, 2, // 1105: decode to V6_zextract using decoder 276 |
| 9061 | // 1105: } |
| 9062 | 32, 0, // 1110: case 0x20: { |
| 9063 | OPC_CheckPredicate, 15, // 1112: check predicate 15 |
| 9064 | OPC_Decode, 231, 23, 149, 2, // 1114: decode to V6_vinsertwr using decoder 277 |
| 9065 | // 1114: } |
| 9066 | // 1114: } // switch Inst[13:8] |
| 9067 | // 1114: } |
| 9068 | // 1114: } // switch Inst[5] |
| 9069 | // 1114: } |
| 9070 | 1, 42, // 1119: case 0x1: { |
| 9071 | OPC_SwitchField, 2, 4, // 1121: switch Inst[5:2] { |
| 9072 | 1, 11, // 1124: case 0x1: { |
| 9073 | OPC_CheckPredicate, 15, // 1126: check predicate 15 |
| 9074 | OPC_CheckField, 8, 6, 0, // 1128: check Inst[13:8] == 0x0 |
| 9075 | OPC_Decode, 224, 20, 150, 2, // 1132: decode to V6_pred_scalar2 using decoder 278 |
| 9076 | // 1132: } |
| 9077 | 2, 11, // 1137: case 0x2: { |
| 9078 | OPC_CheckPredicate, 15, // 1139: check predicate 15 |
| 9079 | OPC_CheckField, 13, 1, 0, // 1141: check Inst[13] == 0x0 |
| 9080 | OPC_Decode, 169, 22, 151, 2, // 1145: decode to V6_vandvrt using decoder 279 |
| 9081 | // 1145: } |
| 9082 | 3, 0, // 1150: case 0x3: { |
| 9083 | OPC_CheckPredicate, 12, // 1152: check predicate 12 |
| 9084 | OPC_CheckField, 8, 6, 0, // 1154: check Inst[13:8] == 0x0 |
| 9085 | OPC_Decode, 225, 20, 150, 2, // 1158: decode to V6_pred_scalar2v2 using decoder 278 |
| 9086 | // 1158: } |
| 9087 | // 1158: } // switch Inst[5:2] |
| 9088 | // 1158: } |
| 9089 | 2, 63, // 1163: case 0x2: { |
| 9090 | OPC_SwitchField, 5, 1, // 1165: switch Inst[5] { |
| 9091 | 0, 21, // 1168: case 0x0: { |
| 9092 | OPC_SwitchField, 13, 1, // 1170: switch Inst[13] { |
| 9093 | 0, 7, // 1173: case 0x0: { |
| 9094 | OPC_CheckPredicate, 15, // 1175: check predicate 15 |
| 9095 | OPC_Decode, 242, 25, 133, 2, // 1177: decode to V6_vtmpyhb using decoder 261 |
| 9096 | // 1177: } |
| 9097 | 1, 0, // 1182: case 0x1: { |
| 9098 | OPC_CheckPredicate, 13, // 1184: check predicate 13 |
| 9099 | OPC_Decode, 143, 24, 134, 2, // 1186: decode to V6_vmpabuu_acc using decoder 262 |
| 9100 | // 1186: } |
| 9101 | // 1186: } // switch Inst[13] |
| 9102 | // 1186: } |
| 9103 | 1, 0, // 1191: case 0x1: { |
| 9104 | OPC_SwitchField, 13, 1, // 1193: switch Inst[13] { |
| 9105 | 0, 21, // 1196: case 0x0: { |
| 9106 | OPC_SwitchField, 10, 3, // 1198: switch Inst[12:10] { |
| 9107 | 0, 7, // 1201: case 0x0: { |
| 9108 | OPC_CheckPredicate, 15, // 1203: check predicate 15 |
| 9109 | OPC_Decode, 165, 22, 152, 2, // 1205: decode to V6_vandqrt using decoder 280 |
| 9110 | // 1205: } |
| 9111 | 1, 0, // 1210: case 0x1: { |
| 9112 | OPC_CheckPredicate, 12, // 1212: check predicate 12 |
| 9113 | OPC_Decode, 163, 22, 152, 2, // 1214: decode to V6_vandnqrt using decoder 280 |
| 9114 | // 1214: } |
| 9115 | // 1214: } // switch Inst[12:10] |
| 9116 | // 1214: } |
| 9117 | 1, 0, // 1219: case 0x1: { |
| 9118 | OPC_CheckPredicate, 13, // 1221: check predicate 13 |
| 9119 | OPC_Decode, 172, 22, 136, 2, // 1223: decode to V6_vaslh_acc using decoder 264 |
| 9120 | // 1223: } |
| 9121 | // 1223: } // switch Inst[13] |
| 9122 | // 1223: } |
| 9123 | // 1223: } // switch Inst[5] |
| 9124 | // 1223: } |
| 9125 | 3, 0, // 1228: case 0x3: { |
| 9126 | OPC_SwitchField, 13, 1, // 1230: switch Inst[13] { |
| 9127 | 0, 7, // 1233: case 0x0: { |
| 9128 | OPC_CheckPredicate, 15, // 1235: check predicate 15 |
| 9129 | OPC_Decode, 135, 25, 141, 2, // 1237: decode to V6_vrmpyubi using decoder 269 |
| 9130 | // 1237: } |
| 9131 | 1, 0, // 1242: case 0x1: { |
| 9132 | OPC_SwitchField, 5, 1, // 1244: switch Inst[5] { |
| 9133 | 0, 7, // 1247: case 0x0: { |
| 9134 | OPC_CheckPredicate, 13, // 1249: check predicate 13 |
| 9135 | OPC_Decode, 181, 24, 140, 2, // 1251: decode to V6_vmpyh_acc using decoder 268 |
| 9136 | // 1251: } |
| 9137 | 1, 0, // 1256: case 0x1: { |
| 9138 | OPC_CheckPredicate, 13, // 1258: check predicate 13 |
| 9139 | OPC_Decode, 134, 25, 147, 2, // 1260: decode to V6_vrmpyub_rtt_acc using decoder 275 |
| 9140 | // 1260: } |
| 9141 | // 1260: } // switch Inst[5] |
| 9142 | // 1260: } |
| 9143 | // 1260: } // switch Inst[13] |
| 9144 | // 1260: } |
| 9145 | // 1260: } // switch Inst[7:6] |
| 9146 | // 1260: } |
| 9147 | 6, 223, 1, // 1265: case 0x6: { |
| 9148 | OPC_SwitchField, 5, 3, // 1268: switch Inst[7:5] { |
| 9149 | 0, 11, // 1271: case 0x0: { |
| 9150 | OPC_CheckPredicate, 15, // 1273: check predicate 15 |
| 9151 | OPC_CheckField, 13, 1, 0, // 1275: check Inst[13] == 0x0 |
| 9152 | OPC_Decode, 210, 24, 139, 2, // 1279: decode to V6_vmpyub using decoder 267 |
| 9153 | // 1279: } |
| 9154 | 1, 57, // 1284: case 0x1: { |
| 9155 | OPC_SwitchField, 13, 1, // 1286: switch Inst[13] { |
| 9156 | 0, 11, // 1289: case 0x0: { |
| 9157 | OPC_CheckPredicate, 12, // 1291: check predicate 12 |
| 9158 | OPC_CheckField, 8, 5, 0, // 1293: check Inst[12:8] == 0x0 |
| 9159 | OPC_Decode, 217, 20, 148, 2, // 1297: decode to V6_lvsplath using decoder 276 |
| 9160 | // 1297: } |
| 9161 | 1, 0, // 1302: case 0x1: { |
| 9162 | OPC_SwitchField, 19, 2, // 1304: switch Inst[20:19] { |
| 9163 | 0, 7, // 1307: case 0x0: { |
| 9164 | OPC_CheckPredicate, 16, // 1309: check predicate 16 |
| 9165 | OPC_Decode, 152, 25, 153, 2, // 1311: decode to V6_vrmpyzcbs_rt_acc using decoder 281 |
| 9166 | // 1311: } |
| 9167 | 1, 7, // 1316: case 0x1: { |
| 9168 | OPC_CheckPredicate, 16, // 1318: check predicate 16 |
| 9169 | OPC_Decode, 154, 25, 154, 2, // 1320: decode to V6_vrmpyzcbs_rx_acc using decoder 282 |
| 9170 | // 1320: } |
| 9171 | 2, 7, // 1325: case 0x2: { |
| 9172 | OPC_CheckPredicate, 16, // 1327: check predicate 16 |
| 9173 | OPC_Decode, 144, 25, 153, 2, // 1329: decode to V6_vrmpyzbub_rt_acc using decoder 281 |
| 9174 | // 1329: } |
| 9175 | 3, 0, // 1334: case 0x3: { |
| 9176 | OPC_CheckPredicate, 16, // 1336: check predicate 16 |
| 9177 | OPC_Decode, 146, 25, 154, 2, // 1338: decode to V6_vrmpyzbub_rx_acc using decoder 282 |
| 9178 | // 1338: } |
| 9179 | // 1338: } // switch Inst[20:19] |
| 9180 | // 1338: } |
| 9181 | // 1338: } // switch Inst[13] |
| 9182 | // 1338: } |
| 9183 | 2, 57, // 1343: case 0x2: { |
| 9184 | OPC_SwitchField, 13, 1, // 1345: switch Inst[13] { |
| 9185 | 0, 11, // 1348: case 0x0: { |
| 9186 | OPC_CheckPredicate, 12, // 1350: check predicate 12 |
| 9187 | OPC_CheckField, 8, 5, 0, // 1352: check Inst[12:8] == 0x0 |
| 9188 | OPC_Decode, 216, 20, 148, 2, // 1356: decode to V6_lvsplatb using decoder 276 |
| 9189 | // 1356: } |
| 9190 | 1, 0, // 1361: case 0x1: { |
| 9191 | OPC_SwitchField, 19, 2, // 1363: switch Inst[20:19] { |
| 9192 | 0, 7, // 1366: case 0x0: { |
| 9193 | OPC_CheckPredicate, 16, // 1368: check predicate 16 |
| 9194 | OPC_Decode, 140, 25, 153, 2, // 1370: decode to V6_vrmpyzbb_rt_acc using decoder 281 |
| 9195 | // 1370: } |
| 9196 | 1, 7, // 1375: case 0x1: { |
| 9197 | OPC_CheckPredicate, 16, // 1377: check predicate 16 |
| 9198 | OPC_Decode, 142, 25, 154, 2, // 1379: decode to V6_vrmpyzbb_rx_acc using decoder 282 |
| 9199 | // 1379: } |
| 9200 | 2, 7, // 1384: case 0x2: { |
| 9201 | OPC_CheckPredicate, 16, // 1386: check predicate 16 |
| 9202 | OPC_Decode, 156, 25, 153, 2, // 1388: decode to V6_vrmpyznb_rt_acc using decoder 281 |
| 9203 | // 1388: } |
| 9204 | 3, 0, // 1393: case 0x3: { |
| 9205 | OPC_CheckPredicate, 16, // 1395: check predicate 16 |
| 9206 | OPC_Decode, 158, 25, 154, 2, // 1397: decode to V6_vrmpyznb_rx_acc using decoder 282 |
| 9207 | // 1397: } |
| 9208 | // 1397: } // switch Inst[20:19] |
| 9209 | // 1397: } |
| 9210 | // 1397: } // switch Inst[13] |
| 9211 | // 1397: } |
| 9212 | 3, 35, // 1402: case 0x3: { |
| 9213 | OPC_SwitchField, 13, 1, // 1404: switch Inst[13] { |
| 9214 | 0, 7, // 1407: case 0x0: { |
| 9215 | OPC_CheckPredicate, 17, // 1409: check predicate 17 |
| 9216 | OPC_Decode, 227, 20, 135, 2, // 1411: decode to V6_set_qfext using decoder 263 |
| 9217 | // 1411: } |
| 9218 | 1, 0, // 1416: case 0x1: { |
| 9219 | OPC_SwitchField, 19, 2, // 1418: switch Inst[20:19] { |
| 9220 | 0, 7, // 1421: case 0x0: { |
| 9221 | OPC_CheckPredicate, 16, // 1423: check predicate 16 |
| 9222 | OPC_Decode, 148, 25, 153, 2, // 1425: decode to V6_vrmpyzcb_rt_acc using decoder 281 |
| 9223 | // 1425: } |
| 9224 | 1, 0, // 1430: case 0x1: { |
| 9225 | OPC_CheckPredicate, 16, // 1432: check predicate 16 |
| 9226 | OPC_Decode, 150, 25, 154, 2, // 1434: decode to V6_vrmpyzcb_rx_acc using decoder 282 |
| 9227 | // 1434: } |
| 9228 | // 1434: } // switch Inst[20:19] |
| 9229 | // 1434: } |
| 9230 | // 1434: } // switch Inst[13] |
| 9231 | // 1434: } |
| 9232 | 4, 11, // 1439: case 0x4: { |
| 9233 | OPC_CheckPredicate, 13, // 1441: check predicate 13 |
| 9234 | OPC_CheckField, 13, 1, 0, // 1443: check Inst[13] == 0x0 |
| 9235 | OPC_Decode, 133, 25, 155, 2, // 1447: decode to V6_vrmpyub_rtt using decoder 283 |
| 9236 | // 1447: } |
| 9237 | 5, 11, // 1452: case 0x5: { |
| 9238 | OPC_CheckPredicate, 13, // 1454: check predicate 13 |
| 9239 | OPC_CheckField, 13, 1, 0, // 1456: check Inst[13] == 0x0 |
| 9240 | OPC_Decode, 249, 24, 155, 2, // 1460: decode to V6_vrmpybub_rtt using decoder 283 |
| 9241 | // 1460: } |
| 9242 | 6, 11, // 1465: case 0x6: { |
| 9243 | OPC_CheckPredicate, 17, // 1467: check predicate 17 |
| 9244 | OPC_CheckField, 13, 1, 0, // 1469: check Inst[13] == 0x0 |
| 9245 | OPC_Decode, 215, 20, 136, 2, // 1473: decode to V6_get_qfext_oracc using decoder 264 |
| 9246 | // 1473: } |
| 9247 | 7, 0, // 1478: case 0x7: { |
| 9248 | OPC_CheckPredicate, 17, // 1480: check predicate 17 |
| 9249 | OPC_CheckField, 13, 1, 0, // 1482: check Inst[13] == 0x0 |
| 9250 | OPC_Decode, 214, 20, 135, 2, // 1486: decode to V6_get_qfext using decoder 263 |
| 9251 | // 1486: } |
| 9252 | // 1486: } // switch Inst[7:5] |
| 9253 | // 1486: } |
| 9254 | 7, 0, // 1491: case 0x7: { |
| 9255 | OPC_SwitchField, 5, 3, // 1493: switch Inst[7:5] { |
| 9256 | 0, 55, // 1496: case 0x0: { |
| 9257 | OPC_SwitchField, 19, 2, // 1498: switch Inst[20:19] { |
| 9258 | 0, 11, // 1501: case 0x0: { |
| 9259 | OPC_CheckPredicate, 16, // 1503: check predicate 16 |
| 9260 | OPC_CheckField, 13, 1, 0, // 1505: check Inst[13] == 0x0 |
| 9261 | OPC_Decode, 141, 25, 156, 2, // 1509: decode to V6_vrmpyzbb_rx using decoder 284 |
| 9262 | // 1509: } |
| 9263 | 1, 11, // 1514: case 0x1: { |
| 9264 | OPC_CheckPredicate, 16, // 1516: check predicate 16 |
| 9265 | OPC_CheckField, 13, 1, 0, // 1518: check Inst[13] == 0x0 |
| 9266 | OPC_Decode, 139, 25, 157, 2, // 1522: decode to V6_vrmpyzbb_rt using decoder 285 |
| 9267 | // 1522: } |
| 9268 | 2, 11, // 1527: case 0x2: { |
| 9269 | OPC_CheckPredicate, 16, // 1529: check predicate 16 |
| 9270 | OPC_CheckField, 13, 1, 0, // 1531: check Inst[13] == 0x0 |
| 9271 | OPC_Decode, 157, 25, 156, 2, // 1535: decode to V6_vrmpyznb_rx using decoder 284 |
| 9272 | // 1535: } |
| 9273 | 3, 0, // 1540: case 0x3: { |
| 9274 | OPC_CheckPredicate, 16, // 1542: check predicate 16 |
| 9275 | OPC_CheckField, 13, 1, 0, // 1544: check Inst[13] == 0x0 |
| 9276 | OPC_Decode, 155, 25, 157, 2, // 1548: decode to V6_vrmpyznb_rt using decoder 285 |
| 9277 | // 1548: } |
| 9278 | // 1548: } // switch Inst[20:19] |
| 9279 | // 1548: } |
| 9280 | 1, 35, // 1553: case 0x1: { |
| 9281 | OPC_SwitchField, 13, 1, // 1555: switch Inst[13] { |
| 9282 | 0, 21, // 1558: case 0x0: { |
| 9283 | OPC_SwitchField, 19, 2, // 1560: switch Inst[20:19] { |
| 9284 | 0, 7, // 1563: case 0x0: { |
| 9285 | OPC_CheckPredicate, 16, // 1565: check predicate 16 |
| 9286 | OPC_Decode, 149, 25, 156, 2, // 1567: decode to V6_vrmpyzcb_rx using decoder 284 |
| 9287 | // 1567: } |
| 9288 | 1, 0, // 1572: case 0x1: { |
| 9289 | OPC_CheckPredicate, 16, // 1574: check predicate 16 |
| 9290 | OPC_Decode, 147, 25, 157, 2, // 1576: decode to V6_vrmpyzcb_rt using decoder 285 |
| 9291 | // 1576: } |
| 9292 | // 1576: } // switch Inst[20:19] |
| 9293 | // 1576: } |
| 9294 | 1, 0, // 1581: case 0x1: { |
| 9295 | OPC_CheckPredicate, 15, // 1583: check predicate 15 |
| 9296 | OPC_Decode, 185, 25, 158, 2, // 1585: decode to V6_vshuff using decoder 286 |
| 9297 | // 1585: } |
| 9298 | // 1585: } // switch Inst[13] |
| 9299 | // 1585: } |
| 9300 | 2, 0, // 1590: case 0x2: { |
| 9301 | OPC_SwitchField, 13, 1, // 1592: switch Inst[13] { |
| 9302 | 0, 39, // 1595: case 0x0: { |
| 9303 | OPC_SwitchField, 19, 2, // 1597: switch Inst[20:19] { |
| 9304 | 0, 7, // 1600: case 0x0: { |
| 9305 | OPC_CheckPredicate, 16, // 1602: check predicate 16 |
| 9306 | OPC_Decode, 153, 25, 156, 2, // 1604: decode to V6_vrmpyzcbs_rx using decoder 284 |
| 9307 | // 1604: } |
| 9308 | 1, 7, // 1609: case 0x1: { |
| 9309 | OPC_CheckPredicate, 16, // 1611: check predicate 16 |
| 9310 | OPC_Decode, 151, 25, 157, 2, // 1613: decode to V6_vrmpyzcbs_rt using decoder 285 |
| 9311 | // 1613: } |
| 9312 | 2, 7, // 1618: case 0x2: { |
| 9313 | OPC_CheckPredicate, 16, // 1620: check predicate 16 |
| 9314 | OPC_Decode, 145, 25, 156, 2, // 1622: decode to V6_vrmpyzbub_rx using decoder 284 |
| 9315 | // 1622: } |
| 9316 | 3, 0, // 1627: case 0x3: { |
| 9317 | OPC_CheckPredicate, 16, // 1629: check predicate 16 |
| 9318 | OPC_Decode, 143, 25, 157, 2, // 1631: decode to V6_vrmpyzbub_rt using decoder 285 |
| 9319 | // 1631: } |
| 9320 | // 1631: } // switch Inst[20:19] |
| 9321 | // 1631: } |
| 9322 | 1, 0, // 1636: case 0x1: { |
| 9323 | OPC_CheckPredicate, 15, // 1638: check predicate 15 |
| 9324 | OPC_Decode, 254, 22, 158, 2, // 1640: decode to V6_vdeal using decoder 286 |
| 9325 | // 1640: } |
| 9326 | // 1640: } // switch Inst[13] |
| 9327 | // 1640: } |
| 9328 | // 1640: } // switch Inst[7:5] |
| 9329 | // 1640: } |
| 9330 | // 1640: } // switch Inst[23:21] |
| 9331 | // 1640: } |
| 9332 | 26, 204, 1, // 1645: case 0x1a: { |
| 9333 | OPC_SwitchField, 21, 3, // 1648: switch Inst[23:21] { |
| 9334 | 0, 79, // 1651: case 0x0: { |
| 9335 | OPC_SwitchField, 7, 1, // 1653: switch Inst[7] { |
| 9336 | 0, 57, // 1656: case 0x0: { |
| 9337 | OPC_SwitchField, 13, 1, // 1658: switch Inst[13] { |
| 9338 | 0, 11, // 1661: case 0x0: { |
| 9339 | OPC_CheckPredicate, 15, // 1663: check predicate 15 |
| 9340 | OPC_CheckField, 16, 5, 0, // 1665: check Inst[20:16] == 0x0 |
| 9341 | OPC_Decode, 219, 22, 159, 2, // 1669: decode to V6_vcmov using decoder 287 |
| 9342 | // 1669: } |
| 9343 | 1, 0, // 1674: case 0x1: { |
| 9344 | OPC_SwitchField, 5, 2, // 1676: switch Inst[6:5] { |
| 9345 | 0, 7, // 1679: case 0x0: { |
| 9346 | OPC_CheckPredicate, 18, // 1681: check predicate 18 |
| 9347 | OPC_Decode, 205, 25, 160, 2, // 1683: decode to V6_vsub_sf_mix using decoder 288 |
| 9348 | // 1683: } |
| 9349 | 1, 7, // 1688: case 0x1: { |
| 9350 | OPC_CheckPredicate, 17, // 1690: check predicate 17 |
| 9351 | OPC_Decode, 166, 24, 135, 2, // 1692: decode to V6_vmpy_rt_sf using decoder 263 |
| 9352 | // 1692: } |
| 9353 | 2, 7, // 1697: case 0x2: { |
| 9354 | OPC_CheckPredicate, 17, // 1699: check predicate 17 |
| 9355 | OPC_Decode, 165, 24, 135, 2, // 1701: decode to V6_vmpy_rt_qf16 using decoder 263 |
| 9356 | // 1701: } |
| 9357 | 3, 0, // 1706: case 0x3: { |
| 9358 | OPC_CheckPredicate, 17, // 1708: check predicate 17 |
| 9359 | OPC_Decode, 164, 24, 135, 2, // 1710: decode to V6_vmpy_rt_hf using decoder 263 |
| 9360 | // 1710: } |
| 9361 | // 1710: } // switch Inst[6:5] |
| 9362 | // 1710: } |
| 9363 | // 1710: } // switch Inst[13] |
| 9364 | // 1710: } |
| 9365 | 1, 0, // 1715: case 0x1: { |
| 9366 | OPC_CheckPredicate, 18, // 1717: check predicate 18 |
| 9367 | OPC_CheckField, 13, 1, 1, // 1719: check Inst[13] == 0x1 |
| 9368 | OPC_CheckField, 5, 2, 0, // 1723: check Inst[6:5] == 0x0 |
| 9369 | OPC_Decode, 197, 25, 160, 2, // 1727: decode to V6_vsub_hf_mix using decoder 288 |
| 9370 | // 1727: } |
| 9371 | // 1727: } // switch Inst[7] |
| 9372 | // 1727: } |
| 9373 | 1, 19, // 1732: case 0x1: { |
| 9374 | OPC_CheckPredicate, 15, // 1734: check predicate 15 |
| 9375 | OPC_CheckField, 16, 5, 0, // 1736: check Inst[20:16] == 0x0 |
| 9376 | OPC_CheckField, 13, 1, 0, // 1740: check Inst[13] == 0x0 |
| 9377 | OPC_CheckField, 7, 1, 0, // 1744: check Inst[7] == 0x0 |
| 9378 | OPC_Decode, 227, 24, 159, 2, // 1748: decode to V6_vncmov using decoder 287 |
| 9379 | // 1748: } |
| 9380 | 2, 15, // 1753: case 0x2: { |
| 9381 | OPC_CheckPredicate, 15, // 1755: check predicate 15 |
| 9382 | OPC_CheckField, 13, 1, 0, // 1757: check Inst[13] == 0x0 |
| 9383 | OPC_CheckField, 7, 1, 0, // 1761: check Inst[7] == 0x0 |
| 9384 | OPC_Decode, 226, 24, 161, 2, // 1765: decode to V6_vnccombine using decoder 289 |
| 9385 | // 1765: } |
| 9386 | 3, 15, // 1770: case 0x3: { |
| 9387 | OPC_CheckPredicate, 15, // 1772: check predicate 15 |
| 9388 | OPC_CheckField, 13, 1, 0, // 1774: check Inst[13] == 0x0 |
| 9389 | OPC_CheckField, 7, 1, 0, // 1778: check Inst[7] == 0x0 |
| 9390 | OPC_Decode, 216, 22, 161, 2, // 1782: decode to V6_vccombine using decoder 289 |
| 9391 | // 1782: } |
| 9392 | 4, 15, // 1787: case 0x4: { |
| 9393 | OPC_CheckPredicate, 19, // 1789: check predicate 19 |
| 9394 | OPC_CheckField, 13, 1, 1, // 1791: check Inst[13] == 0x1 |
| 9395 | OPC_CheckField, 5, 3, 7, // 1795: check Inst[7:5] == 0x7 |
| 9396 | OPC_Decode, 160, 25, 160, 2, // 1799: decode to V6_vrotr using decoder 288 |
| 9397 | // 1799: } |
| 9398 | 5, 15, // 1804: case 0x5: { |
| 9399 | OPC_CheckPredicate, 19, // 1806: check predicate 19 |
| 9400 | OPC_CheckField, 13, 1, 1, // 1808: check Inst[13] == 0x1 |
| 9401 | OPC_CheckField, 5, 3, 7, // 1812: check Inst[7:5] == 0x7 |
| 9402 | OPC_Decode, 177, 22, 162, 2, // 1816: decode to V6_vasr_into using decoder 290 |
| 9403 | // 1816: } |
| 9404 | 6, 0, // 1821: case 0x6: { |
| 9405 | OPC_SwitchField, 5, 3, // 1823: switch Inst[7:5] { |
| 9406 | 6, 11, // 1826: case 0x6: { |
| 9407 | OPC_CheckPredicate, 20, // 1828: check predicate 20 |
| 9408 | OPC_CheckField, 13, 1, 1, // 1830: check Inst[13] == 0x1 |
| 9409 | OPC_Decode, 237, 22, 160, 2, // 1834: decode to V6_vcvt2_b_hf using decoder 288 |
| 9410 | // 1834: } |
| 9411 | 7, 0, // 1839: case 0x7: { |
| 9412 | OPC_CheckPredicate, 20, // 1841: check predicate 20 |
| 9413 | OPC_CheckField, 13, 1, 1, // 1843: check Inst[13] == 0x1 |
| 9414 | OPC_Decode, 240, 22, 160, 2, // 1847: decode to V6_vcvt2_ub_hf using decoder 288 |
| 9415 | // 1847: } |
| 9416 | // 1847: } // switch Inst[7:5] |
| 9417 | // 1847: } |
| 9418 | // 1847: } // switch Inst[23:21] |
| 9419 | // 1847: } |
| 9420 | 27, 177, 1, // 1852: case 0x1b: { |
| 9421 | OPC_SwitchField, 5, 3, // 1855: switch Inst[7:5] { |
| 9422 | 0, 21, // 1858: case 0x0: { |
| 9423 | OPC_SwitchField, 13, 1, // 1860: switch Inst[13] { |
| 9424 | 0, 7, // 1863: case 0x0: { |
| 9425 | OPC_CheckPredicate, 15, // 1865: check predicate 15 |
| 9426 | OPC_Decode, 160, 22, 131, 2, // 1867: decode to V6_valignb using decoder 259 |
| 9427 | // 1867: } |
| 9428 | 1, 0, // 1872: case 0x1: { |
| 9429 | OPC_CheckPredicate, 15, // 1874: check predicate 15 |
| 9430 | OPC_Decode, 180, 22, 131, 2, // 1876: decode to V6_vasrhbrndsat using decoder 259 |
| 9431 | // 1876: } |
| 9432 | // 1876: } // switch Inst[13] |
| 9433 | // 1876: } |
| 9434 | 1, 21, // 1881: case 0x1: { |
| 9435 | OPC_SwitchField, 13, 1, // 1883: switch Inst[13] { |
| 9436 | 0, 7, // 1886: case 0x0: { |
| 9437 | OPC_CheckPredicate, 15, // 1888: check predicate 15 |
| 9438 | OPC_Decode, 232, 23, 131, 2, // 1890: decode to V6_vlalignb using decoder 259 |
| 9439 | // 1890: } |
| 9440 | 1, 0, // 1895: case 0x1: { |
| 9441 | OPC_CheckPredicate, 15, // 1897: check predicate 15 |
| 9442 | OPC_Decode, 240, 23, 131, 2, // 1899: decode to V6_vlutvvb using decoder 259 |
| 9443 | // 1899: } |
| 9444 | // 1899: } // switch Inst[13] |
| 9445 | // 1899: } |
| 9446 | 2, 11, // 1904: case 0x2: { |
| 9447 | OPC_CheckPredicate, 15, // 1906: check predicate 15 |
| 9448 | OPC_CheckField, 13, 1, 0, // 1908: check Inst[13] == 0x0 |
| 9449 | OPC_Decode, 195, 22, 131, 2, // 1912: decode to V6_vasrwh using decoder 259 |
| 9450 | // 1912: } |
| 9451 | 3, 21, // 1917: case 0x3: { |
| 9452 | OPC_SwitchField, 13, 1, // 1919: switch Inst[13] { |
| 9453 | 0, 7, // 1922: case 0x0: { |
| 9454 | OPC_CheckPredicate, 15, // 1924: check predicate 15 |
| 9455 | OPC_Decode, 197, 22, 131, 2, // 1926: decode to V6_vasrwhsat using decoder 259 |
| 9456 | // 1926: } |
| 9457 | 1, 0, // 1931: case 0x1: { |
| 9458 | OPC_CheckPredicate, 15, // 1933: check predicate 15 |
| 9459 | OPC_Decode, 190, 25, 132, 2, // 1935: decode to V6_vshuffvdd using decoder 260 |
| 9460 | // 1935: } |
| 9461 | // 1935: } // switch Inst[13] |
| 9462 | // 1935: } |
| 9463 | 4, 21, // 1940: case 0x4: { |
| 9464 | OPC_SwitchField, 13, 1, // 1942: switch Inst[13] { |
| 9465 | 0, 7, // 1945: case 0x0: { |
| 9466 | OPC_CheckPredicate, 15, // 1947: check predicate 15 |
| 9467 | OPC_Decode, 196, 22, 131, 2, // 1949: decode to V6_vasrwhrndsat using decoder 259 |
| 9468 | // 1949: } |
| 9469 | 1, 0, // 1954: case 0x1: { |
| 9470 | OPC_CheckPredicate, 15, // 1956: check predicate 15 |
| 9471 | OPC_Decode, 130, 23, 132, 2, // 1958: decode to V6_vdealvdd using decoder 260 |
| 9472 | // 1958: } |
| 9473 | // 1958: } // switch Inst[13] |
| 9474 | // 1958: } |
| 9475 | 5, 21, // 1963: case 0x5: { |
| 9476 | OPC_SwitchField, 13, 1, // 1965: switch Inst[13] { |
| 9477 | 0, 7, // 1968: case 0x0: { |
| 9478 | OPC_CheckPredicate, 15, // 1970: check predicate 15 |
| 9479 | OPC_Decode, 199, 22, 131, 2, // 1972: decode to V6_vasrwuhsat using decoder 259 |
| 9480 | // 1972: } |
| 9481 | 1, 0, // 1977: case 0x1: { |
| 9482 | OPC_CheckPredicate, 15, // 1979: check predicate 15 |
| 9483 | OPC_Decode, 242, 23, 163, 2, // 1981: decode to V6_vlutvvb_oracc using decoder 291 |
| 9484 | // 1981: } |
| 9485 | // 1981: } // switch Inst[13] |
| 9486 | // 1981: } |
| 9487 | 6, 21, // 1986: case 0x6: { |
| 9488 | OPC_SwitchField, 13, 1, // 1988: switch Inst[13] { |
| 9489 | 0, 7, // 1991: case 0x0: { |
| 9490 | OPC_CheckPredicate, 15, // 1993: check predicate 15 |
| 9491 | OPC_Decode, 183, 22, 131, 2, // 1995: decode to V6_vasrhubsat using decoder 259 |
| 9492 | // 1995: } |
| 9493 | 1, 0, // 2000: case 0x1: { |
| 9494 | OPC_CheckPredicate, 15, // 2002: check predicate 15 |
| 9495 | OPC_Decode, 245, 23, 132, 2, // 2004: decode to V6_vlutvwh using decoder 260 |
| 9496 | // 2004: } |
| 9497 | // 2004: } // switch Inst[13] |
| 9498 | // 2004: } |
| 9499 | 7, 0, // 2009: case 0x7: { |
| 9500 | OPC_SwitchField, 13, 1, // 2011: switch Inst[13] { |
| 9501 | 0, 7, // 2014: case 0x0: { |
| 9502 | OPC_CheckPredicate, 15, // 2016: check predicate 15 |
| 9503 | OPC_Decode, 182, 22, 131, 2, // 2018: decode to V6_vasrhubrndsat using decoder 259 |
| 9504 | // 2018: } |
| 9505 | 1, 0, // 2023: case 0x1: { |
| 9506 | OPC_CheckPredicate, 15, // 2025: check predicate 15 |
| 9507 | OPC_Decode, 247, 23, 164, 2, // 2027: decode to V6_vlutvwh_oracc using decoder 292 |
| 9508 | // 2027: } |
| 9509 | // 2027: } // switch Inst[13] |
| 9510 | // 2027: } |
| 9511 | // 2027: } // switch Inst[7:5] |
| 9512 | // 2027: } |
| 9513 | 28, 203, 12, // 2032: case 0x1c: { |
| 9514 | OPC_SwitchField, 21, 3, // 2035: switch Inst[23:21] { |
| 9515 | 0, 187, 1, // 2038: case 0x0: { |
| 9516 | OPC_SwitchField, 5, 3, // 2041: switch Inst[7:5] { |
| 9517 | 0, 21, // 2044: case 0x0: { |
| 9518 | OPC_SwitchField, 13, 1, // 2046: switch Inst[13] { |
| 9519 | 0, 7, // 2049: case 0x0: { |
| 9520 | OPC_CheckPredicate, 15, // 2051: check predicate 15 |
| 9521 | OPC_Decode, 137, 25, 160, 2, // 2053: decode to V6_vrmpyubv using decoder 288 |
| 9522 | // 2053: } |
| 9523 | 1, 0, // 2058: case 0x1: { |
| 9524 | OPC_CheckPredicate, 15, // 2060: check predicate 15 |
| 9525 | OPC_Decode, 138, 25, 165, 2, // 2062: decode to V6_vrmpyubv_acc using decoder 293 |
| 9526 | // 2062: } |
| 9527 | // 2062: } // switch Inst[13] |
| 9528 | // 2062: } |
| 9529 | 1, 21, // 2067: case 0x1: { |
| 9530 | OPC_SwitchField, 13, 1, // 2069: switch Inst[13] { |
| 9531 | 0, 7, // 2072: case 0x0: { |
| 9532 | OPC_CheckPredicate, 15, // 2074: check predicate 15 |
| 9533 | OPC_Decode, 129, 25, 160, 2, // 2076: decode to V6_vrmpybv using decoder 288 |
| 9534 | // 2076: } |
| 9535 | 1, 0, // 2081: case 0x1: { |
| 9536 | OPC_CheckPredicate, 15, // 2083: check predicate 15 |
| 9537 | OPC_Decode, 130, 25, 165, 2, // 2085: decode to V6_vrmpybv_acc using decoder 293 |
| 9538 | // 2085: } |
| 9539 | // 2085: } // switch Inst[13] |
| 9540 | // 2085: } |
| 9541 | 2, 21, // 2090: case 0x2: { |
| 9542 | OPC_SwitchField, 13, 1, // 2092: switch Inst[13] { |
| 9543 | 0, 7, // 2095: case 0x0: { |
| 9544 | OPC_CheckPredicate, 15, // 2097: check predicate 15 |
| 9545 | OPC_Decode, 255, 24, 160, 2, // 2099: decode to V6_vrmpybusv using decoder 288 |
| 9546 | // 2099: } |
| 9547 | 1, 0, // 2104: case 0x1: { |
| 9548 | OPC_CheckPredicate, 15, // 2106: check predicate 15 |
| 9549 | OPC_Decode, 128, 25, 165, 2, // 2108: decode to V6_vrmpybusv_acc using decoder 293 |
| 9550 | // 2108: } |
| 9551 | // 2108: } // switch Inst[13] |
| 9552 | // 2108: } |
| 9553 | 3, 21, // 2113: case 0x3: { |
| 9554 | OPC_SwitchField, 13, 1, // 2115: switch Inst[13] { |
| 9555 | 0, 7, // 2118: case 0x0: { |
| 9556 | OPC_CheckPredicate, 15, // 2120: check predicate 15 |
| 9557 | OPC_Decode, 150, 23, 160, 2, // 2122: decode to V6_vdmpyhvsat using decoder 288 |
| 9558 | // 2122: } |
| 9559 | 1, 0, // 2127: case 0x1: { |
| 9560 | OPC_CheckPredicate, 15, // 2129: check predicate 15 |
| 9561 | OPC_Decode, 151, 23, 165, 2, // 2131: decode to V6_vdmpyhvsat_acc using decoder 293 |
| 9562 | // 2131: } |
| 9563 | // 2131: } // switch Inst[13] |
| 9564 | // 2131: } |
| 9565 | 4, 21, // 2136: case 0x4: { |
| 9566 | OPC_SwitchField, 13, 1, // 2138: switch Inst[13] { |
| 9567 | 0, 7, // 2141: case 0x0: { |
| 9568 | OPC_CheckPredicate, 15, // 2143: check predicate 15 |
| 9569 | OPC_Decode, 176, 24, 166, 2, // 2145: decode to V6_vmpybv using decoder 294 |
| 9570 | // 2145: } |
| 9571 | 1, 0, // 2150: case 0x1: { |
| 9572 | OPC_CheckPredicate, 15, // 2152: check predicate 15 |
| 9573 | OPC_Decode, 177, 24, 162, 2, // 2154: decode to V6_vmpybv_acc using decoder 290 |
| 9574 | // 2154: } |
| 9575 | // 2154: } // switch Inst[13] |
| 9576 | // 2154: } |
| 9577 | 5, 21, // 2159: case 0x5: { |
| 9578 | OPC_SwitchField, 13, 1, // 2161: switch Inst[13] { |
| 9579 | 0, 7, // 2164: case 0x0: { |
| 9580 | OPC_CheckPredicate, 15, // 2166: check predicate 15 |
| 9581 | OPC_Decode, 212, 24, 166, 2, // 2168: decode to V6_vmpyubv using decoder 294 |
| 9582 | // 2168: } |
| 9583 | 1, 0, // 2173: case 0x1: { |
| 9584 | OPC_CheckPredicate, 15, // 2175: check predicate 15 |
| 9585 | OPC_Decode, 213, 24, 162, 2, // 2177: decode to V6_vmpyubv_acc using decoder 290 |
| 9586 | // 2177: } |
| 9587 | // 2177: } // switch Inst[13] |
| 9588 | // 2177: } |
| 9589 | 6, 21, // 2182: case 0x6: { |
| 9590 | OPC_SwitchField, 13, 1, // 2184: switch Inst[13] { |
| 9591 | 0, 7, // 2187: case 0x0: { |
| 9592 | OPC_CheckPredicate, 15, // 2189: check predicate 15 |
| 9593 | OPC_Decode, 174, 24, 166, 2, // 2191: decode to V6_vmpybusv using decoder 294 |
| 9594 | // 2191: } |
| 9595 | 1, 0, // 2196: case 0x1: { |
| 9596 | OPC_CheckPredicate, 15, // 2198: check predicate 15 |
| 9597 | OPC_Decode, 175, 24, 162, 2, // 2200: decode to V6_vmpybusv_acc using decoder 290 |
| 9598 | // 2200: } |
| 9599 | // 2200: } // switch Inst[13] |
| 9600 | // 2200: } |
| 9601 | 7, 0, // 2205: case 0x7: { |
| 9602 | OPC_SwitchField, 13, 1, // 2207: switch Inst[13] { |
| 9603 | 0, 7, // 2210: case 0x0: { |
| 9604 | OPC_CheckPredicate, 15, // 2212: check predicate 15 |
| 9605 | OPC_Decode, 187, 24, 166, 2, // 2214: decode to V6_vmpyhv using decoder 294 |
| 9606 | // 2214: } |
| 9607 | 1, 0, // 2219: case 0x1: { |
| 9608 | OPC_CheckPredicate, 15, // 2221: check predicate 15 |
| 9609 | OPC_Decode, 188, 24, 162, 2, // 2223: decode to V6_vmpyhv_acc using decoder 290 |
| 9610 | // 2223: } |
| 9611 | // 2223: } // switch Inst[13] |
| 9612 | // 2223: } |
| 9613 | // 2223: } // switch Inst[7:5] |
| 9614 | // 2223: } |
| 9615 | 1, 187, 1, // 2228: case 0x1: { |
| 9616 | OPC_SwitchField, 5, 3, // 2231: switch Inst[7:5] { |
| 9617 | 0, 21, // 2234: case 0x0: { |
| 9618 | OPC_SwitchField, 13, 1, // 2236: switch Inst[13] { |
| 9619 | 0, 7, // 2239: case 0x0: { |
| 9620 | OPC_CheckPredicate, 15, // 2241: check predicate 15 |
| 9621 | OPC_Decode, 218, 24, 166, 2, // 2243: decode to V6_vmpyuhv using decoder 294 |
| 9622 | // 2243: } |
| 9623 | 1, 0, // 2248: case 0x1: { |
| 9624 | OPC_CheckPredicate, 15, // 2250: check predicate 15 |
| 9625 | OPC_Decode, 219, 24, 162, 2, // 2252: decode to V6_vmpyuhv_acc using decoder 290 |
| 9626 | // 2252: } |
| 9627 | // 2252: } // switch Inst[13] |
| 9628 | // 2252: } |
| 9629 | 1, 21, // 2257: case 0x1: { |
| 9630 | OPC_SwitchField, 13, 1, // 2259: switch Inst[13] { |
| 9631 | 0, 7, // 2262: case 0x0: { |
| 9632 | OPC_CheckPredicate, 15, // 2264: check predicate 15 |
| 9633 | OPC_Decode, 189, 24, 160, 2, // 2266: decode to V6_vmpyhvsrs using decoder 288 |
| 9634 | // 2266: } |
| 9635 | 1, 0, // 2271: case 0x1: { |
| 9636 | OPC_CheckPredicate, 15, // 2273: check predicate 15 |
| 9637 | OPC_Decode, 186, 24, 162, 2, // 2275: decode to V6_vmpyhus_acc using decoder 290 |
| 9638 | // 2275: } |
| 9639 | // 2275: } // switch Inst[13] |
| 9640 | // 2275: } |
| 9641 | 2, 21, // 2280: case 0x2: { |
| 9642 | OPC_SwitchField, 13, 1, // 2282: switch Inst[13] { |
| 9643 | 0, 7, // 2285: case 0x0: { |
| 9644 | OPC_CheckPredicate, 15, // 2287: check predicate 15 |
| 9645 | OPC_Decode, 185, 24, 166, 2, // 2289: decode to V6_vmpyhus using decoder 294 |
| 9646 | // 2289: } |
| 9647 | 1, 0, // 2294: case 0x1: { |
| 9648 | OPC_CheckPredicate, 12, // 2296: check predicate 12 |
| 9649 | OPC_Decode, 141, 22, 162, 2, // 2298: decode to V6_vaddhw_acc using decoder 290 |
| 9650 | // 2298: } |
| 9651 | // 2298: } // switch Inst[13] |
| 9652 | // 2298: } |
| 9653 | 3, 21, // 2303: case 0x3: { |
| 9654 | OPC_SwitchField, 13, 1, // 2305: switch Inst[13] { |
| 9655 | 0, 7, // 2308: case 0x0: { |
| 9656 | OPC_CheckPredicate, 15, // 2310: check predicate 15 |
| 9657 | OPC_Decode, 141, 24, 167, 2, // 2312: decode to V6_vmpabusv using decoder 295 |
| 9658 | // 2312: } |
| 9659 | 1, 0, // 2317: case 0x1: { |
| 9660 | OPC_CheckPredicate, 12, // 2319: check predicate 12 |
| 9661 | OPC_Decode, 206, 24, 162, 2, // 2321: decode to V6_vmpyowh_64_acc using decoder 290 |
| 9662 | // 2321: } |
| 9663 | // 2321: } // switch Inst[13] |
| 9664 | // 2321: } |
| 9665 | 4, 21, // 2326: case 0x4: { |
| 9666 | OPC_SwitchField, 13, 1, // 2328: switch Inst[13] { |
| 9667 | 0, 7, // 2331: case 0x0: { |
| 9668 | OPC_CheckPredicate, 15, // 2333: check predicate 15 |
| 9669 | OPC_Decode, 194, 24, 160, 2, // 2335: decode to V6_vmpyih using decoder 288 |
| 9670 | // 2335: } |
| 9671 | 1, 0, // 2340: case 0x1: { |
| 9672 | OPC_CheckPredicate, 15, // 2342: check predicate 15 |
| 9673 | OPC_Decode, 195, 24, 165, 2, // 2344: decode to V6_vmpyih_acc using decoder 293 |
| 9674 | // 2344: } |
| 9675 | // 2344: } // switch Inst[13] |
| 9676 | // 2344: } |
| 9677 | 5, 21, // 2349: case 0x5: { |
| 9678 | OPC_SwitchField, 13, 1, // 2351: switch Inst[13] { |
| 9679 | 0, 7, // 2354: case 0x0: { |
| 9680 | OPC_CheckPredicate, 15, // 2356: check predicate 15 |
| 9681 | OPC_Decode, 162, 22, 160, 2, // 2358: decode to V6_vand using decoder 288 |
| 9682 | // 2358: } |
| 9683 | 1, 0, // 2363: case 0x1: { |
| 9684 | OPC_CheckPredicate, 15, // 2365: check predicate 15 |
| 9685 | OPC_Decode, 193, 24, 165, 2, // 2367: decode to V6_vmpyiewuh_acc using decoder 293 |
| 9686 | // 2367: } |
| 9687 | // 2367: } // switch Inst[13] |
| 9688 | // 2367: } |
| 9689 | 6, 21, // 2372: case 0x6: { |
| 9690 | OPC_SwitchField, 13, 1, // 2374: switch Inst[13] { |
| 9691 | 0, 7, // 2377: case 0x0: { |
| 9692 | OPC_CheckPredicate, 15, // 2379: check predicate 15 |
| 9693 | OPC_Decode, 235, 24, 160, 2, // 2381: decode to V6_vor using decoder 288 |
| 9694 | // 2381: } |
| 9695 | 1, 0, // 2386: case 0x1: { |
| 9696 | OPC_CheckPredicate, 15, // 2388: check predicate 15 |
| 9697 | OPC_Decode, 209, 24, 165, 2, // 2390: decode to V6_vmpyowh_sacc using decoder 293 |
| 9698 | // 2390: } |
| 9699 | // 2390: } // switch Inst[13] |
| 9700 | // 2390: } |
| 9701 | 7, 0, // 2395: case 0x7: { |
| 9702 | OPC_SwitchField, 13, 1, // 2397: switch Inst[13] { |
| 9703 | 0, 7, // 2400: case 0x0: { |
| 9704 | OPC_CheckPredicate, 15, // 2402: check predicate 15 |
| 9705 | OPC_Decode, 130, 26, 160, 2, // 2404: decode to V6_vxor using decoder 288 |
| 9706 | // 2404: } |
| 9707 | 1, 0, // 2409: case 0x1: { |
| 9708 | OPC_CheckPredicate, 15, // 2411: check predicate 15 |
| 9709 | OPC_Decode, 208, 24, 165, 2, // 2413: decode to V6_vmpyowh_rnd_sacc using decoder 293 |
| 9710 | // 2413: } |
| 9711 | // 2413: } // switch Inst[13] |
| 9712 | // 2413: } |
| 9713 | // 2413: } // switch Inst[7:5] |
| 9714 | // 2413: } |
| 9715 | 2, 167, 1, // 2418: case 0x2: { |
| 9716 | OPC_SwitchField, 5, 3, // 2421: switch Inst[7:5] { |
| 9717 | 0, 21, // 2424: case 0x0: { |
| 9718 | OPC_SwitchField, 13, 1, // 2426: switch Inst[13] { |
| 9719 | 0, 7, // 2429: case 0x0: { |
| 9720 | OPC_CheckPredicate, 15, // 2431: check predicate 15 |
| 9721 | OPC_Decode, 153, 22, 160, 2, // 2433: decode to V6_vaddw using decoder 288 |
| 9722 | // 2433: } |
| 9723 | 1, 0, // 2438: case 0x1: { |
| 9724 | OPC_CheckPredicate, 15, // 2440: check predicate 15 |
| 9725 | OPC_Decode, 191, 24, 165, 2, // 2442: decode to V6_vmpyiewh_acc using decoder 293 |
| 9726 | // 2442: } |
| 9727 | // 2442: } // switch Inst[13] |
| 9728 | // 2442: } |
| 9729 | 1, 21, // 2447: case 0x1: { |
| 9730 | OPC_SwitchField, 13, 1, // 2449: switch Inst[13] { |
| 9731 | 0, 7, // 2452: case 0x0: { |
| 9732 | OPC_CheckPredicate, 15, // 2454: check predicate 15 |
| 9733 | OPC_Decode, 144, 22, 160, 2, // 2456: decode to V6_vaddubsat using decoder 288 |
| 9734 | // 2456: } |
| 9735 | 1, 0, // 2461: case 0x1: { |
| 9736 | OPC_CheckPredicate, 21, // 2463: check predicate 21 |
| 9737 | OPC_Decode, 170, 24, 162, 2, // 2465: decode to V6_vmpy_sf_hf_acc using decoder 290 |
| 9738 | // 2465: } |
| 9739 | // 2465: } // switch Inst[13] |
| 9740 | // 2465: } |
| 9741 | 2, 21, // 2470: case 0x2: { |
| 9742 | OPC_SwitchField, 13, 1, // 2472: switch Inst[13] { |
| 9743 | 0, 7, // 2475: case 0x0: { |
| 9744 | OPC_CheckPredicate, 15, // 2477: check predicate 15 |
| 9745 | OPC_Decode, 147, 22, 160, 2, // 2479: decode to V6_vadduhsat using decoder 288 |
| 9746 | // 2479: } |
| 9747 | 1, 0, // 2484: case 0x1: { |
| 9748 | OPC_CheckPredicate, 21, // 2486: check predicate 21 |
| 9749 | OPC_Decode, 155, 24, 165, 2, // 2488: decode to V6_vmpy_hf_hf_acc using decoder 293 |
| 9750 | // 2488: } |
| 9751 | // 2488: } // switch Inst[13] |
| 9752 | // 2488: } |
| 9753 | 3, 21, // 2493: case 0x3: { |
| 9754 | OPC_SwitchField, 13, 1, // 2495: switch Inst[13] { |
| 9755 | 0, 7, // 2498: case 0x0: { |
| 9756 | OPC_CheckPredicate, 15, // 2500: check predicate 15 |
| 9757 | OPC_Decode, 138, 22, 160, 2, // 2502: decode to V6_vaddhsat using decoder 288 |
| 9758 | // 2502: } |
| 9759 | 1, 0, // 2507: case 0x1: { |
| 9760 | OPC_CheckPredicate, 21, // 2509: check predicate 21 |
| 9761 | OPC_Decode, 133, 23, 165, 2, // 2511: decode to V6_vdmpy_sf_hf_acc using decoder 293 |
| 9762 | // 2511: } |
| 9763 | // 2511: } // switch Inst[13] |
| 9764 | // 2511: } |
| 9765 | 4, 21, // 2516: case 0x4: { |
| 9766 | OPC_SwitchField, 13, 1, // 2518: switch Inst[13] { |
| 9767 | 0, 7, // 2521: case 0x0: { |
| 9768 | OPC_CheckPredicate, 15, // 2523: check predicate 15 |
| 9769 | OPC_Decode, 157, 22, 160, 2, // 2525: decode to V6_vaddwsat using decoder 288 |
| 9770 | // 2525: } |
| 9771 | 1, 0, // 2530: case 0x1: { |
| 9772 | OPC_CheckPredicate, 12, // 2532: check predicate 12 |
| 9773 | OPC_Decode, 150, 22, 162, 2, // 2534: decode to V6_vadduhw_acc using decoder 290 |
| 9774 | // 2534: } |
| 9775 | // 2534: } // switch Inst[13] |
| 9776 | // 2534: } |
| 9777 | 5, 21, // 2539: case 0x5: { |
| 9778 | OPC_SwitchField, 13, 1, // 2541: switch Inst[13] { |
| 9779 | 0, 7, // 2544: case 0x0: { |
| 9780 | OPC_CheckPredicate, 15, // 2546: check predicate 15 |
| 9781 | OPC_Decode, 207, 25, 160, 2, // 2548: decode to V6_vsubb using decoder 288 |
| 9782 | // 2548: } |
| 9783 | 1, 0, // 2553: case 0x1: { |
| 9784 | OPC_CheckPredicate, 12, // 2555: check predicate 12 |
| 9785 | OPC_Decode, 143, 22, 162, 2, // 2557: decode to V6_vaddubh_acc using decoder 290 |
| 9786 | // 2557: } |
| 9787 | // 2557: } // switch Inst[13] |
| 9788 | // 2557: } |
| 9789 | 6, 11, // 2562: case 0x6: { |
| 9790 | OPC_CheckPredicate, 15, // 2564: check predicate 15 |
| 9791 | OPC_CheckField, 13, 1, 0, // 2566: check Inst[13] == 0x0 |
| 9792 | OPC_Decode, 215, 25, 160, 2, // 2570: decode to V6_vsubh using decoder 288 |
| 9793 | // 2570: } |
| 9794 | 7, 0, // 2575: case 0x7: { |
| 9795 | OPC_CheckPredicate, 15, // 2577: check predicate 15 |
| 9796 | OPC_CheckField, 13, 1, 0, // 2579: check Inst[13] == 0x0 |
| 9797 | OPC_Decode, 231, 25, 160, 2, // 2583: decode to V6_vsubw using decoder 288 |
| 9798 | // 2583: } |
| 9799 | // 2583: } // switch Inst[7:5] |
| 9800 | // 2583: } |
| 9801 | 3, 195, 1, // 2588: case 0x3: { |
| 9802 | OPC_SwitchField, 5, 3, // 2591: switch Inst[7:5] { |
| 9803 | 0, 21, // 2594: case 0x0: { |
| 9804 | OPC_SwitchField, 13, 1, // 2596: switch Inst[13] { |
| 9805 | 0, 7, // 2599: case 0x0: { |
| 9806 | OPC_CheckPredicate, 15, // 2601: check predicate 15 |
| 9807 | OPC_Decode, 223, 25, 160, 2, // 2603: decode to V6_vsububsat using decoder 288 |
| 9808 | // 2603: } |
| 9809 | 1, 0, // 2608: case 0x1: { |
| 9810 | OPC_CheckPredicate, 21, // 2610: check predicate 21 |
| 9811 | OPC_Decode, 178, 23, 160, 2, // 2612: decode to V6_vfmin_hf using decoder 288 |
| 9812 | // 2612: } |
| 9813 | // 2612: } // switch Inst[13] |
| 9814 | // 2612: } |
| 9815 | 1, 21, // 2617: case 0x1: { |
| 9816 | OPC_SwitchField, 13, 1, // 2619: switch Inst[13] { |
| 9817 | 0, 7, // 2622: case 0x0: { |
| 9818 | OPC_CheckPredicate, 15, // 2624: check predicate 15 |
| 9819 | OPC_Decode, 226, 25, 160, 2, // 2626: decode to V6_vsubuhsat using decoder 288 |
| 9820 | // 2626: } |
| 9821 | 1, 0, // 2631: case 0x1: { |
| 9822 | OPC_CheckPredicate, 21, // 2633: check predicate 21 |
| 9823 | OPC_Decode, 179, 23, 160, 2, // 2635: decode to V6_vfmin_sf using decoder 288 |
| 9824 | // 2635: } |
| 9825 | // 2635: } // switch Inst[13] |
| 9826 | // 2635: } |
| 9827 | 2, 21, // 2640: case 0x2: { |
| 9828 | OPC_SwitchField, 13, 1, // 2642: switch Inst[13] { |
| 9829 | 0, 7, // 2645: case 0x0: { |
| 9830 | OPC_CheckPredicate, 15, // 2647: check predicate 15 |
| 9831 | OPC_Decode, 219, 25, 160, 2, // 2649: decode to V6_vsubhsat using decoder 288 |
| 9832 | // 2649: } |
| 9833 | 1, 0, // 2654: case 0x1: { |
| 9834 | OPC_CheckPredicate, 21, // 2656: check predicate 21 |
| 9835 | OPC_Decode, 175, 23, 160, 2, // 2658: decode to V6_vfmax_hf using decoder 288 |
| 9836 | // 2658: } |
| 9837 | // 2658: } // switch Inst[13] |
| 9838 | // 2658: } |
| 9839 | 3, 21, // 2663: case 0x3: { |
| 9840 | OPC_SwitchField, 13, 1, // 2665: switch Inst[13] { |
| 9841 | 0, 7, // 2668: case 0x0: { |
| 9842 | OPC_CheckPredicate, 15, // 2670: check predicate 15 |
| 9843 | OPC_Decode, 235, 25, 160, 2, // 2672: decode to V6_vsubwsat using decoder 288 |
| 9844 | // 2672: } |
| 9845 | 1, 0, // 2677: case 0x1: { |
| 9846 | OPC_CheckPredicate, 21, // 2679: check predicate 21 |
| 9847 | OPC_Decode, 176, 23, 160, 2, // 2681: decode to V6_vfmax_sf using decoder 288 |
| 9848 | // 2681: } |
| 9849 | // 2681: } // switch Inst[13] |
| 9850 | // 2681: } |
| 9851 | 4, 21, // 2686: case 0x4: { |
| 9852 | OPC_SwitchField, 13, 1, // 2688: switch Inst[13] { |
| 9853 | 0, 7, // 2691: case 0x0: { |
| 9854 | OPC_CheckPredicate, 15, // 2693: check predicate 15 |
| 9855 | OPC_Decode, 252, 21, 167, 2, // 2695: decode to V6_vaddb_dv using decoder 295 |
| 9856 | // 2695: } |
| 9857 | 1, 0, // 2700: case 0x1: { |
| 9858 | OPC_CheckPredicate, 20, // 2702: check predicate 20 |
| 9859 | OPC_Decode, 177, 23, 160, 2, // 2704: decode to V6_vfmin_f8 using decoder 288 |
| 9860 | // 2704: } |
| 9861 | // 2704: } // switch Inst[13] |
| 9862 | // 2704: } |
| 9863 | 5, 21, // 2709: case 0x5: { |
| 9864 | OPC_SwitchField, 13, 1, // 2711: switch Inst[13] { |
| 9865 | 0, 7, // 2714: case 0x0: { |
| 9866 | OPC_CheckPredicate, 15, // 2716: check predicate 15 |
| 9867 | OPC_Decode, 135, 22, 167, 2, // 2718: decode to V6_vaddh_dv using decoder 295 |
| 9868 | // 2718: } |
| 9869 | 1, 0, // 2723: case 0x1: { |
| 9870 | OPC_CheckPredicate, 20, // 2725: check predicate 20 |
| 9871 | OPC_Decode, 174, 23, 160, 2, // 2727: decode to V6_vfmax_f8 using decoder 288 |
| 9872 | // 2727: } |
| 9873 | // 2727: } // switch Inst[13] |
| 9874 | // 2727: } |
| 9875 | 6, 25, // 2732: case 0x6: { |
| 9876 | OPC_SwitchField, 13, 1, // 2734: switch Inst[13] { |
| 9877 | 0, 7, // 2737: case 0x0: { |
| 9878 | OPC_CheckPredicate, 15, // 2739: check predicate 15 |
| 9879 | OPC_Decode, 154, 22, 167, 2, // 2741: decode to V6_vaddw_dv using decoder 295 |
| 9880 | // 2741: } |
| 9881 | 1, 0, // 2746: case 0x1: { |
| 9882 | OPC_CheckPredicate, 20, // 2748: check predicate 20 |
| 9883 | OPC_CheckField, 16, 5, 6, // 2750: check Inst[20:16] == 0x6 |
| 9884 | OPC_Decode, 223, 21, 168, 2, // 2754: decode to V6_vabs_f8 using decoder 296 |
| 9885 | // 2754: } |
| 9886 | // 2754: } // switch Inst[13] |
| 9887 | // 2754: } |
| 9888 | 7, 0, // 2759: case 0x7: { |
| 9889 | OPC_SwitchField, 13, 1, // 2761: switch Inst[13] { |
| 9890 | 0, 7, // 2764: case 0x0: { |
| 9891 | OPC_CheckPredicate, 15, // 2766: check predicate 15 |
| 9892 | OPC_Decode, 145, 22, 167, 2, // 2768: decode to V6_vaddubsat_dv using decoder 295 |
| 9893 | // 2768: } |
| 9894 | 1, 0, // 2773: case 0x1: { |
| 9895 | OPC_CheckPredicate, 20, // 2775: check predicate 20 |
| 9896 | OPC_CheckField, 16, 5, 6, // 2777: check Inst[20:16] == 0x6 |
| 9897 | OPC_Decode, 180, 23, 168, 2, // 2781: decode to V6_vfneg_f8 using decoder 296 |
| 9898 | // 2781: } |
| 9899 | // 2781: } // switch Inst[13] |
| 9900 | // 2781: } |
| 9901 | // 2781: } // switch Inst[7:5] |
| 9902 | // 2781: } |
| 9903 | 4, 176, 4, // 2786: case 0x4: { |
| 9904 | OPC_SwitchField, 5, 3, // 2789: switch Inst[7:5] { |
| 9905 | 0, 89, // 2792: case 0x0: { |
| 9906 | OPC_SwitchField, 13, 1, // 2794: switch Inst[13] { |
| 9907 | 0, 7, // 2797: case 0x0: { |
| 9908 | OPC_CheckPredicate, 15, // 2799: check predicate 15 |
| 9909 | OPC_Decode, 148, 22, 167, 2, // 2801: decode to V6_vadduhsat_dv using decoder 295 |
| 9910 | // 2801: } |
| 9911 | 1, 0, // 2806: case 0x1: { |
| 9912 | OPC_SwitchField, 2, 3, // 2808: switch Inst[4:2] { |
| 9913 | 0, 7, // 2811: case 0x0: { |
| 9914 | OPC_CheckPredicate, 15, // 2813: check predicate 15 |
| 9915 | OPC_Decode, 155, 23, 169, 2, // 2815: decode to V6_veqb_and using decoder 297 |
| 9916 | // 2815: } |
| 9917 | 1, 7, // 2820: case 0x1: { |
| 9918 | OPC_CheckPredicate, 15, // 2822: check predicate 15 |
| 9919 | OPC_Decode, 159, 23, 169, 2, // 2824: decode to V6_veqh_and using decoder 297 |
| 9920 | // 2824: } |
| 9921 | 2, 7, // 2829: case 0x2: { |
| 9922 | OPC_CheckPredicate, 15, // 2831: check predicate 15 |
| 9923 | OPC_Decode, 171, 23, 169, 2, // 2833: decode to V6_veqw_and using decoder 297 |
| 9924 | // 2833: } |
| 9925 | 3, 7, // 2838: case 0x3: { |
| 9926 | OPC_CheckPredicate, 18, // 2840: check predicate 18 |
| 9927 | OPC_Decode, 167, 23, 169, 2, // 2842: decode to V6_veqsf_and using decoder 297 |
| 9928 | // 2842: } |
| 9929 | 4, 7, // 2847: case 0x4: { |
| 9930 | OPC_CheckPredicate, 15, // 2849: check predicate 15 |
| 9931 | OPC_Decode, 190, 23, 169, 2, // 2851: decode to V6_vgtb_and using decoder 297 |
| 9932 | // 2851: } |
| 9933 | 5, 7, // 2856: case 0x5: { |
| 9934 | OPC_CheckPredicate, 15, // 2858: check predicate 15 |
| 9935 | OPC_Decode, 198, 23, 169, 2, // 2860: decode to V6_vgth_and using decoder 297 |
| 9936 | // 2860: } |
| 9937 | 6, 7, // 2865: case 0x6: { |
| 9938 | OPC_CheckPredicate, 15, // 2867: check predicate 15 |
| 9939 | OPC_Decode, 222, 23, 169, 2, // 2869: decode to V6_vgtw_and using decoder 297 |
| 9940 | // 2869: } |
| 9941 | 7, 0, // 2874: case 0x7: { |
| 9942 | OPC_CheckPredicate, 18, // 2876: check predicate 18 |
| 9943 | OPC_Decode, 163, 23, 169, 2, // 2878: decode to V6_veqhf_and using decoder 297 |
| 9944 | // 2878: } |
| 9945 | // 2878: } // switch Inst[4:2] |
| 9946 | // 2878: } |
| 9947 | // 2878: } // switch Inst[13] |
| 9948 | // 2878: } |
| 9949 | 1, 71, // 2883: case 0x1: { |
| 9950 | OPC_SwitchField, 13, 1, // 2885: switch Inst[13] { |
| 9951 | 0, 7, // 2888: case 0x0: { |
| 9952 | OPC_CheckPredicate, 15, // 2890: check predicate 15 |
| 9953 | OPC_Decode, 139, 22, 167, 2, // 2892: decode to V6_vaddhsat_dv using decoder 295 |
| 9954 | // 2892: } |
| 9955 | 1, 0, // 2897: case 0x1: { |
| 9956 | OPC_SwitchField, 2, 3, // 2899: switch Inst[4:2] { |
| 9957 | 0, 7, // 2902: case 0x0: { |
| 9958 | OPC_CheckPredicate, 15, // 2904: check predicate 15 |
| 9959 | OPC_Decode, 210, 23, 169, 2, // 2906: decode to V6_vgtub_and using decoder 297 |
| 9960 | // 2906: } |
| 9961 | 1, 7, // 2911: case 0x1: { |
| 9962 | OPC_CheckPredicate, 15, // 2913: check predicate 15 |
| 9963 | OPC_Decode, 214, 23, 169, 2, // 2915: decode to V6_vgtuh_and using decoder 297 |
| 9964 | // 2915: } |
| 9965 | 2, 7, // 2920: case 0x2: { |
| 9966 | OPC_CheckPredicate, 15, // 2922: check predicate 15 |
| 9967 | OPC_Decode, 218, 23, 169, 2, // 2924: decode to V6_vgtuw_and using decoder 297 |
| 9968 | // 2924: } |
| 9969 | 4, 7, // 2929: case 0x4: { |
| 9970 | OPC_CheckPredicate, 22, // 2931: check predicate 22 |
| 9971 | OPC_Decode, 207, 23, 169, 2, // 2933: decode to V6_vgtsf_or using decoder 297 |
| 9972 | // 2933: } |
| 9973 | 5, 7, // 2938: case 0x5: { |
| 9974 | OPC_CheckPredicate, 22, // 2940: check predicate 22 |
| 9975 | OPC_Decode, 203, 23, 169, 2, // 2942: decode to V6_vgthf_or using decoder 297 |
| 9976 | // 2942: } |
| 9977 | 6, 0, // 2947: case 0x6: { |
| 9978 | OPC_CheckPredicate, 23, // 2949: check predicate 23 |
| 9979 | OPC_Decode, 195, 23, 169, 2, // 2951: decode to V6_vgtbf_or using decoder 297 |
| 9980 | // 2951: } |
| 9981 | // 2951: } // switch Inst[4:2] |
| 9982 | // 2951: } |
| 9983 | // 2951: } // switch Inst[13] |
| 9984 | // 2951: } |
| 9985 | 2, 89, // 2956: case 0x2: { |
| 9986 | OPC_SwitchField, 13, 1, // 2958: switch Inst[13] { |
| 9987 | 0, 7, // 2961: case 0x0: { |
| 9988 | OPC_CheckPredicate, 15, // 2963: check predicate 15 |
| 9989 | OPC_Decode, 158, 22, 167, 2, // 2965: decode to V6_vaddwsat_dv using decoder 295 |
| 9990 | // 2965: } |
| 9991 | 1, 0, // 2970: case 0x1: { |
| 9992 | OPC_SwitchField, 2, 3, // 2972: switch Inst[4:2] { |
| 9993 | 0, 7, // 2975: case 0x0: { |
| 9994 | OPC_CheckPredicate, 15, // 2977: check predicate 15 |
| 9995 | OPC_Decode, 156, 23, 169, 2, // 2979: decode to V6_veqb_or using decoder 297 |
| 9996 | // 2979: } |
| 9997 | 1, 7, // 2984: case 0x1: { |
| 9998 | OPC_CheckPredicate, 15, // 2986: check predicate 15 |
| 9999 | OPC_Decode, 160, 23, 169, 2, // 2988: decode to V6_veqh_or using decoder 297 |
| 10000 | // 2988: } |
| 10001 | 2, 7, // 2993: case 0x2: { |
| 10002 | OPC_CheckPredicate, 15, // 2995: check predicate 15 |
| 10003 | OPC_Decode, 172, 23, 169, 2, // 2997: decode to V6_veqw_or using decoder 297 |
| 10004 | // 2997: } |
| 10005 | 3, 7, // 3002: case 0x3: { |
| 10006 | OPC_CheckPredicate, 18, // 3004: check predicate 18 |
| 10007 | OPC_Decode, 168, 23, 169, 2, // 3006: decode to V6_veqsf_or using decoder 297 |
| 10008 | // 3006: } |
| 10009 | 4, 7, // 3011: case 0x4: { |
| 10010 | OPC_CheckPredicate, 15, // 3013: check predicate 15 |
| 10011 | OPC_Decode, 191, 23, 169, 2, // 3015: decode to V6_vgtb_or using decoder 297 |
| 10012 | // 3015: } |
| 10013 | 5, 7, // 3020: case 0x5: { |
| 10014 | OPC_CheckPredicate, 15, // 3022: check predicate 15 |
| 10015 | OPC_Decode, 199, 23, 169, 2, // 3024: decode to V6_vgth_or using decoder 297 |
| 10016 | // 3024: } |
| 10017 | 6, 7, // 3029: case 0x6: { |
| 10018 | OPC_CheckPredicate, 15, // 3031: check predicate 15 |
| 10019 | OPC_Decode, 223, 23, 169, 2, // 3033: decode to V6_vgtw_or using decoder 297 |
| 10020 | // 3033: } |
| 10021 | 7, 0, // 3038: case 0x7: { |
| 10022 | OPC_CheckPredicate, 18, // 3040: check predicate 18 |
| 10023 | OPC_Decode, 164, 23, 169, 2, // 3042: decode to V6_veqhf_or using decoder 297 |
| 10024 | // 3042: } |
| 10025 | // 3042: } // switch Inst[4:2] |
| 10026 | // 3042: } |
| 10027 | // 3042: } // switch Inst[13] |
| 10028 | // 3042: } |
| 10029 | 3, 71, // 3047: case 0x3: { |
| 10030 | OPC_SwitchField, 13, 1, // 3049: switch Inst[13] { |
| 10031 | 0, 7, // 3052: case 0x0: { |
| 10032 | OPC_CheckPredicate, 15, // 3054: check predicate 15 |
| 10033 | OPC_Decode, 208, 25, 167, 2, // 3056: decode to V6_vsubb_dv using decoder 295 |
| 10034 | // 3056: } |
| 10035 | 1, 0, // 3061: case 0x1: { |
| 10036 | OPC_SwitchField, 2, 3, // 3063: switch Inst[4:2] { |
| 10037 | 0, 7, // 3066: case 0x0: { |
| 10038 | OPC_CheckPredicate, 15, // 3068: check predicate 15 |
| 10039 | OPC_Decode, 211, 23, 169, 2, // 3070: decode to V6_vgtub_or using decoder 297 |
| 10040 | // 3070: } |
| 10041 | 1, 7, // 3075: case 0x1: { |
| 10042 | OPC_CheckPredicate, 15, // 3077: check predicate 15 |
| 10043 | OPC_Decode, 215, 23, 169, 2, // 3079: decode to V6_vgtuh_or using decoder 297 |
| 10044 | // 3079: } |
| 10045 | 2, 7, // 3084: case 0x2: { |
| 10046 | OPC_CheckPredicate, 15, // 3086: check predicate 15 |
| 10047 | OPC_Decode, 219, 23, 169, 2, // 3088: decode to V6_vgtuw_or using decoder 297 |
| 10048 | // 3088: } |
| 10049 | 4, 7, // 3093: case 0x4: { |
| 10050 | OPC_CheckPredicate, 22, // 3095: check predicate 22 |
| 10051 | OPC_Decode, 205, 23, 170, 2, // 3097: decode to V6_vgtsf using decoder 298 |
| 10052 | // 3097: } |
| 10053 | 5, 7, // 3102: case 0x5: { |
| 10054 | OPC_CheckPredicate, 22, // 3104: check predicate 22 |
| 10055 | OPC_Decode, 201, 23, 170, 2, // 3106: decode to V6_vgthf using decoder 298 |
| 10056 | // 3106: } |
| 10057 | 6, 0, // 3111: case 0x6: { |
| 10058 | OPC_CheckPredicate, 23, // 3113: check predicate 23 |
| 10059 | OPC_Decode, 193, 23, 170, 2, // 3115: decode to V6_vgtbf using decoder 298 |
| 10060 | // 3115: } |
| 10061 | // 3115: } // switch Inst[4:2] |
| 10062 | // 3115: } |
| 10063 | // 3115: } // switch Inst[13] |
| 10064 | // 3115: } |
| 10065 | 4, 89, // 3120: case 0x4: { |
| 10066 | OPC_SwitchField, 13, 1, // 3122: switch Inst[13] { |
| 10067 | 0, 7, // 3125: case 0x0: { |
| 10068 | OPC_CheckPredicate, 15, // 3127: check predicate 15 |
| 10069 | OPC_Decode, 216, 25, 167, 2, // 3129: decode to V6_vsubh_dv using decoder 295 |
| 10070 | // 3129: } |
| 10071 | 1, 0, // 3134: case 0x1: { |
| 10072 | OPC_SwitchField, 2, 3, // 3136: switch Inst[4:2] { |
| 10073 | 0, 7, // 3139: case 0x0: { |
| 10074 | OPC_CheckPredicate, 15, // 3141: check predicate 15 |
| 10075 | OPC_Decode, 157, 23, 169, 2, // 3143: decode to V6_veqb_xor using decoder 297 |
| 10076 | // 3143: } |
| 10077 | 1, 7, // 3148: case 0x1: { |
| 10078 | OPC_CheckPredicate, 15, // 3150: check predicate 15 |
| 10079 | OPC_Decode, 161, 23, 169, 2, // 3152: decode to V6_veqh_xor using decoder 297 |
| 10080 | // 3152: } |
| 10081 | 2, 7, // 3157: case 0x2: { |
| 10082 | OPC_CheckPredicate, 15, // 3159: check predicate 15 |
| 10083 | OPC_Decode, 173, 23, 169, 2, // 3161: decode to V6_veqw_xor using decoder 297 |
| 10084 | // 3161: } |
| 10085 | 3, 7, // 3166: case 0x3: { |
| 10086 | OPC_CheckPredicate, 18, // 3168: check predicate 18 |
| 10087 | OPC_Decode, 169, 23, 169, 2, // 3170: decode to V6_veqsf_xor using decoder 297 |
| 10088 | // 3170: } |
| 10089 | 4, 7, // 3175: case 0x4: { |
| 10090 | OPC_CheckPredicate, 15, // 3177: check predicate 15 |
| 10091 | OPC_Decode, 192, 23, 169, 2, // 3179: decode to V6_vgtb_xor using decoder 297 |
| 10092 | // 3179: } |
| 10093 | 5, 7, // 3184: case 0x5: { |
| 10094 | OPC_CheckPredicate, 15, // 3186: check predicate 15 |
| 10095 | OPC_Decode, 200, 23, 169, 2, // 3188: decode to V6_vgth_xor using decoder 297 |
| 10096 | // 3188: } |
| 10097 | 6, 7, // 3193: case 0x6: { |
| 10098 | OPC_CheckPredicate, 15, // 3195: check predicate 15 |
| 10099 | OPC_Decode, 224, 23, 169, 2, // 3197: decode to V6_vgtw_xor using decoder 297 |
| 10100 | // 3197: } |
| 10101 | 7, 0, // 3202: case 0x7: { |
| 10102 | OPC_CheckPredicate, 18, // 3204: check predicate 18 |
| 10103 | OPC_Decode, 165, 23, 169, 2, // 3206: decode to V6_veqhf_xor using decoder 297 |
| 10104 | // 3206: } |
| 10105 | // 3206: } // switch Inst[4:2] |
| 10106 | // 3206: } |
| 10107 | // 3206: } // switch Inst[13] |
| 10108 | // 3206: } |
| 10109 | 5, 44, // 3211: case 0x5: { |
| 10110 | OPC_SwitchField, 13, 1, // 3213: switch Inst[13] { |
| 10111 | 0, 7, // 3216: case 0x0: { |
| 10112 | OPC_CheckPredicate, 15, // 3218: check predicate 15 |
| 10113 | OPC_Decode, 232, 25, 167, 2, // 3220: decode to V6_vsubw_dv using decoder 295 |
| 10114 | // 3220: } |
| 10115 | 1, 0, // 3225: case 0x1: { |
| 10116 | OPC_SwitchField, 2, 3, // 3227: switch Inst[4:2] { |
| 10117 | 0, 7, // 3230: case 0x0: { |
| 10118 | OPC_CheckPredicate, 15, // 3232: check predicate 15 |
| 10119 | OPC_Decode, 212, 23, 169, 2, // 3234: decode to V6_vgtub_xor using decoder 297 |
| 10120 | // 3234: } |
| 10121 | 1, 7, // 3239: case 0x1: { |
| 10122 | OPC_CheckPredicate, 15, // 3241: check predicate 15 |
| 10123 | OPC_Decode, 216, 23, 169, 2, // 3243: decode to V6_vgtuh_xor using decoder 297 |
| 10124 | // 3243: } |
| 10125 | 2, 0, // 3248: case 0x2: { |
| 10126 | OPC_CheckPredicate, 15, // 3250: check predicate 15 |
| 10127 | OPC_Decode, 220, 23, 169, 2, // 3252: decode to V6_vgtuw_xor using decoder 297 |
| 10128 | // 3252: } |
| 10129 | // 3252: } // switch Inst[4:2] |
| 10130 | // 3252: } |
| 10131 | // 3252: } // switch Inst[13] |
| 10132 | // 3252: } |
| 10133 | 6, 44, // 3257: case 0x6: { |
| 10134 | OPC_SwitchField, 13, 1, // 3259: switch Inst[13] { |
| 10135 | 0, 7, // 3262: case 0x0: { |
| 10136 | OPC_CheckPredicate, 15, // 3264: check predicate 15 |
| 10137 | OPC_Decode, 224, 25, 167, 2, // 3266: decode to V6_vsububsat_dv using decoder 295 |
| 10138 | // 3266: } |
| 10139 | 1, 0, // 3271: case 0x1: { |
| 10140 | OPC_SwitchField, 2, 3, // 3273: switch Inst[4:2] { |
| 10141 | 2, 7, // 3276: case 0x2: { |
| 10142 | OPC_CheckPredicate, 22, // 3278: check predicate 22 |
| 10143 | OPC_Decode, 206, 23, 169, 2, // 3280: decode to V6_vgtsf_and using decoder 297 |
| 10144 | // 3280: } |
| 10145 | 3, 7, // 3285: case 0x3: { |
| 10146 | OPC_CheckPredicate, 22, // 3287: check predicate 22 |
| 10147 | OPC_Decode, 202, 23, 169, 2, // 3289: decode to V6_vgthf_and using decoder 297 |
| 10148 | // 3289: } |
| 10149 | 4, 0, // 3294: case 0x4: { |
| 10150 | OPC_CheckPredicate, 23, // 3296: check predicate 23 |
| 10151 | OPC_Decode, 194, 23, 169, 2, // 3298: decode to V6_vgtbf_and using decoder 297 |
| 10152 | // 3298: } |
| 10153 | // 3298: } // switch Inst[4:2] |
| 10154 | // 3298: } |
| 10155 | // 3298: } // switch Inst[13] |
| 10156 | // 3298: } |
| 10157 | 7, 0, // 3303: case 0x7: { |
| 10158 | OPC_SwitchField, 13, 1, // 3305: switch Inst[13] { |
| 10159 | 0, 7, // 3308: case 0x0: { |
| 10160 | OPC_CheckPredicate, 15, // 3310: check predicate 15 |
| 10161 | OPC_Decode, 227, 25, 167, 2, // 3312: decode to V6_vsubuhsat_dv using decoder 295 |
| 10162 | // 3312: } |
| 10163 | 1, 0, // 3317: case 0x1: { |
| 10164 | OPC_SwitchField, 2, 3, // 3319: switch Inst[4:2] { |
| 10165 | 2, 7, // 3322: case 0x2: { |
| 10166 | OPC_CheckPredicate, 22, // 3324: check predicate 22 |
| 10167 | OPC_Decode, 208, 23, 169, 2, // 3326: decode to V6_vgtsf_xor using decoder 297 |
| 10168 | // 3326: } |
| 10169 | 3, 7, // 3331: case 0x3: { |
| 10170 | OPC_CheckPredicate, 22, // 3333: check predicate 22 |
| 10171 | OPC_Decode, 204, 23, 169, 2, // 3335: decode to V6_vgthf_xor using decoder 297 |
| 10172 | // 3335: } |
| 10173 | 4, 0, // 3340: case 0x4: { |
| 10174 | OPC_CheckPredicate, 23, // 3342: check predicate 23 |
| 10175 | OPC_Decode, 196, 23, 169, 2, // 3344: decode to V6_vgtbf_xor using decoder 297 |
| 10176 | // 3344: } |
| 10177 | // 3344: } // switch Inst[4:2] |
| 10178 | // 3344: } |
| 10179 | // 3344: } // switch Inst[13] |
| 10180 | // 3344: } |
| 10181 | // 3344: } // switch Inst[7:5] |
| 10182 | // 3344: } |
| 10183 | 5, 113, // 3349: case 0x5: { |
| 10184 | OPC_SwitchField, 7, 1, // 3351: switch Inst[7] { |
| 10185 | 0, 53, // 3354: case 0x0: { |
| 10186 | OPC_SwitchField, 13, 1, // 3356: switch Inst[13] { |
| 10187 | 0, 39, // 3359: case 0x0: { |
| 10188 | OPC_SwitchField, 5, 2, // 3361: switch Inst[6:5] { |
| 10189 | 0, 7, // 3364: case 0x0: { |
| 10190 | OPC_CheckPredicate, 15, // 3366: check predicate 15 |
| 10191 | OPC_Decode, 220, 25, 167, 2, // 3368: decode to V6_vsubhsat_dv using decoder 295 |
| 10192 | // 3368: } |
| 10193 | 1, 7, // 3373: case 0x1: { |
| 10194 | OPC_CheckPredicate, 15, // 3375: check predicate 15 |
| 10195 | OPC_Decode, 236, 25, 167, 2, // 3377: decode to V6_vsubwsat_dv using decoder 295 |
| 10196 | // 3377: } |
| 10197 | 2, 7, // 3382: case 0x2: { |
| 10198 | OPC_CheckPredicate, 15, // 3384: check predicate 15 |
| 10199 | OPC_Decode, 142, 22, 166, 2, // 3386: decode to V6_vaddubh using decoder 294 |
| 10200 | // 3386: } |
| 10201 | 3, 0, // 3391: case 0x3: { |
| 10202 | OPC_CheckPredicate, 15, // 3393: check predicate 15 |
| 10203 | OPC_Decode, 149, 22, 166, 2, // 3395: decode to V6_vadduhw using decoder 294 |
| 10204 | // 3395: } |
| 10205 | // 3395: } // switch Inst[6:5] |
| 10206 | // 3395: } |
| 10207 | 1, 0, // 3400: case 0x1: { |
| 10208 | OPC_CheckPredicate, 12, // 3402: check predicate 12 |
| 10209 | OPC_Decode, 129, 22, 171, 2, // 3404: decode to V6_vaddcarry using decoder 299 |
| 10210 | // 3404: } |
| 10211 | // 3404: } // switch Inst[13] |
| 10212 | // 3404: } |
| 10213 | 1, 0, // 3409: case 0x1: { |
| 10214 | OPC_SwitchField, 13, 1, // 3411: switch Inst[13] { |
| 10215 | 0, 39, // 3414: case 0x0: { |
| 10216 | OPC_SwitchField, 5, 2, // 3416: switch Inst[6:5] { |
| 10217 | 0, 7, // 3419: case 0x0: { |
| 10218 | OPC_CheckPredicate, 15, // 3421: check predicate 15 |
| 10219 | OPC_Decode, 140, 22, 166, 2, // 3423: decode to V6_vaddhw using decoder 294 |
| 10220 | // 3423: } |
| 10221 | 1, 7, // 3428: case 0x1: { |
| 10222 | OPC_CheckPredicate, 15, // 3430: check predicate 15 |
| 10223 | OPC_Decode, 222, 25, 166, 2, // 3432: decode to V6_vsububh using decoder 294 |
| 10224 | // 3432: } |
| 10225 | 2, 7, // 3437: case 0x2: { |
| 10226 | OPC_CheckPredicate, 15, // 3439: check predicate 15 |
| 10227 | OPC_Decode, 228, 25, 166, 2, // 3441: decode to V6_vsubuhw using decoder 294 |
| 10228 | // 3441: } |
| 10229 | 3, 0, // 3446: case 0x3: { |
| 10230 | OPC_CheckPredicate, 15, // 3448: check predicate 15 |
| 10231 | OPC_Decode, 221, 25, 166, 2, // 3450: decode to V6_vsubhw using decoder 294 |
| 10232 | // 3450: } |
| 10233 | // 3450: } // switch Inst[6:5] |
| 10234 | // 3450: } |
| 10235 | 1, 0, // 3455: case 0x1: { |
| 10236 | OPC_CheckPredicate, 12, // 3457: check predicate 12 |
| 10237 | OPC_Decode, 213, 25, 171, 2, // 3459: decode to V6_vsubcarry using decoder 299 |
| 10238 | // 3459: } |
| 10239 | // 3459: } // switch Inst[13] |
| 10240 | // 3459: } |
| 10241 | // 3459: } // switch Inst[7] |
| 10242 | // 3459: } |
| 10243 | 6, 89, // 3464: case 0x6: { |
| 10244 | OPC_SwitchField, 13, 1, // 3466: switch Inst[13] { |
| 10245 | 0, 75, // 3469: case 0x0: { |
| 10246 | OPC_SwitchField, 5, 3, // 3471: switch Inst[7:5] { |
| 10247 | 0, 7, // 3474: case 0x0: { |
| 10248 | OPC_CheckPredicate, 15, // 3476: check predicate 15 |
| 10249 | OPC_Decode, 233, 21, 160, 2, // 3478: decode to V6_vabsdiffub using decoder 288 |
| 10250 | // 3478: } |
| 10251 | 1, 7, // 3483: case 0x1: { |
| 10252 | OPC_CheckPredicate, 15, // 3485: check predicate 15 |
| 10253 | OPC_Decode, 232, 21, 160, 2, // 3487: decode to V6_vabsdiffh using decoder 288 |
| 10254 | // 3487: } |
| 10255 | 2, 7, // 3492: case 0x2: { |
| 10256 | OPC_CheckPredicate, 15, // 3494: check predicate 15 |
| 10257 | OPC_Decode, 234, 21, 160, 2, // 3496: decode to V6_vabsdiffuh using decoder 288 |
| 10258 | // 3496: } |
| 10259 | 3, 7, // 3501: case 0x3: { |
| 10260 | OPC_CheckPredicate, 15, // 3503: check predicate 15 |
| 10261 | OPC_Decode, 235, 21, 160, 2, // 3505: decode to V6_vabsdiffw using decoder 288 |
| 10262 | // 3505: } |
| 10263 | 4, 7, // 3510: case 0x4: { |
| 10264 | OPC_CheckPredicate, 15, // 3512: check predicate 15 |
| 10265 | OPC_Decode, 208, 22, 160, 2, // 3514: decode to V6_vavgub using decoder 288 |
| 10266 | // 3514: } |
| 10267 | 5, 7, // 3519: case 0x5: { |
| 10268 | OPC_CheckPredicate, 15, // 3521: check predicate 15 |
| 10269 | OPC_Decode, 210, 22, 160, 2, // 3523: decode to V6_vavguh using decoder 288 |
| 10270 | // 3523: } |
| 10271 | 6, 7, // 3528: case 0x6: { |
| 10272 | OPC_CheckPredicate, 15, // 3530: check predicate 15 |
| 10273 | OPC_Decode, 206, 22, 160, 2, // 3532: decode to V6_vavgh using decoder 288 |
| 10274 | // 3532: } |
| 10275 | 7, 0, // 3537: case 0x7: { |
| 10276 | OPC_CheckPredicate, 15, // 3539: check predicate 15 |
| 10277 | OPC_Decode, 214, 22, 160, 2, // 3541: decode to V6_vavgw using decoder 288 |
| 10278 | // 3541: } |
| 10279 | // 3541: } // switch Inst[7:5] |
| 10280 | // 3541: } |
| 10281 | 1, 0, // 3546: case 0x1: { |
| 10282 | OPC_CheckPredicate, 12, // 3548: check predicate 12 |
| 10283 | OPC_Decode, 243, 23, 172, 2, // 3550: decode to V6_vlutvvb_oracci using decoder 300 |
| 10284 | // 3550: } |
| 10285 | // 3550: } // switch Inst[13] |
| 10286 | // 3550: } |
| 10287 | 7, 0, // 3555: case 0x7: { |
| 10288 | OPC_SwitchField, 13, 1, // 3557: switch Inst[13] { |
| 10289 | 0, 75, // 3560: case 0x0: { |
| 10290 | OPC_SwitchField, 5, 3, // 3562: switch Inst[7:5] { |
| 10291 | 0, 7, // 3565: case 0x0: { |
| 10292 | OPC_CheckPredicate, 15, // 3567: check predicate 15 |
| 10293 | OPC_Decode, 224, 24, 160, 2, // 3569: decode to V6_vnavgub using decoder 288 |
| 10294 | // 3569: } |
| 10295 | 1, 7, // 3574: case 0x1: { |
| 10296 | OPC_CheckPredicate, 15, // 3576: check predicate 15 |
| 10297 | OPC_Decode, 223, 24, 160, 2, // 3578: decode to V6_vnavgh using decoder 288 |
| 10298 | // 3578: } |
| 10299 | 2, 7, // 3583: case 0x2: { |
| 10300 | OPC_CheckPredicate, 15, // 3585: check predicate 15 |
| 10301 | OPC_Decode, 225, 24, 160, 2, // 3587: decode to V6_vnavgw using decoder 288 |
| 10302 | // 3587: } |
| 10303 | 3, 7, // 3592: case 0x3: { |
| 10304 | OPC_CheckPredicate, 15, // 3594: check predicate 15 |
| 10305 | OPC_Decode, 209, 22, 160, 2, // 3596: decode to V6_vavgubrnd using decoder 288 |
| 10306 | // 3596: } |
| 10307 | 4, 7, // 3601: case 0x4: { |
| 10308 | OPC_CheckPredicate, 15, // 3603: check predicate 15 |
| 10309 | OPC_Decode, 211, 22, 160, 2, // 3605: decode to V6_vavguhrnd using decoder 288 |
| 10310 | // 3605: } |
| 10311 | 5, 7, // 3610: case 0x5: { |
| 10312 | OPC_CheckPredicate, 15, // 3612: check predicate 15 |
| 10313 | OPC_Decode, 207, 22, 160, 2, // 3614: decode to V6_vavghrnd using decoder 288 |
| 10314 | // 3614: } |
| 10315 | 6, 7, // 3619: case 0x6: { |
| 10316 | OPC_CheckPredicate, 15, // 3621: check predicate 15 |
| 10317 | OPC_Decode, 215, 22, 160, 2, // 3623: decode to V6_vavgwrnd using decoder 288 |
| 10318 | // 3623: } |
| 10319 | 7, 0, // 3628: case 0x7: { |
| 10320 | OPC_CheckPredicate, 15, // 3630: check predicate 15 |
| 10321 | OPC_Decode, 144, 24, 167, 2, // 3632: decode to V6_vmpabuuv using decoder 295 |
| 10322 | // 3632: } |
| 10323 | // 3632: } // switch Inst[7:5] |
| 10324 | // 3632: } |
| 10325 | 1, 0, // 3637: case 0x1: { |
| 10326 | OPC_CheckPredicate, 12, // 3639: check predicate 12 |
| 10327 | OPC_Decode, 248, 23, 173, 2, // 3641: decode to V6_vlutvwh_oracci using decoder 301 |
| 10328 | // 3641: } |
| 10329 | // 3641: } // switch Inst[13] |
| 10330 | // 3641: } |
| 10331 | // 3641: } // switch Inst[23:21] |
| 10332 | // 3641: } |
| 10333 | 29, 219, 1, // 3646: case 0x1d: { |
| 10334 | OPC_SwitchField, 21, 3, // 3649: switch Inst[23:21] { |
| 10335 | 0, 65, // 3652: case 0x0: { |
| 10336 | OPC_SwitchField, 5, 3, // 3654: switch Inst[7:5] { |
| 10337 | 0, 21, // 3657: case 0x0: { |
| 10338 | OPC_SwitchField, 13, 1, // 3659: switch Inst[13] { |
| 10339 | 0, 7, // 3662: case 0x0: { |
| 10340 | OPC_CheckPredicate, 24, // 3664: check predicate 24 |
| 10341 | OPC_Decode, 192, 22, 174, 2, // 3666: decode to V6_vasrvwuhsat using decoder 302 |
| 10342 | // 3666: } |
| 10343 | 1, 0, // 3671: case 0x1: { |
| 10344 | OPC_CheckPredicate, 25, // 3673: check predicate 25 |
| 10345 | OPC_Decode, 168, 24, 162, 2, // 3675: decode to V6_vmpy_sf_bf_acc using decoder 290 |
| 10346 | // 3675: } |
| 10347 | // 3675: } // switch Inst[13] |
| 10348 | // 3675: } |
| 10349 | 1, 11, // 3680: case 0x1: { |
| 10350 | OPC_CheckPredicate, 24, // 3682: check predicate 24 |
| 10351 | OPC_CheckField, 13, 1, 0, // 3684: check Inst[13] == 0x0 |
| 10352 | OPC_Decode, 191, 22, 174, 2, // 3688: decode to V6_vasrvwuhrndsat using decoder 302 |
| 10353 | // 3688: } |
| 10354 | 2, 11, // 3693: case 0x2: { |
| 10355 | OPC_CheckPredicate, 24, // 3695: check predicate 24 |
| 10356 | OPC_CheckField, 13, 1, 0, // 3697: check Inst[13] == 0x0 |
| 10357 | OPC_Decode, 190, 22, 174, 2, // 3701: decode to V6_vasrvuhubsat using decoder 302 |
| 10358 | // 3701: } |
| 10359 | 3, 0, // 3706: case 0x3: { |
| 10360 | OPC_CheckPredicate, 24, // 3708: check predicate 24 |
| 10361 | OPC_CheckField, 13, 1, 0, // 3710: check Inst[13] == 0x0 |
| 10362 | OPC_Decode, 189, 22, 174, 2, // 3714: decode to V6_vasrvuhubrndsat using decoder 302 |
| 10363 | // 3714: } |
| 10364 | // 3714: } // switch Inst[7:5] |
| 10365 | // 3714: } |
| 10366 | 2, 81, // 3719: case 0x2: { |
| 10367 | OPC_SwitchField, 5, 3, // 3721: switch Inst[7:5] { |
| 10368 | 0, 11, // 3724: case 0x0: { |
| 10369 | OPC_CheckPredicate, 25, // 3726: check predicate 25 |
| 10370 | OPC_CheckField, 13, 1, 1, // 3728: check Inst[13] == 0x1 |
| 10371 | OPC_Decode, 131, 24, 160, 2, // 3732: decode to V6_vmin_bf using decoder 288 |
| 10372 | // 3732: } |
| 10373 | 3, 11, // 3737: case 0x3: { |
| 10374 | OPC_CheckPredicate, 25, // 3739: check predicate 25 |
| 10375 | OPC_CheckField, 13, 1, 1, // 3741: check Inst[13] == 0x1 |
| 10376 | OPC_Decode, 242, 22, 160, 2, // 3745: decode to V6_vcvt_bf_sf using decoder 288 |
| 10377 | // 3745: } |
| 10378 | 4, 11, // 3750: case 0x4: { |
| 10379 | OPC_CheckPredicate, 25, // 3752: check predicate 25 |
| 10380 | OPC_CheckField, 13, 1, 1, // 3754: check Inst[13] == 0x1 |
| 10381 | OPC_Decode, 167, 24, 166, 2, // 3758: decode to V6_vmpy_sf_bf using decoder 294 |
| 10382 | // 3758: } |
| 10383 | 5, 11, // 3763: case 0x5: { |
| 10384 | OPC_CheckPredicate, 25, // 3765: check predicate 25 |
| 10385 | OPC_CheckField, 13, 1, 1, // 3767: check Inst[13] == 0x1 |
| 10386 | OPC_Decode, 203, 25, 166, 2, // 3771: decode to V6_vsub_sf_bf using decoder 294 |
| 10387 | // 3771: } |
| 10388 | 6, 11, // 3776: case 0x6: { |
| 10389 | OPC_CheckPredicate, 25, // 3778: check predicate 25 |
| 10390 | OPC_CheckField, 13, 1, 1, // 3780: check Inst[13] == 0x1 |
| 10391 | OPC_Decode, 248, 21, 166, 2, // 3784: decode to V6_vadd_sf_bf using decoder 294 |
| 10392 | // 3784: } |
| 10393 | 7, 0, // 3789: case 0x7: { |
| 10394 | OPC_CheckPredicate, 25, // 3791: check predicate 25 |
| 10395 | OPC_CheckField, 13, 1, 1, // 3793: check Inst[13] == 0x1 |
| 10396 | OPC_Decode, 250, 23, 160, 2, // 3797: decode to V6_vmax_bf using decoder 288 |
| 10397 | // 3797: } |
| 10398 | // 3797: } // switch Inst[7:5] |
| 10399 | // 3797: } |
| 10400 | 4, 33, // 3802: case 0x4: { |
| 10401 | OPC_SwitchField, 7, 1, // 3804: switch Inst[7] { |
| 10402 | 0, 11, // 3807: case 0x0: { |
| 10403 | OPC_CheckPredicate, 19, // 3809: check predicate 19 |
| 10404 | OPC_CheckField, 13, 1, 1, // 3811: check Inst[13] == 0x1 |
| 10405 | OPC_Decode, 131, 22, 175, 2, // 3815: decode to V6_vaddcarrysat using decoder 303 |
| 10406 | // 3815: } |
| 10407 | 1, 0, // 3820: case 0x1: { |
| 10408 | OPC_CheckPredicate, 19, // 3822: check predicate 19 |
| 10409 | OPC_CheckField, 13, 1, 1, // 3824: check Inst[13] == 0x1 |
| 10410 | OPC_CheckField, 5, 2, 3, // 3828: check Inst[6:5] == 0x3 |
| 10411 | OPC_Decode, 169, 25, 160, 2, // 3832: decode to V6_vsatdw using decoder 288 |
| 10412 | // 3832: } |
| 10413 | // 3832: } // switch Inst[7] |
| 10414 | // 3832: } |
| 10415 | 5, 0, // 3837: case 0x5: { |
| 10416 | OPC_SwitchField, 7, 1, // 3839: switch Inst[7] { |
| 10417 | 0, 11, // 3842: case 0x0: { |
| 10418 | OPC_CheckPredicate, 19, // 3844: check predicate 19 |
| 10419 | OPC_CheckField, 13, 1, 1, // 3846: check Inst[13] == 0x1 |
| 10420 | OPC_Decode, 130, 22, 176, 2, // 3850: decode to V6_vaddcarryo using decoder 304 |
| 10421 | // 3850: } |
| 10422 | 1, 0, // 3855: case 0x1: { |
| 10423 | OPC_CheckPredicate, 19, // 3857: check predicate 19 |
| 10424 | OPC_CheckField, 13, 1, 1, // 3859: check Inst[13] == 0x1 |
| 10425 | OPC_Decode, 214, 25, 176, 2, // 3863: decode to V6_vsubcarryo using decoder 304 |
| 10426 | // 3863: } |
| 10427 | // 3863: } // switch Inst[7] |
| 10428 | // 3863: } |
| 10429 | // 3863: } // switch Inst[23:21] |
| 10430 | // 3863: } |
| 10431 | 30, 227, 12, // 3868: case 0x1e: { |
| 10432 | OPC_SwitchField, 13, 1, // 3871: switch Inst[13] { |
| 10433 | 0, 204, 4, // 3874: case 0x0: { |
| 10434 | OPC_SwitchField, 21, 1, // 3877: switch Inst[21] { |
| 10435 | 0, 226, 3, // 3880: case 0x0: { |
| 10436 | OPC_SwitchField, 5, 3, // 3883: switch Inst[7:5] { |
| 10437 | 0, 155, 1, // 3886: case 0x0: { |
| 10438 | OPC_SwitchField, 16, 5, // 3889: switch Inst[20:16] { |
| 10439 | 0, 11, // 3892: case 0x0: { |
| 10440 | OPC_CheckPredicate, 15, // 3894: check predicate 15 |
| 10441 | OPC_CheckField, 22, 2, 0, // 3896: check Inst[23:22] == 0x0 |
| 10442 | OPC_Decode, 236, 21, 168, 2, // 3900: decode to V6_vabsh using decoder 296 |
| 10443 | // 3900: } |
| 10444 | 1, 11, // 3905: case 0x1: { |
| 10445 | OPC_CheckPredicate, 15, // 3907: check predicate 15 |
| 10446 | OPC_CheckField, 22, 2, 0, // 3909: check Inst[23:22] == 0x0 |
| 10447 | OPC_Decode, 248, 25, 177, 2, // 3913: decode to V6_vunpackub using decoder 305 |
| 10448 | // 3913: } |
| 10449 | 2, 11, // 3918: case 0x2: { |
| 10450 | OPC_CheckPredicate, 15, // 3920: check predicate 15 |
| 10451 | OPC_CheckField, 22, 2, 0, // 3922: check Inst[23:22] == 0x0 |
| 10452 | OPC_Decode, 186, 25, 168, 2, // 3926: decode to V6_vshuffb using decoder 296 |
| 10453 | // 3926: } |
| 10454 | 3, 0, // 3931: case 0x3: { |
| 10455 | OPC_SwitchField, 2, 3, // 3933: switch Inst[4:2] { |
| 10456 | 0, 11, // 3936: case 0x0: { |
| 10457 | OPC_CheckPredicate, 15, // 3938: check predicate 15 |
| 10458 | OPC_CheckField, 10, 3, 0, // 3940: check Inst[12:10] == 0x0 |
| 10459 | OPC_Decode, 219, 20, 178, 2, // 3944: decode to V6_pred_and using decoder 306 |
| 10460 | // 3944: } |
| 10461 | 1, 11, // 3949: case 0x1: { |
| 10462 | OPC_CheckPredicate, 15, // 3951: check predicate 15 |
| 10463 | OPC_CheckField, 10, 3, 0, // 3953: check Inst[12:10] == 0x0 |
| 10464 | OPC_Decode, 222, 20, 178, 2, // 3957: decode to V6_pred_or using decoder 306 |
| 10465 | // 3957: } |
| 10466 | 2, 15, // 3962: case 0x2: { |
| 10467 | OPC_CheckPredicate, 15, // 3964: check predicate 15 |
| 10468 | OPC_CheckField, 22, 2, 0, // 3966: check Inst[23:22] == 0x0 |
| 10469 | OPC_CheckField, 10, 3, 0, // 3970: check Inst[12:10] == 0x0 |
| 10470 | OPC_Decode, 221, 20, 179, 2, // 3974: decode to V6_pred_not using decoder 307 |
| 10471 | // 3974: } |
| 10472 | 3, 11, // 3979: case 0x3: { |
| 10473 | OPC_CheckPredicate, 15, // 3981: check predicate 15 |
| 10474 | OPC_CheckField, 10, 3, 0, // 3983: check Inst[12:10] == 0x0 |
| 10475 | OPC_Decode, 226, 20, 178, 2, // 3987: decode to V6_pred_xor using decoder 306 |
| 10476 | // 3987: } |
| 10477 | 4, 11, // 3992: case 0x4: { |
| 10478 | OPC_CheckPredicate, 15, // 3994: check predicate 15 |
| 10479 | OPC_CheckField, 10, 3, 0, // 3996: check Inst[12:10] == 0x0 |
| 10480 | OPC_Decode, 223, 20, 178, 2, // 4000: decode to V6_pred_or_n using decoder 306 |
| 10481 | // 4000: } |
| 10482 | 5, 11, // 4005: case 0x5: { |
| 10483 | OPC_CheckPredicate, 15, // 4007: check predicate 15 |
| 10484 | OPC_CheckField, 10, 3, 0, // 4009: check Inst[12:10] == 0x0 |
| 10485 | OPC_Decode, 220, 20, 178, 2, // 4013: decode to V6_pred_and_n using decoder 306 |
| 10486 | // 4013: } |
| 10487 | 6, 11, // 4018: case 0x6: { |
| 10488 | OPC_CheckPredicate, 12, // 4020: check predicate 12 |
| 10489 | OPC_CheckField, 10, 3, 0, // 4022: check Inst[12:10] == 0x0 |
| 10490 | OPC_Decode, 228, 20, 178, 2, // 4026: decode to V6_shuffeqh using decoder 306 |
| 10491 | // 4026: } |
| 10492 | 7, 0, // 4031: case 0x7: { |
| 10493 | OPC_CheckPredicate, 12, // 4033: check predicate 12 |
| 10494 | OPC_CheckField, 10, 3, 0, // 4035: check Inst[12:10] == 0x0 |
| 10495 | OPC_Decode, 229, 20, 178, 2, // 4039: decode to V6_shuffeqw using decoder 306 |
| 10496 | // 4039: } |
| 10497 | // 4039: } // switch Inst[4:2] |
| 10498 | // 4039: } |
| 10499 | // 4039: } // switch Inst[20:16] |
| 10500 | // 4039: } |
| 10501 | 1, 42, // 4044: case 0x1: { |
| 10502 | OPC_SwitchField, 16, 5, // 4046: switch Inst[20:16] { |
| 10503 | 0, 11, // 4049: case 0x0: { |
| 10504 | OPC_CheckPredicate, 15, // 4051: check predicate 15 |
| 10505 | OPC_CheckField, 22, 2, 0, // 4053: check Inst[23:22] == 0x0 |
| 10506 | OPC_Decode, 237, 21, 168, 2, // 4057: decode to V6_vabsh_sat using decoder 296 |
| 10507 | // 4057: } |
| 10508 | 1, 11, // 4062: case 0x1: { |
| 10509 | OPC_CheckPredicate, 15, // 4064: check predicate 15 |
| 10510 | OPC_CheckField, 22, 2, 0, // 4066: check Inst[23:22] == 0x0 |
| 10511 | OPC_Decode, 249, 25, 177, 2, // 4070: decode to V6_vunpackuh using decoder 305 |
| 10512 | // 4070: } |
| 10513 | 2, 0, // 4075: case 0x2: { |
| 10514 | OPC_CheckPredicate, 15, // 4077: check predicate 15 |
| 10515 | OPC_CheckField, 22, 2, 0, // 4079: check Inst[23:22] == 0x0 |
| 10516 | OPC_Decode, 131, 26, 177, 2, // 4083: decode to V6_vzb using decoder 305 |
| 10517 | // 4083: } |
| 10518 | // 4083: } // switch Inst[20:16] |
| 10519 | // 4083: } |
| 10520 | 2, 42, // 4088: case 0x2: { |
| 10521 | OPC_SwitchField, 16, 5, // 4090: switch Inst[20:16] { |
| 10522 | 0, 11, // 4093: case 0x0: { |
| 10523 | OPC_CheckPredicate, 15, // 4095: check predicate 15 |
| 10524 | OPC_CheckField, 22, 2, 0, // 4097: check Inst[23:22] == 0x0 |
| 10525 | OPC_Decode, 238, 21, 168, 2, // 4101: decode to V6_vabsw using decoder 296 |
| 10526 | // 4101: } |
| 10527 | 1, 11, // 4106: case 0x1: { |
| 10528 | OPC_CheckPredicate, 15, // 4108: check predicate 15 |
| 10529 | OPC_CheckField, 22, 2, 0, // 4110: check Inst[23:22] == 0x0 |
| 10530 | OPC_Decode, 244, 25, 177, 2, // 4114: decode to V6_vunpackb using decoder 305 |
| 10531 | // 4114: } |
| 10532 | 2, 0, // 4119: case 0x2: { |
| 10533 | OPC_CheckPredicate, 15, // 4121: check predicate 15 |
| 10534 | OPC_CheckField, 22, 2, 0, // 4123: check Inst[23:22] == 0x0 |
| 10535 | OPC_Decode, 132, 26, 177, 2, // 4127: decode to V6_vzh using decoder 305 |
| 10536 | // 4127: } |
| 10537 | // 4127: } // switch Inst[20:16] |
| 10538 | // 4127: } |
| 10539 | 3, 42, // 4132: case 0x3: { |
| 10540 | OPC_SwitchField, 16, 5, // 4134: switch Inst[20:16] { |
| 10541 | 0, 11, // 4137: case 0x0: { |
| 10542 | OPC_CheckPredicate, 15, // 4139: check predicate 15 |
| 10543 | OPC_CheckField, 22, 2, 0, // 4141: check Inst[23:22] == 0x0 |
| 10544 | OPC_Decode, 239, 21, 168, 2, // 4145: decode to V6_vabsw_sat using decoder 296 |
| 10545 | // 4145: } |
| 10546 | 1, 11, // 4150: case 0x1: { |
| 10547 | OPC_CheckPredicate, 15, // 4152: check predicate 15 |
| 10548 | OPC_CheckField, 22, 2, 0, // 4154: check Inst[23:22] == 0x0 |
| 10549 | OPC_Decode, 245, 25, 177, 2, // 4158: decode to V6_vunpackh using decoder 305 |
| 10550 | // 4158: } |
| 10551 | 2, 0, // 4163: case 0x2: { |
| 10552 | OPC_CheckPredicate, 15, // 4165: check predicate 15 |
| 10553 | OPC_CheckField, 22, 2, 0, // 4167: check Inst[23:22] == 0x0 |
| 10554 | OPC_Decode, 173, 25, 177, 2, // 4171: decode to V6_vsb using decoder 305 |
| 10555 | // 4171: } |
| 10556 | // 4171: } // switch Inst[20:16] |
| 10557 | // 4171: } |
| 10558 | 4, 55, // 4176: case 0x4: { |
| 10559 | OPC_SwitchField, 16, 5, // 4178: switch Inst[20:16] { |
| 10560 | 0, 11, // 4181: case 0x0: { |
| 10561 | OPC_CheckPredicate, 15, // 4183: check predicate 15 |
| 10562 | OPC_CheckField, 22, 2, 0, // 4185: check Inst[23:22] == 0x0 |
| 10563 | OPC_Decode, 234, 24, 168, 2, // 4189: decode to V6_vnot using decoder 296 |
| 10564 | // 4189: } |
| 10565 | 1, 11, // 4194: case 0x1: { |
| 10566 | OPC_CheckPredicate, 13, // 4196: check predicate 13 |
| 10567 | OPC_CheckField, 22, 2, 0, // 4198: check Inst[23:22] == 0x0 |
| 10568 | OPC_Decode, 230, 21, 168, 2, // 4202: decode to V6_vabsb using decoder 296 |
| 10569 | // 4202: } |
| 10570 | 2, 11, // 4207: case 0x2: { |
| 10571 | OPC_CheckPredicate, 15, // 4209: check predicate 15 |
| 10572 | OPC_CheckField, 22, 2, 0, // 4211: check Inst[23:22] == 0x0 |
| 10573 | OPC_Decode, 183, 25, 177, 2, // 4215: decode to V6_vsh using decoder 305 |
| 10574 | // 4215: } |
| 10575 | 3, 0, // 4220: case 0x3: { |
| 10576 | OPC_CheckPredicate, 15, // 4222: check predicate 15 |
| 10577 | OPC_CheckField, 22, 2, 0, // 4224: check Inst[23:22] == 0x0 |
| 10578 | OPC_Decode, 233, 24, 168, 2, // 4228: decode to V6_vnormamtw using decoder 296 |
| 10579 | // 4228: } |
| 10580 | // 4228: } // switch Inst[20:16] |
| 10581 | // 4228: } |
| 10582 | 5, 42, // 4233: case 0x5: { |
| 10583 | OPC_SwitchField, 16, 5, // 4235: switch Inst[20:16] { |
| 10584 | 1, 11, // 4238: case 0x1: { |
| 10585 | OPC_CheckPredicate, 13, // 4240: check predicate 13 |
| 10586 | OPC_CheckField, 22, 2, 0, // 4242: check Inst[23:22] == 0x0 |
| 10587 | OPC_Decode, 231, 21, 168, 2, // 4246: decode to V6_vabsb_sat using decoder 296 |
| 10588 | // 4246: } |
| 10589 | 2, 11, // 4251: case 0x2: { |
| 10590 | OPC_CheckPredicate, 15, // 4253: check predicate 15 |
| 10591 | OPC_CheckField, 22, 2, 0, // 4255: check Inst[23:22] == 0x0 |
| 10592 | OPC_Decode, 218, 22, 168, 2, // 4259: decode to V6_vcl0w using decoder 296 |
| 10593 | // 4259: } |
| 10594 | 3, 0, // 4264: case 0x3: { |
| 10595 | OPC_CheckPredicate, 15, // 4266: check predicate 15 |
| 10596 | OPC_CheckField, 22, 2, 0, // 4268: check Inst[23:22] == 0x0 |
| 10597 | OPC_Decode, 232, 24, 168, 2, // 4272: decode to V6_vnormamth using decoder 296 |
| 10598 | // 4272: } |
| 10599 | // 4272: } // switch Inst[20:16] |
| 10600 | // 4272: } |
| 10601 | 6, 42, // 4277: case 0x6: { |
| 10602 | OPC_SwitchField, 16, 5, // 4279: switch Inst[20:16] { |
| 10603 | 0, 11, // 4282: case 0x0: { |
| 10604 | OPC_CheckPredicate, 15, // 4284: check predicate 15 |
| 10605 | OPC_CheckField, 22, 2, 0, // 4286: check Inst[23:22] == 0x0 |
| 10606 | OPC_Decode, 129, 23, 168, 2, // 4290: decode to V6_vdealh using decoder 296 |
| 10607 | // 4290: } |
| 10608 | 1, 11, // 4295: case 0x1: { |
| 10609 | OPC_CheckPredicate, 24, // 4297: check predicate 24 |
| 10610 | OPC_CheckField, 22, 2, 0, // 4299: check Inst[23:22] == 0x0 |
| 10611 | OPC_Decode, 203, 22, 168, 2, // 4303: decode to V6_vassign_tmp using decoder 296 |
| 10612 | // 4303: } |
| 10613 | 2, 0, // 4308: case 0x2: { |
| 10614 | OPC_CheckPredicate, 15, // 4310: check predicate 15 |
| 10615 | OPC_CheckField, 22, 2, 0, // 4312: check Inst[23:22] == 0x0 |
| 10616 | OPC_Decode, 244, 24, 168, 2, // 4316: decode to V6_vpopcounth using decoder 296 |
| 10617 | // 4316: } |
| 10618 | // 4316: } // switch Inst[20:16] |
| 10619 | // 4316: } |
| 10620 | 7, 0, // 4321: case 0x7: { |
| 10621 | OPC_SwitchField, 16, 5, // 4323: switch Inst[20:16] { |
| 10622 | 0, 11, // 4326: case 0x0: { |
| 10623 | OPC_CheckPredicate, 15, // 4328: check predicate 15 |
| 10624 | OPC_CheckField, 22, 2, 0, // 4330: check Inst[23:22] == 0x0 |
| 10625 | OPC_Decode, 255, 22, 168, 2, // 4334: decode to V6_vdealb using decoder 296 |
| 10626 | // 4334: } |
| 10627 | 1, 11, // 4339: case 0x1: { |
| 10628 | OPC_CheckPredicate, 15, // 4341: check predicate 15 |
| 10629 | OPC_CheckField, 22, 2, 0, // 4343: check Inst[23:22] == 0x0 |
| 10630 | OPC_Decode, 188, 25, 168, 2, // 4347: decode to V6_vshuffh using decoder 296 |
| 10631 | // 4347: } |
| 10632 | 2, 0, // 4352: case 0x2: { |
| 10633 | OPC_CheckPredicate, 15, // 4354: check predicate 15 |
| 10634 | OPC_CheckField, 22, 2, 0, // 4356: check Inst[23:22] == 0x0 |
| 10635 | OPC_Decode, 217, 22, 168, 2, // 4360: decode to V6_vcl0h using decoder 296 |
| 10636 | // 4360: } |
| 10637 | // 4360: } // switch Inst[20:16] |
| 10638 | // 4360: } |
| 10639 | // 4360: } // switch Inst[7:5] |
| 10640 | // 4360: } |
| 10641 | 1, 0, // 4365: case 0x1: { |
| 10642 | OPC_SwitchField, 22, 2, // 4367: switch Inst[23:22] { |
| 10643 | 0, 7, // 4370: case 0x0: { |
| 10644 | OPC_CheckPredicate, 12, // 4372: check predicate 12 |
| 10645 | OPC_Decode, 244, 23, 180, 2, // 4374: decode to V6_vlutvvbi using decoder 308 |
| 10646 | // 4374: } |
| 10647 | 1, 7, // 4379: case 0x1: { |
| 10648 | OPC_CheckPredicate, 12, // 4381: check predicate 12 |
| 10649 | OPC_Decode, 249, 23, 181, 2, // 4383: decode to V6_vlutvwhi using decoder 309 |
| 10650 | // 4383: } |
| 10651 | 2, 0, // 4388: case 0x2: { |
| 10652 | OPC_SwitchField, 5, 3, // 4390: switch Inst[7:5] { |
| 10653 | 0, 7, // 4393: case 0x0: { |
| 10654 | OPC_CheckPredicate, 12, // 4395: check predicate 12 |
| 10655 | OPC_Decode, 128, 22, 167, 2, // 4397: decode to V6_vaddbsat_dv using decoder 295 |
| 10656 | // 4397: } |
| 10657 | 1, 7, // 4402: case 0x1: { |
| 10658 | OPC_CheckPredicate, 12, // 4404: check predicate 12 |
| 10659 | OPC_Decode, 212, 25, 167, 2, // 4406: decode to V6_vsubbsat_dv using decoder 295 |
| 10660 | // 4406: } |
| 10661 | 2, 7, // 4411: case 0x2: { |
| 10662 | OPC_CheckPredicate, 12, // 4413: check predicate 12 |
| 10663 | OPC_Decode, 152, 22, 167, 2, // 4415: decode to V6_vadduwsat_dv using decoder 295 |
| 10664 | // 4415: } |
| 10665 | 3, 7, // 4420: case 0x3: { |
| 10666 | OPC_CheckPredicate, 12, // 4422: check predicate 12 |
| 10667 | OPC_Decode, 230, 25, 167, 2, // 4424: decode to V6_vsubuwsat_dv using decoder 295 |
| 10668 | // 4424: } |
| 10669 | 4, 7, // 4429: case 0x4: { |
| 10670 | OPC_CheckPredicate, 12, // 4431: check predicate 12 |
| 10671 | OPC_Decode, 146, 22, 160, 2, // 4433: decode to V6_vaddububb_sat using decoder 288 |
| 10672 | // 4433: } |
| 10673 | 5, 7, // 4438: case 0x5: { |
| 10674 | OPC_CheckPredicate, 12, // 4440: check predicate 12 |
| 10675 | OPC_Decode, 225, 25, 160, 2, // 4442: decode to V6_vsubububb_sat using decoder 288 |
| 10676 | // 4442: } |
| 10677 | 6, 7, // 4447: case 0x6: { |
| 10678 | OPC_CheckPredicate, 12, // 4449: check predicate 12 |
| 10679 | OPC_Decode, 179, 24, 166, 2, // 4451: decode to V6_vmpyewuh_64 using decoder 294 |
| 10680 | // 4451: } |
| 10681 | 7, 0, // 4456: case 0x7: { |
| 10682 | OPC_CheckPredicate, 24, // 4458: check predicate 24 |
| 10683 | OPC_Decode, 221, 22, 166, 2, // 4460: decode to V6_vcombine_tmp using decoder 294 |
| 10684 | // 4460: } |
| 10685 | // 4460: } // switch Inst[7:5] |
| 10686 | // 4460: } |
| 10687 | // 4460: } // switch Inst[23:22] |
| 10688 | // 4460: } |
| 10689 | // 4460: } // switch Inst[21] |
| 10690 | // 4460: } |
| 10691 | 1, 0, // 4465: case 0x1: { |
| 10692 | OPC_SwitchField, 21, 1, // 4467: switch Inst[21] { |
| 10693 | 0, 216, 7, // 4470: case 0x0: { |
| 10694 | OPC_SwitchField, 16, 5, // 4473: switch Inst[20:16] { |
| 10695 | 0, 128, 1, // 4476: case 0x0: { |
| 10696 | OPC_SwitchField, 5, 3, // 4479: switch Inst[7:5] { |
| 10697 | 0, 11, // 4482: case 0x0: { |
| 10698 | OPC_CheckPredicate, 15, // 4484: check predicate 15 |
| 10699 | OPC_CheckField, 22, 2, 0, // 4486: check Inst[23:22] == 0x0 |
| 10700 | OPC_Decode, 246, 25, 182, 2, // 4490: decode to V6_vunpackob using decoder 310 |
| 10701 | // 4490: } |
| 10702 | 1, 11, // 4495: case 0x1: { |
| 10703 | OPC_CheckPredicate, 15, // 4497: check predicate 15 |
| 10704 | OPC_CheckField, 22, 2, 0, // 4499: check Inst[23:22] == 0x0 |
| 10705 | OPC_Decode, 247, 25, 182, 2, // 4503: decode to V6_vunpackoh using decoder 310 |
| 10706 | // 4503: } |
| 10707 | 4, 0, // 4508: case 0x4: { |
| 10708 | OPC_SwitchField, 9, 4, // 4510: switch Inst[12:9] { |
| 10709 | 0, 18, // 4513: case 0x0: { |
| 10710 | OPC_CheckPredicate, 15, // 4515: check predicate 15 |
| 10711 | OPC_CheckField, 22, 2, 0, // 4517: check Inst[23:22] == 0x0 |
| 10712 | OPC_CheckField, 8, 1, 0, // 4521: check Inst[8] == 0x0 |
| 10713 | OPC_CheckField, 0, 5, 0, // 4525: check Inst[4:0] == 0x0 |
| 10714 | OPC_Decode, 225, 23, 63, // 4529: decode to V6_vhist using decoder 63 |
| 10715 | // 4529: } |
| 10716 | 1, 35, // 4533: case 0x1: { |
| 10717 | OPC_SwitchField, 8, 1, // 4535: switch Inst[8] { |
| 10718 | 0, 14, // 4538: case 0x0: { |
| 10719 | OPC_CheckPredicate, 12, // 4540: check predicate 12 |
| 10720 | OPC_CheckField, 22, 2, 0, // 4542: check Inst[23:22] == 0x0 |
| 10721 | OPC_CheckField, 0, 5, 0, // 4546: check Inst[4:0] == 0x0 |
| 10722 | OPC_Decode, 254, 25, 63, // 4550: decode to V6_vwhist256 using decoder 63 |
| 10723 | // 4550: } |
| 10724 | 1, 0, // 4554: case 0x1: { |
| 10725 | OPC_CheckPredicate, 12, // 4556: check predicate 12 |
| 10726 | OPC_CheckField, 22, 2, 0, // 4558: check Inst[23:22] == 0x0 |
| 10727 | OPC_CheckField, 0, 5, 0, // 4562: check Inst[4:0] == 0x0 |
| 10728 | OPC_Decode, 255, 25, 63, // 4566: decode to V6_vwhist256_sat using decoder 63 |
| 10729 | // 4566: } |
| 10730 | // 4566: } // switch Inst[8] |
| 10731 | // 4566: } |
| 10732 | 2, 18, // 4570: case 0x2: { |
| 10733 | OPC_CheckPredicate, 12, // 4572: check predicate 12 |
| 10734 | OPC_CheckField, 22, 2, 0, // 4574: check Inst[23:22] == 0x0 |
| 10735 | OPC_CheckField, 8, 1, 0, // 4578: check Inst[8] == 0x0 |
| 10736 | OPC_CheckField, 0, 5, 0, // 4582: check Inst[4:0] == 0x0 |
| 10737 | OPC_Decode, 250, 25, 63, // 4586: decode to V6_vwhist128 using decoder 63 |
| 10738 | // 4586: } |
| 10739 | 3, 0, // 4590: case 0x3: { |
| 10740 | OPC_CheckPredicate, 12, // 4592: check predicate 12 |
| 10741 | OPC_CheckField, 22, 2, 0, // 4594: check Inst[23:22] == 0x0 |
| 10742 | OPC_CheckField, 0, 5, 0, // 4598: check Inst[4:0] == 0x0 |
| 10743 | OPC_Decode, 251, 25, 183, 2, // 4602: decode to V6_vwhist128m using decoder 311 |
| 10744 | // 4602: } |
| 10745 | // 4602: } // switch Inst[12:9] |
| 10746 | // 4602: } |
| 10747 | // 4602: } // switch Inst[7:5] |
| 10748 | // 4602: } |
| 10749 | 1, 75, // 4607: case 0x1: { |
| 10750 | OPC_SwitchField, 5, 3, // 4609: switch Inst[7:5] { |
| 10751 | 0, 7, // 4612: case 0x0: { |
| 10752 | OPC_CheckPredicate, 15, // 4614: check predicate 15 |
| 10753 | OPC_Decode, 254, 21, 184, 2, // 4616: decode to V6_vaddbq using decoder 312 |
| 10754 | // 4616: } |
| 10755 | 1, 7, // 4621: case 0x1: { |
| 10756 | OPC_CheckPredicate, 15, // 4623: check predicate 15 |
| 10757 | OPC_Decode, 137, 22, 184, 2, // 4625: decode to V6_vaddhq using decoder 312 |
| 10758 | // 4625: } |
| 10759 | 2, 7, // 4630: case 0x2: { |
| 10760 | OPC_CheckPredicate, 15, // 4632: check predicate 15 |
| 10761 | OPC_Decode, 156, 22, 184, 2, // 4634: decode to V6_vaddwq using decoder 312 |
| 10762 | // 4634: } |
| 10763 | 3, 7, // 4639: case 0x3: { |
| 10764 | OPC_CheckPredicate, 15, // 4641: check predicate 15 |
| 10765 | OPC_Decode, 253, 21, 184, 2, // 4643: decode to V6_vaddbnq using decoder 312 |
| 10766 | // 4643: } |
| 10767 | 4, 7, // 4648: case 0x4: { |
| 10768 | OPC_CheckPredicate, 15, // 4650: check predicate 15 |
| 10769 | OPC_Decode, 136, 22, 184, 2, // 4652: decode to V6_vaddhnq using decoder 312 |
| 10770 | // 4652: } |
| 10771 | 5, 7, // 4657: case 0x5: { |
| 10772 | OPC_CheckPredicate, 15, // 4659: check predicate 15 |
| 10773 | OPC_Decode, 155, 22, 184, 2, // 4661: decode to V6_vaddwnq using decoder 312 |
| 10774 | // 4661: } |
| 10775 | 6, 7, // 4666: case 0x6: { |
| 10776 | OPC_CheckPredicate, 15, // 4668: check predicate 15 |
| 10777 | OPC_Decode, 210, 25, 184, 2, // 4670: decode to V6_vsubbq using decoder 312 |
| 10778 | // 4670: } |
| 10779 | 7, 0, // 4675: case 0x7: { |
| 10780 | OPC_CheckPredicate, 15, // 4677: check predicate 15 |
| 10781 | OPC_Decode, 218, 25, 184, 2, // 4679: decode to V6_vsubhq using decoder 312 |
| 10782 | // 4679: } |
| 10783 | // 4679: } // switch Inst[7:5] |
| 10784 | // 4679: } |
| 10785 | 2, 122, // 4684: case 0x2: { |
| 10786 | OPC_SwitchField, 5, 3, // 4686: switch Inst[7:5] { |
| 10787 | 0, 7, // 4689: case 0x0: { |
| 10788 | OPC_CheckPredicate, 15, // 4691: check predicate 15 |
| 10789 | OPC_Decode, 234, 25, 184, 2, // 4693: decode to V6_vsubwq using decoder 312 |
| 10790 | // 4693: } |
| 10791 | 1, 7, // 4698: case 0x1: { |
| 10792 | OPC_CheckPredicate, 15, // 4700: check predicate 15 |
| 10793 | OPC_Decode, 209, 25, 184, 2, // 4702: decode to V6_vsubbnq using decoder 312 |
| 10794 | // 4702: } |
| 10795 | 2, 7, // 4707: case 0x2: { |
| 10796 | OPC_CheckPredicate, 15, // 4709: check predicate 15 |
| 10797 | OPC_Decode, 217, 25, 184, 2, // 4711: decode to V6_vsubhnq using decoder 312 |
| 10798 | // 4711: } |
| 10799 | 3, 7, // 4716: case 0x3: { |
| 10800 | OPC_CheckPredicate, 15, // 4718: check predicate 15 |
| 10801 | OPC_Decode, 233, 25, 184, 2, // 4720: decode to V6_vsubwnq using decoder 312 |
| 10802 | // 4720: } |
| 10803 | 4, 0, // 4725: case 0x4: { |
| 10804 | OPC_SwitchField, 9, 4, // 4727: switch Inst[12:9] { |
| 10805 | 0, 15, // 4730: case 0x0: { |
| 10806 | OPC_CheckPredicate, 15, // 4732: check predicate 15 |
| 10807 | OPC_CheckField, 8, 1, 0, // 4734: check Inst[8] == 0x0 |
| 10808 | OPC_CheckField, 0, 5, 0, // 4738: check Inst[4:0] == 0x0 |
| 10809 | OPC_Decode, 226, 23, 185, 2, // 4742: decode to V6_vhistq using decoder 313 |
| 10810 | // 4742: } |
| 10811 | 1, 29, // 4747: case 0x1: { |
| 10812 | OPC_SwitchField, 8, 1, // 4749: switch Inst[8] { |
| 10813 | 0, 11, // 4752: case 0x0: { |
| 10814 | OPC_CheckPredicate, 12, // 4754: check predicate 12 |
| 10815 | OPC_CheckField, 0, 5, 0, // 4756: check Inst[4:0] == 0x0 |
| 10816 | OPC_Decode, 128, 26, 185, 2, // 4760: decode to V6_vwhist256q using decoder 313 |
| 10817 | // 4760: } |
| 10818 | 1, 0, // 4765: case 0x1: { |
| 10819 | OPC_CheckPredicate, 12, // 4767: check predicate 12 |
| 10820 | OPC_CheckField, 0, 5, 0, // 4769: check Inst[4:0] == 0x0 |
| 10821 | OPC_Decode, 129, 26, 185, 2, // 4773: decode to V6_vwhist256q_sat using decoder 313 |
| 10822 | // 4773: } |
| 10823 | // 4773: } // switch Inst[8] |
| 10824 | // 4773: } |
| 10825 | 2, 15, // 4778: case 0x2: { |
| 10826 | OPC_CheckPredicate, 12, // 4780: check predicate 12 |
| 10827 | OPC_CheckField, 8, 1, 0, // 4782: check Inst[8] == 0x0 |
| 10828 | OPC_CheckField, 0, 5, 0, // 4786: check Inst[4:0] == 0x0 |
| 10829 | OPC_Decode, 252, 25, 185, 2, // 4790: decode to V6_vwhist128q using decoder 313 |
| 10830 | // 4790: } |
| 10831 | 3, 0, // 4795: case 0x3: { |
| 10832 | OPC_CheckPredicate, 12, // 4797: check predicate 12 |
| 10833 | OPC_CheckField, 0, 5, 0, // 4799: check Inst[4:0] == 0x0 |
| 10834 | OPC_Decode, 253, 25, 186, 2, // 4803: decode to V6_vwhist128qm using decoder 314 |
| 10835 | // 4803: } |
| 10836 | // 4803: } // switch Inst[12:9] |
| 10837 | // 4803: } |
| 10838 | // 4803: } // switch Inst[7:5] |
| 10839 | // 4803: } |
| 10840 | 3, 66, // 4808: case 0x3: { |
| 10841 | OPC_SwitchField, 5, 3, // 4810: switch Inst[7:5] { |
| 10842 | 0, 7, // 4813: case 0x0: { |
| 10843 | OPC_CheckPredicate, 12, // 4815: check predicate 12 |
| 10844 | OPC_Decode, 168, 22, 187, 2, // 4817: decode to V6_vandvqv using decoder 315 |
| 10845 | // 4817: } |
| 10846 | 1, 7, // 4822: case 0x1: { |
| 10847 | OPC_CheckPredicate, 12, // 4824: check predicate 12 |
| 10848 | OPC_Decode, 167, 22, 187, 2, // 4826: decode to V6_vandvnqv using decoder 315 |
| 10849 | // 4826: } |
| 10850 | 2, 30, // 4831: case 0x2: { |
| 10851 | OPC_SwitchField, 8, 5, // 4833: switch Inst[12:8] { |
| 10852 | 0, 7, // 4836: case 0x0: { |
| 10853 | OPC_CheckPredicate, 13, // 4838: check predicate 13 |
| 10854 | OPC_Decode, 245, 24, 188, 2, // 4840: decode to V6_vprefixqb using decoder 316 |
| 10855 | // 4840: } |
| 10856 | 1, 7, // 4845: case 0x1: { |
| 10857 | OPC_CheckPredicate, 13, // 4847: check predicate 13 |
| 10858 | OPC_Decode, 246, 24, 188, 2, // 4849: decode to V6_vprefixqh using decoder 316 |
| 10859 | // 4849: } |
| 10860 | 2, 0, // 4854: case 0x2: { |
| 10861 | OPC_CheckPredicate, 13, // 4856: check predicate 13 |
| 10862 | OPC_Decode, 247, 24, 188, 2, // 4858: decode to V6_vprefixqw using decoder 316 |
| 10863 | // 4858: } |
| 10864 | // 4858: } // switch Inst[12:8] |
| 10865 | // 4858: } |
| 10866 | 7, 0, // 4863: case 0x7: { |
| 10867 | OPC_CheckPredicate, 15, // 4865: check predicate 15 |
| 10868 | OPC_CheckField, 22, 2, 0, // 4867: check Inst[23:22] == 0x0 |
| 10869 | OPC_Decode, 201, 22, 168, 2, // 4871: decode to V6_vassign using decoder 296 |
| 10870 | // 4871: } |
| 10871 | // 4871: } // switch Inst[7:5] |
| 10872 | // 4871: } |
| 10873 | 4, 107, // 4876: case 0x4: { |
| 10874 | OPC_SwitchField, 5, 3, // 4878: switch Inst[7:5] { |
| 10875 | 0, 11, // 4881: case 0x0: { |
| 10876 | OPC_CheckPredicate, 26, // 4883: check predicate 26 |
| 10877 | OPC_CheckField, 22, 2, 0, // 4885: check Inst[23:22] == 0x0 |
| 10878 | OPC_Decode, 234, 22, 168, 2, // 4889: decode to V6_vconv_sf_qf32 using decoder 296 |
| 10879 | // 4889: } |
| 10880 | 1, 11, // 4894: case 0x1: { |
| 10881 | OPC_CheckPredicate, 21, // 4896: check predicate 21 |
| 10882 | OPC_CheckField, 22, 2, 0, // 4898: check Inst[23:22] == 0x0 |
| 10883 | OPC_Decode, 249, 22, 177, 2, // 4902: decode to V6_vcvt_hf_ub using decoder 305 |
| 10884 | // 4902: } |
| 10885 | 2, 11, // 4907: case 0x2: { |
| 10886 | OPC_CheckPredicate, 21, // 4909: check predicate 21 |
| 10887 | OPC_CheckField, 22, 2, 0, // 4911: check Inst[23:22] == 0x0 |
| 10888 | OPC_Decode, 245, 22, 177, 2, // 4915: decode to V6_vcvt_hf_b using decoder 305 |
| 10889 | // 4915: } |
| 10890 | 3, 11, // 4920: case 0x3: { |
| 10891 | OPC_CheckPredicate, 26, // 4922: check predicate 26 |
| 10892 | OPC_CheckField, 22, 2, 0, // 4924: check Inst[23:22] == 0x0 |
| 10893 | OPC_Decode, 227, 22, 168, 2, // 4928: decode to V6_vconv_hf_qf16 using decoder 296 |
| 10894 | // 4928: } |
| 10895 | 4, 11, // 4933: case 0x4: { |
| 10896 | OPC_CheckPredicate, 21, // 4935: check predicate 21 |
| 10897 | OPC_CheckField, 22, 2, 0, // 4937: check Inst[23:22] == 0x0 |
| 10898 | OPC_Decode, 251, 22, 177, 2, // 4941: decode to V6_vcvt_sf_hf using decoder 305 |
| 10899 | // 4941: } |
| 10900 | 5, 11, // 4946: case 0x5: { |
| 10901 | OPC_CheckPredicate, 21, // 4948: check predicate 21 |
| 10902 | OPC_CheckField, 22, 2, 0, // 4950: check Inst[23:22] == 0x0 |
| 10903 | OPC_Decode, 250, 22, 168, 2, // 4954: decode to V6_vcvt_hf_uh using decoder 296 |
| 10904 | // 4954: } |
| 10905 | 6, 11, // 4959: case 0x6: { |
| 10906 | OPC_CheckPredicate, 26, // 4961: check predicate 26 |
| 10907 | OPC_CheckField, 22, 2, 0, // 4963: check Inst[23:22] == 0x0 |
| 10908 | OPC_Decode, 228, 22, 189, 2, // 4967: decode to V6_vconv_hf_qf32 using decoder 317 |
| 10909 | // 4967: } |
| 10910 | 7, 0, // 4972: case 0x7: { |
| 10911 | OPC_CheckPredicate, 21, // 4974: check predicate 21 |
| 10912 | OPC_CheckField, 22, 2, 0, // 4976: check Inst[23:22] == 0x0 |
| 10913 | OPC_Decode, 247, 22, 168, 2, // 4980: decode to V6_vcvt_hf_h using decoder 296 |
| 10914 | // 4980: } |
| 10915 | // 4980: } // switch Inst[7:5] |
| 10916 | // 4980: } |
| 10917 | 5, 81, // 4985: case 0x5: { |
| 10918 | OPC_SwitchField, 5, 3, // 4987: switch Inst[7:5] { |
| 10919 | 0, 11, // 4990: case 0x0: { |
| 10920 | OPC_CheckPredicate, 21, // 4992: check predicate 21 |
| 10921 | OPC_CheckField, 22, 2, 0, // 4994: check Inst[23:22] == 0x0 |
| 10922 | OPC_Decode, 253, 22, 168, 2, // 4998: decode to V6_vcvt_uh_hf using decoder 296 |
| 10923 | // 4998: } |
| 10924 | 1, 11, // 5003: case 0x1: { |
| 10925 | OPC_CheckPredicate, 27, // 5005: check predicate 27 |
| 10926 | OPC_CheckField, 22, 2, 0, // 5007: check Inst[23:22] == 0x0 |
| 10927 | OPC_Decode, 236, 22, 168, 2, // 5011: decode to V6_vconv_w_sf using decoder 296 |
| 10928 | // 5011: } |
| 10929 | 2, 11, // 5016: case 0x2: { |
| 10930 | OPC_CheckPredicate, 27, // 5018: check predicate 27 |
| 10931 | OPC_CheckField, 22, 2, 0, // 5020: check Inst[23:22] == 0x0 |
| 10932 | OPC_Decode, 224, 22, 168, 2, // 5024: decode to V6_vconv_h_hf using decoder 296 |
| 10933 | // 5024: } |
| 10934 | 3, 11, // 5029: case 0x3: { |
| 10935 | OPC_CheckPredicate, 27, // 5031: check predicate 27 |
| 10936 | OPC_CheckField, 22, 2, 0, // 5033: check Inst[23:22] == 0x0 |
| 10937 | OPC_Decode, 235, 22, 168, 2, // 5037: decode to V6_vconv_sf_w using decoder 296 |
| 10938 | // 5037: } |
| 10939 | 4, 11, // 5042: case 0x4: { |
| 10940 | OPC_CheckPredicate, 27, // 5044: check predicate 27 |
| 10941 | OPC_CheckField, 22, 2, 0, // 5046: check Inst[23:22] == 0x0 |
| 10942 | OPC_Decode, 226, 22, 168, 2, // 5050: decode to V6_vconv_hf_h using decoder 296 |
| 10943 | // 5050: } |
| 10944 | 5, 0, // 5055: case 0x5: { |
| 10945 | OPC_CheckPredicate, 20, // 5057: check predicate 20 |
| 10946 | OPC_CheckField, 22, 2, 0, // 5059: check Inst[23:22] == 0x0 |
| 10947 | OPC_Decode, 246, 22, 177, 2, // 5063: decode to V6_vcvt_hf_f8 using decoder 305 |
| 10948 | // 5063: } |
| 10949 | // 5063: } // switch Inst[7:5] |
| 10950 | // 5063: } |
| 10951 | 6, 107, // 5068: case 0x6: { |
| 10952 | OPC_SwitchField, 5, 3, // 5070: switch Inst[7:5] { |
| 10953 | 0, 11, // 5073: case 0x0: { |
| 10954 | OPC_CheckPredicate, 21, // 5075: check predicate 21 |
| 10955 | OPC_CheckField, 22, 2, 0, // 5077: check Inst[23:22] == 0x0 |
| 10956 | OPC_Decode, 244, 22, 168, 2, // 5081: decode to V6_vcvt_h_hf using decoder 296 |
| 10957 | // 5081: } |
| 10958 | 1, 11, // 5086: case 0x1: { |
| 10959 | OPC_CheckPredicate, 21, // 5088: check predicate 21 |
| 10960 | OPC_CheckField, 22, 2, 0, // 5090: check Inst[23:22] == 0x0 |
| 10961 | OPC_Decode, 202, 22, 168, 2, // 5094: decode to V6_vassign_fp using decoder 296 |
| 10962 | // 5094: } |
| 10963 | 2, 11, // 5099: case 0x2: { |
| 10964 | OPC_CheckPredicate, 21, // 5101: check predicate 21 |
| 10965 | OPC_CheckField, 22, 2, 0, // 5103: check Inst[23:22] == 0x0 |
| 10966 | OPC_Decode, 181, 23, 168, 2, // 5107: decode to V6_vfneg_hf using decoder 296 |
| 10967 | // 5107: } |
| 10968 | 3, 11, // 5112: case 0x3: { |
| 10969 | OPC_CheckPredicate, 21, // 5114: check predicate 21 |
| 10970 | OPC_CheckField, 22, 2, 0, // 5116: check Inst[23:22] == 0x0 |
| 10971 | OPC_Decode, 182, 23, 168, 2, // 5120: decode to V6_vfneg_sf using decoder 296 |
| 10972 | // 5120: } |
| 10973 | 4, 11, // 5125: case 0x4: { |
| 10974 | OPC_CheckPredicate, 21, // 5127: check predicate 21 |
| 10975 | OPC_CheckField, 22, 2, 0, // 5129: check Inst[23:22] == 0x0 |
| 10976 | OPC_Decode, 224, 21, 168, 2, // 5133: decode to V6_vabs_hf using decoder 296 |
| 10977 | // 5133: } |
| 10978 | 5, 11, // 5138: case 0x5: { |
| 10979 | OPC_CheckPredicate, 21, // 5140: check predicate 21 |
| 10980 | OPC_CheckField, 22, 2, 0, // 5142: check Inst[23:22] == 0x0 |
| 10981 | OPC_Decode, 229, 21, 168, 2, // 5146: decode to V6_vabs_sf using decoder 296 |
| 10982 | // 5146: } |
| 10983 | 6, 11, // 5151: case 0x6: { |
| 10984 | OPC_CheckPredicate, 14, // 5153: check predicate 14 |
| 10985 | OPC_CheckField, 22, 2, 0, // 5155: check Inst[23:22] == 0x0 |
| 10986 | OPC_Decode, 225, 22, 168, 2, // 5159: decode to V6_vconv_h_hf_rnd using decoder 296 |
| 10987 | // 5159: } |
| 10988 | 7, 0, // 5164: case 0x7: { |
| 10989 | OPC_CheckPredicate, 18, // 5166: check predicate 18 |
| 10990 | OPC_CheckField, 22, 2, 0, // 5168: check Inst[23:22] == 0x0 |
| 10991 | OPC_Decode, 222, 22, 189, 2, // 5172: decode to V6_vconv_bf_qf32 using decoder 317 |
| 10992 | // 5172: } |
| 10993 | // 5172: } // switch Inst[7:5] |
| 10994 | // 5172: } |
| 10995 | 12, 107, // 5177: case 0xc: { |
| 10996 | OPC_SwitchField, 5, 3, // 5179: switch Inst[7:5] { |
| 10997 | 0, 11, // 5182: case 0x0: { |
| 10998 | OPC_CheckPredicate, 18, // 5184: check predicate 18 |
| 10999 | OPC_CheckField, 22, 2, 0, // 5186: check Inst[23:22] == 0x0 |
| 11000 | OPC_Decode, 229, 23, 168, 2, // 5190: decode to V6_vilog2_qf32 using decoder 296 |
| 11001 | // 5190: } |
| 11002 | 1, 11, // 5195: case 0x1: { |
| 11003 | OPC_CheckPredicate, 18, // 5197: check predicate 18 |
| 11004 | OPC_CheckField, 22, 2, 0, // 5199: check Inst[23:22] == 0x0 |
| 11005 | OPC_Decode, 228, 23, 168, 2, // 5203: decode to V6_vilog2_qf16 using decoder 296 |
| 11006 | // 5203: } |
| 11007 | 2, 11, // 5208: case 0x2: { |
| 11008 | OPC_CheckPredicate, 18, // 5210: check predicate 18 |
| 11009 | OPC_CheckField, 22, 2, 0, // 5212: check Inst[23:22] == 0x0 |
| 11010 | OPC_Decode, 230, 23, 168, 2, // 5216: decode to V6_vilog2_sf using decoder 296 |
| 11011 | // 5216: } |
| 11012 | 3, 11, // 5221: case 0x3: { |
| 11013 | OPC_CheckPredicate, 18, // 5223: check predicate 18 |
| 11014 | OPC_CheckField, 22, 2, 0, // 5225: check Inst[23:22] == 0x0 |
| 11015 | OPC_Decode, 227, 23, 168, 2, // 5229: decode to V6_vilog2_hf using decoder 296 |
| 11016 | // 5229: } |
| 11017 | 4, 11, // 5234: case 0x4: { |
| 11018 | OPC_CheckPredicate, 18, // 5236: check predicate 18 |
| 11019 | OPC_CheckField, 22, 2, 0, // 5238: check Inst[23:22] == 0x0 |
| 11020 | OPC_Decode, 230, 22, 168, 2, // 5242: decode to V6_vconv_qf16_hf using decoder 296 |
| 11021 | // 5242: } |
| 11022 | 5, 11, // 5247: case 0x5: { |
| 11023 | OPC_CheckPredicate, 18, // 5249: check predicate 18 |
| 11024 | OPC_CheckField, 22, 2, 0, // 5251: check Inst[23:22] == 0x0 |
| 11025 | OPC_Decode, 229, 22, 177, 2, // 5255: decode to V6_vconv_qf16_f8 using decoder 305 |
| 11026 | // 5255: } |
| 11027 | 6, 11, // 5260: case 0x6: { |
| 11028 | OPC_CheckPredicate, 18, // 5262: check predicate 18 |
| 11029 | OPC_CheckField, 22, 2, 0, // 5264: check Inst[23:22] == 0x0 |
| 11030 | OPC_Decode, 231, 22, 168, 2, // 5268: decode to V6_vconv_qf16_qf16 using decoder 296 |
| 11031 | // 5268: } |
| 11032 | 7, 0, // 5273: case 0x7: { |
| 11033 | OPC_CheckPredicate, 18, // 5275: check predicate 18 |
| 11034 | OPC_CheckField, 22, 2, 0, // 5277: check Inst[23:22] == 0x0 |
| 11035 | OPC_Decode, 223, 22, 168, 2, // 5281: decode to V6_vconv_f8_qf16 using decoder 296 |
| 11036 | // 5281: } |
| 11037 | // 5281: } // switch Inst[7:5] |
| 11038 | // 5281: } |
| 11039 | 13, 29, // 5286: case 0xd: { |
| 11040 | OPC_SwitchField, 5, 3, // 5288: switch Inst[7:5] { |
| 11041 | 6, 11, // 5291: case 0x6: { |
| 11042 | OPC_CheckPredicate, 18, // 5293: check predicate 18 |
| 11043 | OPC_CheckField, 22, 2, 0, // 5295: check Inst[23:22] == 0x0 |
| 11044 | OPC_Decode, 233, 22, 168, 2, // 5299: decode to V6_vconv_qf32_sf using decoder 296 |
| 11045 | // 5299: } |
| 11046 | 7, 0, // 5304: case 0x7: { |
| 11047 | OPC_CheckPredicate, 18, // 5306: check predicate 18 |
| 11048 | OPC_CheckField, 22, 2, 0, // 5308: check Inst[23:22] == 0x0 |
| 11049 | OPC_Decode, 232, 22, 168, 2, // 5312: decode to V6_vconv_qf32_qf32 using decoder 296 |
| 11050 | // 5312: } |
| 11051 | // 5312: } // switch Inst[7:5] |
| 11052 | // 5312: } |
| 11053 | 14, 107, // 5317: case 0xe: { |
| 11054 | OPC_SwitchField, 5, 3, // 5319: switch Inst[7:5] { |
| 11055 | 0, 11, // 5322: case 0x0: { |
| 11056 | OPC_CheckPredicate, 18, // 5324: check predicate 18 |
| 11057 | OPC_CheckField, 22, 2, 0, // 5326: check Inst[23:22] == 0x0 |
| 11058 | OPC_Decode, 231, 24, 168, 2, // 5330: decode to V6_vneg_qf32_sf using decoder 296 |
| 11059 | // 5330: } |
| 11060 | 1, 11, // 5335: case 0x1: { |
| 11061 | OPC_CheckPredicate, 18, // 5337: check predicate 18 |
| 11062 | OPC_CheckField, 22, 2, 0, // 5339: check Inst[23:22] == 0x0 |
| 11063 | OPC_Decode, 230, 24, 168, 2, // 5343: decode to V6_vneg_qf32_qf32 using decoder 296 |
| 11064 | // 5343: } |
| 11065 | 2, 11, // 5348: case 0x2: { |
| 11066 | OPC_CheckPredicate, 18, // 5350: check predicate 18 |
| 11067 | OPC_CheckField, 22, 2, 0, // 5352: check Inst[23:22] == 0x0 |
| 11068 | OPC_Decode, 228, 24, 168, 2, // 5356: decode to V6_vneg_qf16_hf using decoder 296 |
| 11069 | // 5356: } |
| 11070 | 3, 11, // 5361: case 0x3: { |
| 11071 | OPC_CheckPredicate, 18, // 5363: check predicate 18 |
| 11072 | OPC_CheckField, 22, 2, 0, // 5365: check Inst[23:22] == 0x0 |
| 11073 | OPC_Decode, 229, 24, 168, 2, // 5369: decode to V6_vneg_qf16_qf16 using decoder 296 |
| 11074 | // 5369: } |
| 11075 | 4, 11, // 5374: case 0x4: { |
| 11076 | OPC_CheckPredicate, 18, // 5376: check predicate 18 |
| 11077 | OPC_CheckField, 22, 2, 0, // 5378: check Inst[23:22] == 0x0 |
| 11078 | OPC_Decode, 228, 21, 168, 2, // 5382: decode to V6_vabs_qf32_sf using decoder 296 |
| 11079 | // 5382: } |
| 11080 | 5, 11, // 5387: case 0x5: { |
| 11081 | OPC_CheckPredicate, 18, // 5389: check predicate 18 |
| 11082 | OPC_CheckField, 22, 2, 0, // 5391: check Inst[23:22] == 0x0 |
| 11083 | OPC_Decode, 227, 21, 168, 2, // 5395: decode to V6_vabs_qf32_qf32 using decoder 296 |
| 11084 | // 5395: } |
| 11085 | 6, 11, // 5400: case 0x6: { |
| 11086 | OPC_CheckPredicate, 18, // 5402: check predicate 18 |
| 11087 | OPC_CheckField, 22, 2, 0, // 5404: check Inst[23:22] == 0x0 |
| 11088 | OPC_Decode, 225, 21, 168, 2, // 5408: decode to V6_vabs_qf16_hf using decoder 296 |
| 11089 | // 5408: } |
| 11090 | 7, 0, // 5413: case 0x7: { |
| 11091 | OPC_CheckPredicate, 18, // 5415: check predicate 18 |
| 11092 | OPC_CheckField, 22, 2, 0, // 5417: check Inst[23:22] == 0x0 |
| 11093 | OPC_Decode, 226, 21, 168, 2, // 5421: decode to V6_vabs_qf16_qf16 using decoder 296 |
| 11094 | // 5421: } |
| 11095 | // 5421: } // switch Inst[7:5] |
| 11096 | // 5421: } |
| 11097 | 21, 0, // 5426: case 0x15: { |
| 11098 | OPC_SwitchField, 5, 3, // 5428: switch Inst[7:5] { |
| 11099 | 6, 11, // 5431: case 0x6: { |
| 11100 | OPC_CheckPredicate, 20, // 5433: check predicate 20 |
| 11101 | OPC_CheckField, 22, 2, 3, // 5435: check Inst[23:22] == 0x3 |
| 11102 | OPC_Decode, 238, 22, 177, 2, // 5439: decode to V6_vcvt2_hf_b using decoder 305 |
| 11103 | // 5439: } |
| 11104 | 7, 0, // 5444: case 0x7: { |
| 11105 | OPC_CheckPredicate, 20, // 5446: check predicate 20 |
| 11106 | OPC_CheckField, 22, 2, 3, // 5448: check Inst[23:22] == 0x3 |
| 11107 | OPC_Decode, 239, 22, 177, 2, // 5452: decode to V6_vcvt2_hf_ub using decoder 305 |
| 11108 | // 5452: } |
| 11109 | // 5452: } // switch Inst[7:5] |
| 11110 | // 5452: } |
| 11111 | // 5452: } // switch Inst[20:16] |
| 11112 | // 5452: } |
| 11113 | 1, 0, // 5457: case 0x1: { |
| 11114 | OPC_SwitchField, 22, 2, // 5459: switch Inst[23:22] { |
| 11115 | 0, 7, // 5462: case 0x0: { |
| 11116 | OPC_CheckPredicate, 15, // 5464: check predicate 15 |
| 11117 | OPC_Decode, 161, 22, 180, 2, // 5466: decode to V6_valignbi using decoder 308 |
| 11118 | // 5466: } |
| 11119 | 1, 7, // 5471: case 0x1: { |
| 11120 | OPC_CheckPredicate, 15, // 5473: check predicate 15 |
| 11121 | OPC_Decode, 233, 23, 180, 2, // 5475: decode to V6_vlalignbi using decoder 308 |
| 11122 | // 5475: } |
| 11123 | 2, 11, // 5480: case 0x2: { |
| 11124 | OPC_CheckPredicate, 15, // 5482: check predicate 15 |
| 11125 | OPC_CheckField, 7, 1, 0, // 5484: check Inst[7] == 0x0 |
| 11126 | OPC_Decode, 237, 25, 190, 2, // 5488: decode to V6_vswap using decoder 318 |
| 11127 | // 5488: } |
| 11128 | 3, 0, // 5493: case 0x3: { |
| 11129 | OPC_CheckPredicate, 15, // 5495: check predicate 15 |
| 11130 | OPC_CheckField, 7, 1, 0, // 5497: check Inst[7] == 0x0 |
| 11131 | OPC_Decode, 221, 24, 176, 2, // 5501: decode to V6_vmux using decoder 304 |
| 11132 | // 5501: } |
| 11133 | // 5501: } // switch Inst[23:22] |
| 11134 | // 5501: } |
| 11135 | // 5501: } // switch Inst[21] |
| 11136 | // 5501: } |
| 11137 | // 5501: } // switch Inst[13] |
| 11138 | // 5501: } |
| 11139 | 31, 143, 11, // 5506: case 0x1f: { |
| 11140 | OPC_SwitchField, 21, 3, // 5509: switch Inst[23:21] { |
| 11141 | 0, 187, 1, // 5512: case 0x0: { |
| 11142 | OPC_SwitchField, 5, 3, // 5515: switch Inst[7:5] { |
| 11143 | 0, 21, // 5518: case 0x0: { |
| 11144 | OPC_SwitchField, 13, 1, // 5520: switch Inst[13] { |
| 11145 | 0, 7, // 5523: case 0x0: { |
| 11146 | OPC_CheckPredicate, 12, // 5525: check predicate 12 |
| 11147 | OPC_Decode, 255, 21, 160, 2, // 5527: decode to V6_vaddbsat using decoder 288 |
| 11148 | // 5527: } |
| 11149 | 1, 0, // 5532: case 0x1: { |
| 11150 | OPC_CheckPredicate, 12, // 5534: check predicate 12 |
| 11151 | OPC_Decode, 132, 22, 160, 2, // 5536: decode to V6_vaddclbh using decoder 288 |
| 11152 | // 5536: } |
| 11153 | // 5536: } // switch Inst[13] |
| 11154 | // 5536: } |
| 11155 | 1, 21, // 5541: case 0x1: { |
| 11156 | OPC_SwitchField, 13, 1, // 5543: switch Inst[13] { |
| 11157 | 0, 7, // 5546: case 0x0: { |
| 11158 | OPC_CheckPredicate, 15, // 5548: check predicate 15 |
| 11159 | OPC_Decode, 136, 24, 160, 2, // 5550: decode to V6_vminub using decoder 288 |
| 11160 | // 5550: } |
| 11161 | 1, 0, // 5555: case 0x1: { |
| 11162 | OPC_CheckPredicate, 12, // 5557: check predicate 12 |
| 11163 | OPC_Decode, 133, 22, 160, 2, // 5559: decode to V6_vaddclbw using decoder 288 |
| 11164 | // 5559: } |
| 11165 | // 5559: } // switch Inst[13] |
| 11166 | // 5559: } |
| 11167 | 2, 21, // 5564: case 0x2: { |
| 11168 | OPC_SwitchField, 13, 1, // 5566: switch Inst[13] { |
| 11169 | 0, 7, // 5569: case 0x0: { |
| 11170 | OPC_CheckPredicate, 15, // 5571: check predicate 15 |
| 11171 | OPC_Decode, 137, 24, 160, 2, // 5573: decode to V6_vminuh using decoder 288 |
| 11172 | // 5573: } |
| 11173 | 1, 0, // 5578: case 0x1: { |
| 11174 | OPC_CheckPredicate, 13, // 5580: check predicate 13 |
| 11175 | OPC_Decode, 212, 22, 160, 2, // 5582: decode to V6_vavguw using decoder 288 |
| 11176 | // 5582: } |
| 11177 | // 5582: } // switch Inst[13] |
| 11178 | // 5582: } |
| 11179 | 3, 21, // 5587: case 0x3: { |
| 11180 | OPC_SwitchField, 13, 1, // 5589: switch Inst[13] { |
| 11181 | 0, 7, // 5592: case 0x0: { |
| 11182 | OPC_CheckPredicate, 15, // 5594: check predicate 15 |
| 11183 | OPC_Decode, 135, 24, 160, 2, // 5596: decode to V6_vminh using decoder 288 |
| 11184 | // 5596: } |
| 11185 | 1, 0, // 5601: case 0x1: { |
| 11186 | OPC_CheckPredicate, 13, // 5603: check predicate 13 |
| 11187 | OPC_Decode, 213, 22, 160, 2, // 5605: decode to V6_vavguwrnd using decoder 288 |
| 11188 | // 5605: } |
| 11189 | // 5605: } // switch Inst[13] |
| 11190 | // 5605: } |
| 11191 | 4, 21, // 5610: case 0x4: { |
| 11192 | OPC_SwitchField, 13, 1, // 5612: switch Inst[13] { |
| 11193 | 0, 7, // 5615: case 0x0: { |
| 11194 | OPC_CheckPredicate, 15, // 5617: check predicate 15 |
| 11195 | OPC_Decode, 138, 24, 160, 2, // 5619: decode to V6_vminw using decoder 288 |
| 11196 | // 5619: } |
| 11197 | 1, 0, // 5624: case 0x1: { |
| 11198 | OPC_CheckPredicate, 13, // 5626: check predicate 13 |
| 11199 | OPC_Decode, 204, 22, 160, 2, // 5628: decode to V6_vavgb using decoder 288 |
| 11200 | // 5628: } |
| 11201 | // 5628: } // switch Inst[13] |
| 11202 | // 5628: } |
| 11203 | 5, 21, // 5633: case 0x5: { |
| 11204 | OPC_SwitchField, 13, 1, // 5635: switch Inst[13] { |
| 11205 | 0, 7, // 5638: case 0x0: { |
| 11206 | OPC_CheckPredicate, 15, // 5640: check predicate 15 |
| 11207 | OPC_Decode, 255, 23, 160, 2, // 5642: decode to V6_vmaxub using decoder 288 |
| 11208 | // 5642: } |
| 11209 | 1, 0, // 5647: case 0x1: { |
| 11210 | OPC_CheckPredicate, 13, // 5649: check predicate 13 |
| 11211 | OPC_Decode, 205, 22, 160, 2, // 5651: decode to V6_vavgbrnd using decoder 288 |
| 11212 | // 5651: } |
| 11213 | // 5651: } // switch Inst[13] |
| 11214 | // 5651: } |
| 11215 | 6, 21, // 5656: case 0x6: { |
| 11216 | OPC_SwitchField, 13, 1, // 5658: switch Inst[13] { |
| 11217 | 0, 7, // 5661: case 0x0: { |
| 11218 | OPC_CheckPredicate, 15, // 5663: check predicate 15 |
| 11219 | OPC_Decode, 128, 24, 160, 2, // 5665: decode to V6_vmaxuh using decoder 288 |
| 11220 | // 5665: } |
| 11221 | 1, 0, // 5670: case 0x1: { |
| 11222 | OPC_CheckPredicate, 13, // 5672: check predicate 13 |
| 11223 | OPC_Decode, 222, 24, 160, 2, // 5674: decode to V6_vnavgb using decoder 288 |
| 11224 | // 5674: } |
| 11225 | // 5674: } // switch Inst[13] |
| 11226 | // 5674: } |
| 11227 | 7, 0, // 5679: case 0x7: { |
| 11228 | OPC_SwitchField, 13, 1, // 5681: switch Inst[13] { |
| 11229 | 0, 7, // 5684: case 0x0: { |
| 11230 | OPC_CheckPredicate, 15, // 5686: check predicate 15 |
| 11231 | OPC_Decode, 254, 23, 160, 2, // 5688: decode to V6_vmaxh using decoder 288 |
| 11232 | // 5688: } |
| 11233 | 1, 0, // 5693: case 0x1: { |
| 11234 | OPC_CheckPredicate, 17, // 5695: check predicate 17 |
| 11235 | OPC_Decode, 130, 24, 160, 2, // 5697: decode to V6_vmerge_qf using decoder 288 |
| 11236 | // 5697: } |
| 11237 | // 5697: } // switch Inst[13] |
| 11238 | // 5697: } |
| 11239 | // 5697: } // switch Inst[7:5] |
| 11240 | // 5697: } |
| 11241 | 1, 113, // 5702: case 0x1: { |
| 11242 | OPC_SwitchField, 7, 1, // 5704: switch Inst[7] { |
| 11243 | 0, 53, // 5707: case 0x0: { |
| 11244 | OPC_SwitchField, 13, 1, // 5709: switch Inst[13] { |
| 11245 | 0, 39, // 5712: case 0x0: { |
| 11246 | OPC_SwitchField, 5, 2, // 5714: switch Inst[6:5] { |
| 11247 | 0, 7, // 5717: case 0x0: { |
| 11248 | OPC_CheckPredicate, 15, // 5719: check predicate 15 |
| 11249 | OPC_Decode, 129, 24, 160, 2, // 5721: decode to V6_vmaxw using decoder 288 |
| 11250 | // 5721: } |
| 11251 | 1, 7, // 5726: case 0x1: { |
| 11252 | OPC_CheckPredicate, 15, // 5728: check predicate 15 |
| 11253 | OPC_Decode, 131, 23, 160, 2, // 5730: decode to V6_vdelta using decoder 288 |
| 11254 | // 5730: } |
| 11255 | 2, 7, // 5735: case 0x2: { |
| 11256 | OPC_CheckPredicate, 12, // 5737: check predicate 12 |
| 11257 | OPC_Decode, 211, 25, 160, 2, // 5739: decode to V6_vsubbsat using decoder 288 |
| 11258 | // 5739: } |
| 11259 | 3, 0, // 5744: case 0x3: { |
| 11260 | OPC_CheckPredicate, 15, // 5746: check predicate 15 |
| 11261 | OPC_Decode, 248, 24, 160, 2, // 5748: decode to V6_vrdelta using decoder 288 |
| 11262 | // 5748: } |
| 11263 | // 5748: } // switch Inst[6:5] |
| 11264 | // 5748: } |
| 11265 | 1, 0, // 5753: case 0x1: { |
| 11266 | OPC_CheckPredicate, 22, // 5755: check predicate 22 |
| 11267 | OPC_Decode, 233, 20, 191, 2, // 5757: decode to V6_v6mpyvubs10_vxx using decoder 319 |
| 11268 | // 5757: } |
| 11269 | // 5757: } // switch Inst[13] |
| 11270 | // 5757: } |
| 11271 | 1, 0, // 5762: case 0x1: { |
| 11272 | OPC_SwitchField, 13, 1, // 5764: switch Inst[13] { |
| 11273 | 0, 39, // 5767: case 0x0: { |
| 11274 | OPC_SwitchField, 5, 2, // 5769: switch Inst[6:5] { |
| 11275 | 0, 7, // 5772: case 0x0: { |
| 11276 | OPC_CheckPredicate, 12, // 5774: check predicate 12 |
| 11277 | OPC_Decode, 134, 24, 160, 2, // 5776: decode to V6_vminb using decoder 288 |
| 11278 | // 5776: } |
| 11279 | 1, 7, // 5781: case 0x1: { |
| 11280 | OPC_CheckPredicate, 12, // 5783: check predicate 12 |
| 11281 | OPC_Decode, 253, 23, 160, 2, // 5785: decode to V6_vmaxb using decoder 288 |
| 11282 | // 5785: } |
| 11283 | 2, 7, // 5790: case 0x2: { |
| 11284 | OPC_CheckPredicate, 12, // 5792: check predicate 12 |
| 11285 | OPC_Decode, 171, 25, 160, 2, // 5794: decode to V6_vsatuwuh using decoder 288 |
| 11286 | // 5794: } |
| 11287 | 3, 0, // 5799: case 0x3: { |
| 11288 | OPC_CheckPredicate, 15, // 5801: check predicate 15 |
| 11289 | OPC_Decode, 128, 23, 160, 2, // 5803: decode to V6_vdealb4w using decoder 288 |
| 11290 | // 5803: } |
| 11291 | // 5803: } // switch Inst[6:5] |
| 11292 | // 5803: } |
| 11293 | 1, 0, // 5808: case 0x1: { |
| 11294 | OPC_CheckPredicate, 22, // 5810: check predicate 22 |
| 11295 | OPC_Decode, 231, 20, 191, 2, // 5812: decode to V6_v6mpyhubs10_vxx using decoder 319 |
| 11296 | // 5812: } |
| 11297 | // 5812: } // switch Inst[13] |
| 11298 | // 5812: } |
| 11299 | // 5812: } // switch Inst[7] |
| 11300 | // 5812: } |
| 11301 | 2, 113, // 5817: case 0x2: { |
| 11302 | OPC_SwitchField, 7, 1, // 5819: switch Inst[7] { |
| 11303 | 0, 53, // 5822: case 0x0: { |
| 11304 | OPC_SwitchField, 13, 1, // 5824: switch Inst[13] { |
| 11305 | 0, 39, // 5827: case 0x0: { |
| 11306 | OPC_SwitchField, 5, 2, // 5829: switch Inst[6:5] { |
| 11307 | 0, 7, // 5832: case 0x0: { |
| 11308 | OPC_CheckPredicate, 15, // 5834: check predicate 15 |
| 11309 | OPC_Decode, 207, 24, 160, 2, // 5836: decode to V6_vmpyowh_rnd using decoder 288 |
| 11310 | // 5836: } |
| 11311 | 1, 7, // 5841: case 0x1: { |
| 11312 | OPC_CheckPredicate, 15, // 5843: check predicate 15 |
| 11313 | OPC_Decode, 187, 25, 160, 2, // 5845: decode to V6_vshuffeb using decoder 288 |
| 11314 | // 5845: } |
| 11315 | 2, 7, // 5850: case 0x2: { |
| 11316 | OPC_CheckPredicate, 15, // 5852: check predicate 15 |
| 11317 | OPC_Decode, 189, 25, 160, 2, // 5854: decode to V6_vshuffob using decoder 288 |
| 11318 | // 5854: } |
| 11319 | 3, 0, // 5859: case 0x3: { |
| 11320 | OPC_CheckPredicate, 15, // 5861: check predicate 15 |
| 11321 | OPC_Decode, 184, 25, 160, 2, // 5863: decode to V6_vshufeh using decoder 288 |
| 11322 | // 5863: } |
| 11323 | // 5863: } // switch Inst[6:5] |
| 11324 | // 5863: } |
| 11325 | 1, 0, // 5868: case 0x1: { |
| 11326 | OPC_CheckPredicate, 22, // 5870: check predicate 22 |
| 11327 | OPC_Decode, 232, 20, 192, 2, // 5872: decode to V6_v6mpyvubs10 using decoder 320 |
| 11328 | // 5872: } |
| 11329 | // 5872: } // switch Inst[13] |
| 11330 | // 5872: } |
| 11331 | 1, 0, // 5877: case 0x1: { |
| 11332 | OPC_SwitchField, 13, 1, // 5879: switch Inst[13] { |
| 11333 | 0, 39, // 5882: case 0x0: { |
| 11334 | OPC_SwitchField, 5, 2, // 5884: switch Inst[6:5] { |
| 11335 | 0, 7, // 5887: case 0x0: { |
| 11336 | OPC_CheckPredicate, 15, // 5889: check predicate 15 |
| 11337 | OPC_Decode, 193, 25, 160, 2, // 5891: decode to V6_vshufoh using decoder 288 |
| 11338 | // 5891: } |
| 11339 | 1, 7, // 5896: case 0x1: { |
| 11340 | OPC_CheckPredicate, 15, // 5898: check predicate 15 |
| 11341 | OPC_Decode, 192, 25, 166, 2, // 5900: decode to V6_vshufoeh using decoder 294 |
| 11342 | // 5900: } |
| 11343 | 2, 7, // 5905: case 0x2: { |
| 11344 | OPC_CheckPredicate, 15, // 5907: check predicate 15 |
| 11345 | OPC_Decode, 191, 25, 166, 2, // 5909: decode to V6_vshufoeb using decoder 294 |
| 11346 | // 5909: } |
| 11347 | 3, 0, // 5914: case 0x3: { |
| 11348 | OPC_CheckPredicate, 15, // 5916: check predicate 15 |
| 11349 | OPC_Decode, 220, 22, 166, 2, // 5918: decode to V6_vcombine using decoder 294 |
| 11350 | // 5918: } |
| 11351 | // 5918: } // switch Inst[6:5] |
| 11352 | // 5918: } |
| 11353 | 1, 0, // 5923: case 0x1: { |
| 11354 | OPC_CheckPredicate, 22, // 5925: check predicate 22 |
| 11355 | OPC_Decode, 230, 20, 192, 2, // 5927: decode to V6_v6mpyhubs10 using decoder 320 |
| 11356 | // 5927: } |
| 11357 | // 5927: } // switch Inst[13] |
| 11358 | // 5927: } |
| 11359 | // 5927: } // switch Inst[7] |
| 11360 | // 5927: } |
| 11361 | 3, 187, 1, // 5932: case 0x3: { |
| 11362 | OPC_SwitchField, 5, 3, // 5935: switch Inst[7:5] { |
| 11363 | 0, 21, // 5938: case 0x0: { |
| 11364 | OPC_SwitchField, 13, 1, // 5940: switch Inst[13] { |
| 11365 | 0, 7, // 5943: case 0x0: { |
| 11366 | OPC_CheckPredicate, 15, // 5945: check predicate 15 |
| 11367 | OPC_Decode, 190, 24, 160, 2, // 5947: decode to V6_vmpyieoh using decoder 288 |
| 11368 | // 5947: } |
| 11369 | 1, 0, // 5952: case 0x1: { |
| 11370 | OPC_CheckPredicate, 21, // 5954: check predicate 21 |
| 11371 | OPC_Decode, 196, 25, 160, 2, // 5956: decode to V6_vsub_hf_hf using decoder 288 |
| 11372 | // 5956: } |
| 11373 | // 5956: } // switch Inst[13] |
| 11374 | // 5956: } |
| 11375 | 1, 21, // 5961: case 0x1: { |
| 11376 | OPC_SwitchField, 13, 1, // 5963: switch Inst[13] { |
| 11377 | 0, 7, // 5966: case 0x0: { |
| 11378 | OPC_CheckPredicate, 12, // 5968: check predicate 12 |
| 11379 | OPC_Decode, 151, 22, 160, 2, // 5970: decode to V6_vadduwsat using decoder 288 |
| 11380 | // 5970: } |
| 11381 | 1, 0, // 5975: case 0x1: { |
| 11382 | OPC_CheckPredicate, 21, // 5977: check predicate 21 |
| 11383 | OPC_Decode, 248, 22, 160, 2, // 5979: decode to V6_vcvt_hf_sf using decoder 288 |
| 11384 | // 5979: } |
| 11385 | // 5979: } // switch Inst[13] |
| 11386 | // 5979: } |
| 11387 | 2, 21, // 5984: case 0x2: { |
| 11388 | OPC_SwitchField, 13, 1, // 5986: switch Inst[13] { |
| 11389 | 0, 7, // 5989: case 0x0: { |
| 11390 | OPC_CheckPredicate, 15, // 5991: check predicate 15 |
| 11391 | OPC_Decode, 170, 25, 160, 2, // 5993: decode to V6_vsathub using decoder 288 |
| 11392 | // 5993: } |
| 11393 | 1, 0, // 5998: case 0x1: { |
| 11394 | OPC_CheckPredicate, 26, // 6000: check predicate 26 |
| 11395 | OPC_Decode, 243, 21, 160, 2, // 6002: decode to V6_vadd_qf16 using decoder 288 |
| 11396 | // 6002: } |
| 11397 | // 6002: } // switch Inst[13] |
| 11398 | // 6002: } |
| 11399 | 3, 21, // 6007: case 0x3: { |
| 11400 | OPC_SwitchField, 13, 1, // 6009: switch Inst[13] { |
| 11401 | 0, 7, // 6012: case 0x0: { |
| 11402 | OPC_CheckPredicate, 15, // 6014: check predicate 15 |
| 11403 | OPC_Decode, 172, 25, 160, 2, // 6016: decode to V6_vsatwh using decoder 288 |
| 11404 | // 6016: } |
| 11405 | 1, 0, // 6021: case 0x1: { |
| 11406 | OPC_CheckPredicate, 26, // 6023: check predicate 26 |
| 11407 | OPC_Decode, 240, 21, 160, 2, // 6025: decode to V6_vadd_hf using decoder 288 |
| 11408 | // 6025: } |
| 11409 | // 6025: } // switch Inst[13] |
| 11410 | // 6025: } |
| 11411 | 4, 21, // 6030: case 0x4: { |
| 11412 | OPC_SwitchField, 13, 1, // 6032: switch Inst[13] { |
| 11413 | 0, 7, // 6035: case 0x0: { |
| 11414 | OPC_CheckPredicate, 15, // 6037: check predicate 15 |
| 11415 | OPC_Decode, 165, 25, 160, 2, // 6039: decode to V6_vroundwh using decoder 288 |
| 11416 | // 6039: } |
| 11417 | 1, 0, // 6044: case 0x1: { |
| 11418 | OPC_CheckPredicate, 26, // 6046: check predicate 26 |
| 11419 | OPC_Decode, 244, 21, 160, 2, // 6048: decode to V6_vadd_qf16_mix using decoder 288 |
| 11420 | // 6048: } |
| 11421 | // 6048: } // switch Inst[13] |
| 11422 | // 6048: } |
| 11423 | 5, 21, // 6053: case 0x5: { |
| 11424 | OPC_SwitchField, 13, 1, // 6055: switch Inst[13] { |
| 11425 | 0, 7, // 6058: case 0x0: { |
| 11426 | OPC_CheckPredicate, 15, // 6060: check predicate 15 |
| 11427 | OPC_Decode, 166, 25, 160, 2, // 6062: decode to V6_vroundwuh using decoder 288 |
| 11428 | // 6062: } |
| 11429 | 1, 0, // 6067: case 0x1: { |
| 11430 | OPC_CheckPredicate, 26, // 6069: check predicate 26 |
| 11431 | OPC_Decode, 198, 25, 160, 2, // 6071: decode to V6_vsub_qf16 using decoder 288 |
| 11432 | // 6071: } |
| 11433 | // 6071: } // switch Inst[13] |
| 11434 | // 6071: } |
| 11435 | 6, 21, // 6076: case 0x6: { |
| 11436 | OPC_SwitchField, 13, 1, // 6078: switch Inst[13] { |
| 11437 | 0, 7, // 6081: case 0x0: { |
| 11438 | OPC_CheckPredicate, 15, // 6083: check predicate 15 |
| 11439 | OPC_Decode, 161, 25, 160, 2, // 6085: decode to V6_vroundhb using decoder 288 |
| 11440 | // 6085: } |
| 11441 | 1, 0, // 6090: case 0x1: { |
| 11442 | OPC_CheckPredicate, 26, // 6092: check predicate 26 |
| 11443 | OPC_Decode, 194, 25, 160, 2, // 6094: decode to V6_vsub_hf using decoder 288 |
| 11444 | // 6094: } |
| 11445 | // 6094: } // switch Inst[13] |
| 11446 | // 6094: } |
| 11447 | 7, 0, // 6099: case 0x7: { |
| 11448 | OPC_SwitchField, 13, 1, // 6101: switch Inst[13] { |
| 11449 | 0, 7, // 6104: case 0x0: { |
| 11450 | OPC_CheckPredicate, 15, // 6106: check predicate 15 |
| 11451 | OPC_Decode, 162, 25, 160, 2, // 6108: decode to V6_vroundhub using decoder 288 |
| 11452 | // 6108: } |
| 11453 | 1, 0, // 6113: case 0x1: { |
| 11454 | OPC_CheckPredicate, 26, // 6115: check predicate 26 |
| 11455 | OPC_Decode, 199, 25, 160, 2, // 6117: decode to V6_vsub_qf16_mix using decoder 288 |
| 11456 | // 6117: } |
| 11457 | // 6117: } // switch Inst[13] |
| 11458 | // 6117: } |
| 11459 | // 6117: } // switch Inst[7:5] |
| 11460 | // 6117: } |
| 11461 | 4, 130, 2, // 6122: case 0x4: { |
| 11462 | OPC_SwitchField, 5, 3, // 6125: switch Inst[7:5] { |
| 11463 | 0, 89, // 6128: case 0x0: { |
| 11464 | OPC_SwitchField, 13, 1, // 6130: switch Inst[13] { |
| 11465 | 0, 75, // 6133: case 0x0: { |
| 11466 | OPC_SwitchField, 2, 3, // 6135: switch Inst[4:2] { |
| 11467 | 0, 7, // 6138: case 0x0: { |
| 11468 | OPC_CheckPredicate, 15, // 6140: check predicate 15 |
| 11469 | OPC_Decode, 154, 23, 170, 2, // 6142: decode to V6_veqb using decoder 298 |
| 11470 | // 6142: } |
| 11471 | 1, 7, // 6147: case 0x1: { |
| 11472 | OPC_CheckPredicate, 15, // 6149: check predicate 15 |
| 11473 | OPC_Decode, 158, 23, 170, 2, // 6151: decode to V6_veqh using decoder 298 |
| 11474 | // 6151: } |
| 11475 | 2, 7, // 6156: case 0x2: { |
| 11476 | OPC_CheckPredicate, 15, // 6158: check predicate 15 |
| 11477 | OPC_Decode, 170, 23, 170, 2, // 6160: decode to V6_veqw using decoder 298 |
| 11478 | // 6160: } |
| 11479 | 3, 7, // 6165: case 0x3: { |
| 11480 | OPC_CheckPredicate, 18, // 6167: check predicate 18 |
| 11481 | OPC_Decode, 166, 23, 170, 2, // 6169: decode to V6_veqsf using decoder 298 |
| 11482 | // 6169: } |
| 11483 | 4, 7, // 6174: case 0x4: { |
| 11484 | OPC_CheckPredicate, 15, // 6176: check predicate 15 |
| 11485 | OPC_Decode, 189, 23, 170, 2, // 6178: decode to V6_vgtb using decoder 298 |
| 11486 | // 6178: } |
| 11487 | 5, 7, // 6183: case 0x5: { |
| 11488 | OPC_CheckPredicate, 15, // 6185: check predicate 15 |
| 11489 | OPC_Decode, 197, 23, 170, 2, // 6187: decode to V6_vgth using decoder 298 |
| 11490 | // 6187: } |
| 11491 | 6, 7, // 6192: case 0x6: { |
| 11492 | OPC_CheckPredicate, 15, // 6194: check predicate 15 |
| 11493 | OPC_Decode, 221, 23, 170, 2, // 6196: decode to V6_vgtw using decoder 298 |
| 11494 | // 6196: } |
| 11495 | 7, 0, // 6201: case 0x7: { |
| 11496 | OPC_CheckPredicate, 18, // 6203: check predicate 18 |
| 11497 | OPC_Decode, 162, 23, 170, 2, // 6205: decode to V6_veqhf using decoder 298 |
| 11498 | // 6205: } |
| 11499 | // 6205: } // switch Inst[4:2] |
| 11500 | // 6205: } |
| 11501 | 1, 0, // 6210: case 0x1: { |
| 11502 | OPC_CheckPredicate, 26, // 6212: check predicate 26 |
| 11503 | OPC_Decode, 161, 24, 166, 2, // 6214: decode to V6_vmpy_qf32_mix_hf using decoder 294 |
| 11504 | // 6214: } |
| 11505 | // 6214: } // switch Inst[13] |
| 11506 | // 6214: } |
| 11507 | 1, 44, // 6219: case 0x1: { |
| 11508 | OPC_SwitchField, 13, 1, // 6221: switch Inst[13] { |
| 11509 | 0, 30, // 6224: case 0x0: { |
| 11510 | OPC_SwitchField, 2, 3, // 6226: switch Inst[4:2] { |
| 11511 | 0, 7, // 6229: case 0x0: { |
| 11512 | OPC_CheckPredicate, 15, // 6231: check predicate 15 |
| 11513 | OPC_Decode, 209, 23, 170, 2, // 6233: decode to V6_vgtub using decoder 298 |
| 11514 | // 6233: } |
| 11515 | 1, 7, // 6238: case 0x1: { |
| 11516 | OPC_CheckPredicate, 15, // 6240: check predicate 15 |
| 11517 | OPC_Decode, 213, 23, 170, 2, // 6242: decode to V6_vgtuh using decoder 298 |
| 11518 | // 6242: } |
| 11519 | 2, 0, // 6247: case 0x2: { |
| 11520 | OPC_CheckPredicate, 15, // 6249: check predicate 15 |
| 11521 | OPC_Decode, 217, 23, 170, 2, // 6251: decode to V6_vgtuw using decoder 298 |
| 11522 | // 6251: } |
| 11523 | // 6251: } // switch Inst[4:2] |
| 11524 | // 6251: } |
| 11525 | 1, 0, // 6256: case 0x1: { |
| 11526 | OPC_CheckPredicate, 21, // 6258: check predicate 21 |
| 11527 | OPC_Decode, 171, 24, 160, 2, // 6260: decode to V6_vmpy_sf_sf using decoder 288 |
| 11528 | // 6260: } |
| 11529 | // 6260: } // switch Inst[13] |
| 11530 | // 6260: } |
| 11531 | 2, 11, // 6265: case 0x2: { |
| 11532 | OPC_CheckPredicate, 21, // 6267: check predicate 21 |
| 11533 | OPC_CheckField, 13, 1, 1, // 6269: check Inst[13] == 0x1 |
| 11534 | OPC_Decode, 169, 24, 166, 2, // 6273: decode to V6_vmpy_sf_hf using decoder 294 |
| 11535 | // 6273: } |
| 11536 | 3, 11, // 6278: case 0x3: { |
| 11537 | OPC_CheckPredicate, 21, // 6280: check predicate 21 |
| 11538 | OPC_CheckField, 13, 1, 1, // 6282: check Inst[13] == 0x1 |
| 11539 | OPC_Decode, 154, 24, 160, 2, // 6286: decode to V6_vmpy_hf_hf using decoder 288 |
| 11540 | // 6286: } |
| 11541 | 4, 21, // 6291: case 0x4: { |
| 11542 | OPC_SwitchField, 13, 1, // 6293: switch Inst[13] { |
| 11543 | 0, 7, // 6296: case 0x0: { |
| 11544 | OPC_CheckPredicate, 20, // 6298: check predicate 20 |
| 11545 | OPC_Decode, 241, 21, 166, 2, // 6300: decode to V6_vadd_hf_f8 using decoder 294 |
| 11546 | // 6300: } |
| 11547 | 1, 0, // 6305: case 0x1: { |
| 11548 | OPC_CheckPredicate, 21, // 6307: check predicate 21 |
| 11549 | OPC_Decode, 249, 21, 166, 2, // 6309: decode to V6_vadd_sf_hf using decoder 294 |
| 11550 | // 6309: } |
| 11551 | // 6309: } // switch Inst[13] |
| 11552 | // 6309: } |
| 11553 | 5, 21, // 6314: case 0x5: { |
| 11554 | OPC_SwitchField, 13, 1, // 6316: switch Inst[13] { |
| 11555 | 0, 7, // 6319: case 0x0: { |
| 11556 | OPC_CheckPredicate, 20, // 6321: check predicate 20 |
| 11557 | OPC_Decode, 195, 25, 166, 2, // 6323: decode to V6_vsub_hf_f8 using decoder 294 |
| 11558 | // 6323: } |
| 11559 | 1, 0, // 6328: case 0x1: { |
| 11560 | OPC_CheckPredicate, 21, // 6330: check predicate 21 |
| 11561 | OPC_Decode, 204, 25, 166, 2, // 6332: decode to V6_vsub_sf_hf using decoder 294 |
| 11562 | // 6332: } |
| 11563 | // 6332: } // switch Inst[13] |
| 11564 | // 6332: } |
| 11565 | 6, 21, // 6337: case 0x6: { |
| 11566 | OPC_SwitchField, 13, 1, // 6339: switch Inst[13] { |
| 11567 | 0, 7, // 6342: case 0x0: { |
| 11568 | OPC_CheckPredicate, 20, // 6344: check predicate 20 |
| 11569 | OPC_Decode, 152, 24, 166, 2, // 6346: decode to V6_vmpy_hf_f8 using decoder 294 |
| 11570 | // 6346: } |
| 11571 | 1, 0, // 6351: case 0x1: { |
| 11572 | OPC_CheckPredicate, 21, // 6353: check predicate 21 |
| 11573 | OPC_Decode, 250, 21, 160, 2, // 6355: decode to V6_vadd_sf_sf using decoder 288 |
| 11574 | // 6355: } |
| 11575 | // 6355: } // switch Inst[13] |
| 11576 | // 6355: } |
| 11577 | 7, 0, // 6360: case 0x7: { |
| 11578 | OPC_SwitchField, 13, 1, // 6362: switch Inst[13] { |
| 11579 | 0, 7, // 6365: case 0x0: { |
| 11580 | OPC_CheckPredicate, 20, // 6367: check predicate 20 |
| 11581 | OPC_Decode, 153, 24, 162, 2, // 6369: decode to V6_vmpy_hf_f8_acc using decoder 290 |
| 11582 | // 6369: } |
| 11583 | 1, 0, // 6374: case 0x1: { |
| 11584 | OPC_CheckPredicate, 21, // 6376: check predicate 21 |
| 11585 | OPC_Decode, 206, 25, 160, 2, // 6378: decode to V6_vsub_sf_sf using decoder 288 |
| 11586 | // 6378: } |
| 11587 | // 6378: } // switch Inst[13] |
| 11588 | // 6378: } |
| 11589 | // 6378: } // switch Inst[7:5] |
| 11590 | // 6378: } |
| 11591 | 5, 187, 1, // 6383: case 0x5: { |
| 11592 | OPC_SwitchField, 5, 3, // 6386: switch Inst[7:5] { |
| 11593 | 0, 21, // 6389: case 0x0: { |
| 11594 | OPC_SwitchField, 13, 1, // 6391: switch Inst[13] { |
| 11595 | 0, 7, // 6394: case 0x0: { |
| 11596 | OPC_CheckPredicate, 15, // 6396: check predicate 15 |
| 11597 | OPC_Decode, 200, 22, 160, 2, // 6398: decode to V6_vasrwv using decoder 288 |
| 11598 | // 6398: } |
| 11599 | 1, 0, // 6403: case 0x1: { |
| 11600 | OPC_CheckPredicate, 26, // 6405: check predicate 26 |
| 11601 | OPC_Decode, 245, 21, 160, 2, // 6407: decode to V6_vadd_qf32 using decoder 288 |
| 11602 | // 6407: } |
| 11603 | // 6407: } // switch Inst[13] |
| 11604 | // 6407: } |
| 11605 | 1, 21, // 6412: case 0x1: { |
| 11606 | OPC_SwitchField, 13, 1, // 6414: switch Inst[13] { |
| 11607 | 0, 7, // 6417: case 0x0: { |
| 11608 | OPC_CheckPredicate, 15, // 6419: check predicate 15 |
| 11609 | OPC_Decode, 238, 23, 160, 2, // 6421: decode to V6_vlsrwv using decoder 288 |
| 11610 | // 6421: } |
| 11611 | 1, 0, // 6426: case 0x1: { |
| 11612 | OPC_CheckPredicate, 26, // 6428: check predicate 26 |
| 11613 | OPC_Decode, 247, 21, 160, 2, // 6430: decode to V6_vadd_sf using decoder 288 |
| 11614 | // 6430: } |
| 11615 | // 6430: } // switch Inst[13] |
| 11616 | // 6430: } |
| 11617 | 2, 21, // 6435: case 0x2: { |
| 11618 | OPC_SwitchField, 13, 1, // 6437: switch Inst[13] { |
| 11619 | 0, 7, // 6440: case 0x0: { |
| 11620 | OPC_CheckPredicate, 15, // 6442: check predicate 15 |
| 11621 | OPC_Decode, 236, 23, 160, 2, // 6444: decode to V6_vlsrhv using decoder 288 |
| 11622 | // 6444: } |
| 11623 | 1, 0, // 6449: case 0x1: { |
| 11624 | OPC_CheckPredicate, 26, // 6451: check predicate 26 |
| 11625 | OPC_Decode, 246, 21, 160, 2, // 6453: decode to V6_vadd_qf32_mix using decoder 288 |
| 11626 | // 6453: } |
| 11627 | // 6453: } // switch Inst[13] |
| 11628 | // 6453: } |
| 11629 | 3, 21, // 6458: case 0x3: { |
| 11630 | OPC_SwitchField, 13, 1, // 6460: switch Inst[13] { |
| 11631 | 0, 7, // 6463: case 0x0: { |
| 11632 | OPC_CheckPredicate, 15, // 6465: check predicate 15 |
| 11633 | OPC_Decode, 184, 22, 160, 2, // 6467: decode to V6_vasrhv using decoder 288 |
| 11634 | // 6467: } |
| 11635 | 1, 0, // 6472: case 0x1: { |
| 11636 | OPC_CheckPredicate, 26, // 6474: check predicate 26 |
| 11637 | OPC_Decode, 200, 25, 160, 2, // 6476: decode to V6_vsub_qf32 using decoder 288 |
| 11638 | // 6476: } |
| 11639 | // 6476: } // switch Inst[13] |
| 11640 | // 6476: } |
| 11641 | 4, 21, // 6481: case 0x4: { |
| 11642 | OPC_SwitchField, 13, 1, // 6483: switch Inst[13] { |
| 11643 | 0, 7, // 6486: case 0x0: { |
| 11644 | OPC_CheckPredicate, 15, // 6488: check predicate 15 |
| 11645 | OPC_Decode, 176, 22, 160, 2, // 6490: decode to V6_vaslwv using decoder 288 |
| 11646 | // 6490: } |
| 11647 | 1, 0, // 6495: case 0x1: { |
| 11648 | OPC_CheckPredicate, 26, // 6497: check predicate 26 |
| 11649 | OPC_Decode, 202, 25, 160, 2, // 6499: decode to V6_vsub_sf using decoder 288 |
| 11650 | // 6499: } |
| 11651 | // 6499: } // switch Inst[13] |
| 11652 | // 6499: } |
| 11653 | 5, 21, // 6504: case 0x5: { |
| 11654 | OPC_SwitchField, 13, 1, // 6506: switch Inst[13] { |
| 11655 | 0, 7, // 6509: case 0x0: { |
| 11656 | OPC_CheckPredicate, 15, // 6511: check predicate 15 |
| 11657 | OPC_Decode, 173, 22, 160, 2, // 6513: decode to V6_vaslhv using decoder 288 |
| 11658 | // 6513: } |
| 11659 | 1, 0, // 6518: case 0x1: { |
| 11660 | OPC_CheckPredicate, 26, // 6520: check predicate 26 |
| 11661 | OPC_Decode, 201, 25, 160, 2, // 6522: decode to V6_vsub_qf32_mix using decoder 288 |
| 11662 | // 6522: } |
| 11663 | // 6522: } // switch Inst[13] |
| 11664 | // 6522: } |
| 11665 | 6, 21, // 6527: case 0x6: { |
| 11666 | OPC_SwitchField, 13, 1, // 6529: switch Inst[13] { |
| 11667 | 0, 7, // 6532: case 0x0: { |
| 11668 | OPC_CheckPredicate, 15, // 6534: check predicate 15 |
| 11669 | OPC_Decode, 251, 21, 160, 2, // 6536: decode to V6_vaddb using decoder 288 |
| 11670 | // 6536: } |
| 11671 | 1, 0, // 6541: case 0x1: { |
| 11672 | OPC_CheckPredicate, 21, // 6543: check predicate 21 |
| 11673 | OPC_Decode, 132, 23, 160, 2, // 6545: decode to V6_vdmpy_sf_hf using decoder 288 |
| 11674 | // 6545: } |
| 11675 | // 6545: } // switch Inst[13] |
| 11676 | // 6545: } |
| 11677 | 7, 0, // 6550: case 0x7: { |
| 11678 | OPC_SwitchField, 13, 1, // 6552: switch Inst[13] { |
| 11679 | 0, 7, // 6555: case 0x0: { |
| 11680 | OPC_CheckPredicate, 15, // 6557: check predicate 15 |
| 11681 | OPC_Decode, 134, 22, 160, 2, // 6559: decode to V6_vaddh using decoder 288 |
| 11682 | // 6559: } |
| 11683 | 1, 0, // 6564: case 0x1: { |
| 11684 | OPC_CheckPredicate, 21, // 6566: check predicate 21 |
| 11685 | OPC_Decode, 242, 21, 160, 2, // 6568: decode to V6_vadd_hf_hf using decoder 288 |
| 11686 | // 6568: } |
| 11687 | // 6568: } // switch Inst[13] |
| 11688 | // 6568: } |
| 11689 | // 6568: } // switch Inst[7:5] |
| 11690 | // 6568: } |
| 11691 | 6, 177, 1, // 6573: case 0x6: { |
| 11692 | OPC_SwitchField, 5, 3, // 6576: switch Inst[7:5] { |
| 11693 | 0, 11, // 6579: case 0x0: { |
| 11694 | OPC_CheckPredicate, 15, // 6581: check predicate 15 |
| 11695 | OPC_CheckField, 13, 1, 0, // 6583: check Inst[13] == 0x0 |
| 11696 | OPC_Decode, 192, 24, 160, 2, // 6587: decode to V6_vmpyiewuh using decoder 288 |
| 11697 | // 6587: } |
| 11698 | 1, 21, // 6592: case 0x1: { |
| 11699 | OPC_SwitchField, 13, 1, // 6594: switch Inst[13] { |
| 11700 | 0, 7, // 6597: case 0x0: { |
| 11701 | OPC_CheckPredicate, 15, // 6599: check predicate 15 |
| 11702 | OPC_Decode, 198, 24, 160, 2, // 6601: decode to V6_vmpyiowh using decoder 288 |
| 11703 | // 6601: } |
| 11704 | 1, 0, // 6606: case 0x1: { |
| 11705 | OPC_CheckPredicate, 26, // 6608: check predicate 26 |
| 11706 | OPC_Decode, 252, 23, 160, 2, // 6610: decode to V6_vmax_sf using decoder 288 |
| 11707 | // 6610: } |
| 11708 | // 6610: } // switch Inst[13] |
| 11709 | // 6610: } |
| 11710 | 2, 21, // 6615: case 0x2: { |
| 11711 | OPC_SwitchField, 13, 1, // 6617: switch Inst[13] { |
| 11712 | 0, 7, // 6620: case 0x0: { |
| 11713 | OPC_CheckPredicate, 15, // 6622: check predicate 15 |
| 11714 | OPC_Decode, 236, 24, 160, 2, // 6624: decode to V6_vpackeb using decoder 288 |
| 11715 | // 6624: } |
| 11716 | 1, 0, // 6629: case 0x1: { |
| 11717 | OPC_CheckPredicate, 26, // 6631: check predicate 26 |
| 11718 | OPC_Decode, 133, 24, 160, 2, // 6633: decode to V6_vmin_sf using decoder 288 |
| 11719 | // 6633: } |
| 11720 | // 6633: } // switch Inst[13] |
| 11721 | // 6633: } |
| 11722 | 3, 21, // 6638: case 0x3: { |
| 11723 | OPC_SwitchField, 13, 1, // 6640: switch Inst[13] { |
| 11724 | 0, 7, // 6643: case 0x0: { |
| 11725 | OPC_CheckPredicate, 15, // 6645: check predicate 15 |
| 11726 | OPC_Decode, 237, 24, 160, 2, // 6647: decode to V6_vpackeh using decoder 288 |
| 11727 | // 6647: } |
| 11728 | 1, 0, // 6652: case 0x1: { |
| 11729 | OPC_CheckPredicate, 26, // 6654: check predicate 26 |
| 11730 | OPC_Decode, 251, 23, 160, 2, // 6656: decode to V6_vmax_hf using decoder 288 |
| 11731 | // 6656: } |
| 11732 | // 6656: } // switch Inst[13] |
| 11733 | // 6656: } |
| 11734 | 4, 21, // 6661: case 0x4: { |
| 11735 | OPC_SwitchField, 13, 1, // 6663: switch Inst[13] { |
| 11736 | 0, 7, // 6666: case 0x0: { |
| 11737 | OPC_CheckPredicate, 12, // 6668: check predicate 12 |
| 11738 | OPC_Decode, 229, 25, 160, 2, // 6670: decode to V6_vsubuwsat using decoder 288 |
| 11739 | // 6670: } |
| 11740 | 1, 0, // 6675: case 0x1: { |
| 11741 | OPC_CheckPredicate, 26, // 6677: check predicate 26 |
| 11742 | OPC_Decode, 132, 24, 160, 2, // 6679: decode to V6_vmin_hf using decoder 288 |
| 11743 | // 6679: } |
| 11744 | // 6679: } // switch Inst[13] |
| 11745 | // 6679: } |
| 11746 | 5, 21, // 6684: case 0x5: { |
| 11747 | OPC_SwitchField, 13, 1, // 6686: switch Inst[13] { |
| 11748 | 0, 7, // 6689: case 0x0: { |
| 11749 | OPC_CheckPredicate, 15, // 6691: check predicate 15 |
| 11750 | OPC_Decode, 239, 24, 160, 2, // 6693: decode to V6_vpackhub_sat using decoder 288 |
| 11751 | // 6693: } |
| 11752 | 1, 0, // 6698: case 0x1: { |
| 11753 | OPC_CheckPredicate, 21, // 6700: check predicate 21 |
| 11754 | OPC_Decode, 252, 22, 160, 2, // 6702: decode to V6_vcvt_ub_hf using decoder 288 |
| 11755 | // 6702: } |
| 11756 | // 6702: } // switch Inst[13] |
| 11757 | // 6702: } |
| 11758 | 6, 21, // 6707: case 0x6: { |
| 11759 | OPC_SwitchField, 13, 1, // 6709: switch Inst[13] { |
| 11760 | 0, 7, // 6712: case 0x0: { |
| 11761 | OPC_CheckPredicate, 15, // 6714: check predicate 15 |
| 11762 | OPC_Decode, 238, 24, 160, 2, // 6716: decode to V6_vpackhb_sat using decoder 288 |
| 11763 | // 6716: } |
| 11764 | 1, 0, // 6721: case 0x1: { |
| 11765 | OPC_CheckPredicate, 21, // 6723: check predicate 21 |
| 11766 | OPC_Decode, 241, 22, 160, 2, // 6725: decode to V6_vcvt_b_hf using decoder 288 |
| 11767 | // 6725: } |
| 11768 | // 6725: } // switch Inst[13] |
| 11769 | // 6725: } |
| 11770 | 7, 0, // 6730: case 0x7: { |
| 11771 | OPC_SwitchField, 13, 1, // 6732: switch Inst[13] { |
| 11772 | 0, 7, // 6735: case 0x0: { |
| 11773 | OPC_CheckPredicate, 15, // 6737: check predicate 15 |
| 11774 | OPC_Decode, 243, 24, 160, 2, // 6739: decode to V6_vpackwuh_sat using decoder 288 |
| 11775 | // 6739: } |
| 11776 | 1, 0, // 6744: case 0x1: { |
| 11777 | OPC_CheckPredicate, 24, // 6746: check predicate 24 |
| 11778 | OPC_Decode, 220, 24, 160, 2, // 6748: decode to V6_vmpyuhvs using decoder 288 |
| 11779 | // 6748: } |
| 11780 | // 6748: } // switch Inst[13] |
| 11781 | // 6748: } |
| 11782 | // 6748: } // switch Inst[7:5] |
| 11783 | // 6748: } |
| 11784 | 7, 0, // 6753: case 0x7: { |
| 11785 | OPC_SwitchField, 5, 3, // 6755: switch Inst[7:5] { |
| 11786 | 0, 21, // 6758: case 0x0: { |
| 11787 | OPC_SwitchField, 13, 1, // 6760: switch Inst[13] { |
| 11788 | 0, 7, // 6763: case 0x0: { |
| 11789 | OPC_CheckPredicate, 15, // 6765: check predicate 15 |
| 11790 | OPC_Decode, 242, 24, 160, 2, // 6767: decode to V6_vpackwh_sat using decoder 288 |
| 11791 | // 6767: } |
| 11792 | 1, 0, // 6772: case 0x1: { |
| 11793 | OPC_CheckPredicate, 26, // 6774: check predicate 26 |
| 11794 | OPC_Decode, 159, 24, 160, 2, // 6776: decode to V6_vmpy_qf32 using decoder 288 |
| 11795 | // 6776: } |
| 11796 | // 6776: } // switch Inst[13] |
| 11797 | // 6776: } |
| 11798 | 1, 21, // 6781: case 0x1: { |
| 11799 | OPC_SwitchField, 13, 1, // 6783: switch Inst[13] { |
| 11800 | 0, 7, // 6786: case 0x0: { |
| 11801 | OPC_CheckPredicate, 15, // 6788: check predicate 15 |
| 11802 | OPC_Decode, 240, 24, 160, 2, // 6790: decode to V6_vpackob using decoder 288 |
| 11803 | // 6790: } |
| 11804 | 1, 0, // 6795: case 0x1: { |
| 11805 | OPC_CheckPredicate, 26, // 6797: check predicate 26 |
| 11806 | OPC_Decode, 163, 24, 160, 2, // 6799: decode to V6_vmpy_qf32_sf using decoder 288 |
| 11807 | // 6799: } |
| 11808 | // 6799: } // switch Inst[13] |
| 11809 | // 6799: } |
| 11810 | 2, 21, // 6804: case 0x2: { |
| 11811 | OPC_SwitchField, 13, 1, // 6806: switch Inst[13] { |
| 11812 | 0, 7, // 6809: case 0x0: { |
| 11813 | OPC_CheckPredicate, 15, // 6811: check predicate 15 |
| 11814 | OPC_Decode, 241, 24, 160, 2, // 6813: decode to V6_vpackoh using decoder 288 |
| 11815 | // 6813: } |
| 11816 | 1, 0, // 6818: case 0x1: { |
| 11817 | OPC_CheckPredicate, 20, // 6820: check predicate 20 |
| 11818 | OPC_Decode, 243, 22, 160, 2, // 6822: decode to V6_vcvt_f8_hf using decoder 288 |
| 11819 | // 6822: } |
| 11820 | // 6822: } // switch Inst[13] |
| 11821 | // 6822: } |
| 11822 | 3, 21, // 6827: case 0x3: { |
| 11823 | OPC_SwitchField, 13, 1, // 6829: switch Inst[13] { |
| 11824 | 0, 7, // 6832: case 0x0: { |
| 11825 | OPC_CheckPredicate, 12, // 6834: check predicate 12 |
| 11826 | OPC_Decode, 163, 25, 160, 2, // 6836: decode to V6_vrounduhub using decoder 288 |
| 11827 | // 6836: } |
| 11828 | 1, 0, // 6841: case 0x1: { |
| 11829 | OPC_CheckPredicate, 26, // 6843: check predicate 26 |
| 11830 | OPC_Decode, 156, 24, 160, 2, // 6845: decode to V6_vmpy_qf16 using decoder 288 |
| 11831 | // 6845: } |
| 11832 | // 6845: } // switch Inst[13] |
| 11833 | // 6845: } |
| 11834 | 4, 21, // 6850: case 0x4: { |
| 11835 | OPC_SwitchField, 13, 1, // 6852: switch Inst[13] { |
| 11836 | 0, 7, // 6855: case 0x0: { |
| 11837 | OPC_CheckPredicate, 12, // 6857: check predicate 12 |
| 11838 | OPC_Decode, 164, 25, 160, 2, // 6859: decode to V6_vrounduwuh using decoder 288 |
| 11839 | // 6859: } |
| 11840 | 1, 0, // 6864: case 0x1: { |
| 11841 | OPC_CheckPredicate, 26, // 6866: check predicate 26 |
| 11842 | OPC_Decode, 157, 24, 160, 2, // 6868: decode to V6_vmpy_qf16_hf using decoder 288 |
| 11843 | // 6868: } |
| 11844 | // 6868: } // switch Inst[13] |
| 11845 | // 6868: } |
| 11846 | 5, 21, // 6873: case 0x5: { |
| 11847 | OPC_SwitchField, 13, 1, // 6875: switch Inst[13] { |
| 11848 | 0, 7, // 6878: case 0x0: { |
| 11849 | OPC_CheckPredicate, 15, // 6880: check predicate 15 |
| 11850 | OPC_Decode, 178, 24, 160, 2, // 6882: decode to V6_vmpyewuh using decoder 288 |
| 11851 | // 6882: } |
| 11852 | 1, 0, // 6887: case 0x1: { |
| 11853 | OPC_CheckPredicate, 26, // 6889: check predicate 26 |
| 11854 | OPC_Decode, 158, 24, 160, 2, // 6891: decode to V6_vmpy_qf16_mix_hf using decoder 288 |
| 11855 | // 6891: } |
| 11856 | // 6891: } // switch Inst[13] |
| 11857 | // 6891: } |
| 11858 | 6, 11, // 6896: case 0x6: { |
| 11859 | OPC_CheckPredicate, 26, // 6898: check predicate 26 |
| 11860 | OPC_CheckField, 13, 1, 1, // 6900: check Inst[13] == 0x1 |
| 11861 | OPC_Decode, 162, 24, 166, 2, // 6904: decode to V6_vmpy_qf32_qf16 using decoder 294 |
| 11862 | // 6904: } |
| 11863 | 7, 0, // 6909: case 0x7: { |
| 11864 | OPC_SwitchField, 13, 1, // 6911: switch Inst[13] { |
| 11865 | 0, 7, // 6914: case 0x0: { |
| 11866 | OPC_CheckPredicate, 15, // 6916: check predicate 15 |
| 11867 | OPC_Decode, 205, 24, 160, 2, // 6918: decode to V6_vmpyowh using decoder 288 |
| 11868 | // 6918: } |
| 11869 | 1, 0, // 6923: case 0x1: { |
| 11870 | OPC_CheckPredicate, 26, // 6925: check predicate 26 |
| 11871 | OPC_Decode, 160, 24, 166, 2, // 6927: decode to V6_vmpy_qf32_hf using decoder 294 |
| 11872 | // 6927: } |
| 11873 | // 6927: } // switch Inst[13] |
| 11874 | // 6927: } |
| 11875 | // 6927: } // switch Inst[7:5] |
| 11876 | // 6927: } |
| 11877 | // 6927: } // switch Inst[23:21] |
| 11878 | // 6927: } |
| 11879 | 40, 219, 3, // 6932: case 0x28: { |
| 11880 | OPC_SwitchField, 5, 3, // 6935: switch Inst[7:5] { |
| 11881 | 0, 91, // 6938: case 0x0: { |
| 11882 | OPC_SwitchField, 21, 3, // 6940: switch Inst[23:21] { |
| 11883 | 0, 11, // 6943: case 0x0: { |
| 11884 | OPC_CheckPredicate, 15, // 6945: check predicate 15 |
| 11885 | OPC_CheckField, 11, 2, 0, // 6947: check Inst[12:11] == 0x0 |
| 11886 | OPC_Decode, 237, 20, 193, 2, // 6951: decode to V6_vL32b_ai using decoder 321 |
| 11887 | // 6951: } |
| 11888 | 1, 11, // 6956: case 0x1: { |
| 11889 | OPC_CheckPredicate, 15, // 6958: check predicate 15 |
| 11890 | OPC_CheckField, 11, 2, 0, // 6960: check Inst[12:11] == 0x0 |
| 11891 | OPC_Decode, 172, 21, 194, 2, // 6964: decode to V6_vS32b_ai using decoder 322 |
| 11892 | // 6964: } |
| 11893 | 2, 11, // 6969: case 0x2: { |
| 11894 | OPC_CheckPredicate, 15, // 6971: check predicate 15 |
| 11895 | OPC_CheckField, 11, 2, 0, // 6973: check Inst[12:11] == 0x0 |
| 11896 | OPC_Decode, 250, 20, 193, 2, // 6977: decode to V6_vL32b_nt_ai using decoder 321 |
| 11897 | // 6977: } |
| 11898 | 3, 11, // 6982: case 0x3: { |
| 11899 | OPC_CheckPredicate, 15, // 6984: check predicate 15 |
| 11900 | OPC_CheckField, 11, 2, 0, // 6986: check Inst[12:11] == 0x0 |
| 11901 | OPC_Decode, 188, 21, 194, 2, // 6990: decode to V6_vS32b_nt_ai using decoder 322 |
| 11902 | // 6990: } |
| 11903 | 4, 7, // 6995: case 0x4: { |
| 11904 | OPC_CheckPredicate, 15, // 6997: check predicate 15 |
| 11905 | OPC_Decode, 217, 21, 195, 2, // 6999: decode to V6_vS32b_qpred_ai using decoder 323 |
| 11906 | // 6999: } |
| 11907 | 5, 7, // 7004: case 0x5: { |
| 11908 | OPC_CheckPredicate, 15, // 7006: check predicate 15 |
| 11909 | OPC_Decode, 214, 21, 196, 2, // 7008: decode to V6_vS32b_pred_ai using decoder 324 |
| 11910 | // 7008: } |
| 11911 | 6, 7, // 7013: case 0x6: { |
| 11912 | OPC_CheckPredicate, 15, // 7015: check predicate 15 |
| 11913 | OPC_Decode, 209, 21, 195, 2, // 7017: decode to V6_vS32b_nt_qpred_ai using decoder 323 |
| 11914 | // 7017: } |
| 11915 | 7, 0, // 7022: case 0x7: { |
| 11916 | OPC_CheckPredicate, 15, // 7024: check predicate 15 |
| 11917 | OPC_Decode, 206, 21, 196, 2, // 7026: decode to V6_vS32b_nt_pred_ai using decoder 324 |
| 11918 | // 7026: } |
| 11919 | // 7026: } // switch Inst[23:21] |
| 11920 | // 7026: } |
| 11921 | 1, 117, // 7031: case 0x1: { |
| 11922 | OPC_SwitchField, 21, 3, // 7033: switch Inst[23:21] { |
| 11923 | 0, 11, // 7036: case 0x0: { |
| 11924 | OPC_CheckPredicate, 15, // 7038: check predicate 15 |
| 11925 | OPC_CheckField, 11, 2, 0, // 7040: check Inst[12:11] == 0x0 |
| 11926 | OPC_Decode, 238, 20, 193, 2, // 7044: decode to V6_vL32b_cur_ai using decoder 321 |
| 11927 | // 7044: } |
| 11928 | 1, 33, // 7049: case 0x1: { |
| 11929 | OPC_SwitchField, 3, 2, // 7051: switch Inst[4:3] { |
| 11930 | 0, 11, // 7054: case 0x0: { |
| 11931 | OPC_CheckPredicate, 15, // 7056: check predicate 15 |
| 11932 | OPC_CheckField, 11, 2, 0, // 7058: check Inst[12:11] == 0x0 |
| 11933 | OPC_Decode, 173, 21, 197, 2, // 7062: decode to V6_vS32b_new_ai using decoder 325 |
| 11934 | // 7062: } |
| 11935 | 1, 0, // 7067: case 0x1: { |
| 11936 | OPC_CheckPredicate, 13, // 7069: check predicate 13 |
| 11937 | OPC_CheckField, 11, 2, 0, // 7071: check Inst[12:11] == 0x0 |
| 11938 | OPC_CheckField, 0, 3, 0, // 7075: check Inst[2:0] == 0x0 |
| 11939 | OPC_Decode, 220, 21, 198, 2, // 7079: decode to V6_vS32b_srls_ai using decoder 326 |
| 11940 | // 7079: } |
| 11941 | // 7079: } // switch Inst[4:3] |
| 11942 | // 7079: } |
| 11943 | 2, 11, // 7084: case 0x2: { |
| 11944 | OPC_CheckPredicate, 15, // 7086: check predicate 15 |
| 11945 | OPC_CheckField, 11, 2, 0, // 7088: check Inst[12:11] == 0x0 |
| 11946 | OPC_Decode, 251, 20, 193, 2, // 7092: decode to V6_vL32b_nt_cur_ai using decoder 321 |
| 11947 | // 7092: } |
| 11948 | 3, 15, // 7097: case 0x3: { |
| 11949 | OPC_CheckPredicate, 15, // 7099: check predicate 15 |
| 11950 | OPC_CheckField, 11, 2, 0, // 7101: check Inst[12:11] == 0x0 |
| 11951 | OPC_CheckField, 3, 2, 0, // 7105: check Inst[4:3] == 0x0 |
| 11952 | OPC_Decode, 189, 21, 197, 2, // 7109: decode to V6_vS32b_nt_new_ai using decoder 325 |
| 11953 | // 7109: } |
| 11954 | 4, 7, // 7114: case 0x4: { |
| 11955 | OPC_CheckPredicate, 15, // 7116: check predicate 15 |
| 11956 | OPC_Decode, 185, 21, 195, 2, // 7118: decode to V6_vS32b_nqpred_ai using decoder 323 |
| 11957 | // 7118: } |
| 11958 | 5, 7, // 7123: case 0x5: { |
| 11959 | OPC_CheckPredicate, 15, // 7125: check predicate 15 |
| 11960 | OPC_Decode, 182, 21, 196, 2, // 7127: decode to V6_vS32b_npred_ai using decoder 324 |
| 11961 | // 7127: } |
| 11962 | 6, 7, // 7132: case 0x6: { |
| 11963 | OPC_CheckPredicate, 15, // 7134: check predicate 15 |
| 11964 | OPC_Decode, 201, 21, 195, 2, // 7136: decode to V6_vS32b_nt_nqpred_ai using decoder 323 |
| 11965 | // 7136: } |
| 11966 | 7, 0, // 7141: case 0x7: { |
| 11967 | OPC_CheckPredicate, 15, // 7143: check predicate 15 |
| 11968 | OPC_Decode, 198, 21, 196, 2, // 7145: decode to V6_vS32b_nt_npred_ai using decoder 324 |
| 11969 | // 7145: } |
| 11970 | // 7145: } // switch Inst[23:21] |
| 11971 | // 7145: } |
| 11972 | 2, 73, // 7150: case 0x2: { |
| 11973 | OPC_SwitchField, 21, 3, // 7152: switch Inst[23:21] { |
| 11974 | 0, 11, // 7155: case 0x0: { |
| 11975 | OPC_CheckPredicate, 15, // 7157: check predicate 15 |
| 11976 | OPC_CheckField, 11, 2, 0, // 7159: check Inst[12:11] == 0x0 |
| 11977 | OPC_Decode, 154, 21, 193, 2, // 7163: decode to V6_vL32b_tmp_ai using decoder 321 |
| 11978 | // 7163: } |
| 11979 | 2, 11, // 7168: case 0x2: { |
| 11980 | OPC_CheckPredicate, 15, // 7170: check predicate 15 |
| 11981 | OPC_CheckField, 11, 2, 0, // 7172: check Inst[12:11] == 0x0 |
| 11982 | OPC_Decode, 140, 21, 193, 2, // 7176: decode to V6_vL32b_nt_tmp_ai using decoder 321 |
| 11983 | // 7176: } |
| 11984 | 4, 7, // 7181: case 0x4: { |
| 11985 | OPC_CheckPredicate, 12, // 7183: check predicate 12 |
| 11986 | OPC_Decode, 151, 21, 199, 2, // 7185: decode to V6_vL32b_pred_ai using decoder 327 |
| 11987 | // 7185: } |
| 11988 | 5, 11, // 7190: case 0x5: { |
| 11989 | OPC_CheckPredicate, 15, // 7192: check predicate 15 |
| 11990 | OPC_CheckField, 3, 2, 0, // 7194: check Inst[4:3] == 0x0 |
| 11991 | OPC_Decode, 179, 21, 200, 2, // 7198: decode to V6_vS32b_new_pred_ai using decoder 328 |
| 11992 | // 7198: } |
| 11993 | 6, 7, // 7203: case 0x6: { |
| 11994 | OPC_CheckPredicate, 12, // 7205: check predicate 12 |
| 11995 | OPC_Decode, 137, 21, 199, 2, // 7207: decode to V6_vL32b_nt_pred_ai using decoder 327 |
| 11996 | // 7207: } |
| 11997 | 7, 0, // 7212: case 0x7: { |
| 11998 | OPC_CheckPredicate, 15, // 7214: check predicate 15 |
| 11999 | OPC_CheckField, 3, 2, 2, // 7216: check Inst[4:3] == 0x2 |
| 12000 | OPC_Decode, 195, 21, 200, 2, // 7220: decode to V6_vS32b_nt_new_pred_ai using decoder 328 |
| 12001 | // 7220: } |
| 12002 | // 7220: } // switch Inst[23:21] |
| 12003 | // 7220: } |
| 12004 | 3, 47, // 7225: case 0x3: { |
| 12005 | OPC_SwitchField, 21, 3, // 7227: switch Inst[23:21] { |
| 12006 | 4, 7, // 7230: case 0x4: { |
| 12007 | OPC_CheckPredicate, 12, // 7232: check predicate 12 |
| 12008 | OPC_Decode, 247, 20, 199, 2, // 7234: decode to V6_vL32b_npred_ai using decoder 327 |
| 12009 | // 7234: } |
| 12010 | 5, 11, // 7239: case 0x5: { |
| 12011 | OPC_CheckPredicate, 15, // 7241: check predicate 15 |
| 12012 | OPC_CheckField, 3, 2, 1, // 7243: check Inst[4:3] == 0x1 |
| 12013 | OPC_Decode, 174, 21, 200, 2, // 7247: decode to V6_vS32b_new_npred_ai using decoder 328 |
| 12014 | // 7247: } |
| 12015 | 6, 7, // 7252: case 0x6: { |
| 12016 | OPC_CheckPredicate, 12, // 7254: check predicate 12 |
| 12017 | OPC_Decode, 132, 21, 199, 2, // 7256: decode to V6_vL32b_nt_npred_ai using decoder 327 |
| 12018 | // 7256: } |
| 12019 | 7, 0, // 7261: case 0x7: { |
| 12020 | OPC_CheckPredicate, 15, // 7263: check predicate 15 |
| 12021 | OPC_CheckField, 3, 2, 3, // 7265: check Inst[4:3] == 0x3 |
| 12022 | OPC_Decode, 190, 21, 200, 2, // 7269: decode to V6_vS32b_nt_new_npred_ai using decoder 328 |
| 12023 | // 7269: } |
| 12024 | // 7269: } // switch Inst[23:21] |
| 12025 | // 7269: } |
| 12026 | 4, 21, // 7274: case 0x4: { |
| 12027 | OPC_SwitchField, 21, 3, // 7276: switch Inst[23:21] { |
| 12028 | 4, 7, // 7279: case 0x4: { |
| 12029 | OPC_CheckPredicate, 12, // 7281: check predicate 12 |
| 12030 | OPC_Decode, 244, 20, 199, 2, // 7283: decode to V6_vL32b_cur_pred_ai using decoder 327 |
| 12031 | // 7283: } |
| 12032 | 6, 0, // 7288: case 0x6: { |
| 12033 | OPC_CheckPredicate, 12, // 7290: check predicate 12 |
| 12034 | OPC_Decode, 129, 21, 199, 2, // 7292: decode to V6_vL32b_nt_cur_pred_ai using decoder 327 |
| 12035 | // 7292: } |
| 12036 | // 7292: } // switch Inst[23:21] |
| 12037 | // 7292: } |
| 12038 | 5, 21, // 7297: case 0x5: { |
| 12039 | OPC_SwitchField, 21, 3, // 7299: switch Inst[23:21] { |
| 12040 | 4, 7, // 7302: case 0x4: { |
| 12041 | OPC_CheckPredicate, 12, // 7304: check predicate 12 |
| 12042 | OPC_Decode, 239, 20, 199, 2, // 7306: decode to V6_vL32b_cur_npred_ai using decoder 327 |
| 12043 | // 7306: } |
| 12044 | 6, 0, // 7311: case 0x6: { |
| 12045 | OPC_CheckPredicate, 12, // 7313: check predicate 12 |
| 12046 | OPC_Decode, 252, 20, 199, 2, // 7315: decode to V6_vL32b_nt_cur_npred_ai using decoder 327 |
| 12047 | // 7315: } |
| 12048 | // 7315: } // switch Inst[23:21] |
| 12049 | // 7315: } |
| 12050 | 6, 30, // 7320: case 0x6: { |
| 12051 | OPC_SwitchField, 21, 3, // 7322: switch Inst[23:21] { |
| 12052 | 4, 7, // 7325: case 0x4: { |
| 12053 | OPC_CheckPredicate, 12, // 7327: check predicate 12 |
| 12054 | OPC_Decode, 160, 21, 199, 2, // 7329: decode to V6_vL32b_tmp_pred_ai using decoder 327 |
| 12055 | // 7329: } |
| 12056 | 5, 7, // 7334: case 0x5: { |
| 12057 | OPC_CheckPredicate, 15, // 7336: check predicate 15 |
| 12058 | OPC_Decode, 169, 21, 196, 2, // 7338: decode to V6_vS32Ub_pred_ai using decoder 324 |
| 12059 | // 7338: } |
| 12060 | 6, 0, // 7343: case 0x6: { |
| 12061 | OPC_CheckPredicate, 12, // 7345: check predicate 12 |
| 12062 | OPC_Decode, 146, 21, 199, 2, // 7347: decode to V6_vL32b_nt_tmp_pred_ai using decoder 327 |
| 12063 | // 7347: } |
| 12064 | // 7347: } // switch Inst[23:21] |
| 12065 | // 7347: } |
| 12066 | 7, 0, // 7352: case 0x7: { |
| 12067 | OPC_SwitchField, 21, 3, // 7354: switch Inst[23:21] { |
| 12068 | 0, 11, // 7357: case 0x0: { |
| 12069 | OPC_CheckPredicate, 15, // 7359: check predicate 15 |
| 12070 | OPC_CheckField, 11, 2, 0, // 7361: check Inst[12:11] == 0x0 |
| 12071 | OPC_Decode, 234, 20, 193, 2, // 7365: decode to V6_vL32Ub_ai using decoder 321 |
| 12072 | // 7365: } |
| 12073 | 1, 11, // 7370: case 0x1: { |
| 12074 | OPC_CheckPredicate, 15, // 7372: check predicate 15 |
| 12075 | OPC_CheckField, 11, 2, 0, // 7374: check Inst[12:11] == 0x0 |
| 12076 | OPC_Decode, 163, 21, 194, 2, // 7378: decode to V6_vS32Ub_ai using decoder 322 |
| 12077 | // 7378: } |
| 12078 | 4, 7, // 7383: case 0x4: { |
| 12079 | OPC_CheckPredicate, 12, // 7385: check predicate 12 |
| 12080 | OPC_Decode, 155, 21, 199, 2, // 7387: decode to V6_vL32b_tmp_npred_ai using decoder 327 |
| 12081 | // 7387: } |
| 12082 | 5, 7, // 7392: case 0x5: { |
| 12083 | OPC_CheckPredicate, 15, // 7394: check predicate 15 |
| 12084 | OPC_Decode, 164, 21, 196, 2, // 7396: decode to V6_vS32Ub_npred_ai using decoder 324 |
| 12085 | // 7396: } |
| 12086 | 6, 0, // 7401: case 0x6: { |
| 12087 | OPC_CheckPredicate, 12, // 7403: check predicate 12 |
| 12088 | OPC_Decode, 141, 21, 199, 2, // 7405: decode to V6_vL32b_nt_tmp_npred_ai using decoder 327 |
| 12089 | // 7405: } |
| 12090 | // 7405: } // switch Inst[23:21] |
| 12091 | // 7405: } |
| 12092 | // 7405: } // switch Inst[7:5] |
| 12093 | // 7405: } |
| 12094 | 41, 196, 4, // 7410: case 0x29: { |
| 12095 | OPC_SwitchField, 5, 3, // 7413: switch Inst[7:5] { |
| 12096 | 0, 107, // 7416: case 0x0: { |
| 12097 | OPC_SwitchField, 21, 3, // 7418: switch Inst[23:21] { |
| 12098 | 0, 11, // 7421: case 0x0: { |
| 12099 | OPC_CheckPredicate, 15, // 7423: check predicate 15 |
| 12100 | OPC_CheckField, 11, 3, 0, // 7425: check Inst[13:11] == 0x0 |
| 12101 | OPC_Decode, 149, 21, 201, 2, // 7429: decode to V6_vL32b_pi using decoder 329 |
| 12102 | // 7429: } |
| 12103 | 1, 11, // 7434: case 0x1: { |
| 12104 | OPC_CheckPredicate, 15, // 7436: check predicate 15 |
| 12105 | OPC_CheckField, 11, 3, 0, // 7438: check Inst[13:11] == 0x0 |
| 12106 | OPC_Decode, 212, 21, 202, 2, // 7442: decode to V6_vS32b_pi using decoder 330 |
| 12107 | // 7442: } |
| 12108 | 2, 11, // 7447: case 0x2: { |
| 12109 | OPC_CheckPredicate, 15, // 7449: check predicate 15 |
| 12110 | OPC_CheckField, 11, 3, 0, // 7451: check Inst[13:11] == 0x0 |
| 12111 | OPC_Decode, 135, 21, 201, 2, // 7455: decode to V6_vL32b_nt_pi using decoder 329 |
| 12112 | // 7455: } |
| 12113 | 3, 11, // 7460: case 0x3: { |
| 12114 | OPC_CheckPredicate, 15, // 7462: check predicate 15 |
| 12115 | OPC_CheckField, 11, 3, 0, // 7464: check Inst[13:11] == 0x0 |
| 12116 | OPC_Decode, 204, 21, 202, 2, // 7468: decode to V6_vS32b_nt_pi using decoder 330 |
| 12117 | // 7468: } |
| 12118 | 4, 11, // 7473: case 0x4: { |
| 12119 | OPC_CheckPredicate, 15, // 7475: check predicate 15 |
| 12120 | OPC_CheckField, 13, 1, 0, // 7477: check Inst[13] == 0x0 |
| 12121 | OPC_Decode, 218, 21, 203, 2, // 7481: decode to V6_vS32b_qpred_pi using decoder 331 |
| 12122 | // 7481: } |
| 12123 | 5, 11, // 7486: case 0x5: { |
| 12124 | OPC_CheckPredicate, 15, // 7488: check predicate 15 |
| 12125 | OPC_CheckField, 13, 1, 0, // 7490: check Inst[13] == 0x0 |
| 12126 | OPC_Decode, 215, 21, 204, 2, // 7494: decode to V6_vS32b_pred_pi using decoder 332 |
| 12127 | // 7494: } |
| 12128 | 6, 11, // 7499: case 0x6: { |
| 12129 | OPC_CheckPredicate, 15, // 7501: check predicate 15 |
| 12130 | OPC_CheckField, 13, 1, 0, // 7503: check Inst[13] == 0x0 |
| 12131 | OPC_Decode, 210, 21, 203, 2, // 7507: decode to V6_vS32b_nt_qpred_pi using decoder 331 |
| 12132 | // 7507: } |
| 12133 | 7, 0, // 7512: case 0x7: { |
| 12134 | OPC_CheckPredicate, 15, // 7514: check predicate 15 |
| 12135 | OPC_CheckField, 13, 1, 0, // 7516: check Inst[13] == 0x0 |
| 12136 | OPC_Decode, 207, 21, 204, 2, // 7520: decode to V6_vS32b_nt_pred_pi using decoder 332 |
| 12137 | // 7520: } |
| 12138 | // 7520: } // switch Inst[23:21] |
| 12139 | // 7520: } |
| 12140 | 1, 133, 1, // 7525: case 0x1: { |
| 12141 | OPC_SwitchField, 21, 3, // 7528: switch Inst[23:21] { |
| 12142 | 0, 11, // 7531: case 0x0: { |
| 12143 | OPC_CheckPredicate, 15, // 7533: check predicate 15 |
| 12144 | OPC_CheckField, 11, 3, 0, // 7535: check Inst[13:11] == 0x0 |
| 12145 | OPC_Decode, 242, 20, 201, 2, // 7539: decode to V6_vL32b_cur_pi using decoder 329 |
| 12146 | // 7539: } |
| 12147 | 1, 33, // 7544: case 0x1: { |
| 12148 | OPC_SwitchField, 3, 2, // 7546: switch Inst[4:3] { |
| 12149 | 0, 11, // 7549: case 0x0: { |
| 12150 | OPC_CheckPredicate, 15, // 7551: check predicate 15 |
| 12151 | OPC_CheckField, 11, 3, 0, // 7553: check Inst[13:11] == 0x0 |
| 12152 | OPC_Decode, 177, 21, 205, 2, // 7557: decode to V6_vS32b_new_pi using decoder 333 |
| 12153 | // 7557: } |
| 12154 | 1, 0, // 7562: case 0x1: { |
| 12155 | OPC_CheckPredicate, 13, // 7564: check predicate 13 |
| 12156 | OPC_CheckField, 11, 3, 0, // 7566: check Inst[13:11] == 0x0 |
| 12157 | OPC_CheckField, 0, 3, 0, // 7570: check Inst[2:0] == 0x0 |
| 12158 | OPC_Decode, 221, 21, 206, 2, // 7574: decode to V6_vS32b_srls_pi using decoder 334 |
| 12159 | // 7574: } |
| 12160 | // 7574: } // switch Inst[4:3] |
| 12161 | // 7574: } |
| 12162 | 2, 11, // 7579: case 0x2: { |
| 12163 | OPC_CheckPredicate, 15, // 7581: check predicate 15 |
| 12164 | OPC_CheckField, 11, 3, 0, // 7583: check Inst[13:11] == 0x0 |
| 12165 | OPC_Decode, 255, 20, 201, 2, // 7587: decode to V6_vL32b_nt_cur_pi using decoder 329 |
| 12166 | // 7587: } |
| 12167 | 3, 15, // 7592: case 0x3: { |
| 12168 | OPC_CheckPredicate, 15, // 7594: check predicate 15 |
| 12169 | OPC_CheckField, 11, 3, 0, // 7596: check Inst[13:11] == 0x0 |
| 12170 | OPC_CheckField, 3, 2, 0, // 7600: check Inst[4:3] == 0x0 |
| 12171 | OPC_Decode, 193, 21, 205, 2, // 7604: decode to V6_vS32b_nt_new_pi using decoder 333 |
| 12172 | // 7604: } |
| 12173 | 4, 11, // 7609: case 0x4: { |
| 12174 | OPC_CheckPredicate, 15, // 7611: check predicate 15 |
| 12175 | OPC_CheckField, 13, 1, 0, // 7613: check Inst[13] == 0x0 |
| 12176 | OPC_Decode, 186, 21, 203, 2, // 7617: decode to V6_vS32b_nqpred_pi using decoder 331 |
| 12177 | // 7617: } |
| 12178 | 5, 11, // 7622: case 0x5: { |
| 12179 | OPC_CheckPredicate, 15, // 7624: check predicate 15 |
| 12180 | OPC_CheckField, 13, 1, 0, // 7626: check Inst[13] == 0x0 |
| 12181 | OPC_Decode, 183, 21, 204, 2, // 7630: decode to V6_vS32b_npred_pi using decoder 332 |
| 12182 | // 7630: } |
| 12183 | 6, 11, // 7635: case 0x6: { |
| 12184 | OPC_CheckPredicate, 15, // 7637: check predicate 15 |
| 12185 | OPC_CheckField, 13, 1, 0, // 7639: check Inst[13] == 0x0 |
| 12186 | OPC_Decode, 202, 21, 203, 2, // 7643: decode to V6_vS32b_nt_nqpred_pi using decoder 331 |
| 12187 | // 7643: } |
| 12188 | 7, 0, // 7648: case 0x7: { |
| 12189 | OPC_CheckPredicate, 15, // 7650: check predicate 15 |
| 12190 | OPC_CheckField, 13, 1, 0, // 7652: check Inst[13] == 0x0 |
| 12191 | OPC_Decode, 199, 21, 204, 2, // 7656: decode to V6_vS32b_nt_npred_pi using decoder 332 |
| 12192 | // 7656: } |
| 12193 | // 7656: } // switch Inst[23:21] |
| 12194 | // 7656: } |
| 12195 | 2, 89, // 7661: case 0x2: { |
| 12196 | OPC_SwitchField, 21, 3, // 7663: switch Inst[23:21] { |
| 12197 | 0, 11, // 7666: case 0x0: { |
| 12198 | OPC_CheckPredicate, 15, // 7668: check predicate 15 |
| 12199 | OPC_CheckField, 11, 3, 0, // 7670: check Inst[13:11] == 0x0 |
| 12200 | OPC_Decode, 158, 21, 201, 2, // 7674: decode to V6_vL32b_tmp_pi using decoder 329 |
| 12201 | // 7674: } |
| 12202 | 2, 11, // 7679: case 0x2: { |
| 12203 | OPC_CheckPredicate, 15, // 7681: check predicate 15 |
| 12204 | OPC_CheckField, 11, 3, 0, // 7683: check Inst[13:11] == 0x0 |
| 12205 | OPC_Decode, 144, 21, 201, 2, // 7687: decode to V6_vL32b_nt_tmp_pi using decoder 329 |
| 12206 | // 7687: } |
| 12207 | 4, 11, // 7692: case 0x4: { |
| 12208 | OPC_CheckPredicate, 12, // 7694: check predicate 12 |
| 12209 | OPC_CheckField, 13, 1, 0, // 7696: check Inst[13] == 0x0 |
| 12210 | OPC_Decode, 152, 21, 207, 2, // 7700: decode to V6_vL32b_pred_pi using decoder 335 |
| 12211 | // 7700: } |
| 12212 | 5, 15, // 7705: case 0x5: { |
| 12213 | OPC_CheckPredicate, 15, // 7707: check predicate 15 |
| 12214 | OPC_CheckField, 13, 1, 0, // 7709: check Inst[13] == 0x0 |
| 12215 | OPC_CheckField, 3, 2, 0, // 7713: check Inst[4:3] == 0x0 |
| 12216 | OPC_Decode, 180, 21, 208, 2, // 7717: decode to V6_vS32b_new_pred_pi using decoder 336 |
| 12217 | // 7717: } |
| 12218 | 6, 11, // 7722: case 0x6: { |
| 12219 | OPC_CheckPredicate, 12, // 7724: check predicate 12 |
| 12220 | OPC_CheckField, 13, 1, 0, // 7726: check Inst[13] == 0x0 |
| 12221 | OPC_Decode, 138, 21, 207, 2, // 7730: decode to V6_vL32b_nt_pred_pi using decoder 335 |
| 12222 | // 7730: } |
| 12223 | 7, 0, // 7735: case 0x7: { |
| 12224 | OPC_CheckPredicate, 15, // 7737: check predicate 15 |
| 12225 | OPC_CheckField, 13, 1, 0, // 7739: check Inst[13] == 0x0 |
| 12226 | OPC_CheckField, 3, 2, 2, // 7743: check Inst[4:3] == 0x2 |
| 12227 | OPC_Decode, 196, 21, 208, 2, // 7747: decode to V6_vS32b_nt_new_pred_pi using decoder 336 |
| 12228 | // 7747: } |
| 12229 | // 7747: } // switch Inst[23:21] |
| 12230 | // 7747: } |
| 12231 | 3, 63, // 7752: case 0x3: { |
| 12232 | OPC_SwitchField, 21, 3, // 7754: switch Inst[23:21] { |
| 12233 | 4, 11, // 7757: case 0x4: { |
| 12234 | OPC_CheckPredicate, 12, // 7759: check predicate 12 |
| 12235 | OPC_CheckField, 13, 1, 0, // 7761: check Inst[13] == 0x0 |
| 12236 | OPC_Decode, 248, 20, 207, 2, // 7765: decode to V6_vL32b_npred_pi using decoder 335 |
| 12237 | // 7765: } |
| 12238 | 5, 15, // 7770: case 0x5: { |
| 12239 | OPC_CheckPredicate, 15, // 7772: check predicate 15 |
| 12240 | OPC_CheckField, 13, 1, 0, // 7774: check Inst[13] == 0x0 |
| 12241 | OPC_CheckField, 3, 2, 1, // 7778: check Inst[4:3] == 0x1 |
| 12242 | OPC_Decode, 175, 21, 208, 2, // 7782: decode to V6_vS32b_new_npred_pi using decoder 336 |
| 12243 | // 7782: } |
| 12244 | 6, 11, // 7787: case 0x6: { |
| 12245 | OPC_CheckPredicate, 12, // 7789: check predicate 12 |
| 12246 | OPC_CheckField, 13, 1, 0, // 7791: check Inst[13] == 0x0 |
| 12247 | OPC_Decode, 133, 21, 207, 2, // 7795: decode to V6_vL32b_nt_npred_pi using decoder 335 |
| 12248 | // 7795: } |
| 12249 | 7, 0, // 7800: case 0x7: { |
| 12250 | OPC_CheckPredicate, 15, // 7802: check predicate 15 |
| 12251 | OPC_CheckField, 13, 1, 0, // 7804: check Inst[13] == 0x0 |
| 12252 | OPC_CheckField, 3, 2, 3, // 7808: check Inst[4:3] == 0x3 |
| 12253 | OPC_Decode, 191, 21, 208, 2, // 7812: decode to V6_vS32b_nt_new_npred_pi using decoder 336 |
| 12254 | // 7812: } |
| 12255 | // 7812: } // switch Inst[23:21] |
| 12256 | // 7812: } |
| 12257 | 4, 29, // 7817: case 0x4: { |
| 12258 | OPC_SwitchField, 21, 3, // 7819: switch Inst[23:21] { |
| 12259 | 4, 11, // 7822: case 0x4: { |
| 12260 | OPC_CheckPredicate, 12, // 7824: check predicate 12 |
| 12261 | OPC_CheckField, 13, 1, 0, // 7826: check Inst[13] == 0x0 |
| 12262 | OPC_Decode, 245, 20, 207, 2, // 7830: decode to V6_vL32b_cur_pred_pi using decoder 335 |
| 12263 | // 7830: } |
| 12264 | 6, 0, // 7835: case 0x6: { |
| 12265 | OPC_CheckPredicate, 12, // 7837: check predicate 12 |
| 12266 | OPC_CheckField, 13, 1, 0, // 7839: check Inst[13] == 0x0 |
| 12267 | OPC_Decode, 130, 21, 207, 2, // 7843: decode to V6_vL32b_nt_cur_pred_pi using decoder 335 |
| 12268 | // 7843: } |
| 12269 | // 7843: } // switch Inst[23:21] |
| 12270 | // 7843: } |
| 12271 | 5, 29, // 7848: case 0x5: { |
| 12272 | OPC_SwitchField, 21, 3, // 7850: switch Inst[23:21] { |
| 12273 | 4, 11, // 7853: case 0x4: { |
| 12274 | OPC_CheckPredicate, 12, // 7855: check predicate 12 |
| 12275 | OPC_CheckField, 13, 1, 0, // 7857: check Inst[13] == 0x0 |
| 12276 | OPC_Decode, 240, 20, 207, 2, // 7861: decode to V6_vL32b_cur_npred_pi using decoder 335 |
| 12277 | // 7861: } |
| 12278 | 6, 0, // 7866: case 0x6: { |
| 12279 | OPC_CheckPredicate, 12, // 7868: check predicate 12 |
| 12280 | OPC_CheckField, 13, 1, 0, // 7870: check Inst[13] == 0x0 |
| 12281 | OPC_Decode, 253, 20, 207, 2, // 7874: decode to V6_vL32b_nt_cur_npred_pi using decoder 335 |
| 12282 | // 7874: } |
| 12283 | // 7874: } // switch Inst[23:21] |
| 12284 | // 7874: } |
| 12285 | 6, 42, // 7879: case 0x6: { |
| 12286 | OPC_SwitchField, 21, 3, // 7881: switch Inst[23:21] { |
| 12287 | 4, 11, // 7884: case 0x4: { |
| 12288 | OPC_CheckPredicate, 12, // 7886: check predicate 12 |
| 12289 | OPC_CheckField, 13, 1, 0, // 7888: check Inst[13] == 0x0 |
| 12290 | OPC_Decode, 161, 21, 207, 2, // 7892: decode to V6_vL32b_tmp_pred_pi using decoder 335 |
| 12291 | // 7892: } |
| 12292 | 5, 11, // 7897: case 0x5: { |
| 12293 | OPC_CheckPredicate, 15, // 7899: check predicate 15 |
| 12294 | OPC_CheckField, 13, 1, 0, // 7901: check Inst[13] == 0x0 |
| 12295 | OPC_Decode, 170, 21, 204, 2, // 7905: decode to V6_vS32Ub_pred_pi using decoder 332 |
| 12296 | // 7905: } |
| 12297 | 6, 0, // 7910: case 0x6: { |
| 12298 | OPC_CheckPredicate, 12, // 7912: check predicate 12 |
| 12299 | OPC_CheckField, 13, 1, 0, // 7914: check Inst[13] == 0x0 |
| 12300 | OPC_Decode, 147, 21, 207, 2, // 7918: decode to V6_vL32b_nt_tmp_pred_pi using decoder 335 |
| 12301 | // 7918: } |
| 12302 | // 7918: } // switch Inst[23:21] |
| 12303 | // 7918: } |
| 12304 | 7, 0, // 7923: case 0x7: { |
| 12305 | OPC_SwitchField, 21, 3, // 7925: switch Inst[23:21] { |
| 12306 | 0, 11, // 7928: case 0x0: { |
| 12307 | OPC_CheckPredicate, 15, // 7930: check predicate 15 |
| 12308 | OPC_CheckField, 11, 3, 0, // 7932: check Inst[13:11] == 0x0 |
| 12309 | OPC_Decode, 235, 20, 201, 2, // 7936: decode to V6_vL32Ub_pi using decoder 329 |
| 12310 | // 7936: } |
| 12311 | 1, 11, // 7941: case 0x1: { |
| 12312 | OPC_CheckPredicate, 15, // 7943: check predicate 15 |
| 12313 | OPC_CheckField, 11, 3, 0, // 7945: check Inst[13:11] == 0x0 |
| 12314 | OPC_Decode, 167, 21, 202, 2, // 7949: decode to V6_vS32Ub_pi using decoder 330 |
| 12315 | // 7949: } |
| 12316 | 4, 11, // 7954: case 0x4: { |
| 12317 | OPC_CheckPredicate, 12, // 7956: check predicate 12 |
| 12318 | OPC_CheckField, 13, 1, 0, // 7958: check Inst[13] == 0x0 |
| 12319 | OPC_Decode, 156, 21, 207, 2, // 7962: decode to V6_vL32b_tmp_npred_pi using decoder 335 |
| 12320 | // 7962: } |
| 12321 | 5, 11, // 7967: case 0x5: { |
| 12322 | OPC_CheckPredicate, 15, // 7969: check predicate 15 |
| 12323 | OPC_CheckField, 13, 1, 0, // 7971: check Inst[13] == 0x0 |
| 12324 | OPC_Decode, 165, 21, 204, 2, // 7975: decode to V6_vS32Ub_npred_pi using decoder 332 |
| 12325 | // 7975: } |
| 12326 | 6, 0, // 7980: case 0x6: { |
| 12327 | OPC_CheckPredicate, 12, // 7982: check predicate 12 |
| 12328 | OPC_CheckField, 13, 1, 0, // 7984: check Inst[13] == 0x0 |
| 12329 | OPC_Decode, 142, 21, 207, 2, // 7988: decode to V6_vL32b_nt_tmp_npred_pi using decoder 335 |
| 12330 | // 7988: } |
| 12331 | // 7988: } // switch Inst[23:21] |
| 12332 | // 7988: } |
| 12333 | // 7988: } // switch Inst[7:5] |
| 12334 | // 7988: } |
| 12335 | 43, 219, 3, // 7993: case 0x2b: { |
| 12336 | OPC_SwitchField, 5, 6, // 7996: switch Inst[10:5] { |
| 12337 | 0, 91, // 7999: case 0x0: { |
| 12338 | OPC_SwitchField, 21, 3, // 8001: switch Inst[23:21] { |
| 12339 | 0, 11, // 8004: case 0x0: { |
| 12340 | OPC_CheckPredicate, 15, // 8006: check predicate 15 |
| 12341 | OPC_CheckField, 11, 2, 0, // 8008: check Inst[12:11] == 0x0 |
| 12342 | OPC_Decode, 150, 21, 209, 2, // 8012: decode to V6_vL32b_ppu using decoder 337 |
| 12343 | // 8012: } |
| 12344 | 1, 11, // 8017: case 0x1: { |
| 12345 | OPC_CheckPredicate, 15, // 8019: check predicate 15 |
| 12346 | OPC_CheckField, 11, 2, 0, // 8021: check Inst[12:11] == 0x0 |
| 12347 | OPC_Decode, 213, 21, 210, 2, // 8025: decode to V6_vS32b_ppu using decoder 338 |
| 12348 | // 8025: } |
| 12349 | 2, 11, // 8030: case 0x2: { |
| 12350 | OPC_CheckPredicate, 15, // 8032: check predicate 15 |
| 12351 | OPC_CheckField, 11, 2, 0, // 8034: check Inst[12:11] == 0x0 |
| 12352 | OPC_Decode, 136, 21, 209, 2, // 8038: decode to V6_vL32b_nt_ppu using decoder 337 |
| 12353 | // 8038: } |
| 12354 | 3, 11, // 8043: case 0x3: { |
| 12355 | OPC_CheckPredicate, 15, // 8045: check predicate 15 |
| 12356 | OPC_CheckField, 11, 2, 0, // 8047: check Inst[12:11] == 0x0 |
| 12357 | OPC_Decode, 205, 21, 210, 2, // 8051: decode to V6_vS32b_nt_ppu using decoder 338 |
| 12358 | // 8051: } |
| 12359 | 4, 7, // 8056: case 0x4: { |
| 12360 | OPC_CheckPredicate, 15, // 8058: check predicate 15 |
| 12361 | OPC_Decode, 219, 21, 211, 2, // 8060: decode to V6_vS32b_qpred_ppu using decoder 339 |
| 12362 | // 8060: } |
| 12363 | 5, 7, // 8065: case 0x5: { |
| 12364 | OPC_CheckPredicate, 15, // 8067: check predicate 15 |
| 12365 | OPC_Decode, 216, 21, 212, 2, // 8069: decode to V6_vS32b_pred_ppu using decoder 340 |
| 12366 | // 8069: } |
| 12367 | 6, 7, // 8074: case 0x6: { |
| 12368 | OPC_CheckPredicate, 15, // 8076: check predicate 15 |
| 12369 | OPC_Decode, 211, 21, 211, 2, // 8078: decode to V6_vS32b_nt_qpred_ppu using decoder 339 |
| 12370 | // 8078: } |
| 12371 | 7, 0, // 8083: case 0x7: { |
| 12372 | OPC_CheckPredicate, 15, // 8085: check predicate 15 |
| 12373 | OPC_Decode, 208, 21, 212, 2, // 8087: decode to V6_vS32b_nt_pred_ppu using decoder 340 |
| 12374 | // 8087: } |
| 12375 | // 8087: } // switch Inst[23:21] |
| 12376 | // 8087: } |
| 12377 | 1, 117, // 8092: case 0x1: { |
| 12378 | OPC_SwitchField, 21, 3, // 8094: switch Inst[23:21] { |
| 12379 | 0, 11, // 8097: case 0x0: { |
| 12380 | OPC_CheckPredicate, 15, // 8099: check predicate 15 |
| 12381 | OPC_CheckField, 11, 2, 0, // 8101: check Inst[12:11] == 0x0 |
| 12382 | OPC_Decode, 243, 20, 209, 2, // 8105: decode to V6_vL32b_cur_ppu using decoder 337 |
| 12383 | // 8105: } |
| 12384 | 1, 33, // 8110: case 0x1: { |
| 12385 | OPC_SwitchField, 3, 2, // 8112: switch Inst[4:3] { |
| 12386 | 0, 11, // 8115: case 0x0: { |
| 12387 | OPC_CheckPredicate, 15, // 8117: check predicate 15 |
| 12388 | OPC_CheckField, 11, 2, 0, // 8119: check Inst[12:11] == 0x0 |
| 12389 | OPC_Decode, 178, 21, 213, 2, // 8123: decode to V6_vS32b_new_ppu using decoder 341 |
| 12390 | // 8123: } |
| 12391 | 1, 0, // 8128: case 0x1: { |
| 12392 | OPC_CheckPredicate, 13, // 8130: check predicate 13 |
| 12393 | OPC_CheckField, 11, 2, 0, // 8132: check Inst[12:11] == 0x0 |
| 12394 | OPC_CheckField, 0, 3, 0, // 8136: check Inst[2:0] == 0x0 |
| 12395 | OPC_Decode, 222, 21, 214, 2, // 8140: decode to V6_vS32b_srls_ppu using decoder 342 |
| 12396 | // 8140: } |
| 12397 | // 8140: } // switch Inst[4:3] |
| 12398 | // 8140: } |
| 12399 | 2, 11, // 8145: case 0x2: { |
| 12400 | OPC_CheckPredicate, 15, // 8147: check predicate 15 |
| 12401 | OPC_CheckField, 11, 2, 0, // 8149: check Inst[12:11] == 0x0 |
| 12402 | OPC_Decode, 128, 21, 209, 2, // 8153: decode to V6_vL32b_nt_cur_ppu using decoder 337 |
| 12403 | // 8153: } |
| 12404 | 3, 15, // 8158: case 0x3: { |
| 12405 | OPC_CheckPredicate, 15, // 8160: check predicate 15 |
| 12406 | OPC_CheckField, 11, 2, 0, // 8162: check Inst[12:11] == 0x0 |
| 12407 | OPC_CheckField, 3, 2, 0, // 8166: check Inst[4:3] == 0x0 |
| 12408 | OPC_Decode, 194, 21, 213, 2, // 8170: decode to V6_vS32b_nt_new_ppu using decoder 341 |
| 12409 | // 8170: } |
| 12410 | 4, 7, // 8175: case 0x4: { |
| 12411 | OPC_CheckPredicate, 15, // 8177: check predicate 15 |
| 12412 | OPC_Decode, 187, 21, 211, 2, // 8179: decode to V6_vS32b_nqpred_ppu using decoder 339 |
| 12413 | // 8179: } |
| 12414 | 5, 7, // 8184: case 0x5: { |
| 12415 | OPC_CheckPredicate, 15, // 8186: check predicate 15 |
| 12416 | OPC_Decode, 184, 21, 212, 2, // 8188: decode to V6_vS32b_npred_ppu using decoder 340 |
| 12417 | // 8188: } |
| 12418 | 6, 7, // 8193: case 0x6: { |
| 12419 | OPC_CheckPredicate, 15, // 8195: check predicate 15 |
| 12420 | OPC_Decode, 203, 21, 211, 2, // 8197: decode to V6_vS32b_nt_nqpred_ppu using decoder 339 |
| 12421 | // 8197: } |
| 12422 | 7, 0, // 8202: case 0x7: { |
| 12423 | OPC_CheckPredicate, 15, // 8204: check predicate 15 |
| 12424 | OPC_Decode, 200, 21, 212, 2, // 8206: decode to V6_vS32b_nt_npred_ppu using decoder 340 |
| 12425 | // 8206: } |
| 12426 | // 8206: } // switch Inst[23:21] |
| 12427 | // 8206: } |
| 12428 | 2, 73, // 8211: case 0x2: { |
| 12429 | OPC_SwitchField, 21, 3, // 8213: switch Inst[23:21] { |
| 12430 | 0, 11, // 8216: case 0x0: { |
| 12431 | OPC_CheckPredicate, 15, // 8218: check predicate 15 |
| 12432 | OPC_CheckField, 11, 2, 0, // 8220: check Inst[12:11] == 0x0 |
| 12433 | OPC_Decode, 159, 21, 209, 2, // 8224: decode to V6_vL32b_tmp_ppu using decoder 337 |
| 12434 | // 8224: } |
| 12435 | 2, 11, // 8229: case 0x2: { |
| 12436 | OPC_CheckPredicate, 15, // 8231: check predicate 15 |
| 12437 | OPC_CheckField, 11, 2, 0, // 8233: check Inst[12:11] == 0x0 |
| 12438 | OPC_Decode, 145, 21, 209, 2, // 8237: decode to V6_vL32b_nt_tmp_ppu using decoder 337 |
| 12439 | // 8237: } |
| 12440 | 4, 7, // 8242: case 0x4: { |
| 12441 | OPC_CheckPredicate, 12, // 8244: check predicate 12 |
| 12442 | OPC_Decode, 153, 21, 215, 2, // 8246: decode to V6_vL32b_pred_ppu using decoder 343 |
| 12443 | // 8246: } |
| 12444 | 5, 11, // 8251: case 0x5: { |
| 12445 | OPC_CheckPredicate, 15, // 8253: check predicate 15 |
| 12446 | OPC_CheckField, 3, 2, 0, // 8255: check Inst[4:3] == 0x0 |
| 12447 | OPC_Decode, 181, 21, 216, 2, // 8259: decode to V6_vS32b_new_pred_ppu using decoder 344 |
| 12448 | // 8259: } |
| 12449 | 6, 7, // 8264: case 0x6: { |
| 12450 | OPC_CheckPredicate, 12, // 8266: check predicate 12 |
| 12451 | OPC_Decode, 139, 21, 215, 2, // 8268: decode to V6_vL32b_nt_pred_ppu using decoder 343 |
| 12452 | // 8268: } |
| 12453 | 7, 0, // 8273: case 0x7: { |
| 12454 | OPC_CheckPredicate, 15, // 8275: check predicate 15 |
| 12455 | OPC_CheckField, 3, 2, 2, // 8277: check Inst[4:3] == 0x2 |
| 12456 | OPC_Decode, 197, 21, 216, 2, // 8281: decode to V6_vS32b_nt_new_pred_ppu using decoder 344 |
| 12457 | // 8281: } |
| 12458 | // 8281: } // switch Inst[23:21] |
| 12459 | // 8281: } |
| 12460 | 3, 47, // 8286: case 0x3: { |
| 12461 | OPC_SwitchField, 21, 3, // 8288: switch Inst[23:21] { |
| 12462 | 4, 7, // 8291: case 0x4: { |
| 12463 | OPC_CheckPredicate, 12, // 8293: check predicate 12 |
| 12464 | OPC_Decode, 249, 20, 215, 2, // 8295: decode to V6_vL32b_npred_ppu using decoder 343 |
| 12465 | // 8295: } |
| 12466 | 5, 11, // 8300: case 0x5: { |
| 12467 | OPC_CheckPredicate, 15, // 8302: check predicate 15 |
| 12468 | OPC_CheckField, 3, 2, 1, // 8304: check Inst[4:3] == 0x1 |
| 12469 | OPC_Decode, 176, 21, 216, 2, // 8308: decode to V6_vS32b_new_npred_ppu using decoder 344 |
| 12470 | // 8308: } |
| 12471 | 6, 7, // 8313: case 0x6: { |
| 12472 | OPC_CheckPredicate, 12, // 8315: check predicate 12 |
| 12473 | OPC_Decode, 134, 21, 215, 2, // 8317: decode to V6_vL32b_nt_npred_ppu using decoder 343 |
| 12474 | // 8317: } |
| 12475 | 7, 0, // 8322: case 0x7: { |
| 12476 | OPC_CheckPredicate, 15, // 8324: check predicate 15 |
| 12477 | OPC_CheckField, 3, 2, 3, // 8326: check Inst[4:3] == 0x3 |
| 12478 | OPC_Decode, 192, 21, 216, 2, // 8330: decode to V6_vS32b_nt_new_npred_ppu using decoder 344 |
| 12479 | // 8330: } |
| 12480 | // 8330: } // switch Inst[23:21] |
| 12481 | // 8330: } |
| 12482 | 4, 21, // 8335: case 0x4: { |
| 12483 | OPC_SwitchField, 21, 3, // 8337: switch Inst[23:21] { |
| 12484 | 4, 7, // 8340: case 0x4: { |
| 12485 | OPC_CheckPredicate, 12, // 8342: check predicate 12 |
| 12486 | OPC_Decode, 246, 20, 215, 2, // 8344: decode to V6_vL32b_cur_pred_ppu using decoder 343 |
| 12487 | // 8344: } |
| 12488 | 6, 0, // 8349: case 0x6: { |
| 12489 | OPC_CheckPredicate, 12, // 8351: check predicate 12 |
| 12490 | OPC_Decode, 131, 21, 215, 2, // 8353: decode to V6_vL32b_nt_cur_pred_ppu using decoder 343 |
| 12491 | // 8353: } |
| 12492 | // 8353: } // switch Inst[23:21] |
| 12493 | // 8353: } |
| 12494 | 5, 21, // 8358: case 0x5: { |
| 12495 | OPC_SwitchField, 21, 3, // 8360: switch Inst[23:21] { |
| 12496 | 4, 7, // 8363: case 0x4: { |
| 12497 | OPC_CheckPredicate, 12, // 8365: check predicate 12 |
| 12498 | OPC_Decode, 241, 20, 215, 2, // 8367: decode to V6_vL32b_cur_npred_ppu using decoder 343 |
| 12499 | // 8367: } |
| 12500 | 6, 0, // 8372: case 0x6: { |
| 12501 | OPC_CheckPredicate, 12, // 8374: check predicate 12 |
| 12502 | OPC_Decode, 254, 20, 215, 2, // 8376: decode to V6_vL32b_nt_cur_npred_ppu using decoder 343 |
| 12503 | // 8376: } |
| 12504 | // 8376: } // switch Inst[23:21] |
| 12505 | // 8376: } |
| 12506 | 6, 30, // 8381: case 0x6: { |
| 12507 | OPC_SwitchField, 21, 3, // 8383: switch Inst[23:21] { |
| 12508 | 4, 7, // 8386: case 0x4: { |
| 12509 | OPC_CheckPredicate, 12, // 8388: check predicate 12 |
| 12510 | OPC_Decode, 162, 21, 215, 2, // 8390: decode to V6_vL32b_tmp_pred_ppu using decoder 343 |
| 12511 | // 8390: } |
| 12512 | 5, 7, // 8395: case 0x5: { |
| 12513 | OPC_CheckPredicate, 15, // 8397: check predicate 15 |
| 12514 | OPC_Decode, 171, 21, 212, 2, // 8399: decode to V6_vS32Ub_pred_ppu using decoder 340 |
| 12515 | // 8399: } |
| 12516 | 6, 0, // 8404: case 0x6: { |
| 12517 | OPC_CheckPredicate, 12, // 8406: check predicate 12 |
| 12518 | OPC_Decode, 148, 21, 215, 2, // 8408: decode to V6_vL32b_nt_tmp_pred_ppu using decoder 343 |
| 12519 | // 8408: } |
| 12520 | // 8408: } // switch Inst[23:21] |
| 12521 | // 8408: } |
| 12522 | 7, 0, // 8413: case 0x7: { |
| 12523 | OPC_SwitchField, 21, 3, // 8415: switch Inst[23:21] { |
| 12524 | 0, 11, // 8418: case 0x0: { |
| 12525 | OPC_CheckPredicate, 15, // 8420: check predicate 15 |
| 12526 | OPC_CheckField, 11, 2, 0, // 8422: check Inst[12:11] == 0x0 |
| 12527 | OPC_Decode, 236, 20, 209, 2, // 8426: decode to V6_vL32Ub_ppu using decoder 337 |
| 12528 | // 8426: } |
| 12529 | 1, 11, // 8431: case 0x1: { |
| 12530 | OPC_CheckPredicate, 15, // 8433: check predicate 15 |
| 12531 | OPC_CheckField, 11, 2, 0, // 8435: check Inst[12:11] == 0x0 |
| 12532 | OPC_Decode, 168, 21, 210, 2, // 8439: decode to V6_vS32Ub_ppu using decoder 338 |
| 12533 | // 8439: } |
| 12534 | 4, 7, // 8444: case 0x4: { |
| 12535 | OPC_CheckPredicate, 12, // 8446: check predicate 12 |
| 12536 | OPC_Decode, 157, 21, 215, 2, // 8448: decode to V6_vL32b_tmp_npred_ppu using decoder 343 |
| 12537 | // 8448: } |
| 12538 | 5, 7, // 8453: case 0x5: { |
| 12539 | OPC_CheckPredicate, 15, // 8455: check predicate 15 |
| 12540 | OPC_Decode, 166, 21, 212, 2, // 8457: decode to V6_vS32Ub_npred_ppu using decoder 340 |
| 12541 | // 8457: } |
| 12542 | 6, 0, // 8462: case 0x6: { |
| 12543 | OPC_CheckPredicate, 12, // 8464: check predicate 12 |
| 12544 | OPC_Decode, 143, 21, 215, 2, // 8466: decode to V6_vL32b_nt_tmp_npred_ppu using decoder 343 |
| 12545 | // 8466: } |
| 12546 | // 8466: } // switch Inst[23:21] |
| 12547 | // 8466: } |
| 12548 | // 8466: } // switch Inst[10:5] |
| 12549 | // 8466: } |
| 12550 | 44, 33, // 8471: case 0x2c: { |
| 12551 | OPC_SwitchField, 21, 3, // 8473: switch Inst[23:21] { |
| 12552 | 0, 15, // 8476: case 0x0: { |
| 12553 | OPC_CheckPredicate, 16, // 8478: check predicate 16 |
| 12554 | OPC_CheckField, 11, 2, 0, // 8480: check Inst[12:11] == 0x0 |
| 12555 | OPC_CheckField, 0, 8, 0, // 8484: check Inst[7:0] == 0x0 |
| 12556 | OPC_Decode, 133, 26, 198, 2, // 8488: decode to V6_zLd_ai using decoder 326 |
| 12557 | // 8488: } |
| 12558 | 4, 0, // 8493: case 0x4: { |
| 12559 | OPC_CheckPredicate, 16, // 8495: check predicate 16 |
| 12560 | OPC_CheckField, 0, 8, 0, // 8497: check Inst[7:0] == 0x0 |
| 12561 | OPC_Decode, 136, 26, 217, 2, // 8501: decode to V6_zLd_pred_ai using decoder 345 |
| 12562 | // 8501: } |
| 12563 | // 8501: } // switch Inst[23:21] |
| 12564 | // 8501: } |
| 12565 | 45, 65, // 8506: case 0x2d: { |
| 12566 | OPC_SwitchField, 0, 8, // 8508: switch Inst[7:0] { |
| 12567 | 0, 29, // 8511: case 0x0: { |
| 12568 | OPC_SwitchField, 21, 3, // 8513: switch Inst[23:21] { |
| 12569 | 0, 11, // 8516: case 0x0: { |
| 12570 | OPC_CheckPredicate, 16, // 8518: check predicate 16 |
| 12571 | OPC_CheckField, 11, 3, 0, // 8520: check Inst[13:11] == 0x0 |
| 12572 | OPC_Decode, 134, 26, 206, 2, // 8524: decode to V6_zLd_pi using decoder 334 |
| 12573 | // 8524: } |
| 12574 | 4, 0, // 8529: case 0x4: { |
| 12575 | OPC_CheckPredicate, 16, // 8531: check predicate 16 |
| 12576 | OPC_CheckField, 13, 1, 0, // 8533: check Inst[13] == 0x0 |
| 12577 | OPC_Decode, 137, 26, 218, 2, // 8537: decode to V6_zLd_pred_pi using decoder 346 |
| 12578 | // 8537: } |
| 12579 | // 8537: } // switch Inst[23:21] |
| 12580 | // 8537: } |
| 12581 | 1, 0, // 8542: case 0x1: { |
| 12582 | OPC_SwitchField, 21, 3, // 8544: switch Inst[23:21] { |
| 12583 | 0, 11, // 8547: case 0x0: { |
| 12584 | OPC_CheckPredicate, 16, // 8549: check predicate 16 |
| 12585 | OPC_CheckField, 8, 5, 0, // 8551: check Inst[12:8] == 0x0 |
| 12586 | OPC_Decode, 135, 26, 214, 2, // 8555: decode to V6_zLd_ppu using decoder 342 |
| 12587 | // 8555: } |
| 12588 | 4, 0, // 8560: case 0x4: { |
| 12589 | OPC_CheckPredicate, 16, // 8562: check predicate 16 |
| 12590 | OPC_CheckField, 8, 3, 0, // 8564: check Inst[10:8] == 0x0 |
| 12591 | OPC_Decode, 138, 26, 219, 2, // 8568: decode to V6_zLd_pred_ppu using decoder 347 |
| 12592 | // 8568: } |
| 12593 | // 8568: } // switch Inst[23:21] |
| 12594 | // 8568: } |
| 12595 | // 8568: } // switch Inst[7:0] |
| 12596 | // 8568: } |
| 12597 | 47, 169, 1, // 8573: case 0x2f: { |
| 12598 | OPC_SwitchField, 21, 3, // 8576: switch Inst[23:21] { |
| 12599 | 0, 69, // 8579: case 0x0: { |
| 12600 | OPC_SwitchField, 7, 6, // 8581: switch Inst[12:7] { |
| 12601 | 0, 11, // 8584: case 0x0: { |
| 12602 | OPC_CheckPredicate, 13, // 8586: check predicate 13 |
| 12603 | OPC_CheckField, 5, 2, 0, // 8588: check Inst[6:5] == 0x0 |
| 12604 | OPC_Decode, 187, 23, 220, 2, // 8592: decode to V6_vgathermw using decoder 348 |
| 12605 | // 8592: } |
| 12606 | 2, 11, // 8597: case 0x2: { |
| 12607 | OPC_CheckPredicate, 13, // 8599: check predicate 13 |
| 12608 | OPC_CheckField, 5, 2, 0, // 8601: check Inst[6:5] == 0x0 |
| 12609 | OPC_Decode, 183, 23, 220, 2, // 8605: decode to V6_vgathermh using decoder 348 |
| 12610 | // 8605: } |
| 12611 | 4, 11, // 8610: case 0x4: { |
| 12612 | OPC_CheckPredicate, 13, // 8612: check predicate 13 |
| 12613 | OPC_CheckField, 5, 2, 0, // 8614: check Inst[6:5] == 0x0 |
| 12614 | OPC_Decode, 185, 23, 221, 2, // 8618: decode to V6_vgathermhw using decoder 349 |
| 12615 | // 8618: } |
| 12616 | 8, 7, // 8623: case 0x8: { |
| 12617 | OPC_CheckPredicate, 13, // 8625: check predicate 13 |
| 12618 | OPC_Decode, 188, 23, 222, 2, // 8627: decode to V6_vgathermwq using decoder 350 |
| 12619 | // 8627: } |
| 12620 | 10, 7, // 8632: case 0xa: { |
| 12621 | OPC_CheckPredicate, 13, // 8634: check predicate 13 |
| 12622 | OPC_Decode, 184, 23, 222, 2, // 8636: decode to V6_vgathermhq using decoder 350 |
| 12623 | // 8636: } |
| 12624 | 12, 0, // 8641: case 0xc: { |
| 12625 | OPC_CheckPredicate, 13, // 8643: check predicate 13 |
| 12626 | OPC_Decode, 186, 23, 223, 2, // 8645: decode to V6_vgathermhwq using decoder 351 |
| 12627 | // 8645: } |
| 12628 | // 8645: } // switch Inst[12:7] |
| 12629 | // 8645: } |
| 12630 | 1, 57, // 8650: case 0x1: { |
| 12631 | OPC_SwitchField, 5, 3, // 8652: switch Inst[7:5] { |
| 12632 | 0, 7, // 8655: case 0x0: { |
| 12633 | OPC_CheckPredicate, 13, // 8657: check predicate 13 |
| 12634 | OPC_Decode, 180, 25, 224, 2, // 8659: decode to V6_vscattermw using decoder 352 |
| 12635 | // 8659: } |
| 12636 | 1, 7, // 8664: case 0x1: { |
| 12637 | OPC_CheckPredicate, 13, // 8666: check predicate 13 |
| 12638 | OPC_Decode, 174, 25, 224, 2, // 8668: decode to V6_vscattermh using decoder 352 |
| 12639 | // 8668: } |
| 12640 | 2, 7, // 8673: case 0x2: { |
| 12641 | OPC_CheckPredicate, 13, // 8675: check predicate 13 |
| 12642 | OPC_Decode, 177, 25, 225, 2, // 8677: decode to V6_vscattermhw using decoder 353 |
| 12643 | // 8677: } |
| 12644 | 4, 7, // 8682: case 0x4: { |
| 12645 | OPC_CheckPredicate, 13, // 8684: check predicate 13 |
| 12646 | OPC_Decode, 181, 25, 224, 2, // 8686: decode to V6_vscattermw_add using decoder 352 |
| 12647 | // 8686: } |
| 12648 | 5, 7, // 8691: case 0x5: { |
| 12649 | OPC_CheckPredicate, 13, // 8693: check predicate 13 |
| 12650 | OPC_Decode, 175, 25, 224, 2, // 8695: decode to V6_vscattermh_add using decoder 352 |
| 12651 | // 8695: } |
| 12652 | 6, 0, // 8700: case 0x6: { |
| 12653 | OPC_CheckPredicate, 13, // 8702: check predicate 13 |
| 12654 | OPC_Decode, 178, 25, 225, 2, // 8704: decode to V6_vscattermhw_add using decoder 353 |
| 12655 | // 8704: } |
| 12656 | // 8704: } // switch Inst[7:5] |
| 12657 | // 8704: } |
| 12658 | 4, 21, // 8709: case 0x4: { |
| 12659 | OPC_SwitchField, 7, 1, // 8711: switch Inst[7] { |
| 12660 | 0, 7, // 8714: case 0x0: { |
| 12661 | OPC_CheckPredicate, 13, // 8716: check predicate 13 |
| 12662 | OPC_Decode, 182, 25, 226, 2, // 8718: decode to V6_vscattermwq using decoder 354 |
| 12663 | // 8718: } |
| 12664 | 1, 0, // 8723: case 0x1: { |
| 12665 | OPC_CheckPredicate, 13, // 8725: check predicate 13 |
| 12666 | OPC_Decode, 176, 25, 226, 2, // 8727: decode to V6_vscattermhq using decoder 354 |
| 12667 | // 8727: } |
| 12668 | // 8727: } // switch Inst[7] |
| 12669 | // 8727: } |
| 12670 | 5, 0, // 8732: case 0x5: { |
| 12671 | OPC_CheckPredicate, 13, // 8734: check predicate 13 |
| 12672 | OPC_CheckField, 7, 1, 0, // 8736: check Inst[7] == 0x0 |
| 12673 | OPC_Decode, 179, 25, 227, 2, // 8740: decode to V6_vscattermhwq using decoder 355 |
| 12674 | // 8740: } |
| 12675 | // 8740: } // switch Inst[23:21] |
| 12676 | // 8740: } |
| 12677 | 146, 1, 0, // 8745: case 0x92: { |
| 12678 | OPC_CheckPredicate, 15, // 8748: check predicate 15 |
| 12679 | OPC_CheckField, 21, 3, 0, // 8750: check Inst[23:21] == 0x0 |
| 12680 | OPC_CheckField, 13, 1, 0, // 8754: check Inst[13] == 0x0 |
| 12681 | OPC_CheckField, 5, 3, 1, // 8758: check Inst[7:5] == 0x1 |
| 12682 | OPC_Decode, 213, 20, 228, 2, // 8762: decode to V6_extractw using decoder 356 |
| 12683 | // 8762: } |
| 12684 | // 8762: } // switch Inst[31:24] |
| 12685 | }; |
| 12686 | static const uint8_t DecoderTableMustExtend32[1687] = { |
| 12687 | OPC_SwitchField, 21, 4, // 0: switch Inst[24:21] { |
| 12688 | 0, 8, // 3: case 0x0: { |
| 12689 | OPC_CheckField, 27, 5, 9, // 5: check Inst[31:27] == 0x9 |
| 12690 | OPC_Decode, 190, 16, 35, // 9: decode to PS_storerbabs using decoder 35 |
| 12691 | // 9: } |
| 12692 | 1, 29, // 13: case 0x1: { |
| 12693 | OPC_SwitchField, 25, 7, // 15: switch Inst[31:25] { |
| 12694 | 77, 13, // 18: case 0x4d: { |
| 12695 | OPC_CheckField, 12, 2, 1, // 20: check Inst[13:12] == 0x1 |
| 12696 | OPC_CheckField, 7, 1, 0, // 24: check Inst[7] == 0x0 |
| 12697 | OPC_Decode, 131, 13, 229, 2, // 28: decode to L4_loadbsw2_ap using decoder 357 |
| 12698 | // 28: } |
| 12699 | 78, 0, // 33: case 0x4e: { |
| 12700 | OPC_CheckField, 12, 1, 1, // 35: check Inst[12] == 0x1 |
| 12701 | OPC_Decode, 132, 13, 230, 2, // 39: decode to L4_loadbsw2_ur using decoder 358 |
| 12702 | // 39: } |
| 12703 | // 39: } // switch Inst[31:25] |
| 12704 | // 39: } |
| 12705 | 2, 40, // 44: case 0x2: { |
| 12706 | OPC_SwitchField, 27, 5, // 46: switch Inst[31:27] { |
| 12707 | 9, 4, // 49: case 0x9: { |
| 12708 | OPC_Decode, 194, 16, 37, // 51: decode to PS_storerhabs using decoder 37 |
| 12709 | // 51: } |
| 12710 | 19, 0, // 55: case 0x13: { |
| 12711 | OPC_SwitchField, 25, 2, // 57: switch Inst[26:25] { |
| 12712 | 1, 13, // 60: case 0x1: { |
| 12713 | OPC_CheckField, 12, 2, 1, // 62: check Inst[13:12] == 0x1 |
| 12714 | OPC_CheckField, 7, 1, 0, // 66: check Inst[7] == 0x0 |
| 12715 | OPC_Decode, 129, 13, 231, 2, // 70: decode to L4_loadalignh_ap using decoder 359 |
| 12716 | // 70: } |
| 12717 | 2, 0, // 75: case 0x2: { |
| 12718 | OPC_CheckField, 12, 1, 1, // 77: check Inst[12] == 0x1 |
| 12719 | OPC_Decode, 130, 13, 232, 2, // 81: decode to L4_loadalignh_ur using decoder 360 |
| 12720 | // 81: } |
| 12721 | // 81: } // switch Inst[26:25] |
| 12722 | // 81: } |
| 12723 | // 81: } // switch Inst[31:27] |
| 12724 | // 81: } |
| 12725 | 3, 40, // 86: case 0x3: { |
| 12726 | OPC_SwitchField, 27, 5, // 88: switch Inst[31:27] { |
| 12727 | 9, 4, // 91: case 0x9: { |
| 12728 | OPC_Decode, 193, 16, 37, // 93: decode to PS_storerfabs using decoder 37 |
| 12729 | // 93: } |
| 12730 | 19, 0, // 97: case 0x13: { |
| 12731 | OPC_SwitchField, 25, 2, // 99: switch Inst[26:25] { |
| 12732 | 1, 13, // 102: case 0x1: { |
| 12733 | OPC_CheckField, 12, 2, 1, // 104: check Inst[13:12] == 0x1 |
| 12734 | OPC_CheckField, 7, 1, 0, // 108: check Inst[7] == 0x0 |
| 12735 | OPC_Decode, 135, 13, 229, 2, // 112: decode to L4_loadbzw2_ap using decoder 357 |
| 12736 | // 112: } |
| 12737 | 2, 0, // 117: case 0x2: { |
| 12738 | OPC_CheckField, 12, 1, 1, // 119: check Inst[12] == 0x1 |
| 12739 | OPC_Decode, 136, 13, 230, 2, // 123: decode to L4_loadbzw2_ur using decoder 358 |
| 12740 | // 123: } |
| 12741 | // 123: } // switch Inst[26:25] |
| 12742 | // 123: } |
| 12743 | // 123: } // switch Inst[31:27] |
| 12744 | // 123: } |
| 12745 | 4, 40, // 128: case 0x4: { |
| 12746 | OPC_SwitchField, 27, 5, // 130: switch Inst[31:27] { |
| 12747 | 9, 4, // 133: case 0x9: { |
| 12748 | OPC_Decode, 196, 16, 39, // 135: decode to PS_storeriabs using decoder 39 |
| 12749 | // 135: } |
| 12750 | 19, 0, // 139: case 0x13: { |
| 12751 | OPC_SwitchField, 25, 2, // 141: switch Inst[26:25] { |
| 12752 | 1, 13, // 144: case 0x1: { |
| 12753 | OPC_CheckField, 12, 2, 1, // 146: check Inst[13:12] == 0x1 |
| 12754 | OPC_CheckField, 7, 1, 0, // 150: check Inst[7] == 0x0 |
| 12755 | OPC_Decode, 255, 12, 231, 2, // 154: decode to L4_loadalignb_ap using decoder 359 |
| 12756 | // 154: } |
| 12757 | 2, 0, // 159: case 0x2: { |
| 12758 | OPC_CheckField, 12, 1, 1, // 161: check Inst[12] == 0x1 |
| 12759 | OPC_Decode, 128, 13, 232, 2, // 165: decode to L4_loadalignb_ur using decoder 360 |
| 12760 | // 165: } |
| 12761 | // 165: } // switch Inst[26:25] |
| 12762 | // 165: } |
| 12763 | // 165: } // switch Inst[31:27] |
| 12764 | // 165: } |
| 12765 | 5, 70, // 170: case 0x5: { |
| 12766 | OPC_SwitchField, 12, 1, // 172: switch Inst[12] { |
| 12767 | 0, 23, // 175: case 0x0: { |
| 12768 | OPC_SwitchField, 11, 1, // 177: switch Inst[11] { |
| 12769 | 0, 8, // 180: case 0x0: { |
| 12770 | OPC_CheckField, 27, 5, 9, // 182: check Inst[31:27] == 0x9 |
| 12771 | OPC_Decode, 191, 16, 41, // 186: decode to PS_storerbnewabs using decoder 41 |
| 12772 | // 186: } |
| 12773 | 1, 0, // 190: case 0x1: { |
| 12774 | OPC_CheckField, 27, 5, 9, // 192: check Inst[31:27] == 0x9 |
| 12775 | OPC_Decode, 195, 16, 43, // 196: decode to PS_storerhnewabs using decoder 43 |
| 12776 | // 196: } |
| 12777 | // 196: } // switch Inst[11] |
| 12778 | // 196: } |
| 12779 | 1, 0, // 200: case 0x1: { |
| 12780 | OPC_SwitchField, 27, 5, // 202: switch Inst[31:27] { |
| 12781 | 9, 8, // 205: case 0x9: { |
| 12782 | OPC_CheckField, 11, 1, 0, // 207: check Inst[11] == 0x0 |
| 12783 | OPC_Decode, 197, 16, 45, // 211: decode to PS_storerinewabs using decoder 45 |
| 12784 | // 211: } |
| 12785 | 19, 0, // 215: case 0x13: { |
| 12786 | OPC_SwitchField, 25, 2, // 217: switch Inst[26:25] { |
| 12787 | 1, 13, // 220: case 0x1: { |
| 12788 | OPC_CheckField, 13, 1, 0, // 222: check Inst[13] == 0x0 |
| 12789 | OPC_CheckField, 7, 1, 0, // 226: check Inst[7] == 0x0 |
| 12790 | OPC_Decode, 137, 13, 233, 2, // 230: decode to L4_loadbzw4_ap using decoder 361 |
| 12791 | // 230: } |
| 12792 | 2, 0, // 235: case 0x2: { |
| 12793 | OPC_Decode, 138, 13, 234, 2, // 237: decode to L4_loadbzw4_ur using decoder 362 |
| 12794 | // 237: } |
| 12795 | // 237: } // switch Inst[26:25] |
| 12796 | // 237: } |
| 12797 | // 237: } // switch Inst[31:27] |
| 12798 | // 237: } |
| 12799 | // 237: } // switch Inst[12] |
| 12800 | // 237: } |
| 12801 | 6, 8, // 242: case 0x6: { |
| 12802 | OPC_CheckField, 27, 5, 9, // 244: check Inst[31:27] == 0x9 |
| 12803 | OPC_Decode, 192, 16, 47, // 248: decode to PS_storerdabs using decoder 47 |
| 12804 | // 248: } |
| 12805 | 7, 29, // 252: case 0x7: { |
| 12806 | OPC_SwitchField, 25, 7, // 254: switch Inst[31:25] { |
| 12807 | 77, 13, // 257: case 0x4d: { |
| 12808 | OPC_CheckField, 12, 2, 1, // 259: check Inst[13:12] == 0x1 |
| 12809 | OPC_CheckField, 7, 1, 0, // 263: check Inst[7] == 0x0 |
| 12810 | OPC_Decode, 133, 13, 233, 2, // 267: decode to L4_loadbsw4_ap using decoder 361 |
| 12811 | // 267: } |
| 12812 | 78, 0, // 272: case 0x4e: { |
| 12813 | OPC_CheckField, 12, 1, 1, // 274: check Inst[12] == 0x1 |
| 12814 | OPC_Decode, 134, 13, 234, 2, // 278: decode to L4_loadbsw4_ur using decoder 362 |
| 12815 | // 278: } |
| 12816 | // 278: } // switch Inst[31:25] |
| 12817 | // 278: } |
| 12818 | 8, 195, 1, // 283: case 0x8: { |
| 12819 | OPC_SwitchField, 27, 5, // 286: switch Inst[31:27] { |
| 12820 | 9, 4, // 289: case 0x9: { |
| 12821 | OPC_Decode, 184, 16, 49, // 291: decode to PS_loadrbabs using decoder 49 |
| 12822 | // 291: } |
| 12823 | 19, 78, // 295: case 0x13: { |
| 12824 | OPC_SwitchField, 25, 2, // 297: switch Inst[26:25] { |
| 12825 | 1, 13, // 300: case 0x1: { |
| 12826 | OPC_CheckField, 12, 2, 1, // 302: check Inst[13:12] == 0x1 |
| 12827 | OPC_CheckField, 7, 1, 0, // 306: check Inst[7] == 0x0 |
| 12828 | OPC_Decode, 141, 13, 229, 2, // 310: decode to L4_loadrb_ap using decoder 357 |
| 12829 | // 310: } |
| 12830 | 2, 9, // 315: case 0x2: { |
| 12831 | OPC_CheckField, 12, 1, 1, // 317: check Inst[12] == 0x1 |
| 12832 | OPC_Decode, 143, 13, 230, 2, // 321: decode to L4_loadrb_ur using decoder 358 |
| 12833 | // 321: } |
| 12834 | 3, 0, // 326: case 0x3: { |
| 12835 | OPC_SwitchField, 11, 3, // 328: switch Inst[13:11] { |
| 12836 | 4, 9, // 331: case 0x4: { |
| 12837 | OPC_CheckField, 5, 3, 4, // 333: check Inst[7:5] == 0x4 |
| 12838 | OPC_Decode, 167, 13, 235, 2, // 337: decode to L4_ploadrbt_abs using decoder 363 |
| 12839 | // 337: } |
| 12840 | 5, 9, // 342: case 0x5: { |
| 12841 | OPC_CheckField, 5, 3, 4, // 344: check Inst[7:5] == 0x4 |
| 12842 | OPC_Decode, 163, 13, 235, 2, // 348: decode to L4_ploadrbf_abs using decoder 363 |
| 12843 | // 348: } |
| 12844 | 6, 9, // 353: case 0x6: { |
| 12845 | OPC_CheckField, 5, 3, 4, // 355: check Inst[7:5] == 0x4 |
| 12846 | OPC_Decode, 169, 13, 235, 2, // 359: decode to L4_ploadrbtnew_abs using decoder 363 |
| 12847 | // 359: } |
| 12848 | 7, 0, // 364: case 0x7: { |
| 12849 | OPC_CheckField, 5, 3, 4, // 366: check Inst[7:5] == 0x4 |
| 12850 | OPC_Decode, 165, 13, 235, 2, // 370: decode to L4_ploadrbfnew_abs using decoder 363 |
| 12851 | // 370: } |
| 12852 | // 370: } // switch Inst[13:11] |
| 12853 | // 370: } |
| 12854 | // 370: } // switch Inst[26:25] |
| 12855 | // 370: } |
| 12856 | 21, 0, // 375: case 0x15: { |
| 12857 | OPC_SwitchField, 25, 2, // 377: switch Inst[26:25] { |
| 12858 | 1, 13, // 380: case 0x1: { |
| 12859 | OPC_CheckField, 13, 1, 0, // 382: check Inst[13] == 0x0 |
| 12860 | OPC_CheckField, 6, 2, 2, // 386: check Inst[7:6] == 0x2 |
| 12861 | OPC_Decode, 225, 19, 236, 2, // 390: decode to S4_storerb_ap using decoder 364 |
| 12862 | // 390: } |
| 12863 | 2, 9, // 395: case 0x2: { |
| 12864 | OPC_CheckField, 7, 1, 1, // 397: check Inst[7] == 0x1 |
| 12865 | OPC_Decode, 227, 19, 237, 2, // 401: decode to S4_storerb_ur using decoder 365 |
| 12866 | // 401: } |
| 12867 | 3, 0, // 406: case 0x3: { |
| 12868 | OPC_SwitchField, 2, 1, // 408: switch Inst[2] { |
| 12869 | 0, 33, // 411: case 0x0: { |
| 12870 | OPC_SwitchField, 13, 1, // 413: switch Inst[13] { |
| 12871 | 0, 13, // 416: case 0x0: { |
| 12872 | OPC_CheckField, 18, 3, 0, // 418: check Inst[20:18] == 0x0 |
| 12873 | OPC_CheckField, 7, 1, 1, // 422: check Inst[7] == 0x1 |
| 12874 | OPC_Decode, 142, 19, 238, 2, // 426: decode to S4_pstorerbt_abs using decoder 366 |
| 12875 | // 426: } |
| 12876 | 1, 0, // 431: case 0x1: { |
| 12877 | OPC_CheckField, 18, 3, 0, // 433: check Inst[20:18] == 0x0 |
| 12878 | OPC_CheckField, 7, 1, 1, // 437: check Inst[7] == 0x1 |
| 12879 | OPC_Decode, 144, 19, 238, 2, // 441: decode to S4_pstorerbtnew_abs using decoder 366 |
| 12880 | // 441: } |
| 12881 | // 441: } // switch Inst[13] |
| 12882 | // 441: } |
| 12883 | 1, 0, // 446: case 0x1: { |
| 12884 | OPC_SwitchField, 13, 1, // 448: switch Inst[13] { |
| 12885 | 0, 13, // 451: case 0x0: { |
| 12886 | OPC_CheckField, 18, 3, 0, // 453: check Inst[20:18] == 0x0 |
| 12887 | OPC_CheckField, 7, 1, 1, // 457: check Inst[7] == 0x1 |
| 12888 | OPC_Decode, 255, 18, 238, 2, // 461: decode to S4_pstorerbf_abs using decoder 366 |
| 12889 | // 461: } |
| 12890 | 1, 0, // 466: case 0x1: { |
| 12891 | OPC_CheckField, 18, 3, 0, // 468: check Inst[20:18] == 0x0 |
| 12892 | OPC_CheckField, 7, 1, 1, // 472: check Inst[7] == 0x1 |
| 12893 | OPC_Decode, 129, 19, 238, 2, // 476: decode to S4_pstorerbfnew_abs using decoder 366 |
| 12894 | // 476: } |
| 12895 | // 476: } // switch Inst[13] |
| 12896 | // 476: } |
| 12897 | // 476: } // switch Inst[2] |
| 12898 | // 476: } |
| 12899 | // 476: } // switch Inst[26:25] |
| 12900 | // 476: } |
| 12901 | // 476: } // switch Inst[31:27] |
| 12902 | // 476: } |
| 12903 | 9, 89, // 481: case 0x9: { |
| 12904 | OPC_SwitchField, 27, 5, // 483: switch Inst[31:27] { |
| 12905 | 9, 4, // 486: case 0x9: { |
| 12906 | OPC_Decode, 188, 16, 49, // 488: decode to PS_loadrubabs using decoder 49 |
| 12907 | // 488: } |
| 12908 | 19, 0, // 492: case 0x13: { |
| 12909 | OPC_SwitchField, 25, 2, // 494: switch Inst[26:25] { |
| 12910 | 1, 13, // 497: case 0x1: { |
| 12911 | OPC_CheckField, 12, 2, 1, // 499: check Inst[13:12] == 0x1 |
| 12912 | OPC_CheckField, 7, 1, 0, // 503: check Inst[7] == 0x0 |
| 12913 | OPC_Decode, 153, 13, 229, 2, // 507: decode to L4_loadrub_ap using decoder 357 |
| 12914 | // 507: } |
| 12915 | 2, 9, // 512: case 0x2: { |
| 12916 | OPC_CheckField, 12, 1, 1, // 514: check Inst[12] == 0x1 |
| 12917 | OPC_Decode, 155, 13, 230, 2, // 518: decode to L4_loadrub_ur using decoder 358 |
| 12918 | // 518: } |
| 12919 | 3, 0, // 523: case 0x3: { |
| 12920 | OPC_SwitchField, 11, 3, // 525: switch Inst[13:11] { |
| 12921 | 4, 9, // 528: case 0x4: { |
| 12922 | OPC_CheckField, 5, 3, 4, // 530: check Inst[7:5] == 0x4 |
| 12923 | OPC_Decode, 199, 13, 235, 2, // 534: decode to L4_ploadrubt_abs using decoder 363 |
| 12924 | // 534: } |
| 12925 | 5, 9, // 539: case 0x5: { |
| 12926 | OPC_CheckField, 5, 3, 4, // 541: check Inst[7:5] == 0x4 |
| 12927 | OPC_Decode, 195, 13, 235, 2, // 545: decode to L4_ploadrubf_abs using decoder 363 |
| 12928 | // 545: } |
| 12929 | 6, 9, // 550: case 0x6: { |
| 12930 | OPC_CheckField, 5, 3, 4, // 552: check Inst[7:5] == 0x4 |
| 12931 | OPC_Decode, 201, 13, 235, 2, // 556: decode to L4_ploadrubtnew_abs using decoder 363 |
| 12932 | // 556: } |
| 12933 | 7, 0, // 561: case 0x7: { |
| 12934 | OPC_CheckField, 5, 3, 4, // 563: check Inst[7:5] == 0x4 |
| 12935 | OPC_Decode, 197, 13, 235, 2, // 567: decode to L4_ploadrubfnew_abs using decoder 363 |
| 12936 | // 567: } |
| 12937 | // 567: } // switch Inst[13:11] |
| 12938 | // 567: } |
| 12939 | // 567: } // switch Inst[26:25] |
| 12940 | // 567: } |
| 12941 | // 567: } // switch Inst[31:27] |
| 12942 | // 567: } |
| 12943 | 10, 195, 1, // 572: case 0xa: { |
| 12944 | OPC_SwitchField, 27, 5, // 575: switch Inst[31:27] { |
| 12945 | 9, 4, // 578: case 0x9: { |
| 12946 | OPC_Decode, 186, 16, 51, // 580: decode to PS_loadrhabs using decoder 51 |
| 12947 | // 580: } |
| 12948 | 19, 78, // 584: case 0x13: { |
| 12949 | OPC_SwitchField, 25, 2, // 586: switch Inst[26:25] { |
| 12950 | 1, 13, // 589: case 0x1: { |
| 12951 | OPC_CheckField, 12, 2, 1, // 591: check Inst[13:12] == 0x1 |
| 12952 | OPC_CheckField, 7, 1, 0, // 595: check Inst[7] == 0x0 |
| 12953 | OPC_Decode, 147, 13, 229, 2, // 599: decode to L4_loadrh_ap using decoder 357 |
| 12954 | // 599: } |
| 12955 | 2, 9, // 604: case 0x2: { |
| 12956 | OPC_CheckField, 12, 1, 1, // 606: check Inst[12] == 0x1 |
| 12957 | OPC_Decode, 149, 13, 230, 2, // 610: decode to L4_loadrh_ur using decoder 358 |
| 12958 | // 610: } |
| 12959 | 3, 0, // 615: case 0x3: { |
| 12960 | OPC_SwitchField, 11, 3, // 617: switch Inst[13:11] { |
| 12961 | 4, 9, // 620: case 0x4: { |
| 12962 | OPC_CheckField, 5, 3, 4, // 622: check Inst[7:5] == 0x4 |
| 12963 | OPC_Decode, 183, 13, 235, 2, // 626: decode to L4_ploadrht_abs using decoder 363 |
| 12964 | // 626: } |
| 12965 | 5, 9, // 631: case 0x5: { |
| 12966 | OPC_CheckField, 5, 3, 4, // 633: check Inst[7:5] == 0x4 |
| 12967 | OPC_Decode, 179, 13, 235, 2, // 637: decode to L4_ploadrhf_abs using decoder 363 |
| 12968 | // 637: } |
| 12969 | 6, 9, // 642: case 0x6: { |
| 12970 | OPC_CheckField, 5, 3, 4, // 644: check Inst[7:5] == 0x4 |
| 12971 | OPC_Decode, 185, 13, 235, 2, // 648: decode to L4_ploadrhtnew_abs using decoder 363 |
| 12972 | // 648: } |
| 12973 | 7, 0, // 653: case 0x7: { |
| 12974 | OPC_CheckField, 5, 3, 4, // 655: check Inst[7:5] == 0x4 |
| 12975 | OPC_Decode, 181, 13, 235, 2, // 659: decode to L4_ploadrhfnew_abs using decoder 363 |
| 12976 | // 659: } |
| 12977 | // 659: } // switch Inst[13:11] |
| 12978 | // 659: } |
| 12979 | // 659: } // switch Inst[26:25] |
| 12980 | // 659: } |
| 12981 | 21, 0, // 664: case 0x15: { |
| 12982 | OPC_SwitchField, 25, 2, // 666: switch Inst[26:25] { |
| 12983 | 1, 13, // 669: case 0x1: { |
| 12984 | OPC_CheckField, 13, 1, 0, // 671: check Inst[13] == 0x0 |
| 12985 | OPC_CheckField, 6, 2, 2, // 675: check Inst[7:6] == 0x2 |
| 12986 | OPC_Decode, 237, 19, 236, 2, // 679: decode to S4_storerh_ap using decoder 364 |
| 12987 | // 679: } |
| 12988 | 2, 9, // 684: case 0x2: { |
| 12989 | OPC_CheckField, 7, 1, 1, // 686: check Inst[7] == 0x1 |
| 12990 | OPC_Decode, 239, 19, 237, 2, // 690: decode to S4_storerh_ur using decoder 365 |
| 12991 | // 690: } |
| 12992 | 3, 0, // 695: case 0x3: { |
| 12993 | OPC_SwitchField, 2, 1, // 697: switch Inst[2] { |
| 12994 | 0, 33, // 700: case 0x0: { |
| 12995 | OPC_SwitchField, 13, 1, // 702: switch Inst[13] { |
| 12996 | 0, 13, // 705: case 0x0: { |
| 12997 | OPC_CheckField, 18, 3, 0, // 707: check Inst[20:18] == 0x0 |
| 12998 | OPC_CheckField, 7, 1, 1, // 711: check Inst[7] == 0x1 |
| 12999 | OPC_Decode, 182, 19, 238, 2, // 715: decode to S4_pstorerht_abs using decoder 366 |
| 13000 | // 715: } |
| 13001 | 1, 0, // 720: case 0x1: { |
| 13002 | OPC_CheckField, 18, 3, 0, // 722: check Inst[20:18] == 0x0 |
| 13003 | OPC_CheckField, 7, 1, 1, // 726: check Inst[7] == 0x1 |
| 13004 | OPC_Decode, 184, 19, 238, 2, // 730: decode to S4_pstorerhtnew_abs using decoder 366 |
| 13005 | // 730: } |
| 13006 | // 730: } // switch Inst[13] |
| 13007 | // 730: } |
| 13008 | 1, 0, // 735: case 0x1: { |
| 13009 | OPC_SwitchField, 13, 1, // 737: switch Inst[13] { |
| 13010 | 0, 13, // 740: case 0x0: { |
| 13011 | OPC_CheckField, 18, 3, 0, // 742: check Inst[20:18] == 0x0 |
| 13012 | OPC_CheckField, 7, 1, 1, // 746: check Inst[7] == 0x1 |
| 13013 | OPC_Decode, 167, 19, 238, 2, // 750: decode to S4_pstorerhf_abs using decoder 366 |
| 13014 | // 750: } |
| 13015 | 1, 0, // 755: case 0x1: { |
| 13016 | OPC_CheckField, 18, 3, 0, // 757: check Inst[20:18] == 0x0 |
| 13017 | OPC_CheckField, 7, 1, 1, // 761: check Inst[7] == 0x1 |
| 13018 | OPC_Decode, 169, 19, 238, 2, // 765: decode to S4_pstorerhfnew_abs using decoder 366 |
| 13019 | // 765: } |
| 13020 | // 765: } // switch Inst[13] |
| 13021 | // 765: } |
| 13022 | // 765: } // switch Inst[2] |
| 13023 | // 765: } |
| 13024 | // 765: } // switch Inst[26:25] |
| 13025 | // 765: } |
| 13026 | // 765: } // switch Inst[31:27] |
| 13027 | // 765: } |
| 13028 | 11, 195, 1, // 770: case 0xb: { |
| 13029 | OPC_SwitchField, 27, 5, // 773: switch Inst[31:27] { |
| 13030 | 9, 4, // 776: case 0x9: { |
| 13031 | OPC_Decode, 189, 16, 51, // 778: decode to PS_loadruhabs using decoder 51 |
| 13032 | // 778: } |
| 13033 | 19, 78, // 782: case 0x13: { |
| 13034 | OPC_SwitchField, 25, 2, // 784: switch Inst[26:25] { |
| 13035 | 1, 13, // 787: case 0x1: { |
| 13036 | OPC_CheckField, 12, 2, 1, // 789: check Inst[13:12] == 0x1 |
| 13037 | OPC_CheckField, 7, 1, 0, // 793: check Inst[7] == 0x0 |
| 13038 | OPC_Decode, 156, 13, 229, 2, // 797: decode to L4_loadruh_ap using decoder 357 |
| 13039 | // 797: } |
| 13040 | 2, 9, // 802: case 0x2: { |
| 13041 | OPC_CheckField, 12, 1, 1, // 804: check Inst[12] == 0x1 |
| 13042 | OPC_Decode, 158, 13, 230, 2, // 808: decode to L4_loadruh_ur using decoder 358 |
| 13043 | // 808: } |
| 13044 | 3, 0, // 813: case 0x3: { |
| 13045 | OPC_SwitchField, 11, 3, // 815: switch Inst[13:11] { |
| 13046 | 4, 9, // 818: case 0x4: { |
| 13047 | OPC_CheckField, 5, 3, 4, // 820: check Inst[7:5] == 0x4 |
| 13048 | OPC_Decode, 207, 13, 235, 2, // 824: decode to L4_ploadruht_abs using decoder 363 |
| 13049 | // 824: } |
| 13050 | 5, 9, // 829: case 0x5: { |
| 13051 | OPC_CheckField, 5, 3, 4, // 831: check Inst[7:5] == 0x4 |
| 13052 | OPC_Decode, 203, 13, 235, 2, // 835: decode to L4_ploadruhf_abs using decoder 363 |
| 13053 | // 835: } |
| 13054 | 6, 9, // 840: case 0x6: { |
| 13055 | OPC_CheckField, 5, 3, 4, // 842: check Inst[7:5] == 0x4 |
| 13056 | OPC_Decode, 209, 13, 235, 2, // 846: decode to L4_ploadruhtnew_abs using decoder 363 |
| 13057 | // 846: } |
| 13058 | 7, 0, // 851: case 0x7: { |
| 13059 | OPC_CheckField, 5, 3, 4, // 853: check Inst[7:5] == 0x4 |
| 13060 | OPC_Decode, 205, 13, 235, 2, // 857: decode to L4_ploadruhfnew_abs using decoder 363 |
| 13061 | // 857: } |
| 13062 | // 857: } // switch Inst[13:11] |
| 13063 | // 857: } |
| 13064 | // 857: } // switch Inst[26:25] |
| 13065 | // 857: } |
| 13066 | 21, 0, // 862: case 0x15: { |
| 13067 | OPC_SwitchField, 25, 2, // 864: switch Inst[26:25] { |
| 13068 | 1, 13, // 867: case 0x1: { |
| 13069 | OPC_CheckField, 13, 1, 0, // 869: check Inst[13] == 0x0 |
| 13070 | OPC_CheckField, 6, 2, 2, // 873: check Inst[7:6] == 0x2 |
| 13071 | OPC_Decode, 234, 19, 236, 2, // 877: decode to S4_storerf_ap using decoder 364 |
| 13072 | // 877: } |
| 13073 | 2, 9, // 882: case 0x2: { |
| 13074 | OPC_CheckField, 7, 1, 1, // 884: check Inst[7] == 0x1 |
| 13075 | OPC_Decode, 236, 19, 237, 2, // 888: decode to S4_storerf_ur using decoder 365 |
| 13076 | // 888: } |
| 13077 | 3, 0, // 893: case 0x3: { |
| 13078 | OPC_SwitchField, 2, 1, // 895: switch Inst[2] { |
| 13079 | 0, 33, // 898: case 0x0: { |
| 13080 | OPC_SwitchField, 13, 1, // 900: switch Inst[13] { |
| 13081 | 0, 13, // 903: case 0x0: { |
| 13082 | OPC_CheckField, 18, 3, 0, // 905: check Inst[20:18] == 0x0 |
| 13083 | OPC_CheckField, 7, 1, 1, // 909: check Inst[7] == 0x1 |
| 13084 | OPC_Decode, 162, 19, 238, 2, // 913: decode to S4_pstorerft_abs using decoder 366 |
| 13085 | // 913: } |
| 13086 | 1, 0, // 918: case 0x1: { |
| 13087 | OPC_CheckField, 18, 3, 0, // 920: check Inst[20:18] == 0x0 |
| 13088 | OPC_CheckField, 7, 1, 1, // 924: check Inst[7] == 0x1 |
| 13089 | OPC_Decode, 164, 19, 238, 2, // 928: decode to S4_pstorerftnew_abs using decoder 366 |
| 13090 | // 928: } |
| 13091 | // 928: } // switch Inst[13] |
| 13092 | // 928: } |
| 13093 | 1, 0, // 933: case 0x1: { |
| 13094 | OPC_SwitchField, 13, 1, // 935: switch Inst[13] { |
| 13095 | 0, 13, // 938: case 0x0: { |
| 13096 | OPC_CheckField, 18, 3, 0, // 940: check Inst[20:18] == 0x0 |
| 13097 | OPC_CheckField, 7, 1, 1, // 944: check Inst[7] == 0x1 |
| 13098 | OPC_Decode, 157, 19, 238, 2, // 948: decode to S4_pstorerff_abs using decoder 366 |
| 13099 | // 948: } |
| 13100 | 1, 0, // 953: case 0x1: { |
| 13101 | OPC_CheckField, 18, 3, 0, // 955: check Inst[20:18] == 0x0 |
| 13102 | OPC_CheckField, 7, 1, 1, // 959: check Inst[7] == 0x1 |
| 13103 | OPC_Decode, 159, 19, 238, 2, // 963: decode to S4_pstorerffnew_abs using decoder 366 |
| 13104 | // 963: } |
| 13105 | // 963: } // switch Inst[13] |
| 13106 | // 963: } |
| 13107 | // 963: } // switch Inst[2] |
| 13108 | // 963: } |
| 13109 | // 963: } // switch Inst[26:25] |
| 13110 | // 963: } |
| 13111 | // 963: } // switch Inst[31:27] |
| 13112 | // 963: } |
| 13113 | 12, 195, 1, // 968: case 0xc: { |
| 13114 | OPC_SwitchField, 27, 5, // 971: switch Inst[31:27] { |
| 13115 | 9, 4, // 974: case 0x9: { |
| 13116 | OPC_Decode, 187, 16, 53, // 976: decode to PS_loadriabs using decoder 53 |
| 13117 | // 976: } |
| 13118 | 19, 78, // 980: case 0x13: { |
| 13119 | OPC_SwitchField, 25, 2, // 982: switch Inst[26:25] { |
| 13120 | 1, 13, // 985: case 0x1: { |
| 13121 | OPC_CheckField, 12, 2, 1, // 987: check Inst[13:12] == 0x1 |
| 13122 | OPC_CheckField, 7, 1, 0, // 991: check Inst[7] == 0x0 |
| 13123 | OPC_Decode, 150, 13, 229, 2, // 995: decode to L4_loadri_ap using decoder 357 |
| 13124 | // 995: } |
| 13125 | 2, 9, // 1000: case 0x2: { |
| 13126 | OPC_CheckField, 12, 1, 1, // 1002: check Inst[12] == 0x1 |
| 13127 | OPC_Decode, 152, 13, 230, 2, // 1006: decode to L4_loadri_ur using decoder 358 |
| 13128 | // 1006: } |
| 13129 | 3, 0, // 1011: case 0x3: { |
| 13130 | OPC_SwitchField, 11, 3, // 1013: switch Inst[13:11] { |
| 13131 | 4, 9, // 1016: case 0x4: { |
| 13132 | OPC_CheckField, 5, 3, 4, // 1018: check Inst[7:5] == 0x4 |
| 13133 | OPC_Decode, 191, 13, 235, 2, // 1022: decode to L4_ploadrit_abs using decoder 363 |
| 13134 | // 1022: } |
| 13135 | 5, 9, // 1027: case 0x5: { |
| 13136 | OPC_CheckField, 5, 3, 4, // 1029: check Inst[7:5] == 0x4 |
| 13137 | OPC_Decode, 187, 13, 235, 2, // 1033: decode to L4_ploadrif_abs using decoder 363 |
| 13138 | // 1033: } |
| 13139 | 6, 9, // 1038: case 0x6: { |
| 13140 | OPC_CheckField, 5, 3, 4, // 1040: check Inst[7:5] == 0x4 |
| 13141 | OPC_Decode, 193, 13, 235, 2, // 1044: decode to L4_ploadritnew_abs using decoder 363 |
| 13142 | // 1044: } |
| 13143 | 7, 0, // 1049: case 0x7: { |
| 13144 | OPC_CheckField, 5, 3, 4, // 1051: check Inst[7:5] == 0x4 |
| 13145 | OPC_Decode, 189, 13, 235, 2, // 1055: decode to L4_ploadrifnew_abs using decoder 363 |
| 13146 | // 1055: } |
| 13147 | // 1055: } // switch Inst[13:11] |
| 13148 | // 1055: } |
| 13149 | // 1055: } // switch Inst[26:25] |
| 13150 | // 1055: } |
| 13151 | 21, 0, // 1060: case 0x15: { |
| 13152 | OPC_SwitchField, 25, 2, // 1062: switch Inst[26:25] { |
| 13153 | 1, 13, // 1065: case 0x1: { |
| 13154 | OPC_CheckField, 13, 1, 0, // 1067: check Inst[13] == 0x0 |
| 13155 | OPC_CheckField, 6, 2, 2, // 1071: check Inst[7:6] == 0x2 |
| 13156 | OPC_Decode, 243, 19, 236, 2, // 1075: decode to S4_storeri_ap using decoder 364 |
| 13157 | // 1075: } |
| 13158 | 2, 9, // 1080: case 0x2: { |
| 13159 | OPC_CheckField, 7, 1, 1, // 1082: check Inst[7] == 0x1 |
| 13160 | OPC_Decode, 245, 19, 237, 2, // 1086: decode to S4_storeri_ur using decoder 365 |
| 13161 | // 1086: } |
| 13162 | 3, 0, // 1091: case 0x3: { |
| 13163 | OPC_SwitchField, 2, 1, // 1093: switch Inst[2] { |
| 13164 | 0, 33, // 1096: case 0x0: { |
| 13165 | OPC_SwitchField, 13, 1, // 1098: switch Inst[13] { |
| 13166 | 0, 13, // 1101: case 0x0: { |
| 13167 | OPC_CheckField, 18, 3, 0, // 1103: check Inst[20:18] == 0x0 |
| 13168 | OPC_CheckField, 7, 1, 1, // 1107: check Inst[7] == 0x1 |
| 13169 | OPC_Decode, 202, 19, 238, 2, // 1111: decode to S4_pstorerit_abs using decoder 366 |
| 13170 | // 1111: } |
| 13171 | 1, 0, // 1116: case 0x1: { |
| 13172 | OPC_CheckField, 18, 3, 0, // 1118: check Inst[20:18] == 0x0 |
| 13173 | OPC_CheckField, 7, 1, 1, // 1122: check Inst[7] == 0x1 |
| 13174 | OPC_Decode, 204, 19, 238, 2, // 1126: decode to S4_pstoreritnew_abs using decoder 366 |
| 13175 | // 1126: } |
| 13176 | // 1126: } // switch Inst[13] |
| 13177 | // 1126: } |
| 13178 | 1, 0, // 1131: case 0x1: { |
| 13179 | OPC_SwitchField, 13, 1, // 1133: switch Inst[13] { |
| 13180 | 0, 13, // 1136: case 0x0: { |
| 13181 | OPC_CheckField, 18, 3, 0, // 1138: check Inst[20:18] == 0x0 |
| 13182 | OPC_CheckField, 7, 1, 1, // 1142: check Inst[7] == 0x1 |
| 13183 | OPC_Decode, 187, 19, 238, 2, // 1146: decode to S4_pstorerif_abs using decoder 366 |
| 13184 | // 1146: } |
| 13185 | 1, 0, // 1151: case 0x1: { |
| 13186 | OPC_CheckField, 18, 3, 0, // 1153: check Inst[20:18] == 0x0 |
| 13187 | OPC_CheckField, 7, 1, 1, // 1157: check Inst[7] == 0x1 |
| 13188 | OPC_Decode, 189, 19, 238, 2, // 1161: decode to S4_pstorerifnew_abs using decoder 366 |
| 13189 | // 1161: } |
| 13190 | // 1161: } // switch Inst[13] |
| 13191 | // 1161: } |
| 13192 | // 1161: } // switch Inst[2] |
| 13193 | // 1161: } |
| 13194 | // 1161: } // switch Inst[26:25] |
| 13195 | // 1161: } |
| 13196 | // 1161: } // switch Inst[31:27] |
| 13197 | // 1161: } |
| 13198 | 13, 193, 2, // 1166: case 0xd: { |
| 13199 | OPC_SwitchField, 11, 2, // 1169: switch Inst[12:11] { |
| 13200 | 0, 104, // 1172: case 0x0: { |
| 13201 | OPC_SwitchField, 25, 7, // 1174: switch Inst[31:25] { |
| 13202 | 85, 13, // 1177: case 0x55: { |
| 13203 | OPC_CheckField, 13, 1, 0, // 1179: check Inst[13] == 0x0 |
| 13204 | OPC_CheckField, 6, 2, 2, // 1183: check Inst[7:6] == 0x2 |
| 13205 | OPC_Decode, 228, 19, 239, 2, // 1187: decode to S4_storerbnew_ap using decoder 367 |
| 13206 | // 1187: } |
| 13207 | 86, 9, // 1192: case 0x56: { |
| 13208 | OPC_CheckField, 7, 1, 1, // 1194: check Inst[7] == 0x1 |
| 13209 | OPC_Decode, 230, 19, 240, 2, // 1198: decode to S4_storerbnew_ur using decoder 368 |
| 13210 | // 1198: } |
| 13211 | 87, 0, // 1203: case 0x57: { |
| 13212 | OPC_SwitchField, 2, 1, // 1205: switch Inst[2] { |
| 13213 | 0, 33, // 1208: case 0x0: { |
| 13214 | OPC_SwitchField, 13, 1, // 1210: switch Inst[13] { |
| 13215 | 0, 13, // 1213: case 0x0: { |
| 13216 | OPC_CheckField, 18, 3, 0, // 1215: check Inst[20:18] == 0x0 |
| 13217 | OPC_CheckField, 7, 1, 1, // 1219: check Inst[7] == 0x1 |
| 13218 | OPC_Decode, 137, 19, 241, 2, // 1223: decode to S4_pstorerbnewt_abs using decoder 369 |
| 13219 | // 1223: } |
| 13220 | 1, 0, // 1228: case 0x1: { |
| 13221 | OPC_CheckField, 18, 3, 0, // 1230: check Inst[20:18] == 0x0 |
| 13222 | OPC_CheckField, 7, 1, 1, // 1234: check Inst[7] == 0x1 |
| 13223 | OPC_Decode, 139, 19, 241, 2, // 1238: decode to S4_pstorerbnewtnew_abs using decoder 369 |
| 13224 | // 1238: } |
| 13225 | // 1238: } // switch Inst[13] |
| 13226 | // 1238: } |
| 13227 | 1, 0, // 1243: case 0x1: { |
| 13228 | OPC_SwitchField, 13, 1, // 1245: switch Inst[13] { |
| 13229 | 0, 13, // 1248: case 0x0: { |
| 13230 | OPC_CheckField, 18, 3, 0, // 1250: check Inst[20:18] == 0x0 |
| 13231 | OPC_CheckField, 7, 1, 1, // 1254: check Inst[7] == 0x1 |
| 13232 | OPC_Decode, 132, 19, 241, 2, // 1258: decode to S4_pstorerbnewf_abs using decoder 369 |
| 13233 | // 1258: } |
| 13234 | 1, 0, // 1263: case 0x1: { |
| 13235 | OPC_CheckField, 18, 3, 0, // 1265: check Inst[20:18] == 0x0 |
| 13236 | OPC_CheckField, 7, 1, 1, // 1269: check Inst[7] == 0x1 |
| 13237 | OPC_Decode, 134, 19, 241, 2, // 1273: decode to S4_pstorerbnewfnew_abs using decoder 369 |
| 13238 | // 1273: } |
| 13239 | // 1273: } // switch Inst[13] |
| 13240 | // 1273: } |
| 13241 | // 1273: } // switch Inst[2] |
| 13242 | // 1273: } |
| 13243 | // 1273: } // switch Inst[31:25] |
| 13244 | // 1273: } |
| 13245 | 1, 104, // 1278: case 0x1: { |
| 13246 | OPC_SwitchField, 25, 7, // 1280: switch Inst[31:25] { |
| 13247 | 85, 13, // 1283: case 0x55: { |
| 13248 | OPC_CheckField, 13, 1, 0, // 1285: check Inst[13] == 0x0 |
| 13249 | OPC_CheckField, 6, 2, 2, // 1289: check Inst[7:6] == 0x2 |
| 13250 | OPC_Decode, 240, 19, 239, 2, // 1293: decode to S4_storerhnew_ap using decoder 367 |
| 13251 | // 1293: } |
| 13252 | 86, 9, // 1298: case 0x56: { |
| 13253 | OPC_CheckField, 7, 1, 1, // 1300: check Inst[7] == 0x1 |
| 13254 | OPC_Decode, 242, 19, 240, 2, // 1304: decode to S4_storerhnew_ur using decoder 368 |
| 13255 | // 1304: } |
| 13256 | 87, 0, // 1309: case 0x57: { |
| 13257 | OPC_SwitchField, 2, 1, // 1311: switch Inst[2] { |
| 13258 | 0, 33, // 1314: case 0x0: { |
| 13259 | OPC_SwitchField, 13, 1, // 1316: switch Inst[13] { |
| 13260 | 0, 13, // 1319: case 0x0: { |
| 13261 | OPC_CheckField, 18, 3, 0, // 1321: check Inst[20:18] == 0x0 |
| 13262 | OPC_CheckField, 7, 1, 1, // 1325: check Inst[7] == 0x1 |
| 13263 | OPC_Decode, 177, 19, 241, 2, // 1329: decode to S4_pstorerhnewt_abs using decoder 369 |
| 13264 | // 1329: } |
| 13265 | 1, 0, // 1334: case 0x1: { |
| 13266 | OPC_CheckField, 18, 3, 0, // 1336: check Inst[20:18] == 0x0 |
| 13267 | OPC_CheckField, 7, 1, 1, // 1340: check Inst[7] == 0x1 |
| 13268 | OPC_Decode, 179, 19, 241, 2, // 1344: decode to S4_pstorerhnewtnew_abs using decoder 369 |
| 13269 | // 1344: } |
| 13270 | // 1344: } // switch Inst[13] |
| 13271 | // 1344: } |
| 13272 | 1, 0, // 1349: case 0x1: { |
| 13273 | OPC_SwitchField, 13, 1, // 1351: switch Inst[13] { |
| 13274 | 0, 13, // 1354: case 0x0: { |
| 13275 | OPC_CheckField, 18, 3, 0, // 1356: check Inst[20:18] == 0x0 |
| 13276 | OPC_CheckField, 7, 1, 1, // 1360: check Inst[7] == 0x1 |
| 13277 | OPC_Decode, 172, 19, 241, 2, // 1364: decode to S4_pstorerhnewf_abs using decoder 369 |
| 13278 | // 1364: } |
| 13279 | 1, 0, // 1369: case 0x1: { |
| 13280 | OPC_CheckField, 18, 3, 0, // 1371: check Inst[20:18] == 0x0 |
| 13281 | OPC_CheckField, 7, 1, 1, // 1375: check Inst[7] == 0x1 |
| 13282 | OPC_Decode, 174, 19, 241, 2, // 1379: decode to S4_pstorerhnewfnew_abs using decoder 369 |
| 13283 | // 1379: } |
| 13284 | // 1379: } // switch Inst[13] |
| 13285 | // 1379: } |
| 13286 | // 1379: } // switch Inst[2] |
| 13287 | // 1379: } |
| 13288 | // 1379: } // switch Inst[31:25] |
| 13289 | // 1379: } |
| 13290 | 2, 0, // 1384: case 0x2: { |
| 13291 | OPC_SwitchField, 25, 7, // 1386: switch Inst[31:25] { |
| 13292 | 85, 13, // 1389: case 0x55: { |
| 13293 | OPC_CheckField, 13, 1, 0, // 1391: check Inst[13] == 0x0 |
| 13294 | OPC_CheckField, 6, 2, 2, // 1395: check Inst[7:6] == 0x2 |
| 13295 | OPC_Decode, 246, 19, 239, 2, // 1399: decode to S4_storerinew_ap using decoder 367 |
| 13296 | // 1399: } |
| 13297 | 86, 9, // 1404: case 0x56: { |
| 13298 | OPC_CheckField, 7, 1, 1, // 1406: check Inst[7] == 0x1 |
| 13299 | OPC_Decode, 248, 19, 240, 2, // 1410: decode to S4_storerinew_ur using decoder 368 |
| 13300 | // 1410: } |
| 13301 | 87, 0, // 1415: case 0x57: { |
| 13302 | OPC_SwitchField, 2, 1, // 1417: switch Inst[2] { |
| 13303 | 0, 33, // 1420: case 0x0: { |
| 13304 | OPC_SwitchField, 13, 1, // 1422: switch Inst[13] { |
| 13305 | 0, 13, // 1425: case 0x0: { |
| 13306 | OPC_CheckField, 18, 3, 0, // 1427: check Inst[20:18] == 0x0 |
| 13307 | OPC_CheckField, 7, 1, 1, // 1431: check Inst[7] == 0x1 |
| 13308 | OPC_Decode, 197, 19, 241, 2, // 1435: decode to S4_pstorerinewt_abs using decoder 369 |
| 13309 | // 1435: } |
| 13310 | 1, 0, // 1440: case 0x1: { |
| 13311 | OPC_CheckField, 18, 3, 0, // 1442: check Inst[20:18] == 0x0 |
| 13312 | OPC_CheckField, 7, 1, 1, // 1446: check Inst[7] == 0x1 |
| 13313 | OPC_Decode, 199, 19, 241, 2, // 1450: decode to S4_pstorerinewtnew_abs using decoder 369 |
| 13314 | // 1450: } |
| 13315 | // 1450: } // switch Inst[13] |
| 13316 | // 1450: } |
| 13317 | 1, 0, // 1455: case 0x1: { |
| 13318 | OPC_SwitchField, 13, 1, // 1457: switch Inst[13] { |
| 13319 | 0, 13, // 1460: case 0x0: { |
| 13320 | OPC_CheckField, 18, 3, 0, // 1462: check Inst[20:18] == 0x0 |
| 13321 | OPC_CheckField, 7, 1, 1, // 1466: check Inst[7] == 0x1 |
| 13322 | OPC_Decode, 192, 19, 241, 2, // 1470: decode to S4_pstorerinewf_abs using decoder 369 |
| 13323 | // 1470: } |
| 13324 | 1, 0, // 1475: case 0x1: { |
| 13325 | OPC_CheckField, 18, 3, 0, // 1477: check Inst[20:18] == 0x0 |
| 13326 | OPC_CheckField, 7, 1, 1, // 1481: check Inst[7] == 0x1 |
| 13327 | OPC_Decode, 194, 19, 241, 2, // 1485: decode to S4_pstorerinewfnew_abs using decoder 369 |
| 13328 | // 1485: } |
| 13329 | // 1485: } // switch Inst[13] |
| 13330 | // 1485: } |
| 13331 | // 1485: } // switch Inst[2] |
| 13332 | // 1485: } |
| 13333 | // 1485: } // switch Inst[31:25] |
| 13334 | // 1485: } |
| 13335 | // 1485: } // switch Inst[12:11] |
| 13336 | // 1485: } |
| 13337 | 14, 0, // 1490: case 0xe: { |
| 13338 | OPC_SwitchField, 27, 5, // 1492: switch Inst[31:27] { |
| 13339 | 9, 4, // 1495: case 0x9: { |
| 13340 | OPC_Decode, 185, 16, 55, // 1497: decode to PS_loadrdabs using decoder 55 |
| 13341 | // 1497: } |
| 13342 | 19, 78, // 1501: case 0x13: { |
| 13343 | OPC_SwitchField, 25, 2, // 1503: switch Inst[26:25] { |
| 13344 | 1, 13, // 1506: case 0x1: { |
| 13345 | OPC_CheckField, 12, 2, 1, // 1508: check Inst[13:12] == 0x1 |
| 13346 | OPC_CheckField, 7, 1, 0, // 1512: check Inst[7] == 0x0 |
| 13347 | OPC_Decode, 144, 13, 233, 2, // 1516: decode to L4_loadrd_ap using decoder 361 |
| 13348 | // 1516: } |
| 13349 | 2, 9, // 1521: case 0x2: { |
| 13350 | OPC_CheckField, 12, 1, 1, // 1523: check Inst[12] == 0x1 |
| 13351 | OPC_Decode, 146, 13, 234, 2, // 1527: decode to L4_loadrd_ur using decoder 362 |
| 13352 | // 1527: } |
| 13353 | 3, 0, // 1532: case 0x3: { |
| 13354 | OPC_SwitchField, 11, 3, // 1534: switch Inst[13:11] { |
| 13355 | 4, 9, // 1537: case 0x4: { |
| 13356 | OPC_CheckField, 5, 3, 4, // 1539: check Inst[7:5] == 0x4 |
| 13357 | OPC_Decode, 175, 13, 242, 2, // 1543: decode to L4_ploadrdt_abs using decoder 370 |
| 13358 | // 1543: } |
| 13359 | 5, 9, // 1548: case 0x5: { |
| 13360 | OPC_CheckField, 5, 3, 4, // 1550: check Inst[7:5] == 0x4 |
| 13361 | OPC_Decode, 171, 13, 242, 2, // 1554: decode to L4_ploadrdf_abs using decoder 370 |
| 13362 | // 1554: } |
| 13363 | 6, 9, // 1559: case 0x6: { |
| 13364 | OPC_CheckField, 5, 3, 4, // 1561: check Inst[7:5] == 0x4 |
| 13365 | OPC_Decode, 177, 13, 242, 2, // 1565: decode to L4_ploadrdtnew_abs using decoder 370 |
| 13366 | // 1565: } |
| 13367 | 7, 0, // 1570: case 0x7: { |
| 13368 | OPC_CheckField, 5, 3, 4, // 1572: check Inst[7:5] == 0x4 |
| 13369 | OPC_Decode, 173, 13, 242, 2, // 1576: decode to L4_ploadrdfnew_abs using decoder 370 |
| 13370 | // 1576: } |
| 13371 | // 1576: } // switch Inst[13:11] |
| 13372 | // 1576: } |
| 13373 | // 1576: } // switch Inst[26:25] |
| 13374 | // 1576: } |
| 13375 | 21, 0, // 1581: case 0x15: { |
| 13376 | OPC_SwitchField, 25, 2, // 1583: switch Inst[26:25] { |
| 13377 | 1, 13, // 1586: case 0x1: { |
| 13378 | OPC_CheckField, 13, 1, 0, // 1588: check Inst[13] == 0x0 |
| 13379 | OPC_CheckField, 6, 2, 2, // 1592: check Inst[7:6] == 0x2 |
| 13380 | OPC_Decode, 231, 19, 243, 2, // 1596: decode to S4_storerd_ap using decoder 371 |
| 13381 | // 1596: } |
| 13382 | 2, 9, // 1601: case 0x2: { |
| 13383 | OPC_CheckField, 7, 1, 1, // 1603: check Inst[7] == 0x1 |
| 13384 | OPC_Decode, 233, 19, 244, 2, // 1607: decode to S4_storerd_ur using decoder 372 |
| 13385 | // 1607: } |
| 13386 | 3, 0, // 1612: case 0x3: { |
| 13387 | OPC_SwitchField, 2, 1, // 1614: switch Inst[2] { |
| 13388 | 0, 33, // 1617: case 0x0: { |
| 13389 | OPC_SwitchField, 13, 1, // 1619: switch Inst[13] { |
| 13390 | 0, 13, // 1622: case 0x0: { |
| 13391 | OPC_CheckField, 18, 3, 0, // 1624: check Inst[20:18] == 0x0 |
| 13392 | OPC_CheckField, 7, 1, 1, // 1628: check Inst[7] == 0x1 |
| 13393 | OPC_Decode, 152, 19, 245, 2, // 1632: decode to S4_pstorerdt_abs using decoder 373 |
| 13394 | // 1632: } |
| 13395 | 1, 0, // 1637: case 0x1: { |
| 13396 | OPC_CheckField, 18, 3, 0, // 1639: check Inst[20:18] == 0x0 |
| 13397 | OPC_CheckField, 7, 1, 1, // 1643: check Inst[7] == 0x1 |
| 13398 | OPC_Decode, 154, 19, 245, 2, // 1647: decode to S4_pstorerdtnew_abs using decoder 373 |
| 13399 | // 1647: } |
| 13400 | // 1647: } // switch Inst[13] |
| 13401 | // 1647: } |
| 13402 | 1, 0, // 1652: case 0x1: { |
| 13403 | OPC_SwitchField, 13, 1, // 1654: switch Inst[13] { |
| 13404 | 0, 13, // 1657: case 0x0: { |
| 13405 | OPC_CheckField, 18, 3, 0, // 1659: check Inst[20:18] == 0x0 |
| 13406 | OPC_CheckField, 7, 1, 1, // 1663: check Inst[7] == 0x1 |
| 13407 | OPC_Decode, 147, 19, 245, 2, // 1667: decode to S4_pstorerdf_abs using decoder 373 |
| 13408 | // 1667: } |
| 13409 | 1, 0, // 1672: case 0x1: { |
| 13410 | OPC_CheckField, 18, 3, 0, // 1674: check Inst[20:18] == 0x0 |
| 13411 | OPC_CheckField, 7, 1, 1, // 1678: check Inst[7] == 0x1 |
| 13412 | OPC_Decode, 149, 19, 245, 2, // 1682: decode to S4_pstorerdfnew_abs using decoder 373 |
| 13413 | // 1682: } |
| 13414 | // 1682: } // switch Inst[13] |
| 13415 | // 1682: } |
| 13416 | // 1682: } // switch Inst[2] |
| 13417 | // 1682: } |
| 13418 | // 1682: } // switch Inst[26:25] |
| 13419 | // 1682: } |
| 13420 | // 1682: } // switch Inst[31:27] |
| 13421 | // 1682: } |
| 13422 | // 1682: } // switch Inst[24:21] |
| 13423 | }; |
| 13424 | static const uint8_t DecoderTableSUBINSN_A32[317] = { |
| 13425 | OPC_SwitchField, 11, 2, // 0: switch Inst[12:11] { |
| 13426 | 0, 9, // 3: case 0x0: { |
| 13427 | OPC_CheckField, 28, 4, 0, // 5: check Inst[31:28] == 0x0 |
| 13428 | OPC_Decode, 151, 20, 246, 2, // 9: decode to SA1_addi using decoder 374 |
| 13429 | // 9: } |
| 13430 | 1, 25, // 14: case 0x1: { |
| 13431 | OPC_SwitchField, 10, 1, // 16: switch Inst[10] { |
| 13432 | 0, 9, // 19: case 0x0: { |
| 13433 | OPC_CheckField, 28, 4, 0, // 21: check Inst[31:28] == 0x0 |
| 13434 | OPC_Decode, 168, 20, 247, 2, // 25: decode to SA1_seti using decoder 375 |
| 13435 | // 25: } |
| 13436 | 1, 0, // 30: case 0x1: { |
| 13437 | OPC_CheckField, 28, 4, 0, // 32: check Inst[31:28] == 0x0 |
| 13438 | OPC_Decode, 153, 20, 248, 2, // 36: decode to SA1_addsp using decoder 376 |
| 13439 | // 36: } |
| 13440 | // 36: } // switch Inst[10] |
| 13441 | // 36: } |
| 13442 | 2, 91, // 41: case 0x2: { |
| 13443 | OPC_SwitchField, 8, 3, // 43: switch Inst[10:8] { |
| 13444 | 0, 9, // 46: case 0x0: { |
| 13445 | OPC_CheckField, 28, 4, 0, // 48: check Inst[31:28] == 0x0 |
| 13446 | OPC_Decode, 172, 20, 249, 2, // 52: decode to SA1_tfr using decoder 377 |
| 13447 | // 52: } |
| 13448 | 1, 9, // 57: case 0x1: { |
| 13449 | OPC_CheckField, 28, 4, 0, // 59: check Inst[31:28] == 0x0 |
| 13450 | OPC_Decode, 167, 20, 249, 2, // 63: decode to SA1_inc using decoder 377 |
| 13451 | // 63: } |
| 13452 | 2, 9, // 68: case 0x2: { |
| 13453 | OPC_CheckField, 28, 4, 0, // 70: check Inst[31:28] == 0x0 |
| 13454 | OPC_Decode, 154, 20, 249, 2, // 74: decode to SA1_and1 using decoder 377 |
| 13455 | // 74: } |
| 13456 | 3, 9, // 79: case 0x3: { |
| 13457 | OPC_CheckField, 28, 4, 0, // 81: check Inst[31:28] == 0x0 |
| 13458 | OPC_Decode, 166, 20, 250, 2, // 85: decode to SA1_dec using decoder 378 |
| 13459 | // 85: } |
| 13460 | 4, 9, // 90: case 0x4: { |
| 13461 | OPC_CheckField, 28, 4, 0, // 92: check Inst[31:28] == 0x0 |
| 13462 | OPC_Decode, 171, 20, 249, 2, // 96: decode to SA1_sxth using decoder 377 |
| 13463 | // 96: } |
| 13464 | 5, 9, // 101: case 0x5: { |
| 13465 | OPC_CheckField, 28, 4, 0, // 103: check Inst[31:28] == 0x0 |
| 13466 | OPC_Decode, 170, 20, 249, 2, // 107: decode to SA1_sxtb using decoder 377 |
| 13467 | // 107: } |
| 13468 | 6, 9, // 112: case 0x6: { |
| 13469 | OPC_CheckField, 28, 4, 0, // 114: check Inst[31:28] == 0x0 |
| 13470 | OPC_Decode, 174, 20, 249, 2, // 118: decode to SA1_zxth using decoder 377 |
| 13471 | // 118: } |
| 13472 | 7, 0, // 123: case 0x7: { |
| 13473 | OPC_CheckField, 28, 4, 0, // 125: check Inst[31:28] == 0x0 |
| 13474 | OPC_Decode, 173, 20, 249, 2, // 129: decode to SA1_zxtb using decoder 377 |
| 13475 | // 129: } |
| 13476 | // 129: } // switch Inst[10:8] |
| 13477 | // 129: } |
| 13478 | 3, 0, // 134: case 0x3: { |
| 13479 | OPC_SwitchField, 8, 3, // 136: switch Inst[10:8] { |
| 13480 | 0, 9, // 139: case 0x0: { |
| 13481 | OPC_CheckField, 28, 4, 0, // 141: check Inst[31:28] == 0x0 |
| 13482 | OPC_Decode, 152, 20, 251, 2, // 145: decode to SA1_addrx using decoder 379 |
| 13483 | // 145: } |
| 13484 | 1, 13, // 150: case 0x1: { |
| 13485 | OPC_CheckField, 28, 4, 0, // 152: check Inst[31:28] == 0x0 |
| 13486 | OPC_CheckField, 2, 2, 0, // 156: check Inst[3:2] == 0x0 |
| 13487 | OPC_Decode, 159, 20, 252, 2, // 160: decode to SA1_cmpeqi using decoder 380 |
| 13488 | // 160: } |
| 13489 | 2, 58, // 165: case 0x2: { |
| 13490 | OPC_SwitchField, 4, 4, // 167: switch Inst[7:4] { |
| 13491 | 0, 9, // 170: case 0x0: { |
| 13492 | OPC_CheckField, 28, 4, 0, // 172: check Inst[31:28] == 0x0 |
| 13493 | OPC_Decode, 169, 20, 253, 2, // 176: decode to SA1_setin1 using decoder 381 |
| 13494 | // 176: } |
| 13495 | 4, 9, // 181: case 0x4: { |
| 13496 | OPC_CheckField, 28, 4, 0, // 183: check Inst[31:28] == 0x0 |
| 13497 | OPC_Decode, 158, 20, 254, 2, // 187: decode to SA1_clrtnew using decoder 382 |
| 13498 | // 187: } |
| 13499 | 5, 9, // 192: case 0x5: { |
| 13500 | OPC_CheckField, 28, 4, 0, // 194: check Inst[31:28] == 0x0 |
| 13501 | OPC_Decode, 156, 20, 254, 2, // 198: decode to SA1_clrfnew using decoder 382 |
| 13502 | // 198: } |
| 13503 | 6, 9, // 203: case 0x6: { |
| 13504 | OPC_CheckField, 28, 4, 0, // 205: check Inst[31:28] == 0x0 |
| 13505 | OPC_Decode, 157, 20, 254, 2, // 209: decode to SA1_clrt using decoder 382 |
| 13506 | // 209: } |
| 13507 | 7, 0, // 214: case 0x7: { |
| 13508 | OPC_CheckField, 28, 4, 0, // 216: check Inst[31:28] == 0x0 |
| 13509 | OPC_Decode, 155, 20, 254, 2, // 220: decode to SA1_clrf using decoder 382 |
| 13510 | // 220: } |
| 13511 | // 220: } // switch Inst[7:4] |
| 13512 | // 220: } |
| 13513 | 4, 63, // 225: case 0x4: { |
| 13514 | OPC_SwitchField, 3, 2, // 227: switch Inst[4:3] { |
| 13515 | 0, 13, // 230: case 0x0: { |
| 13516 | OPC_CheckField, 28, 4, 0, // 232: check Inst[31:28] == 0x0 |
| 13517 | OPC_CheckField, 7, 1, 0, // 236: check Inst[7] == 0x0 |
| 13518 | OPC_Decode, 160, 20, 255, 2, // 240: decode to SA1_combine0i using decoder 383 |
| 13519 | // 240: } |
| 13520 | 1, 13, // 245: case 0x1: { |
| 13521 | OPC_CheckField, 28, 4, 0, // 247: check Inst[31:28] == 0x0 |
| 13522 | OPC_CheckField, 7, 1, 0, // 251: check Inst[7] == 0x0 |
| 13523 | OPC_Decode, 161, 20, 255, 2, // 255: decode to SA1_combine1i using decoder 383 |
| 13524 | // 255: } |
| 13525 | 2, 13, // 260: case 0x2: { |
| 13526 | OPC_CheckField, 28, 4, 0, // 262: check Inst[31:28] == 0x0 |
| 13527 | OPC_CheckField, 7, 1, 0, // 266: check Inst[7] == 0x0 |
| 13528 | OPC_Decode, 162, 20, 255, 2, // 270: decode to SA1_combine2i using decoder 383 |
| 13529 | // 270: } |
| 13530 | 3, 0, // 275: case 0x3: { |
| 13531 | OPC_CheckField, 28, 4, 0, // 277: check Inst[31:28] == 0x0 |
| 13532 | OPC_CheckField, 7, 1, 0, // 281: check Inst[7] == 0x0 |
| 13533 | OPC_Decode, 163, 20, 255, 2, // 285: decode to SA1_combine3i using decoder 383 |
| 13534 | // 285: } |
| 13535 | // 285: } // switch Inst[4:3] |
| 13536 | // 285: } |
| 13537 | 5, 0, // 290: case 0x5: { |
| 13538 | OPC_SwitchField, 3, 1, // 292: switch Inst[3] { |
| 13539 | 0, 9, // 295: case 0x0: { |
| 13540 | OPC_CheckField, 28, 4, 0, // 297: check Inst[31:28] == 0x0 |
| 13541 | OPC_Decode, 165, 20, 128, 3, // 301: decode to SA1_combinezr using decoder 384 |
| 13542 | // 301: } |
| 13543 | 1, 0, // 306: case 0x1: { |
| 13544 | OPC_CheckField, 28, 4, 0, // 308: check Inst[31:28] == 0x0 |
| 13545 | OPC_Decode, 164, 20, 128, 3, // 312: decode to SA1_combinerz using decoder 384 |
| 13546 | // 312: } |
| 13547 | // 312: } // switch Inst[3] |
| 13548 | // 312: } |
| 13549 | // 312: } // switch Inst[10:8] |
| 13550 | // 312: } |
| 13551 | // 312: } // switch Inst[12:11] |
| 13552 | }; |
| 13553 | static const uint8_t DecoderTableSUBINSN_L132[25] = { |
| 13554 | OPC_SwitchField, 12, 1, // 0: switch Inst[12] { |
| 13555 | 0, 9, // 3: case 0x0: { |
| 13556 | OPC_CheckField, 28, 4, 0, // 5: check Inst[31:28] == 0x0 |
| 13557 | OPC_Decode, 183, 20, 129, 3, // 9: decode to SL1_loadri_io using decoder 385 |
| 13558 | // 9: } |
| 13559 | 1, 0, // 14: case 0x1: { |
| 13560 | OPC_CheckField, 28, 4, 0, // 16: check Inst[31:28] == 0x0 |
| 13561 | OPC_Decode, 184, 20, 130, 3, // 20: decode to SL1_loadrub_io using decoder 386 |
| 13562 | // 20: } |
| 13563 | // 20: } // switch Inst[12] |
| 13564 | }; |
| 13565 | static const uint8_t DecoderTableSUBINSN_L232[188] = { |
| 13566 | OPC_SwitchField, 11, 2, // 0: switch Inst[12:11] { |
| 13567 | 0, 9, // 3: case 0x0: { |
| 13568 | OPC_CheckField, 28, 4, 0, // 5: check Inst[31:28] == 0x0 |
| 13569 | OPC_Decode, 193, 20, 131, 3, // 9: decode to SL2_loadrh_io using decoder 387 |
| 13570 | // 9: } |
| 13571 | 1, 9, // 14: case 0x1: { |
| 13572 | OPC_CheckField, 28, 4, 0, // 16: check Inst[31:28] == 0x0 |
| 13573 | OPC_Decode, 195, 20, 131, 3, // 20: decode to SL2_loadruh_io using decoder 387 |
| 13574 | // 20: } |
| 13575 | 2, 9, // 25: case 0x2: { |
| 13576 | OPC_CheckField, 28, 4, 0, // 27: check Inst[31:28] == 0x0 |
| 13577 | OPC_Decode, 191, 20, 132, 3, // 31: decode to SL2_loadrb_io using decoder 388 |
| 13578 | // 31: } |
| 13579 | 3, 0, // 36: case 0x3: { |
| 13580 | OPC_SwitchField, 9, 2, // 38: switch Inst[10:9] { |
| 13581 | 2, 9, // 41: case 0x2: { |
| 13582 | OPC_CheckField, 28, 4, 0, // 43: check Inst[31:28] == 0x0 |
| 13583 | OPC_Decode, 194, 20, 133, 3, // 47: decode to SL2_loadri_sp using decoder 389 |
| 13584 | // 47: } |
| 13585 | 3, 0, // 52: case 0x3: { |
| 13586 | OPC_SwitchField, 8, 1, // 54: switch Inst[8] { |
| 13587 | 0, 9, // 57: case 0x0: { |
| 13588 | OPC_CheckField, 28, 4, 0, // 59: check Inst[31:28] == 0x0 |
| 13589 | OPC_Decode, 192, 20, 134, 3, // 63: decode to SL2_loadrd_sp using decoder 390 |
| 13590 | // 63: } |
| 13591 | 1, 0, // 68: case 0x1: { |
| 13592 | OPC_SwitchField, 0, 8, // 70: switch Inst[7:0] { |
| 13593 | 0, 8, // 73: case 0x0: { |
| 13594 | OPC_CheckField, 28, 4, 0, // 75: check Inst[31:28] == 0x0 |
| 13595 | OPC_Decode, 185, 20, 63, // 79: decode to SL2_deallocframe using decoder 63 |
| 13596 | // 79: } |
| 13597 | 64, 8, // 83: case 0x40: { |
| 13598 | OPC_CheckField, 28, 4, 0, // 85: check Inst[31:28] == 0x0 |
| 13599 | OPC_Decode, 196, 20, 63, // 89: decode to SL2_return using decoder 63 |
| 13600 | // 89: } |
| 13601 | 68, 8, // 93: case 0x44: { |
| 13602 | OPC_CheckField, 28, 4, 0, // 95: check Inst[31:28] == 0x0 |
| 13603 | OPC_Decode, 199, 20, 63, // 99: decode to SL2_return_t using decoder 63 |
| 13604 | // 99: } |
| 13605 | 69, 8, // 103: case 0x45: { |
| 13606 | OPC_CheckField, 28, 4, 0, // 105: check Inst[31:28] == 0x0 |
| 13607 | OPC_Decode, 197, 20, 63, // 109: decode to SL2_return_f using decoder 63 |
| 13608 | // 109: } |
| 13609 | 70, 8, // 113: case 0x46: { |
| 13610 | OPC_CheckField, 28, 4, 0, // 115: check Inst[31:28] == 0x0 |
| 13611 | OPC_Decode, 200, 20, 63, // 119: decode to SL2_return_tnew using decoder 63 |
| 13612 | // 119: } |
| 13613 | 71, 8, // 123: case 0x47: { |
| 13614 | OPC_CheckField, 28, 4, 0, // 125: check Inst[31:28] == 0x0 |
| 13615 | OPC_Decode, 198, 20, 63, // 129: decode to SL2_return_fnew using decoder 63 |
| 13616 | // 129: } |
| 13617 | 192, 1, 8, // 133: case 0xc0: { |
| 13618 | OPC_CheckField, 28, 4, 0, // 136: check Inst[31:28] == 0x0 |
| 13619 | OPC_Decode, 186, 20, 63, // 140: decode to SL2_jumpr31 using decoder 63 |
| 13620 | // 140: } |
| 13621 | 196, 1, 8, // 144: case 0xc4: { |
| 13622 | OPC_CheckField, 28, 4, 0, // 147: check Inst[31:28] == 0x0 |
| 13623 | OPC_Decode, 189, 20, 63, // 151: decode to SL2_jumpr31_t using decoder 63 |
| 13624 | // 151: } |
| 13625 | 197, 1, 8, // 155: case 0xc5: { |
| 13626 | OPC_CheckField, 28, 4, 0, // 158: check Inst[31:28] == 0x0 |
| 13627 | OPC_Decode, 187, 20, 63, // 162: decode to SL2_jumpr31_f using decoder 63 |
| 13628 | // 162: } |
| 13629 | 198, 1, 8, // 166: case 0xc6: { |
| 13630 | OPC_CheckField, 28, 4, 0, // 169: check Inst[31:28] == 0x0 |
| 13631 | OPC_Decode, 190, 20, 63, // 173: decode to SL2_jumpr31_tnew using decoder 63 |
| 13632 | // 173: } |
| 13633 | 199, 1, 0, // 177: case 0xc7: { |
| 13634 | OPC_CheckField, 28, 4, 0, // 180: check Inst[31:28] == 0x0 |
| 13635 | OPC_Decode, 188, 20, 63, // 184: decode to SL2_jumpr31_fnew using decoder 63 |
| 13636 | // 184: } |
| 13637 | // 184: } // switch Inst[7:0] |
| 13638 | // 184: } |
| 13639 | // 184: } // switch Inst[8] |
| 13640 | // 184: } |
| 13641 | // 184: } // switch Inst[10:9] |
| 13642 | // 184: } |
| 13643 | // 184: } // switch Inst[12:11] |
| 13644 | }; |
| 13645 | static const uint8_t DecoderTableSUBINSN_S132[25] = { |
| 13646 | OPC_SwitchField, 12, 1, // 0: switch Inst[12] { |
| 13647 | 0, 9, // 3: case 0x0: { |
| 13648 | OPC_CheckField, 28, 4, 0, // 5: check Inst[31:28] == 0x0 |
| 13649 | OPC_Decode, 202, 20, 135, 3, // 9: decode to SS1_storew_io using decoder 391 |
| 13650 | // 9: } |
| 13651 | 1, 0, // 14: case 0x1: { |
| 13652 | OPC_CheckField, 28, 4, 0, // 16: check Inst[31:28] == 0x0 |
| 13653 | OPC_Decode, 201, 20, 136, 3, // 20: decode to SS1_storeb_io using decoder 392 |
| 13654 | // 20: } |
| 13655 | // 20: } // switch Inst[12] |
| 13656 | }; |
| 13657 | static const uint8_t DecoderTableSUBINSN_S232[109] = { |
| 13658 | OPC_SwitchField, 11, 2, // 0: switch Inst[12:11] { |
| 13659 | 0, 9, // 3: case 0x0: { |
| 13660 | OPC_CheckField, 28, 4, 0, // 5: check Inst[31:28] == 0x0 |
| 13661 | OPC_Decode, 207, 20, 137, 3, // 9: decode to SS2_storeh_io using decoder 393 |
| 13662 | // 9: } |
| 13663 | 1, 25, // 14: case 0x1: { |
| 13664 | OPC_SwitchField, 9, 2, // 16: switch Inst[10:9] { |
| 13665 | 0, 9, // 19: case 0x0: { |
| 13666 | OPC_CheckField, 28, 4, 0, // 21: check Inst[31:28] == 0x0 |
| 13667 | OPC_Decode, 208, 20, 138, 3, // 25: decode to SS2_storew_sp using decoder 394 |
| 13668 | // 25: } |
| 13669 | 1, 0, // 30: case 0x1: { |
| 13670 | OPC_CheckField, 28, 4, 0, // 32: check Inst[31:28] == 0x0 |
| 13671 | OPC_Decode, 206, 20, 139, 3, // 36: decode to SS2_stored_sp using decoder 395 |
| 13672 | // 36: } |
| 13673 | // 36: } // switch Inst[10:9] |
| 13674 | // 36: } |
| 13675 | 2, 47, // 41: case 0x2: { |
| 13676 | OPC_SwitchField, 8, 3, // 43: switch Inst[10:8] { |
| 13677 | 0, 9, // 46: case 0x0: { |
| 13678 | OPC_CheckField, 28, 4, 0, // 48: check Inst[31:28] == 0x0 |
| 13679 | OPC_Decode, 209, 20, 140, 3, // 52: decode to SS2_storewi0 using decoder 396 |
| 13680 | // 52: } |
| 13681 | 1, 9, // 57: case 0x1: { |
| 13682 | OPC_CheckField, 28, 4, 0, // 59: check Inst[31:28] == 0x0 |
| 13683 | OPC_Decode, 210, 20, 140, 3, // 63: decode to SS2_storewi1 using decoder 396 |
| 13684 | // 63: } |
| 13685 | 2, 9, // 68: case 0x2: { |
| 13686 | OPC_CheckField, 28, 4, 0, // 70: check Inst[31:28] == 0x0 |
| 13687 | OPC_Decode, 204, 20, 141, 3, // 74: decode to SS2_storebi0 using decoder 397 |
| 13688 | // 74: } |
| 13689 | 3, 0, // 79: case 0x3: { |
| 13690 | OPC_CheckField, 28, 4, 0, // 81: check Inst[31:28] == 0x0 |
| 13691 | OPC_Decode, 205, 20, 141, 3, // 85: decode to SS2_storebi1 using decoder 397 |
| 13692 | // 85: } |
| 13693 | // 85: } // switch Inst[10:8] |
| 13694 | // 85: } |
| 13695 | 3, 0, // 90: case 0x3: { |
| 13696 | OPC_CheckField, 28, 4, 0, // 92: check Inst[31:28] == 0x0 |
| 13697 | OPC_CheckField, 9, 2, 2, // 96: check Inst[10:9] == 0x2 |
| 13698 | OPC_CheckField, 0, 4, 0, // 100: check Inst[3:0] == 0x0 |
| 13699 | OPC_Decode, 203, 20, 142, 3, // 104: decode to SS2_allocframe using decoder 398 |
| 13700 | // 104: } |
| 13701 | // 104: } // switch Inst[12:11] |
| 13702 | }; |
| 13703 | // Handling 399 cases. |
| 13704 | template <typename InsnType> |
| 13705 | static DecodeStatus decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) { |
| 13706 | DecodeComplete = true; |
| 13707 | using TmpType = std::conditional_t<std::is_integral<InsnType>::value, InsnType, uint64_t>; |
| 13708 | TmpType tmp; |
| 13709 | switch (Idx) { |
| 13710 | default: llvm_unreachable("Invalid decoder index!"); |
| 13711 | case 0: |
| 13712 | tmp = 0x0; |
| 13713 | tmp |= fieldFromInstruction(insn, 0, 14) << 6; |
| 13714 | tmp |= fieldFromInstruction(insn, 16, 12) << 20; |
| 13715 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13716 | return S; |
| 13717 | case 1: |
| 13718 | tmp = fieldFromInstruction(insn, 16, 4); |
| 13719 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13720 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13721 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13722 | tmp = 0x0; |
| 13723 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13724 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13725 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13726 | return S; |
| 13727 | case 2: |
| 13728 | tmp = fieldFromInstruction(insn, 16, 4); |
| 13729 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13730 | if (!Check(Out&: S, In: n1ConstDecoder(MI, Decoder))) |
| 13731 | return MCDisassembler::Fail; |
| 13732 | tmp = 0x0; |
| 13733 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13734 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13735 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13736 | return S; |
| 13737 | case 3: |
| 13738 | tmp = fieldFromInstruction(insn, 16, 4); |
| 13739 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13740 | tmp = 0x0; |
| 13741 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13742 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13743 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13744 | return S; |
| 13745 | case 4: |
| 13746 | tmp = fieldFromInstruction(insn, 16, 4); |
| 13747 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13748 | tmp = fieldFromInstruction(insn, 8, 4); |
| 13749 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13750 | tmp = 0x0; |
| 13751 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13752 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13753 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13754 | return S; |
| 13755 | case 5: |
| 13756 | tmp = fieldFromInstruction(insn, 16, 4); |
| 13757 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13758 | tmp = fieldFromInstruction(insn, 8, 6); |
| 13759 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13760 | tmp = 0x0; |
| 13761 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13762 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13763 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13764 | return S; |
| 13765 | case 6: |
| 13766 | tmp = fieldFromInstruction(insn, 8, 4); |
| 13767 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13768 | tmp = fieldFromInstruction(insn, 16, 4); |
| 13769 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13770 | tmp = 0x0; |
| 13771 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13772 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13773 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13774 | return S; |
| 13775 | case 7: |
| 13776 | tmp = fieldFromInstruction(insn, 16, 3); |
| 13777 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13778 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13779 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13780 | tmp = 0x0; |
| 13781 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13782 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13783 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13784 | return S; |
| 13785 | case 8: |
| 13786 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13787 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13788 | tmp = fieldFromInstruction(insn, 16, 3); |
| 13789 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13790 | tmp = 0x0; |
| 13791 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13792 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13793 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13794 | return S; |
| 13795 | case 9: |
| 13796 | tmp = fieldFromInstruction(insn, 16, 3); |
| 13797 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13798 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13799 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13800 | tmp = 0x0; |
| 13801 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13802 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13803 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13804 | return S; |
| 13805 | case 10: |
| 13806 | tmp = fieldFromInstruction(insn, 16, 3); |
| 13807 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13808 | tmp = 0x0; |
| 13809 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13810 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13811 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13812 | return S; |
| 13813 | case 11: |
| 13814 | tmp = fieldFromInstruction(insn, 16, 3); |
| 13815 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13816 | if (!Check(Out&: S, In: n1ConstDecoder(MI, Decoder))) |
| 13817 | return MCDisassembler::Fail; |
| 13818 | tmp = 0x0; |
| 13819 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 13820 | tmp |= fieldFromInstruction(insn, 20, 2) << 9; |
| 13821 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13822 | return S; |
| 13823 | case 12: |
| 13824 | tmp = fieldFromInstruction(insn, 0, 5); |
| 13825 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13826 | tmp = fieldFromInstruction(insn, 5, 2); |
| 13827 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13828 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13829 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13830 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13831 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13832 | tmp = 0x0; |
| 13833 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13834 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13835 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13836 | return S; |
| 13837 | case 13: |
| 13838 | tmp = fieldFromInstruction(insn, 0, 5); |
| 13839 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13840 | tmp = fieldFromInstruction(insn, 5, 2); |
| 13841 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13842 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13843 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13844 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13845 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13846 | tmp = 0x0; |
| 13847 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13848 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13849 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13850 | return S; |
| 13851 | case 14: |
| 13852 | tmp = fieldFromInstruction(insn, 5, 2); |
| 13853 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13854 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13855 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13856 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13857 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13858 | tmp = 0x0; |
| 13859 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13860 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13861 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13862 | tmp = fieldFromInstruction(insn, 0, 5); |
| 13863 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13864 | return S; |
| 13865 | case 15: |
| 13866 | tmp = fieldFromInstruction(insn, 5, 2); |
| 13867 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13868 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13869 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13870 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13871 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13872 | tmp = 0x0; |
| 13873 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13874 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13875 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13876 | tmp = fieldFromInstruction(insn, 0, 3); |
| 13877 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13878 | return S; |
| 13879 | case 16: |
| 13880 | tmp = fieldFromInstruction(insn, 5, 2); |
| 13881 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13882 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13883 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13884 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13885 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13886 | tmp = 0x0; |
| 13887 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13888 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13889 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13890 | tmp = fieldFromInstruction(insn, 0, 5); |
| 13891 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13892 | return S; |
| 13893 | case 17: |
| 13894 | tmp = fieldFromInstruction(insn, 5, 2); |
| 13895 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13896 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13897 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13898 | tmp = fieldFromInstruction(insn, 7, 6); |
| 13899 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13900 | tmp = 0x0; |
| 13901 | tmp |= fieldFromInstruction(insn, 0, 5); |
| 13902 | tmp |= fieldFromInstruction(insn, 13, 1) << 5; |
| 13903 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13904 | return S; |
| 13905 | case 18: |
| 13906 | tmp = fieldFromInstruction(insn, 5, 2); |
| 13907 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13908 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13909 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13910 | tmp = fieldFromInstruction(insn, 7, 6) << 1; |
| 13911 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13912 | tmp = 0x0; |
| 13913 | tmp |= fieldFromInstruction(insn, 0, 5); |
| 13914 | tmp |= fieldFromInstruction(insn, 13, 1) << 5; |
| 13915 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13916 | return S; |
| 13917 | case 19: |
| 13918 | tmp = fieldFromInstruction(insn, 5, 2); |
| 13919 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13920 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13921 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13922 | tmp = fieldFromInstruction(insn, 7, 6) << 2; |
| 13923 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13924 | tmp = 0x0; |
| 13925 | tmp |= fieldFromInstruction(insn, 0, 5); |
| 13926 | tmp |= fieldFromInstruction(insn, 13, 1) << 5; |
| 13927 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13928 | return S; |
| 13929 | case 20: |
| 13930 | tmp = fieldFromInstruction(insn, 0, 5); |
| 13931 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13932 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13933 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13934 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13935 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13936 | tmp = 0x0; |
| 13937 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13938 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13939 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13940 | return S; |
| 13941 | case 21: |
| 13942 | tmp = fieldFromInstruction(insn, 0, 5); |
| 13943 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13944 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13945 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13946 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13947 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13948 | tmp = 0x0; |
| 13949 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13950 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13951 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13952 | return S; |
| 13953 | case 22: |
| 13954 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13955 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13956 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13957 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13958 | tmp = 0x0; |
| 13959 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13960 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13961 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13962 | tmp = fieldFromInstruction(insn, 0, 5); |
| 13963 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13964 | return S; |
| 13965 | case 23: |
| 13966 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13967 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13968 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13969 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13970 | tmp = 0x0; |
| 13971 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13972 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13973 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13974 | tmp = fieldFromInstruction(insn, 0, 3); |
| 13975 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13976 | return S; |
| 13977 | case 24: |
| 13978 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13979 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13980 | tmp = fieldFromInstruction(insn, 8, 5); |
| 13981 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13982 | tmp = 0x0; |
| 13983 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 13984 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 13985 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13986 | tmp = fieldFromInstruction(insn, 0, 5); |
| 13987 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13988 | return S; |
| 13989 | case 25: |
| 13990 | tmp = fieldFromInstruction(insn, 16, 5); |
| 13991 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13992 | tmp = fieldFromInstruction(insn, 7, 6); |
| 13993 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13994 | tmp = 0x0; |
| 13995 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 13996 | tmp |= fieldFromInstruction(insn, 13, 1) << 7; |
| 13997 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 13998 | return S; |
| 13999 | case 26: |
| 14000 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14001 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14002 | tmp = fieldFromInstruction(insn, 7, 6) << 1; |
| 14003 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14004 | tmp = 0x0; |
| 14005 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 14006 | tmp |= fieldFromInstruction(insn, 13, 1) << 7; |
| 14007 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14008 | return S; |
| 14009 | case 27: |
| 14010 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14011 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14012 | tmp = fieldFromInstruction(insn, 7, 6) << 2; |
| 14013 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14014 | tmp = 0x0; |
| 14015 | tmp |= fieldFromInstruction(insn, 0, 7); |
| 14016 | tmp |= fieldFromInstruction(insn, 13, 1) << 7; |
| 14017 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14018 | return S; |
| 14019 | case 28: |
| 14020 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14021 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14022 | tmp = fieldFromInstruction(insn, 7, 6); |
| 14023 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14024 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14025 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14026 | return S; |
| 14027 | case 29: |
| 14028 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14029 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14030 | tmp = fieldFromInstruction(insn, 7, 6) << 1; |
| 14031 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14032 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14033 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14034 | return S; |
| 14035 | case 30: |
| 14036 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14037 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14038 | tmp = fieldFromInstruction(insn, 7, 6) << 2; |
| 14039 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14040 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14041 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14042 | return S; |
| 14043 | case 31: |
| 14044 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14045 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14046 | tmp = fieldFromInstruction(insn, 7, 6); |
| 14047 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14048 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14049 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14050 | return S; |
| 14051 | case 32: |
| 14052 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14053 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14054 | tmp = fieldFromInstruction(insn, 7, 6) << 1; |
| 14055 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14056 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14057 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14058 | return S; |
| 14059 | case 33: |
| 14060 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14061 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14062 | tmp = fieldFromInstruction(insn, 7, 6) << 2; |
| 14063 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14064 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14065 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14066 | return S; |
| 14067 | case 34: |
| 14068 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14069 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14070 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14071 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14072 | tmp = 0x0; |
| 14073 | tmp |= fieldFromInstruction(insn, 3, 5); |
| 14074 | tmp |= fieldFromInstruction(insn, 13, 1) << 5; |
| 14075 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14076 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14077 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14078 | return S; |
| 14079 | case 35: |
| 14080 | tmp = 0x0; |
| 14081 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 14082 | tmp |= fieldFromInstruction(insn, 13, 1) << 8; |
| 14083 | tmp |= fieldFromInstruction(insn, 16, 5) << 9; |
| 14084 | tmp |= fieldFromInstruction(insn, 25, 2) << 14; |
| 14085 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14086 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14087 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14088 | return S; |
| 14089 | case 36: |
| 14090 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14091 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14092 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14093 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14094 | tmp = 0x0; |
| 14095 | tmp |= fieldFromInstruction(insn, 3, 5) << 1; |
| 14096 | tmp |= fieldFromInstruction(insn, 13, 1) << 6; |
| 14097 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14098 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14099 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14100 | return S; |
| 14101 | case 37: |
| 14102 | tmp = 0x0; |
| 14103 | tmp |= fieldFromInstruction(insn, 0, 8) << 1; |
| 14104 | tmp |= fieldFromInstruction(insn, 13, 1) << 9; |
| 14105 | tmp |= fieldFromInstruction(insn, 16, 5) << 10; |
| 14106 | tmp |= fieldFromInstruction(insn, 25, 2) << 15; |
| 14107 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14108 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14109 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14110 | return S; |
| 14111 | case 38: |
| 14112 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14113 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14114 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14115 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14116 | tmp = 0x0; |
| 14117 | tmp |= fieldFromInstruction(insn, 3, 5) << 2; |
| 14118 | tmp |= fieldFromInstruction(insn, 13, 1) << 7; |
| 14119 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14120 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14121 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14122 | return S; |
| 14123 | case 39: |
| 14124 | tmp = 0x0; |
| 14125 | tmp |= fieldFromInstruction(insn, 0, 8) << 2; |
| 14126 | tmp |= fieldFromInstruction(insn, 13, 1) << 10; |
| 14127 | tmp |= fieldFromInstruction(insn, 16, 5) << 11; |
| 14128 | tmp |= fieldFromInstruction(insn, 25, 2) << 16; |
| 14129 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14130 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14131 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14132 | return S; |
| 14133 | case 40: |
| 14134 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14135 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14136 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14137 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14138 | tmp = 0x0; |
| 14139 | tmp |= fieldFromInstruction(insn, 3, 5); |
| 14140 | tmp |= fieldFromInstruction(insn, 13, 1) << 5; |
| 14141 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14142 | tmp = fieldFromInstruction(insn, 8, 3); |
| 14143 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14144 | return S; |
| 14145 | case 41: |
| 14146 | tmp = 0x0; |
| 14147 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 14148 | tmp |= fieldFromInstruction(insn, 13, 1) << 8; |
| 14149 | tmp |= fieldFromInstruction(insn, 16, 5) << 9; |
| 14150 | tmp |= fieldFromInstruction(insn, 25, 2) << 14; |
| 14151 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14152 | tmp = fieldFromInstruction(insn, 8, 3); |
| 14153 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14154 | return S; |
| 14155 | case 42: |
| 14156 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14157 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14158 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14159 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14160 | tmp = 0x0; |
| 14161 | tmp |= fieldFromInstruction(insn, 3, 5) << 1; |
| 14162 | tmp |= fieldFromInstruction(insn, 13, 1) << 6; |
| 14163 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14164 | tmp = fieldFromInstruction(insn, 8, 3); |
| 14165 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14166 | return S; |
| 14167 | case 43: |
| 14168 | tmp = 0x0; |
| 14169 | tmp |= fieldFromInstruction(insn, 0, 8) << 1; |
| 14170 | tmp |= fieldFromInstruction(insn, 13, 1) << 9; |
| 14171 | tmp |= fieldFromInstruction(insn, 16, 5) << 10; |
| 14172 | tmp |= fieldFromInstruction(insn, 25, 2) << 15; |
| 14173 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14174 | tmp = fieldFromInstruction(insn, 8, 3); |
| 14175 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14176 | return S; |
| 14177 | case 44: |
| 14178 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14179 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14180 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14181 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14182 | tmp = 0x0; |
| 14183 | tmp |= fieldFromInstruction(insn, 3, 5) << 2; |
| 14184 | tmp |= fieldFromInstruction(insn, 13, 1) << 7; |
| 14185 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14186 | tmp = fieldFromInstruction(insn, 8, 3); |
| 14187 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14188 | return S; |
| 14189 | case 45: |
| 14190 | tmp = 0x0; |
| 14191 | tmp |= fieldFromInstruction(insn, 0, 8) << 2; |
| 14192 | tmp |= fieldFromInstruction(insn, 13, 1) << 10; |
| 14193 | tmp |= fieldFromInstruction(insn, 16, 5) << 11; |
| 14194 | tmp |= fieldFromInstruction(insn, 25, 2) << 16; |
| 14195 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14196 | tmp = fieldFromInstruction(insn, 8, 3); |
| 14197 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14198 | return S; |
| 14199 | case 46: |
| 14200 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14201 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14202 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14203 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14204 | tmp = 0x0; |
| 14205 | tmp |= fieldFromInstruction(insn, 3, 5) << 3; |
| 14206 | tmp |= fieldFromInstruction(insn, 13, 1) << 8; |
| 14207 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14208 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14209 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14210 | return S; |
| 14211 | case 47: |
| 14212 | tmp = 0x0; |
| 14213 | tmp |= fieldFromInstruction(insn, 0, 8) << 3; |
| 14214 | tmp |= fieldFromInstruction(insn, 13, 1) << 11; |
| 14215 | tmp |= fieldFromInstruction(insn, 16, 5) << 12; |
| 14216 | tmp |= fieldFromInstruction(insn, 25, 2) << 17; |
| 14217 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14218 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14219 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14220 | return S; |
| 14221 | case 48: |
| 14222 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14223 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14224 | tmp = fieldFromInstruction(insn, 11, 2); |
| 14225 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14226 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14227 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14228 | tmp = fieldFromInstruction(insn, 5, 6); |
| 14229 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14230 | return S; |
| 14231 | case 49: |
| 14232 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14233 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14234 | tmp = 0x0; |
| 14235 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 14236 | tmp |= fieldFromInstruction(insn, 16, 5) << 9; |
| 14237 | tmp |= fieldFromInstruction(insn, 25, 2) << 14; |
| 14238 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14239 | return S; |
| 14240 | case 50: |
| 14241 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14242 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14243 | tmp = fieldFromInstruction(insn, 11, 2); |
| 14244 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14245 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14246 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14247 | tmp = fieldFromInstruction(insn, 5, 6) << 1; |
| 14248 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14249 | return S; |
| 14250 | case 51: |
| 14251 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14252 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14253 | tmp = 0x0; |
| 14254 | tmp |= fieldFromInstruction(insn, 5, 9) << 1; |
| 14255 | tmp |= fieldFromInstruction(insn, 16, 5) << 10; |
| 14256 | tmp |= fieldFromInstruction(insn, 25, 2) << 15; |
| 14257 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14258 | return S; |
| 14259 | case 52: |
| 14260 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14261 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14262 | tmp = fieldFromInstruction(insn, 11, 2); |
| 14263 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14264 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14265 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14266 | tmp = fieldFromInstruction(insn, 5, 6) << 2; |
| 14267 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14268 | return S; |
| 14269 | case 53: |
| 14270 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14271 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14272 | tmp = 0x0; |
| 14273 | tmp |= fieldFromInstruction(insn, 5, 9) << 2; |
| 14274 | tmp |= fieldFromInstruction(insn, 16, 5) << 11; |
| 14275 | tmp |= fieldFromInstruction(insn, 25, 2) << 16; |
| 14276 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14277 | return S; |
| 14278 | case 54: |
| 14279 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14280 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14281 | tmp = fieldFromInstruction(insn, 11, 2); |
| 14282 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14283 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14284 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14285 | tmp = fieldFromInstruction(insn, 5, 6) << 3; |
| 14286 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14287 | return S; |
| 14288 | case 55: |
| 14289 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14290 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14291 | tmp = 0x0; |
| 14292 | tmp |= fieldFromInstruction(insn, 5, 9) << 3; |
| 14293 | tmp |= fieldFromInstruction(insn, 16, 5) << 12; |
| 14294 | tmp |= fieldFromInstruction(insn, 25, 2) << 17; |
| 14295 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14296 | return S; |
| 14297 | case 56: |
| 14298 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14299 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14300 | return S; |
| 14301 | case 57: |
| 14302 | tmp = fieldFromInstruction(insn, 8, 2); |
| 14303 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14304 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14305 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14306 | return S; |
| 14307 | case 58: |
| 14308 | tmp = 0x0; |
| 14309 | tmp |= fieldFromInstruction(insn, 2, 3); |
| 14310 | tmp |= fieldFromInstruction(insn, 8, 5) << 3; |
| 14311 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14312 | return S; |
| 14313 | case 59: |
| 14314 | tmp = 0x0; |
| 14315 | tmp |= fieldFromInstruction(insn, 2, 3); |
| 14316 | tmp |= fieldFromInstruction(insn, 8, 5) << 3; |
| 14317 | tmp |= fieldFromInstruction(insn, 16, 2) << 8; |
| 14318 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14319 | return S; |
| 14320 | case 60: |
| 14321 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14322 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14323 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14324 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14325 | tmp = 0x0; |
| 14326 | tmp |= fieldFromInstruction(insn, 2, 3); |
| 14327 | tmp |= fieldFromInstruction(insn, 8, 5) << 3; |
| 14328 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14329 | return S; |
| 14330 | case 61: |
| 14331 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14332 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14333 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14334 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14335 | return S; |
| 14336 | case 62: |
| 14337 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14338 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14339 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14340 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14341 | return S; |
| 14342 | case 63: |
| 14343 | return S; |
| 14344 | case 64: |
| 14345 | tmp = 0x0; |
| 14346 | tmp |= fieldFromInstruction(insn, 1, 13) << 2; |
| 14347 | tmp |= fieldFromInstruction(insn, 16, 9) << 15; |
| 14348 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14349 | return S; |
| 14350 | case 65: |
| 14351 | tmp = fieldFromInstruction(insn, 8, 2); |
| 14352 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14353 | tmp = 0x0; |
| 14354 | tmp |= fieldFromInstruction(insn, 1, 7) << 2; |
| 14355 | tmp |= fieldFromInstruction(insn, 13, 1) << 9; |
| 14356 | tmp |= fieldFromInstruction(insn, 16, 5) << 10; |
| 14357 | tmp |= fieldFromInstruction(insn, 22, 2) << 15; |
| 14358 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14359 | return S; |
| 14360 | case 66: |
| 14361 | tmp = 0x0; |
| 14362 | tmp |= fieldFromInstruction(insn, 3, 2) << 2; |
| 14363 | tmp |= fieldFromInstruction(insn, 8, 5) << 4; |
| 14364 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14365 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14366 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14367 | return S; |
| 14368 | case 67: |
| 14369 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14370 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14371 | tmp = 0x0; |
| 14372 | tmp |= fieldFromInstruction(insn, 1, 11) << 2; |
| 14373 | tmp |= fieldFromInstruction(insn, 13, 1) << 13; |
| 14374 | tmp |= fieldFromInstruction(insn, 21, 1) << 14; |
| 14375 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14376 | return S; |
| 14377 | case 68: |
| 14378 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14379 | if (!Check(S, DecodeGuestRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14380 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14381 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14382 | return S; |
| 14383 | case 69: |
| 14384 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14385 | if (!Check(S, DecodeCtrRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14386 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14387 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14388 | return S; |
| 14389 | case 70: |
| 14390 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14391 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14392 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14393 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14394 | return S; |
| 14395 | case 71: |
| 14396 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14397 | if (!Check(S, DecodeGuestRegs64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14398 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14399 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14400 | return S; |
| 14401 | case 72: |
| 14402 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14403 | if (!Check(S, DecodeCtrRegs64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14404 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14405 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14406 | return S; |
| 14407 | case 73: |
| 14408 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14409 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14410 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14411 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14412 | return S; |
| 14413 | case 74: |
| 14414 | tmp = fieldFromInstruction(insn, 0, 7); |
| 14415 | if (!Check(S, DecodeSysRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14416 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14417 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14418 | return S; |
| 14419 | case 75: |
| 14420 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14421 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14422 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14423 | if (!Check(S, DecodeCtrRegs64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14424 | return S; |
| 14425 | case 76: |
| 14426 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14427 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14428 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14429 | if (!Check(S, DecodeGuestRegs64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14430 | return S; |
| 14431 | case 77: |
| 14432 | tmp = 0x0; |
| 14433 | tmp |= fieldFromInstruction(insn, 3, 2) << 2; |
| 14434 | tmp |= fieldFromInstruction(insn, 8, 5) << 4; |
| 14435 | if (!Check(S, brtargetDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14436 | tmp = 0x0; |
| 14437 | tmp |= fieldFromInstruction(insn, 0, 2); |
| 14438 | tmp |= fieldFromInstruction(insn, 5, 3) << 2; |
| 14439 | tmp |= fieldFromInstruction(insn, 16, 5) << 5; |
| 14440 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14441 | return S; |
| 14442 | case 78: |
| 14443 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14444 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14445 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14446 | if (!Check(S, DecodeCtrRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14447 | return S; |
| 14448 | case 79: |
| 14449 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14450 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14451 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14452 | if (!Check(S, DecodeGuestRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14453 | return S; |
| 14454 | case 80: |
| 14455 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14456 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14457 | tmp = fieldFromInstruction(insn, 7, 6); |
| 14458 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14459 | return S; |
| 14460 | case 81: |
| 14461 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14462 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14463 | tmp = fieldFromInstruction(insn, 8, 2); |
| 14464 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14465 | tmp = fieldFromInstruction(insn, 16, 2); |
| 14466 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14467 | return S; |
| 14468 | case 82: |
| 14469 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14470 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14471 | tmp = fieldFromInstruction(insn, 16, 2); |
| 14472 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14473 | tmp = fieldFromInstruction(insn, 8, 2); |
| 14474 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14475 | return S; |
| 14476 | case 83: |
| 14477 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14478 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14479 | tmp = fieldFromInstruction(insn, 16, 2); |
| 14480 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14481 | tmp = fieldFromInstruction(insn, 8, 2); |
| 14482 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14483 | tmp = fieldFromInstruction(insn, 6, 2); |
| 14484 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14485 | return S; |
| 14486 | case 84: |
| 14487 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14488 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14489 | tmp = fieldFromInstruction(insn, 16, 2); |
| 14490 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14491 | return S; |
| 14492 | case 85: |
| 14493 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14494 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14495 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14496 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14497 | return S; |
| 14498 | case 86: |
| 14499 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14500 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14501 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14502 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14503 | return S; |
| 14504 | case 87: |
| 14505 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14506 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14507 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14508 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14509 | return S; |
| 14510 | case 88: |
| 14511 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14512 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14513 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14514 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14515 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14516 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14517 | return S; |
| 14518 | case 89: |
| 14519 | tmp = fieldFromInstruction(insn, 0, 7); |
| 14520 | if (!Check(S, DecodeSysRegs64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14521 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14522 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14523 | return S; |
| 14524 | case 90: |
| 14525 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14526 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14527 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14528 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14529 | if (!Check(Out&: S, In: sgp10ConstDecoder(MI, Decoder))) |
| 14530 | return MCDisassembler::Fail; |
| 14531 | return S; |
| 14532 | case 91: |
| 14533 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14534 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14535 | tmp = fieldFromInstruction(insn, 16, 7); |
| 14536 | if (!Check(S, DecodeSysRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14537 | return S; |
| 14538 | case 92: |
| 14539 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14540 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14541 | tmp = fieldFromInstruction(insn, 16, 7); |
| 14542 | if (!Check(S, DecodeSysRegs64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14543 | return S; |
| 14544 | case 93: |
| 14545 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14546 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14547 | tmp = fieldFromInstruction(insn, 8, 2); |
| 14548 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14549 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14550 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14551 | return S; |
| 14552 | case 94: |
| 14553 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14554 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14555 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14556 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14557 | tmp = 0x0; |
| 14558 | tmp |= fieldFromInstruction(insn, 0, 14); |
| 14559 | tmp |= fieldFromInstruction(insn, 22, 2) << 14; |
| 14560 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14561 | return S; |
| 14562 | case 95: |
| 14563 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14564 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14565 | tmp = fieldFromInstruction(insn, 21, 2); |
| 14566 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14567 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14568 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14569 | tmp = fieldFromInstruction(insn, 5, 8); |
| 14570 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14571 | return S; |
| 14572 | case 96: |
| 14573 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14574 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14575 | tmp = fieldFromInstruction(insn, 21, 2); |
| 14576 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14577 | tmp = fieldFromInstruction(insn, 5, 8); |
| 14578 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14579 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14580 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14581 | return S; |
| 14582 | case 97: |
| 14583 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14584 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14585 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14586 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14587 | tmp = fieldFromInstruction(insn, 5, 8); |
| 14588 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14589 | return S; |
| 14590 | case 98: |
| 14591 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14592 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14593 | tmp = fieldFromInstruction(insn, 5, 8); |
| 14594 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14595 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14596 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14597 | return S; |
| 14598 | case 99: |
| 14599 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14600 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14601 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14602 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14603 | tmp = fieldFromInstruction(insn, 5, 8); |
| 14604 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14605 | return S; |
| 14606 | case 100: |
| 14607 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14608 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14609 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14610 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14611 | tmp = 0x0; |
| 14612 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 14613 | tmp |= fieldFromInstruction(insn, 21, 1) << 9; |
| 14614 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14615 | return S; |
| 14616 | case 101: |
| 14617 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14618 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14619 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14620 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14621 | tmp = fieldFromInstruction(insn, 5, 9); |
| 14622 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14623 | return S; |
| 14624 | case 102: |
| 14625 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14626 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14627 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14628 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14629 | tmp = 0x0; |
| 14630 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 14631 | tmp |= fieldFromInstruction(insn, 21, 1) << 9; |
| 14632 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14633 | return S; |
| 14634 | case 103: |
| 14635 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14636 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14637 | tmp = 0x0; |
| 14638 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 14639 | tmp |= fieldFromInstruction(insn, 21, 1) << 9; |
| 14640 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14641 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14642 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14643 | return S; |
| 14644 | case 104: |
| 14645 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14646 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14647 | tmp = 0x0; |
| 14648 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 14649 | tmp |= fieldFromInstruction(insn, 16, 5) << 9; |
| 14650 | tmp |= fieldFromInstruction(insn, 22, 2) << 14; |
| 14651 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14652 | return S; |
| 14653 | case 105: |
| 14654 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14655 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14656 | tmp = fieldFromInstruction(insn, 23, 2); |
| 14657 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14658 | tmp = fieldFromInstruction(insn, 5, 8); |
| 14659 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14660 | tmp = 0x0; |
| 14661 | tmp |= fieldFromInstruction(insn, 13, 1); |
| 14662 | tmp |= fieldFromInstruction(insn, 16, 7) << 1; |
| 14663 | if (!Check(S, s8_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14664 | return S; |
| 14665 | case 106: |
| 14666 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14667 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14668 | tmp = fieldFromInstruction(insn, 5, 8); |
| 14669 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14670 | tmp = 0x0; |
| 14671 | tmp |= fieldFromInstruction(insn, 13, 1); |
| 14672 | tmp |= fieldFromInstruction(insn, 16, 7) << 1; |
| 14673 | if (!Check(S, s8_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14674 | return S; |
| 14675 | case 107: |
| 14676 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14677 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14678 | tmp = fieldFromInstruction(insn, 5, 8); |
| 14679 | if (!Check(S, s8_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14680 | tmp = 0x0; |
| 14681 | tmp |= fieldFromInstruction(insn, 13, 1); |
| 14682 | tmp |= fieldFromInstruction(insn, 16, 5) << 1; |
| 14683 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14684 | return S; |
| 14685 | case 108: |
| 14686 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14687 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14688 | tmp = fieldFromInstruction(insn, 21, 2); |
| 14689 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14690 | tmp = 0x0; |
| 14691 | tmp |= fieldFromInstruction(insn, 5, 8); |
| 14692 | tmp |= fieldFromInstruction(insn, 16, 4) << 8; |
| 14693 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14694 | return S; |
| 14695 | case 109: |
| 14696 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14697 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14698 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14699 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14700 | tmp = fieldFromInstruction(insn, 8, 6); |
| 14701 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14702 | return S; |
| 14703 | case 110: |
| 14704 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14705 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14706 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14707 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14708 | tmp = fieldFromInstruction(insn, 8, 4); |
| 14709 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14710 | return S; |
| 14711 | case 111: |
| 14712 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14713 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14714 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14715 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14716 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14717 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14718 | return S; |
| 14719 | case 112: |
| 14720 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14721 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14722 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14723 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14724 | return S; |
| 14725 | case 113: |
| 14726 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14727 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14728 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14729 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14730 | tmp = fieldFromInstruction(insn, 8, 6); |
| 14731 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14732 | tmp = 0x0; |
| 14733 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 14734 | tmp |= fieldFromInstruction(insn, 21, 3) << 3; |
| 14735 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14736 | return S; |
| 14737 | case 114: |
| 14738 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14739 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14740 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14741 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14742 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14743 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14744 | tmp = fieldFromInstruction(insn, 8, 6); |
| 14745 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14746 | return S; |
| 14747 | case 115: |
| 14748 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14749 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14750 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14751 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14752 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14753 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14754 | tmp = fieldFromInstruction(insn, 8, 6); |
| 14755 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14756 | tmp = 0x0; |
| 14757 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 14758 | tmp |= fieldFromInstruction(insn, 21, 3) << 3; |
| 14759 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14760 | return S; |
| 14761 | case 116: |
| 14762 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14763 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14764 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14765 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14766 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14767 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14768 | return S; |
| 14769 | case 117: |
| 14770 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14771 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14772 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14773 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14774 | return S; |
| 14775 | case 118: |
| 14776 | tmp = fieldFromInstruction(insn, 0, 2); |
| 14777 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14778 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14779 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14780 | tmp = fieldFromInstruction(insn, 8, 6); |
| 14781 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14782 | return S; |
| 14783 | case 119: |
| 14784 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14785 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14786 | tmp = fieldFromInstruction(insn, 8, 2); |
| 14787 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14788 | return S; |
| 14789 | case 120: |
| 14790 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14791 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14792 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14793 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14794 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14795 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14796 | tmp = 0x0; |
| 14797 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 14798 | tmp |= fieldFromInstruction(insn, 21, 1) << 3; |
| 14799 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14800 | tmp = fieldFromInstruction(insn, 8, 6); |
| 14801 | if (!Check(S, s6_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14802 | return S; |
| 14803 | case 121: |
| 14804 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14805 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14806 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14807 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14808 | tmp = fieldFromInstruction(insn, 8, 6); |
| 14809 | if (!Check(S, s6_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14810 | return S; |
| 14811 | case 122: |
| 14812 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14813 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14814 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14815 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14816 | tmp = fieldFromInstruction(insn, 8, 4); |
| 14817 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14818 | return S; |
| 14819 | case 123: |
| 14820 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14821 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14822 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14823 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14824 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14825 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14826 | return S; |
| 14827 | case 124: |
| 14828 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14829 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14830 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14831 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14832 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14833 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14834 | return S; |
| 14835 | case 125: |
| 14836 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14837 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14838 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14839 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14840 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14841 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14842 | return S; |
| 14843 | case 126: |
| 14844 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14845 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14846 | tmp = fieldFromInstruction(insn, 16, 2); |
| 14847 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14848 | tmp = fieldFromInstruction(insn, 8, 2); |
| 14849 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14850 | return S; |
| 14851 | case 127: |
| 14852 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14853 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14854 | tmp = fieldFromInstruction(insn, 16, 2); |
| 14855 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14856 | return S; |
| 14857 | case 128: |
| 14858 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14859 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14860 | tmp = fieldFromInstruction(insn, 5, 2); |
| 14861 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14862 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14863 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14864 | return S; |
| 14865 | case 129: |
| 14866 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14867 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14868 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14869 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14870 | tmp = fieldFromInstruction(insn, 8, 6); |
| 14871 | if (!Check(S, s6_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14872 | return S; |
| 14873 | case 130: |
| 14874 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14875 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14876 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14877 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14878 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14879 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14880 | tmp = 0x0; |
| 14881 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 14882 | tmp |= fieldFromInstruction(insn, 21, 2) << 3; |
| 14883 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14884 | return S; |
| 14885 | case 131: |
| 14886 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14887 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14888 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14889 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14890 | tmp = 0x0; |
| 14891 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 14892 | tmp |= fieldFromInstruction(insn, 21, 2) << 3; |
| 14893 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14894 | return S; |
| 14895 | case 132: |
| 14896 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14897 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14898 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14899 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14900 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14901 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14902 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14903 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14904 | return S; |
| 14905 | case 133: |
| 14906 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14907 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14908 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14909 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14910 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14911 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14912 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14913 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14914 | tmp = 0x0; |
| 14915 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 14916 | tmp |= fieldFromInstruction(insn, 21, 2) << 3; |
| 14917 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14918 | return S; |
| 14919 | case 134: |
| 14920 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14921 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14922 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14923 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14924 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14925 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14926 | return S; |
| 14927 | case 135: |
| 14928 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14929 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14930 | tmp = fieldFromInstruction(insn, 8, 5); |
| 14931 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14932 | tmp = fieldFromInstruction(insn, 13, 1); |
| 14933 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14934 | return S; |
| 14935 | case 136: |
| 14936 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14937 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14938 | tmp = fieldFromInstruction(insn, 0, 11) << 3; |
| 14939 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14940 | return S; |
| 14941 | case 137: |
| 14942 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14943 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14944 | tmp = fieldFromInstruction(insn, 8, 2); |
| 14945 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14946 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14947 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14948 | return S; |
| 14949 | case 138: |
| 14950 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14951 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14952 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14953 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14954 | tmp = 0x0; |
| 14955 | tmp |= fieldFromInstruction(insn, 5, 9) << 1; |
| 14956 | tmp |= fieldFromInstruction(insn, 25, 2) << 10; |
| 14957 | if (!Check(S, s31_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14958 | return S; |
| 14959 | case 139: |
| 14960 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14961 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14962 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14963 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14964 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14965 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14966 | tmp = fieldFromInstruction(insn, 5, 4) << 1; |
| 14967 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14968 | tmp = fieldFromInstruction(insn, 13, 1); |
| 14969 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14970 | return S; |
| 14971 | case 140: |
| 14972 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14973 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14974 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14975 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14976 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14977 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14978 | tmp = fieldFromInstruction(insn, 13, 1); |
| 14979 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14980 | return S; |
| 14981 | case 141: |
| 14982 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14983 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14984 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14985 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14986 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14987 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14988 | tmp = fieldFromInstruction(insn, 5, 4) << 1; |
| 14989 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14990 | return S; |
| 14991 | case 142: |
| 14992 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14993 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14994 | tmp = fieldFromInstruction(insn, 0, 5); |
| 14995 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14996 | tmp = fieldFromInstruction(insn, 16, 5); |
| 14997 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 14998 | tmp = 0x0; |
| 14999 | tmp |= fieldFromInstruction(insn, 5, 9) << 1; |
| 15000 | tmp |= fieldFromInstruction(insn, 25, 2) << 10; |
| 15001 | if (!Check(S, s31_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15002 | return S; |
| 15003 | case 143: |
| 15004 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15005 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15006 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15007 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15008 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15009 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15010 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15011 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15012 | tmp = fieldFromInstruction(insn, 5, 4) << 1; |
| 15013 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15014 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15015 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15016 | return S; |
| 15017 | case 144: |
| 15018 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15019 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15020 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15021 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15022 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15023 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15024 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15025 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15026 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15027 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15028 | return S; |
| 15029 | case 145: |
| 15030 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15031 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15032 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15033 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15034 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15035 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15036 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15037 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15038 | tmp = fieldFromInstruction(insn, 5, 4) << 1; |
| 15039 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15040 | return S; |
| 15041 | case 146: |
| 15042 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15043 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15044 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15045 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15046 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15047 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15048 | tmp = 0x0; |
| 15049 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 15050 | tmp |= fieldFromInstruction(insn, 25, 2) << 9; |
| 15051 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15052 | return S; |
| 15053 | case 147: |
| 15054 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15055 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15056 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15057 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15058 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15059 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15060 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15061 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15062 | tmp = fieldFromInstruction(insn, 5, 4); |
| 15063 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15064 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15065 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15066 | return S; |
| 15067 | case 148: |
| 15068 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15069 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15070 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15071 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15072 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15073 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15074 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15075 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15076 | tmp = fieldFromInstruction(insn, 5, 4); |
| 15077 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15078 | return S; |
| 15079 | case 149: |
| 15080 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15081 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15082 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15083 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15084 | tmp = 0x0; |
| 15085 | tmp |= fieldFromInstruction(insn, 5, 9) << 2; |
| 15086 | tmp |= fieldFromInstruction(insn, 25, 2) << 11; |
| 15087 | if (!Check(S, s30_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15088 | return S; |
| 15089 | case 150: |
| 15090 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15091 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15092 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15093 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15094 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15095 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15096 | tmp = fieldFromInstruction(insn, 5, 4) << 2; |
| 15097 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15098 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15099 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15100 | return S; |
| 15101 | case 151: |
| 15102 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15103 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15104 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15105 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15106 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15107 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15108 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15109 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15110 | return S; |
| 15111 | case 152: |
| 15112 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15113 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15114 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15115 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15116 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15117 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15118 | tmp = fieldFromInstruction(insn, 5, 4) << 2; |
| 15119 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15120 | return S; |
| 15121 | case 153: |
| 15122 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15123 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15124 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15125 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15126 | tmp = 0x0; |
| 15127 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 15128 | tmp |= fieldFromInstruction(insn, 25, 2) << 9; |
| 15129 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15130 | return S; |
| 15131 | case 154: |
| 15132 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15133 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15134 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15135 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15136 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15137 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15138 | tmp = fieldFromInstruction(insn, 5, 4); |
| 15139 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15140 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15141 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15142 | return S; |
| 15143 | case 155: |
| 15144 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15145 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15146 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15147 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15148 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15149 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15150 | tmp = fieldFromInstruction(insn, 5, 4); |
| 15151 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15152 | return S; |
| 15153 | case 156: |
| 15154 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15155 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15156 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15157 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15158 | tmp = fieldFromInstruction(insn, 9, 2); |
| 15159 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15160 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15161 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15162 | tmp = fieldFromInstruction(insn, 5, 4); |
| 15163 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15164 | return S; |
| 15165 | case 157: |
| 15166 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15167 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15168 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15169 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15170 | tmp = fieldFromInstruction(insn, 9, 2); |
| 15171 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15172 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15173 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15174 | tmp = fieldFromInstruction(insn, 5, 4) << 1; |
| 15175 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15176 | return S; |
| 15177 | case 158: |
| 15178 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15179 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15180 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15181 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15182 | tmp = 0x0; |
| 15183 | tmp |= fieldFromInstruction(insn, 5, 9) << 2; |
| 15184 | tmp |= fieldFromInstruction(insn, 25, 2) << 11; |
| 15185 | if (!Check(S, s30_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15186 | return S; |
| 15187 | case 159: |
| 15188 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15189 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15190 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15191 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15192 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15193 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15194 | tmp = fieldFromInstruction(insn, 5, 4) << 2; |
| 15195 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15196 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15197 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15198 | return S; |
| 15199 | case 160: |
| 15200 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15201 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15202 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15203 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15204 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15205 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15206 | tmp = fieldFromInstruction(insn, 5, 4) << 2; |
| 15207 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15208 | return S; |
| 15209 | case 161: |
| 15210 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15211 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15212 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15213 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15214 | tmp = fieldFromInstruction(insn, 9, 2); |
| 15215 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15216 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15217 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15218 | tmp = fieldFromInstruction(insn, 5, 4) << 2; |
| 15219 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15220 | return S; |
| 15221 | case 162: |
| 15222 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15223 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15224 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15225 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15226 | tmp = 0x0; |
| 15227 | tmp |= fieldFromInstruction(insn, 5, 9) << 3; |
| 15228 | tmp |= fieldFromInstruction(insn, 25, 2) << 12; |
| 15229 | if (!Check(S, s29_3ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15230 | return S; |
| 15231 | case 163: |
| 15232 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15233 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15234 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15235 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15236 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15237 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15238 | tmp = fieldFromInstruction(insn, 5, 4) << 3; |
| 15239 | if (!Check(S, s4_3ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15240 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15241 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15242 | return S; |
| 15243 | case 164: |
| 15244 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15245 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15246 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15247 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15248 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15249 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15250 | tmp = fieldFromInstruction(insn, 5, 4) << 3; |
| 15251 | if (!Check(S, s4_3ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15252 | return S; |
| 15253 | case 165: |
| 15254 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15255 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15256 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15257 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15258 | tmp = fieldFromInstruction(insn, 9, 2); |
| 15259 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15260 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15261 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15262 | tmp = fieldFromInstruction(insn, 5, 4) << 3; |
| 15263 | if (!Check(S, s4_3ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15264 | return S; |
| 15265 | case 166: |
| 15266 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15267 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15268 | return S; |
| 15269 | case 167: |
| 15270 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15271 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15272 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15273 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15274 | tmp = fieldFromInstruction(insn, 0, 11) << 3; |
| 15275 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15276 | return S; |
| 15277 | case 168: |
| 15278 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15279 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15280 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15281 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15282 | return S; |
| 15283 | case 169: |
| 15284 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15285 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15286 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15287 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15288 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15289 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15290 | return S; |
| 15291 | case 170: |
| 15292 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15293 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15294 | return S; |
| 15295 | case 171: |
| 15296 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15297 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15298 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15299 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15300 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15301 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15302 | return S; |
| 15303 | case 172: |
| 15304 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15305 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15306 | tmp = 0x0; |
| 15307 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 15308 | tmp |= fieldFromInstruction(insn, 13, 1) << 8; |
| 15309 | tmp |= fieldFromInstruction(insn, 25, 2) << 9; |
| 15310 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15311 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15312 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15313 | return S; |
| 15314 | case 173: |
| 15315 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15316 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15317 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15318 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15319 | tmp = fieldFromInstruction(insn, 3, 4); |
| 15320 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15321 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15322 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15323 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15324 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15325 | return S; |
| 15326 | case 174: |
| 15327 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15328 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15329 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15330 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15331 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15332 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15333 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15334 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15335 | return S; |
| 15336 | case 175: |
| 15337 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15338 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15339 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15340 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15341 | tmp = fieldFromInstruction(insn, 3, 4); |
| 15342 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15343 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15344 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15345 | return S; |
| 15346 | case 176: |
| 15347 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15348 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15349 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15350 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15351 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15352 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15353 | tmp = fieldFromInstruction(insn, 3, 4); |
| 15354 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15355 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15356 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15357 | return S; |
| 15358 | case 177: |
| 15359 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15360 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15361 | tmp = 0x0; |
| 15362 | tmp |= fieldFromInstruction(insn, 0, 8) << 1; |
| 15363 | tmp |= fieldFromInstruction(insn, 13, 1) << 9; |
| 15364 | tmp |= fieldFromInstruction(insn, 25, 2) << 10; |
| 15365 | if (!Check(S, s31_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15366 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15367 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15368 | return S; |
| 15369 | case 178: |
| 15370 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15371 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15372 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15373 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15374 | tmp = fieldFromInstruction(insn, 3, 4) << 1; |
| 15375 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15376 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15377 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15378 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15379 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15380 | return S; |
| 15381 | case 179: |
| 15382 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15383 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15384 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15385 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15386 | tmp = fieldFromInstruction(insn, 3, 4) << 1; |
| 15387 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15388 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15389 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15390 | return S; |
| 15391 | case 180: |
| 15392 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15393 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15394 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15395 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15396 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15397 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15398 | tmp = fieldFromInstruction(insn, 3, 4) << 1; |
| 15399 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15400 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15401 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15402 | return S; |
| 15403 | case 181: |
| 15404 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15405 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15406 | tmp = 0x0; |
| 15407 | tmp |= fieldFromInstruction(insn, 0, 8) << 2; |
| 15408 | tmp |= fieldFromInstruction(insn, 13, 1) << 10; |
| 15409 | tmp |= fieldFromInstruction(insn, 25, 2) << 11; |
| 15410 | if (!Check(S, s30_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15411 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15412 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15413 | return S; |
| 15414 | case 182: |
| 15415 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15416 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15417 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15418 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15419 | tmp = fieldFromInstruction(insn, 3, 4) << 2; |
| 15420 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15421 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15422 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15423 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15424 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15425 | return S; |
| 15426 | case 183: |
| 15427 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15428 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15429 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15430 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15431 | tmp = fieldFromInstruction(insn, 3, 4) << 2; |
| 15432 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15433 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15434 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15435 | return S; |
| 15436 | case 184: |
| 15437 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15438 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15439 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15440 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15441 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15442 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15443 | tmp = fieldFromInstruction(insn, 3, 4) << 2; |
| 15444 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15445 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15446 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15447 | return S; |
| 15448 | case 185: |
| 15449 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15450 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15451 | tmp = 0x0; |
| 15452 | tmp |= fieldFromInstruction(insn, 0, 8); |
| 15453 | tmp |= fieldFromInstruction(insn, 13, 1) << 8; |
| 15454 | tmp |= fieldFromInstruction(insn, 25, 2) << 9; |
| 15455 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15456 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15457 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15458 | return S; |
| 15459 | case 186: |
| 15460 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15461 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15462 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15463 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15464 | tmp = fieldFromInstruction(insn, 3, 4); |
| 15465 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15466 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15467 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15468 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15469 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15470 | return S; |
| 15471 | case 187: |
| 15472 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15473 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15474 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15475 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15476 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15477 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15478 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15479 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15480 | return S; |
| 15481 | case 188: |
| 15482 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15483 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15484 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15485 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15486 | tmp = fieldFromInstruction(insn, 3, 4); |
| 15487 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15488 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15489 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15490 | return S; |
| 15491 | case 189: |
| 15492 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15493 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15494 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15495 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15496 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15497 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15498 | tmp = fieldFromInstruction(insn, 3, 4); |
| 15499 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15500 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15501 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15502 | return S; |
| 15503 | case 190: |
| 15504 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15505 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15506 | tmp = 0x0; |
| 15507 | tmp |= fieldFromInstruction(insn, 0, 8) << 1; |
| 15508 | tmp |= fieldFromInstruction(insn, 13, 1) << 9; |
| 15509 | tmp |= fieldFromInstruction(insn, 25, 2) << 10; |
| 15510 | if (!Check(S, s31_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15511 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15512 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15513 | return S; |
| 15514 | case 191: |
| 15515 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15516 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15517 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15518 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15519 | tmp = fieldFromInstruction(insn, 3, 4) << 1; |
| 15520 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15521 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15522 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15523 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15524 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15525 | return S; |
| 15526 | case 192: |
| 15527 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15528 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15529 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15530 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15531 | tmp = fieldFromInstruction(insn, 3, 4) << 1; |
| 15532 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15533 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15534 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15535 | return S; |
| 15536 | case 193: |
| 15537 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15538 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15539 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15540 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15541 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15542 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15543 | tmp = fieldFromInstruction(insn, 3, 4) << 1; |
| 15544 | if (!Check(S, s4_1ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15545 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15546 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15547 | return S; |
| 15548 | case 194: |
| 15549 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15550 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15551 | tmp = 0x0; |
| 15552 | tmp |= fieldFromInstruction(insn, 0, 8) << 2; |
| 15553 | tmp |= fieldFromInstruction(insn, 13, 1) << 10; |
| 15554 | tmp |= fieldFromInstruction(insn, 25, 2) << 11; |
| 15555 | if (!Check(S, s30_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15556 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15557 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15558 | return S; |
| 15559 | case 195: |
| 15560 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15561 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15562 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15563 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15564 | tmp = fieldFromInstruction(insn, 3, 4) << 2; |
| 15565 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15566 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15567 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15568 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15569 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15570 | return S; |
| 15571 | case 196: |
| 15572 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15573 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15574 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15575 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15576 | tmp = fieldFromInstruction(insn, 3, 4) << 2; |
| 15577 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15578 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15579 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15580 | return S; |
| 15581 | case 197: |
| 15582 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15583 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15584 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15585 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15586 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15587 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15588 | tmp = fieldFromInstruction(insn, 3, 4) << 2; |
| 15589 | if (!Check(S, s4_2ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15590 | tmp = fieldFromInstruction(insn, 8, 3); |
| 15591 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15592 | return S; |
| 15593 | case 198: |
| 15594 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15595 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15596 | tmp = 0x0; |
| 15597 | tmp |= fieldFromInstruction(insn, 0, 8) << 3; |
| 15598 | tmp |= fieldFromInstruction(insn, 13, 1) << 11; |
| 15599 | tmp |= fieldFromInstruction(insn, 25, 2) << 12; |
| 15600 | if (!Check(S, s29_3ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15601 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15602 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15603 | return S; |
| 15604 | case 199: |
| 15605 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15606 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15607 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15608 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15609 | tmp = fieldFromInstruction(insn, 3, 4) << 3; |
| 15610 | if (!Check(S, s4_3ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15611 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15612 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15613 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15614 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15615 | return S; |
| 15616 | case 200: |
| 15617 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15618 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15619 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15620 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15621 | tmp = fieldFromInstruction(insn, 13, 1); |
| 15622 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15623 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15624 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15625 | return S; |
| 15626 | case 201: |
| 15627 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15628 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15629 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15630 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15631 | tmp = fieldFromInstruction(insn, 3, 4) << 3; |
| 15632 | if (!Check(S, s4_3ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15633 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15634 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15635 | return S; |
| 15636 | case 202: |
| 15637 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15638 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15639 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15640 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15641 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15642 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15643 | tmp = fieldFromInstruction(insn, 3, 4) << 3; |
| 15644 | if (!Check(S, s4_3ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15645 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15646 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15647 | return S; |
| 15648 | case 203: |
| 15649 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15650 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15651 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15652 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15653 | tmp = 0x0; |
| 15654 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 15655 | tmp |= fieldFromInstruction(insn, 21, 7) << 9; |
| 15656 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15657 | return S; |
| 15658 | case 204: |
| 15659 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15660 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15661 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15662 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15663 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15664 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15665 | tmp = fieldFromInstruction(insn, 5, 3); |
| 15666 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15667 | return S; |
| 15668 | case 205: |
| 15669 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15670 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15671 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15672 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15673 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15674 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15675 | tmp = fieldFromInstruction(insn, 5, 3); |
| 15676 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15677 | return S; |
| 15678 | case 206: |
| 15679 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15680 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15681 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15682 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15683 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15684 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15685 | return S; |
| 15686 | case 207: |
| 15687 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15688 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15689 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15690 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15691 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15692 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15693 | return S; |
| 15694 | case 208: |
| 15695 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15696 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15697 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15698 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15699 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15700 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15701 | return S; |
| 15702 | case 209: |
| 15703 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15704 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15705 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15706 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15707 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15708 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15709 | tmp = fieldFromInstruction(insn, 5, 2); |
| 15710 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15711 | return S; |
| 15712 | case 210: |
| 15713 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15714 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15715 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15716 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15717 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15718 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15719 | tmp = fieldFromInstruction(insn, 5, 2); |
| 15720 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15721 | return S; |
| 15722 | case 211: |
| 15723 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15724 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15725 | tmp = fieldFromInstruction(insn, 5, 2); |
| 15726 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15727 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15728 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15729 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15730 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15731 | tmp = fieldFromInstruction(insn, 5, 2); |
| 15732 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15733 | return S; |
| 15734 | case 212: |
| 15735 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15736 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15737 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15738 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15739 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15740 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15741 | return S; |
| 15742 | case 213: |
| 15743 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15744 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15745 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15746 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15747 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15748 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15749 | tmp = 0x0; |
| 15750 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 15751 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 15752 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15753 | return S; |
| 15754 | case 214: |
| 15755 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15756 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15757 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15758 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15759 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15760 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15761 | tmp = fieldFromInstruction(insn, 5, 3); |
| 15762 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15763 | return S; |
| 15764 | case 215: |
| 15765 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15766 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15767 | tmp = 0x0; |
| 15768 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 15769 | tmp |= fieldFromInstruction(insn, 16, 5) << 1; |
| 15770 | if (!Check(S, s6_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15771 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15772 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15773 | return S; |
| 15774 | case 216: |
| 15775 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15776 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15777 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15778 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15779 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15780 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15781 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15782 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15783 | return S; |
| 15784 | case 217: |
| 15785 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15786 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15787 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15788 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15789 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15790 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15791 | return S; |
| 15792 | case 218: |
| 15793 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15794 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15795 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15796 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15797 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15798 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15799 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15800 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15801 | return S; |
| 15802 | case 219: |
| 15803 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15804 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15805 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15806 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15807 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15808 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15809 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15810 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15811 | return S; |
| 15812 | case 220: |
| 15813 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15814 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15815 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15816 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15817 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15818 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15819 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15820 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15821 | return S; |
| 15822 | case 221: |
| 15823 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15824 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15825 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15826 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15827 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15828 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15829 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15830 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15831 | tmp = 0x0; |
| 15832 | tmp |= fieldFromInstruction(insn, 5, 1); |
| 15833 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 15834 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15835 | return S; |
| 15836 | case 222: |
| 15837 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15838 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15839 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15840 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15841 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15842 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15843 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15844 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15845 | return S; |
| 15846 | case 223: |
| 15847 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15848 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15849 | tmp = fieldFromInstruction(insn, 5, 2); |
| 15850 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15851 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15852 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15853 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15854 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15855 | return S; |
| 15856 | case 224: |
| 15857 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15858 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15859 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15860 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15861 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15862 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15863 | return S; |
| 15864 | case 225: |
| 15865 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15866 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15867 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15868 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15869 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15870 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15871 | return S; |
| 15872 | case 226: |
| 15873 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15874 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15875 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15876 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15877 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15878 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15879 | return S; |
| 15880 | case 227: |
| 15881 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15882 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15883 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15884 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15885 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15886 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15887 | return S; |
| 15888 | case 228: |
| 15889 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15890 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15891 | tmp = 0x0; |
| 15892 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 15893 | tmp |= fieldFromInstruction(insn, 21, 1) << 9; |
| 15894 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15895 | return S; |
| 15896 | case 229: |
| 15897 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15898 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15899 | tmp = 0x0; |
| 15900 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 15901 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 15902 | tmp |= fieldFromInstruction(insn, 21, 2) << 4; |
| 15903 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15904 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15905 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15906 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15907 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15908 | return S; |
| 15909 | case 230: |
| 15910 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15911 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15912 | tmp = 0x0; |
| 15913 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 15914 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 15915 | tmp |= fieldFromInstruction(insn, 21, 2) << 4; |
| 15916 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15917 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15918 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15919 | tmp = 0x0; |
| 15920 | tmp |= fieldFromInstruction(insn, 0, 5); |
| 15921 | tmp |= fieldFromInstruction(insn, 23, 1) << 5; |
| 15922 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15923 | return S; |
| 15924 | case 231: |
| 15925 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15926 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15927 | tmp = 0x0; |
| 15928 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 15929 | tmp |= fieldFromInstruction(insn, 21, 1) << 9; |
| 15930 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15931 | return S; |
| 15932 | case 232: |
| 15933 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15934 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15935 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15936 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15937 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15938 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15939 | tmp = 0x0; |
| 15940 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 15941 | tmp |= fieldFromInstruction(insn, 21, 1) << 9; |
| 15942 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15943 | return S; |
| 15944 | case 233: |
| 15945 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15946 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15947 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15948 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15949 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15950 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15951 | tmp = 0x0; |
| 15952 | tmp |= fieldFromInstruction(insn, 5, 9); |
| 15953 | tmp |= fieldFromInstruction(insn, 21, 1) << 9; |
| 15954 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15955 | return S; |
| 15956 | case 234: |
| 15957 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15958 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15959 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15960 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15961 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15962 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15963 | tmp = 0x0; |
| 15964 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 15965 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 15966 | tmp |= fieldFromInstruction(insn, 21, 2) << 4; |
| 15967 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15968 | return S; |
| 15969 | case 235: |
| 15970 | tmp = fieldFromInstruction(insn, 8, 5); |
| 15971 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15972 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15973 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15974 | tmp = 0x0; |
| 15975 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 15976 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 15977 | tmp |= fieldFromInstruction(insn, 21, 2) << 4; |
| 15978 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15979 | tmp = fieldFromInstruction(insn, 0, 5); |
| 15980 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15981 | return S; |
| 15982 | case 236: |
| 15983 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15984 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15985 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15986 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15987 | tmp = fieldFromInstruction(insn, 5, 8); |
| 15988 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15989 | return S; |
| 15990 | case 237: |
| 15991 | tmp = fieldFromInstruction(insn, 0, 2); |
| 15992 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15993 | tmp = fieldFromInstruction(insn, 16, 5); |
| 15994 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15995 | tmp = fieldFromInstruction(insn, 5, 8); |
| 15996 | if (!Check(S, s8_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 15997 | return S; |
| 15998 | case 238: |
| 15999 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16000 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16001 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16002 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16003 | tmp = fieldFromInstruction(insn, 5, 7); |
| 16004 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16005 | return S; |
| 16006 | case 239: |
| 16007 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16008 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16009 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16010 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16011 | tmp = fieldFromInstruction(insn, 5, 5); |
| 16012 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16013 | return S; |
| 16014 | case 240: |
| 16015 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16016 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16017 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16018 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16019 | tmp = fieldFromInstruction(insn, 5, 8); |
| 16020 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16021 | return S; |
| 16022 | case 241: |
| 16023 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16024 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16025 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16026 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16027 | tmp = fieldFromInstruction(insn, 5, 8); |
| 16028 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16029 | return S; |
| 16030 | case 242: |
| 16031 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16032 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16033 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16034 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16035 | tmp = fieldFromInstruction(insn, 5, 8); |
| 16036 | if (!Check(S, s8_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16037 | return S; |
| 16038 | case 243: |
| 16039 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16040 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16041 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16042 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16043 | tmp = fieldFromInstruction(insn, 5, 7); |
| 16044 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16045 | return S; |
| 16046 | case 244: |
| 16047 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16048 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16049 | tmp = 0x0; |
| 16050 | tmp |= fieldFromInstruction(insn, 3, 1); |
| 16051 | tmp |= fieldFromInstruction(insn, 5, 3) << 1; |
| 16052 | tmp |= fieldFromInstruction(insn, 13, 1) << 4; |
| 16053 | tmp |= fieldFromInstruction(insn, 21, 3) << 5; |
| 16054 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16055 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16056 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16057 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16058 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16059 | return S; |
| 16060 | case 245: |
| 16061 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16062 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16063 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16064 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16065 | tmp = 0x0; |
| 16066 | tmp |= fieldFromInstruction(insn, 5, 3) << 2; |
| 16067 | tmp |= fieldFromInstruction(insn, 13, 1) << 5; |
| 16068 | tmp |= fieldFromInstruction(insn, 21, 2) << 6; |
| 16069 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16070 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16071 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16072 | return S; |
| 16073 | case 246: |
| 16074 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16075 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16076 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16077 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16078 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16079 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16080 | tmp = 0x0; |
| 16081 | tmp |= fieldFromInstruction(insn, 5, 3); |
| 16082 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 16083 | tmp |= fieldFromInstruction(insn, 21, 2) << 4; |
| 16084 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16085 | return S; |
| 16086 | case 247: |
| 16087 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16088 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16089 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16090 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16091 | tmp = fieldFromInstruction(insn, 5, 8); |
| 16092 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16093 | return S; |
| 16094 | case 248: |
| 16095 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16096 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16097 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16098 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16099 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16100 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16101 | tmp = fieldFromInstruction(insn, 5, 8); |
| 16102 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16103 | return S; |
| 16104 | case 249: |
| 16105 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16106 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16107 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16108 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16109 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16110 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16111 | tmp = fieldFromInstruction(insn, 5, 8); |
| 16112 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16113 | return S; |
| 16114 | case 250: |
| 16115 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16116 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16117 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16118 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16119 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16120 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16121 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16122 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16123 | return S; |
| 16124 | case 251: |
| 16125 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16126 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16127 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16128 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16129 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16130 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16131 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16132 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16133 | return S; |
| 16134 | case 252: |
| 16135 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16136 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16137 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16138 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16139 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16140 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16141 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16142 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16143 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16144 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16145 | return S; |
| 16146 | case 253: |
| 16147 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16148 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16149 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16150 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16151 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16152 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16153 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16154 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16155 | return S; |
| 16156 | case 254: |
| 16157 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16158 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16159 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16160 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16161 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16162 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16163 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16164 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16165 | return S; |
| 16166 | case 255: |
| 16167 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16168 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16169 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16170 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16171 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16172 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16173 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16174 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16175 | return S; |
| 16176 | case 256: |
| 16177 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16178 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16179 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16180 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16181 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16182 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16183 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16184 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16185 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16186 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16187 | return S; |
| 16188 | case 257: |
| 16189 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16190 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16191 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16192 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16193 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16194 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16195 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16196 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16197 | return S; |
| 16198 | case 258: |
| 16199 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16200 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16201 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16202 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16203 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16204 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16205 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16206 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16207 | return S; |
| 16208 | case 259: |
| 16209 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16210 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16211 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16212 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16213 | tmp = fieldFromInstruction(insn, 19, 5); |
| 16214 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16215 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16216 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16217 | return S; |
| 16218 | case 260: |
| 16219 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16220 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16221 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16222 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16223 | tmp = fieldFromInstruction(insn, 19, 5); |
| 16224 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16225 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16226 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16227 | return S; |
| 16228 | case 261: |
| 16229 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16230 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16231 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16232 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16233 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16234 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16235 | return S; |
| 16236 | case 262: |
| 16237 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16238 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16239 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16240 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16241 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16242 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16243 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16244 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16245 | return S; |
| 16246 | case 263: |
| 16247 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16248 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16249 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16250 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16251 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16252 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16253 | return S; |
| 16254 | case 264: |
| 16255 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16256 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16257 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16258 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16259 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16260 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16261 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16262 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16263 | return S; |
| 16264 | case 265: |
| 16265 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16266 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16267 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16268 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16269 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16270 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16271 | return S; |
| 16272 | case 266: |
| 16273 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16274 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16275 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16276 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16277 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16278 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16279 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16280 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16281 | return S; |
| 16282 | case 267: |
| 16283 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16284 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16285 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16286 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16287 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16288 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16289 | return S; |
| 16290 | case 268: |
| 16291 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16292 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16293 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16294 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16295 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16296 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16297 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16298 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16299 | return S; |
| 16300 | case 269: |
| 16301 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16302 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16303 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16304 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16305 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16306 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16307 | tmp = fieldFromInstruction(insn, 5, 1); |
| 16308 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16309 | return S; |
| 16310 | case 270: |
| 16311 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16312 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16313 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16314 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16315 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16316 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16317 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16318 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16319 | tmp = fieldFromInstruction(insn, 5, 1); |
| 16320 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16321 | return S; |
| 16322 | case 271: |
| 16323 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16324 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16325 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16326 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16327 | tmp = fieldFromInstruction(insn, 8, 2); |
| 16328 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16329 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16330 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16331 | return S; |
| 16332 | case 272: |
| 16333 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16334 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16335 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16336 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16337 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16338 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16339 | return S; |
| 16340 | case 273: |
| 16341 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16342 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16343 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16344 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16345 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16346 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16347 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16348 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16349 | return S; |
| 16350 | case 274: |
| 16351 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16352 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16353 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16354 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16355 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16356 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16357 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16358 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16359 | return S; |
| 16360 | case 275: |
| 16361 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16362 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16363 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16364 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16365 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16366 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16367 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16368 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16369 | return S; |
| 16370 | case 276: |
| 16371 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16372 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16373 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16374 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16375 | return S; |
| 16376 | case 277: |
| 16377 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16378 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16379 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16380 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16381 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16382 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16383 | return S; |
| 16384 | case 278: |
| 16385 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16386 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16387 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16388 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16389 | return S; |
| 16390 | case 279: |
| 16391 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16392 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16393 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16394 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16395 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16396 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16397 | return S; |
| 16398 | case 280: |
| 16399 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16400 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16401 | tmp = fieldFromInstruction(insn, 8, 2); |
| 16402 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16403 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16404 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16405 | return S; |
| 16406 | case 281: |
| 16407 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16408 | if (!Check(S, DecodeHvxVQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16409 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16410 | if (!Check(S, DecodeHvxVQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16411 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16412 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16413 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16414 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16415 | return S; |
| 16416 | case 282: |
| 16417 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16418 | if (!Check(S, DecodeHvxVQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16419 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16420 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16421 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16422 | if (!Check(S, DecodeHvxVQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16423 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16424 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16425 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16426 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16427 | return S; |
| 16428 | case 283: |
| 16429 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16430 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16431 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16432 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16433 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16434 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16435 | return S; |
| 16436 | case 284: |
| 16437 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16438 | if (!Check(S, DecodeHvxVQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16439 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16440 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16441 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16442 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16443 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16444 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16445 | return S; |
| 16446 | case 285: |
| 16447 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16448 | if (!Check(S, DecodeHvxVQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16449 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16450 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16451 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16452 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16453 | return S; |
| 16454 | case 286: |
| 16455 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16456 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16457 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16458 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16459 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16460 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16461 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16462 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16463 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16464 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16465 | return S; |
| 16466 | case 287: |
| 16467 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16468 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16469 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16470 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16471 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16472 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16473 | return S; |
| 16474 | case 288: |
| 16475 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16476 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16477 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16478 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16479 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16480 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16481 | return S; |
| 16482 | case 289: |
| 16483 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16484 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16485 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16486 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16487 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16488 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16489 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16490 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16491 | return S; |
| 16492 | case 290: |
| 16493 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16494 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16495 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16496 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16497 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16498 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16499 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16500 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16501 | return S; |
| 16502 | case 291: |
| 16503 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16504 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16505 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16506 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16507 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16508 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16509 | tmp = fieldFromInstruction(insn, 19, 5); |
| 16510 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16511 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16512 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16513 | return S; |
| 16514 | case 292: |
| 16515 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16516 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16517 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16518 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16519 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16520 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16521 | tmp = fieldFromInstruction(insn, 19, 5); |
| 16522 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16523 | tmp = fieldFromInstruction(insn, 16, 3); |
| 16524 | if (!Check(S, DecodeIntRegsLow8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16525 | return S; |
| 16526 | case 293: |
| 16527 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16528 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16529 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16530 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16531 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16532 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16533 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16534 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16535 | return S; |
| 16536 | case 294: |
| 16537 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16538 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16539 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16540 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16541 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16542 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16543 | return S; |
| 16544 | case 295: |
| 16545 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16546 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16547 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16548 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16549 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16550 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16551 | return S; |
| 16552 | case 296: |
| 16553 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16554 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16555 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16556 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16557 | return S; |
| 16558 | case 297: |
| 16559 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16560 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16561 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16562 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16563 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16564 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16565 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16566 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16567 | return S; |
| 16568 | case 298: |
| 16569 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16570 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16571 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16572 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16573 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16574 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16575 | return S; |
| 16576 | case 299: |
| 16577 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16578 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16579 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16580 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16581 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16582 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16583 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16584 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16585 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16586 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16587 | return S; |
| 16588 | case 300: |
| 16589 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16590 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16591 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16592 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16593 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16594 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16595 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16596 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16597 | tmp = fieldFromInstruction(insn, 5, 3); |
| 16598 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16599 | return S; |
| 16600 | case 301: |
| 16601 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16602 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16603 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16604 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16605 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16606 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16607 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16608 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16609 | tmp = fieldFromInstruction(insn, 5, 3); |
| 16610 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16611 | return S; |
| 16612 | case 302: |
| 16613 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16614 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16615 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16616 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16617 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16618 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16619 | return S; |
| 16620 | case 303: |
| 16621 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16622 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16623 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16624 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16625 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16626 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16627 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16628 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16629 | return S; |
| 16630 | case 304: |
| 16631 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16632 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16633 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16634 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16635 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16636 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16637 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16638 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16639 | return S; |
| 16640 | case 305: |
| 16641 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16642 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16643 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16644 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16645 | return S; |
| 16646 | case 306: |
| 16647 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16648 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16649 | tmp = fieldFromInstruction(insn, 8, 2); |
| 16650 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16651 | tmp = fieldFromInstruction(insn, 22, 2); |
| 16652 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16653 | return S; |
| 16654 | case 307: |
| 16655 | tmp = fieldFromInstruction(insn, 0, 2); |
| 16656 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16657 | tmp = fieldFromInstruction(insn, 8, 2); |
| 16658 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16659 | return S; |
| 16660 | case 308: |
| 16661 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16662 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16663 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16664 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16665 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16666 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16667 | tmp = fieldFromInstruction(insn, 5, 3); |
| 16668 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16669 | return S; |
| 16670 | case 309: |
| 16671 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16672 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16673 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16674 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16675 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16676 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16677 | tmp = fieldFromInstruction(insn, 5, 3); |
| 16678 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16679 | return S; |
| 16680 | case 310: |
| 16681 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16682 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16683 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16684 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16685 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16686 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16687 | return S; |
| 16688 | case 311: |
| 16689 | tmp = fieldFromInstruction(insn, 8, 1); |
| 16690 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16691 | return S; |
| 16692 | case 312: |
| 16693 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16694 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16695 | tmp = fieldFromInstruction(insn, 22, 2); |
| 16696 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16697 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16698 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16699 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16700 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16701 | return S; |
| 16702 | case 313: |
| 16703 | tmp = fieldFromInstruction(insn, 22, 2); |
| 16704 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16705 | return S; |
| 16706 | case 314: |
| 16707 | tmp = fieldFromInstruction(insn, 22, 2); |
| 16708 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16709 | tmp = fieldFromInstruction(insn, 8, 1); |
| 16710 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16711 | return S; |
| 16712 | case 315: |
| 16713 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16714 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16715 | tmp = fieldFromInstruction(insn, 22, 2); |
| 16716 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16717 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16718 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16719 | return S; |
| 16720 | case 316: |
| 16721 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16722 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16723 | tmp = fieldFromInstruction(insn, 22, 2); |
| 16724 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16725 | return S; |
| 16726 | case 317: |
| 16727 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16728 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16729 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16730 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16731 | return S; |
| 16732 | case 318: |
| 16733 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16734 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16735 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16736 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16737 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16738 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16739 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16740 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16741 | return S; |
| 16742 | case 319: |
| 16743 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16744 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16745 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16746 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16747 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16748 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16749 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16750 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16751 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16752 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16753 | return S; |
| 16754 | case 320: |
| 16755 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16756 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16757 | tmp = fieldFromInstruction(insn, 8, 5); |
| 16758 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16759 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16760 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16761 | tmp = fieldFromInstruction(insn, 5, 2); |
| 16762 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16763 | return S; |
| 16764 | case 321: |
| 16765 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16766 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16767 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16768 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16769 | tmp = 0x0; |
| 16770 | tmp |= fieldFromInstruction(insn, 8, 3); |
| 16771 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 16772 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16773 | return S; |
| 16774 | case 322: |
| 16775 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16776 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16777 | tmp = 0x0; |
| 16778 | tmp |= fieldFromInstruction(insn, 8, 3); |
| 16779 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 16780 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16781 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16782 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16783 | return S; |
| 16784 | case 323: |
| 16785 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16786 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16787 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16788 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16789 | tmp = 0x0; |
| 16790 | tmp |= fieldFromInstruction(insn, 8, 3); |
| 16791 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 16792 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16793 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16794 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16795 | return S; |
| 16796 | case 324: |
| 16797 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16798 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16799 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16800 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16801 | tmp = 0x0; |
| 16802 | tmp |= fieldFromInstruction(insn, 8, 3); |
| 16803 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 16804 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16805 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16806 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16807 | return S; |
| 16808 | case 325: |
| 16809 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16810 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16811 | tmp = 0x0; |
| 16812 | tmp |= fieldFromInstruction(insn, 8, 3); |
| 16813 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 16814 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16815 | tmp = fieldFromInstruction(insn, 0, 3); |
| 16816 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16817 | return S; |
| 16818 | case 326: |
| 16819 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16820 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16821 | tmp = 0x0; |
| 16822 | tmp |= fieldFromInstruction(insn, 8, 3); |
| 16823 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 16824 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16825 | return S; |
| 16826 | case 327: |
| 16827 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16828 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16829 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16830 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16831 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16832 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16833 | tmp = 0x0; |
| 16834 | tmp |= fieldFromInstruction(insn, 8, 3); |
| 16835 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 16836 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16837 | return S; |
| 16838 | case 328: |
| 16839 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16840 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16841 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16842 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16843 | tmp = 0x0; |
| 16844 | tmp |= fieldFromInstruction(insn, 8, 3); |
| 16845 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 16846 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16847 | tmp = fieldFromInstruction(insn, 0, 3); |
| 16848 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16849 | return S; |
| 16850 | case 329: |
| 16851 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16852 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16853 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16854 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16855 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16856 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16857 | tmp = fieldFromInstruction(insn, 8, 3); |
| 16858 | if (!Check(S, s3_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16859 | return S; |
| 16860 | case 330: |
| 16861 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16862 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16863 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16864 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16865 | tmp = fieldFromInstruction(insn, 8, 3); |
| 16866 | if (!Check(S, s3_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16867 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16868 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16869 | return S; |
| 16870 | case 331: |
| 16871 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16872 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16873 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16874 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16875 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16876 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16877 | tmp = fieldFromInstruction(insn, 8, 3); |
| 16878 | if (!Check(S, s3_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16879 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16880 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16881 | return S; |
| 16882 | case 332: |
| 16883 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16884 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16885 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16886 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16887 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16888 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16889 | tmp = fieldFromInstruction(insn, 8, 3); |
| 16890 | if (!Check(S, s3_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16891 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16892 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16893 | return S; |
| 16894 | case 333: |
| 16895 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16896 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16897 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16898 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16899 | tmp = fieldFromInstruction(insn, 8, 3); |
| 16900 | if (!Check(S, s3_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16901 | tmp = fieldFromInstruction(insn, 0, 3); |
| 16902 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16903 | return S; |
| 16904 | case 334: |
| 16905 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16906 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16907 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16908 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16909 | tmp = fieldFromInstruction(insn, 8, 3); |
| 16910 | if (!Check(S, s3_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16911 | return S; |
| 16912 | case 335: |
| 16913 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16914 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16915 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16916 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16917 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16918 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16919 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16920 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16921 | tmp = fieldFromInstruction(insn, 8, 3); |
| 16922 | if (!Check(S, s3_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16923 | return S; |
| 16924 | case 336: |
| 16925 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16926 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16927 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16928 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16929 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16930 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16931 | tmp = fieldFromInstruction(insn, 8, 3); |
| 16932 | if (!Check(S, s3_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16933 | tmp = fieldFromInstruction(insn, 0, 3); |
| 16934 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16935 | return S; |
| 16936 | case 337: |
| 16937 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16938 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16939 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16940 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16941 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16942 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16943 | tmp = fieldFromInstruction(insn, 13, 1); |
| 16944 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16945 | return S; |
| 16946 | case 338: |
| 16947 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16948 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16949 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16950 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16951 | tmp = fieldFromInstruction(insn, 13, 1); |
| 16952 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16953 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16954 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16955 | return S; |
| 16956 | case 339: |
| 16957 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16958 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16959 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16960 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16961 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16962 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16963 | tmp = fieldFromInstruction(insn, 13, 1); |
| 16964 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16965 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16966 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16967 | return S; |
| 16968 | case 340: |
| 16969 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16970 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16971 | tmp = fieldFromInstruction(insn, 11, 2); |
| 16972 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16973 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16974 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16975 | tmp = fieldFromInstruction(insn, 13, 1); |
| 16976 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16977 | tmp = fieldFromInstruction(insn, 0, 5); |
| 16978 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16979 | return S; |
| 16980 | case 341: |
| 16981 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16982 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16983 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16984 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16985 | tmp = fieldFromInstruction(insn, 13, 1); |
| 16986 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16987 | tmp = fieldFromInstruction(insn, 0, 3); |
| 16988 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16989 | return S; |
| 16990 | case 342: |
| 16991 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16992 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16993 | tmp = fieldFromInstruction(insn, 16, 5); |
| 16994 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16995 | tmp = fieldFromInstruction(insn, 13, 1); |
| 16996 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 16997 | return S; |
| 16998 | case 343: |
| 16999 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17000 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17001 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17002 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17003 | tmp = fieldFromInstruction(insn, 11, 2); |
| 17004 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17005 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17006 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17007 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17008 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17009 | return S; |
| 17010 | case 344: |
| 17011 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17012 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17013 | tmp = fieldFromInstruction(insn, 11, 2); |
| 17014 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17015 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17016 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17017 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17018 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17019 | tmp = fieldFromInstruction(insn, 0, 3); |
| 17020 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17021 | return S; |
| 17022 | case 345: |
| 17023 | tmp = fieldFromInstruction(insn, 11, 2); |
| 17024 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17025 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17026 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17027 | tmp = 0x0; |
| 17028 | tmp |= fieldFromInstruction(insn, 8, 3); |
| 17029 | tmp |= fieldFromInstruction(insn, 13, 1) << 3; |
| 17030 | if (!Check(S, s4_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17031 | return S; |
| 17032 | case 346: |
| 17033 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17034 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17035 | tmp = fieldFromInstruction(insn, 11, 2); |
| 17036 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17037 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17038 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17039 | tmp = fieldFromInstruction(insn, 8, 3); |
| 17040 | if (!Check(S, s3_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17041 | return S; |
| 17042 | case 347: |
| 17043 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17044 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17045 | tmp = fieldFromInstruction(insn, 11, 2); |
| 17046 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17047 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17048 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17049 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17050 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17051 | return S; |
| 17052 | case 348: |
| 17053 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17054 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17055 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17056 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17057 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17058 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17059 | return S; |
| 17060 | case 349: |
| 17061 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17062 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17063 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17064 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17065 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17066 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17067 | return S; |
| 17068 | case 350: |
| 17069 | tmp = fieldFromInstruction(insn, 5, 2); |
| 17070 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17071 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17072 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17073 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17074 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17075 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17076 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17077 | return S; |
| 17078 | case 351: |
| 17079 | tmp = fieldFromInstruction(insn, 5, 2); |
| 17080 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17081 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17082 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17083 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17084 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17085 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17086 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17087 | return S; |
| 17088 | case 352: |
| 17089 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17090 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17091 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17092 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17093 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17094 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17095 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17096 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17097 | return S; |
| 17098 | case 353: |
| 17099 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17100 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17101 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17102 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17103 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17104 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17105 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17106 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17107 | return S; |
| 17108 | case 354: |
| 17109 | tmp = fieldFromInstruction(insn, 5, 2); |
| 17110 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17111 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17112 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17113 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17114 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17115 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17116 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17117 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17118 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17119 | return S; |
| 17120 | case 355: |
| 17121 | tmp = fieldFromInstruction(insn, 5, 2); |
| 17122 | if (!Check(S, DecodeHvxQRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17123 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17124 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17125 | tmp = fieldFromInstruction(insn, 13, 1); |
| 17126 | if (!Check(S, DecodeModRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17127 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17128 | if (!Check(S, DecodeHvxWRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17129 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17130 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17131 | return S; |
| 17132 | case 356: |
| 17133 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17134 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17135 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17136 | if (!Check(S, DecodeHvxVRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17137 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17138 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17139 | return S; |
| 17140 | case 357: |
| 17141 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17142 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17143 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17144 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17145 | tmp = 0x0; |
| 17146 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 17147 | tmp |= fieldFromInstruction(insn, 8, 4) << 2; |
| 17148 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17149 | return S; |
| 17150 | case 358: |
| 17151 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17152 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17153 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17154 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17155 | tmp = 0x0; |
| 17156 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 17157 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 17158 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17159 | tmp = 0x0; |
| 17160 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 17161 | tmp |= fieldFromInstruction(insn, 8, 4) << 2; |
| 17162 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17163 | return S; |
| 17164 | case 359: |
| 17165 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17166 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17167 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17168 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17169 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17170 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17171 | tmp = 0x0; |
| 17172 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 17173 | tmp |= fieldFromInstruction(insn, 8, 4) << 2; |
| 17174 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17175 | return S; |
| 17176 | case 360: |
| 17177 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17178 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17179 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17180 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17181 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17182 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17183 | tmp = 0x0; |
| 17184 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 17185 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 17186 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17187 | tmp = 0x0; |
| 17188 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 17189 | tmp |= fieldFromInstruction(insn, 8, 4) << 2; |
| 17190 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17191 | return S; |
| 17192 | case 361: |
| 17193 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17194 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17195 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17196 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17197 | tmp = 0x0; |
| 17198 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 17199 | tmp |= fieldFromInstruction(insn, 8, 4) << 2; |
| 17200 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17201 | return S; |
| 17202 | case 362: |
| 17203 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17204 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17205 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17206 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17207 | tmp = 0x0; |
| 17208 | tmp |= fieldFromInstruction(insn, 7, 1); |
| 17209 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 17210 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17211 | tmp = 0x0; |
| 17212 | tmp |= fieldFromInstruction(insn, 5, 2); |
| 17213 | tmp |= fieldFromInstruction(insn, 8, 4) << 2; |
| 17214 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17215 | return S; |
| 17216 | case 363: |
| 17217 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17218 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17219 | tmp = fieldFromInstruction(insn, 9, 2); |
| 17220 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17221 | tmp = 0x0; |
| 17222 | tmp |= fieldFromInstruction(insn, 8, 1); |
| 17223 | tmp |= fieldFromInstruction(insn, 16, 5) << 1; |
| 17224 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17225 | return S; |
| 17226 | case 364: |
| 17227 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17228 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17229 | tmp = fieldFromInstruction(insn, 0, 6); |
| 17230 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17231 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17232 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17233 | return S; |
| 17234 | case 365: |
| 17235 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17236 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17237 | tmp = 0x0; |
| 17238 | tmp |= fieldFromInstruction(insn, 6, 1); |
| 17239 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 17240 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17241 | tmp = fieldFromInstruction(insn, 0, 6); |
| 17242 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17243 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17244 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17245 | return S; |
| 17246 | case 366: |
| 17247 | tmp = fieldFromInstruction(insn, 0, 2); |
| 17248 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17249 | tmp = 0x0; |
| 17250 | tmp |= fieldFromInstruction(insn, 3, 4); |
| 17251 | tmp |= fieldFromInstruction(insn, 16, 2) << 4; |
| 17252 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17253 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17254 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17255 | return S; |
| 17256 | case 367: |
| 17257 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17258 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17259 | tmp = fieldFromInstruction(insn, 0, 6); |
| 17260 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17261 | tmp = fieldFromInstruction(insn, 8, 3); |
| 17262 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17263 | return S; |
| 17264 | case 368: |
| 17265 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17266 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17267 | tmp = 0x0; |
| 17268 | tmp |= fieldFromInstruction(insn, 6, 1); |
| 17269 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 17270 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17271 | tmp = fieldFromInstruction(insn, 0, 6); |
| 17272 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17273 | tmp = fieldFromInstruction(insn, 8, 3); |
| 17274 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17275 | return S; |
| 17276 | case 369: |
| 17277 | tmp = fieldFromInstruction(insn, 0, 2); |
| 17278 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17279 | tmp = 0x0; |
| 17280 | tmp |= fieldFromInstruction(insn, 3, 4); |
| 17281 | tmp |= fieldFromInstruction(insn, 16, 2) << 4; |
| 17282 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17283 | tmp = fieldFromInstruction(insn, 8, 3); |
| 17284 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17285 | return S; |
| 17286 | case 370: |
| 17287 | tmp = fieldFromInstruction(insn, 0, 5); |
| 17288 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17289 | tmp = fieldFromInstruction(insn, 9, 2); |
| 17290 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17291 | tmp = 0x0; |
| 17292 | tmp |= fieldFromInstruction(insn, 8, 1); |
| 17293 | tmp |= fieldFromInstruction(insn, 16, 5) << 1; |
| 17294 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17295 | return S; |
| 17296 | case 371: |
| 17297 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17298 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17299 | tmp = fieldFromInstruction(insn, 0, 6); |
| 17300 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17301 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17302 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17303 | return S; |
| 17304 | case 372: |
| 17305 | tmp = fieldFromInstruction(insn, 16, 5); |
| 17306 | if (!Check(S, DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17307 | tmp = 0x0; |
| 17308 | tmp |= fieldFromInstruction(insn, 6, 1); |
| 17309 | tmp |= fieldFromInstruction(insn, 13, 1) << 1; |
| 17310 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17311 | tmp = fieldFromInstruction(insn, 0, 6); |
| 17312 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17313 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17314 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17315 | return S; |
| 17316 | case 373: |
| 17317 | tmp = fieldFromInstruction(insn, 0, 2); |
| 17318 | if (!Check(S, DecodePredRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17319 | tmp = 0x0; |
| 17320 | tmp |= fieldFromInstruction(insn, 3, 4); |
| 17321 | tmp |= fieldFromInstruction(insn, 16, 2) << 4; |
| 17322 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17323 | tmp = fieldFromInstruction(insn, 8, 5); |
| 17324 | if (!Check(S, DecodeDoubleRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17325 | return S; |
| 17326 | case 374: |
| 17327 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17328 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17329 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17330 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17331 | tmp = fieldFromInstruction(insn, 4, 7); |
| 17332 | if (!Check(S, s32_0ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17333 | return S; |
| 17334 | case 375: |
| 17335 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17336 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17337 | tmp = fieldFromInstruction(insn, 4, 6); |
| 17338 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17339 | return S; |
| 17340 | case 376: |
| 17341 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17342 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17343 | tmp = fieldFromInstruction(insn, 4, 6) << 2; |
| 17344 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17345 | return S; |
| 17346 | case 377: |
| 17347 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17348 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17349 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17350 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17351 | return S; |
| 17352 | case 378: |
| 17353 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17354 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17355 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17356 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17357 | if (!Check(Out&: S, In: n1ConstDecoder(MI, Decoder))) |
| 17358 | return MCDisassembler::Fail; |
| 17359 | return S; |
| 17360 | case 379: |
| 17361 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17362 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17363 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17364 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17365 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17366 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17367 | return S; |
| 17368 | case 380: |
| 17369 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17370 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17371 | tmp = fieldFromInstruction(insn, 0, 2); |
| 17372 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17373 | return S; |
| 17374 | case 381: |
| 17375 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17376 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17377 | if (!Check(Out&: S, In: n1ConstDecoder(MI, Decoder))) |
| 17378 | return MCDisassembler::Fail; |
| 17379 | return S; |
| 17380 | case 382: |
| 17381 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17382 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17383 | return S; |
| 17384 | case 383: |
| 17385 | tmp = fieldFromInstruction(insn, 0, 3); |
| 17386 | if (!Check(S, DecodeGeneralDoubleLow8RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17387 | tmp = fieldFromInstruction(insn, 5, 2); |
| 17388 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17389 | return S; |
| 17390 | case 384: |
| 17391 | tmp = fieldFromInstruction(insn, 0, 3); |
| 17392 | if (!Check(S, DecodeGeneralDoubleLow8RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17393 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17394 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17395 | return S; |
| 17396 | case 385: |
| 17397 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17398 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17399 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17400 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17401 | tmp = fieldFromInstruction(insn, 8, 4) << 2; |
| 17402 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17403 | return S; |
| 17404 | case 386: |
| 17405 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17406 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17407 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17408 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17409 | tmp = fieldFromInstruction(insn, 8, 4); |
| 17410 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17411 | return S; |
| 17412 | case 387: |
| 17413 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17414 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17415 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17416 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17417 | tmp = fieldFromInstruction(insn, 8, 3) << 1; |
| 17418 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17419 | return S; |
| 17420 | case 388: |
| 17421 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17422 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17423 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17424 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17425 | tmp = fieldFromInstruction(insn, 8, 3); |
| 17426 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17427 | return S; |
| 17428 | case 389: |
| 17429 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17430 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17431 | tmp = fieldFromInstruction(insn, 4, 5) << 2; |
| 17432 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17433 | return S; |
| 17434 | case 390: |
| 17435 | tmp = fieldFromInstruction(insn, 0, 3); |
| 17436 | if (!Check(S, DecodeGeneralDoubleLow8RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17437 | tmp = fieldFromInstruction(insn, 3, 5) << 3; |
| 17438 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17439 | return S; |
| 17440 | case 391: |
| 17441 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17442 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17443 | tmp = fieldFromInstruction(insn, 8, 4) << 2; |
| 17444 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17445 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17446 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17447 | return S; |
| 17448 | case 392: |
| 17449 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17450 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17451 | tmp = fieldFromInstruction(insn, 8, 4); |
| 17452 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17453 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17454 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17455 | return S; |
| 17456 | case 393: |
| 17457 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17458 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17459 | tmp = fieldFromInstruction(insn, 8, 3) << 1; |
| 17460 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17461 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17462 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17463 | return S; |
| 17464 | case 394: |
| 17465 | tmp = fieldFromInstruction(insn, 4, 5) << 2; |
| 17466 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17467 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17468 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17469 | return S; |
| 17470 | case 395: |
| 17471 | tmp = fieldFromInstruction(insn, 3, 6) << 3; |
| 17472 | if (!Check(S, s6_3ImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17473 | tmp = fieldFromInstruction(insn, 0, 3); |
| 17474 | if (!Check(S, DecodeGeneralDoubleLow8RegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17475 | return S; |
| 17476 | case 396: |
| 17477 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17478 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17479 | tmp = fieldFromInstruction(insn, 0, 4) << 2; |
| 17480 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17481 | return S; |
| 17482 | case 397: |
| 17483 | tmp = fieldFromInstruction(insn, 4, 4); |
| 17484 | if (!Check(S, DecodeGeneralSubRegsRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17485 | tmp = fieldFromInstruction(insn, 0, 4); |
| 17486 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17487 | return S; |
| 17488 | case 398: |
| 17489 | tmp = fieldFromInstruction(insn, 4, 5) << 3; |
| 17490 | if (!Check(S, unsignedImmDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; } |
| 17491 | return S; |
| 17492 | } |
| 17493 | } |
| 17494 | static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset &FB) { |
| 17495 | switch (Idx) { |
| 17496 | default: llvm_unreachable("Invalid index!"); |
| 17497 | case 0: |
| 17498 | return FB[Hexagon::ArchV73]; |
| 17499 | case 1: |
| 17500 | return FB[Hexagon::ArchV60]; |
| 17501 | case 2: |
| 17502 | return FB[Hexagon::FeaturePreV65]; |
| 17503 | case 3: |
| 17504 | return FB[Hexagon::ArchV65]; |
| 17505 | case 4: |
| 17506 | return FB[Hexagon::ArchV66]; |
| 17507 | case 5: |
| 17508 | return FB[Hexagon::ArchV67]; |
| 17509 | case 6: |
| 17510 | return FB[Hexagon::ArchV81]; |
| 17511 | case 7: |
| 17512 | return FB[Hexagon::ArchV62]; |
| 17513 | case 8: |
| 17514 | return FB[Hexagon::ArchV67] && FB[Hexagon::ExtensionAudio]; |
| 17515 | case 9: |
| 17516 | return FB[Hexagon::ArchV68]; |
| 17517 | case 10: |
| 17518 | return FB[Hexagon::FeatureCabac]; |
| 17519 | case 11: |
| 17520 | return FB[Hexagon::ArchV55]; |
| 17521 | case 12: |
| 17522 | return FB[Hexagon::ExtensionHVXV62]; |
| 17523 | case 13: |
| 17524 | return FB[Hexagon::ExtensionHVXV65]; |
| 17525 | case 14: |
| 17526 | return FB[Hexagon::ExtensionHVXV81]; |
| 17527 | case 15: |
| 17528 | return FB[Hexagon::ExtensionHVXV60]; |
| 17529 | case 16: |
| 17530 | return FB[Hexagon::ExtensionHVXV66] && FB[Hexagon::ExtensionZReg]; |
| 17531 | case 17: |
| 17532 | return FB[Hexagon::ExtensionHVXV79] && FB[Hexagon::ExtensionHVXQFloat]; |
| 17533 | case 18: |
| 17534 | return FB[Hexagon::ExtensionHVXV81] && FB[Hexagon::ExtensionHVXQFloat]; |
| 17535 | case 19: |
| 17536 | return FB[Hexagon::ExtensionHVXV66]; |
| 17537 | case 20: |
| 17538 | return FB[Hexagon::ExtensionHVXV79] && FB[Hexagon::ExtensionHVXIEEEFP]; |
| 17539 | case 21: |
| 17540 | return FB[Hexagon::ExtensionHVXV68] && FB[Hexagon::ExtensionHVXIEEEFP]; |
| 17541 | case 22: |
| 17542 | return FB[Hexagon::ExtensionHVXV68]; |
| 17543 | case 23: |
| 17544 | return FB[Hexagon::ExtensionHVXV73] && FB[Hexagon::ExtensionHVXQFloat]; |
| 17545 | case 24: |
| 17546 | return FB[Hexagon::ExtensionHVXV69]; |
| 17547 | case 25: |
| 17548 | return FB[Hexagon::ExtensionHVXV73] && FB[Hexagon::ExtensionHVXIEEEFP]; |
| 17549 | case 26: |
| 17550 | return FB[Hexagon::ExtensionHVXV68] && FB[Hexagon::ExtensionHVXQFloat]; |
| 17551 | case 27: |
| 17552 | return FB[Hexagon::ExtensionHVXV73]; |
| 17553 | } |
| 17554 | } |
| 17555 | |
| 17556 | |
| 17557 | template <typename InsnType> |
| 17558 | static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI, |
| 17559 | InsnType insn, uint64_t Address, |
| 17560 | const MCDisassembler *DisAsm, |
| 17561 | const MCSubtargetInfo &STI) { |
| 17562 | const FeatureBitset &Bits = STI.getFeatureBits(); |
| 17563 | const uint8_t *Ptr = DecodeTable; |
| 17564 | |
| 17565 | SmallVector<const uint8_t *, 8> ScopeStack; |
| 17566 | DecodeStatus S = MCDisassembler::Success; |
| 17567 | while (true) { |
| 17568 | ptrdiff_t Loc = Ptr - DecodeTable; |
| 17569 | const uint8_t DecoderOp = *Ptr++; |
| 17570 | switch (DecoderOp) { |
| 17571 | default: |
| 17572 | errs() << Loc << ": Unexpected decode table opcode: " |
| 17573 | << (int)DecoderOp << '\n'; |
| 17574 | return MCDisassembler::Fail; |
| 17575 | case OPC_Scope: { |
| 17576 | unsigned NumToSkip = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17577 | const uint8_t *SkipTo = Ptr + NumToSkip; |
| 17578 | ScopeStack.push_back(Elt: SkipTo); |
| 17579 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Scope("<< SkipTo - DecodeTable |
| 17580 | << ")\n"); |
| 17581 | continue; |
| 17582 | } |
| 17583 | case OPC_SwitchField: { |
| 17584 | // Decode the start value. |
| 17585 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17586 | unsigned Len = *Ptr++; |
| 17587 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 17588 | uint64_t CaseValue; |
| 17589 | unsigned CaseSize; |
| 17590 | while (true) { |
| 17591 | CaseValue = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17592 | CaseSize = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17593 | if (FieldValue == CaseValue || !CaseSize) |
| 17594 | break; |
| 17595 | Ptr += CaseSize; |
| 17596 | } |
| 17597 | if (FieldValue == CaseValue) { |
| 17598 | LLVM_DEBUG(dbgs() << Loc << ": OPC_SwitchField("<< Start << ", "<< Len |
| 17599 | << "): "<< FieldValue << '\n'); |
| 17600 | continue; |
| 17601 | } |
| 17602 | break; |
| 17603 | } |
| 17604 | case OPC_CheckField: { |
| 17605 | // Decode the start value. |
| 17606 | unsigned Start = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17607 | unsigned Len = *Ptr; |
| 17608 | uint64_t FieldValue = fieldFromInstruction(insn, Start, Len); |
| 17609 | // Decode the field value. |
| 17610 | unsigned PtrLen = 0; |
| 17611 | uint64_t ExpectedValue = decodeULEB128(p: ++Ptr, n: &PtrLen); |
| 17612 | Ptr += PtrLen; |
| 17613 | bool Failed = ExpectedValue != FieldValue; |
| 17614 | |
| 17615 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField("<< Start << ", "<< Len |
| 17616 | << ", "<< ExpectedValue << "): FieldValue = " |
| 17617 | << FieldValue << ", ExpectedValue = "<< ExpectedValue |
| 17618 | << ": "<< (Failed ? "FAIL, ": "PASS\n");); |
| 17619 | if (!Failed) |
| 17620 | continue; |
| 17621 | break; |
| 17622 | } |
| 17623 | case OPC_CheckPredicate: { |
| 17624 | // Decode the Predicate Index value. |
| 17625 | unsigned PIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17626 | // Check the predicate. |
| 17627 | bool Failed = !checkDecoderPredicate(Idx: PIdx, FB: Bits); |
| 17628 | |
| 17629 | LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate("<< PIdx << "): " |
| 17630 | << (Failed ? "FAIL, ": "PASS\n");); |
| 17631 | if (!Failed) |
| 17632 | continue; |
| 17633 | break; |
| 17634 | } |
| 17635 | case OPC_Decode: { |
| 17636 | // Decode the Opcode value. |
| 17637 | unsigned Opc = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17638 | unsigned DecodeIdx = decodeULEB128AndIncUnsafe(p&: Ptr); |
| 17639 | |
| 17640 | MI.clear(); |
| 17641 | MI.setOpcode(Opc); |
| 17642 | bool DecodeComplete; |
| 17643 | S = decodeToMCInst(DecodeIdx, S, insn, MI, Address, DisAsm, |
| 17644 | DecodeComplete); |
| 17645 | LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode "<< Opc |
| 17646 | << ", using decoder "<< DecodeIdx << ": " |
| 17647 | << (S ? "PASS, ": "FAIL, ")); |
| 17648 | |
| 17649 | if (DecodeComplete) { |
| 17650 | LLVM_DEBUG(dbgs() << "decoding complete\n"); |
| 17651 | return S; |
| 17652 | } |
| 17653 | assert(S == MCDisassembler::Fail); |
| 17654 | // Reset decode status. This also drops a SoftFail status that could be |
| 17655 | // set before the decode attempt. |
| 17656 | S = MCDisassembler::Success; |
| 17657 | break; |
| 17658 | } |
| 17659 | } |
| 17660 | if (ScopeStack.empty()) { |
| 17661 | LLVM_DEBUG(dbgs() << "returning Fail\n"); |
| 17662 | return MCDisassembler::Fail; |
| 17663 | } |
| 17664 | Ptr = ScopeStack.pop_back_val(); |
| 17665 | LLVM_DEBUG(dbgs() << "continuing at "<< Ptr - DecodeTable << '\n'); |
| 17666 | } |
| 17667 | llvm_unreachable("bogosity detected in disassembler state machine!"); |
| 17668 | } |
| 17669 | |
| 17670 | |
| 17671 | } // namespace |
| 17672 |
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